Merge changes from topic "bring_up_hps_demo"
* changes:
[sw][matcha] Update ISP registes setup for raw and bypass modes
[sw][matcha] Update demo script for new server setup
diff --git a/BUILD.bazel b/BUILD.bazel
index 4a84fd4..ee42854 100644
--- a/BUILD.bazel
+++ b/BUILD.bazel
@@ -11,6 +11,7 @@
# Add a file from each directory and let fusesoc to pick the directory.
"@lowrisc_opentitan//hw/dv:BUILD",
"@lowrisc_opentitan//hw/ip:BUILD",
+ "@kelvin_hw//hdl/chisel:kelvin.core",
"@lowrisc_opentitan//hw/lint:BUILD",
"@lowrisc_opentitan//hw/vendor:BUILD",
# Place the following file to make compilation works
diff --git a/WORKSPACE b/WORKSPACE
index 7ebf632..cb11705 100644
--- a/WORKSPACE
+++ b/WORKSPACE
@@ -21,6 +21,11 @@
path = "../../hw/ip/isp/axi2sramcrs",
)
+local_repository(
+ name = "kelvin_hw",
+ path = "../kelvin",
+)
+
new_local_repository(
name = "kelvin-gcc",
build_file = "third_party/kelvin-gcc/BUILD",
@@ -110,8 +115,6 @@
freertos_repos()
-load("@bazel_tools//tools/build_defs/repo:http.bzl", "http_archive")
-
# Binary firmware image for HyperDebug
load("@bazel_tools//tools/build_defs/repo:http.bzl", "http_file")
@@ -120,3 +123,22 @@
sha256 = "e9c93d2935b9b6a571b547f20fe6177c48a909535d87533b7a0c64fb049bd643",
urls = ["https://storage.googleapis.com/aoa-recovery-test-images/hyperdebug_v2.0.20491-956ccf530.bin"],
)
+
+# kelvin verilog dependencies
+load("@kelvin_hw//rules:repos.bzl", "kelvin_repos")
+kelvin_repos()
+
+# Scala setup
+load("@io_bazel_rules_scala//:scala_config.bzl", "scala_config")
+scala_config(scala_version = "2.13.6")
+load("@io_bazel_rules_scala//scala:scala.bzl", "rules_scala_setup", "rules_scala_toolchain_deps_repositories")
+rules_scala_setup()
+rules_scala_toolchain_deps_repositories(fetch_sources = True)
+load("@io_bazel_rules_scala//scala:toolchains.bzl", "scala_register_toolchains")
+scala_register_toolchains()
+load("@rules_proto//proto:repositories.bzl", "rules_proto_dependencies", "rules_proto_toolchains")
+rules_proto_dependencies()
+rules_proto_toolchains()
+
+load("@kelvin_hw//rules:deps.bzl", "kelvin_chisel_deps")
+kelvin_chisel_deps()
diff --git a/doc/getting_started/setup_dv.md b/doc/getting_started/setup_dv.md
index a893518..f58f008 100644
--- a/doc/getting_started/setup_dv.md
+++ b/doc/getting_started/setup_dv.md
@@ -7,7 +7,7 @@
[Design Verification Methodology in Opentitan](https://docs.opentitan.org/doc/ug/dv_methodology/) has been followed in matcha.
-Currently, [VCS](https://www.synopsys.com/verification/simulation/vcs.html) is used as the major simulator for running DV tests in matcha.
+Currently, [VCS](https://www.synopsys.com/verification/simulation/vcs.html) is used as the major simulator for running DV tests in matcha.
### DV Settings
@@ -25,6 +25,7 @@
```
cd $ROOTDIR/hw/matcha
+bazel build @kelvin_hw//hdl/chisel:kelvin.core # build kelvin RTL
util/dvsim_match/dvsim.py \
hw/top_matcha/dv/chip_sim_cfg.hjson \
-i <test_name>
@@ -88,3 +89,13 @@
end
```
+2. Add the following lines:
+ ```
+ `define STOP_COND 0
+ `define PRINTF_COND 0
+ ```
+ at the top of the files:
+ ```
+ hw/top_matcha/ip/ml_top/rtl/xbar_sram.v
+ ```
+ to turn off the $fatal statements and the unwanted debug messages
diff --git a/hw/BUILD b/hw/BUILD
index 68aad89..e763510 100644
--- a/hw/BUILD
+++ b/hw/BUILD
@@ -82,6 +82,8 @@
name = "all_files",
srcs = glob(["**"]) + [
"//hw/top_matcha:all_files",
+ "@kelvin_hw//hdl/chisel:matcha_kelvin_verilog",
+ "@kelvin_hw//hdl/chisel:kelvin.core",
"@lowrisc_opentitan//hw/dv:all_files",
],
)
diff --git a/hw/dv/tools/dvsim/fusesoc.hjson b/hw/dv/tools/dvsim/fusesoc.hjson
index 85c966c..db7c762 100644
--- a/hw/dv/tools/dvsim/fusesoc.hjson
+++ b/hw/dv/tools/dvsim/fusesoc.hjson
@@ -11,13 +11,15 @@
"--target=sim",
"--build-root={build_dir}",
"--setup {fusesoc_core}"]
- fusesoc_cores_root_dirs: ["--cores-root {titan_root}/hw/ip",
- "--cores-root {titan_root}/hw/dv/sv",
- "--cores-root {titan_root}/hw/dv/verilator",
- "--cores-root {titan_root}/hw/formal",
- "--cores-root {titan_root}/hw/vendor",
- "--cores-root {proj_root}/../ip/isp",
- "--cores-root {proj_root}"]
+ fusesoc_cores_root_dirs: ["--cores-root {titan_root}/hw/ip",
+ "--cores-root {proj_root}/bazel-bin/external/kelvin_hw/hdl/chisel",
+ "--cores-root {titan_root}/hw/dv/sv",
+ "--cores-root {titan_root}/hw/dv/verilator",
+ "--cores-root {titan_root}/hw/formal",
+ "--cores-root {titan_root}/hw/vendor",
+ "--cores-root {proj_root}/../ip/isp/ispyocto",
+ "--cores-root {proj_root}/../ip/isp/axi2sramcrs",
+ "--cores-root {proj_root}/hw"]
sv_flist_gen_dir: "{build_dir}/sim-vcs"
sv_flist: "{sv_flist_gen_dir}/{fusesoc_core_}.scr"
sv_flist_gen_flags: ["--flag=fileset_{design_level}"]
diff --git a/hw/top_matcha/ip/ml_top/ml_top.core b/hw/top_matcha/ip/ml_top/ml_top.core
index 6fed143..127344a 100644
--- a/hw/top_matcha/ip/ml_top/ml_top.core
+++ b/hw/top_matcha/ip/ml_top/ml_top.core
@@ -10,6 +10,7 @@
- lowrisc:prim:all
- lowrisc:ip:tlul
- lowrisc:prim:mubi
+ - google:ip:kelvin
files:
- rtl/ml_pkg.sv
@@ -18,10 +19,6 @@
- rtl/ml_dmem.sv
- rtl/ml_top.sv
- rtl/xbar_sram.v
- - rtl/kelvin.v
- - rtl/Sram_1rw_256x256.v
- - rtl/Sram_1rwm_256x288.v
- - rtl/ClockGate.v
file_type: systemVerilogSource
files_verilator_waiver:
@@ -73,6 +70,3 @@
mode: lint-only
verilator_options:
- "-Wall"
-
-
-
diff --git a/hw/top_matcha/ip/ml_top/rtl/ClockGate.v b/hw/top_matcha/ip/ml_top/rtl/ClockGate.v
deleted file mode 100644
index 27250b2..0000000
--- a/hw/top_matcha/ip/ml_top/rtl/ClockGate.v
+++ /dev/null
@@ -1,38 +0,0 @@
-// Copyright 2023 Google LLC
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-module ClockGate(
- input clk_i,
- input enable, // '1' passthrough, '0' disable.
- output clk_o
-);
-// Note: Bypass clock gate for now. It causes FPGA build failures and
-// simulation issues
-assign clk_o = clk_i;
-/*
-reg clk_en;
-`ifdef FPGA
- assign clk_o = clk_i;
-`else
- // Capture 'enable' during low phase of the clock.
- always @(clk_i or enable)
- begin
- if (~clk_i)
- clk_en = enable;
- end
-
- assign clk_o = clk_i & clk_en;
-`endif
-*/
-endmodule // ClockGate
diff --git a/hw/top_matcha/ip/ml_top/rtl/Sram_1rw_256x256.v b/hw/top_matcha/ip/ml_top/rtl/Sram_1rw_256x256.v
deleted file mode 100644
index f580dd2..0000000
--- a/hw/top_matcha/ip/ml_top/rtl/Sram_1rw_256x256.v
+++ /dev/null
@@ -1,38 +0,0 @@
-// Copyright 2023 Google LLC
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-module Sram_1rw_256x256(
- input clock,
- input valid,
- input write,
- input [7:0] addr,
- input [255:0] wdata,
- output [255:0] rdata,
- input volt_sel
-);
-
- reg [255:0] mem [0:255];
- reg [7:0] raddr;
-
- assign rdata = mem[raddr];
-
- always @(posedge clock) begin
- if (valid & write) begin
- mem[addr] <= wdata;
- end
- if (valid & ~write) begin
- raddr <= addr;
- end
- end
-endmodule
diff --git a/hw/top_matcha/ip/ml_top/rtl/Sram_1rwm_256x288.v b/hw/top_matcha/ip/ml_top/rtl/Sram_1rwm_256x288.v
deleted file mode 100644
index f0cdb49..0000000
--- a/hw/top_matcha/ip/ml_top/rtl/Sram_1rwm_256x288.v
+++ /dev/null
@@ -1,107 +0,0 @@
-// Copyright 2023 Google LLC
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-module Sram_1rwm_256x288(
- input clock,
- input valid,
- input write,
- input [7:0] addr,
- input [287:0] wdata,
- input [31:0] wmask,
- output [287:0] rdata,
- input volt_sel
-);
-
-`ifdef FPGA
-reg [287:0] mem [0:255];
-reg [7:0] raddr;
-
-assign rdata = mem[raddr];
-
-always @(posedge clock) begin
- for (int i = 0; i < 32; i++) begin
- if (valid & write & wmask[i]) begin
- mem[addr][i*9 +: 9] <= wdata[i*9 +: 9];
- end
- end
- if (valid & ~write) begin
- raddr <= addr;
- end
-end
-
-endmodule // Sram_1rwm_256x288
-
-`else // !FPGA
-
-Sram_1rw_256x9 u_bl00(clock, valid & (~write | wmask[0]), write, addr, wdata[ 0 +: 9], rdata[ 0 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl01(clock, valid & (~write | wmask[1]), write, addr, wdata[ 9 +: 9], rdata[ 9 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl02(clock, valid & (~write | wmask[2]), write, addr, wdata[ 18 +: 9], rdata[ 18 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl03(clock, valid & (~write | wmask[3]), write, addr, wdata[ 27 +: 9], rdata[ 27 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl04(clock, valid & (~write | wmask[4]), write, addr, wdata[ 36 +: 9], rdata[ 36 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl05(clock, valid & (~write | wmask[5]), write, addr, wdata[ 45 +: 9], rdata[ 45 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl06(clock, valid & (~write | wmask[6]), write, addr, wdata[ 54 +: 9], rdata[ 54 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl07(clock, valid & (~write | wmask[7]), write, addr, wdata[ 63 +: 9], rdata[ 63 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl08(clock, valid & (~write | wmask[8]), write, addr, wdata[ 72 +: 9], rdata[ 72 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl09(clock, valid & (~write | wmask[9]), write, addr, wdata[ 81 +: 9], rdata[ 81 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl10(clock, valid & (~write | wmask[10]), write, addr, wdata[ 90 +: 9], rdata[ 90 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl11(clock, valid & (~write | wmask[11]), write, addr, wdata[ 99 +: 9], rdata[ 99 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl12(clock, valid & (~write | wmask[12]), write, addr, wdata[108 +: 9], rdata[108 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl13(clock, valid & (~write | wmask[13]), write, addr, wdata[117 +: 9], rdata[117 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl14(clock, valid & (~write | wmask[14]), write, addr, wdata[126 +: 9], rdata[126 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl15(clock, valid & (~write | wmask[15]), write, addr, wdata[135 +: 9], rdata[135 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl16(clock, valid & (~write | wmask[16]), write, addr, wdata[144 +: 9], rdata[144 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl17(clock, valid & (~write | wmask[17]), write, addr, wdata[153 +: 9], rdata[153 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl18(clock, valid & (~write | wmask[18]), write, addr, wdata[162 +: 9], rdata[162 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl19(clock, valid & (~write | wmask[19]), write, addr, wdata[171 +: 9], rdata[171 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl20(clock, valid & (~write | wmask[20]), write, addr, wdata[180 +: 9], rdata[180 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl21(clock, valid & (~write | wmask[21]), write, addr, wdata[189 +: 9], rdata[189 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl22(clock, valid & (~write | wmask[22]), write, addr, wdata[198 +: 9], rdata[198 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl23(clock, valid & (~write | wmask[23]), write, addr, wdata[207 +: 9], rdata[207 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl24(clock, valid & (~write | wmask[24]), write, addr, wdata[216 +: 9], rdata[216 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl25(clock, valid & (~write | wmask[25]), write, addr, wdata[225 +: 9], rdata[225 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl26(clock, valid & (~write | wmask[26]), write, addr, wdata[234 +: 9], rdata[234 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl27(clock, valid & (~write | wmask[27]), write, addr, wdata[243 +: 9], rdata[243 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl28(clock, valid & (~write | wmask[28]), write, addr, wdata[252 +: 9], rdata[252 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl29(clock, valid & (~write | wmask[29]), write, addr, wdata[261 +: 9], rdata[261 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl30(clock, valid & (~write | wmask[30]), write, addr, wdata[270 +: 9], rdata[270 +: 9], volt_sel);
-Sram_1rw_256x9 u_bl31(clock, valid & (~write | wmask[31]), write, addr, wdata[279 +: 9], rdata[279 +: 9], volt_sel);
-
-endmodule // Sram_1rwm_256x288
-
-module Sram_1rw_256x9(
- input clock,
- input valid,
- input write,
- input [7:0] addr,
- input [8:0] wdata,
- output [8:0] rdata,
- input volt_sel
-);
-
- reg [8:0] mem [0:255];
- reg [7:0] raddr;
-
- assign rdata = mem[raddr];
-
- always @(posedge clock) begin
- if (valid & write) begin
- mem[addr] <= wdata;
- end
- if (valid & ~write) begin
- raddr <= addr;
- end
- end
-endmodule // Sram_1rw_256x9
-
-`endif // FPGA
diff --git a/hw/top_matcha/ip/ml_top/rtl/kelvin.v b/hw/top_matcha/ip/ml_top/rtl/kelvin.v
deleted file mode 100644
index f78aa61..0000000
--- a/hw/top_matcha/ip/ml_top/rtl/kelvin.v
+++ /dev/null
@@ -1,198345 +0,0 @@
-// Copyright 2023 Google LLC
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-// SHA: f9c11453e0d356ba16f0b0d7306e9d0ebe090d12
-module Regfile(
- input clock,
- input reset,
- input io_readAddr_0_valid,
- input [4:0] io_readAddr_0_addr,
- input io_readAddr_1_valid,
- input [4:0] io_readAddr_1_addr,
- input io_readAddr_2_valid,
- input [4:0] io_readAddr_2_addr,
- input io_readAddr_3_valid,
- input [4:0] io_readAddr_3_addr,
- input io_readAddr_4_valid,
- input [4:0] io_readAddr_4_addr,
- input io_readAddr_5_valid,
- input [4:0] io_readAddr_5_addr,
- input io_readAddr_6_valid,
- input [4:0] io_readAddr_6_addr,
- input io_readAddr_7_valid,
- input [4:0] io_readAddr_7_addr,
- input io_readSet_0_valid,
- input [31:0] io_readSet_0_value,
- input io_readSet_1_valid,
- input [31:0] io_readSet_1_value,
- input io_readSet_2_valid,
- input [31:0] io_readSet_2_value,
- input io_readSet_3_valid,
- input [31:0] io_readSet_3_value,
- input io_readSet_4_valid,
- input [31:0] io_readSet_4_value,
- input io_readSet_5_valid,
- input [31:0] io_readSet_5_value,
- input io_readSet_6_valid,
- input [31:0] io_readSet_6_value,
- input io_readSet_7_valid,
- input [31:0] io_readSet_7_value,
- input io_writeAddr_0_valid,
- input [4:0] io_writeAddr_0_addr,
- input io_writeAddr_1_valid,
- input [4:0] io_writeAddr_1_addr,
- input io_writeAddr_2_valid,
- input [4:0] io_writeAddr_2_addr,
- input io_writeAddr_3_valid,
- input [4:0] io_writeAddr_3_addr,
- input io_busAddr_0_bypass,
- input io_busAddr_0_immen,
- input [31:0] io_busAddr_0_immed,
- input io_busAddr_1_bypass,
- input [31:0] io_busAddr_1_immed,
- input io_busAddr_2_bypass,
- input [31:0] io_busAddr_2_immed,
- input io_busAddr_3_bypass,
- input [31:0] io_busAddr_3_immed,
- output [31:0] io_target_0_data,
- output [31:0] io_target_1_data,
- output [31:0] io_target_2_data,
- output [31:0] io_target_3_data,
- output io_linkPort_valid,
- output [31:0] io_linkPort_value,
- output [31:0] io_busPort_addr_0,
- output [31:0] io_busPort_addr_1,
- output [31:0] io_busPort_addr_2,
- output [31:0] io_busPort_addr_3,
- output [31:0] io_busPort_data_0,
- output [31:0] io_busPort_data_1,
- output [31:0] io_busPort_data_2,
- output [31:0] io_busPort_data_3,
- output io_readData_0_valid,
- output [31:0] io_readData_0_data,
- output io_readData_1_valid,
- output [31:0] io_readData_1_data,
- output io_readData_2_valid,
- output [31:0] io_readData_2_data,
- output io_readData_3_valid,
- output [31:0] io_readData_3_data,
- output io_readData_4_valid,
- output [31:0] io_readData_4_data,
- output io_readData_5_valid,
- output [31:0] io_readData_5_data,
- output io_readData_6_valid,
- output [31:0] io_readData_6_data,
- output io_readData_7_valid,
- output [31:0] io_readData_7_data,
- input io_writeData_0_valid,
- input [4:0] io_writeData_0_addr,
- input [31:0] io_writeData_0_data,
- input io_writeData_1_valid,
- input [4:0] io_writeData_1_addr,
- input [31:0] io_writeData_1_data,
- input io_writeData_2_valid,
- input [4:0] io_writeData_2_addr,
- input [31:0] io_writeData_2_data,
- input io_writeData_3_valid,
- input [4:0] io_writeData_3_addr,
- input [31:0] io_writeData_3_data,
- input io_writeData_4_valid,
- input [4:0] io_writeData_4_addr,
- input [31:0] io_writeData_4_data,
- input io_writeData_5_valid,
- input [4:0] io_writeData_5_addr,
- input [31:0] io_writeData_5_data,
- input io_writeMask_0_valid,
- input io_writeMask_1_valid,
- input io_writeMask_2_valid,
- input io_writeMask_3_valid,
- output [31:0] io_scoreboard_regd,
- output [31:0] io_scoreboard_comb
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
- reg [31:0] _RAND_34;
- reg [31:0] _RAND_35;
- reg [31:0] _RAND_36;
- reg [31:0] _RAND_37;
- reg [31:0] _RAND_38;
- reg [31:0] _RAND_39;
- reg [31:0] _RAND_40;
- reg [31:0] _RAND_41;
- reg [31:0] _RAND_42;
- reg [31:0] _RAND_43;
- reg [31:0] _RAND_44;
- reg [31:0] _RAND_45;
- reg [31:0] _RAND_46;
- reg [31:0] _RAND_47;
- reg [31:0] _RAND_48;
- reg [31:0] _RAND_49;
- reg [31:0] _RAND_50;
- reg [31:0] _RAND_51;
- reg [31:0] _RAND_52;
- reg [31:0] _RAND_53;
- reg [31:0] _RAND_54;
- reg [31:0] _RAND_55;
- reg [31:0] _RAND_56;
- reg [31:0] _RAND_57;
- reg [31:0] _RAND_58;
- reg [31:0] _RAND_59;
- reg [31:0] _RAND_60;
- reg [31:0] _RAND_61;
- reg [31:0] _RAND_62;
- reg [31:0] _RAND_63;
-`endif // RANDOMIZE_REG_INIT
- reg [31:0] regfile_1; // @[Regfile.scala 101:20]
- reg [31:0] regfile_2; // @[Regfile.scala 101:20]
- reg [31:0] regfile_3; // @[Regfile.scala 101:20]
- reg [31:0] regfile_4; // @[Regfile.scala 101:20]
- reg [31:0] regfile_5; // @[Regfile.scala 101:20]
- reg [31:0] regfile_6; // @[Regfile.scala 101:20]
- reg [31:0] regfile_7; // @[Regfile.scala 101:20]
- reg [31:0] regfile_8; // @[Regfile.scala 101:20]
- reg [31:0] regfile_9; // @[Regfile.scala 101:20]
- reg [31:0] regfile_10; // @[Regfile.scala 101:20]
- reg [31:0] regfile_11; // @[Regfile.scala 101:20]
- reg [31:0] regfile_12; // @[Regfile.scala 101:20]
- reg [31:0] regfile_13; // @[Regfile.scala 101:20]
- reg [31:0] regfile_14; // @[Regfile.scala 101:20]
- reg [31:0] regfile_15; // @[Regfile.scala 101:20]
- reg [31:0] regfile_16; // @[Regfile.scala 101:20]
- reg [31:0] regfile_17; // @[Regfile.scala 101:20]
- reg [31:0] regfile_18; // @[Regfile.scala 101:20]
- reg [31:0] regfile_19; // @[Regfile.scala 101:20]
- reg [31:0] regfile_20; // @[Regfile.scala 101:20]
- reg [31:0] regfile_21; // @[Regfile.scala 101:20]
- reg [31:0] regfile_22; // @[Regfile.scala 101:20]
- reg [31:0] regfile_23; // @[Regfile.scala 101:20]
- reg [31:0] regfile_24; // @[Regfile.scala 101:20]
- reg [31:0] regfile_25; // @[Regfile.scala 101:20]
- reg [31:0] regfile_26; // @[Regfile.scala 101:20]
- reg [31:0] regfile_27; // @[Regfile.scala 101:20]
- reg [31:0] regfile_28; // @[Regfile.scala 101:20]
- reg [31:0] regfile_29; // @[Regfile.scala 101:20]
- reg [31:0] regfile_30; // @[Regfile.scala 101:20]
- reg [31:0] regfile_31; // @[Regfile.scala 101:20]
- reg [31:0] scoreboard; // @[Regfile.scala 106:27]
- wire [31:0] _scoreboard_set_T = 32'h1 << io_writeAddr_0_addr; // @[OneHot.scala 64:12]
- wire [31:0] _scoreboard_set_T_2 = io_writeAddr_0_valid ? _scoreboard_set_T : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _scoreboard_set_T_3 = 32'h1 << io_writeAddr_1_addr; // @[OneHot.scala 64:12]
- wire [31:0] _scoreboard_set_T_5 = io_writeAddr_1_valid ? _scoreboard_set_T_3 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _scoreboard_set_T_6 = _scoreboard_set_T_2 | _scoreboard_set_T_5; // @[Regfile.scala 112:68]
- wire [31:0] _scoreboard_set_T_7 = 32'h1 << io_writeAddr_2_addr; // @[OneHot.scala 64:12]
- wire [31:0] _scoreboard_set_T_9 = io_writeAddr_2_valid ? _scoreboard_set_T_7 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _scoreboard_set_T_10 = _scoreboard_set_T_6 | _scoreboard_set_T_9; // @[Regfile.scala 113:68]
- wire [31:0] _scoreboard_set_T_11 = 32'h1 << io_writeAddr_3_addr; // @[OneHot.scala 64:12]
- wire [31:0] _scoreboard_set_T_13 = io_writeAddr_3_valid ? _scoreboard_set_T_11 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] scoreboard_set = _scoreboard_set_T_10 | _scoreboard_set_T_13; // @[Regfile.scala 114:68]
- wire [31:0] _scoreboard_clr0_T = 32'h1 << io_writeData_0_addr; // @[OneHot.scala 64:12]
- wire [31:0] _scoreboard_clr0_T_2 = io_writeData_0_valid ? _scoreboard_clr0_T : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _scoreboard_clr0_T_3 = 32'h1 << io_writeData_1_addr; // @[OneHot.scala 64:12]
- wire [31:0] _scoreboard_clr0_T_5 = io_writeData_1_valid ? _scoreboard_clr0_T_3 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _scoreboard_clr0_T_6 = _scoreboard_clr0_T_2 | _scoreboard_clr0_T_5; // @[Regfile.scala 118:68]
- wire [31:0] _scoreboard_clr0_T_7 = 32'h1 << io_writeData_2_addr; // @[OneHot.scala 64:12]
- wire [31:0] _scoreboard_clr0_T_9 = io_writeData_2_valid ? _scoreboard_clr0_T_7 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _scoreboard_clr0_T_10 = _scoreboard_clr0_T_6 | _scoreboard_clr0_T_9; // @[Regfile.scala 119:68]
- wire [31:0] _scoreboard_clr0_T_11 = 32'h1 << io_writeData_3_addr; // @[OneHot.scala 64:12]
- wire [31:0] _scoreboard_clr0_T_13 = io_writeData_3_valid ? _scoreboard_clr0_T_11 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _scoreboard_clr0_T_14 = _scoreboard_clr0_T_10 | _scoreboard_clr0_T_13; // @[Regfile.scala 120:68]
- wire [31:0] _scoreboard_clr0_T_15 = 32'h1 << io_writeData_4_addr; // @[OneHot.scala 64:12]
- wire [31:0] _scoreboard_clr0_T_17 = io_writeData_4_valid ? _scoreboard_clr0_T_15 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _scoreboard_clr0_T_18 = _scoreboard_clr0_T_14 | _scoreboard_clr0_T_17; // @[Regfile.scala 121:68]
- wire [31:0] _scoreboard_clr0_T_19 = 32'h1 << io_writeData_5_addr; // @[OneHot.scala 64:12]
- wire [31:0] _scoreboard_clr0_T_21 = io_writeData_5_valid ? _scoreboard_clr0_T_19 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] scoreboard_clr0 = _scoreboard_clr0_T_18 | _scoreboard_clr0_T_21; // @[Regfile.scala 122:68]
- wire [31:0] scoreboard_clr = {scoreboard_clr0[31:1],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] _nxtScoreboard_T = ~scoreboard_clr; // @[Regfile.scala 128:39]
- wire [31:0] _nxtScoreboard_T_1 = scoreboard & _nxtScoreboard_T; // @[Regfile.scala 128:37]
- wire [31:0] nxtScoreboard = _nxtScoreboard_T_1 | scoreboard_set; // @[Regfile.scala 128:56]
- wire [31:0] _scoreboard_T_1 = {nxtScoreboard[31:1],1'h0}; // @[Cat.scala 31:58]
- reg readDataReady_0; // @[Regfile.scala 138:30]
- reg readDataReady_1; // @[Regfile.scala 138:30]
- reg readDataReady_2; // @[Regfile.scala 138:30]
- reg readDataReady_3; // @[Regfile.scala 138:30]
- reg readDataReady_4; // @[Regfile.scala 138:30]
- reg readDataReady_5; // @[Regfile.scala 138:30]
- reg readDataReady_6; // @[Regfile.scala 138:30]
- reg readDataReady_7; // @[Regfile.scala 138:30]
- reg [31:0] readDataBits_0; // @[Regfile.scala 139:26]
- reg [31:0] readDataBits_1; // @[Regfile.scala 139:26]
- reg [31:0] readDataBits_2; // @[Regfile.scala 139:26]
- reg [31:0] readDataBits_3; // @[Regfile.scala 139:26]
- reg [31:0] readDataBits_4; // @[Regfile.scala 139:26]
- reg [31:0] readDataBits_5; // @[Regfile.scala 139:26]
- reg [31:0] readDataBits_6; // @[Regfile.scala 139:26]
- reg [31:0] readDataBits_7; // @[Regfile.scala 139:26]
- wire _valid_T_1 = io_writeData_5_valid & io_writeData_5_addr == 5'h1; // @[Regfile.scala 157:43]
- wire _valid_T_3 = io_writeData_4_valid & io_writeData_4_addr == 5'h1; // @[Regfile.scala 158:43]
- wire _valid_T_6 = ~io_writeMask_3_valid; // @[Regfile.scala 160:23]
- wire _valid_T_7 = io_writeData_3_valid & io_writeData_3_addr == 5'h1 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_10 = ~io_writeMask_2_valid; // @[Regfile.scala 162:23]
- wire _valid_T_11 = io_writeData_2_valid & io_writeData_2_addr == 5'h1 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_14 = ~io_writeMask_1_valid; // @[Regfile.scala 164:23]
- wire _valid_T_15 = io_writeData_1_valid & io_writeData_1_addr == 5'h1 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_17 = io_writeData_0_valid & io_writeData_0_addr == 5'h1; // @[Regfile.scala 165:43]
- wire [5:0] valid = {_valid_T_1,_valid_T_3,_valid_T_7,_valid_T_11,_valid_T_15,_valid_T_17}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_1 = valid[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_3 = valid[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_4 = _data_T_1 | _data_T_3; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_6 = valid[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_7 = _data_T_4 | _data_T_6; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_9 = valid[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_10 = _data_T_7 | _data_T_9; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_12 = valid[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_13 = _data_T_10 | _data_T_12; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_15 = valid[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data = _data_T_13 | _data_T_15; // @[Regfile.scala 172:55]
- wire writeValid_1 = valid != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_9 = valid[1] + valid[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_41 = {{1'd0}, valid[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_11 = _GEN_41 + _T_9; // @[Bitwise.scala 48:55]
- wire [1:0] _T_13 = valid[4] + valid[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_42 = {{1'd0}, valid[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_15 = _GEN_42 + _T_13; // @[Bitwise.scala 48:55]
- wire [2:0] _T_17 = _T_11[1:0] + _T_15[1:0]; // @[Bitwise.scala 48:55]
- wire _T_21 = ~reset; // @[Regfile.scala 178:11]
- wire _valid_T_21 = io_writeData_5_valid & io_writeData_5_addr == 5'h2; // @[Regfile.scala 157:43]
- wire _valid_T_23 = io_writeData_4_valid & io_writeData_4_addr == 5'h2; // @[Regfile.scala 158:43]
- wire _valid_T_27 = io_writeData_3_valid & io_writeData_3_addr == 5'h2 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_31 = io_writeData_2_valid & io_writeData_2_addr == 5'h2 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_35 = io_writeData_1_valid & io_writeData_1_addr == 5'h2 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_37 = io_writeData_0_valid & io_writeData_0_addr == 5'h2; // @[Regfile.scala 165:43]
- wire [5:0] valid_1 = {_valid_T_21,_valid_T_23,_valid_T_27,_valid_T_31,_valid_T_35,_valid_T_37}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_17 = valid_1[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_19 = valid_1[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_20 = _data_T_17 | _data_T_19; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_22 = valid_1[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_23 = _data_T_20 | _data_T_22; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_25 = valid_1[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_26 = _data_T_23 | _data_T_25; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_28 = valid_1[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_29 = _data_T_26 | _data_T_28; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_31 = valid_1[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_1 = _data_T_29 | _data_T_31; // @[Regfile.scala 172:55]
- wire writeValid_2 = valid_1 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_29 = valid_1[1] + valid_1[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_43 = {{1'd0}, valid_1[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_31 = _GEN_43 + _T_29; // @[Bitwise.scala 48:55]
- wire [1:0] _T_33 = valid_1[4] + valid_1[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_44 = {{1'd0}, valid_1[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_35 = _GEN_44 + _T_33; // @[Bitwise.scala 48:55]
- wire [2:0] _T_37 = _T_31[1:0] + _T_35[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_41 = io_writeData_5_valid & io_writeData_5_addr == 5'h3; // @[Regfile.scala 157:43]
- wire _valid_T_43 = io_writeData_4_valid & io_writeData_4_addr == 5'h3; // @[Regfile.scala 158:43]
- wire _valid_T_47 = io_writeData_3_valid & io_writeData_3_addr == 5'h3 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_51 = io_writeData_2_valid & io_writeData_2_addr == 5'h3 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_55 = io_writeData_1_valid & io_writeData_1_addr == 5'h3 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_57 = io_writeData_0_valid & io_writeData_0_addr == 5'h3; // @[Regfile.scala 165:43]
- wire [5:0] valid_2 = {_valid_T_41,_valid_T_43,_valid_T_47,_valid_T_51,_valid_T_55,_valid_T_57}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_33 = valid_2[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_35 = valid_2[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_36 = _data_T_33 | _data_T_35; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_38 = valid_2[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_39 = _data_T_36 | _data_T_38; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_41 = valid_2[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_42 = _data_T_39 | _data_T_41; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_44 = valid_2[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_45 = _data_T_42 | _data_T_44; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_47 = valid_2[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_2 = _data_T_45 | _data_T_47; // @[Regfile.scala 172:55]
- wire writeValid_3 = valid_2 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_49 = valid_2[1] + valid_2[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_45 = {{1'd0}, valid_2[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_51 = _GEN_45 + _T_49; // @[Bitwise.scala 48:55]
- wire [1:0] _T_53 = valid_2[4] + valid_2[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_46 = {{1'd0}, valid_2[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_55 = _GEN_46 + _T_53; // @[Bitwise.scala 48:55]
- wire [2:0] _T_57 = _T_51[1:0] + _T_55[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_61 = io_writeData_5_valid & io_writeData_5_addr == 5'h4; // @[Regfile.scala 157:43]
- wire _valid_T_63 = io_writeData_4_valid & io_writeData_4_addr == 5'h4; // @[Regfile.scala 158:43]
- wire _valid_T_67 = io_writeData_3_valid & io_writeData_3_addr == 5'h4 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_71 = io_writeData_2_valid & io_writeData_2_addr == 5'h4 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_75 = io_writeData_1_valid & io_writeData_1_addr == 5'h4 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_77 = io_writeData_0_valid & io_writeData_0_addr == 5'h4; // @[Regfile.scala 165:43]
- wire [5:0] valid_3 = {_valid_T_61,_valid_T_63,_valid_T_67,_valid_T_71,_valid_T_75,_valid_T_77}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_49 = valid_3[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_51 = valid_3[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_52 = _data_T_49 | _data_T_51; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_54 = valid_3[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_55 = _data_T_52 | _data_T_54; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_57 = valid_3[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_58 = _data_T_55 | _data_T_57; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_60 = valid_3[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_61 = _data_T_58 | _data_T_60; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_63 = valid_3[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_3 = _data_T_61 | _data_T_63; // @[Regfile.scala 172:55]
- wire writeValid_4 = valid_3 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_69 = valid_3[1] + valid_3[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_47 = {{1'd0}, valid_3[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_71 = _GEN_47 + _T_69; // @[Bitwise.scala 48:55]
- wire [1:0] _T_73 = valid_3[4] + valid_3[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_48 = {{1'd0}, valid_3[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_75 = _GEN_48 + _T_73; // @[Bitwise.scala 48:55]
- wire [2:0] _T_77 = _T_71[1:0] + _T_75[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_81 = io_writeData_5_valid & io_writeData_5_addr == 5'h5; // @[Regfile.scala 157:43]
- wire _valid_T_83 = io_writeData_4_valid & io_writeData_4_addr == 5'h5; // @[Regfile.scala 158:43]
- wire _valid_T_87 = io_writeData_3_valid & io_writeData_3_addr == 5'h5 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_91 = io_writeData_2_valid & io_writeData_2_addr == 5'h5 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_95 = io_writeData_1_valid & io_writeData_1_addr == 5'h5 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_97 = io_writeData_0_valid & io_writeData_0_addr == 5'h5; // @[Regfile.scala 165:43]
- wire [5:0] valid_4 = {_valid_T_81,_valid_T_83,_valid_T_87,_valid_T_91,_valid_T_95,_valid_T_97}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_65 = valid_4[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_67 = valid_4[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_68 = _data_T_65 | _data_T_67; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_70 = valid_4[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_71 = _data_T_68 | _data_T_70; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_73 = valid_4[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_74 = _data_T_71 | _data_T_73; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_76 = valid_4[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_77 = _data_T_74 | _data_T_76; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_79 = valid_4[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_4 = _data_T_77 | _data_T_79; // @[Regfile.scala 172:55]
- wire writeValid_5 = valid_4 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_89 = valid_4[1] + valid_4[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_49 = {{1'd0}, valid_4[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_91 = _GEN_49 + _T_89; // @[Bitwise.scala 48:55]
- wire [1:0] _T_93 = valid_4[4] + valid_4[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_50 = {{1'd0}, valid_4[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_95 = _GEN_50 + _T_93; // @[Bitwise.scala 48:55]
- wire [2:0] _T_97 = _T_91[1:0] + _T_95[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_101 = io_writeData_5_valid & io_writeData_5_addr == 5'h6; // @[Regfile.scala 157:43]
- wire _valid_T_103 = io_writeData_4_valid & io_writeData_4_addr == 5'h6; // @[Regfile.scala 158:43]
- wire _valid_T_107 = io_writeData_3_valid & io_writeData_3_addr == 5'h6 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_111 = io_writeData_2_valid & io_writeData_2_addr == 5'h6 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_115 = io_writeData_1_valid & io_writeData_1_addr == 5'h6 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_117 = io_writeData_0_valid & io_writeData_0_addr == 5'h6; // @[Regfile.scala 165:43]
- wire [5:0] valid_5 = {_valid_T_101,_valid_T_103,_valid_T_107,_valid_T_111,_valid_T_115,_valid_T_117}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_81 = valid_5[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_83 = valid_5[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_84 = _data_T_81 | _data_T_83; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_86 = valid_5[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_87 = _data_T_84 | _data_T_86; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_89 = valid_5[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_90 = _data_T_87 | _data_T_89; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_92 = valid_5[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_93 = _data_T_90 | _data_T_92; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_95 = valid_5[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_5 = _data_T_93 | _data_T_95; // @[Regfile.scala 172:55]
- wire writeValid_6 = valid_5 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_109 = valid_5[1] + valid_5[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_51 = {{1'd0}, valid_5[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_111 = _GEN_51 + _T_109; // @[Bitwise.scala 48:55]
- wire [1:0] _T_113 = valid_5[4] + valid_5[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_52 = {{1'd0}, valid_5[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_115 = _GEN_52 + _T_113; // @[Bitwise.scala 48:55]
- wire [2:0] _T_117 = _T_111[1:0] + _T_115[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_121 = io_writeData_5_valid & io_writeData_5_addr == 5'h7; // @[Regfile.scala 157:43]
- wire _valid_T_123 = io_writeData_4_valid & io_writeData_4_addr == 5'h7; // @[Regfile.scala 158:43]
- wire _valid_T_127 = io_writeData_3_valid & io_writeData_3_addr == 5'h7 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_131 = io_writeData_2_valid & io_writeData_2_addr == 5'h7 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_135 = io_writeData_1_valid & io_writeData_1_addr == 5'h7 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_137 = io_writeData_0_valid & io_writeData_0_addr == 5'h7; // @[Regfile.scala 165:43]
- wire [5:0] valid_6 = {_valid_T_121,_valid_T_123,_valid_T_127,_valid_T_131,_valid_T_135,_valid_T_137}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_97 = valid_6[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_99 = valid_6[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_100 = _data_T_97 | _data_T_99; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_102 = valid_6[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_103 = _data_T_100 | _data_T_102; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_105 = valid_6[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_106 = _data_T_103 | _data_T_105; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_108 = valid_6[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_109 = _data_T_106 | _data_T_108; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_111 = valid_6[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_6 = _data_T_109 | _data_T_111; // @[Regfile.scala 172:55]
- wire writeValid_7 = valid_6 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_129 = valid_6[1] + valid_6[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_53 = {{1'd0}, valid_6[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_131 = _GEN_53 + _T_129; // @[Bitwise.scala 48:55]
- wire [1:0] _T_133 = valid_6[4] + valid_6[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_54 = {{1'd0}, valid_6[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_135 = _GEN_54 + _T_133; // @[Bitwise.scala 48:55]
- wire [2:0] _T_137 = _T_131[1:0] + _T_135[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_141 = io_writeData_5_valid & io_writeData_5_addr == 5'h8; // @[Regfile.scala 157:43]
- wire _valid_T_143 = io_writeData_4_valid & io_writeData_4_addr == 5'h8; // @[Regfile.scala 158:43]
- wire _valid_T_147 = io_writeData_3_valid & io_writeData_3_addr == 5'h8 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_151 = io_writeData_2_valid & io_writeData_2_addr == 5'h8 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_155 = io_writeData_1_valid & io_writeData_1_addr == 5'h8 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_157 = io_writeData_0_valid & io_writeData_0_addr == 5'h8; // @[Regfile.scala 165:43]
- wire [5:0] valid_7 = {_valid_T_141,_valid_T_143,_valid_T_147,_valid_T_151,_valid_T_155,_valid_T_157}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_113 = valid_7[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_115 = valid_7[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_116 = _data_T_113 | _data_T_115; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_118 = valid_7[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_119 = _data_T_116 | _data_T_118; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_121 = valid_7[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_122 = _data_T_119 | _data_T_121; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_124 = valid_7[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_125 = _data_T_122 | _data_T_124; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_127 = valid_7[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_7 = _data_T_125 | _data_T_127; // @[Regfile.scala 172:55]
- wire writeValid_8 = valid_7 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_149 = valid_7[1] + valid_7[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_55 = {{1'd0}, valid_7[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_151 = _GEN_55 + _T_149; // @[Bitwise.scala 48:55]
- wire [1:0] _T_153 = valid_7[4] + valid_7[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_56 = {{1'd0}, valid_7[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_155 = _GEN_56 + _T_153; // @[Bitwise.scala 48:55]
- wire [2:0] _T_157 = _T_151[1:0] + _T_155[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_161 = io_writeData_5_valid & io_writeData_5_addr == 5'h9; // @[Regfile.scala 157:43]
- wire _valid_T_163 = io_writeData_4_valid & io_writeData_4_addr == 5'h9; // @[Regfile.scala 158:43]
- wire _valid_T_167 = io_writeData_3_valid & io_writeData_3_addr == 5'h9 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_171 = io_writeData_2_valid & io_writeData_2_addr == 5'h9 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_175 = io_writeData_1_valid & io_writeData_1_addr == 5'h9 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_177 = io_writeData_0_valid & io_writeData_0_addr == 5'h9; // @[Regfile.scala 165:43]
- wire [5:0] valid_8 = {_valid_T_161,_valid_T_163,_valid_T_167,_valid_T_171,_valid_T_175,_valid_T_177}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_129 = valid_8[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_131 = valid_8[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_132 = _data_T_129 | _data_T_131; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_134 = valid_8[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_135 = _data_T_132 | _data_T_134; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_137 = valid_8[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_138 = _data_T_135 | _data_T_137; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_140 = valid_8[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_141 = _data_T_138 | _data_T_140; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_143 = valid_8[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_8 = _data_T_141 | _data_T_143; // @[Regfile.scala 172:55]
- wire writeValid_9 = valid_8 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_169 = valid_8[1] + valid_8[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_57 = {{1'd0}, valid_8[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_171 = _GEN_57 + _T_169; // @[Bitwise.scala 48:55]
- wire [1:0] _T_173 = valid_8[4] + valid_8[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_58 = {{1'd0}, valid_8[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_175 = _GEN_58 + _T_173; // @[Bitwise.scala 48:55]
- wire [2:0] _T_177 = _T_171[1:0] + _T_175[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_181 = io_writeData_5_valid & io_writeData_5_addr == 5'ha; // @[Regfile.scala 157:43]
- wire _valid_T_183 = io_writeData_4_valid & io_writeData_4_addr == 5'ha; // @[Regfile.scala 158:43]
- wire _valid_T_187 = io_writeData_3_valid & io_writeData_3_addr == 5'ha & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_191 = io_writeData_2_valid & io_writeData_2_addr == 5'ha & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_195 = io_writeData_1_valid & io_writeData_1_addr == 5'ha & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_197 = io_writeData_0_valid & io_writeData_0_addr == 5'ha; // @[Regfile.scala 165:43]
- wire [5:0] valid_9 = {_valid_T_181,_valid_T_183,_valid_T_187,_valid_T_191,_valid_T_195,_valid_T_197}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_145 = valid_9[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_147 = valid_9[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_148 = _data_T_145 | _data_T_147; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_150 = valid_9[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_151 = _data_T_148 | _data_T_150; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_153 = valid_9[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_154 = _data_T_151 | _data_T_153; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_156 = valid_9[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_157 = _data_T_154 | _data_T_156; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_159 = valid_9[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_9 = _data_T_157 | _data_T_159; // @[Regfile.scala 172:55]
- wire writeValid_10 = valid_9 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_189 = valid_9[1] + valid_9[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_59 = {{1'd0}, valid_9[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_191 = _GEN_59 + _T_189; // @[Bitwise.scala 48:55]
- wire [1:0] _T_193 = valid_9[4] + valid_9[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_60 = {{1'd0}, valid_9[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_195 = _GEN_60 + _T_193; // @[Bitwise.scala 48:55]
- wire [2:0] _T_197 = _T_191[1:0] + _T_195[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_201 = io_writeData_5_valid & io_writeData_5_addr == 5'hb; // @[Regfile.scala 157:43]
- wire _valid_T_203 = io_writeData_4_valid & io_writeData_4_addr == 5'hb; // @[Regfile.scala 158:43]
- wire _valid_T_207 = io_writeData_3_valid & io_writeData_3_addr == 5'hb & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_211 = io_writeData_2_valid & io_writeData_2_addr == 5'hb & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_215 = io_writeData_1_valid & io_writeData_1_addr == 5'hb & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_217 = io_writeData_0_valid & io_writeData_0_addr == 5'hb; // @[Regfile.scala 165:43]
- wire [5:0] valid_10 = {_valid_T_201,_valid_T_203,_valid_T_207,_valid_T_211,_valid_T_215,_valid_T_217}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_161 = valid_10[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_163 = valid_10[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_164 = _data_T_161 | _data_T_163; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_166 = valid_10[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_167 = _data_T_164 | _data_T_166; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_169 = valid_10[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_170 = _data_T_167 | _data_T_169; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_172 = valid_10[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_173 = _data_T_170 | _data_T_172; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_175 = valid_10[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_10 = _data_T_173 | _data_T_175; // @[Regfile.scala 172:55]
- wire writeValid_11 = valid_10 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_209 = valid_10[1] + valid_10[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_61 = {{1'd0}, valid_10[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_211 = _GEN_61 + _T_209; // @[Bitwise.scala 48:55]
- wire [1:0] _T_213 = valid_10[4] + valid_10[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_62 = {{1'd0}, valid_10[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_215 = _GEN_62 + _T_213; // @[Bitwise.scala 48:55]
- wire [2:0] _T_217 = _T_211[1:0] + _T_215[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_221 = io_writeData_5_valid & io_writeData_5_addr == 5'hc; // @[Regfile.scala 157:43]
- wire _valid_T_223 = io_writeData_4_valid & io_writeData_4_addr == 5'hc; // @[Regfile.scala 158:43]
- wire _valid_T_227 = io_writeData_3_valid & io_writeData_3_addr == 5'hc & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_231 = io_writeData_2_valid & io_writeData_2_addr == 5'hc & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_235 = io_writeData_1_valid & io_writeData_1_addr == 5'hc & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_237 = io_writeData_0_valid & io_writeData_0_addr == 5'hc; // @[Regfile.scala 165:43]
- wire [5:0] valid_11 = {_valid_T_221,_valid_T_223,_valid_T_227,_valid_T_231,_valid_T_235,_valid_T_237}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_177 = valid_11[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_179 = valid_11[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_180 = _data_T_177 | _data_T_179; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_182 = valid_11[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_183 = _data_T_180 | _data_T_182; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_185 = valid_11[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_186 = _data_T_183 | _data_T_185; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_188 = valid_11[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_189 = _data_T_186 | _data_T_188; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_191 = valid_11[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_11 = _data_T_189 | _data_T_191; // @[Regfile.scala 172:55]
- wire writeValid_12 = valid_11 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_229 = valid_11[1] + valid_11[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_63 = {{1'd0}, valid_11[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_231 = _GEN_63 + _T_229; // @[Bitwise.scala 48:55]
- wire [1:0] _T_233 = valid_11[4] + valid_11[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_64 = {{1'd0}, valid_11[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_235 = _GEN_64 + _T_233; // @[Bitwise.scala 48:55]
- wire [2:0] _T_237 = _T_231[1:0] + _T_235[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_241 = io_writeData_5_valid & io_writeData_5_addr == 5'hd; // @[Regfile.scala 157:43]
- wire _valid_T_243 = io_writeData_4_valid & io_writeData_4_addr == 5'hd; // @[Regfile.scala 158:43]
- wire _valid_T_247 = io_writeData_3_valid & io_writeData_3_addr == 5'hd & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_251 = io_writeData_2_valid & io_writeData_2_addr == 5'hd & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_255 = io_writeData_1_valid & io_writeData_1_addr == 5'hd & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_257 = io_writeData_0_valid & io_writeData_0_addr == 5'hd; // @[Regfile.scala 165:43]
- wire [5:0] valid_12 = {_valid_T_241,_valid_T_243,_valid_T_247,_valid_T_251,_valid_T_255,_valid_T_257}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_193 = valid_12[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_195 = valid_12[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_196 = _data_T_193 | _data_T_195; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_198 = valid_12[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_199 = _data_T_196 | _data_T_198; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_201 = valid_12[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_202 = _data_T_199 | _data_T_201; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_204 = valid_12[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_205 = _data_T_202 | _data_T_204; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_207 = valid_12[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_12 = _data_T_205 | _data_T_207; // @[Regfile.scala 172:55]
- wire writeValid_13 = valid_12 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_249 = valid_12[1] + valid_12[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_65 = {{1'd0}, valid_12[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_251 = _GEN_65 + _T_249; // @[Bitwise.scala 48:55]
- wire [1:0] _T_253 = valid_12[4] + valid_12[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_66 = {{1'd0}, valid_12[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_255 = _GEN_66 + _T_253; // @[Bitwise.scala 48:55]
- wire [2:0] _T_257 = _T_251[1:0] + _T_255[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_261 = io_writeData_5_valid & io_writeData_5_addr == 5'he; // @[Regfile.scala 157:43]
- wire _valid_T_263 = io_writeData_4_valid & io_writeData_4_addr == 5'he; // @[Regfile.scala 158:43]
- wire _valid_T_267 = io_writeData_3_valid & io_writeData_3_addr == 5'he & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_271 = io_writeData_2_valid & io_writeData_2_addr == 5'he & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_275 = io_writeData_1_valid & io_writeData_1_addr == 5'he & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_277 = io_writeData_0_valid & io_writeData_0_addr == 5'he; // @[Regfile.scala 165:43]
- wire [5:0] valid_13 = {_valid_T_261,_valid_T_263,_valid_T_267,_valid_T_271,_valid_T_275,_valid_T_277}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_209 = valid_13[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_211 = valid_13[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_212 = _data_T_209 | _data_T_211; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_214 = valid_13[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_215 = _data_T_212 | _data_T_214; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_217 = valid_13[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_218 = _data_T_215 | _data_T_217; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_220 = valid_13[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_221 = _data_T_218 | _data_T_220; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_223 = valid_13[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_13 = _data_T_221 | _data_T_223; // @[Regfile.scala 172:55]
- wire writeValid_14 = valid_13 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_269 = valid_13[1] + valid_13[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_67 = {{1'd0}, valid_13[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_271 = _GEN_67 + _T_269; // @[Bitwise.scala 48:55]
- wire [1:0] _T_273 = valid_13[4] + valid_13[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_68 = {{1'd0}, valid_13[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_275 = _GEN_68 + _T_273; // @[Bitwise.scala 48:55]
- wire [2:0] _T_277 = _T_271[1:0] + _T_275[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_281 = io_writeData_5_valid & io_writeData_5_addr == 5'hf; // @[Regfile.scala 157:43]
- wire _valid_T_283 = io_writeData_4_valid & io_writeData_4_addr == 5'hf; // @[Regfile.scala 158:43]
- wire _valid_T_287 = io_writeData_3_valid & io_writeData_3_addr == 5'hf & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_291 = io_writeData_2_valid & io_writeData_2_addr == 5'hf & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_295 = io_writeData_1_valid & io_writeData_1_addr == 5'hf & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_297 = io_writeData_0_valid & io_writeData_0_addr == 5'hf; // @[Regfile.scala 165:43]
- wire [5:0] valid_14 = {_valid_T_281,_valid_T_283,_valid_T_287,_valid_T_291,_valid_T_295,_valid_T_297}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_225 = valid_14[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_227 = valid_14[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_228 = _data_T_225 | _data_T_227; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_230 = valid_14[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_231 = _data_T_228 | _data_T_230; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_233 = valid_14[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_234 = _data_T_231 | _data_T_233; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_236 = valid_14[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_237 = _data_T_234 | _data_T_236; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_239 = valid_14[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_14 = _data_T_237 | _data_T_239; // @[Regfile.scala 172:55]
- wire writeValid_15 = valid_14 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_289 = valid_14[1] + valid_14[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_69 = {{1'd0}, valid_14[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_291 = _GEN_69 + _T_289; // @[Bitwise.scala 48:55]
- wire [1:0] _T_293 = valid_14[4] + valid_14[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_70 = {{1'd0}, valid_14[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_295 = _GEN_70 + _T_293; // @[Bitwise.scala 48:55]
- wire [2:0] _T_297 = _T_291[1:0] + _T_295[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_301 = io_writeData_5_valid & io_writeData_5_addr == 5'h10; // @[Regfile.scala 157:43]
- wire _valid_T_303 = io_writeData_4_valid & io_writeData_4_addr == 5'h10; // @[Regfile.scala 158:43]
- wire _valid_T_307 = io_writeData_3_valid & io_writeData_3_addr == 5'h10 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_311 = io_writeData_2_valid & io_writeData_2_addr == 5'h10 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_315 = io_writeData_1_valid & io_writeData_1_addr == 5'h10 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_317 = io_writeData_0_valid & io_writeData_0_addr == 5'h10; // @[Regfile.scala 165:43]
- wire [5:0] valid_15 = {_valid_T_301,_valid_T_303,_valid_T_307,_valid_T_311,_valid_T_315,_valid_T_317}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_241 = valid_15[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_243 = valid_15[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_244 = _data_T_241 | _data_T_243; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_246 = valid_15[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_247 = _data_T_244 | _data_T_246; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_249 = valid_15[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_250 = _data_T_247 | _data_T_249; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_252 = valid_15[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_253 = _data_T_250 | _data_T_252; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_255 = valid_15[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_15 = _data_T_253 | _data_T_255; // @[Regfile.scala 172:55]
- wire writeValid_16 = valid_15 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_309 = valid_15[1] + valid_15[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_71 = {{1'd0}, valid_15[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_311 = _GEN_71 + _T_309; // @[Bitwise.scala 48:55]
- wire [1:0] _T_313 = valid_15[4] + valid_15[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_72 = {{1'd0}, valid_15[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_315 = _GEN_72 + _T_313; // @[Bitwise.scala 48:55]
- wire [2:0] _T_317 = _T_311[1:0] + _T_315[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_321 = io_writeData_5_valid & io_writeData_5_addr == 5'h11; // @[Regfile.scala 157:43]
- wire _valid_T_323 = io_writeData_4_valid & io_writeData_4_addr == 5'h11; // @[Regfile.scala 158:43]
- wire _valid_T_327 = io_writeData_3_valid & io_writeData_3_addr == 5'h11 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_331 = io_writeData_2_valid & io_writeData_2_addr == 5'h11 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_335 = io_writeData_1_valid & io_writeData_1_addr == 5'h11 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_337 = io_writeData_0_valid & io_writeData_0_addr == 5'h11; // @[Regfile.scala 165:43]
- wire [5:0] valid_16 = {_valid_T_321,_valid_T_323,_valid_T_327,_valid_T_331,_valid_T_335,_valid_T_337}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_257 = valid_16[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_259 = valid_16[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_260 = _data_T_257 | _data_T_259; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_262 = valid_16[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_263 = _data_T_260 | _data_T_262; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_265 = valid_16[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_266 = _data_T_263 | _data_T_265; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_268 = valid_16[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_269 = _data_T_266 | _data_T_268; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_271 = valid_16[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_16 = _data_T_269 | _data_T_271; // @[Regfile.scala 172:55]
- wire writeValid_17 = valid_16 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_329 = valid_16[1] + valid_16[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_73 = {{1'd0}, valid_16[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_331 = _GEN_73 + _T_329; // @[Bitwise.scala 48:55]
- wire [1:0] _T_333 = valid_16[4] + valid_16[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_74 = {{1'd0}, valid_16[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_335 = _GEN_74 + _T_333; // @[Bitwise.scala 48:55]
- wire [2:0] _T_337 = _T_331[1:0] + _T_335[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_341 = io_writeData_5_valid & io_writeData_5_addr == 5'h12; // @[Regfile.scala 157:43]
- wire _valid_T_343 = io_writeData_4_valid & io_writeData_4_addr == 5'h12; // @[Regfile.scala 158:43]
- wire _valid_T_347 = io_writeData_3_valid & io_writeData_3_addr == 5'h12 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_351 = io_writeData_2_valid & io_writeData_2_addr == 5'h12 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_355 = io_writeData_1_valid & io_writeData_1_addr == 5'h12 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_357 = io_writeData_0_valid & io_writeData_0_addr == 5'h12; // @[Regfile.scala 165:43]
- wire [5:0] valid_17 = {_valid_T_341,_valid_T_343,_valid_T_347,_valid_T_351,_valid_T_355,_valid_T_357}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_273 = valid_17[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_275 = valid_17[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_276 = _data_T_273 | _data_T_275; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_278 = valid_17[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_279 = _data_T_276 | _data_T_278; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_281 = valid_17[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_282 = _data_T_279 | _data_T_281; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_284 = valid_17[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_285 = _data_T_282 | _data_T_284; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_287 = valid_17[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_17 = _data_T_285 | _data_T_287; // @[Regfile.scala 172:55]
- wire writeValid_18 = valid_17 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_349 = valid_17[1] + valid_17[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_75 = {{1'd0}, valid_17[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_351 = _GEN_75 + _T_349; // @[Bitwise.scala 48:55]
- wire [1:0] _T_353 = valid_17[4] + valid_17[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_76 = {{1'd0}, valid_17[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_355 = _GEN_76 + _T_353; // @[Bitwise.scala 48:55]
- wire [2:0] _T_357 = _T_351[1:0] + _T_355[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_361 = io_writeData_5_valid & io_writeData_5_addr == 5'h13; // @[Regfile.scala 157:43]
- wire _valid_T_363 = io_writeData_4_valid & io_writeData_4_addr == 5'h13; // @[Regfile.scala 158:43]
- wire _valid_T_367 = io_writeData_3_valid & io_writeData_3_addr == 5'h13 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_371 = io_writeData_2_valid & io_writeData_2_addr == 5'h13 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_375 = io_writeData_1_valid & io_writeData_1_addr == 5'h13 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_377 = io_writeData_0_valid & io_writeData_0_addr == 5'h13; // @[Regfile.scala 165:43]
- wire [5:0] valid_18 = {_valid_T_361,_valid_T_363,_valid_T_367,_valid_T_371,_valid_T_375,_valid_T_377}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_289 = valid_18[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_291 = valid_18[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_292 = _data_T_289 | _data_T_291; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_294 = valid_18[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_295 = _data_T_292 | _data_T_294; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_297 = valid_18[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_298 = _data_T_295 | _data_T_297; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_300 = valid_18[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_301 = _data_T_298 | _data_T_300; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_303 = valid_18[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_18 = _data_T_301 | _data_T_303; // @[Regfile.scala 172:55]
- wire writeValid_19 = valid_18 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_369 = valid_18[1] + valid_18[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_77 = {{1'd0}, valid_18[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_371 = _GEN_77 + _T_369; // @[Bitwise.scala 48:55]
- wire [1:0] _T_373 = valid_18[4] + valid_18[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_78 = {{1'd0}, valid_18[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_375 = _GEN_78 + _T_373; // @[Bitwise.scala 48:55]
- wire [2:0] _T_377 = _T_371[1:0] + _T_375[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_381 = io_writeData_5_valid & io_writeData_5_addr == 5'h14; // @[Regfile.scala 157:43]
- wire _valid_T_383 = io_writeData_4_valid & io_writeData_4_addr == 5'h14; // @[Regfile.scala 158:43]
- wire _valid_T_387 = io_writeData_3_valid & io_writeData_3_addr == 5'h14 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_391 = io_writeData_2_valid & io_writeData_2_addr == 5'h14 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_395 = io_writeData_1_valid & io_writeData_1_addr == 5'h14 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_397 = io_writeData_0_valid & io_writeData_0_addr == 5'h14; // @[Regfile.scala 165:43]
- wire [5:0] valid_19 = {_valid_T_381,_valid_T_383,_valid_T_387,_valid_T_391,_valid_T_395,_valid_T_397}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_305 = valid_19[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_307 = valid_19[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_308 = _data_T_305 | _data_T_307; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_310 = valid_19[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_311 = _data_T_308 | _data_T_310; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_313 = valid_19[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_314 = _data_T_311 | _data_T_313; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_316 = valid_19[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_317 = _data_T_314 | _data_T_316; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_319 = valid_19[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_19 = _data_T_317 | _data_T_319; // @[Regfile.scala 172:55]
- wire writeValid_20 = valid_19 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_389 = valid_19[1] + valid_19[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_79 = {{1'd0}, valid_19[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_391 = _GEN_79 + _T_389; // @[Bitwise.scala 48:55]
- wire [1:0] _T_393 = valid_19[4] + valid_19[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_80 = {{1'd0}, valid_19[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_395 = _GEN_80 + _T_393; // @[Bitwise.scala 48:55]
- wire [2:0] _T_397 = _T_391[1:0] + _T_395[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_401 = io_writeData_5_valid & io_writeData_5_addr == 5'h15; // @[Regfile.scala 157:43]
- wire _valid_T_403 = io_writeData_4_valid & io_writeData_4_addr == 5'h15; // @[Regfile.scala 158:43]
- wire _valid_T_407 = io_writeData_3_valid & io_writeData_3_addr == 5'h15 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_411 = io_writeData_2_valid & io_writeData_2_addr == 5'h15 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_415 = io_writeData_1_valid & io_writeData_1_addr == 5'h15 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_417 = io_writeData_0_valid & io_writeData_0_addr == 5'h15; // @[Regfile.scala 165:43]
- wire [5:0] valid_20 = {_valid_T_401,_valid_T_403,_valid_T_407,_valid_T_411,_valid_T_415,_valid_T_417}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_321 = valid_20[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_323 = valid_20[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_324 = _data_T_321 | _data_T_323; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_326 = valid_20[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_327 = _data_T_324 | _data_T_326; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_329 = valid_20[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_330 = _data_T_327 | _data_T_329; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_332 = valid_20[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_333 = _data_T_330 | _data_T_332; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_335 = valid_20[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_20 = _data_T_333 | _data_T_335; // @[Regfile.scala 172:55]
- wire writeValid_21 = valid_20 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_409 = valid_20[1] + valid_20[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_81 = {{1'd0}, valid_20[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_411 = _GEN_81 + _T_409; // @[Bitwise.scala 48:55]
- wire [1:0] _T_413 = valid_20[4] + valid_20[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_82 = {{1'd0}, valid_20[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_415 = _GEN_82 + _T_413; // @[Bitwise.scala 48:55]
- wire [2:0] _T_417 = _T_411[1:0] + _T_415[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_421 = io_writeData_5_valid & io_writeData_5_addr == 5'h16; // @[Regfile.scala 157:43]
- wire _valid_T_423 = io_writeData_4_valid & io_writeData_4_addr == 5'h16; // @[Regfile.scala 158:43]
- wire _valid_T_427 = io_writeData_3_valid & io_writeData_3_addr == 5'h16 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_431 = io_writeData_2_valid & io_writeData_2_addr == 5'h16 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_435 = io_writeData_1_valid & io_writeData_1_addr == 5'h16 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_437 = io_writeData_0_valid & io_writeData_0_addr == 5'h16; // @[Regfile.scala 165:43]
- wire [5:0] valid_21 = {_valid_T_421,_valid_T_423,_valid_T_427,_valid_T_431,_valid_T_435,_valid_T_437}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_337 = valid_21[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_339 = valid_21[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_340 = _data_T_337 | _data_T_339; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_342 = valid_21[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_343 = _data_T_340 | _data_T_342; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_345 = valid_21[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_346 = _data_T_343 | _data_T_345; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_348 = valid_21[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_349 = _data_T_346 | _data_T_348; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_351 = valid_21[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_21 = _data_T_349 | _data_T_351; // @[Regfile.scala 172:55]
- wire writeValid_22 = valid_21 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_429 = valid_21[1] + valid_21[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_83 = {{1'd0}, valid_21[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_431 = _GEN_83 + _T_429; // @[Bitwise.scala 48:55]
- wire [1:0] _T_433 = valid_21[4] + valid_21[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_84 = {{1'd0}, valid_21[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_435 = _GEN_84 + _T_433; // @[Bitwise.scala 48:55]
- wire [2:0] _T_437 = _T_431[1:0] + _T_435[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_441 = io_writeData_5_valid & io_writeData_5_addr == 5'h17; // @[Regfile.scala 157:43]
- wire _valid_T_443 = io_writeData_4_valid & io_writeData_4_addr == 5'h17; // @[Regfile.scala 158:43]
- wire _valid_T_447 = io_writeData_3_valid & io_writeData_3_addr == 5'h17 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_451 = io_writeData_2_valid & io_writeData_2_addr == 5'h17 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_455 = io_writeData_1_valid & io_writeData_1_addr == 5'h17 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_457 = io_writeData_0_valid & io_writeData_0_addr == 5'h17; // @[Regfile.scala 165:43]
- wire [5:0] valid_22 = {_valid_T_441,_valid_T_443,_valid_T_447,_valid_T_451,_valid_T_455,_valid_T_457}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_353 = valid_22[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_355 = valid_22[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_356 = _data_T_353 | _data_T_355; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_358 = valid_22[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_359 = _data_T_356 | _data_T_358; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_361 = valid_22[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_362 = _data_T_359 | _data_T_361; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_364 = valid_22[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_365 = _data_T_362 | _data_T_364; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_367 = valid_22[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_22 = _data_T_365 | _data_T_367; // @[Regfile.scala 172:55]
- wire writeValid_23 = valid_22 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_449 = valid_22[1] + valid_22[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_85 = {{1'd0}, valid_22[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_451 = _GEN_85 + _T_449; // @[Bitwise.scala 48:55]
- wire [1:0] _T_453 = valid_22[4] + valid_22[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_86 = {{1'd0}, valid_22[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_455 = _GEN_86 + _T_453; // @[Bitwise.scala 48:55]
- wire [2:0] _T_457 = _T_451[1:0] + _T_455[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_461 = io_writeData_5_valid & io_writeData_5_addr == 5'h18; // @[Regfile.scala 157:43]
- wire _valid_T_463 = io_writeData_4_valid & io_writeData_4_addr == 5'h18; // @[Regfile.scala 158:43]
- wire _valid_T_467 = io_writeData_3_valid & io_writeData_3_addr == 5'h18 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_471 = io_writeData_2_valid & io_writeData_2_addr == 5'h18 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_475 = io_writeData_1_valid & io_writeData_1_addr == 5'h18 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_477 = io_writeData_0_valid & io_writeData_0_addr == 5'h18; // @[Regfile.scala 165:43]
- wire [5:0] valid_23 = {_valid_T_461,_valid_T_463,_valid_T_467,_valid_T_471,_valid_T_475,_valid_T_477}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_369 = valid_23[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_371 = valid_23[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_372 = _data_T_369 | _data_T_371; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_374 = valid_23[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_375 = _data_T_372 | _data_T_374; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_377 = valid_23[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_378 = _data_T_375 | _data_T_377; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_380 = valid_23[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_381 = _data_T_378 | _data_T_380; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_383 = valid_23[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_23 = _data_T_381 | _data_T_383; // @[Regfile.scala 172:55]
- wire writeValid_24 = valid_23 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_469 = valid_23[1] + valid_23[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_87 = {{1'd0}, valid_23[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_471 = _GEN_87 + _T_469; // @[Bitwise.scala 48:55]
- wire [1:0] _T_473 = valid_23[4] + valid_23[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_88 = {{1'd0}, valid_23[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_475 = _GEN_88 + _T_473; // @[Bitwise.scala 48:55]
- wire [2:0] _T_477 = _T_471[1:0] + _T_475[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_481 = io_writeData_5_valid & io_writeData_5_addr == 5'h19; // @[Regfile.scala 157:43]
- wire _valid_T_483 = io_writeData_4_valid & io_writeData_4_addr == 5'h19; // @[Regfile.scala 158:43]
- wire _valid_T_487 = io_writeData_3_valid & io_writeData_3_addr == 5'h19 & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_491 = io_writeData_2_valid & io_writeData_2_addr == 5'h19 & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_495 = io_writeData_1_valid & io_writeData_1_addr == 5'h19 & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_497 = io_writeData_0_valid & io_writeData_0_addr == 5'h19; // @[Regfile.scala 165:43]
- wire [5:0] valid_24 = {_valid_T_481,_valid_T_483,_valid_T_487,_valid_T_491,_valid_T_495,_valid_T_497}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_385 = valid_24[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_387 = valid_24[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_388 = _data_T_385 | _data_T_387; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_390 = valid_24[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_391 = _data_T_388 | _data_T_390; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_393 = valid_24[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_394 = _data_T_391 | _data_T_393; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_396 = valid_24[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_397 = _data_T_394 | _data_T_396; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_399 = valid_24[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_24 = _data_T_397 | _data_T_399; // @[Regfile.scala 172:55]
- wire writeValid_25 = valid_24 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_489 = valid_24[1] + valid_24[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_89 = {{1'd0}, valid_24[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_491 = _GEN_89 + _T_489; // @[Bitwise.scala 48:55]
- wire [1:0] _T_493 = valid_24[4] + valid_24[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_90 = {{1'd0}, valid_24[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_495 = _GEN_90 + _T_493; // @[Bitwise.scala 48:55]
- wire [2:0] _T_497 = _T_491[1:0] + _T_495[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_501 = io_writeData_5_valid & io_writeData_5_addr == 5'h1a; // @[Regfile.scala 157:43]
- wire _valid_T_503 = io_writeData_4_valid & io_writeData_4_addr == 5'h1a; // @[Regfile.scala 158:43]
- wire _valid_T_507 = io_writeData_3_valid & io_writeData_3_addr == 5'h1a & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_511 = io_writeData_2_valid & io_writeData_2_addr == 5'h1a & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_515 = io_writeData_1_valid & io_writeData_1_addr == 5'h1a & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_517 = io_writeData_0_valid & io_writeData_0_addr == 5'h1a; // @[Regfile.scala 165:43]
- wire [5:0] valid_25 = {_valid_T_501,_valid_T_503,_valid_T_507,_valid_T_511,_valid_T_515,_valid_T_517}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_401 = valid_25[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_403 = valid_25[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_404 = _data_T_401 | _data_T_403; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_406 = valid_25[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_407 = _data_T_404 | _data_T_406; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_409 = valid_25[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_410 = _data_T_407 | _data_T_409; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_412 = valid_25[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_413 = _data_T_410 | _data_T_412; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_415 = valid_25[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_25 = _data_T_413 | _data_T_415; // @[Regfile.scala 172:55]
- wire writeValid_26 = valid_25 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_509 = valid_25[1] + valid_25[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_91 = {{1'd0}, valid_25[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_511 = _GEN_91 + _T_509; // @[Bitwise.scala 48:55]
- wire [1:0] _T_513 = valid_25[4] + valid_25[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_92 = {{1'd0}, valid_25[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_515 = _GEN_92 + _T_513; // @[Bitwise.scala 48:55]
- wire [2:0] _T_517 = _T_511[1:0] + _T_515[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_521 = io_writeData_5_valid & io_writeData_5_addr == 5'h1b; // @[Regfile.scala 157:43]
- wire _valid_T_523 = io_writeData_4_valid & io_writeData_4_addr == 5'h1b; // @[Regfile.scala 158:43]
- wire _valid_T_527 = io_writeData_3_valid & io_writeData_3_addr == 5'h1b & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_531 = io_writeData_2_valid & io_writeData_2_addr == 5'h1b & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_535 = io_writeData_1_valid & io_writeData_1_addr == 5'h1b & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_537 = io_writeData_0_valid & io_writeData_0_addr == 5'h1b; // @[Regfile.scala 165:43]
- wire [5:0] valid_26 = {_valid_T_521,_valid_T_523,_valid_T_527,_valid_T_531,_valid_T_535,_valid_T_537}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_417 = valid_26[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_419 = valid_26[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_420 = _data_T_417 | _data_T_419; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_422 = valid_26[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_423 = _data_T_420 | _data_T_422; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_425 = valid_26[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_426 = _data_T_423 | _data_T_425; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_428 = valid_26[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_429 = _data_T_426 | _data_T_428; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_431 = valid_26[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_26 = _data_T_429 | _data_T_431; // @[Regfile.scala 172:55]
- wire writeValid_27 = valid_26 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_529 = valid_26[1] + valid_26[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_93 = {{1'd0}, valid_26[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_531 = _GEN_93 + _T_529; // @[Bitwise.scala 48:55]
- wire [1:0] _T_533 = valid_26[4] + valid_26[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_94 = {{1'd0}, valid_26[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_535 = _GEN_94 + _T_533; // @[Bitwise.scala 48:55]
- wire [2:0] _T_537 = _T_531[1:0] + _T_535[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_541 = io_writeData_5_valid & io_writeData_5_addr == 5'h1c; // @[Regfile.scala 157:43]
- wire _valid_T_543 = io_writeData_4_valid & io_writeData_4_addr == 5'h1c; // @[Regfile.scala 158:43]
- wire _valid_T_547 = io_writeData_3_valid & io_writeData_3_addr == 5'h1c & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_551 = io_writeData_2_valid & io_writeData_2_addr == 5'h1c & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_555 = io_writeData_1_valid & io_writeData_1_addr == 5'h1c & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_557 = io_writeData_0_valid & io_writeData_0_addr == 5'h1c; // @[Regfile.scala 165:43]
- wire [5:0] valid_27 = {_valid_T_541,_valid_T_543,_valid_T_547,_valid_T_551,_valid_T_555,_valid_T_557}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_433 = valid_27[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_435 = valid_27[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_436 = _data_T_433 | _data_T_435; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_438 = valid_27[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_439 = _data_T_436 | _data_T_438; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_441 = valid_27[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_442 = _data_T_439 | _data_T_441; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_444 = valid_27[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_445 = _data_T_442 | _data_T_444; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_447 = valid_27[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_27 = _data_T_445 | _data_T_447; // @[Regfile.scala 172:55]
- wire writeValid_28 = valid_27 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_549 = valid_27[1] + valid_27[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_95 = {{1'd0}, valid_27[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_551 = _GEN_95 + _T_549; // @[Bitwise.scala 48:55]
- wire [1:0] _T_553 = valid_27[4] + valid_27[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_96 = {{1'd0}, valid_27[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_555 = _GEN_96 + _T_553; // @[Bitwise.scala 48:55]
- wire [2:0] _T_557 = _T_551[1:0] + _T_555[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_561 = io_writeData_5_valid & io_writeData_5_addr == 5'h1d; // @[Regfile.scala 157:43]
- wire _valid_T_563 = io_writeData_4_valid & io_writeData_4_addr == 5'h1d; // @[Regfile.scala 158:43]
- wire _valid_T_567 = io_writeData_3_valid & io_writeData_3_addr == 5'h1d & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_571 = io_writeData_2_valid & io_writeData_2_addr == 5'h1d & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_575 = io_writeData_1_valid & io_writeData_1_addr == 5'h1d & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_577 = io_writeData_0_valid & io_writeData_0_addr == 5'h1d; // @[Regfile.scala 165:43]
- wire [5:0] valid_28 = {_valid_T_561,_valid_T_563,_valid_T_567,_valid_T_571,_valid_T_575,_valid_T_577}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_449 = valid_28[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_451 = valid_28[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_452 = _data_T_449 | _data_T_451; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_454 = valid_28[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_455 = _data_T_452 | _data_T_454; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_457 = valid_28[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_458 = _data_T_455 | _data_T_457; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_460 = valid_28[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_461 = _data_T_458 | _data_T_460; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_463 = valid_28[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_28 = _data_T_461 | _data_T_463; // @[Regfile.scala 172:55]
- wire writeValid_29 = valid_28 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_569 = valid_28[1] + valid_28[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_97 = {{1'd0}, valid_28[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_571 = _GEN_97 + _T_569; // @[Bitwise.scala 48:55]
- wire [1:0] _T_573 = valid_28[4] + valid_28[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_98 = {{1'd0}, valid_28[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_575 = _GEN_98 + _T_573; // @[Bitwise.scala 48:55]
- wire [2:0] _T_577 = _T_571[1:0] + _T_575[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_581 = io_writeData_5_valid & io_writeData_5_addr == 5'h1e; // @[Regfile.scala 157:43]
- wire _valid_T_583 = io_writeData_4_valid & io_writeData_4_addr == 5'h1e; // @[Regfile.scala 158:43]
- wire _valid_T_587 = io_writeData_3_valid & io_writeData_3_addr == 5'h1e & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_591 = io_writeData_2_valid & io_writeData_2_addr == 5'h1e & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_595 = io_writeData_1_valid & io_writeData_1_addr == 5'h1e & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_597 = io_writeData_0_valid & io_writeData_0_addr == 5'h1e; // @[Regfile.scala 165:43]
- wire [5:0] valid_29 = {_valid_T_581,_valid_T_583,_valid_T_587,_valid_T_591,_valid_T_595,_valid_T_597}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_465 = valid_29[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_467 = valid_29[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_468 = _data_T_465 | _data_T_467; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_470 = valid_29[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_471 = _data_T_468 | _data_T_470; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_473 = valid_29[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_474 = _data_T_471 | _data_T_473; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_476 = valid_29[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_477 = _data_T_474 | _data_T_476; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_479 = valid_29[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_29 = _data_T_477 | _data_T_479; // @[Regfile.scala 172:55]
- wire writeValid_30 = valid_29 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_589 = valid_29[1] + valid_29[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_99 = {{1'd0}, valid_29[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_591 = _GEN_99 + _T_589; // @[Bitwise.scala 48:55]
- wire [1:0] _T_593 = valid_29[4] + valid_29[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_100 = {{1'd0}, valid_29[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_595 = _GEN_100 + _T_593; // @[Bitwise.scala 48:55]
- wire [2:0] _T_597 = _T_591[1:0] + _T_595[1:0]; // @[Bitwise.scala 48:55]
- wire _valid_T_601 = io_writeData_5_valid & io_writeData_5_addr == 5'h1f; // @[Regfile.scala 157:43]
- wire _valid_T_603 = io_writeData_4_valid & io_writeData_4_addr == 5'h1f; // @[Regfile.scala 158:43]
- wire _valid_T_607 = io_writeData_3_valid & io_writeData_3_addr == 5'h1f & _valid_T_6; // @[Regfile.scala 159:75]
- wire _valid_T_611 = io_writeData_2_valid & io_writeData_2_addr == 5'h1f & _valid_T_10; // @[Regfile.scala 161:75]
- wire _valid_T_615 = io_writeData_1_valid & io_writeData_1_addr == 5'h1f & _valid_T_14; // @[Regfile.scala 163:75]
- wire _valid_T_617 = io_writeData_0_valid & io_writeData_0_addr == 5'h1f; // @[Regfile.scala 165:43]
- wire [5:0] valid_30 = {_valid_T_601,_valid_T_603,_valid_T_607,_valid_T_611,_valid_T_615,_valid_T_617}; // @[Cat.scala 31:58]
- wire [31:0] _data_T_481 = valid_30[0] ? io_writeData_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_483 = valid_30[1] ? io_writeData_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_484 = _data_T_481 | _data_T_483; // @[Regfile.scala 168:55]
- wire [31:0] _data_T_486 = valid_30[2] ? io_writeData_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_487 = _data_T_484 | _data_T_486; // @[Regfile.scala 169:55]
- wire [31:0] _data_T_489 = valid_30[3] ? io_writeData_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_490 = _data_T_487 | _data_T_489; // @[Regfile.scala 170:55]
- wire [31:0] _data_T_492 = valid_30[4] ? io_writeData_4_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_T_493 = _data_T_490 | _data_T_492; // @[Regfile.scala 171:55]
- wire [31:0] _data_T_495 = valid_30[5] ? io_writeData_5_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] data_30 = _data_T_493 | _data_T_495; // @[Regfile.scala 172:55]
- wire writeValid_31 = valid_30 != 6'h0; // @[Regfile.scala 175:28]
- wire [1:0] _T_609 = valid_30[1] + valid_30[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_101 = {{1'd0}, valid_30[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_611 = _GEN_101 + _T_609; // @[Bitwise.scala 48:55]
- wire [1:0] _T_613 = valid_30[4] + valid_30[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_102 = {{1'd0}, valid_30[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_615 = _GEN_102 + _T_613; // @[Bitwise.scala 48:55]
- wire [2:0] _T_617 = _T_611[1:0] + _T_615[1:0]; // @[Bitwise.scala 48:55]
- wire write_value__0 = 5'h0 == io_readAddr_0_addr; // @[Library.scala 115:27]
- wire write_value__1 = 5'h1 == io_readAddr_0_addr & writeValid_1; // @[Library.scala 115:22]
- wire write_value__2 = 5'h2 == io_readAddr_0_addr & writeValid_2; // @[Library.scala 115:22]
- wire write_value__3 = 5'h3 == io_readAddr_0_addr & writeValid_3; // @[Library.scala 115:22]
- wire write_value__4 = 5'h4 == io_readAddr_0_addr & writeValid_4; // @[Library.scala 115:22]
- wire write_value__5 = 5'h5 == io_readAddr_0_addr & writeValid_5; // @[Library.scala 115:22]
- wire write_value__6 = 5'h6 == io_readAddr_0_addr & writeValid_6; // @[Library.scala 115:22]
- wire write_value__7 = 5'h7 == io_readAddr_0_addr & writeValid_7; // @[Library.scala 115:22]
- wire write_value__8 = 5'h8 == io_readAddr_0_addr & writeValid_8; // @[Library.scala 115:22]
- wire write_value__9 = 5'h9 == io_readAddr_0_addr & writeValid_9; // @[Library.scala 115:22]
- wire write_value__10 = 5'ha == io_readAddr_0_addr & writeValid_10; // @[Library.scala 115:22]
- wire write_value__11 = 5'hb == io_readAddr_0_addr & writeValid_11; // @[Library.scala 115:22]
- wire write_value__12 = 5'hc == io_readAddr_0_addr & writeValid_12; // @[Library.scala 115:22]
- wire write_value__13 = 5'hd == io_readAddr_0_addr & writeValid_13; // @[Library.scala 115:22]
- wire write_value__14 = 5'he == io_readAddr_0_addr & writeValid_14; // @[Library.scala 115:22]
- wire write_value__15 = 5'hf == io_readAddr_0_addr & writeValid_15; // @[Library.scala 115:22]
- wire write_value__16 = 5'h10 == io_readAddr_0_addr & writeValid_16; // @[Library.scala 115:22]
- wire write_value__17 = 5'h11 == io_readAddr_0_addr & writeValid_17; // @[Library.scala 115:22]
- wire write_value__18 = 5'h12 == io_readAddr_0_addr & writeValid_18; // @[Library.scala 115:22]
- wire write_value__19 = 5'h13 == io_readAddr_0_addr & writeValid_19; // @[Library.scala 115:22]
- wire write_value__20 = 5'h14 == io_readAddr_0_addr & writeValid_20; // @[Library.scala 115:22]
- wire write_value__21 = 5'h15 == io_readAddr_0_addr & writeValid_21; // @[Library.scala 115:22]
- wire write_value__22 = 5'h16 == io_readAddr_0_addr & writeValid_22; // @[Library.scala 115:22]
- wire write_value__23 = 5'h17 == io_readAddr_0_addr & writeValid_23; // @[Library.scala 115:22]
- wire write_value__24 = 5'h18 == io_readAddr_0_addr & writeValid_24; // @[Library.scala 115:22]
- wire write_value__25 = 5'h19 == io_readAddr_0_addr & writeValid_25; // @[Library.scala 115:22]
- wire write_value__26 = 5'h1a == io_readAddr_0_addr & writeValid_26; // @[Library.scala 115:22]
- wire write_value__27 = 5'h1b == io_readAddr_0_addr & writeValid_27; // @[Library.scala 115:22]
- wire write_value__28 = 5'h1c == io_readAddr_0_addr & writeValid_28; // @[Library.scala 115:22]
- wire write_value__29 = 5'h1d == io_readAddr_0_addr & writeValid_29; // @[Library.scala 115:22]
- wire write_value__30 = 5'h1e == io_readAddr_0_addr & writeValid_30; // @[Library.scala 115:22]
- wire write_value__31 = 5'h1f == io_readAddr_0_addr & writeValid_31; // @[Library.scala 115:22]
- wire write_value_1_0 = write_value__0 | write_value__1; // @[Library.scala 129:37]
- wire write_value_1_1 = write_value__2 | write_value__3; // @[Library.scala 129:37]
- wire write_value_1_2 = write_value__4 | write_value__5; // @[Library.scala 129:37]
- wire write_value_1_3 = write_value__6 | write_value__7; // @[Library.scala 129:37]
- wire write_value_1_4 = write_value__8 | write_value__9; // @[Library.scala 129:37]
- wire write_value_1_5 = write_value__10 | write_value__11; // @[Library.scala 129:37]
- wire write_value_1_6 = write_value__12 | write_value__13; // @[Library.scala 129:37]
- wire write_value_1_7 = write_value__14 | write_value__15; // @[Library.scala 129:37]
- wire write_value_1_8 = write_value__16 | write_value__17; // @[Library.scala 129:37]
- wire write_value_1_9 = write_value__18 | write_value__19; // @[Library.scala 129:37]
- wire write_value_1_10 = write_value__20 | write_value__21; // @[Library.scala 129:37]
- wire write_value_1_11 = write_value__22 | write_value__23; // @[Library.scala 129:37]
- wire write_value_1_12 = write_value__24 | write_value__25; // @[Library.scala 129:37]
- wire write_value_1_13 = write_value__26 | write_value__27; // @[Library.scala 129:37]
- wire write_value_1_14 = write_value__28 | write_value__29; // @[Library.scala 129:37]
- wire write_value_1_15 = write_value__30 | write_value__31; // @[Library.scala 129:37]
- wire write_value_2_0 = write_value_1_0 | write_value_1_1; // @[Library.scala 129:37]
- wire write_value_2_1 = write_value_1_2 | write_value_1_3; // @[Library.scala 129:37]
- wire write_value_2_2 = write_value_1_4 | write_value_1_5; // @[Library.scala 129:37]
- wire write_value_2_3 = write_value_1_6 | write_value_1_7; // @[Library.scala 129:37]
- wire write_value_2_4 = write_value_1_8 | write_value_1_9; // @[Library.scala 129:37]
- wire write_value_2_5 = write_value_1_10 | write_value_1_11; // @[Library.scala 129:37]
- wire write_value_2_6 = write_value_1_12 | write_value_1_13; // @[Library.scala 129:37]
- wire write_value_2_7 = write_value_1_14 | write_value_1_15; // @[Library.scala 129:37]
- wire write_value_3_0 = write_value_2_0 | write_value_2_1; // @[Library.scala 129:37]
- wire write_value_3_1 = write_value_2_2 | write_value_2_3; // @[Library.scala 129:37]
- wire write_value_3_2 = write_value_2_4 | write_value_2_5; // @[Library.scala 129:37]
- wire write_value_3_3 = write_value_2_6 | write_value_2_7; // @[Library.scala 129:37]
- wire write_value_4_0 = write_value_3_0 | write_value_3_1; // @[Library.scala 129:37]
- wire write_value_4_1 = write_value_3_2 | write_value_3_3; // @[Library.scala 129:37]
- wire write_value_5_0 = write_value_4_0 | write_value_4_1; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value__1 = 5'h1 == io_readAddr_0_addr ? regfile_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__2 = 5'h2 == io_readAddr_0_addr ? regfile_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__3 = 5'h3 == io_readAddr_0_addr ? regfile_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__4 = 5'h4 == io_readAddr_0_addr ? regfile_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__5 = 5'h5 == io_readAddr_0_addr ? regfile_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__6 = 5'h6 == io_readAddr_0_addr ? regfile_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__7 = 5'h7 == io_readAddr_0_addr ? regfile_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__8 = 5'h8 == io_readAddr_0_addr ? regfile_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__9 = 5'h9 == io_readAddr_0_addr ? regfile_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__10 = 5'ha == io_readAddr_0_addr ? regfile_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__11 = 5'hb == io_readAddr_0_addr ? regfile_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__12 = 5'hc == io_readAddr_0_addr ? regfile_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__13 = 5'hd == io_readAddr_0_addr ? regfile_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__14 = 5'he == io_readAddr_0_addr ? regfile_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__15 = 5'hf == io_readAddr_0_addr ? regfile_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__16 = 5'h10 == io_readAddr_0_addr ? regfile_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__17 = 5'h11 == io_readAddr_0_addr ? regfile_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__18 = 5'h12 == io_readAddr_0_addr ? regfile_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__19 = 5'h13 == io_readAddr_0_addr ? regfile_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__20 = 5'h14 == io_readAddr_0_addr ? regfile_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__21 = 5'h15 == io_readAddr_0_addr ? regfile_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__22 = 5'h16 == io_readAddr_0_addr ? regfile_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__23 = 5'h17 == io_readAddr_0_addr ? regfile_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__24 = 5'h18 == io_readAddr_0_addr ? regfile_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__25 = 5'h19 == io_readAddr_0_addr ? regfile_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__26 = 5'h1a == io_readAddr_0_addr ? regfile_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__27 = 5'h1b == io_readAddr_0_addr ? regfile_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__28 = 5'h1c == io_readAddr_0_addr ? regfile_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__29 = 5'h1d == io_readAddr_0_addr ? regfile_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__30 = 5'h1e == io_readAddr_0_addr ? regfile_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value__31 = 5'h1f == io_readAddr_0_addr ? regfile_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_0_value_1_1 = rdata_0_value__2 | rdata_0_value__3; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_2 = rdata_0_value__4 | rdata_0_value__5; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_3 = rdata_0_value__6 | rdata_0_value__7; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_4 = rdata_0_value__8 | rdata_0_value__9; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_5 = rdata_0_value__10 | rdata_0_value__11; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_6 = rdata_0_value__12 | rdata_0_value__13; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_7 = rdata_0_value__14 | rdata_0_value__15; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_8 = rdata_0_value__16 | rdata_0_value__17; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_9 = rdata_0_value__18 | rdata_0_value__19; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_10 = rdata_0_value__20 | rdata_0_value__21; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_11 = rdata_0_value__22 | rdata_0_value__23; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_12 = rdata_0_value__24 | rdata_0_value__25; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_13 = rdata_0_value__26 | rdata_0_value__27; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_14 = rdata_0_value__28 | rdata_0_value__29; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_1_15 = rdata_0_value__30 | rdata_0_value__31; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_2_0 = rdata_0_value__1 | rdata_0_value_1_1; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_2_1 = rdata_0_value_1_2 | rdata_0_value_1_3; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_2_2 = rdata_0_value_1_4 | rdata_0_value_1_5; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_2_3 = rdata_0_value_1_6 | rdata_0_value_1_7; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_2_4 = rdata_0_value_1_8 | rdata_0_value_1_9; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_2_5 = rdata_0_value_1_10 | rdata_0_value_1_11; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_2_6 = rdata_0_value_1_12 | rdata_0_value_1_13; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_2_7 = rdata_0_value_1_14 | rdata_0_value_1_15; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_3_0 = rdata_0_value_2_0 | rdata_0_value_2_1; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_3_1 = rdata_0_value_2_2 | rdata_0_value_2_3; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_3_2 = rdata_0_value_2_4 | rdata_0_value_2_5; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_3_3 = rdata_0_value_2_6 | rdata_0_value_2_7; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_4_0 = rdata_0_value_3_0 | rdata_0_value_3_1; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_4_1 = rdata_0_value_3_2 | rdata_0_value_3_3; // @[Library.scala 129:37]
- wire [31:0] rdata_0_value_5_0 = rdata_0_value_4_0 | rdata_0_value_4_1; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value__1 = 5'h1 == io_readAddr_0_addr ? data : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__2 = 5'h2 == io_readAddr_0_addr ? data_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__3 = 5'h3 == io_readAddr_0_addr ? data_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__4 = 5'h4 == io_readAddr_0_addr ? data_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__5 = 5'h5 == io_readAddr_0_addr ? data_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__6 = 5'h6 == io_readAddr_0_addr ? data_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__7 = 5'h7 == io_readAddr_0_addr ? data_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__8 = 5'h8 == io_readAddr_0_addr ? data_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__9 = 5'h9 == io_readAddr_0_addr ? data_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__10 = 5'ha == io_readAddr_0_addr ? data_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__11 = 5'hb == io_readAddr_0_addr ? data_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__12 = 5'hc == io_readAddr_0_addr ? data_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__13 = 5'hd == io_readAddr_0_addr ? data_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__14 = 5'he == io_readAddr_0_addr ? data_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__15 = 5'hf == io_readAddr_0_addr ? data_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__16 = 5'h10 == io_readAddr_0_addr ? data_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__17 = 5'h11 == io_readAddr_0_addr ? data_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__18 = 5'h12 == io_readAddr_0_addr ? data_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__19 = 5'h13 == io_readAddr_0_addr ? data_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__20 = 5'h14 == io_readAddr_0_addr ? data_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__21 = 5'h15 == io_readAddr_0_addr ? data_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__22 = 5'h16 == io_readAddr_0_addr ? data_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__23 = 5'h17 == io_readAddr_0_addr ? data_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__24 = 5'h18 == io_readAddr_0_addr ? data_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__25 = 5'h19 == io_readAddr_0_addr ? data_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__26 = 5'h1a == io_readAddr_0_addr ? data_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__27 = 5'h1b == io_readAddr_0_addr ? data_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__28 = 5'h1c == io_readAddr_0_addr ? data_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__29 = 5'h1d == io_readAddr_0_addr ? data_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__30 = 5'h1e == io_readAddr_0_addr ? data_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value__31 = 5'h1f == io_readAddr_0_addr ? data_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_0_value_1_1 = wdata_0_value__2 | wdata_0_value__3; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_2 = wdata_0_value__4 | wdata_0_value__5; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_3 = wdata_0_value__6 | wdata_0_value__7; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_4 = wdata_0_value__8 | wdata_0_value__9; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_5 = wdata_0_value__10 | wdata_0_value__11; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_6 = wdata_0_value__12 | wdata_0_value__13; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_7 = wdata_0_value__14 | wdata_0_value__15; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_8 = wdata_0_value__16 | wdata_0_value__17; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_9 = wdata_0_value__18 | wdata_0_value__19; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_10 = wdata_0_value__20 | wdata_0_value__21; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_11 = wdata_0_value__22 | wdata_0_value__23; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_12 = wdata_0_value__24 | wdata_0_value__25; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_13 = wdata_0_value__26 | wdata_0_value__27; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_14 = wdata_0_value__28 | wdata_0_value__29; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_1_15 = wdata_0_value__30 | wdata_0_value__31; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_2_0 = wdata_0_value__1 | wdata_0_value_1_1; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_2_1 = wdata_0_value_1_2 | wdata_0_value_1_3; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_2_2 = wdata_0_value_1_4 | wdata_0_value_1_5; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_2_3 = wdata_0_value_1_6 | wdata_0_value_1_7; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_2_4 = wdata_0_value_1_8 | wdata_0_value_1_9; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_2_5 = wdata_0_value_1_10 | wdata_0_value_1_11; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_2_6 = wdata_0_value_1_12 | wdata_0_value_1_13; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_2_7 = wdata_0_value_1_14 | wdata_0_value_1_15; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_3_0 = wdata_0_value_2_0 | wdata_0_value_2_1; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_3_1 = wdata_0_value_2_2 | wdata_0_value_2_3; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_3_2 = wdata_0_value_2_4 | wdata_0_value_2_5; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_3_3 = wdata_0_value_2_6 | wdata_0_value_2_7; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_4_0 = wdata_0_value_3_0 | wdata_0_value_3_1; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_4_1 = wdata_0_value_3_2 | wdata_0_value_3_3; // @[Library.scala 129:37]
- wire [31:0] wdata_0_value_5_0 = wdata_0_value_4_0 | wdata_0_value_4_1; // @[Library.scala 129:37]
- wire [31:0] rwdata_0 = write_value_5_0 ? wdata_0_value_5_0 : rdata_0_value_5_0; // @[Regfile.scala 198:21]
- wire write_value_6_0 = 5'h0 == io_readAddr_1_addr; // @[Library.scala 115:27]
- wire write_value_6_1 = 5'h1 == io_readAddr_1_addr & writeValid_1; // @[Library.scala 115:22]
- wire write_value_6_2 = 5'h2 == io_readAddr_1_addr & writeValid_2; // @[Library.scala 115:22]
- wire write_value_6_3 = 5'h3 == io_readAddr_1_addr & writeValid_3; // @[Library.scala 115:22]
- wire write_value_6_4 = 5'h4 == io_readAddr_1_addr & writeValid_4; // @[Library.scala 115:22]
- wire write_value_6_5 = 5'h5 == io_readAddr_1_addr & writeValid_5; // @[Library.scala 115:22]
- wire write_value_6_6 = 5'h6 == io_readAddr_1_addr & writeValid_6; // @[Library.scala 115:22]
- wire write_value_6_7 = 5'h7 == io_readAddr_1_addr & writeValid_7; // @[Library.scala 115:22]
- wire write_value_6_8 = 5'h8 == io_readAddr_1_addr & writeValid_8; // @[Library.scala 115:22]
- wire write_value_6_9 = 5'h9 == io_readAddr_1_addr & writeValid_9; // @[Library.scala 115:22]
- wire write_value_6_10 = 5'ha == io_readAddr_1_addr & writeValid_10; // @[Library.scala 115:22]
- wire write_value_6_11 = 5'hb == io_readAddr_1_addr & writeValid_11; // @[Library.scala 115:22]
- wire write_value_6_12 = 5'hc == io_readAddr_1_addr & writeValid_12; // @[Library.scala 115:22]
- wire write_value_6_13 = 5'hd == io_readAddr_1_addr & writeValid_13; // @[Library.scala 115:22]
- wire write_value_6_14 = 5'he == io_readAddr_1_addr & writeValid_14; // @[Library.scala 115:22]
- wire write_value_6_15 = 5'hf == io_readAddr_1_addr & writeValid_15; // @[Library.scala 115:22]
- wire write_value_6_16 = 5'h10 == io_readAddr_1_addr & writeValid_16; // @[Library.scala 115:22]
- wire write_value_6_17 = 5'h11 == io_readAddr_1_addr & writeValid_17; // @[Library.scala 115:22]
- wire write_value_6_18 = 5'h12 == io_readAddr_1_addr & writeValid_18; // @[Library.scala 115:22]
- wire write_value_6_19 = 5'h13 == io_readAddr_1_addr & writeValid_19; // @[Library.scala 115:22]
- wire write_value_6_20 = 5'h14 == io_readAddr_1_addr & writeValid_20; // @[Library.scala 115:22]
- wire write_value_6_21 = 5'h15 == io_readAddr_1_addr & writeValid_21; // @[Library.scala 115:22]
- wire write_value_6_22 = 5'h16 == io_readAddr_1_addr & writeValid_22; // @[Library.scala 115:22]
- wire write_value_6_23 = 5'h17 == io_readAddr_1_addr & writeValid_23; // @[Library.scala 115:22]
- wire write_value_6_24 = 5'h18 == io_readAddr_1_addr & writeValid_24; // @[Library.scala 115:22]
- wire write_value_6_25 = 5'h19 == io_readAddr_1_addr & writeValid_25; // @[Library.scala 115:22]
- wire write_value_6_26 = 5'h1a == io_readAddr_1_addr & writeValid_26; // @[Library.scala 115:22]
- wire write_value_6_27 = 5'h1b == io_readAddr_1_addr & writeValid_27; // @[Library.scala 115:22]
- wire write_value_6_28 = 5'h1c == io_readAddr_1_addr & writeValid_28; // @[Library.scala 115:22]
- wire write_value_6_29 = 5'h1d == io_readAddr_1_addr & writeValid_29; // @[Library.scala 115:22]
- wire write_value_6_30 = 5'h1e == io_readAddr_1_addr & writeValid_30; // @[Library.scala 115:22]
- wire write_value_6_31 = 5'h1f == io_readAddr_1_addr & writeValid_31; // @[Library.scala 115:22]
- wire write_value_7_0 = write_value_6_0 | write_value_6_1; // @[Library.scala 129:37]
- wire write_value_7_1 = write_value_6_2 | write_value_6_3; // @[Library.scala 129:37]
- wire write_value_7_2 = write_value_6_4 | write_value_6_5; // @[Library.scala 129:37]
- wire write_value_7_3 = write_value_6_6 | write_value_6_7; // @[Library.scala 129:37]
- wire write_value_7_4 = write_value_6_8 | write_value_6_9; // @[Library.scala 129:37]
- wire write_value_7_5 = write_value_6_10 | write_value_6_11; // @[Library.scala 129:37]
- wire write_value_7_6 = write_value_6_12 | write_value_6_13; // @[Library.scala 129:37]
- wire write_value_7_7 = write_value_6_14 | write_value_6_15; // @[Library.scala 129:37]
- wire write_value_7_8 = write_value_6_16 | write_value_6_17; // @[Library.scala 129:37]
- wire write_value_7_9 = write_value_6_18 | write_value_6_19; // @[Library.scala 129:37]
- wire write_value_7_10 = write_value_6_20 | write_value_6_21; // @[Library.scala 129:37]
- wire write_value_7_11 = write_value_6_22 | write_value_6_23; // @[Library.scala 129:37]
- wire write_value_7_12 = write_value_6_24 | write_value_6_25; // @[Library.scala 129:37]
- wire write_value_7_13 = write_value_6_26 | write_value_6_27; // @[Library.scala 129:37]
- wire write_value_7_14 = write_value_6_28 | write_value_6_29; // @[Library.scala 129:37]
- wire write_value_7_15 = write_value_6_30 | write_value_6_31; // @[Library.scala 129:37]
- wire write_value_8_0 = write_value_7_0 | write_value_7_1; // @[Library.scala 129:37]
- wire write_value_8_1 = write_value_7_2 | write_value_7_3; // @[Library.scala 129:37]
- wire write_value_8_2 = write_value_7_4 | write_value_7_5; // @[Library.scala 129:37]
- wire write_value_8_3 = write_value_7_6 | write_value_7_7; // @[Library.scala 129:37]
- wire write_value_8_4 = write_value_7_8 | write_value_7_9; // @[Library.scala 129:37]
- wire write_value_8_5 = write_value_7_10 | write_value_7_11; // @[Library.scala 129:37]
- wire write_value_8_6 = write_value_7_12 | write_value_7_13; // @[Library.scala 129:37]
- wire write_value_8_7 = write_value_7_14 | write_value_7_15; // @[Library.scala 129:37]
- wire write_value_9_0 = write_value_8_0 | write_value_8_1; // @[Library.scala 129:37]
- wire write_value_9_1 = write_value_8_2 | write_value_8_3; // @[Library.scala 129:37]
- wire write_value_9_2 = write_value_8_4 | write_value_8_5; // @[Library.scala 129:37]
- wire write_value_9_3 = write_value_8_6 | write_value_8_7; // @[Library.scala 129:37]
- wire write_value_10_0 = write_value_9_0 | write_value_9_1; // @[Library.scala 129:37]
- wire write_value_10_1 = write_value_9_2 | write_value_9_3; // @[Library.scala 129:37]
- wire write_value_11_0 = write_value_10_0 | write_value_10_1; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value__1 = 5'h1 == io_readAddr_1_addr ? regfile_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__2 = 5'h2 == io_readAddr_1_addr ? regfile_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__3 = 5'h3 == io_readAddr_1_addr ? regfile_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__4 = 5'h4 == io_readAddr_1_addr ? regfile_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__5 = 5'h5 == io_readAddr_1_addr ? regfile_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__6 = 5'h6 == io_readAddr_1_addr ? regfile_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__7 = 5'h7 == io_readAddr_1_addr ? regfile_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__8 = 5'h8 == io_readAddr_1_addr ? regfile_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__9 = 5'h9 == io_readAddr_1_addr ? regfile_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__10 = 5'ha == io_readAddr_1_addr ? regfile_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__11 = 5'hb == io_readAddr_1_addr ? regfile_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__12 = 5'hc == io_readAddr_1_addr ? regfile_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__13 = 5'hd == io_readAddr_1_addr ? regfile_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__14 = 5'he == io_readAddr_1_addr ? regfile_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__15 = 5'hf == io_readAddr_1_addr ? regfile_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__16 = 5'h10 == io_readAddr_1_addr ? regfile_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__17 = 5'h11 == io_readAddr_1_addr ? regfile_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__18 = 5'h12 == io_readAddr_1_addr ? regfile_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__19 = 5'h13 == io_readAddr_1_addr ? regfile_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__20 = 5'h14 == io_readAddr_1_addr ? regfile_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__21 = 5'h15 == io_readAddr_1_addr ? regfile_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__22 = 5'h16 == io_readAddr_1_addr ? regfile_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__23 = 5'h17 == io_readAddr_1_addr ? regfile_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__24 = 5'h18 == io_readAddr_1_addr ? regfile_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__25 = 5'h19 == io_readAddr_1_addr ? regfile_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__26 = 5'h1a == io_readAddr_1_addr ? regfile_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__27 = 5'h1b == io_readAddr_1_addr ? regfile_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__28 = 5'h1c == io_readAddr_1_addr ? regfile_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__29 = 5'h1d == io_readAddr_1_addr ? regfile_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__30 = 5'h1e == io_readAddr_1_addr ? regfile_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value__31 = 5'h1f == io_readAddr_1_addr ? regfile_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_1_value_1_1 = rdata_1_value__2 | rdata_1_value__3; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_2 = rdata_1_value__4 | rdata_1_value__5; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_3 = rdata_1_value__6 | rdata_1_value__7; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_4 = rdata_1_value__8 | rdata_1_value__9; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_5 = rdata_1_value__10 | rdata_1_value__11; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_6 = rdata_1_value__12 | rdata_1_value__13; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_7 = rdata_1_value__14 | rdata_1_value__15; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_8 = rdata_1_value__16 | rdata_1_value__17; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_9 = rdata_1_value__18 | rdata_1_value__19; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_10 = rdata_1_value__20 | rdata_1_value__21; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_11 = rdata_1_value__22 | rdata_1_value__23; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_12 = rdata_1_value__24 | rdata_1_value__25; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_13 = rdata_1_value__26 | rdata_1_value__27; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_14 = rdata_1_value__28 | rdata_1_value__29; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_1_15 = rdata_1_value__30 | rdata_1_value__31; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_2_0 = rdata_1_value__1 | rdata_1_value_1_1; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_2_1 = rdata_1_value_1_2 | rdata_1_value_1_3; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_2_2 = rdata_1_value_1_4 | rdata_1_value_1_5; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_2_3 = rdata_1_value_1_6 | rdata_1_value_1_7; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_2_4 = rdata_1_value_1_8 | rdata_1_value_1_9; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_2_5 = rdata_1_value_1_10 | rdata_1_value_1_11; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_2_6 = rdata_1_value_1_12 | rdata_1_value_1_13; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_2_7 = rdata_1_value_1_14 | rdata_1_value_1_15; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_3_0 = rdata_1_value_2_0 | rdata_1_value_2_1; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_3_1 = rdata_1_value_2_2 | rdata_1_value_2_3; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_3_2 = rdata_1_value_2_4 | rdata_1_value_2_5; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_3_3 = rdata_1_value_2_6 | rdata_1_value_2_7; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_4_0 = rdata_1_value_3_0 | rdata_1_value_3_1; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_4_1 = rdata_1_value_3_2 | rdata_1_value_3_3; // @[Library.scala 129:37]
- wire [31:0] rdata_1_value_5_0 = rdata_1_value_4_0 | rdata_1_value_4_1; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value__1 = 5'h1 == io_readAddr_1_addr ? data : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__2 = 5'h2 == io_readAddr_1_addr ? data_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__3 = 5'h3 == io_readAddr_1_addr ? data_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__4 = 5'h4 == io_readAddr_1_addr ? data_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__5 = 5'h5 == io_readAddr_1_addr ? data_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__6 = 5'h6 == io_readAddr_1_addr ? data_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__7 = 5'h7 == io_readAddr_1_addr ? data_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__8 = 5'h8 == io_readAddr_1_addr ? data_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__9 = 5'h9 == io_readAddr_1_addr ? data_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__10 = 5'ha == io_readAddr_1_addr ? data_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__11 = 5'hb == io_readAddr_1_addr ? data_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__12 = 5'hc == io_readAddr_1_addr ? data_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__13 = 5'hd == io_readAddr_1_addr ? data_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__14 = 5'he == io_readAddr_1_addr ? data_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__15 = 5'hf == io_readAddr_1_addr ? data_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__16 = 5'h10 == io_readAddr_1_addr ? data_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__17 = 5'h11 == io_readAddr_1_addr ? data_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__18 = 5'h12 == io_readAddr_1_addr ? data_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__19 = 5'h13 == io_readAddr_1_addr ? data_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__20 = 5'h14 == io_readAddr_1_addr ? data_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__21 = 5'h15 == io_readAddr_1_addr ? data_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__22 = 5'h16 == io_readAddr_1_addr ? data_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__23 = 5'h17 == io_readAddr_1_addr ? data_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__24 = 5'h18 == io_readAddr_1_addr ? data_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__25 = 5'h19 == io_readAddr_1_addr ? data_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__26 = 5'h1a == io_readAddr_1_addr ? data_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__27 = 5'h1b == io_readAddr_1_addr ? data_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__28 = 5'h1c == io_readAddr_1_addr ? data_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__29 = 5'h1d == io_readAddr_1_addr ? data_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__30 = 5'h1e == io_readAddr_1_addr ? data_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value__31 = 5'h1f == io_readAddr_1_addr ? data_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_1_value_1_1 = wdata_1_value__2 | wdata_1_value__3; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_2 = wdata_1_value__4 | wdata_1_value__5; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_3 = wdata_1_value__6 | wdata_1_value__7; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_4 = wdata_1_value__8 | wdata_1_value__9; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_5 = wdata_1_value__10 | wdata_1_value__11; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_6 = wdata_1_value__12 | wdata_1_value__13; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_7 = wdata_1_value__14 | wdata_1_value__15; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_8 = wdata_1_value__16 | wdata_1_value__17; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_9 = wdata_1_value__18 | wdata_1_value__19; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_10 = wdata_1_value__20 | wdata_1_value__21; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_11 = wdata_1_value__22 | wdata_1_value__23; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_12 = wdata_1_value__24 | wdata_1_value__25; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_13 = wdata_1_value__26 | wdata_1_value__27; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_14 = wdata_1_value__28 | wdata_1_value__29; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_1_15 = wdata_1_value__30 | wdata_1_value__31; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_2_0 = wdata_1_value__1 | wdata_1_value_1_1; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_2_1 = wdata_1_value_1_2 | wdata_1_value_1_3; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_2_2 = wdata_1_value_1_4 | wdata_1_value_1_5; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_2_3 = wdata_1_value_1_6 | wdata_1_value_1_7; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_2_4 = wdata_1_value_1_8 | wdata_1_value_1_9; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_2_5 = wdata_1_value_1_10 | wdata_1_value_1_11; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_2_6 = wdata_1_value_1_12 | wdata_1_value_1_13; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_2_7 = wdata_1_value_1_14 | wdata_1_value_1_15; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_3_0 = wdata_1_value_2_0 | wdata_1_value_2_1; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_3_1 = wdata_1_value_2_2 | wdata_1_value_2_3; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_3_2 = wdata_1_value_2_4 | wdata_1_value_2_5; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_3_3 = wdata_1_value_2_6 | wdata_1_value_2_7; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_4_0 = wdata_1_value_3_0 | wdata_1_value_3_1; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_4_1 = wdata_1_value_3_2 | wdata_1_value_3_3; // @[Library.scala 129:37]
- wire [31:0] wdata_1_value_5_0 = wdata_1_value_4_0 | wdata_1_value_4_1; // @[Library.scala 129:37]
- wire [31:0] rwdata_1 = write_value_11_0 ? wdata_1_value_5_0 : rdata_1_value_5_0; // @[Regfile.scala 198:21]
- wire write_value_12_0 = 5'h0 == io_readAddr_2_addr; // @[Library.scala 115:27]
- wire write_value_12_1 = 5'h1 == io_readAddr_2_addr & writeValid_1; // @[Library.scala 115:22]
- wire write_value_12_2 = 5'h2 == io_readAddr_2_addr & writeValid_2; // @[Library.scala 115:22]
- wire write_value_12_3 = 5'h3 == io_readAddr_2_addr & writeValid_3; // @[Library.scala 115:22]
- wire write_value_12_4 = 5'h4 == io_readAddr_2_addr & writeValid_4; // @[Library.scala 115:22]
- wire write_value_12_5 = 5'h5 == io_readAddr_2_addr & writeValid_5; // @[Library.scala 115:22]
- wire write_value_12_6 = 5'h6 == io_readAddr_2_addr & writeValid_6; // @[Library.scala 115:22]
- wire write_value_12_7 = 5'h7 == io_readAddr_2_addr & writeValid_7; // @[Library.scala 115:22]
- wire write_value_12_8 = 5'h8 == io_readAddr_2_addr & writeValid_8; // @[Library.scala 115:22]
- wire write_value_12_9 = 5'h9 == io_readAddr_2_addr & writeValid_9; // @[Library.scala 115:22]
- wire write_value_12_10 = 5'ha == io_readAddr_2_addr & writeValid_10; // @[Library.scala 115:22]
- wire write_value_12_11 = 5'hb == io_readAddr_2_addr & writeValid_11; // @[Library.scala 115:22]
- wire write_value_12_12 = 5'hc == io_readAddr_2_addr & writeValid_12; // @[Library.scala 115:22]
- wire write_value_12_13 = 5'hd == io_readAddr_2_addr & writeValid_13; // @[Library.scala 115:22]
- wire write_value_12_14 = 5'he == io_readAddr_2_addr & writeValid_14; // @[Library.scala 115:22]
- wire write_value_12_15 = 5'hf == io_readAddr_2_addr & writeValid_15; // @[Library.scala 115:22]
- wire write_value_12_16 = 5'h10 == io_readAddr_2_addr & writeValid_16; // @[Library.scala 115:22]
- wire write_value_12_17 = 5'h11 == io_readAddr_2_addr & writeValid_17; // @[Library.scala 115:22]
- wire write_value_12_18 = 5'h12 == io_readAddr_2_addr & writeValid_18; // @[Library.scala 115:22]
- wire write_value_12_19 = 5'h13 == io_readAddr_2_addr & writeValid_19; // @[Library.scala 115:22]
- wire write_value_12_20 = 5'h14 == io_readAddr_2_addr & writeValid_20; // @[Library.scala 115:22]
- wire write_value_12_21 = 5'h15 == io_readAddr_2_addr & writeValid_21; // @[Library.scala 115:22]
- wire write_value_12_22 = 5'h16 == io_readAddr_2_addr & writeValid_22; // @[Library.scala 115:22]
- wire write_value_12_23 = 5'h17 == io_readAddr_2_addr & writeValid_23; // @[Library.scala 115:22]
- wire write_value_12_24 = 5'h18 == io_readAddr_2_addr & writeValid_24; // @[Library.scala 115:22]
- wire write_value_12_25 = 5'h19 == io_readAddr_2_addr & writeValid_25; // @[Library.scala 115:22]
- wire write_value_12_26 = 5'h1a == io_readAddr_2_addr & writeValid_26; // @[Library.scala 115:22]
- wire write_value_12_27 = 5'h1b == io_readAddr_2_addr & writeValid_27; // @[Library.scala 115:22]
- wire write_value_12_28 = 5'h1c == io_readAddr_2_addr & writeValid_28; // @[Library.scala 115:22]
- wire write_value_12_29 = 5'h1d == io_readAddr_2_addr & writeValid_29; // @[Library.scala 115:22]
- wire write_value_12_30 = 5'h1e == io_readAddr_2_addr & writeValid_30; // @[Library.scala 115:22]
- wire write_value_12_31 = 5'h1f == io_readAddr_2_addr & writeValid_31; // @[Library.scala 115:22]
- wire write_value_13_0 = write_value_12_0 | write_value_12_1; // @[Library.scala 129:37]
- wire write_value_13_1 = write_value_12_2 | write_value_12_3; // @[Library.scala 129:37]
- wire write_value_13_2 = write_value_12_4 | write_value_12_5; // @[Library.scala 129:37]
- wire write_value_13_3 = write_value_12_6 | write_value_12_7; // @[Library.scala 129:37]
- wire write_value_13_4 = write_value_12_8 | write_value_12_9; // @[Library.scala 129:37]
- wire write_value_13_5 = write_value_12_10 | write_value_12_11; // @[Library.scala 129:37]
- wire write_value_13_6 = write_value_12_12 | write_value_12_13; // @[Library.scala 129:37]
- wire write_value_13_7 = write_value_12_14 | write_value_12_15; // @[Library.scala 129:37]
- wire write_value_13_8 = write_value_12_16 | write_value_12_17; // @[Library.scala 129:37]
- wire write_value_13_9 = write_value_12_18 | write_value_12_19; // @[Library.scala 129:37]
- wire write_value_13_10 = write_value_12_20 | write_value_12_21; // @[Library.scala 129:37]
- wire write_value_13_11 = write_value_12_22 | write_value_12_23; // @[Library.scala 129:37]
- wire write_value_13_12 = write_value_12_24 | write_value_12_25; // @[Library.scala 129:37]
- wire write_value_13_13 = write_value_12_26 | write_value_12_27; // @[Library.scala 129:37]
- wire write_value_13_14 = write_value_12_28 | write_value_12_29; // @[Library.scala 129:37]
- wire write_value_13_15 = write_value_12_30 | write_value_12_31; // @[Library.scala 129:37]
- wire write_value_14_0 = write_value_13_0 | write_value_13_1; // @[Library.scala 129:37]
- wire write_value_14_1 = write_value_13_2 | write_value_13_3; // @[Library.scala 129:37]
- wire write_value_14_2 = write_value_13_4 | write_value_13_5; // @[Library.scala 129:37]
- wire write_value_14_3 = write_value_13_6 | write_value_13_7; // @[Library.scala 129:37]
- wire write_value_14_4 = write_value_13_8 | write_value_13_9; // @[Library.scala 129:37]
- wire write_value_14_5 = write_value_13_10 | write_value_13_11; // @[Library.scala 129:37]
- wire write_value_14_6 = write_value_13_12 | write_value_13_13; // @[Library.scala 129:37]
- wire write_value_14_7 = write_value_13_14 | write_value_13_15; // @[Library.scala 129:37]
- wire write_value_15_0 = write_value_14_0 | write_value_14_1; // @[Library.scala 129:37]
- wire write_value_15_1 = write_value_14_2 | write_value_14_3; // @[Library.scala 129:37]
- wire write_value_15_2 = write_value_14_4 | write_value_14_5; // @[Library.scala 129:37]
- wire write_value_15_3 = write_value_14_6 | write_value_14_7; // @[Library.scala 129:37]
- wire write_value_16_0 = write_value_15_0 | write_value_15_1; // @[Library.scala 129:37]
- wire write_value_16_1 = write_value_15_2 | write_value_15_3; // @[Library.scala 129:37]
- wire write_value_17_0 = write_value_16_0 | write_value_16_1; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value__1 = 5'h1 == io_readAddr_2_addr ? regfile_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__2 = 5'h2 == io_readAddr_2_addr ? regfile_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__3 = 5'h3 == io_readAddr_2_addr ? regfile_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__4 = 5'h4 == io_readAddr_2_addr ? regfile_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__5 = 5'h5 == io_readAddr_2_addr ? regfile_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__6 = 5'h6 == io_readAddr_2_addr ? regfile_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__7 = 5'h7 == io_readAddr_2_addr ? regfile_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__8 = 5'h8 == io_readAddr_2_addr ? regfile_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__9 = 5'h9 == io_readAddr_2_addr ? regfile_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__10 = 5'ha == io_readAddr_2_addr ? regfile_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__11 = 5'hb == io_readAddr_2_addr ? regfile_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__12 = 5'hc == io_readAddr_2_addr ? regfile_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__13 = 5'hd == io_readAddr_2_addr ? regfile_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__14 = 5'he == io_readAddr_2_addr ? regfile_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__15 = 5'hf == io_readAddr_2_addr ? regfile_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__16 = 5'h10 == io_readAddr_2_addr ? regfile_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__17 = 5'h11 == io_readAddr_2_addr ? regfile_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__18 = 5'h12 == io_readAddr_2_addr ? regfile_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__19 = 5'h13 == io_readAddr_2_addr ? regfile_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__20 = 5'h14 == io_readAddr_2_addr ? regfile_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__21 = 5'h15 == io_readAddr_2_addr ? regfile_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__22 = 5'h16 == io_readAddr_2_addr ? regfile_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__23 = 5'h17 == io_readAddr_2_addr ? regfile_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__24 = 5'h18 == io_readAddr_2_addr ? regfile_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__25 = 5'h19 == io_readAddr_2_addr ? regfile_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__26 = 5'h1a == io_readAddr_2_addr ? regfile_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__27 = 5'h1b == io_readAddr_2_addr ? regfile_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__28 = 5'h1c == io_readAddr_2_addr ? regfile_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__29 = 5'h1d == io_readAddr_2_addr ? regfile_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__30 = 5'h1e == io_readAddr_2_addr ? regfile_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value__31 = 5'h1f == io_readAddr_2_addr ? regfile_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_2_value_1_1 = rdata_2_value__2 | rdata_2_value__3; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_2 = rdata_2_value__4 | rdata_2_value__5; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_3 = rdata_2_value__6 | rdata_2_value__7; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_4 = rdata_2_value__8 | rdata_2_value__9; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_5 = rdata_2_value__10 | rdata_2_value__11; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_6 = rdata_2_value__12 | rdata_2_value__13; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_7 = rdata_2_value__14 | rdata_2_value__15; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_8 = rdata_2_value__16 | rdata_2_value__17; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_9 = rdata_2_value__18 | rdata_2_value__19; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_10 = rdata_2_value__20 | rdata_2_value__21; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_11 = rdata_2_value__22 | rdata_2_value__23; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_12 = rdata_2_value__24 | rdata_2_value__25; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_13 = rdata_2_value__26 | rdata_2_value__27; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_14 = rdata_2_value__28 | rdata_2_value__29; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_1_15 = rdata_2_value__30 | rdata_2_value__31; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_2_0 = rdata_2_value__1 | rdata_2_value_1_1; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_2_1 = rdata_2_value_1_2 | rdata_2_value_1_3; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_2_2 = rdata_2_value_1_4 | rdata_2_value_1_5; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_2_3 = rdata_2_value_1_6 | rdata_2_value_1_7; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_2_4 = rdata_2_value_1_8 | rdata_2_value_1_9; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_2_5 = rdata_2_value_1_10 | rdata_2_value_1_11; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_2_6 = rdata_2_value_1_12 | rdata_2_value_1_13; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_2_7 = rdata_2_value_1_14 | rdata_2_value_1_15; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_3_0 = rdata_2_value_2_0 | rdata_2_value_2_1; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_3_1 = rdata_2_value_2_2 | rdata_2_value_2_3; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_3_2 = rdata_2_value_2_4 | rdata_2_value_2_5; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_3_3 = rdata_2_value_2_6 | rdata_2_value_2_7; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_4_0 = rdata_2_value_3_0 | rdata_2_value_3_1; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_4_1 = rdata_2_value_3_2 | rdata_2_value_3_3; // @[Library.scala 129:37]
- wire [31:0] rdata_2_value_5_0 = rdata_2_value_4_0 | rdata_2_value_4_1; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value__1 = 5'h1 == io_readAddr_2_addr ? data : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__2 = 5'h2 == io_readAddr_2_addr ? data_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__3 = 5'h3 == io_readAddr_2_addr ? data_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__4 = 5'h4 == io_readAddr_2_addr ? data_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__5 = 5'h5 == io_readAddr_2_addr ? data_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__6 = 5'h6 == io_readAddr_2_addr ? data_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__7 = 5'h7 == io_readAddr_2_addr ? data_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__8 = 5'h8 == io_readAddr_2_addr ? data_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__9 = 5'h9 == io_readAddr_2_addr ? data_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__10 = 5'ha == io_readAddr_2_addr ? data_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__11 = 5'hb == io_readAddr_2_addr ? data_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__12 = 5'hc == io_readAddr_2_addr ? data_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__13 = 5'hd == io_readAddr_2_addr ? data_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__14 = 5'he == io_readAddr_2_addr ? data_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__15 = 5'hf == io_readAddr_2_addr ? data_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__16 = 5'h10 == io_readAddr_2_addr ? data_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__17 = 5'h11 == io_readAddr_2_addr ? data_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__18 = 5'h12 == io_readAddr_2_addr ? data_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__19 = 5'h13 == io_readAddr_2_addr ? data_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__20 = 5'h14 == io_readAddr_2_addr ? data_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__21 = 5'h15 == io_readAddr_2_addr ? data_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__22 = 5'h16 == io_readAddr_2_addr ? data_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__23 = 5'h17 == io_readAddr_2_addr ? data_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__24 = 5'h18 == io_readAddr_2_addr ? data_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__25 = 5'h19 == io_readAddr_2_addr ? data_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__26 = 5'h1a == io_readAddr_2_addr ? data_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__27 = 5'h1b == io_readAddr_2_addr ? data_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__28 = 5'h1c == io_readAddr_2_addr ? data_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__29 = 5'h1d == io_readAddr_2_addr ? data_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__30 = 5'h1e == io_readAddr_2_addr ? data_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value__31 = 5'h1f == io_readAddr_2_addr ? data_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_2_value_1_1 = wdata_2_value__2 | wdata_2_value__3; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_2 = wdata_2_value__4 | wdata_2_value__5; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_3 = wdata_2_value__6 | wdata_2_value__7; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_4 = wdata_2_value__8 | wdata_2_value__9; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_5 = wdata_2_value__10 | wdata_2_value__11; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_6 = wdata_2_value__12 | wdata_2_value__13; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_7 = wdata_2_value__14 | wdata_2_value__15; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_8 = wdata_2_value__16 | wdata_2_value__17; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_9 = wdata_2_value__18 | wdata_2_value__19; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_10 = wdata_2_value__20 | wdata_2_value__21; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_11 = wdata_2_value__22 | wdata_2_value__23; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_12 = wdata_2_value__24 | wdata_2_value__25; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_13 = wdata_2_value__26 | wdata_2_value__27; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_14 = wdata_2_value__28 | wdata_2_value__29; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_1_15 = wdata_2_value__30 | wdata_2_value__31; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_2_0 = wdata_2_value__1 | wdata_2_value_1_1; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_2_1 = wdata_2_value_1_2 | wdata_2_value_1_3; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_2_2 = wdata_2_value_1_4 | wdata_2_value_1_5; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_2_3 = wdata_2_value_1_6 | wdata_2_value_1_7; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_2_4 = wdata_2_value_1_8 | wdata_2_value_1_9; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_2_5 = wdata_2_value_1_10 | wdata_2_value_1_11; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_2_6 = wdata_2_value_1_12 | wdata_2_value_1_13; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_2_7 = wdata_2_value_1_14 | wdata_2_value_1_15; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_3_0 = wdata_2_value_2_0 | wdata_2_value_2_1; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_3_1 = wdata_2_value_2_2 | wdata_2_value_2_3; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_3_2 = wdata_2_value_2_4 | wdata_2_value_2_5; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_3_3 = wdata_2_value_2_6 | wdata_2_value_2_7; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_4_0 = wdata_2_value_3_0 | wdata_2_value_3_1; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_4_1 = wdata_2_value_3_2 | wdata_2_value_3_3; // @[Library.scala 129:37]
- wire [31:0] wdata_2_value_5_0 = wdata_2_value_4_0 | wdata_2_value_4_1; // @[Library.scala 129:37]
- wire [31:0] rwdata_2 = write_value_17_0 ? wdata_2_value_5_0 : rdata_2_value_5_0; // @[Regfile.scala 198:21]
- wire write_value_18_0 = 5'h0 == io_readAddr_3_addr; // @[Library.scala 115:27]
- wire write_value_18_1 = 5'h1 == io_readAddr_3_addr & writeValid_1; // @[Library.scala 115:22]
- wire write_value_18_2 = 5'h2 == io_readAddr_3_addr & writeValid_2; // @[Library.scala 115:22]
- wire write_value_18_3 = 5'h3 == io_readAddr_3_addr & writeValid_3; // @[Library.scala 115:22]
- wire write_value_18_4 = 5'h4 == io_readAddr_3_addr & writeValid_4; // @[Library.scala 115:22]
- wire write_value_18_5 = 5'h5 == io_readAddr_3_addr & writeValid_5; // @[Library.scala 115:22]
- wire write_value_18_6 = 5'h6 == io_readAddr_3_addr & writeValid_6; // @[Library.scala 115:22]
- wire write_value_18_7 = 5'h7 == io_readAddr_3_addr & writeValid_7; // @[Library.scala 115:22]
- wire write_value_18_8 = 5'h8 == io_readAddr_3_addr & writeValid_8; // @[Library.scala 115:22]
- wire write_value_18_9 = 5'h9 == io_readAddr_3_addr & writeValid_9; // @[Library.scala 115:22]
- wire write_value_18_10 = 5'ha == io_readAddr_3_addr & writeValid_10; // @[Library.scala 115:22]
- wire write_value_18_11 = 5'hb == io_readAddr_3_addr & writeValid_11; // @[Library.scala 115:22]
- wire write_value_18_12 = 5'hc == io_readAddr_3_addr & writeValid_12; // @[Library.scala 115:22]
- wire write_value_18_13 = 5'hd == io_readAddr_3_addr & writeValid_13; // @[Library.scala 115:22]
- wire write_value_18_14 = 5'he == io_readAddr_3_addr & writeValid_14; // @[Library.scala 115:22]
- wire write_value_18_15 = 5'hf == io_readAddr_3_addr & writeValid_15; // @[Library.scala 115:22]
- wire write_value_18_16 = 5'h10 == io_readAddr_3_addr & writeValid_16; // @[Library.scala 115:22]
- wire write_value_18_17 = 5'h11 == io_readAddr_3_addr & writeValid_17; // @[Library.scala 115:22]
- wire write_value_18_18 = 5'h12 == io_readAddr_3_addr & writeValid_18; // @[Library.scala 115:22]
- wire write_value_18_19 = 5'h13 == io_readAddr_3_addr & writeValid_19; // @[Library.scala 115:22]
- wire write_value_18_20 = 5'h14 == io_readAddr_3_addr & writeValid_20; // @[Library.scala 115:22]
- wire write_value_18_21 = 5'h15 == io_readAddr_3_addr & writeValid_21; // @[Library.scala 115:22]
- wire write_value_18_22 = 5'h16 == io_readAddr_3_addr & writeValid_22; // @[Library.scala 115:22]
- wire write_value_18_23 = 5'h17 == io_readAddr_3_addr & writeValid_23; // @[Library.scala 115:22]
- wire write_value_18_24 = 5'h18 == io_readAddr_3_addr & writeValid_24; // @[Library.scala 115:22]
- wire write_value_18_25 = 5'h19 == io_readAddr_3_addr & writeValid_25; // @[Library.scala 115:22]
- wire write_value_18_26 = 5'h1a == io_readAddr_3_addr & writeValid_26; // @[Library.scala 115:22]
- wire write_value_18_27 = 5'h1b == io_readAddr_3_addr & writeValid_27; // @[Library.scala 115:22]
- wire write_value_18_28 = 5'h1c == io_readAddr_3_addr & writeValid_28; // @[Library.scala 115:22]
- wire write_value_18_29 = 5'h1d == io_readAddr_3_addr & writeValid_29; // @[Library.scala 115:22]
- wire write_value_18_30 = 5'h1e == io_readAddr_3_addr & writeValid_30; // @[Library.scala 115:22]
- wire write_value_18_31 = 5'h1f == io_readAddr_3_addr & writeValid_31; // @[Library.scala 115:22]
- wire write_value_19_0 = write_value_18_0 | write_value_18_1; // @[Library.scala 129:37]
- wire write_value_19_1 = write_value_18_2 | write_value_18_3; // @[Library.scala 129:37]
- wire write_value_19_2 = write_value_18_4 | write_value_18_5; // @[Library.scala 129:37]
- wire write_value_19_3 = write_value_18_6 | write_value_18_7; // @[Library.scala 129:37]
- wire write_value_19_4 = write_value_18_8 | write_value_18_9; // @[Library.scala 129:37]
- wire write_value_19_5 = write_value_18_10 | write_value_18_11; // @[Library.scala 129:37]
- wire write_value_19_6 = write_value_18_12 | write_value_18_13; // @[Library.scala 129:37]
- wire write_value_19_7 = write_value_18_14 | write_value_18_15; // @[Library.scala 129:37]
- wire write_value_19_8 = write_value_18_16 | write_value_18_17; // @[Library.scala 129:37]
- wire write_value_19_9 = write_value_18_18 | write_value_18_19; // @[Library.scala 129:37]
- wire write_value_19_10 = write_value_18_20 | write_value_18_21; // @[Library.scala 129:37]
- wire write_value_19_11 = write_value_18_22 | write_value_18_23; // @[Library.scala 129:37]
- wire write_value_19_12 = write_value_18_24 | write_value_18_25; // @[Library.scala 129:37]
- wire write_value_19_13 = write_value_18_26 | write_value_18_27; // @[Library.scala 129:37]
- wire write_value_19_14 = write_value_18_28 | write_value_18_29; // @[Library.scala 129:37]
- wire write_value_19_15 = write_value_18_30 | write_value_18_31; // @[Library.scala 129:37]
- wire write_value_20_0 = write_value_19_0 | write_value_19_1; // @[Library.scala 129:37]
- wire write_value_20_1 = write_value_19_2 | write_value_19_3; // @[Library.scala 129:37]
- wire write_value_20_2 = write_value_19_4 | write_value_19_5; // @[Library.scala 129:37]
- wire write_value_20_3 = write_value_19_6 | write_value_19_7; // @[Library.scala 129:37]
- wire write_value_20_4 = write_value_19_8 | write_value_19_9; // @[Library.scala 129:37]
- wire write_value_20_5 = write_value_19_10 | write_value_19_11; // @[Library.scala 129:37]
- wire write_value_20_6 = write_value_19_12 | write_value_19_13; // @[Library.scala 129:37]
- wire write_value_20_7 = write_value_19_14 | write_value_19_15; // @[Library.scala 129:37]
- wire write_value_21_0 = write_value_20_0 | write_value_20_1; // @[Library.scala 129:37]
- wire write_value_21_1 = write_value_20_2 | write_value_20_3; // @[Library.scala 129:37]
- wire write_value_21_2 = write_value_20_4 | write_value_20_5; // @[Library.scala 129:37]
- wire write_value_21_3 = write_value_20_6 | write_value_20_7; // @[Library.scala 129:37]
- wire write_value_22_0 = write_value_21_0 | write_value_21_1; // @[Library.scala 129:37]
- wire write_value_22_1 = write_value_21_2 | write_value_21_3; // @[Library.scala 129:37]
- wire write_value_23_0 = write_value_22_0 | write_value_22_1; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value__1 = 5'h1 == io_readAddr_3_addr ? regfile_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__2 = 5'h2 == io_readAddr_3_addr ? regfile_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__3 = 5'h3 == io_readAddr_3_addr ? regfile_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__4 = 5'h4 == io_readAddr_3_addr ? regfile_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__5 = 5'h5 == io_readAddr_3_addr ? regfile_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__6 = 5'h6 == io_readAddr_3_addr ? regfile_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__7 = 5'h7 == io_readAddr_3_addr ? regfile_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__8 = 5'h8 == io_readAddr_3_addr ? regfile_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__9 = 5'h9 == io_readAddr_3_addr ? regfile_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__10 = 5'ha == io_readAddr_3_addr ? regfile_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__11 = 5'hb == io_readAddr_3_addr ? regfile_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__12 = 5'hc == io_readAddr_3_addr ? regfile_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__13 = 5'hd == io_readAddr_3_addr ? regfile_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__14 = 5'he == io_readAddr_3_addr ? regfile_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__15 = 5'hf == io_readAddr_3_addr ? regfile_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__16 = 5'h10 == io_readAddr_3_addr ? regfile_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__17 = 5'h11 == io_readAddr_3_addr ? regfile_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__18 = 5'h12 == io_readAddr_3_addr ? regfile_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__19 = 5'h13 == io_readAddr_3_addr ? regfile_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__20 = 5'h14 == io_readAddr_3_addr ? regfile_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__21 = 5'h15 == io_readAddr_3_addr ? regfile_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__22 = 5'h16 == io_readAddr_3_addr ? regfile_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__23 = 5'h17 == io_readAddr_3_addr ? regfile_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__24 = 5'h18 == io_readAddr_3_addr ? regfile_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__25 = 5'h19 == io_readAddr_3_addr ? regfile_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__26 = 5'h1a == io_readAddr_3_addr ? regfile_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__27 = 5'h1b == io_readAddr_3_addr ? regfile_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__28 = 5'h1c == io_readAddr_3_addr ? regfile_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__29 = 5'h1d == io_readAddr_3_addr ? regfile_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__30 = 5'h1e == io_readAddr_3_addr ? regfile_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value__31 = 5'h1f == io_readAddr_3_addr ? regfile_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_3_value_1_1 = rdata_3_value__2 | rdata_3_value__3; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_2 = rdata_3_value__4 | rdata_3_value__5; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_3 = rdata_3_value__6 | rdata_3_value__7; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_4 = rdata_3_value__8 | rdata_3_value__9; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_5 = rdata_3_value__10 | rdata_3_value__11; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_6 = rdata_3_value__12 | rdata_3_value__13; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_7 = rdata_3_value__14 | rdata_3_value__15; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_8 = rdata_3_value__16 | rdata_3_value__17; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_9 = rdata_3_value__18 | rdata_3_value__19; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_10 = rdata_3_value__20 | rdata_3_value__21; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_11 = rdata_3_value__22 | rdata_3_value__23; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_12 = rdata_3_value__24 | rdata_3_value__25; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_13 = rdata_3_value__26 | rdata_3_value__27; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_14 = rdata_3_value__28 | rdata_3_value__29; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_1_15 = rdata_3_value__30 | rdata_3_value__31; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_2_0 = rdata_3_value__1 | rdata_3_value_1_1; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_2_1 = rdata_3_value_1_2 | rdata_3_value_1_3; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_2_2 = rdata_3_value_1_4 | rdata_3_value_1_5; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_2_3 = rdata_3_value_1_6 | rdata_3_value_1_7; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_2_4 = rdata_3_value_1_8 | rdata_3_value_1_9; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_2_5 = rdata_3_value_1_10 | rdata_3_value_1_11; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_2_6 = rdata_3_value_1_12 | rdata_3_value_1_13; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_2_7 = rdata_3_value_1_14 | rdata_3_value_1_15; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_3_0 = rdata_3_value_2_0 | rdata_3_value_2_1; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_3_1 = rdata_3_value_2_2 | rdata_3_value_2_3; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_3_2 = rdata_3_value_2_4 | rdata_3_value_2_5; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_3_3 = rdata_3_value_2_6 | rdata_3_value_2_7; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_4_0 = rdata_3_value_3_0 | rdata_3_value_3_1; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_4_1 = rdata_3_value_3_2 | rdata_3_value_3_3; // @[Library.scala 129:37]
- wire [31:0] rdata_3_value_5_0 = rdata_3_value_4_0 | rdata_3_value_4_1; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value__1 = 5'h1 == io_readAddr_3_addr ? data : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__2 = 5'h2 == io_readAddr_3_addr ? data_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__3 = 5'h3 == io_readAddr_3_addr ? data_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__4 = 5'h4 == io_readAddr_3_addr ? data_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__5 = 5'h5 == io_readAddr_3_addr ? data_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__6 = 5'h6 == io_readAddr_3_addr ? data_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__7 = 5'h7 == io_readAddr_3_addr ? data_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__8 = 5'h8 == io_readAddr_3_addr ? data_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__9 = 5'h9 == io_readAddr_3_addr ? data_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__10 = 5'ha == io_readAddr_3_addr ? data_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__11 = 5'hb == io_readAddr_3_addr ? data_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__12 = 5'hc == io_readAddr_3_addr ? data_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__13 = 5'hd == io_readAddr_3_addr ? data_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__14 = 5'he == io_readAddr_3_addr ? data_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__15 = 5'hf == io_readAddr_3_addr ? data_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__16 = 5'h10 == io_readAddr_3_addr ? data_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__17 = 5'h11 == io_readAddr_3_addr ? data_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__18 = 5'h12 == io_readAddr_3_addr ? data_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__19 = 5'h13 == io_readAddr_3_addr ? data_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__20 = 5'h14 == io_readAddr_3_addr ? data_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__21 = 5'h15 == io_readAddr_3_addr ? data_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__22 = 5'h16 == io_readAddr_3_addr ? data_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__23 = 5'h17 == io_readAddr_3_addr ? data_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__24 = 5'h18 == io_readAddr_3_addr ? data_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__25 = 5'h19 == io_readAddr_3_addr ? data_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__26 = 5'h1a == io_readAddr_3_addr ? data_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__27 = 5'h1b == io_readAddr_3_addr ? data_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__28 = 5'h1c == io_readAddr_3_addr ? data_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__29 = 5'h1d == io_readAddr_3_addr ? data_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__30 = 5'h1e == io_readAddr_3_addr ? data_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value__31 = 5'h1f == io_readAddr_3_addr ? data_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_3_value_1_1 = wdata_3_value__2 | wdata_3_value__3; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_2 = wdata_3_value__4 | wdata_3_value__5; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_3 = wdata_3_value__6 | wdata_3_value__7; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_4 = wdata_3_value__8 | wdata_3_value__9; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_5 = wdata_3_value__10 | wdata_3_value__11; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_6 = wdata_3_value__12 | wdata_3_value__13; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_7 = wdata_3_value__14 | wdata_3_value__15; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_8 = wdata_3_value__16 | wdata_3_value__17; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_9 = wdata_3_value__18 | wdata_3_value__19; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_10 = wdata_3_value__20 | wdata_3_value__21; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_11 = wdata_3_value__22 | wdata_3_value__23; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_12 = wdata_3_value__24 | wdata_3_value__25; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_13 = wdata_3_value__26 | wdata_3_value__27; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_14 = wdata_3_value__28 | wdata_3_value__29; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_1_15 = wdata_3_value__30 | wdata_3_value__31; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_2_0 = wdata_3_value__1 | wdata_3_value_1_1; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_2_1 = wdata_3_value_1_2 | wdata_3_value_1_3; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_2_2 = wdata_3_value_1_4 | wdata_3_value_1_5; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_2_3 = wdata_3_value_1_6 | wdata_3_value_1_7; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_2_4 = wdata_3_value_1_8 | wdata_3_value_1_9; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_2_5 = wdata_3_value_1_10 | wdata_3_value_1_11; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_2_6 = wdata_3_value_1_12 | wdata_3_value_1_13; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_2_7 = wdata_3_value_1_14 | wdata_3_value_1_15; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_3_0 = wdata_3_value_2_0 | wdata_3_value_2_1; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_3_1 = wdata_3_value_2_2 | wdata_3_value_2_3; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_3_2 = wdata_3_value_2_4 | wdata_3_value_2_5; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_3_3 = wdata_3_value_2_6 | wdata_3_value_2_7; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_4_0 = wdata_3_value_3_0 | wdata_3_value_3_1; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_4_1 = wdata_3_value_3_2 | wdata_3_value_3_3; // @[Library.scala 129:37]
- wire [31:0] wdata_3_value_5_0 = wdata_3_value_4_0 | wdata_3_value_4_1; // @[Library.scala 129:37]
- wire [31:0] rwdata_3 = write_value_23_0 ? wdata_3_value_5_0 : rdata_3_value_5_0; // @[Regfile.scala 198:21]
- wire write_value_24_0 = 5'h0 == io_readAddr_4_addr; // @[Library.scala 115:27]
- wire write_value_24_1 = 5'h1 == io_readAddr_4_addr & writeValid_1; // @[Library.scala 115:22]
- wire write_value_24_2 = 5'h2 == io_readAddr_4_addr & writeValid_2; // @[Library.scala 115:22]
- wire write_value_24_3 = 5'h3 == io_readAddr_4_addr & writeValid_3; // @[Library.scala 115:22]
- wire write_value_24_4 = 5'h4 == io_readAddr_4_addr & writeValid_4; // @[Library.scala 115:22]
- wire write_value_24_5 = 5'h5 == io_readAddr_4_addr & writeValid_5; // @[Library.scala 115:22]
- wire write_value_24_6 = 5'h6 == io_readAddr_4_addr & writeValid_6; // @[Library.scala 115:22]
- wire write_value_24_7 = 5'h7 == io_readAddr_4_addr & writeValid_7; // @[Library.scala 115:22]
- wire write_value_24_8 = 5'h8 == io_readAddr_4_addr & writeValid_8; // @[Library.scala 115:22]
- wire write_value_24_9 = 5'h9 == io_readAddr_4_addr & writeValid_9; // @[Library.scala 115:22]
- wire write_value_24_10 = 5'ha == io_readAddr_4_addr & writeValid_10; // @[Library.scala 115:22]
- wire write_value_24_11 = 5'hb == io_readAddr_4_addr & writeValid_11; // @[Library.scala 115:22]
- wire write_value_24_12 = 5'hc == io_readAddr_4_addr & writeValid_12; // @[Library.scala 115:22]
- wire write_value_24_13 = 5'hd == io_readAddr_4_addr & writeValid_13; // @[Library.scala 115:22]
- wire write_value_24_14 = 5'he == io_readAddr_4_addr & writeValid_14; // @[Library.scala 115:22]
- wire write_value_24_15 = 5'hf == io_readAddr_4_addr & writeValid_15; // @[Library.scala 115:22]
- wire write_value_24_16 = 5'h10 == io_readAddr_4_addr & writeValid_16; // @[Library.scala 115:22]
- wire write_value_24_17 = 5'h11 == io_readAddr_4_addr & writeValid_17; // @[Library.scala 115:22]
- wire write_value_24_18 = 5'h12 == io_readAddr_4_addr & writeValid_18; // @[Library.scala 115:22]
- wire write_value_24_19 = 5'h13 == io_readAddr_4_addr & writeValid_19; // @[Library.scala 115:22]
- wire write_value_24_20 = 5'h14 == io_readAddr_4_addr & writeValid_20; // @[Library.scala 115:22]
- wire write_value_24_21 = 5'h15 == io_readAddr_4_addr & writeValid_21; // @[Library.scala 115:22]
- wire write_value_24_22 = 5'h16 == io_readAddr_4_addr & writeValid_22; // @[Library.scala 115:22]
- wire write_value_24_23 = 5'h17 == io_readAddr_4_addr & writeValid_23; // @[Library.scala 115:22]
- wire write_value_24_24 = 5'h18 == io_readAddr_4_addr & writeValid_24; // @[Library.scala 115:22]
- wire write_value_24_25 = 5'h19 == io_readAddr_4_addr & writeValid_25; // @[Library.scala 115:22]
- wire write_value_24_26 = 5'h1a == io_readAddr_4_addr & writeValid_26; // @[Library.scala 115:22]
- wire write_value_24_27 = 5'h1b == io_readAddr_4_addr & writeValid_27; // @[Library.scala 115:22]
- wire write_value_24_28 = 5'h1c == io_readAddr_4_addr & writeValid_28; // @[Library.scala 115:22]
- wire write_value_24_29 = 5'h1d == io_readAddr_4_addr & writeValid_29; // @[Library.scala 115:22]
- wire write_value_24_30 = 5'h1e == io_readAddr_4_addr & writeValid_30; // @[Library.scala 115:22]
- wire write_value_24_31 = 5'h1f == io_readAddr_4_addr & writeValid_31; // @[Library.scala 115:22]
- wire write_value_25_0 = write_value_24_0 | write_value_24_1; // @[Library.scala 129:37]
- wire write_value_25_1 = write_value_24_2 | write_value_24_3; // @[Library.scala 129:37]
- wire write_value_25_2 = write_value_24_4 | write_value_24_5; // @[Library.scala 129:37]
- wire write_value_25_3 = write_value_24_6 | write_value_24_7; // @[Library.scala 129:37]
- wire write_value_25_4 = write_value_24_8 | write_value_24_9; // @[Library.scala 129:37]
- wire write_value_25_5 = write_value_24_10 | write_value_24_11; // @[Library.scala 129:37]
- wire write_value_25_6 = write_value_24_12 | write_value_24_13; // @[Library.scala 129:37]
- wire write_value_25_7 = write_value_24_14 | write_value_24_15; // @[Library.scala 129:37]
- wire write_value_25_8 = write_value_24_16 | write_value_24_17; // @[Library.scala 129:37]
- wire write_value_25_9 = write_value_24_18 | write_value_24_19; // @[Library.scala 129:37]
- wire write_value_25_10 = write_value_24_20 | write_value_24_21; // @[Library.scala 129:37]
- wire write_value_25_11 = write_value_24_22 | write_value_24_23; // @[Library.scala 129:37]
- wire write_value_25_12 = write_value_24_24 | write_value_24_25; // @[Library.scala 129:37]
- wire write_value_25_13 = write_value_24_26 | write_value_24_27; // @[Library.scala 129:37]
- wire write_value_25_14 = write_value_24_28 | write_value_24_29; // @[Library.scala 129:37]
- wire write_value_25_15 = write_value_24_30 | write_value_24_31; // @[Library.scala 129:37]
- wire write_value_26_0 = write_value_25_0 | write_value_25_1; // @[Library.scala 129:37]
- wire write_value_26_1 = write_value_25_2 | write_value_25_3; // @[Library.scala 129:37]
- wire write_value_26_2 = write_value_25_4 | write_value_25_5; // @[Library.scala 129:37]
- wire write_value_26_3 = write_value_25_6 | write_value_25_7; // @[Library.scala 129:37]
- wire write_value_26_4 = write_value_25_8 | write_value_25_9; // @[Library.scala 129:37]
- wire write_value_26_5 = write_value_25_10 | write_value_25_11; // @[Library.scala 129:37]
- wire write_value_26_6 = write_value_25_12 | write_value_25_13; // @[Library.scala 129:37]
- wire write_value_26_7 = write_value_25_14 | write_value_25_15; // @[Library.scala 129:37]
- wire write_value_27_0 = write_value_26_0 | write_value_26_1; // @[Library.scala 129:37]
- wire write_value_27_1 = write_value_26_2 | write_value_26_3; // @[Library.scala 129:37]
- wire write_value_27_2 = write_value_26_4 | write_value_26_5; // @[Library.scala 129:37]
- wire write_value_27_3 = write_value_26_6 | write_value_26_7; // @[Library.scala 129:37]
- wire write_value_28_0 = write_value_27_0 | write_value_27_1; // @[Library.scala 129:37]
- wire write_value_28_1 = write_value_27_2 | write_value_27_3; // @[Library.scala 129:37]
- wire write_value_29_0 = write_value_28_0 | write_value_28_1; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value__1 = 5'h1 == io_readAddr_4_addr ? regfile_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__2 = 5'h2 == io_readAddr_4_addr ? regfile_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__3 = 5'h3 == io_readAddr_4_addr ? regfile_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__4 = 5'h4 == io_readAddr_4_addr ? regfile_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__5 = 5'h5 == io_readAddr_4_addr ? regfile_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__6 = 5'h6 == io_readAddr_4_addr ? regfile_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__7 = 5'h7 == io_readAddr_4_addr ? regfile_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__8 = 5'h8 == io_readAddr_4_addr ? regfile_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__9 = 5'h9 == io_readAddr_4_addr ? regfile_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__10 = 5'ha == io_readAddr_4_addr ? regfile_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__11 = 5'hb == io_readAddr_4_addr ? regfile_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__12 = 5'hc == io_readAddr_4_addr ? regfile_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__13 = 5'hd == io_readAddr_4_addr ? regfile_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__14 = 5'he == io_readAddr_4_addr ? regfile_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__15 = 5'hf == io_readAddr_4_addr ? regfile_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__16 = 5'h10 == io_readAddr_4_addr ? regfile_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__17 = 5'h11 == io_readAddr_4_addr ? regfile_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__18 = 5'h12 == io_readAddr_4_addr ? regfile_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__19 = 5'h13 == io_readAddr_4_addr ? regfile_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__20 = 5'h14 == io_readAddr_4_addr ? regfile_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__21 = 5'h15 == io_readAddr_4_addr ? regfile_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__22 = 5'h16 == io_readAddr_4_addr ? regfile_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__23 = 5'h17 == io_readAddr_4_addr ? regfile_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__24 = 5'h18 == io_readAddr_4_addr ? regfile_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__25 = 5'h19 == io_readAddr_4_addr ? regfile_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__26 = 5'h1a == io_readAddr_4_addr ? regfile_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__27 = 5'h1b == io_readAddr_4_addr ? regfile_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__28 = 5'h1c == io_readAddr_4_addr ? regfile_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__29 = 5'h1d == io_readAddr_4_addr ? regfile_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__30 = 5'h1e == io_readAddr_4_addr ? regfile_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value__31 = 5'h1f == io_readAddr_4_addr ? regfile_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_4_value_1_1 = rdata_4_value__2 | rdata_4_value__3; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_2 = rdata_4_value__4 | rdata_4_value__5; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_3 = rdata_4_value__6 | rdata_4_value__7; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_4 = rdata_4_value__8 | rdata_4_value__9; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_5 = rdata_4_value__10 | rdata_4_value__11; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_6 = rdata_4_value__12 | rdata_4_value__13; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_7 = rdata_4_value__14 | rdata_4_value__15; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_8 = rdata_4_value__16 | rdata_4_value__17; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_9 = rdata_4_value__18 | rdata_4_value__19; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_10 = rdata_4_value__20 | rdata_4_value__21; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_11 = rdata_4_value__22 | rdata_4_value__23; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_12 = rdata_4_value__24 | rdata_4_value__25; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_13 = rdata_4_value__26 | rdata_4_value__27; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_14 = rdata_4_value__28 | rdata_4_value__29; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_1_15 = rdata_4_value__30 | rdata_4_value__31; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_2_0 = rdata_4_value__1 | rdata_4_value_1_1; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_2_1 = rdata_4_value_1_2 | rdata_4_value_1_3; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_2_2 = rdata_4_value_1_4 | rdata_4_value_1_5; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_2_3 = rdata_4_value_1_6 | rdata_4_value_1_7; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_2_4 = rdata_4_value_1_8 | rdata_4_value_1_9; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_2_5 = rdata_4_value_1_10 | rdata_4_value_1_11; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_2_6 = rdata_4_value_1_12 | rdata_4_value_1_13; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_2_7 = rdata_4_value_1_14 | rdata_4_value_1_15; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_3_0 = rdata_4_value_2_0 | rdata_4_value_2_1; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_3_1 = rdata_4_value_2_2 | rdata_4_value_2_3; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_3_2 = rdata_4_value_2_4 | rdata_4_value_2_5; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_3_3 = rdata_4_value_2_6 | rdata_4_value_2_7; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_4_0 = rdata_4_value_3_0 | rdata_4_value_3_1; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_4_1 = rdata_4_value_3_2 | rdata_4_value_3_3; // @[Library.scala 129:37]
- wire [31:0] rdata_4_value_5_0 = rdata_4_value_4_0 | rdata_4_value_4_1; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value__1 = 5'h1 == io_readAddr_4_addr ? data : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__2 = 5'h2 == io_readAddr_4_addr ? data_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__3 = 5'h3 == io_readAddr_4_addr ? data_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__4 = 5'h4 == io_readAddr_4_addr ? data_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__5 = 5'h5 == io_readAddr_4_addr ? data_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__6 = 5'h6 == io_readAddr_4_addr ? data_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__7 = 5'h7 == io_readAddr_4_addr ? data_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__8 = 5'h8 == io_readAddr_4_addr ? data_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__9 = 5'h9 == io_readAddr_4_addr ? data_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__10 = 5'ha == io_readAddr_4_addr ? data_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__11 = 5'hb == io_readAddr_4_addr ? data_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__12 = 5'hc == io_readAddr_4_addr ? data_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__13 = 5'hd == io_readAddr_4_addr ? data_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__14 = 5'he == io_readAddr_4_addr ? data_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__15 = 5'hf == io_readAddr_4_addr ? data_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__16 = 5'h10 == io_readAddr_4_addr ? data_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__17 = 5'h11 == io_readAddr_4_addr ? data_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__18 = 5'h12 == io_readAddr_4_addr ? data_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__19 = 5'h13 == io_readAddr_4_addr ? data_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__20 = 5'h14 == io_readAddr_4_addr ? data_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__21 = 5'h15 == io_readAddr_4_addr ? data_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__22 = 5'h16 == io_readAddr_4_addr ? data_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__23 = 5'h17 == io_readAddr_4_addr ? data_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__24 = 5'h18 == io_readAddr_4_addr ? data_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__25 = 5'h19 == io_readAddr_4_addr ? data_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__26 = 5'h1a == io_readAddr_4_addr ? data_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__27 = 5'h1b == io_readAddr_4_addr ? data_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__28 = 5'h1c == io_readAddr_4_addr ? data_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__29 = 5'h1d == io_readAddr_4_addr ? data_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__30 = 5'h1e == io_readAddr_4_addr ? data_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value__31 = 5'h1f == io_readAddr_4_addr ? data_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_4_value_1_1 = wdata_4_value__2 | wdata_4_value__3; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_2 = wdata_4_value__4 | wdata_4_value__5; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_3 = wdata_4_value__6 | wdata_4_value__7; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_4 = wdata_4_value__8 | wdata_4_value__9; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_5 = wdata_4_value__10 | wdata_4_value__11; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_6 = wdata_4_value__12 | wdata_4_value__13; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_7 = wdata_4_value__14 | wdata_4_value__15; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_8 = wdata_4_value__16 | wdata_4_value__17; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_9 = wdata_4_value__18 | wdata_4_value__19; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_10 = wdata_4_value__20 | wdata_4_value__21; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_11 = wdata_4_value__22 | wdata_4_value__23; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_12 = wdata_4_value__24 | wdata_4_value__25; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_13 = wdata_4_value__26 | wdata_4_value__27; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_14 = wdata_4_value__28 | wdata_4_value__29; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_1_15 = wdata_4_value__30 | wdata_4_value__31; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_2_0 = wdata_4_value__1 | wdata_4_value_1_1; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_2_1 = wdata_4_value_1_2 | wdata_4_value_1_3; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_2_2 = wdata_4_value_1_4 | wdata_4_value_1_5; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_2_3 = wdata_4_value_1_6 | wdata_4_value_1_7; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_2_4 = wdata_4_value_1_8 | wdata_4_value_1_9; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_2_5 = wdata_4_value_1_10 | wdata_4_value_1_11; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_2_6 = wdata_4_value_1_12 | wdata_4_value_1_13; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_2_7 = wdata_4_value_1_14 | wdata_4_value_1_15; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_3_0 = wdata_4_value_2_0 | wdata_4_value_2_1; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_3_1 = wdata_4_value_2_2 | wdata_4_value_2_3; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_3_2 = wdata_4_value_2_4 | wdata_4_value_2_5; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_3_3 = wdata_4_value_2_6 | wdata_4_value_2_7; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_4_0 = wdata_4_value_3_0 | wdata_4_value_3_1; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_4_1 = wdata_4_value_3_2 | wdata_4_value_3_3; // @[Library.scala 129:37]
- wire [31:0] wdata_4_value_5_0 = wdata_4_value_4_0 | wdata_4_value_4_1; // @[Library.scala 129:37]
- wire [31:0] rwdata_4 = write_value_29_0 ? wdata_4_value_5_0 : rdata_4_value_5_0; // @[Regfile.scala 198:21]
- wire write_value_30_0 = 5'h0 == io_readAddr_5_addr; // @[Library.scala 115:27]
- wire write_value_30_1 = 5'h1 == io_readAddr_5_addr & writeValid_1; // @[Library.scala 115:22]
- wire write_value_30_2 = 5'h2 == io_readAddr_5_addr & writeValid_2; // @[Library.scala 115:22]
- wire write_value_30_3 = 5'h3 == io_readAddr_5_addr & writeValid_3; // @[Library.scala 115:22]
- wire write_value_30_4 = 5'h4 == io_readAddr_5_addr & writeValid_4; // @[Library.scala 115:22]
- wire write_value_30_5 = 5'h5 == io_readAddr_5_addr & writeValid_5; // @[Library.scala 115:22]
- wire write_value_30_6 = 5'h6 == io_readAddr_5_addr & writeValid_6; // @[Library.scala 115:22]
- wire write_value_30_7 = 5'h7 == io_readAddr_5_addr & writeValid_7; // @[Library.scala 115:22]
- wire write_value_30_8 = 5'h8 == io_readAddr_5_addr & writeValid_8; // @[Library.scala 115:22]
- wire write_value_30_9 = 5'h9 == io_readAddr_5_addr & writeValid_9; // @[Library.scala 115:22]
- wire write_value_30_10 = 5'ha == io_readAddr_5_addr & writeValid_10; // @[Library.scala 115:22]
- wire write_value_30_11 = 5'hb == io_readAddr_5_addr & writeValid_11; // @[Library.scala 115:22]
- wire write_value_30_12 = 5'hc == io_readAddr_5_addr & writeValid_12; // @[Library.scala 115:22]
- wire write_value_30_13 = 5'hd == io_readAddr_5_addr & writeValid_13; // @[Library.scala 115:22]
- wire write_value_30_14 = 5'he == io_readAddr_5_addr & writeValid_14; // @[Library.scala 115:22]
- wire write_value_30_15 = 5'hf == io_readAddr_5_addr & writeValid_15; // @[Library.scala 115:22]
- wire write_value_30_16 = 5'h10 == io_readAddr_5_addr & writeValid_16; // @[Library.scala 115:22]
- wire write_value_30_17 = 5'h11 == io_readAddr_5_addr & writeValid_17; // @[Library.scala 115:22]
- wire write_value_30_18 = 5'h12 == io_readAddr_5_addr & writeValid_18; // @[Library.scala 115:22]
- wire write_value_30_19 = 5'h13 == io_readAddr_5_addr & writeValid_19; // @[Library.scala 115:22]
- wire write_value_30_20 = 5'h14 == io_readAddr_5_addr & writeValid_20; // @[Library.scala 115:22]
- wire write_value_30_21 = 5'h15 == io_readAddr_5_addr & writeValid_21; // @[Library.scala 115:22]
- wire write_value_30_22 = 5'h16 == io_readAddr_5_addr & writeValid_22; // @[Library.scala 115:22]
- wire write_value_30_23 = 5'h17 == io_readAddr_5_addr & writeValid_23; // @[Library.scala 115:22]
- wire write_value_30_24 = 5'h18 == io_readAddr_5_addr & writeValid_24; // @[Library.scala 115:22]
- wire write_value_30_25 = 5'h19 == io_readAddr_5_addr & writeValid_25; // @[Library.scala 115:22]
- wire write_value_30_26 = 5'h1a == io_readAddr_5_addr & writeValid_26; // @[Library.scala 115:22]
- wire write_value_30_27 = 5'h1b == io_readAddr_5_addr & writeValid_27; // @[Library.scala 115:22]
- wire write_value_30_28 = 5'h1c == io_readAddr_5_addr & writeValid_28; // @[Library.scala 115:22]
- wire write_value_30_29 = 5'h1d == io_readAddr_5_addr & writeValid_29; // @[Library.scala 115:22]
- wire write_value_30_30 = 5'h1e == io_readAddr_5_addr & writeValid_30; // @[Library.scala 115:22]
- wire write_value_30_31 = 5'h1f == io_readAddr_5_addr & writeValid_31; // @[Library.scala 115:22]
- wire write_value_31_0 = write_value_30_0 | write_value_30_1; // @[Library.scala 129:37]
- wire write_value_31_1 = write_value_30_2 | write_value_30_3; // @[Library.scala 129:37]
- wire write_value_31_2 = write_value_30_4 | write_value_30_5; // @[Library.scala 129:37]
- wire write_value_31_3 = write_value_30_6 | write_value_30_7; // @[Library.scala 129:37]
- wire write_value_31_4 = write_value_30_8 | write_value_30_9; // @[Library.scala 129:37]
- wire write_value_31_5 = write_value_30_10 | write_value_30_11; // @[Library.scala 129:37]
- wire write_value_31_6 = write_value_30_12 | write_value_30_13; // @[Library.scala 129:37]
- wire write_value_31_7 = write_value_30_14 | write_value_30_15; // @[Library.scala 129:37]
- wire write_value_31_8 = write_value_30_16 | write_value_30_17; // @[Library.scala 129:37]
- wire write_value_31_9 = write_value_30_18 | write_value_30_19; // @[Library.scala 129:37]
- wire write_value_31_10 = write_value_30_20 | write_value_30_21; // @[Library.scala 129:37]
- wire write_value_31_11 = write_value_30_22 | write_value_30_23; // @[Library.scala 129:37]
- wire write_value_31_12 = write_value_30_24 | write_value_30_25; // @[Library.scala 129:37]
- wire write_value_31_13 = write_value_30_26 | write_value_30_27; // @[Library.scala 129:37]
- wire write_value_31_14 = write_value_30_28 | write_value_30_29; // @[Library.scala 129:37]
- wire write_value_31_15 = write_value_30_30 | write_value_30_31; // @[Library.scala 129:37]
- wire write_value_32_0 = write_value_31_0 | write_value_31_1; // @[Library.scala 129:37]
- wire write_value_32_1 = write_value_31_2 | write_value_31_3; // @[Library.scala 129:37]
- wire write_value_32_2 = write_value_31_4 | write_value_31_5; // @[Library.scala 129:37]
- wire write_value_32_3 = write_value_31_6 | write_value_31_7; // @[Library.scala 129:37]
- wire write_value_32_4 = write_value_31_8 | write_value_31_9; // @[Library.scala 129:37]
- wire write_value_32_5 = write_value_31_10 | write_value_31_11; // @[Library.scala 129:37]
- wire write_value_32_6 = write_value_31_12 | write_value_31_13; // @[Library.scala 129:37]
- wire write_value_32_7 = write_value_31_14 | write_value_31_15; // @[Library.scala 129:37]
- wire write_value_33_0 = write_value_32_0 | write_value_32_1; // @[Library.scala 129:37]
- wire write_value_33_1 = write_value_32_2 | write_value_32_3; // @[Library.scala 129:37]
- wire write_value_33_2 = write_value_32_4 | write_value_32_5; // @[Library.scala 129:37]
- wire write_value_33_3 = write_value_32_6 | write_value_32_7; // @[Library.scala 129:37]
- wire write_value_34_0 = write_value_33_0 | write_value_33_1; // @[Library.scala 129:37]
- wire write_value_34_1 = write_value_33_2 | write_value_33_3; // @[Library.scala 129:37]
- wire write_value_35_0 = write_value_34_0 | write_value_34_1; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value__1 = 5'h1 == io_readAddr_5_addr ? regfile_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__2 = 5'h2 == io_readAddr_5_addr ? regfile_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__3 = 5'h3 == io_readAddr_5_addr ? regfile_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__4 = 5'h4 == io_readAddr_5_addr ? regfile_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__5 = 5'h5 == io_readAddr_5_addr ? regfile_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__6 = 5'h6 == io_readAddr_5_addr ? regfile_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__7 = 5'h7 == io_readAddr_5_addr ? regfile_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__8 = 5'h8 == io_readAddr_5_addr ? regfile_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__9 = 5'h9 == io_readAddr_5_addr ? regfile_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__10 = 5'ha == io_readAddr_5_addr ? regfile_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__11 = 5'hb == io_readAddr_5_addr ? regfile_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__12 = 5'hc == io_readAddr_5_addr ? regfile_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__13 = 5'hd == io_readAddr_5_addr ? regfile_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__14 = 5'he == io_readAddr_5_addr ? regfile_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__15 = 5'hf == io_readAddr_5_addr ? regfile_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__16 = 5'h10 == io_readAddr_5_addr ? regfile_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__17 = 5'h11 == io_readAddr_5_addr ? regfile_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__18 = 5'h12 == io_readAddr_5_addr ? regfile_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__19 = 5'h13 == io_readAddr_5_addr ? regfile_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__20 = 5'h14 == io_readAddr_5_addr ? regfile_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__21 = 5'h15 == io_readAddr_5_addr ? regfile_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__22 = 5'h16 == io_readAddr_5_addr ? regfile_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__23 = 5'h17 == io_readAddr_5_addr ? regfile_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__24 = 5'h18 == io_readAddr_5_addr ? regfile_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__25 = 5'h19 == io_readAddr_5_addr ? regfile_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__26 = 5'h1a == io_readAddr_5_addr ? regfile_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__27 = 5'h1b == io_readAddr_5_addr ? regfile_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__28 = 5'h1c == io_readAddr_5_addr ? regfile_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__29 = 5'h1d == io_readAddr_5_addr ? regfile_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__30 = 5'h1e == io_readAddr_5_addr ? regfile_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value__31 = 5'h1f == io_readAddr_5_addr ? regfile_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_5_value_1_1 = rdata_5_value__2 | rdata_5_value__3; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_2 = rdata_5_value__4 | rdata_5_value__5; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_3 = rdata_5_value__6 | rdata_5_value__7; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_4 = rdata_5_value__8 | rdata_5_value__9; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_5 = rdata_5_value__10 | rdata_5_value__11; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_6 = rdata_5_value__12 | rdata_5_value__13; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_7 = rdata_5_value__14 | rdata_5_value__15; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_8 = rdata_5_value__16 | rdata_5_value__17; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_9 = rdata_5_value__18 | rdata_5_value__19; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_10 = rdata_5_value__20 | rdata_5_value__21; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_11 = rdata_5_value__22 | rdata_5_value__23; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_12 = rdata_5_value__24 | rdata_5_value__25; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_13 = rdata_5_value__26 | rdata_5_value__27; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_14 = rdata_5_value__28 | rdata_5_value__29; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_1_15 = rdata_5_value__30 | rdata_5_value__31; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_2_0 = rdata_5_value__1 | rdata_5_value_1_1; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_2_1 = rdata_5_value_1_2 | rdata_5_value_1_3; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_2_2 = rdata_5_value_1_4 | rdata_5_value_1_5; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_2_3 = rdata_5_value_1_6 | rdata_5_value_1_7; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_2_4 = rdata_5_value_1_8 | rdata_5_value_1_9; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_2_5 = rdata_5_value_1_10 | rdata_5_value_1_11; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_2_6 = rdata_5_value_1_12 | rdata_5_value_1_13; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_2_7 = rdata_5_value_1_14 | rdata_5_value_1_15; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_3_0 = rdata_5_value_2_0 | rdata_5_value_2_1; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_3_1 = rdata_5_value_2_2 | rdata_5_value_2_3; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_3_2 = rdata_5_value_2_4 | rdata_5_value_2_5; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_3_3 = rdata_5_value_2_6 | rdata_5_value_2_7; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_4_0 = rdata_5_value_3_0 | rdata_5_value_3_1; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_4_1 = rdata_5_value_3_2 | rdata_5_value_3_3; // @[Library.scala 129:37]
- wire [31:0] rdata_5_value_5_0 = rdata_5_value_4_0 | rdata_5_value_4_1; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value__1 = 5'h1 == io_readAddr_5_addr ? data : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__2 = 5'h2 == io_readAddr_5_addr ? data_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__3 = 5'h3 == io_readAddr_5_addr ? data_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__4 = 5'h4 == io_readAddr_5_addr ? data_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__5 = 5'h5 == io_readAddr_5_addr ? data_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__6 = 5'h6 == io_readAddr_5_addr ? data_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__7 = 5'h7 == io_readAddr_5_addr ? data_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__8 = 5'h8 == io_readAddr_5_addr ? data_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__9 = 5'h9 == io_readAddr_5_addr ? data_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__10 = 5'ha == io_readAddr_5_addr ? data_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__11 = 5'hb == io_readAddr_5_addr ? data_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__12 = 5'hc == io_readAddr_5_addr ? data_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__13 = 5'hd == io_readAddr_5_addr ? data_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__14 = 5'he == io_readAddr_5_addr ? data_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__15 = 5'hf == io_readAddr_5_addr ? data_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__16 = 5'h10 == io_readAddr_5_addr ? data_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__17 = 5'h11 == io_readAddr_5_addr ? data_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__18 = 5'h12 == io_readAddr_5_addr ? data_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__19 = 5'h13 == io_readAddr_5_addr ? data_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__20 = 5'h14 == io_readAddr_5_addr ? data_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__21 = 5'h15 == io_readAddr_5_addr ? data_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__22 = 5'h16 == io_readAddr_5_addr ? data_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__23 = 5'h17 == io_readAddr_5_addr ? data_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__24 = 5'h18 == io_readAddr_5_addr ? data_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__25 = 5'h19 == io_readAddr_5_addr ? data_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__26 = 5'h1a == io_readAddr_5_addr ? data_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__27 = 5'h1b == io_readAddr_5_addr ? data_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__28 = 5'h1c == io_readAddr_5_addr ? data_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__29 = 5'h1d == io_readAddr_5_addr ? data_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__30 = 5'h1e == io_readAddr_5_addr ? data_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value__31 = 5'h1f == io_readAddr_5_addr ? data_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_5_value_1_1 = wdata_5_value__2 | wdata_5_value__3; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_2 = wdata_5_value__4 | wdata_5_value__5; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_3 = wdata_5_value__6 | wdata_5_value__7; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_4 = wdata_5_value__8 | wdata_5_value__9; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_5 = wdata_5_value__10 | wdata_5_value__11; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_6 = wdata_5_value__12 | wdata_5_value__13; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_7 = wdata_5_value__14 | wdata_5_value__15; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_8 = wdata_5_value__16 | wdata_5_value__17; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_9 = wdata_5_value__18 | wdata_5_value__19; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_10 = wdata_5_value__20 | wdata_5_value__21; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_11 = wdata_5_value__22 | wdata_5_value__23; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_12 = wdata_5_value__24 | wdata_5_value__25; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_13 = wdata_5_value__26 | wdata_5_value__27; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_14 = wdata_5_value__28 | wdata_5_value__29; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_1_15 = wdata_5_value__30 | wdata_5_value__31; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_2_0 = wdata_5_value__1 | wdata_5_value_1_1; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_2_1 = wdata_5_value_1_2 | wdata_5_value_1_3; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_2_2 = wdata_5_value_1_4 | wdata_5_value_1_5; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_2_3 = wdata_5_value_1_6 | wdata_5_value_1_7; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_2_4 = wdata_5_value_1_8 | wdata_5_value_1_9; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_2_5 = wdata_5_value_1_10 | wdata_5_value_1_11; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_2_6 = wdata_5_value_1_12 | wdata_5_value_1_13; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_2_7 = wdata_5_value_1_14 | wdata_5_value_1_15; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_3_0 = wdata_5_value_2_0 | wdata_5_value_2_1; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_3_1 = wdata_5_value_2_2 | wdata_5_value_2_3; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_3_2 = wdata_5_value_2_4 | wdata_5_value_2_5; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_3_3 = wdata_5_value_2_6 | wdata_5_value_2_7; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_4_0 = wdata_5_value_3_0 | wdata_5_value_3_1; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_4_1 = wdata_5_value_3_2 | wdata_5_value_3_3; // @[Library.scala 129:37]
- wire [31:0] wdata_5_value_5_0 = wdata_5_value_4_0 | wdata_5_value_4_1; // @[Library.scala 129:37]
- wire [31:0] rwdata_5 = write_value_35_0 ? wdata_5_value_5_0 : rdata_5_value_5_0; // @[Regfile.scala 198:21]
- wire write_value_36_0 = 5'h0 == io_readAddr_6_addr; // @[Library.scala 115:27]
- wire write_value_36_1 = 5'h1 == io_readAddr_6_addr & writeValid_1; // @[Library.scala 115:22]
- wire write_value_36_2 = 5'h2 == io_readAddr_6_addr & writeValid_2; // @[Library.scala 115:22]
- wire write_value_36_3 = 5'h3 == io_readAddr_6_addr & writeValid_3; // @[Library.scala 115:22]
- wire write_value_36_4 = 5'h4 == io_readAddr_6_addr & writeValid_4; // @[Library.scala 115:22]
- wire write_value_36_5 = 5'h5 == io_readAddr_6_addr & writeValid_5; // @[Library.scala 115:22]
- wire write_value_36_6 = 5'h6 == io_readAddr_6_addr & writeValid_6; // @[Library.scala 115:22]
- wire write_value_36_7 = 5'h7 == io_readAddr_6_addr & writeValid_7; // @[Library.scala 115:22]
- wire write_value_36_8 = 5'h8 == io_readAddr_6_addr & writeValid_8; // @[Library.scala 115:22]
- wire write_value_36_9 = 5'h9 == io_readAddr_6_addr & writeValid_9; // @[Library.scala 115:22]
- wire write_value_36_10 = 5'ha == io_readAddr_6_addr & writeValid_10; // @[Library.scala 115:22]
- wire write_value_36_11 = 5'hb == io_readAddr_6_addr & writeValid_11; // @[Library.scala 115:22]
- wire write_value_36_12 = 5'hc == io_readAddr_6_addr & writeValid_12; // @[Library.scala 115:22]
- wire write_value_36_13 = 5'hd == io_readAddr_6_addr & writeValid_13; // @[Library.scala 115:22]
- wire write_value_36_14 = 5'he == io_readAddr_6_addr & writeValid_14; // @[Library.scala 115:22]
- wire write_value_36_15 = 5'hf == io_readAddr_6_addr & writeValid_15; // @[Library.scala 115:22]
- wire write_value_36_16 = 5'h10 == io_readAddr_6_addr & writeValid_16; // @[Library.scala 115:22]
- wire write_value_36_17 = 5'h11 == io_readAddr_6_addr & writeValid_17; // @[Library.scala 115:22]
- wire write_value_36_18 = 5'h12 == io_readAddr_6_addr & writeValid_18; // @[Library.scala 115:22]
- wire write_value_36_19 = 5'h13 == io_readAddr_6_addr & writeValid_19; // @[Library.scala 115:22]
- wire write_value_36_20 = 5'h14 == io_readAddr_6_addr & writeValid_20; // @[Library.scala 115:22]
- wire write_value_36_21 = 5'h15 == io_readAddr_6_addr & writeValid_21; // @[Library.scala 115:22]
- wire write_value_36_22 = 5'h16 == io_readAddr_6_addr & writeValid_22; // @[Library.scala 115:22]
- wire write_value_36_23 = 5'h17 == io_readAddr_6_addr & writeValid_23; // @[Library.scala 115:22]
- wire write_value_36_24 = 5'h18 == io_readAddr_6_addr & writeValid_24; // @[Library.scala 115:22]
- wire write_value_36_25 = 5'h19 == io_readAddr_6_addr & writeValid_25; // @[Library.scala 115:22]
- wire write_value_36_26 = 5'h1a == io_readAddr_6_addr & writeValid_26; // @[Library.scala 115:22]
- wire write_value_36_27 = 5'h1b == io_readAddr_6_addr & writeValid_27; // @[Library.scala 115:22]
- wire write_value_36_28 = 5'h1c == io_readAddr_6_addr & writeValid_28; // @[Library.scala 115:22]
- wire write_value_36_29 = 5'h1d == io_readAddr_6_addr & writeValid_29; // @[Library.scala 115:22]
- wire write_value_36_30 = 5'h1e == io_readAddr_6_addr & writeValid_30; // @[Library.scala 115:22]
- wire write_value_36_31 = 5'h1f == io_readAddr_6_addr & writeValid_31; // @[Library.scala 115:22]
- wire write_value_37_0 = write_value_36_0 | write_value_36_1; // @[Library.scala 129:37]
- wire write_value_37_1 = write_value_36_2 | write_value_36_3; // @[Library.scala 129:37]
- wire write_value_37_2 = write_value_36_4 | write_value_36_5; // @[Library.scala 129:37]
- wire write_value_37_3 = write_value_36_6 | write_value_36_7; // @[Library.scala 129:37]
- wire write_value_37_4 = write_value_36_8 | write_value_36_9; // @[Library.scala 129:37]
- wire write_value_37_5 = write_value_36_10 | write_value_36_11; // @[Library.scala 129:37]
- wire write_value_37_6 = write_value_36_12 | write_value_36_13; // @[Library.scala 129:37]
- wire write_value_37_7 = write_value_36_14 | write_value_36_15; // @[Library.scala 129:37]
- wire write_value_37_8 = write_value_36_16 | write_value_36_17; // @[Library.scala 129:37]
- wire write_value_37_9 = write_value_36_18 | write_value_36_19; // @[Library.scala 129:37]
- wire write_value_37_10 = write_value_36_20 | write_value_36_21; // @[Library.scala 129:37]
- wire write_value_37_11 = write_value_36_22 | write_value_36_23; // @[Library.scala 129:37]
- wire write_value_37_12 = write_value_36_24 | write_value_36_25; // @[Library.scala 129:37]
- wire write_value_37_13 = write_value_36_26 | write_value_36_27; // @[Library.scala 129:37]
- wire write_value_37_14 = write_value_36_28 | write_value_36_29; // @[Library.scala 129:37]
- wire write_value_37_15 = write_value_36_30 | write_value_36_31; // @[Library.scala 129:37]
- wire write_value_38_0 = write_value_37_0 | write_value_37_1; // @[Library.scala 129:37]
- wire write_value_38_1 = write_value_37_2 | write_value_37_3; // @[Library.scala 129:37]
- wire write_value_38_2 = write_value_37_4 | write_value_37_5; // @[Library.scala 129:37]
- wire write_value_38_3 = write_value_37_6 | write_value_37_7; // @[Library.scala 129:37]
- wire write_value_38_4 = write_value_37_8 | write_value_37_9; // @[Library.scala 129:37]
- wire write_value_38_5 = write_value_37_10 | write_value_37_11; // @[Library.scala 129:37]
- wire write_value_38_6 = write_value_37_12 | write_value_37_13; // @[Library.scala 129:37]
- wire write_value_38_7 = write_value_37_14 | write_value_37_15; // @[Library.scala 129:37]
- wire write_value_39_0 = write_value_38_0 | write_value_38_1; // @[Library.scala 129:37]
- wire write_value_39_1 = write_value_38_2 | write_value_38_3; // @[Library.scala 129:37]
- wire write_value_39_2 = write_value_38_4 | write_value_38_5; // @[Library.scala 129:37]
- wire write_value_39_3 = write_value_38_6 | write_value_38_7; // @[Library.scala 129:37]
- wire write_value_40_0 = write_value_39_0 | write_value_39_1; // @[Library.scala 129:37]
- wire write_value_40_1 = write_value_39_2 | write_value_39_3; // @[Library.scala 129:37]
- wire write_value_41_0 = write_value_40_0 | write_value_40_1; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value__1 = 5'h1 == io_readAddr_6_addr ? regfile_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__2 = 5'h2 == io_readAddr_6_addr ? regfile_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__3 = 5'h3 == io_readAddr_6_addr ? regfile_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__4 = 5'h4 == io_readAddr_6_addr ? regfile_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__5 = 5'h5 == io_readAddr_6_addr ? regfile_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__6 = 5'h6 == io_readAddr_6_addr ? regfile_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__7 = 5'h7 == io_readAddr_6_addr ? regfile_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__8 = 5'h8 == io_readAddr_6_addr ? regfile_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__9 = 5'h9 == io_readAddr_6_addr ? regfile_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__10 = 5'ha == io_readAddr_6_addr ? regfile_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__11 = 5'hb == io_readAddr_6_addr ? regfile_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__12 = 5'hc == io_readAddr_6_addr ? regfile_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__13 = 5'hd == io_readAddr_6_addr ? regfile_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__14 = 5'he == io_readAddr_6_addr ? regfile_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__15 = 5'hf == io_readAddr_6_addr ? regfile_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__16 = 5'h10 == io_readAddr_6_addr ? regfile_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__17 = 5'h11 == io_readAddr_6_addr ? regfile_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__18 = 5'h12 == io_readAddr_6_addr ? regfile_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__19 = 5'h13 == io_readAddr_6_addr ? regfile_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__20 = 5'h14 == io_readAddr_6_addr ? regfile_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__21 = 5'h15 == io_readAddr_6_addr ? regfile_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__22 = 5'h16 == io_readAddr_6_addr ? regfile_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__23 = 5'h17 == io_readAddr_6_addr ? regfile_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__24 = 5'h18 == io_readAddr_6_addr ? regfile_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__25 = 5'h19 == io_readAddr_6_addr ? regfile_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__26 = 5'h1a == io_readAddr_6_addr ? regfile_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__27 = 5'h1b == io_readAddr_6_addr ? regfile_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__28 = 5'h1c == io_readAddr_6_addr ? regfile_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__29 = 5'h1d == io_readAddr_6_addr ? regfile_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__30 = 5'h1e == io_readAddr_6_addr ? regfile_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value__31 = 5'h1f == io_readAddr_6_addr ? regfile_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_6_value_1_1 = rdata_6_value__2 | rdata_6_value__3; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_2 = rdata_6_value__4 | rdata_6_value__5; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_3 = rdata_6_value__6 | rdata_6_value__7; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_4 = rdata_6_value__8 | rdata_6_value__9; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_5 = rdata_6_value__10 | rdata_6_value__11; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_6 = rdata_6_value__12 | rdata_6_value__13; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_7 = rdata_6_value__14 | rdata_6_value__15; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_8 = rdata_6_value__16 | rdata_6_value__17; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_9 = rdata_6_value__18 | rdata_6_value__19; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_10 = rdata_6_value__20 | rdata_6_value__21; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_11 = rdata_6_value__22 | rdata_6_value__23; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_12 = rdata_6_value__24 | rdata_6_value__25; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_13 = rdata_6_value__26 | rdata_6_value__27; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_14 = rdata_6_value__28 | rdata_6_value__29; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_1_15 = rdata_6_value__30 | rdata_6_value__31; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_2_0 = rdata_6_value__1 | rdata_6_value_1_1; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_2_1 = rdata_6_value_1_2 | rdata_6_value_1_3; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_2_2 = rdata_6_value_1_4 | rdata_6_value_1_5; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_2_3 = rdata_6_value_1_6 | rdata_6_value_1_7; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_2_4 = rdata_6_value_1_8 | rdata_6_value_1_9; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_2_5 = rdata_6_value_1_10 | rdata_6_value_1_11; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_2_6 = rdata_6_value_1_12 | rdata_6_value_1_13; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_2_7 = rdata_6_value_1_14 | rdata_6_value_1_15; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_3_0 = rdata_6_value_2_0 | rdata_6_value_2_1; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_3_1 = rdata_6_value_2_2 | rdata_6_value_2_3; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_3_2 = rdata_6_value_2_4 | rdata_6_value_2_5; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_3_3 = rdata_6_value_2_6 | rdata_6_value_2_7; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_4_0 = rdata_6_value_3_0 | rdata_6_value_3_1; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_4_1 = rdata_6_value_3_2 | rdata_6_value_3_3; // @[Library.scala 129:37]
- wire [31:0] rdata_6_value_5_0 = rdata_6_value_4_0 | rdata_6_value_4_1; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value__1 = 5'h1 == io_readAddr_6_addr ? data : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__2 = 5'h2 == io_readAddr_6_addr ? data_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__3 = 5'h3 == io_readAddr_6_addr ? data_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__4 = 5'h4 == io_readAddr_6_addr ? data_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__5 = 5'h5 == io_readAddr_6_addr ? data_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__6 = 5'h6 == io_readAddr_6_addr ? data_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__7 = 5'h7 == io_readAddr_6_addr ? data_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__8 = 5'h8 == io_readAddr_6_addr ? data_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__9 = 5'h9 == io_readAddr_6_addr ? data_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__10 = 5'ha == io_readAddr_6_addr ? data_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__11 = 5'hb == io_readAddr_6_addr ? data_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__12 = 5'hc == io_readAddr_6_addr ? data_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__13 = 5'hd == io_readAddr_6_addr ? data_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__14 = 5'he == io_readAddr_6_addr ? data_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__15 = 5'hf == io_readAddr_6_addr ? data_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__16 = 5'h10 == io_readAddr_6_addr ? data_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__17 = 5'h11 == io_readAddr_6_addr ? data_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__18 = 5'h12 == io_readAddr_6_addr ? data_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__19 = 5'h13 == io_readAddr_6_addr ? data_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__20 = 5'h14 == io_readAddr_6_addr ? data_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__21 = 5'h15 == io_readAddr_6_addr ? data_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__22 = 5'h16 == io_readAddr_6_addr ? data_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__23 = 5'h17 == io_readAddr_6_addr ? data_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__24 = 5'h18 == io_readAddr_6_addr ? data_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__25 = 5'h19 == io_readAddr_6_addr ? data_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__26 = 5'h1a == io_readAddr_6_addr ? data_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__27 = 5'h1b == io_readAddr_6_addr ? data_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__28 = 5'h1c == io_readAddr_6_addr ? data_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__29 = 5'h1d == io_readAddr_6_addr ? data_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__30 = 5'h1e == io_readAddr_6_addr ? data_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value__31 = 5'h1f == io_readAddr_6_addr ? data_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_6_value_1_1 = wdata_6_value__2 | wdata_6_value__3; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_2 = wdata_6_value__4 | wdata_6_value__5; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_3 = wdata_6_value__6 | wdata_6_value__7; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_4 = wdata_6_value__8 | wdata_6_value__9; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_5 = wdata_6_value__10 | wdata_6_value__11; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_6 = wdata_6_value__12 | wdata_6_value__13; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_7 = wdata_6_value__14 | wdata_6_value__15; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_8 = wdata_6_value__16 | wdata_6_value__17; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_9 = wdata_6_value__18 | wdata_6_value__19; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_10 = wdata_6_value__20 | wdata_6_value__21; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_11 = wdata_6_value__22 | wdata_6_value__23; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_12 = wdata_6_value__24 | wdata_6_value__25; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_13 = wdata_6_value__26 | wdata_6_value__27; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_14 = wdata_6_value__28 | wdata_6_value__29; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_1_15 = wdata_6_value__30 | wdata_6_value__31; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_2_0 = wdata_6_value__1 | wdata_6_value_1_1; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_2_1 = wdata_6_value_1_2 | wdata_6_value_1_3; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_2_2 = wdata_6_value_1_4 | wdata_6_value_1_5; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_2_3 = wdata_6_value_1_6 | wdata_6_value_1_7; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_2_4 = wdata_6_value_1_8 | wdata_6_value_1_9; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_2_5 = wdata_6_value_1_10 | wdata_6_value_1_11; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_2_6 = wdata_6_value_1_12 | wdata_6_value_1_13; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_2_7 = wdata_6_value_1_14 | wdata_6_value_1_15; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_3_0 = wdata_6_value_2_0 | wdata_6_value_2_1; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_3_1 = wdata_6_value_2_2 | wdata_6_value_2_3; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_3_2 = wdata_6_value_2_4 | wdata_6_value_2_5; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_3_3 = wdata_6_value_2_6 | wdata_6_value_2_7; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_4_0 = wdata_6_value_3_0 | wdata_6_value_3_1; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_4_1 = wdata_6_value_3_2 | wdata_6_value_3_3; // @[Library.scala 129:37]
- wire [31:0] wdata_6_value_5_0 = wdata_6_value_4_0 | wdata_6_value_4_1; // @[Library.scala 129:37]
- wire [31:0] rwdata_6 = write_value_41_0 ? wdata_6_value_5_0 : rdata_6_value_5_0; // @[Regfile.scala 198:21]
- wire write_value_42_0 = 5'h0 == io_readAddr_7_addr; // @[Library.scala 115:27]
- wire write_value_42_1 = 5'h1 == io_readAddr_7_addr & writeValid_1; // @[Library.scala 115:22]
- wire write_value_42_2 = 5'h2 == io_readAddr_7_addr & writeValid_2; // @[Library.scala 115:22]
- wire write_value_42_3 = 5'h3 == io_readAddr_7_addr & writeValid_3; // @[Library.scala 115:22]
- wire write_value_42_4 = 5'h4 == io_readAddr_7_addr & writeValid_4; // @[Library.scala 115:22]
- wire write_value_42_5 = 5'h5 == io_readAddr_7_addr & writeValid_5; // @[Library.scala 115:22]
- wire write_value_42_6 = 5'h6 == io_readAddr_7_addr & writeValid_6; // @[Library.scala 115:22]
- wire write_value_42_7 = 5'h7 == io_readAddr_7_addr & writeValid_7; // @[Library.scala 115:22]
- wire write_value_42_8 = 5'h8 == io_readAddr_7_addr & writeValid_8; // @[Library.scala 115:22]
- wire write_value_42_9 = 5'h9 == io_readAddr_7_addr & writeValid_9; // @[Library.scala 115:22]
- wire write_value_42_10 = 5'ha == io_readAddr_7_addr & writeValid_10; // @[Library.scala 115:22]
- wire write_value_42_11 = 5'hb == io_readAddr_7_addr & writeValid_11; // @[Library.scala 115:22]
- wire write_value_42_12 = 5'hc == io_readAddr_7_addr & writeValid_12; // @[Library.scala 115:22]
- wire write_value_42_13 = 5'hd == io_readAddr_7_addr & writeValid_13; // @[Library.scala 115:22]
- wire write_value_42_14 = 5'he == io_readAddr_7_addr & writeValid_14; // @[Library.scala 115:22]
- wire write_value_42_15 = 5'hf == io_readAddr_7_addr & writeValid_15; // @[Library.scala 115:22]
- wire write_value_42_16 = 5'h10 == io_readAddr_7_addr & writeValid_16; // @[Library.scala 115:22]
- wire write_value_42_17 = 5'h11 == io_readAddr_7_addr & writeValid_17; // @[Library.scala 115:22]
- wire write_value_42_18 = 5'h12 == io_readAddr_7_addr & writeValid_18; // @[Library.scala 115:22]
- wire write_value_42_19 = 5'h13 == io_readAddr_7_addr & writeValid_19; // @[Library.scala 115:22]
- wire write_value_42_20 = 5'h14 == io_readAddr_7_addr & writeValid_20; // @[Library.scala 115:22]
- wire write_value_42_21 = 5'h15 == io_readAddr_7_addr & writeValid_21; // @[Library.scala 115:22]
- wire write_value_42_22 = 5'h16 == io_readAddr_7_addr & writeValid_22; // @[Library.scala 115:22]
- wire write_value_42_23 = 5'h17 == io_readAddr_7_addr & writeValid_23; // @[Library.scala 115:22]
- wire write_value_42_24 = 5'h18 == io_readAddr_7_addr & writeValid_24; // @[Library.scala 115:22]
- wire write_value_42_25 = 5'h19 == io_readAddr_7_addr & writeValid_25; // @[Library.scala 115:22]
- wire write_value_42_26 = 5'h1a == io_readAddr_7_addr & writeValid_26; // @[Library.scala 115:22]
- wire write_value_42_27 = 5'h1b == io_readAddr_7_addr & writeValid_27; // @[Library.scala 115:22]
- wire write_value_42_28 = 5'h1c == io_readAddr_7_addr & writeValid_28; // @[Library.scala 115:22]
- wire write_value_42_29 = 5'h1d == io_readAddr_7_addr & writeValid_29; // @[Library.scala 115:22]
- wire write_value_42_30 = 5'h1e == io_readAddr_7_addr & writeValid_30; // @[Library.scala 115:22]
- wire write_value_42_31 = 5'h1f == io_readAddr_7_addr & writeValid_31; // @[Library.scala 115:22]
- wire write_value_43_0 = write_value_42_0 | write_value_42_1; // @[Library.scala 129:37]
- wire write_value_43_1 = write_value_42_2 | write_value_42_3; // @[Library.scala 129:37]
- wire write_value_43_2 = write_value_42_4 | write_value_42_5; // @[Library.scala 129:37]
- wire write_value_43_3 = write_value_42_6 | write_value_42_7; // @[Library.scala 129:37]
- wire write_value_43_4 = write_value_42_8 | write_value_42_9; // @[Library.scala 129:37]
- wire write_value_43_5 = write_value_42_10 | write_value_42_11; // @[Library.scala 129:37]
- wire write_value_43_6 = write_value_42_12 | write_value_42_13; // @[Library.scala 129:37]
- wire write_value_43_7 = write_value_42_14 | write_value_42_15; // @[Library.scala 129:37]
- wire write_value_43_8 = write_value_42_16 | write_value_42_17; // @[Library.scala 129:37]
- wire write_value_43_9 = write_value_42_18 | write_value_42_19; // @[Library.scala 129:37]
- wire write_value_43_10 = write_value_42_20 | write_value_42_21; // @[Library.scala 129:37]
- wire write_value_43_11 = write_value_42_22 | write_value_42_23; // @[Library.scala 129:37]
- wire write_value_43_12 = write_value_42_24 | write_value_42_25; // @[Library.scala 129:37]
- wire write_value_43_13 = write_value_42_26 | write_value_42_27; // @[Library.scala 129:37]
- wire write_value_43_14 = write_value_42_28 | write_value_42_29; // @[Library.scala 129:37]
- wire write_value_43_15 = write_value_42_30 | write_value_42_31; // @[Library.scala 129:37]
- wire write_value_44_0 = write_value_43_0 | write_value_43_1; // @[Library.scala 129:37]
- wire write_value_44_1 = write_value_43_2 | write_value_43_3; // @[Library.scala 129:37]
- wire write_value_44_2 = write_value_43_4 | write_value_43_5; // @[Library.scala 129:37]
- wire write_value_44_3 = write_value_43_6 | write_value_43_7; // @[Library.scala 129:37]
- wire write_value_44_4 = write_value_43_8 | write_value_43_9; // @[Library.scala 129:37]
- wire write_value_44_5 = write_value_43_10 | write_value_43_11; // @[Library.scala 129:37]
- wire write_value_44_6 = write_value_43_12 | write_value_43_13; // @[Library.scala 129:37]
- wire write_value_44_7 = write_value_43_14 | write_value_43_15; // @[Library.scala 129:37]
- wire write_value_45_0 = write_value_44_0 | write_value_44_1; // @[Library.scala 129:37]
- wire write_value_45_1 = write_value_44_2 | write_value_44_3; // @[Library.scala 129:37]
- wire write_value_45_2 = write_value_44_4 | write_value_44_5; // @[Library.scala 129:37]
- wire write_value_45_3 = write_value_44_6 | write_value_44_7; // @[Library.scala 129:37]
- wire write_value_46_0 = write_value_45_0 | write_value_45_1; // @[Library.scala 129:37]
- wire write_value_46_1 = write_value_45_2 | write_value_45_3; // @[Library.scala 129:37]
- wire write_value_47_0 = write_value_46_0 | write_value_46_1; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value__1 = 5'h1 == io_readAddr_7_addr ? regfile_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__2 = 5'h2 == io_readAddr_7_addr ? regfile_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__3 = 5'h3 == io_readAddr_7_addr ? regfile_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__4 = 5'h4 == io_readAddr_7_addr ? regfile_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__5 = 5'h5 == io_readAddr_7_addr ? regfile_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__6 = 5'h6 == io_readAddr_7_addr ? regfile_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__7 = 5'h7 == io_readAddr_7_addr ? regfile_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__8 = 5'h8 == io_readAddr_7_addr ? regfile_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__9 = 5'h9 == io_readAddr_7_addr ? regfile_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__10 = 5'ha == io_readAddr_7_addr ? regfile_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__11 = 5'hb == io_readAddr_7_addr ? regfile_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__12 = 5'hc == io_readAddr_7_addr ? regfile_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__13 = 5'hd == io_readAddr_7_addr ? regfile_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__14 = 5'he == io_readAddr_7_addr ? regfile_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__15 = 5'hf == io_readAddr_7_addr ? regfile_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__16 = 5'h10 == io_readAddr_7_addr ? regfile_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__17 = 5'h11 == io_readAddr_7_addr ? regfile_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__18 = 5'h12 == io_readAddr_7_addr ? regfile_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__19 = 5'h13 == io_readAddr_7_addr ? regfile_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__20 = 5'h14 == io_readAddr_7_addr ? regfile_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__21 = 5'h15 == io_readAddr_7_addr ? regfile_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__22 = 5'h16 == io_readAddr_7_addr ? regfile_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__23 = 5'h17 == io_readAddr_7_addr ? regfile_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__24 = 5'h18 == io_readAddr_7_addr ? regfile_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__25 = 5'h19 == io_readAddr_7_addr ? regfile_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__26 = 5'h1a == io_readAddr_7_addr ? regfile_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__27 = 5'h1b == io_readAddr_7_addr ? regfile_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__28 = 5'h1c == io_readAddr_7_addr ? regfile_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__29 = 5'h1d == io_readAddr_7_addr ? regfile_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__30 = 5'h1e == io_readAddr_7_addr ? regfile_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value__31 = 5'h1f == io_readAddr_7_addr ? regfile_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] rdata_7_value_1_1 = rdata_7_value__2 | rdata_7_value__3; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_2 = rdata_7_value__4 | rdata_7_value__5; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_3 = rdata_7_value__6 | rdata_7_value__7; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_4 = rdata_7_value__8 | rdata_7_value__9; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_5 = rdata_7_value__10 | rdata_7_value__11; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_6 = rdata_7_value__12 | rdata_7_value__13; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_7 = rdata_7_value__14 | rdata_7_value__15; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_8 = rdata_7_value__16 | rdata_7_value__17; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_9 = rdata_7_value__18 | rdata_7_value__19; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_10 = rdata_7_value__20 | rdata_7_value__21; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_11 = rdata_7_value__22 | rdata_7_value__23; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_12 = rdata_7_value__24 | rdata_7_value__25; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_13 = rdata_7_value__26 | rdata_7_value__27; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_14 = rdata_7_value__28 | rdata_7_value__29; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_1_15 = rdata_7_value__30 | rdata_7_value__31; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_2_0 = rdata_7_value__1 | rdata_7_value_1_1; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_2_1 = rdata_7_value_1_2 | rdata_7_value_1_3; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_2_2 = rdata_7_value_1_4 | rdata_7_value_1_5; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_2_3 = rdata_7_value_1_6 | rdata_7_value_1_7; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_2_4 = rdata_7_value_1_8 | rdata_7_value_1_9; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_2_5 = rdata_7_value_1_10 | rdata_7_value_1_11; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_2_6 = rdata_7_value_1_12 | rdata_7_value_1_13; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_2_7 = rdata_7_value_1_14 | rdata_7_value_1_15; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_3_0 = rdata_7_value_2_0 | rdata_7_value_2_1; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_3_1 = rdata_7_value_2_2 | rdata_7_value_2_3; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_3_2 = rdata_7_value_2_4 | rdata_7_value_2_5; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_3_3 = rdata_7_value_2_6 | rdata_7_value_2_7; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_4_0 = rdata_7_value_3_0 | rdata_7_value_3_1; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_4_1 = rdata_7_value_3_2 | rdata_7_value_3_3; // @[Library.scala 129:37]
- wire [31:0] rdata_7_value_5_0 = rdata_7_value_4_0 | rdata_7_value_4_1; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value__1 = 5'h1 == io_readAddr_7_addr ? data : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__2 = 5'h2 == io_readAddr_7_addr ? data_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__3 = 5'h3 == io_readAddr_7_addr ? data_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__4 = 5'h4 == io_readAddr_7_addr ? data_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__5 = 5'h5 == io_readAddr_7_addr ? data_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__6 = 5'h6 == io_readAddr_7_addr ? data_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__7 = 5'h7 == io_readAddr_7_addr ? data_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__8 = 5'h8 == io_readAddr_7_addr ? data_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__9 = 5'h9 == io_readAddr_7_addr ? data_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__10 = 5'ha == io_readAddr_7_addr ? data_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__11 = 5'hb == io_readAddr_7_addr ? data_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__12 = 5'hc == io_readAddr_7_addr ? data_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__13 = 5'hd == io_readAddr_7_addr ? data_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__14 = 5'he == io_readAddr_7_addr ? data_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__15 = 5'hf == io_readAddr_7_addr ? data_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__16 = 5'h10 == io_readAddr_7_addr ? data_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__17 = 5'h11 == io_readAddr_7_addr ? data_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__18 = 5'h12 == io_readAddr_7_addr ? data_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__19 = 5'h13 == io_readAddr_7_addr ? data_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__20 = 5'h14 == io_readAddr_7_addr ? data_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__21 = 5'h15 == io_readAddr_7_addr ? data_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__22 = 5'h16 == io_readAddr_7_addr ? data_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__23 = 5'h17 == io_readAddr_7_addr ? data_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__24 = 5'h18 == io_readAddr_7_addr ? data_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__25 = 5'h19 == io_readAddr_7_addr ? data_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__26 = 5'h1a == io_readAddr_7_addr ? data_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__27 = 5'h1b == io_readAddr_7_addr ? data_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__28 = 5'h1c == io_readAddr_7_addr ? data_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__29 = 5'h1d == io_readAddr_7_addr ? data_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__30 = 5'h1e == io_readAddr_7_addr ? data_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value__31 = 5'h1f == io_readAddr_7_addr ? data_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] wdata_7_value_1_1 = wdata_7_value__2 | wdata_7_value__3; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_2 = wdata_7_value__4 | wdata_7_value__5; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_3 = wdata_7_value__6 | wdata_7_value__7; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_4 = wdata_7_value__8 | wdata_7_value__9; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_5 = wdata_7_value__10 | wdata_7_value__11; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_6 = wdata_7_value__12 | wdata_7_value__13; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_7 = wdata_7_value__14 | wdata_7_value__15; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_8 = wdata_7_value__16 | wdata_7_value__17; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_9 = wdata_7_value__18 | wdata_7_value__19; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_10 = wdata_7_value__20 | wdata_7_value__21; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_11 = wdata_7_value__22 | wdata_7_value__23; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_12 = wdata_7_value__24 | wdata_7_value__25; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_13 = wdata_7_value__26 | wdata_7_value__27; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_14 = wdata_7_value__28 | wdata_7_value__29; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_1_15 = wdata_7_value__30 | wdata_7_value__31; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_2_0 = wdata_7_value__1 | wdata_7_value_1_1; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_2_1 = wdata_7_value_1_2 | wdata_7_value_1_3; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_2_2 = wdata_7_value_1_4 | wdata_7_value_1_5; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_2_3 = wdata_7_value_1_6 | wdata_7_value_1_7; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_2_4 = wdata_7_value_1_8 | wdata_7_value_1_9; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_2_5 = wdata_7_value_1_10 | wdata_7_value_1_11; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_2_6 = wdata_7_value_1_12 | wdata_7_value_1_13; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_2_7 = wdata_7_value_1_14 | wdata_7_value_1_15; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_3_0 = wdata_7_value_2_0 | wdata_7_value_2_1; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_3_1 = wdata_7_value_2_2 | wdata_7_value_2_3; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_3_2 = wdata_7_value_2_4 | wdata_7_value_2_5; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_3_3 = wdata_7_value_2_6 | wdata_7_value_2_7; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_4_0 = wdata_7_value_3_0 | wdata_7_value_3_1; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_4_1 = wdata_7_value_3_2 | wdata_7_value_3_3; // @[Library.scala 129:37]
- wire [31:0] wdata_7_value_5_0 = wdata_7_value_4_0 | wdata_7_value_4_1; // @[Library.scala 129:37]
- wire [31:0] rwdata_7 = write_value_47_0 ? wdata_7_value_5_0 : rdata_7_value_5_0; // @[Regfile.scala 198:21]
- wire nxtReadDataReady = io_readAddr_0_valid | io_readSet_0_valid; // @[Regfile.scala 205:49]
- wire nxtReadDataReady_1 = io_readAddr_1_valid | io_readSet_1_valid; // @[Regfile.scala 205:49]
- wire nxtReadDataReady_2 = io_readAddr_2_valid | io_readSet_2_valid; // @[Regfile.scala 205:49]
- wire nxtReadDataReady_3 = io_readAddr_3_valid | io_readSet_3_valid; // @[Regfile.scala 205:49]
- wire nxtReadDataReady_4 = io_readAddr_4_valid | io_readSet_4_valid; // @[Regfile.scala 205:49]
- wire nxtReadDataReady_5 = io_readAddr_5_valid | io_readSet_5_valid; // @[Regfile.scala 205:49]
- wire nxtReadDataReady_6 = io_readAddr_6_valid | io_readSet_6_valid; // @[Regfile.scala 205:49]
- wire nxtReadDataReady_7 = io_readAddr_7_valid | io_readSet_7_valid; // @[Regfile.scala 205:49]
- wire [31:0] _busAddr_0_T_1 = rdata_0_value_5_0 + io_busAddr_0_immed; // @[Regfile.scala 223:57]
- wire [31:0] _busAddr_0_T_2 = io_busAddr_0_immen ? _busAddr_0_T_1 : rdata_0_value_5_0; // @[Regfile.scala 223:22]
- wire [31:0] _busAddr_1_T_1 = rdata_2_value_5_0 + io_busAddr_1_immed; // @[Regfile.scala 223:57]
- wire [31:0] _busAddr_2_T_1 = rdata_4_value_5_0 + io_busAddr_2_immed; // @[Regfile.scala 223:57]
- wire [31:0] _busAddr_3_T_1 = rdata_6_value_5_0 + io_busAddr_3_immed; // @[Regfile.scala 223:57]
- reg write_fail; // @[Regfile.scala 253:31]
- wire _write_fail_T_1 = io_writeData_0_addr == io_writeData_1_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_2 = io_writeData_0_valid & io_writeData_1_valid & _write_fail_T_1; // @[Regfile.scala 254:68]
- wire _write_fail_T_3 = io_writeData_0_addr != 5'h0; // @[Regfile.scala 256:42]
- reg write_fail_1; // @[Regfile.scala 253:31]
- wire _write_fail_T_6 = io_writeData_0_addr == io_writeData_2_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_7 = io_writeData_0_valid & io_writeData_2_valid & _write_fail_T_6; // @[Regfile.scala 254:68]
- reg write_fail_2; // @[Regfile.scala 253:31]
- wire _write_fail_T_11 = io_writeData_0_addr == io_writeData_3_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_12 = io_writeData_0_valid & io_writeData_3_valid & _write_fail_T_11; // @[Regfile.scala 254:68]
- reg write_fail_3; // @[Regfile.scala 253:31]
- wire _write_fail_T_16 = io_writeData_0_addr == io_writeData_4_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_17 = io_writeData_0_valid & io_writeData_4_valid & _write_fail_T_16; // @[Regfile.scala 254:68]
- reg write_fail_4; // @[Regfile.scala 253:31]
- wire _write_fail_T_21 = io_writeData_0_addr == io_writeData_5_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_22 = io_writeData_0_valid & io_writeData_5_valid & _write_fail_T_21; // @[Regfile.scala 254:68]
- reg write_fail_5; // @[Regfile.scala 253:31]
- wire _write_fail_T_26 = io_writeData_1_addr == io_writeData_2_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_27 = io_writeData_1_valid & io_writeData_2_valid & _write_fail_T_26; // @[Regfile.scala 254:68]
- wire _write_fail_T_28 = io_writeData_1_addr != 5'h0; // @[Regfile.scala 256:42]
- reg write_fail_6; // @[Regfile.scala 253:31]
- wire _write_fail_T_31 = io_writeData_1_addr == io_writeData_3_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_32 = io_writeData_1_valid & io_writeData_3_valid & _write_fail_T_31; // @[Regfile.scala 254:68]
- reg write_fail_7; // @[Regfile.scala 253:31]
- wire _write_fail_T_36 = io_writeData_1_addr == io_writeData_4_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_37 = io_writeData_1_valid & io_writeData_4_valid & _write_fail_T_36; // @[Regfile.scala 254:68]
- reg write_fail_8; // @[Regfile.scala 253:31]
- wire _write_fail_T_41 = io_writeData_1_addr == io_writeData_5_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_42 = io_writeData_1_valid & io_writeData_5_valid & _write_fail_T_41; // @[Regfile.scala 254:68]
- reg write_fail_9; // @[Regfile.scala 253:31]
- wire _write_fail_T_46 = io_writeData_2_addr == io_writeData_3_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_47 = io_writeData_2_valid & io_writeData_3_valid & _write_fail_T_46; // @[Regfile.scala 254:68]
- wire _write_fail_T_48 = io_writeData_2_addr != 5'h0; // @[Regfile.scala 256:42]
- reg write_fail_10; // @[Regfile.scala 253:31]
- wire _write_fail_T_51 = io_writeData_2_addr == io_writeData_4_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_52 = io_writeData_2_valid & io_writeData_4_valid & _write_fail_T_51; // @[Regfile.scala 254:68]
- reg write_fail_11; // @[Regfile.scala 253:31]
- wire _write_fail_T_56 = io_writeData_2_addr == io_writeData_5_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_57 = io_writeData_2_valid & io_writeData_5_valid & _write_fail_T_56; // @[Regfile.scala 254:68]
- reg write_fail_12; // @[Regfile.scala 253:31]
- wire _write_fail_T_61 = io_writeData_3_addr == io_writeData_4_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_62 = io_writeData_3_valid & io_writeData_4_valid & _write_fail_T_61; // @[Regfile.scala 254:68]
- wire _write_fail_T_63 = io_writeData_3_addr != 5'h0; // @[Regfile.scala 256:42]
- reg write_fail_13; // @[Regfile.scala 253:31]
- wire _write_fail_T_66 = io_writeData_3_addr == io_writeData_5_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_67 = io_writeData_3_valid & io_writeData_5_valid & _write_fail_T_66; // @[Regfile.scala 254:68]
- reg write_fail_14; // @[Regfile.scala 253:31]
- wire _write_fail_T_71 = io_writeData_4_addr == io_writeData_5_addr; // @[Regfile.scala 255:42]
- wire _write_fail_T_72 = io_writeData_4_valid & io_writeData_5_valid & _write_fail_T_71; // @[Regfile.scala 254:68]
- wire _write_fail_T_73 = io_writeData_4_addr != 5'h0; // @[Regfile.scala 256:42]
- reg scoreboard_error; // @[Regfile.scala 261:33]
- wire [31:0] _scoreboard_error_T = scoreboard & scoreboard_clr; // @[Regfile.scala 262:35]
- assign io_target_0_data = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 222:22]
- assign io_target_1_data = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 222:22]
- assign io_target_2_data = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 222:22]
- assign io_target_3_data = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 222:22]
- assign io_linkPort_valid = ~scoreboard[1]; // @[Regfile.scala 240:24]
- assign io_linkPort_value = regfile_1; // @[Regfile.scala 241:21]
- assign io_busPort_addr_0 = io_busAddr_0_bypass ? rwdata_0 : _busAddr_0_T_2; // @[Regfile.scala 222:22]
- assign io_busPort_addr_1 = io_busAddr_1_bypass ? rwdata_2 : _busAddr_1_T_1; // @[Regfile.scala 222:22]
- assign io_busPort_addr_2 = io_busAddr_2_bypass ? rwdata_4 : _busAddr_2_T_1; // @[Regfile.scala 222:22]
- assign io_busPort_addr_3 = io_busAddr_3_bypass ? rwdata_6 : _busAddr_3_T_1; // @[Regfile.scala 222:22]
- assign io_busPort_data_0 = io_readSet_1_valid ? io_readSet_1_value : rwdata_1; // @[Regfile.scala 209:30]
- assign io_busPort_data_1 = io_readSet_3_valid ? io_readSet_3_value : rwdata_3; // @[Regfile.scala 209:30]
- assign io_busPort_data_2 = io_readSet_5_valid ? io_readSet_5_value : rwdata_5; // @[Regfile.scala 209:30]
- assign io_busPort_data_3 = io_readSet_7_valid ? io_readSet_7_value : rwdata_7; // @[Regfile.scala 209:30]
- assign io_readData_0_valid = readDataReady_0; // @[Regfile.scala 143:26]
- assign io_readData_0_data = readDataBits_0; // @[Regfile.scala 144:26]
- assign io_readData_1_valid = readDataReady_1; // @[Regfile.scala 143:26]
- assign io_readData_1_data = readDataBits_1; // @[Regfile.scala 144:26]
- assign io_readData_2_valid = readDataReady_2; // @[Regfile.scala 143:26]
- assign io_readData_2_data = readDataBits_2; // @[Regfile.scala 144:26]
- assign io_readData_3_valid = readDataReady_3; // @[Regfile.scala 143:26]
- assign io_readData_3_data = readDataBits_3; // @[Regfile.scala 144:26]
- assign io_readData_4_valid = readDataReady_4; // @[Regfile.scala 143:26]
- assign io_readData_4_data = readDataBits_4; // @[Regfile.scala 144:26]
- assign io_readData_5_valid = readDataReady_5; // @[Regfile.scala 143:26]
- assign io_readData_5_data = readDataBits_5; // @[Regfile.scala 144:26]
- assign io_readData_6_valid = readDataReady_6; // @[Regfile.scala 143:26]
- assign io_readData_6_data = readDataBits_6; // @[Regfile.scala 144:26]
- assign io_readData_7_valid = readDataReady_7; // @[Regfile.scala 143:26]
- assign io_readData_7_data = readDataBits_7; // @[Regfile.scala 144:26]
- assign io_scoreboard_regd = scoreboard; // @[Regfile.scala 132:22]
- assign io_scoreboard_comb = scoreboard & _nxtScoreboard_T; // @[Regfile.scala 133:36]
- always @(posedge clock) begin
- if (writeValid_1) begin // @[Regfile.scala 182:26]
- regfile_1 <= data; // @[Regfile.scala 183:18]
- end
- if (writeValid_2) begin // @[Regfile.scala 182:26]
- regfile_2 <= data_1; // @[Regfile.scala 183:18]
- end
- if (writeValid_3) begin // @[Regfile.scala 182:26]
- regfile_3 <= data_2; // @[Regfile.scala 183:18]
- end
- if (writeValid_4) begin // @[Regfile.scala 182:26]
- regfile_4 <= data_3; // @[Regfile.scala 183:18]
- end
- if (writeValid_5) begin // @[Regfile.scala 182:26]
- regfile_5 <= data_4; // @[Regfile.scala 183:18]
- end
- if (writeValid_6) begin // @[Regfile.scala 182:26]
- regfile_6 <= data_5; // @[Regfile.scala 183:18]
- end
- if (writeValid_7) begin // @[Regfile.scala 182:26]
- regfile_7 <= data_6; // @[Regfile.scala 183:18]
- end
- if (writeValid_8) begin // @[Regfile.scala 182:26]
- regfile_8 <= data_7; // @[Regfile.scala 183:18]
- end
- if (writeValid_9) begin // @[Regfile.scala 182:26]
- regfile_9 <= data_8; // @[Regfile.scala 183:18]
- end
- if (writeValid_10) begin // @[Regfile.scala 182:26]
- regfile_10 <= data_9; // @[Regfile.scala 183:18]
- end
- if (writeValid_11) begin // @[Regfile.scala 182:26]
- regfile_11 <= data_10; // @[Regfile.scala 183:18]
- end
- if (writeValid_12) begin // @[Regfile.scala 182:26]
- regfile_12 <= data_11; // @[Regfile.scala 183:18]
- end
- if (writeValid_13) begin // @[Regfile.scala 182:26]
- regfile_13 <= data_12; // @[Regfile.scala 183:18]
- end
- if (writeValid_14) begin // @[Regfile.scala 182:26]
- regfile_14 <= data_13; // @[Regfile.scala 183:18]
- end
- if (writeValid_15) begin // @[Regfile.scala 182:26]
- regfile_15 <= data_14; // @[Regfile.scala 183:18]
- end
- if (writeValid_16) begin // @[Regfile.scala 182:26]
- regfile_16 <= data_15; // @[Regfile.scala 183:18]
- end
- if (writeValid_17) begin // @[Regfile.scala 182:26]
- regfile_17 <= data_16; // @[Regfile.scala 183:18]
- end
- if (writeValid_18) begin // @[Regfile.scala 182:26]
- regfile_18 <= data_17; // @[Regfile.scala 183:18]
- end
- if (writeValid_19) begin // @[Regfile.scala 182:26]
- regfile_19 <= data_18; // @[Regfile.scala 183:18]
- end
- if (writeValid_20) begin // @[Regfile.scala 182:26]
- regfile_20 <= data_19; // @[Regfile.scala 183:18]
- end
- if (writeValid_21) begin // @[Regfile.scala 182:26]
- regfile_21 <= data_20; // @[Regfile.scala 183:18]
- end
- if (writeValid_22) begin // @[Regfile.scala 182:26]
- regfile_22 <= data_21; // @[Regfile.scala 183:18]
- end
- if (writeValid_23) begin // @[Regfile.scala 182:26]
- regfile_23 <= data_22; // @[Regfile.scala 183:18]
- end
- if (writeValid_24) begin // @[Regfile.scala 182:26]
- regfile_24 <= data_23; // @[Regfile.scala 183:18]
- end
- if (writeValid_25) begin // @[Regfile.scala 182:26]
- regfile_25 <= data_24; // @[Regfile.scala 183:18]
- end
- if (writeValid_26) begin // @[Regfile.scala 182:26]
- regfile_26 <= data_25; // @[Regfile.scala 183:18]
- end
- if (writeValid_27) begin // @[Regfile.scala 182:26]
- regfile_27 <= data_26; // @[Regfile.scala 183:18]
- end
- if (writeValid_28) begin // @[Regfile.scala 182:26]
- regfile_28 <= data_27; // @[Regfile.scala 183:18]
- end
- if (writeValid_29) begin // @[Regfile.scala 182:26]
- regfile_29 <= data_28; // @[Regfile.scala 183:18]
- end
- if (writeValid_30) begin // @[Regfile.scala 182:26]
- regfile_30 <= data_29; // @[Regfile.scala 183:18]
- end
- if (writeValid_31) begin // @[Regfile.scala 182:26]
- regfile_31 <= data_30; // @[Regfile.scala 183:18]
- end
- if (nxtReadDataReady) begin // @[Regfile.scala 211:29]
- if (io_readSet_0_valid) begin // @[Regfile.scala 209:30]
- readDataBits_0 <= io_readSet_0_value;
- end else if (write_value_5_0) begin // @[Regfile.scala 198:21]
- readDataBits_0 <= wdata_0_value_5_0;
- end else begin
- readDataBits_0 <= rdata_0_value_5_0;
- end
- end
- if (nxtReadDataReady_1) begin // @[Regfile.scala 211:29]
- if (io_readSet_1_valid) begin // @[Regfile.scala 209:30]
- readDataBits_1 <= io_readSet_1_value;
- end else if (write_value_11_0) begin // @[Regfile.scala 198:21]
- readDataBits_1 <= wdata_1_value_5_0;
- end else begin
- readDataBits_1 <= rdata_1_value_5_0;
- end
- end
- if (nxtReadDataReady_2) begin // @[Regfile.scala 211:29]
- if (io_readSet_2_valid) begin // @[Regfile.scala 209:30]
- readDataBits_2 <= io_readSet_2_value;
- end else if (write_value_17_0) begin // @[Regfile.scala 198:21]
- readDataBits_2 <= wdata_2_value_5_0;
- end else begin
- readDataBits_2 <= rdata_2_value_5_0;
- end
- end
- if (nxtReadDataReady_3) begin // @[Regfile.scala 211:29]
- if (io_readSet_3_valid) begin // @[Regfile.scala 209:30]
- readDataBits_3 <= io_readSet_3_value;
- end else if (write_value_23_0) begin // @[Regfile.scala 198:21]
- readDataBits_3 <= wdata_3_value_5_0;
- end else begin
- readDataBits_3 <= rdata_3_value_5_0;
- end
- end
- if (nxtReadDataReady_4) begin // @[Regfile.scala 211:29]
- if (io_readSet_4_valid) begin // @[Regfile.scala 209:30]
- readDataBits_4 <= io_readSet_4_value;
- end else if (write_value_29_0) begin // @[Regfile.scala 198:21]
- readDataBits_4 <= wdata_4_value_5_0;
- end else begin
- readDataBits_4 <= rdata_4_value_5_0;
- end
- end
- if (nxtReadDataReady_5) begin // @[Regfile.scala 211:29]
- if (io_readSet_5_valid) begin // @[Regfile.scala 209:30]
- readDataBits_5 <= io_readSet_5_value;
- end else if (write_value_35_0) begin // @[Regfile.scala 198:21]
- readDataBits_5 <= wdata_5_value_5_0;
- end else begin
- readDataBits_5 <= rdata_5_value_5_0;
- end
- end
- if (nxtReadDataReady_6) begin // @[Regfile.scala 211:29]
- if (io_readSet_6_valid) begin // @[Regfile.scala 209:30]
- readDataBits_6 <= io_readSet_6_value;
- end else if (write_value_41_0) begin // @[Regfile.scala 198:21]
- readDataBits_6 <= wdata_6_value_5_0;
- end else begin
- readDataBits_6 <= rdata_6_value_5_0;
- end
- end
- if (nxtReadDataReady_7) begin // @[Regfile.scala 211:29]
- if (io_readSet_7_valid) begin // @[Regfile.scala 209:30]
- readDataBits_7 <= io_readSet_7_value;
- end else if (write_value_47_0) begin // @[Regfile.scala 198:21]
- readDataBits_7 <= wdata_7_value_5_0;
- end else begin
- readDataBits_7 <= rdata_7_value_5_0;
- end
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_17 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_17 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_37 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_37 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_57 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_57 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_77 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_77 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_97 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_97 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_117 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_117 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_137 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_137 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_157 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_157 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_177 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_177 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_197 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_197 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_217 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_217 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_237 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_237 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_257 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_257 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_277 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_277 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_297 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_297 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_317 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_317 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_337 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_337 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_357 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_357 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_377 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_377 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_397 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_397 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_417 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_417 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_437 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_437 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_457 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_457 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_477 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_477 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_497 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_497 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_517 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_517 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_537 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_537 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_557 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_557 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_577 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_577 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_597 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_597 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_617 <= 3'h1)) begin
- $fatal; // @[Regfile.scala 178:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_617 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:178 assert(PopCount(valid) <= 1.U)\n"); // @[Regfile.scala 178:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_1)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_2)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_2)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_3)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_3)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_4)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_5)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_5)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_6)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_6)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_7)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_7)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_8)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_8)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_9)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_9)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_10)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_10)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_11)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_11)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_12)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_12)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_13)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_13)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_14)) begin
- $fatal; // @[Regfile.scala 257:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~write_fail_14)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:257 assert(!write_fail)\n"); // @[Regfile.scala 257:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_21 & ~(~scoreboard_error)) begin
- $fatal; // @[Regfile.scala 263:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_21 & ~(~scoreboard_error)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Regfile.scala:263 assert(!scoreboard_error)\n"); // @[Regfile.scala 263:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 127:59]
- scoreboard <= 32'h0; // @[Regfile.scala 129:16]
- end else if (scoreboard_set != 32'h0 | scoreboard_clr != 32'h0) begin // @[Regfile.scala 106:27]
- scoreboard <= _scoreboard_T_1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 205:49]
- readDataReady_0 <= 1'h0;
- end else begin
- readDataReady_0 <= io_readAddr_0_valid | io_readSet_0_valid;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 205:49]
- readDataReady_1 <= 1'h0;
- end else begin
- readDataReady_1 <= io_readAddr_1_valid | io_readSet_1_valid;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 205:49]
- readDataReady_2 <= 1'h0;
- end else begin
- readDataReady_2 <= io_readAddr_2_valid | io_readSet_2_valid;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 205:49]
- readDataReady_3 <= 1'h0;
- end else begin
- readDataReady_3 <= io_readAddr_3_valid | io_readSet_3_valid;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 205:49]
- readDataReady_4 <= 1'h0;
- end else begin
- readDataReady_4 <= io_readAddr_4_valid | io_readSet_4_valid;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 205:49]
- readDataReady_5 <= 1'h0;
- end else begin
- readDataReady_5 <= io_readAddr_5_valid | io_readSet_5_valid;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 205:49]
- readDataReady_6 <= 1'h0;
- end else begin
- readDataReady_6 <= io_readAddr_6_valid | io_readSet_6_valid;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 205:49]
- readDataReady_7 <= 1'h0;
- end else begin
- readDataReady_7 <= io_readAddr_7_valid | io_readSet_7_valid;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail <= 1'h0;
- end else begin
- write_fail <= _write_fail_T_2 & _write_fail_T_3;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_1 <= 1'h0;
- end else begin
- write_fail_1 <= _write_fail_T_7 & _write_fail_T_3;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_2 <= 1'h0;
- end else begin
- write_fail_2 <= _write_fail_T_12 & _write_fail_T_3;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_3 <= 1'h0;
- end else begin
- write_fail_3 <= _write_fail_T_17 & _write_fail_T_3;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_4 <= 1'h0;
- end else begin
- write_fail_4 <= _write_fail_T_22 & _write_fail_T_3;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_5 <= 1'h0;
- end else begin
- write_fail_5 <= _write_fail_T_27 & _write_fail_T_28;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_6 <= 1'h0;
- end else begin
- write_fail_6 <= _write_fail_T_32 & _write_fail_T_28;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_7 <= 1'h0;
- end else begin
- write_fail_7 <= _write_fail_T_37 & _write_fail_T_28;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_8 <= 1'h0;
- end else begin
- write_fail_8 <= _write_fail_T_42 & _write_fail_T_28;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_9 <= 1'h0;
- end else begin
- write_fail_9 <= _write_fail_T_47 & _write_fail_T_48;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_10 <= 1'h0;
- end else begin
- write_fail_10 <= _write_fail_T_52 & _write_fail_T_48;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_11 <= 1'h0;
- end else begin
- write_fail_11 <= _write_fail_T_57 & _write_fail_T_48;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_12 <= 1'h0;
- end else begin
- write_fail_12 <= _write_fail_T_62 & _write_fail_T_63;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_13 <= 1'h0;
- end else begin
- write_fail_13 <= _write_fail_T_67 & _write_fail_T_63;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 255:67]
- write_fail_14 <= 1'h0;
- end else begin
- write_fail_14 <= _write_fail_T_72 & _write_fail_T_73;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Regfile.scala 262:53]
- scoreboard_error <= 1'h0;
- end else begin
- scoreboard_error <= _scoreboard_error_T != scoreboard_clr;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- regfile_1 = _RAND_0[31:0];
- _RAND_1 = {1{`RANDOM}};
- regfile_2 = _RAND_1[31:0];
- _RAND_2 = {1{`RANDOM}};
- regfile_3 = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- regfile_4 = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- regfile_5 = _RAND_4[31:0];
- _RAND_5 = {1{`RANDOM}};
- regfile_6 = _RAND_5[31:0];
- _RAND_6 = {1{`RANDOM}};
- regfile_7 = _RAND_6[31:0];
- _RAND_7 = {1{`RANDOM}};
- regfile_8 = _RAND_7[31:0];
- _RAND_8 = {1{`RANDOM}};
- regfile_9 = _RAND_8[31:0];
- _RAND_9 = {1{`RANDOM}};
- regfile_10 = _RAND_9[31:0];
- _RAND_10 = {1{`RANDOM}};
- regfile_11 = _RAND_10[31:0];
- _RAND_11 = {1{`RANDOM}};
- regfile_12 = _RAND_11[31:0];
- _RAND_12 = {1{`RANDOM}};
- regfile_13 = _RAND_12[31:0];
- _RAND_13 = {1{`RANDOM}};
- regfile_14 = _RAND_13[31:0];
- _RAND_14 = {1{`RANDOM}};
- regfile_15 = _RAND_14[31:0];
- _RAND_15 = {1{`RANDOM}};
- regfile_16 = _RAND_15[31:0];
- _RAND_16 = {1{`RANDOM}};
- regfile_17 = _RAND_16[31:0];
- _RAND_17 = {1{`RANDOM}};
- regfile_18 = _RAND_17[31:0];
- _RAND_18 = {1{`RANDOM}};
- regfile_19 = _RAND_18[31:0];
- _RAND_19 = {1{`RANDOM}};
- regfile_20 = _RAND_19[31:0];
- _RAND_20 = {1{`RANDOM}};
- regfile_21 = _RAND_20[31:0];
- _RAND_21 = {1{`RANDOM}};
- regfile_22 = _RAND_21[31:0];
- _RAND_22 = {1{`RANDOM}};
- regfile_23 = _RAND_22[31:0];
- _RAND_23 = {1{`RANDOM}};
- regfile_24 = _RAND_23[31:0];
- _RAND_24 = {1{`RANDOM}};
- regfile_25 = _RAND_24[31:0];
- _RAND_25 = {1{`RANDOM}};
- regfile_26 = _RAND_25[31:0];
- _RAND_26 = {1{`RANDOM}};
- regfile_27 = _RAND_26[31:0];
- _RAND_27 = {1{`RANDOM}};
- regfile_28 = _RAND_27[31:0];
- _RAND_28 = {1{`RANDOM}};
- regfile_29 = _RAND_28[31:0];
- _RAND_29 = {1{`RANDOM}};
- regfile_30 = _RAND_29[31:0];
- _RAND_30 = {1{`RANDOM}};
- regfile_31 = _RAND_30[31:0];
- _RAND_31 = {1{`RANDOM}};
- scoreboard = _RAND_31[31:0];
- _RAND_32 = {1{`RANDOM}};
- readDataReady_0 = _RAND_32[0:0];
- _RAND_33 = {1{`RANDOM}};
- readDataReady_1 = _RAND_33[0:0];
- _RAND_34 = {1{`RANDOM}};
- readDataReady_2 = _RAND_34[0:0];
- _RAND_35 = {1{`RANDOM}};
- readDataReady_3 = _RAND_35[0:0];
- _RAND_36 = {1{`RANDOM}};
- readDataReady_4 = _RAND_36[0:0];
- _RAND_37 = {1{`RANDOM}};
- readDataReady_5 = _RAND_37[0:0];
- _RAND_38 = {1{`RANDOM}};
- readDataReady_6 = _RAND_38[0:0];
- _RAND_39 = {1{`RANDOM}};
- readDataReady_7 = _RAND_39[0:0];
- _RAND_40 = {1{`RANDOM}};
- readDataBits_0 = _RAND_40[31:0];
- _RAND_41 = {1{`RANDOM}};
- readDataBits_1 = _RAND_41[31:0];
- _RAND_42 = {1{`RANDOM}};
- readDataBits_2 = _RAND_42[31:0];
- _RAND_43 = {1{`RANDOM}};
- readDataBits_3 = _RAND_43[31:0];
- _RAND_44 = {1{`RANDOM}};
- readDataBits_4 = _RAND_44[31:0];
- _RAND_45 = {1{`RANDOM}};
- readDataBits_5 = _RAND_45[31:0];
- _RAND_46 = {1{`RANDOM}};
- readDataBits_6 = _RAND_46[31:0];
- _RAND_47 = {1{`RANDOM}};
- readDataBits_7 = _RAND_47[31:0];
- _RAND_48 = {1{`RANDOM}};
- write_fail = _RAND_48[0:0];
- _RAND_49 = {1{`RANDOM}};
- write_fail_1 = _RAND_49[0:0];
- _RAND_50 = {1{`RANDOM}};
- write_fail_2 = _RAND_50[0:0];
- _RAND_51 = {1{`RANDOM}};
- write_fail_3 = _RAND_51[0:0];
- _RAND_52 = {1{`RANDOM}};
- write_fail_4 = _RAND_52[0:0];
- _RAND_53 = {1{`RANDOM}};
- write_fail_5 = _RAND_53[0:0];
- _RAND_54 = {1{`RANDOM}};
- write_fail_6 = _RAND_54[0:0];
- _RAND_55 = {1{`RANDOM}};
- write_fail_7 = _RAND_55[0:0];
- _RAND_56 = {1{`RANDOM}};
- write_fail_8 = _RAND_56[0:0];
- _RAND_57 = {1{`RANDOM}};
- write_fail_9 = _RAND_57[0:0];
- _RAND_58 = {1{`RANDOM}};
- write_fail_10 = _RAND_58[0:0];
- _RAND_59 = {1{`RANDOM}};
- write_fail_11 = _RAND_59[0:0];
- _RAND_60 = {1{`RANDOM}};
- write_fail_12 = _RAND_60[0:0];
- _RAND_61 = {1{`RANDOM}};
- write_fail_13 = _RAND_61[0:0];
- _RAND_62 = {1{`RANDOM}};
- write_fail_14 = _RAND_62[0:0];
- _RAND_63 = {1{`RANDOM}};
- scoreboard_error = _RAND_63[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- scoreboard = 32'h0;
- end
- if (reset) begin
- readDataReady_0 = 1'h0;
- end
- if (reset) begin
- readDataReady_1 = 1'h0;
- end
- if (reset) begin
- readDataReady_2 = 1'h0;
- end
- if (reset) begin
- readDataReady_3 = 1'h0;
- end
- if (reset) begin
- readDataReady_4 = 1'h0;
- end
- if (reset) begin
- readDataReady_5 = 1'h0;
- end
- if (reset) begin
- readDataReady_6 = 1'h0;
- end
- if (reset) begin
- readDataReady_7 = 1'h0;
- end
- if (reset) begin
- write_fail = 1'h0;
- end
- if (reset) begin
- write_fail_1 = 1'h0;
- end
- if (reset) begin
- write_fail_2 = 1'h0;
- end
- if (reset) begin
- write_fail_3 = 1'h0;
- end
- if (reset) begin
- write_fail_4 = 1'h0;
- end
- if (reset) begin
- write_fail_5 = 1'h0;
- end
- if (reset) begin
- write_fail_6 = 1'h0;
- end
- if (reset) begin
- write_fail_7 = 1'h0;
- end
- if (reset) begin
- write_fail_8 = 1'h0;
- end
- if (reset) begin
- write_fail_9 = 1'h0;
- end
- if (reset) begin
- write_fail_10 = 1'h0;
- end
- if (reset) begin
- write_fail_11 = 1'h0;
- end
- if (reset) begin
- write_fail_12 = 1'h0;
- end
- if (reset) begin
- write_fail_13 = 1'h0;
- end
- if (reset) begin
- write_fail_14 = 1'h0;
- end
- if (reset) begin
- scoreboard_error = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Slice(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input [31:0] io_in_bits,
- input io_out_ready,
- output io_out_valid,
- output [31:0] io_out_bits
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
-`endif // RANDOMIZE_REG_INIT
- reg [1:0] ipos; // @[Slice.scala 38:21]
- reg [1:0] opos; // @[Slice.scala 39:21]
- reg [31:0] mem_0; // @[Slice.scala 41:16]
- reg [31:0] mem_1; // @[Slice.scala 41:16]
- wire empty = ipos == opos; // @[Slice.scala 43:20]
- wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 45:28]
- wire ovalid = io_out_valid & io_out_ready; // @[Slice.scala 46:29]
- wire [1:0] _ipos_T_1 = ipos + 2'h1; // @[Slice.scala 49:18]
- wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 53:18]
- wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 61:36]
- wire _io_in_ready_T = ~full; // @[Slice.scala 65:22]
- wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 72:18]
- wire _T_5 = ivalid & ovalid; // @[Slice.scala 73:18]
- wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 73:28]
- wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 72:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 78:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 77:39]
- assign io_in_ready = ~full; // @[Slice.scala 65:22]
- assign io_out_valid = ~empty; // @[Slice.scala 102:21]
- assign io_out_bits = mem_0; // @[Slice.scala 103:18]
- always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0 <= io_in_bits; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0 <= mem_1; // @[Slice.scala 69:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1 <= io_in_bits; // @[Slice.scala 79:14]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 48:17]
- ipos <= 2'h0; // @[Slice.scala 49:10]
- end else if (ivalid) begin // @[Slice.scala 38:21]
- ipos <= _ipos_T_1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 52:17]
- opos <= 2'h0; // @[Slice.scala 53:10]
- end else if (ovalid) begin // @[Slice.scala 39:21]
- opos <= _opos_T_1;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- ipos = _RAND_0[1:0];
- _RAND_1 = {1{`RANDOM}};
- opos = _RAND_1[1:0];
- _RAND_2 = {1{`RANDOM}};
- mem_0 = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- mem_1 = _RAND_3[31:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- ipos = 2'h0;
- end
- if (reset) begin
- opos = 2'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Fetch(
- input clock,
- input reset,
- input [31:0] io_csr_value_0,
- output io_ibus_valid,
- input io_ibus_ready,
- output [31:0] io_ibus_addr,
- input [255:0] io_ibus_rdata,
- output io_inst_lanes_0_valid,
- input io_inst_lanes_0_ready,
- output [31:0] io_inst_lanes_0_addr,
- output [31:0] io_inst_lanes_0_inst,
- output io_inst_lanes_0_brchFwd,
- output io_inst_lanes_1_valid,
- input io_inst_lanes_1_ready,
- output [31:0] io_inst_lanes_1_addr,
- output [31:0] io_inst_lanes_1_inst,
- output io_inst_lanes_1_brchFwd,
- output io_inst_lanes_2_valid,
- input io_inst_lanes_2_ready,
- output [31:0] io_inst_lanes_2_addr,
- output [31:0] io_inst_lanes_2_inst,
- output io_inst_lanes_2_brchFwd,
- output io_inst_lanes_3_valid,
- input io_inst_lanes_3_ready,
- output [31:0] io_inst_lanes_3_addr,
- output [31:0] io_inst_lanes_3_inst,
- output io_inst_lanes_3_brchFwd,
- input io_branch_0_valid,
- input [31:0] io_branch_0_value,
- input io_branch_1_valid,
- input [31:0] io_branch_1_value,
- input io_branch_2_valid,
- input [31:0] io_branch_2_value,
- input io_branch_3_valid,
- input [31:0] io_branch_3_value,
- input io_linkPort_valid,
- input [31:0] io_linkPort_value,
- input io_iflush_valid,
- output io_iflush_ready
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
- reg [31:0] _RAND_34;
- reg [31:0] _RAND_35;
- reg [255:0] _RAND_36;
- reg [255:0] _RAND_37;
- reg [255:0] _RAND_38;
- reg [255:0] _RAND_39;
- reg [255:0] _RAND_40;
- reg [255:0] _RAND_41;
- reg [255:0] _RAND_42;
- reg [255:0] _RAND_43;
- reg [255:0] _RAND_44;
- reg [255:0] _RAND_45;
- reg [255:0] _RAND_46;
- reg [255:0] _RAND_47;
- reg [255:0] _RAND_48;
- reg [255:0] _RAND_49;
- reg [255:0] _RAND_50;
- reg [255:0] _RAND_51;
- reg [255:0] _RAND_52;
- reg [255:0] _RAND_53;
- reg [255:0] _RAND_54;
- reg [255:0] _RAND_55;
- reg [255:0] _RAND_56;
- reg [255:0] _RAND_57;
- reg [255:0] _RAND_58;
- reg [255:0] _RAND_59;
- reg [255:0] _RAND_60;
- reg [255:0] _RAND_61;
- reg [255:0] _RAND_62;
- reg [255:0] _RAND_63;
- reg [255:0] _RAND_64;
- reg [255:0] _RAND_65;
- reg [255:0] _RAND_66;
- reg [255:0] _RAND_67;
- reg [31:0] _RAND_68;
- reg [31:0] _RAND_69;
- reg [31:0] _RAND_70;
- reg [31:0] _RAND_71;
- reg [31:0] _RAND_72;
- reg [31:0] _RAND_73;
- reg [31:0] _RAND_74;
- reg [31:0] _RAND_75;
- reg [31:0] _RAND_76;
- reg [31:0] _RAND_77;
- reg [31:0] _RAND_78;
- reg [31:0] _RAND_79;
-`endif // RANDOMIZE_REG_INIT
- wire aslice_clock; // @[Slice.scala 23:11]
- wire aslice_reset; // @[Slice.scala 23:11]
- wire aslice_io_in_ready; // @[Slice.scala 23:11]
- wire aslice_io_in_valid; // @[Slice.scala 23:11]
- wire [31:0] aslice_io_in_bits; // @[Slice.scala 23:11]
- wire aslice_io_out_ready; // @[Slice.scala 23:11]
- wire aslice_io_out_valid; // @[Slice.scala 23:11]
- wire [31:0] aslice_io_out_bits; // @[Slice.scala 23:11]
- reg [31:0] readAddr; // @[Fetch.scala 68:21]
- reg readDataEn; // @[Fetch.scala 69:27]
- wire readAddrEn = io_ibus_valid & io_ibus_ready; // @[Fetch.scala 71:34]
- wire _readDataEn_T = ~io_iflush_valid; // @[Fetch.scala 73:31]
- reg [31:0] l0valid; // @[Fetch.scala 99:24]
- reg [31:0] l0req; // @[Fetch.scala 100:24]
- reg [21:0] l0tag_0; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_1; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_2; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_3; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_4; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_5; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_6; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_7; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_8; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_9; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_10; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_11; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_12; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_13; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_14; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_15; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_16; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_17; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_18; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_19; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_20; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_21; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_22; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_23; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_24; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_25; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_26; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_27; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_28; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_29; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_30; // @[Fetch.scala 101:20]
- reg [21:0] l0tag_31; // @[Fetch.scala 101:20]
- reg [255:0] l0data_0; // @[Fetch.scala 102:20]
- reg [255:0] l0data_1; // @[Fetch.scala 102:20]
- reg [255:0] l0data_2; // @[Fetch.scala 102:20]
- reg [255:0] l0data_3; // @[Fetch.scala 102:20]
- reg [255:0] l0data_4; // @[Fetch.scala 102:20]
- reg [255:0] l0data_5; // @[Fetch.scala 102:20]
- reg [255:0] l0data_6; // @[Fetch.scala 102:20]
- reg [255:0] l0data_7; // @[Fetch.scala 102:20]
- reg [255:0] l0data_8; // @[Fetch.scala 102:20]
- reg [255:0] l0data_9; // @[Fetch.scala 102:20]
- reg [255:0] l0data_10; // @[Fetch.scala 102:20]
- reg [255:0] l0data_11; // @[Fetch.scala 102:20]
- reg [255:0] l0data_12; // @[Fetch.scala 102:20]
- reg [255:0] l0data_13; // @[Fetch.scala 102:20]
- reg [255:0] l0data_14; // @[Fetch.scala 102:20]
- reg [255:0] l0data_15; // @[Fetch.scala 102:20]
- reg [255:0] l0data_16; // @[Fetch.scala 102:20]
- reg [255:0] l0data_17; // @[Fetch.scala 102:20]
- reg [255:0] l0data_18; // @[Fetch.scala 102:20]
- reg [255:0] l0data_19; // @[Fetch.scala 102:20]
- reg [255:0] l0data_20; // @[Fetch.scala 102:20]
- reg [255:0] l0data_21; // @[Fetch.scala 102:20]
- reg [255:0] l0data_22; // @[Fetch.scala 102:20]
- reg [255:0] l0data_23; // @[Fetch.scala 102:20]
- reg [255:0] l0data_24; // @[Fetch.scala 102:20]
- reg [255:0] l0data_25; // @[Fetch.scala 102:20]
- reg [255:0] l0data_26; // @[Fetch.scala 102:20]
- reg [255:0] l0data_27; // @[Fetch.scala 102:20]
- reg [255:0] l0data_28; // @[Fetch.scala 102:20]
- reg [255:0] l0data_29; // @[Fetch.scala 102:20]
- reg [255:0] l0data_30; // @[Fetch.scala 102:20]
- reg [255:0] l0data_31; // @[Fetch.scala 102:20]
- reg instValid_0; // @[Fetch.scala 105:26]
- reg instValid_1; // @[Fetch.scala 105:26]
- reg instValid_2; // @[Fetch.scala 105:26]
- reg instValid_3; // @[Fetch.scala 105:26]
- reg [31:0] instAddr_0; // @[Fetch.scala 106:22]
- reg [31:0] instAddr_1; // @[Fetch.scala 106:22]
- reg [31:0] instAddr_2; // @[Fetch.scala 106:22]
- reg [31:0] instAddr_3; // @[Fetch.scala 106:22]
- reg [31:0] instBits_0; // @[Fetch.scala 107:22]
- reg [31:0] instBits_1; // @[Fetch.scala 107:22]
- reg [31:0] instBits_2; // @[Fetch.scala 107:22]
- reg [31:0] instBits_3; // @[Fetch.scala 107:22]
- wire [31:0] instAligned0 = {instAddr_0[31:5],5'h0}; // @[Cat.scala 31:58]
- wire [31:0] instAligned1 = instAligned0 + 32'h20; // @[Fetch.scala 110:35]
- wire [4:0] instIndex0 = instAligned0[9:5]; // @[Fetch.scala 112:32]
- wire [4:0] instIndex1 = instAligned1[9:5]; // @[Fetch.scala 113:32]
- wire [21:0] instTag0 = instAligned0[31:10]; // @[Fetch.scala 115:30]
- wire [21:0] instTag1 = instAligned1[31:10]; // @[Fetch.scala 116:30]
- wire [31:0] _l0valid0_T = l0valid >> instIndex0; // @[Fetch.scala 118:25]
- wire l0valid0 = _l0valid0_T[0]; // @[Fetch.scala 118:25]
- wire [31:0] _l0valid1_T = l0valid >> instIndex1; // @[Fetch.scala 119:25]
- wire l0valid1 = _l0valid1_T[0]; // @[Fetch.scala 119:25]
- wire [21:0] l0tag0_value__0 = 5'h0 == instIndex0 ? l0tag_0 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__1 = 5'h1 == instIndex0 ? l0tag_1 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__2 = 5'h2 == instIndex0 ? l0tag_2 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__3 = 5'h3 == instIndex0 ? l0tag_3 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__4 = 5'h4 == instIndex0 ? l0tag_4 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__5 = 5'h5 == instIndex0 ? l0tag_5 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__6 = 5'h6 == instIndex0 ? l0tag_6 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__7 = 5'h7 == instIndex0 ? l0tag_7 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__8 = 5'h8 == instIndex0 ? l0tag_8 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__9 = 5'h9 == instIndex0 ? l0tag_9 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__10 = 5'ha == instIndex0 ? l0tag_10 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__11 = 5'hb == instIndex0 ? l0tag_11 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__12 = 5'hc == instIndex0 ? l0tag_12 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__13 = 5'hd == instIndex0 ? l0tag_13 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__14 = 5'he == instIndex0 ? l0tag_14 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__15 = 5'hf == instIndex0 ? l0tag_15 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__16 = 5'h10 == instIndex0 ? l0tag_16 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__17 = 5'h11 == instIndex0 ? l0tag_17 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__18 = 5'h12 == instIndex0 ? l0tag_18 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__19 = 5'h13 == instIndex0 ? l0tag_19 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__20 = 5'h14 == instIndex0 ? l0tag_20 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__21 = 5'h15 == instIndex0 ? l0tag_21 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__22 = 5'h16 == instIndex0 ? l0tag_22 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__23 = 5'h17 == instIndex0 ? l0tag_23 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__24 = 5'h18 == instIndex0 ? l0tag_24 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__25 = 5'h19 == instIndex0 ? l0tag_25 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__26 = 5'h1a == instIndex0 ? l0tag_26 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__27 = 5'h1b == instIndex0 ? l0tag_27 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__28 = 5'h1c == instIndex0 ? l0tag_28 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__29 = 5'h1d == instIndex0 ? l0tag_29 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__30 = 5'h1e == instIndex0 ? l0tag_30 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value__31 = 5'h1f == instIndex0 ? l0tag_31 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag0_value_1_0 = l0tag0_value__0 | l0tag0_value__1; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_1 = l0tag0_value__2 | l0tag0_value__3; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_2 = l0tag0_value__4 | l0tag0_value__5; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_3 = l0tag0_value__6 | l0tag0_value__7; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_4 = l0tag0_value__8 | l0tag0_value__9; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_5 = l0tag0_value__10 | l0tag0_value__11; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_6 = l0tag0_value__12 | l0tag0_value__13; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_7 = l0tag0_value__14 | l0tag0_value__15; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_8 = l0tag0_value__16 | l0tag0_value__17; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_9 = l0tag0_value__18 | l0tag0_value__19; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_10 = l0tag0_value__20 | l0tag0_value__21; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_11 = l0tag0_value__22 | l0tag0_value__23; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_12 = l0tag0_value__24 | l0tag0_value__25; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_13 = l0tag0_value__26 | l0tag0_value__27; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_14 = l0tag0_value__28 | l0tag0_value__29; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_1_15 = l0tag0_value__30 | l0tag0_value__31; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_2_0 = l0tag0_value_1_0 | l0tag0_value_1_1; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_2_1 = l0tag0_value_1_2 | l0tag0_value_1_3; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_2_2 = l0tag0_value_1_4 | l0tag0_value_1_5; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_2_3 = l0tag0_value_1_6 | l0tag0_value_1_7; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_2_4 = l0tag0_value_1_8 | l0tag0_value_1_9; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_2_5 = l0tag0_value_1_10 | l0tag0_value_1_11; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_2_6 = l0tag0_value_1_12 | l0tag0_value_1_13; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_2_7 = l0tag0_value_1_14 | l0tag0_value_1_15; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_3_0 = l0tag0_value_2_0 | l0tag0_value_2_1; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_3_1 = l0tag0_value_2_2 | l0tag0_value_2_3; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_3_2 = l0tag0_value_2_4 | l0tag0_value_2_5; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_3_3 = l0tag0_value_2_6 | l0tag0_value_2_7; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_4_0 = l0tag0_value_3_0 | l0tag0_value_3_1; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_4_1 = l0tag0_value_3_2 | l0tag0_value_3_3; // @[Library.scala 129:37]
- wire [21:0] l0tag0_value_5_0 = l0tag0_value_4_0 | l0tag0_value_4_1; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value__0 = 5'h0 == instIndex1 ? l0tag_0 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__1 = 5'h1 == instIndex1 ? l0tag_1 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__2 = 5'h2 == instIndex1 ? l0tag_2 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__3 = 5'h3 == instIndex1 ? l0tag_3 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__4 = 5'h4 == instIndex1 ? l0tag_4 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__5 = 5'h5 == instIndex1 ? l0tag_5 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__6 = 5'h6 == instIndex1 ? l0tag_6 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__7 = 5'h7 == instIndex1 ? l0tag_7 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__8 = 5'h8 == instIndex1 ? l0tag_8 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__9 = 5'h9 == instIndex1 ? l0tag_9 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__10 = 5'ha == instIndex1 ? l0tag_10 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__11 = 5'hb == instIndex1 ? l0tag_11 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__12 = 5'hc == instIndex1 ? l0tag_12 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__13 = 5'hd == instIndex1 ? l0tag_13 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__14 = 5'he == instIndex1 ? l0tag_14 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__15 = 5'hf == instIndex1 ? l0tag_15 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__16 = 5'h10 == instIndex1 ? l0tag_16 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__17 = 5'h11 == instIndex1 ? l0tag_17 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__18 = 5'h12 == instIndex1 ? l0tag_18 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__19 = 5'h13 == instIndex1 ? l0tag_19 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__20 = 5'h14 == instIndex1 ? l0tag_20 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__21 = 5'h15 == instIndex1 ? l0tag_21 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__22 = 5'h16 == instIndex1 ? l0tag_22 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__23 = 5'h17 == instIndex1 ? l0tag_23 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__24 = 5'h18 == instIndex1 ? l0tag_24 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__25 = 5'h19 == instIndex1 ? l0tag_25 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__26 = 5'h1a == instIndex1 ? l0tag_26 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__27 = 5'h1b == instIndex1 ? l0tag_27 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__28 = 5'h1c == instIndex1 ? l0tag_28 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__29 = 5'h1d == instIndex1 ? l0tag_29 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__30 = 5'h1e == instIndex1 ? l0tag_30 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value__31 = 5'h1f == instIndex1 ? l0tag_31 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tag1_value_1_0 = l0tag1_value__0 | l0tag1_value__1; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_1 = l0tag1_value__2 | l0tag1_value__3; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_2 = l0tag1_value__4 | l0tag1_value__5; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_3 = l0tag1_value__6 | l0tag1_value__7; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_4 = l0tag1_value__8 | l0tag1_value__9; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_5 = l0tag1_value__10 | l0tag1_value__11; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_6 = l0tag1_value__12 | l0tag1_value__13; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_7 = l0tag1_value__14 | l0tag1_value__15; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_8 = l0tag1_value__16 | l0tag1_value__17; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_9 = l0tag1_value__18 | l0tag1_value__19; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_10 = l0tag1_value__20 | l0tag1_value__21; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_11 = l0tag1_value__22 | l0tag1_value__23; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_12 = l0tag1_value__24 | l0tag1_value__25; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_13 = l0tag1_value__26 | l0tag1_value__27; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_14 = l0tag1_value__28 | l0tag1_value__29; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_1_15 = l0tag1_value__30 | l0tag1_value__31; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_2_0 = l0tag1_value_1_0 | l0tag1_value_1_1; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_2_1 = l0tag1_value_1_2 | l0tag1_value_1_3; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_2_2 = l0tag1_value_1_4 | l0tag1_value_1_5; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_2_3 = l0tag1_value_1_6 | l0tag1_value_1_7; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_2_4 = l0tag1_value_1_8 | l0tag1_value_1_9; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_2_5 = l0tag1_value_1_10 | l0tag1_value_1_11; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_2_6 = l0tag1_value_1_12 | l0tag1_value_1_13; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_2_7 = l0tag1_value_1_14 | l0tag1_value_1_15; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_3_0 = l0tag1_value_2_0 | l0tag1_value_2_1; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_3_1 = l0tag1_value_2_2 | l0tag1_value_2_3; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_3_2 = l0tag1_value_2_4 | l0tag1_value_2_5; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_3_3 = l0tag1_value_2_6 | l0tag1_value_2_7; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_4_0 = l0tag1_value_3_0 | l0tag1_value_3_1; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_4_1 = l0tag1_value_3_2 | l0tag1_value_3_3; // @[Library.scala 129:37]
- wire [21:0] l0tag1_value_5_0 = l0tag1_value_4_0 | l0tag1_value_4_1; // @[Library.scala 129:37]
- wire match0 = l0valid0 & instTag0 == l0tag0_value_5_0; // @[Fetch.scala 124:25]
- wire match1 = l0valid1 & instTag1 == l0tag1_value_5_0; // @[Fetch.scala 125:25]
- wire jal_bit = instBits_0[31]; // @[Library.scala 332:23]
- wire jal_bit_1 = instBits_0[30]; // @[Library.scala 332:23]
- wire jal_bit_2 = instBits_0[29]; // @[Library.scala 332:23]
- wire jal_bit_3 = instBits_0[28]; // @[Library.scala 332:23]
- wire jal_bit_4 = instBits_0[27]; // @[Library.scala 332:23]
- wire jal_bit_5 = instBits_0[26]; // @[Library.scala 332:23]
- wire jal_bit_6 = instBits_0[25]; // @[Library.scala 332:23]
- wire jal_bit_7 = instBits_0[24]; // @[Library.scala 332:23]
- wire jal_bit_8 = instBits_0[23]; // @[Library.scala 332:23]
- wire jal_bit_9 = instBits_0[22]; // @[Library.scala 332:23]
- wire jal_bit_10 = instBits_0[21]; // @[Library.scala 332:23]
- wire jal_bit_11 = instBits_0[20]; // @[Library.scala 332:23]
- wire jal_bit_12 = instBits_0[19]; // @[Library.scala 332:23]
- wire jal_bit_13 = instBits_0[18]; // @[Library.scala 332:23]
- wire jal_bit_14 = instBits_0[17]; // @[Library.scala 332:23]
- wire jal_bit_15 = instBits_0[16]; // @[Library.scala 332:23]
- wire jal_bit_16 = instBits_0[15]; // @[Library.scala 332:23]
- wire jal_bit_17 = instBits_0[14]; // @[Library.scala 332:23]
- wire jal_bit_18 = instBits_0[13]; // @[Library.scala 332:23]
- wire jal_bit_19 = instBits_0[12]; // @[Library.scala 332:23]
- wire jal_bit_20 = instBits_0[11]; // @[Library.scala 332:23]
- wire jal_bit_21 = instBits_0[10]; // @[Library.scala 332:23]
- wire jal_bit_22 = instBits_0[9]; // @[Library.scala 332:23]
- wire jal_bit_23 = instBits_0[8]; // @[Library.scala 332:23]
- wire jal_bit_24 = instBits_0[7]; // @[Library.scala 332:23]
- wire jal_bit_25 = instBits_0[6]; // @[Library.scala 329:23]
- wire jal_bit_26 = instBits_0[5]; // @[Library.scala 329:23]
- wire _jal_T_1 = jal_bit_25 & jal_bit_26; // @[Library.scala 330:48]
- wire jal_bit_27 = ~instBits_0[4]; // @[Library.scala 326:19]
- wire _jal_T_2 = _jal_T_1 & jal_bit_27; // @[Library.scala 327:48]
- wire jal_bit_28 = instBits_0[3]; // @[Library.scala 329:23]
- wire jal_bit_29 = instBits_0[2]; // @[Library.scala 329:23]
- wire jal_bit_30 = instBits_0[1]; // @[Library.scala 329:23]
- wire jal_bit_31 = instBits_0[0]; // @[Library.scala 329:23]
- wire preBranchTaken0 = _jal_T_2 & jal_bit_28 & jal_bit_29 & jal_bit_30 & jal_bit_31; // @[Library.scala 330:48]
- wire [11:0] _immed_T_2 = jal_bit ? 12'hfff : 12'h0; // @[Bitwise.scala 74:12]
- wire [31:0] immed = {_immed_T_2,instBits_0[19:12],jal_bit_11,instBits_0[30:21],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] preBranchTarget0 = instAddr_0 + immed; // @[Fetch.scala 133:23]
- wire jal_bit_32 = instBits_1[31]; // @[Library.scala 332:23]
- wire jal_bit_33 = instBits_1[30]; // @[Library.scala 332:23]
- wire jal_bit_34 = instBits_1[29]; // @[Library.scala 332:23]
- wire jal_bit_35 = instBits_1[28]; // @[Library.scala 332:23]
- wire jal_bit_36 = instBits_1[27]; // @[Library.scala 332:23]
- wire jal_bit_37 = instBits_1[26]; // @[Library.scala 332:23]
- wire jal_bit_38 = instBits_1[25]; // @[Library.scala 332:23]
- wire jal_bit_39 = instBits_1[24]; // @[Library.scala 332:23]
- wire jal_bit_40 = instBits_1[23]; // @[Library.scala 332:23]
- wire jal_bit_41 = instBits_1[22]; // @[Library.scala 332:23]
- wire jal_bit_42 = instBits_1[21]; // @[Library.scala 332:23]
- wire jal_bit_43 = instBits_1[20]; // @[Library.scala 332:23]
- wire jal_bit_44 = instBits_1[19]; // @[Library.scala 332:23]
- wire jal_bit_45 = instBits_1[18]; // @[Library.scala 332:23]
- wire jal_bit_46 = instBits_1[17]; // @[Library.scala 332:23]
- wire jal_bit_47 = instBits_1[16]; // @[Library.scala 332:23]
- wire jal_bit_48 = instBits_1[15]; // @[Library.scala 332:23]
- wire jal_bit_49 = instBits_1[14]; // @[Library.scala 332:23]
- wire jal_bit_50 = instBits_1[13]; // @[Library.scala 332:23]
- wire jal_bit_51 = instBits_1[12]; // @[Library.scala 332:23]
- wire jal_bit_52 = instBits_1[11]; // @[Library.scala 332:23]
- wire jal_bit_53 = instBits_1[10]; // @[Library.scala 332:23]
- wire jal_bit_54 = instBits_1[9]; // @[Library.scala 332:23]
- wire jal_bit_55 = instBits_1[8]; // @[Library.scala 332:23]
- wire jal_bit_56 = instBits_1[7]; // @[Library.scala 332:23]
- wire jal_bit_57 = instBits_1[6]; // @[Library.scala 329:23]
- wire jal_bit_58 = instBits_1[5]; // @[Library.scala 329:23]
- wire _jal_T_7 = jal_bit_57 & jal_bit_58; // @[Library.scala 330:48]
- wire jal_bit_59 = ~instBits_1[4]; // @[Library.scala 326:19]
- wire _jal_T_8 = _jal_T_7 & jal_bit_59; // @[Library.scala 327:48]
- wire jal_bit_60 = instBits_1[3]; // @[Library.scala 329:23]
- wire jal_bit_61 = instBits_1[2]; // @[Library.scala 329:23]
- wire jal_bit_62 = instBits_1[1]; // @[Library.scala 329:23]
- wire jal_bit_63 = instBits_1[0]; // @[Library.scala 329:23]
- wire preBranchTaken1 = _jal_T_8 & jal_bit_60 & jal_bit_61 & jal_bit_62 & jal_bit_63; // @[Library.scala 330:48]
- wire [11:0] _immed_T_8 = jal_bit_32 ? 12'hfff : 12'h0; // @[Bitwise.scala 74:12]
- wire [31:0] immed_1 = {_immed_T_8,instBits_1[19:12],jal_bit_43,instBits_1[30:21],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] preBranchTarget1 = instAddr_1 + immed_1; // @[Fetch.scala 133:23]
- wire jal_bit_64 = instBits_2[31]; // @[Library.scala 332:23]
- wire jal_bit_65 = instBits_2[30]; // @[Library.scala 332:23]
- wire jal_bit_66 = instBits_2[29]; // @[Library.scala 332:23]
- wire jal_bit_67 = instBits_2[28]; // @[Library.scala 332:23]
- wire jal_bit_68 = instBits_2[27]; // @[Library.scala 332:23]
- wire jal_bit_69 = instBits_2[26]; // @[Library.scala 332:23]
- wire jal_bit_70 = instBits_2[25]; // @[Library.scala 332:23]
- wire jal_bit_71 = instBits_2[24]; // @[Library.scala 332:23]
- wire jal_bit_72 = instBits_2[23]; // @[Library.scala 332:23]
- wire jal_bit_73 = instBits_2[22]; // @[Library.scala 332:23]
- wire jal_bit_74 = instBits_2[21]; // @[Library.scala 332:23]
- wire jal_bit_75 = instBits_2[20]; // @[Library.scala 332:23]
- wire jal_bit_76 = instBits_2[19]; // @[Library.scala 332:23]
- wire jal_bit_77 = instBits_2[18]; // @[Library.scala 332:23]
- wire jal_bit_78 = instBits_2[17]; // @[Library.scala 332:23]
- wire jal_bit_79 = instBits_2[16]; // @[Library.scala 332:23]
- wire jal_bit_80 = instBits_2[15]; // @[Library.scala 332:23]
- wire jal_bit_81 = instBits_2[14]; // @[Library.scala 332:23]
- wire jal_bit_82 = instBits_2[13]; // @[Library.scala 332:23]
- wire jal_bit_83 = instBits_2[12]; // @[Library.scala 332:23]
- wire jal_bit_84 = instBits_2[11]; // @[Library.scala 332:23]
- wire jal_bit_85 = instBits_2[10]; // @[Library.scala 332:23]
- wire jal_bit_86 = instBits_2[9]; // @[Library.scala 332:23]
- wire jal_bit_87 = instBits_2[8]; // @[Library.scala 332:23]
- wire jal_bit_88 = instBits_2[7]; // @[Library.scala 332:23]
- wire jal_bit_89 = instBits_2[6]; // @[Library.scala 329:23]
- wire jal_bit_90 = instBits_2[5]; // @[Library.scala 329:23]
- wire _jal_T_13 = jal_bit_89 & jal_bit_90; // @[Library.scala 330:48]
- wire jal_bit_91 = ~instBits_2[4]; // @[Library.scala 326:19]
- wire _jal_T_14 = _jal_T_13 & jal_bit_91; // @[Library.scala 327:48]
- wire jal_bit_92 = instBits_2[3]; // @[Library.scala 329:23]
- wire jal_bit_93 = instBits_2[2]; // @[Library.scala 329:23]
- wire jal_bit_94 = instBits_2[1]; // @[Library.scala 329:23]
- wire jal_bit_95 = instBits_2[0]; // @[Library.scala 329:23]
- wire preBranchTaken2 = _jal_T_14 & jal_bit_92 & jal_bit_93 & jal_bit_94 & jal_bit_95; // @[Library.scala 330:48]
- wire [11:0] _immed_T_14 = jal_bit_64 ? 12'hfff : 12'h0; // @[Bitwise.scala 74:12]
- wire [31:0] immed_2 = {_immed_T_14,instBits_2[19:12],jal_bit_75,instBits_2[30:21],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] preBranchTarget2 = instAddr_2 + immed_2; // @[Fetch.scala 133:23]
- wire jal_bit_96 = instBits_3[31]; // @[Library.scala 332:23]
- wire jal_bit_97 = instBits_3[30]; // @[Library.scala 332:23]
- wire jal_bit_98 = instBits_3[29]; // @[Library.scala 332:23]
- wire jal_bit_99 = instBits_3[28]; // @[Library.scala 332:23]
- wire jal_bit_100 = instBits_3[27]; // @[Library.scala 332:23]
- wire jal_bit_101 = instBits_3[26]; // @[Library.scala 332:23]
- wire jal_bit_102 = instBits_3[25]; // @[Library.scala 332:23]
- wire jal_bit_103 = instBits_3[24]; // @[Library.scala 332:23]
- wire jal_bit_104 = instBits_3[23]; // @[Library.scala 332:23]
- wire jal_bit_105 = instBits_3[22]; // @[Library.scala 332:23]
- wire jal_bit_106 = instBits_3[21]; // @[Library.scala 332:23]
- wire jal_bit_107 = instBits_3[20]; // @[Library.scala 332:23]
- wire jal_bit_108 = instBits_3[19]; // @[Library.scala 332:23]
- wire jal_bit_109 = instBits_3[18]; // @[Library.scala 332:23]
- wire jal_bit_110 = instBits_3[17]; // @[Library.scala 332:23]
- wire jal_bit_111 = instBits_3[16]; // @[Library.scala 332:23]
- wire jal_bit_112 = instBits_3[15]; // @[Library.scala 332:23]
- wire jal_bit_113 = instBits_3[14]; // @[Library.scala 332:23]
- wire jal_bit_114 = instBits_3[13]; // @[Library.scala 332:23]
- wire jal_bit_115 = instBits_3[12]; // @[Library.scala 332:23]
- wire jal_bit_116 = instBits_3[11]; // @[Library.scala 332:23]
- wire jal_bit_117 = instBits_3[10]; // @[Library.scala 332:23]
- wire jal_bit_118 = instBits_3[9]; // @[Library.scala 332:23]
- wire jal_bit_119 = instBits_3[8]; // @[Library.scala 332:23]
- wire jal_bit_120 = instBits_3[7]; // @[Library.scala 332:23]
- wire jal_bit_121 = instBits_3[6]; // @[Library.scala 329:23]
- wire jal_bit_122 = instBits_3[5]; // @[Library.scala 329:23]
- wire _jal_T_19 = jal_bit_121 & jal_bit_122; // @[Library.scala 330:48]
- wire jal_bit_123 = ~instBits_3[4]; // @[Library.scala 326:19]
- wire _jal_T_20 = _jal_T_19 & jal_bit_123; // @[Library.scala 327:48]
- wire jal_bit_124 = instBits_3[3]; // @[Library.scala 329:23]
- wire jal_bit_125 = instBits_3[2]; // @[Library.scala 329:23]
- wire jal_bit_126 = instBits_3[1]; // @[Library.scala 329:23]
- wire jal_bit_127 = instBits_3[0]; // @[Library.scala 329:23]
- wire preBranchTaken3 = _jal_T_20 & jal_bit_124 & jal_bit_125 & jal_bit_126 & jal_bit_127; // @[Library.scala 330:48]
- wire [11:0] _immed_T_20 = jal_bit_96 ? 12'hfff : 12'h0; // @[Bitwise.scala 74:12]
- wire [31:0] immed_3 = {_immed_T_20,instBits_3[19:12],jal_bit_107,instBits_3[30:21],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] preBranchTarget3 = instAddr_3 + immed_3; // @[Fetch.scala 133:23]
- wire _preBranchTaken_T_1 = io_inst_lanes_1_valid & preBranchTaken1; // @[Fetch.scala 147:47]
- wire _preBranchTaken_T_2 = io_inst_lanes_0_valid & preBranchTaken0 | _preBranchTaken_T_1; // @[Fetch.scala 146:66]
- wire _preBranchTaken_T_3 = io_inst_lanes_2_valid & preBranchTaken2; // @[Fetch.scala 148:47]
- wire _preBranchTaken_T_4 = _preBranchTaken_T_2 | _preBranchTaken_T_3; // @[Fetch.scala 147:66]
- wire _preBranchTaken_T_5 = io_inst_lanes_3_valid & preBranchTaken3; // @[Fetch.scala 149:47]
- wire preBranchTaken = _preBranchTaken_T_4 | _preBranchTaken_T_5; // @[Fetch.scala 148:66]
- wire [31:0] _preBranchTarget_T = preBranchTaken2 ? preBranchTarget2 : preBranchTarget3; // @[Fetch.scala 153:28]
- wire [31:0] _preBranchTarget_T_1 = preBranchTaken1 ? preBranchTarget1 : _preBranchTarget_T; // @[Fetch.scala 152:28]
- wire [31:0] preBranchTarget = preBranchTaken0 ? preBranchTarget0 : _preBranchTarget_T_1; // @[Fetch.scala 151:28]
- wire [21:0] preBranchTag = preBranchTarget[31:10]; // @[Fetch.scala 156:37]
- wire [4:0] preBranchIndex = preBranchTarget[9:5]; // @[Fetch.scala 157:39]
- wire [21:0] branchTag0 = io_branch_0_value[31:10]; // @[Fetch.scala 159:38]
- wire [21:0] branchTag1 = io_branch_1_value[31:10]; // @[Fetch.scala 160:38]
- wire [21:0] branchTag2 = io_branch_2_value[31:10]; // @[Fetch.scala 161:38]
- wire [21:0] branchTag3 = io_branch_3_value[31:10]; // @[Fetch.scala 162:38]
- wire [4:0] branchIndex0 = io_branch_0_value[9:5]; // @[Fetch.scala 163:40]
- wire [4:0] branchIndex1 = io_branch_1_value[9:5]; // @[Fetch.scala 164:40]
- wire [4:0] branchIndex2 = io_branch_2_value[9:5]; // @[Fetch.scala 165:40]
- wire [4:0] branchIndex3 = io_branch_3_value[9:5]; // @[Fetch.scala 166:40]
- wire [31:0] _l0validB0_T = l0valid >> branchIndex0; // @[Fetch.scala 168:26]
- wire l0validB0 = _l0validB0_T[0]; // @[Fetch.scala 168:26]
- wire [31:0] _l0validB1_T = l0valid >> branchIndex1; // @[Fetch.scala 169:26]
- wire l0validB1 = _l0validB1_T[0]; // @[Fetch.scala 169:26]
- wire [31:0] _l0validB2_T = l0valid >> branchIndex2; // @[Fetch.scala 170:26]
- wire l0validB2 = _l0validB2_T[0]; // @[Fetch.scala 170:26]
- wire [31:0] _l0validB3_T = l0valid >> branchIndex3; // @[Fetch.scala 171:26]
- wire l0validB3 = _l0validB3_T[0]; // @[Fetch.scala 171:26]
- wire [31:0] _l0validP_T = l0valid >> preBranchIndex; // @[Fetch.scala 172:26]
- wire l0validP = _l0validP_T[0]; // @[Fetch.scala 172:26]
- wire [21:0] l0tagB0_value__0 = 5'h0 == branchIndex0 ? l0tag_0 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__1 = 5'h1 == branchIndex0 ? l0tag_1 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__2 = 5'h2 == branchIndex0 ? l0tag_2 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__3 = 5'h3 == branchIndex0 ? l0tag_3 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__4 = 5'h4 == branchIndex0 ? l0tag_4 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__5 = 5'h5 == branchIndex0 ? l0tag_5 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__6 = 5'h6 == branchIndex0 ? l0tag_6 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__7 = 5'h7 == branchIndex0 ? l0tag_7 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__8 = 5'h8 == branchIndex0 ? l0tag_8 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__9 = 5'h9 == branchIndex0 ? l0tag_9 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__10 = 5'ha == branchIndex0 ? l0tag_10 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__11 = 5'hb == branchIndex0 ? l0tag_11 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__12 = 5'hc == branchIndex0 ? l0tag_12 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__13 = 5'hd == branchIndex0 ? l0tag_13 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__14 = 5'he == branchIndex0 ? l0tag_14 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__15 = 5'hf == branchIndex0 ? l0tag_15 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__16 = 5'h10 == branchIndex0 ? l0tag_16 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__17 = 5'h11 == branchIndex0 ? l0tag_17 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__18 = 5'h12 == branchIndex0 ? l0tag_18 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__19 = 5'h13 == branchIndex0 ? l0tag_19 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__20 = 5'h14 == branchIndex0 ? l0tag_20 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__21 = 5'h15 == branchIndex0 ? l0tag_21 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__22 = 5'h16 == branchIndex0 ? l0tag_22 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__23 = 5'h17 == branchIndex0 ? l0tag_23 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__24 = 5'h18 == branchIndex0 ? l0tag_24 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__25 = 5'h19 == branchIndex0 ? l0tag_25 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__26 = 5'h1a == branchIndex0 ? l0tag_26 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__27 = 5'h1b == branchIndex0 ? l0tag_27 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__28 = 5'h1c == branchIndex0 ? l0tag_28 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__29 = 5'h1d == branchIndex0 ? l0tag_29 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__30 = 5'h1e == branchIndex0 ? l0tag_30 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value__31 = 5'h1f == branchIndex0 ? l0tag_31 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB0_value_1_0 = l0tagB0_value__0 | l0tagB0_value__1; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_1 = l0tagB0_value__2 | l0tagB0_value__3; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_2 = l0tagB0_value__4 | l0tagB0_value__5; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_3 = l0tagB0_value__6 | l0tagB0_value__7; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_4 = l0tagB0_value__8 | l0tagB0_value__9; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_5 = l0tagB0_value__10 | l0tagB0_value__11; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_6 = l0tagB0_value__12 | l0tagB0_value__13; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_7 = l0tagB0_value__14 | l0tagB0_value__15; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_8 = l0tagB0_value__16 | l0tagB0_value__17; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_9 = l0tagB0_value__18 | l0tagB0_value__19; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_10 = l0tagB0_value__20 | l0tagB0_value__21; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_11 = l0tagB0_value__22 | l0tagB0_value__23; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_12 = l0tagB0_value__24 | l0tagB0_value__25; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_13 = l0tagB0_value__26 | l0tagB0_value__27; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_14 = l0tagB0_value__28 | l0tagB0_value__29; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_1_15 = l0tagB0_value__30 | l0tagB0_value__31; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_2_0 = l0tagB0_value_1_0 | l0tagB0_value_1_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_2_1 = l0tagB0_value_1_2 | l0tagB0_value_1_3; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_2_2 = l0tagB0_value_1_4 | l0tagB0_value_1_5; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_2_3 = l0tagB0_value_1_6 | l0tagB0_value_1_7; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_2_4 = l0tagB0_value_1_8 | l0tagB0_value_1_9; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_2_5 = l0tagB0_value_1_10 | l0tagB0_value_1_11; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_2_6 = l0tagB0_value_1_12 | l0tagB0_value_1_13; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_2_7 = l0tagB0_value_1_14 | l0tagB0_value_1_15; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_3_0 = l0tagB0_value_2_0 | l0tagB0_value_2_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_3_1 = l0tagB0_value_2_2 | l0tagB0_value_2_3; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_3_2 = l0tagB0_value_2_4 | l0tagB0_value_2_5; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_3_3 = l0tagB0_value_2_6 | l0tagB0_value_2_7; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_4_0 = l0tagB0_value_3_0 | l0tagB0_value_3_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_4_1 = l0tagB0_value_3_2 | l0tagB0_value_3_3; // @[Library.scala 129:37]
- wire [21:0] l0tagB0_value_5_0 = l0tagB0_value_4_0 | l0tagB0_value_4_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value__0 = 5'h0 == branchIndex1 ? l0tag_0 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__1 = 5'h1 == branchIndex1 ? l0tag_1 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__2 = 5'h2 == branchIndex1 ? l0tag_2 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__3 = 5'h3 == branchIndex1 ? l0tag_3 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__4 = 5'h4 == branchIndex1 ? l0tag_4 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__5 = 5'h5 == branchIndex1 ? l0tag_5 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__6 = 5'h6 == branchIndex1 ? l0tag_6 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__7 = 5'h7 == branchIndex1 ? l0tag_7 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__8 = 5'h8 == branchIndex1 ? l0tag_8 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__9 = 5'h9 == branchIndex1 ? l0tag_9 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__10 = 5'ha == branchIndex1 ? l0tag_10 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__11 = 5'hb == branchIndex1 ? l0tag_11 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__12 = 5'hc == branchIndex1 ? l0tag_12 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__13 = 5'hd == branchIndex1 ? l0tag_13 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__14 = 5'he == branchIndex1 ? l0tag_14 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__15 = 5'hf == branchIndex1 ? l0tag_15 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__16 = 5'h10 == branchIndex1 ? l0tag_16 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__17 = 5'h11 == branchIndex1 ? l0tag_17 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__18 = 5'h12 == branchIndex1 ? l0tag_18 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__19 = 5'h13 == branchIndex1 ? l0tag_19 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__20 = 5'h14 == branchIndex1 ? l0tag_20 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__21 = 5'h15 == branchIndex1 ? l0tag_21 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__22 = 5'h16 == branchIndex1 ? l0tag_22 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__23 = 5'h17 == branchIndex1 ? l0tag_23 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__24 = 5'h18 == branchIndex1 ? l0tag_24 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__25 = 5'h19 == branchIndex1 ? l0tag_25 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__26 = 5'h1a == branchIndex1 ? l0tag_26 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__27 = 5'h1b == branchIndex1 ? l0tag_27 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__28 = 5'h1c == branchIndex1 ? l0tag_28 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__29 = 5'h1d == branchIndex1 ? l0tag_29 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__30 = 5'h1e == branchIndex1 ? l0tag_30 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value__31 = 5'h1f == branchIndex1 ? l0tag_31 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB1_value_1_0 = l0tagB1_value__0 | l0tagB1_value__1; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_1 = l0tagB1_value__2 | l0tagB1_value__3; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_2 = l0tagB1_value__4 | l0tagB1_value__5; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_3 = l0tagB1_value__6 | l0tagB1_value__7; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_4 = l0tagB1_value__8 | l0tagB1_value__9; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_5 = l0tagB1_value__10 | l0tagB1_value__11; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_6 = l0tagB1_value__12 | l0tagB1_value__13; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_7 = l0tagB1_value__14 | l0tagB1_value__15; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_8 = l0tagB1_value__16 | l0tagB1_value__17; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_9 = l0tagB1_value__18 | l0tagB1_value__19; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_10 = l0tagB1_value__20 | l0tagB1_value__21; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_11 = l0tagB1_value__22 | l0tagB1_value__23; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_12 = l0tagB1_value__24 | l0tagB1_value__25; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_13 = l0tagB1_value__26 | l0tagB1_value__27; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_14 = l0tagB1_value__28 | l0tagB1_value__29; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_1_15 = l0tagB1_value__30 | l0tagB1_value__31; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_2_0 = l0tagB1_value_1_0 | l0tagB1_value_1_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_2_1 = l0tagB1_value_1_2 | l0tagB1_value_1_3; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_2_2 = l0tagB1_value_1_4 | l0tagB1_value_1_5; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_2_3 = l0tagB1_value_1_6 | l0tagB1_value_1_7; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_2_4 = l0tagB1_value_1_8 | l0tagB1_value_1_9; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_2_5 = l0tagB1_value_1_10 | l0tagB1_value_1_11; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_2_6 = l0tagB1_value_1_12 | l0tagB1_value_1_13; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_2_7 = l0tagB1_value_1_14 | l0tagB1_value_1_15; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_3_0 = l0tagB1_value_2_0 | l0tagB1_value_2_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_3_1 = l0tagB1_value_2_2 | l0tagB1_value_2_3; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_3_2 = l0tagB1_value_2_4 | l0tagB1_value_2_5; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_3_3 = l0tagB1_value_2_6 | l0tagB1_value_2_7; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_4_0 = l0tagB1_value_3_0 | l0tagB1_value_3_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_4_1 = l0tagB1_value_3_2 | l0tagB1_value_3_3; // @[Library.scala 129:37]
- wire [21:0] l0tagB1_value_5_0 = l0tagB1_value_4_0 | l0tagB1_value_4_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value__0 = 5'h0 == branchIndex2 ? l0tag_0 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__1 = 5'h1 == branchIndex2 ? l0tag_1 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__2 = 5'h2 == branchIndex2 ? l0tag_2 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__3 = 5'h3 == branchIndex2 ? l0tag_3 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__4 = 5'h4 == branchIndex2 ? l0tag_4 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__5 = 5'h5 == branchIndex2 ? l0tag_5 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__6 = 5'h6 == branchIndex2 ? l0tag_6 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__7 = 5'h7 == branchIndex2 ? l0tag_7 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__8 = 5'h8 == branchIndex2 ? l0tag_8 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__9 = 5'h9 == branchIndex2 ? l0tag_9 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__10 = 5'ha == branchIndex2 ? l0tag_10 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__11 = 5'hb == branchIndex2 ? l0tag_11 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__12 = 5'hc == branchIndex2 ? l0tag_12 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__13 = 5'hd == branchIndex2 ? l0tag_13 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__14 = 5'he == branchIndex2 ? l0tag_14 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__15 = 5'hf == branchIndex2 ? l0tag_15 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__16 = 5'h10 == branchIndex2 ? l0tag_16 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__17 = 5'h11 == branchIndex2 ? l0tag_17 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__18 = 5'h12 == branchIndex2 ? l0tag_18 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__19 = 5'h13 == branchIndex2 ? l0tag_19 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__20 = 5'h14 == branchIndex2 ? l0tag_20 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__21 = 5'h15 == branchIndex2 ? l0tag_21 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__22 = 5'h16 == branchIndex2 ? l0tag_22 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__23 = 5'h17 == branchIndex2 ? l0tag_23 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__24 = 5'h18 == branchIndex2 ? l0tag_24 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__25 = 5'h19 == branchIndex2 ? l0tag_25 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__26 = 5'h1a == branchIndex2 ? l0tag_26 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__27 = 5'h1b == branchIndex2 ? l0tag_27 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__28 = 5'h1c == branchIndex2 ? l0tag_28 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__29 = 5'h1d == branchIndex2 ? l0tag_29 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__30 = 5'h1e == branchIndex2 ? l0tag_30 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value__31 = 5'h1f == branchIndex2 ? l0tag_31 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB2_value_1_0 = l0tagB2_value__0 | l0tagB2_value__1; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_1 = l0tagB2_value__2 | l0tagB2_value__3; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_2 = l0tagB2_value__4 | l0tagB2_value__5; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_3 = l0tagB2_value__6 | l0tagB2_value__7; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_4 = l0tagB2_value__8 | l0tagB2_value__9; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_5 = l0tagB2_value__10 | l0tagB2_value__11; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_6 = l0tagB2_value__12 | l0tagB2_value__13; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_7 = l0tagB2_value__14 | l0tagB2_value__15; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_8 = l0tagB2_value__16 | l0tagB2_value__17; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_9 = l0tagB2_value__18 | l0tagB2_value__19; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_10 = l0tagB2_value__20 | l0tagB2_value__21; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_11 = l0tagB2_value__22 | l0tagB2_value__23; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_12 = l0tagB2_value__24 | l0tagB2_value__25; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_13 = l0tagB2_value__26 | l0tagB2_value__27; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_14 = l0tagB2_value__28 | l0tagB2_value__29; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_1_15 = l0tagB2_value__30 | l0tagB2_value__31; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_2_0 = l0tagB2_value_1_0 | l0tagB2_value_1_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_2_1 = l0tagB2_value_1_2 | l0tagB2_value_1_3; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_2_2 = l0tagB2_value_1_4 | l0tagB2_value_1_5; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_2_3 = l0tagB2_value_1_6 | l0tagB2_value_1_7; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_2_4 = l0tagB2_value_1_8 | l0tagB2_value_1_9; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_2_5 = l0tagB2_value_1_10 | l0tagB2_value_1_11; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_2_6 = l0tagB2_value_1_12 | l0tagB2_value_1_13; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_2_7 = l0tagB2_value_1_14 | l0tagB2_value_1_15; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_3_0 = l0tagB2_value_2_0 | l0tagB2_value_2_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_3_1 = l0tagB2_value_2_2 | l0tagB2_value_2_3; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_3_2 = l0tagB2_value_2_4 | l0tagB2_value_2_5; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_3_3 = l0tagB2_value_2_6 | l0tagB2_value_2_7; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_4_0 = l0tagB2_value_3_0 | l0tagB2_value_3_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_4_1 = l0tagB2_value_3_2 | l0tagB2_value_3_3; // @[Library.scala 129:37]
- wire [21:0] l0tagB2_value_5_0 = l0tagB2_value_4_0 | l0tagB2_value_4_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value__0 = 5'h0 == branchIndex3 ? l0tag_0 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__1 = 5'h1 == branchIndex3 ? l0tag_1 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__2 = 5'h2 == branchIndex3 ? l0tag_2 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__3 = 5'h3 == branchIndex3 ? l0tag_3 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__4 = 5'h4 == branchIndex3 ? l0tag_4 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__5 = 5'h5 == branchIndex3 ? l0tag_5 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__6 = 5'h6 == branchIndex3 ? l0tag_6 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__7 = 5'h7 == branchIndex3 ? l0tag_7 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__8 = 5'h8 == branchIndex3 ? l0tag_8 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__9 = 5'h9 == branchIndex3 ? l0tag_9 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__10 = 5'ha == branchIndex3 ? l0tag_10 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__11 = 5'hb == branchIndex3 ? l0tag_11 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__12 = 5'hc == branchIndex3 ? l0tag_12 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__13 = 5'hd == branchIndex3 ? l0tag_13 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__14 = 5'he == branchIndex3 ? l0tag_14 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__15 = 5'hf == branchIndex3 ? l0tag_15 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__16 = 5'h10 == branchIndex3 ? l0tag_16 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__17 = 5'h11 == branchIndex3 ? l0tag_17 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__18 = 5'h12 == branchIndex3 ? l0tag_18 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__19 = 5'h13 == branchIndex3 ? l0tag_19 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__20 = 5'h14 == branchIndex3 ? l0tag_20 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__21 = 5'h15 == branchIndex3 ? l0tag_21 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__22 = 5'h16 == branchIndex3 ? l0tag_22 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__23 = 5'h17 == branchIndex3 ? l0tag_23 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__24 = 5'h18 == branchIndex3 ? l0tag_24 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__25 = 5'h19 == branchIndex3 ? l0tag_25 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__26 = 5'h1a == branchIndex3 ? l0tag_26 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__27 = 5'h1b == branchIndex3 ? l0tag_27 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__28 = 5'h1c == branchIndex3 ? l0tag_28 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__29 = 5'h1d == branchIndex3 ? l0tag_29 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__30 = 5'h1e == branchIndex3 ? l0tag_30 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value__31 = 5'h1f == branchIndex3 ? l0tag_31 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagB3_value_1_0 = l0tagB3_value__0 | l0tagB3_value__1; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_1 = l0tagB3_value__2 | l0tagB3_value__3; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_2 = l0tagB3_value__4 | l0tagB3_value__5; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_3 = l0tagB3_value__6 | l0tagB3_value__7; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_4 = l0tagB3_value__8 | l0tagB3_value__9; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_5 = l0tagB3_value__10 | l0tagB3_value__11; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_6 = l0tagB3_value__12 | l0tagB3_value__13; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_7 = l0tagB3_value__14 | l0tagB3_value__15; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_8 = l0tagB3_value__16 | l0tagB3_value__17; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_9 = l0tagB3_value__18 | l0tagB3_value__19; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_10 = l0tagB3_value__20 | l0tagB3_value__21; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_11 = l0tagB3_value__22 | l0tagB3_value__23; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_12 = l0tagB3_value__24 | l0tagB3_value__25; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_13 = l0tagB3_value__26 | l0tagB3_value__27; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_14 = l0tagB3_value__28 | l0tagB3_value__29; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_1_15 = l0tagB3_value__30 | l0tagB3_value__31; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_2_0 = l0tagB3_value_1_0 | l0tagB3_value_1_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_2_1 = l0tagB3_value_1_2 | l0tagB3_value_1_3; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_2_2 = l0tagB3_value_1_4 | l0tagB3_value_1_5; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_2_3 = l0tagB3_value_1_6 | l0tagB3_value_1_7; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_2_4 = l0tagB3_value_1_8 | l0tagB3_value_1_9; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_2_5 = l0tagB3_value_1_10 | l0tagB3_value_1_11; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_2_6 = l0tagB3_value_1_12 | l0tagB3_value_1_13; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_2_7 = l0tagB3_value_1_14 | l0tagB3_value_1_15; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_3_0 = l0tagB3_value_2_0 | l0tagB3_value_2_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_3_1 = l0tagB3_value_2_2 | l0tagB3_value_2_3; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_3_2 = l0tagB3_value_2_4 | l0tagB3_value_2_5; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_3_3 = l0tagB3_value_2_6 | l0tagB3_value_2_7; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_4_0 = l0tagB3_value_3_0 | l0tagB3_value_3_1; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_4_1 = l0tagB3_value_3_2 | l0tagB3_value_3_3; // @[Library.scala 129:37]
- wire [21:0] l0tagB3_value_5_0 = l0tagB3_value_4_0 | l0tagB3_value_4_1; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value__0 = 5'h0 == preBranchIndex ? l0tag_0 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__1 = 5'h1 == preBranchIndex ? l0tag_1 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__2 = 5'h2 == preBranchIndex ? l0tag_2 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__3 = 5'h3 == preBranchIndex ? l0tag_3 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__4 = 5'h4 == preBranchIndex ? l0tag_4 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__5 = 5'h5 == preBranchIndex ? l0tag_5 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__6 = 5'h6 == preBranchIndex ? l0tag_6 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__7 = 5'h7 == preBranchIndex ? l0tag_7 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__8 = 5'h8 == preBranchIndex ? l0tag_8 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__9 = 5'h9 == preBranchIndex ? l0tag_9 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__10 = 5'ha == preBranchIndex ? l0tag_10 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__11 = 5'hb == preBranchIndex ? l0tag_11 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__12 = 5'hc == preBranchIndex ? l0tag_12 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__13 = 5'hd == preBranchIndex ? l0tag_13 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__14 = 5'he == preBranchIndex ? l0tag_14 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__15 = 5'hf == preBranchIndex ? l0tag_15 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__16 = 5'h10 == preBranchIndex ? l0tag_16 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__17 = 5'h11 == preBranchIndex ? l0tag_17 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__18 = 5'h12 == preBranchIndex ? l0tag_18 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__19 = 5'h13 == preBranchIndex ? l0tag_19 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__20 = 5'h14 == preBranchIndex ? l0tag_20 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__21 = 5'h15 == preBranchIndex ? l0tag_21 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__22 = 5'h16 == preBranchIndex ? l0tag_22 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__23 = 5'h17 == preBranchIndex ? l0tag_23 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__24 = 5'h18 == preBranchIndex ? l0tag_24 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__25 = 5'h19 == preBranchIndex ? l0tag_25 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__26 = 5'h1a == preBranchIndex ? l0tag_26 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__27 = 5'h1b == preBranchIndex ? l0tag_27 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__28 = 5'h1c == preBranchIndex ? l0tag_28 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__29 = 5'h1d == preBranchIndex ? l0tag_29 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__30 = 5'h1e == preBranchIndex ? l0tag_30 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value__31 = 5'h1f == preBranchIndex ? l0tag_31 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] l0tagP_value_1_0 = l0tagP_value__0 | l0tagP_value__1; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_1 = l0tagP_value__2 | l0tagP_value__3; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_2 = l0tagP_value__4 | l0tagP_value__5; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_3 = l0tagP_value__6 | l0tagP_value__7; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_4 = l0tagP_value__8 | l0tagP_value__9; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_5 = l0tagP_value__10 | l0tagP_value__11; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_6 = l0tagP_value__12 | l0tagP_value__13; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_7 = l0tagP_value__14 | l0tagP_value__15; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_8 = l0tagP_value__16 | l0tagP_value__17; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_9 = l0tagP_value__18 | l0tagP_value__19; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_10 = l0tagP_value__20 | l0tagP_value__21; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_11 = l0tagP_value__22 | l0tagP_value__23; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_12 = l0tagP_value__24 | l0tagP_value__25; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_13 = l0tagP_value__26 | l0tagP_value__27; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_14 = l0tagP_value__28 | l0tagP_value__29; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_1_15 = l0tagP_value__30 | l0tagP_value__31; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_2_0 = l0tagP_value_1_0 | l0tagP_value_1_1; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_2_1 = l0tagP_value_1_2 | l0tagP_value_1_3; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_2_2 = l0tagP_value_1_4 | l0tagP_value_1_5; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_2_3 = l0tagP_value_1_6 | l0tagP_value_1_7; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_2_4 = l0tagP_value_1_8 | l0tagP_value_1_9; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_2_5 = l0tagP_value_1_10 | l0tagP_value_1_11; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_2_6 = l0tagP_value_1_12 | l0tagP_value_1_13; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_2_7 = l0tagP_value_1_14 | l0tagP_value_1_15; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_3_0 = l0tagP_value_2_0 | l0tagP_value_2_1; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_3_1 = l0tagP_value_2_2 | l0tagP_value_2_3; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_3_2 = l0tagP_value_2_4 | l0tagP_value_2_5; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_3_3 = l0tagP_value_2_6 | l0tagP_value_2_7; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_4_0 = l0tagP_value_3_0 | l0tagP_value_3_1; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_4_1 = l0tagP_value_3_2 | l0tagP_value_3_3; // @[Library.scala 129:37]
- wire [21:0] l0tagP_value_5_0 = l0tagP_value_4_0 | l0tagP_value_4_1; // @[Library.scala 129:37]
- wire [31:0] _reqB0_T = l0req >> branchIndex0; // @[Fetch.scala 180:43]
- wire _reqB0_T_6 = branchTag0 != l0tagB0_value_5_0 | ~l0validB0; // @[Fetch.scala 181:31]
- wire reqB0 = io_branch_0_valid & ~_reqB0_T[0] & _reqB0_T_6; // @[Fetch.scala 180:58]
- wire [31:0] _reqB1_T = l0req >> branchIndex1; // @[Fetch.scala 182:43]
- wire _reqB1_T_6 = branchTag1 != l0tagB1_value_5_0 | ~l0validB1; // @[Fetch.scala 183:31]
- wire _reqB1_T_7 = io_branch_1_valid & ~_reqB1_T[0] & _reqB1_T_6; // @[Fetch.scala 182:58]
- wire _reqB1_T_8 = ~io_branch_0_valid; // @[Fetch.scala 184:7]
- wire reqB1 = _reqB1_T_7 & _reqB1_T_8; // @[Fetch.scala 183:46]
- wire [31:0] _reqB2_T = l0req >> branchIndex2; // @[Fetch.scala 185:43]
- wire _reqB2_T_6 = branchTag2 != l0tagB2_value_5_0 | ~l0validB2; // @[Fetch.scala 186:31]
- wire _reqB2_T_7 = io_branch_2_valid & ~_reqB2_T[0] & _reqB2_T_6; // @[Fetch.scala 185:58]
- wire _reqB2_T_9 = _reqB2_T_7 & _reqB1_T_8; // @[Fetch.scala 186:46]
- wire _reqB2_T_10 = ~io_branch_1_valid; // @[Fetch.scala 187:30]
- wire reqB2 = _reqB2_T_9 & ~io_branch_1_valid; // @[Fetch.scala 187:27]
- wire [31:0] _reqB3_T = l0req >> branchIndex3; // @[Fetch.scala 188:43]
- wire _reqB3_T_6 = branchTag3 != l0tagB3_value_5_0 | ~l0validB3; // @[Fetch.scala 189:31]
- wire _reqB3_T_7 = io_branch_3_valid & ~_reqB3_T[0] & _reqB3_T_6; // @[Fetch.scala 188:58]
- wire _reqB3_T_9 = _reqB3_T_7 & _reqB1_T_8; // @[Fetch.scala 189:46]
- wire reqB3 = _reqB3_T_9 & _reqB2_T_10 & ~io_branch_2_valid; // @[Fetch.scala 190:50]
- wire [31:0] _reqP_T = l0req >> preBranchIndex; // @[Fetch.scala 191:38]
- wire reqP = preBranchTaken & ~_reqP_T[0] & (preBranchTag != l0tagP_value_5_0 | ~l0validP); // @[Fetch.scala 191:55]
- wire [31:0] _req0_T_1 = l0req >> instIndex0; // @[Fetch.scala 192:31]
- wire req0 = ~match0 & ~_req0_T_1[0]; // @[Fetch.scala 192:22]
- wire [31:0] _req1_T_1 = l0req >> instIndex1; // @[Fetch.scala 193:31]
- wire req1 = ~match1 & ~_req1_T_1[0]; // @[Fetch.scala 193:22]
- wire [31:0] _aslice_io_in_bits_T_1 = {io_branch_0_value[31:5],5'h0}; // @[Cat.scala 31:58]
- wire [31:0] _aslice_io_in_bits_T_3 = {io_branch_1_value[31:5],5'h0}; // @[Cat.scala 31:58]
- wire [31:0] _aslice_io_in_bits_T_5 = {io_branch_2_value[31:5],5'h0}; // @[Cat.scala 31:58]
- wire [31:0] _aslice_io_in_bits_T_7 = {io_branch_3_value[31:5],5'h0}; // @[Cat.scala 31:58]
- wire [31:0] _aslice_io_in_bits_T_9 = {preBranchTarget[31:5],5'h0}; // @[Cat.scala 31:58]
- wire [31:0] _aslice_io_in_bits_T_10 = req0 ? instAligned0 : instAligned1; // @[Fetch.scala 201:28]
- wire [31:0] _aslice_io_in_bits_T_11 = reqP ? _aslice_io_in_bits_T_9 : _aslice_io_in_bits_T_10; // @[Fetch.scala 200:28]
- wire [31:0] _aslice_io_in_bits_T_12 = reqB3 ? _aslice_io_in_bits_T_7 : _aslice_io_in_bits_T_11; // @[Fetch.scala 199:28]
- wire [31:0] _aslice_io_in_bits_T_13 = reqB2 ? _aslice_io_in_bits_T_5 : _aslice_io_in_bits_T_12; // @[Fetch.scala 198:28]
- wire [31:0] _aslice_io_in_bits_T_14 = reqB1 ? _aslice_io_in_bits_T_3 : _aslice_io_in_bits_T_13; // @[Fetch.scala 197:28]
- wire [4:0] readIdx = readAddr[9:5]; // @[Fetch.scala 217:25]
- wire [31:0] bits = 32'h1 << readIdx; // @[OneHot.scala 64:12]
- wire [31:0] l0validSet = readDataEn ? bits : 32'h0; // @[Fetch.scala 226:21 228:16]
- wire [31:0] l0validClr = io_iflush_valid ? 32'hffffffff : 32'h0; // @[Fetch.scala 232:26 234:16]
- wire [31:0] l0reqClr = io_iflush_valid ? 32'hffffffff : l0validSet; // @[Fetch.scala 232:26 235:16]
- wire [4:0] l0reqSet_shiftAmount = aslice_io_in_bits[9:5]; // @[Fetch.scala 239:41]
- wire [31:0] _l0reqSet_T_1 = 32'h1 << l0reqSet_shiftAmount; // @[OneHot.scala 64:12]
- wire [31:0] l0reqSet = aslice_io_in_valid & aslice_io_in_ready ? _l0reqSet_T_1 : 32'h0; // @[Fetch.scala 238:51 239:14]
- wire [31:0] _l0valid_T = l0valid | l0validSet; // @[Fetch.scala 243:25]
- wire [31:0] _l0valid_T_1 = ~l0validClr; // @[Fetch.scala 243:41]
- wire [31:0] _l0valid_T_2 = _l0valid_T & _l0valid_T_1; // @[Fetch.scala 243:39]
- wire [31:0] _l0req_T = l0req | l0reqSet; // @[Fetch.scala 247:21]
- wire [31:0] _l0req_T_1 = ~l0reqClr; // @[Fetch.scala 247:35]
- wire [31:0] _l0req_T_2 = _l0req_T & _l0req_T_1; // @[Fetch.scala 247:33]
- wire fetchEn_0 = io_inst_lanes_0_valid & io_inst_lanes_0_ready; // @[Fetch.scala 258:42]
- wire fetchEn_1 = io_inst_lanes_1_valid & io_inst_lanes_1_ready; // @[Fetch.scala 258:42]
- wire fetchEn_2 = io_inst_lanes_2_valid & io_inst_lanes_2_ready; // @[Fetch.scala 258:42]
- wire fetchEn_3 = io_inst_lanes_3_valid & io_inst_lanes_3_ready; // @[Fetch.scala 258:42]
- wire _fsel_T = ~fetchEn_3; // @[Fetch.scala 262:32]
- wire _fsel_T_1 = fetchEn_2 & ~fetchEn_3; // @[Fetch.scala 262:29]
- wire _fsel_T_2 = ~fetchEn_2; // @[Fetch.scala 263:32]
- wire _fsel_T_5 = fetchEn_1 & ~fetchEn_2 & _fsel_T; // @[Fetch.scala 263:44]
- wire _fsel_T_6 = ~fetchEn_1; // @[Fetch.scala 264:32]
- wire _fsel_T_11 = fetchEn_0 & ~fetchEn_1 & _fsel_T_2 & _fsel_T; // @[Fetch.scala 264:59]
- wire _fsel_T_18 = ~fetchEn_0 & _fsel_T_6 & _fsel_T_2 & _fsel_T; // @[Fetch.scala 265:60]
- wire [4:0] fsel = {fetchEn_3,_fsel_T_1,_fsel_T_5,_fsel_T_11,_fsel_T_18}; // @[Cat.scala 31:58]
- wire [31:0] nxtInstAddr4 = instAddr_0 + 32'h10; // @[Fetch.scala 271:34]
- wire [31:0] nxtInstAddr5 = instAddr_1 + 32'h10; // @[Fetch.scala 272:34]
- wire [31:0] nxtInstAddr6 = instAddr_2 + 32'h10; // @[Fetch.scala 273:34]
- wire [31:0] nxtInstAddr7 = instAddr_3 + 32'h10; // @[Fetch.scala 274:34]
- wire [31:0] _nxtInstAddr_0_T_1 = fsel[4] ? nxtInstAddr4 : 32'h0; // @[Fetch.scala 278:24]
- wire [31:0] _nxtInstAddr_0_T_3 = fsel[3] ? instAddr_3 : 32'h0; // @[Fetch.scala 279:24]
- wire [31:0] _nxtInstAddr_0_T_4 = _nxtInstAddr_0_T_1 | _nxtInstAddr_0_T_3; // @[Fetch.scala 278:53]
- wire [31:0] _nxtInstAddr_0_T_6 = fsel[2] ? instAddr_2 : 32'h0; // @[Fetch.scala 280:24]
- wire [31:0] _nxtInstAddr_0_T_7 = _nxtInstAddr_0_T_4 | _nxtInstAddr_0_T_6; // @[Fetch.scala 279:53]
- wire [31:0] _nxtInstAddr_0_T_9 = fsel[1] ? instAddr_1 : 32'h0; // @[Fetch.scala 281:24]
- wire [31:0] _nxtInstAddr_0_T_10 = _nxtInstAddr_0_T_7 | _nxtInstAddr_0_T_9; // @[Fetch.scala 280:53]
- wire [31:0] _nxtInstAddr_0_T_12 = fsel[0] ? instAddr_0 : 32'h0; // @[Fetch.scala 282:24]
- wire [31:0] nxtInstAddr_0 = _nxtInstAddr_0_T_10 | _nxtInstAddr_0_T_12; // @[Fetch.scala 281:53]
- wire [31:0] _nxtInstAddr_1_T_1 = fsel[4] ? nxtInstAddr5 : 32'h0; // @[Fetch.scala 284:24]
- wire [31:0] _nxtInstAddr_1_T_3 = fsel[3] ? nxtInstAddr4 : 32'h0; // @[Fetch.scala 285:24]
- wire [31:0] _nxtInstAddr_1_T_4 = _nxtInstAddr_1_T_1 | _nxtInstAddr_1_T_3; // @[Fetch.scala 284:53]
- wire [31:0] _nxtInstAddr_1_T_6 = fsel[2] ? instAddr_3 : 32'h0; // @[Fetch.scala 286:24]
- wire [31:0] _nxtInstAddr_1_T_7 = _nxtInstAddr_1_T_4 | _nxtInstAddr_1_T_6; // @[Fetch.scala 285:53]
- wire [31:0] _nxtInstAddr_1_T_9 = fsel[1] ? instAddr_2 : 32'h0; // @[Fetch.scala 287:24]
- wire [31:0] _nxtInstAddr_1_T_10 = _nxtInstAddr_1_T_7 | _nxtInstAddr_1_T_9; // @[Fetch.scala 286:53]
- wire [31:0] _nxtInstAddr_1_T_12 = fsel[0] ? instAddr_1 : 32'h0; // @[Fetch.scala 288:24]
- wire [31:0] nxtInstAddr_1 = _nxtInstAddr_1_T_10 | _nxtInstAddr_1_T_12; // @[Fetch.scala 287:53]
- wire [31:0] _nxtInstAddr_2_T_1 = fsel[4] ? nxtInstAddr6 : 32'h0; // @[Fetch.scala 290:24]
- wire [31:0] _nxtInstAddr_2_T_3 = fsel[3] ? nxtInstAddr5 : 32'h0; // @[Fetch.scala 291:24]
- wire [31:0] _nxtInstAddr_2_T_4 = _nxtInstAddr_2_T_1 | _nxtInstAddr_2_T_3; // @[Fetch.scala 290:53]
- wire [31:0] _nxtInstAddr_2_T_6 = fsel[2] ? nxtInstAddr4 : 32'h0; // @[Fetch.scala 292:24]
- wire [31:0] _nxtInstAddr_2_T_7 = _nxtInstAddr_2_T_4 | _nxtInstAddr_2_T_6; // @[Fetch.scala 291:53]
- wire [31:0] _nxtInstAddr_2_T_9 = fsel[1] ? instAddr_3 : 32'h0; // @[Fetch.scala 293:24]
- wire [31:0] _nxtInstAddr_2_T_10 = _nxtInstAddr_2_T_7 | _nxtInstAddr_2_T_9; // @[Fetch.scala 292:53]
- wire [31:0] _nxtInstAddr_2_T_12 = fsel[0] ? instAddr_2 : 32'h0; // @[Fetch.scala 294:24]
- wire [31:0] nxtInstAddr_2 = _nxtInstAddr_2_T_10 | _nxtInstAddr_2_T_12; // @[Fetch.scala 293:53]
- wire [31:0] _nxtInstAddr_3_T_1 = fsel[4] ? nxtInstAddr7 : 32'h0; // @[Fetch.scala 296:24]
- wire [31:0] _nxtInstAddr_3_T_3 = fsel[3] ? nxtInstAddr6 : 32'h0; // @[Fetch.scala 297:24]
- wire [31:0] _nxtInstAddr_3_T_4 = _nxtInstAddr_3_T_1 | _nxtInstAddr_3_T_3; // @[Fetch.scala 296:53]
- wire [31:0] _nxtInstAddr_3_T_6 = fsel[2] ? nxtInstAddr5 : 32'h0; // @[Fetch.scala 298:24]
- wire [31:0] _nxtInstAddr_3_T_7 = _nxtInstAddr_3_T_4 | _nxtInstAddr_3_T_6; // @[Fetch.scala 297:53]
- wire [31:0] _nxtInstAddr_3_T_9 = fsel[1] ? nxtInstAddr4 : 32'h0; // @[Fetch.scala 299:24]
- wire [31:0] _nxtInstAddr_3_T_10 = _nxtInstAddr_3_T_7 | _nxtInstAddr_3_T_9; // @[Fetch.scala 298:53]
- wire [31:0] _nxtInstAddr_3_T_12 = fsel[0] ? instAddr_3 : 32'h0; // @[Fetch.scala 300:24]
- wire [31:0] nxtInstAddr_3 = _nxtInstAddr_3_T_10 | _nxtInstAddr_3_T_12; // @[Fetch.scala 299:53]
- wire [4:0] nxtInstIndex0 = nxtInstAddr_0[9:5]; // @[Fetch.scala 302:37]
- wire [4:0] nxtInstIndex1 = nxtInstAddr_3[9:5]; // @[Fetch.scala 303:37]
- wire readFwd0 = readDataEn & readAddr[31:5] == instAligned0[31:5]; // @[Fetch.scala 306:18]
- wire readFwd1 = readDataEn & readAddr[31:5] == instAligned1[31:5]; // @[Fetch.scala 308:18]
- wire nxtMatch0Fwd = match0 | readFwd0; // @[Fetch.scala 310:29]
- wire nxtMatch1Fwd = match1 | readFwd1; // @[Fetch.scala 311:29]
- wire nxtMatch0 = instIndex0[0] == nxtInstIndex0[0] ? nxtMatch0Fwd : nxtMatch1Fwd; // @[Fetch.scala 314:10]
- wire nxtMatch1 = instIndex0[0] == nxtInstIndex1[0] ? nxtMatch0Fwd : nxtMatch1Fwd; // @[Fetch.scala 316:10]
- wire [255:0] nxtInstBits0_value__0 = 5'h0 == instIndex0 ? l0data_0 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__1 = 5'h1 == instIndex0 ? l0data_1 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__2 = 5'h2 == instIndex0 ? l0data_2 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__3 = 5'h3 == instIndex0 ? l0data_3 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__4 = 5'h4 == instIndex0 ? l0data_4 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__5 = 5'h5 == instIndex0 ? l0data_5 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__6 = 5'h6 == instIndex0 ? l0data_6 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__7 = 5'h7 == instIndex0 ? l0data_7 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__8 = 5'h8 == instIndex0 ? l0data_8 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__9 = 5'h9 == instIndex0 ? l0data_9 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__10 = 5'ha == instIndex0 ? l0data_10 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__11 = 5'hb == instIndex0 ? l0data_11 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__12 = 5'hc == instIndex0 ? l0data_12 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__13 = 5'hd == instIndex0 ? l0data_13 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__14 = 5'he == instIndex0 ? l0data_14 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__15 = 5'hf == instIndex0 ? l0data_15 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__16 = 5'h10 == instIndex0 ? l0data_16 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__17 = 5'h11 == instIndex0 ? l0data_17 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__18 = 5'h12 == instIndex0 ? l0data_18 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__19 = 5'h13 == instIndex0 ? l0data_19 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__20 = 5'h14 == instIndex0 ? l0data_20 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__21 = 5'h15 == instIndex0 ? l0data_21 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__22 = 5'h16 == instIndex0 ? l0data_22 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__23 = 5'h17 == instIndex0 ? l0data_23 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__24 = 5'h18 == instIndex0 ? l0data_24 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__25 = 5'h19 == instIndex0 ? l0data_25 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__26 = 5'h1a == instIndex0 ? l0data_26 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__27 = 5'h1b == instIndex0 ? l0data_27 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__28 = 5'h1c == instIndex0 ? l0data_28 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__29 = 5'h1d == instIndex0 ? l0data_29 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__30 = 5'h1e == instIndex0 ? l0data_30 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value__31 = 5'h1f == instIndex0 ? l0data_31 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits0_value_1_0 = nxtInstBits0_value__0 | nxtInstBits0_value__1; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_1 = nxtInstBits0_value__2 | nxtInstBits0_value__3; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_2 = nxtInstBits0_value__4 | nxtInstBits0_value__5; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_3 = nxtInstBits0_value__6 | nxtInstBits0_value__7; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_4 = nxtInstBits0_value__8 | nxtInstBits0_value__9; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_5 = nxtInstBits0_value__10 | nxtInstBits0_value__11; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_6 = nxtInstBits0_value__12 | nxtInstBits0_value__13; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_7 = nxtInstBits0_value__14 | nxtInstBits0_value__15; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_8 = nxtInstBits0_value__16 | nxtInstBits0_value__17; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_9 = nxtInstBits0_value__18 | nxtInstBits0_value__19; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_10 = nxtInstBits0_value__20 | nxtInstBits0_value__21; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_11 = nxtInstBits0_value__22 | nxtInstBits0_value__23; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_12 = nxtInstBits0_value__24 | nxtInstBits0_value__25; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_13 = nxtInstBits0_value__26 | nxtInstBits0_value__27; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_14 = nxtInstBits0_value__28 | nxtInstBits0_value__29; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_1_15 = nxtInstBits0_value__30 | nxtInstBits0_value__31; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_2_0 = nxtInstBits0_value_1_0 | nxtInstBits0_value_1_1; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_2_1 = nxtInstBits0_value_1_2 | nxtInstBits0_value_1_3; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_2_2 = nxtInstBits0_value_1_4 | nxtInstBits0_value_1_5; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_2_3 = nxtInstBits0_value_1_6 | nxtInstBits0_value_1_7; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_2_4 = nxtInstBits0_value_1_8 | nxtInstBits0_value_1_9; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_2_5 = nxtInstBits0_value_1_10 | nxtInstBits0_value_1_11; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_2_6 = nxtInstBits0_value_1_12 | nxtInstBits0_value_1_13; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_2_7 = nxtInstBits0_value_1_14 | nxtInstBits0_value_1_15; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_3_0 = nxtInstBits0_value_2_0 | nxtInstBits0_value_2_1; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_3_1 = nxtInstBits0_value_2_2 | nxtInstBits0_value_2_3; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_3_2 = nxtInstBits0_value_2_4 | nxtInstBits0_value_2_5; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_3_3 = nxtInstBits0_value_2_6 | nxtInstBits0_value_2_7; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_4_0 = nxtInstBits0_value_3_0 | nxtInstBits0_value_3_1; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_4_1 = nxtInstBits0_value_3_2 | nxtInstBits0_value_3_3; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0_value_5_0 = nxtInstBits0_value_4_0 | nxtInstBits0_value_4_1; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits0 = readFwd0 ? io_ibus_rdata : nxtInstBits0_value_5_0; // @[Fetch.scala 320:25]
- wire [255:0] nxtInstBits1_value__0 = 5'h0 == instIndex1 ? l0data_0 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__1 = 5'h1 == instIndex1 ? l0data_1 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__2 = 5'h2 == instIndex1 ? l0data_2 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__3 = 5'h3 == instIndex1 ? l0data_3 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__4 = 5'h4 == instIndex1 ? l0data_4 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__5 = 5'h5 == instIndex1 ? l0data_5 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__6 = 5'h6 == instIndex1 ? l0data_6 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__7 = 5'h7 == instIndex1 ? l0data_7 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__8 = 5'h8 == instIndex1 ? l0data_8 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__9 = 5'h9 == instIndex1 ? l0data_9 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__10 = 5'ha == instIndex1 ? l0data_10 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__11 = 5'hb == instIndex1 ? l0data_11 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__12 = 5'hc == instIndex1 ? l0data_12 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__13 = 5'hd == instIndex1 ? l0data_13 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__14 = 5'he == instIndex1 ? l0data_14 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__15 = 5'hf == instIndex1 ? l0data_15 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__16 = 5'h10 == instIndex1 ? l0data_16 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__17 = 5'h11 == instIndex1 ? l0data_17 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__18 = 5'h12 == instIndex1 ? l0data_18 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__19 = 5'h13 == instIndex1 ? l0data_19 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__20 = 5'h14 == instIndex1 ? l0data_20 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__21 = 5'h15 == instIndex1 ? l0data_21 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__22 = 5'h16 == instIndex1 ? l0data_22 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__23 = 5'h17 == instIndex1 ? l0data_23 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__24 = 5'h18 == instIndex1 ? l0data_24 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__25 = 5'h19 == instIndex1 ? l0data_25 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__26 = 5'h1a == instIndex1 ? l0data_26 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__27 = 5'h1b == instIndex1 ? l0data_27 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__28 = 5'h1c == instIndex1 ? l0data_28 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__29 = 5'h1d == instIndex1 ? l0data_29 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__30 = 5'h1e == instIndex1 ? l0data_30 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value__31 = 5'h1f == instIndex1 ? l0data_31 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] nxtInstBits1_value_1_0 = nxtInstBits1_value__0 | nxtInstBits1_value__1; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_1 = nxtInstBits1_value__2 | nxtInstBits1_value__3; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_2 = nxtInstBits1_value__4 | nxtInstBits1_value__5; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_3 = nxtInstBits1_value__6 | nxtInstBits1_value__7; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_4 = nxtInstBits1_value__8 | nxtInstBits1_value__9; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_5 = nxtInstBits1_value__10 | nxtInstBits1_value__11; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_6 = nxtInstBits1_value__12 | nxtInstBits1_value__13; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_7 = nxtInstBits1_value__14 | nxtInstBits1_value__15; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_8 = nxtInstBits1_value__16 | nxtInstBits1_value__17; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_9 = nxtInstBits1_value__18 | nxtInstBits1_value__19; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_10 = nxtInstBits1_value__20 | nxtInstBits1_value__21; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_11 = nxtInstBits1_value__22 | nxtInstBits1_value__23; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_12 = nxtInstBits1_value__24 | nxtInstBits1_value__25; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_13 = nxtInstBits1_value__26 | nxtInstBits1_value__27; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_14 = nxtInstBits1_value__28 | nxtInstBits1_value__29; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_1_15 = nxtInstBits1_value__30 | nxtInstBits1_value__31; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_2_0 = nxtInstBits1_value_1_0 | nxtInstBits1_value_1_1; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_2_1 = nxtInstBits1_value_1_2 | nxtInstBits1_value_1_3; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_2_2 = nxtInstBits1_value_1_4 | nxtInstBits1_value_1_5; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_2_3 = nxtInstBits1_value_1_6 | nxtInstBits1_value_1_7; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_2_4 = nxtInstBits1_value_1_8 | nxtInstBits1_value_1_9; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_2_5 = nxtInstBits1_value_1_10 | nxtInstBits1_value_1_11; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_2_6 = nxtInstBits1_value_1_12 | nxtInstBits1_value_1_13; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_2_7 = nxtInstBits1_value_1_14 | nxtInstBits1_value_1_15; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_3_0 = nxtInstBits1_value_2_0 | nxtInstBits1_value_2_1; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_3_1 = nxtInstBits1_value_2_2 | nxtInstBits1_value_2_3; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_3_2 = nxtInstBits1_value_2_4 | nxtInstBits1_value_2_5; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_3_3 = nxtInstBits1_value_2_6 | nxtInstBits1_value_2_7; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_4_0 = nxtInstBits1_value_3_0 | nxtInstBits1_value_3_1; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_4_1 = nxtInstBits1_value_3_2 | nxtInstBits1_value_3_3; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1_value_5_0 = nxtInstBits1_value_4_0 | nxtInstBits1_value_4_1; // @[Library.scala 129:37]
- wire [255:0] nxtInstBits1 = readFwd1 ? io_ibus_rdata : nxtInstBits1_value_5_0; // @[Fetch.scala 321:25]
- wire [31:0] nxtInstBits_0 = nxtInstBits0[31:0]; // @[Fetch.scala 326:39]
- wire [31:0] nxtInstBits_8 = nxtInstBits1[31:0]; // @[Fetch.scala 327:39]
- wire [31:0] nxtInstBits_1 = nxtInstBits0[63:32]; // @[Fetch.scala 326:39]
- wire [31:0] nxtInstBits_9 = nxtInstBits1[63:32]; // @[Fetch.scala 327:39]
- wire [31:0] nxtInstBits_2 = nxtInstBits0[95:64]; // @[Fetch.scala 326:39]
- wire [31:0] nxtInstBits_10 = nxtInstBits1[95:64]; // @[Fetch.scala 327:39]
- wire [31:0] nxtInstBits_3 = nxtInstBits0[127:96]; // @[Fetch.scala 326:39]
- wire [31:0] nxtInstBits_11 = nxtInstBits1[127:96]; // @[Fetch.scala 327:39]
- wire [31:0] nxtInstBits_4 = nxtInstBits0[159:128]; // @[Fetch.scala 326:39]
- wire [31:0] nxtInstBits_12 = nxtInstBits1[159:128]; // @[Fetch.scala 327:39]
- wire [31:0] nxtInstBits_5 = nxtInstBits0[191:160]; // @[Fetch.scala 326:39]
- wire [31:0] nxtInstBits_13 = nxtInstBits1[191:160]; // @[Fetch.scala 327:39]
- wire [31:0] nxtInstBits_6 = nxtInstBits0[223:192]; // @[Fetch.scala 326:39]
- wire [31:0] nxtInstBits_14 = nxtInstBits1[223:192]; // @[Fetch.scala 327:39]
- wire [31:0] nxtInstBits_7 = nxtInstBits0[255:224]; // @[Fetch.scala 326:39]
- wire [31:0] nxtInstBits_15 = nxtInstBits1[255:224]; // @[Fetch.scala 327:39]
- wire ret_bit = ~jal_bit; // @[Library.scala 326:19]
- wire ret_bit_1 = ~jal_bit_1; // @[Library.scala 326:19]
- wire ret_bit_2 = ~jal_bit_2; // @[Library.scala 326:19]
- wire ret_bit_3 = ~jal_bit_3; // @[Library.scala 326:19]
- wire ret_bit_4 = ~jal_bit_4; // @[Library.scala 326:19]
- wire ret_bit_5 = ~jal_bit_5; // @[Library.scala 326:19]
- wire ret_bit_6 = ~jal_bit_6; // @[Library.scala 326:19]
- wire ret_bit_7 = ~jal_bit_7; // @[Library.scala 326:19]
- wire ret_bit_8 = ~jal_bit_8; // @[Library.scala 326:19]
- wire ret_bit_9 = ~jal_bit_9; // @[Library.scala 326:19]
- wire ret_bit_10 = ~jal_bit_10; // @[Library.scala 326:19]
- wire ret_bit_11 = ~jal_bit_11; // @[Library.scala 326:19]
- wire ret_bit_12 = ~jal_bit_12; // @[Library.scala 326:19]
- wire ret_bit_13 = ~jal_bit_13; // @[Library.scala 326:19]
- wire ret_bit_14 = ~jal_bit_14; // @[Library.scala 326:19]
- wire ret_bit_15 = ~jal_bit_15; // @[Library.scala 326:19]
- wire _ret_T_15 = ret_bit & ret_bit_1 & ret_bit_2 & ret_bit_3 & ret_bit_4 & ret_bit_5 & ret_bit_6 & ret_bit_7 &
- ret_bit_8 & ret_bit_9 & ret_bit_10 & ret_bit_11 & ret_bit_12 & ret_bit_13 & ret_bit_14 & ret_bit_15; // @[Library.scala 327:48]
- wire _ret_T_16 = _ret_T_15 & jal_bit_16; // @[Library.scala 330:48]
- wire ret_bit_17 = ~jal_bit_17; // @[Library.scala 326:19]
- wire ret_bit_18 = ~jal_bit_18; // @[Library.scala 326:19]
- wire ret_bit_19 = ~jal_bit_19; // @[Library.scala 326:19]
- wire ret_bit_20 = ~jal_bit_20; // @[Library.scala 326:19]
- wire ret_bit_21 = ~jal_bit_21; // @[Library.scala 326:19]
- wire ret_bit_22 = ~jal_bit_22; // @[Library.scala 326:19]
- wire ret_bit_23 = ~jal_bit_23; // @[Library.scala 326:19]
- wire ret_bit_24 = ~jal_bit_24; // @[Library.scala 326:19]
- wire _ret_T_24 = _ret_T_16 & ret_bit_17 & ret_bit_18 & ret_bit_19 & ret_bit_20 & ret_bit_21 & ret_bit_22 & ret_bit_23
- & ret_bit_24; // @[Library.scala 327:48]
- wire _ret_T_26 = _ret_T_24 & jal_bit_25 & jal_bit_26; // @[Library.scala 330:48]
- wire ret_bit_28 = ~jal_bit_28; // @[Library.scala 326:19]
- wire _ret_T_28 = _ret_T_26 & jal_bit_27 & ret_bit_28; // @[Library.scala 327:48]
- wire _ret_T_31 = _ret_T_28 & jal_bit_29 & jal_bit_30 & jal_bit_31; // @[Library.scala 330:48]
- wire ret = _ret_T_31 & io_linkPort_valid; // @[Fetch.scala 420:70]
- wire bxx_bit_29 = ~jal_bit_29; // @[Library.scala 326:19]
- wire _bxx_T_4 = _jal_T_1 & jal_bit_27 & ret_bit_28 & bxx_bit_29; // @[Library.scala 327:48]
- wire _bxx_T_6 = _bxx_T_4 & jal_bit_30 & jal_bit_31; // @[Library.scala 330:48]
- wire _bxx_T_8 = _bxx_T_6 & jal_bit; // @[Fetch.scala 422:71]
- wire bxx = _bxx_T_8 & instBits_0[14:13] != 2'h1; // @[Fetch.scala 423:24]
- wire [19:0] _immbxx_T_2 = jal_bit ? 20'hfffff : 20'h0; // @[Bitwise.scala 74:12]
- wire [31:0] immbxx = {_immbxx_T_2,jal_bit_24,instBits_0[30:25],instBits_0[11:8],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] immed_4 = jal_bit_29 ? immed : immbxx; // @[Fetch.scala 426:20]
- wire [31:0] _target_T_5 = instAddr_0 + immed_4; // @[Fetch.scala 427:51]
- wire [31:0] brchTargetDe0 = ret ? io_linkPort_value : _target_T_5; // @[Fetch.scala 427:21]
- wire brchTakenDe0 = preBranchTaken0 | ret | bxx; // @[Fetch.scala 428:17]
- wire ret_bit_32 = ~jal_bit_32; // @[Library.scala 326:19]
- wire ret_bit_33 = ~jal_bit_33; // @[Library.scala 326:19]
- wire ret_bit_34 = ~jal_bit_34; // @[Library.scala 326:19]
- wire ret_bit_35 = ~jal_bit_35; // @[Library.scala 326:19]
- wire ret_bit_36 = ~jal_bit_36; // @[Library.scala 326:19]
- wire ret_bit_37 = ~jal_bit_37; // @[Library.scala 326:19]
- wire ret_bit_38 = ~jal_bit_38; // @[Library.scala 326:19]
- wire ret_bit_39 = ~jal_bit_39; // @[Library.scala 326:19]
- wire ret_bit_40 = ~jal_bit_40; // @[Library.scala 326:19]
- wire ret_bit_41 = ~jal_bit_41; // @[Library.scala 326:19]
- wire ret_bit_42 = ~jal_bit_42; // @[Library.scala 326:19]
- wire ret_bit_43 = ~jal_bit_43; // @[Library.scala 326:19]
- wire ret_bit_44 = ~jal_bit_44; // @[Library.scala 326:19]
- wire ret_bit_45 = ~jal_bit_45; // @[Library.scala 326:19]
- wire ret_bit_46 = ~jal_bit_46; // @[Library.scala 326:19]
- wire ret_bit_47 = ~jal_bit_47; // @[Library.scala 326:19]
- wire _ret_T_47 = ret_bit_32 & ret_bit_33 & ret_bit_34 & ret_bit_35 & ret_bit_36 & ret_bit_37 & ret_bit_38 &
- ret_bit_39 & ret_bit_40 & ret_bit_41 & ret_bit_42 & ret_bit_43 & ret_bit_44 & ret_bit_45 & ret_bit_46 & ret_bit_47; // @[Library.scala 327:48]
- wire _ret_T_48 = _ret_T_47 & jal_bit_48; // @[Library.scala 330:48]
- wire ret_bit_49 = ~jal_bit_49; // @[Library.scala 326:19]
- wire ret_bit_50 = ~jal_bit_50; // @[Library.scala 326:19]
- wire ret_bit_51 = ~jal_bit_51; // @[Library.scala 326:19]
- wire ret_bit_52 = ~jal_bit_52; // @[Library.scala 326:19]
- wire ret_bit_53 = ~jal_bit_53; // @[Library.scala 326:19]
- wire ret_bit_54 = ~jal_bit_54; // @[Library.scala 326:19]
- wire ret_bit_55 = ~jal_bit_55; // @[Library.scala 326:19]
- wire ret_bit_56 = ~jal_bit_56; // @[Library.scala 326:19]
- wire _ret_T_56 = _ret_T_48 & ret_bit_49 & ret_bit_50 & ret_bit_51 & ret_bit_52 & ret_bit_53 & ret_bit_54 & ret_bit_55
- & ret_bit_56; // @[Library.scala 327:48]
- wire _ret_T_58 = _ret_T_56 & jal_bit_57 & jal_bit_58; // @[Library.scala 330:48]
- wire ret_bit_60 = ~jal_bit_60; // @[Library.scala 326:19]
- wire _ret_T_60 = _ret_T_58 & jal_bit_59 & ret_bit_60; // @[Library.scala 327:48]
- wire _ret_T_63 = _ret_T_60 & jal_bit_61 & jal_bit_62 & jal_bit_63; // @[Library.scala 330:48]
- wire ret_1 = _ret_T_63 & io_linkPort_valid; // @[Fetch.scala 420:70]
- wire bxx_bit_61 = ~jal_bit_61; // @[Library.scala 326:19]
- wire _bxx_T_15 = _jal_T_7 & jal_bit_59 & ret_bit_60 & bxx_bit_61; // @[Library.scala 327:48]
- wire _bxx_T_17 = _bxx_T_15 & jal_bit_62 & jal_bit_63; // @[Library.scala 330:48]
- wire _bxx_T_19 = _bxx_T_17 & jal_bit_32; // @[Fetch.scala 422:71]
- wire bxx_1 = _bxx_T_19 & instBits_1[14:13] != 2'h1; // @[Fetch.scala 423:24]
- wire [19:0] _immbxx_T_8 = jal_bit_32 ? 20'hfffff : 20'h0; // @[Bitwise.scala 74:12]
- wire [31:0] immbxx_1 = {_immbxx_T_8,jal_bit_56,instBits_1[30:25],instBits_1[11:8],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] immed_5 = jal_bit_61 ? immed_1 : immbxx_1; // @[Fetch.scala 426:20]
- wire [31:0] _target_T_7 = instAddr_1 + immed_5; // @[Fetch.scala 427:51]
- wire [31:0] brchTargetDe1 = ret_1 ? io_linkPort_value : _target_T_7; // @[Fetch.scala 427:21]
- wire brchTakenDe1 = preBranchTaken1 | ret_1 | bxx_1; // @[Fetch.scala 428:17]
- wire ret_bit_64 = ~jal_bit_64; // @[Library.scala 326:19]
- wire ret_bit_65 = ~jal_bit_65; // @[Library.scala 326:19]
- wire ret_bit_66 = ~jal_bit_66; // @[Library.scala 326:19]
- wire ret_bit_67 = ~jal_bit_67; // @[Library.scala 326:19]
- wire ret_bit_68 = ~jal_bit_68; // @[Library.scala 326:19]
- wire ret_bit_69 = ~jal_bit_69; // @[Library.scala 326:19]
- wire ret_bit_70 = ~jal_bit_70; // @[Library.scala 326:19]
- wire ret_bit_71 = ~jal_bit_71; // @[Library.scala 326:19]
- wire ret_bit_72 = ~jal_bit_72; // @[Library.scala 326:19]
- wire ret_bit_73 = ~jal_bit_73; // @[Library.scala 326:19]
- wire ret_bit_74 = ~jal_bit_74; // @[Library.scala 326:19]
- wire ret_bit_75 = ~jal_bit_75; // @[Library.scala 326:19]
- wire ret_bit_76 = ~jal_bit_76; // @[Library.scala 326:19]
- wire ret_bit_77 = ~jal_bit_77; // @[Library.scala 326:19]
- wire ret_bit_78 = ~jal_bit_78; // @[Library.scala 326:19]
- wire ret_bit_79 = ~jal_bit_79; // @[Library.scala 326:19]
- wire _ret_T_79 = ret_bit_64 & ret_bit_65 & ret_bit_66 & ret_bit_67 & ret_bit_68 & ret_bit_69 & ret_bit_70 &
- ret_bit_71 & ret_bit_72 & ret_bit_73 & ret_bit_74 & ret_bit_75 & ret_bit_76 & ret_bit_77 & ret_bit_78 & ret_bit_79; // @[Library.scala 327:48]
- wire _ret_T_80 = _ret_T_79 & jal_bit_80; // @[Library.scala 330:48]
- wire ret_bit_81 = ~jal_bit_81; // @[Library.scala 326:19]
- wire ret_bit_82 = ~jal_bit_82; // @[Library.scala 326:19]
- wire ret_bit_83 = ~jal_bit_83; // @[Library.scala 326:19]
- wire ret_bit_84 = ~jal_bit_84; // @[Library.scala 326:19]
- wire ret_bit_85 = ~jal_bit_85; // @[Library.scala 326:19]
- wire ret_bit_86 = ~jal_bit_86; // @[Library.scala 326:19]
- wire ret_bit_87 = ~jal_bit_87; // @[Library.scala 326:19]
- wire ret_bit_88 = ~jal_bit_88; // @[Library.scala 326:19]
- wire _ret_T_88 = _ret_T_80 & ret_bit_81 & ret_bit_82 & ret_bit_83 & ret_bit_84 & ret_bit_85 & ret_bit_86 & ret_bit_87
- & ret_bit_88; // @[Library.scala 327:48]
- wire _ret_T_90 = _ret_T_88 & jal_bit_89 & jal_bit_90; // @[Library.scala 330:48]
- wire ret_bit_92 = ~jal_bit_92; // @[Library.scala 326:19]
- wire _ret_T_92 = _ret_T_90 & jal_bit_91 & ret_bit_92; // @[Library.scala 327:48]
- wire _ret_T_95 = _ret_T_92 & jal_bit_93 & jal_bit_94 & jal_bit_95; // @[Library.scala 330:48]
- wire ret_2 = _ret_T_95 & io_linkPort_valid; // @[Fetch.scala 420:70]
- wire bxx_bit_93 = ~jal_bit_93; // @[Library.scala 326:19]
- wire _bxx_T_26 = _jal_T_13 & jal_bit_91 & ret_bit_92 & bxx_bit_93; // @[Library.scala 327:48]
- wire _bxx_T_28 = _bxx_T_26 & jal_bit_94 & jal_bit_95; // @[Library.scala 330:48]
- wire _bxx_T_30 = _bxx_T_28 & jal_bit_64; // @[Fetch.scala 422:71]
- wire bxx_2 = _bxx_T_30 & instBits_2[14:13] != 2'h1; // @[Fetch.scala 423:24]
- wire [19:0] _immbxx_T_14 = jal_bit_64 ? 20'hfffff : 20'h0; // @[Bitwise.scala 74:12]
- wire [31:0] immbxx_2 = {_immbxx_T_14,jal_bit_88,instBits_2[30:25],instBits_2[11:8],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] immed_6 = jal_bit_93 ? immed_2 : immbxx_2; // @[Fetch.scala 426:20]
- wire [31:0] _target_T_9 = instAddr_2 + immed_6; // @[Fetch.scala 427:51]
- wire [31:0] brchTargetDe2 = ret_2 ? io_linkPort_value : _target_T_9; // @[Fetch.scala 427:21]
- wire brchTakenDe2 = preBranchTaken2 | ret_2 | bxx_2; // @[Fetch.scala 428:17]
- wire ret_bit_96 = ~jal_bit_96; // @[Library.scala 326:19]
- wire ret_bit_97 = ~jal_bit_97; // @[Library.scala 326:19]
- wire ret_bit_98 = ~jal_bit_98; // @[Library.scala 326:19]
- wire ret_bit_99 = ~jal_bit_99; // @[Library.scala 326:19]
- wire ret_bit_100 = ~jal_bit_100; // @[Library.scala 326:19]
- wire ret_bit_101 = ~jal_bit_101; // @[Library.scala 326:19]
- wire ret_bit_102 = ~jal_bit_102; // @[Library.scala 326:19]
- wire ret_bit_103 = ~jal_bit_103; // @[Library.scala 326:19]
- wire ret_bit_104 = ~jal_bit_104; // @[Library.scala 326:19]
- wire ret_bit_105 = ~jal_bit_105; // @[Library.scala 326:19]
- wire ret_bit_106 = ~jal_bit_106; // @[Library.scala 326:19]
- wire ret_bit_107 = ~jal_bit_107; // @[Library.scala 326:19]
- wire ret_bit_108 = ~jal_bit_108; // @[Library.scala 326:19]
- wire ret_bit_109 = ~jal_bit_109; // @[Library.scala 326:19]
- wire ret_bit_110 = ~jal_bit_110; // @[Library.scala 326:19]
- wire ret_bit_111 = ~jal_bit_111; // @[Library.scala 326:19]
- wire _ret_T_111 = ret_bit_96 & ret_bit_97 & ret_bit_98 & ret_bit_99 & ret_bit_100 & ret_bit_101 & ret_bit_102 &
- ret_bit_103 & ret_bit_104 & ret_bit_105 & ret_bit_106 & ret_bit_107 & ret_bit_108 & ret_bit_109 & ret_bit_110 &
- ret_bit_111; // @[Library.scala 327:48]
- wire _ret_T_112 = _ret_T_111 & jal_bit_112; // @[Library.scala 330:48]
- wire ret_bit_113 = ~jal_bit_113; // @[Library.scala 326:19]
- wire ret_bit_114 = ~jal_bit_114; // @[Library.scala 326:19]
- wire ret_bit_115 = ~jal_bit_115; // @[Library.scala 326:19]
- wire ret_bit_116 = ~jal_bit_116; // @[Library.scala 326:19]
- wire ret_bit_117 = ~jal_bit_117; // @[Library.scala 326:19]
- wire ret_bit_118 = ~jal_bit_118; // @[Library.scala 326:19]
- wire ret_bit_119 = ~jal_bit_119; // @[Library.scala 326:19]
- wire ret_bit_120 = ~jal_bit_120; // @[Library.scala 326:19]
- wire _ret_T_120 = _ret_T_112 & ret_bit_113 & ret_bit_114 & ret_bit_115 & ret_bit_116 & ret_bit_117 & ret_bit_118 &
- ret_bit_119 & ret_bit_120; // @[Library.scala 327:48]
- wire _ret_T_122 = _ret_T_120 & jal_bit_121 & jal_bit_122; // @[Library.scala 330:48]
- wire ret_bit_124 = ~jal_bit_124; // @[Library.scala 326:19]
- wire _ret_T_124 = _ret_T_122 & jal_bit_123 & ret_bit_124; // @[Library.scala 327:48]
- wire _ret_T_127 = _ret_T_124 & jal_bit_125 & jal_bit_126 & jal_bit_127; // @[Library.scala 330:48]
- wire ret_3 = _ret_T_127 & io_linkPort_valid; // @[Fetch.scala 420:70]
- wire bxx_bit_125 = ~jal_bit_125; // @[Library.scala 326:19]
- wire _bxx_T_37 = _jal_T_19 & jal_bit_123 & ret_bit_124 & bxx_bit_125; // @[Library.scala 327:48]
- wire _bxx_T_39 = _bxx_T_37 & jal_bit_126 & jal_bit_127; // @[Library.scala 330:48]
- wire _bxx_T_41 = _bxx_T_39 & jal_bit_96; // @[Fetch.scala 422:71]
- wire bxx_3 = _bxx_T_41 & instBits_3[14:13] != 2'h1; // @[Fetch.scala 423:24]
- wire [19:0] _immbxx_T_20 = jal_bit_96 ? 20'hfffff : 20'h0; // @[Bitwise.scala 74:12]
- wire [31:0] immbxx_3 = {_immbxx_T_20,jal_bit_120,instBits_3[30:25],instBits_3[11:8],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] immed_7 = jal_bit_125 ? immed_3 : immbxx_3; // @[Fetch.scala 426:20]
- wire [31:0] _target_T_11 = instAddr_3 + immed_7; // @[Fetch.scala 427:51]
- wire [31:0] brchTargetDe3 = ret_3 ? io_linkPort_value : _target_T_11; // @[Fetch.scala 427:21]
- wire brchTakenDe3 = preBranchTaken3 | ret_3 | bxx_3; // @[Fetch.scala 428:17]
- wire _brchTakenDeOr_T_3 = fetchEn_1 & brchTakenDe1; // @[Fetch.scala 438:56]
- wire _brchTakenDeOr_T_4 = fetchEn_0 & brchTakenDe0 | _brchTakenDeOr_T_3; // @[Fetch.scala 437:72]
- wire _brchTakenDeOr_T_6 = fetchEn_2 & brchTakenDe2; // @[Fetch.scala 439:56]
- wire _brchTakenDeOr_T_7 = _brchTakenDeOr_T_4 | _brchTakenDeOr_T_6; // @[Fetch.scala 438:72]
- wire _brchTakenDeOr_T_9 = fetchEn_3 & brchTakenDe3; // @[Fetch.scala 440:56]
- wire brchTakenDe = _brchTakenDeOr_T_7 | _brchTakenDeOr_T_9; // @[Fetch.scala 439:72]
- wire [31:0] _brchTargetDe_T = brchTakenDe2 ? brchTargetDe2 : brchTargetDe3; // @[Fetch.scala 444:25]
- wire [31:0] _brchTargetDe_T_1 = brchTakenDe1 ? brchTargetDe1 : _brchTargetDe_T; // @[Fetch.scala 443:25]
- wire [31:0] brchTargetDe = brchTakenDe0 ? brchTargetDe0 : _brchTargetDe_T_1; // @[Fetch.scala 442:25]
- wire [31:0] brchAddrDe_1 = brchTargetDe + 32'h4; // @[Fetch.scala 334:30]
- wire [31:0] brchAddrDe_2 = brchTargetDe + 32'h8; // @[Fetch.scala 335:30]
- wire [31:0] brchAddrDe_3 = brchTargetDe + 32'hc; // @[Fetch.scala 336:30]
- wire [31:0] _match0_T_2 = l0valid >> brchTargetDe[9:5]; // @[Fetch.scala 338:25]
- wire [21:0] match0_value__0 = 5'h0 == brchTargetDe[9:5] ? l0tag_0 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__1 = 5'h1 == brchTargetDe[9:5] ? l0tag_1 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__2 = 5'h2 == brchTargetDe[9:5] ? l0tag_2 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__3 = 5'h3 == brchTargetDe[9:5] ? l0tag_3 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__4 = 5'h4 == brchTargetDe[9:5] ? l0tag_4 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__5 = 5'h5 == brchTargetDe[9:5] ? l0tag_5 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__6 = 5'h6 == brchTargetDe[9:5] ? l0tag_6 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__7 = 5'h7 == brchTargetDe[9:5] ? l0tag_7 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__8 = 5'h8 == brchTargetDe[9:5] ? l0tag_8 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__9 = 5'h9 == brchTargetDe[9:5] ? l0tag_9 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__10 = 5'ha == brchTargetDe[9:5] ? l0tag_10 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__11 = 5'hb == brchTargetDe[9:5] ? l0tag_11 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__12 = 5'hc == brchTargetDe[9:5] ? l0tag_12 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__13 = 5'hd == brchTargetDe[9:5] ? l0tag_13 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__14 = 5'he == brchTargetDe[9:5] ? l0tag_14 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__15 = 5'hf == brchTargetDe[9:5] ? l0tag_15 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__16 = 5'h10 == brchTargetDe[9:5] ? l0tag_16 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__17 = 5'h11 == brchTargetDe[9:5] ? l0tag_17 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__18 = 5'h12 == brchTargetDe[9:5] ? l0tag_18 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__19 = 5'h13 == brchTargetDe[9:5] ? l0tag_19 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__20 = 5'h14 == brchTargetDe[9:5] ? l0tag_20 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__21 = 5'h15 == brchTargetDe[9:5] ? l0tag_21 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__22 = 5'h16 == brchTargetDe[9:5] ? l0tag_22 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__23 = 5'h17 == brchTargetDe[9:5] ? l0tag_23 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__24 = 5'h18 == brchTargetDe[9:5] ? l0tag_24 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__25 = 5'h19 == brchTargetDe[9:5] ? l0tag_25 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__26 = 5'h1a == brchTargetDe[9:5] ? l0tag_26 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__27 = 5'h1b == brchTargetDe[9:5] ? l0tag_27 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__28 = 5'h1c == brchTargetDe[9:5] ? l0tag_28 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__29 = 5'h1d == brchTargetDe[9:5] ? l0tag_29 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__30 = 5'h1e == brchTargetDe[9:5] ? l0tag_30 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value__31 = 5'h1f == brchTargetDe[9:5] ? l0tag_31 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_1_0 = match0_value__0 | match0_value__1; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_1 = match0_value__2 | match0_value__3; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_2 = match0_value__4 | match0_value__5; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_3 = match0_value__6 | match0_value__7; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_4 = match0_value__8 | match0_value__9; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_5 = match0_value__10 | match0_value__11; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_6 = match0_value__12 | match0_value__13; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_7 = match0_value__14 | match0_value__15; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_8 = match0_value__16 | match0_value__17; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_9 = match0_value__18 | match0_value__19; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_10 = match0_value__20 | match0_value__21; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_11 = match0_value__22 | match0_value__23; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_12 = match0_value__24 | match0_value__25; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_13 = match0_value__26 | match0_value__27; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_14 = match0_value__28 | match0_value__29; // @[Library.scala 129:37]
- wire [21:0] match0_value_1_15 = match0_value__30 | match0_value__31; // @[Library.scala 129:37]
- wire [21:0] match0_value_2_0 = match0_value_1_0 | match0_value_1_1; // @[Library.scala 129:37]
- wire [21:0] match0_value_2_1 = match0_value_1_2 | match0_value_1_3; // @[Library.scala 129:37]
- wire [21:0] match0_value_2_2 = match0_value_1_4 | match0_value_1_5; // @[Library.scala 129:37]
- wire [21:0] match0_value_2_3 = match0_value_1_6 | match0_value_1_7; // @[Library.scala 129:37]
- wire [21:0] match0_value_2_4 = match0_value_1_8 | match0_value_1_9; // @[Library.scala 129:37]
- wire [21:0] match0_value_2_5 = match0_value_1_10 | match0_value_1_11; // @[Library.scala 129:37]
- wire [21:0] match0_value_2_6 = match0_value_1_12 | match0_value_1_13; // @[Library.scala 129:37]
- wire [21:0] match0_value_2_7 = match0_value_1_14 | match0_value_1_15; // @[Library.scala 129:37]
- wire [21:0] match0_value_3_0 = match0_value_2_0 | match0_value_2_1; // @[Library.scala 129:37]
- wire [21:0] match0_value_3_1 = match0_value_2_2 | match0_value_2_3; // @[Library.scala 129:37]
- wire [21:0] match0_value_3_2 = match0_value_2_4 | match0_value_2_5; // @[Library.scala 129:37]
- wire [21:0] match0_value_3_3 = match0_value_2_6 | match0_value_2_7; // @[Library.scala 129:37]
- wire [21:0] match0_value_4_0 = match0_value_3_0 | match0_value_3_1; // @[Library.scala 129:37]
- wire [21:0] match0_value_4_1 = match0_value_3_2 | match0_value_3_3; // @[Library.scala 129:37]
- wire [21:0] match0_value_5_0 = match0_value_4_0 | match0_value_4_1; // @[Library.scala 129:37]
- wire _match0_T_6 = brchTargetDe[31:10] == match0_value_5_0; // @[Fetch.scala 339:32]
- wire match0_1 = _match0_T_2[0] & _match0_T_6; // @[Fetch.scala 338:54]
- wire [31:0] _match1_T_2 = l0valid >> brchAddrDe_3[9:5]; // @[Fetch.scala 340:25]
- wire [21:0] match1_value__0 = 5'h0 == brchAddrDe_3[9:5] ? l0tag_0 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__1 = 5'h1 == brchAddrDe_3[9:5] ? l0tag_1 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__2 = 5'h2 == brchAddrDe_3[9:5] ? l0tag_2 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__3 = 5'h3 == brchAddrDe_3[9:5] ? l0tag_3 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__4 = 5'h4 == brchAddrDe_3[9:5] ? l0tag_4 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__5 = 5'h5 == brchAddrDe_3[9:5] ? l0tag_5 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__6 = 5'h6 == brchAddrDe_3[9:5] ? l0tag_6 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__7 = 5'h7 == brchAddrDe_3[9:5] ? l0tag_7 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__8 = 5'h8 == brchAddrDe_3[9:5] ? l0tag_8 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__9 = 5'h9 == brchAddrDe_3[9:5] ? l0tag_9 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__10 = 5'ha == brchAddrDe_3[9:5] ? l0tag_10 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__11 = 5'hb == brchAddrDe_3[9:5] ? l0tag_11 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__12 = 5'hc == brchAddrDe_3[9:5] ? l0tag_12 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__13 = 5'hd == brchAddrDe_3[9:5] ? l0tag_13 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__14 = 5'he == brchAddrDe_3[9:5] ? l0tag_14 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__15 = 5'hf == brchAddrDe_3[9:5] ? l0tag_15 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__16 = 5'h10 == brchAddrDe_3[9:5] ? l0tag_16 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__17 = 5'h11 == brchAddrDe_3[9:5] ? l0tag_17 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__18 = 5'h12 == brchAddrDe_3[9:5] ? l0tag_18 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__19 = 5'h13 == brchAddrDe_3[9:5] ? l0tag_19 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__20 = 5'h14 == brchAddrDe_3[9:5] ? l0tag_20 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__21 = 5'h15 == brchAddrDe_3[9:5] ? l0tag_21 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__22 = 5'h16 == brchAddrDe_3[9:5] ? l0tag_22 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__23 = 5'h17 == brchAddrDe_3[9:5] ? l0tag_23 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__24 = 5'h18 == brchAddrDe_3[9:5] ? l0tag_24 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__25 = 5'h19 == brchAddrDe_3[9:5] ? l0tag_25 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__26 = 5'h1a == brchAddrDe_3[9:5] ? l0tag_26 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__27 = 5'h1b == brchAddrDe_3[9:5] ? l0tag_27 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__28 = 5'h1c == brchAddrDe_3[9:5] ? l0tag_28 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__29 = 5'h1d == brchAddrDe_3[9:5] ? l0tag_29 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__30 = 5'h1e == brchAddrDe_3[9:5] ? l0tag_30 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value__31 = 5'h1f == brchAddrDe_3[9:5] ? l0tag_31 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_1_0 = match1_value__0 | match1_value__1; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_1 = match1_value__2 | match1_value__3; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_2 = match1_value__4 | match1_value__5; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_3 = match1_value__6 | match1_value__7; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_4 = match1_value__8 | match1_value__9; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_5 = match1_value__10 | match1_value__11; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_6 = match1_value__12 | match1_value__13; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_7 = match1_value__14 | match1_value__15; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_8 = match1_value__16 | match1_value__17; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_9 = match1_value__18 | match1_value__19; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_10 = match1_value__20 | match1_value__21; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_11 = match1_value__22 | match1_value__23; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_12 = match1_value__24 | match1_value__25; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_13 = match1_value__26 | match1_value__27; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_14 = match1_value__28 | match1_value__29; // @[Library.scala 129:37]
- wire [21:0] match1_value_1_15 = match1_value__30 | match1_value__31; // @[Library.scala 129:37]
- wire [21:0] match1_value_2_0 = match1_value_1_0 | match1_value_1_1; // @[Library.scala 129:37]
- wire [21:0] match1_value_2_1 = match1_value_1_2 | match1_value_1_3; // @[Library.scala 129:37]
- wire [21:0] match1_value_2_2 = match1_value_1_4 | match1_value_1_5; // @[Library.scala 129:37]
- wire [21:0] match1_value_2_3 = match1_value_1_6 | match1_value_1_7; // @[Library.scala 129:37]
- wire [21:0] match1_value_2_4 = match1_value_1_8 | match1_value_1_9; // @[Library.scala 129:37]
- wire [21:0] match1_value_2_5 = match1_value_1_10 | match1_value_1_11; // @[Library.scala 129:37]
- wire [21:0] match1_value_2_6 = match1_value_1_12 | match1_value_1_13; // @[Library.scala 129:37]
- wire [21:0] match1_value_2_7 = match1_value_1_14 | match1_value_1_15; // @[Library.scala 129:37]
- wire [21:0] match1_value_3_0 = match1_value_2_0 | match1_value_2_1; // @[Library.scala 129:37]
- wire [21:0] match1_value_3_1 = match1_value_2_2 | match1_value_2_3; // @[Library.scala 129:37]
- wire [21:0] match1_value_3_2 = match1_value_2_4 | match1_value_2_5; // @[Library.scala 129:37]
- wire [21:0] match1_value_3_3 = match1_value_2_6 | match1_value_2_7; // @[Library.scala 129:37]
- wire [21:0] match1_value_4_0 = match1_value_3_0 | match1_value_3_1; // @[Library.scala 129:37]
- wire [21:0] match1_value_4_1 = match1_value_3_2 | match1_value_3_3; // @[Library.scala 129:37]
- wire [21:0] match1_value_5_0 = match1_value_4_0 | match1_value_4_1; // @[Library.scala 129:37]
- wire _match1_T_6 = brchAddrDe_3[31:10] == match1_value_5_0; // @[Fetch.scala 341:32]
- wire match1_1 = _match1_T_2[0] & _match1_T_6; // @[Fetch.scala 340:54]
- wire vvalid__1 = brchTargetDe[4:2] <= 3'h6 ? match0_1 : match1_1; // @[Fetch.scala 344:29]
- wire vvalid__2 = brchTargetDe[4:2] <= 3'h5 ? match0_1 : match1_1; // @[Fetch.scala 345:29]
- wire vvalid__3 = brchTargetDe[4:2] <= 3'h4 ? match0_1 : match1_1; // @[Fetch.scala 346:29]
- wire [255:0] muxbits0_value__0 = 5'h0 == brchTargetDe[9:5] ? l0data_0 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__1 = 5'h1 == brchTargetDe[9:5] ? l0data_1 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__2 = 5'h2 == brchTargetDe[9:5] ? l0data_2 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__3 = 5'h3 == brchTargetDe[9:5] ? l0data_3 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__4 = 5'h4 == brchTargetDe[9:5] ? l0data_4 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__5 = 5'h5 == brchTargetDe[9:5] ? l0data_5 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__6 = 5'h6 == brchTargetDe[9:5] ? l0data_6 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__7 = 5'h7 == brchTargetDe[9:5] ? l0data_7 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__8 = 5'h8 == brchTargetDe[9:5] ? l0data_8 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__9 = 5'h9 == brchTargetDe[9:5] ? l0data_9 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__10 = 5'ha == brchTargetDe[9:5] ? l0data_10 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__11 = 5'hb == brchTargetDe[9:5] ? l0data_11 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__12 = 5'hc == brchTargetDe[9:5] ? l0data_12 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__13 = 5'hd == brchTargetDe[9:5] ? l0data_13 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__14 = 5'he == brchTargetDe[9:5] ? l0data_14 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__15 = 5'hf == brchTargetDe[9:5] ? l0data_15 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__16 = 5'h10 == brchTargetDe[9:5] ? l0data_16 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__17 = 5'h11 == brchTargetDe[9:5] ? l0data_17 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__18 = 5'h12 == brchTargetDe[9:5] ? l0data_18 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__19 = 5'h13 == brchTargetDe[9:5] ? l0data_19 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__20 = 5'h14 == brchTargetDe[9:5] ? l0data_20 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__21 = 5'h15 == brchTargetDe[9:5] ? l0data_21 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__22 = 5'h16 == brchTargetDe[9:5] ? l0data_22 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__23 = 5'h17 == brchTargetDe[9:5] ? l0data_23 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__24 = 5'h18 == brchTargetDe[9:5] ? l0data_24 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__25 = 5'h19 == brchTargetDe[9:5] ? l0data_25 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__26 = 5'h1a == brchTargetDe[9:5] ? l0data_26 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__27 = 5'h1b == brchTargetDe[9:5] ? l0data_27 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__28 = 5'h1c == brchTargetDe[9:5] ? l0data_28 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__29 = 5'h1d == brchTargetDe[9:5] ? l0data_29 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__30 = 5'h1e == brchTargetDe[9:5] ? l0data_30 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value__31 = 5'h1f == brchTargetDe[9:5] ? l0data_31 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_1_0 = muxbits0_value__0 | muxbits0_value__1; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_1 = muxbits0_value__2 | muxbits0_value__3; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_2 = muxbits0_value__4 | muxbits0_value__5; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_3 = muxbits0_value__6 | muxbits0_value__7; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_4 = muxbits0_value__8 | muxbits0_value__9; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_5 = muxbits0_value__10 | muxbits0_value__11; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_6 = muxbits0_value__12 | muxbits0_value__13; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_7 = muxbits0_value__14 | muxbits0_value__15; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_8 = muxbits0_value__16 | muxbits0_value__17; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_9 = muxbits0_value__18 | muxbits0_value__19; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_10 = muxbits0_value__20 | muxbits0_value__21; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_11 = muxbits0_value__22 | muxbits0_value__23; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_12 = muxbits0_value__24 | muxbits0_value__25; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_13 = muxbits0_value__26 | muxbits0_value__27; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_14 = muxbits0_value__28 | muxbits0_value__29; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_1_15 = muxbits0_value__30 | muxbits0_value__31; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_2_0 = muxbits0_value_1_0 | muxbits0_value_1_1; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_2_1 = muxbits0_value_1_2 | muxbits0_value_1_3; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_2_2 = muxbits0_value_1_4 | muxbits0_value_1_5; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_2_3 = muxbits0_value_1_6 | muxbits0_value_1_7; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_2_4 = muxbits0_value_1_8 | muxbits0_value_1_9; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_2_5 = muxbits0_value_1_10 | muxbits0_value_1_11; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_2_6 = muxbits0_value_1_12 | muxbits0_value_1_13; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_2_7 = muxbits0_value_1_14 | muxbits0_value_1_15; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_3_0 = muxbits0_value_2_0 | muxbits0_value_2_1; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_3_1 = muxbits0_value_2_2 | muxbits0_value_2_3; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_3_2 = muxbits0_value_2_4 | muxbits0_value_2_5; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_3_3 = muxbits0_value_2_6 | muxbits0_value_2_7; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_4_0 = muxbits0_value_3_0 | muxbits0_value_3_1; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_4_1 = muxbits0_value_3_2 | muxbits0_value_3_3; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_5_0 = muxbits0_value_4_0 | muxbits0_value_4_1; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value__0 = 5'h0 == brchAddrDe_3[9:5] ? l0data_0 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__1 = 5'h1 == brchAddrDe_3[9:5] ? l0data_1 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__2 = 5'h2 == brchAddrDe_3[9:5] ? l0data_2 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__3 = 5'h3 == brchAddrDe_3[9:5] ? l0data_3 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__4 = 5'h4 == brchAddrDe_3[9:5] ? l0data_4 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__5 = 5'h5 == brchAddrDe_3[9:5] ? l0data_5 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__6 = 5'h6 == brchAddrDe_3[9:5] ? l0data_6 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__7 = 5'h7 == brchAddrDe_3[9:5] ? l0data_7 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__8 = 5'h8 == brchAddrDe_3[9:5] ? l0data_8 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__9 = 5'h9 == brchAddrDe_3[9:5] ? l0data_9 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__10 = 5'ha == brchAddrDe_3[9:5] ? l0data_10 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__11 = 5'hb == brchAddrDe_3[9:5] ? l0data_11 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__12 = 5'hc == brchAddrDe_3[9:5] ? l0data_12 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__13 = 5'hd == brchAddrDe_3[9:5] ? l0data_13 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__14 = 5'he == brchAddrDe_3[9:5] ? l0data_14 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__15 = 5'hf == brchAddrDe_3[9:5] ? l0data_15 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__16 = 5'h10 == brchAddrDe_3[9:5] ? l0data_16 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__17 = 5'h11 == brchAddrDe_3[9:5] ? l0data_17 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__18 = 5'h12 == brchAddrDe_3[9:5] ? l0data_18 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__19 = 5'h13 == brchAddrDe_3[9:5] ? l0data_19 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__20 = 5'h14 == brchAddrDe_3[9:5] ? l0data_20 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__21 = 5'h15 == brchAddrDe_3[9:5] ? l0data_21 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__22 = 5'h16 == brchAddrDe_3[9:5] ? l0data_22 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__23 = 5'h17 == brchAddrDe_3[9:5] ? l0data_23 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__24 = 5'h18 == brchAddrDe_3[9:5] ? l0data_24 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__25 = 5'h19 == brchAddrDe_3[9:5] ? l0data_25 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__26 = 5'h1a == brchAddrDe_3[9:5] ? l0data_26 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__27 = 5'h1b == brchAddrDe_3[9:5] ? l0data_27 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__28 = 5'h1c == brchAddrDe_3[9:5] ? l0data_28 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__29 = 5'h1d == brchAddrDe_3[9:5] ? l0data_29 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__30 = 5'h1e == brchAddrDe_3[9:5] ? l0data_30 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value__31 = 5'h1f == brchAddrDe_3[9:5] ? l0data_31 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_1_0 = muxbits1_value__0 | muxbits1_value__1; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_1 = muxbits1_value__2 | muxbits1_value__3; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_2 = muxbits1_value__4 | muxbits1_value__5; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_3 = muxbits1_value__6 | muxbits1_value__7; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_4 = muxbits1_value__8 | muxbits1_value__9; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_5 = muxbits1_value__10 | muxbits1_value__11; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_6 = muxbits1_value__12 | muxbits1_value__13; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_7 = muxbits1_value__14 | muxbits1_value__15; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_8 = muxbits1_value__16 | muxbits1_value__17; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_9 = muxbits1_value__18 | muxbits1_value__19; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_10 = muxbits1_value__20 | muxbits1_value__21; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_11 = muxbits1_value__22 | muxbits1_value__23; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_12 = muxbits1_value__24 | muxbits1_value__25; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_13 = muxbits1_value__26 | muxbits1_value__27; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_14 = muxbits1_value__28 | muxbits1_value__29; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_1_15 = muxbits1_value__30 | muxbits1_value__31; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_2_0 = muxbits1_value_1_0 | muxbits1_value_1_1; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_2_1 = muxbits1_value_1_2 | muxbits1_value_1_3; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_2_2 = muxbits1_value_1_4 | muxbits1_value_1_5; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_2_3 = muxbits1_value_1_6 | muxbits1_value_1_7; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_2_4 = muxbits1_value_1_8 | muxbits1_value_1_9; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_2_5 = muxbits1_value_1_10 | muxbits1_value_1_11; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_2_6 = muxbits1_value_1_12 | muxbits1_value_1_13; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_2_7 = muxbits1_value_1_14 | muxbits1_value_1_15; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_3_0 = muxbits1_value_2_0 | muxbits1_value_2_1; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_3_1 = muxbits1_value_2_2 | muxbits1_value_2_3; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_3_2 = muxbits1_value_2_4 | muxbits1_value_2_5; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_3_3 = muxbits1_value_2_6 | muxbits1_value_2_7; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_4_0 = muxbits1_value_3_0 | muxbits1_value_3_1; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_4_1 = muxbits1_value_3_2 | muxbits1_value_3_3; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_5_0 = muxbits1_value_4_0 | muxbits1_value_4_1; // @[Library.scala 129:37]
- wire [31:0] muxbits__0 = muxbits0_value_5_0[31:0]; // @[Fetch.scala 354:33]
- wire [31:0] muxbits__8 = muxbits1_value_5_0[31:0]; // @[Fetch.scala 355:33]
- wire [31:0] muxbits__1 = muxbits0_value_5_0[63:32]; // @[Fetch.scala 354:33]
- wire [31:0] muxbits__9 = muxbits1_value_5_0[63:32]; // @[Fetch.scala 355:33]
- wire [31:0] muxbits__2 = muxbits0_value_5_0[95:64]; // @[Fetch.scala 354:33]
- wire [31:0] muxbits__10 = muxbits1_value_5_0[95:64]; // @[Fetch.scala 355:33]
- wire [31:0] muxbits__3 = muxbits0_value_5_0[127:96]; // @[Fetch.scala 354:33]
- wire [31:0] muxbits__11 = muxbits1_value_5_0[127:96]; // @[Fetch.scala 355:33]
- wire [31:0] muxbits__4 = muxbits0_value_5_0[159:128]; // @[Fetch.scala 354:33]
- wire [31:0] muxbits__12 = muxbits1_value_5_0[159:128]; // @[Fetch.scala 355:33]
- wire [31:0] muxbits__5 = muxbits0_value_5_0[191:160]; // @[Fetch.scala 354:33]
- wire [31:0] muxbits__13 = muxbits1_value_5_0[191:160]; // @[Fetch.scala 355:33]
- wire [31:0] muxbits__6 = muxbits0_value_5_0[223:192]; // @[Fetch.scala 354:33]
- wire [31:0] muxbits__14 = muxbits1_value_5_0[223:192]; // @[Fetch.scala 355:33]
- wire [31:0] muxbits__7 = muxbits0_value_5_0[255:224]; // @[Fetch.scala 354:33]
- wire [31:0] muxbits__15 = muxbits1_value_5_0[255:224]; // @[Fetch.scala 355:33]
- wire _idx_T_2 = brchTargetDe[5] != brchTargetDe[5]; // @[Fetch.scala 360:32]
- wire [3:0] idx = {_idx_T_2,brchTargetDe[4:2]}; // @[Cat.scala 31:58]
- wire [31:0] bits_0_value__0 = 4'h0 == idx ? muxbits__0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__1 = 4'h1 == idx ? muxbits__1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__2 = 4'h2 == idx ? muxbits__2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__3 = 4'h3 == idx ? muxbits__3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__4 = 4'h4 == idx ? muxbits__4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__5 = 4'h5 == idx ? muxbits__5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__6 = 4'h6 == idx ? muxbits__6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__7 = 4'h7 == idx ? muxbits__7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__8 = 4'h8 == idx ? muxbits__8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__9 = 4'h9 == idx ? muxbits__9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__10 = 4'ha == idx ? muxbits__10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__11 = 4'hb == idx ? muxbits__11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__12 = 4'hc == idx ? muxbits__12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__13 = 4'hd == idx ? muxbits__13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__14 = 4'he == idx ? muxbits__14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value__15 = 4'hf == idx ? muxbits__15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_1_0 = bits_0_value__0 | bits_0_value__1; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_1_1 = bits_0_value__2 | bits_0_value__3; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_1_2 = bits_0_value__4 | bits_0_value__5; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_1_3 = bits_0_value__6 | bits_0_value__7; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_1_4 = bits_0_value__8 | bits_0_value__9; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_1_5 = bits_0_value__10 | bits_0_value__11; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_1_6 = bits_0_value__12 | bits_0_value__13; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_1_7 = bits_0_value__14 | bits_0_value__15; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_2_0 = bits_0_value_1_0 | bits_0_value_1_1; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_2_1 = bits_0_value_1_2 | bits_0_value_1_3; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_2_2 = bits_0_value_1_4 | bits_0_value_1_5; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_2_3 = bits_0_value_1_6 | bits_0_value_1_7; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_3_0 = bits_0_value_2_0 | bits_0_value_2_1; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_3_1 = bits_0_value_2_2 | bits_0_value_2_3; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_4_0 = bits_0_value_3_0 | bits_0_value_3_1; // @[Library.scala 129:37]
- wire _idx_T_6 = brchTargetDe[5] != brchAddrDe_1[5]; // @[Fetch.scala 360:32]
- wire [3:0] idx_1 = {_idx_T_6,brchAddrDe_1[4:2]}; // @[Cat.scala 31:58]
- wire [31:0] bits_1_value__0 = 4'h0 == idx_1 ? muxbits__0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__1 = 4'h1 == idx_1 ? muxbits__1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__2 = 4'h2 == idx_1 ? muxbits__2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__3 = 4'h3 == idx_1 ? muxbits__3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__4 = 4'h4 == idx_1 ? muxbits__4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__5 = 4'h5 == idx_1 ? muxbits__5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__6 = 4'h6 == idx_1 ? muxbits__6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__7 = 4'h7 == idx_1 ? muxbits__7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__8 = 4'h8 == idx_1 ? muxbits__8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__9 = 4'h9 == idx_1 ? muxbits__9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__10 = 4'ha == idx_1 ? muxbits__10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__11 = 4'hb == idx_1 ? muxbits__11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__12 = 4'hc == idx_1 ? muxbits__12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__13 = 4'hd == idx_1 ? muxbits__13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__14 = 4'he == idx_1 ? muxbits__14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value__15 = 4'hf == idx_1 ? muxbits__15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_1_0 = bits_1_value__0 | bits_1_value__1; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_1_1 = bits_1_value__2 | bits_1_value__3; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_1_2 = bits_1_value__4 | bits_1_value__5; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_1_3 = bits_1_value__6 | bits_1_value__7; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_1_4 = bits_1_value__8 | bits_1_value__9; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_1_5 = bits_1_value__10 | bits_1_value__11; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_1_6 = bits_1_value__12 | bits_1_value__13; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_1_7 = bits_1_value__14 | bits_1_value__15; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_2_0 = bits_1_value_1_0 | bits_1_value_1_1; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_2_1 = bits_1_value_1_2 | bits_1_value_1_3; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_2_2 = bits_1_value_1_4 | bits_1_value_1_5; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_2_3 = bits_1_value_1_6 | bits_1_value_1_7; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_3_0 = bits_1_value_2_0 | bits_1_value_2_1; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_3_1 = bits_1_value_2_2 | bits_1_value_2_3; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_4_0 = bits_1_value_3_0 | bits_1_value_3_1; // @[Library.scala 129:37]
- wire _idx_T_10 = brchTargetDe[5] != brchAddrDe_2[5]; // @[Fetch.scala 360:32]
- wire [3:0] idx_2 = {_idx_T_10,brchAddrDe_2[4:2]}; // @[Cat.scala 31:58]
- wire [31:0] bits_2_value__0 = 4'h0 == idx_2 ? muxbits__0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__1 = 4'h1 == idx_2 ? muxbits__1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__2 = 4'h2 == idx_2 ? muxbits__2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__3 = 4'h3 == idx_2 ? muxbits__3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__4 = 4'h4 == idx_2 ? muxbits__4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__5 = 4'h5 == idx_2 ? muxbits__5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__6 = 4'h6 == idx_2 ? muxbits__6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__7 = 4'h7 == idx_2 ? muxbits__7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__8 = 4'h8 == idx_2 ? muxbits__8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__9 = 4'h9 == idx_2 ? muxbits__9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__10 = 4'ha == idx_2 ? muxbits__10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__11 = 4'hb == idx_2 ? muxbits__11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__12 = 4'hc == idx_2 ? muxbits__12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__13 = 4'hd == idx_2 ? muxbits__13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__14 = 4'he == idx_2 ? muxbits__14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value__15 = 4'hf == idx_2 ? muxbits__15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_1_0 = bits_2_value__0 | bits_2_value__1; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_1_1 = bits_2_value__2 | bits_2_value__3; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_1_2 = bits_2_value__4 | bits_2_value__5; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_1_3 = bits_2_value__6 | bits_2_value__7; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_1_4 = bits_2_value__8 | bits_2_value__9; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_1_5 = bits_2_value__10 | bits_2_value__11; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_1_6 = bits_2_value__12 | bits_2_value__13; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_1_7 = bits_2_value__14 | bits_2_value__15; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_2_0 = bits_2_value_1_0 | bits_2_value_1_1; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_2_1 = bits_2_value_1_2 | bits_2_value_1_3; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_2_2 = bits_2_value_1_4 | bits_2_value_1_5; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_2_3 = bits_2_value_1_6 | bits_2_value_1_7; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_3_0 = bits_2_value_2_0 | bits_2_value_2_1; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_3_1 = bits_2_value_2_2 | bits_2_value_2_3; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_4_0 = bits_2_value_3_0 | bits_2_value_3_1; // @[Library.scala 129:37]
- wire _idx_T_14 = brchTargetDe[5] != brchAddrDe_3[5]; // @[Fetch.scala 360:32]
- wire [3:0] idx_3 = {_idx_T_14,brchAddrDe_3[4:2]}; // @[Cat.scala 31:58]
- wire [31:0] bits_3_value__0 = 4'h0 == idx_3 ? muxbits__0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__1 = 4'h1 == idx_3 ? muxbits__1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__2 = 4'h2 == idx_3 ? muxbits__2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__3 = 4'h3 == idx_3 ? muxbits__3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__4 = 4'h4 == idx_3 ? muxbits__4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__5 = 4'h5 == idx_3 ? muxbits__5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__6 = 4'h6 == idx_3 ? muxbits__6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__7 = 4'h7 == idx_3 ? muxbits__7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__8 = 4'h8 == idx_3 ? muxbits__8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__9 = 4'h9 == idx_3 ? muxbits__9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__10 = 4'ha == idx_3 ? muxbits__10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__11 = 4'hb == idx_3 ? muxbits__11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__12 = 4'hc == idx_3 ? muxbits__12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__13 = 4'hd == idx_3 ? muxbits__13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__14 = 4'he == idx_3 ? muxbits__14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value__15 = 4'hf == idx_3 ? muxbits__15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_1_0 = bits_3_value__0 | bits_3_value__1; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_1_1 = bits_3_value__2 | bits_3_value__3; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_1_2 = bits_3_value__4 | bits_3_value__5; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_1_3 = bits_3_value__6 | bits_3_value__7; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_1_4 = bits_3_value__8 | bits_3_value__9; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_1_5 = bits_3_value__10 | bits_3_value__11; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_1_6 = bits_3_value__12 | bits_3_value__13; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_1_7 = bits_3_value__14 | bits_3_value__15; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_2_0 = bits_3_value_1_0 | bits_3_value_1_1; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_2_1 = bits_3_value_1_2 | bits_3_value_1_3; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_2_2 = bits_3_value_1_4 | bits_3_value_1_5; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_2_3 = bits_3_value_1_6 | bits_3_value_1_7; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_3_0 = bits_3_value_2_0 | bits_3_value_2_1; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_3_1 = bits_3_value_2_2 | bits_3_value_2_3; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_4_0 = bits_3_value_3_0 | bits_3_value_3_1; // @[Library.scala 129:37]
- wire [3:0] brchValidDe = {vvalid__3,vvalid__2,vvalid__1,match0_1}; // @[Fetch.scala 364:20]
- wire _valid_T_1 = io_branch_0_valid | io_branch_1_valid | io_branch_2_valid; // @[Fetch.scala 369:52]
- wire brchTakenEx = _valid_T_1 | io_branch_3_valid; // @[Fetch.scala 370:33]
- wire [31:0] _addr_T_6 = io_branch_2_valid ? io_branch_2_value : io_branch_3_value; // @[Fetch.scala 374:27]
- wire [31:0] _addr_T_7 = io_branch_1_valid ? io_branch_1_value : _addr_T_6; // @[Fetch.scala 373:27]
- wire [31:0] brchAddrEx_0 = io_branch_0_valid ? io_branch_0_value : _addr_T_7; // @[Fetch.scala 372:27]
- wire [31:0] _addr_T_10 = io_branch_0_value + 32'h4; // @[Fetch.scala 376:61]
- wire [31:0] _addr_T_12 = io_branch_1_value + 32'h4; // @[Fetch.scala 377:61]
- wire [31:0] _addr_T_14 = io_branch_2_value + 32'h4; // @[Fetch.scala 378:61]
- wire [31:0] _addr_T_16 = io_branch_3_value + 32'h4; // @[Fetch.scala 379:61]
- wire [31:0] _addr_T_17 = io_branch_2_valid ? _addr_T_14 : _addr_T_16; // @[Fetch.scala 378:27]
- wire [31:0] _addr_T_18 = io_branch_1_valid ? _addr_T_12 : _addr_T_17; // @[Fetch.scala 377:27]
- wire [31:0] brchAddrEx_1 = io_branch_0_valid ? _addr_T_10 : _addr_T_18; // @[Fetch.scala 376:27]
- wire [31:0] _addr_T_21 = io_branch_0_value + 32'h8; // @[Fetch.scala 380:61]
- wire [31:0] _addr_T_23 = io_branch_1_value + 32'h8; // @[Fetch.scala 381:61]
- wire [31:0] _addr_T_25 = io_branch_2_value + 32'h8; // @[Fetch.scala 382:61]
- wire [31:0] _addr_T_27 = io_branch_3_value + 32'h8; // @[Fetch.scala 383:61]
- wire [31:0] _addr_T_28 = io_branch_2_valid ? _addr_T_25 : _addr_T_27; // @[Fetch.scala 382:27]
- wire [31:0] _addr_T_29 = io_branch_1_valid ? _addr_T_23 : _addr_T_28; // @[Fetch.scala 381:27]
- wire [31:0] brchAddrEx_2 = io_branch_0_valid ? _addr_T_21 : _addr_T_29; // @[Fetch.scala 380:27]
- wire [31:0] _addr_T_32 = io_branch_0_value + 32'hc; // @[Fetch.scala 384:61]
- wire [31:0] _addr_T_34 = io_branch_1_value + 32'hc; // @[Fetch.scala 385:61]
- wire [31:0] _addr_T_36 = io_branch_2_value + 32'hc; // @[Fetch.scala 386:61]
- wire [31:0] _addr_T_38 = io_branch_3_value + 32'hc; // @[Fetch.scala 387:61]
- wire [31:0] _addr_T_39 = io_branch_2_valid ? _addr_T_36 : _addr_T_38; // @[Fetch.scala 386:27]
- wire [31:0] _addr_T_40 = io_branch_1_valid ? _addr_T_34 : _addr_T_39; // @[Fetch.scala 385:27]
- wire [31:0] brchAddrEx_3 = io_branch_0_valid ? _addr_T_32 : _addr_T_40; // @[Fetch.scala 384:27]
- wire [31:0] _match0_T_8 = l0valid >> brchAddrEx_0[9:5]; // @[Fetch.scala 389:25]
- wire [21:0] match0_value_6_0 = 5'h0 == brchAddrEx_0[9:5] ? l0tag_0 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_1 = 5'h1 == brchAddrEx_0[9:5] ? l0tag_1 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_2 = 5'h2 == brchAddrEx_0[9:5] ? l0tag_2 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_3 = 5'h3 == brchAddrEx_0[9:5] ? l0tag_3 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_4 = 5'h4 == brchAddrEx_0[9:5] ? l0tag_4 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_5 = 5'h5 == brchAddrEx_0[9:5] ? l0tag_5 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_6 = 5'h6 == brchAddrEx_0[9:5] ? l0tag_6 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_7 = 5'h7 == brchAddrEx_0[9:5] ? l0tag_7 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_8 = 5'h8 == brchAddrEx_0[9:5] ? l0tag_8 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_9 = 5'h9 == brchAddrEx_0[9:5] ? l0tag_9 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_10 = 5'ha == brchAddrEx_0[9:5] ? l0tag_10 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_11 = 5'hb == brchAddrEx_0[9:5] ? l0tag_11 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_12 = 5'hc == brchAddrEx_0[9:5] ? l0tag_12 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_13 = 5'hd == brchAddrEx_0[9:5] ? l0tag_13 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_14 = 5'he == brchAddrEx_0[9:5] ? l0tag_14 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_15 = 5'hf == brchAddrEx_0[9:5] ? l0tag_15 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_16 = 5'h10 == brchAddrEx_0[9:5] ? l0tag_16 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_17 = 5'h11 == brchAddrEx_0[9:5] ? l0tag_17 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_18 = 5'h12 == brchAddrEx_0[9:5] ? l0tag_18 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_19 = 5'h13 == brchAddrEx_0[9:5] ? l0tag_19 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_20 = 5'h14 == brchAddrEx_0[9:5] ? l0tag_20 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_21 = 5'h15 == brchAddrEx_0[9:5] ? l0tag_21 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_22 = 5'h16 == brchAddrEx_0[9:5] ? l0tag_22 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_23 = 5'h17 == brchAddrEx_0[9:5] ? l0tag_23 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_24 = 5'h18 == brchAddrEx_0[9:5] ? l0tag_24 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_25 = 5'h19 == brchAddrEx_0[9:5] ? l0tag_25 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_26 = 5'h1a == brchAddrEx_0[9:5] ? l0tag_26 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_27 = 5'h1b == brchAddrEx_0[9:5] ? l0tag_27 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_28 = 5'h1c == brchAddrEx_0[9:5] ? l0tag_28 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_29 = 5'h1d == brchAddrEx_0[9:5] ? l0tag_29 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_30 = 5'h1e == brchAddrEx_0[9:5] ? l0tag_30 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_6_31 = 5'h1f == brchAddrEx_0[9:5] ? l0tag_31 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match0_value_7_0 = match0_value_6_0 | match0_value_6_1; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_1 = match0_value_6_2 | match0_value_6_3; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_2 = match0_value_6_4 | match0_value_6_5; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_3 = match0_value_6_6 | match0_value_6_7; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_4 = match0_value_6_8 | match0_value_6_9; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_5 = match0_value_6_10 | match0_value_6_11; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_6 = match0_value_6_12 | match0_value_6_13; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_7 = match0_value_6_14 | match0_value_6_15; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_8 = match0_value_6_16 | match0_value_6_17; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_9 = match0_value_6_18 | match0_value_6_19; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_10 = match0_value_6_20 | match0_value_6_21; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_11 = match0_value_6_22 | match0_value_6_23; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_12 = match0_value_6_24 | match0_value_6_25; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_13 = match0_value_6_26 | match0_value_6_27; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_14 = match0_value_6_28 | match0_value_6_29; // @[Library.scala 129:37]
- wire [21:0] match0_value_7_15 = match0_value_6_30 | match0_value_6_31; // @[Library.scala 129:37]
- wire [21:0] match0_value_8_0 = match0_value_7_0 | match0_value_7_1; // @[Library.scala 129:37]
- wire [21:0] match0_value_8_1 = match0_value_7_2 | match0_value_7_3; // @[Library.scala 129:37]
- wire [21:0] match0_value_8_2 = match0_value_7_4 | match0_value_7_5; // @[Library.scala 129:37]
- wire [21:0] match0_value_8_3 = match0_value_7_6 | match0_value_7_7; // @[Library.scala 129:37]
- wire [21:0] match0_value_8_4 = match0_value_7_8 | match0_value_7_9; // @[Library.scala 129:37]
- wire [21:0] match0_value_8_5 = match0_value_7_10 | match0_value_7_11; // @[Library.scala 129:37]
- wire [21:0] match0_value_8_6 = match0_value_7_12 | match0_value_7_13; // @[Library.scala 129:37]
- wire [21:0] match0_value_8_7 = match0_value_7_14 | match0_value_7_15; // @[Library.scala 129:37]
- wire [21:0] match0_value_9_0 = match0_value_8_0 | match0_value_8_1; // @[Library.scala 129:37]
- wire [21:0] match0_value_9_1 = match0_value_8_2 | match0_value_8_3; // @[Library.scala 129:37]
- wire [21:0] match0_value_9_2 = match0_value_8_4 | match0_value_8_5; // @[Library.scala 129:37]
- wire [21:0] match0_value_9_3 = match0_value_8_6 | match0_value_8_7; // @[Library.scala 129:37]
- wire [21:0] match0_value_10_0 = match0_value_9_0 | match0_value_9_1; // @[Library.scala 129:37]
- wire [21:0] match0_value_10_1 = match0_value_9_2 | match0_value_9_3; // @[Library.scala 129:37]
- wire [21:0] match0_value_11_0 = match0_value_10_0 | match0_value_10_1; // @[Library.scala 129:37]
- wire _match0_T_12 = brchAddrEx_0[31:10] == match0_value_11_0; // @[Fetch.scala 390:32]
- wire match0_2 = _match0_T_8[0] & _match0_T_12; // @[Fetch.scala 389:54]
- wire [31:0] _match1_T_8 = l0valid >> brchAddrEx_3[9:5]; // @[Fetch.scala 391:25]
- wire [21:0] match1_value_6_0 = 5'h0 == brchAddrEx_3[9:5] ? l0tag_0 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_1 = 5'h1 == brchAddrEx_3[9:5] ? l0tag_1 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_2 = 5'h2 == brchAddrEx_3[9:5] ? l0tag_2 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_3 = 5'h3 == brchAddrEx_3[9:5] ? l0tag_3 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_4 = 5'h4 == brchAddrEx_3[9:5] ? l0tag_4 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_5 = 5'h5 == brchAddrEx_3[9:5] ? l0tag_5 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_6 = 5'h6 == brchAddrEx_3[9:5] ? l0tag_6 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_7 = 5'h7 == brchAddrEx_3[9:5] ? l0tag_7 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_8 = 5'h8 == brchAddrEx_3[9:5] ? l0tag_8 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_9 = 5'h9 == brchAddrEx_3[9:5] ? l0tag_9 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_10 = 5'ha == brchAddrEx_3[9:5] ? l0tag_10 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_11 = 5'hb == brchAddrEx_3[9:5] ? l0tag_11 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_12 = 5'hc == brchAddrEx_3[9:5] ? l0tag_12 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_13 = 5'hd == brchAddrEx_3[9:5] ? l0tag_13 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_14 = 5'he == brchAddrEx_3[9:5] ? l0tag_14 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_15 = 5'hf == brchAddrEx_3[9:5] ? l0tag_15 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_16 = 5'h10 == brchAddrEx_3[9:5] ? l0tag_16 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_17 = 5'h11 == brchAddrEx_3[9:5] ? l0tag_17 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_18 = 5'h12 == brchAddrEx_3[9:5] ? l0tag_18 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_19 = 5'h13 == brchAddrEx_3[9:5] ? l0tag_19 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_20 = 5'h14 == brchAddrEx_3[9:5] ? l0tag_20 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_21 = 5'h15 == brchAddrEx_3[9:5] ? l0tag_21 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_22 = 5'h16 == brchAddrEx_3[9:5] ? l0tag_22 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_23 = 5'h17 == brchAddrEx_3[9:5] ? l0tag_23 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_24 = 5'h18 == brchAddrEx_3[9:5] ? l0tag_24 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_25 = 5'h19 == brchAddrEx_3[9:5] ? l0tag_25 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_26 = 5'h1a == brchAddrEx_3[9:5] ? l0tag_26 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_27 = 5'h1b == brchAddrEx_3[9:5] ? l0tag_27 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_28 = 5'h1c == brchAddrEx_3[9:5] ? l0tag_28 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_29 = 5'h1d == brchAddrEx_3[9:5] ? l0tag_29 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_30 = 5'h1e == brchAddrEx_3[9:5] ? l0tag_30 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_6_31 = 5'h1f == brchAddrEx_3[9:5] ? l0tag_31 : 22'h0; // @[Library.scala 115:22]
- wire [21:0] match1_value_7_0 = match1_value_6_0 | match1_value_6_1; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_1 = match1_value_6_2 | match1_value_6_3; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_2 = match1_value_6_4 | match1_value_6_5; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_3 = match1_value_6_6 | match1_value_6_7; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_4 = match1_value_6_8 | match1_value_6_9; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_5 = match1_value_6_10 | match1_value_6_11; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_6 = match1_value_6_12 | match1_value_6_13; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_7 = match1_value_6_14 | match1_value_6_15; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_8 = match1_value_6_16 | match1_value_6_17; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_9 = match1_value_6_18 | match1_value_6_19; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_10 = match1_value_6_20 | match1_value_6_21; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_11 = match1_value_6_22 | match1_value_6_23; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_12 = match1_value_6_24 | match1_value_6_25; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_13 = match1_value_6_26 | match1_value_6_27; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_14 = match1_value_6_28 | match1_value_6_29; // @[Library.scala 129:37]
- wire [21:0] match1_value_7_15 = match1_value_6_30 | match1_value_6_31; // @[Library.scala 129:37]
- wire [21:0] match1_value_8_0 = match1_value_7_0 | match1_value_7_1; // @[Library.scala 129:37]
- wire [21:0] match1_value_8_1 = match1_value_7_2 | match1_value_7_3; // @[Library.scala 129:37]
- wire [21:0] match1_value_8_2 = match1_value_7_4 | match1_value_7_5; // @[Library.scala 129:37]
- wire [21:0] match1_value_8_3 = match1_value_7_6 | match1_value_7_7; // @[Library.scala 129:37]
- wire [21:0] match1_value_8_4 = match1_value_7_8 | match1_value_7_9; // @[Library.scala 129:37]
- wire [21:0] match1_value_8_5 = match1_value_7_10 | match1_value_7_11; // @[Library.scala 129:37]
- wire [21:0] match1_value_8_6 = match1_value_7_12 | match1_value_7_13; // @[Library.scala 129:37]
- wire [21:0] match1_value_8_7 = match1_value_7_14 | match1_value_7_15; // @[Library.scala 129:37]
- wire [21:0] match1_value_9_0 = match1_value_8_0 | match1_value_8_1; // @[Library.scala 129:37]
- wire [21:0] match1_value_9_1 = match1_value_8_2 | match1_value_8_3; // @[Library.scala 129:37]
- wire [21:0] match1_value_9_2 = match1_value_8_4 | match1_value_8_5; // @[Library.scala 129:37]
- wire [21:0] match1_value_9_3 = match1_value_8_6 | match1_value_8_7; // @[Library.scala 129:37]
- wire [21:0] match1_value_10_0 = match1_value_9_0 | match1_value_9_1; // @[Library.scala 129:37]
- wire [21:0] match1_value_10_1 = match1_value_9_2 | match1_value_9_3; // @[Library.scala 129:37]
- wire [21:0] match1_value_11_0 = match1_value_10_0 | match1_value_10_1; // @[Library.scala 129:37]
- wire _match1_T_12 = brchAddrEx_3[31:10] == match1_value_11_0; // @[Fetch.scala 392:32]
- wire match1_2 = _match1_T_8[0] & _match1_T_12; // @[Fetch.scala 391:54]
- wire vvalid_1_1 = brchAddrEx_0[4:2] <= 3'h6 ? match0_2 : match1_2; // @[Fetch.scala 395:29]
- wire vvalid_1_2 = brchAddrEx_0[4:2] <= 3'h5 ? match0_2 : match1_2; // @[Fetch.scala 396:29]
- wire vvalid_1_3 = brchAddrEx_0[4:2] <= 3'h4 ? match0_2 : match1_2; // @[Fetch.scala 397:29]
- wire [255:0] muxbits0_value_6_0 = 5'h0 == brchAddrEx_0[9:5] ? l0data_0 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_1 = 5'h1 == brchAddrEx_0[9:5] ? l0data_1 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_2 = 5'h2 == brchAddrEx_0[9:5] ? l0data_2 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_3 = 5'h3 == brchAddrEx_0[9:5] ? l0data_3 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_4 = 5'h4 == brchAddrEx_0[9:5] ? l0data_4 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_5 = 5'h5 == brchAddrEx_0[9:5] ? l0data_5 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_6 = 5'h6 == brchAddrEx_0[9:5] ? l0data_6 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_7 = 5'h7 == brchAddrEx_0[9:5] ? l0data_7 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_8 = 5'h8 == brchAddrEx_0[9:5] ? l0data_8 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_9 = 5'h9 == brchAddrEx_0[9:5] ? l0data_9 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_10 = 5'ha == brchAddrEx_0[9:5] ? l0data_10 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_11 = 5'hb == brchAddrEx_0[9:5] ? l0data_11 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_12 = 5'hc == brchAddrEx_0[9:5] ? l0data_12 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_13 = 5'hd == brchAddrEx_0[9:5] ? l0data_13 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_14 = 5'he == brchAddrEx_0[9:5] ? l0data_14 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_15 = 5'hf == brchAddrEx_0[9:5] ? l0data_15 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_16 = 5'h10 == brchAddrEx_0[9:5] ? l0data_16 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_17 = 5'h11 == brchAddrEx_0[9:5] ? l0data_17 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_18 = 5'h12 == brchAddrEx_0[9:5] ? l0data_18 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_19 = 5'h13 == brchAddrEx_0[9:5] ? l0data_19 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_20 = 5'h14 == brchAddrEx_0[9:5] ? l0data_20 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_21 = 5'h15 == brchAddrEx_0[9:5] ? l0data_21 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_22 = 5'h16 == brchAddrEx_0[9:5] ? l0data_22 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_23 = 5'h17 == brchAddrEx_0[9:5] ? l0data_23 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_24 = 5'h18 == brchAddrEx_0[9:5] ? l0data_24 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_25 = 5'h19 == brchAddrEx_0[9:5] ? l0data_25 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_26 = 5'h1a == brchAddrEx_0[9:5] ? l0data_26 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_27 = 5'h1b == brchAddrEx_0[9:5] ? l0data_27 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_28 = 5'h1c == brchAddrEx_0[9:5] ? l0data_28 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_29 = 5'h1d == brchAddrEx_0[9:5] ? l0data_29 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_30 = 5'h1e == brchAddrEx_0[9:5] ? l0data_30 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_6_31 = 5'h1f == brchAddrEx_0[9:5] ? l0data_31 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits0_value_7_0 = muxbits0_value_6_0 | muxbits0_value_6_1; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_1 = muxbits0_value_6_2 | muxbits0_value_6_3; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_2 = muxbits0_value_6_4 | muxbits0_value_6_5; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_3 = muxbits0_value_6_6 | muxbits0_value_6_7; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_4 = muxbits0_value_6_8 | muxbits0_value_6_9; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_5 = muxbits0_value_6_10 | muxbits0_value_6_11; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_6 = muxbits0_value_6_12 | muxbits0_value_6_13; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_7 = muxbits0_value_6_14 | muxbits0_value_6_15; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_8 = muxbits0_value_6_16 | muxbits0_value_6_17; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_9 = muxbits0_value_6_18 | muxbits0_value_6_19; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_10 = muxbits0_value_6_20 | muxbits0_value_6_21; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_11 = muxbits0_value_6_22 | muxbits0_value_6_23; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_12 = muxbits0_value_6_24 | muxbits0_value_6_25; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_13 = muxbits0_value_6_26 | muxbits0_value_6_27; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_14 = muxbits0_value_6_28 | muxbits0_value_6_29; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_7_15 = muxbits0_value_6_30 | muxbits0_value_6_31; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_8_0 = muxbits0_value_7_0 | muxbits0_value_7_1; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_8_1 = muxbits0_value_7_2 | muxbits0_value_7_3; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_8_2 = muxbits0_value_7_4 | muxbits0_value_7_5; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_8_3 = muxbits0_value_7_6 | muxbits0_value_7_7; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_8_4 = muxbits0_value_7_8 | muxbits0_value_7_9; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_8_5 = muxbits0_value_7_10 | muxbits0_value_7_11; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_8_6 = muxbits0_value_7_12 | muxbits0_value_7_13; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_8_7 = muxbits0_value_7_14 | muxbits0_value_7_15; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_9_0 = muxbits0_value_8_0 | muxbits0_value_8_1; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_9_1 = muxbits0_value_8_2 | muxbits0_value_8_3; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_9_2 = muxbits0_value_8_4 | muxbits0_value_8_5; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_9_3 = muxbits0_value_8_6 | muxbits0_value_8_7; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_10_0 = muxbits0_value_9_0 | muxbits0_value_9_1; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_10_1 = muxbits0_value_9_2 | muxbits0_value_9_3; // @[Library.scala 129:37]
- wire [255:0] muxbits0_value_11_0 = muxbits0_value_10_0 | muxbits0_value_10_1; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_6_0 = 5'h0 == brchAddrEx_3[9:5] ? l0data_0 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_1 = 5'h1 == brchAddrEx_3[9:5] ? l0data_1 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_2 = 5'h2 == brchAddrEx_3[9:5] ? l0data_2 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_3 = 5'h3 == brchAddrEx_3[9:5] ? l0data_3 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_4 = 5'h4 == brchAddrEx_3[9:5] ? l0data_4 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_5 = 5'h5 == brchAddrEx_3[9:5] ? l0data_5 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_6 = 5'h6 == brchAddrEx_3[9:5] ? l0data_6 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_7 = 5'h7 == brchAddrEx_3[9:5] ? l0data_7 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_8 = 5'h8 == brchAddrEx_3[9:5] ? l0data_8 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_9 = 5'h9 == brchAddrEx_3[9:5] ? l0data_9 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_10 = 5'ha == brchAddrEx_3[9:5] ? l0data_10 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_11 = 5'hb == brchAddrEx_3[9:5] ? l0data_11 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_12 = 5'hc == brchAddrEx_3[9:5] ? l0data_12 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_13 = 5'hd == brchAddrEx_3[9:5] ? l0data_13 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_14 = 5'he == brchAddrEx_3[9:5] ? l0data_14 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_15 = 5'hf == brchAddrEx_3[9:5] ? l0data_15 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_16 = 5'h10 == brchAddrEx_3[9:5] ? l0data_16 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_17 = 5'h11 == brchAddrEx_3[9:5] ? l0data_17 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_18 = 5'h12 == brchAddrEx_3[9:5] ? l0data_18 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_19 = 5'h13 == brchAddrEx_3[9:5] ? l0data_19 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_20 = 5'h14 == brchAddrEx_3[9:5] ? l0data_20 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_21 = 5'h15 == brchAddrEx_3[9:5] ? l0data_21 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_22 = 5'h16 == brchAddrEx_3[9:5] ? l0data_22 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_23 = 5'h17 == brchAddrEx_3[9:5] ? l0data_23 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_24 = 5'h18 == brchAddrEx_3[9:5] ? l0data_24 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_25 = 5'h19 == brchAddrEx_3[9:5] ? l0data_25 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_26 = 5'h1a == brchAddrEx_3[9:5] ? l0data_26 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_27 = 5'h1b == brchAddrEx_3[9:5] ? l0data_27 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_28 = 5'h1c == brchAddrEx_3[9:5] ? l0data_28 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_29 = 5'h1d == brchAddrEx_3[9:5] ? l0data_29 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_30 = 5'h1e == brchAddrEx_3[9:5] ? l0data_30 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_6_31 = 5'h1f == brchAddrEx_3[9:5] ? l0data_31 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] muxbits1_value_7_0 = muxbits1_value_6_0 | muxbits1_value_6_1; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_1 = muxbits1_value_6_2 | muxbits1_value_6_3; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_2 = muxbits1_value_6_4 | muxbits1_value_6_5; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_3 = muxbits1_value_6_6 | muxbits1_value_6_7; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_4 = muxbits1_value_6_8 | muxbits1_value_6_9; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_5 = muxbits1_value_6_10 | muxbits1_value_6_11; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_6 = muxbits1_value_6_12 | muxbits1_value_6_13; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_7 = muxbits1_value_6_14 | muxbits1_value_6_15; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_8 = muxbits1_value_6_16 | muxbits1_value_6_17; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_9 = muxbits1_value_6_18 | muxbits1_value_6_19; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_10 = muxbits1_value_6_20 | muxbits1_value_6_21; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_11 = muxbits1_value_6_22 | muxbits1_value_6_23; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_12 = muxbits1_value_6_24 | muxbits1_value_6_25; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_13 = muxbits1_value_6_26 | muxbits1_value_6_27; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_14 = muxbits1_value_6_28 | muxbits1_value_6_29; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_7_15 = muxbits1_value_6_30 | muxbits1_value_6_31; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_8_0 = muxbits1_value_7_0 | muxbits1_value_7_1; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_8_1 = muxbits1_value_7_2 | muxbits1_value_7_3; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_8_2 = muxbits1_value_7_4 | muxbits1_value_7_5; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_8_3 = muxbits1_value_7_6 | muxbits1_value_7_7; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_8_4 = muxbits1_value_7_8 | muxbits1_value_7_9; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_8_5 = muxbits1_value_7_10 | muxbits1_value_7_11; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_8_6 = muxbits1_value_7_12 | muxbits1_value_7_13; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_8_7 = muxbits1_value_7_14 | muxbits1_value_7_15; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_9_0 = muxbits1_value_8_0 | muxbits1_value_8_1; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_9_1 = muxbits1_value_8_2 | muxbits1_value_8_3; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_9_2 = muxbits1_value_8_4 | muxbits1_value_8_5; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_9_3 = muxbits1_value_8_6 | muxbits1_value_8_7; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_10_0 = muxbits1_value_9_0 | muxbits1_value_9_1; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_10_1 = muxbits1_value_9_2 | muxbits1_value_9_3; // @[Library.scala 129:37]
- wire [255:0] muxbits1_value_11_0 = muxbits1_value_10_0 | muxbits1_value_10_1; // @[Library.scala 129:37]
- wire [31:0] muxbits_1_0 = muxbits0_value_11_0[31:0]; // @[Fetch.scala 405:33]
- wire [31:0] muxbits_1_8 = muxbits1_value_11_0[31:0]; // @[Fetch.scala 406:33]
- wire [31:0] muxbits_1_1 = muxbits0_value_11_0[63:32]; // @[Fetch.scala 405:33]
- wire [31:0] muxbits_1_9 = muxbits1_value_11_0[63:32]; // @[Fetch.scala 406:33]
- wire [31:0] muxbits_1_2 = muxbits0_value_11_0[95:64]; // @[Fetch.scala 405:33]
- wire [31:0] muxbits_1_10 = muxbits1_value_11_0[95:64]; // @[Fetch.scala 406:33]
- wire [31:0] muxbits_1_3 = muxbits0_value_11_0[127:96]; // @[Fetch.scala 405:33]
- wire [31:0] muxbits_1_11 = muxbits1_value_11_0[127:96]; // @[Fetch.scala 406:33]
- wire [31:0] muxbits_1_4 = muxbits0_value_11_0[159:128]; // @[Fetch.scala 405:33]
- wire [31:0] muxbits_1_12 = muxbits1_value_11_0[159:128]; // @[Fetch.scala 406:33]
- wire [31:0] muxbits_1_5 = muxbits0_value_11_0[191:160]; // @[Fetch.scala 405:33]
- wire [31:0] muxbits_1_13 = muxbits1_value_11_0[191:160]; // @[Fetch.scala 406:33]
- wire [31:0] muxbits_1_6 = muxbits0_value_11_0[223:192]; // @[Fetch.scala 405:33]
- wire [31:0] muxbits_1_14 = muxbits1_value_11_0[223:192]; // @[Fetch.scala 406:33]
- wire [31:0] muxbits_1_7 = muxbits0_value_11_0[255:224]; // @[Fetch.scala 405:33]
- wire [31:0] muxbits_1_15 = muxbits1_value_11_0[255:224]; // @[Fetch.scala 406:33]
- wire _idx_T_18 = brchAddrEx_0[5] != brchAddrEx_0[5]; // @[Fetch.scala 411:32]
- wire [3:0] idx_4 = {_idx_T_18,brchAddrEx_0[4:2]}; // @[Cat.scala 31:58]
- wire [31:0] bits_0_value_5_0 = 4'h0 == idx_4 ? muxbits_1_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_1 = 4'h1 == idx_4 ? muxbits_1_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_2 = 4'h2 == idx_4 ? muxbits_1_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_3 = 4'h3 == idx_4 ? muxbits_1_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_4 = 4'h4 == idx_4 ? muxbits_1_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_5 = 4'h5 == idx_4 ? muxbits_1_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_6 = 4'h6 == idx_4 ? muxbits_1_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_7 = 4'h7 == idx_4 ? muxbits_1_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_8 = 4'h8 == idx_4 ? muxbits_1_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_9 = 4'h9 == idx_4 ? muxbits_1_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_10 = 4'ha == idx_4 ? muxbits_1_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_11 = 4'hb == idx_4 ? muxbits_1_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_12 = 4'hc == idx_4 ? muxbits_1_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_13 = 4'hd == idx_4 ? muxbits_1_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_14 = 4'he == idx_4 ? muxbits_1_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_5_15 = 4'hf == idx_4 ? muxbits_1_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_0_value_6_0 = bits_0_value_5_0 | bits_0_value_5_1; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_6_1 = bits_0_value_5_2 | bits_0_value_5_3; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_6_2 = bits_0_value_5_4 | bits_0_value_5_5; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_6_3 = bits_0_value_5_6 | bits_0_value_5_7; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_6_4 = bits_0_value_5_8 | bits_0_value_5_9; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_6_5 = bits_0_value_5_10 | bits_0_value_5_11; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_6_6 = bits_0_value_5_12 | bits_0_value_5_13; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_6_7 = bits_0_value_5_14 | bits_0_value_5_15; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_7_0 = bits_0_value_6_0 | bits_0_value_6_1; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_7_1 = bits_0_value_6_2 | bits_0_value_6_3; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_7_2 = bits_0_value_6_4 | bits_0_value_6_5; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_7_3 = bits_0_value_6_6 | bits_0_value_6_7; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_8_0 = bits_0_value_7_0 | bits_0_value_7_1; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_8_1 = bits_0_value_7_2 | bits_0_value_7_3; // @[Library.scala 129:37]
- wire [31:0] bits_0_value_9_0 = bits_0_value_8_0 | bits_0_value_8_1; // @[Library.scala 129:37]
- wire _idx_T_22 = brchAddrEx_0[5] != brchAddrEx_1[5]; // @[Fetch.scala 411:32]
- wire [3:0] idx_5 = {_idx_T_22,brchAddrEx_1[4:2]}; // @[Cat.scala 31:58]
- wire [31:0] bits_1_value_5_0 = 4'h0 == idx_5 ? muxbits_1_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_1 = 4'h1 == idx_5 ? muxbits_1_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_2 = 4'h2 == idx_5 ? muxbits_1_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_3 = 4'h3 == idx_5 ? muxbits_1_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_4 = 4'h4 == idx_5 ? muxbits_1_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_5 = 4'h5 == idx_5 ? muxbits_1_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_6 = 4'h6 == idx_5 ? muxbits_1_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_7 = 4'h7 == idx_5 ? muxbits_1_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_8 = 4'h8 == idx_5 ? muxbits_1_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_9 = 4'h9 == idx_5 ? muxbits_1_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_10 = 4'ha == idx_5 ? muxbits_1_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_11 = 4'hb == idx_5 ? muxbits_1_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_12 = 4'hc == idx_5 ? muxbits_1_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_13 = 4'hd == idx_5 ? muxbits_1_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_14 = 4'he == idx_5 ? muxbits_1_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_5_15 = 4'hf == idx_5 ? muxbits_1_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_1_value_6_0 = bits_1_value_5_0 | bits_1_value_5_1; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_6_1 = bits_1_value_5_2 | bits_1_value_5_3; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_6_2 = bits_1_value_5_4 | bits_1_value_5_5; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_6_3 = bits_1_value_5_6 | bits_1_value_5_7; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_6_4 = bits_1_value_5_8 | bits_1_value_5_9; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_6_5 = bits_1_value_5_10 | bits_1_value_5_11; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_6_6 = bits_1_value_5_12 | bits_1_value_5_13; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_6_7 = bits_1_value_5_14 | bits_1_value_5_15; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_7_0 = bits_1_value_6_0 | bits_1_value_6_1; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_7_1 = bits_1_value_6_2 | bits_1_value_6_3; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_7_2 = bits_1_value_6_4 | bits_1_value_6_5; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_7_3 = bits_1_value_6_6 | bits_1_value_6_7; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_8_0 = bits_1_value_7_0 | bits_1_value_7_1; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_8_1 = bits_1_value_7_2 | bits_1_value_7_3; // @[Library.scala 129:37]
- wire [31:0] bits_1_value_9_0 = bits_1_value_8_0 | bits_1_value_8_1; // @[Library.scala 129:37]
- wire _idx_T_26 = brchAddrEx_0[5] != brchAddrEx_2[5]; // @[Fetch.scala 411:32]
- wire [3:0] idx_6 = {_idx_T_26,brchAddrEx_2[4:2]}; // @[Cat.scala 31:58]
- wire [31:0] bits_2_value_5_0 = 4'h0 == idx_6 ? muxbits_1_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_1 = 4'h1 == idx_6 ? muxbits_1_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_2 = 4'h2 == idx_6 ? muxbits_1_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_3 = 4'h3 == idx_6 ? muxbits_1_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_4 = 4'h4 == idx_6 ? muxbits_1_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_5 = 4'h5 == idx_6 ? muxbits_1_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_6 = 4'h6 == idx_6 ? muxbits_1_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_7 = 4'h7 == idx_6 ? muxbits_1_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_8 = 4'h8 == idx_6 ? muxbits_1_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_9 = 4'h9 == idx_6 ? muxbits_1_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_10 = 4'ha == idx_6 ? muxbits_1_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_11 = 4'hb == idx_6 ? muxbits_1_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_12 = 4'hc == idx_6 ? muxbits_1_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_13 = 4'hd == idx_6 ? muxbits_1_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_14 = 4'he == idx_6 ? muxbits_1_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_5_15 = 4'hf == idx_6 ? muxbits_1_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_2_value_6_0 = bits_2_value_5_0 | bits_2_value_5_1; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_6_1 = bits_2_value_5_2 | bits_2_value_5_3; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_6_2 = bits_2_value_5_4 | bits_2_value_5_5; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_6_3 = bits_2_value_5_6 | bits_2_value_5_7; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_6_4 = bits_2_value_5_8 | bits_2_value_5_9; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_6_5 = bits_2_value_5_10 | bits_2_value_5_11; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_6_6 = bits_2_value_5_12 | bits_2_value_5_13; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_6_7 = bits_2_value_5_14 | bits_2_value_5_15; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_7_0 = bits_2_value_6_0 | bits_2_value_6_1; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_7_1 = bits_2_value_6_2 | bits_2_value_6_3; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_7_2 = bits_2_value_6_4 | bits_2_value_6_5; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_7_3 = bits_2_value_6_6 | bits_2_value_6_7; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_8_0 = bits_2_value_7_0 | bits_2_value_7_1; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_8_1 = bits_2_value_7_2 | bits_2_value_7_3; // @[Library.scala 129:37]
- wire [31:0] bits_2_value_9_0 = bits_2_value_8_0 | bits_2_value_8_1; // @[Library.scala 129:37]
- wire _idx_T_30 = brchAddrEx_0[5] != brchAddrEx_3[5]; // @[Fetch.scala 411:32]
- wire [3:0] idx_7 = {_idx_T_30,brchAddrEx_3[4:2]}; // @[Cat.scala 31:58]
- wire [31:0] bits_3_value_5_0 = 4'h0 == idx_7 ? muxbits_1_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_1 = 4'h1 == idx_7 ? muxbits_1_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_2 = 4'h2 == idx_7 ? muxbits_1_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_3 = 4'h3 == idx_7 ? muxbits_1_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_4 = 4'h4 == idx_7 ? muxbits_1_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_5 = 4'h5 == idx_7 ? muxbits_1_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_6 = 4'h6 == idx_7 ? muxbits_1_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_7 = 4'h7 == idx_7 ? muxbits_1_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_8 = 4'h8 == idx_7 ? muxbits_1_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_9 = 4'h9 == idx_7 ? muxbits_1_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_10 = 4'ha == idx_7 ? muxbits_1_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_11 = 4'hb == idx_7 ? muxbits_1_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_12 = 4'hc == idx_7 ? muxbits_1_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_13 = 4'hd == idx_7 ? muxbits_1_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_14 = 4'he == idx_7 ? muxbits_1_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_5_15 = 4'hf == idx_7 ? muxbits_1_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] bits_3_value_6_0 = bits_3_value_5_0 | bits_3_value_5_1; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_6_1 = bits_3_value_5_2 | bits_3_value_5_3; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_6_2 = bits_3_value_5_4 | bits_3_value_5_5; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_6_3 = bits_3_value_5_6 | bits_3_value_5_7; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_6_4 = bits_3_value_5_8 | bits_3_value_5_9; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_6_5 = bits_3_value_5_10 | bits_3_value_5_11; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_6_6 = bits_3_value_5_12 | bits_3_value_5_13; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_6_7 = bits_3_value_5_14 | bits_3_value_5_15; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_7_0 = bits_3_value_6_0 | bits_3_value_6_1; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_7_1 = bits_3_value_6_2 | bits_3_value_6_3; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_7_2 = bits_3_value_6_4 | bits_3_value_6_5; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_7_3 = bits_3_value_6_6 | bits_3_value_6_7; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_8_0 = bits_3_value_7_0 | bits_3_value_7_1; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_8_1 = bits_3_value_7_2 | bits_3_value_7_3; // @[Library.scala 129:37]
- wire [31:0] bits_3_value_9_0 = bits_3_value_8_0 | bits_3_value_8_1; // @[Library.scala 129:37]
- wire [3:0] brchValidEx = {vvalid_1_3,vvalid_1_2,vvalid_1_1,match0_2}; // @[Fetch.scala 415:20]
- wire _brchValidDeMask_T = ~brchTakenDe0; // @[Fetch.scala 454:11]
- wire _brchValidDeMask_T_1 = ~brchTakenDe1; // @[Fetch.scala 454:28]
- wire _brchValidDeMask_T_2 = ~brchTakenDe0 & ~brchTakenDe1; // @[Fetch.scala 454:25]
- wire _brchValidDeMask_T_3 = ~brchTakenDe2; // @[Fetch.scala 454:45]
- wire _brchValidDeMask_T_4 = ~brchTakenDe0 & ~brchTakenDe1 & ~brchTakenDe2; // @[Fetch.scala 454:42]
- wire [3:0] brchValidDeMask = {_brchValidDeMask_T_4,_brchValidDeMask_T_2,_brchValidDeMask_T,1'h1}; // @[Cat.scala 31:58]
- wire _brchFwd_T_5 = brchTakenDe3 & _brchValidDeMask_T & _brchValidDeMask_T_1 & _brchValidDeMask_T_3; // @[Fetch.scala 460:54]
- wire _brchFwd_T_9 = brchTakenDe2 & _brchValidDeMask_T & _brchValidDeMask_T_1; // @[Fetch.scala 461:37]
- wire _brchFwd_T_11 = brchTakenDe1 & _brchValidDeMask_T; // @[Fetch.scala 462:20]
- wire [3:0] brchFwd = {_brchFwd_T_5,_brchFwd_T_9,_brchFwd_T_11,brchTakenDe0}; // @[Cat.scala 31:58]
- wire nxtInstValid_1 = nxtInstAddr_0[4:2] <= 3'h6 ? nxtMatch0 : nxtMatch1; // @[Fetch.scala 467:27]
- wire nxtInstValid_3 = nxtInstAddr_0[4:2] <= 3'h4 ? nxtMatch0 : nxtMatch1; // @[Fetch.scala 467:27]
- wire nxtInstValid_2 = nxtInstAddr_0[4:2] <= 3'h5 ? nxtMatch0 : nxtMatch1; // @[Fetch.scala 467:27]
- wire [3:0] nxtInstValidUInt = {nxtInstValid_3,nxtInstValid_2,nxtInstValid_1,nxtMatch0}; // @[Fetch.scala 469:41]
- wire _instValid_0_T_9 = brchTakenDe ? brchValidDe[0] : nxtInstValidUInt[0]; // @[Fetch.scala 471:24]
- wire _instValid_0_T_10 = brchTakenEx ? brchValidEx[0] : _instValid_0_T_9; // @[Fetch.scala 470:24]
- wire _idx_T_34 = instAddr_0[5] != nxtInstAddr_0[5]; // @[Fetch.scala 480:34]
- wire [3:0] idx_8 = {_idx_T_34,nxtInstAddr_0[4:2]}; // @[Cat.scala 31:58]
- wire [31:0] instBits_0_value__0 = 4'h0 == idx_8 ? nxtInstBits_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__1 = 4'h1 == idx_8 ? nxtInstBits_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__2 = 4'h2 == idx_8 ? nxtInstBits_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__3 = 4'h3 == idx_8 ? nxtInstBits_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__4 = 4'h4 == idx_8 ? nxtInstBits_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__5 = 4'h5 == idx_8 ? nxtInstBits_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__6 = 4'h6 == idx_8 ? nxtInstBits_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__7 = 4'h7 == idx_8 ? nxtInstBits_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__8 = 4'h8 == idx_8 ? nxtInstBits_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__9 = 4'h9 == idx_8 ? nxtInstBits_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__10 = 4'ha == idx_8 ? nxtInstBits_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__11 = 4'hb == idx_8 ? nxtInstBits_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__12 = 4'hc == idx_8 ? nxtInstBits_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__13 = 4'hd == idx_8 ? nxtInstBits_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__14 = 4'he == idx_8 ? nxtInstBits_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value__15 = 4'hf == idx_8 ? nxtInstBits_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_0_value_1_0 = instBits_0_value__0 | instBits_0_value__1; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_1_1 = instBits_0_value__2 | instBits_0_value__3; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_1_2 = instBits_0_value__4 | instBits_0_value__5; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_1_3 = instBits_0_value__6 | instBits_0_value__7; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_1_4 = instBits_0_value__8 | instBits_0_value__9; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_1_5 = instBits_0_value__10 | instBits_0_value__11; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_1_6 = instBits_0_value__12 | instBits_0_value__13; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_1_7 = instBits_0_value__14 | instBits_0_value__15; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_2_0 = instBits_0_value_1_0 | instBits_0_value_1_1; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_2_1 = instBits_0_value_1_2 | instBits_0_value_1_3; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_2_2 = instBits_0_value_1_4 | instBits_0_value_1_5; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_2_3 = instBits_0_value_1_6 | instBits_0_value_1_7; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_3_0 = instBits_0_value_2_0 | instBits_0_value_2_1; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_3_1 = instBits_0_value_2_2 | instBits_0_value_2_3; // @[Library.scala 129:37]
- wire [31:0] instBits_0_value_4_0 = instBits_0_value_3_0 | instBits_0_value_3_1; // @[Library.scala 129:37]
- wire _instValid_1_T_8 = nxtInstValidUInt[1:0] == 2'h3; // @[Fetch.scala 472:43]
- wire _instValid_1_T_9 = brchTakenDe ? brchValidDe[1:0] == 2'h3 : _instValid_1_T_8; // @[Fetch.scala 471:24]
- wire _instValid_1_T_10 = brchTakenEx ? brchValidEx[1:0] == 2'h3 : _instValid_1_T_9; // @[Fetch.scala 470:24]
- wire _idx_T_38 = instAddr_0[5] != nxtInstAddr_1[5]; // @[Fetch.scala 480:34]
- wire [3:0] idx_9 = {_idx_T_38,nxtInstAddr_1[4:2]}; // @[Cat.scala 31:58]
- wire [31:0] instBits_1_value__0 = 4'h0 == idx_9 ? nxtInstBits_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__1 = 4'h1 == idx_9 ? nxtInstBits_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__2 = 4'h2 == idx_9 ? nxtInstBits_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__3 = 4'h3 == idx_9 ? nxtInstBits_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__4 = 4'h4 == idx_9 ? nxtInstBits_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__5 = 4'h5 == idx_9 ? nxtInstBits_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__6 = 4'h6 == idx_9 ? nxtInstBits_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__7 = 4'h7 == idx_9 ? nxtInstBits_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__8 = 4'h8 == idx_9 ? nxtInstBits_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__9 = 4'h9 == idx_9 ? nxtInstBits_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__10 = 4'ha == idx_9 ? nxtInstBits_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__11 = 4'hb == idx_9 ? nxtInstBits_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__12 = 4'hc == idx_9 ? nxtInstBits_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__13 = 4'hd == idx_9 ? nxtInstBits_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__14 = 4'he == idx_9 ? nxtInstBits_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value__15 = 4'hf == idx_9 ? nxtInstBits_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_1_value_1_0 = instBits_1_value__0 | instBits_1_value__1; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_1_1 = instBits_1_value__2 | instBits_1_value__3; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_1_2 = instBits_1_value__4 | instBits_1_value__5; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_1_3 = instBits_1_value__6 | instBits_1_value__7; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_1_4 = instBits_1_value__8 | instBits_1_value__9; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_1_5 = instBits_1_value__10 | instBits_1_value__11; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_1_6 = instBits_1_value__12 | instBits_1_value__13; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_1_7 = instBits_1_value__14 | instBits_1_value__15; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_2_0 = instBits_1_value_1_0 | instBits_1_value_1_1; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_2_1 = instBits_1_value_1_2 | instBits_1_value_1_3; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_2_2 = instBits_1_value_1_4 | instBits_1_value_1_5; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_2_3 = instBits_1_value_1_6 | instBits_1_value_1_7; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_3_0 = instBits_1_value_2_0 | instBits_1_value_2_1; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_3_1 = instBits_1_value_2_2 | instBits_1_value_2_3; // @[Library.scala 129:37]
- wire [31:0] instBits_1_value_4_0 = instBits_1_value_3_0 | instBits_1_value_3_1; // @[Library.scala 129:37]
- wire _instValid_2_T_8 = nxtInstValidUInt[2:0] == 3'h7; // @[Fetch.scala 472:43]
- wire _instValid_2_T_9 = brchTakenDe ? brchValidDe[2:0] == 3'h7 : _instValid_2_T_8; // @[Fetch.scala 471:24]
- wire _instValid_2_T_10 = brchTakenEx ? brchValidEx[2:0] == 3'h7 : _instValid_2_T_9; // @[Fetch.scala 470:24]
- wire _idx_T_42 = instAddr_0[5] != nxtInstAddr_2[5]; // @[Fetch.scala 480:34]
- wire [3:0] idx_10 = {_idx_T_42,nxtInstAddr_2[4:2]}; // @[Cat.scala 31:58]
- wire [31:0] instBits_2_value__0 = 4'h0 == idx_10 ? nxtInstBits_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__1 = 4'h1 == idx_10 ? nxtInstBits_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__2 = 4'h2 == idx_10 ? nxtInstBits_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__3 = 4'h3 == idx_10 ? nxtInstBits_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__4 = 4'h4 == idx_10 ? nxtInstBits_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__5 = 4'h5 == idx_10 ? nxtInstBits_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__6 = 4'h6 == idx_10 ? nxtInstBits_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__7 = 4'h7 == idx_10 ? nxtInstBits_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__8 = 4'h8 == idx_10 ? nxtInstBits_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__9 = 4'h9 == idx_10 ? nxtInstBits_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__10 = 4'ha == idx_10 ? nxtInstBits_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__11 = 4'hb == idx_10 ? nxtInstBits_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__12 = 4'hc == idx_10 ? nxtInstBits_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__13 = 4'hd == idx_10 ? nxtInstBits_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__14 = 4'he == idx_10 ? nxtInstBits_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value__15 = 4'hf == idx_10 ? nxtInstBits_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_2_value_1_0 = instBits_2_value__0 | instBits_2_value__1; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_1_1 = instBits_2_value__2 | instBits_2_value__3; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_1_2 = instBits_2_value__4 | instBits_2_value__5; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_1_3 = instBits_2_value__6 | instBits_2_value__7; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_1_4 = instBits_2_value__8 | instBits_2_value__9; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_1_5 = instBits_2_value__10 | instBits_2_value__11; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_1_6 = instBits_2_value__12 | instBits_2_value__13; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_1_7 = instBits_2_value__14 | instBits_2_value__15; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_2_0 = instBits_2_value_1_0 | instBits_2_value_1_1; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_2_1 = instBits_2_value_1_2 | instBits_2_value_1_3; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_2_2 = instBits_2_value_1_4 | instBits_2_value_1_5; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_2_3 = instBits_2_value_1_6 | instBits_2_value_1_7; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_3_0 = instBits_2_value_2_0 | instBits_2_value_2_1; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_3_1 = instBits_2_value_2_2 | instBits_2_value_2_3; // @[Library.scala 129:37]
- wire [31:0] instBits_2_value_4_0 = instBits_2_value_3_0 | instBits_2_value_3_1; // @[Library.scala 129:37]
- wire _instValid_3_T_8 = nxtInstValidUInt == 4'hf; // @[Fetch.scala 472:43]
- wire _instValid_3_T_9 = brchTakenDe ? brchValidDe == 4'hf : _instValid_3_T_8; // @[Fetch.scala 471:24]
- wire _instValid_3_T_10 = brchTakenEx ? brchValidEx == 4'hf : _instValid_3_T_9; // @[Fetch.scala 470:24]
- wire _idx_T_46 = instAddr_0[5] != nxtInstAddr_3[5]; // @[Fetch.scala 480:34]
- wire [3:0] idx_11 = {_idx_T_46,nxtInstAddr_3[4:2]}; // @[Cat.scala 31:58]
- wire [31:0] instBits_3_value__0 = 4'h0 == idx_11 ? nxtInstBits_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__1 = 4'h1 == idx_11 ? nxtInstBits_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__2 = 4'h2 == idx_11 ? nxtInstBits_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__3 = 4'h3 == idx_11 ? nxtInstBits_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__4 = 4'h4 == idx_11 ? nxtInstBits_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__5 = 4'h5 == idx_11 ? nxtInstBits_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__6 = 4'h6 == idx_11 ? nxtInstBits_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__7 = 4'h7 == idx_11 ? nxtInstBits_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__8 = 4'h8 == idx_11 ? nxtInstBits_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__9 = 4'h9 == idx_11 ? nxtInstBits_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__10 = 4'ha == idx_11 ? nxtInstBits_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__11 = 4'hb == idx_11 ? nxtInstBits_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__12 = 4'hc == idx_11 ? nxtInstBits_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__13 = 4'hd == idx_11 ? nxtInstBits_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__14 = 4'he == idx_11 ? nxtInstBits_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value__15 = 4'hf == idx_11 ? nxtInstBits_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] instBits_3_value_1_0 = instBits_3_value__0 | instBits_3_value__1; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_1_1 = instBits_3_value__2 | instBits_3_value__3; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_1_2 = instBits_3_value__4 | instBits_3_value__5; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_1_3 = instBits_3_value__6 | instBits_3_value__7; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_1_4 = instBits_3_value__8 | instBits_3_value__9; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_1_5 = instBits_3_value__10 | instBits_3_value__11; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_1_6 = instBits_3_value__12 | instBits_3_value__13; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_1_7 = instBits_3_value__14 | instBits_3_value__15; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_2_0 = instBits_3_value_1_0 | instBits_3_value_1_1; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_2_1 = instBits_3_value_1_2 | instBits_3_value_1_3; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_2_2 = instBits_3_value_1_4 | instBits_3_value_1_5; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_2_3 = instBits_3_value_1_6 | instBits_3_value_1_7; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_3_0 = instBits_3_value_2_0 | instBits_3_value_2_1; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_3_1 = instBits_3_value_2_2 | instBits_3_value_2_3; // @[Library.scala 129:37]
- wire [31:0] instBits_3_value_4_0 = instBits_3_value_3_0 | instBits_3_value_3_1; // @[Library.scala 129:37]
- wire [31:0] addr = {io_csr_value_0[31:2],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] _instAddr_1_T_3 = addr + 32'h4; // @[Fetch.scala 490:25]
- wire [31:0] _instAddr_2_T_3 = addr + 32'h8; // @[Fetch.scala 491:25]
- wire [31:0] _instAddr_3_T_3 = addr + 32'hc; // @[Fetch.scala 492:25]
- wire [31:0] _T_77 = instAddr_0 + 32'h4; // @[Fetch.scala 504:22]
- wire _T_80 = ~reset; // @[Fetch.scala 504:9]
- wire [31:0] _T_83 = instAddr_0 + 32'h8; // @[Fetch.scala 505:22]
- wire [31:0] _T_89 = instAddr_0 + 32'hc; // @[Fetch.scala 506:22]
- wire [1:0] _T_99 = fsel[0] + fsel[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_101 = fsel[3] + fsel[4]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_75 = {{1'd0}, fsel[2]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_103 = _GEN_75 + _T_101; // @[Bitwise.scala 48:55]
- wire [2:0] _T_105 = _T_99 + _T_103[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] instValidUInt = {instValid_3,instValid_2,instValid_1,instValid_0}; // @[Fetch.scala 511:33]
- wire [3:0] instLanesReady = {io_inst_lanes_3_ready,io_inst_lanes_2_ready,io_inst_lanes_1_ready,io_inst_lanes_0_ready}; // @[Cat.scala 31:58]
- Slice aslice ( // @[Slice.scala 23:11]
- .clock(aslice_clock),
- .reset(aslice_reset),
- .io_in_ready(aslice_io_in_ready),
- .io_in_valid(aslice_io_in_valid),
- .io_in_bits(aslice_io_in_bits),
- .io_out_ready(aslice_io_out_ready),
- .io_out_valid(aslice_io_out_valid),
- .io_out_bits(aslice_io_out_bits)
- );
- assign io_ibus_valid = aslice_io_out_valid; // @[Fetch.scala 207:17]
- assign io_ibus_addr = aslice_io_out_bits; // @[Fetch.scala 209:16]
- assign io_inst_lanes_0_valid = instValid_0 & brchValidDeMask[0]; // @[Fetch.scala 497:44]
- assign io_inst_lanes_0_addr = instAddr_0; // @[Fetch.scala 498:28]
- assign io_inst_lanes_0_inst = instBits_0; // @[Fetch.scala 499:28]
- assign io_inst_lanes_0_brchFwd = brchFwd[0]; // @[Fetch.scala 500:40]
- assign io_inst_lanes_1_valid = instValid_1 & brchValidDeMask[1]; // @[Fetch.scala 497:44]
- assign io_inst_lanes_1_addr = instAddr_1; // @[Fetch.scala 498:28]
- assign io_inst_lanes_1_inst = instBits_1; // @[Fetch.scala 499:28]
- assign io_inst_lanes_1_brchFwd = brchFwd[1]; // @[Fetch.scala 500:40]
- assign io_inst_lanes_2_valid = instValid_2 & brchValidDeMask[2]; // @[Fetch.scala 497:44]
- assign io_inst_lanes_2_addr = instAddr_2; // @[Fetch.scala 498:28]
- assign io_inst_lanes_2_inst = instBits_2; // @[Fetch.scala 499:28]
- assign io_inst_lanes_2_brchFwd = brchFwd[2]; // @[Fetch.scala 500:40]
- assign io_inst_lanes_3_valid = instValid_3 & brchValidDeMask[3]; // @[Fetch.scala 497:44]
- assign io_inst_lanes_3_addr = instAddr_3; // @[Fetch.scala 498:28]
- assign io_inst_lanes_3_inst = instBits_3; // @[Fetch.scala 499:28]
- assign io_inst_lanes_3_brchFwd = brchFwd[3]; // @[Fetch.scala 500:40]
- assign io_iflush_ready = ~aslice_io_out_valid; // @[Fetch.scala 75:22]
- assign aslice_clock = clock;
- assign aslice_reset = reset;
- assign aslice_io_in_valid = (reqB0 | reqB1 | reqB2 | reqB3 | reqP | req0 | req1) & _readDataEn_T; // @[Fetch.scala 195:84]
- assign aslice_io_in_bits = reqB0 ? _aslice_io_in_bits_T_1 : _aslice_io_in_bits_T_14; // @[Fetch.scala 196:28]
- assign aslice_io_out_ready = io_ibus_ready | io_iflush_valid; // @[Fetch.scala 208:40]
- always @(posedge clock) begin
- if (readAddrEn) begin // @[Fetch.scala 203:21]
- readAddr <= io_ibus_addr; // @[Fetch.scala 204:14]
- end
- if (readDataEn & readIdx == 5'h0) begin // @[Fetch.scala 220:42]
- l0tag_0 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h1) begin // @[Fetch.scala 220:42]
- l0tag_1 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h2) begin // @[Fetch.scala 220:42]
- l0tag_2 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h3) begin // @[Fetch.scala 220:42]
- l0tag_3 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h4) begin // @[Fetch.scala 220:42]
- l0tag_4 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h5) begin // @[Fetch.scala 220:42]
- l0tag_5 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h6) begin // @[Fetch.scala 220:42]
- l0tag_6 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h7) begin // @[Fetch.scala 220:42]
- l0tag_7 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h8) begin // @[Fetch.scala 220:42]
- l0tag_8 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h9) begin // @[Fetch.scala 220:42]
- l0tag_9 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'ha) begin // @[Fetch.scala 220:42]
- l0tag_10 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'hb) begin // @[Fetch.scala 220:42]
- l0tag_11 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'hc) begin // @[Fetch.scala 220:42]
- l0tag_12 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'hd) begin // @[Fetch.scala 220:42]
- l0tag_13 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'he) begin // @[Fetch.scala 220:42]
- l0tag_14 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'hf) begin // @[Fetch.scala 220:42]
- l0tag_15 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h10) begin // @[Fetch.scala 220:42]
- l0tag_16 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h11) begin // @[Fetch.scala 220:42]
- l0tag_17 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h12) begin // @[Fetch.scala 220:42]
- l0tag_18 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h13) begin // @[Fetch.scala 220:42]
- l0tag_19 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h14) begin // @[Fetch.scala 220:42]
- l0tag_20 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h15) begin // @[Fetch.scala 220:42]
- l0tag_21 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h16) begin // @[Fetch.scala 220:42]
- l0tag_22 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h17) begin // @[Fetch.scala 220:42]
- l0tag_23 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h18) begin // @[Fetch.scala 220:42]
- l0tag_24 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h19) begin // @[Fetch.scala 220:42]
- l0tag_25 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h1a) begin // @[Fetch.scala 220:42]
- l0tag_26 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h1b) begin // @[Fetch.scala 220:42]
- l0tag_27 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h1c) begin // @[Fetch.scala 220:42]
- l0tag_28 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h1d) begin // @[Fetch.scala 220:42]
- l0tag_29 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h1e) begin // @[Fetch.scala 220:42]
- l0tag_30 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h1f) begin // @[Fetch.scala 220:42]
- l0tag_31 <= readAddr[31:10]; // @[Fetch.scala 221:19]
- end
- if (readDataEn & readIdx == 5'h0) begin // @[Fetch.scala 220:42]
- l0data_0 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h1) begin // @[Fetch.scala 220:42]
- l0data_1 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h2) begin // @[Fetch.scala 220:42]
- l0data_2 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h3) begin // @[Fetch.scala 220:42]
- l0data_3 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h4) begin // @[Fetch.scala 220:42]
- l0data_4 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h5) begin // @[Fetch.scala 220:42]
- l0data_5 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h6) begin // @[Fetch.scala 220:42]
- l0data_6 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h7) begin // @[Fetch.scala 220:42]
- l0data_7 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h8) begin // @[Fetch.scala 220:42]
- l0data_8 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h9) begin // @[Fetch.scala 220:42]
- l0data_9 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'ha) begin // @[Fetch.scala 220:42]
- l0data_10 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'hb) begin // @[Fetch.scala 220:42]
- l0data_11 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'hc) begin // @[Fetch.scala 220:42]
- l0data_12 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'hd) begin // @[Fetch.scala 220:42]
- l0data_13 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'he) begin // @[Fetch.scala 220:42]
- l0data_14 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'hf) begin // @[Fetch.scala 220:42]
- l0data_15 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h10) begin // @[Fetch.scala 220:42]
- l0data_16 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h11) begin // @[Fetch.scala 220:42]
- l0data_17 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h12) begin // @[Fetch.scala 220:42]
- l0data_18 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h13) begin // @[Fetch.scala 220:42]
- l0data_19 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h14) begin // @[Fetch.scala 220:42]
- l0data_20 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h15) begin // @[Fetch.scala 220:42]
- l0data_21 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h16) begin // @[Fetch.scala 220:42]
- l0data_22 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h17) begin // @[Fetch.scala 220:42]
- l0data_23 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h18) begin // @[Fetch.scala 220:42]
- l0data_24 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h19) begin // @[Fetch.scala 220:42]
- l0data_25 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h1a) begin // @[Fetch.scala 220:42]
- l0data_26 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h1b) begin // @[Fetch.scala 220:42]
- l0data_27 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h1c) begin // @[Fetch.scala 220:42]
- l0data_28 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h1d) begin // @[Fetch.scala 220:42]
- l0data_29 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h1e) begin // @[Fetch.scala 220:42]
- l0data_30 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (readDataEn & readIdx == 5'h1f) begin // @[Fetch.scala 220:42]
- l0data_31 <= io_ibus_rdata; // @[Fetch.scala 222:19]
- end
- if (reset) begin // @[Fetch.scala 487:23]
- instAddr_0 <= addr; // @[Fetch.scala 489:17]
- end else if (brchTakenEx) begin // @[Fetch.scala 474:23]
- if (io_branch_0_valid) begin // @[Fetch.scala 372:27]
- instAddr_0 <= io_branch_0_value;
- end else if (io_branch_1_valid) begin // @[Fetch.scala 373:27]
- instAddr_0 <= io_branch_1_value;
- end else begin
- instAddr_0 <= _addr_T_6;
- end
- end else if (brchTakenDe) begin // @[Fetch.scala 475:23]
- if (brchTakenDe0) begin // @[Fetch.scala 442:25]
- instAddr_0 <= brchTargetDe0;
- end else begin
- instAddr_0 <= _brchTargetDe_T_1;
- end
- end else begin
- instAddr_0 <= nxtInstAddr_0;
- end
- if (reset) begin // @[Fetch.scala 487:23]
- instAddr_1 <= _instAddr_1_T_3; // @[Fetch.scala 490:17]
- end else if (brchTakenEx) begin // @[Fetch.scala 474:23]
- if (io_branch_0_valid) begin // @[Fetch.scala 376:27]
- instAddr_1 <= _addr_T_10;
- end else if (io_branch_1_valid) begin // @[Fetch.scala 377:27]
- instAddr_1 <= _addr_T_12;
- end else begin
- instAddr_1 <= _addr_T_17;
- end
- end else if (brchTakenDe) begin // @[Fetch.scala 475:23]
- instAddr_1 <= brchAddrDe_1;
- end else begin
- instAddr_1 <= nxtInstAddr_1;
- end
- if (reset) begin // @[Fetch.scala 487:23]
- instAddr_2 <= _instAddr_2_T_3; // @[Fetch.scala 491:17]
- end else if (brchTakenEx) begin // @[Fetch.scala 474:23]
- if (io_branch_0_valid) begin // @[Fetch.scala 380:27]
- instAddr_2 <= _addr_T_21;
- end else if (io_branch_1_valid) begin // @[Fetch.scala 381:27]
- instAddr_2 <= _addr_T_23;
- end else begin
- instAddr_2 <= _addr_T_28;
- end
- end else if (brchTakenDe) begin // @[Fetch.scala 475:23]
- instAddr_2 <= brchAddrDe_2;
- end else begin
- instAddr_2 <= nxtInstAddr_2;
- end
- if (reset) begin // @[Fetch.scala 487:23]
- instAddr_3 <= _instAddr_3_T_3; // @[Fetch.scala 492:17]
- end else if (brchTakenEx) begin // @[Fetch.scala 474:23]
- if (io_branch_0_valid) begin // @[Fetch.scala 384:27]
- instAddr_3 <= _addr_T_32;
- end else if (io_branch_1_valid) begin // @[Fetch.scala 385:27]
- instAddr_3 <= _addr_T_34;
- end else begin
- instAddr_3 <= _addr_T_39;
- end
- end else if (brchTakenDe) begin // @[Fetch.scala 475:23]
- instAddr_3 <= brchAddrDe_3;
- end else begin
- instAddr_3 <= nxtInstAddr_3;
- end
- if (brchTakenEx) begin // @[Fetch.scala 481:23]
- instBits_0 <= bits_0_value_9_0;
- end else if (brchTakenDe) begin // @[Fetch.scala 482:23]
- instBits_0 <= bits_0_value_4_0;
- end else begin
- instBits_0 <= instBits_0_value_4_0;
- end
- if (brchTakenEx) begin // @[Fetch.scala 481:23]
- instBits_1 <= bits_1_value_9_0;
- end else if (brchTakenDe) begin // @[Fetch.scala 482:23]
- instBits_1 <= bits_1_value_4_0;
- end else begin
- instBits_1 <= instBits_1_value_4_0;
- end
- if (brchTakenEx) begin // @[Fetch.scala 481:23]
- instBits_2 <= bits_2_value_9_0;
- end else if (brchTakenDe) begin // @[Fetch.scala 482:23]
- instBits_2 <= bits_2_value_4_0;
- end else begin
- instBits_2 <= instBits_2_value_4_0;
- end
- if (brchTakenEx) begin // @[Fetch.scala 481:23]
- instBits_3 <= bits_3_value_9_0;
- end else if (brchTakenDe) begin // @[Fetch.scala 482:23]
- instBits_3 <= bits_3_value_4_0;
- end else begin
- instBits_3 <= instBits_3_value_4_0;
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_77 == instAddr_1)) begin
- $fatal; // @[Fetch.scala 504:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_77 == instAddr_1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Fetch.scala:504 assert(instAddr(0) + 4.U === instAddr(1))\n"); // @[Fetch.scala 504:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_80 & ~(_T_83 == instAddr_2)) begin
- $fatal; // @[Fetch.scala 505:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_80 & ~(_T_83 == instAddr_2)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Fetch.scala:505 assert(instAddr(0) + 8.U === instAddr(2))\n"); // @[Fetch.scala 505:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_80 & ~(_T_89 == instAddr_3)) begin
- $fatal; // @[Fetch.scala 506:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_80 & ~(_T_89 == instAddr_3)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Fetch.scala:506 assert(instAddr(0) + 12.U === instAddr(3))\n"); // @[Fetch.scala 506:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_80 & ~(_T_105 <= 3'h1)) begin
- $fatal; // @[Fetch.scala 509:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_80 & ~(_T_105 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Fetch.scala:509 assert(PopCount(fsel) <= 1.U)\n"); // @[Fetch.scala 509:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_80 & ~(~(~instValidUInt[0] & instValidUInt[3:1] != 3'h0))) begin
- $fatal; // @[Fetch.scala 512:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_80 & ~(~(~instValidUInt[0] & instValidUInt[3:1] != 3'h0))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fetch.scala:512 assert(!(!instValidUInt(0) && (instValidUInt(3,1) =/= 0.U)))\n"); // @[Fetch.scala 512:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_80 & ~(~(~instValidUInt[1] & instValidUInt[3:2] != 2'h0))) begin
- $fatal; // @[Fetch.scala 513:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_80 & ~(~(~instValidUInt[1] & instValidUInt[3:2] != 2'h0))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fetch.scala:513 assert(!(!instValidUInt(1) && (instValidUInt(3,2) =/= 0.U)))\n"); // @[Fetch.scala 513:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_80 & ~(~(~instValidUInt[2] & instValidUInt[3]))) begin
- $fatal; // @[Fetch.scala 514:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_80 & ~(~(~instValidUInt[2] & instValidUInt[3]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fetch.scala:514 assert(!(!instValidUInt(2) && (instValidUInt(3,3) =/= 0.U)))\n"); // @[Fetch.scala 514:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_80 & ~(~(~instLanesReady[0] & instLanesReady[3:1] != 3'h0))) begin
- $fatal; // @[Fetch.scala 518:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_80 & ~(~(~instLanesReady[0] & instLanesReady[3:1] != 3'h0))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fetch.scala:518 assert(!(!instLanesReady(0) && (instLanesReady(3,1) =/= 0.U)))\n"
- ); // @[Fetch.scala 518:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_80 & ~(~(~instLanesReady[1] & instLanesReady[3:2] != 2'h0))) begin
- $fatal; // @[Fetch.scala 519:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_80 & ~(~(~instLanesReady[1] & instLanesReady[3:2] != 2'h0))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fetch.scala:519 assert(!(!instLanesReady(1) && (instLanesReady(3,2) =/= 0.U)))\n"
- ); // @[Fetch.scala 519:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_80 & ~(~(~instLanesReady[2] & instLanesReady[3]))) begin
- $fatal; // @[Fetch.scala 520:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_80 & ~(~(~instLanesReady[2] & instLanesReady[3]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fetch.scala:520 assert(!(!instLanesReady(2) && (instLanesReady(3,3) =/= 0.U)))\n"
- ); // @[Fetch.scala 520:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fetch.scala 73:28]
- readDataEn <= 1'h0;
- end else begin
- readDataEn <= readAddrEn & ~io_iflush_valid;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fetch.scala 242:51]
- l0valid <= 32'h0; // @[Fetch.scala 243:13]
- end else if (l0validClr != 32'h0 | l0validSet != 32'h0) begin // @[Fetch.scala 99:24]
- l0valid <= _l0valid_T_2;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fetch.scala 246:47]
- l0req <= 32'h0; // @[Fetch.scala 247:11]
- end else if (l0reqClr != 32'h0 | l0reqSet != 32'h0) begin // @[Fetch.scala 100:24]
- l0req <= _l0req_T_2;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fetch.scala 472:63]
- instValid_0 <= 1'h0;
- end else begin
- instValid_0 <= _instValid_0_T_10 & _readDataEn_T;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fetch.scala 472:63]
- instValid_1 <= 1'h0;
- end else begin
- instValid_1 <= _instValid_1_T_10 & _readDataEn_T;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fetch.scala 472:63]
- instValid_2 <= 1'h0;
- end else begin
- instValid_2 <= _instValid_2_T_10 & _readDataEn_T;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fetch.scala 472:63]
- instValid_3 <= 1'h0;
- end else begin
- instValid_3 <= _instValid_3_T_10 & _readDataEn_T;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- readAddr = _RAND_0[31:0];
- _RAND_1 = {1{`RANDOM}};
- readDataEn = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- l0valid = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- l0req = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- l0tag_0 = _RAND_4[21:0];
- _RAND_5 = {1{`RANDOM}};
- l0tag_1 = _RAND_5[21:0];
- _RAND_6 = {1{`RANDOM}};
- l0tag_2 = _RAND_6[21:0];
- _RAND_7 = {1{`RANDOM}};
- l0tag_3 = _RAND_7[21:0];
- _RAND_8 = {1{`RANDOM}};
- l0tag_4 = _RAND_8[21:0];
- _RAND_9 = {1{`RANDOM}};
- l0tag_5 = _RAND_9[21:0];
- _RAND_10 = {1{`RANDOM}};
- l0tag_6 = _RAND_10[21:0];
- _RAND_11 = {1{`RANDOM}};
- l0tag_7 = _RAND_11[21:0];
- _RAND_12 = {1{`RANDOM}};
- l0tag_8 = _RAND_12[21:0];
- _RAND_13 = {1{`RANDOM}};
- l0tag_9 = _RAND_13[21:0];
- _RAND_14 = {1{`RANDOM}};
- l0tag_10 = _RAND_14[21:0];
- _RAND_15 = {1{`RANDOM}};
- l0tag_11 = _RAND_15[21:0];
- _RAND_16 = {1{`RANDOM}};
- l0tag_12 = _RAND_16[21:0];
- _RAND_17 = {1{`RANDOM}};
- l0tag_13 = _RAND_17[21:0];
- _RAND_18 = {1{`RANDOM}};
- l0tag_14 = _RAND_18[21:0];
- _RAND_19 = {1{`RANDOM}};
- l0tag_15 = _RAND_19[21:0];
- _RAND_20 = {1{`RANDOM}};
- l0tag_16 = _RAND_20[21:0];
- _RAND_21 = {1{`RANDOM}};
- l0tag_17 = _RAND_21[21:0];
- _RAND_22 = {1{`RANDOM}};
- l0tag_18 = _RAND_22[21:0];
- _RAND_23 = {1{`RANDOM}};
- l0tag_19 = _RAND_23[21:0];
- _RAND_24 = {1{`RANDOM}};
- l0tag_20 = _RAND_24[21:0];
- _RAND_25 = {1{`RANDOM}};
- l0tag_21 = _RAND_25[21:0];
- _RAND_26 = {1{`RANDOM}};
- l0tag_22 = _RAND_26[21:0];
- _RAND_27 = {1{`RANDOM}};
- l0tag_23 = _RAND_27[21:0];
- _RAND_28 = {1{`RANDOM}};
- l0tag_24 = _RAND_28[21:0];
- _RAND_29 = {1{`RANDOM}};
- l0tag_25 = _RAND_29[21:0];
- _RAND_30 = {1{`RANDOM}};
- l0tag_26 = _RAND_30[21:0];
- _RAND_31 = {1{`RANDOM}};
- l0tag_27 = _RAND_31[21:0];
- _RAND_32 = {1{`RANDOM}};
- l0tag_28 = _RAND_32[21:0];
- _RAND_33 = {1{`RANDOM}};
- l0tag_29 = _RAND_33[21:0];
- _RAND_34 = {1{`RANDOM}};
- l0tag_30 = _RAND_34[21:0];
- _RAND_35 = {1{`RANDOM}};
- l0tag_31 = _RAND_35[21:0];
- _RAND_36 = {8{`RANDOM}};
- l0data_0 = _RAND_36[255:0];
- _RAND_37 = {8{`RANDOM}};
- l0data_1 = _RAND_37[255:0];
- _RAND_38 = {8{`RANDOM}};
- l0data_2 = _RAND_38[255:0];
- _RAND_39 = {8{`RANDOM}};
- l0data_3 = _RAND_39[255:0];
- _RAND_40 = {8{`RANDOM}};
- l0data_4 = _RAND_40[255:0];
- _RAND_41 = {8{`RANDOM}};
- l0data_5 = _RAND_41[255:0];
- _RAND_42 = {8{`RANDOM}};
- l0data_6 = _RAND_42[255:0];
- _RAND_43 = {8{`RANDOM}};
- l0data_7 = _RAND_43[255:0];
- _RAND_44 = {8{`RANDOM}};
- l0data_8 = _RAND_44[255:0];
- _RAND_45 = {8{`RANDOM}};
- l0data_9 = _RAND_45[255:0];
- _RAND_46 = {8{`RANDOM}};
- l0data_10 = _RAND_46[255:0];
- _RAND_47 = {8{`RANDOM}};
- l0data_11 = _RAND_47[255:0];
- _RAND_48 = {8{`RANDOM}};
- l0data_12 = _RAND_48[255:0];
- _RAND_49 = {8{`RANDOM}};
- l0data_13 = _RAND_49[255:0];
- _RAND_50 = {8{`RANDOM}};
- l0data_14 = _RAND_50[255:0];
- _RAND_51 = {8{`RANDOM}};
- l0data_15 = _RAND_51[255:0];
- _RAND_52 = {8{`RANDOM}};
- l0data_16 = _RAND_52[255:0];
- _RAND_53 = {8{`RANDOM}};
- l0data_17 = _RAND_53[255:0];
- _RAND_54 = {8{`RANDOM}};
- l0data_18 = _RAND_54[255:0];
- _RAND_55 = {8{`RANDOM}};
- l0data_19 = _RAND_55[255:0];
- _RAND_56 = {8{`RANDOM}};
- l0data_20 = _RAND_56[255:0];
- _RAND_57 = {8{`RANDOM}};
- l0data_21 = _RAND_57[255:0];
- _RAND_58 = {8{`RANDOM}};
- l0data_22 = _RAND_58[255:0];
- _RAND_59 = {8{`RANDOM}};
- l0data_23 = _RAND_59[255:0];
- _RAND_60 = {8{`RANDOM}};
- l0data_24 = _RAND_60[255:0];
- _RAND_61 = {8{`RANDOM}};
- l0data_25 = _RAND_61[255:0];
- _RAND_62 = {8{`RANDOM}};
- l0data_26 = _RAND_62[255:0];
- _RAND_63 = {8{`RANDOM}};
- l0data_27 = _RAND_63[255:0];
- _RAND_64 = {8{`RANDOM}};
- l0data_28 = _RAND_64[255:0];
- _RAND_65 = {8{`RANDOM}};
- l0data_29 = _RAND_65[255:0];
- _RAND_66 = {8{`RANDOM}};
- l0data_30 = _RAND_66[255:0];
- _RAND_67 = {8{`RANDOM}};
- l0data_31 = _RAND_67[255:0];
- _RAND_68 = {1{`RANDOM}};
- instValid_0 = _RAND_68[0:0];
- _RAND_69 = {1{`RANDOM}};
- instValid_1 = _RAND_69[0:0];
- _RAND_70 = {1{`RANDOM}};
- instValid_2 = _RAND_70[0:0];
- _RAND_71 = {1{`RANDOM}};
- instValid_3 = _RAND_71[0:0];
- _RAND_72 = {1{`RANDOM}};
- instAddr_0 = _RAND_72[31:0];
- _RAND_73 = {1{`RANDOM}};
- instAddr_1 = _RAND_73[31:0];
- _RAND_74 = {1{`RANDOM}};
- instAddr_2 = _RAND_74[31:0];
- _RAND_75 = {1{`RANDOM}};
- instAddr_3 = _RAND_75[31:0];
- _RAND_76 = {1{`RANDOM}};
- instBits_0 = _RAND_76[31:0];
- _RAND_77 = {1{`RANDOM}};
- instBits_1 = _RAND_77[31:0];
- _RAND_78 = {1{`RANDOM}};
- instBits_2 = _RAND_78[31:0];
- _RAND_79 = {1{`RANDOM}};
- instBits_3 = _RAND_79[31:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- readDataEn = 1'h0;
- end
- if (reset) begin
- l0valid = 32'h0;
- end
- if (reset) begin
- l0req = 32'h0;
- end
- if (reset) begin
- instValid_0 = 1'h0;
- end
- if (reset) begin
- instValid_1 = 1'h0;
- end
- if (reset) begin
- instValid_2 = 1'h0;
- end
- if (reset) begin
- instValid_3 = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module DecodedInstruction(
- input clock,
- input reset,
- input [31:0] io_addr,
- input [31:0] io_inst,
- output [31:0] io_imm12,
- output [31:0] io_imm20,
- output [31:0] io_immjal,
- output [31:0] io_immbr,
- output [31:0] io_immcsr,
- output [31:0] io_immst,
- output io_lui,
- output io_auipc,
- output io_jal,
- output io_jalr,
- output io_beq,
- output io_bne,
- output io_blt,
- output io_bge,
- output io_bltu,
- output io_bgeu,
- output io_csrrw,
- output io_csrrs,
- output io_csrrc,
- output io_lb,
- output io_lh,
- output io_lw,
- output io_lbu,
- output io_lhu,
- output io_sb,
- output io_sh,
- output io_sw,
- output io_fence,
- output io_addi,
- output io_slti,
- output io_sltiu,
- output io_xori,
- output io_ori,
- output io_andi,
- output io_slli,
- output io_srli,
- output io_srai,
- output io_add,
- output io_sub,
- output io_slt,
- output io_sltu,
- output io_xor,
- output io_or,
- output io_and,
- output io_sll,
- output io_srl,
- output io_sra,
- output io_mul,
- output io_mulh,
- output io_mulhsu,
- output io_mulhu,
- output io_mulhr,
- output io_mulhsur,
- output io_mulhur,
- output io_dmulh,
- output io_dmulhr,
- output io_div,
- output io_divu,
- output io_rem,
- output io_remu,
- output io_clz,
- output io_ctz,
- output io_pcnt,
- output io_min,
- output io_minu,
- output io_max,
- output io_maxu,
- output io_getvl,
- output io_getmaxvl,
- output io_vld,
- output io_vst,
- output io_viop,
- output io_ebreak,
- output io_ecall,
- output io_eexit,
- output io_eyield,
- output io_ectxsw,
- output io_mpause,
- output io_mret,
- output io_undef,
- output io_fencei,
- output io_flushat,
- output io_flushall,
- output io_slog
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
-`endif // RANDOMIZE_REG_INIT
- wire [19:0] _io_imm12_T_2 = io_inst[31] ? 20'hfffff : 20'h0; // @[Bitwise.scala 74:12]
- wire [11:0] _io_immjal_T_2 = io_inst[31] ? 12'hfff : 12'h0; // @[Bitwise.scala 74:12]
- wire [10:0] io_immjal_lo = {io_inst[30:21],1'h0}; // @[Cat.scala 31:58]
- wire [20:0] io_immjal_hi = {_io_immjal_T_2,io_inst[19:12],io_inst[20]}; // @[Cat.scala 31:58]
- wire [4:0] io_immbr_lo = {io_inst[11:8],1'h0}; // @[Cat.scala 31:58]
- wire [26:0] io_immbr_hi = {_io_imm12_T_2,io_inst[7],io_inst[30:25]}; // @[Cat.scala 31:58]
- wire [26:0] io_immst_hi = {_io_imm12_T_2,io_inst[31:25]}; // @[Cat.scala 31:58]
- wire io_lui_bit_1 = io_inst[30]; // @[Library.scala 332:23]
- wire io_lui_bit_2 = io_inst[29]; // @[Library.scala 332:23]
- wire io_lui_bit_3 = io_inst[28]; // @[Library.scala 332:23]
- wire io_lui_bit_4 = io_inst[27]; // @[Library.scala 332:23]
- wire io_lui_bit_5 = io_inst[26]; // @[Library.scala 332:23]
- wire io_lui_bit_6 = io_inst[25]; // @[Library.scala 332:23]
- wire io_lui_bit_7 = io_inst[24]; // @[Library.scala 332:23]
- wire io_lui_bit_8 = io_inst[23]; // @[Library.scala 332:23]
- wire io_lui_bit_9 = io_inst[22]; // @[Library.scala 332:23]
- wire io_lui_bit_10 = io_inst[21]; // @[Library.scala 332:23]
- wire io_lui_bit_12 = io_inst[19]; // @[Library.scala 332:23]
- wire io_lui_bit_13 = io_inst[18]; // @[Library.scala 332:23]
- wire io_lui_bit_14 = io_inst[17]; // @[Library.scala 332:23]
- wire io_lui_bit_15 = io_inst[16]; // @[Library.scala 332:23]
- wire io_lui_bit_16 = io_inst[15]; // @[Library.scala 332:23]
- wire io_lui_bit_17 = io_inst[14]; // @[Library.scala 332:23]
- wire io_lui_bit_18 = io_inst[13]; // @[Library.scala 332:23]
- wire io_lui_bit_19 = io_inst[12]; // @[Library.scala 332:23]
- wire io_lui_bit_20 = io_inst[11]; // @[Library.scala 332:23]
- wire io_lui_bit_21 = io_inst[10]; // @[Library.scala 332:23]
- wire io_lui_bit_22 = io_inst[9]; // @[Library.scala 332:23]
- wire io_lui_bit_23 = io_inst[8]; // @[Library.scala 332:23]
- wire io_lui_bit_25 = ~io_inst[6]; // @[Library.scala 326:19]
- wire io_lui_bit_26 = io_inst[5]; // @[Library.scala 329:23]
- wire io_lui_bit_27 = io_inst[4]; // @[Library.scala 329:23]
- wire _io_lui_T_2 = io_lui_bit_25 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire io_lui_bit_28 = ~io_inst[3]; // @[Library.scala 326:19]
- wire _io_lui_T_3 = _io_lui_T_2 & io_lui_bit_28; // @[Library.scala 327:48]
- wire io_lui_bit_29 = io_inst[2]; // @[Library.scala 329:23]
- wire io_lui_bit_30 = io_inst[1]; // @[Library.scala 329:23]
- wire io_lui_bit_31 = io_inst[0]; // @[Library.scala 329:23]
- wire io_auipc_bit_26 = ~io_lui_bit_26; // @[Library.scala 326:19]
- wire _io_auipc_T_1 = io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_auipc_T_2 = _io_auipc_T_1 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_auipc_T_3 = _io_auipc_T_2 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_jal_T_1 = io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire io_jal_bit_27 = ~io_lui_bit_27; // @[Library.scala 326:19]
- wire _io_jal_T_2 = _io_jal_T_1 & io_jal_bit_27; // @[Library.scala 327:48]
- wire io_jalr_bit_17 = ~io_lui_bit_17; // @[Library.scala 326:19]
- wire io_jalr_bit_18 = ~io_lui_bit_18; // @[Library.scala 326:19]
- wire _io_jalr_T_1 = io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire io_jalr_bit_19 = ~io_lui_bit_19; // @[Library.scala 326:19]
- wire _io_jalr_T_2 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_jalr_T_4 = _io_jalr_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_jalr_T_6 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 327:48]
- wire io_beq_bit_29 = ~io_lui_bit_29; // @[Library.scala 326:19]
- wire _io_beq_T_7 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bne_T_2 = _io_jalr_T_1 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_bne_T_4 = _io_jalr_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bne_T_7 = _io_bne_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_blt_T_1 = io_lui_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_blt_T_2 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_blt_T_4 = _io_blt_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_blt_T_7 = _io_blt_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bge_T_2 = _io_blt_T_1 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_bge_T_4 = _io_blt_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bge_T_7 = _io_bge_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bltu_T_1 = io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_bltu_T_2 = _io_bltu_T_1 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_bltu_T_4 = _io_bltu_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bltu_T_7 = _io_bltu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bgeu_T_2 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_bgeu_T_4 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bgeu_T_7 = _io_bgeu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_csrrw_T_4 = io_jalr_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_csrrw_T_6 = _io_csrrw_T_4 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_csrrs_T_1 = io_lui_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_csrrs_T_4 = _io_csrrs_T_1 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_csrrs_T_6 = _io_csrrs_T_4 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_csrrc_T_4 = io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_csrrc_T_6 = _io_csrrc_T_4 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lb_T_3 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_lb_T_4 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_lb_T_7 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
- & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lh_T_3 = _io_bne_T_2 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_lh_T_7 = _io_bne_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lw_T_1 = io_jalr_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_lw_T_3 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_lw_T_4 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_lw_T_7 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 &
- io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lbu_T_4 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_lbu_T_7 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
- & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lhu_T_7 = _io_bge_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sb_T_4 = _io_lb_T_3 & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_sb_T_7 = _io_sb_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sh_T_4 = _io_lh_T_3 & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_sh_T_7 = _io_sh_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sw_T_4 = _io_lw_T_3 & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_sw_T_7 = _io_sw_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire io_fence_bit = ~io_inst[31]; // @[Library.scala 326:19]
- wire io_fence_bit_1 = ~io_lui_bit_1; // @[Library.scala 326:19]
- wire _io_fence_T_1 = io_fence_bit & io_fence_bit_1; // @[Library.scala 327:48]
- wire io_fence_bit_2 = ~io_lui_bit_2; // @[Library.scala 326:19]
- wire _io_fence_T_2 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2; // @[Library.scala 327:48]
- wire io_fence_bit_3 = ~io_lui_bit_3; // @[Library.scala 326:19]
- wire _io_fence_T_3 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3; // @[Library.scala 327:48]
- wire io_fence_bit_12 = ~io_lui_bit_12; // @[Library.scala 326:19]
- wire io_fence_bit_13 = ~io_lui_bit_13; // @[Library.scala 326:19]
- wire io_fence_bit_14 = ~io_lui_bit_14; // @[Library.scala 326:19]
- wire io_fence_bit_15 = ~io_lui_bit_15; // @[Library.scala 326:19]
- wire io_fence_bit_16 = ~io_lui_bit_16; // @[Library.scala 326:19]
- wire io_fence_bit_20 = ~io_lui_bit_20; // @[Library.scala 326:19]
- wire io_fence_bit_21 = ~io_lui_bit_21; // @[Library.scala 326:19]
- wire io_fence_bit_22 = ~io_lui_bit_22; // @[Library.scala 326:19]
- wire io_fence_bit_23 = ~io_lui_bit_23; // @[Library.scala 326:19]
- wire io_fence_bit_24 = ~io_inst[7]; // @[Library.scala 326:19]
- wire _io_fence_T_19 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_fence_bit_12 &
- io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 &
- io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24 &
- io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27; // @[Library.scala 327:48]
- wire _io_addi_T_5 = _io_lb_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_addi_T_7 = _io_addi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_slti_T_5 = _io_lw_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_slti_T_7 = _io_slti_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sltiu_T_2 = io_jalr_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_sltiu_T_4 = _io_sltiu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_sltiu_T_5 = _io_sltiu_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sltiu_T_7 = _io_sltiu_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_xori_T_5 = _io_lbu_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_xori_T_7 = _io_xori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_ori_T_4 = _io_bltu_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_ori_T_5 = _io_ori_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_ori_T_7 = _io_ori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_andi_T_4 = _io_bgeu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_andi_T_5 = _io_andi_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_andi_T_7 = _io_andi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire io_slli_bit_4 = ~io_lui_bit_4; // @[Library.scala 326:19]
- wire _io_slli_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 327:48]
- wire io_slli_bit_5 = ~io_lui_bit_5; // @[Library.scala 326:19]
- wire _io_slli_T_5 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 327:48]
- wire io_slli_bit_6 = ~io_lui_bit_6; // @[Library.scala 326:19]
- wire _io_slli_T_6 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6; // @[Library.scala 327:48]
- wire _io_slli_T_7 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_slli_T_8 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_slli_T_9 = _io_slli_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_slli_T_10 = _io_slli_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_slli_T_11 = _io_slli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_slli_T_12 = _io_slli_T_11 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_slli_T_14 = _io_slli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_srli_T_7 = _io_slli_T_6 & io_lui_bit_17; // @[Library.scala 330:48]
- wire _io_srli_T_8 = _io_srli_T_7 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_srli_T_9 = _io_srli_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_srli_T_10 = _io_srli_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_srli_T_11 = _io_srli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_srli_T_12 = _io_srli_T_11 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_srli_T_14 = _io_srli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_srai_T_1 = io_fence_bit & io_lui_bit_1; // @[Library.scala 330:48]
- wire _io_srai_T_2 = _io_srai_T_1 & io_fence_bit_2; // @[Library.scala 327:48]
- wire _io_srai_T_6 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 327:48]
- wire _io_srai_T_7 = _io_srai_T_6 & io_lui_bit_17; // @[Library.scala 330:48]
- wire _io_srai_T_8 = _io_srai_T_7 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_srai_T_9 = _io_srai_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_srai_T_10 = _io_srai_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_srai_T_11 = _io_srai_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_srai_T_12 = _io_srai_T_11 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_srai_T_14 = _io_srai_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_add_T_10 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_add_T_12 = _io_add_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_add_T_14 = _io_add_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sub_T_10 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 &
- io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_sub_T_12 = _io_sub_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sub_T_14 = _io_sub_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_slt_T_8 = _io_slli_T_7 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_slt_T_10 = _io_slt_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_slt_T_12 = _io_slt_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_slt_T_14 = _io_slt_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sltu_T_9 = _io_slli_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_sltu_T_10 = _io_sltu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_sltu_T_12 = _io_sltu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sltu_T_14 = _io_sltu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_xor_T_10 = _io_srli_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_xor_T_12 = _io_xor_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_xor_T_14 = _io_xor_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_or_T_8 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_or_T_10 = _io_or_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_or_T_12 = _io_or_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_or_T_14 = _io_or_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_and_T_9 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_and_T_10 = _io_and_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_and_T_12 = _io_and_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_and_T_14 = _io_and_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sll_T_12 = _io_slli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sll_T_14 = _io_sll_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_srl_T_12 = _io_srli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_srl_T_14 = _io_srl_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sra_T_12 = _io_srai_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sra_T_14 = _io_sra_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mul_T_6 = _io_slli_T_5 & io_lui_bit_6; // @[Library.scala 330:48]
- wire _io_mul_T_7 = _io_mul_T_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_mul_T_8 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_mul_T_10 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mul_T_12 = _io_mul_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mul_T_14 = _io_mul_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulh_T_9 = _io_mul_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulh_T_10 = _io_mulh_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulh_T_12 = _io_mulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulh_T_14 = _io_mulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhsu_T_8 = _io_mul_T_7 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_mulhsu_T_10 = _io_mulhsu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhsu_T_12 = _io_mulhsu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhsu_T_14 = _io_mulhsu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhu_T_9 = _io_mul_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulhu_T_10 = _io_mulhu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhu_T_12 = _io_mulhu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhu_T_14 = _io_mulhu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhr_T_2 = _io_fence_T_1 & io_lui_bit_2; // @[Library.scala 330:48]
- wire _io_mulhr_T_4 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 327:48]
- wire _io_mulhr_T_5 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 327:48]
- wire _io_mulhr_T_6 = _io_mulhr_T_5 & io_lui_bit_6; // @[Library.scala 330:48]
- wire _io_mulhr_T_7 = _io_mulhr_T_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_mulhr_T_8 = _io_mulhr_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_mulhr_T_9 = _io_mulhr_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulhr_T_10 = _io_mulhr_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhr_T_12 = _io_mulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhr_T_14 = _io_mulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhsur_T_8 = _io_mulhr_T_7 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_mulhsur_T_10 = _io_mulhsur_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhsur_T_12 = _io_mulhsur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhsur_T_14 = _io_mulhsur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhur_T_9 = _io_mulhr_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulhur_T_10 = _io_mulhur_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhur_T_12 = _io_mulhur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhur_T_14 = _io_mulhur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_dmulh_T_5 = _io_slli_T_4 & io_lui_bit_5; // @[Library.scala 330:48]
- wire _io_dmulh_T_8 = _io_dmulh_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_dmulh_T_9 = _io_dmulh_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_dmulh_T_10 = _io_dmulh_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_dmulh_T_12 = _io_dmulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_dmulh_T_14 = _io_dmulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_dmulhr_T_5 = _io_mulhr_T_4 & io_lui_bit_5; // @[Library.scala 330:48]
- wire _io_dmulhr_T_8 = _io_dmulhr_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_dmulhr_T_9 = _io_dmulhr_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_dmulhr_T_10 = _io_dmulhr_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_dmulhr_T_12 = _io_dmulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_dmulhr_T_14 = _io_dmulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_div_T_7 = _io_slli_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 330:48]
- wire _io_div_T_8 = _io_div_T_7 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_div_T_10 = _io_div_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_div_T_12 = _io_div_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_div_T_14 = _io_div_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_divu_T_9 = _io_div_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_divu_T_10 = _io_divu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_divu_T_12 = _io_divu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_divu_T_14 = _io_divu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_rem_T_8 = _io_slli_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_rem_T_10 = _io_rem_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_rem_T_12 = _io_rem_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_rem_T_14 = _io_rem_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_remu_T_9 = _io_slli_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_remu_T_10 = _io_remu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_remu_T_12 = _io_remu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_remu_T_14 = _io_remu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_clz_T_2 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2; // @[Library.scala 330:48]
- wire io_clz_bit_7 = ~io_lui_bit_7; // @[Library.scala 326:19]
- wire io_clz_bit_8 = ~io_lui_bit_8; // @[Library.scala 326:19]
- wire io_clz_bit_9 = ~io_lui_bit_9; // @[Library.scala 326:19]
- wire _io_clz_T_9 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
- io_clz_bit_8 & io_clz_bit_9; // @[Library.scala 327:48]
- wire io_clz_bit_10 = ~io_lui_bit_10; // @[Library.scala 326:19]
- wire _io_clz_T_10 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
- io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10; // @[Library.scala 327:48]
- wire io_clz_bit_11 = ~io_inst[20]; // @[Library.scala 326:19]
- wire _io_clz_T_13 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
- io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_clz_T_14 = _io_clz_T_13 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_clz_T_16 = _io_clz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_clz_T_17 = _io_clz_T_16 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_clz_T_19 = _io_clz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_ctz_T_11 = _io_clz_T_10 & io_inst[20]; // @[Library.scala 330:48]
- wire _io_ctz_T_13 = _io_ctz_T_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_ctz_T_14 = _io_ctz_T_13 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_ctz_T_16 = _io_ctz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_ctz_T_17 = _io_ctz_T_16 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_ctz_T_19 = _io_ctz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_pcnt_T_10 = _io_clz_T_9 & io_lui_bit_10; // @[Library.scala 330:48]
- wire _io_pcnt_T_13 = _io_pcnt_T_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_pcnt_T_14 = _io_pcnt_T_13 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_pcnt_T_16 = _io_pcnt_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_pcnt_T_17 = _io_pcnt_T_16 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_pcnt_T_19 = _io_pcnt_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_min_T_4 = _io_fence_T_3 & io_lui_bit_4; // @[Library.scala 330:48]
- wire _io_min_T_5 = _io_min_T_4 & io_slli_bit_5; // @[Library.scala 327:48]
- wire _io_min_T_7 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 330:48]
- wire _io_min_T_8 = _io_min_T_7 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_min_T_10 = _io_min_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_min_T_12 = _io_min_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_min_T_14 = _io_min_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_minu_T_9 = _io_min_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_minu_T_10 = _io_minu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_minu_T_12 = _io_minu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_minu_T_14 = _io_minu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_max_T_8 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_max_T_10 = _io_max_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_max_T_12 = _io_max_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_max_T_14 = _io_max_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_maxu_T_9 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_maxu_T_10 = _io_maxu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_maxu_T_12 = _io_maxu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_maxu_T_14 = _io_maxu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _slog_T_4 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2 & io_lui_bit_3 & io_lui_bit_4; // @[Library.scala 330:48]
- wire _slog_T_17 = _slog_T_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 &
- io_clz_bit_10 & io_clz_bit_11 & io_jalr_bit_17 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 &
- io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 327:48]
- wire _slog_T_20 = _slog_T_17 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _slog_T_21 = _slog_T_20 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_getvl_T_3 = _io_fence_T_2 & io_lui_bit_3; // @[Library.scala 330:48]
- wire _io_getvl_T_6 = _io_getvl_T_3 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 584:89]
- wire _io_getvl_T_20 = io_inst[19:15] != 5'h0; // @[Decode.scala 584:132]
- wire _io_getmaxvl_T_16 = _io_getvl_T_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11
- & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 &
- io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_getmaxvl_T_19 = _io_getmaxvl_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_getmaxvl_T_20 = _io_getmaxvl_T_19 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_getmaxvl_T_23 = _io_getmaxvl_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _io_vld_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_vst_T_4 = _io_mulhr_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_vst_T_9 = _io_vst_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _io_vst_T_14 = _io_clz_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_vst_T_19 = _io_vst_T_14 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _vconv_T_3 = _io_srai_T_2 & io_lui_bit_3; // @[Library.scala 330:48]
- wire _vconv_T_17 = _vconv_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 &
- io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15
- & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire vconv = _vconv_T_17 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _vdup_T_11 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_6 & io_fence_bit_12 &
- io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 597:72]
- wire vdupi = vdup & io_slli_bit_5; // @[Decode.scala 598:20]
- wire _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 602:22]
- wire _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 601:28]
- wire _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 602:30]
- wire _io_ebreak_T_10 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 &
- io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10; // @[Library.scala 327:48]
- wire _io_ebreak_T_11 = _io_ebreak_T_10 & io_inst[20]; // @[Library.scala 330:48]
- wire _io_ebreak_T_24 = _io_ebreak_T_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 &
- io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 &
- io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 327:48]
- wire _io_ebreak_T_27 = _io_ebreak_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_ebreak_T_29 = _io_ebreak_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_ecall_T_18 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 &
- io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_ecall_T_24 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 &
- io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 &
- io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 327:48]
- wire _io_ecall_T_27 = _io_ecall_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_ecall_T_29 = _io_ecall_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_eexit_T_24 = _io_mul_T_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 &
- io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 &
- io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 &
- io_fence_bit_24; // @[Library.scala 327:48]
- wire _io_eexit_T_27 = _io_eexit_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_eexit_T_29 = _io_eexit_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_eyield_T_24 = _io_dmulh_T_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 &
- io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 &
- io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 &
- io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 327:48]
- wire _io_eyield_T_27 = _io_eyield_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_eyield_T_29 = _io_eyield_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_ectxsw_T_6 = _io_slli_T_4 & io_lui_bit_5 & io_lui_bit_6; // @[Library.scala 330:48]
- wire _io_ectxsw_T_24 = _io_ectxsw_T_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 &
- io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 &
- io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 &
- io_fence_bit_24; // @[Library.scala 327:48]
- wire _io_ectxsw_T_27 = _io_ectxsw_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_ectxsw_T_29 = _io_ectxsw_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mpause_T_24 = _io_min_T_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 &
- io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 &
- io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 &
- io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 327:48]
- wire _io_mpause_T_27 = _io_mpause_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mpause_T_29 = _io_mpause_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mret_T_3 = _io_fence_T_1 & io_lui_bit_2 & io_lui_bit_3; // @[Library.scala 330:48]
- wire _io_mret_T_9 = _io_mret_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 &
- io_clz_bit_9; // @[Library.scala 327:48]
- wire _io_mret_T_10 = _io_mret_T_9 & io_lui_bit_10; // @[Library.scala 330:48]
- wire _io_mret_T_24 = _io_mret_T_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 &
- io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 &
- io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 327:48]
- wire _io_mret_T_27 = _io_mret_T_24 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mret_T_29 = _io_mret_T_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_fencei_T_19 = _io_ecall_T_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_fencei_T_27 = _io_fencei_T_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 & io_fence_bit_23 &
- io_fence_bit_24 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27; // @[Library.scala 327:48]
- wire _io_flushat_T_16 = _io_mulhr_T_2 & io_fence_bit_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10
- & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 &
- io_fence_bit_22 & io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 327:48]
- wire _io_flushat_T_19 = _io_flushat_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_flushat_T_20 = _io_flushat_T_19 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_flushat_T_23 = _io_flushat_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _io_flushall_T_21 = _io_mulhr_T_2 & io_fence_bit_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10
- & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 &
- io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_fence_bit_20 & io_fence_bit_21 & io_fence_bit_22 &
- io_fence_bit_23 & io_fence_bit_24; // @[Library.scala 327:48]
- wire _io_flushall_T_24 = _io_flushall_T_21 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_flushall_T_25 = _io_flushall_T_24 & io_lui_bit_28; // @[Library.scala 327:48]
- wire [9:0] decoded_lo_lo_hi = {io_minu,io_max,io_maxu,io_viop,io_vld,io_vst,io_getvl,io_getmaxvl,io_ebreak,io_ecall}; // @[Cat.scala 31:58]
- wire [18:0] decoded_lo_lo = {decoded_lo_lo_hi,io_eexit,io_eyield,io_ectxsw,io_mpause,io_mret,io_fencei,io_flushat,
- io_flushall,io_slog}; // @[Cat.scala 31:58]
- wire [9:0] decoded_lo_hi_hi = {io_srl,io_sra,io_mul,io_mulh,io_mulhsu,io_mulhu,io_mulhr,io_mulhsur,io_mulhur,io_dmulh}
- ; // @[Cat.scala 31:58]
- wire [18:0] decoded_lo_hi = {decoded_lo_hi_hi,io_dmulhr,io_div,io_divu,io_rem,io_remu,io_clz,io_ctz,io_pcnt,io_min}; // @[Cat.scala 31:58]
- wire [9:0] decoded_hi_lo_hi = {io_sw,io_fence,io_addi,io_slti,io_sltiu,io_xori,io_ori,io_andi,io_add,io_sub}; // @[Cat.scala 31:58]
- wire [18:0] decoded_hi_lo = {decoded_hi_lo_hi,io_slt,io_sltu,io_xor,io_or,io_and,io_slli,io_srli,io_srai,io_sll}; // @[Cat.scala 31:58]
- wire [9:0] decoded_hi_hi_lo = {io_csrrw,io_csrrs,io_csrrc,io_lb,io_lh,io_lw,io_lbu,io_lhu,io_sb,io_sh}; // @[Cat.scala 31:58]
- wire [9:0] decoded_hi_hi_hi = {io_lui,io_auipc,io_jal,io_jalr,io_beq,io_bne,io_blt,io_bge,io_bltu,io_bgeu}; // @[Cat.scala 31:58]
- wire [76:0] decoded = {decoded_hi_hi_hi,decoded_hi_hi_lo,decoded_hi_lo,decoded_lo_hi,decoded_lo_lo}; // @[Cat.scala 31:58]
- wire io_undef_value__38 = decoded[76]; // @[Library.scala 196:26]
- wire io_undef_value__0 = decoded[0] | decoded[1]; // @[Library.scala 208:39]
- wire io_undef_value__1 = decoded[2] | decoded[3]; // @[Library.scala 208:39]
- wire io_undef_value__2 = decoded[4] | decoded[5]; // @[Library.scala 208:39]
- wire io_undef_value__3 = decoded[6] | decoded[7]; // @[Library.scala 208:39]
- wire io_undef_value__4 = decoded[8] | decoded[9]; // @[Library.scala 208:39]
- wire io_undef_value__5 = decoded[10] | decoded[11]; // @[Library.scala 208:39]
- wire io_undef_value__6 = decoded[12] | decoded[13]; // @[Library.scala 208:39]
- wire io_undef_value__7 = decoded[14] | decoded[15]; // @[Library.scala 208:39]
- wire io_undef_value__8 = decoded[16] | decoded[17]; // @[Library.scala 208:39]
- wire io_undef_value__9 = decoded[18] | decoded[19]; // @[Library.scala 208:39]
- wire io_undef_value__10 = decoded[20] | decoded[21]; // @[Library.scala 208:39]
- wire io_undef_value__11 = decoded[22] | decoded[23]; // @[Library.scala 208:39]
- wire io_undef_value__12 = decoded[24] | decoded[25]; // @[Library.scala 208:39]
- wire io_undef_value__13 = decoded[26] | decoded[27]; // @[Library.scala 208:39]
- wire io_undef_value__14 = decoded[28] | decoded[29]; // @[Library.scala 208:39]
- wire io_undef_value__15 = decoded[30] | decoded[31]; // @[Library.scala 208:39]
- wire io_undef_value__16 = decoded[32] | decoded[33]; // @[Library.scala 208:39]
- wire io_undef_value__17 = decoded[34] | decoded[35]; // @[Library.scala 208:39]
- wire io_undef_value__18 = decoded[36] | decoded[37]; // @[Library.scala 208:39]
- wire io_undef_value__19 = decoded[38] | decoded[39]; // @[Library.scala 208:39]
- wire io_undef_value__20 = decoded[40] | decoded[41]; // @[Library.scala 208:39]
- wire io_undef_value__21 = decoded[42] | decoded[43]; // @[Library.scala 208:39]
- wire io_undef_value__22 = decoded[44] | decoded[45]; // @[Library.scala 208:39]
- wire io_undef_value__23 = decoded[46] | decoded[47]; // @[Library.scala 208:39]
- wire io_undef_value__24 = decoded[48] | decoded[49]; // @[Library.scala 208:39]
- wire io_undef_value__25 = decoded[50] | decoded[51]; // @[Library.scala 208:39]
- wire io_undef_value__26 = decoded[52] | decoded[53]; // @[Library.scala 208:39]
- wire io_undef_value__27 = decoded[54] | decoded[55]; // @[Library.scala 208:39]
- wire io_undef_value__28 = decoded[56] | decoded[57]; // @[Library.scala 208:39]
- wire io_undef_value__29 = decoded[58] | decoded[59]; // @[Library.scala 208:39]
- wire io_undef_value__30 = decoded[60] | decoded[61]; // @[Library.scala 208:39]
- wire io_undef_value__31 = decoded[62] | decoded[63]; // @[Library.scala 208:39]
- wire io_undef_value__32 = decoded[64] | decoded[65]; // @[Library.scala 208:39]
- wire io_undef_value__33 = decoded[66] | decoded[67]; // @[Library.scala 208:39]
- wire io_undef_value__34 = decoded[68] | decoded[69]; // @[Library.scala 208:39]
- wire io_undef_value__35 = decoded[70] | decoded[71]; // @[Library.scala 208:39]
- wire io_undef_value__36 = decoded[72] | decoded[73]; // @[Library.scala 208:39]
- wire io_undef_value__37 = decoded[74] | decoded[75]; // @[Library.scala 208:39]
- wire io_undef_value_1_0 = io_undef_value__0 | io_undef_value__1; // @[Library.scala 208:39]
- wire io_undef_value_1_1 = io_undef_value__2 | io_undef_value__3; // @[Library.scala 208:39]
- wire io_undef_value_1_2 = io_undef_value__4 | io_undef_value__5; // @[Library.scala 208:39]
- wire io_undef_value_1_3 = io_undef_value__6 | io_undef_value__7; // @[Library.scala 208:39]
- wire io_undef_value_1_4 = io_undef_value__8 | io_undef_value__9; // @[Library.scala 208:39]
- wire io_undef_value_1_5 = io_undef_value__10 | io_undef_value__11; // @[Library.scala 208:39]
- wire io_undef_value_1_6 = io_undef_value__12 | io_undef_value__13; // @[Library.scala 208:39]
- wire io_undef_value_1_7 = io_undef_value__14 | io_undef_value__15; // @[Library.scala 208:39]
- wire io_undef_value_1_8 = io_undef_value__16 | io_undef_value__17; // @[Library.scala 208:39]
- wire io_undef_value_1_9 = io_undef_value__18 | io_undef_value__19; // @[Library.scala 208:39]
- wire io_undef_value_1_10 = io_undef_value__20 | io_undef_value__21; // @[Library.scala 208:39]
- wire io_undef_value_1_11 = io_undef_value__22 | io_undef_value__23; // @[Library.scala 208:39]
- wire io_undef_value_1_12 = io_undef_value__24 | io_undef_value__25; // @[Library.scala 208:39]
- wire io_undef_value_1_13 = io_undef_value__26 | io_undef_value__27; // @[Library.scala 208:39]
- wire io_undef_value_1_14 = io_undef_value__28 | io_undef_value__29; // @[Library.scala 208:39]
- wire io_undef_value_1_15 = io_undef_value__30 | io_undef_value__31; // @[Library.scala 208:39]
- wire io_undef_value_1_16 = io_undef_value__32 | io_undef_value__33; // @[Library.scala 208:39]
- wire io_undef_value_1_17 = io_undef_value__34 | io_undef_value__35; // @[Library.scala 208:39]
- wire io_undef_value_1_18 = io_undef_value__36 | io_undef_value__37; // @[Library.scala 208:39]
- wire io_undef_value_2_0 = io_undef_value_1_0 | io_undef_value_1_1; // @[Library.scala 208:39]
- wire io_undef_value_2_1 = io_undef_value_1_2 | io_undef_value_1_3; // @[Library.scala 208:39]
- wire io_undef_value_2_2 = io_undef_value_1_4 | io_undef_value_1_5; // @[Library.scala 208:39]
- wire io_undef_value_2_3 = io_undef_value_1_6 | io_undef_value_1_7; // @[Library.scala 208:39]
- wire io_undef_value_2_4 = io_undef_value_1_8 | io_undef_value_1_9; // @[Library.scala 208:39]
- wire io_undef_value_2_5 = io_undef_value_1_10 | io_undef_value_1_11; // @[Library.scala 208:39]
- wire io_undef_value_2_6 = io_undef_value_1_12 | io_undef_value_1_13; // @[Library.scala 208:39]
- wire io_undef_value_2_7 = io_undef_value_1_14 | io_undef_value_1_15; // @[Library.scala 208:39]
- wire io_undef_value_2_8 = io_undef_value_1_16 | io_undef_value_1_17; // @[Library.scala 208:39]
- wire io_undef_value_2_9 = io_undef_value_1_18 | io_undef_value__38; // @[Library.scala 208:39]
- wire io_undef_value_3_0 = io_undef_value_2_0 | io_undef_value_2_1; // @[Library.scala 208:39]
- wire io_undef_value_3_1 = io_undef_value_2_2 | io_undef_value_2_3; // @[Library.scala 208:39]
- wire io_undef_value_3_2 = io_undef_value_2_4 | io_undef_value_2_5; // @[Library.scala 208:39]
- wire io_undef_value_3_3 = io_undef_value_2_6 | io_undef_value_2_7; // @[Library.scala 208:39]
- wire io_undef_value_3_4 = io_undef_value_2_8 | io_undef_value_2_9; // @[Library.scala 208:39]
- wire io_undef_value_4_0 = io_undef_value_3_0 | io_undef_value_3_1; // @[Library.scala 208:39]
- wire io_undef_value_4_1 = io_undef_value_3_2 | io_undef_value_3_3; // @[Library.scala 208:39]
- wire io_undef_value_5_0 = io_undef_value_4_0 | io_undef_value_4_1; // @[Library.scala 208:39]
- wire io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_3_4; // @[Library.scala 208:39]
- reg onehot_failed; // @[Decode.scala 670:30]
- wire _T_2 = ~reset; // @[Decode.scala 671:9]
- wire [1:0] _onehot_decode_T_77 = decoded[0] + decoded[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_79 = decoded[2] + decoded[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_81 = _onehot_decode_T_77 + _onehot_decode_T_79; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_83 = decoded[4] + decoded[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_85 = decoded[7] + decoded[8]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_1 = {{1'd0}, decoded[6]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_87 = _GEN_1 + _onehot_decode_T_85; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_89 = _onehot_decode_T_83 + _onehot_decode_T_87[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_91 = _onehot_decode_T_81 + _onehot_decode_T_89; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_93 = decoded[9] + decoded[10]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_95 = decoded[12] + decoded[13]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_2 = {{1'd0}, decoded[11]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_97 = _GEN_2 + _onehot_decode_T_95; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_99 = _onehot_decode_T_93 + _onehot_decode_T_97[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_101 = decoded[14] + decoded[15]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_103 = decoded[17] + decoded[18]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_3 = {{1'd0}, decoded[16]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_105 = _GEN_3 + _onehot_decode_T_103; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_107 = _onehot_decode_T_101 + _onehot_decode_T_105[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_109 = _onehot_decode_T_99 + _onehot_decode_T_107; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_111 = _onehot_decode_T_91 + _onehot_decode_T_109; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_113 = decoded[19] + decoded[20]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_115 = decoded[21] + decoded[22]; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_117 = _onehot_decode_T_113 + _onehot_decode_T_115; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_119 = decoded[23] + decoded[24]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_121 = decoded[26] + decoded[27]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_4 = {{1'd0}, decoded[25]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_123 = _GEN_4 + _onehot_decode_T_121; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_125 = _onehot_decode_T_119 + _onehot_decode_T_123[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_127 = _onehot_decode_T_117 + _onehot_decode_T_125; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_129 = decoded[28] + decoded[29]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_131 = decoded[31] + decoded[32]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_5 = {{1'd0}, decoded[30]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_133 = _GEN_5 + _onehot_decode_T_131; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_135 = _onehot_decode_T_129 + _onehot_decode_T_133[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_137 = decoded[33] + decoded[34]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_139 = decoded[36] + decoded[37]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_6 = {{1'd0}, decoded[35]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_141 = _GEN_6 + _onehot_decode_T_139; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_143 = _onehot_decode_T_137 + _onehot_decode_T_141[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_145 = _onehot_decode_T_135 + _onehot_decode_T_143; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_147 = _onehot_decode_T_127 + _onehot_decode_T_145; // @[Bitwise.scala 48:55]
- wire [5:0] _onehot_decode_T_149 = _onehot_decode_T_111 + _onehot_decode_T_147; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_151 = decoded[38] + decoded[39]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_153 = decoded[40] + decoded[41]; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_155 = _onehot_decode_T_151 + _onehot_decode_T_153; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_157 = decoded[42] + decoded[43]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_159 = decoded[45] + decoded[46]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_7 = {{1'd0}, decoded[44]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_161 = _GEN_7 + _onehot_decode_T_159; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_163 = _onehot_decode_T_157 + _onehot_decode_T_161[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_165 = _onehot_decode_T_155 + _onehot_decode_T_163; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_167 = decoded[47] + decoded[48]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_169 = decoded[50] + decoded[51]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_8 = {{1'd0}, decoded[49]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_171 = _GEN_8 + _onehot_decode_T_169; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_173 = _onehot_decode_T_167 + _onehot_decode_T_171[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_175 = decoded[52] + decoded[53]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_177 = decoded[55] + decoded[56]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_9 = {{1'd0}, decoded[54]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_179 = _GEN_9 + _onehot_decode_T_177; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_181 = _onehot_decode_T_175 + _onehot_decode_T_179[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_183 = _onehot_decode_T_173 + _onehot_decode_T_181; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_185 = _onehot_decode_T_165 + _onehot_decode_T_183; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_187 = decoded[57] + decoded[58]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_189 = decoded[60] + decoded[61]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_10 = {{1'd0}, decoded[59]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_191 = _GEN_10 + _onehot_decode_T_189; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_193 = _onehot_decode_T_187 + _onehot_decode_T_191[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_195 = decoded[62] + decoded[63]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_197 = decoded[65] + decoded[66]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_11 = {{1'd0}, decoded[64]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_199 = _GEN_11 + _onehot_decode_T_197; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_201 = _onehot_decode_T_195 + _onehot_decode_T_199[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_203 = _onehot_decode_T_193 + _onehot_decode_T_201; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_205 = decoded[67] + decoded[68]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_207 = decoded[70] + decoded[71]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_12 = {{1'd0}, decoded[69]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_209 = _GEN_12 + _onehot_decode_T_207; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_211 = _onehot_decode_T_205 + _onehot_decode_T_209[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_213 = decoded[72] + decoded[73]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_215 = decoded[75] + io_undef_value__38; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_13 = {{1'd0}, decoded[74]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_217 = _GEN_13 + _onehot_decode_T_215; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_219 = _onehot_decode_T_213 + _onehot_decode_T_217[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_221 = _onehot_decode_T_211 + _onehot_decode_T_219; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_223 = _onehot_decode_T_203 + _onehot_decode_T_221; // @[Bitwise.scala 48:55]
- wire [5:0] _onehot_decode_T_225 = _onehot_decode_T_185 + _onehot_decode_T_223; // @[Bitwise.scala 48:55]
- wire [6:0] onehot_decode = _onehot_decode_T_149 + _onehot_decode_T_225; // @[Bitwise.scala 48:55]
- wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 674:24]
- wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 674:24]
- wire _T_6 = _T_5 != 7'h1; // @[Decode.scala 674:36]
- assign io_imm12 = {_io_imm12_T_2,io_inst[31:20]}; // @[Cat.scala 31:58]
- assign io_imm20 = {io_inst[31:12],12'h0}; // @[Cat.scala 31:58]
- assign io_immjal = {io_immjal_hi,io_immjal_lo}; // @[Cat.scala 31:58]
- assign io_immbr = {io_immbr_hi,io_immbr_lo}; // @[Cat.scala 31:58]
- assign io_immcsr = {{27'd0}, io_inst[19:15]}; // @[Decode.scala 510:13]
- assign io_immst = {io_immst_hi,io_inst[11:7]}; // @[Cat.scala 31:58]
- assign io_lui = _io_lui_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_auipc = _io_auipc_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_jal = _io_jal_T_2 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_jalr = _io_jalr_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_beq = _io_beq_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bne = _io_bne_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_blt = _io_blt_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_csrrw = _io_csrrw_T_6 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_csrrs = _io_csrrs_T_6 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_csrrc = _io_csrrc_T_6 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lbu = _io_lbu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lhu = _io_lhu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_fence = _io_fence_T_19 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_xori = _io_xori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_ori = _io_ori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_andi = _io_andi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_slli = _io_slli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_srli = _io_srli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_srai = _io_srai_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_add = _io_add_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sub = _io_sub_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_slt = _io_slt_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sltu = _io_sltu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_xor = _io_xor_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_or = _io_or_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_and = _io_and_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sll = _io_sll_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_srl = _io_srl_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sra = _io_sra_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mul = _io_mul_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulh = _io_mulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhsu = _io_mulhsu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhu = _io_mulhu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhr = _io_mulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhsur = _io_mulhsur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_div = _io_div_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_divu = _io_divu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_rem = _io_rem_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_remu = _io_remu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_min = _io_min_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 584:97]
- assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 585:76]
- assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 590:71]
- assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 603:20]
- assign io_ebreak = _io_ebreak_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_ecall = _io_ecall_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_eexit = _io_eexit_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_eyield = _io_eyield_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_ectxsw = _io_ectxsw_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mpause = _io_mpause_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mret = _io_mret_T_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 667:15]
- assign io_fencei = _io_fencei_T_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_flushat = _io_flushat_T_23 & _io_getvl_T_20; // @[Decode.scala 616:76]
- assign io_flushall = _io_flushall_T_25 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_slog = _slog_T_21 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- always @(posedge clock) begin
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~onehot_failed)) begin
- $fatal; // @[Decode.scala 671:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~onehot_failed)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Decode.scala:671 assert(!onehot_failed)\n"); // @[Decode.scala 671:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_6 & _T_2) begin
- $fwrite(32'h80000002,"[FAIL] decode inst=%x addr=%x decoded=0b%b pipeline=%d\n",io_inst,io_addr,decoded,1'h0
- ); // @[Decode.scala 676:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Decode.scala 674:45]
- onehot_failed <= 1'h0; // @[Decode.scala 675:19]
- end else begin
- onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 670:30]
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- onehot_failed = _RAND_0[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- onehot_failed = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Decode(
- input clock,
- input reset,
- input io_halted,
- input io_inst_valid,
- output io_inst_ready,
- input [31:0] io_inst_addr,
- input [31:0] io_inst_inst,
- input io_inst_brchFwd,
- input [31:0] io_scoreboard_regd,
- input [31:0] io_scoreboard_comb,
- output [31:0] io_scoreboard_spec,
- input io_mactive,
- output io_rs1Read_valid,
- output [4:0] io_rs1Read_addr,
- output io_rs1Set_valid,
- output [31:0] io_rs1Set_value,
- output io_rs2Read_valid,
- output [4:0] io_rs2Read_addr,
- output io_rs2Set_valid,
- output [31:0] io_rs2Set_value,
- output io_rdMark_valid,
- output [4:0] io_rdMark_addr,
- output io_busRead_bypass,
- output io_busRead_immen,
- output [31:0] io_busRead_immed,
- output io_alu_valid,
- output [4:0] io_alu_addr,
- output [17:0] io_alu_op,
- output io_bru_valid,
- output io_bru_fwd,
- output [16:0] io_bru_op,
- output [31:0] io_bru_pc,
- output [31:0] io_bru_target,
- output [4:0] io_bru_link,
- output io_csr_valid,
- output [4:0] io_csr_addr,
- output [11:0] io_csr_index,
- output [2:0] io_csr_op,
- output io_lsu_valid,
- input io_lsu_ready,
- output [4:0] io_lsu_addr,
- output [11:0] io_lsu_op,
- output io_mlu_valid,
- output [4:0] io_mlu_addr,
- output [8:0] io_mlu_op,
- output io_dvu_valid,
- input io_dvu_ready,
- output [4:0] io_dvu_addr,
- output [3:0] io_dvu_op,
- output io_vinst_valid,
- input io_vinst_ready,
- output [4:0] io_vinst_addr,
- output [31:0] io_vinst_inst,
- output [4:0] io_vinst_op,
- input io_branchTaken,
- input io_interlock,
- output io_serializeOut_mul,
- output io_serializeOut_jump,
- output io_serializeOut_brcond,
- output io_slog
-);
- wire d_clock; // @[Decode.scala 107:17]
- wire d_reset; // @[Decode.scala 107:17]
- wire [31:0] d_io_addr; // @[Decode.scala 107:17]
- wire [31:0] d_io_inst; // @[Decode.scala 107:17]
- wire [31:0] d_io_imm12; // @[Decode.scala 107:17]
- wire [31:0] d_io_imm20; // @[Decode.scala 107:17]
- wire [31:0] d_io_immjal; // @[Decode.scala 107:17]
- wire [31:0] d_io_immbr; // @[Decode.scala 107:17]
- wire [31:0] d_io_immcsr; // @[Decode.scala 107:17]
- wire [31:0] d_io_immst; // @[Decode.scala 107:17]
- wire d_io_lui; // @[Decode.scala 107:17]
- wire d_io_auipc; // @[Decode.scala 107:17]
- wire d_io_jal; // @[Decode.scala 107:17]
- wire d_io_jalr; // @[Decode.scala 107:17]
- wire d_io_beq; // @[Decode.scala 107:17]
- wire d_io_bne; // @[Decode.scala 107:17]
- wire d_io_blt; // @[Decode.scala 107:17]
- wire d_io_bge; // @[Decode.scala 107:17]
- wire d_io_bltu; // @[Decode.scala 107:17]
- wire d_io_bgeu; // @[Decode.scala 107:17]
- wire d_io_csrrw; // @[Decode.scala 107:17]
- wire d_io_csrrs; // @[Decode.scala 107:17]
- wire d_io_csrrc; // @[Decode.scala 107:17]
- wire d_io_lb; // @[Decode.scala 107:17]
- wire d_io_lh; // @[Decode.scala 107:17]
- wire d_io_lw; // @[Decode.scala 107:17]
- wire d_io_lbu; // @[Decode.scala 107:17]
- wire d_io_lhu; // @[Decode.scala 107:17]
- wire d_io_sb; // @[Decode.scala 107:17]
- wire d_io_sh; // @[Decode.scala 107:17]
- wire d_io_sw; // @[Decode.scala 107:17]
- wire d_io_fence; // @[Decode.scala 107:17]
- wire d_io_addi; // @[Decode.scala 107:17]
- wire d_io_slti; // @[Decode.scala 107:17]
- wire d_io_sltiu; // @[Decode.scala 107:17]
- wire d_io_xori; // @[Decode.scala 107:17]
- wire d_io_ori; // @[Decode.scala 107:17]
- wire d_io_andi; // @[Decode.scala 107:17]
- wire d_io_slli; // @[Decode.scala 107:17]
- wire d_io_srli; // @[Decode.scala 107:17]
- wire d_io_srai; // @[Decode.scala 107:17]
- wire d_io_add; // @[Decode.scala 107:17]
- wire d_io_sub; // @[Decode.scala 107:17]
- wire d_io_slt; // @[Decode.scala 107:17]
- wire d_io_sltu; // @[Decode.scala 107:17]
- wire d_io_xor; // @[Decode.scala 107:17]
- wire d_io_or; // @[Decode.scala 107:17]
- wire d_io_and; // @[Decode.scala 107:17]
- wire d_io_sll; // @[Decode.scala 107:17]
- wire d_io_srl; // @[Decode.scala 107:17]
- wire d_io_sra; // @[Decode.scala 107:17]
- wire d_io_mul; // @[Decode.scala 107:17]
- wire d_io_mulh; // @[Decode.scala 107:17]
- wire d_io_mulhsu; // @[Decode.scala 107:17]
- wire d_io_mulhu; // @[Decode.scala 107:17]
- wire d_io_mulhr; // @[Decode.scala 107:17]
- wire d_io_mulhsur; // @[Decode.scala 107:17]
- wire d_io_mulhur; // @[Decode.scala 107:17]
- wire d_io_dmulh; // @[Decode.scala 107:17]
- wire d_io_dmulhr; // @[Decode.scala 107:17]
- wire d_io_div; // @[Decode.scala 107:17]
- wire d_io_divu; // @[Decode.scala 107:17]
- wire d_io_rem; // @[Decode.scala 107:17]
- wire d_io_remu; // @[Decode.scala 107:17]
- wire d_io_clz; // @[Decode.scala 107:17]
- wire d_io_ctz; // @[Decode.scala 107:17]
- wire d_io_pcnt; // @[Decode.scala 107:17]
- wire d_io_min; // @[Decode.scala 107:17]
- wire d_io_minu; // @[Decode.scala 107:17]
- wire d_io_max; // @[Decode.scala 107:17]
- wire d_io_maxu; // @[Decode.scala 107:17]
- wire d_io_getvl; // @[Decode.scala 107:17]
- wire d_io_getmaxvl; // @[Decode.scala 107:17]
- wire d_io_vld; // @[Decode.scala 107:17]
- wire d_io_vst; // @[Decode.scala 107:17]
- wire d_io_viop; // @[Decode.scala 107:17]
- wire d_io_ebreak; // @[Decode.scala 107:17]
- wire d_io_ecall; // @[Decode.scala 107:17]
- wire d_io_eexit; // @[Decode.scala 107:17]
- wire d_io_eyield; // @[Decode.scala 107:17]
- wire d_io_ectxsw; // @[Decode.scala 107:17]
- wire d_io_mpause; // @[Decode.scala 107:17]
- wire d_io_mret; // @[Decode.scala 107:17]
- wire d_io_undef; // @[Decode.scala 107:17]
- wire d_io_fencei; // @[Decode.scala 107:17]
- wire d_io_flushat; // @[Decode.scala 107:17]
- wire d_io_flushall; // @[Decode.scala 107:17]
- wire d_io_slog; // @[Decode.scala 107:17]
- wire decodeEn = io_inst_valid & io_inst_ready & ~io_branchTaken; // @[Decode.scala 104:49]
- wire vldst = d_io_vld | d_io_vst; // @[Decode.scala 111:24]
- wire vldst_wb = vldst & io_inst_inst[28]; // @[Decode.scala 112:24]
- wire [4:0] rdAddr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- wire [4:0] rs2Addr = io_inst_inst[24:20]; // @[Decode.scala 116:29]
- wire [4:0] rs3Addr = io_inst_inst[31:27]; // @[Decode.scala 117:29]
- wire _isAluImm_T_3 = d_io_addi | d_io_slti | d_io_sltiu | d_io_xori | d_io_ori; // @[Decode.scala 119:68]
- wire isAluImm = _isAluImm_T_3 | d_io_andi | d_io_slli | d_io_srli | d_io_srai; // @[Decode.scala 120:66]
- wire _isAluReg_T_4 = d_io_add | d_io_sub | d_io_slt | d_io_sltu | d_io_xor | d_io_or; // @[Decode.scala 122:76]
- wire isAluReg = _isAluReg_T_4 | d_io_and | d_io_sll | d_io_srl | d_io_sra; // @[Decode.scala 123:62]
- wire isAlu1Bit = d_io_clz | d_io_ctz | d_io_pcnt; // @[Decode.scala 125:40]
- wire isAlu2Bit = d_io_min | d_io_minu | d_io_max | d_io_maxu; // @[Decode.scala 126:53]
- wire _isCondBr_T_3 = d_io_beq | d_io_bne | d_io_blt | d_io_bge | d_io_bltu; // @[Decode.scala 128:63]
- wire isCondBr = _isCondBr_T_3 | d_io_bgeu; // @[Decode.scala 129:28]
- wire isCsr = d_io_csrrw | d_io_csrrs | d_io_csrrc; // @[Decode.scala 131:40]
- wire isCsrImm = isCsr & io_inst_inst[14]; // @[Decode.scala 132:24]
- wire isCsrReg = isCsr & ~io_inst_inst[14]; // @[Decode.scala 133:24]
- wire isLoad = d_io_lb | d_io_lh | d_io_lw | d_io_lbu | d_io_lhu; // @[Decode.scala 135:58]
- wire isStore = d_io_sb | d_io_sh | d_io_sw; // @[Decode.scala 136:36]
- wire isLsu = isLoad | isStore | d_io_vld | d_io_vst | d_io_flushat | d_io_flushall; // @[Decode.scala 137:73]
- wire isMul = d_io_mul | d_io_mulh | d_io_mulhsu | d_io_mulhu | d_io_mulhr | d_io_mulhsur | d_io_mulhur | d_io_dmulh
- | d_io_dmulhr; // @[Decode.scala 139:125]
- wire isDvu = d_io_div | d_io_divu | d_io_rem | d_io_remu; // @[Decode.scala 141:49]
- wire isVIop = io_vinst_op[4]; // @[Decode.scala 143:27]
- wire isVIopVs2 = isVIop & io_inst_inst[1:0] == 2'h0; // @[Decode.scala 146:26]
- wire [31:0] _aluRdEn_T = io_scoreboard_comb >> rdAddr; // @[Decode.scala 150:37]
- wire aluRdEn = ~_aluRdEn_T[0] | isVIop | isStore | isCondBr; // @[Decode.scala 150:71]
- wire [31:0] _aluRs1En_T = io_scoreboard_comb >> io_inst_inst[19:15]; // @[Decode.scala 151:37]
- wire aluRs1En = ~_aluRs1En_T[0] | isVIop | isLsu | d_io_auipc; // @[Decode.scala 151:69]
- wire [31:0] _aluRs2En_T = io_scoreboard_comb >> rs2Addr; // @[Decode.scala 152:37]
- wire aluRs2En = ~_aluRs2En_T[0] | isVIopVs2 | isLsu | d_io_auipc | isAluImm | isAlu1Bit; // @[Decode.scala 152:95]
- wire aluEn = aluRdEn & aluRs1En & aluRs2En; // @[Decode.scala 155:35]
- wire [31:0] _bruEn_T_1 = io_scoreboard_regd >> io_inst_inst[19:15]; // @[Decode.scala 158:48]
- wire _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 159:35]
- wire bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 158:58]
- wire _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 165:20]
- wire _lsuEn_T_15 = _aluRs2En_T[0] & (isStore | vldst); // @[Decode.scala 167:49]
- wire _lsuEn_T_16 = _lsuEn_T_11 | _lsuEn_T_15; // @[Decode.scala 166:50]
- wire _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 165:15]
- wire _lsuEn_T_18 = io_lsu_ready & _lsuEn_T_17; // @[Decode.scala 164:50]
- wire lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 162:22]
- wire vinstEn = ~(io_vinst_op != 5'h0 & ~io_vinst_ready); // @[Decode.scala 175:17]
- wire fenceEn = ~(d_io_fence & io_mactive); // @[Decode.scala 179:17]
- wire aluValid_value__0 = io_alu_op[0] | io_alu_op[1]; // @[Library.scala 208:39]
- wire aluValid_value__1 = io_alu_op[2] | io_alu_op[3]; // @[Library.scala 208:39]
- wire aluValid_value__2 = io_alu_op[4] | io_alu_op[5]; // @[Library.scala 208:39]
- wire aluValid_value__3 = io_alu_op[6] | io_alu_op[7]; // @[Library.scala 208:39]
- wire aluValid_value__4 = io_alu_op[8] | io_alu_op[9]; // @[Library.scala 208:39]
- wire aluValid_value__5 = io_alu_op[10] | io_alu_op[11]; // @[Library.scala 208:39]
- wire aluValid_value__6 = io_alu_op[12] | io_alu_op[13]; // @[Library.scala 208:39]
- wire aluValid_value__7 = io_alu_op[14] | io_alu_op[15]; // @[Library.scala 208:39]
- wire aluValid_value__8 = io_alu_op[16] | io_alu_op[17]; // @[Library.scala 208:39]
- wire aluValid_value_1_0 = aluValid_value__0 | aluValid_value__1; // @[Library.scala 208:39]
- wire aluValid_value_1_1 = aluValid_value__2 | aluValid_value__3; // @[Library.scala 208:39]
- wire aluValid_value_1_2 = aluValid_value__4 | aluValid_value__5; // @[Library.scala 208:39]
- wire aluValid_value_1_3 = aluValid_value__6 | aluValid_value__7; // @[Library.scala 208:39]
- wire aluValid_value_2_0 = aluValid_value_1_0 | aluValid_value_1_1; // @[Library.scala 208:39]
- wire aluValid_value_2_1 = aluValid_value_1_2 | aluValid_value_1_3; // @[Library.scala 208:39]
- wire aluValid_value_3_0 = aluValid_value_2_0 | aluValid_value_2_1; // @[Library.scala 208:39]
- wire aluValid_value_4_0 = aluValid_value_3_0 | aluValid_value__8; // @[Library.scala 208:39]
- wire aluOp_1 = d_io_sub; // @[Decode.scala 183:19 190:19]
- wire aluOp_0 = d_io_auipc | d_io_addi | d_io_add; // @[Decode.scala 189:46]
- wire aluOp_3 = d_io_sltiu | d_io_sltu; // @[Decode.scala 192:33]
- wire aluOp_2 = d_io_slti | d_io_slt; // @[Decode.scala 191:32]
- wire aluOp_5 = d_io_ori | d_io_or; // @[Decode.scala 194:31]
- wire aluOp_4 = d_io_xori | d_io_xor; // @[Decode.scala 193:32]
- wire aluOp_8 = d_io_srli | d_io_srl; // @[Decode.scala 197:32]
- wire aluOp_7 = d_io_slli | d_io_sll; // @[Decode.scala 196:32]
- wire aluOp_6 = d_io_andi | d_io_and; // @[Decode.scala 195:32]
- wire [8:0] io_alu_op_lo = {aluOp_8,aluOp_7,aluOp_6,aluOp_5,aluOp_4,aluOp_3,aluOp_2,aluOp_1,aluOp_0}; // @[Decode.scala 187:22]
- wire aluOp_10 = d_io_lui; // @[Decode.scala 183:19 199:19]
- wire aluOp_9 = d_io_srai | d_io_sra; // @[Decode.scala 198:32]
- wire aluOp_12 = d_io_ctz; // @[Decode.scala 183:19 201:19]
- wire aluOp_11 = d_io_clz; // @[Decode.scala 183:19 200:19]
- wire aluOp_14 = d_io_min; // @[Decode.scala 183:19 203:19]
- wire aluOp_13 = d_io_pcnt; // @[Decode.scala 183:19 202:19]
- wire aluOp_17 = d_io_maxu; // @[Decode.scala 183:19 206:19]
- wire aluOp_16 = d_io_max; // @[Decode.scala 183:19 205:19]
- wire aluOp_15 = d_io_minu; // @[Decode.scala 183:19 204:19]
- wire [8:0] io_alu_op_hi = {aluOp_17,aluOp_16,aluOp_15,aluOp_14,aluOp_13,aluOp_12,aluOp_11,aluOp_10,aluOp_9}; // @[Decode.scala 187:22]
- wire bruValid_value__8 = io_bru_op[16]; // @[Library.scala 196:26]
- wire bruValid_value__0 = io_bru_op[0] | io_bru_op[1]; // @[Library.scala 208:39]
- wire bruValid_value__1 = io_bru_op[2] | io_bru_op[3]; // @[Library.scala 208:39]
- wire bruValid_value__2 = io_bru_op[4] | io_bru_op[5]; // @[Library.scala 208:39]
- wire bruValid_value__3 = io_bru_op[6] | io_bru_op[7]; // @[Library.scala 208:39]
- wire bruValid_value__4 = io_bru_op[8] | io_bru_op[9]; // @[Library.scala 208:39]
- wire bruValid_value__5 = io_bru_op[10] | io_bru_op[11]; // @[Library.scala 208:39]
- wire bruValid_value__6 = io_bru_op[12] | io_bru_op[13]; // @[Library.scala 208:39]
- wire bruValid_value__7 = io_bru_op[14] | io_bru_op[15]; // @[Library.scala 208:39]
- wire bruValid_value_1_0 = bruValid_value__0 | bruValid_value__1; // @[Library.scala 208:39]
- wire bruValid_value_1_1 = bruValid_value__2 | bruValid_value__3; // @[Library.scala 208:39]
- wire bruValid_value_1_2 = bruValid_value__4 | bruValid_value__5; // @[Library.scala 208:39]
- wire bruValid_value_1_3 = bruValid_value__6 | bruValid_value__7; // @[Library.scala 208:39]
- wire bruValid_value_2_0 = bruValid_value_1_0 | bruValid_value_1_1; // @[Library.scala 208:39]
- wire bruValid_value_2_1 = bruValid_value_1_2 | bruValid_value_1_3; // @[Library.scala 208:39]
- wire bruValid_value_3_0 = bruValid_value_2_0 | bruValid_value_2_1; // @[Library.scala 208:39]
- wire bruValid_value_4_0 = bruValid_value_3_0 | bruValid_value__8; // @[Library.scala 208:39]
- wire bruOp_1 = d_io_jalr; // @[Decode.scala 210:19 220:19]
- wire bruOp_0 = d_io_jal; // @[Decode.scala 210:19 219:19]
- wire bruOp_3 = d_io_bne; // @[Decode.scala 210:19 222:19]
- wire bruOp_2 = d_io_beq; // @[Decode.scala 210:19 221:19]
- wire bruOp_5 = d_io_bge; // @[Decode.scala 210:19 224:19]
- wire bruOp_4 = d_io_blt; // @[Decode.scala 210:19 223:19]
- wire bruOp_7 = d_io_bgeu; // @[Decode.scala 210:19 226:19]
- wire bruOp_6 = d_io_bltu; // @[Decode.scala 210:19 225:19]
- wire [7:0] io_bru_op_lo = {bruOp_7,bruOp_6,bruOp_5,bruOp_4,bruOp_3,bruOp_2,bruOp_1,bruOp_0}; // @[Decode.scala 214:22]
- wire bruOp_9 = d_io_ecall; // @[Decode.scala 210:19 228:21]
- wire bruOp_8 = d_io_ebreak; // @[Decode.scala 210:19 227:21]
- wire bruOp_11 = d_io_eyield; // @[Decode.scala 210:19 230:21]
- wire bruOp_10 = d_io_eexit; // @[Decode.scala 210:19 229:21]
- wire bruOp_13 = d_io_mpause; // @[Decode.scala 210:19 232:21]
- wire bruOp_12 = d_io_ectxsw; // @[Decode.scala 210:19 231:21]
- wire bruOp_16 = d_io_undef; // @[Decode.scala 210:19 235:21]
- wire bruOp_15 = d_io_fencei; // @[Decode.scala 210:19 234:21]
- wire bruOp_14 = d_io_mret; // @[Decode.scala 210:19 233:21]
- wire [8:0] io_bru_op_hi = {bruOp_16,bruOp_15,bruOp_14,bruOp_13,bruOp_12,bruOp_11,bruOp_10,bruOp_9,bruOp_8}; // @[Decode.scala 214:22]
- wire [31:0] _io_bru_target_T_1 = io_inst_inst[2] ? d_io_immjal : d_io_immbr; // @[Decode.scala 216:38]
- wire csrValid_value__1 = io_csr_op[2]; // @[Library.scala 196:26]
- wire csrValid_value__0 = io_csr_op[0] | io_csr_op[1]; // @[Library.scala 208:39]
- wire csrValid_value_1_0 = csrValid_value__0 | csrValid_value__1; // @[Library.scala 208:39]
- wire csrOp_2 = d_io_csrrc; // @[Decode.scala 239:19 248:20]
- wire csrOp_1 = d_io_csrrs; // @[Decode.scala 239:19 247:20]
- wire [1:0] io_csr_op_hi = {csrOp_2,csrOp_1}; // @[Decode.scala 244:22]
- wire csrOp_0 = d_io_csrrw; // @[Decode.scala 239:19 246:20]
- wire lsuValid_value__0 = io_lsu_op[0] | io_lsu_op[1]; // @[Library.scala 208:39]
- wire lsuValid_value__1 = io_lsu_op[2] | io_lsu_op[3]; // @[Library.scala 208:39]
- wire lsuValid_value__2 = io_lsu_op[4] | io_lsu_op[5]; // @[Library.scala 208:39]
- wire lsuValid_value__3 = io_lsu_op[6] | io_lsu_op[7]; // @[Library.scala 208:39]
- wire lsuValid_value__4 = io_lsu_op[8] | io_lsu_op[9]; // @[Library.scala 208:39]
- wire lsuValid_value__5 = io_lsu_op[10] | io_lsu_op[11]; // @[Library.scala 208:39]
- wire lsuValid_value_1_0 = lsuValid_value__0 | lsuValid_value__1; // @[Library.scala 208:39]
- wire lsuValid_value_1_1 = lsuValid_value__2 | lsuValid_value__3; // @[Library.scala 208:39]
- wire lsuValid_value_1_2 = lsuValid_value__4 | lsuValid_value__5; // @[Library.scala 208:39]
- wire lsuValid_value_2_0 = lsuValid_value_1_0 | lsuValid_value_1_1; // @[Library.scala 208:39]
- wire lsuValid_value_3_0 = lsuValid_value_2_0 | lsuValid_value_1_2; // @[Library.scala 208:39]
- wire lsuOp_2 = d_io_lw; // @[Decode.scala 252:19 261:18]
- wire lsuOp_1 = d_io_lh; // @[Decode.scala 252:19 260:18]
- wire lsuOp_0 = d_io_lb; // @[Decode.scala 252:19 259:18]
- wire lsuOp_5 = d_io_sb; // @[Decode.scala 252:19 264:18]
- wire lsuOp_4 = d_io_lhu; // @[Decode.scala 252:19 263:18]
- wire lsuOp_3 = d_io_lbu; // @[Decode.scala 252:19 262:18]
- wire [5:0] io_lsu_op_lo = {lsuOp_5,lsuOp_4,lsuOp_3,lsuOp_2,lsuOp_1,lsuOp_0}; // @[Decode.scala 257:22]
- wire lsuOp_7 = d_io_sw; // @[Decode.scala 252:19 266:18]
- wire lsuOp_6 = d_io_sh; // @[Decode.scala 252:19 265:18]
- wire lsuOp_10 = d_io_flushall; // @[Decode.scala 252:19 269:23]
- wire lsuOp_9 = d_io_flushat; // @[Decode.scala 252:19 268:23]
- wire [5:0] io_lsu_op_hi = {vldst,lsuOp_10,lsuOp_9,bruOp_15,lsuOp_7,lsuOp_6}; // @[Decode.scala 257:22]
- wire mluValid_value__4 = io_mlu_op[8]; // @[Library.scala 196:26]
- wire mluValid_value__0 = io_mlu_op[0] | io_mlu_op[1]; // @[Library.scala 208:39]
- wire mluValid_value__1 = io_mlu_op[2] | io_mlu_op[3]; // @[Library.scala 208:39]
- wire mluValid_value__2 = io_mlu_op[4] | io_mlu_op[5]; // @[Library.scala 208:39]
- wire mluValid_value__3 = io_mlu_op[6] | io_mlu_op[7]; // @[Library.scala 208:39]
- wire mluValid_value_1_0 = mluValid_value__0 | mluValid_value__1; // @[Library.scala 208:39]
- wire mluValid_value_1_1 = mluValid_value__2 | mluValid_value__3; // @[Library.scala 208:39]
- wire mluValid_value_2_0 = mluValid_value_1_0 | mluValid_value_1_1; // @[Library.scala 208:39]
- wire mluValid_value_3_0 = mluValid_value_2_0 | mluValid_value__4; // @[Library.scala 208:39]
- wire mluOp_1 = d_io_mulh; // @[Decode.scala 275:19 282:22]
- wire mluOp_0 = d_io_mul; // @[Decode.scala 275:19 281:22]
- wire mluOp_3 = d_io_mulhu; // @[Decode.scala 275:19 284:22]
- wire mluOp_2 = d_io_mulhsu; // @[Decode.scala 275:19 283:22]
- wire [3:0] io_mlu_op_lo = {mluOp_3,mluOp_2,mluOp_1,mluOp_0}; // @[Decode.scala 279:22]
- wire mluOp_5 = d_io_mulhsur; // @[Decode.scala 275:19 286:22]
- wire mluOp_4 = d_io_mulhr; // @[Decode.scala 275:19 285:22]
- wire mluOp_8 = d_io_dmulhr; // @[Decode.scala 275:19 289:22]
- wire mluOp_7 = d_io_dmulh; // @[Decode.scala 275:19 288:22]
- wire mluOp_6 = d_io_mulhur; // @[Decode.scala 275:19 287:22]
- wire [4:0] io_mlu_op_hi = {mluOp_8,mluOp_7,mluOp_6,mluOp_5,mluOp_4}; // @[Decode.scala 279:22]
- wire dvuValid_value__0 = io_dvu_op[0] | io_dvu_op[1]; // @[Library.scala 208:39]
- wire dvuValid_value__1 = io_dvu_op[2] | io_dvu_op[3]; // @[Library.scala 208:39]
- wire dvuValid_value_1_0 = dvuValid_value__0 | dvuValid_value__1; // @[Library.scala 208:39]
- wire dvuOp_1 = d_io_divu; // @[Decode.scala 293:19 300:19]
- wire dvuOp_0 = d_io_div; // @[Decode.scala 293:19 299:19]
- wire [1:0] io_dvu_op_lo = {dvuOp_1,dvuOp_0}; // @[Decode.scala 297:22]
- wire dvuOp_3 = d_io_remu; // @[Decode.scala 293:19 302:19]
- wire dvuOp_2 = d_io_rem; // @[Decode.scala 293:19 301:19]
- wire [1:0] io_dvu_op_hi = {dvuOp_3,dvuOp_2}; // @[Decode.scala 297:22]
- wire dvuEn = ~dvuValid_value_1_0 | io_dvu_ready; // @[Decode.scala 304:42]
- wire vinstOp_0 = d_io_getvl; // @[Decode.scala 308:21 319:24]
- wire vinstOp_1 = d_io_getmaxvl; // @[Decode.scala 308:21 320:27]
- wire vinstValid_value__0 = vinstOp_0 | vinstOp_1; // @[Library.scala 208:39]
- wire vinstOp_2 = d_io_vld; // @[Decode.scala 308:21 316:22]
- wire vinstOp_3 = d_io_vst; // @[Decode.scala 308:21 317:22]
- wire vinstValid_value__1 = vinstOp_2 | vinstOp_3; // @[Library.scala 208:39]
- wire vinstValid_value_1_0 = vinstValid_value__0 | vinstValid_value__1; // @[Library.scala 208:39]
- wire vinstOp_4 = d_io_viop; // @[Decode.scala 308:21 318:23]
- wire vinstValid_value_2_0 = vinstValid_value_1_0 | vinstOp_4; // @[Library.scala 208:39]
- wire [1:0] io_vinst_op_lo = {vinstOp_1,vinstOp_0}; // @[Decode.scala 314:26]
- wire [2:0] io_vinst_op_hi = {vinstOp_4,vinstOp_3,vinstOp_2}; // @[Decode.scala 314:26]
- wire _io_rs1Read_valid_T = isCondBr | isAluReg; // @[Decode.scala 326:45]
- wire _io_rs1Read_valid_T_4 = isCondBr | isAluReg | isAluImm | isAlu1Bit | isAlu2Bit | isCsrImm; // @[Decode.scala 326:95]
- wire _io_rs1Read_valid_T_9 = _io_rs1Read_valid_T_4 | isCsrReg | isMul | isDvu | d_io_slog | d_io_getvl; // @[Decode.scala 327:75]
- wire _io_rs1Read_valid_T_11 = _io_rs1Read_valid_T_9 | d_io_vld | d_io_vst; // @[Decode.scala 328:46]
- wire _io_rs2Read_valid_T_3 = _io_rs1Read_valid_T | isAlu2Bit | isStore | isCsrReg; // @[Decode.scala 329:81]
- wire _io_rs2Read_valid_T_8 = _io_rs2Read_valid_T_3 | isMul | isDvu | d_io_slog | d_io_getvl | d_io_vld; // @[Decode.scala 330:77]
- wire _io_rs2Read_valid_T_10 = _io_rs2Read_valid_T_8 | d_io_vst | d_io_viop; // @[Decode.scala 331:44]
- wire _io_rs2Set_value_T = d_io_auipc | d_io_lui; // @[Decode.scala 346:45]
- wire _rdMark_valid_T_4 = lsuValid_value_3_0 & isLoad; // @[Decode.scala 352:16]
- wire _rdMark_valid_T_5 = aluValid_value_4_0 | csrValid_value_1_0 | mluValid_value_3_0 | dvuValid_value_1_0 &
- io_dvu_ready | _rdMark_valid_T_4; // @[Decode.scala 351:68]
- wire _rdMark_valid_T_6 = _rdMark_valid_T_5 | d_io_getvl; // @[Decode.scala 352:26]
- wire _rdMark_valid_T_12 = bruValid_value_4_0 & (bruOp_0 | bruOp_1) & rdAddr != 5'h0; // @[Decode.scala 354:55]
- wire rdMark_valid = _rdMark_valid_T_6 | d_io_getmaxvl | vldst_wb | _rdMark_valid_T_12; // @[Decode.scala 353:47]
- wire [31:0] _scoreboard_spec_T = 32'h1 << rdAddr; // @[OneHot.scala 64:12]
- wire [31:0] scoreboard_spec = rdMark_valid ? _scoreboard_spec_T : 32'h0; // @[Decode.scala 357:28]
- wire _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 369:65]
- wire _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 368:8]
- wire storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 372:47]
- wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 375:30]
- wire _io_inst_ready_T_5 = aluEn & bruEn & lsuEn & dvuEn & vinstEn & fenceEn; // @[Decode.scala 380:73]
- wire _io_serializeOut_jump_T_2 = bruOp_0 | d_io_jalr | d_io_ebreak; // @[Decode.scala 389:72]
- wire _io_serializeOut_jump_T_5 = _io_serializeOut_jump_T_2 | d_io_ecall | d_io_eexit | d_io_eyield; // @[Decode.scala 390:67]
- DecodedInstruction d ( // @[Decode.scala 107:17]
- .clock(d_clock),
- .reset(d_reset),
- .io_addr(d_io_addr),
- .io_inst(d_io_inst),
- .io_imm12(d_io_imm12),
- .io_imm20(d_io_imm20),
- .io_immjal(d_io_immjal),
- .io_immbr(d_io_immbr),
- .io_immcsr(d_io_immcsr),
- .io_immst(d_io_immst),
- .io_lui(d_io_lui),
- .io_auipc(d_io_auipc),
- .io_jal(d_io_jal),
- .io_jalr(d_io_jalr),
- .io_beq(d_io_beq),
- .io_bne(d_io_bne),
- .io_blt(d_io_blt),
- .io_bge(d_io_bge),
- .io_bltu(d_io_bltu),
- .io_bgeu(d_io_bgeu),
- .io_csrrw(d_io_csrrw),
- .io_csrrs(d_io_csrrs),
- .io_csrrc(d_io_csrrc),
- .io_lb(d_io_lb),
- .io_lh(d_io_lh),
- .io_lw(d_io_lw),
- .io_lbu(d_io_lbu),
- .io_lhu(d_io_lhu),
- .io_sb(d_io_sb),
- .io_sh(d_io_sh),
- .io_sw(d_io_sw),
- .io_fence(d_io_fence),
- .io_addi(d_io_addi),
- .io_slti(d_io_slti),
- .io_sltiu(d_io_sltiu),
- .io_xori(d_io_xori),
- .io_ori(d_io_ori),
- .io_andi(d_io_andi),
- .io_slli(d_io_slli),
- .io_srli(d_io_srli),
- .io_srai(d_io_srai),
- .io_add(d_io_add),
- .io_sub(d_io_sub),
- .io_slt(d_io_slt),
- .io_sltu(d_io_sltu),
- .io_xor(d_io_xor),
- .io_or(d_io_or),
- .io_and(d_io_and),
- .io_sll(d_io_sll),
- .io_srl(d_io_srl),
- .io_sra(d_io_sra),
- .io_mul(d_io_mul),
- .io_mulh(d_io_mulh),
- .io_mulhsu(d_io_mulhsu),
- .io_mulhu(d_io_mulhu),
- .io_mulhr(d_io_mulhr),
- .io_mulhsur(d_io_mulhsur),
- .io_mulhur(d_io_mulhur),
- .io_dmulh(d_io_dmulh),
- .io_dmulhr(d_io_dmulhr),
- .io_div(d_io_div),
- .io_divu(d_io_divu),
- .io_rem(d_io_rem),
- .io_remu(d_io_remu),
- .io_clz(d_io_clz),
- .io_ctz(d_io_ctz),
- .io_pcnt(d_io_pcnt),
- .io_min(d_io_min),
- .io_minu(d_io_minu),
- .io_max(d_io_max),
- .io_maxu(d_io_maxu),
- .io_getvl(d_io_getvl),
- .io_getmaxvl(d_io_getmaxvl),
- .io_vld(d_io_vld),
- .io_vst(d_io_vst),
- .io_viop(d_io_viop),
- .io_ebreak(d_io_ebreak),
- .io_ecall(d_io_ecall),
- .io_eexit(d_io_eexit),
- .io_eyield(d_io_eyield),
- .io_ectxsw(d_io_ectxsw),
- .io_mpause(d_io_mpause),
- .io_mret(d_io_mret),
- .io_undef(d_io_undef),
- .io_fencei(d_io_fencei),
- .io_flushat(d_io_flushat),
- .io_flushall(d_io_flushall),
- .io_slog(d_io_slog)
- );
- assign io_inst_ready = _io_inst_ready_T_5 & ~io_halted & ~io_interlock; // @[Decode.scala 381:55]
- assign io_scoreboard_spec = {scoreboard_spec[31:1],1'h0}; // @[Cat.scala 31:58]
- assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_11; // @[Decode.scala 326:32]
- assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 334:25]
- assign io_rs1Set_valid = decodeEn & (d_io_auipc | isCsrImm); // @[Decode.scala 340:31]
- assign io_rs1Set_value = isCsr ? d_io_immcsr : io_inst_addr; // @[Decode.scala 343:25]
- assign io_rs2Read_valid = decodeEn & _io_rs2Read_valid_T_10; // @[Decode.scala 329:32]
- assign io_rs2Read_addr = io_inst_inst[24:20]; // @[Decode.scala 116:29]
- assign io_rs2Set_valid = io_rs1Set_valid | decodeEn & (isAluImm | isAlu1Bit | d_io_lui); // @[Decode.scala 341:38]
- assign io_rs2Set_value = _io_rs2Set_value_T ? d_io_imm20 : d_io_imm12; // @[Mux.scala 101:16]
- assign io_rdMark_valid = decodeEn & rdMark_valid; // @[Decode.scala 360:31]
- assign io_rdMark_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_busRead_bypass = io_inst_inst[31:25] == 7'h0 & _io_busRead_bypass_T_10; // @[Decode.scala 367:52]
- assign io_busRead_immen = ~d_io_flushat; // @[Decode.scala 373:23]
- assign io_busRead_immed = {d_io_imm12[31:5],_io_busRead_immed_T_3}; // @[Cat.scala 31:58]
- assign io_alu_valid = decodeEn & aluValid_value_4_0; // @[Decode.scala 185:28]
- assign io_alu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_alu_op = {io_alu_op_hi,io_alu_op_lo}; // @[Decode.scala 187:22]
- assign io_bru_valid = decodeEn & bruValid_value_4_0; // @[Decode.scala 212:28]
- assign io_bru_fwd = io_inst_brchFwd; // @[Decode.scala 213:14]
- assign io_bru_op = {io_bru_op_hi,io_bru_op_lo}; // @[Decode.scala 214:22]
- assign io_bru_pc = io_inst_addr; // @[Decode.scala 215:13]
- assign io_bru_target = io_inst_addr + _io_bru_target_T_1; // @[Decode.scala 216:33]
- assign io_bru_link = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_csr_valid = decodeEn & csrValid_value_1_0; // @[Decode.scala 241:28]
- assign io_csr_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_csr_index = io_inst_inst[31:20]; // @[Decode.scala 243:31]
- assign io_csr_op = {io_csr_op_hi,csrOp_0}; // @[Decode.scala 244:22]
- assign io_lsu_valid = decodeEn & lsuValid_value_3_0; // @[Decode.scala 254:28]
- assign io_lsu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_lsu_op = {io_lsu_op_hi,io_lsu_op_lo}; // @[Decode.scala 257:22]
- assign io_mlu_valid = decodeEn & mluValid_value_3_0; // @[Decode.scala 277:28]
- assign io_mlu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_mlu_op = {io_mlu_op_hi,io_mlu_op_lo}; // @[Decode.scala 279:22]
- assign io_dvu_valid = decodeEn & dvuValid_value_1_0; // @[Decode.scala 295:28]
- assign io_dvu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_dvu_op = {io_dvu_op_hi,io_dvu_op_lo}; // @[Decode.scala 297:22]
- assign io_vinst_valid = decodeEn & vinstValid_value_2_0; // @[Decode.scala 311:30]
- assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_vinst_inst = io_inst_inst; // @[Decode.scala 313:17]
- assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 314:26]
- assign io_serializeOut_mul = mluValid_value_2_0 | mluValid_value__4; // @[Library.scala 208:39]
- assign io_serializeOut_jump = _io_serializeOut_jump_T_5 | d_io_ectxsw | d_io_mpause | d_io_mret; // @[Decode.scala 391:69]
- assign io_serializeOut_brcond = bruOp_2 | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 393:65]
- assign io_slog = decodeEn & d_io_slog; // @[Decode.scala 323:23]
- assign d_clock = clock;
- assign d_reset = reset;
- assign d_io_addr = io_inst_addr; // @[Decode.scala 108:13]
- assign d_io_inst = io_inst_inst; // @[Decode.scala 109:13]
-endmodule
-module DecodedInstruction_1(
- input clock,
- input reset,
- input [31:0] io_addr,
- input [31:0] io_inst,
- output [31:0] io_imm12,
- output [31:0] io_imm20,
- output [31:0] io_immjal,
- output [31:0] io_immbr,
- output [31:0] io_immst,
- output io_lui,
- output io_auipc,
- output io_jal,
- output io_jalr,
- output io_beq,
- output io_bne,
- output io_blt,
- output io_bge,
- output io_bltu,
- output io_bgeu,
- output io_csrrw,
- output io_csrrs,
- output io_csrrc,
- output io_lb,
- output io_lh,
- output io_lw,
- output io_lbu,
- output io_lhu,
- output io_sb,
- output io_sh,
- output io_sw,
- output io_fence,
- output io_addi,
- output io_slti,
- output io_sltiu,
- output io_xori,
- output io_ori,
- output io_andi,
- output io_slli,
- output io_srli,
- output io_srai,
- output io_add,
- output io_sub,
- output io_slt,
- output io_sltu,
- output io_xor,
- output io_or,
- output io_and,
- output io_sll,
- output io_srl,
- output io_sra,
- output io_mul,
- output io_mulh,
- output io_mulhsu,
- output io_mulhu,
- output io_mulhr,
- output io_mulhsur,
- output io_mulhur,
- output io_dmulh,
- output io_dmulhr,
- output io_div,
- output io_divu,
- output io_rem,
- output io_remu,
- output io_clz,
- output io_ctz,
- output io_pcnt,
- output io_min,
- output io_minu,
- output io_max,
- output io_maxu,
- output io_getvl,
- output io_getmaxvl,
- output io_vld,
- output io_vst,
- output io_viop,
- output io_ebreak,
- output io_ecall,
- output io_eexit,
- output io_eyield,
- output io_ectxsw,
- output io_mpause,
- output io_mret,
- output io_undef,
- output io_fencei,
- output io_flushat,
- output io_flushall,
- output io_slog
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
-`endif // RANDOMIZE_REG_INIT
- wire [19:0] _io_imm12_T_2 = io_inst[31] ? 20'hfffff : 20'h0; // @[Bitwise.scala 74:12]
- wire [11:0] _io_immjal_T_2 = io_inst[31] ? 12'hfff : 12'h0; // @[Bitwise.scala 74:12]
- wire [10:0] io_immjal_lo = {io_inst[30:21],1'h0}; // @[Cat.scala 31:58]
- wire [20:0] io_immjal_hi = {_io_immjal_T_2,io_inst[19:12],io_inst[20]}; // @[Cat.scala 31:58]
- wire [4:0] io_immbr_lo = {io_inst[11:8],1'h0}; // @[Cat.scala 31:58]
- wire [26:0] io_immbr_hi = {_io_imm12_T_2,io_inst[7],io_inst[30:25]}; // @[Cat.scala 31:58]
- wire [26:0] io_immst_hi = {_io_imm12_T_2,io_inst[31:25]}; // @[Cat.scala 31:58]
- wire io_lui_bit_1 = io_inst[30]; // @[Library.scala 332:23]
- wire io_lui_bit_2 = io_inst[29]; // @[Library.scala 332:23]
- wire io_lui_bit_3 = io_inst[28]; // @[Library.scala 332:23]
- wire io_lui_bit_4 = io_inst[27]; // @[Library.scala 332:23]
- wire io_lui_bit_5 = io_inst[26]; // @[Library.scala 332:23]
- wire io_lui_bit_6 = io_inst[25]; // @[Library.scala 332:23]
- wire io_lui_bit_7 = io_inst[24]; // @[Library.scala 332:23]
- wire io_lui_bit_8 = io_inst[23]; // @[Library.scala 332:23]
- wire io_lui_bit_9 = io_inst[22]; // @[Library.scala 332:23]
- wire io_lui_bit_10 = io_inst[21]; // @[Library.scala 332:23]
- wire io_lui_bit_12 = io_inst[19]; // @[Library.scala 332:23]
- wire io_lui_bit_13 = io_inst[18]; // @[Library.scala 332:23]
- wire io_lui_bit_14 = io_inst[17]; // @[Library.scala 332:23]
- wire io_lui_bit_15 = io_inst[16]; // @[Library.scala 332:23]
- wire io_lui_bit_16 = io_inst[15]; // @[Library.scala 332:23]
- wire io_lui_bit_17 = io_inst[14]; // @[Library.scala 332:23]
- wire io_lui_bit_18 = io_inst[13]; // @[Library.scala 332:23]
- wire io_lui_bit_19 = io_inst[12]; // @[Library.scala 332:23]
- wire io_lui_bit_25 = ~io_inst[6]; // @[Library.scala 326:19]
- wire io_lui_bit_26 = io_inst[5]; // @[Library.scala 329:23]
- wire io_lui_bit_27 = io_inst[4]; // @[Library.scala 329:23]
- wire _io_lui_T_2 = io_lui_bit_25 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire io_lui_bit_28 = ~io_inst[3]; // @[Library.scala 326:19]
- wire _io_lui_T_3 = _io_lui_T_2 & io_lui_bit_28; // @[Library.scala 327:48]
- wire io_lui_bit_29 = io_inst[2]; // @[Library.scala 329:23]
- wire io_lui_bit_30 = io_inst[1]; // @[Library.scala 329:23]
- wire io_lui_bit_31 = io_inst[0]; // @[Library.scala 329:23]
- wire io_auipc_bit_26 = ~io_lui_bit_26; // @[Library.scala 326:19]
- wire _io_auipc_T_1 = io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_auipc_T_2 = _io_auipc_T_1 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_auipc_T_3 = _io_auipc_T_2 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_jal_T_1 = io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire io_jal_bit_27 = ~io_lui_bit_27; // @[Library.scala 326:19]
- wire _io_jal_T_2 = _io_jal_T_1 & io_jal_bit_27; // @[Library.scala 327:48]
- wire io_jalr_bit_17 = ~io_lui_bit_17; // @[Library.scala 326:19]
- wire io_jalr_bit_18 = ~io_lui_bit_18; // @[Library.scala 326:19]
- wire _io_jalr_T_1 = io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire io_jalr_bit_19 = ~io_lui_bit_19; // @[Library.scala 326:19]
- wire _io_jalr_T_2 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_jalr_T_4 = _io_jalr_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_jalr_T_6 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 327:48]
- wire io_beq_bit_29 = ~io_lui_bit_29; // @[Library.scala 326:19]
- wire _io_beq_T_7 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bne_T_2 = _io_jalr_T_1 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_bne_T_4 = _io_jalr_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bne_T_7 = _io_bne_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_blt_T_1 = io_lui_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_blt_T_2 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_blt_T_4 = _io_blt_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_blt_T_7 = _io_blt_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bge_T_2 = _io_blt_T_1 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_bge_T_4 = _io_blt_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bge_T_7 = _io_bge_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bltu_T_1 = io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_bltu_T_2 = _io_bltu_T_1 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_bltu_T_4 = _io_bltu_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bltu_T_7 = _io_bltu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bgeu_T_2 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_bgeu_T_4 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bgeu_T_7 = _io_bgeu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lb_T_3 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_lb_T_4 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_lb_T_7 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
- & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lh_T_3 = _io_bne_T_2 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_lh_T_7 = _io_bne_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lw_T_1 = io_jalr_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_lw_T_3 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_lw_T_4 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_lw_T_7 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 &
- io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lbu_T_4 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_lbu_T_7 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
- & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lhu_T_7 = _io_bge_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sb_T_4 = _io_lb_T_3 & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_sb_T_7 = _io_sb_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sh_T_4 = _io_lh_T_3 & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_sh_T_7 = _io_sh_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sw_T_4 = _io_lw_T_3 & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_sw_T_7 = _io_sw_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire io_fence_bit = ~io_inst[31]; // @[Library.scala 326:19]
- wire io_fence_bit_1 = ~io_lui_bit_1; // @[Library.scala 326:19]
- wire _io_fence_T_1 = io_fence_bit & io_fence_bit_1; // @[Library.scala 327:48]
- wire io_fence_bit_2 = ~io_lui_bit_2; // @[Library.scala 326:19]
- wire _io_fence_T_2 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2; // @[Library.scala 327:48]
- wire io_fence_bit_3 = ~io_lui_bit_3; // @[Library.scala 326:19]
- wire _io_fence_T_3 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3; // @[Library.scala 327:48]
- wire io_fence_bit_12 = ~io_lui_bit_12; // @[Library.scala 326:19]
- wire io_fence_bit_13 = ~io_lui_bit_13; // @[Library.scala 326:19]
- wire io_fence_bit_14 = ~io_lui_bit_14; // @[Library.scala 326:19]
- wire io_fence_bit_15 = ~io_lui_bit_15; // @[Library.scala 326:19]
- wire io_fence_bit_16 = ~io_lui_bit_16; // @[Library.scala 326:19]
- wire _io_addi_T_5 = _io_lb_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_addi_T_7 = _io_addi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_slti_T_5 = _io_lw_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_slti_T_7 = _io_slti_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sltiu_T_2 = io_jalr_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_sltiu_T_4 = _io_sltiu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_sltiu_T_5 = _io_sltiu_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sltiu_T_7 = _io_sltiu_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_xori_T_5 = _io_lbu_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_xori_T_7 = _io_xori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_ori_T_4 = _io_bltu_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_ori_T_5 = _io_ori_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_ori_T_7 = _io_ori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_andi_T_4 = _io_bgeu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_andi_T_5 = _io_andi_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_andi_T_7 = _io_andi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire io_slli_bit_4 = ~io_lui_bit_4; // @[Library.scala 326:19]
- wire _io_slli_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 327:48]
- wire io_slli_bit_5 = ~io_lui_bit_5; // @[Library.scala 326:19]
- wire _io_slli_T_5 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 327:48]
- wire io_slli_bit_6 = ~io_lui_bit_6; // @[Library.scala 326:19]
- wire _io_slli_T_6 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6; // @[Library.scala 327:48]
- wire _io_slli_T_7 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_slli_T_8 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_slli_T_9 = _io_slli_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_slli_T_10 = _io_slli_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_slli_T_11 = _io_slli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_slli_T_12 = _io_slli_T_11 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_slli_T_14 = _io_slli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_srli_T_7 = _io_slli_T_6 & io_lui_bit_17; // @[Library.scala 330:48]
- wire _io_srli_T_8 = _io_srli_T_7 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_srli_T_9 = _io_srli_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_srli_T_10 = _io_srli_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_srli_T_11 = _io_srli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_srli_T_12 = _io_srli_T_11 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_srli_T_14 = _io_srli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_srai_T_1 = io_fence_bit & io_lui_bit_1; // @[Library.scala 330:48]
- wire _io_srai_T_2 = _io_srai_T_1 & io_fence_bit_2; // @[Library.scala 327:48]
- wire _io_srai_T_6 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 327:48]
- wire _io_srai_T_7 = _io_srai_T_6 & io_lui_bit_17; // @[Library.scala 330:48]
- wire _io_srai_T_8 = _io_srai_T_7 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_srai_T_9 = _io_srai_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_srai_T_10 = _io_srai_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_srai_T_11 = _io_srai_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_srai_T_12 = _io_srai_T_11 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_srai_T_14 = _io_srai_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_add_T_10 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_add_T_12 = _io_add_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_add_T_14 = _io_add_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sub_T_10 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 &
- io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_sub_T_12 = _io_sub_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sub_T_14 = _io_sub_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_slt_T_8 = _io_slli_T_7 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_slt_T_10 = _io_slt_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_slt_T_12 = _io_slt_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_slt_T_14 = _io_slt_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sltu_T_9 = _io_slli_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_sltu_T_10 = _io_sltu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_sltu_T_12 = _io_sltu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sltu_T_14 = _io_sltu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_xor_T_10 = _io_srli_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_xor_T_12 = _io_xor_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_xor_T_14 = _io_xor_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_or_T_8 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_or_T_10 = _io_or_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_or_T_12 = _io_or_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_or_T_14 = _io_or_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_and_T_9 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_and_T_10 = _io_and_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_and_T_12 = _io_and_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_and_T_14 = _io_and_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sll_T_12 = _io_slli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sll_T_14 = _io_sll_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_srl_T_12 = _io_srli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_srl_T_14 = _io_srl_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sra_T_12 = _io_srai_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sra_T_14 = _io_sra_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mul_T_6 = _io_slli_T_5 & io_lui_bit_6; // @[Library.scala 330:48]
- wire _io_mul_T_7 = _io_mul_T_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_mul_T_8 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_mul_T_10 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mul_T_12 = _io_mul_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mul_T_14 = _io_mul_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulh_T_9 = _io_mul_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulh_T_10 = _io_mulh_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulh_T_12 = _io_mulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulh_T_14 = _io_mulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhsu_T_8 = _io_mul_T_7 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_mulhsu_T_10 = _io_mulhsu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhsu_T_12 = _io_mulhsu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhsu_T_14 = _io_mulhsu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhu_T_9 = _io_mul_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulhu_T_10 = _io_mulhu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhu_T_12 = _io_mulhu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhu_T_14 = _io_mulhu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhr_T_2 = _io_fence_T_1 & io_lui_bit_2; // @[Library.scala 330:48]
- wire _io_mulhr_T_4 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 327:48]
- wire _io_mulhr_T_5 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 327:48]
- wire _io_mulhr_T_6 = _io_mulhr_T_5 & io_lui_bit_6; // @[Library.scala 330:48]
- wire _io_mulhr_T_7 = _io_mulhr_T_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_mulhr_T_8 = _io_mulhr_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_mulhr_T_9 = _io_mulhr_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulhr_T_10 = _io_mulhr_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhr_T_12 = _io_mulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhr_T_14 = _io_mulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhsur_T_8 = _io_mulhr_T_7 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_mulhsur_T_10 = _io_mulhsur_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhsur_T_12 = _io_mulhsur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhsur_T_14 = _io_mulhsur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhur_T_9 = _io_mulhr_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulhur_T_10 = _io_mulhur_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhur_T_12 = _io_mulhur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhur_T_14 = _io_mulhur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_dmulh_T_5 = _io_slli_T_4 & io_lui_bit_5; // @[Library.scala 330:48]
- wire _io_dmulh_T_8 = _io_dmulh_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_dmulh_T_9 = _io_dmulh_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_dmulh_T_10 = _io_dmulh_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_dmulh_T_12 = _io_dmulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_dmulh_T_14 = _io_dmulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_dmulhr_T_5 = _io_mulhr_T_4 & io_lui_bit_5; // @[Library.scala 330:48]
- wire _io_dmulhr_T_8 = _io_dmulhr_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_dmulhr_T_9 = _io_dmulhr_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_dmulhr_T_10 = _io_dmulhr_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_dmulhr_T_12 = _io_dmulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_dmulhr_T_14 = _io_dmulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_clz_T_2 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2; // @[Library.scala 330:48]
- wire io_clz_bit_7 = ~io_lui_bit_7; // @[Library.scala 326:19]
- wire io_clz_bit_8 = ~io_lui_bit_8; // @[Library.scala 326:19]
- wire io_clz_bit_9 = ~io_lui_bit_9; // @[Library.scala 326:19]
- wire _io_clz_T_9 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
- io_clz_bit_8 & io_clz_bit_9; // @[Library.scala 327:48]
- wire io_clz_bit_10 = ~io_lui_bit_10; // @[Library.scala 326:19]
- wire _io_clz_T_10 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
- io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10; // @[Library.scala 327:48]
- wire io_clz_bit_11 = ~io_inst[20]; // @[Library.scala 326:19]
- wire _io_clz_T_13 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
- io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_clz_T_14 = _io_clz_T_13 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_clz_T_16 = _io_clz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_clz_T_17 = _io_clz_T_16 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_clz_T_19 = _io_clz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_ctz_T_11 = _io_clz_T_10 & io_inst[20]; // @[Library.scala 330:48]
- wire _io_ctz_T_13 = _io_ctz_T_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_ctz_T_14 = _io_ctz_T_13 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_ctz_T_16 = _io_ctz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_ctz_T_17 = _io_ctz_T_16 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_ctz_T_19 = _io_ctz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_pcnt_T_10 = _io_clz_T_9 & io_lui_bit_10; // @[Library.scala 330:48]
- wire _io_pcnt_T_13 = _io_pcnt_T_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_pcnt_T_14 = _io_pcnt_T_13 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_pcnt_T_16 = _io_pcnt_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_pcnt_T_17 = _io_pcnt_T_16 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_pcnt_T_19 = _io_pcnt_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_min_T_4 = _io_fence_T_3 & io_lui_bit_4; // @[Library.scala 330:48]
- wire _io_min_T_5 = _io_min_T_4 & io_slli_bit_5; // @[Library.scala 327:48]
- wire _io_min_T_7 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 330:48]
- wire _io_min_T_8 = _io_min_T_7 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_min_T_10 = _io_min_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_min_T_12 = _io_min_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_min_T_14 = _io_min_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_minu_T_9 = _io_min_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_minu_T_10 = _io_minu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_minu_T_12 = _io_minu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_minu_T_14 = _io_minu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_max_T_8 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_max_T_10 = _io_max_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_max_T_12 = _io_max_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_max_T_14 = _io_max_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_maxu_T_9 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_maxu_T_10 = _io_maxu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_maxu_T_12 = _io_maxu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_maxu_T_14 = _io_maxu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_getvl_T_3 = _io_fence_T_2 & io_lui_bit_3; // @[Library.scala 330:48]
- wire _io_getvl_T_6 = _io_getvl_T_3 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 584:89]
- wire _io_getmaxvl_T_16 = _io_getvl_T_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11
- & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 &
- io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_getmaxvl_T_19 = _io_getmaxvl_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_getmaxvl_T_20 = _io_getmaxvl_T_19 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_getmaxvl_T_23 = _io_getmaxvl_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _io_vld_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_vst_T_4 = _io_mulhr_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_vst_T_9 = _io_vst_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _io_vst_T_14 = _io_clz_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_vst_T_19 = _io_vst_T_14 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _vconv_T_3 = _io_srai_T_2 & io_lui_bit_3; // @[Library.scala 330:48]
- wire _vconv_T_17 = _vconv_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 &
- io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15
- & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire vconv = _vconv_T_17 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _vdup_T_11 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_6 & io_fence_bit_12 &
- io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 597:72]
- wire vdupi = vdup & io_slli_bit_5; // @[Decode.scala 598:20]
- wire _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 602:22]
- wire _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 601:28]
- wire _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 602:30]
- wire [9:0] decoded_lo_lo_hi = {io_minu,io_max,io_maxu,io_viop,io_vld,io_vst,io_getvl,io_getmaxvl,io_ebreak,io_ecall}; // @[Cat.scala 31:58]
- wire [18:0] decoded_lo_lo = {decoded_lo_lo_hi,io_eexit,io_eyield,io_ectxsw,io_mpause,io_mret,io_fencei,io_flushat,
- io_flushall,io_slog}; // @[Cat.scala 31:58]
- wire [9:0] decoded_lo_hi_hi = {io_srl,io_sra,io_mul,io_mulh,io_mulhsu,io_mulhu,io_mulhr,io_mulhsur,io_mulhur,io_dmulh}
- ; // @[Cat.scala 31:58]
- wire [18:0] decoded_lo_hi = {decoded_lo_hi_hi,io_dmulhr,io_div,io_divu,io_rem,io_remu,io_clz,io_ctz,io_pcnt,io_min}; // @[Cat.scala 31:58]
- wire [9:0] decoded_hi_lo_hi = {io_sw,io_fence,io_addi,io_slti,io_sltiu,io_xori,io_ori,io_andi,io_add,io_sub}; // @[Cat.scala 31:58]
- wire [18:0] decoded_hi_lo = {decoded_hi_lo_hi,io_slt,io_sltu,io_xor,io_or,io_and,io_slli,io_srli,io_srai,io_sll}; // @[Cat.scala 31:58]
- wire [9:0] decoded_hi_hi_lo = {io_csrrw,io_csrrs,io_csrrc,io_lb,io_lh,io_lw,io_lbu,io_lhu,io_sb,io_sh}; // @[Cat.scala 31:58]
- wire [9:0] decoded_hi_hi_hi = {io_lui,io_auipc,io_jal,io_jalr,io_beq,io_bne,io_blt,io_bge,io_bltu,io_bgeu}; // @[Cat.scala 31:58]
- wire [76:0] decoded = {decoded_hi_hi_hi,decoded_hi_hi_lo,decoded_hi_lo,decoded_lo_hi,decoded_lo_lo}; // @[Cat.scala 31:58]
- wire io_undef_value__38 = decoded[76]; // @[Library.scala 196:26]
- wire io_undef_value__0 = decoded[0] | decoded[1]; // @[Library.scala 208:39]
- wire io_undef_value__1 = decoded[2] | decoded[3]; // @[Library.scala 208:39]
- wire io_undef_value__2 = decoded[4] | decoded[5]; // @[Library.scala 208:39]
- wire io_undef_value__3 = decoded[6] | decoded[7]; // @[Library.scala 208:39]
- wire io_undef_value__4 = decoded[8] | decoded[9]; // @[Library.scala 208:39]
- wire io_undef_value__5 = decoded[10] | decoded[11]; // @[Library.scala 208:39]
- wire io_undef_value__6 = decoded[12] | decoded[13]; // @[Library.scala 208:39]
- wire io_undef_value__7 = decoded[14] | decoded[15]; // @[Library.scala 208:39]
- wire io_undef_value__8 = decoded[16] | decoded[17]; // @[Library.scala 208:39]
- wire io_undef_value__9 = decoded[18] | decoded[19]; // @[Library.scala 208:39]
- wire io_undef_value__10 = decoded[20] | decoded[21]; // @[Library.scala 208:39]
- wire io_undef_value__11 = decoded[22] | decoded[23]; // @[Library.scala 208:39]
- wire io_undef_value__12 = decoded[24] | decoded[25]; // @[Library.scala 208:39]
- wire io_undef_value__13 = decoded[26] | decoded[27]; // @[Library.scala 208:39]
- wire io_undef_value__14 = decoded[28] | decoded[29]; // @[Library.scala 208:39]
- wire io_undef_value__15 = decoded[30] | decoded[31]; // @[Library.scala 208:39]
- wire io_undef_value__16 = decoded[32] | decoded[33]; // @[Library.scala 208:39]
- wire io_undef_value__17 = decoded[34] | decoded[35]; // @[Library.scala 208:39]
- wire io_undef_value__18 = decoded[36] | decoded[37]; // @[Library.scala 208:39]
- wire io_undef_value__19 = decoded[38] | decoded[39]; // @[Library.scala 208:39]
- wire io_undef_value__20 = decoded[40] | decoded[41]; // @[Library.scala 208:39]
- wire io_undef_value__21 = decoded[42] | decoded[43]; // @[Library.scala 208:39]
- wire io_undef_value__22 = decoded[44] | decoded[45]; // @[Library.scala 208:39]
- wire io_undef_value__23 = decoded[46] | decoded[47]; // @[Library.scala 208:39]
- wire io_undef_value__24 = decoded[48] | decoded[49]; // @[Library.scala 208:39]
- wire io_undef_value__25 = decoded[50] | decoded[51]; // @[Library.scala 208:39]
- wire io_undef_value__26 = decoded[52] | decoded[53]; // @[Library.scala 208:39]
- wire io_undef_value__27 = decoded[54] | decoded[55]; // @[Library.scala 208:39]
- wire io_undef_value__28 = decoded[56] | decoded[57]; // @[Library.scala 208:39]
- wire io_undef_value__29 = decoded[58] | decoded[59]; // @[Library.scala 208:39]
- wire io_undef_value__30 = decoded[60] | decoded[61]; // @[Library.scala 208:39]
- wire io_undef_value__31 = decoded[62] | decoded[63]; // @[Library.scala 208:39]
- wire io_undef_value__32 = decoded[64] | decoded[65]; // @[Library.scala 208:39]
- wire io_undef_value__33 = decoded[66] | decoded[67]; // @[Library.scala 208:39]
- wire io_undef_value__34 = decoded[68] | decoded[69]; // @[Library.scala 208:39]
- wire io_undef_value__35 = decoded[70] | decoded[71]; // @[Library.scala 208:39]
- wire io_undef_value__36 = decoded[72] | decoded[73]; // @[Library.scala 208:39]
- wire io_undef_value__37 = decoded[74] | decoded[75]; // @[Library.scala 208:39]
- wire io_undef_value_1_0 = io_undef_value__0 | io_undef_value__1; // @[Library.scala 208:39]
- wire io_undef_value_1_1 = io_undef_value__2 | io_undef_value__3; // @[Library.scala 208:39]
- wire io_undef_value_1_2 = io_undef_value__4 | io_undef_value__5; // @[Library.scala 208:39]
- wire io_undef_value_1_3 = io_undef_value__6 | io_undef_value__7; // @[Library.scala 208:39]
- wire io_undef_value_1_4 = io_undef_value__8 | io_undef_value__9; // @[Library.scala 208:39]
- wire io_undef_value_1_5 = io_undef_value__10 | io_undef_value__11; // @[Library.scala 208:39]
- wire io_undef_value_1_6 = io_undef_value__12 | io_undef_value__13; // @[Library.scala 208:39]
- wire io_undef_value_1_7 = io_undef_value__14 | io_undef_value__15; // @[Library.scala 208:39]
- wire io_undef_value_1_8 = io_undef_value__16 | io_undef_value__17; // @[Library.scala 208:39]
- wire io_undef_value_1_9 = io_undef_value__18 | io_undef_value__19; // @[Library.scala 208:39]
- wire io_undef_value_1_10 = io_undef_value__20 | io_undef_value__21; // @[Library.scala 208:39]
- wire io_undef_value_1_11 = io_undef_value__22 | io_undef_value__23; // @[Library.scala 208:39]
- wire io_undef_value_1_12 = io_undef_value__24 | io_undef_value__25; // @[Library.scala 208:39]
- wire io_undef_value_1_13 = io_undef_value__26 | io_undef_value__27; // @[Library.scala 208:39]
- wire io_undef_value_1_14 = io_undef_value__28 | io_undef_value__29; // @[Library.scala 208:39]
- wire io_undef_value_1_15 = io_undef_value__30 | io_undef_value__31; // @[Library.scala 208:39]
- wire io_undef_value_1_16 = io_undef_value__32 | io_undef_value__33; // @[Library.scala 208:39]
- wire io_undef_value_1_17 = io_undef_value__34 | io_undef_value__35; // @[Library.scala 208:39]
- wire io_undef_value_1_18 = io_undef_value__36 | io_undef_value__37; // @[Library.scala 208:39]
- wire io_undef_value_2_0 = io_undef_value_1_0 | io_undef_value_1_1; // @[Library.scala 208:39]
- wire io_undef_value_2_1 = io_undef_value_1_2 | io_undef_value_1_3; // @[Library.scala 208:39]
- wire io_undef_value_2_2 = io_undef_value_1_4 | io_undef_value_1_5; // @[Library.scala 208:39]
- wire io_undef_value_2_3 = io_undef_value_1_6 | io_undef_value_1_7; // @[Library.scala 208:39]
- wire io_undef_value_2_4 = io_undef_value_1_8 | io_undef_value_1_9; // @[Library.scala 208:39]
- wire io_undef_value_2_5 = io_undef_value_1_10 | io_undef_value_1_11; // @[Library.scala 208:39]
- wire io_undef_value_2_6 = io_undef_value_1_12 | io_undef_value_1_13; // @[Library.scala 208:39]
- wire io_undef_value_2_7 = io_undef_value_1_14 | io_undef_value_1_15; // @[Library.scala 208:39]
- wire io_undef_value_2_8 = io_undef_value_1_16 | io_undef_value_1_17; // @[Library.scala 208:39]
- wire io_undef_value_2_9 = io_undef_value_1_18 | io_undef_value__38; // @[Library.scala 208:39]
- wire io_undef_value_3_0 = io_undef_value_2_0 | io_undef_value_2_1; // @[Library.scala 208:39]
- wire io_undef_value_3_1 = io_undef_value_2_2 | io_undef_value_2_3; // @[Library.scala 208:39]
- wire io_undef_value_3_2 = io_undef_value_2_4 | io_undef_value_2_5; // @[Library.scala 208:39]
- wire io_undef_value_3_3 = io_undef_value_2_6 | io_undef_value_2_7; // @[Library.scala 208:39]
- wire io_undef_value_3_4 = io_undef_value_2_8 | io_undef_value_2_9; // @[Library.scala 208:39]
- wire io_undef_value_4_0 = io_undef_value_3_0 | io_undef_value_3_1; // @[Library.scala 208:39]
- wire io_undef_value_4_1 = io_undef_value_3_2 | io_undef_value_3_3; // @[Library.scala 208:39]
- wire io_undef_value_5_0 = io_undef_value_4_0 | io_undef_value_4_1; // @[Library.scala 208:39]
- wire io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_3_4; // @[Library.scala 208:39]
- reg onehot_failed; // @[Decode.scala 670:30]
- wire _T_2 = ~reset; // @[Decode.scala 671:9]
- wire [1:0] _onehot_decode_T_77 = decoded[0] + decoded[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_79 = decoded[2] + decoded[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_81 = _onehot_decode_T_77 + _onehot_decode_T_79; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_83 = decoded[4] + decoded[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_85 = decoded[7] + decoded[8]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_1 = {{1'd0}, decoded[6]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_87 = _GEN_1 + _onehot_decode_T_85; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_89 = _onehot_decode_T_83 + _onehot_decode_T_87[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_91 = _onehot_decode_T_81 + _onehot_decode_T_89; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_93 = decoded[9] + decoded[10]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_95 = decoded[12] + decoded[13]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_2 = {{1'd0}, decoded[11]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_97 = _GEN_2 + _onehot_decode_T_95; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_99 = _onehot_decode_T_93 + _onehot_decode_T_97[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_101 = decoded[14] + decoded[15]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_103 = decoded[17] + decoded[18]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_3 = {{1'd0}, decoded[16]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_105 = _GEN_3 + _onehot_decode_T_103; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_107 = _onehot_decode_T_101 + _onehot_decode_T_105[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_109 = _onehot_decode_T_99 + _onehot_decode_T_107; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_111 = _onehot_decode_T_91 + _onehot_decode_T_109; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_113 = decoded[19] + decoded[20]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_115 = decoded[21] + decoded[22]; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_117 = _onehot_decode_T_113 + _onehot_decode_T_115; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_119 = decoded[23] + decoded[24]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_121 = decoded[26] + decoded[27]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_4 = {{1'd0}, decoded[25]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_123 = _GEN_4 + _onehot_decode_T_121; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_125 = _onehot_decode_T_119 + _onehot_decode_T_123[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_127 = _onehot_decode_T_117 + _onehot_decode_T_125; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_129 = decoded[28] + decoded[29]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_131 = decoded[31] + decoded[32]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_5 = {{1'd0}, decoded[30]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_133 = _GEN_5 + _onehot_decode_T_131; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_135 = _onehot_decode_T_129 + _onehot_decode_T_133[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_137 = decoded[33] + decoded[34]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_139 = decoded[36] + decoded[37]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_6 = {{1'd0}, decoded[35]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_141 = _GEN_6 + _onehot_decode_T_139; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_143 = _onehot_decode_T_137 + _onehot_decode_T_141[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_145 = _onehot_decode_T_135 + _onehot_decode_T_143; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_147 = _onehot_decode_T_127 + _onehot_decode_T_145; // @[Bitwise.scala 48:55]
- wire [5:0] _onehot_decode_T_149 = _onehot_decode_T_111 + _onehot_decode_T_147; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_151 = decoded[38] + decoded[39]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_153 = decoded[40] + decoded[41]; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_155 = _onehot_decode_T_151 + _onehot_decode_T_153; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_157 = decoded[42] + decoded[43]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_159 = decoded[45] + decoded[46]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_7 = {{1'd0}, decoded[44]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_161 = _GEN_7 + _onehot_decode_T_159; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_163 = _onehot_decode_T_157 + _onehot_decode_T_161[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_165 = _onehot_decode_T_155 + _onehot_decode_T_163; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_167 = decoded[47] + decoded[48]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_169 = decoded[50] + decoded[51]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_8 = {{1'd0}, decoded[49]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_171 = _GEN_8 + _onehot_decode_T_169; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_173 = _onehot_decode_T_167 + _onehot_decode_T_171[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_175 = decoded[52] + decoded[53]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_177 = decoded[55] + decoded[56]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_9 = {{1'd0}, decoded[54]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_179 = _GEN_9 + _onehot_decode_T_177; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_181 = _onehot_decode_T_175 + _onehot_decode_T_179[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_183 = _onehot_decode_T_173 + _onehot_decode_T_181; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_185 = _onehot_decode_T_165 + _onehot_decode_T_183; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_187 = decoded[57] + decoded[58]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_189 = decoded[60] + decoded[61]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_10 = {{1'd0}, decoded[59]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_191 = _GEN_10 + _onehot_decode_T_189; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_193 = _onehot_decode_T_187 + _onehot_decode_T_191[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_195 = decoded[62] + decoded[63]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_197 = decoded[65] + decoded[66]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_11 = {{1'd0}, decoded[64]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_199 = _GEN_11 + _onehot_decode_T_197; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_201 = _onehot_decode_T_195 + _onehot_decode_T_199[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_203 = _onehot_decode_T_193 + _onehot_decode_T_201; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_205 = decoded[67] + decoded[68]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_207 = decoded[70] + decoded[71]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_12 = {{1'd0}, decoded[69]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_209 = _GEN_12 + _onehot_decode_T_207; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_211 = _onehot_decode_T_205 + _onehot_decode_T_209[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_213 = decoded[72] + decoded[73]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_215 = decoded[75] + io_undef_value__38; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_13 = {{1'd0}, decoded[74]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_217 = _GEN_13 + _onehot_decode_T_215; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_219 = _onehot_decode_T_213 + _onehot_decode_T_217[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_221 = _onehot_decode_T_211 + _onehot_decode_T_219; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_223 = _onehot_decode_T_203 + _onehot_decode_T_221; // @[Bitwise.scala 48:55]
- wire [5:0] _onehot_decode_T_225 = _onehot_decode_T_185 + _onehot_decode_T_223; // @[Bitwise.scala 48:55]
- wire [6:0] onehot_decode = _onehot_decode_T_149 + _onehot_decode_T_225; // @[Bitwise.scala 48:55]
- wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 674:24]
- wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 674:24]
- wire _T_6 = _T_5 != 7'h1; // @[Decode.scala 674:36]
- assign io_imm12 = {_io_imm12_T_2,io_inst[31:20]}; // @[Cat.scala 31:58]
- assign io_imm20 = {io_inst[31:12],12'h0}; // @[Cat.scala 31:58]
- assign io_immjal = {io_immjal_hi,io_immjal_lo}; // @[Cat.scala 31:58]
- assign io_immbr = {io_immbr_hi,io_immbr_lo}; // @[Cat.scala 31:58]
- assign io_immst = {io_immst_hi,io_inst[11:7]}; // @[Cat.scala 31:58]
- assign io_lui = _io_lui_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_auipc = _io_auipc_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_jal = _io_jal_T_2 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_jalr = _io_jalr_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_beq = _io_beq_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bne = _io_bne_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_blt = _io_blt_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_csrrw = 1'h0; // @[Decode.scala 624:14]
- assign io_csrrs = 1'h0; // @[Decode.scala 625:14]
- assign io_csrrc = 1'h0; // @[Decode.scala 626:14]
- assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lbu = _io_lbu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lhu = _io_lhu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_fence = 1'h0; // @[Decode.scala 641:17]
- assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_xori = _io_xori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_ori = _io_ori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_andi = _io_andi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_slli = _io_slli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_srli = _io_srli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_srai = _io_srai_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_add = _io_add_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sub = _io_sub_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_slt = _io_slt_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sltu = _io_sltu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_xor = _io_xor_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_or = _io_or_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_and = _io_and_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sll = _io_sll_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_srl = _io_srl_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sra = _io_sra_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mul = _io_mul_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulh = _io_mulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhsu = _io_mulhsu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhu = _io_mulhu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhr = _io_mulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhsur = _io_mulhsur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_div = 1'h0; // @[Decode.scala 628:12]
- assign io_divu = 1'h0; // @[Decode.scala 629:13]
- assign io_rem = 1'h0; // @[Decode.scala 630:12]
- assign io_remu = 1'h0; // @[Decode.scala 631:13]
- assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_min = _io_min_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 584:97]
- assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 585:76]
- assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 590:71]
- assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 603:20]
- assign io_ebreak = 1'h0; // @[Decode.scala 633:15]
- assign io_ecall = 1'h0; // @[Decode.scala 634:15]
- assign io_eexit = 1'h0; // @[Decode.scala 635:15]
- assign io_eyield = 1'h0; // @[Decode.scala 636:15]
- assign io_ectxsw = 1'h0; // @[Decode.scala 637:15]
- assign io_mpause = 1'h0; // @[Decode.scala 638:15]
- assign io_mret = 1'h0; // @[Decode.scala 639:15]
- assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 667:15]
- assign io_fencei = 1'h0; // @[Decode.scala 642:17]
- assign io_flushat = 1'h0; // @[Decode.scala 643:17]
- assign io_flushall = 1'h0; // @[Decode.scala 644:17]
- assign io_slog = 1'h0; // @[Decode.scala 646:13]
- always @(posedge clock) begin
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~onehot_failed)) begin
- $fatal; // @[Decode.scala 671:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~onehot_failed)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Decode.scala:671 assert(!onehot_failed)\n"); // @[Decode.scala 671:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_6 & _T_2) begin
- $fwrite(32'h80000002,"[FAIL] decode inst=%x addr=%x decoded=0b%b pipeline=%d\n",io_inst,io_addr,decoded,1'h1
- ); // @[Decode.scala 676:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Decode.scala 674:45]
- onehot_failed <= 1'h0; // @[Decode.scala 675:19]
- end else begin
- onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 670:30]
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- onehot_failed = _RAND_0[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- onehot_failed = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Decode_1(
- input clock,
- input reset,
- input io_halted,
- input io_inst_valid,
- output io_inst_ready,
- input [31:0] io_inst_addr,
- input [31:0] io_inst_inst,
- input io_inst_brchFwd,
- input [31:0] io_scoreboard_regd,
- input [31:0] io_scoreboard_comb,
- output [31:0] io_scoreboard_spec,
- output io_rs1Read_valid,
- output [4:0] io_rs1Read_addr,
- output io_rs1Set_valid,
- output [31:0] io_rs1Set_value,
- output io_rs2Read_valid,
- output [4:0] io_rs2Read_addr,
- output io_rs2Set_valid,
- output [31:0] io_rs2Set_value,
- output io_rdMark_valid,
- output [4:0] io_rdMark_addr,
- output io_busRead_bypass,
- output [31:0] io_busRead_immed,
- output io_alu_valid,
- output [4:0] io_alu_addr,
- output [17:0] io_alu_op,
- output io_bru_valid,
- output io_bru_fwd,
- output [16:0] io_bru_op,
- output [31:0] io_bru_pc,
- output [31:0] io_bru_target,
- output [4:0] io_bru_link,
- output [2:0] io_csr_op,
- output io_lsu_valid,
- input io_lsu_ready,
- output [4:0] io_lsu_addr,
- output [11:0] io_lsu_op,
- output io_mlu_valid,
- output [4:0] io_mlu_addr,
- output [8:0] io_mlu_op,
- output [3:0] io_dvu_op,
- output io_vinst_valid,
- input io_vinst_ready,
- output [4:0] io_vinst_addr,
- output [31:0] io_vinst_inst,
- output [4:0] io_vinst_op,
- input io_branchTaken,
- input io_interlock,
- input io_serializeIn_mul,
- input io_serializeIn_jump,
- input io_serializeIn_brcond,
- output io_serializeOut_mul,
- output io_serializeOut_jump,
- output io_serializeOut_brcond
-);
- wire d_clock; // @[Decode.scala 107:17]
- wire d_reset; // @[Decode.scala 107:17]
- wire [31:0] d_io_addr; // @[Decode.scala 107:17]
- wire [31:0] d_io_inst; // @[Decode.scala 107:17]
- wire [31:0] d_io_imm12; // @[Decode.scala 107:17]
- wire [31:0] d_io_imm20; // @[Decode.scala 107:17]
- wire [31:0] d_io_immjal; // @[Decode.scala 107:17]
- wire [31:0] d_io_immbr; // @[Decode.scala 107:17]
- wire [31:0] d_io_immst; // @[Decode.scala 107:17]
- wire d_io_lui; // @[Decode.scala 107:17]
- wire d_io_auipc; // @[Decode.scala 107:17]
- wire d_io_jal; // @[Decode.scala 107:17]
- wire d_io_jalr; // @[Decode.scala 107:17]
- wire d_io_beq; // @[Decode.scala 107:17]
- wire d_io_bne; // @[Decode.scala 107:17]
- wire d_io_blt; // @[Decode.scala 107:17]
- wire d_io_bge; // @[Decode.scala 107:17]
- wire d_io_bltu; // @[Decode.scala 107:17]
- wire d_io_bgeu; // @[Decode.scala 107:17]
- wire d_io_csrrw; // @[Decode.scala 107:17]
- wire d_io_csrrs; // @[Decode.scala 107:17]
- wire d_io_csrrc; // @[Decode.scala 107:17]
- wire d_io_lb; // @[Decode.scala 107:17]
- wire d_io_lh; // @[Decode.scala 107:17]
- wire d_io_lw; // @[Decode.scala 107:17]
- wire d_io_lbu; // @[Decode.scala 107:17]
- wire d_io_lhu; // @[Decode.scala 107:17]
- wire d_io_sb; // @[Decode.scala 107:17]
- wire d_io_sh; // @[Decode.scala 107:17]
- wire d_io_sw; // @[Decode.scala 107:17]
- wire d_io_fence; // @[Decode.scala 107:17]
- wire d_io_addi; // @[Decode.scala 107:17]
- wire d_io_slti; // @[Decode.scala 107:17]
- wire d_io_sltiu; // @[Decode.scala 107:17]
- wire d_io_xori; // @[Decode.scala 107:17]
- wire d_io_ori; // @[Decode.scala 107:17]
- wire d_io_andi; // @[Decode.scala 107:17]
- wire d_io_slli; // @[Decode.scala 107:17]
- wire d_io_srli; // @[Decode.scala 107:17]
- wire d_io_srai; // @[Decode.scala 107:17]
- wire d_io_add; // @[Decode.scala 107:17]
- wire d_io_sub; // @[Decode.scala 107:17]
- wire d_io_slt; // @[Decode.scala 107:17]
- wire d_io_sltu; // @[Decode.scala 107:17]
- wire d_io_xor; // @[Decode.scala 107:17]
- wire d_io_or; // @[Decode.scala 107:17]
- wire d_io_and; // @[Decode.scala 107:17]
- wire d_io_sll; // @[Decode.scala 107:17]
- wire d_io_srl; // @[Decode.scala 107:17]
- wire d_io_sra; // @[Decode.scala 107:17]
- wire d_io_mul; // @[Decode.scala 107:17]
- wire d_io_mulh; // @[Decode.scala 107:17]
- wire d_io_mulhsu; // @[Decode.scala 107:17]
- wire d_io_mulhu; // @[Decode.scala 107:17]
- wire d_io_mulhr; // @[Decode.scala 107:17]
- wire d_io_mulhsur; // @[Decode.scala 107:17]
- wire d_io_mulhur; // @[Decode.scala 107:17]
- wire d_io_dmulh; // @[Decode.scala 107:17]
- wire d_io_dmulhr; // @[Decode.scala 107:17]
- wire d_io_div; // @[Decode.scala 107:17]
- wire d_io_divu; // @[Decode.scala 107:17]
- wire d_io_rem; // @[Decode.scala 107:17]
- wire d_io_remu; // @[Decode.scala 107:17]
- wire d_io_clz; // @[Decode.scala 107:17]
- wire d_io_ctz; // @[Decode.scala 107:17]
- wire d_io_pcnt; // @[Decode.scala 107:17]
- wire d_io_min; // @[Decode.scala 107:17]
- wire d_io_minu; // @[Decode.scala 107:17]
- wire d_io_max; // @[Decode.scala 107:17]
- wire d_io_maxu; // @[Decode.scala 107:17]
- wire d_io_getvl; // @[Decode.scala 107:17]
- wire d_io_getmaxvl; // @[Decode.scala 107:17]
- wire d_io_vld; // @[Decode.scala 107:17]
- wire d_io_vst; // @[Decode.scala 107:17]
- wire d_io_viop; // @[Decode.scala 107:17]
- wire d_io_ebreak; // @[Decode.scala 107:17]
- wire d_io_ecall; // @[Decode.scala 107:17]
- wire d_io_eexit; // @[Decode.scala 107:17]
- wire d_io_eyield; // @[Decode.scala 107:17]
- wire d_io_ectxsw; // @[Decode.scala 107:17]
- wire d_io_mpause; // @[Decode.scala 107:17]
- wire d_io_mret; // @[Decode.scala 107:17]
- wire d_io_undef; // @[Decode.scala 107:17]
- wire d_io_fencei; // @[Decode.scala 107:17]
- wire d_io_flushat; // @[Decode.scala 107:17]
- wire d_io_flushall; // @[Decode.scala 107:17]
- wire d_io_slog; // @[Decode.scala 107:17]
- wire decodeEn = io_inst_valid & io_inst_ready & ~io_branchTaken; // @[Decode.scala 104:49]
- wire vldst = d_io_vld | d_io_vst; // @[Decode.scala 111:24]
- wire vldst_wb = vldst & io_inst_inst[28]; // @[Decode.scala 112:24]
- wire [4:0] rdAddr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- wire [4:0] rs2Addr = io_inst_inst[24:20]; // @[Decode.scala 116:29]
- wire [4:0] rs3Addr = io_inst_inst[31:27]; // @[Decode.scala 117:29]
- wire _isAluImm_T_3 = d_io_addi | d_io_slti | d_io_sltiu | d_io_xori | d_io_ori; // @[Decode.scala 119:68]
- wire isAluImm = _isAluImm_T_3 | d_io_andi | d_io_slli | d_io_srli | d_io_srai; // @[Decode.scala 120:66]
- wire _isAluReg_T_4 = d_io_add | d_io_sub | d_io_slt | d_io_sltu | d_io_xor | d_io_or; // @[Decode.scala 122:76]
- wire isAluReg = _isAluReg_T_4 | d_io_and | d_io_sll | d_io_srl | d_io_sra; // @[Decode.scala 123:62]
- wire isAlu1Bit = d_io_clz | d_io_ctz | d_io_pcnt; // @[Decode.scala 125:40]
- wire isAlu2Bit = d_io_min | d_io_minu | d_io_max | d_io_maxu; // @[Decode.scala 126:53]
- wire _isCondBr_T_3 = d_io_beq | d_io_bne | d_io_blt | d_io_bge | d_io_bltu; // @[Decode.scala 128:63]
- wire isCondBr = _isCondBr_T_3 | d_io_bgeu; // @[Decode.scala 129:28]
- wire isLoad = d_io_lb | d_io_lh | d_io_lw | d_io_lbu | d_io_lhu; // @[Decode.scala 135:58]
- wire isStore = d_io_sb | d_io_sh | d_io_sw; // @[Decode.scala 136:36]
- wire isLsu = isLoad | isStore | d_io_vld | d_io_vst; // @[Decode.scala 137:45]
- wire isMul = d_io_mul | d_io_mulh | d_io_mulhsu | d_io_mulhu | d_io_mulhr | d_io_mulhsur | d_io_mulhur | d_io_dmulh
- | d_io_dmulhr; // @[Decode.scala 139:125]
- wire isVIop = io_vinst_op[4]; // @[Decode.scala 143:27]
- wire isVIopVs2 = isVIop & io_inst_inst[1:0] == 2'h0; // @[Decode.scala 146:26]
- wire [31:0] _aluRdEn_T = io_scoreboard_comb >> rdAddr; // @[Decode.scala 150:37]
- wire aluRdEn = ~_aluRdEn_T[0] | isVIop | isStore | isCondBr; // @[Decode.scala 150:71]
- wire [31:0] _aluRs1En_T = io_scoreboard_comb >> io_inst_inst[19:15]; // @[Decode.scala 151:37]
- wire aluRs1En = ~_aluRs1En_T[0] | isVIop | isLsu | d_io_auipc; // @[Decode.scala 151:69]
- wire [31:0] _aluRs2En_T = io_scoreboard_comb >> rs2Addr; // @[Decode.scala 152:37]
- wire aluRs2En = ~_aluRs2En_T[0] | isVIopVs2 | isLsu | d_io_auipc | isAluImm | isAlu1Bit; // @[Decode.scala 152:95]
- wire aluEn = aluRdEn & aluRs1En & aluRs2En; // @[Decode.scala 155:35]
- wire [31:0] _bruEn_T_1 = io_scoreboard_regd >> io_inst_inst[19:15]; // @[Decode.scala 158:48]
- wire _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 159:35]
- wire bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 158:58]
- wire _lsuEn_T = ~isLsu; // @[Decode.scala 162:15]
- wire _lsuEn_T_4 = ~io_serializeIn_brcond; // @[Decode.scala 164:26]
- wire _lsuEn_T_5 = _lsuEn_T | ~io_serializeIn_brcond; // @[Decode.scala 164:23]
- wire _lsuEn_T_6 = io_lsu_ready & _lsuEn_T_5; // @[Decode.scala 163:51]
- wire _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 165:20]
- wire _lsuEn_T_15 = _aluRs2En_T[0] & (isStore | vldst); // @[Decode.scala 167:49]
- wire _lsuEn_T_16 = _lsuEn_T_11 | _lsuEn_T_15; // @[Decode.scala 166:50]
- wire _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 165:15]
- wire _lsuEn_T_18 = _lsuEn_T_6 & _lsuEn_T_17; // @[Decode.scala 164:50]
- wire lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 162:22]
- wire mulEn = (~isMul | ~io_serializeIn_mul) & _lsuEn_T_4; // @[Decode.scala 170:47]
- wire _vinstEn_T_6 = ~(io_vinst_op != 5'h0 & ~io_vinst_ready); // @[Decode.scala 175:17]
- wire vinstEn = ~(isVIop & io_serializeIn_brcond) & _vinstEn_T_6; // @[Decode.scala 174:76]
- wire aluValid_value__0 = io_alu_op[0] | io_alu_op[1]; // @[Library.scala 208:39]
- wire aluValid_value__1 = io_alu_op[2] | io_alu_op[3]; // @[Library.scala 208:39]
- wire aluValid_value__2 = io_alu_op[4] | io_alu_op[5]; // @[Library.scala 208:39]
- wire aluValid_value__3 = io_alu_op[6] | io_alu_op[7]; // @[Library.scala 208:39]
- wire aluValid_value__4 = io_alu_op[8] | io_alu_op[9]; // @[Library.scala 208:39]
- wire aluValid_value__5 = io_alu_op[10] | io_alu_op[11]; // @[Library.scala 208:39]
- wire aluValid_value__6 = io_alu_op[12] | io_alu_op[13]; // @[Library.scala 208:39]
- wire aluValid_value__7 = io_alu_op[14] | io_alu_op[15]; // @[Library.scala 208:39]
- wire aluValid_value__8 = io_alu_op[16] | io_alu_op[17]; // @[Library.scala 208:39]
- wire aluValid_value_1_0 = aluValid_value__0 | aluValid_value__1; // @[Library.scala 208:39]
- wire aluValid_value_1_1 = aluValid_value__2 | aluValid_value__3; // @[Library.scala 208:39]
- wire aluValid_value_1_2 = aluValid_value__4 | aluValid_value__5; // @[Library.scala 208:39]
- wire aluValid_value_1_3 = aluValid_value__6 | aluValid_value__7; // @[Library.scala 208:39]
- wire aluValid_value_2_0 = aluValid_value_1_0 | aluValid_value_1_1; // @[Library.scala 208:39]
- wire aluValid_value_2_1 = aluValid_value_1_2 | aluValid_value_1_3; // @[Library.scala 208:39]
- wire aluValid_value_3_0 = aluValid_value_2_0 | aluValid_value_2_1; // @[Library.scala 208:39]
- wire aluValid_value_4_0 = aluValid_value_3_0 | aluValid_value__8; // @[Library.scala 208:39]
- wire aluOp_1 = d_io_sub; // @[Decode.scala 183:19 190:19]
- wire aluOp_0 = d_io_auipc | d_io_addi | d_io_add; // @[Decode.scala 189:46]
- wire aluOp_3 = d_io_sltiu | d_io_sltu; // @[Decode.scala 192:33]
- wire aluOp_2 = d_io_slti | d_io_slt; // @[Decode.scala 191:32]
- wire aluOp_5 = d_io_ori | d_io_or; // @[Decode.scala 194:31]
- wire aluOp_4 = d_io_xori | d_io_xor; // @[Decode.scala 193:32]
- wire aluOp_8 = d_io_srli | d_io_srl; // @[Decode.scala 197:32]
- wire aluOp_7 = d_io_slli | d_io_sll; // @[Decode.scala 196:32]
- wire aluOp_6 = d_io_andi | d_io_and; // @[Decode.scala 195:32]
- wire [8:0] io_alu_op_lo = {aluOp_8,aluOp_7,aluOp_6,aluOp_5,aluOp_4,aluOp_3,aluOp_2,aluOp_1,aluOp_0}; // @[Decode.scala 187:22]
- wire aluOp_10 = d_io_lui; // @[Decode.scala 183:19 199:19]
- wire aluOp_9 = d_io_srai | d_io_sra; // @[Decode.scala 198:32]
- wire aluOp_12 = d_io_ctz; // @[Decode.scala 183:19 201:19]
- wire aluOp_11 = d_io_clz; // @[Decode.scala 183:19 200:19]
- wire aluOp_14 = d_io_min; // @[Decode.scala 183:19 203:19]
- wire aluOp_13 = d_io_pcnt; // @[Decode.scala 183:19 202:19]
- wire aluOp_17 = d_io_maxu; // @[Decode.scala 183:19 206:19]
- wire aluOp_16 = d_io_max; // @[Decode.scala 183:19 205:19]
- wire aluOp_15 = d_io_minu; // @[Decode.scala 183:19 204:19]
- wire [8:0] io_alu_op_hi = {aluOp_17,aluOp_16,aluOp_15,aluOp_14,aluOp_13,aluOp_12,aluOp_11,aluOp_10,aluOp_9}; // @[Decode.scala 187:22]
- wire bruValid_value__8 = io_bru_op[16]; // @[Library.scala 196:26]
- wire bruValid_value__0 = io_bru_op[0] | io_bru_op[1]; // @[Library.scala 208:39]
- wire bruValid_value__1 = io_bru_op[2] | io_bru_op[3]; // @[Library.scala 208:39]
- wire bruValid_value__2 = io_bru_op[4] | io_bru_op[5]; // @[Library.scala 208:39]
- wire bruValid_value__3 = io_bru_op[6] | io_bru_op[7]; // @[Library.scala 208:39]
- wire bruValid_value__4 = io_bru_op[8] | io_bru_op[9]; // @[Library.scala 208:39]
- wire bruValid_value__5 = io_bru_op[10] | io_bru_op[11]; // @[Library.scala 208:39]
- wire bruValid_value__6 = io_bru_op[12] | io_bru_op[13]; // @[Library.scala 208:39]
- wire bruValid_value__7 = io_bru_op[14] | io_bru_op[15]; // @[Library.scala 208:39]
- wire bruValid_value_1_0 = bruValid_value__0 | bruValid_value__1; // @[Library.scala 208:39]
- wire bruValid_value_1_1 = bruValid_value__2 | bruValid_value__3; // @[Library.scala 208:39]
- wire bruValid_value_1_2 = bruValid_value__4 | bruValid_value__5; // @[Library.scala 208:39]
- wire bruValid_value_1_3 = bruValid_value__6 | bruValid_value__7; // @[Library.scala 208:39]
- wire bruValid_value_2_0 = bruValid_value_1_0 | bruValid_value_1_1; // @[Library.scala 208:39]
- wire bruValid_value_2_1 = bruValid_value_1_2 | bruValid_value_1_3; // @[Library.scala 208:39]
- wire bruValid_value_3_0 = bruValid_value_2_0 | bruValid_value_2_1; // @[Library.scala 208:39]
- wire bruValid_value_4_0 = bruValid_value_3_0 | bruValid_value__8; // @[Library.scala 208:39]
- wire bruOp_1 = d_io_jalr; // @[Decode.scala 210:19 220:19]
- wire bruOp_0 = d_io_jal; // @[Decode.scala 210:19 219:19]
- wire bruOp_3 = d_io_bne; // @[Decode.scala 210:19 222:19]
- wire bruOp_2 = d_io_beq; // @[Decode.scala 210:19 221:19]
- wire bruOp_5 = d_io_bge; // @[Decode.scala 210:19 224:19]
- wire bruOp_4 = d_io_blt; // @[Decode.scala 210:19 223:19]
- wire bruOp_7 = d_io_bgeu; // @[Decode.scala 210:19 226:19]
- wire bruOp_6 = d_io_bltu; // @[Decode.scala 210:19 225:19]
- wire [7:0] io_bru_op_lo = {bruOp_7,bruOp_6,bruOp_5,bruOp_4,bruOp_3,bruOp_2,bruOp_1,bruOp_0}; // @[Decode.scala 214:22]
- wire bruOp_16 = d_io_undef; // @[Decode.scala 210:19 235:21]
- wire [8:0] io_bru_op_hi = {bruOp_16,1'h0,1'h0,2'h0,4'h0}; // @[Decode.scala 214:22]
- wire [31:0] _io_bru_target_T_1 = io_inst_inst[2] ? d_io_immjal : d_io_immbr; // @[Decode.scala 216:38]
- wire csrValid_value__1 = io_csr_op[2]; // @[Library.scala 196:26]
- wire csrValid_value__0 = io_csr_op[0] | io_csr_op[1]; // @[Library.scala 208:39]
- wire csrValid_value_1_0 = csrValid_value__0 | csrValid_value__1; // @[Library.scala 208:39]
- wire lsuValid_value__0 = io_lsu_op[0] | io_lsu_op[1]; // @[Library.scala 208:39]
- wire lsuValid_value__1 = io_lsu_op[2] | io_lsu_op[3]; // @[Library.scala 208:39]
- wire lsuValid_value__2 = io_lsu_op[4] | io_lsu_op[5]; // @[Library.scala 208:39]
- wire lsuValid_value__3 = io_lsu_op[6] | io_lsu_op[7]; // @[Library.scala 208:39]
- wire lsuValid_value__4 = io_lsu_op[8] | io_lsu_op[9]; // @[Library.scala 208:39]
- wire lsuValid_value__5 = io_lsu_op[10] | io_lsu_op[11]; // @[Library.scala 208:39]
- wire lsuValid_value_1_0 = lsuValid_value__0 | lsuValid_value__1; // @[Library.scala 208:39]
- wire lsuValid_value_1_1 = lsuValid_value__2 | lsuValid_value__3; // @[Library.scala 208:39]
- wire lsuValid_value_1_2 = lsuValid_value__4 | lsuValid_value__5; // @[Library.scala 208:39]
- wire lsuValid_value_2_0 = lsuValid_value_1_0 | lsuValid_value_1_1; // @[Library.scala 208:39]
- wire lsuValid_value_3_0 = lsuValid_value_2_0 | lsuValid_value_1_2; // @[Library.scala 208:39]
- wire lsuOp_2 = d_io_lw; // @[Decode.scala 252:19 261:18]
- wire lsuOp_1 = d_io_lh; // @[Decode.scala 252:19 260:18]
- wire lsuOp_0 = d_io_lb; // @[Decode.scala 252:19 259:18]
- wire lsuOp_5 = d_io_sb; // @[Decode.scala 252:19 264:18]
- wire lsuOp_4 = d_io_lhu; // @[Decode.scala 252:19 263:18]
- wire lsuOp_3 = d_io_lbu; // @[Decode.scala 252:19 262:18]
- wire [5:0] io_lsu_op_lo = {lsuOp_5,lsuOp_4,lsuOp_3,lsuOp_2,lsuOp_1,lsuOp_0}; // @[Decode.scala 257:22]
- wire lsuOp_7 = d_io_sw; // @[Decode.scala 252:19 266:18]
- wire lsuOp_6 = d_io_sh; // @[Decode.scala 252:19 265:18]
- wire [5:0] io_lsu_op_hi = {vldst,1'h0,1'h0,1'h0,lsuOp_7,lsuOp_6}; // @[Decode.scala 257:22]
- wire mluValid_value__4 = io_mlu_op[8]; // @[Library.scala 196:26]
- wire mluValid_value__0 = io_mlu_op[0] | io_mlu_op[1]; // @[Library.scala 208:39]
- wire mluValid_value__1 = io_mlu_op[2] | io_mlu_op[3]; // @[Library.scala 208:39]
- wire mluValid_value__2 = io_mlu_op[4] | io_mlu_op[5]; // @[Library.scala 208:39]
- wire mluValid_value__3 = io_mlu_op[6] | io_mlu_op[7]; // @[Library.scala 208:39]
- wire mluValid_value_1_0 = mluValid_value__0 | mluValid_value__1; // @[Library.scala 208:39]
- wire mluValid_value_1_1 = mluValid_value__2 | mluValid_value__3; // @[Library.scala 208:39]
- wire mluValid_value_2_0 = mluValid_value_1_0 | mluValid_value_1_1; // @[Library.scala 208:39]
- wire mluValid_value_3_0 = mluValid_value_2_0 | mluValid_value__4; // @[Library.scala 208:39]
- wire mluOp_1 = d_io_mulh; // @[Decode.scala 275:19 282:22]
- wire mluOp_0 = d_io_mul; // @[Decode.scala 275:19 281:22]
- wire mluOp_3 = d_io_mulhu; // @[Decode.scala 275:19 284:22]
- wire mluOp_2 = d_io_mulhsu; // @[Decode.scala 275:19 283:22]
- wire [3:0] io_mlu_op_lo = {mluOp_3,mluOp_2,mluOp_1,mluOp_0}; // @[Decode.scala 279:22]
- wire mluOp_5 = d_io_mulhsur; // @[Decode.scala 275:19 286:22]
- wire mluOp_4 = d_io_mulhr; // @[Decode.scala 275:19 285:22]
- wire mluOp_8 = d_io_dmulhr; // @[Decode.scala 275:19 289:22]
- wire mluOp_7 = d_io_dmulh; // @[Decode.scala 275:19 288:22]
- wire mluOp_6 = d_io_mulhur; // @[Decode.scala 275:19 287:22]
- wire [4:0] io_mlu_op_hi = {mluOp_8,mluOp_7,mluOp_6,mluOp_5,mluOp_4}; // @[Decode.scala 279:22]
- wire dvuValid_value__0 = io_dvu_op[0] | io_dvu_op[1]; // @[Library.scala 208:39]
- wire dvuValid_value__1 = io_dvu_op[2] | io_dvu_op[3]; // @[Library.scala 208:39]
- wire dvuValid_value_1_0 = dvuValid_value__0 | dvuValid_value__1; // @[Library.scala 208:39]
- wire dvuEn = ~dvuValid_value_1_0; // @[Decode.scala 304:34]
- wire vinstOp_0 = d_io_getvl; // @[Decode.scala 308:21 319:24]
- wire vinstOp_1 = d_io_getmaxvl; // @[Decode.scala 308:21 320:27]
- wire vinstValid_value__0 = vinstOp_0 | vinstOp_1; // @[Library.scala 208:39]
- wire vinstOp_2 = d_io_vld; // @[Decode.scala 308:21 316:22]
- wire vinstOp_3 = d_io_vst; // @[Decode.scala 308:21 317:22]
- wire vinstValid_value__1 = vinstOp_2 | vinstOp_3; // @[Library.scala 208:39]
- wire vinstValid_value_1_0 = vinstValid_value__0 | vinstValid_value__1; // @[Library.scala 208:39]
- wire vinstOp_4 = d_io_viop; // @[Decode.scala 308:21 318:23]
- wire vinstValid_value_2_0 = vinstValid_value_1_0 | vinstOp_4; // @[Library.scala 208:39]
- wire [1:0] io_vinst_op_lo = {vinstOp_1,vinstOp_0}; // @[Decode.scala 314:26]
- wire [2:0] io_vinst_op_hi = {vinstOp_4,vinstOp_3,vinstOp_2}; // @[Decode.scala 314:26]
- wire _io_rs1Read_valid_T = isCondBr | isAluReg; // @[Decode.scala 326:45]
- wire _io_rs1Read_valid_T_3 = isCondBr | isAluReg | isAluImm | isAlu1Bit | isAlu2Bit; // @[Decode.scala 326:82]
- wire _io_rs1Read_valid_T_9 = _io_rs1Read_valid_T_3 | isMul | d_io_getvl; // @[Decode.scala 327:75]
- wire _io_rs1Read_valid_T_11 = _io_rs1Read_valid_T_9 | d_io_vld | d_io_vst; // @[Decode.scala 328:46]
- wire _io_rs2Read_valid_T_2 = _io_rs1Read_valid_T | isAlu2Bit | isStore; // @[Decode.scala 329:70]
- wire _io_rs2Read_valid_T_8 = _io_rs2Read_valid_T_2 | isMul | d_io_getvl | d_io_vld; // @[Decode.scala 330:77]
- wire _io_rs2Read_valid_T_10 = _io_rs2Read_valid_T_8 | d_io_vst | d_io_viop; // @[Decode.scala 331:44]
- wire _io_rs2Set_value_T = d_io_auipc | d_io_lui; // @[Decode.scala 346:45]
- wire _rdMark_valid_T_4 = lsuValid_value_3_0 & isLoad; // @[Decode.scala 352:16]
- wire _rdMark_valid_T_5 = aluValid_value_4_0 | csrValid_value_1_0 | mluValid_value_3_0 | _rdMark_valid_T_4; // @[Decode.scala 351:68]
- wire _rdMark_valid_T_6 = _rdMark_valid_T_5 | d_io_getvl; // @[Decode.scala 352:26]
- wire _rdMark_valid_T_12 = bruValid_value_4_0 & (bruOp_0 | bruOp_1) & rdAddr != 5'h0; // @[Decode.scala 354:55]
- wire rdMark_valid = _rdMark_valid_T_6 | d_io_getmaxvl | vldst_wb | _rdMark_valid_T_12; // @[Decode.scala 353:47]
- wire [31:0] _scoreboard_spec_T = 32'h1 << rdAddr; // @[OneHot.scala 64:12]
- wire [31:0] scoreboard_spec = rdMark_valid ? _scoreboard_spec_T : 32'h0; // @[Decode.scala 357:28]
- wire _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 369:65]
- wire _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 368:8]
- wire storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 372:47]
- wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 375:30]
- wire _io_inst_ready_T_6 = ~io_serializeIn_jump; // @[Decode.scala 381:20]
- wire _io_inst_ready_T_7 = aluEn & bruEn & lsuEn & mulEn & dvuEn & vinstEn & _io_inst_ready_T_6; // @[Decode.scala 380:84]
- wire _io_inst_ready_T_13 = ~d_io_undef; // @[Decode.scala 382:43]
- wire _io_serializeOut_brcond_T = io_serializeIn_brcond | d_io_beq; // @[Decode.scala 392:51]
- DecodedInstruction_1 d ( // @[Decode.scala 107:17]
- .clock(d_clock),
- .reset(d_reset),
- .io_addr(d_io_addr),
- .io_inst(d_io_inst),
- .io_imm12(d_io_imm12),
- .io_imm20(d_io_imm20),
- .io_immjal(d_io_immjal),
- .io_immbr(d_io_immbr),
- .io_immst(d_io_immst),
- .io_lui(d_io_lui),
- .io_auipc(d_io_auipc),
- .io_jal(d_io_jal),
- .io_jalr(d_io_jalr),
- .io_beq(d_io_beq),
- .io_bne(d_io_bne),
- .io_blt(d_io_blt),
- .io_bge(d_io_bge),
- .io_bltu(d_io_bltu),
- .io_bgeu(d_io_bgeu),
- .io_csrrw(d_io_csrrw),
- .io_csrrs(d_io_csrrs),
- .io_csrrc(d_io_csrrc),
- .io_lb(d_io_lb),
- .io_lh(d_io_lh),
- .io_lw(d_io_lw),
- .io_lbu(d_io_lbu),
- .io_lhu(d_io_lhu),
- .io_sb(d_io_sb),
- .io_sh(d_io_sh),
- .io_sw(d_io_sw),
- .io_fence(d_io_fence),
- .io_addi(d_io_addi),
- .io_slti(d_io_slti),
- .io_sltiu(d_io_sltiu),
- .io_xori(d_io_xori),
- .io_ori(d_io_ori),
- .io_andi(d_io_andi),
- .io_slli(d_io_slli),
- .io_srli(d_io_srli),
- .io_srai(d_io_srai),
- .io_add(d_io_add),
- .io_sub(d_io_sub),
- .io_slt(d_io_slt),
- .io_sltu(d_io_sltu),
- .io_xor(d_io_xor),
- .io_or(d_io_or),
- .io_and(d_io_and),
- .io_sll(d_io_sll),
- .io_srl(d_io_srl),
- .io_sra(d_io_sra),
- .io_mul(d_io_mul),
- .io_mulh(d_io_mulh),
- .io_mulhsu(d_io_mulhsu),
- .io_mulhu(d_io_mulhu),
- .io_mulhr(d_io_mulhr),
- .io_mulhsur(d_io_mulhsur),
- .io_mulhur(d_io_mulhur),
- .io_dmulh(d_io_dmulh),
- .io_dmulhr(d_io_dmulhr),
- .io_div(d_io_div),
- .io_divu(d_io_divu),
- .io_rem(d_io_rem),
- .io_remu(d_io_remu),
- .io_clz(d_io_clz),
- .io_ctz(d_io_ctz),
- .io_pcnt(d_io_pcnt),
- .io_min(d_io_min),
- .io_minu(d_io_minu),
- .io_max(d_io_max),
- .io_maxu(d_io_maxu),
- .io_getvl(d_io_getvl),
- .io_getmaxvl(d_io_getmaxvl),
- .io_vld(d_io_vld),
- .io_vst(d_io_vst),
- .io_viop(d_io_viop),
- .io_ebreak(d_io_ebreak),
- .io_ecall(d_io_ecall),
- .io_eexit(d_io_eexit),
- .io_eyield(d_io_eyield),
- .io_ectxsw(d_io_ectxsw),
- .io_mpause(d_io_mpause),
- .io_mret(d_io_mret),
- .io_undef(d_io_undef),
- .io_fencei(d_io_fencei),
- .io_flushat(d_io_flushat),
- .io_flushall(d_io_flushall),
- .io_slog(d_io_slog)
- );
- assign io_inst_ready = _io_inst_ready_T_7 & ~io_halted & ~io_interlock & _io_inst_ready_T_13; // @[Decode.scala 381:72]
- assign io_scoreboard_spec = {scoreboard_spec[31:1],1'h0}; // @[Cat.scala 31:58]
- assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_11; // @[Decode.scala 326:32]
- assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 334:25]
- assign io_rs1Set_valid = decodeEn & d_io_auipc; // @[Decode.scala 340:31]
- assign io_rs1Set_value = io_inst_addr; // @[Decode.scala 343:25]
- assign io_rs2Read_valid = decodeEn & _io_rs2Read_valid_T_10; // @[Decode.scala 329:32]
- assign io_rs2Read_addr = io_inst_inst[24:20]; // @[Decode.scala 116:29]
- assign io_rs2Set_valid = io_rs1Set_valid | decodeEn & (isAluImm | isAlu1Bit | d_io_lui); // @[Decode.scala 341:38]
- assign io_rs2Set_value = _io_rs2Set_value_T ? d_io_imm20 : d_io_imm12; // @[Mux.scala 101:16]
- assign io_rdMark_valid = decodeEn & rdMark_valid; // @[Decode.scala 360:31]
- assign io_rdMark_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_busRead_bypass = io_inst_inst[31:25] == 7'h0 & _io_busRead_bypass_T_10; // @[Decode.scala 367:52]
- assign io_busRead_immed = {d_io_imm12[31:5],_io_busRead_immed_T_3}; // @[Cat.scala 31:58]
- assign io_alu_valid = decodeEn & aluValid_value_4_0; // @[Decode.scala 185:28]
- assign io_alu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_alu_op = {io_alu_op_hi,io_alu_op_lo}; // @[Decode.scala 187:22]
- assign io_bru_valid = decodeEn & bruValid_value_4_0; // @[Decode.scala 212:28]
- assign io_bru_fwd = io_inst_brchFwd; // @[Decode.scala 213:14]
- assign io_bru_op = {io_bru_op_hi,io_bru_op_lo}; // @[Decode.scala 214:22]
- assign io_bru_pc = io_inst_addr; // @[Decode.scala 215:13]
- assign io_bru_target = io_inst_addr + _io_bru_target_T_1; // @[Decode.scala 216:33]
- assign io_bru_link = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_csr_op = 3'h0; // @[Decode.scala 244:22]
- assign io_lsu_valid = decodeEn & lsuValid_value_3_0; // @[Decode.scala 254:28]
- assign io_lsu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_lsu_op = {io_lsu_op_hi,io_lsu_op_lo}; // @[Decode.scala 257:22]
- assign io_mlu_valid = decodeEn & mluValid_value_3_0; // @[Decode.scala 277:28]
- assign io_mlu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_mlu_op = {io_mlu_op_hi,io_mlu_op_lo}; // @[Decode.scala 279:22]
- assign io_dvu_op = 4'h0; // @[Decode.scala 297:22]
- assign io_vinst_valid = decodeEn & vinstValid_value_2_0; // @[Decode.scala 311:30]
- assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_vinst_inst = io_inst_inst; // @[Decode.scala 313:17]
- assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 314:26]
- assign io_serializeOut_mul = io_serializeIn_mul | mluValid_value_3_0; // @[Decode.scala 388:46]
- assign io_serializeOut_jump = io_serializeIn_jump | d_io_jal | d_io_jalr; // @[Decode.scala 389:59]
- assign io_serializeOut_brcond = _io_serializeOut_brcond_T | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 393:65]
- assign d_clock = clock;
- assign d_reset = reset;
- assign d_io_addr = io_inst_addr; // @[Decode.scala 108:13]
- assign d_io_inst = io_inst_inst; // @[Decode.scala 109:13]
-endmodule
-module DecodedInstruction_2(
- input clock,
- input reset,
- input [31:0] io_addr,
- input [31:0] io_inst,
- output [31:0] io_imm12,
- output [31:0] io_imm20,
- output [31:0] io_immjal,
- output [31:0] io_immbr,
- output [31:0] io_immst,
- output io_lui,
- output io_auipc,
- output io_jal,
- output io_jalr,
- output io_beq,
- output io_bne,
- output io_blt,
- output io_bge,
- output io_bltu,
- output io_bgeu,
- output io_csrrw,
- output io_csrrs,
- output io_csrrc,
- output io_lb,
- output io_lh,
- output io_lw,
- output io_lbu,
- output io_lhu,
- output io_sb,
- output io_sh,
- output io_sw,
- output io_fence,
- output io_addi,
- output io_slti,
- output io_sltiu,
- output io_xori,
- output io_ori,
- output io_andi,
- output io_slli,
- output io_srli,
- output io_srai,
- output io_add,
- output io_sub,
- output io_slt,
- output io_sltu,
- output io_xor,
- output io_or,
- output io_and,
- output io_sll,
- output io_srl,
- output io_sra,
- output io_mul,
- output io_mulh,
- output io_mulhsu,
- output io_mulhu,
- output io_mulhr,
- output io_mulhsur,
- output io_mulhur,
- output io_dmulh,
- output io_dmulhr,
- output io_div,
- output io_divu,
- output io_rem,
- output io_remu,
- output io_clz,
- output io_ctz,
- output io_pcnt,
- output io_min,
- output io_minu,
- output io_max,
- output io_maxu,
- output io_getvl,
- output io_getmaxvl,
- output io_vld,
- output io_vst,
- output io_viop,
- output io_ebreak,
- output io_ecall,
- output io_eexit,
- output io_eyield,
- output io_ectxsw,
- output io_mpause,
- output io_mret,
- output io_undef,
- output io_fencei,
- output io_flushat,
- output io_flushall,
- output io_slog
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
-`endif // RANDOMIZE_REG_INIT
- wire [19:0] _io_imm12_T_2 = io_inst[31] ? 20'hfffff : 20'h0; // @[Bitwise.scala 74:12]
- wire [11:0] _io_immjal_T_2 = io_inst[31] ? 12'hfff : 12'h0; // @[Bitwise.scala 74:12]
- wire [10:0] io_immjal_lo = {io_inst[30:21],1'h0}; // @[Cat.scala 31:58]
- wire [20:0] io_immjal_hi = {_io_immjal_T_2,io_inst[19:12],io_inst[20]}; // @[Cat.scala 31:58]
- wire [4:0] io_immbr_lo = {io_inst[11:8],1'h0}; // @[Cat.scala 31:58]
- wire [26:0] io_immbr_hi = {_io_imm12_T_2,io_inst[7],io_inst[30:25]}; // @[Cat.scala 31:58]
- wire [26:0] io_immst_hi = {_io_imm12_T_2,io_inst[31:25]}; // @[Cat.scala 31:58]
- wire io_lui_bit_1 = io_inst[30]; // @[Library.scala 332:23]
- wire io_lui_bit_2 = io_inst[29]; // @[Library.scala 332:23]
- wire io_lui_bit_3 = io_inst[28]; // @[Library.scala 332:23]
- wire io_lui_bit_4 = io_inst[27]; // @[Library.scala 332:23]
- wire io_lui_bit_5 = io_inst[26]; // @[Library.scala 332:23]
- wire io_lui_bit_6 = io_inst[25]; // @[Library.scala 332:23]
- wire io_lui_bit_7 = io_inst[24]; // @[Library.scala 332:23]
- wire io_lui_bit_8 = io_inst[23]; // @[Library.scala 332:23]
- wire io_lui_bit_9 = io_inst[22]; // @[Library.scala 332:23]
- wire io_lui_bit_10 = io_inst[21]; // @[Library.scala 332:23]
- wire io_lui_bit_12 = io_inst[19]; // @[Library.scala 332:23]
- wire io_lui_bit_13 = io_inst[18]; // @[Library.scala 332:23]
- wire io_lui_bit_14 = io_inst[17]; // @[Library.scala 332:23]
- wire io_lui_bit_15 = io_inst[16]; // @[Library.scala 332:23]
- wire io_lui_bit_16 = io_inst[15]; // @[Library.scala 332:23]
- wire io_lui_bit_17 = io_inst[14]; // @[Library.scala 332:23]
- wire io_lui_bit_18 = io_inst[13]; // @[Library.scala 332:23]
- wire io_lui_bit_19 = io_inst[12]; // @[Library.scala 332:23]
- wire io_lui_bit_25 = ~io_inst[6]; // @[Library.scala 326:19]
- wire io_lui_bit_26 = io_inst[5]; // @[Library.scala 329:23]
- wire io_lui_bit_27 = io_inst[4]; // @[Library.scala 329:23]
- wire _io_lui_T_2 = io_lui_bit_25 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire io_lui_bit_28 = ~io_inst[3]; // @[Library.scala 326:19]
- wire _io_lui_T_3 = _io_lui_T_2 & io_lui_bit_28; // @[Library.scala 327:48]
- wire io_lui_bit_29 = io_inst[2]; // @[Library.scala 329:23]
- wire io_lui_bit_30 = io_inst[1]; // @[Library.scala 329:23]
- wire io_lui_bit_31 = io_inst[0]; // @[Library.scala 329:23]
- wire io_auipc_bit_26 = ~io_lui_bit_26; // @[Library.scala 326:19]
- wire _io_auipc_T_1 = io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_auipc_T_2 = _io_auipc_T_1 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_auipc_T_3 = _io_auipc_T_2 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_jal_T_1 = io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire io_jal_bit_27 = ~io_lui_bit_27; // @[Library.scala 326:19]
- wire _io_jal_T_2 = _io_jal_T_1 & io_jal_bit_27; // @[Library.scala 327:48]
- wire io_jalr_bit_17 = ~io_lui_bit_17; // @[Library.scala 326:19]
- wire io_jalr_bit_18 = ~io_lui_bit_18; // @[Library.scala 326:19]
- wire _io_jalr_T_1 = io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire io_jalr_bit_19 = ~io_lui_bit_19; // @[Library.scala 326:19]
- wire _io_jalr_T_2 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_jalr_T_4 = _io_jalr_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_jalr_T_6 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 327:48]
- wire io_beq_bit_29 = ~io_lui_bit_29; // @[Library.scala 326:19]
- wire _io_beq_T_7 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bne_T_2 = _io_jalr_T_1 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_bne_T_4 = _io_jalr_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bne_T_7 = _io_bne_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_blt_T_1 = io_lui_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_blt_T_2 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_blt_T_4 = _io_blt_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_blt_T_7 = _io_blt_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bge_T_2 = _io_blt_T_1 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_bge_T_4 = _io_blt_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bge_T_7 = _io_bge_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bltu_T_1 = io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_bltu_T_2 = _io_bltu_T_1 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_bltu_T_4 = _io_bltu_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bltu_T_7 = _io_bltu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bgeu_T_2 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_bgeu_T_4 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bgeu_T_7 = _io_bgeu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lb_T_3 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_lb_T_4 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_lb_T_7 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
- & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lh_T_3 = _io_bne_T_2 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_lh_T_7 = _io_bne_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lw_T_1 = io_jalr_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_lw_T_3 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_lw_T_4 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_lw_T_7 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 &
- io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lbu_T_4 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_lbu_T_7 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
- & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lhu_T_7 = _io_bge_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sb_T_4 = _io_lb_T_3 & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_sb_T_7 = _io_sb_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sh_T_4 = _io_lh_T_3 & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_sh_T_7 = _io_sh_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sw_T_4 = _io_lw_T_3 & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_sw_T_7 = _io_sw_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire io_fence_bit = ~io_inst[31]; // @[Library.scala 326:19]
- wire io_fence_bit_1 = ~io_lui_bit_1; // @[Library.scala 326:19]
- wire _io_fence_T_1 = io_fence_bit & io_fence_bit_1; // @[Library.scala 327:48]
- wire io_fence_bit_2 = ~io_lui_bit_2; // @[Library.scala 326:19]
- wire _io_fence_T_2 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2; // @[Library.scala 327:48]
- wire io_fence_bit_3 = ~io_lui_bit_3; // @[Library.scala 326:19]
- wire _io_fence_T_3 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3; // @[Library.scala 327:48]
- wire io_fence_bit_12 = ~io_lui_bit_12; // @[Library.scala 326:19]
- wire io_fence_bit_13 = ~io_lui_bit_13; // @[Library.scala 326:19]
- wire io_fence_bit_14 = ~io_lui_bit_14; // @[Library.scala 326:19]
- wire io_fence_bit_15 = ~io_lui_bit_15; // @[Library.scala 326:19]
- wire io_fence_bit_16 = ~io_lui_bit_16; // @[Library.scala 326:19]
- wire _io_addi_T_5 = _io_lb_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_addi_T_7 = _io_addi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_slti_T_5 = _io_lw_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_slti_T_7 = _io_slti_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sltiu_T_2 = io_jalr_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_sltiu_T_4 = _io_sltiu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_sltiu_T_5 = _io_sltiu_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sltiu_T_7 = _io_sltiu_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_xori_T_5 = _io_lbu_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_xori_T_7 = _io_xori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_ori_T_4 = _io_bltu_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_ori_T_5 = _io_ori_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_ori_T_7 = _io_ori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_andi_T_4 = _io_bgeu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_andi_T_5 = _io_andi_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_andi_T_7 = _io_andi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire io_slli_bit_4 = ~io_lui_bit_4; // @[Library.scala 326:19]
- wire _io_slli_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 327:48]
- wire io_slli_bit_5 = ~io_lui_bit_5; // @[Library.scala 326:19]
- wire _io_slli_T_5 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 327:48]
- wire io_slli_bit_6 = ~io_lui_bit_6; // @[Library.scala 326:19]
- wire _io_slli_T_6 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6; // @[Library.scala 327:48]
- wire _io_slli_T_7 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_slli_T_8 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_slli_T_9 = _io_slli_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_slli_T_10 = _io_slli_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_slli_T_11 = _io_slli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_slli_T_12 = _io_slli_T_11 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_slli_T_14 = _io_slli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_srli_T_7 = _io_slli_T_6 & io_lui_bit_17; // @[Library.scala 330:48]
- wire _io_srli_T_8 = _io_srli_T_7 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_srli_T_9 = _io_srli_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_srli_T_10 = _io_srli_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_srli_T_11 = _io_srli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_srli_T_12 = _io_srli_T_11 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_srli_T_14 = _io_srli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_srai_T_1 = io_fence_bit & io_lui_bit_1; // @[Library.scala 330:48]
- wire _io_srai_T_2 = _io_srai_T_1 & io_fence_bit_2; // @[Library.scala 327:48]
- wire _io_srai_T_6 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 327:48]
- wire _io_srai_T_7 = _io_srai_T_6 & io_lui_bit_17; // @[Library.scala 330:48]
- wire _io_srai_T_8 = _io_srai_T_7 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_srai_T_9 = _io_srai_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_srai_T_10 = _io_srai_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_srai_T_11 = _io_srai_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_srai_T_12 = _io_srai_T_11 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_srai_T_14 = _io_srai_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_add_T_10 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_add_T_12 = _io_add_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_add_T_14 = _io_add_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sub_T_10 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 &
- io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_sub_T_12 = _io_sub_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sub_T_14 = _io_sub_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_slt_T_8 = _io_slli_T_7 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_slt_T_10 = _io_slt_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_slt_T_12 = _io_slt_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_slt_T_14 = _io_slt_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sltu_T_9 = _io_slli_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_sltu_T_10 = _io_sltu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_sltu_T_12 = _io_sltu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sltu_T_14 = _io_sltu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_xor_T_10 = _io_srli_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_xor_T_12 = _io_xor_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_xor_T_14 = _io_xor_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_or_T_8 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_or_T_10 = _io_or_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_or_T_12 = _io_or_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_or_T_14 = _io_or_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_and_T_9 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_and_T_10 = _io_and_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_and_T_12 = _io_and_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_and_T_14 = _io_and_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sll_T_12 = _io_slli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sll_T_14 = _io_sll_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_srl_T_12 = _io_srli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_srl_T_14 = _io_srl_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sra_T_12 = _io_srai_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sra_T_14 = _io_sra_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mul_T_6 = _io_slli_T_5 & io_lui_bit_6; // @[Library.scala 330:48]
- wire _io_mul_T_7 = _io_mul_T_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_mul_T_8 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_mul_T_10 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mul_T_12 = _io_mul_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mul_T_14 = _io_mul_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulh_T_9 = _io_mul_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulh_T_10 = _io_mulh_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulh_T_12 = _io_mulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulh_T_14 = _io_mulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhsu_T_8 = _io_mul_T_7 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_mulhsu_T_10 = _io_mulhsu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhsu_T_12 = _io_mulhsu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhsu_T_14 = _io_mulhsu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhu_T_9 = _io_mul_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulhu_T_10 = _io_mulhu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhu_T_12 = _io_mulhu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhu_T_14 = _io_mulhu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhr_T_2 = _io_fence_T_1 & io_lui_bit_2; // @[Library.scala 330:48]
- wire _io_mulhr_T_4 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 327:48]
- wire _io_mulhr_T_5 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 327:48]
- wire _io_mulhr_T_6 = _io_mulhr_T_5 & io_lui_bit_6; // @[Library.scala 330:48]
- wire _io_mulhr_T_7 = _io_mulhr_T_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_mulhr_T_8 = _io_mulhr_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_mulhr_T_9 = _io_mulhr_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulhr_T_10 = _io_mulhr_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhr_T_12 = _io_mulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhr_T_14 = _io_mulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhsur_T_8 = _io_mulhr_T_7 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_mulhsur_T_10 = _io_mulhsur_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhsur_T_12 = _io_mulhsur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhsur_T_14 = _io_mulhsur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhur_T_9 = _io_mulhr_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulhur_T_10 = _io_mulhur_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhur_T_12 = _io_mulhur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhur_T_14 = _io_mulhur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_dmulh_T_5 = _io_slli_T_4 & io_lui_bit_5; // @[Library.scala 330:48]
- wire _io_dmulh_T_8 = _io_dmulh_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_dmulh_T_9 = _io_dmulh_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_dmulh_T_10 = _io_dmulh_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_dmulh_T_12 = _io_dmulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_dmulh_T_14 = _io_dmulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_dmulhr_T_5 = _io_mulhr_T_4 & io_lui_bit_5; // @[Library.scala 330:48]
- wire _io_dmulhr_T_8 = _io_dmulhr_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_dmulhr_T_9 = _io_dmulhr_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_dmulhr_T_10 = _io_dmulhr_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_dmulhr_T_12 = _io_dmulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_dmulhr_T_14 = _io_dmulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_clz_T_2 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2; // @[Library.scala 330:48]
- wire io_clz_bit_7 = ~io_lui_bit_7; // @[Library.scala 326:19]
- wire io_clz_bit_8 = ~io_lui_bit_8; // @[Library.scala 326:19]
- wire io_clz_bit_9 = ~io_lui_bit_9; // @[Library.scala 326:19]
- wire _io_clz_T_9 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
- io_clz_bit_8 & io_clz_bit_9; // @[Library.scala 327:48]
- wire io_clz_bit_10 = ~io_lui_bit_10; // @[Library.scala 326:19]
- wire _io_clz_T_10 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
- io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10; // @[Library.scala 327:48]
- wire io_clz_bit_11 = ~io_inst[20]; // @[Library.scala 326:19]
- wire _io_clz_T_13 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
- io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_clz_T_14 = _io_clz_T_13 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_clz_T_16 = _io_clz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_clz_T_17 = _io_clz_T_16 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_clz_T_19 = _io_clz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_ctz_T_11 = _io_clz_T_10 & io_inst[20]; // @[Library.scala 330:48]
- wire _io_ctz_T_13 = _io_ctz_T_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_ctz_T_14 = _io_ctz_T_13 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_ctz_T_16 = _io_ctz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_ctz_T_17 = _io_ctz_T_16 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_ctz_T_19 = _io_ctz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_pcnt_T_10 = _io_clz_T_9 & io_lui_bit_10; // @[Library.scala 330:48]
- wire _io_pcnt_T_13 = _io_pcnt_T_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_pcnt_T_14 = _io_pcnt_T_13 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_pcnt_T_16 = _io_pcnt_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_pcnt_T_17 = _io_pcnt_T_16 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_pcnt_T_19 = _io_pcnt_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_min_T_4 = _io_fence_T_3 & io_lui_bit_4; // @[Library.scala 330:48]
- wire _io_min_T_5 = _io_min_T_4 & io_slli_bit_5; // @[Library.scala 327:48]
- wire _io_min_T_7 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 330:48]
- wire _io_min_T_8 = _io_min_T_7 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_min_T_10 = _io_min_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_min_T_12 = _io_min_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_min_T_14 = _io_min_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_minu_T_9 = _io_min_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_minu_T_10 = _io_minu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_minu_T_12 = _io_minu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_minu_T_14 = _io_minu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_max_T_8 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_max_T_10 = _io_max_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_max_T_12 = _io_max_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_max_T_14 = _io_max_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_maxu_T_9 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_maxu_T_10 = _io_maxu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_maxu_T_12 = _io_maxu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_maxu_T_14 = _io_maxu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_getvl_T_3 = _io_fence_T_2 & io_lui_bit_3; // @[Library.scala 330:48]
- wire _io_getvl_T_6 = _io_getvl_T_3 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 584:89]
- wire _io_getmaxvl_T_16 = _io_getvl_T_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11
- & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 &
- io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_getmaxvl_T_19 = _io_getmaxvl_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_getmaxvl_T_20 = _io_getmaxvl_T_19 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_getmaxvl_T_23 = _io_getmaxvl_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _io_vld_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_vst_T_4 = _io_mulhr_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_vst_T_9 = _io_vst_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _io_vst_T_14 = _io_clz_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_vst_T_19 = _io_vst_T_14 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _vconv_T_3 = _io_srai_T_2 & io_lui_bit_3; // @[Library.scala 330:48]
- wire _vconv_T_17 = _vconv_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 &
- io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15
- & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire vconv = _vconv_T_17 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _vdup_T_11 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_6 & io_fence_bit_12 &
- io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 597:72]
- wire vdupi = vdup & io_slli_bit_5; // @[Decode.scala 598:20]
- wire _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 602:22]
- wire _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 601:28]
- wire _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 602:30]
- wire [9:0] decoded_lo_lo_hi = {io_minu,io_max,io_maxu,io_viop,io_vld,io_vst,io_getvl,io_getmaxvl,io_ebreak,io_ecall}; // @[Cat.scala 31:58]
- wire [18:0] decoded_lo_lo = {decoded_lo_lo_hi,io_eexit,io_eyield,io_ectxsw,io_mpause,io_mret,io_fencei,io_flushat,
- io_flushall,io_slog}; // @[Cat.scala 31:58]
- wire [9:0] decoded_lo_hi_hi = {io_srl,io_sra,io_mul,io_mulh,io_mulhsu,io_mulhu,io_mulhr,io_mulhsur,io_mulhur,io_dmulh}
- ; // @[Cat.scala 31:58]
- wire [18:0] decoded_lo_hi = {decoded_lo_hi_hi,io_dmulhr,io_div,io_divu,io_rem,io_remu,io_clz,io_ctz,io_pcnt,io_min}; // @[Cat.scala 31:58]
- wire [9:0] decoded_hi_lo_hi = {io_sw,io_fence,io_addi,io_slti,io_sltiu,io_xori,io_ori,io_andi,io_add,io_sub}; // @[Cat.scala 31:58]
- wire [18:0] decoded_hi_lo = {decoded_hi_lo_hi,io_slt,io_sltu,io_xor,io_or,io_and,io_slli,io_srli,io_srai,io_sll}; // @[Cat.scala 31:58]
- wire [9:0] decoded_hi_hi_lo = {io_csrrw,io_csrrs,io_csrrc,io_lb,io_lh,io_lw,io_lbu,io_lhu,io_sb,io_sh}; // @[Cat.scala 31:58]
- wire [9:0] decoded_hi_hi_hi = {io_lui,io_auipc,io_jal,io_jalr,io_beq,io_bne,io_blt,io_bge,io_bltu,io_bgeu}; // @[Cat.scala 31:58]
- wire [76:0] decoded = {decoded_hi_hi_hi,decoded_hi_hi_lo,decoded_hi_lo,decoded_lo_hi,decoded_lo_lo}; // @[Cat.scala 31:58]
- wire io_undef_value__38 = decoded[76]; // @[Library.scala 196:26]
- wire io_undef_value__0 = decoded[0] | decoded[1]; // @[Library.scala 208:39]
- wire io_undef_value__1 = decoded[2] | decoded[3]; // @[Library.scala 208:39]
- wire io_undef_value__2 = decoded[4] | decoded[5]; // @[Library.scala 208:39]
- wire io_undef_value__3 = decoded[6] | decoded[7]; // @[Library.scala 208:39]
- wire io_undef_value__4 = decoded[8] | decoded[9]; // @[Library.scala 208:39]
- wire io_undef_value__5 = decoded[10] | decoded[11]; // @[Library.scala 208:39]
- wire io_undef_value__6 = decoded[12] | decoded[13]; // @[Library.scala 208:39]
- wire io_undef_value__7 = decoded[14] | decoded[15]; // @[Library.scala 208:39]
- wire io_undef_value__8 = decoded[16] | decoded[17]; // @[Library.scala 208:39]
- wire io_undef_value__9 = decoded[18] | decoded[19]; // @[Library.scala 208:39]
- wire io_undef_value__10 = decoded[20] | decoded[21]; // @[Library.scala 208:39]
- wire io_undef_value__11 = decoded[22] | decoded[23]; // @[Library.scala 208:39]
- wire io_undef_value__12 = decoded[24] | decoded[25]; // @[Library.scala 208:39]
- wire io_undef_value__13 = decoded[26] | decoded[27]; // @[Library.scala 208:39]
- wire io_undef_value__14 = decoded[28] | decoded[29]; // @[Library.scala 208:39]
- wire io_undef_value__15 = decoded[30] | decoded[31]; // @[Library.scala 208:39]
- wire io_undef_value__16 = decoded[32] | decoded[33]; // @[Library.scala 208:39]
- wire io_undef_value__17 = decoded[34] | decoded[35]; // @[Library.scala 208:39]
- wire io_undef_value__18 = decoded[36] | decoded[37]; // @[Library.scala 208:39]
- wire io_undef_value__19 = decoded[38] | decoded[39]; // @[Library.scala 208:39]
- wire io_undef_value__20 = decoded[40] | decoded[41]; // @[Library.scala 208:39]
- wire io_undef_value__21 = decoded[42] | decoded[43]; // @[Library.scala 208:39]
- wire io_undef_value__22 = decoded[44] | decoded[45]; // @[Library.scala 208:39]
- wire io_undef_value__23 = decoded[46] | decoded[47]; // @[Library.scala 208:39]
- wire io_undef_value__24 = decoded[48] | decoded[49]; // @[Library.scala 208:39]
- wire io_undef_value__25 = decoded[50] | decoded[51]; // @[Library.scala 208:39]
- wire io_undef_value__26 = decoded[52] | decoded[53]; // @[Library.scala 208:39]
- wire io_undef_value__27 = decoded[54] | decoded[55]; // @[Library.scala 208:39]
- wire io_undef_value__28 = decoded[56] | decoded[57]; // @[Library.scala 208:39]
- wire io_undef_value__29 = decoded[58] | decoded[59]; // @[Library.scala 208:39]
- wire io_undef_value__30 = decoded[60] | decoded[61]; // @[Library.scala 208:39]
- wire io_undef_value__31 = decoded[62] | decoded[63]; // @[Library.scala 208:39]
- wire io_undef_value__32 = decoded[64] | decoded[65]; // @[Library.scala 208:39]
- wire io_undef_value__33 = decoded[66] | decoded[67]; // @[Library.scala 208:39]
- wire io_undef_value__34 = decoded[68] | decoded[69]; // @[Library.scala 208:39]
- wire io_undef_value__35 = decoded[70] | decoded[71]; // @[Library.scala 208:39]
- wire io_undef_value__36 = decoded[72] | decoded[73]; // @[Library.scala 208:39]
- wire io_undef_value__37 = decoded[74] | decoded[75]; // @[Library.scala 208:39]
- wire io_undef_value_1_0 = io_undef_value__0 | io_undef_value__1; // @[Library.scala 208:39]
- wire io_undef_value_1_1 = io_undef_value__2 | io_undef_value__3; // @[Library.scala 208:39]
- wire io_undef_value_1_2 = io_undef_value__4 | io_undef_value__5; // @[Library.scala 208:39]
- wire io_undef_value_1_3 = io_undef_value__6 | io_undef_value__7; // @[Library.scala 208:39]
- wire io_undef_value_1_4 = io_undef_value__8 | io_undef_value__9; // @[Library.scala 208:39]
- wire io_undef_value_1_5 = io_undef_value__10 | io_undef_value__11; // @[Library.scala 208:39]
- wire io_undef_value_1_6 = io_undef_value__12 | io_undef_value__13; // @[Library.scala 208:39]
- wire io_undef_value_1_7 = io_undef_value__14 | io_undef_value__15; // @[Library.scala 208:39]
- wire io_undef_value_1_8 = io_undef_value__16 | io_undef_value__17; // @[Library.scala 208:39]
- wire io_undef_value_1_9 = io_undef_value__18 | io_undef_value__19; // @[Library.scala 208:39]
- wire io_undef_value_1_10 = io_undef_value__20 | io_undef_value__21; // @[Library.scala 208:39]
- wire io_undef_value_1_11 = io_undef_value__22 | io_undef_value__23; // @[Library.scala 208:39]
- wire io_undef_value_1_12 = io_undef_value__24 | io_undef_value__25; // @[Library.scala 208:39]
- wire io_undef_value_1_13 = io_undef_value__26 | io_undef_value__27; // @[Library.scala 208:39]
- wire io_undef_value_1_14 = io_undef_value__28 | io_undef_value__29; // @[Library.scala 208:39]
- wire io_undef_value_1_15 = io_undef_value__30 | io_undef_value__31; // @[Library.scala 208:39]
- wire io_undef_value_1_16 = io_undef_value__32 | io_undef_value__33; // @[Library.scala 208:39]
- wire io_undef_value_1_17 = io_undef_value__34 | io_undef_value__35; // @[Library.scala 208:39]
- wire io_undef_value_1_18 = io_undef_value__36 | io_undef_value__37; // @[Library.scala 208:39]
- wire io_undef_value_2_0 = io_undef_value_1_0 | io_undef_value_1_1; // @[Library.scala 208:39]
- wire io_undef_value_2_1 = io_undef_value_1_2 | io_undef_value_1_3; // @[Library.scala 208:39]
- wire io_undef_value_2_2 = io_undef_value_1_4 | io_undef_value_1_5; // @[Library.scala 208:39]
- wire io_undef_value_2_3 = io_undef_value_1_6 | io_undef_value_1_7; // @[Library.scala 208:39]
- wire io_undef_value_2_4 = io_undef_value_1_8 | io_undef_value_1_9; // @[Library.scala 208:39]
- wire io_undef_value_2_5 = io_undef_value_1_10 | io_undef_value_1_11; // @[Library.scala 208:39]
- wire io_undef_value_2_6 = io_undef_value_1_12 | io_undef_value_1_13; // @[Library.scala 208:39]
- wire io_undef_value_2_7 = io_undef_value_1_14 | io_undef_value_1_15; // @[Library.scala 208:39]
- wire io_undef_value_2_8 = io_undef_value_1_16 | io_undef_value_1_17; // @[Library.scala 208:39]
- wire io_undef_value_2_9 = io_undef_value_1_18 | io_undef_value__38; // @[Library.scala 208:39]
- wire io_undef_value_3_0 = io_undef_value_2_0 | io_undef_value_2_1; // @[Library.scala 208:39]
- wire io_undef_value_3_1 = io_undef_value_2_2 | io_undef_value_2_3; // @[Library.scala 208:39]
- wire io_undef_value_3_2 = io_undef_value_2_4 | io_undef_value_2_5; // @[Library.scala 208:39]
- wire io_undef_value_3_3 = io_undef_value_2_6 | io_undef_value_2_7; // @[Library.scala 208:39]
- wire io_undef_value_3_4 = io_undef_value_2_8 | io_undef_value_2_9; // @[Library.scala 208:39]
- wire io_undef_value_4_0 = io_undef_value_3_0 | io_undef_value_3_1; // @[Library.scala 208:39]
- wire io_undef_value_4_1 = io_undef_value_3_2 | io_undef_value_3_3; // @[Library.scala 208:39]
- wire io_undef_value_5_0 = io_undef_value_4_0 | io_undef_value_4_1; // @[Library.scala 208:39]
- wire io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_3_4; // @[Library.scala 208:39]
- reg onehot_failed; // @[Decode.scala 670:30]
- wire _T_2 = ~reset; // @[Decode.scala 671:9]
- wire [1:0] _onehot_decode_T_77 = decoded[0] + decoded[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_79 = decoded[2] + decoded[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_81 = _onehot_decode_T_77 + _onehot_decode_T_79; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_83 = decoded[4] + decoded[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_85 = decoded[7] + decoded[8]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_1 = {{1'd0}, decoded[6]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_87 = _GEN_1 + _onehot_decode_T_85; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_89 = _onehot_decode_T_83 + _onehot_decode_T_87[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_91 = _onehot_decode_T_81 + _onehot_decode_T_89; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_93 = decoded[9] + decoded[10]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_95 = decoded[12] + decoded[13]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_2 = {{1'd0}, decoded[11]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_97 = _GEN_2 + _onehot_decode_T_95; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_99 = _onehot_decode_T_93 + _onehot_decode_T_97[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_101 = decoded[14] + decoded[15]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_103 = decoded[17] + decoded[18]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_3 = {{1'd0}, decoded[16]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_105 = _GEN_3 + _onehot_decode_T_103; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_107 = _onehot_decode_T_101 + _onehot_decode_T_105[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_109 = _onehot_decode_T_99 + _onehot_decode_T_107; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_111 = _onehot_decode_T_91 + _onehot_decode_T_109; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_113 = decoded[19] + decoded[20]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_115 = decoded[21] + decoded[22]; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_117 = _onehot_decode_T_113 + _onehot_decode_T_115; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_119 = decoded[23] + decoded[24]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_121 = decoded[26] + decoded[27]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_4 = {{1'd0}, decoded[25]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_123 = _GEN_4 + _onehot_decode_T_121; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_125 = _onehot_decode_T_119 + _onehot_decode_T_123[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_127 = _onehot_decode_T_117 + _onehot_decode_T_125; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_129 = decoded[28] + decoded[29]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_131 = decoded[31] + decoded[32]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_5 = {{1'd0}, decoded[30]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_133 = _GEN_5 + _onehot_decode_T_131; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_135 = _onehot_decode_T_129 + _onehot_decode_T_133[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_137 = decoded[33] + decoded[34]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_139 = decoded[36] + decoded[37]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_6 = {{1'd0}, decoded[35]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_141 = _GEN_6 + _onehot_decode_T_139; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_143 = _onehot_decode_T_137 + _onehot_decode_T_141[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_145 = _onehot_decode_T_135 + _onehot_decode_T_143; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_147 = _onehot_decode_T_127 + _onehot_decode_T_145; // @[Bitwise.scala 48:55]
- wire [5:0] _onehot_decode_T_149 = _onehot_decode_T_111 + _onehot_decode_T_147; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_151 = decoded[38] + decoded[39]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_153 = decoded[40] + decoded[41]; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_155 = _onehot_decode_T_151 + _onehot_decode_T_153; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_157 = decoded[42] + decoded[43]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_159 = decoded[45] + decoded[46]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_7 = {{1'd0}, decoded[44]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_161 = _GEN_7 + _onehot_decode_T_159; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_163 = _onehot_decode_T_157 + _onehot_decode_T_161[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_165 = _onehot_decode_T_155 + _onehot_decode_T_163; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_167 = decoded[47] + decoded[48]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_169 = decoded[50] + decoded[51]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_8 = {{1'd0}, decoded[49]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_171 = _GEN_8 + _onehot_decode_T_169; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_173 = _onehot_decode_T_167 + _onehot_decode_T_171[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_175 = decoded[52] + decoded[53]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_177 = decoded[55] + decoded[56]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_9 = {{1'd0}, decoded[54]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_179 = _GEN_9 + _onehot_decode_T_177; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_181 = _onehot_decode_T_175 + _onehot_decode_T_179[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_183 = _onehot_decode_T_173 + _onehot_decode_T_181; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_185 = _onehot_decode_T_165 + _onehot_decode_T_183; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_187 = decoded[57] + decoded[58]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_189 = decoded[60] + decoded[61]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_10 = {{1'd0}, decoded[59]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_191 = _GEN_10 + _onehot_decode_T_189; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_193 = _onehot_decode_T_187 + _onehot_decode_T_191[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_195 = decoded[62] + decoded[63]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_197 = decoded[65] + decoded[66]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_11 = {{1'd0}, decoded[64]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_199 = _GEN_11 + _onehot_decode_T_197; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_201 = _onehot_decode_T_195 + _onehot_decode_T_199[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_203 = _onehot_decode_T_193 + _onehot_decode_T_201; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_205 = decoded[67] + decoded[68]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_207 = decoded[70] + decoded[71]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_12 = {{1'd0}, decoded[69]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_209 = _GEN_12 + _onehot_decode_T_207; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_211 = _onehot_decode_T_205 + _onehot_decode_T_209[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_213 = decoded[72] + decoded[73]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_215 = decoded[75] + io_undef_value__38; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_13 = {{1'd0}, decoded[74]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_217 = _GEN_13 + _onehot_decode_T_215; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_219 = _onehot_decode_T_213 + _onehot_decode_T_217[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_221 = _onehot_decode_T_211 + _onehot_decode_T_219; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_223 = _onehot_decode_T_203 + _onehot_decode_T_221; // @[Bitwise.scala 48:55]
- wire [5:0] _onehot_decode_T_225 = _onehot_decode_T_185 + _onehot_decode_T_223; // @[Bitwise.scala 48:55]
- wire [6:0] onehot_decode = _onehot_decode_T_149 + _onehot_decode_T_225; // @[Bitwise.scala 48:55]
- wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 674:24]
- wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 674:24]
- wire _T_6 = _T_5 != 7'h1; // @[Decode.scala 674:36]
- assign io_imm12 = {_io_imm12_T_2,io_inst[31:20]}; // @[Cat.scala 31:58]
- assign io_imm20 = {io_inst[31:12],12'h0}; // @[Cat.scala 31:58]
- assign io_immjal = {io_immjal_hi,io_immjal_lo}; // @[Cat.scala 31:58]
- assign io_immbr = {io_immbr_hi,io_immbr_lo}; // @[Cat.scala 31:58]
- assign io_immst = {io_immst_hi,io_inst[11:7]}; // @[Cat.scala 31:58]
- assign io_lui = _io_lui_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_auipc = _io_auipc_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_jal = _io_jal_T_2 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_jalr = _io_jalr_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_beq = _io_beq_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bne = _io_bne_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_blt = _io_blt_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_csrrw = 1'h0; // @[Decode.scala 624:14]
- assign io_csrrs = 1'h0; // @[Decode.scala 625:14]
- assign io_csrrc = 1'h0; // @[Decode.scala 626:14]
- assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lbu = _io_lbu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lhu = _io_lhu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_fence = 1'h0; // @[Decode.scala 641:17]
- assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_xori = _io_xori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_ori = _io_ori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_andi = _io_andi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_slli = _io_slli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_srli = _io_srli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_srai = _io_srai_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_add = _io_add_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sub = _io_sub_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_slt = _io_slt_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sltu = _io_sltu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_xor = _io_xor_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_or = _io_or_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_and = _io_and_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sll = _io_sll_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_srl = _io_srl_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sra = _io_sra_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mul = _io_mul_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulh = _io_mulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhsu = _io_mulhsu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhu = _io_mulhu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhr = _io_mulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhsur = _io_mulhsur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_div = 1'h0; // @[Decode.scala 628:12]
- assign io_divu = 1'h0; // @[Decode.scala 629:13]
- assign io_rem = 1'h0; // @[Decode.scala 630:12]
- assign io_remu = 1'h0; // @[Decode.scala 631:13]
- assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_min = _io_min_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 584:97]
- assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 585:76]
- assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 590:71]
- assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 603:20]
- assign io_ebreak = 1'h0; // @[Decode.scala 633:15]
- assign io_ecall = 1'h0; // @[Decode.scala 634:15]
- assign io_eexit = 1'h0; // @[Decode.scala 635:15]
- assign io_eyield = 1'h0; // @[Decode.scala 636:15]
- assign io_ectxsw = 1'h0; // @[Decode.scala 637:15]
- assign io_mpause = 1'h0; // @[Decode.scala 638:15]
- assign io_mret = 1'h0; // @[Decode.scala 639:15]
- assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 667:15]
- assign io_fencei = 1'h0; // @[Decode.scala 642:17]
- assign io_flushat = 1'h0; // @[Decode.scala 643:17]
- assign io_flushall = 1'h0; // @[Decode.scala 644:17]
- assign io_slog = 1'h0; // @[Decode.scala 646:13]
- always @(posedge clock) begin
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~onehot_failed)) begin
- $fatal; // @[Decode.scala 671:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~onehot_failed)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Decode.scala:671 assert(!onehot_failed)\n"); // @[Decode.scala 671:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_6 & _T_2) begin
- $fwrite(32'h80000002,"[FAIL] decode inst=%x addr=%x decoded=0b%b pipeline=%d\n",io_inst,io_addr,decoded,2'h2
- ); // @[Decode.scala 676:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Decode.scala 674:45]
- onehot_failed <= 1'h0; // @[Decode.scala 675:19]
- end else begin
- onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 670:30]
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- onehot_failed = _RAND_0[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- onehot_failed = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Decode_2(
- input clock,
- input reset,
- input io_halted,
- input io_inst_valid,
- output io_inst_ready,
- input [31:0] io_inst_addr,
- input [31:0] io_inst_inst,
- input io_inst_brchFwd,
- input [31:0] io_scoreboard_regd,
- input [31:0] io_scoreboard_comb,
- output [31:0] io_scoreboard_spec,
- output io_rs1Read_valid,
- output [4:0] io_rs1Read_addr,
- output io_rs1Set_valid,
- output [31:0] io_rs1Set_value,
- output io_rs2Read_valid,
- output [4:0] io_rs2Read_addr,
- output io_rs2Set_valid,
- output [31:0] io_rs2Set_value,
- output io_rdMark_valid,
- output [4:0] io_rdMark_addr,
- output io_busRead_bypass,
- output [31:0] io_busRead_immed,
- output io_alu_valid,
- output [4:0] io_alu_addr,
- output [17:0] io_alu_op,
- output io_bru_valid,
- output io_bru_fwd,
- output [16:0] io_bru_op,
- output [31:0] io_bru_pc,
- output [31:0] io_bru_target,
- output [4:0] io_bru_link,
- output [2:0] io_csr_op,
- output io_lsu_valid,
- input io_lsu_ready,
- output [4:0] io_lsu_addr,
- output [11:0] io_lsu_op,
- output io_mlu_valid,
- output [4:0] io_mlu_addr,
- output [8:0] io_mlu_op,
- output [3:0] io_dvu_op,
- output io_vinst_valid,
- input io_vinst_ready,
- output [4:0] io_vinst_addr,
- output [31:0] io_vinst_inst,
- output [4:0] io_vinst_op,
- input io_branchTaken,
- input io_interlock,
- input io_serializeIn_mul,
- input io_serializeIn_jump,
- input io_serializeIn_brcond,
- output io_serializeOut_mul,
- output io_serializeOut_jump,
- output io_serializeOut_brcond
-);
- wire d_clock; // @[Decode.scala 107:17]
- wire d_reset; // @[Decode.scala 107:17]
- wire [31:0] d_io_addr; // @[Decode.scala 107:17]
- wire [31:0] d_io_inst; // @[Decode.scala 107:17]
- wire [31:0] d_io_imm12; // @[Decode.scala 107:17]
- wire [31:0] d_io_imm20; // @[Decode.scala 107:17]
- wire [31:0] d_io_immjal; // @[Decode.scala 107:17]
- wire [31:0] d_io_immbr; // @[Decode.scala 107:17]
- wire [31:0] d_io_immst; // @[Decode.scala 107:17]
- wire d_io_lui; // @[Decode.scala 107:17]
- wire d_io_auipc; // @[Decode.scala 107:17]
- wire d_io_jal; // @[Decode.scala 107:17]
- wire d_io_jalr; // @[Decode.scala 107:17]
- wire d_io_beq; // @[Decode.scala 107:17]
- wire d_io_bne; // @[Decode.scala 107:17]
- wire d_io_blt; // @[Decode.scala 107:17]
- wire d_io_bge; // @[Decode.scala 107:17]
- wire d_io_bltu; // @[Decode.scala 107:17]
- wire d_io_bgeu; // @[Decode.scala 107:17]
- wire d_io_csrrw; // @[Decode.scala 107:17]
- wire d_io_csrrs; // @[Decode.scala 107:17]
- wire d_io_csrrc; // @[Decode.scala 107:17]
- wire d_io_lb; // @[Decode.scala 107:17]
- wire d_io_lh; // @[Decode.scala 107:17]
- wire d_io_lw; // @[Decode.scala 107:17]
- wire d_io_lbu; // @[Decode.scala 107:17]
- wire d_io_lhu; // @[Decode.scala 107:17]
- wire d_io_sb; // @[Decode.scala 107:17]
- wire d_io_sh; // @[Decode.scala 107:17]
- wire d_io_sw; // @[Decode.scala 107:17]
- wire d_io_fence; // @[Decode.scala 107:17]
- wire d_io_addi; // @[Decode.scala 107:17]
- wire d_io_slti; // @[Decode.scala 107:17]
- wire d_io_sltiu; // @[Decode.scala 107:17]
- wire d_io_xori; // @[Decode.scala 107:17]
- wire d_io_ori; // @[Decode.scala 107:17]
- wire d_io_andi; // @[Decode.scala 107:17]
- wire d_io_slli; // @[Decode.scala 107:17]
- wire d_io_srli; // @[Decode.scala 107:17]
- wire d_io_srai; // @[Decode.scala 107:17]
- wire d_io_add; // @[Decode.scala 107:17]
- wire d_io_sub; // @[Decode.scala 107:17]
- wire d_io_slt; // @[Decode.scala 107:17]
- wire d_io_sltu; // @[Decode.scala 107:17]
- wire d_io_xor; // @[Decode.scala 107:17]
- wire d_io_or; // @[Decode.scala 107:17]
- wire d_io_and; // @[Decode.scala 107:17]
- wire d_io_sll; // @[Decode.scala 107:17]
- wire d_io_srl; // @[Decode.scala 107:17]
- wire d_io_sra; // @[Decode.scala 107:17]
- wire d_io_mul; // @[Decode.scala 107:17]
- wire d_io_mulh; // @[Decode.scala 107:17]
- wire d_io_mulhsu; // @[Decode.scala 107:17]
- wire d_io_mulhu; // @[Decode.scala 107:17]
- wire d_io_mulhr; // @[Decode.scala 107:17]
- wire d_io_mulhsur; // @[Decode.scala 107:17]
- wire d_io_mulhur; // @[Decode.scala 107:17]
- wire d_io_dmulh; // @[Decode.scala 107:17]
- wire d_io_dmulhr; // @[Decode.scala 107:17]
- wire d_io_div; // @[Decode.scala 107:17]
- wire d_io_divu; // @[Decode.scala 107:17]
- wire d_io_rem; // @[Decode.scala 107:17]
- wire d_io_remu; // @[Decode.scala 107:17]
- wire d_io_clz; // @[Decode.scala 107:17]
- wire d_io_ctz; // @[Decode.scala 107:17]
- wire d_io_pcnt; // @[Decode.scala 107:17]
- wire d_io_min; // @[Decode.scala 107:17]
- wire d_io_minu; // @[Decode.scala 107:17]
- wire d_io_max; // @[Decode.scala 107:17]
- wire d_io_maxu; // @[Decode.scala 107:17]
- wire d_io_getvl; // @[Decode.scala 107:17]
- wire d_io_getmaxvl; // @[Decode.scala 107:17]
- wire d_io_vld; // @[Decode.scala 107:17]
- wire d_io_vst; // @[Decode.scala 107:17]
- wire d_io_viop; // @[Decode.scala 107:17]
- wire d_io_ebreak; // @[Decode.scala 107:17]
- wire d_io_ecall; // @[Decode.scala 107:17]
- wire d_io_eexit; // @[Decode.scala 107:17]
- wire d_io_eyield; // @[Decode.scala 107:17]
- wire d_io_ectxsw; // @[Decode.scala 107:17]
- wire d_io_mpause; // @[Decode.scala 107:17]
- wire d_io_mret; // @[Decode.scala 107:17]
- wire d_io_undef; // @[Decode.scala 107:17]
- wire d_io_fencei; // @[Decode.scala 107:17]
- wire d_io_flushat; // @[Decode.scala 107:17]
- wire d_io_flushall; // @[Decode.scala 107:17]
- wire d_io_slog; // @[Decode.scala 107:17]
- wire decodeEn = io_inst_valid & io_inst_ready & ~io_branchTaken; // @[Decode.scala 104:49]
- wire vldst = d_io_vld | d_io_vst; // @[Decode.scala 111:24]
- wire vldst_wb = vldst & io_inst_inst[28]; // @[Decode.scala 112:24]
- wire [4:0] rdAddr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- wire [4:0] rs2Addr = io_inst_inst[24:20]; // @[Decode.scala 116:29]
- wire [4:0] rs3Addr = io_inst_inst[31:27]; // @[Decode.scala 117:29]
- wire _isAluImm_T_3 = d_io_addi | d_io_slti | d_io_sltiu | d_io_xori | d_io_ori; // @[Decode.scala 119:68]
- wire isAluImm = _isAluImm_T_3 | d_io_andi | d_io_slli | d_io_srli | d_io_srai; // @[Decode.scala 120:66]
- wire _isAluReg_T_4 = d_io_add | d_io_sub | d_io_slt | d_io_sltu | d_io_xor | d_io_or; // @[Decode.scala 122:76]
- wire isAluReg = _isAluReg_T_4 | d_io_and | d_io_sll | d_io_srl | d_io_sra; // @[Decode.scala 123:62]
- wire isAlu1Bit = d_io_clz | d_io_ctz | d_io_pcnt; // @[Decode.scala 125:40]
- wire isAlu2Bit = d_io_min | d_io_minu | d_io_max | d_io_maxu; // @[Decode.scala 126:53]
- wire _isCondBr_T_3 = d_io_beq | d_io_bne | d_io_blt | d_io_bge | d_io_bltu; // @[Decode.scala 128:63]
- wire isCondBr = _isCondBr_T_3 | d_io_bgeu; // @[Decode.scala 129:28]
- wire isLoad = d_io_lb | d_io_lh | d_io_lw | d_io_lbu | d_io_lhu; // @[Decode.scala 135:58]
- wire isStore = d_io_sb | d_io_sh | d_io_sw; // @[Decode.scala 136:36]
- wire isLsu = isLoad | isStore | d_io_vld | d_io_vst; // @[Decode.scala 137:45]
- wire isMul = d_io_mul | d_io_mulh | d_io_mulhsu | d_io_mulhu | d_io_mulhr | d_io_mulhsur | d_io_mulhur | d_io_dmulh
- | d_io_dmulhr; // @[Decode.scala 139:125]
- wire isVIop = io_vinst_op[4]; // @[Decode.scala 143:27]
- wire isVIopVs2 = isVIop & io_inst_inst[1:0] == 2'h0; // @[Decode.scala 146:26]
- wire [31:0] _aluRdEn_T = io_scoreboard_comb >> rdAddr; // @[Decode.scala 150:37]
- wire aluRdEn = ~_aluRdEn_T[0] | isVIop | isStore | isCondBr; // @[Decode.scala 150:71]
- wire [31:0] _aluRs1En_T = io_scoreboard_comb >> io_inst_inst[19:15]; // @[Decode.scala 151:37]
- wire aluRs1En = ~_aluRs1En_T[0] | isVIop | isLsu | d_io_auipc; // @[Decode.scala 151:69]
- wire [31:0] _aluRs2En_T = io_scoreboard_comb >> rs2Addr; // @[Decode.scala 152:37]
- wire aluRs2En = ~_aluRs2En_T[0] | isVIopVs2 | isLsu | d_io_auipc | isAluImm | isAlu1Bit; // @[Decode.scala 152:95]
- wire aluEn = aluRdEn & aluRs1En & aluRs2En; // @[Decode.scala 155:35]
- wire [31:0] _bruEn_T_1 = io_scoreboard_regd >> io_inst_inst[19:15]; // @[Decode.scala 158:48]
- wire _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 159:35]
- wire bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 158:58]
- wire _lsuEn_T = ~isLsu; // @[Decode.scala 162:15]
- wire _lsuEn_T_4 = ~io_serializeIn_brcond; // @[Decode.scala 164:26]
- wire _lsuEn_T_5 = _lsuEn_T | ~io_serializeIn_brcond; // @[Decode.scala 164:23]
- wire _lsuEn_T_6 = io_lsu_ready & _lsuEn_T_5; // @[Decode.scala 163:51]
- wire _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 165:20]
- wire _lsuEn_T_15 = _aluRs2En_T[0] & (isStore | vldst); // @[Decode.scala 167:49]
- wire _lsuEn_T_16 = _lsuEn_T_11 | _lsuEn_T_15; // @[Decode.scala 166:50]
- wire _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 165:15]
- wire _lsuEn_T_18 = _lsuEn_T_6 & _lsuEn_T_17; // @[Decode.scala 164:50]
- wire lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 162:22]
- wire mulEn = (~isMul | ~io_serializeIn_mul) & _lsuEn_T_4; // @[Decode.scala 170:47]
- wire _vinstEn_T_6 = ~(io_vinst_op != 5'h0 & ~io_vinst_ready); // @[Decode.scala 175:17]
- wire vinstEn = ~(isVIop & io_serializeIn_brcond) & _vinstEn_T_6; // @[Decode.scala 174:76]
- wire aluValid_value__0 = io_alu_op[0] | io_alu_op[1]; // @[Library.scala 208:39]
- wire aluValid_value__1 = io_alu_op[2] | io_alu_op[3]; // @[Library.scala 208:39]
- wire aluValid_value__2 = io_alu_op[4] | io_alu_op[5]; // @[Library.scala 208:39]
- wire aluValid_value__3 = io_alu_op[6] | io_alu_op[7]; // @[Library.scala 208:39]
- wire aluValid_value__4 = io_alu_op[8] | io_alu_op[9]; // @[Library.scala 208:39]
- wire aluValid_value__5 = io_alu_op[10] | io_alu_op[11]; // @[Library.scala 208:39]
- wire aluValid_value__6 = io_alu_op[12] | io_alu_op[13]; // @[Library.scala 208:39]
- wire aluValid_value__7 = io_alu_op[14] | io_alu_op[15]; // @[Library.scala 208:39]
- wire aluValid_value__8 = io_alu_op[16] | io_alu_op[17]; // @[Library.scala 208:39]
- wire aluValid_value_1_0 = aluValid_value__0 | aluValid_value__1; // @[Library.scala 208:39]
- wire aluValid_value_1_1 = aluValid_value__2 | aluValid_value__3; // @[Library.scala 208:39]
- wire aluValid_value_1_2 = aluValid_value__4 | aluValid_value__5; // @[Library.scala 208:39]
- wire aluValid_value_1_3 = aluValid_value__6 | aluValid_value__7; // @[Library.scala 208:39]
- wire aluValid_value_2_0 = aluValid_value_1_0 | aluValid_value_1_1; // @[Library.scala 208:39]
- wire aluValid_value_2_1 = aluValid_value_1_2 | aluValid_value_1_3; // @[Library.scala 208:39]
- wire aluValid_value_3_0 = aluValid_value_2_0 | aluValid_value_2_1; // @[Library.scala 208:39]
- wire aluValid_value_4_0 = aluValid_value_3_0 | aluValid_value__8; // @[Library.scala 208:39]
- wire aluOp_1 = d_io_sub; // @[Decode.scala 183:19 190:19]
- wire aluOp_0 = d_io_auipc | d_io_addi | d_io_add; // @[Decode.scala 189:46]
- wire aluOp_3 = d_io_sltiu | d_io_sltu; // @[Decode.scala 192:33]
- wire aluOp_2 = d_io_slti | d_io_slt; // @[Decode.scala 191:32]
- wire aluOp_5 = d_io_ori | d_io_or; // @[Decode.scala 194:31]
- wire aluOp_4 = d_io_xori | d_io_xor; // @[Decode.scala 193:32]
- wire aluOp_8 = d_io_srli | d_io_srl; // @[Decode.scala 197:32]
- wire aluOp_7 = d_io_slli | d_io_sll; // @[Decode.scala 196:32]
- wire aluOp_6 = d_io_andi | d_io_and; // @[Decode.scala 195:32]
- wire [8:0] io_alu_op_lo = {aluOp_8,aluOp_7,aluOp_6,aluOp_5,aluOp_4,aluOp_3,aluOp_2,aluOp_1,aluOp_0}; // @[Decode.scala 187:22]
- wire aluOp_10 = d_io_lui; // @[Decode.scala 183:19 199:19]
- wire aluOp_9 = d_io_srai | d_io_sra; // @[Decode.scala 198:32]
- wire aluOp_12 = d_io_ctz; // @[Decode.scala 183:19 201:19]
- wire aluOp_11 = d_io_clz; // @[Decode.scala 183:19 200:19]
- wire aluOp_14 = d_io_min; // @[Decode.scala 183:19 203:19]
- wire aluOp_13 = d_io_pcnt; // @[Decode.scala 183:19 202:19]
- wire aluOp_17 = d_io_maxu; // @[Decode.scala 183:19 206:19]
- wire aluOp_16 = d_io_max; // @[Decode.scala 183:19 205:19]
- wire aluOp_15 = d_io_minu; // @[Decode.scala 183:19 204:19]
- wire [8:0] io_alu_op_hi = {aluOp_17,aluOp_16,aluOp_15,aluOp_14,aluOp_13,aluOp_12,aluOp_11,aluOp_10,aluOp_9}; // @[Decode.scala 187:22]
- wire bruValid_value__8 = io_bru_op[16]; // @[Library.scala 196:26]
- wire bruValid_value__0 = io_bru_op[0] | io_bru_op[1]; // @[Library.scala 208:39]
- wire bruValid_value__1 = io_bru_op[2] | io_bru_op[3]; // @[Library.scala 208:39]
- wire bruValid_value__2 = io_bru_op[4] | io_bru_op[5]; // @[Library.scala 208:39]
- wire bruValid_value__3 = io_bru_op[6] | io_bru_op[7]; // @[Library.scala 208:39]
- wire bruValid_value__4 = io_bru_op[8] | io_bru_op[9]; // @[Library.scala 208:39]
- wire bruValid_value__5 = io_bru_op[10] | io_bru_op[11]; // @[Library.scala 208:39]
- wire bruValid_value__6 = io_bru_op[12] | io_bru_op[13]; // @[Library.scala 208:39]
- wire bruValid_value__7 = io_bru_op[14] | io_bru_op[15]; // @[Library.scala 208:39]
- wire bruValid_value_1_0 = bruValid_value__0 | bruValid_value__1; // @[Library.scala 208:39]
- wire bruValid_value_1_1 = bruValid_value__2 | bruValid_value__3; // @[Library.scala 208:39]
- wire bruValid_value_1_2 = bruValid_value__4 | bruValid_value__5; // @[Library.scala 208:39]
- wire bruValid_value_1_3 = bruValid_value__6 | bruValid_value__7; // @[Library.scala 208:39]
- wire bruValid_value_2_0 = bruValid_value_1_0 | bruValid_value_1_1; // @[Library.scala 208:39]
- wire bruValid_value_2_1 = bruValid_value_1_2 | bruValid_value_1_3; // @[Library.scala 208:39]
- wire bruValid_value_3_0 = bruValid_value_2_0 | bruValid_value_2_1; // @[Library.scala 208:39]
- wire bruValid_value_4_0 = bruValid_value_3_0 | bruValid_value__8; // @[Library.scala 208:39]
- wire bruOp_1 = d_io_jalr; // @[Decode.scala 210:19 220:19]
- wire bruOp_0 = d_io_jal; // @[Decode.scala 210:19 219:19]
- wire bruOp_3 = d_io_bne; // @[Decode.scala 210:19 222:19]
- wire bruOp_2 = d_io_beq; // @[Decode.scala 210:19 221:19]
- wire bruOp_5 = d_io_bge; // @[Decode.scala 210:19 224:19]
- wire bruOp_4 = d_io_blt; // @[Decode.scala 210:19 223:19]
- wire bruOp_7 = d_io_bgeu; // @[Decode.scala 210:19 226:19]
- wire bruOp_6 = d_io_bltu; // @[Decode.scala 210:19 225:19]
- wire [7:0] io_bru_op_lo = {bruOp_7,bruOp_6,bruOp_5,bruOp_4,bruOp_3,bruOp_2,bruOp_1,bruOp_0}; // @[Decode.scala 214:22]
- wire bruOp_16 = d_io_undef; // @[Decode.scala 210:19 235:21]
- wire [8:0] io_bru_op_hi = {bruOp_16,1'h0,1'h0,2'h0,4'h0}; // @[Decode.scala 214:22]
- wire [31:0] _io_bru_target_T_1 = io_inst_inst[2] ? d_io_immjal : d_io_immbr; // @[Decode.scala 216:38]
- wire csrValid_value__1 = io_csr_op[2]; // @[Library.scala 196:26]
- wire csrValid_value__0 = io_csr_op[0] | io_csr_op[1]; // @[Library.scala 208:39]
- wire csrValid_value_1_0 = csrValid_value__0 | csrValid_value__1; // @[Library.scala 208:39]
- wire lsuValid_value__0 = io_lsu_op[0] | io_lsu_op[1]; // @[Library.scala 208:39]
- wire lsuValid_value__1 = io_lsu_op[2] | io_lsu_op[3]; // @[Library.scala 208:39]
- wire lsuValid_value__2 = io_lsu_op[4] | io_lsu_op[5]; // @[Library.scala 208:39]
- wire lsuValid_value__3 = io_lsu_op[6] | io_lsu_op[7]; // @[Library.scala 208:39]
- wire lsuValid_value__4 = io_lsu_op[8] | io_lsu_op[9]; // @[Library.scala 208:39]
- wire lsuValid_value__5 = io_lsu_op[10] | io_lsu_op[11]; // @[Library.scala 208:39]
- wire lsuValid_value_1_0 = lsuValid_value__0 | lsuValid_value__1; // @[Library.scala 208:39]
- wire lsuValid_value_1_1 = lsuValid_value__2 | lsuValid_value__3; // @[Library.scala 208:39]
- wire lsuValid_value_1_2 = lsuValid_value__4 | lsuValid_value__5; // @[Library.scala 208:39]
- wire lsuValid_value_2_0 = lsuValid_value_1_0 | lsuValid_value_1_1; // @[Library.scala 208:39]
- wire lsuValid_value_3_0 = lsuValid_value_2_0 | lsuValid_value_1_2; // @[Library.scala 208:39]
- wire lsuOp_2 = d_io_lw; // @[Decode.scala 252:19 261:18]
- wire lsuOp_1 = d_io_lh; // @[Decode.scala 252:19 260:18]
- wire lsuOp_0 = d_io_lb; // @[Decode.scala 252:19 259:18]
- wire lsuOp_5 = d_io_sb; // @[Decode.scala 252:19 264:18]
- wire lsuOp_4 = d_io_lhu; // @[Decode.scala 252:19 263:18]
- wire lsuOp_3 = d_io_lbu; // @[Decode.scala 252:19 262:18]
- wire [5:0] io_lsu_op_lo = {lsuOp_5,lsuOp_4,lsuOp_3,lsuOp_2,lsuOp_1,lsuOp_0}; // @[Decode.scala 257:22]
- wire lsuOp_7 = d_io_sw; // @[Decode.scala 252:19 266:18]
- wire lsuOp_6 = d_io_sh; // @[Decode.scala 252:19 265:18]
- wire [5:0] io_lsu_op_hi = {vldst,1'h0,1'h0,1'h0,lsuOp_7,lsuOp_6}; // @[Decode.scala 257:22]
- wire mluValid_value__4 = io_mlu_op[8]; // @[Library.scala 196:26]
- wire mluValid_value__0 = io_mlu_op[0] | io_mlu_op[1]; // @[Library.scala 208:39]
- wire mluValid_value__1 = io_mlu_op[2] | io_mlu_op[3]; // @[Library.scala 208:39]
- wire mluValid_value__2 = io_mlu_op[4] | io_mlu_op[5]; // @[Library.scala 208:39]
- wire mluValid_value__3 = io_mlu_op[6] | io_mlu_op[7]; // @[Library.scala 208:39]
- wire mluValid_value_1_0 = mluValid_value__0 | mluValid_value__1; // @[Library.scala 208:39]
- wire mluValid_value_1_1 = mluValid_value__2 | mluValid_value__3; // @[Library.scala 208:39]
- wire mluValid_value_2_0 = mluValid_value_1_0 | mluValid_value_1_1; // @[Library.scala 208:39]
- wire mluValid_value_3_0 = mluValid_value_2_0 | mluValid_value__4; // @[Library.scala 208:39]
- wire mluOp_1 = d_io_mulh; // @[Decode.scala 275:19 282:22]
- wire mluOp_0 = d_io_mul; // @[Decode.scala 275:19 281:22]
- wire mluOp_3 = d_io_mulhu; // @[Decode.scala 275:19 284:22]
- wire mluOp_2 = d_io_mulhsu; // @[Decode.scala 275:19 283:22]
- wire [3:0] io_mlu_op_lo = {mluOp_3,mluOp_2,mluOp_1,mluOp_0}; // @[Decode.scala 279:22]
- wire mluOp_5 = d_io_mulhsur; // @[Decode.scala 275:19 286:22]
- wire mluOp_4 = d_io_mulhr; // @[Decode.scala 275:19 285:22]
- wire mluOp_8 = d_io_dmulhr; // @[Decode.scala 275:19 289:22]
- wire mluOp_7 = d_io_dmulh; // @[Decode.scala 275:19 288:22]
- wire mluOp_6 = d_io_mulhur; // @[Decode.scala 275:19 287:22]
- wire [4:0] io_mlu_op_hi = {mluOp_8,mluOp_7,mluOp_6,mluOp_5,mluOp_4}; // @[Decode.scala 279:22]
- wire dvuValid_value__0 = io_dvu_op[0] | io_dvu_op[1]; // @[Library.scala 208:39]
- wire dvuValid_value__1 = io_dvu_op[2] | io_dvu_op[3]; // @[Library.scala 208:39]
- wire dvuValid_value_1_0 = dvuValid_value__0 | dvuValid_value__1; // @[Library.scala 208:39]
- wire dvuEn = ~dvuValid_value_1_0; // @[Decode.scala 304:34]
- wire vinstOp_0 = d_io_getvl; // @[Decode.scala 308:21 319:24]
- wire vinstOp_1 = d_io_getmaxvl; // @[Decode.scala 308:21 320:27]
- wire vinstValid_value__0 = vinstOp_0 | vinstOp_1; // @[Library.scala 208:39]
- wire vinstOp_2 = d_io_vld; // @[Decode.scala 308:21 316:22]
- wire vinstOp_3 = d_io_vst; // @[Decode.scala 308:21 317:22]
- wire vinstValid_value__1 = vinstOp_2 | vinstOp_3; // @[Library.scala 208:39]
- wire vinstValid_value_1_0 = vinstValid_value__0 | vinstValid_value__1; // @[Library.scala 208:39]
- wire vinstOp_4 = d_io_viop; // @[Decode.scala 308:21 318:23]
- wire vinstValid_value_2_0 = vinstValid_value_1_0 | vinstOp_4; // @[Library.scala 208:39]
- wire [1:0] io_vinst_op_lo = {vinstOp_1,vinstOp_0}; // @[Decode.scala 314:26]
- wire [2:0] io_vinst_op_hi = {vinstOp_4,vinstOp_3,vinstOp_2}; // @[Decode.scala 314:26]
- wire _io_rs1Read_valid_T = isCondBr | isAluReg; // @[Decode.scala 326:45]
- wire _io_rs1Read_valid_T_3 = isCondBr | isAluReg | isAluImm | isAlu1Bit | isAlu2Bit; // @[Decode.scala 326:82]
- wire _io_rs1Read_valid_T_9 = _io_rs1Read_valid_T_3 | isMul | d_io_getvl; // @[Decode.scala 327:75]
- wire _io_rs1Read_valid_T_11 = _io_rs1Read_valid_T_9 | d_io_vld | d_io_vst; // @[Decode.scala 328:46]
- wire _io_rs2Read_valid_T_2 = _io_rs1Read_valid_T | isAlu2Bit | isStore; // @[Decode.scala 329:70]
- wire _io_rs2Read_valid_T_8 = _io_rs2Read_valid_T_2 | isMul | d_io_getvl | d_io_vld; // @[Decode.scala 330:77]
- wire _io_rs2Read_valid_T_10 = _io_rs2Read_valid_T_8 | d_io_vst | d_io_viop; // @[Decode.scala 331:44]
- wire _io_rs2Set_value_T = d_io_auipc | d_io_lui; // @[Decode.scala 346:45]
- wire _rdMark_valid_T_4 = lsuValid_value_3_0 & isLoad; // @[Decode.scala 352:16]
- wire _rdMark_valid_T_5 = aluValid_value_4_0 | csrValid_value_1_0 | mluValid_value_3_0 | _rdMark_valid_T_4; // @[Decode.scala 351:68]
- wire _rdMark_valid_T_6 = _rdMark_valid_T_5 | d_io_getvl; // @[Decode.scala 352:26]
- wire _rdMark_valid_T_12 = bruValid_value_4_0 & (bruOp_0 | bruOp_1) & rdAddr != 5'h0; // @[Decode.scala 354:55]
- wire rdMark_valid = _rdMark_valid_T_6 | d_io_getmaxvl | vldst_wb | _rdMark_valid_T_12; // @[Decode.scala 353:47]
- wire [31:0] _scoreboard_spec_T = 32'h1 << rdAddr; // @[OneHot.scala 64:12]
- wire [31:0] scoreboard_spec = rdMark_valid ? _scoreboard_spec_T : 32'h0; // @[Decode.scala 357:28]
- wire _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 369:65]
- wire _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 368:8]
- wire storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 372:47]
- wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 375:30]
- wire _io_inst_ready_T_6 = ~io_serializeIn_jump; // @[Decode.scala 381:20]
- wire _io_inst_ready_T_7 = aluEn & bruEn & lsuEn & mulEn & dvuEn & vinstEn & _io_inst_ready_T_6; // @[Decode.scala 380:84]
- wire _io_inst_ready_T_13 = ~d_io_undef; // @[Decode.scala 382:43]
- wire _io_serializeOut_brcond_T = io_serializeIn_brcond | d_io_beq; // @[Decode.scala 392:51]
- DecodedInstruction_2 d ( // @[Decode.scala 107:17]
- .clock(d_clock),
- .reset(d_reset),
- .io_addr(d_io_addr),
- .io_inst(d_io_inst),
- .io_imm12(d_io_imm12),
- .io_imm20(d_io_imm20),
- .io_immjal(d_io_immjal),
- .io_immbr(d_io_immbr),
- .io_immst(d_io_immst),
- .io_lui(d_io_lui),
- .io_auipc(d_io_auipc),
- .io_jal(d_io_jal),
- .io_jalr(d_io_jalr),
- .io_beq(d_io_beq),
- .io_bne(d_io_bne),
- .io_blt(d_io_blt),
- .io_bge(d_io_bge),
- .io_bltu(d_io_bltu),
- .io_bgeu(d_io_bgeu),
- .io_csrrw(d_io_csrrw),
- .io_csrrs(d_io_csrrs),
- .io_csrrc(d_io_csrrc),
- .io_lb(d_io_lb),
- .io_lh(d_io_lh),
- .io_lw(d_io_lw),
- .io_lbu(d_io_lbu),
- .io_lhu(d_io_lhu),
- .io_sb(d_io_sb),
- .io_sh(d_io_sh),
- .io_sw(d_io_sw),
- .io_fence(d_io_fence),
- .io_addi(d_io_addi),
- .io_slti(d_io_slti),
- .io_sltiu(d_io_sltiu),
- .io_xori(d_io_xori),
- .io_ori(d_io_ori),
- .io_andi(d_io_andi),
- .io_slli(d_io_slli),
- .io_srli(d_io_srli),
- .io_srai(d_io_srai),
- .io_add(d_io_add),
- .io_sub(d_io_sub),
- .io_slt(d_io_slt),
- .io_sltu(d_io_sltu),
- .io_xor(d_io_xor),
- .io_or(d_io_or),
- .io_and(d_io_and),
- .io_sll(d_io_sll),
- .io_srl(d_io_srl),
- .io_sra(d_io_sra),
- .io_mul(d_io_mul),
- .io_mulh(d_io_mulh),
- .io_mulhsu(d_io_mulhsu),
- .io_mulhu(d_io_mulhu),
- .io_mulhr(d_io_mulhr),
- .io_mulhsur(d_io_mulhsur),
- .io_mulhur(d_io_mulhur),
- .io_dmulh(d_io_dmulh),
- .io_dmulhr(d_io_dmulhr),
- .io_div(d_io_div),
- .io_divu(d_io_divu),
- .io_rem(d_io_rem),
- .io_remu(d_io_remu),
- .io_clz(d_io_clz),
- .io_ctz(d_io_ctz),
- .io_pcnt(d_io_pcnt),
- .io_min(d_io_min),
- .io_minu(d_io_minu),
- .io_max(d_io_max),
- .io_maxu(d_io_maxu),
- .io_getvl(d_io_getvl),
- .io_getmaxvl(d_io_getmaxvl),
- .io_vld(d_io_vld),
- .io_vst(d_io_vst),
- .io_viop(d_io_viop),
- .io_ebreak(d_io_ebreak),
- .io_ecall(d_io_ecall),
- .io_eexit(d_io_eexit),
- .io_eyield(d_io_eyield),
- .io_ectxsw(d_io_ectxsw),
- .io_mpause(d_io_mpause),
- .io_mret(d_io_mret),
- .io_undef(d_io_undef),
- .io_fencei(d_io_fencei),
- .io_flushat(d_io_flushat),
- .io_flushall(d_io_flushall),
- .io_slog(d_io_slog)
- );
- assign io_inst_ready = _io_inst_ready_T_7 & ~io_halted & ~io_interlock & _io_inst_ready_T_13; // @[Decode.scala 381:72]
- assign io_scoreboard_spec = {scoreboard_spec[31:1],1'h0}; // @[Cat.scala 31:58]
- assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_11; // @[Decode.scala 326:32]
- assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 334:25]
- assign io_rs1Set_valid = decodeEn & d_io_auipc; // @[Decode.scala 340:31]
- assign io_rs1Set_value = io_inst_addr; // @[Decode.scala 343:25]
- assign io_rs2Read_valid = decodeEn & _io_rs2Read_valid_T_10; // @[Decode.scala 329:32]
- assign io_rs2Read_addr = io_inst_inst[24:20]; // @[Decode.scala 116:29]
- assign io_rs2Set_valid = io_rs1Set_valid | decodeEn & (isAluImm | isAlu1Bit | d_io_lui); // @[Decode.scala 341:38]
- assign io_rs2Set_value = _io_rs2Set_value_T ? d_io_imm20 : d_io_imm12; // @[Mux.scala 101:16]
- assign io_rdMark_valid = decodeEn & rdMark_valid; // @[Decode.scala 360:31]
- assign io_rdMark_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_busRead_bypass = io_inst_inst[31:25] == 7'h0 & _io_busRead_bypass_T_10; // @[Decode.scala 367:52]
- assign io_busRead_immed = {d_io_imm12[31:5],_io_busRead_immed_T_3}; // @[Cat.scala 31:58]
- assign io_alu_valid = decodeEn & aluValid_value_4_0; // @[Decode.scala 185:28]
- assign io_alu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_alu_op = {io_alu_op_hi,io_alu_op_lo}; // @[Decode.scala 187:22]
- assign io_bru_valid = decodeEn & bruValid_value_4_0; // @[Decode.scala 212:28]
- assign io_bru_fwd = io_inst_brchFwd; // @[Decode.scala 213:14]
- assign io_bru_op = {io_bru_op_hi,io_bru_op_lo}; // @[Decode.scala 214:22]
- assign io_bru_pc = io_inst_addr; // @[Decode.scala 215:13]
- assign io_bru_target = io_inst_addr + _io_bru_target_T_1; // @[Decode.scala 216:33]
- assign io_bru_link = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_csr_op = 3'h0; // @[Decode.scala 244:22]
- assign io_lsu_valid = decodeEn & lsuValid_value_3_0; // @[Decode.scala 254:28]
- assign io_lsu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_lsu_op = {io_lsu_op_hi,io_lsu_op_lo}; // @[Decode.scala 257:22]
- assign io_mlu_valid = decodeEn & mluValid_value_3_0; // @[Decode.scala 277:28]
- assign io_mlu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_mlu_op = {io_mlu_op_hi,io_mlu_op_lo}; // @[Decode.scala 279:22]
- assign io_dvu_op = 4'h0; // @[Decode.scala 297:22]
- assign io_vinst_valid = decodeEn & vinstValid_value_2_0; // @[Decode.scala 311:30]
- assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_vinst_inst = io_inst_inst; // @[Decode.scala 313:17]
- assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 314:26]
- assign io_serializeOut_mul = io_serializeIn_mul | mluValid_value_3_0; // @[Decode.scala 388:46]
- assign io_serializeOut_jump = io_serializeIn_jump | d_io_jal | d_io_jalr; // @[Decode.scala 389:59]
- assign io_serializeOut_brcond = _io_serializeOut_brcond_T | d_io_bne | d_io_blt | d_io_bge | d_io_bltu | d_io_bgeu; // @[Decode.scala 393:65]
- assign d_clock = clock;
- assign d_reset = reset;
- assign d_io_addr = io_inst_addr; // @[Decode.scala 108:13]
- assign d_io_inst = io_inst_inst; // @[Decode.scala 109:13]
-endmodule
-module DecodedInstruction_3(
- input clock,
- input reset,
- input [31:0] io_addr,
- input [31:0] io_inst,
- output [31:0] io_imm12,
- output [31:0] io_imm20,
- output [31:0] io_immjal,
- output [31:0] io_immbr,
- output [31:0] io_immst,
- output io_lui,
- output io_auipc,
- output io_jal,
- output io_jalr,
- output io_beq,
- output io_bne,
- output io_blt,
- output io_bge,
- output io_bltu,
- output io_bgeu,
- output io_csrrw,
- output io_csrrs,
- output io_csrrc,
- output io_lb,
- output io_lh,
- output io_lw,
- output io_lbu,
- output io_lhu,
- output io_sb,
- output io_sh,
- output io_sw,
- output io_fence,
- output io_addi,
- output io_slti,
- output io_sltiu,
- output io_xori,
- output io_ori,
- output io_andi,
- output io_slli,
- output io_srli,
- output io_srai,
- output io_add,
- output io_sub,
- output io_slt,
- output io_sltu,
- output io_xor,
- output io_or,
- output io_and,
- output io_sll,
- output io_srl,
- output io_sra,
- output io_mul,
- output io_mulh,
- output io_mulhsu,
- output io_mulhu,
- output io_mulhr,
- output io_mulhsur,
- output io_mulhur,
- output io_dmulh,
- output io_dmulhr,
- output io_div,
- output io_divu,
- output io_rem,
- output io_remu,
- output io_clz,
- output io_ctz,
- output io_pcnt,
- output io_min,
- output io_minu,
- output io_max,
- output io_maxu,
- output io_getvl,
- output io_getmaxvl,
- output io_vld,
- output io_vst,
- output io_viop,
- output io_ebreak,
- output io_ecall,
- output io_eexit,
- output io_eyield,
- output io_ectxsw,
- output io_mpause,
- output io_mret,
- output io_undef,
- output io_fencei,
- output io_flushat,
- output io_flushall,
- output io_slog
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
-`endif // RANDOMIZE_REG_INIT
- wire [19:0] _io_imm12_T_2 = io_inst[31] ? 20'hfffff : 20'h0; // @[Bitwise.scala 74:12]
- wire [11:0] _io_immjal_T_2 = io_inst[31] ? 12'hfff : 12'h0; // @[Bitwise.scala 74:12]
- wire [10:0] io_immjal_lo = {io_inst[30:21],1'h0}; // @[Cat.scala 31:58]
- wire [20:0] io_immjal_hi = {_io_immjal_T_2,io_inst[19:12],io_inst[20]}; // @[Cat.scala 31:58]
- wire [4:0] io_immbr_lo = {io_inst[11:8],1'h0}; // @[Cat.scala 31:58]
- wire [26:0] io_immbr_hi = {_io_imm12_T_2,io_inst[7],io_inst[30:25]}; // @[Cat.scala 31:58]
- wire [26:0] io_immst_hi = {_io_imm12_T_2,io_inst[31:25]}; // @[Cat.scala 31:58]
- wire io_lui_bit_1 = io_inst[30]; // @[Library.scala 332:23]
- wire io_lui_bit_2 = io_inst[29]; // @[Library.scala 332:23]
- wire io_lui_bit_3 = io_inst[28]; // @[Library.scala 332:23]
- wire io_lui_bit_4 = io_inst[27]; // @[Library.scala 332:23]
- wire io_lui_bit_5 = io_inst[26]; // @[Library.scala 332:23]
- wire io_lui_bit_6 = io_inst[25]; // @[Library.scala 332:23]
- wire io_lui_bit_7 = io_inst[24]; // @[Library.scala 332:23]
- wire io_lui_bit_8 = io_inst[23]; // @[Library.scala 332:23]
- wire io_lui_bit_9 = io_inst[22]; // @[Library.scala 332:23]
- wire io_lui_bit_10 = io_inst[21]; // @[Library.scala 332:23]
- wire io_lui_bit_12 = io_inst[19]; // @[Library.scala 332:23]
- wire io_lui_bit_13 = io_inst[18]; // @[Library.scala 332:23]
- wire io_lui_bit_14 = io_inst[17]; // @[Library.scala 332:23]
- wire io_lui_bit_15 = io_inst[16]; // @[Library.scala 332:23]
- wire io_lui_bit_16 = io_inst[15]; // @[Library.scala 332:23]
- wire io_lui_bit_17 = io_inst[14]; // @[Library.scala 332:23]
- wire io_lui_bit_18 = io_inst[13]; // @[Library.scala 332:23]
- wire io_lui_bit_19 = io_inst[12]; // @[Library.scala 332:23]
- wire io_lui_bit_25 = ~io_inst[6]; // @[Library.scala 326:19]
- wire io_lui_bit_26 = io_inst[5]; // @[Library.scala 329:23]
- wire io_lui_bit_27 = io_inst[4]; // @[Library.scala 329:23]
- wire _io_lui_T_2 = io_lui_bit_25 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire io_lui_bit_28 = ~io_inst[3]; // @[Library.scala 326:19]
- wire _io_lui_T_3 = _io_lui_T_2 & io_lui_bit_28; // @[Library.scala 327:48]
- wire io_lui_bit_29 = io_inst[2]; // @[Library.scala 329:23]
- wire io_lui_bit_30 = io_inst[1]; // @[Library.scala 329:23]
- wire io_lui_bit_31 = io_inst[0]; // @[Library.scala 329:23]
- wire io_auipc_bit_26 = ~io_lui_bit_26; // @[Library.scala 326:19]
- wire _io_auipc_T_1 = io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_auipc_T_2 = _io_auipc_T_1 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_auipc_T_3 = _io_auipc_T_2 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_jal_T_1 = io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire io_jal_bit_27 = ~io_lui_bit_27; // @[Library.scala 326:19]
- wire _io_jal_T_2 = _io_jal_T_1 & io_jal_bit_27; // @[Library.scala 327:48]
- wire io_jalr_bit_17 = ~io_lui_bit_17; // @[Library.scala 326:19]
- wire io_jalr_bit_18 = ~io_lui_bit_18; // @[Library.scala 326:19]
- wire _io_jalr_T_1 = io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire io_jalr_bit_19 = ~io_lui_bit_19; // @[Library.scala 326:19]
- wire _io_jalr_T_2 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_jalr_T_4 = _io_jalr_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_jalr_T_6 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28; // @[Library.scala 327:48]
- wire io_beq_bit_29 = ~io_lui_bit_29; // @[Library.scala 326:19]
- wire _io_beq_T_7 = _io_jalr_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bne_T_2 = _io_jalr_T_1 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_bne_T_4 = _io_jalr_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bne_T_7 = _io_bne_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_blt_T_1 = io_lui_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_blt_T_2 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_blt_T_4 = _io_blt_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_blt_T_7 = _io_blt_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bge_T_2 = _io_blt_T_1 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_bge_T_4 = _io_blt_T_1 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bge_T_7 = _io_bge_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bltu_T_1 = io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_bltu_T_2 = _io_bltu_T_1 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_bltu_T_4 = _io_bltu_T_2 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bltu_T_7 = _io_bltu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_bgeu_T_2 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_bgeu_T_4 = io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19 & io_inst[6] & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_bgeu_T_7 = _io_bgeu_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lb_T_3 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_lb_T_4 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_lb_T_7 = io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
- & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lh_T_3 = _io_bne_T_2 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_lh_T_7 = _io_bne_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lw_T_1 = io_jalr_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_lw_T_3 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_lw_T_4 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_lw_T_7 = _io_lw_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 &
- io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lbu_T_4 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_lbu_T_7 = io_lui_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27
- & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_lhu_T_7 = _io_bge_T_2 & io_lui_bit_25 & io_auipc_bit_26 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sb_T_4 = _io_lb_T_3 & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_sb_T_7 = _io_sb_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sh_T_4 = _io_lh_T_3 & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_sh_T_7 = _io_sh_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sw_T_4 = _io_lw_T_3 & io_lui_bit_26; // @[Library.scala 330:48]
- wire _io_sw_T_7 = _io_sw_T_4 & io_jal_bit_27 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire io_fence_bit = ~io_inst[31]; // @[Library.scala 326:19]
- wire io_fence_bit_1 = ~io_lui_bit_1; // @[Library.scala 326:19]
- wire _io_fence_T_1 = io_fence_bit & io_fence_bit_1; // @[Library.scala 327:48]
- wire io_fence_bit_2 = ~io_lui_bit_2; // @[Library.scala 326:19]
- wire _io_fence_T_2 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2; // @[Library.scala 327:48]
- wire io_fence_bit_3 = ~io_lui_bit_3; // @[Library.scala 326:19]
- wire _io_fence_T_3 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3; // @[Library.scala 327:48]
- wire io_fence_bit_12 = ~io_lui_bit_12; // @[Library.scala 326:19]
- wire io_fence_bit_13 = ~io_lui_bit_13; // @[Library.scala 326:19]
- wire io_fence_bit_14 = ~io_lui_bit_14; // @[Library.scala 326:19]
- wire io_fence_bit_15 = ~io_lui_bit_15; // @[Library.scala 326:19]
- wire io_fence_bit_16 = ~io_lui_bit_16; // @[Library.scala 326:19]
- wire _io_addi_T_5 = _io_lb_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_addi_T_7 = _io_addi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_slti_T_5 = _io_lw_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_slti_T_7 = _io_slti_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sltiu_T_2 = io_jalr_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_sltiu_T_4 = _io_sltiu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_sltiu_T_5 = _io_sltiu_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sltiu_T_7 = _io_sltiu_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_xori_T_5 = _io_lbu_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_xori_T_7 = _io_xori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_ori_T_4 = _io_bltu_T_1 & io_jalr_bit_19 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_ori_T_5 = _io_ori_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_ori_T_7 = _io_ori_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_andi_T_4 = _io_bgeu_T_2 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_andi_T_5 = _io_andi_T_4 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_andi_T_7 = _io_andi_T_5 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire io_slli_bit_4 = ~io_lui_bit_4; // @[Library.scala 326:19]
- wire _io_slli_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 327:48]
- wire io_slli_bit_5 = ~io_lui_bit_5; // @[Library.scala 326:19]
- wire _io_slli_T_5 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 327:48]
- wire io_slli_bit_6 = ~io_lui_bit_6; // @[Library.scala 326:19]
- wire _io_slli_T_6 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6; // @[Library.scala 327:48]
- wire _io_slli_T_7 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_slli_T_8 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_slli_T_9 = _io_slli_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_slli_T_10 = _io_slli_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_slli_T_11 = _io_slli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_slli_T_12 = _io_slli_T_11 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_slli_T_14 = _io_slli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_srli_T_7 = _io_slli_T_6 & io_lui_bit_17; // @[Library.scala 330:48]
- wire _io_srli_T_8 = _io_srli_T_7 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_srli_T_9 = _io_srli_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_srli_T_10 = _io_srli_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_srli_T_11 = _io_srli_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_srli_T_12 = _io_srli_T_11 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_srli_T_14 = _io_srli_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_srai_T_1 = io_fence_bit & io_lui_bit_1; // @[Library.scala 330:48]
- wire _io_srai_T_2 = _io_srai_T_1 & io_fence_bit_2; // @[Library.scala 327:48]
- wire _io_srai_T_6 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6; // @[Library.scala 327:48]
- wire _io_srai_T_7 = _io_srai_T_6 & io_lui_bit_17; // @[Library.scala 330:48]
- wire _io_srai_T_8 = _io_srai_T_7 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_srai_T_9 = _io_srai_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_srai_T_10 = _io_srai_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_srai_T_11 = _io_srai_T_9 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_srai_T_12 = _io_srai_T_11 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_srai_T_14 = _io_srai_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_add_T_10 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5
- & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_add_T_12 = _io_add_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_add_T_14 = _io_add_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sub_T_10 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 &
- io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_sub_T_12 = _io_sub_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sub_T_14 = _io_sub_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_slt_T_8 = _io_slli_T_7 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_slt_T_10 = _io_slt_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_slt_T_12 = _io_slt_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_slt_T_14 = _io_slt_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sltu_T_9 = _io_slli_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_sltu_T_10 = _io_sltu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_sltu_T_12 = _io_sltu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sltu_T_14 = _io_sltu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_xor_T_10 = _io_srli_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_xor_T_12 = _io_xor_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_xor_T_14 = _io_xor_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_or_T_8 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_or_T_10 = _io_or_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_or_T_12 = _io_or_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_or_T_14 = _io_or_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_and_T_9 = _io_slli_T_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_and_T_10 = _io_and_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_and_T_12 = _io_and_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_and_T_14 = _io_and_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sll_T_12 = _io_slli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sll_T_14 = _io_sll_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_srl_T_12 = _io_srli_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_srl_T_14 = _io_srl_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_sra_T_12 = _io_srai_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_sra_T_14 = _io_sra_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mul_T_6 = _io_slli_T_5 & io_lui_bit_6; // @[Library.scala 330:48]
- wire _io_mul_T_7 = _io_mul_T_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_mul_T_8 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_mul_T_10 = _io_mul_T_6 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mul_T_12 = _io_mul_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mul_T_14 = _io_mul_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulh_T_9 = _io_mul_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulh_T_10 = _io_mulh_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulh_T_12 = _io_mulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulh_T_14 = _io_mulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhsu_T_8 = _io_mul_T_7 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_mulhsu_T_10 = _io_mulhsu_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhsu_T_12 = _io_mulhsu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhsu_T_14 = _io_mulhsu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhu_T_9 = _io_mul_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulhu_T_10 = _io_mulhu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhu_T_12 = _io_mulhu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhu_T_14 = _io_mulhu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhr_T_2 = _io_fence_T_1 & io_lui_bit_2; // @[Library.scala 330:48]
- wire _io_mulhr_T_4 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4; // @[Library.scala 327:48]
- wire _io_mulhr_T_5 = _io_mulhr_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5; // @[Library.scala 327:48]
- wire _io_mulhr_T_6 = _io_mulhr_T_5 & io_lui_bit_6; // @[Library.scala 330:48]
- wire _io_mulhr_T_7 = _io_mulhr_T_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_mulhr_T_8 = _io_mulhr_T_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_mulhr_T_9 = _io_mulhr_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulhr_T_10 = _io_mulhr_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhr_T_12 = _io_mulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhr_T_14 = _io_mulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhsur_T_8 = _io_mulhr_T_7 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_mulhsur_T_10 = _io_mulhsur_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhsur_T_12 = _io_mulhsur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhsur_T_14 = _io_mulhsur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_mulhur_T_9 = _io_mulhr_T_7 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_mulhur_T_10 = _io_mulhur_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_mulhur_T_12 = _io_mulhur_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_mulhur_T_14 = _io_mulhur_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_dmulh_T_5 = _io_slli_T_4 & io_lui_bit_5; // @[Library.scala 330:48]
- wire _io_dmulh_T_8 = _io_dmulh_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_dmulh_T_9 = _io_dmulh_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_dmulh_T_10 = _io_dmulh_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_dmulh_T_12 = _io_dmulh_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_dmulh_T_14 = _io_dmulh_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_dmulhr_T_5 = _io_mulhr_T_4 & io_lui_bit_5; // @[Library.scala 330:48]
- wire _io_dmulhr_T_8 = _io_dmulhr_T_5 & io_slli_bit_6 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_dmulhr_T_9 = _io_dmulhr_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_dmulhr_T_10 = _io_dmulhr_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_dmulhr_T_12 = _io_dmulhr_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_dmulhr_T_14 = _io_dmulhr_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_clz_T_2 = io_fence_bit & io_lui_bit_1 & io_lui_bit_2; // @[Library.scala 330:48]
- wire io_clz_bit_7 = ~io_lui_bit_7; // @[Library.scala 326:19]
- wire io_clz_bit_8 = ~io_lui_bit_8; // @[Library.scala 326:19]
- wire io_clz_bit_9 = ~io_lui_bit_9; // @[Library.scala 326:19]
- wire _io_clz_T_9 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
- io_clz_bit_8 & io_clz_bit_9; // @[Library.scala 327:48]
- wire io_clz_bit_10 = ~io_lui_bit_10; // @[Library.scala 326:19]
- wire _io_clz_T_10 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
- io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10; // @[Library.scala 327:48]
- wire io_clz_bit_11 = ~io_inst[20]; // @[Library.scala 326:19]
- wire _io_clz_T_13 = _io_clz_T_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 &
- io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_clz_T_14 = _io_clz_T_13 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_clz_T_16 = _io_clz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_clz_T_17 = _io_clz_T_16 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_clz_T_19 = _io_clz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_ctz_T_11 = _io_clz_T_10 & io_inst[20]; // @[Library.scala 330:48]
- wire _io_ctz_T_13 = _io_ctz_T_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_ctz_T_14 = _io_ctz_T_13 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_ctz_T_16 = _io_ctz_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_ctz_T_17 = _io_ctz_T_16 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_ctz_T_19 = _io_ctz_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_pcnt_T_10 = _io_clz_T_9 & io_lui_bit_10; // @[Library.scala 330:48]
- wire _io_pcnt_T_13 = _io_pcnt_T_10 & io_clz_bit_11 & io_jalr_bit_17 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_pcnt_T_14 = _io_pcnt_T_13 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_pcnt_T_16 = _io_pcnt_T_14 & io_lui_bit_25 & io_auipc_bit_26; // @[Library.scala 327:48]
- wire _io_pcnt_T_17 = _io_pcnt_T_16 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_pcnt_T_19 = _io_pcnt_T_17 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_min_T_4 = _io_fence_T_3 & io_lui_bit_4; // @[Library.scala 330:48]
- wire _io_min_T_5 = _io_min_T_4 & io_slli_bit_5; // @[Library.scala 327:48]
- wire _io_min_T_7 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17; // @[Library.scala 330:48]
- wire _io_min_T_8 = _io_min_T_7 & io_jalr_bit_18; // @[Library.scala 327:48]
- wire _io_min_T_10 = _io_min_T_7 & io_jalr_bit_18 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_min_T_12 = _io_min_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_min_T_14 = _io_min_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_minu_T_9 = _io_min_T_8 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_minu_T_10 = _io_minu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_minu_T_12 = _io_minu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_minu_T_14 = _io_minu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_max_T_8 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18; // @[Library.scala 330:48]
- wire _io_max_T_10 = _io_max_T_8 & io_jalr_bit_19 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_max_T_12 = _io_max_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_max_T_14 = _io_max_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_maxu_T_9 = _io_min_T_5 & io_lui_bit_6 & io_lui_bit_17 & io_lui_bit_18 & io_lui_bit_19; // @[Library.scala 330:48]
- wire _io_maxu_T_10 = _io_maxu_T_9 & io_lui_bit_25; // @[Library.scala 327:48]
- wire _io_maxu_T_12 = _io_maxu_T_10 & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_maxu_T_14 = _io_maxu_T_12 & io_lui_bit_28 & io_beq_bit_29; // @[Library.scala 327:48]
- wire _io_getvl_T_3 = _io_fence_T_2 & io_lui_bit_3; // @[Library.scala 330:48]
- wire _io_getvl_T_6 = _io_getvl_T_3 & io_jalr_bit_17 & io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_getvl_T_9 = _io_getvl_T_6 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_getvl_T_10 = _io_getvl_T_9 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_getvl_T_13 = _io_getvl_T_10 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _io_getvl_T_15 = io_inst[26:25] != 2'h3; // @[Decode.scala 584:89]
- wire _io_getmaxvl_T_16 = _io_getvl_T_3 & io_clz_bit_7 & io_clz_bit_8 & io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11
- & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17 &
- io_jalr_bit_18 & io_jalr_bit_19; // @[Library.scala 327:48]
- wire _io_getmaxvl_T_19 = _io_getmaxvl_T_16 & io_inst[6] & io_lui_bit_26 & io_lui_bit_27; // @[Library.scala 330:48]
- wire _io_getmaxvl_T_20 = _io_getmaxvl_T_19 & io_lui_bit_28; // @[Library.scala 327:48]
- wire _io_getmaxvl_T_23 = _io_getmaxvl_T_20 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _io_vld_T_4 = io_fence_bit & io_fence_bit_1 & io_fence_bit_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_vst_T_4 = _io_mulhr_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_vst_T_9 = _io_vst_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _io_vst_T_14 = _io_clz_T_2 & io_slli_bit_6 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _io_vst_T_19 = _io_vst_T_14 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _vconv_T_3 = _io_srai_T_2 & io_lui_bit_3; // @[Library.scala 330:48]
- wire _vconv_T_17 = _vconv_T_3 & io_slli_bit_4 & io_slli_bit_5 & io_slli_bit_6 & io_clz_bit_7 & io_clz_bit_8 &
- io_clz_bit_9 & io_clz_bit_10 & io_clz_bit_11 & io_fence_bit_12 & io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15
- & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire vconv = _vconv_T_17 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire _vdup_T_11 = _io_srai_T_1 & io_fence_bit_2 & io_fence_bit_3 & io_slli_bit_4 & io_slli_bit_6 & io_fence_bit_12 &
- io_fence_bit_13 & io_fence_bit_14 & io_fence_bit_15 & io_fence_bit_16 & io_jalr_bit_17; // @[Library.scala 327:48]
- wire _vdup_T_16 = _vdup_T_11 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- wire vdup = _vdup_T_16 & io_inst[13:12] <= 2'h2; // @[Decode.scala 597:72]
- wire vdupi = vdup & io_slli_bit_5; // @[Decode.scala 598:20]
- wire _io_viop_T_3 = io_inst[1:0] == 2'h1; // @[Decode.scala 602:22]
- wire _io_viop_T_4 = ~io_lui_bit_31 | _io_viop_T_3; // @[Decode.scala 601:28]
- wire _io_viop_T_5 = _io_viop_T_4 | vconv; // @[Decode.scala 602:30]
- wire [9:0] decoded_lo_lo_hi = {io_minu,io_max,io_maxu,io_viop,io_vld,io_vst,io_getvl,io_getmaxvl,io_ebreak,io_ecall}; // @[Cat.scala 31:58]
- wire [18:0] decoded_lo_lo = {decoded_lo_lo_hi,io_eexit,io_eyield,io_ectxsw,io_mpause,io_mret,io_fencei,io_flushat,
- io_flushall,io_slog}; // @[Cat.scala 31:58]
- wire [9:0] decoded_lo_hi_hi = {io_srl,io_sra,io_mul,io_mulh,io_mulhsu,io_mulhu,io_mulhr,io_mulhsur,io_mulhur,io_dmulh}
- ; // @[Cat.scala 31:58]
- wire [18:0] decoded_lo_hi = {decoded_lo_hi_hi,io_dmulhr,io_div,io_divu,io_rem,io_remu,io_clz,io_ctz,io_pcnt,io_min}; // @[Cat.scala 31:58]
- wire [9:0] decoded_hi_lo_hi = {io_sw,io_fence,io_addi,io_slti,io_sltiu,io_xori,io_ori,io_andi,io_add,io_sub}; // @[Cat.scala 31:58]
- wire [18:0] decoded_hi_lo = {decoded_hi_lo_hi,io_slt,io_sltu,io_xor,io_or,io_and,io_slli,io_srli,io_srai,io_sll}; // @[Cat.scala 31:58]
- wire [9:0] decoded_hi_hi_lo = {io_csrrw,io_csrrs,io_csrrc,io_lb,io_lh,io_lw,io_lbu,io_lhu,io_sb,io_sh}; // @[Cat.scala 31:58]
- wire [9:0] decoded_hi_hi_hi = {io_lui,io_auipc,io_jal,io_jalr,io_beq,io_bne,io_blt,io_bge,io_bltu,io_bgeu}; // @[Cat.scala 31:58]
- wire [76:0] decoded = {decoded_hi_hi_hi,decoded_hi_hi_lo,decoded_hi_lo,decoded_lo_hi,decoded_lo_lo}; // @[Cat.scala 31:58]
- wire io_undef_value__38 = decoded[76]; // @[Library.scala 196:26]
- wire io_undef_value__0 = decoded[0] | decoded[1]; // @[Library.scala 208:39]
- wire io_undef_value__1 = decoded[2] | decoded[3]; // @[Library.scala 208:39]
- wire io_undef_value__2 = decoded[4] | decoded[5]; // @[Library.scala 208:39]
- wire io_undef_value__3 = decoded[6] | decoded[7]; // @[Library.scala 208:39]
- wire io_undef_value__4 = decoded[8] | decoded[9]; // @[Library.scala 208:39]
- wire io_undef_value__5 = decoded[10] | decoded[11]; // @[Library.scala 208:39]
- wire io_undef_value__6 = decoded[12] | decoded[13]; // @[Library.scala 208:39]
- wire io_undef_value__7 = decoded[14] | decoded[15]; // @[Library.scala 208:39]
- wire io_undef_value__8 = decoded[16] | decoded[17]; // @[Library.scala 208:39]
- wire io_undef_value__9 = decoded[18] | decoded[19]; // @[Library.scala 208:39]
- wire io_undef_value__10 = decoded[20] | decoded[21]; // @[Library.scala 208:39]
- wire io_undef_value__11 = decoded[22] | decoded[23]; // @[Library.scala 208:39]
- wire io_undef_value__12 = decoded[24] | decoded[25]; // @[Library.scala 208:39]
- wire io_undef_value__13 = decoded[26] | decoded[27]; // @[Library.scala 208:39]
- wire io_undef_value__14 = decoded[28] | decoded[29]; // @[Library.scala 208:39]
- wire io_undef_value__15 = decoded[30] | decoded[31]; // @[Library.scala 208:39]
- wire io_undef_value__16 = decoded[32] | decoded[33]; // @[Library.scala 208:39]
- wire io_undef_value__17 = decoded[34] | decoded[35]; // @[Library.scala 208:39]
- wire io_undef_value__18 = decoded[36] | decoded[37]; // @[Library.scala 208:39]
- wire io_undef_value__19 = decoded[38] | decoded[39]; // @[Library.scala 208:39]
- wire io_undef_value__20 = decoded[40] | decoded[41]; // @[Library.scala 208:39]
- wire io_undef_value__21 = decoded[42] | decoded[43]; // @[Library.scala 208:39]
- wire io_undef_value__22 = decoded[44] | decoded[45]; // @[Library.scala 208:39]
- wire io_undef_value__23 = decoded[46] | decoded[47]; // @[Library.scala 208:39]
- wire io_undef_value__24 = decoded[48] | decoded[49]; // @[Library.scala 208:39]
- wire io_undef_value__25 = decoded[50] | decoded[51]; // @[Library.scala 208:39]
- wire io_undef_value__26 = decoded[52] | decoded[53]; // @[Library.scala 208:39]
- wire io_undef_value__27 = decoded[54] | decoded[55]; // @[Library.scala 208:39]
- wire io_undef_value__28 = decoded[56] | decoded[57]; // @[Library.scala 208:39]
- wire io_undef_value__29 = decoded[58] | decoded[59]; // @[Library.scala 208:39]
- wire io_undef_value__30 = decoded[60] | decoded[61]; // @[Library.scala 208:39]
- wire io_undef_value__31 = decoded[62] | decoded[63]; // @[Library.scala 208:39]
- wire io_undef_value__32 = decoded[64] | decoded[65]; // @[Library.scala 208:39]
- wire io_undef_value__33 = decoded[66] | decoded[67]; // @[Library.scala 208:39]
- wire io_undef_value__34 = decoded[68] | decoded[69]; // @[Library.scala 208:39]
- wire io_undef_value__35 = decoded[70] | decoded[71]; // @[Library.scala 208:39]
- wire io_undef_value__36 = decoded[72] | decoded[73]; // @[Library.scala 208:39]
- wire io_undef_value__37 = decoded[74] | decoded[75]; // @[Library.scala 208:39]
- wire io_undef_value_1_0 = io_undef_value__0 | io_undef_value__1; // @[Library.scala 208:39]
- wire io_undef_value_1_1 = io_undef_value__2 | io_undef_value__3; // @[Library.scala 208:39]
- wire io_undef_value_1_2 = io_undef_value__4 | io_undef_value__5; // @[Library.scala 208:39]
- wire io_undef_value_1_3 = io_undef_value__6 | io_undef_value__7; // @[Library.scala 208:39]
- wire io_undef_value_1_4 = io_undef_value__8 | io_undef_value__9; // @[Library.scala 208:39]
- wire io_undef_value_1_5 = io_undef_value__10 | io_undef_value__11; // @[Library.scala 208:39]
- wire io_undef_value_1_6 = io_undef_value__12 | io_undef_value__13; // @[Library.scala 208:39]
- wire io_undef_value_1_7 = io_undef_value__14 | io_undef_value__15; // @[Library.scala 208:39]
- wire io_undef_value_1_8 = io_undef_value__16 | io_undef_value__17; // @[Library.scala 208:39]
- wire io_undef_value_1_9 = io_undef_value__18 | io_undef_value__19; // @[Library.scala 208:39]
- wire io_undef_value_1_10 = io_undef_value__20 | io_undef_value__21; // @[Library.scala 208:39]
- wire io_undef_value_1_11 = io_undef_value__22 | io_undef_value__23; // @[Library.scala 208:39]
- wire io_undef_value_1_12 = io_undef_value__24 | io_undef_value__25; // @[Library.scala 208:39]
- wire io_undef_value_1_13 = io_undef_value__26 | io_undef_value__27; // @[Library.scala 208:39]
- wire io_undef_value_1_14 = io_undef_value__28 | io_undef_value__29; // @[Library.scala 208:39]
- wire io_undef_value_1_15 = io_undef_value__30 | io_undef_value__31; // @[Library.scala 208:39]
- wire io_undef_value_1_16 = io_undef_value__32 | io_undef_value__33; // @[Library.scala 208:39]
- wire io_undef_value_1_17 = io_undef_value__34 | io_undef_value__35; // @[Library.scala 208:39]
- wire io_undef_value_1_18 = io_undef_value__36 | io_undef_value__37; // @[Library.scala 208:39]
- wire io_undef_value_2_0 = io_undef_value_1_0 | io_undef_value_1_1; // @[Library.scala 208:39]
- wire io_undef_value_2_1 = io_undef_value_1_2 | io_undef_value_1_3; // @[Library.scala 208:39]
- wire io_undef_value_2_2 = io_undef_value_1_4 | io_undef_value_1_5; // @[Library.scala 208:39]
- wire io_undef_value_2_3 = io_undef_value_1_6 | io_undef_value_1_7; // @[Library.scala 208:39]
- wire io_undef_value_2_4 = io_undef_value_1_8 | io_undef_value_1_9; // @[Library.scala 208:39]
- wire io_undef_value_2_5 = io_undef_value_1_10 | io_undef_value_1_11; // @[Library.scala 208:39]
- wire io_undef_value_2_6 = io_undef_value_1_12 | io_undef_value_1_13; // @[Library.scala 208:39]
- wire io_undef_value_2_7 = io_undef_value_1_14 | io_undef_value_1_15; // @[Library.scala 208:39]
- wire io_undef_value_2_8 = io_undef_value_1_16 | io_undef_value_1_17; // @[Library.scala 208:39]
- wire io_undef_value_2_9 = io_undef_value_1_18 | io_undef_value__38; // @[Library.scala 208:39]
- wire io_undef_value_3_0 = io_undef_value_2_0 | io_undef_value_2_1; // @[Library.scala 208:39]
- wire io_undef_value_3_1 = io_undef_value_2_2 | io_undef_value_2_3; // @[Library.scala 208:39]
- wire io_undef_value_3_2 = io_undef_value_2_4 | io_undef_value_2_5; // @[Library.scala 208:39]
- wire io_undef_value_3_3 = io_undef_value_2_6 | io_undef_value_2_7; // @[Library.scala 208:39]
- wire io_undef_value_3_4 = io_undef_value_2_8 | io_undef_value_2_9; // @[Library.scala 208:39]
- wire io_undef_value_4_0 = io_undef_value_3_0 | io_undef_value_3_1; // @[Library.scala 208:39]
- wire io_undef_value_4_1 = io_undef_value_3_2 | io_undef_value_3_3; // @[Library.scala 208:39]
- wire io_undef_value_5_0 = io_undef_value_4_0 | io_undef_value_4_1; // @[Library.scala 208:39]
- wire io_undef_value_6_0 = io_undef_value_5_0 | io_undef_value_3_4; // @[Library.scala 208:39]
- reg onehot_failed; // @[Decode.scala 670:30]
- wire _T_2 = ~reset; // @[Decode.scala 671:9]
- wire [1:0] _onehot_decode_T_77 = decoded[0] + decoded[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_79 = decoded[2] + decoded[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_81 = _onehot_decode_T_77 + _onehot_decode_T_79; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_83 = decoded[4] + decoded[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_85 = decoded[7] + decoded[8]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_1 = {{1'd0}, decoded[6]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_87 = _GEN_1 + _onehot_decode_T_85; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_89 = _onehot_decode_T_83 + _onehot_decode_T_87[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_91 = _onehot_decode_T_81 + _onehot_decode_T_89; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_93 = decoded[9] + decoded[10]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_95 = decoded[12] + decoded[13]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_2 = {{1'd0}, decoded[11]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_97 = _GEN_2 + _onehot_decode_T_95; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_99 = _onehot_decode_T_93 + _onehot_decode_T_97[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_101 = decoded[14] + decoded[15]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_103 = decoded[17] + decoded[18]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_3 = {{1'd0}, decoded[16]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_105 = _GEN_3 + _onehot_decode_T_103; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_107 = _onehot_decode_T_101 + _onehot_decode_T_105[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_109 = _onehot_decode_T_99 + _onehot_decode_T_107; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_111 = _onehot_decode_T_91 + _onehot_decode_T_109; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_113 = decoded[19] + decoded[20]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_115 = decoded[21] + decoded[22]; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_117 = _onehot_decode_T_113 + _onehot_decode_T_115; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_119 = decoded[23] + decoded[24]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_121 = decoded[26] + decoded[27]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_4 = {{1'd0}, decoded[25]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_123 = _GEN_4 + _onehot_decode_T_121; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_125 = _onehot_decode_T_119 + _onehot_decode_T_123[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_127 = _onehot_decode_T_117 + _onehot_decode_T_125; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_129 = decoded[28] + decoded[29]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_131 = decoded[31] + decoded[32]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_5 = {{1'd0}, decoded[30]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_133 = _GEN_5 + _onehot_decode_T_131; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_135 = _onehot_decode_T_129 + _onehot_decode_T_133[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_137 = decoded[33] + decoded[34]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_139 = decoded[36] + decoded[37]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_6 = {{1'd0}, decoded[35]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_141 = _GEN_6 + _onehot_decode_T_139; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_143 = _onehot_decode_T_137 + _onehot_decode_T_141[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_145 = _onehot_decode_T_135 + _onehot_decode_T_143; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_147 = _onehot_decode_T_127 + _onehot_decode_T_145; // @[Bitwise.scala 48:55]
- wire [5:0] _onehot_decode_T_149 = _onehot_decode_T_111 + _onehot_decode_T_147; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_151 = decoded[38] + decoded[39]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_153 = decoded[40] + decoded[41]; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_155 = _onehot_decode_T_151 + _onehot_decode_T_153; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_157 = decoded[42] + decoded[43]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_159 = decoded[45] + decoded[46]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_7 = {{1'd0}, decoded[44]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_161 = _GEN_7 + _onehot_decode_T_159; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_163 = _onehot_decode_T_157 + _onehot_decode_T_161[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_165 = _onehot_decode_T_155 + _onehot_decode_T_163; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_167 = decoded[47] + decoded[48]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_169 = decoded[50] + decoded[51]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_8 = {{1'd0}, decoded[49]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_171 = _GEN_8 + _onehot_decode_T_169; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_173 = _onehot_decode_T_167 + _onehot_decode_T_171[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_175 = decoded[52] + decoded[53]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_177 = decoded[55] + decoded[56]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_9 = {{1'd0}, decoded[54]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_179 = _GEN_9 + _onehot_decode_T_177; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_181 = _onehot_decode_T_175 + _onehot_decode_T_179[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_183 = _onehot_decode_T_173 + _onehot_decode_T_181; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_185 = _onehot_decode_T_165 + _onehot_decode_T_183; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_187 = decoded[57] + decoded[58]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_189 = decoded[60] + decoded[61]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_10 = {{1'd0}, decoded[59]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_191 = _GEN_10 + _onehot_decode_T_189; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_193 = _onehot_decode_T_187 + _onehot_decode_T_191[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_195 = decoded[62] + decoded[63]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_197 = decoded[65] + decoded[66]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_11 = {{1'd0}, decoded[64]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_199 = _GEN_11 + _onehot_decode_T_197; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_201 = _onehot_decode_T_195 + _onehot_decode_T_199[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_203 = _onehot_decode_T_193 + _onehot_decode_T_201; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_205 = decoded[67] + decoded[68]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_207 = decoded[70] + decoded[71]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_12 = {{1'd0}, decoded[69]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_209 = _GEN_12 + _onehot_decode_T_207; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_211 = _onehot_decode_T_205 + _onehot_decode_T_209[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_213 = decoded[72] + decoded[73]; // @[Bitwise.scala 48:55]
- wire [1:0] _onehot_decode_T_215 = decoded[75] + io_undef_value__38; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_13 = {{1'd0}, decoded[74]}; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_217 = _GEN_13 + _onehot_decode_T_215; // @[Bitwise.scala 48:55]
- wire [2:0] _onehot_decode_T_219 = _onehot_decode_T_213 + _onehot_decode_T_217[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _onehot_decode_T_221 = _onehot_decode_T_211 + _onehot_decode_T_219; // @[Bitwise.scala 48:55]
- wire [4:0] _onehot_decode_T_223 = _onehot_decode_T_203 + _onehot_decode_T_221; // @[Bitwise.scala 48:55]
- wire [5:0] _onehot_decode_T_225 = _onehot_decode_T_185 + _onehot_decode_T_223; // @[Bitwise.scala 48:55]
- wire [6:0] onehot_decode = _onehot_decode_T_149 + _onehot_decode_T_225; // @[Bitwise.scala 48:55]
- wire [6:0] _GEN_14 = {{6'd0}, io_undef}; // @[Decode.scala 674:24]
- wire [6:0] _T_5 = onehot_decode + _GEN_14; // @[Decode.scala 674:24]
- wire _T_6 = _T_5 != 7'h1; // @[Decode.scala 674:36]
- assign io_imm12 = {_io_imm12_T_2,io_inst[31:20]}; // @[Cat.scala 31:58]
- assign io_imm20 = {io_inst[31:12],12'h0}; // @[Cat.scala 31:58]
- assign io_immjal = {io_immjal_hi,io_immjal_lo}; // @[Cat.scala 31:58]
- assign io_immbr = {io_immbr_hi,io_immbr_lo}; // @[Cat.scala 31:58]
- assign io_immst = {io_immst_hi,io_inst[11:7]}; // @[Cat.scala 31:58]
- assign io_lui = _io_lui_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_auipc = _io_auipc_T_3 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_jal = _io_jal_T_2 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_jalr = _io_jalr_T_6 & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_beq = _io_beq_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bne = _io_bne_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_blt = _io_blt_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bge = _io_bge_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bltu = _io_bltu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_bgeu = _io_bgeu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_csrrw = 1'h0; // @[Decode.scala 624:14]
- assign io_csrrs = 1'h0; // @[Decode.scala 625:14]
- assign io_csrrc = 1'h0; // @[Decode.scala 626:14]
- assign io_lb = _io_lb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lh = _io_lh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lw = _io_lw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lbu = _io_lbu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_lhu = _io_lhu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sb = _io_sb_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sh = _io_sh_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sw = _io_sw_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_fence = 1'h0; // @[Decode.scala 641:17]
- assign io_addi = _io_addi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_slti = _io_slti_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sltiu = _io_sltiu_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_xori = _io_xori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_ori = _io_ori_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_andi = _io_andi_T_7 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_slli = _io_slli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_srli = _io_srli_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_srai = _io_srai_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_add = _io_add_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sub = _io_sub_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_slt = _io_slt_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sltu = _io_sltu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_xor = _io_xor_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_or = _io_or_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_and = _io_and_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sll = _io_sll_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_srl = _io_srl_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_sra = _io_sra_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mul = _io_mul_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulh = _io_mulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhsu = _io_mulhsu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhu = _io_mulhu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhr = _io_mulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhsur = _io_mulhsur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_mulhur = _io_mulhur_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_dmulh = _io_dmulh_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_dmulhr = _io_dmulhr_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_div = 1'h0; // @[Decode.scala 628:12]
- assign io_divu = 1'h0; // @[Decode.scala 629:13]
- assign io_rem = 1'h0; // @[Decode.scala 630:12]
- assign io_remu = 1'h0; // @[Decode.scala 631:13]
- assign io_clz = _io_clz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_ctz = _io_ctz_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_pcnt = _io_pcnt_T_19 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_min = _io_min_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_minu = _io_minu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_max = _io_max_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_maxu = _io_maxu_T_14 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_getvl = _io_getvl_T_13 & io_inst[26:25] != 2'h3 & (io_inst[24:20] != 5'h0 | io_inst[19:15] != 5'h0); // @[Decode.scala 584:97]
- assign io_getmaxvl = _io_getmaxvl_T_23 & _io_getvl_T_15; // @[Decode.scala 585:76]
- assign io_vld = _io_vld_T_4 & io_lui_bit_27 & io_inst[3] & io_lui_bit_29 & io_lui_bit_30 & io_lui_bit_31; // @[Library.scala 330:48]
- assign io_vst = _io_vst_T_9 | _io_vst_T_19; // @[Decode.scala 590:71]
- assign io_viop = _io_viop_T_5 | vdupi; // @[Decode.scala 603:20]
- assign io_ebreak = 1'h0; // @[Decode.scala 633:15]
- assign io_ecall = 1'h0; // @[Decode.scala 634:15]
- assign io_eexit = 1'h0; // @[Decode.scala 635:15]
- assign io_eyield = 1'h0; // @[Decode.scala 636:15]
- assign io_ectxsw = 1'h0; // @[Decode.scala 637:15]
- assign io_mpause = 1'h0; // @[Decode.scala 638:15]
- assign io_mret = 1'h0; // @[Decode.scala 639:15]
- assign io_undef = ~io_undef_value_6_0; // @[Decode.scala 667:15]
- assign io_fencei = 1'h0; // @[Decode.scala 642:17]
- assign io_flushat = 1'h0; // @[Decode.scala 643:17]
- assign io_flushall = 1'h0; // @[Decode.scala 644:17]
- assign io_slog = 1'h0; // @[Decode.scala 646:13]
- always @(posedge clock) begin
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~onehot_failed)) begin
- $fatal; // @[Decode.scala 671:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~onehot_failed)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Decode.scala:671 assert(!onehot_failed)\n"); // @[Decode.scala 671:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_6 & _T_2) begin
- $fwrite(32'h80000002,"[FAIL] decode inst=%x addr=%x decoded=0b%b pipeline=%d\n",io_inst,io_addr,decoded,2'h3
- ); // @[Decode.scala 676:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Decode.scala 674:45]
- onehot_failed <= 1'h0; // @[Decode.scala 675:19]
- end else begin
- onehot_failed <= _T_5 != 7'h1 | onehot_failed; // @[Decode.scala 670:30]
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- onehot_failed = _RAND_0[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- onehot_failed = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Decode_3(
- input clock,
- input reset,
- input io_halted,
- input io_inst_valid,
- output io_inst_ready,
- input [31:0] io_inst_addr,
- input [31:0] io_inst_inst,
- input io_inst_brchFwd,
- input [31:0] io_scoreboard_regd,
- input [31:0] io_scoreboard_comb,
- output io_rs1Read_valid,
- output [4:0] io_rs1Read_addr,
- output io_rs1Set_valid,
- output [31:0] io_rs1Set_value,
- output io_rs2Read_valid,
- output [4:0] io_rs2Read_addr,
- output io_rs2Set_valid,
- output [31:0] io_rs2Set_value,
- output io_rdMark_valid,
- output [4:0] io_rdMark_addr,
- output io_busRead_bypass,
- output [31:0] io_busRead_immed,
- output io_alu_valid,
- output [4:0] io_alu_addr,
- output [17:0] io_alu_op,
- output io_bru_valid,
- output io_bru_fwd,
- output [16:0] io_bru_op,
- output [31:0] io_bru_pc,
- output [31:0] io_bru_target,
- output [4:0] io_bru_link,
- output [2:0] io_csr_op,
- output io_lsu_valid,
- input io_lsu_ready,
- output [4:0] io_lsu_addr,
- output [11:0] io_lsu_op,
- output io_mlu_valid,
- output [4:0] io_mlu_addr,
- output [8:0] io_mlu_op,
- output [3:0] io_dvu_op,
- output io_vinst_valid,
- input io_vinst_ready,
- output [4:0] io_vinst_addr,
- output [31:0] io_vinst_inst,
- output [4:0] io_vinst_op,
- input io_branchTaken,
- input io_interlock,
- input io_serializeIn_mul,
- input io_serializeIn_jump,
- input io_serializeIn_brcond
-);
- wire d_clock; // @[Decode.scala 107:17]
- wire d_reset; // @[Decode.scala 107:17]
- wire [31:0] d_io_addr; // @[Decode.scala 107:17]
- wire [31:0] d_io_inst; // @[Decode.scala 107:17]
- wire [31:0] d_io_imm12; // @[Decode.scala 107:17]
- wire [31:0] d_io_imm20; // @[Decode.scala 107:17]
- wire [31:0] d_io_immjal; // @[Decode.scala 107:17]
- wire [31:0] d_io_immbr; // @[Decode.scala 107:17]
- wire [31:0] d_io_immst; // @[Decode.scala 107:17]
- wire d_io_lui; // @[Decode.scala 107:17]
- wire d_io_auipc; // @[Decode.scala 107:17]
- wire d_io_jal; // @[Decode.scala 107:17]
- wire d_io_jalr; // @[Decode.scala 107:17]
- wire d_io_beq; // @[Decode.scala 107:17]
- wire d_io_bne; // @[Decode.scala 107:17]
- wire d_io_blt; // @[Decode.scala 107:17]
- wire d_io_bge; // @[Decode.scala 107:17]
- wire d_io_bltu; // @[Decode.scala 107:17]
- wire d_io_bgeu; // @[Decode.scala 107:17]
- wire d_io_csrrw; // @[Decode.scala 107:17]
- wire d_io_csrrs; // @[Decode.scala 107:17]
- wire d_io_csrrc; // @[Decode.scala 107:17]
- wire d_io_lb; // @[Decode.scala 107:17]
- wire d_io_lh; // @[Decode.scala 107:17]
- wire d_io_lw; // @[Decode.scala 107:17]
- wire d_io_lbu; // @[Decode.scala 107:17]
- wire d_io_lhu; // @[Decode.scala 107:17]
- wire d_io_sb; // @[Decode.scala 107:17]
- wire d_io_sh; // @[Decode.scala 107:17]
- wire d_io_sw; // @[Decode.scala 107:17]
- wire d_io_fence; // @[Decode.scala 107:17]
- wire d_io_addi; // @[Decode.scala 107:17]
- wire d_io_slti; // @[Decode.scala 107:17]
- wire d_io_sltiu; // @[Decode.scala 107:17]
- wire d_io_xori; // @[Decode.scala 107:17]
- wire d_io_ori; // @[Decode.scala 107:17]
- wire d_io_andi; // @[Decode.scala 107:17]
- wire d_io_slli; // @[Decode.scala 107:17]
- wire d_io_srli; // @[Decode.scala 107:17]
- wire d_io_srai; // @[Decode.scala 107:17]
- wire d_io_add; // @[Decode.scala 107:17]
- wire d_io_sub; // @[Decode.scala 107:17]
- wire d_io_slt; // @[Decode.scala 107:17]
- wire d_io_sltu; // @[Decode.scala 107:17]
- wire d_io_xor; // @[Decode.scala 107:17]
- wire d_io_or; // @[Decode.scala 107:17]
- wire d_io_and; // @[Decode.scala 107:17]
- wire d_io_sll; // @[Decode.scala 107:17]
- wire d_io_srl; // @[Decode.scala 107:17]
- wire d_io_sra; // @[Decode.scala 107:17]
- wire d_io_mul; // @[Decode.scala 107:17]
- wire d_io_mulh; // @[Decode.scala 107:17]
- wire d_io_mulhsu; // @[Decode.scala 107:17]
- wire d_io_mulhu; // @[Decode.scala 107:17]
- wire d_io_mulhr; // @[Decode.scala 107:17]
- wire d_io_mulhsur; // @[Decode.scala 107:17]
- wire d_io_mulhur; // @[Decode.scala 107:17]
- wire d_io_dmulh; // @[Decode.scala 107:17]
- wire d_io_dmulhr; // @[Decode.scala 107:17]
- wire d_io_div; // @[Decode.scala 107:17]
- wire d_io_divu; // @[Decode.scala 107:17]
- wire d_io_rem; // @[Decode.scala 107:17]
- wire d_io_remu; // @[Decode.scala 107:17]
- wire d_io_clz; // @[Decode.scala 107:17]
- wire d_io_ctz; // @[Decode.scala 107:17]
- wire d_io_pcnt; // @[Decode.scala 107:17]
- wire d_io_min; // @[Decode.scala 107:17]
- wire d_io_minu; // @[Decode.scala 107:17]
- wire d_io_max; // @[Decode.scala 107:17]
- wire d_io_maxu; // @[Decode.scala 107:17]
- wire d_io_getvl; // @[Decode.scala 107:17]
- wire d_io_getmaxvl; // @[Decode.scala 107:17]
- wire d_io_vld; // @[Decode.scala 107:17]
- wire d_io_vst; // @[Decode.scala 107:17]
- wire d_io_viop; // @[Decode.scala 107:17]
- wire d_io_ebreak; // @[Decode.scala 107:17]
- wire d_io_ecall; // @[Decode.scala 107:17]
- wire d_io_eexit; // @[Decode.scala 107:17]
- wire d_io_eyield; // @[Decode.scala 107:17]
- wire d_io_ectxsw; // @[Decode.scala 107:17]
- wire d_io_mpause; // @[Decode.scala 107:17]
- wire d_io_mret; // @[Decode.scala 107:17]
- wire d_io_undef; // @[Decode.scala 107:17]
- wire d_io_fencei; // @[Decode.scala 107:17]
- wire d_io_flushat; // @[Decode.scala 107:17]
- wire d_io_flushall; // @[Decode.scala 107:17]
- wire d_io_slog; // @[Decode.scala 107:17]
- wire decodeEn = io_inst_valid & io_inst_ready & ~io_branchTaken; // @[Decode.scala 104:49]
- wire vldst = d_io_vld | d_io_vst; // @[Decode.scala 111:24]
- wire vldst_wb = vldst & io_inst_inst[28]; // @[Decode.scala 112:24]
- wire [4:0] rdAddr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- wire [4:0] rs2Addr = io_inst_inst[24:20]; // @[Decode.scala 116:29]
- wire [4:0] rs3Addr = io_inst_inst[31:27]; // @[Decode.scala 117:29]
- wire _isAluImm_T_3 = d_io_addi | d_io_slti | d_io_sltiu | d_io_xori | d_io_ori; // @[Decode.scala 119:68]
- wire isAluImm = _isAluImm_T_3 | d_io_andi | d_io_slli | d_io_srli | d_io_srai; // @[Decode.scala 120:66]
- wire _isAluReg_T_4 = d_io_add | d_io_sub | d_io_slt | d_io_sltu | d_io_xor | d_io_or; // @[Decode.scala 122:76]
- wire isAluReg = _isAluReg_T_4 | d_io_and | d_io_sll | d_io_srl | d_io_sra; // @[Decode.scala 123:62]
- wire isAlu1Bit = d_io_clz | d_io_ctz | d_io_pcnt; // @[Decode.scala 125:40]
- wire isAlu2Bit = d_io_min | d_io_minu | d_io_max | d_io_maxu; // @[Decode.scala 126:53]
- wire _isCondBr_T_3 = d_io_beq | d_io_bne | d_io_blt | d_io_bge | d_io_bltu; // @[Decode.scala 128:63]
- wire isCondBr = _isCondBr_T_3 | d_io_bgeu; // @[Decode.scala 129:28]
- wire isLoad = d_io_lb | d_io_lh | d_io_lw | d_io_lbu | d_io_lhu; // @[Decode.scala 135:58]
- wire isStore = d_io_sb | d_io_sh | d_io_sw; // @[Decode.scala 136:36]
- wire isLsu = isLoad | isStore | d_io_vld | d_io_vst; // @[Decode.scala 137:45]
- wire isMul = d_io_mul | d_io_mulh | d_io_mulhsu | d_io_mulhu | d_io_mulhr | d_io_mulhsur | d_io_mulhur | d_io_dmulh
- | d_io_dmulhr; // @[Decode.scala 139:125]
- wire isVIop = io_vinst_op[4]; // @[Decode.scala 143:27]
- wire isVIopVs2 = isVIop & io_inst_inst[1:0] == 2'h0; // @[Decode.scala 146:26]
- wire [31:0] _aluRdEn_T = io_scoreboard_comb >> rdAddr; // @[Decode.scala 150:37]
- wire aluRdEn = ~_aluRdEn_T[0] | isVIop | isStore | isCondBr; // @[Decode.scala 150:71]
- wire [31:0] _aluRs1En_T = io_scoreboard_comb >> io_inst_inst[19:15]; // @[Decode.scala 151:37]
- wire aluRs1En = ~_aluRs1En_T[0] | isVIop | isLsu | d_io_auipc; // @[Decode.scala 151:69]
- wire [31:0] _aluRs2En_T = io_scoreboard_comb >> rs2Addr; // @[Decode.scala 152:37]
- wire aluRs2En = ~_aluRs2En_T[0] | isVIopVs2 | isLsu | d_io_auipc | isAluImm | isAlu1Bit; // @[Decode.scala 152:95]
- wire aluEn = aluRdEn & aluRs1En & aluRs2En; // @[Decode.scala 155:35]
- wire [31:0] _bruEn_T_1 = io_scoreboard_regd >> io_inst_inst[19:15]; // @[Decode.scala 158:48]
- wire _bruEn_T_6 = io_inst_inst[31:20] == 12'h0; // @[Decode.scala 159:35]
- wire bruEn = ~d_io_jalr | ~_bruEn_T_1[0] | _bruEn_T_6; // @[Decode.scala 158:58]
- wire _lsuEn_T = ~isLsu; // @[Decode.scala 162:15]
- wire _lsuEn_T_4 = ~io_serializeIn_brcond; // @[Decode.scala 164:26]
- wire _lsuEn_T_5 = _lsuEn_T | ~io_serializeIn_brcond; // @[Decode.scala 164:23]
- wire _lsuEn_T_6 = io_lsu_ready & _lsuEn_T_5; // @[Decode.scala 163:51]
- wire _lsuEn_T_11 = io_busRead_bypass ? _aluRs1En_T[0] : _bruEn_T_1[0]; // @[Decode.scala 165:20]
- wire _lsuEn_T_15 = _aluRs2En_T[0] & (isStore | vldst); // @[Decode.scala 167:49]
- wire _lsuEn_T_16 = _lsuEn_T_11 | _lsuEn_T_15; // @[Decode.scala 166:50]
- wire _lsuEn_T_17 = ~_lsuEn_T_16; // @[Decode.scala 165:15]
- wire _lsuEn_T_18 = _lsuEn_T_6 & _lsuEn_T_17; // @[Decode.scala 164:50]
- wire lsuEn = ~isLsu | _lsuEn_T_18; // @[Decode.scala 162:22]
- wire mulEn = (~isMul | ~io_serializeIn_mul) & _lsuEn_T_4; // @[Decode.scala 170:47]
- wire _vinstEn_T_6 = ~(io_vinst_op != 5'h0 & ~io_vinst_ready); // @[Decode.scala 175:17]
- wire vinstEn = ~(isVIop & io_serializeIn_brcond) & _vinstEn_T_6; // @[Decode.scala 174:76]
- wire aluValid_value__0 = io_alu_op[0] | io_alu_op[1]; // @[Library.scala 208:39]
- wire aluValid_value__1 = io_alu_op[2] | io_alu_op[3]; // @[Library.scala 208:39]
- wire aluValid_value__2 = io_alu_op[4] | io_alu_op[5]; // @[Library.scala 208:39]
- wire aluValid_value__3 = io_alu_op[6] | io_alu_op[7]; // @[Library.scala 208:39]
- wire aluValid_value__4 = io_alu_op[8] | io_alu_op[9]; // @[Library.scala 208:39]
- wire aluValid_value__5 = io_alu_op[10] | io_alu_op[11]; // @[Library.scala 208:39]
- wire aluValid_value__6 = io_alu_op[12] | io_alu_op[13]; // @[Library.scala 208:39]
- wire aluValid_value__7 = io_alu_op[14] | io_alu_op[15]; // @[Library.scala 208:39]
- wire aluValid_value__8 = io_alu_op[16] | io_alu_op[17]; // @[Library.scala 208:39]
- wire aluValid_value_1_0 = aluValid_value__0 | aluValid_value__1; // @[Library.scala 208:39]
- wire aluValid_value_1_1 = aluValid_value__2 | aluValid_value__3; // @[Library.scala 208:39]
- wire aluValid_value_1_2 = aluValid_value__4 | aluValid_value__5; // @[Library.scala 208:39]
- wire aluValid_value_1_3 = aluValid_value__6 | aluValid_value__7; // @[Library.scala 208:39]
- wire aluValid_value_2_0 = aluValid_value_1_0 | aluValid_value_1_1; // @[Library.scala 208:39]
- wire aluValid_value_2_1 = aluValid_value_1_2 | aluValid_value_1_3; // @[Library.scala 208:39]
- wire aluValid_value_3_0 = aluValid_value_2_0 | aluValid_value_2_1; // @[Library.scala 208:39]
- wire aluValid_value_4_0 = aluValid_value_3_0 | aluValid_value__8; // @[Library.scala 208:39]
- wire aluOp_1 = d_io_sub; // @[Decode.scala 183:19 190:19]
- wire aluOp_0 = d_io_auipc | d_io_addi | d_io_add; // @[Decode.scala 189:46]
- wire aluOp_3 = d_io_sltiu | d_io_sltu; // @[Decode.scala 192:33]
- wire aluOp_2 = d_io_slti | d_io_slt; // @[Decode.scala 191:32]
- wire aluOp_5 = d_io_ori | d_io_or; // @[Decode.scala 194:31]
- wire aluOp_4 = d_io_xori | d_io_xor; // @[Decode.scala 193:32]
- wire aluOp_8 = d_io_srli | d_io_srl; // @[Decode.scala 197:32]
- wire aluOp_7 = d_io_slli | d_io_sll; // @[Decode.scala 196:32]
- wire aluOp_6 = d_io_andi | d_io_and; // @[Decode.scala 195:32]
- wire [8:0] io_alu_op_lo = {aluOp_8,aluOp_7,aluOp_6,aluOp_5,aluOp_4,aluOp_3,aluOp_2,aluOp_1,aluOp_0}; // @[Decode.scala 187:22]
- wire aluOp_10 = d_io_lui; // @[Decode.scala 183:19 199:19]
- wire aluOp_9 = d_io_srai | d_io_sra; // @[Decode.scala 198:32]
- wire aluOp_12 = d_io_ctz; // @[Decode.scala 183:19 201:19]
- wire aluOp_11 = d_io_clz; // @[Decode.scala 183:19 200:19]
- wire aluOp_14 = d_io_min; // @[Decode.scala 183:19 203:19]
- wire aluOp_13 = d_io_pcnt; // @[Decode.scala 183:19 202:19]
- wire aluOp_17 = d_io_maxu; // @[Decode.scala 183:19 206:19]
- wire aluOp_16 = d_io_max; // @[Decode.scala 183:19 205:19]
- wire aluOp_15 = d_io_minu; // @[Decode.scala 183:19 204:19]
- wire [8:0] io_alu_op_hi = {aluOp_17,aluOp_16,aluOp_15,aluOp_14,aluOp_13,aluOp_12,aluOp_11,aluOp_10,aluOp_9}; // @[Decode.scala 187:22]
- wire bruValid_value__8 = io_bru_op[16]; // @[Library.scala 196:26]
- wire bruValid_value__0 = io_bru_op[0] | io_bru_op[1]; // @[Library.scala 208:39]
- wire bruValid_value__1 = io_bru_op[2] | io_bru_op[3]; // @[Library.scala 208:39]
- wire bruValid_value__2 = io_bru_op[4] | io_bru_op[5]; // @[Library.scala 208:39]
- wire bruValid_value__3 = io_bru_op[6] | io_bru_op[7]; // @[Library.scala 208:39]
- wire bruValid_value__4 = io_bru_op[8] | io_bru_op[9]; // @[Library.scala 208:39]
- wire bruValid_value__5 = io_bru_op[10] | io_bru_op[11]; // @[Library.scala 208:39]
- wire bruValid_value__6 = io_bru_op[12] | io_bru_op[13]; // @[Library.scala 208:39]
- wire bruValid_value__7 = io_bru_op[14] | io_bru_op[15]; // @[Library.scala 208:39]
- wire bruValid_value_1_0 = bruValid_value__0 | bruValid_value__1; // @[Library.scala 208:39]
- wire bruValid_value_1_1 = bruValid_value__2 | bruValid_value__3; // @[Library.scala 208:39]
- wire bruValid_value_1_2 = bruValid_value__4 | bruValid_value__5; // @[Library.scala 208:39]
- wire bruValid_value_1_3 = bruValid_value__6 | bruValid_value__7; // @[Library.scala 208:39]
- wire bruValid_value_2_0 = bruValid_value_1_0 | bruValid_value_1_1; // @[Library.scala 208:39]
- wire bruValid_value_2_1 = bruValid_value_1_2 | bruValid_value_1_3; // @[Library.scala 208:39]
- wire bruValid_value_3_0 = bruValid_value_2_0 | bruValid_value_2_1; // @[Library.scala 208:39]
- wire bruValid_value_4_0 = bruValid_value_3_0 | bruValid_value__8; // @[Library.scala 208:39]
- wire bruOp_1 = d_io_jalr; // @[Decode.scala 210:19 220:19]
- wire bruOp_0 = d_io_jal; // @[Decode.scala 210:19 219:19]
- wire bruOp_3 = d_io_bne; // @[Decode.scala 210:19 222:19]
- wire bruOp_2 = d_io_beq; // @[Decode.scala 210:19 221:19]
- wire bruOp_5 = d_io_bge; // @[Decode.scala 210:19 224:19]
- wire bruOp_4 = d_io_blt; // @[Decode.scala 210:19 223:19]
- wire bruOp_7 = d_io_bgeu; // @[Decode.scala 210:19 226:19]
- wire bruOp_6 = d_io_bltu; // @[Decode.scala 210:19 225:19]
- wire [7:0] io_bru_op_lo = {bruOp_7,bruOp_6,bruOp_5,bruOp_4,bruOp_3,bruOp_2,bruOp_1,bruOp_0}; // @[Decode.scala 214:22]
- wire bruOp_16 = d_io_undef; // @[Decode.scala 210:19 235:21]
- wire [8:0] io_bru_op_hi = {bruOp_16,1'h0,1'h0,2'h0,4'h0}; // @[Decode.scala 214:22]
- wire [31:0] _io_bru_target_T_1 = io_inst_inst[2] ? d_io_immjal : d_io_immbr; // @[Decode.scala 216:38]
- wire csrValid_value__1 = io_csr_op[2]; // @[Library.scala 196:26]
- wire csrValid_value__0 = io_csr_op[0] | io_csr_op[1]; // @[Library.scala 208:39]
- wire csrValid_value_1_0 = csrValid_value__0 | csrValid_value__1; // @[Library.scala 208:39]
- wire lsuValid_value__0 = io_lsu_op[0] | io_lsu_op[1]; // @[Library.scala 208:39]
- wire lsuValid_value__1 = io_lsu_op[2] | io_lsu_op[3]; // @[Library.scala 208:39]
- wire lsuValid_value__2 = io_lsu_op[4] | io_lsu_op[5]; // @[Library.scala 208:39]
- wire lsuValid_value__3 = io_lsu_op[6] | io_lsu_op[7]; // @[Library.scala 208:39]
- wire lsuValid_value__4 = io_lsu_op[8] | io_lsu_op[9]; // @[Library.scala 208:39]
- wire lsuValid_value__5 = io_lsu_op[10] | io_lsu_op[11]; // @[Library.scala 208:39]
- wire lsuValid_value_1_0 = lsuValid_value__0 | lsuValid_value__1; // @[Library.scala 208:39]
- wire lsuValid_value_1_1 = lsuValid_value__2 | lsuValid_value__3; // @[Library.scala 208:39]
- wire lsuValid_value_1_2 = lsuValid_value__4 | lsuValid_value__5; // @[Library.scala 208:39]
- wire lsuValid_value_2_0 = lsuValid_value_1_0 | lsuValid_value_1_1; // @[Library.scala 208:39]
- wire lsuValid_value_3_0 = lsuValid_value_2_0 | lsuValid_value_1_2; // @[Library.scala 208:39]
- wire lsuOp_2 = d_io_lw; // @[Decode.scala 252:19 261:18]
- wire lsuOp_1 = d_io_lh; // @[Decode.scala 252:19 260:18]
- wire lsuOp_0 = d_io_lb; // @[Decode.scala 252:19 259:18]
- wire lsuOp_5 = d_io_sb; // @[Decode.scala 252:19 264:18]
- wire lsuOp_4 = d_io_lhu; // @[Decode.scala 252:19 263:18]
- wire lsuOp_3 = d_io_lbu; // @[Decode.scala 252:19 262:18]
- wire [5:0] io_lsu_op_lo = {lsuOp_5,lsuOp_4,lsuOp_3,lsuOp_2,lsuOp_1,lsuOp_0}; // @[Decode.scala 257:22]
- wire lsuOp_7 = d_io_sw; // @[Decode.scala 252:19 266:18]
- wire lsuOp_6 = d_io_sh; // @[Decode.scala 252:19 265:18]
- wire [5:0] io_lsu_op_hi = {vldst,1'h0,1'h0,1'h0,lsuOp_7,lsuOp_6}; // @[Decode.scala 257:22]
- wire mluValid_value__4 = io_mlu_op[8]; // @[Library.scala 196:26]
- wire mluValid_value__0 = io_mlu_op[0] | io_mlu_op[1]; // @[Library.scala 208:39]
- wire mluValid_value__1 = io_mlu_op[2] | io_mlu_op[3]; // @[Library.scala 208:39]
- wire mluValid_value__2 = io_mlu_op[4] | io_mlu_op[5]; // @[Library.scala 208:39]
- wire mluValid_value__3 = io_mlu_op[6] | io_mlu_op[7]; // @[Library.scala 208:39]
- wire mluValid_value_1_0 = mluValid_value__0 | mluValid_value__1; // @[Library.scala 208:39]
- wire mluValid_value_1_1 = mluValid_value__2 | mluValid_value__3; // @[Library.scala 208:39]
- wire mluValid_value_2_0 = mluValid_value_1_0 | mluValid_value_1_1; // @[Library.scala 208:39]
- wire mluValid_value_3_0 = mluValid_value_2_0 | mluValid_value__4; // @[Library.scala 208:39]
- wire mluOp_1 = d_io_mulh; // @[Decode.scala 275:19 282:22]
- wire mluOp_0 = d_io_mul; // @[Decode.scala 275:19 281:22]
- wire mluOp_3 = d_io_mulhu; // @[Decode.scala 275:19 284:22]
- wire mluOp_2 = d_io_mulhsu; // @[Decode.scala 275:19 283:22]
- wire [3:0] io_mlu_op_lo = {mluOp_3,mluOp_2,mluOp_1,mluOp_0}; // @[Decode.scala 279:22]
- wire mluOp_5 = d_io_mulhsur; // @[Decode.scala 275:19 286:22]
- wire mluOp_4 = d_io_mulhr; // @[Decode.scala 275:19 285:22]
- wire mluOp_8 = d_io_dmulhr; // @[Decode.scala 275:19 289:22]
- wire mluOp_7 = d_io_dmulh; // @[Decode.scala 275:19 288:22]
- wire mluOp_6 = d_io_mulhur; // @[Decode.scala 275:19 287:22]
- wire [4:0] io_mlu_op_hi = {mluOp_8,mluOp_7,mluOp_6,mluOp_5,mluOp_4}; // @[Decode.scala 279:22]
- wire dvuValid_value__0 = io_dvu_op[0] | io_dvu_op[1]; // @[Library.scala 208:39]
- wire dvuValid_value__1 = io_dvu_op[2] | io_dvu_op[3]; // @[Library.scala 208:39]
- wire dvuValid_value_1_0 = dvuValid_value__0 | dvuValid_value__1; // @[Library.scala 208:39]
- wire dvuEn = ~dvuValid_value_1_0; // @[Decode.scala 304:34]
- wire vinstOp_0 = d_io_getvl; // @[Decode.scala 308:21 319:24]
- wire vinstOp_1 = d_io_getmaxvl; // @[Decode.scala 308:21 320:27]
- wire vinstValid_value__0 = vinstOp_0 | vinstOp_1; // @[Library.scala 208:39]
- wire vinstOp_2 = d_io_vld; // @[Decode.scala 308:21 316:22]
- wire vinstOp_3 = d_io_vst; // @[Decode.scala 308:21 317:22]
- wire vinstValid_value__1 = vinstOp_2 | vinstOp_3; // @[Library.scala 208:39]
- wire vinstValid_value_1_0 = vinstValid_value__0 | vinstValid_value__1; // @[Library.scala 208:39]
- wire vinstOp_4 = d_io_viop; // @[Decode.scala 308:21 318:23]
- wire vinstValid_value_2_0 = vinstValid_value_1_0 | vinstOp_4; // @[Library.scala 208:39]
- wire [1:0] io_vinst_op_lo = {vinstOp_1,vinstOp_0}; // @[Decode.scala 314:26]
- wire [2:0] io_vinst_op_hi = {vinstOp_4,vinstOp_3,vinstOp_2}; // @[Decode.scala 314:26]
- wire _io_rs1Read_valid_T = isCondBr | isAluReg; // @[Decode.scala 326:45]
- wire _io_rs1Read_valid_T_3 = isCondBr | isAluReg | isAluImm | isAlu1Bit | isAlu2Bit; // @[Decode.scala 326:82]
- wire _io_rs1Read_valid_T_9 = _io_rs1Read_valid_T_3 | isMul | d_io_getvl; // @[Decode.scala 327:75]
- wire _io_rs1Read_valid_T_11 = _io_rs1Read_valid_T_9 | d_io_vld | d_io_vst; // @[Decode.scala 328:46]
- wire _io_rs2Read_valid_T_2 = _io_rs1Read_valid_T | isAlu2Bit | isStore; // @[Decode.scala 329:70]
- wire _io_rs2Read_valid_T_8 = _io_rs2Read_valid_T_2 | isMul | d_io_getvl | d_io_vld; // @[Decode.scala 330:77]
- wire _io_rs2Read_valid_T_10 = _io_rs2Read_valid_T_8 | d_io_vst | d_io_viop; // @[Decode.scala 331:44]
- wire _io_rs2Set_value_T = d_io_auipc | d_io_lui; // @[Decode.scala 346:45]
- wire _rdMark_valid_T_4 = lsuValid_value_3_0 & isLoad; // @[Decode.scala 352:16]
- wire _rdMark_valid_T_5 = aluValid_value_4_0 | csrValid_value_1_0 | mluValid_value_3_0 | _rdMark_valid_T_4; // @[Decode.scala 351:68]
- wire _rdMark_valid_T_6 = _rdMark_valid_T_5 | d_io_getvl; // @[Decode.scala 352:26]
- wire _rdMark_valid_T_12 = bruValid_value_4_0 & (bruOp_0 | bruOp_1) & rdAddr != 5'h0; // @[Decode.scala 354:55]
- wire rdMark_valid = _rdMark_valid_T_6 | d_io_getmaxvl | vldst_wb | _rdMark_valid_T_12; // @[Decode.scala 353:47]
- wire _io_busRead_bypass_T_9 = io_inst_inst[11:7] == 5'h0; // @[Decode.scala 369:65]
- wire _io_busRead_bypass_T_10 = ~io_inst_inst[5] | io_inst_inst[6] ? rs2Addr == 5'h0 : _io_busRead_bypass_T_9; // @[Decode.scala 368:8]
- wire storeSelect = io_inst_inst[6:3] == 4'h4 & io_inst_inst[1:0] == 2'h3; // @[Decode.scala 372:47]
- wire [4:0] _io_busRead_immed_T_3 = storeSelect ? d_io_immst[4:0] : d_io_imm12[4:0]; // @[Decode.scala 375:30]
- wire _io_inst_ready_T_6 = ~io_serializeIn_jump; // @[Decode.scala 381:20]
- wire _io_inst_ready_T_7 = aluEn & bruEn & lsuEn & mulEn & dvuEn & vinstEn & _io_inst_ready_T_6; // @[Decode.scala 380:84]
- wire _io_inst_ready_T_13 = ~d_io_undef; // @[Decode.scala 382:43]
- DecodedInstruction_3 d ( // @[Decode.scala 107:17]
- .clock(d_clock),
- .reset(d_reset),
- .io_addr(d_io_addr),
- .io_inst(d_io_inst),
- .io_imm12(d_io_imm12),
- .io_imm20(d_io_imm20),
- .io_immjal(d_io_immjal),
- .io_immbr(d_io_immbr),
- .io_immst(d_io_immst),
- .io_lui(d_io_lui),
- .io_auipc(d_io_auipc),
- .io_jal(d_io_jal),
- .io_jalr(d_io_jalr),
- .io_beq(d_io_beq),
- .io_bne(d_io_bne),
- .io_blt(d_io_blt),
- .io_bge(d_io_bge),
- .io_bltu(d_io_bltu),
- .io_bgeu(d_io_bgeu),
- .io_csrrw(d_io_csrrw),
- .io_csrrs(d_io_csrrs),
- .io_csrrc(d_io_csrrc),
- .io_lb(d_io_lb),
- .io_lh(d_io_lh),
- .io_lw(d_io_lw),
- .io_lbu(d_io_lbu),
- .io_lhu(d_io_lhu),
- .io_sb(d_io_sb),
- .io_sh(d_io_sh),
- .io_sw(d_io_sw),
- .io_fence(d_io_fence),
- .io_addi(d_io_addi),
- .io_slti(d_io_slti),
- .io_sltiu(d_io_sltiu),
- .io_xori(d_io_xori),
- .io_ori(d_io_ori),
- .io_andi(d_io_andi),
- .io_slli(d_io_slli),
- .io_srli(d_io_srli),
- .io_srai(d_io_srai),
- .io_add(d_io_add),
- .io_sub(d_io_sub),
- .io_slt(d_io_slt),
- .io_sltu(d_io_sltu),
- .io_xor(d_io_xor),
- .io_or(d_io_or),
- .io_and(d_io_and),
- .io_sll(d_io_sll),
- .io_srl(d_io_srl),
- .io_sra(d_io_sra),
- .io_mul(d_io_mul),
- .io_mulh(d_io_mulh),
- .io_mulhsu(d_io_mulhsu),
- .io_mulhu(d_io_mulhu),
- .io_mulhr(d_io_mulhr),
- .io_mulhsur(d_io_mulhsur),
- .io_mulhur(d_io_mulhur),
- .io_dmulh(d_io_dmulh),
- .io_dmulhr(d_io_dmulhr),
- .io_div(d_io_div),
- .io_divu(d_io_divu),
- .io_rem(d_io_rem),
- .io_remu(d_io_remu),
- .io_clz(d_io_clz),
- .io_ctz(d_io_ctz),
- .io_pcnt(d_io_pcnt),
- .io_min(d_io_min),
- .io_minu(d_io_minu),
- .io_max(d_io_max),
- .io_maxu(d_io_maxu),
- .io_getvl(d_io_getvl),
- .io_getmaxvl(d_io_getmaxvl),
- .io_vld(d_io_vld),
- .io_vst(d_io_vst),
- .io_viop(d_io_viop),
- .io_ebreak(d_io_ebreak),
- .io_ecall(d_io_ecall),
- .io_eexit(d_io_eexit),
- .io_eyield(d_io_eyield),
- .io_ectxsw(d_io_ectxsw),
- .io_mpause(d_io_mpause),
- .io_mret(d_io_mret),
- .io_undef(d_io_undef),
- .io_fencei(d_io_fencei),
- .io_flushat(d_io_flushat),
- .io_flushall(d_io_flushall),
- .io_slog(d_io_slog)
- );
- assign io_inst_ready = _io_inst_ready_T_7 & ~io_halted & ~io_interlock & _io_inst_ready_T_13; // @[Decode.scala 381:72]
- assign io_rs1Read_valid = decodeEn & _io_rs1Read_valid_T_11; // @[Decode.scala 326:32]
- assign io_rs1Read_addr = io_inst_inst[0] ? io_inst_inst[19:15] : rs3Addr; // @[Decode.scala 334:25]
- assign io_rs1Set_valid = decodeEn & d_io_auipc; // @[Decode.scala 340:31]
- assign io_rs1Set_value = io_inst_addr; // @[Decode.scala 343:25]
- assign io_rs2Read_valid = decodeEn & _io_rs2Read_valid_T_10; // @[Decode.scala 329:32]
- assign io_rs2Read_addr = io_inst_inst[24:20]; // @[Decode.scala 116:29]
- assign io_rs2Set_valid = io_rs1Set_valid | decodeEn & (isAluImm | isAlu1Bit | d_io_lui); // @[Decode.scala 341:38]
- assign io_rs2Set_value = _io_rs2Set_value_T ? d_io_imm20 : d_io_imm12; // @[Mux.scala 101:16]
- assign io_rdMark_valid = decodeEn & rdMark_valid; // @[Decode.scala 360:31]
- assign io_rdMark_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_busRead_bypass = io_inst_inst[31:25] == 7'h0 & _io_busRead_bypass_T_10; // @[Decode.scala 367:52]
- assign io_busRead_immed = {d_io_imm12[31:5],_io_busRead_immed_T_3}; // @[Cat.scala 31:58]
- assign io_alu_valid = decodeEn & aluValid_value_4_0; // @[Decode.scala 185:28]
- assign io_alu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_alu_op = {io_alu_op_hi,io_alu_op_lo}; // @[Decode.scala 187:22]
- assign io_bru_valid = decodeEn & bruValid_value_4_0; // @[Decode.scala 212:28]
- assign io_bru_fwd = io_inst_brchFwd; // @[Decode.scala 213:14]
- assign io_bru_op = {io_bru_op_hi,io_bru_op_lo}; // @[Decode.scala 214:22]
- assign io_bru_pc = io_inst_addr; // @[Decode.scala 215:13]
- assign io_bru_target = io_inst_addr + _io_bru_target_T_1; // @[Decode.scala 216:33]
- assign io_bru_link = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_csr_op = 3'h0; // @[Decode.scala 244:22]
- assign io_lsu_valid = decodeEn & lsuValid_value_3_0; // @[Decode.scala 254:28]
- assign io_lsu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_lsu_op = {io_lsu_op_hi,io_lsu_op_lo}; // @[Decode.scala 257:22]
- assign io_mlu_valid = decodeEn & mluValid_value_3_0; // @[Decode.scala 277:28]
- assign io_mlu_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_mlu_op = {io_mlu_op_hi,io_mlu_op_lo}; // @[Decode.scala 279:22]
- assign io_dvu_op = 4'h0; // @[Decode.scala 297:22]
- assign io_vinst_valid = decodeEn & vinstValid_value_2_0; // @[Decode.scala 311:30]
- assign io_vinst_addr = vldst ? io_inst_inst[19:15] : io_inst_inst[11:7]; // @[Decode.scala 114:20]
- assign io_vinst_inst = io_inst_inst; // @[Decode.scala 313:17]
- assign io_vinst_op = {io_vinst_op_hi,io_vinst_op_lo}; // @[Decode.scala 314:26]
- assign d_clock = clock;
- assign d_reset = reset;
- assign d_io_addr = io_inst_addr; // @[Decode.scala 108:13]
- assign d_io_inst = io_inst_inst; // @[Decode.scala 109:13]
-endmodule
-module Alu(
- input clock,
- input reset,
- input io_req_valid,
- input [4:0] io_req_addr,
- input [17:0] io_req_op,
- input io_rs1_valid,
- input [31:0] io_rs1_data,
- input io_rs2_valid,
- input [31:0] io_rs2_data,
- output io_rd_valid,
- output [4:0] io_rd_addr,
- output [31:0] io_rd_data
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
-`endif // RANDOMIZE_REG_INIT
- reg valid; // @[Alu.scala 68:22]
- reg [4:0] addr; // @[Alu.scala 69:17]
- reg [17:0] op; // @[Alu.scala 70:19]
- wire [4:0] shamt = io_rs2_data[4:0]; // @[Alu.scala 84:18]
- wire [31:0] _io_rd_data_T_2 = io_rs1_data + io_rs2_data; // @[Alu.scala 88:42]
- wire [31:0] _io_rd_data_T_3 = op[0] ? _io_rd_data_T_2 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _io_rd_data_T_6 = io_rs1_data - io_rs2_data; // @[Alu.scala 89:42]
- wire [31:0] _io_rd_data_T_7 = op[1] ? _io_rd_data_T_6 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _io_rd_data_T_8 = _io_rd_data_T_3 | _io_rd_data_T_7; // @[Alu.scala 88:49]
- wire _io_rd_data_T_12 = $signed(io_rs1_data) < $signed(io_rs2_data); // @[Alu.scala 90:49]
- wire _io_rd_data_T_13 = op[2] & _io_rd_data_T_12; // @[Library.scala 26:8]
- wire [31:0] _GEN_2 = {{31'd0}, _io_rd_data_T_13}; // @[Alu.scala 89:49]
- wire [31:0] _io_rd_data_T_14 = _io_rd_data_T_8 | _GEN_2; // @[Alu.scala 89:49]
- wire _io_rd_data_T_16 = io_rs1_data < io_rs2_data; // @[Alu.scala 91:42]
- wire _io_rd_data_T_17 = op[3] & _io_rd_data_T_16; // @[Library.scala 26:8]
- wire [31:0] _GEN_3 = {{31'd0}, _io_rd_data_T_17}; // @[Alu.scala 90:63]
- wire [31:0] _io_rd_data_T_18 = _io_rd_data_T_14 | _GEN_3; // @[Alu.scala 90:63]
- wire [31:0] _io_rd_data_T_20 = io_rs1_data ^ io_rs2_data; // @[Alu.scala 92:42]
- wire [31:0] _io_rd_data_T_21 = op[4] ? _io_rd_data_T_20 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _io_rd_data_T_22 = _io_rd_data_T_18 | _io_rd_data_T_21; // @[Alu.scala 91:49]
- wire [31:0] _io_rd_data_T_24 = io_rs1_data | io_rs2_data; // @[Alu.scala 93:42]
- wire [31:0] _io_rd_data_T_25 = op[5] ? _io_rd_data_T_24 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _io_rd_data_T_26 = _io_rd_data_T_22 | _io_rd_data_T_25; // @[Alu.scala 92:49]
- wire [31:0] _io_rd_data_T_28 = io_rs1_data & io_rs2_data; // @[Alu.scala 94:42]
- wire [31:0] _io_rd_data_T_29 = op[6] ? _io_rd_data_T_28 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _io_rd_data_T_30 = _io_rd_data_T_26 | _io_rd_data_T_29; // @[Alu.scala 93:49]
- wire [62:0] _GEN_0 = {{31'd0}, io_rs1_data}; // @[Alu.scala 95:42]
- wire [62:0] _io_rd_data_T_32 = _GEN_0 << shamt; // @[Alu.scala 95:42]
- wire [62:0] _io_rd_data_T_33 = op[7] ? _io_rd_data_T_32 : 63'h0; // @[Library.scala 22:8]
- wire [62:0] _GEN_4 = {{31'd0}, _io_rd_data_T_30}; // @[Alu.scala 94:49]
- wire [62:0] _io_rd_data_T_34 = _GEN_4 | _io_rd_data_T_33; // @[Alu.scala 94:49]
- wire [31:0] _io_rd_data_T_36 = io_rs1_data >> shamt; // @[Alu.scala 96:42]
- wire [31:0] _io_rd_data_T_37 = op[8] ? _io_rd_data_T_36 : 32'h0; // @[Library.scala 22:8]
- wire [62:0] _GEN_5 = {{31'd0}, _io_rd_data_T_37}; // @[Alu.scala 95:52]
- wire [62:0] _io_rd_data_T_38 = _io_rd_data_T_34 | _GEN_5; // @[Alu.scala 95:52]
- wire [31:0] _io_rd_data_T_42 = $signed(io_rs1_data) >>> shamt; // @[Alu.scala 97:60]
- wire [31:0] _io_rd_data_T_43 = op[9] ? _io_rd_data_T_42 : 32'h0; // @[Library.scala 22:8]
- wire [62:0] _GEN_6 = {{31'd0}, _io_rd_data_T_43}; // @[Alu.scala 96:52]
- wire [62:0] _io_rd_data_T_44 = _io_rd_data_T_38 | _GEN_6; // @[Alu.scala 96:52]
- wire [31:0] _io_rd_data_T_46 = op[10] ? io_rs2_data : 32'h0; // @[Library.scala 22:8]
- wire [62:0] _GEN_7 = {{31'd0}, _io_rd_data_T_46}; // @[Alu.scala 97:68]
- wire [62:0] _io_rd_data_T_47 = _io_rd_data_T_44 | _GEN_7; // @[Alu.scala 97:68]
- wire [31:0] _GEN_8 = {{16'd0}, io_rs1_data[31:16]}; // @[Bitwise.scala 105:31]
- wire [31:0] _io_rd_data_T_52 = _GEN_8 & 32'hffff; // @[Bitwise.scala 105:31]
- wire [31:0] _io_rd_data_T_54 = {io_rs1_data[15:0], 16'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _io_rd_data_T_56 = _io_rd_data_T_54 & 32'hffff0000; // @[Bitwise.scala 105:80]
- wire [31:0] _io_rd_data_T_57 = _io_rd_data_T_52 | _io_rd_data_T_56; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_9 = {{8'd0}, _io_rd_data_T_57[31:8]}; // @[Bitwise.scala 105:31]
- wire [31:0] _io_rd_data_T_62 = _GEN_9 & 32'hff00ff; // @[Bitwise.scala 105:31]
- wire [31:0] _io_rd_data_T_64 = {_io_rd_data_T_57[23:0], 8'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _io_rd_data_T_66 = _io_rd_data_T_64 & 32'hff00ff00; // @[Bitwise.scala 105:80]
- wire [31:0] _io_rd_data_T_67 = _io_rd_data_T_62 | _io_rd_data_T_66; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_10 = {{4'd0}, _io_rd_data_T_67[31:4]}; // @[Bitwise.scala 105:31]
- wire [31:0] _io_rd_data_T_72 = _GEN_10 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
- wire [31:0] _io_rd_data_T_74 = {_io_rd_data_T_67[27:0], 4'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _io_rd_data_T_76 = _io_rd_data_T_74 & 32'hf0f0f0f0; // @[Bitwise.scala 105:80]
- wire [31:0] _io_rd_data_T_77 = _io_rd_data_T_72 | _io_rd_data_T_76; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_11 = {{2'd0}, _io_rd_data_T_77[31:2]}; // @[Bitwise.scala 105:31]
- wire [31:0] _io_rd_data_T_82 = _GEN_11 & 32'h33333333; // @[Bitwise.scala 105:31]
- wire [31:0] _io_rd_data_T_84 = {_io_rd_data_T_77[29:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _io_rd_data_T_86 = _io_rd_data_T_84 & 32'hcccccccc; // @[Bitwise.scala 105:80]
- wire [31:0] _io_rd_data_T_87 = _io_rd_data_T_82 | _io_rd_data_T_86; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_12 = {{1'd0}, _io_rd_data_T_87[31:1]}; // @[Bitwise.scala 105:31]
- wire [31:0] _io_rd_data_T_92 = _GEN_12 & 32'h55555555; // @[Bitwise.scala 105:31]
- wire [31:0] _io_rd_data_T_94 = {_io_rd_data_T_87[30:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _io_rd_data_T_96 = _io_rd_data_T_94 & 32'haaaaaaaa; // @[Bitwise.scala 105:80]
- wire [31:0] _io_rd_data_T_97 = _io_rd_data_T_92 | _io_rd_data_T_96; // @[Bitwise.scala 105:39]
- wire [32:0] _io_rd_data_T_98 = {1'h1,_io_rd_data_T_97}; // @[Cat.scala 31:58]
- wire [5:0] _io_rd_data_T_132 = _io_rd_data_T_98[31] ? 6'h1f : 6'h20; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_133 = _io_rd_data_T_98[30] ? 6'h1e : _io_rd_data_T_132; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_134 = _io_rd_data_T_98[29] ? 6'h1d : _io_rd_data_T_133; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_135 = _io_rd_data_T_98[28] ? 6'h1c : _io_rd_data_T_134; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_136 = _io_rd_data_T_98[27] ? 6'h1b : _io_rd_data_T_135; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_137 = _io_rd_data_T_98[26] ? 6'h1a : _io_rd_data_T_136; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_138 = _io_rd_data_T_98[25] ? 6'h19 : _io_rd_data_T_137; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_139 = _io_rd_data_T_98[24] ? 6'h18 : _io_rd_data_T_138; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_140 = _io_rd_data_T_98[23] ? 6'h17 : _io_rd_data_T_139; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_141 = _io_rd_data_T_98[22] ? 6'h16 : _io_rd_data_T_140; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_142 = _io_rd_data_T_98[21] ? 6'h15 : _io_rd_data_T_141; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_143 = _io_rd_data_T_98[20] ? 6'h14 : _io_rd_data_T_142; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_144 = _io_rd_data_T_98[19] ? 6'h13 : _io_rd_data_T_143; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_145 = _io_rd_data_T_98[18] ? 6'h12 : _io_rd_data_T_144; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_146 = _io_rd_data_T_98[17] ? 6'h11 : _io_rd_data_T_145; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_147 = _io_rd_data_T_98[16] ? 6'h10 : _io_rd_data_T_146; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_148 = _io_rd_data_T_98[15] ? 6'hf : _io_rd_data_T_147; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_149 = _io_rd_data_T_98[14] ? 6'he : _io_rd_data_T_148; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_150 = _io_rd_data_T_98[13] ? 6'hd : _io_rd_data_T_149; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_151 = _io_rd_data_T_98[12] ? 6'hc : _io_rd_data_T_150; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_152 = _io_rd_data_T_98[11] ? 6'hb : _io_rd_data_T_151; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_153 = _io_rd_data_T_98[10] ? 6'ha : _io_rd_data_T_152; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_154 = _io_rd_data_T_98[9] ? 6'h9 : _io_rd_data_T_153; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_155 = _io_rd_data_T_98[8] ? 6'h8 : _io_rd_data_T_154; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_156 = _io_rd_data_T_98[7] ? 6'h7 : _io_rd_data_T_155; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_157 = _io_rd_data_T_98[6] ? 6'h6 : _io_rd_data_T_156; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_158 = _io_rd_data_T_98[5] ? 6'h5 : _io_rd_data_T_157; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_159 = _io_rd_data_T_98[4] ? 6'h4 : _io_rd_data_T_158; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_160 = _io_rd_data_T_98[3] ? 6'h3 : _io_rd_data_T_159; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_161 = _io_rd_data_T_98[2] ? 6'h2 : _io_rd_data_T_160; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_162 = _io_rd_data_T_98[1] ? 6'h1 : _io_rd_data_T_161; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_163 = _io_rd_data_T_98[0] ? 6'h0 : _io_rd_data_T_162; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_164 = op[11] ? _io_rd_data_T_163 : 6'h0; // @[Library.scala 22:8]
- wire [62:0] _GEN_13 = {{57'd0}, _io_rd_data_T_164}; // @[Alu.scala 98:43]
- wire [62:0] _io_rd_data_T_165 = _io_rd_data_T_47 | _GEN_13; // @[Alu.scala 98:43]
- wire [32:0] _io_rd_data_T_167 = {1'h1,io_rs1_data}; // @[Cat.scala 31:58]
- wire [5:0] _io_rd_data_T_201 = _io_rd_data_T_167[31] ? 6'h1f : 6'h20; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_202 = _io_rd_data_T_167[30] ? 6'h1e : _io_rd_data_T_201; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_203 = _io_rd_data_T_167[29] ? 6'h1d : _io_rd_data_T_202; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_204 = _io_rd_data_T_167[28] ? 6'h1c : _io_rd_data_T_203; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_205 = _io_rd_data_T_167[27] ? 6'h1b : _io_rd_data_T_204; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_206 = _io_rd_data_T_167[26] ? 6'h1a : _io_rd_data_T_205; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_207 = _io_rd_data_T_167[25] ? 6'h19 : _io_rd_data_T_206; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_208 = _io_rd_data_T_167[24] ? 6'h18 : _io_rd_data_T_207; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_209 = _io_rd_data_T_167[23] ? 6'h17 : _io_rd_data_T_208; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_210 = _io_rd_data_T_167[22] ? 6'h16 : _io_rd_data_T_209; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_211 = _io_rd_data_T_167[21] ? 6'h15 : _io_rd_data_T_210; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_212 = _io_rd_data_T_167[20] ? 6'h14 : _io_rd_data_T_211; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_213 = _io_rd_data_T_167[19] ? 6'h13 : _io_rd_data_T_212; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_214 = _io_rd_data_T_167[18] ? 6'h12 : _io_rd_data_T_213; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_215 = _io_rd_data_T_167[17] ? 6'h11 : _io_rd_data_T_214; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_216 = _io_rd_data_T_167[16] ? 6'h10 : _io_rd_data_T_215; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_217 = _io_rd_data_T_167[15] ? 6'hf : _io_rd_data_T_216; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_218 = _io_rd_data_T_167[14] ? 6'he : _io_rd_data_T_217; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_219 = _io_rd_data_T_167[13] ? 6'hd : _io_rd_data_T_218; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_220 = _io_rd_data_T_167[12] ? 6'hc : _io_rd_data_T_219; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_221 = _io_rd_data_T_167[11] ? 6'hb : _io_rd_data_T_220; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_222 = _io_rd_data_T_167[10] ? 6'ha : _io_rd_data_T_221; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_223 = _io_rd_data_T_167[9] ? 6'h9 : _io_rd_data_T_222; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_224 = _io_rd_data_T_167[8] ? 6'h8 : _io_rd_data_T_223; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_225 = _io_rd_data_T_167[7] ? 6'h7 : _io_rd_data_T_224; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_226 = _io_rd_data_T_167[6] ? 6'h6 : _io_rd_data_T_225; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_227 = _io_rd_data_T_167[5] ? 6'h5 : _io_rd_data_T_226; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_228 = _io_rd_data_T_167[4] ? 6'h4 : _io_rd_data_T_227; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_229 = _io_rd_data_T_167[3] ? 6'h3 : _io_rd_data_T_228; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_230 = _io_rd_data_T_167[2] ? 6'h2 : _io_rd_data_T_229; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_231 = _io_rd_data_T_167[1] ? 6'h1 : _io_rd_data_T_230; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_232 = _io_rd_data_T_167[0] ? 6'h0 : _io_rd_data_T_231; // @[Mux.scala 47:70]
- wire [5:0] _io_rd_data_T_233 = op[12] ? _io_rd_data_T_232 : 6'h0; // @[Library.scala 22:8]
- wire [62:0] _GEN_14 = {{57'd0}, _io_rd_data_T_233}; // @[Alu.scala 99:48]
- wire [62:0] _io_rd_data_T_234 = _io_rd_data_T_165 | _GEN_14; // @[Alu.scala 99:48]
- wire [1:0] _io_rd_data_T_268 = io_rs1_data[0] + io_rs1_data[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_270 = io_rs1_data[2] + io_rs1_data[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _io_rd_data_T_272 = _io_rd_data_T_268 + _io_rd_data_T_270; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_274 = io_rs1_data[4] + io_rs1_data[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_276 = io_rs1_data[6] + io_rs1_data[7]; // @[Bitwise.scala 48:55]
- wire [2:0] _io_rd_data_T_278 = _io_rd_data_T_274 + _io_rd_data_T_276; // @[Bitwise.scala 48:55]
- wire [3:0] _io_rd_data_T_280 = _io_rd_data_T_272 + _io_rd_data_T_278; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_282 = io_rs1_data[8] + io_rs1_data[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_284 = io_rs1_data[10] + io_rs1_data[11]; // @[Bitwise.scala 48:55]
- wire [2:0] _io_rd_data_T_286 = _io_rd_data_T_282 + _io_rd_data_T_284; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_288 = io_rs1_data[12] + io_rs1_data[13]; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_290 = io_rs1_data[14] + io_rs1_data[15]; // @[Bitwise.scala 48:55]
- wire [2:0] _io_rd_data_T_292 = _io_rd_data_T_288 + _io_rd_data_T_290; // @[Bitwise.scala 48:55]
- wire [3:0] _io_rd_data_T_294 = _io_rd_data_T_286 + _io_rd_data_T_292; // @[Bitwise.scala 48:55]
- wire [4:0] _io_rd_data_T_296 = _io_rd_data_T_280 + _io_rd_data_T_294; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_298 = io_rs1_data[16] + io_rs1_data[17]; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_300 = io_rs1_data[18] + io_rs1_data[19]; // @[Bitwise.scala 48:55]
- wire [2:0] _io_rd_data_T_302 = _io_rd_data_T_298 + _io_rd_data_T_300; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_304 = io_rs1_data[20] + io_rs1_data[21]; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_306 = io_rs1_data[22] + io_rs1_data[23]; // @[Bitwise.scala 48:55]
- wire [2:0] _io_rd_data_T_308 = _io_rd_data_T_304 + _io_rd_data_T_306; // @[Bitwise.scala 48:55]
- wire [3:0] _io_rd_data_T_310 = _io_rd_data_T_302 + _io_rd_data_T_308; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_312 = io_rs1_data[24] + io_rs1_data[25]; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_314 = io_rs1_data[26] + io_rs1_data[27]; // @[Bitwise.scala 48:55]
- wire [2:0] _io_rd_data_T_316 = _io_rd_data_T_312 + _io_rd_data_T_314; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_318 = io_rs1_data[28] + io_rs1_data[29]; // @[Bitwise.scala 48:55]
- wire [1:0] _io_rd_data_T_320 = io_rs1_data[30] + io_rs1_data[31]; // @[Bitwise.scala 48:55]
- wire [2:0] _io_rd_data_T_322 = _io_rd_data_T_318 + _io_rd_data_T_320; // @[Bitwise.scala 48:55]
- wire [3:0] _io_rd_data_T_324 = _io_rd_data_T_316 + _io_rd_data_T_322; // @[Bitwise.scala 48:55]
- wire [4:0] _io_rd_data_T_326 = _io_rd_data_T_310 + _io_rd_data_T_324; // @[Bitwise.scala 48:55]
- wire [5:0] _io_rd_data_T_328 = _io_rd_data_T_296 + _io_rd_data_T_326; // @[Bitwise.scala 48:55]
- wire [5:0] _io_rd_data_T_330 = op[13] ? _io_rd_data_T_328 : 6'h0; // @[Library.scala 22:8]
- wire [62:0] _GEN_15 = {{57'd0}, _io_rd_data_T_330}; // @[Alu.scala 100:48]
- wire [62:0] _io_rd_data_T_331 = _io_rd_data_T_234 | _GEN_15; // @[Alu.scala 100:48]
- wire [31:0] _io_rd_data_T_336 = _io_rd_data_T_12 ? io_rs1_data : io_rs2_data; // @[Alu.scala 102:41]
- wire [31:0] _io_rd_data_T_337 = op[14] ? _io_rd_data_T_336 : 32'h0; // @[Library.scala 22:8]
- wire [62:0] _GEN_16 = {{31'd0}, _io_rd_data_T_337}; // @[Alu.scala 101:53]
- wire [62:0] _io_rd_data_T_338 = _io_rd_data_T_331 | _GEN_16; // @[Alu.scala 101:53]
- wire [31:0] _io_rd_data_T_343 = $signed(io_rs1_data) > $signed(io_rs2_data) ? io_rs1_data : io_rs2_data; // @[Alu.scala 103:41]
- wire [31:0] _io_rd_data_T_344 = op[16] ? _io_rd_data_T_343 : 32'h0; // @[Library.scala 22:8]
- wire [62:0] _GEN_17 = {{31'd0}, _io_rd_data_T_344}; // @[Alu.scala 102:78]
- wire [62:0] _io_rd_data_T_345 = _io_rd_data_T_338 | _GEN_17; // @[Alu.scala 102:78]
- wire [31:0] _io_rd_data_T_348 = _io_rd_data_T_16 ? io_rs1_data : io_rs2_data; // @[Alu.scala 104:41]
- wire [31:0] _io_rd_data_T_349 = op[15] ? _io_rd_data_T_348 : 32'h0; // @[Library.scala 22:8]
- wire [62:0] _GEN_18 = {{31'd0}, _io_rd_data_T_349}; // @[Alu.scala 103:78]
- wire [62:0] _io_rd_data_T_350 = _io_rd_data_T_345 | _GEN_18; // @[Alu.scala 103:78]
- wire [31:0] _io_rd_data_T_353 = io_rs1_data > io_rs2_data ? io_rs1_data : io_rs2_data; // @[Alu.scala 105:41]
- wire [31:0] _io_rd_data_T_354 = op[17] ? _io_rd_data_T_353 : 32'h0; // @[Library.scala 22:8]
- wire [62:0] _GEN_19 = {{31'd0}, _io_rd_data_T_354}; // @[Alu.scala 104:64]
- wire [62:0] _io_rd_data_T_355 = _io_rd_data_T_350 | _GEN_19; // @[Alu.scala 104:64]
- wire _T_7 = ~reset; // @[Alu.scala 108:9]
- assign io_rd_valid = valid; // @[Alu.scala 86:15]
- assign io_rd_addr = addr; // @[Alu.scala 87:15]
- assign io_rd_data = _io_rd_data_T_355[31:0]; // @[Alu.scala 88:15]
- always @(posedge clock) begin
- if (io_req_valid) begin // @[Alu.scala 77:23]
- addr <= io_req_addr; // @[Alu.scala 78:10]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(valid & ~io_rs1_valid & ~op[10]))) begin
- $fatal; // @[Alu.scala 108:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(valid & ~io_rs1_valid & ~op[10]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Alu.scala:108 assert(!(valid && !io.rs1.valid && !op(alu.LUI)))\n"); // @[Alu.scala 108:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(valid & ~io_rs2_valid))) begin
- $fatal; // @[Alu.scala 109:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(valid & ~io_rs2_valid))) begin
- $fwrite(32'h80000002,"Assertion failed\n at Alu.scala:109 assert(!(valid && !io.rs2.valid))\n"); // @[Alu.scala 109:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Alu.scala 68:22]
- valid <= 1'h0; // @[Alu.scala 68:22]
- end else begin
- valid <= io_req_valid; // @[Alu.scala 73:9]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Alu.scala 77:23]
- op <= 18'h0; // @[Alu.scala 79:8]
- end else if (io_req_valid) begin // @[Alu.scala 70:19]
- op <= io_req_op;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- valid = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- addr = _RAND_1[4:0];
- _RAND_2 = {1{`RANDOM}};
- op = _RAND_2[17:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- valid = 1'h0;
- end
- if (reset) begin
- op = 18'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Bru(
- input clock,
- input reset,
- input io_req_valid,
- input io_req_fwd,
- input [16:0] io_req_op,
- input [31:0] io_req_pc,
- input [31:0] io_req_target,
- input [4:0] io_req_link,
- output io_csr_in_mode_valid,
- output io_csr_in_mode_bits,
- output io_csr_in_mcause_valid,
- output [31:0] io_csr_in_mcause_bits,
- output io_csr_in_mepc_valid,
- output [31:0] io_csr_in_mepc_bits,
- output io_csr_in_mtval_valid,
- output [31:0] io_csr_in_mtval_bits,
- output io_csr_in_halt,
- output io_csr_in_fault,
- input io_csr_out_mode,
- input [31:0] io_csr_out_mepc,
- input [31:0] io_csr_out_mtvec,
- input io_rs1_valid,
- input [31:0] io_rs1_data,
- input io_rs2_valid,
- input [31:0] io_rs2_data,
- output io_rd_valid,
- output [4:0] io_rd_addr,
- output [31:0] io_rd_data,
- output io_taken_valid,
- output [31:0] io_taken_value,
- input [31:0] io_target_data,
- output io_interlock,
- output io_iflush
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
-`endif // RANDOMIZE_REG_INIT
- reg interlock; // @[Bru.scala 80:26]
- reg fwd; // @[Bru.scala 83:20]
- reg [16:0] op; // @[Bru.scala 84:19]
- reg [31:0] target; // @[Bru.scala 85:19]
- reg linkValid; // @[Bru.scala 86:26]
- reg [4:0] linkAddr; // @[Bru.scala 87:21]
- reg [31:0] linkData; // @[Bru.scala 88:21]
- reg [31:0] pcEx; // @[Bru.scala 89:17]
- wire _linkValid_T_4 = io_req_op[0] | io_req_op[1]; // @[Bru.scala 92:39]
- wire [31:0] pc4De = io_req_pc + 32'h4; // @[Bru.scala 105:25]
- wire _mret_T_1 = ~io_csr_out_mode; // @[Bru.scala 108:42]
- wire mret = io_req_op[14] & ~io_csr_out_mode; // @[Bru.scala 108:39]
- wire _call_T_3 = io_req_op[14] & io_csr_out_mode | io_req_op[8]; // @[Bru.scala 109:47]
- wire _call_T_5 = _call_T_3 | io_req_op[9]; // @[Bru.scala 110:41]
- wire _call_T_7 = _call_T_5 | io_req_op[10]; // @[Bru.scala 111:40]
- wire _call_T_9 = _call_T_7 | io_req_op[11]; // @[Bru.scala 112:40]
- wire _call_T_11 = _call_T_9 | io_req_op[12]; // @[Bru.scala 113:41]
- wire call = _call_T_11 | io_req_op[13]; // @[Bru.scala 114:41]
- wire [31:0] _target_T_3 = io_req_op[1] ? io_target_data : io_req_target; // @[Bru.scala 119:18]
- wire _interlock_T_2 = io_req_op[8] | io_req_op[9]; // @[Bru.scala 126:58]
- wire _interlock_T_6 = _interlock_T_2 | io_req_op[10] | io_req_op[11]; // @[Bru.scala 127:69]
- wire _interlock_T_10 = _interlock_T_6 | io_req_op[12] | io_req_op[13]; // @[Bru.scala 128:71]
- wire _interlock_T_12 = _interlock_T_10 | io_req_op[14]; // @[Bru.scala 129:43]
- wire eq = io_rs1_data == io_rs2_data; // @[Bru.scala 139:17]
- wire neq = ~eq; // @[Bru.scala 140:13]
- wire lt = $signed(io_rs1_data) < $signed(io_rs2_data); // @[Bru.scala 141:24]
- wire ge = ~lt; // @[Bru.scala 142:13]
- wire ltu = io_rs1_data < io_rs2_data; // @[Bru.scala 143:17]
- wire geu = ~ltu; // @[Bru.scala 144:13]
- wire _io_taken_valid_T_1 = op[8] & io_csr_out_mode; // @[Bru.scala 146:39]
- wire _io_taken_valid_T_3 = op[9] & io_csr_out_mode; // @[Bru.scala 147:39]
- wire _io_taken_valid_T_4 = op[8] & io_csr_out_mode | _io_taken_valid_T_3; // @[Bru.scala 146:47]
- wire _io_taken_valid_T_6 = op[10] & io_csr_out_mode; // @[Bru.scala 148:39]
- wire _io_taken_valid_T_7 = _io_taken_valid_T_4 | _io_taken_valid_T_6; // @[Bru.scala 147:47]
- wire _io_taken_valid_T_9 = op[11] & io_csr_out_mode; // @[Bru.scala 149:39]
- wire _io_taken_valid_T_10 = _io_taken_valid_T_7 | _io_taken_valid_T_9; // @[Bru.scala 148:47]
- wire _io_taken_valid_T_12 = op[12] & io_csr_out_mode; // @[Bru.scala 150:39]
- wire _io_taken_valid_T_13 = _io_taken_valid_T_10 | _io_taken_valid_T_12; // @[Bru.scala 149:47]
- wire _io_taken_valid_T_16 = op[14] & _mret_T_1; // @[Bru.scala 151:39]
- wire _io_taken_valid_T_17 = _io_taken_valid_T_13 | _io_taken_valid_T_16; // @[Bru.scala 150:47]
- wire _io_taken_valid_T_19 = op[14] & io_csr_out_mode; // @[Bru.scala 152:39]
- wire _io_taken_valid_T_20 = _io_taken_valid_T_17 | _io_taken_valid_T_19; // @[Bru.scala 151:48]
- wire _io_taken_valid_T_22 = op[13] & io_csr_out_mode; // @[Bru.scala 153:39]
- wire _io_taken_valid_T_23 = _io_taken_valid_T_20 | _io_taken_valid_T_22; // @[Bru.scala 152:47]
- wire _io_taken_valid_T_25 = _io_taken_valid_T_23 | op[15]; // @[Bru.scala 153:47]
- wire _io_taken_valid_T_28 = op[0] | op[1]; // @[Bru.scala 155:37]
- wire _io_taken_valid_T_30 = op[2] & eq; // @[Bru.scala 157:38]
- wire _io_taken_valid_T_31 = _io_taken_valid_T_28 | _io_taken_valid_T_30; // @[Bru.scala 156:38]
- wire _io_taken_valid_T_33 = op[3] & neq; // @[Bru.scala 158:38]
- wire _io_taken_valid_T_34 = _io_taken_valid_T_31 | _io_taken_valid_T_33; // @[Bru.scala 157:45]
- wire _io_taken_valid_T_36 = op[4] & lt; // @[Bru.scala 159:38]
- wire _io_taken_valid_T_37 = _io_taken_valid_T_34 | _io_taken_valid_T_36; // @[Bru.scala 158:45]
- wire _io_taken_valid_T_39 = op[5] & ge; // @[Bru.scala 160:38]
- wire _io_taken_valid_T_40 = _io_taken_valid_T_37 | _io_taken_valid_T_39; // @[Bru.scala 159:45]
- wire _io_taken_valid_T_42 = op[6] & ltu; // @[Bru.scala 161:38]
- wire _io_taken_valid_T_43 = _io_taken_valid_T_40 | _io_taken_valid_T_42; // @[Bru.scala 160:45]
- wire _io_taken_valid_T_45 = op[7] & geu; // @[Bru.scala 162:38]
- wire _io_taken_valid_T_46 = _io_taken_valid_T_43 | _io_taken_valid_T_45; // @[Bru.scala 161:45]
- wire _io_taken_valid_T_47 = _io_taken_valid_T_46 != fwd; // @[Bru.scala 162:46]
- wire undefFault = op[16]; // @[Bru.scala 171:22]
- wire _usageFault_T_5 = op[9] & _mret_T_1; // @[Bru.scala 175:38]
- wire _usageFault_T_6 = op[8] & _mret_T_1 | _usageFault_T_5; // @[Bru.scala 174:47]
- wire _usageFault_T_9 = op[10] & _mret_T_1; // @[Bru.scala 176:38]
- wire _usageFault_T_10 = _usageFault_T_6 | _usageFault_T_9; // @[Bru.scala 175:47]
- wire _usageFault_T_13 = op[11] & _mret_T_1; // @[Bru.scala 177:38]
- wire _usageFault_T_14 = _usageFault_T_10 | _usageFault_T_13; // @[Bru.scala 176:47]
- wire _usageFault_T_17 = op[12] & _mret_T_1; // @[Bru.scala 178:38]
- wire _usageFault_T_18 = _usageFault_T_14 | _usageFault_T_17; // @[Bru.scala 177:47]
- wire _usageFault_T_21 = _usageFault_T_18 | _io_taken_valid_T_22; // @[Bru.scala 178:47]
- wire usageFault = _usageFault_T_21 | _io_taken_valid_T_19; // @[Bru.scala 179:46]
- wire _io_csr_in_mode_valid_T_16 = _io_taken_valid_T_13 | _io_taken_valid_T_22; // @[Bru.scala 186:53]
- wire _io_csr_in_mode_valid_T_19 = _io_csr_in_mode_valid_T_16 | _io_taken_valid_T_19; // @[Bru.scala 187:53]
- wire _io_csr_in_mcause_valid_T_3 = undefFault | usageFault | _io_taken_valid_T_1; // @[Bru.scala 201:54]
- wire _io_csr_in_mcause_valid_T_6 = _io_csr_in_mcause_valid_T_3 | _io_taken_valid_T_3; // @[Bru.scala 202:55]
- wire _io_csr_in_mcause_valid_T_9 = _io_csr_in_mcause_valid_T_6 | _io_taken_valid_T_6; // @[Bru.scala 203:55]
- wire _io_csr_in_mcause_valid_T_12 = _io_csr_in_mcause_valid_T_9 | _io_taken_valid_T_9; // @[Bru.scala 204:55]
- wire [1:0] _io_csr_in_mcause_bits_T_5 = op[9] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] _GEN_4 = {{1'd0}, op[8]}; // @[Bru.scala 211:60]
- wire [1:0] _io_csr_in_mcause_bits_T_6 = _GEN_4 | _io_csr_in_mcause_bits_T_5; // @[Bru.scala 211:60]
- wire [1:0] _io_csr_in_mcause_bits_T_8 = op[10] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] _io_csr_in_mcause_bits_T_9 = _io_csr_in_mcause_bits_T_6 | _io_csr_in_mcause_bits_T_8; // @[Bru.scala 212:60]
- wire [2:0] _io_csr_in_mcause_bits_T_11 = op[11] ? 3'h4 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _GEN_5 = {{1'd0}, _io_csr_in_mcause_bits_T_9}; // @[Bru.scala 213:60]
- wire [2:0] _io_csr_in_mcause_bits_T_12 = _GEN_5 | _io_csr_in_mcause_bits_T_11; // @[Bru.scala 213:60]
- wire [2:0] _io_csr_in_mcause_bits_T_14 = op[12] ? 3'h5 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _io_csr_in_mcause_bits_T_15 = _io_csr_in_mcause_bits_T_12 | _io_csr_in_mcause_bits_T_14; // @[Bru.scala 214:60]
- wire [31:0] _io_csr_in_mcause_bits_T_16 = usageFault ? 32'h80000010 : {{29'd0}, _io_csr_in_mcause_bits_T_15}; // @[Bru.scala 210:31]
- reg valid; // @[Bru.scala 227:22]
- wire _ignore_T_6 = _io_taken_valid_T_28 | op[8] | op[9]; // @[Bru.scala 228:71]
- wire _ignore_T_12 = _ignore_T_6 | op[10] | op[11] | op[12]; // @[Bru.scala 229:74]
- wire _ignore_T_18 = _ignore_T_12 | op[13] | op[14] | op[15]; // @[Bru.scala 230:74]
- wire ignore = _ignore_T_18 | undefFault; // @[Bru.scala 231:34]
- wire _T_5 = ~reset; // @[Bru.scala 234:9]
- assign io_csr_in_mode_valid = _io_csr_in_mode_valid_T_19 | _io_taken_valid_T_16; // @[Bru.scala 188:53]
- assign io_csr_in_mode_bits = op[14] & _mret_T_1; // @[Bru.scala 190:48]
- assign io_csr_in_mcause_valid = _io_csr_in_mcause_valid_T_12 | _io_taken_valid_T_12; // @[Bru.scala 205:55]
- assign io_csr_in_mcause_bits = undefFault ? 32'h80000002 : _io_csr_in_mcause_bits_T_16; // @[Bru.scala 209:31]
- assign io_csr_in_mepc_valid = _io_csr_in_mode_valid_T_16 | _io_taken_valid_T_19; // @[Bru.scala 197:53]
- assign io_csr_in_mepc_bits = op[11] ? linkData : pcEx; // @[Bru.scala 199:29]
- assign io_csr_in_mtval_valid = undefFault | usageFault; // @[Bru.scala 217:39]
- assign io_csr_in_mtval_bits = pcEx; // @[Bru.scala 218:24]
- assign io_csr_in_halt = op[13] & _mret_T_1 | io_csr_in_fault; // @[Bru.scala 223:48]
- assign io_csr_in_fault = undefFault & _mret_T_1 | usageFault & _mret_T_1; // @[Bru.scala 224:42]
- assign io_rd_valid = linkValid; // @[Bru.scala 166:15]
- assign io_rd_addr = linkAddr; // @[Bru.scala 167:14]
- assign io_rd_data = linkData; // @[Bru.scala 168:14]
- assign io_taken_valid = _io_taken_valid_T_25 | _io_taken_valid_T_47; // @[Bru.scala 154:39]
- assign io_taken_value = target; // @[Bru.scala 164:18]
- assign io_interlock = interlock; // @[Bru.scala 131:16]
- assign io_iflush = op[15]; // @[Bru.scala 220:18]
- always @(posedge clock) begin
- if (io_req_valid) begin // @[Bru.scala 107:23]
- if (mret) begin // @[Bru.scala 116:18]
- target <= io_csr_out_mepc;
- end else if (call) begin // @[Bru.scala 117:18]
- target <= io_csr_out_mtvec;
- end else if (io_req_fwd | io_req_op[15]) begin // @[Bru.scala 118:18]
- target <= pc4De;
- end else begin
- target <= _target_T_3;
- end
- end
- if (io_req_valid) begin // @[Bru.scala 107:23]
- linkAddr <= io_req_link; // @[Bru.scala 121:14]
- end
- if (io_req_valid) begin // @[Bru.scala 107:23]
- linkData <= pc4De; // @[Bru.scala 122:14]
- end
- if (io_req_valid) begin // @[Bru.scala 107:23]
- pcEx <= io_req_pc; // @[Bru.scala 123:10]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(valid & ~io_rs1_valid) | ignore)) begin
- $fatal; // @[Bru.scala 234:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(valid & ~io_rs1_valid) | ignore)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Bru.scala:234 assert(!(valid && !io.rs1.valid) || ignore)\n"); // @[Bru.scala 234:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_5 & ~(~(valid & ~io_rs2_valid) | ignore)) begin
- $fatal; // @[Bru.scala 235:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_5 & ~(~(valid & ~io_rs2_valid) | ignore)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Bru.scala:235 assert(!(valid && !io.rs2.valid) || ignore)\n"); // @[Bru.scala 235:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Bru.scala 126:29]
- interlock <= 1'h0;
- end else begin
- interlock <= io_req_valid & _interlock_T_12;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Bru.scala 95:23]
- fwd <= 1'h0;
- end else begin
- fwd <= io_req_valid & io_req_fwd;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Bru.scala 94:12]
- op <= 17'h0;
- end else if (io_req_valid) begin
- op <= io_req_op;
- end else begin
- op <= 17'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Bru.scala 91:52]
- linkValid <= 1'h0;
- end else begin
- linkValid <= io_req_valid & io_req_link != 5'h0 & _linkValid_T_4;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Bru.scala 227:22]
- valid <= 1'h0; // @[Bru.scala 227:22]
- end else begin
- valid <= io_req_valid; // @[Bru.scala 233:9]
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- interlock = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- fwd = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- op = _RAND_2[16:0];
- _RAND_3 = {1{`RANDOM}};
- target = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- linkValid = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- linkAddr = _RAND_5[4:0];
- _RAND_6 = {1{`RANDOM}};
- linkData = _RAND_6[31:0];
- _RAND_7 = {1{`RANDOM}};
- pcEx = _RAND_7[31:0];
- _RAND_8 = {1{`RANDOM}};
- valid = _RAND_8[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- interlock = 1'h0;
- end
- if (reset) begin
- fwd = 1'h0;
- end
- if (reset) begin
- op = 17'h0;
- end
- if (reset) begin
- linkValid = 1'h0;
- end
- if (reset) begin
- valid = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Csr(
- input clock,
- input reset,
- input [31:0] io_csr_in_value_0,
- input io_req_valid,
- input [4:0] io_req_addr,
- input [11:0] io_req_index,
- input [2:0] io_req_op,
- input io_rs1_valid,
- input [31:0] io_rs1_data,
- output io_rd_valid,
- output [4:0] io_rd_addr,
- output [31:0] io_rd_data,
- input io_bru_in_mode_valid,
- input io_bru_in_mode_bits,
- input io_bru_in_mcause_valid,
- input [31:0] io_bru_in_mcause_bits,
- input io_bru_in_mepc_valid,
- input [31:0] io_bru_in_mepc_bits,
- input io_bru_in_mtval_valid,
- input [31:0] io_bru_in_mtval_bits,
- input io_bru_in_halt,
- input io_bru_in_fault,
- output io_bru_out_mode,
- output [31:0] io_bru_out_mepc,
- output [31:0] io_bru_out_mtvec,
- input io_vcore_undef,
- output io_halted,
- output io_fault
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
-`endif // RANDOMIZE_REG_INIT
- reg valid; // @[Csr.scala 98:22]
- reg [4:0] addr; // @[Csr.scala 99:17]
- reg [11:0] index; // @[Csr.scala 100:18]
- reg [2:0] op; // @[Csr.scala 101:19]
- reg halted; // @[Csr.scala 104:23]
- reg fault; // @[Csr.scala 105:22]
- reg mode; // @[Csr.scala 108:21]
- reg [31:0] mpc; // @[Csr.scala 111:22]
- reg [31:0] msp; // @[Csr.scala 112:22]
- reg [31:0] mcause; // @[Csr.scala 113:22]
- reg [31:0] mtval; // @[Csr.scala 114:22]
- reg [31:0] mcontext0; // @[Csr.scala 115:22]
- reg [31:0] mcontext1; // @[Csr.scala 116:22]
- reg [31:0] mcontext2; // @[Csr.scala 117:22]
- reg [31:0] mcontext3; // @[Csr.scala 118:22]
- reg [31:0] mcontext4; // @[Csr.scala 119:22]
- reg [31:0] mcontext5; // @[Csr.scala 120:22]
- reg [31:0] mcontext6; // @[Csr.scala 121:22]
- reg [31:0] mcontext7; // @[Csr.scala 122:22]
- reg [4:0] fflags; // @[Csr.scala 125:26]
- reg [2:0] frm; // @[Csr.scala 126:26]
- reg mie; // @[Csr.scala 127:26]
- reg [31:0] mtvec; // @[Csr.scala 128:26]
- reg [31:0] mscratch; // @[Csr.scala 129:26]
- reg [31:0] mepc; // @[Csr.scala 130:26]
- wire [7:0] fcsr = {frm,fflags}; // @[Cat.scala 31:58]
- wire fflagsEn = index == 12'h1; // @[Csr.scala 135:27]
- wire frmEn = index == 12'h2; // @[Csr.scala 136:27]
- wire fcsrEn = index == 12'h3; // @[Csr.scala 137:27]
- wire mieEn = index == 12'h304; // @[Csr.scala 138:27]
- wire mtvecEn = index == 12'h305; // @[Csr.scala 139:27]
- wire mscratchEn = index == 12'h340; // @[Csr.scala 140:27]
- wire mepcEn = index == 12'h341; // @[Csr.scala 141:27]
- wire mcauseEn = index == 12'h342; // @[Csr.scala 142:27]
- wire mtvalEn = index == 12'h343; // @[Csr.scala 143:27]
- wire mcontext0En = index == 12'h7c0; // @[Csr.scala 144:27]
- wire mcontext1En = index == 12'h7c1; // @[Csr.scala 145:27]
- wire mcontext2En = index == 12'h7c2; // @[Csr.scala 146:27]
- wire mcontext3En = index == 12'h7c3; // @[Csr.scala 147:27]
- wire mcontext4En = index == 12'h7c4; // @[Csr.scala 148:27]
- wire mcontext5En = index == 12'h7c5; // @[Csr.scala 149:27]
- wire mcontext6En = index == 12'h7c6; // @[Csr.scala 150:27]
- wire mcontext7En = index == 12'h7c7; // @[Csr.scala 151:27]
- wire mpcEn = index == 12'h7e0; // @[Csr.scala 152:27]
- wire mspEn = index == 12'h7e1; // @[Csr.scala 153:27]
- wire _T_6 = ~reset; // @[Csr.scala 180:9]
- wire [4:0] _rdata_T = fflagsEn ? fflags : 5'h0; // @[Library.scala 22:8]
- wire [2:0] _rdata_T_1 = frmEn ? frm : 3'h0; // @[Library.scala 22:8]
- wire [4:0] _GEN_64 = {{2'd0}, _rdata_T_1}; // @[Csr.scala 185:43]
- wire [4:0] _rdata_T_2 = _rdata_T | _GEN_64; // @[Csr.scala 185:43]
- wire [7:0] _rdata_T_3 = fcsrEn ? fcsr : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _GEN_65 = {{3'd0}, _rdata_T_2}; // @[Csr.scala 186:40]
- wire [7:0] _rdata_T_4 = _GEN_65 | _rdata_T_3; // @[Csr.scala 186:40]
- wire _rdata_T_5 = mieEn & mie; // @[Library.scala 22:8]
- wire [7:0] _GEN_66 = {{7'd0}, _rdata_T_5}; // @[Csr.scala 187:41]
- wire [7:0] _rdata_T_6 = _rdata_T_4 | _GEN_66; // @[Csr.scala 187:41]
- wire [31:0] _rdata_T_7 = mtvecEn ? mtvec : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _GEN_67 = {{24'd0}, _rdata_T_6}; // @[Csr.scala 188:40]
- wire [31:0] _rdata_T_8 = _GEN_67 | _rdata_T_7; // @[Csr.scala 188:40]
- wire [31:0] _rdata_T_9 = mscratchEn ? mscratch : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rdata_T_10 = _rdata_T_8 | _rdata_T_9; // @[Csr.scala 189:42]
- wire [31:0] _rdata_T_11 = mepcEn ? mepc : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rdata_T_12 = _rdata_T_10 | _rdata_T_11; // @[Csr.scala 190:45]
- wire [31:0] _rdata_T_13 = mcauseEn ? mcause : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rdata_T_14 = _rdata_T_12 | _rdata_T_13; // @[Csr.scala 191:41]
- wire [31:0] _rdata_T_15 = mtvalEn ? mtval : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rdata_T_16 = _rdata_T_14 | _rdata_T_15; // @[Csr.scala 192:43]
- wire [31:0] _rdata_T_17 = mcontext0En ? mcontext0 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rdata_T_18 = _rdata_T_16 | _rdata_T_17; // @[Csr.scala 193:42]
- wire [31:0] _rdata_T_19 = mcontext1En ? mcontext1 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rdata_T_20 = _rdata_T_18 | _rdata_T_19; // @[Csr.scala 194:46]
- wire [31:0] _rdata_T_21 = mcontext2En ? mcontext2 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rdata_T_22 = _rdata_T_20 | _rdata_T_21; // @[Csr.scala 195:46]
- wire [31:0] _rdata_T_23 = mcontext3En ? mcontext3 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rdata_T_24 = _rdata_T_22 | _rdata_T_23; // @[Csr.scala 196:46]
- wire [31:0] _rdata_T_25 = mcontext4En ? mcontext4 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rdata_T_26 = _rdata_T_24 | _rdata_T_25; // @[Csr.scala 197:46]
- wire [31:0] _rdata_T_27 = mcontext5En ? mcontext5 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rdata_T_28 = _rdata_T_26 | _rdata_T_27; // @[Csr.scala 198:46]
- wire [31:0] _rdata_T_29 = mcontext6En ? mcontext6 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rdata_T_30 = _rdata_T_28 | _rdata_T_29; // @[Csr.scala 199:46]
- wire [31:0] _rdata_T_31 = mcontext7En ? mcontext7 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rdata_T_32 = _rdata_T_30 | _rdata_T_31; // @[Csr.scala 200:46]
- wire [31:0] _rdata_T_33 = mpcEn ? mpc : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rdata_T_34 = _rdata_T_32 | _rdata_T_33; // @[Csr.scala 201:46]
- wire [31:0] _rdata_T_35 = mspEn ? msp : 32'h0; // @[Library.scala 22:8]
- wire [31:0] rdata = _rdata_T_34 | _rdata_T_35; // @[Csr.scala 202:40]
- wire [31:0] _wdata_T_1 = op[0] ? io_rs1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _wdata_T_3 = rdata | io_rs1_data; // @[Csr.scala 206:42]
- wire [31:0] _wdata_T_4 = op[1] ? _wdata_T_3 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _wdata_T_5 = _wdata_T_1 | _wdata_T_4; // @[Csr.scala 205:41]
- wire [31:0] _wdata_T_7 = ~io_rs1_data; // @[Csr.scala 207:44]
- wire [31:0] _wdata_T_8 = rdata & _wdata_T_7; // @[Csr.scala 207:42]
- wire [31:0] _wdata_T_9 = op[2] ? _wdata_T_8 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] wdata = _wdata_T_5 | _wdata_T_9; // @[Csr.scala 206:49]
- wire [31:0] _GEN_10 = fflagsEn ? wdata : {{27'd0}, fflags}; // @[Csr.scala 210:25 125:26 210:37]
- wire [31:0] _GEN_11 = frmEn ? wdata : {{29'd0}, frm}; // @[Csr.scala 211:25 126:26 211:37]
- wire [31:0] _GEN_12 = fcsrEn ? {{27'd0}, wdata[4:0]} : _GEN_10; // @[Csr.scala 212:{25,37}]
- wire [31:0] _GEN_13 = fcsrEn ? {{29'd0}, wdata[7:5]} : _GEN_11; // @[Csr.scala 212:25 213:37]
- wire [31:0] _GEN_14 = mieEn ? wdata : {{31'd0}, mie}; // @[Csr.scala 214:25 127:26 214:37]
- wire [31:0] _GEN_30 = valid ? _GEN_12 : {{27'd0}, fflags}; // @[Csr.scala 209:16 125:26]
- wire [31:0] _GEN_31 = valid ? _GEN_13 : {{29'd0}, frm}; // @[Csr.scala 209:16 126:26]
- wire [31:0] _GEN_32 = valid ? _GEN_14 : {{31'd0}, mie}; // @[Csr.scala 209:16 127:26]
- wire firstFault = ~mcause[31]; // @[Csr.scala 236:20]
- assign io_rd_valid = valid; // @[Csr.scala 281:15]
- assign io_rd_addr = addr; // @[Csr.scala 282:15]
- assign io_rd_data = _rdata_T_34 | _rdata_T_35; // @[Csr.scala 202:40]
- assign io_bru_out_mode = mode; // @[Csr.scala 267:20]
- assign io_bru_out_mepc = mepcEn ? wdata : mepc; // @[Csr.scala 268:26]
- assign io_bru_out_mtvec = mtvecEn ? wdata : mtvec; // @[Csr.scala 269:26]
- assign io_halted = halted; // @[Csr.scala 177:13]
- assign io_fault = fault; // @[Csr.scala 178:13]
- always @(posedge clock) begin
- if (io_req_valid) begin // @[Csr.scala 156:23]
- addr <= io_req_addr; // @[Csr.scala 158:10]
- end else if (valid) begin // @[Csr.scala 161:23]
- addr <= 5'h0; // @[Csr.scala 163:10]
- end
- if (io_req_valid) begin // @[Csr.scala 156:23]
- index <= io_req_index; // @[Csr.scala 159:11]
- end else if (valid) begin // @[Csr.scala 161:23]
- index <= 12'h0; // @[Csr.scala 164:11]
- end
- if (reset) begin // @[Csr.scala 251:23]
- mpc <= io_csr_in_value_0; // @[Csr.scala 252:15]
- end else if (valid) begin // @[Csr.scala 209:16]
- if (mpcEn) begin // @[Csr.scala 220:25]
- mpc <= wdata; // @[Csr.scala 220:37]
- end
- end
- if (reset) begin // @[Csr.scala 251:23]
- msp <= 32'h0; // @[Csr.scala 253:15]
- end else if (valid) begin // @[Csr.scala 209:16]
- if (mspEn) begin // @[Csr.scala 221:25]
- msp <= wdata; // @[Csr.scala 221:37]
- end
- end
- if (reset) begin // @[Csr.scala 251:23]
- mcause <= 32'h0; // @[Csr.scala 254:15]
- end else if (io_bru_in_mcause_valid & firstFault) begin // @[Csr.scala 238:47]
- mcause <= io_bru_in_mcause_bits; // @[Csr.scala 239:12]
- end else if (valid) begin // @[Csr.scala 209:16]
- if (mcauseEn) begin // @[Csr.scala 218:25]
- mcause <= wdata; // @[Csr.scala 218:37]
- end
- end
- if (reset) begin // @[Csr.scala 251:23]
- mtval <= 32'h0; // @[Csr.scala 255:15]
- end else if (io_bru_in_mtval_valid & firstFault) begin // @[Csr.scala 242:46]
- mtval <= io_bru_in_mtval_bits; // @[Csr.scala 243:11]
- end else if (valid) begin // @[Csr.scala 209:16]
- if (mtvalEn) begin // @[Csr.scala 219:25]
- mtval <= wdata; // @[Csr.scala 219:37]
- end
- end
- if (reset) begin // @[Csr.scala 251:23]
- mcontext0 <= 32'h0; // @[Csr.scala 256:15]
- end else if (valid) begin // @[Csr.scala 209:16]
- if (mcontext0En) begin // @[Csr.scala 222:25]
- mcontext0 <= wdata; // @[Csr.scala 222:37]
- end
- end
- if (reset) begin // @[Csr.scala 251:23]
- mcontext1 <= 32'h0; // @[Csr.scala 257:15]
- end else if (valid) begin // @[Csr.scala 209:16]
- if (mcontext1En) begin // @[Csr.scala 223:25]
- mcontext1 <= wdata; // @[Csr.scala 223:37]
- end
- end
- if (reset) begin // @[Csr.scala 251:23]
- mcontext2 <= 32'h0; // @[Csr.scala 258:15]
- end else if (valid) begin // @[Csr.scala 209:16]
- if (mcontext2En) begin // @[Csr.scala 224:25]
- mcontext2 <= wdata; // @[Csr.scala 224:37]
- end
- end
- if (reset) begin // @[Csr.scala 251:23]
- mcontext3 <= 32'h0; // @[Csr.scala 259:15]
- end else if (valid) begin // @[Csr.scala 209:16]
- if (mcontext3En) begin // @[Csr.scala 225:25]
- mcontext3 <= wdata; // @[Csr.scala 225:37]
- end
- end
- if (reset) begin // @[Csr.scala 251:23]
- mcontext4 <= 32'h0; // @[Csr.scala 260:15]
- end else if (valid) begin // @[Csr.scala 209:16]
- if (mcontext4En) begin // @[Csr.scala 226:25]
- mcontext4 <= wdata; // @[Csr.scala 226:37]
- end
- end
- if (reset) begin // @[Csr.scala 251:23]
- mcontext5 <= 32'h0; // @[Csr.scala 261:15]
- end else if (valid) begin // @[Csr.scala 209:16]
- if (mcontext5En) begin // @[Csr.scala 227:25]
- mcontext5 <= wdata; // @[Csr.scala 227:37]
- end
- end
- if (reset) begin // @[Csr.scala 251:23]
- mcontext6 <= 32'h0; // @[Csr.scala 262:15]
- end else if (valid) begin // @[Csr.scala 209:16]
- if (mcontext6En) begin // @[Csr.scala 228:25]
- mcontext6 <= wdata; // @[Csr.scala 228:37]
- end
- end
- if (reset) begin // @[Csr.scala 251:23]
- mcontext7 <= 32'h0; // @[Csr.scala 263:15]
- end else if (valid) begin // @[Csr.scala 209:16]
- if (mcontext7En) begin // @[Csr.scala 229:25]
- mcontext7 <= wdata; // @[Csr.scala 229:37]
- end
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(io_fault & ~io_halted))) begin
- $fatal; // @[Csr.scala 180:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(io_fault & ~io_halted))) begin
- $fwrite(32'h80000002,"Assertion failed\n at Csr.scala:180 assert(!(io.fault && !io.halted))\n"); // @[Csr.scala 180:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_6 & ~(~(valid & ~io_rs1_valid))) begin
- $fatal; // @[Csr.scala 286:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_6 & ~(~(valid & ~io_rs1_valid))) begin
- $fwrite(32'h80000002,"Assertion failed\n at Csr.scala:286 assert(!(valid && !io.rs1.valid))\n"); // @[Csr.scala 286:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Csr.scala 156:23]
- valid <= 1'h0; // @[Csr.scala 157:11]
- end else if (io_req_valid) begin // @[Csr.scala 161:23]
- valid <= io_req_valid; // @[Csr.scala 162:11]
- end else if (valid) begin // @[Csr.scala 98:22]
- valid <= 1'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Csr.scala 156:23]
- op <= 3'h0; // @[Csr.scala 160:8]
- end else if (io_req_valid) begin // @[Csr.scala 161:23]
- op <= io_req_op; // @[Csr.scala 165:8]
- end else if (valid) begin // @[Csr.scala 101:19]
- op <= 3'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Csr.scala 169:43]
- halted <= 1'h0; // @[Csr.scala 170:12]
- end else begin
- halted <= io_bru_in_halt | io_vcore_undef | halted; // @[Csr.scala 104:23]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Csr.scala 173:44]
- fault <= 1'h0; // @[Csr.scala 174:11]
- end else begin
- fault <= io_bru_in_fault | io_vcore_undef | fault; // @[Csr.scala 105:22]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Csr.scala 232:31]
- mode <= 1'h0; // @[Csr.scala 233:10]
- end else if (io_bru_in_mode_valid) begin // @[Csr.scala 108:21]
- mode <= io_bru_in_mode_bits;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Csr.scala 125:26]
- fflags <= 5'h0; // @[Csr.scala 125:26]
- end else begin
- fflags <= _GEN_30[4:0];
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Csr.scala 126:26]
- frm <= 3'h0; // @[Csr.scala 126:26]
- end else begin
- frm <= _GEN_31[2:0];
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Csr.scala 127:26]
- mie <= 1'h0; // @[Csr.scala 127:26]
- end else begin
- mie <= _GEN_32[0];
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Csr.scala 209:16]
- mtvec <= 32'h0; // @[Csr.scala 215:25 128:26 215:37]
- end else if (valid) begin // @[Csr.scala 128:26]
- if (mtvecEn) begin
- mtvec <= wdata;
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Csr.scala 209:16]
- mscratch <= 32'h0; // @[Csr.scala 216:25 129:26 216:37]
- end else if (valid) begin // @[Csr.scala 129:26]
- if (mscratchEn) begin
- mscratch <= wdata;
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Csr.scala 246:31]
- mepc <= 32'h0; // @[Csr.scala 247:10]
- end else if (io_bru_in_mepc_valid) begin // @[Csr.scala 209:16]
- mepc <= io_bru_in_mepc_bits; // @[Csr.scala 217:25 130:26 217:37]
- end else if (valid) begin // @[Csr.scala 130:26]
- if (mepcEn) begin
- mepc <= wdata;
- end
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- valid = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- addr = _RAND_1[4:0];
- _RAND_2 = {1{`RANDOM}};
- index = _RAND_2[11:0];
- _RAND_3 = {1{`RANDOM}};
- op = _RAND_3[2:0];
- _RAND_4 = {1{`RANDOM}};
- halted = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- fault = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- mode = _RAND_6[0:0];
- _RAND_7 = {1{`RANDOM}};
- mpc = _RAND_7[31:0];
- _RAND_8 = {1{`RANDOM}};
- msp = _RAND_8[31:0];
- _RAND_9 = {1{`RANDOM}};
- mcause = _RAND_9[31:0];
- _RAND_10 = {1{`RANDOM}};
- mtval = _RAND_10[31:0];
- _RAND_11 = {1{`RANDOM}};
- mcontext0 = _RAND_11[31:0];
- _RAND_12 = {1{`RANDOM}};
- mcontext1 = _RAND_12[31:0];
- _RAND_13 = {1{`RANDOM}};
- mcontext2 = _RAND_13[31:0];
- _RAND_14 = {1{`RANDOM}};
- mcontext3 = _RAND_14[31:0];
- _RAND_15 = {1{`RANDOM}};
- mcontext4 = _RAND_15[31:0];
- _RAND_16 = {1{`RANDOM}};
- mcontext5 = _RAND_16[31:0];
- _RAND_17 = {1{`RANDOM}};
- mcontext6 = _RAND_17[31:0];
- _RAND_18 = {1{`RANDOM}};
- mcontext7 = _RAND_18[31:0];
- _RAND_19 = {1{`RANDOM}};
- fflags = _RAND_19[4:0];
- _RAND_20 = {1{`RANDOM}};
- frm = _RAND_20[2:0];
- _RAND_21 = {1{`RANDOM}};
- mie = _RAND_21[0:0];
- _RAND_22 = {1{`RANDOM}};
- mtvec = _RAND_22[31:0];
- _RAND_23 = {1{`RANDOM}};
- mscratch = _RAND_23[31:0];
- _RAND_24 = {1{`RANDOM}};
- mepc = _RAND_24[31:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- valid = 1'h0;
- end
- if (reset) begin
- op = 3'h0;
- end
- if (reset) begin
- halted = 1'h0;
- end
- if (reset) begin
- fault = 1'h0;
- end
- if (reset) begin
- mode = 1'h0;
- end
- if (reset) begin
- fflags = 5'h0;
- end
- if (reset) begin
- frm = 3'h0;
- end
- if (reset) begin
- mie = 1'h0;
- end
- if (reset) begin
- mtvec = 32'h0;
- end
- if (reset) begin
- mscratch = 32'h0;
- end
- if (reset) begin
- mepc = 32'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Slice_1(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input [31:0] io_in_bits_addr,
- input [31:0] io_in_bits_adrx,
- input [31:0] io_in_bits_data,
- input [4:0] io_in_bits_index,
- input [5:0] io_in_bits_size,
- input io_in_bits_write,
- input io_in_bits_sext,
- input io_in_bits_iload,
- input io_in_bits_fencei,
- input io_in_bits_flushat,
- input io_in_bits_flushall,
- input io_in_bits_sldst,
- input io_in_bits_vldst,
- input io_in_bits_suncd,
- input io_out_ready,
- output io_out_valid,
- output [31:0] io_out_bits_addr,
- output [31:0] io_out_bits_adrx,
- output [31:0] io_out_bits_data,
- output [4:0] io_out_bits_index,
- output [5:0] io_out_bits_size,
- output io_out_bits_write,
- output io_out_bits_sext,
- output io_out_bits_iload,
- output io_out_bits_fencei,
- output io_out_bits_flushat,
- output io_out_bits_flushall,
- output io_out_bits_sldst,
- output io_out_bits_vldst,
- output io_out_bits_suncd
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
-`endif // RANDOMIZE_REG_INIT
- reg ipos; // @[Slice.scala 38:21]
- reg opos; // @[Slice.scala 39:21]
- reg [31:0] mem_0_addr; // @[Slice.scala 41:16]
- reg [31:0] mem_0_adrx; // @[Slice.scala 41:16]
- reg [31:0] mem_0_data; // @[Slice.scala 41:16]
- reg [4:0] mem_0_index; // @[Slice.scala 41:16]
- reg [5:0] mem_0_size; // @[Slice.scala 41:16]
- reg mem_0_write; // @[Slice.scala 41:16]
- reg mem_0_sext; // @[Slice.scala 41:16]
- reg mem_0_iload; // @[Slice.scala 41:16]
- reg mem_0_fencei; // @[Slice.scala 41:16]
- reg mem_0_flushat; // @[Slice.scala 41:16]
- reg mem_0_flushall; // @[Slice.scala 41:16]
- reg mem_0_sldst; // @[Slice.scala 41:16]
- reg mem_0_vldst; // @[Slice.scala 41:16]
- reg mem_0_suncd; // @[Slice.scala 41:16]
- wire empty = ipos == opos; // @[Slice.scala 43:20]
- wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 45:28]
- wire ovalid = io_out_valid & io_out_ready; // @[Slice.scala 46:29]
- assign io_in_ready = empty | io_out_ready; // @[Slice.scala 88:28]
- assign io_out_valid = ~empty; // @[Slice.scala 102:21]
- assign io_out_bits_addr = mem_0_addr; // @[Slice.scala 103:18]
- assign io_out_bits_adrx = mem_0_adrx; // @[Slice.scala 103:18]
- assign io_out_bits_data = mem_0_data; // @[Slice.scala 103:18]
- assign io_out_bits_index = mem_0_index; // @[Slice.scala 103:18]
- assign io_out_bits_size = mem_0_size; // @[Slice.scala 103:18]
- assign io_out_bits_write = mem_0_write; // @[Slice.scala 103:18]
- assign io_out_bits_sext = mem_0_sext; // @[Slice.scala 103:18]
- assign io_out_bits_iload = mem_0_iload; // @[Slice.scala 103:18]
- assign io_out_bits_fencei = mem_0_fencei; // @[Slice.scala 103:18]
- assign io_out_bits_flushat = mem_0_flushat; // @[Slice.scala 103:18]
- assign io_out_bits_flushall = mem_0_flushall; // @[Slice.scala 103:18]
- assign io_out_bits_sldst = mem_0_sldst; // @[Slice.scala 103:18]
- assign io_out_bits_vldst = mem_0_vldst; // @[Slice.scala 103:18]
- assign io_out_bits_suncd = mem_0_suncd; // @[Slice.scala 103:18]
- always @(posedge clock) begin
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_addr <= io_in_bits_addr; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_adrx <= io_in_bits_adrx; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_data <= io_in_bits_data; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_index <= io_in_bits_index; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_size <= io_in_bits_size; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_write <= io_in_bits_write; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_sext <= io_in_bits_sext; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_iload <= io_in_bits_iload; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_fencei <= io_in_bits_fencei; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_flushat <= io_in_bits_flushat; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_flushall <= io_in_bits_flushall; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_sldst <= io_in_bits_sldst; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_vldst <= io_in_bits_vldst; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_suncd <= io_in_bits_suncd; // @[Slice.scala 94:14]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 48:17]
- ipos <= 1'h0; // @[Slice.scala 49:10]
- end else if (ivalid) begin // @[Slice.scala 38:21]
- ipos <= ipos + 1'h1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 52:17]
- opos <= 1'h0; // @[Slice.scala 53:10]
- end else if (ovalid) begin // @[Slice.scala 39:21]
- opos <= opos + 1'h1;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- ipos = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- opos = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- mem_0_addr = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- mem_0_adrx = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- mem_0_data = _RAND_4[31:0];
- _RAND_5 = {1{`RANDOM}};
- mem_0_index = _RAND_5[4:0];
- _RAND_6 = {1{`RANDOM}};
- mem_0_size = _RAND_6[5:0];
- _RAND_7 = {1{`RANDOM}};
- mem_0_write = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- mem_0_sext = _RAND_8[0:0];
- _RAND_9 = {1{`RANDOM}};
- mem_0_iload = _RAND_9[0:0];
- _RAND_10 = {1{`RANDOM}};
- mem_0_fencei = _RAND_10[0:0];
- _RAND_11 = {1{`RANDOM}};
- mem_0_flushat = _RAND_11[0:0];
- _RAND_12 = {1{`RANDOM}};
- mem_0_flushall = _RAND_12[0:0];
- _RAND_13 = {1{`RANDOM}};
- mem_0_sldst = _RAND_13[0:0];
- _RAND_14 = {1{`RANDOM}};
- mem_0_vldst = _RAND_14[0:0];
- _RAND_15 = {1{`RANDOM}};
- mem_0_suncd = _RAND_15[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- ipos = 1'h0;
- end
- if (reset) begin
- opos = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Fifo4(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [31:0] io_in_bits_0_bits_addr,
- input [31:0] io_in_bits_0_bits_adrx,
- input [31:0] io_in_bits_0_bits_data,
- input [4:0] io_in_bits_0_bits_index,
- input [5:0] io_in_bits_0_bits_size,
- input io_in_bits_0_bits_write,
- input io_in_bits_0_bits_sext,
- input io_in_bits_0_bits_iload,
- input io_in_bits_0_bits_fencei,
- input io_in_bits_0_bits_flushat,
- input io_in_bits_0_bits_flushall,
- input io_in_bits_0_bits_sldst,
- input io_in_bits_0_bits_vldst,
- input io_in_bits_0_bits_suncd,
- input io_in_bits_1_valid,
- input [31:0] io_in_bits_1_bits_addr,
- input [31:0] io_in_bits_1_bits_adrx,
- input [31:0] io_in_bits_1_bits_data,
- input [4:0] io_in_bits_1_bits_index,
- input [5:0] io_in_bits_1_bits_size,
- input io_in_bits_1_bits_write,
- input io_in_bits_1_bits_sext,
- input io_in_bits_1_bits_iload,
- input io_in_bits_1_bits_fencei,
- input io_in_bits_1_bits_flushat,
- input io_in_bits_1_bits_flushall,
- input io_in_bits_1_bits_sldst,
- input io_in_bits_1_bits_vldst,
- input io_in_bits_1_bits_suncd,
- input io_in_bits_2_valid,
- input [31:0] io_in_bits_2_bits_addr,
- input [31:0] io_in_bits_2_bits_adrx,
- input [31:0] io_in_bits_2_bits_data,
- input [4:0] io_in_bits_2_bits_index,
- input [5:0] io_in_bits_2_bits_size,
- input io_in_bits_2_bits_write,
- input io_in_bits_2_bits_sext,
- input io_in_bits_2_bits_iload,
- input io_in_bits_2_bits_fencei,
- input io_in_bits_2_bits_flushat,
- input io_in_bits_2_bits_flushall,
- input io_in_bits_2_bits_sldst,
- input io_in_bits_2_bits_vldst,
- input io_in_bits_2_bits_suncd,
- input io_in_bits_3_valid,
- input [31:0] io_in_bits_3_bits_addr,
- input [31:0] io_in_bits_3_bits_adrx,
- input [31:0] io_in_bits_3_bits_data,
- input [4:0] io_in_bits_3_bits_index,
- input [5:0] io_in_bits_3_bits_size,
- input io_in_bits_3_bits_write,
- input io_in_bits_3_bits_sext,
- input io_in_bits_3_bits_iload,
- input io_in_bits_3_bits_fencei,
- input io_in_bits_3_bits_flushat,
- input io_in_bits_3_bits_flushall,
- input io_in_bits_3_bits_sldst,
- input io_in_bits_3_bits_vldst,
- input io_in_bits_3_bits_suncd,
- input io_out_ready,
- output io_out_valid,
- output [31:0] io_out_bits_addr,
- output [31:0] io_out_bits_adrx,
- output [31:0] io_out_bits_data,
- output [4:0] io_out_bits_index,
- output [5:0] io_out_bits_size,
- output io_out_bits_write,
- output io_out_bits_sext,
- output io_out_bits_iload,
- output io_out_bits_fencei,
- output io_out_bits_flushat,
- output io_out_bits_flushall,
- output io_out_bits_sldst,
- output io_out_bits_vldst,
- output io_out_bits_suncd,
- output [3:0] io_count
-);
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_27;
-`endif // RANDOMIZE_GARBAGE_ASSIGN
-`ifdef RANDOMIZE_MEM_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_26;
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
-`endif // RANDOMIZE_REG_INIT
- reg [31:0] mem_addr [0:6]; // @[Fifo4.scala 73:16]
- wire mem_addr_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_addr_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_addr_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_addr_MPORT_27_en; // @[Fifo4.scala 73:16]
- reg [31:0] mem_adrx [0:6]; // @[Fifo4.scala 73:16]
- wire mem_adrx_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_adrx_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_adrx_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_adrx_MPORT_27_en; // @[Fifo4.scala 73:16]
- reg [31:0] mem_data [0:6]; // @[Fifo4.scala 73:16]
- wire mem_data_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire [31:0] mem_data_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_data_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_data_MPORT_27_en; // @[Fifo4.scala 73:16]
- reg [4:0] mem_index [0:6]; // @[Fifo4.scala 73:16]
- wire mem_index_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire [4:0] mem_index_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_index_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_index_MPORT_27_en; // @[Fifo4.scala 73:16]
- reg [5:0] mem_size [0:6]; // @[Fifo4.scala 73:16]
- wire mem_size_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire [5:0] mem_size_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_size_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_size_MPORT_27_en; // @[Fifo4.scala 73:16]
- reg mem_write [0:6]; // @[Fifo4.scala 73:16]
- wire mem_write_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_write_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_write_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_write_MPORT_27_en; // @[Fifo4.scala 73:16]
- reg mem_sext [0:6]; // @[Fifo4.scala 73:16]
- wire mem_sext_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sext_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_sext_MPORT_27_en; // @[Fifo4.scala 73:16]
- reg mem_iload [0:6]; // @[Fifo4.scala 73:16]
- wire mem_iload_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_iload_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_iload_MPORT_27_en; // @[Fifo4.scala 73:16]
- reg mem_fencei [0:6]; // @[Fifo4.scala 73:16]
- wire mem_fencei_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_fencei_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_fencei_MPORT_27_en; // @[Fifo4.scala 73:16]
- reg mem_flushat [0:6]; // @[Fifo4.scala 73:16]
- wire mem_flushat_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushat_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_flushat_MPORT_27_en; // @[Fifo4.scala 73:16]
- reg mem_flushall [0:6]; // @[Fifo4.scala 73:16]
- wire mem_flushall_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_flushall_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_flushall_MPORT_27_en; // @[Fifo4.scala 73:16]
- reg mem_sldst [0:6]; // @[Fifo4.scala 73:16]
- wire mem_sldst_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_sldst_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_sldst_MPORT_27_en; // @[Fifo4.scala 73:16]
- reg mem_vldst [0:6]; // @[Fifo4.scala 73:16]
- wire mem_vldst_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_vldst_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_vldst_MPORT_27_en; // @[Fifo4.scala 73:16]
- reg mem_suncd [0:6]; // @[Fifo4.scala 73:16]
- wire mem_suncd_mslice_io_in_bits_MPORT_en; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_mslice_io_in_bits_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_mslice_io_in_bits_MPORT_data; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_1_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_1_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_1_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_1_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_2_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_2_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_2_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_2_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_3_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_3_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_3_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_3_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_4_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_4_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_4_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_4_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_5_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_5_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_5_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_5_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_6_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_6_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_6_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_6_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_7_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_7_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_7_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_7_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_8_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_8_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_8_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_8_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_9_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_9_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_9_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_9_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_10_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_10_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_10_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_10_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_11_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_11_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_11_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_11_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_12_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_12_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_12_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_12_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_13_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_13_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_13_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_13_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_14_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_14_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_14_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_14_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_15_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_15_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_15_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_15_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_16_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_16_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_16_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_16_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_17_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_17_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_17_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_17_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_18_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_18_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_18_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_18_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_19_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_19_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_19_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_19_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_20_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_20_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_20_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_20_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_21_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_21_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_21_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_21_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_22_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_22_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_22_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_22_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_23_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_23_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_23_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_23_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_24_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_24_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_24_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_24_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_25_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_25_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_25_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_25_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_26_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_26_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_26_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_26_en; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_27_data; // @[Fifo4.scala 73:16]
- wire [2:0] mem_suncd_MPORT_27_addr; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_27_mask; // @[Fifo4.scala 73:16]
- wire mem_suncd_MPORT_27_en; // @[Fifo4.scala 73:16]
- wire mslice_clock; // @[Slice.scala 23:11]
- wire mslice_reset; // @[Slice.scala 23:11]
- wire mslice_io_in_ready; // @[Slice.scala 23:11]
- wire mslice_io_in_valid; // @[Slice.scala 23:11]
- wire [31:0] mslice_io_in_bits_addr; // @[Slice.scala 23:11]
- wire [31:0] mslice_io_in_bits_adrx; // @[Slice.scala 23:11]
- wire [31:0] mslice_io_in_bits_data; // @[Slice.scala 23:11]
- wire [4:0] mslice_io_in_bits_index; // @[Slice.scala 23:11]
- wire [5:0] mslice_io_in_bits_size; // @[Slice.scala 23:11]
- wire mslice_io_in_bits_write; // @[Slice.scala 23:11]
- wire mslice_io_in_bits_sext; // @[Slice.scala 23:11]
- wire mslice_io_in_bits_iload; // @[Slice.scala 23:11]
- wire mslice_io_in_bits_fencei; // @[Slice.scala 23:11]
- wire mslice_io_in_bits_flushat; // @[Slice.scala 23:11]
- wire mslice_io_in_bits_flushall; // @[Slice.scala 23:11]
- wire mslice_io_in_bits_sldst; // @[Slice.scala 23:11]
- wire mslice_io_in_bits_vldst; // @[Slice.scala 23:11]
- wire mslice_io_in_bits_suncd; // @[Slice.scala 23:11]
- wire mslice_io_out_ready; // @[Slice.scala 23:11]
- wire mslice_io_out_valid; // @[Slice.scala 23:11]
- wire [31:0] mslice_io_out_bits_addr; // @[Slice.scala 23:11]
- wire [31:0] mslice_io_out_bits_adrx; // @[Slice.scala 23:11]
- wire [31:0] mslice_io_out_bits_data; // @[Slice.scala 23:11]
- wire [4:0] mslice_io_out_bits_index; // @[Slice.scala 23:11]
- wire [5:0] mslice_io_out_bits_size; // @[Slice.scala 23:11]
- wire mslice_io_out_bits_write; // @[Slice.scala 23:11]
- wire mslice_io_out_bits_sext; // @[Slice.scala 23:11]
- wire mslice_io_out_bits_iload; // @[Slice.scala 23:11]
- wire mslice_io_out_bits_fencei; // @[Slice.scala 23:11]
- wire mslice_io_out_bits_flushat; // @[Slice.scala 23:11]
- wire mslice_io_out_bits_flushall; // @[Slice.scala 23:11]
- wire mslice_io_out_bits_sldst; // @[Slice.scala 23:11]
- wire mslice_io_out_bits_vldst; // @[Slice.scala 23:11]
- wire mslice_io_out_bits_suncd; // @[Slice.scala 23:11]
- reg [2:0] in0pos; // @[Fifo4.scala 76:23]
- reg [2:0] in1pos; // @[Fifo4.scala 77:23]
- reg [2:0] in2pos; // @[Fifo4.scala 78:23]
- reg [2:0] in3pos; // @[Fifo4.scala 79:23]
- reg [2:0] outpos; // @[Fifo4.scala 80:23]
- reg [3:0] mcount; // @[Fifo4.scala 81:23]
- wire [3:0] _GEN_1846 = {{3'd0}, io_out_valid}; // @[Fifo4.scala 83:22]
- wire ivalid = io_in_valid & io_in_ready; // @[Fifo4.scala 85:28]
- wire ovalid = mslice_io_in_valid & mslice_io_in_ready; // @[Fifo4.scala 86:35]
- wire [3:0] iactive = {io_in_bits_3_valid,io_in_bits_2_valid,io_in_bits_1_valid,io_in_bits_0_valid}; // @[Cat.scala 31:58]
- wire [1:0] _icount_T = io_in_bits_0_valid + io_in_bits_1_valid; // @[Fifo4.scala 91:36]
- wire [1:0] _GEN_1847 = {{1'd0}, io_in_bits_2_valid}; // @[Fifo4.scala 91:59]
- wire [1:0] _icount_T_2 = _icount_T + _GEN_1847; // @[Fifo4.scala 91:59]
- wire [1:0] _GEN_1848 = {{1'd0}, io_in_bits_3_valid}; // @[Fifo4.scala 92:36]
- wire [2:0] icount = _icount_T_2 + _GEN_1848; // @[Fifo4.scala 92:36]
- wire [3:0] in0pos_c = in0pos + icount; // @[Fifo4.scala 68:15]
- wire [3:0] _in0pos_d_T_2 = in0pos_c - 4'h7; // @[Fifo4.scala 69:31]
- wire [3:0] _in0pos_d_T_3 = in0pos_c < 4'h7 ? in0pos_c : _in0pos_d_T_2; // @[Fifo4.scala 69:16]
- wire [2:0] in0pos_d = _in0pos_d_T_3[2:0]; // @[Fifo4.scala 69:37]
- wire [3:0] in1pos_c = in1pos + icount; // @[Fifo4.scala 68:15]
- wire [3:0] _in1pos_d_T_2 = in1pos_c - 4'h7; // @[Fifo4.scala 69:31]
- wire [3:0] _in1pos_d_T_3 = in1pos_c < 4'h7 ? in1pos_c : _in1pos_d_T_2; // @[Fifo4.scala 69:16]
- wire [2:0] in1pos_d = _in1pos_d_T_3[2:0]; // @[Fifo4.scala 69:37]
- wire [3:0] in2pos_c = in2pos + icount; // @[Fifo4.scala 68:15]
- wire [3:0] _in2pos_d_T_2 = in2pos_c - 4'h7; // @[Fifo4.scala 69:31]
- wire [3:0] _in2pos_d_T_3 = in2pos_c < 4'h7 ? in2pos_c : _in2pos_d_T_2; // @[Fifo4.scala 69:16]
- wire [2:0] in2pos_d = _in2pos_d_T_3[2:0]; // @[Fifo4.scala 69:37]
- wire [3:0] in3pos_c = in3pos + icount; // @[Fifo4.scala 68:15]
- wire [3:0] _in3pos_d_T_2 = in3pos_c - 4'h7; // @[Fifo4.scala 69:31]
- wire [3:0] _in3pos_d_T_3 = in3pos_c < 4'h7 ? in3pos_c : _in3pos_d_T_2; // @[Fifo4.scala 69:16]
- wire [2:0] in3pos_d = _in3pos_d_T_3[2:0]; // @[Fifo4.scala 69:37]
- wire [3:0] outpos_c = outpos + 3'h1; // @[Fifo4.scala 68:15]
- wire [3:0] _outpos_d_T_2 = outpos_c - 4'h7; // @[Fifo4.scala 69:31]
- wire [3:0] _outpos_d_T_3 = outpos_c < 4'h7 ? outpos_c : _outpos_d_T_2; // @[Fifo4.scala 69:16]
- wire [2:0] outpos_d = _outpos_d_T_3[2:0]; // @[Fifo4.scala 69:37]
- wire [2:0] inc = ivalid ? icount : 3'h0; // @[Library.scala 22:8]
- wire [3:0] _GEN_1849 = {{1'd0}, inc}; // @[Fifo4.scala 111:22]
- wire [3:0] _mcount_T_1 = mcount + _GEN_1849; // @[Fifo4.scala 111:22]
- wire [3:0] _GEN_1850 = {{3'd0}, ovalid}; // @[Fifo4.scala 111:28]
- wire [3:0] _mcount_T_3 = _mcount_T_1 - _GEN_1850; // @[Fifo4.scala 111:28]
- wire _in0_T_1 = iactive == 4'h8; // @[Fifo4.scala 31:27]
- wire _in0_T_3 = iactive[2:0] == 3'h4; // @[Fifo4.scala 32:27]
- wire _in0_T_5 = iactive[1:0] == 2'h2; // @[Fifo4.scala 33:27]
- wire [3:0] in0valid = {_in0_T_1,_in0_T_3,_in0_T_5,iactive[0]}; // @[Cat.scala 31:58]
- wire _in1_T_3 = iactive == 4'ha; // @[Fifo4.scala 37:27]
- wire _in1_T_4 = iactive == 4'hc | _in1_T_3; // @[Fifo4.scala 36:36]
- wire _in1_T_6 = iactive == 4'h9; // @[Fifo4.scala 38:27]
- wire _in1_T_7 = _in1_T_4 | _in1_T_6; // @[Fifo4.scala 37:36]
- wire _in1_T_11 = iactive[2:0] == 3'h5; // @[Fifo4.scala 40:27]
- wire _in1_T_12 = iactive[2:0] == 3'h6 | _in1_T_11; // @[Fifo4.scala 39:35]
- wire _in1_T_14 = iactive[1:0] == 2'h3; // @[Fifo4.scala 41:27]
- wire [3:0] in1valid = {_in1_T_7,_in1_T_12,_in1_T_14,1'h0}; // @[Cat.scala 31:58]
- wire _in2_T_3 = iactive == 4'hd; // @[Fifo4.scala 45:27]
- wire _in2_T_4 = iactive == 4'he | _in2_T_3; // @[Fifo4.scala 44:36]
- wire _in2_T_6 = iactive == 4'hb; // @[Fifo4.scala 46:27]
- wire _in2_T_7 = _in2_T_4 | _in2_T_6; // @[Fifo4.scala 45:36]
- wire [3:0] _GEN_1851 = {{1'd0}, iactive[2:0]}; // @[Fifo4.scala 47:27]
- wire _in2_T_11 = iactive[2:0] == 3'h7; // @[Fifo4.scala 48:27]
- wire _in2_T_12 = _GEN_1851 == 4'hf | _in2_T_11; // @[Fifo4.scala 47:36]
- wire [3:0] in2valid = {_in2_T_7,_in2_T_12,2'h0}; // @[Cat.scala 31:58]
- wire _in3_T_1 = iactive == 4'hf; // @[Fifo4.scala 51:27]
- wire [3:0] in3valid = {_in3_T_1,1'h0,2'h0}; // @[Cat.scala 31:58]
- wire _valid_T = in0pos == 3'h0; // @[Fifo4.scala 119:28]
- wire _valid_T_3 = in1pos == 3'h0; // @[Fifo4.scala 120:28]
- wire _valid_T_5 = in1pos == 3'h0 & in1valid[3]; // @[Fifo4.scala 120:36]
- wire _valid_T_6 = in0pos == 3'h0 & in0valid[3] | _valid_T_5; // @[Fifo4.scala 119:51]
- wire _valid_T_7 = in2pos == 3'h0; // @[Fifo4.scala 121:28]
- wire _valid_T_9 = in2pos == 3'h0 & in2valid[3]; // @[Fifo4.scala 121:36]
- wire _valid_T_10 = _valid_T_6 | _valid_T_9; // @[Fifo4.scala 120:51]
- wire _valid_T_13 = in3pos == 3'h0 & in3valid[3]; // @[Fifo4.scala 122:36]
- wire _valid_T_14 = _valid_T_10 | _valid_T_13; // @[Fifo4.scala 121:51]
- wire _valid_T_20 = _valid_T_3 & in1valid[2]; // @[Fifo4.scala 124:36]
- wire _valid_T_21 = _valid_T & in0valid[2] | _valid_T_20; // @[Fifo4.scala 123:51]
- wire _valid_T_24 = _valid_T_7 & in2valid[2]; // @[Fifo4.scala 125:36]
- wire _valid_T_25 = _valid_T_21 | _valid_T_24; // @[Fifo4.scala 124:51]
- wire _valid_T_31 = _valid_T_3 & in1valid[1]; // @[Fifo4.scala 127:36]
- wire _valid_T_32 = _valid_T & in0valid[1] | _valid_T_31; // @[Fifo4.scala 126:51]
- wire _valid_T_35 = _valid_T & in0valid[0]; // @[Fifo4.scala 128:36]
- wire [3:0] valid = {_valid_T_14,_valid_T_25,_valid_T_32,_valid_T_35}; // @[Cat.scala 31:58]
- wire _GEN_44 = valid[2] ? 1'h0 : valid[3]; // @[Fifo4.scala 135:30 73:16]
- wire _GEN_80 = valid[1] ? 1'h0 : valid[2]; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_98 = valid[1] ? 1'h0 : _GEN_44; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_134 = valid[0] ? 1'h0 : valid[1]; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_152 = valid[0] ? 1'h0 : _GEN_80; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_170 = valid[0] ? 1'h0 : _GEN_98; // @[Fifo4.scala 131:23 73:16]
- wire _valid_T_36 = in0pos == 3'h1; // @[Fifo4.scala 119:28]
- wire _valid_T_39 = in1pos == 3'h1; // @[Fifo4.scala 120:28]
- wire _valid_T_41 = in1pos == 3'h1 & in1valid[3]; // @[Fifo4.scala 120:36]
- wire _valid_T_42 = in0pos == 3'h1 & in0valid[3] | _valid_T_41; // @[Fifo4.scala 119:51]
- wire _valid_T_43 = in2pos == 3'h1; // @[Fifo4.scala 121:28]
- wire _valid_T_45 = in2pos == 3'h1 & in2valid[3]; // @[Fifo4.scala 121:36]
- wire _valid_T_46 = _valid_T_42 | _valid_T_45; // @[Fifo4.scala 120:51]
- wire _valid_T_49 = in3pos == 3'h1 & in3valid[3]; // @[Fifo4.scala 122:36]
- wire _valid_T_50 = _valid_T_46 | _valid_T_49; // @[Fifo4.scala 121:51]
- wire _valid_T_56 = _valid_T_39 & in1valid[2]; // @[Fifo4.scala 124:36]
- wire _valid_T_57 = _valid_T_36 & in0valid[2] | _valid_T_56; // @[Fifo4.scala 123:51]
- wire _valid_T_60 = _valid_T_43 & in2valid[2]; // @[Fifo4.scala 125:36]
- wire _valid_T_61 = _valid_T_57 | _valid_T_60; // @[Fifo4.scala 124:51]
- wire _valid_T_67 = _valid_T_39 & in1valid[1]; // @[Fifo4.scala 127:36]
- wire _valid_T_68 = _valid_T_36 & in0valid[1] | _valid_T_67; // @[Fifo4.scala 126:51]
- wire _valid_T_71 = _valid_T_36 & in0valid[0]; // @[Fifo4.scala 128:36]
- wire [3:0] valid_1 = {_valid_T_50,_valid_T_61,_valid_T_68,_valid_T_71}; // @[Cat.scala 31:58]
- wire _GEN_294 = valid_1[2] ? 1'h0 : valid_1[3]; // @[Fifo4.scala 135:30 73:16]
- wire _GEN_328 = valid_1[1] ? 1'h0 : valid_1[2]; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_345 = valid_1[1] ? 1'h0 : _GEN_294; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_379 = valid_1[0] ? 1'h0 : valid_1[1]; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_396 = valid_1[0] ? 1'h0 : _GEN_328; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_413 = valid_1[0] ? 1'h0 : _GEN_345; // @[Fifo4.scala 131:23 73:16]
- wire _valid_T_72 = in0pos == 3'h2; // @[Fifo4.scala 119:28]
- wire _valid_T_75 = in1pos == 3'h2; // @[Fifo4.scala 120:28]
- wire _valid_T_77 = in1pos == 3'h2 & in1valid[3]; // @[Fifo4.scala 120:36]
- wire _valid_T_78 = in0pos == 3'h2 & in0valid[3] | _valid_T_77; // @[Fifo4.scala 119:51]
- wire _valid_T_79 = in2pos == 3'h2; // @[Fifo4.scala 121:28]
- wire _valid_T_81 = in2pos == 3'h2 & in2valid[3]; // @[Fifo4.scala 121:36]
- wire _valid_T_82 = _valid_T_78 | _valid_T_81; // @[Fifo4.scala 120:51]
- wire _valid_T_85 = in3pos == 3'h2 & in3valid[3]; // @[Fifo4.scala 122:36]
- wire _valid_T_86 = _valid_T_82 | _valid_T_85; // @[Fifo4.scala 121:51]
- wire _valid_T_92 = _valid_T_75 & in1valid[2]; // @[Fifo4.scala 124:36]
- wire _valid_T_93 = _valid_T_72 & in0valid[2] | _valid_T_92; // @[Fifo4.scala 123:51]
- wire _valid_T_96 = _valid_T_79 & in2valid[2]; // @[Fifo4.scala 125:36]
- wire _valid_T_97 = _valid_T_93 | _valid_T_96; // @[Fifo4.scala 124:51]
- wire _valid_T_103 = _valid_T_75 & in1valid[1]; // @[Fifo4.scala 127:36]
- wire _valid_T_104 = _valid_T_72 & in0valid[1] | _valid_T_103; // @[Fifo4.scala 126:51]
- wire _valid_T_107 = _valid_T_72 & in0valid[0]; // @[Fifo4.scala 128:36]
- wire [3:0] valid_2 = {_valid_T_86,_valid_T_97,_valid_T_104,_valid_T_107}; // @[Cat.scala 31:58]
- wire _GEN_534 = valid_2[2] ? 1'h0 : valid_2[3]; // @[Fifo4.scala 135:30 73:16]
- wire _GEN_570 = valid_2[1] ? 1'h0 : valid_2[2]; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_588 = valid_2[1] ? 1'h0 : _GEN_534; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_624 = valid_2[0] ? 1'h0 : valid_2[1]; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_642 = valid_2[0] ? 1'h0 : _GEN_570; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_660 = valid_2[0] ? 1'h0 : _GEN_588; // @[Fifo4.scala 131:23 73:16]
- wire _valid_T_108 = in0pos == 3'h3; // @[Fifo4.scala 119:28]
- wire _valid_T_111 = in1pos == 3'h3; // @[Fifo4.scala 120:28]
- wire _valid_T_113 = in1pos == 3'h3 & in1valid[3]; // @[Fifo4.scala 120:36]
- wire _valid_T_114 = in0pos == 3'h3 & in0valid[3] | _valid_T_113; // @[Fifo4.scala 119:51]
- wire _valid_T_115 = in2pos == 3'h3; // @[Fifo4.scala 121:28]
- wire _valid_T_117 = in2pos == 3'h3 & in2valid[3]; // @[Fifo4.scala 121:36]
- wire _valid_T_118 = _valid_T_114 | _valid_T_117; // @[Fifo4.scala 120:51]
- wire _valid_T_121 = in3pos == 3'h3 & in3valid[3]; // @[Fifo4.scala 122:36]
- wire _valid_T_122 = _valid_T_118 | _valid_T_121; // @[Fifo4.scala 121:51]
- wire _valid_T_128 = _valid_T_111 & in1valid[2]; // @[Fifo4.scala 124:36]
- wire _valid_T_129 = _valid_T_108 & in0valid[2] | _valid_T_128; // @[Fifo4.scala 123:51]
- wire _valid_T_132 = _valid_T_115 & in2valid[2]; // @[Fifo4.scala 125:36]
- wire _valid_T_133 = _valid_T_129 | _valid_T_132; // @[Fifo4.scala 124:51]
- wire _valid_T_139 = _valid_T_111 & in1valid[1]; // @[Fifo4.scala 127:36]
- wire _valid_T_140 = _valid_T_108 & in0valid[1] | _valid_T_139; // @[Fifo4.scala 126:51]
- wire _valid_T_143 = _valid_T_108 & in0valid[0]; // @[Fifo4.scala 128:36]
- wire [3:0] valid_3 = {_valid_T_122,_valid_T_133,_valid_T_140,_valid_T_143}; // @[Cat.scala 31:58]
- wire _GEN_786 = valid_3[2] ? 1'h0 : valid_3[3]; // @[Fifo4.scala 135:30 73:16]
- wire _GEN_822 = valid_3[1] ? 1'h0 : valid_3[2]; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_840 = valid_3[1] ? 1'h0 : _GEN_786; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_876 = valid_3[0] ? 1'h0 : valid_3[1]; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_894 = valid_3[0] ? 1'h0 : _GEN_822; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_912 = valid_3[0] ? 1'h0 : _GEN_840; // @[Fifo4.scala 131:23 73:16]
- wire _valid_T_144 = in0pos == 3'h4; // @[Fifo4.scala 119:28]
- wire _valid_T_147 = in1pos == 3'h4; // @[Fifo4.scala 120:28]
- wire _valid_T_149 = in1pos == 3'h4 & in1valid[3]; // @[Fifo4.scala 120:36]
- wire _valid_T_150 = in0pos == 3'h4 & in0valid[3] | _valid_T_149; // @[Fifo4.scala 119:51]
- wire _valid_T_151 = in2pos == 3'h4; // @[Fifo4.scala 121:28]
- wire _valid_T_153 = in2pos == 3'h4 & in2valid[3]; // @[Fifo4.scala 121:36]
- wire _valid_T_154 = _valid_T_150 | _valid_T_153; // @[Fifo4.scala 120:51]
- wire _valid_T_157 = in3pos == 3'h4 & in3valid[3]; // @[Fifo4.scala 122:36]
- wire _valid_T_158 = _valid_T_154 | _valid_T_157; // @[Fifo4.scala 121:51]
- wire _valid_T_164 = _valid_T_147 & in1valid[2]; // @[Fifo4.scala 124:36]
- wire _valid_T_165 = _valid_T_144 & in0valid[2] | _valid_T_164; // @[Fifo4.scala 123:51]
- wire _valid_T_168 = _valid_T_151 & in2valid[2]; // @[Fifo4.scala 125:36]
- wire _valid_T_169 = _valid_T_165 | _valid_T_168; // @[Fifo4.scala 124:51]
- wire _valid_T_175 = _valid_T_147 & in1valid[1]; // @[Fifo4.scala 127:36]
- wire _valid_T_176 = _valid_T_144 & in0valid[1] | _valid_T_175; // @[Fifo4.scala 126:51]
- wire _valid_T_179 = _valid_T_144 & in0valid[0]; // @[Fifo4.scala 128:36]
- wire [3:0] valid_4 = {_valid_T_158,_valid_T_169,_valid_T_176,_valid_T_179}; // @[Cat.scala 31:58]
- wire _GEN_1038 = valid_4[2] ? 1'h0 : valid_4[3]; // @[Fifo4.scala 135:30 73:16]
- wire _GEN_1074 = valid_4[1] ? 1'h0 : valid_4[2]; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_1092 = valid_4[1] ? 1'h0 : _GEN_1038; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_1128 = valid_4[0] ? 1'h0 : valid_4[1]; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_1146 = valid_4[0] ? 1'h0 : _GEN_1074; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_1164 = valid_4[0] ? 1'h0 : _GEN_1092; // @[Fifo4.scala 131:23 73:16]
- wire _valid_T_180 = in0pos == 3'h5; // @[Fifo4.scala 119:28]
- wire _valid_T_183 = in1pos == 3'h5; // @[Fifo4.scala 120:28]
- wire _valid_T_185 = in1pos == 3'h5 & in1valid[3]; // @[Fifo4.scala 120:36]
- wire _valid_T_186 = in0pos == 3'h5 & in0valid[3] | _valid_T_185; // @[Fifo4.scala 119:51]
- wire _valid_T_187 = in2pos == 3'h5; // @[Fifo4.scala 121:28]
- wire _valid_T_189 = in2pos == 3'h5 & in2valid[3]; // @[Fifo4.scala 121:36]
- wire _valid_T_190 = _valid_T_186 | _valid_T_189; // @[Fifo4.scala 120:51]
- wire _valid_T_193 = in3pos == 3'h5 & in3valid[3]; // @[Fifo4.scala 122:36]
- wire _valid_T_194 = _valid_T_190 | _valid_T_193; // @[Fifo4.scala 121:51]
- wire _valid_T_200 = _valid_T_183 & in1valid[2]; // @[Fifo4.scala 124:36]
- wire _valid_T_201 = _valid_T_180 & in0valid[2] | _valid_T_200; // @[Fifo4.scala 123:51]
- wire _valid_T_204 = _valid_T_187 & in2valid[2]; // @[Fifo4.scala 125:36]
- wire _valid_T_205 = _valid_T_201 | _valid_T_204; // @[Fifo4.scala 124:51]
- wire _valid_T_211 = _valid_T_183 & in1valid[1]; // @[Fifo4.scala 127:36]
- wire _valid_T_212 = _valid_T_180 & in0valid[1] | _valid_T_211; // @[Fifo4.scala 126:51]
- wire _valid_T_215 = _valid_T_180 & in0valid[0]; // @[Fifo4.scala 128:36]
- wire [3:0] valid_5 = {_valid_T_194,_valid_T_205,_valid_T_212,_valid_T_215}; // @[Cat.scala 31:58]
- wire _GEN_1290 = valid_5[2] ? 1'h0 : valid_5[3]; // @[Fifo4.scala 135:30 73:16]
- wire _GEN_1326 = valid_5[1] ? 1'h0 : valid_5[2]; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_1344 = valid_5[1] ? 1'h0 : _GEN_1290; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_1380 = valid_5[0] ? 1'h0 : valid_5[1]; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_1398 = valid_5[0] ? 1'h0 : _GEN_1326; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_1416 = valid_5[0] ? 1'h0 : _GEN_1344; // @[Fifo4.scala 131:23 73:16]
- wire _valid_T_216 = in0pos == 3'h6; // @[Fifo4.scala 119:28]
- wire _valid_T_219 = in1pos == 3'h6; // @[Fifo4.scala 120:28]
- wire _valid_T_221 = in1pos == 3'h6 & in1valid[3]; // @[Fifo4.scala 120:36]
- wire _valid_T_222 = in0pos == 3'h6 & in0valid[3] | _valid_T_221; // @[Fifo4.scala 119:51]
- wire _valid_T_223 = in2pos == 3'h6; // @[Fifo4.scala 121:28]
- wire _valid_T_225 = in2pos == 3'h6 & in2valid[3]; // @[Fifo4.scala 121:36]
- wire _valid_T_226 = _valid_T_222 | _valid_T_225; // @[Fifo4.scala 120:51]
- wire _valid_T_229 = in3pos == 3'h6 & in3valid[3]; // @[Fifo4.scala 122:36]
- wire _valid_T_230 = _valid_T_226 | _valid_T_229; // @[Fifo4.scala 121:51]
- wire _valid_T_236 = _valid_T_219 & in1valid[2]; // @[Fifo4.scala 124:36]
- wire _valid_T_237 = _valid_T_216 & in0valid[2] | _valid_T_236; // @[Fifo4.scala 123:51]
- wire _valid_T_240 = _valid_T_223 & in2valid[2]; // @[Fifo4.scala 125:36]
- wire _valid_T_241 = _valid_T_237 | _valid_T_240; // @[Fifo4.scala 124:51]
- wire _valid_T_247 = _valid_T_219 & in1valid[1]; // @[Fifo4.scala 127:36]
- wire _valid_T_248 = _valid_T_216 & in0valid[1] | _valid_T_247; // @[Fifo4.scala 126:51]
- wire _valid_T_251 = _valid_T_216 & in0valid[0]; // @[Fifo4.scala 128:36]
- wire [3:0] valid_6 = {_valid_T_230,_valid_T_241,_valid_T_248,_valid_T_251}; // @[Cat.scala 31:58]
- wire _GEN_1542 = valid_6[2] ? 1'h0 : valid_6[3]; // @[Fifo4.scala 135:30 73:16]
- wire _GEN_1578 = valid_6[1] ? 1'h0 : valid_6[2]; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_1596 = valid_6[1] ? 1'h0 : _GEN_1542; // @[Fifo4.scala 133:30 73:16]
- wire _GEN_1632 = valid_6[0] ? 1'h0 : valid_6[1]; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_1650 = valid_6[0] ? 1'h0 : _GEN_1578; // @[Fifo4.scala 131:23 73:16]
- wire _GEN_1668 = valid_6[0] ? 1'h0 : _GEN_1596; // @[Fifo4.scala 131:23 73:16]
- wire _T_29 = mcount > 4'h0; // @[Fifo4.scala 146:16]
- wire _T_31 = ivalid & iactive != 4'h0; // @[Fifo4.scala 151:18]
- wire _GEN_1759 = iactive[3] ? io_in_bits_3_bits_suncd : io_in_bits_0_bits_suncd; // @[Fifo4.scala 144:21 165:30 166:25]
- wire _GEN_1760 = iactive[3] ? io_in_bits_3_bits_vldst : io_in_bits_0_bits_vldst; // @[Fifo4.scala 144:21 165:30 166:25]
- wire _GEN_1761 = iactive[3] ? io_in_bits_3_bits_sldst : io_in_bits_0_bits_sldst; // @[Fifo4.scala 144:21 165:30 166:25]
- wire _GEN_1762 = iactive[3] ? io_in_bits_3_bits_flushall : io_in_bits_0_bits_flushall; // @[Fifo4.scala 144:21 165:30 166:25]
- wire _GEN_1763 = iactive[3] ? io_in_bits_3_bits_flushat : io_in_bits_0_bits_flushat; // @[Fifo4.scala 144:21 165:30 166:25]
- wire _GEN_1764 = iactive[3] ? io_in_bits_3_bits_fencei : io_in_bits_0_bits_fencei; // @[Fifo4.scala 144:21 165:30 166:25]
- wire _GEN_1765 = iactive[3] ? io_in_bits_3_bits_iload : io_in_bits_0_bits_iload; // @[Fifo4.scala 144:21 165:30 166:25]
- wire _GEN_1766 = iactive[3] ? io_in_bits_3_bits_sext : io_in_bits_0_bits_sext; // @[Fifo4.scala 144:21 165:30 166:25]
- wire _GEN_1767 = iactive[3] ? io_in_bits_3_bits_write : io_in_bits_0_bits_write; // @[Fifo4.scala 144:21 165:30 166:25]
- wire [5:0] _GEN_1768 = iactive[3] ? io_in_bits_3_bits_size : io_in_bits_0_bits_size; // @[Fifo4.scala 144:21 165:30 166:25]
- wire [4:0] _GEN_1769 = iactive[3] ? io_in_bits_3_bits_index : io_in_bits_0_bits_index; // @[Fifo4.scala 144:21 165:30 166:25]
- wire [31:0] _GEN_1770 = iactive[3] ? io_in_bits_3_bits_data : io_in_bits_0_bits_data; // @[Fifo4.scala 144:21 165:30 166:25]
- wire [31:0] _GEN_1771 = iactive[3] ? io_in_bits_3_bits_adrx : io_in_bits_0_bits_adrx; // @[Fifo4.scala 144:21 165:30 166:25]
- wire [31:0] _GEN_1772 = iactive[3] ? io_in_bits_3_bits_addr : io_in_bits_0_bits_addr; // @[Fifo4.scala 144:21 165:30 166:25]
- wire _GEN_1773 = iactive[2] ? io_in_bits_2_bits_suncd : _GEN_1759; // @[Fifo4.scala 163:30 164:25]
- wire _GEN_1774 = iactive[2] ? io_in_bits_2_bits_vldst : _GEN_1760; // @[Fifo4.scala 163:30 164:25]
- wire _GEN_1775 = iactive[2] ? io_in_bits_2_bits_sldst : _GEN_1761; // @[Fifo4.scala 163:30 164:25]
- wire _GEN_1776 = iactive[2] ? io_in_bits_2_bits_flushall : _GEN_1762; // @[Fifo4.scala 163:30 164:25]
- wire _GEN_1777 = iactive[2] ? io_in_bits_2_bits_flushat : _GEN_1763; // @[Fifo4.scala 163:30 164:25]
- wire _GEN_1778 = iactive[2] ? io_in_bits_2_bits_fencei : _GEN_1764; // @[Fifo4.scala 163:30 164:25]
- wire _GEN_1779 = iactive[2] ? io_in_bits_2_bits_iload : _GEN_1765; // @[Fifo4.scala 163:30 164:25]
- wire _GEN_1780 = iactive[2] ? io_in_bits_2_bits_sext : _GEN_1766; // @[Fifo4.scala 163:30 164:25]
- wire _GEN_1781 = iactive[2] ? io_in_bits_2_bits_write : _GEN_1767; // @[Fifo4.scala 163:30 164:25]
- wire [5:0] _GEN_1782 = iactive[2] ? io_in_bits_2_bits_size : _GEN_1768; // @[Fifo4.scala 163:30 164:25]
- wire [4:0] _GEN_1783 = iactive[2] ? io_in_bits_2_bits_index : _GEN_1769; // @[Fifo4.scala 163:30 164:25]
- wire [31:0] _GEN_1784 = iactive[2] ? io_in_bits_2_bits_data : _GEN_1770; // @[Fifo4.scala 163:30 164:25]
- wire [31:0] _GEN_1785 = iactive[2] ? io_in_bits_2_bits_adrx : _GEN_1771; // @[Fifo4.scala 163:30 164:25]
- wire [31:0] _GEN_1786 = iactive[2] ? io_in_bits_2_bits_addr : _GEN_1772; // @[Fifo4.scala 163:30 164:25]
- wire _GEN_1787 = iactive[1] ? io_in_bits_1_bits_suncd : _GEN_1773; // @[Fifo4.scala 161:30 162:25]
- wire _GEN_1788 = iactive[1] ? io_in_bits_1_bits_vldst : _GEN_1774; // @[Fifo4.scala 161:30 162:25]
- wire _GEN_1789 = iactive[1] ? io_in_bits_1_bits_sldst : _GEN_1775; // @[Fifo4.scala 161:30 162:25]
- wire _GEN_1790 = iactive[1] ? io_in_bits_1_bits_flushall : _GEN_1776; // @[Fifo4.scala 161:30 162:25]
- wire _GEN_1791 = iactive[1] ? io_in_bits_1_bits_flushat : _GEN_1777; // @[Fifo4.scala 161:30 162:25]
- wire _GEN_1792 = iactive[1] ? io_in_bits_1_bits_fencei : _GEN_1778; // @[Fifo4.scala 161:30 162:25]
- wire _GEN_1793 = iactive[1] ? io_in_bits_1_bits_iload : _GEN_1779; // @[Fifo4.scala 161:30 162:25]
- wire _GEN_1794 = iactive[1] ? io_in_bits_1_bits_sext : _GEN_1780; // @[Fifo4.scala 161:30 162:25]
- wire _GEN_1795 = iactive[1] ? io_in_bits_1_bits_write : _GEN_1781; // @[Fifo4.scala 161:30 162:25]
- wire [5:0] _GEN_1796 = iactive[1] ? io_in_bits_1_bits_size : _GEN_1782; // @[Fifo4.scala 161:30 162:25]
- wire [4:0] _GEN_1797 = iactive[1] ? io_in_bits_1_bits_index : _GEN_1783; // @[Fifo4.scala 161:30 162:25]
- wire [31:0] _GEN_1798 = iactive[1] ? io_in_bits_1_bits_data : _GEN_1784; // @[Fifo4.scala 161:30 162:25]
- wire [31:0] _GEN_1799 = iactive[1] ? io_in_bits_1_bits_adrx : _GEN_1785; // @[Fifo4.scala 161:30 162:25]
- wire [31:0] _GEN_1800 = iactive[1] ? io_in_bits_1_bits_addr : _GEN_1786; // @[Fifo4.scala 161:30 162:25]
- wire _GEN_1801 = iactive[0] ? io_in_bits_0_bits_suncd : _GEN_1787; // @[Fifo4.scala 159:23 160:25]
- wire _GEN_1802 = iactive[0] ? io_in_bits_0_bits_vldst : _GEN_1788; // @[Fifo4.scala 159:23 160:25]
- wire _GEN_1803 = iactive[0] ? io_in_bits_0_bits_sldst : _GEN_1789; // @[Fifo4.scala 159:23 160:25]
- wire _GEN_1804 = iactive[0] ? io_in_bits_0_bits_flushall : _GEN_1790; // @[Fifo4.scala 159:23 160:25]
- wire _GEN_1805 = iactive[0] ? io_in_bits_0_bits_flushat : _GEN_1791; // @[Fifo4.scala 159:23 160:25]
- wire _GEN_1806 = iactive[0] ? io_in_bits_0_bits_fencei : _GEN_1792; // @[Fifo4.scala 159:23 160:25]
- wire _GEN_1807 = iactive[0] ? io_in_bits_0_bits_iload : _GEN_1793; // @[Fifo4.scala 159:23 160:25]
- wire _GEN_1808 = iactive[0] ? io_in_bits_0_bits_sext : _GEN_1794; // @[Fifo4.scala 159:23 160:25]
- wire _GEN_1809 = iactive[0] ? io_in_bits_0_bits_write : _GEN_1795; // @[Fifo4.scala 159:23 160:25]
- wire [5:0] _GEN_1810 = iactive[0] ? io_in_bits_0_bits_size : _GEN_1796; // @[Fifo4.scala 159:23 160:25]
- wire [4:0] _GEN_1811 = iactive[0] ? io_in_bits_0_bits_index : _GEN_1797; // @[Fifo4.scala 159:23 160:25]
- wire [31:0] _GEN_1812 = iactive[0] ? io_in_bits_0_bits_data : _GEN_1798; // @[Fifo4.scala 159:23 160:25]
- wire [31:0] _GEN_1813 = iactive[0] ? io_in_bits_0_bits_adrx : _GEN_1799; // @[Fifo4.scala 159:23 160:25]
- wire [31:0] _GEN_1814 = iactive[0] ? io_in_bits_0_bits_addr : _GEN_1800; // @[Fifo4.scala 159:23 160:25]
- wire _GEN_1815 = ivalid ? _GEN_1801 : io_in_bits_0_bits_suncd; // @[Fifo4.scala 144:21 158:24]
- wire _GEN_1816 = ivalid ? _GEN_1802 : io_in_bits_0_bits_vldst; // @[Fifo4.scala 144:21 158:24]
- wire _GEN_1817 = ivalid ? _GEN_1803 : io_in_bits_0_bits_sldst; // @[Fifo4.scala 144:21 158:24]
- wire _GEN_1818 = ivalid ? _GEN_1804 : io_in_bits_0_bits_flushall; // @[Fifo4.scala 144:21 158:24]
- wire _GEN_1819 = ivalid ? _GEN_1805 : io_in_bits_0_bits_flushat; // @[Fifo4.scala 144:21 158:24]
- wire _GEN_1820 = ivalid ? _GEN_1806 : io_in_bits_0_bits_fencei; // @[Fifo4.scala 144:21 158:24]
- wire _GEN_1821 = ivalid ? _GEN_1807 : io_in_bits_0_bits_iload; // @[Fifo4.scala 144:21 158:24]
- wire _GEN_1822 = ivalid ? _GEN_1808 : io_in_bits_0_bits_sext; // @[Fifo4.scala 144:21 158:24]
- wire _GEN_1823 = ivalid ? _GEN_1809 : io_in_bits_0_bits_write; // @[Fifo4.scala 144:21 158:24]
- wire [5:0] _GEN_1824 = ivalid ? _GEN_1810 : io_in_bits_0_bits_size; // @[Fifo4.scala 144:21 158:24]
- wire [4:0] _GEN_1825 = ivalid ? _GEN_1811 : io_in_bits_0_bits_index; // @[Fifo4.scala 144:21 158:24]
- wire [31:0] _GEN_1826 = ivalid ? _GEN_1812 : io_in_bits_0_bits_data; // @[Fifo4.scala 144:21 158:24]
- wire [31:0] _GEN_1827 = ivalid ? _GEN_1813 : io_in_bits_0_bits_adrx; // @[Fifo4.scala 144:21 158:24]
- wire [31:0] _GEN_1828 = ivalid ? _GEN_1814 : io_in_bits_0_bits_addr; // @[Fifo4.scala 144:21 158:24]
- wire [2:0] _io_in_ready_T_1 = 3'h7 - icount; // @[Fifo4.scala 184:33]
- wire [3:0] _GEN_1853 = {{1'd0}, _io_in_ready_T_1}; // @[Fifo4.scala 184:25]
- Slice_1 mslice ( // @[Slice.scala 23:11]
- .clock(mslice_clock),
- .reset(mslice_reset),
- .io_in_ready(mslice_io_in_ready),
- .io_in_valid(mslice_io_in_valid),
- .io_in_bits_addr(mslice_io_in_bits_addr),
- .io_in_bits_adrx(mslice_io_in_bits_adrx),
- .io_in_bits_data(mslice_io_in_bits_data),
- .io_in_bits_index(mslice_io_in_bits_index),
- .io_in_bits_size(mslice_io_in_bits_size),
- .io_in_bits_write(mslice_io_in_bits_write),
- .io_in_bits_sext(mslice_io_in_bits_sext),
- .io_in_bits_iload(mslice_io_in_bits_iload),
- .io_in_bits_fencei(mslice_io_in_bits_fencei),
- .io_in_bits_flushat(mslice_io_in_bits_flushat),
- .io_in_bits_flushall(mslice_io_in_bits_flushall),
- .io_in_bits_sldst(mslice_io_in_bits_sldst),
- .io_in_bits_vldst(mslice_io_in_bits_vldst),
- .io_in_bits_suncd(mslice_io_in_bits_suncd),
- .io_out_ready(mslice_io_out_ready),
- .io_out_valid(mslice_io_out_valid),
- .io_out_bits_addr(mslice_io_out_bits_addr),
- .io_out_bits_adrx(mslice_io_out_bits_adrx),
- .io_out_bits_data(mslice_io_out_bits_data),
- .io_out_bits_index(mslice_io_out_bits_index),
- .io_out_bits_size(mslice_io_out_bits_size),
- .io_out_bits_write(mslice_io_out_bits_write),
- .io_out_bits_sext(mslice_io_out_bits_sext),
- .io_out_bits_iload(mslice_io_out_bits_iload),
- .io_out_bits_fencei(mslice_io_out_bits_fencei),
- .io_out_bits_flushat(mslice_io_out_bits_flushat),
- .io_out_bits_flushall(mslice_io_out_bits_flushall),
- .io_out_bits_sldst(mslice_io_out_bits_sldst),
- .io_out_bits_vldst(mslice_io_out_bits_vldst),
- .io_out_bits_suncd(mslice_io_out_bits_suncd)
- );
- assign mem_addr_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_addr_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_addr_mslice_io_in_bits_MPORT_data = mem_addr[mem_addr_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_addr_mslice_io_in_bits_MPORT_data = mem_addr_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_1[31:0] :
- mem_addr[mem_addr_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_addr_MPORT_data = io_in_bits_0_bits_addr;
- assign mem_addr_MPORT_addr = 3'h0;
- assign mem_addr_MPORT_mask = 1'h1;
- assign mem_addr_MPORT_en = ivalid & valid[0];
- assign mem_addr_MPORT_1_data = io_in_bits_1_bits_addr;
- assign mem_addr_MPORT_1_addr = 3'h0;
- assign mem_addr_MPORT_1_mask = 1'h1;
- assign mem_addr_MPORT_1_en = ivalid & _GEN_134;
- assign mem_addr_MPORT_2_data = io_in_bits_2_bits_addr;
- assign mem_addr_MPORT_2_addr = 3'h0;
- assign mem_addr_MPORT_2_mask = 1'h1;
- assign mem_addr_MPORT_2_en = ivalid & _GEN_152;
- assign mem_addr_MPORT_3_data = io_in_bits_3_bits_addr;
- assign mem_addr_MPORT_3_addr = 3'h0;
- assign mem_addr_MPORT_3_mask = 1'h1;
- assign mem_addr_MPORT_3_en = ivalid & _GEN_170;
- assign mem_addr_MPORT_4_data = io_in_bits_0_bits_addr;
- assign mem_addr_MPORT_4_addr = 3'h1;
- assign mem_addr_MPORT_4_mask = 1'h1;
- assign mem_addr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_addr_MPORT_5_data = io_in_bits_1_bits_addr;
- assign mem_addr_MPORT_5_addr = 3'h1;
- assign mem_addr_MPORT_5_mask = 1'h1;
- assign mem_addr_MPORT_5_en = ivalid & _GEN_379;
- assign mem_addr_MPORT_6_data = io_in_bits_2_bits_addr;
- assign mem_addr_MPORT_6_addr = 3'h1;
- assign mem_addr_MPORT_6_mask = 1'h1;
- assign mem_addr_MPORT_6_en = ivalid & _GEN_396;
- assign mem_addr_MPORT_7_data = io_in_bits_3_bits_addr;
- assign mem_addr_MPORT_7_addr = 3'h1;
- assign mem_addr_MPORT_7_mask = 1'h1;
- assign mem_addr_MPORT_7_en = ivalid & _GEN_413;
- assign mem_addr_MPORT_8_data = io_in_bits_0_bits_addr;
- assign mem_addr_MPORT_8_addr = 3'h2;
- assign mem_addr_MPORT_8_mask = 1'h1;
- assign mem_addr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_addr_MPORT_9_data = io_in_bits_1_bits_addr;
- assign mem_addr_MPORT_9_addr = 3'h2;
- assign mem_addr_MPORT_9_mask = 1'h1;
- assign mem_addr_MPORT_9_en = ivalid & _GEN_624;
- assign mem_addr_MPORT_10_data = io_in_bits_2_bits_addr;
- assign mem_addr_MPORT_10_addr = 3'h2;
- assign mem_addr_MPORT_10_mask = 1'h1;
- assign mem_addr_MPORT_10_en = ivalid & _GEN_642;
- assign mem_addr_MPORT_11_data = io_in_bits_3_bits_addr;
- assign mem_addr_MPORT_11_addr = 3'h2;
- assign mem_addr_MPORT_11_mask = 1'h1;
- assign mem_addr_MPORT_11_en = ivalid & _GEN_660;
- assign mem_addr_MPORT_12_data = io_in_bits_0_bits_addr;
- assign mem_addr_MPORT_12_addr = 3'h3;
- assign mem_addr_MPORT_12_mask = 1'h1;
- assign mem_addr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_addr_MPORT_13_data = io_in_bits_1_bits_addr;
- assign mem_addr_MPORT_13_addr = 3'h3;
- assign mem_addr_MPORT_13_mask = 1'h1;
- assign mem_addr_MPORT_13_en = ivalid & _GEN_876;
- assign mem_addr_MPORT_14_data = io_in_bits_2_bits_addr;
- assign mem_addr_MPORT_14_addr = 3'h3;
- assign mem_addr_MPORT_14_mask = 1'h1;
- assign mem_addr_MPORT_14_en = ivalid & _GEN_894;
- assign mem_addr_MPORT_15_data = io_in_bits_3_bits_addr;
- assign mem_addr_MPORT_15_addr = 3'h3;
- assign mem_addr_MPORT_15_mask = 1'h1;
- assign mem_addr_MPORT_15_en = ivalid & _GEN_912;
- assign mem_addr_MPORT_16_data = io_in_bits_0_bits_addr;
- assign mem_addr_MPORT_16_addr = 3'h4;
- assign mem_addr_MPORT_16_mask = 1'h1;
- assign mem_addr_MPORT_16_en = ivalid & valid_4[0];
- assign mem_addr_MPORT_17_data = io_in_bits_1_bits_addr;
- assign mem_addr_MPORT_17_addr = 3'h4;
- assign mem_addr_MPORT_17_mask = 1'h1;
- assign mem_addr_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_addr_MPORT_18_data = io_in_bits_2_bits_addr;
- assign mem_addr_MPORT_18_addr = 3'h4;
- assign mem_addr_MPORT_18_mask = 1'h1;
- assign mem_addr_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_addr_MPORT_19_data = io_in_bits_3_bits_addr;
- assign mem_addr_MPORT_19_addr = 3'h4;
- assign mem_addr_MPORT_19_mask = 1'h1;
- assign mem_addr_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_addr_MPORT_20_data = io_in_bits_0_bits_addr;
- assign mem_addr_MPORT_20_addr = 3'h5;
- assign mem_addr_MPORT_20_mask = 1'h1;
- assign mem_addr_MPORT_20_en = ivalid & valid_5[0];
- assign mem_addr_MPORT_21_data = io_in_bits_1_bits_addr;
- assign mem_addr_MPORT_21_addr = 3'h5;
- assign mem_addr_MPORT_21_mask = 1'h1;
- assign mem_addr_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_addr_MPORT_22_data = io_in_bits_2_bits_addr;
- assign mem_addr_MPORT_22_addr = 3'h5;
- assign mem_addr_MPORT_22_mask = 1'h1;
- assign mem_addr_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_addr_MPORT_23_data = io_in_bits_3_bits_addr;
- assign mem_addr_MPORT_23_addr = 3'h5;
- assign mem_addr_MPORT_23_mask = 1'h1;
- assign mem_addr_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_addr_MPORT_24_data = io_in_bits_0_bits_addr;
- assign mem_addr_MPORT_24_addr = 3'h6;
- assign mem_addr_MPORT_24_mask = 1'h1;
- assign mem_addr_MPORT_24_en = ivalid & valid_6[0];
- assign mem_addr_MPORT_25_data = io_in_bits_1_bits_addr;
- assign mem_addr_MPORT_25_addr = 3'h6;
- assign mem_addr_MPORT_25_mask = 1'h1;
- assign mem_addr_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_addr_MPORT_26_data = io_in_bits_2_bits_addr;
- assign mem_addr_MPORT_26_addr = 3'h6;
- assign mem_addr_MPORT_26_mask = 1'h1;
- assign mem_addr_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_addr_MPORT_27_data = io_in_bits_3_bits_addr;
- assign mem_addr_MPORT_27_addr = 3'h6;
- assign mem_addr_MPORT_27_mask = 1'h1;
- assign mem_addr_MPORT_27_en = ivalid & _GEN_1668;
- assign mem_adrx_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_adrx_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_adrx_mslice_io_in_bits_MPORT_data = mem_adrx[mem_adrx_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_adrx_mslice_io_in_bits_MPORT_data = mem_adrx_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_3[31:0] :
- mem_adrx[mem_adrx_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_adrx_MPORT_data = io_in_bits_0_bits_adrx;
- assign mem_adrx_MPORT_addr = 3'h0;
- assign mem_adrx_MPORT_mask = 1'h1;
- assign mem_adrx_MPORT_en = ivalid & valid[0];
- assign mem_adrx_MPORT_1_data = io_in_bits_1_bits_adrx;
- assign mem_adrx_MPORT_1_addr = 3'h0;
- assign mem_adrx_MPORT_1_mask = 1'h1;
- assign mem_adrx_MPORT_1_en = ivalid & _GEN_134;
- assign mem_adrx_MPORT_2_data = io_in_bits_2_bits_adrx;
- assign mem_adrx_MPORT_2_addr = 3'h0;
- assign mem_adrx_MPORT_2_mask = 1'h1;
- assign mem_adrx_MPORT_2_en = ivalid & _GEN_152;
- assign mem_adrx_MPORT_3_data = io_in_bits_3_bits_adrx;
- assign mem_adrx_MPORT_3_addr = 3'h0;
- assign mem_adrx_MPORT_3_mask = 1'h1;
- assign mem_adrx_MPORT_3_en = ivalid & _GEN_170;
- assign mem_adrx_MPORT_4_data = io_in_bits_0_bits_adrx;
- assign mem_adrx_MPORT_4_addr = 3'h1;
- assign mem_adrx_MPORT_4_mask = 1'h1;
- assign mem_adrx_MPORT_4_en = ivalid & valid_1[0];
- assign mem_adrx_MPORT_5_data = io_in_bits_1_bits_adrx;
- assign mem_adrx_MPORT_5_addr = 3'h1;
- assign mem_adrx_MPORT_5_mask = 1'h1;
- assign mem_adrx_MPORT_5_en = ivalid & _GEN_379;
- assign mem_adrx_MPORT_6_data = io_in_bits_2_bits_adrx;
- assign mem_adrx_MPORT_6_addr = 3'h1;
- assign mem_adrx_MPORT_6_mask = 1'h1;
- assign mem_adrx_MPORT_6_en = ivalid & _GEN_396;
- assign mem_adrx_MPORT_7_data = io_in_bits_3_bits_adrx;
- assign mem_adrx_MPORT_7_addr = 3'h1;
- assign mem_adrx_MPORT_7_mask = 1'h1;
- assign mem_adrx_MPORT_7_en = ivalid & _GEN_413;
- assign mem_adrx_MPORT_8_data = io_in_bits_0_bits_adrx;
- assign mem_adrx_MPORT_8_addr = 3'h2;
- assign mem_adrx_MPORT_8_mask = 1'h1;
- assign mem_adrx_MPORT_8_en = ivalid & valid_2[0];
- assign mem_adrx_MPORT_9_data = io_in_bits_1_bits_adrx;
- assign mem_adrx_MPORT_9_addr = 3'h2;
- assign mem_adrx_MPORT_9_mask = 1'h1;
- assign mem_adrx_MPORT_9_en = ivalid & _GEN_624;
- assign mem_adrx_MPORT_10_data = io_in_bits_2_bits_adrx;
- assign mem_adrx_MPORT_10_addr = 3'h2;
- assign mem_adrx_MPORT_10_mask = 1'h1;
- assign mem_adrx_MPORT_10_en = ivalid & _GEN_642;
- assign mem_adrx_MPORT_11_data = io_in_bits_3_bits_adrx;
- assign mem_adrx_MPORT_11_addr = 3'h2;
- assign mem_adrx_MPORT_11_mask = 1'h1;
- assign mem_adrx_MPORT_11_en = ivalid & _GEN_660;
- assign mem_adrx_MPORT_12_data = io_in_bits_0_bits_adrx;
- assign mem_adrx_MPORT_12_addr = 3'h3;
- assign mem_adrx_MPORT_12_mask = 1'h1;
- assign mem_adrx_MPORT_12_en = ivalid & valid_3[0];
- assign mem_adrx_MPORT_13_data = io_in_bits_1_bits_adrx;
- assign mem_adrx_MPORT_13_addr = 3'h3;
- assign mem_adrx_MPORT_13_mask = 1'h1;
- assign mem_adrx_MPORT_13_en = ivalid & _GEN_876;
- assign mem_adrx_MPORT_14_data = io_in_bits_2_bits_adrx;
- assign mem_adrx_MPORT_14_addr = 3'h3;
- assign mem_adrx_MPORT_14_mask = 1'h1;
- assign mem_adrx_MPORT_14_en = ivalid & _GEN_894;
- assign mem_adrx_MPORT_15_data = io_in_bits_3_bits_adrx;
- assign mem_adrx_MPORT_15_addr = 3'h3;
- assign mem_adrx_MPORT_15_mask = 1'h1;
- assign mem_adrx_MPORT_15_en = ivalid & _GEN_912;
- assign mem_adrx_MPORT_16_data = io_in_bits_0_bits_adrx;
- assign mem_adrx_MPORT_16_addr = 3'h4;
- assign mem_adrx_MPORT_16_mask = 1'h1;
- assign mem_adrx_MPORT_16_en = ivalid & valid_4[0];
- assign mem_adrx_MPORT_17_data = io_in_bits_1_bits_adrx;
- assign mem_adrx_MPORT_17_addr = 3'h4;
- assign mem_adrx_MPORT_17_mask = 1'h1;
- assign mem_adrx_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_adrx_MPORT_18_data = io_in_bits_2_bits_adrx;
- assign mem_adrx_MPORT_18_addr = 3'h4;
- assign mem_adrx_MPORT_18_mask = 1'h1;
- assign mem_adrx_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_adrx_MPORT_19_data = io_in_bits_3_bits_adrx;
- assign mem_adrx_MPORT_19_addr = 3'h4;
- assign mem_adrx_MPORT_19_mask = 1'h1;
- assign mem_adrx_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_adrx_MPORT_20_data = io_in_bits_0_bits_adrx;
- assign mem_adrx_MPORT_20_addr = 3'h5;
- assign mem_adrx_MPORT_20_mask = 1'h1;
- assign mem_adrx_MPORT_20_en = ivalid & valid_5[0];
- assign mem_adrx_MPORT_21_data = io_in_bits_1_bits_adrx;
- assign mem_adrx_MPORT_21_addr = 3'h5;
- assign mem_adrx_MPORT_21_mask = 1'h1;
- assign mem_adrx_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_adrx_MPORT_22_data = io_in_bits_2_bits_adrx;
- assign mem_adrx_MPORT_22_addr = 3'h5;
- assign mem_adrx_MPORT_22_mask = 1'h1;
- assign mem_adrx_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_adrx_MPORT_23_data = io_in_bits_3_bits_adrx;
- assign mem_adrx_MPORT_23_addr = 3'h5;
- assign mem_adrx_MPORT_23_mask = 1'h1;
- assign mem_adrx_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_adrx_MPORT_24_data = io_in_bits_0_bits_adrx;
- assign mem_adrx_MPORT_24_addr = 3'h6;
- assign mem_adrx_MPORT_24_mask = 1'h1;
- assign mem_adrx_MPORT_24_en = ivalid & valid_6[0];
- assign mem_adrx_MPORT_25_data = io_in_bits_1_bits_adrx;
- assign mem_adrx_MPORT_25_addr = 3'h6;
- assign mem_adrx_MPORT_25_mask = 1'h1;
- assign mem_adrx_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_adrx_MPORT_26_data = io_in_bits_2_bits_adrx;
- assign mem_adrx_MPORT_26_addr = 3'h6;
- assign mem_adrx_MPORT_26_mask = 1'h1;
- assign mem_adrx_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_adrx_MPORT_27_data = io_in_bits_3_bits_adrx;
- assign mem_adrx_MPORT_27_addr = 3'h6;
- assign mem_adrx_MPORT_27_mask = 1'h1;
- assign mem_adrx_MPORT_27_en = ivalid & _GEN_1668;
- assign mem_data_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_data_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_data_mslice_io_in_bits_MPORT_data = mem_data[mem_data_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_data_mslice_io_in_bits_MPORT_data = mem_data_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_5[31:0] :
- mem_data[mem_data_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_data_MPORT_data = io_in_bits_0_bits_data;
- assign mem_data_MPORT_addr = 3'h0;
- assign mem_data_MPORT_mask = 1'h1;
- assign mem_data_MPORT_en = ivalid & valid[0];
- assign mem_data_MPORT_1_data = io_in_bits_1_bits_data;
- assign mem_data_MPORT_1_addr = 3'h0;
- assign mem_data_MPORT_1_mask = 1'h1;
- assign mem_data_MPORT_1_en = ivalid & _GEN_134;
- assign mem_data_MPORT_2_data = io_in_bits_2_bits_data;
- assign mem_data_MPORT_2_addr = 3'h0;
- assign mem_data_MPORT_2_mask = 1'h1;
- assign mem_data_MPORT_2_en = ivalid & _GEN_152;
- assign mem_data_MPORT_3_data = io_in_bits_3_bits_data;
- assign mem_data_MPORT_3_addr = 3'h0;
- assign mem_data_MPORT_3_mask = 1'h1;
- assign mem_data_MPORT_3_en = ivalid & _GEN_170;
- assign mem_data_MPORT_4_data = io_in_bits_0_bits_data;
- assign mem_data_MPORT_4_addr = 3'h1;
- assign mem_data_MPORT_4_mask = 1'h1;
- assign mem_data_MPORT_4_en = ivalid & valid_1[0];
- assign mem_data_MPORT_5_data = io_in_bits_1_bits_data;
- assign mem_data_MPORT_5_addr = 3'h1;
- assign mem_data_MPORT_5_mask = 1'h1;
- assign mem_data_MPORT_5_en = ivalid & _GEN_379;
- assign mem_data_MPORT_6_data = io_in_bits_2_bits_data;
- assign mem_data_MPORT_6_addr = 3'h1;
- assign mem_data_MPORT_6_mask = 1'h1;
- assign mem_data_MPORT_6_en = ivalid & _GEN_396;
- assign mem_data_MPORT_7_data = io_in_bits_3_bits_data;
- assign mem_data_MPORT_7_addr = 3'h1;
- assign mem_data_MPORT_7_mask = 1'h1;
- assign mem_data_MPORT_7_en = ivalid & _GEN_413;
- assign mem_data_MPORT_8_data = io_in_bits_0_bits_data;
- assign mem_data_MPORT_8_addr = 3'h2;
- assign mem_data_MPORT_8_mask = 1'h1;
- assign mem_data_MPORT_8_en = ivalid & valid_2[0];
- assign mem_data_MPORT_9_data = io_in_bits_1_bits_data;
- assign mem_data_MPORT_9_addr = 3'h2;
- assign mem_data_MPORT_9_mask = 1'h1;
- assign mem_data_MPORT_9_en = ivalid & _GEN_624;
- assign mem_data_MPORT_10_data = io_in_bits_2_bits_data;
- assign mem_data_MPORT_10_addr = 3'h2;
- assign mem_data_MPORT_10_mask = 1'h1;
- assign mem_data_MPORT_10_en = ivalid & _GEN_642;
- assign mem_data_MPORT_11_data = io_in_bits_3_bits_data;
- assign mem_data_MPORT_11_addr = 3'h2;
- assign mem_data_MPORT_11_mask = 1'h1;
- assign mem_data_MPORT_11_en = ivalid & _GEN_660;
- assign mem_data_MPORT_12_data = io_in_bits_0_bits_data;
- assign mem_data_MPORT_12_addr = 3'h3;
- assign mem_data_MPORT_12_mask = 1'h1;
- assign mem_data_MPORT_12_en = ivalid & valid_3[0];
- assign mem_data_MPORT_13_data = io_in_bits_1_bits_data;
- assign mem_data_MPORT_13_addr = 3'h3;
- assign mem_data_MPORT_13_mask = 1'h1;
- assign mem_data_MPORT_13_en = ivalid & _GEN_876;
- assign mem_data_MPORT_14_data = io_in_bits_2_bits_data;
- assign mem_data_MPORT_14_addr = 3'h3;
- assign mem_data_MPORT_14_mask = 1'h1;
- assign mem_data_MPORT_14_en = ivalid & _GEN_894;
- assign mem_data_MPORT_15_data = io_in_bits_3_bits_data;
- assign mem_data_MPORT_15_addr = 3'h3;
- assign mem_data_MPORT_15_mask = 1'h1;
- assign mem_data_MPORT_15_en = ivalid & _GEN_912;
- assign mem_data_MPORT_16_data = io_in_bits_0_bits_data;
- assign mem_data_MPORT_16_addr = 3'h4;
- assign mem_data_MPORT_16_mask = 1'h1;
- assign mem_data_MPORT_16_en = ivalid & valid_4[0];
- assign mem_data_MPORT_17_data = io_in_bits_1_bits_data;
- assign mem_data_MPORT_17_addr = 3'h4;
- assign mem_data_MPORT_17_mask = 1'h1;
- assign mem_data_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_data_MPORT_18_data = io_in_bits_2_bits_data;
- assign mem_data_MPORT_18_addr = 3'h4;
- assign mem_data_MPORT_18_mask = 1'h1;
- assign mem_data_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_data_MPORT_19_data = io_in_bits_3_bits_data;
- assign mem_data_MPORT_19_addr = 3'h4;
- assign mem_data_MPORT_19_mask = 1'h1;
- assign mem_data_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_data_MPORT_20_data = io_in_bits_0_bits_data;
- assign mem_data_MPORT_20_addr = 3'h5;
- assign mem_data_MPORT_20_mask = 1'h1;
- assign mem_data_MPORT_20_en = ivalid & valid_5[0];
- assign mem_data_MPORT_21_data = io_in_bits_1_bits_data;
- assign mem_data_MPORT_21_addr = 3'h5;
- assign mem_data_MPORT_21_mask = 1'h1;
- assign mem_data_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_data_MPORT_22_data = io_in_bits_2_bits_data;
- assign mem_data_MPORT_22_addr = 3'h5;
- assign mem_data_MPORT_22_mask = 1'h1;
- assign mem_data_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_data_MPORT_23_data = io_in_bits_3_bits_data;
- assign mem_data_MPORT_23_addr = 3'h5;
- assign mem_data_MPORT_23_mask = 1'h1;
- assign mem_data_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_data_MPORT_24_data = io_in_bits_0_bits_data;
- assign mem_data_MPORT_24_addr = 3'h6;
- assign mem_data_MPORT_24_mask = 1'h1;
- assign mem_data_MPORT_24_en = ivalid & valid_6[0];
- assign mem_data_MPORT_25_data = io_in_bits_1_bits_data;
- assign mem_data_MPORT_25_addr = 3'h6;
- assign mem_data_MPORT_25_mask = 1'h1;
- assign mem_data_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_data_MPORT_26_data = io_in_bits_2_bits_data;
- assign mem_data_MPORT_26_addr = 3'h6;
- assign mem_data_MPORT_26_mask = 1'h1;
- assign mem_data_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_data_MPORT_27_data = io_in_bits_3_bits_data;
- assign mem_data_MPORT_27_addr = 3'h6;
- assign mem_data_MPORT_27_mask = 1'h1;
- assign mem_data_MPORT_27_en = ivalid & _GEN_1668;
- assign mem_index_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_index_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_index_mslice_io_in_bits_MPORT_data = mem_index[mem_index_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_index_mslice_io_in_bits_MPORT_data = mem_index_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_7[4:0] :
- mem_index[mem_index_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_index_MPORT_data = io_in_bits_0_bits_index;
- assign mem_index_MPORT_addr = 3'h0;
- assign mem_index_MPORT_mask = 1'h1;
- assign mem_index_MPORT_en = ivalid & valid[0];
- assign mem_index_MPORT_1_data = io_in_bits_1_bits_index;
- assign mem_index_MPORT_1_addr = 3'h0;
- assign mem_index_MPORT_1_mask = 1'h1;
- assign mem_index_MPORT_1_en = ivalid & _GEN_134;
- assign mem_index_MPORT_2_data = io_in_bits_2_bits_index;
- assign mem_index_MPORT_2_addr = 3'h0;
- assign mem_index_MPORT_2_mask = 1'h1;
- assign mem_index_MPORT_2_en = ivalid & _GEN_152;
- assign mem_index_MPORT_3_data = io_in_bits_3_bits_index;
- assign mem_index_MPORT_3_addr = 3'h0;
- assign mem_index_MPORT_3_mask = 1'h1;
- assign mem_index_MPORT_3_en = ivalid & _GEN_170;
- assign mem_index_MPORT_4_data = io_in_bits_0_bits_index;
- assign mem_index_MPORT_4_addr = 3'h1;
- assign mem_index_MPORT_4_mask = 1'h1;
- assign mem_index_MPORT_4_en = ivalid & valid_1[0];
- assign mem_index_MPORT_5_data = io_in_bits_1_bits_index;
- assign mem_index_MPORT_5_addr = 3'h1;
- assign mem_index_MPORT_5_mask = 1'h1;
- assign mem_index_MPORT_5_en = ivalid & _GEN_379;
- assign mem_index_MPORT_6_data = io_in_bits_2_bits_index;
- assign mem_index_MPORT_6_addr = 3'h1;
- assign mem_index_MPORT_6_mask = 1'h1;
- assign mem_index_MPORT_6_en = ivalid & _GEN_396;
- assign mem_index_MPORT_7_data = io_in_bits_3_bits_index;
- assign mem_index_MPORT_7_addr = 3'h1;
- assign mem_index_MPORT_7_mask = 1'h1;
- assign mem_index_MPORT_7_en = ivalid & _GEN_413;
- assign mem_index_MPORT_8_data = io_in_bits_0_bits_index;
- assign mem_index_MPORT_8_addr = 3'h2;
- assign mem_index_MPORT_8_mask = 1'h1;
- assign mem_index_MPORT_8_en = ivalid & valid_2[0];
- assign mem_index_MPORT_9_data = io_in_bits_1_bits_index;
- assign mem_index_MPORT_9_addr = 3'h2;
- assign mem_index_MPORT_9_mask = 1'h1;
- assign mem_index_MPORT_9_en = ivalid & _GEN_624;
- assign mem_index_MPORT_10_data = io_in_bits_2_bits_index;
- assign mem_index_MPORT_10_addr = 3'h2;
- assign mem_index_MPORT_10_mask = 1'h1;
- assign mem_index_MPORT_10_en = ivalid & _GEN_642;
- assign mem_index_MPORT_11_data = io_in_bits_3_bits_index;
- assign mem_index_MPORT_11_addr = 3'h2;
- assign mem_index_MPORT_11_mask = 1'h1;
- assign mem_index_MPORT_11_en = ivalid & _GEN_660;
- assign mem_index_MPORT_12_data = io_in_bits_0_bits_index;
- assign mem_index_MPORT_12_addr = 3'h3;
- assign mem_index_MPORT_12_mask = 1'h1;
- assign mem_index_MPORT_12_en = ivalid & valid_3[0];
- assign mem_index_MPORT_13_data = io_in_bits_1_bits_index;
- assign mem_index_MPORT_13_addr = 3'h3;
- assign mem_index_MPORT_13_mask = 1'h1;
- assign mem_index_MPORT_13_en = ivalid & _GEN_876;
- assign mem_index_MPORT_14_data = io_in_bits_2_bits_index;
- assign mem_index_MPORT_14_addr = 3'h3;
- assign mem_index_MPORT_14_mask = 1'h1;
- assign mem_index_MPORT_14_en = ivalid & _GEN_894;
- assign mem_index_MPORT_15_data = io_in_bits_3_bits_index;
- assign mem_index_MPORT_15_addr = 3'h3;
- assign mem_index_MPORT_15_mask = 1'h1;
- assign mem_index_MPORT_15_en = ivalid & _GEN_912;
- assign mem_index_MPORT_16_data = io_in_bits_0_bits_index;
- assign mem_index_MPORT_16_addr = 3'h4;
- assign mem_index_MPORT_16_mask = 1'h1;
- assign mem_index_MPORT_16_en = ivalid & valid_4[0];
- assign mem_index_MPORT_17_data = io_in_bits_1_bits_index;
- assign mem_index_MPORT_17_addr = 3'h4;
- assign mem_index_MPORT_17_mask = 1'h1;
- assign mem_index_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_index_MPORT_18_data = io_in_bits_2_bits_index;
- assign mem_index_MPORT_18_addr = 3'h4;
- assign mem_index_MPORT_18_mask = 1'h1;
- assign mem_index_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_index_MPORT_19_data = io_in_bits_3_bits_index;
- assign mem_index_MPORT_19_addr = 3'h4;
- assign mem_index_MPORT_19_mask = 1'h1;
- assign mem_index_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_index_MPORT_20_data = io_in_bits_0_bits_index;
- assign mem_index_MPORT_20_addr = 3'h5;
- assign mem_index_MPORT_20_mask = 1'h1;
- assign mem_index_MPORT_20_en = ivalid & valid_5[0];
- assign mem_index_MPORT_21_data = io_in_bits_1_bits_index;
- assign mem_index_MPORT_21_addr = 3'h5;
- assign mem_index_MPORT_21_mask = 1'h1;
- assign mem_index_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_index_MPORT_22_data = io_in_bits_2_bits_index;
- assign mem_index_MPORT_22_addr = 3'h5;
- assign mem_index_MPORT_22_mask = 1'h1;
- assign mem_index_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_index_MPORT_23_data = io_in_bits_3_bits_index;
- assign mem_index_MPORT_23_addr = 3'h5;
- assign mem_index_MPORT_23_mask = 1'h1;
- assign mem_index_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_index_MPORT_24_data = io_in_bits_0_bits_index;
- assign mem_index_MPORT_24_addr = 3'h6;
- assign mem_index_MPORT_24_mask = 1'h1;
- assign mem_index_MPORT_24_en = ivalid & valid_6[0];
- assign mem_index_MPORT_25_data = io_in_bits_1_bits_index;
- assign mem_index_MPORT_25_addr = 3'h6;
- assign mem_index_MPORT_25_mask = 1'h1;
- assign mem_index_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_index_MPORT_26_data = io_in_bits_2_bits_index;
- assign mem_index_MPORT_26_addr = 3'h6;
- assign mem_index_MPORT_26_mask = 1'h1;
- assign mem_index_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_index_MPORT_27_data = io_in_bits_3_bits_index;
- assign mem_index_MPORT_27_addr = 3'h6;
- assign mem_index_MPORT_27_mask = 1'h1;
- assign mem_index_MPORT_27_en = ivalid & _GEN_1668;
- assign mem_size_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_size_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_size_mslice_io_in_bits_MPORT_data = mem_size[mem_size_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_size_mslice_io_in_bits_MPORT_data = mem_size_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_9[5:0] :
- mem_size[mem_size_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_size_MPORT_data = io_in_bits_0_bits_size;
- assign mem_size_MPORT_addr = 3'h0;
- assign mem_size_MPORT_mask = 1'h1;
- assign mem_size_MPORT_en = ivalid & valid[0];
- assign mem_size_MPORT_1_data = io_in_bits_1_bits_size;
- assign mem_size_MPORT_1_addr = 3'h0;
- assign mem_size_MPORT_1_mask = 1'h1;
- assign mem_size_MPORT_1_en = ivalid & _GEN_134;
- assign mem_size_MPORT_2_data = io_in_bits_2_bits_size;
- assign mem_size_MPORT_2_addr = 3'h0;
- assign mem_size_MPORT_2_mask = 1'h1;
- assign mem_size_MPORT_2_en = ivalid & _GEN_152;
- assign mem_size_MPORT_3_data = io_in_bits_3_bits_size;
- assign mem_size_MPORT_3_addr = 3'h0;
- assign mem_size_MPORT_3_mask = 1'h1;
- assign mem_size_MPORT_3_en = ivalid & _GEN_170;
- assign mem_size_MPORT_4_data = io_in_bits_0_bits_size;
- assign mem_size_MPORT_4_addr = 3'h1;
- assign mem_size_MPORT_4_mask = 1'h1;
- assign mem_size_MPORT_4_en = ivalid & valid_1[0];
- assign mem_size_MPORT_5_data = io_in_bits_1_bits_size;
- assign mem_size_MPORT_5_addr = 3'h1;
- assign mem_size_MPORT_5_mask = 1'h1;
- assign mem_size_MPORT_5_en = ivalid & _GEN_379;
- assign mem_size_MPORT_6_data = io_in_bits_2_bits_size;
- assign mem_size_MPORT_6_addr = 3'h1;
- assign mem_size_MPORT_6_mask = 1'h1;
- assign mem_size_MPORT_6_en = ivalid & _GEN_396;
- assign mem_size_MPORT_7_data = io_in_bits_3_bits_size;
- assign mem_size_MPORT_7_addr = 3'h1;
- assign mem_size_MPORT_7_mask = 1'h1;
- assign mem_size_MPORT_7_en = ivalid & _GEN_413;
- assign mem_size_MPORT_8_data = io_in_bits_0_bits_size;
- assign mem_size_MPORT_8_addr = 3'h2;
- assign mem_size_MPORT_8_mask = 1'h1;
- assign mem_size_MPORT_8_en = ivalid & valid_2[0];
- assign mem_size_MPORT_9_data = io_in_bits_1_bits_size;
- assign mem_size_MPORT_9_addr = 3'h2;
- assign mem_size_MPORT_9_mask = 1'h1;
- assign mem_size_MPORT_9_en = ivalid & _GEN_624;
- assign mem_size_MPORT_10_data = io_in_bits_2_bits_size;
- assign mem_size_MPORT_10_addr = 3'h2;
- assign mem_size_MPORT_10_mask = 1'h1;
- assign mem_size_MPORT_10_en = ivalid & _GEN_642;
- assign mem_size_MPORT_11_data = io_in_bits_3_bits_size;
- assign mem_size_MPORT_11_addr = 3'h2;
- assign mem_size_MPORT_11_mask = 1'h1;
- assign mem_size_MPORT_11_en = ivalid & _GEN_660;
- assign mem_size_MPORT_12_data = io_in_bits_0_bits_size;
- assign mem_size_MPORT_12_addr = 3'h3;
- assign mem_size_MPORT_12_mask = 1'h1;
- assign mem_size_MPORT_12_en = ivalid & valid_3[0];
- assign mem_size_MPORT_13_data = io_in_bits_1_bits_size;
- assign mem_size_MPORT_13_addr = 3'h3;
- assign mem_size_MPORT_13_mask = 1'h1;
- assign mem_size_MPORT_13_en = ivalid & _GEN_876;
- assign mem_size_MPORT_14_data = io_in_bits_2_bits_size;
- assign mem_size_MPORT_14_addr = 3'h3;
- assign mem_size_MPORT_14_mask = 1'h1;
- assign mem_size_MPORT_14_en = ivalid & _GEN_894;
- assign mem_size_MPORT_15_data = io_in_bits_3_bits_size;
- assign mem_size_MPORT_15_addr = 3'h3;
- assign mem_size_MPORT_15_mask = 1'h1;
- assign mem_size_MPORT_15_en = ivalid & _GEN_912;
- assign mem_size_MPORT_16_data = io_in_bits_0_bits_size;
- assign mem_size_MPORT_16_addr = 3'h4;
- assign mem_size_MPORT_16_mask = 1'h1;
- assign mem_size_MPORT_16_en = ivalid & valid_4[0];
- assign mem_size_MPORT_17_data = io_in_bits_1_bits_size;
- assign mem_size_MPORT_17_addr = 3'h4;
- assign mem_size_MPORT_17_mask = 1'h1;
- assign mem_size_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_size_MPORT_18_data = io_in_bits_2_bits_size;
- assign mem_size_MPORT_18_addr = 3'h4;
- assign mem_size_MPORT_18_mask = 1'h1;
- assign mem_size_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_size_MPORT_19_data = io_in_bits_3_bits_size;
- assign mem_size_MPORT_19_addr = 3'h4;
- assign mem_size_MPORT_19_mask = 1'h1;
- assign mem_size_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_size_MPORT_20_data = io_in_bits_0_bits_size;
- assign mem_size_MPORT_20_addr = 3'h5;
- assign mem_size_MPORT_20_mask = 1'h1;
- assign mem_size_MPORT_20_en = ivalid & valid_5[0];
- assign mem_size_MPORT_21_data = io_in_bits_1_bits_size;
- assign mem_size_MPORT_21_addr = 3'h5;
- assign mem_size_MPORT_21_mask = 1'h1;
- assign mem_size_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_size_MPORT_22_data = io_in_bits_2_bits_size;
- assign mem_size_MPORT_22_addr = 3'h5;
- assign mem_size_MPORT_22_mask = 1'h1;
- assign mem_size_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_size_MPORT_23_data = io_in_bits_3_bits_size;
- assign mem_size_MPORT_23_addr = 3'h5;
- assign mem_size_MPORT_23_mask = 1'h1;
- assign mem_size_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_size_MPORT_24_data = io_in_bits_0_bits_size;
- assign mem_size_MPORT_24_addr = 3'h6;
- assign mem_size_MPORT_24_mask = 1'h1;
- assign mem_size_MPORT_24_en = ivalid & valid_6[0];
- assign mem_size_MPORT_25_data = io_in_bits_1_bits_size;
- assign mem_size_MPORT_25_addr = 3'h6;
- assign mem_size_MPORT_25_mask = 1'h1;
- assign mem_size_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_size_MPORT_26_data = io_in_bits_2_bits_size;
- assign mem_size_MPORT_26_addr = 3'h6;
- assign mem_size_MPORT_26_mask = 1'h1;
- assign mem_size_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_size_MPORT_27_data = io_in_bits_3_bits_size;
- assign mem_size_MPORT_27_addr = 3'h6;
- assign mem_size_MPORT_27_mask = 1'h1;
- assign mem_size_MPORT_27_en = ivalid & _GEN_1668;
- assign mem_write_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_write_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_write_mslice_io_in_bits_MPORT_data = mem_write[mem_write_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_write_mslice_io_in_bits_MPORT_data = mem_write_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_11[0:0] :
- mem_write[mem_write_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_write_MPORT_data = io_in_bits_0_bits_write;
- assign mem_write_MPORT_addr = 3'h0;
- assign mem_write_MPORT_mask = 1'h1;
- assign mem_write_MPORT_en = ivalid & valid[0];
- assign mem_write_MPORT_1_data = io_in_bits_1_bits_write;
- assign mem_write_MPORT_1_addr = 3'h0;
- assign mem_write_MPORT_1_mask = 1'h1;
- assign mem_write_MPORT_1_en = ivalid & _GEN_134;
- assign mem_write_MPORT_2_data = io_in_bits_2_bits_write;
- assign mem_write_MPORT_2_addr = 3'h0;
- assign mem_write_MPORT_2_mask = 1'h1;
- assign mem_write_MPORT_2_en = ivalid & _GEN_152;
- assign mem_write_MPORT_3_data = io_in_bits_3_bits_write;
- assign mem_write_MPORT_3_addr = 3'h0;
- assign mem_write_MPORT_3_mask = 1'h1;
- assign mem_write_MPORT_3_en = ivalid & _GEN_170;
- assign mem_write_MPORT_4_data = io_in_bits_0_bits_write;
- assign mem_write_MPORT_4_addr = 3'h1;
- assign mem_write_MPORT_4_mask = 1'h1;
- assign mem_write_MPORT_4_en = ivalid & valid_1[0];
- assign mem_write_MPORT_5_data = io_in_bits_1_bits_write;
- assign mem_write_MPORT_5_addr = 3'h1;
- assign mem_write_MPORT_5_mask = 1'h1;
- assign mem_write_MPORT_5_en = ivalid & _GEN_379;
- assign mem_write_MPORT_6_data = io_in_bits_2_bits_write;
- assign mem_write_MPORT_6_addr = 3'h1;
- assign mem_write_MPORT_6_mask = 1'h1;
- assign mem_write_MPORT_6_en = ivalid & _GEN_396;
- assign mem_write_MPORT_7_data = io_in_bits_3_bits_write;
- assign mem_write_MPORT_7_addr = 3'h1;
- assign mem_write_MPORT_7_mask = 1'h1;
- assign mem_write_MPORT_7_en = ivalid & _GEN_413;
- assign mem_write_MPORT_8_data = io_in_bits_0_bits_write;
- assign mem_write_MPORT_8_addr = 3'h2;
- assign mem_write_MPORT_8_mask = 1'h1;
- assign mem_write_MPORT_8_en = ivalid & valid_2[0];
- assign mem_write_MPORT_9_data = io_in_bits_1_bits_write;
- assign mem_write_MPORT_9_addr = 3'h2;
- assign mem_write_MPORT_9_mask = 1'h1;
- assign mem_write_MPORT_9_en = ivalid & _GEN_624;
- assign mem_write_MPORT_10_data = io_in_bits_2_bits_write;
- assign mem_write_MPORT_10_addr = 3'h2;
- assign mem_write_MPORT_10_mask = 1'h1;
- assign mem_write_MPORT_10_en = ivalid & _GEN_642;
- assign mem_write_MPORT_11_data = io_in_bits_3_bits_write;
- assign mem_write_MPORT_11_addr = 3'h2;
- assign mem_write_MPORT_11_mask = 1'h1;
- assign mem_write_MPORT_11_en = ivalid & _GEN_660;
- assign mem_write_MPORT_12_data = io_in_bits_0_bits_write;
- assign mem_write_MPORT_12_addr = 3'h3;
- assign mem_write_MPORT_12_mask = 1'h1;
- assign mem_write_MPORT_12_en = ivalid & valid_3[0];
- assign mem_write_MPORT_13_data = io_in_bits_1_bits_write;
- assign mem_write_MPORT_13_addr = 3'h3;
- assign mem_write_MPORT_13_mask = 1'h1;
- assign mem_write_MPORT_13_en = ivalid & _GEN_876;
- assign mem_write_MPORT_14_data = io_in_bits_2_bits_write;
- assign mem_write_MPORT_14_addr = 3'h3;
- assign mem_write_MPORT_14_mask = 1'h1;
- assign mem_write_MPORT_14_en = ivalid & _GEN_894;
- assign mem_write_MPORT_15_data = io_in_bits_3_bits_write;
- assign mem_write_MPORT_15_addr = 3'h3;
- assign mem_write_MPORT_15_mask = 1'h1;
- assign mem_write_MPORT_15_en = ivalid & _GEN_912;
- assign mem_write_MPORT_16_data = io_in_bits_0_bits_write;
- assign mem_write_MPORT_16_addr = 3'h4;
- assign mem_write_MPORT_16_mask = 1'h1;
- assign mem_write_MPORT_16_en = ivalid & valid_4[0];
- assign mem_write_MPORT_17_data = io_in_bits_1_bits_write;
- assign mem_write_MPORT_17_addr = 3'h4;
- assign mem_write_MPORT_17_mask = 1'h1;
- assign mem_write_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_write_MPORT_18_data = io_in_bits_2_bits_write;
- assign mem_write_MPORT_18_addr = 3'h4;
- assign mem_write_MPORT_18_mask = 1'h1;
- assign mem_write_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_write_MPORT_19_data = io_in_bits_3_bits_write;
- assign mem_write_MPORT_19_addr = 3'h4;
- assign mem_write_MPORT_19_mask = 1'h1;
- assign mem_write_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_write_MPORT_20_data = io_in_bits_0_bits_write;
- assign mem_write_MPORT_20_addr = 3'h5;
- assign mem_write_MPORT_20_mask = 1'h1;
- assign mem_write_MPORT_20_en = ivalid & valid_5[0];
- assign mem_write_MPORT_21_data = io_in_bits_1_bits_write;
- assign mem_write_MPORT_21_addr = 3'h5;
- assign mem_write_MPORT_21_mask = 1'h1;
- assign mem_write_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_write_MPORT_22_data = io_in_bits_2_bits_write;
- assign mem_write_MPORT_22_addr = 3'h5;
- assign mem_write_MPORT_22_mask = 1'h1;
- assign mem_write_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_write_MPORT_23_data = io_in_bits_3_bits_write;
- assign mem_write_MPORT_23_addr = 3'h5;
- assign mem_write_MPORT_23_mask = 1'h1;
- assign mem_write_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_write_MPORT_24_data = io_in_bits_0_bits_write;
- assign mem_write_MPORT_24_addr = 3'h6;
- assign mem_write_MPORT_24_mask = 1'h1;
- assign mem_write_MPORT_24_en = ivalid & valid_6[0];
- assign mem_write_MPORT_25_data = io_in_bits_1_bits_write;
- assign mem_write_MPORT_25_addr = 3'h6;
- assign mem_write_MPORT_25_mask = 1'h1;
- assign mem_write_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_write_MPORT_26_data = io_in_bits_2_bits_write;
- assign mem_write_MPORT_26_addr = 3'h6;
- assign mem_write_MPORT_26_mask = 1'h1;
- assign mem_write_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_write_MPORT_27_data = io_in_bits_3_bits_write;
- assign mem_write_MPORT_27_addr = 3'h6;
- assign mem_write_MPORT_27_mask = 1'h1;
- assign mem_write_MPORT_27_en = ivalid & _GEN_1668;
- assign mem_sext_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_sext_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_sext_mslice_io_in_bits_MPORT_data = mem_sext[mem_sext_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_sext_mslice_io_in_bits_MPORT_data = mem_sext_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_13[0:0] :
- mem_sext[mem_sext_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_sext_MPORT_data = io_in_bits_0_bits_sext;
- assign mem_sext_MPORT_addr = 3'h0;
- assign mem_sext_MPORT_mask = 1'h1;
- assign mem_sext_MPORT_en = ivalid & valid[0];
- assign mem_sext_MPORT_1_data = io_in_bits_1_bits_sext;
- assign mem_sext_MPORT_1_addr = 3'h0;
- assign mem_sext_MPORT_1_mask = 1'h1;
- assign mem_sext_MPORT_1_en = ivalid & _GEN_134;
- assign mem_sext_MPORT_2_data = io_in_bits_2_bits_sext;
- assign mem_sext_MPORT_2_addr = 3'h0;
- assign mem_sext_MPORT_2_mask = 1'h1;
- assign mem_sext_MPORT_2_en = ivalid & _GEN_152;
- assign mem_sext_MPORT_3_data = io_in_bits_3_bits_sext;
- assign mem_sext_MPORT_3_addr = 3'h0;
- assign mem_sext_MPORT_3_mask = 1'h1;
- assign mem_sext_MPORT_3_en = ivalid & _GEN_170;
- assign mem_sext_MPORT_4_data = io_in_bits_0_bits_sext;
- assign mem_sext_MPORT_4_addr = 3'h1;
- assign mem_sext_MPORT_4_mask = 1'h1;
- assign mem_sext_MPORT_4_en = ivalid & valid_1[0];
- assign mem_sext_MPORT_5_data = io_in_bits_1_bits_sext;
- assign mem_sext_MPORT_5_addr = 3'h1;
- assign mem_sext_MPORT_5_mask = 1'h1;
- assign mem_sext_MPORT_5_en = ivalid & _GEN_379;
- assign mem_sext_MPORT_6_data = io_in_bits_2_bits_sext;
- assign mem_sext_MPORT_6_addr = 3'h1;
- assign mem_sext_MPORT_6_mask = 1'h1;
- assign mem_sext_MPORT_6_en = ivalid & _GEN_396;
- assign mem_sext_MPORT_7_data = io_in_bits_3_bits_sext;
- assign mem_sext_MPORT_7_addr = 3'h1;
- assign mem_sext_MPORT_7_mask = 1'h1;
- assign mem_sext_MPORT_7_en = ivalid & _GEN_413;
- assign mem_sext_MPORT_8_data = io_in_bits_0_bits_sext;
- assign mem_sext_MPORT_8_addr = 3'h2;
- assign mem_sext_MPORT_8_mask = 1'h1;
- assign mem_sext_MPORT_8_en = ivalid & valid_2[0];
- assign mem_sext_MPORT_9_data = io_in_bits_1_bits_sext;
- assign mem_sext_MPORT_9_addr = 3'h2;
- assign mem_sext_MPORT_9_mask = 1'h1;
- assign mem_sext_MPORT_9_en = ivalid & _GEN_624;
- assign mem_sext_MPORT_10_data = io_in_bits_2_bits_sext;
- assign mem_sext_MPORT_10_addr = 3'h2;
- assign mem_sext_MPORT_10_mask = 1'h1;
- assign mem_sext_MPORT_10_en = ivalid & _GEN_642;
- assign mem_sext_MPORT_11_data = io_in_bits_3_bits_sext;
- assign mem_sext_MPORT_11_addr = 3'h2;
- assign mem_sext_MPORT_11_mask = 1'h1;
- assign mem_sext_MPORT_11_en = ivalid & _GEN_660;
- assign mem_sext_MPORT_12_data = io_in_bits_0_bits_sext;
- assign mem_sext_MPORT_12_addr = 3'h3;
- assign mem_sext_MPORT_12_mask = 1'h1;
- assign mem_sext_MPORT_12_en = ivalid & valid_3[0];
- assign mem_sext_MPORT_13_data = io_in_bits_1_bits_sext;
- assign mem_sext_MPORT_13_addr = 3'h3;
- assign mem_sext_MPORT_13_mask = 1'h1;
- assign mem_sext_MPORT_13_en = ivalid & _GEN_876;
- assign mem_sext_MPORT_14_data = io_in_bits_2_bits_sext;
- assign mem_sext_MPORT_14_addr = 3'h3;
- assign mem_sext_MPORT_14_mask = 1'h1;
- assign mem_sext_MPORT_14_en = ivalid & _GEN_894;
- assign mem_sext_MPORT_15_data = io_in_bits_3_bits_sext;
- assign mem_sext_MPORT_15_addr = 3'h3;
- assign mem_sext_MPORT_15_mask = 1'h1;
- assign mem_sext_MPORT_15_en = ivalid & _GEN_912;
- assign mem_sext_MPORT_16_data = io_in_bits_0_bits_sext;
- assign mem_sext_MPORT_16_addr = 3'h4;
- assign mem_sext_MPORT_16_mask = 1'h1;
- assign mem_sext_MPORT_16_en = ivalid & valid_4[0];
- assign mem_sext_MPORT_17_data = io_in_bits_1_bits_sext;
- assign mem_sext_MPORT_17_addr = 3'h4;
- assign mem_sext_MPORT_17_mask = 1'h1;
- assign mem_sext_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_sext_MPORT_18_data = io_in_bits_2_bits_sext;
- assign mem_sext_MPORT_18_addr = 3'h4;
- assign mem_sext_MPORT_18_mask = 1'h1;
- assign mem_sext_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_sext_MPORT_19_data = io_in_bits_3_bits_sext;
- assign mem_sext_MPORT_19_addr = 3'h4;
- assign mem_sext_MPORT_19_mask = 1'h1;
- assign mem_sext_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_sext_MPORT_20_data = io_in_bits_0_bits_sext;
- assign mem_sext_MPORT_20_addr = 3'h5;
- assign mem_sext_MPORT_20_mask = 1'h1;
- assign mem_sext_MPORT_20_en = ivalid & valid_5[0];
- assign mem_sext_MPORT_21_data = io_in_bits_1_bits_sext;
- assign mem_sext_MPORT_21_addr = 3'h5;
- assign mem_sext_MPORT_21_mask = 1'h1;
- assign mem_sext_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_sext_MPORT_22_data = io_in_bits_2_bits_sext;
- assign mem_sext_MPORT_22_addr = 3'h5;
- assign mem_sext_MPORT_22_mask = 1'h1;
- assign mem_sext_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_sext_MPORT_23_data = io_in_bits_3_bits_sext;
- assign mem_sext_MPORT_23_addr = 3'h5;
- assign mem_sext_MPORT_23_mask = 1'h1;
- assign mem_sext_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_sext_MPORT_24_data = io_in_bits_0_bits_sext;
- assign mem_sext_MPORT_24_addr = 3'h6;
- assign mem_sext_MPORT_24_mask = 1'h1;
- assign mem_sext_MPORT_24_en = ivalid & valid_6[0];
- assign mem_sext_MPORT_25_data = io_in_bits_1_bits_sext;
- assign mem_sext_MPORT_25_addr = 3'h6;
- assign mem_sext_MPORT_25_mask = 1'h1;
- assign mem_sext_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_sext_MPORT_26_data = io_in_bits_2_bits_sext;
- assign mem_sext_MPORT_26_addr = 3'h6;
- assign mem_sext_MPORT_26_mask = 1'h1;
- assign mem_sext_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_sext_MPORT_27_data = io_in_bits_3_bits_sext;
- assign mem_sext_MPORT_27_addr = 3'h6;
- assign mem_sext_MPORT_27_mask = 1'h1;
- assign mem_sext_MPORT_27_en = ivalid & _GEN_1668;
- assign mem_iload_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_iload_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_iload_mslice_io_in_bits_MPORT_data = mem_iload[mem_iload_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_iload_mslice_io_in_bits_MPORT_data = mem_iload_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_15[0:0] :
- mem_iload[mem_iload_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_iload_MPORT_data = io_in_bits_0_bits_iload;
- assign mem_iload_MPORT_addr = 3'h0;
- assign mem_iload_MPORT_mask = 1'h1;
- assign mem_iload_MPORT_en = ivalid & valid[0];
- assign mem_iload_MPORT_1_data = io_in_bits_1_bits_iload;
- assign mem_iload_MPORT_1_addr = 3'h0;
- assign mem_iload_MPORT_1_mask = 1'h1;
- assign mem_iload_MPORT_1_en = ivalid & _GEN_134;
- assign mem_iload_MPORT_2_data = io_in_bits_2_bits_iload;
- assign mem_iload_MPORT_2_addr = 3'h0;
- assign mem_iload_MPORT_2_mask = 1'h1;
- assign mem_iload_MPORT_2_en = ivalid & _GEN_152;
- assign mem_iload_MPORT_3_data = io_in_bits_3_bits_iload;
- assign mem_iload_MPORT_3_addr = 3'h0;
- assign mem_iload_MPORT_3_mask = 1'h1;
- assign mem_iload_MPORT_3_en = ivalid & _GEN_170;
- assign mem_iload_MPORT_4_data = io_in_bits_0_bits_iload;
- assign mem_iload_MPORT_4_addr = 3'h1;
- assign mem_iload_MPORT_4_mask = 1'h1;
- assign mem_iload_MPORT_4_en = ivalid & valid_1[0];
- assign mem_iload_MPORT_5_data = io_in_bits_1_bits_iload;
- assign mem_iload_MPORT_5_addr = 3'h1;
- assign mem_iload_MPORT_5_mask = 1'h1;
- assign mem_iload_MPORT_5_en = ivalid & _GEN_379;
- assign mem_iload_MPORT_6_data = io_in_bits_2_bits_iload;
- assign mem_iload_MPORT_6_addr = 3'h1;
- assign mem_iload_MPORT_6_mask = 1'h1;
- assign mem_iload_MPORT_6_en = ivalid & _GEN_396;
- assign mem_iload_MPORT_7_data = io_in_bits_3_bits_iload;
- assign mem_iload_MPORT_7_addr = 3'h1;
- assign mem_iload_MPORT_7_mask = 1'h1;
- assign mem_iload_MPORT_7_en = ivalid & _GEN_413;
- assign mem_iload_MPORT_8_data = io_in_bits_0_bits_iload;
- assign mem_iload_MPORT_8_addr = 3'h2;
- assign mem_iload_MPORT_8_mask = 1'h1;
- assign mem_iload_MPORT_8_en = ivalid & valid_2[0];
- assign mem_iload_MPORT_9_data = io_in_bits_1_bits_iload;
- assign mem_iload_MPORT_9_addr = 3'h2;
- assign mem_iload_MPORT_9_mask = 1'h1;
- assign mem_iload_MPORT_9_en = ivalid & _GEN_624;
- assign mem_iload_MPORT_10_data = io_in_bits_2_bits_iload;
- assign mem_iload_MPORT_10_addr = 3'h2;
- assign mem_iload_MPORT_10_mask = 1'h1;
- assign mem_iload_MPORT_10_en = ivalid & _GEN_642;
- assign mem_iload_MPORT_11_data = io_in_bits_3_bits_iload;
- assign mem_iload_MPORT_11_addr = 3'h2;
- assign mem_iload_MPORT_11_mask = 1'h1;
- assign mem_iload_MPORT_11_en = ivalid & _GEN_660;
- assign mem_iload_MPORT_12_data = io_in_bits_0_bits_iload;
- assign mem_iload_MPORT_12_addr = 3'h3;
- assign mem_iload_MPORT_12_mask = 1'h1;
- assign mem_iload_MPORT_12_en = ivalid & valid_3[0];
- assign mem_iload_MPORT_13_data = io_in_bits_1_bits_iload;
- assign mem_iload_MPORT_13_addr = 3'h3;
- assign mem_iload_MPORT_13_mask = 1'h1;
- assign mem_iload_MPORT_13_en = ivalid & _GEN_876;
- assign mem_iload_MPORT_14_data = io_in_bits_2_bits_iload;
- assign mem_iload_MPORT_14_addr = 3'h3;
- assign mem_iload_MPORT_14_mask = 1'h1;
- assign mem_iload_MPORT_14_en = ivalid & _GEN_894;
- assign mem_iload_MPORT_15_data = io_in_bits_3_bits_iload;
- assign mem_iload_MPORT_15_addr = 3'h3;
- assign mem_iload_MPORT_15_mask = 1'h1;
- assign mem_iload_MPORT_15_en = ivalid & _GEN_912;
- assign mem_iload_MPORT_16_data = io_in_bits_0_bits_iload;
- assign mem_iload_MPORT_16_addr = 3'h4;
- assign mem_iload_MPORT_16_mask = 1'h1;
- assign mem_iload_MPORT_16_en = ivalid & valid_4[0];
- assign mem_iload_MPORT_17_data = io_in_bits_1_bits_iload;
- assign mem_iload_MPORT_17_addr = 3'h4;
- assign mem_iload_MPORT_17_mask = 1'h1;
- assign mem_iload_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_iload_MPORT_18_data = io_in_bits_2_bits_iload;
- assign mem_iload_MPORT_18_addr = 3'h4;
- assign mem_iload_MPORT_18_mask = 1'h1;
- assign mem_iload_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_iload_MPORT_19_data = io_in_bits_3_bits_iload;
- assign mem_iload_MPORT_19_addr = 3'h4;
- assign mem_iload_MPORT_19_mask = 1'h1;
- assign mem_iload_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_iload_MPORT_20_data = io_in_bits_0_bits_iload;
- assign mem_iload_MPORT_20_addr = 3'h5;
- assign mem_iload_MPORT_20_mask = 1'h1;
- assign mem_iload_MPORT_20_en = ivalid & valid_5[0];
- assign mem_iload_MPORT_21_data = io_in_bits_1_bits_iload;
- assign mem_iload_MPORT_21_addr = 3'h5;
- assign mem_iload_MPORT_21_mask = 1'h1;
- assign mem_iload_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_iload_MPORT_22_data = io_in_bits_2_bits_iload;
- assign mem_iload_MPORT_22_addr = 3'h5;
- assign mem_iload_MPORT_22_mask = 1'h1;
- assign mem_iload_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_iload_MPORT_23_data = io_in_bits_3_bits_iload;
- assign mem_iload_MPORT_23_addr = 3'h5;
- assign mem_iload_MPORT_23_mask = 1'h1;
- assign mem_iload_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_iload_MPORT_24_data = io_in_bits_0_bits_iload;
- assign mem_iload_MPORT_24_addr = 3'h6;
- assign mem_iload_MPORT_24_mask = 1'h1;
- assign mem_iload_MPORT_24_en = ivalid & valid_6[0];
- assign mem_iload_MPORT_25_data = io_in_bits_1_bits_iload;
- assign mem_iload_MPORT_25_addr = 3'h6;
- assign mem_iload_MPORT_25_mask = 1'h1;
- assign mem_iload_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_iload_MPORT_26_data = io_in_bits_2_bits_iload;
- assign mem_iload_MPORT_26_addr = 3'h6;
- assign mem_iload_MPORT_26_mask = 1'h1;
- assign mem_iload_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_iload_MPORT_27_data = io_in_bits_3_bits_iload;
- assign mem_iload_MPORT_27_addr = 3'h6;
- assign mem_iload_MPORT_27_mask = 1'h1;
- assign mem_iload_MPORT_27_en = ivalid & _GEN_1668;
- assign mem_fencei_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_fencei_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_fencei_mslice_io_in_bits_MPORT_data = mem_fencei[mem_fencei_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_fencei_mslice_io_in_bits_MPORT_data = mem_fencei_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_17[0:0] :
- mem_fencei[mem_fencei_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_fencei_MPORT_data = io_in_bits_0_bits_fencei;
- assign mem_fencei_MPORT_addr = 3'h0;
- assign mem_fencei_MPORT_mask = 1'h1;
- assign mem_fencei_MPORT_en = ivalid & valid[0];
- assign mem_fencei_MPORT_1_data = io_in_bits_1_bits_fencei;
- assign mem_fencei_MPORT_1_addr = 3'h0;
- assign mem_fencei_MPORT_1_mask = 1'h1;
- assign mem_fencei_MPORT_1_en = ivalid & _GEN_134;
- assign mem_fencei_MPORT_2_data = io_in_bits_2_bits_fencei;
- assign mem_fencei_MPORT_2_addr = 3'h0;
- assign mem_fencei_MPORT_2_mask = 1'h1;
- assign mem_fencei_MPORT_2_en = ivalid & _GEN_152;
- assign mem_fencei_MPORT_3_data = io_in_bits_3_bits_fencei;
- assign mem_fencei_MPORT_3_addr = 3'h0;
- assign mem_fencei_MPORT_3_mask = 1'h1;
- assign mem_fencei_MPORT_3_en = ivalid & _GEN_170;
- assign mem_fencei_MPORT_4_data = io_in_bits_0_bits_fencei;
- assign mem_fencei_MPORT_4_addr = 3'h1;
- assign mem_fencei_MPORT_4_mask = 1'h1;
- assign mem_fencei_MPORT_4_en = ivalid & valid_1[0];
- assign mem_fencei_MPORT_5_data = io_in_bits_1_bits_fencei;
- assign mem_fencei_MPORT_5_addr = 3'h1;
- assign mem_fencei_MPORT_5_mask = 1'h1;
- assign mem_fencei_MPORT_5_en = ivalid & _GEN_379;
- assign mem_fencei_MPORT_6_data = io_in_bits_2_bits_fencei;
- assign mem_fencei_MPORT_6_addr = 3'h1;
- assign mem_fencei_MPORT_6_mask = 1'h1;
- assign mem_fencei_MPORT_6_en = ivalid & _GEN_396;
- assign mem_fencei_MPORT_7_data = io_in_bits_3_bits_fencei;
- assign mem_fencei_MPORT_7_addr = 3'h1;
- assign mem_fencei_MPORT_7_mask = 1'h1;
- assign mem_fencei_MPORT_7_en = ivalid & _GEN_413;
- assign mem_fencei_MPORT_8_data = io_in_bits_0_bits_fencei;
- assign mem_fencei_MPORT_8_addr = 3'h2;
- assign mem_fencei_MPORT_8_mask = 1'h1;
- assign mem_fencei_MPORT_8_en = ivalid & valid_2[0];
- assign mem_fencei_MPORT_9_data = io_in_bits_1_bits_fencei;
- assign mem_fencei_MPORT_9_addr = 3'h2;
- assign mem_fencei_MPORT_9_mask = 1'h1;
- assign mem_fencei_MPORT_9_en = ivalid & _GEN_624;
- assign mem_fencei_MPORT_10_data = io_in_bits_2_bits_fencei;
- assign mem_fencei_MPORT_10_addr = 3'h2;
- assign mem_fencei_MPORT_10_mask = 1'h1;
- assign mem_fencei_MPORT_10_en = ivalid & _GEN_642;
- assign mem_fencei_MPORT_11_data = io_in_bits_3_bits_fencei;
- assign mem_fencei_MPORT_11_addr = 3'h2;
- assign mem_fencei_MPORT_11_mask = 1'h1;
- assign mem_fencei_MPORT_11_en = ivalid & _GEN_660;
- assign mem_fencei_MPORT_12_data = io_in_bits_0_bits_fencei;
- assign mem_fencei_MPORT_12_addr = 3'h3;
- assign mem_fencei_MPORT_12_mask = 1'h1;
- assign mem_fencei_MPORT_12_en = ivalid & valid_3[0];
- assign mem_fencei_MPORT_13_data = io_in_bits_1_bits_fencei;
- assign mem_fencei_MPORT_13_addr = 3'h3;
- assign mem_fencei_MPORT_13_mask = 1'h1;
- assign mem_fencei_MPORT_13_en = ivalid & _GEN_876;
- assign mem_fencei_MPORT_14_data = io_in_bits_2_bits_fencei;
- assign mem_fencei_MPORT_14_addr = 3'h3;
- assign mem_fencei_MPORT_14_mask = 1'h1;
- assign mem_fencei_MPORT_14_en = ivalid & _GEN_894;
- assign mem_fencei_MPORT_15_data = io_in_bits_3_bits_fencei;
- assign mem_fencei_MPORT_15_addr = 3'h3;
- assign mem_fencei_MPORT_15_mask = 1'h1;
- assign mem_fencei_MPORT_15_en = ivalid & _GEN_912;
- assign mem_fencei_MPORT_16_data = io_in_bits_0_bits_fencei;
- assign mem_fencei_MPORT_16_addr = 3'h4;
- assign mem_fencei_MPORT_16_mask = 1'h1;
- assign mem_fencei_MPORT_16_en = ivalid & valid_4[0];
- assign mem_fencei_MPORT_17_data = io_in_bits_1_bits_fencei;
- assign mem_fencei_MPORT_17_addr = 3'h4;
- assign mem_fencei_MPORT_17_mask = 1'h1;
- assign mem_fencei_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_fencei_MPORT_18_data = io_in_bits_2_bits_fencei;
- assign mem_fencei_MPORT_18_addr = 3'h4;
- assign mem_fencei_MPORT_18_mask = 1'h1;
- assign mem_fencei_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_fencei_MPORT_19_data = io_in_bits_3_bits_fencei;
- assign mem_fencei_MPORT_19_addr = 3'h4;
- assign mem_fencei_MPORT_19_mask = 1'h1;
- assign mem_fencei_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_fencei_MPORT_20_data = io_in_bits_0_bits_fencei;
- assign mem_fencei_MPORT_20_addr = 3'h5;
- assign mem_fencei_MPORT_20_mask = 1'h1;
- assign mem_fencei_MPORT_20_en = ivalid & valid_5[0];
- assign mem_fencei_MPORT_21_data = io_in_bits_1_bits_fencei;
- assign mem_fencei_MPORT_21_addr = 3'h5;
- assign mem_fencei_MPORT_21_mask = 1'h1;
- assign mem_fencei_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_fencei_MPORT_22_data = io_in_bits_2_bits_fencei;
- assign mem_fencei_MPORT_22_addr = 3'h5;
- assign mem_fencei_MPORT_22_mask = 1'h1;
- assign mem_fencei_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_fencei_MPORT_23_data = io_in_bits_3_bits_fencei;
- assign mem_fencei_MPORT_23_addr = 3'h5;
- assign mem_fencei_MPORT_23_mask = 1'h1;
- assign mem_fencei_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_fencei_MPORT_24_data = io_in_bits_0_bits_fencei;
- assign mem_fencei_MPORT_24_addr = 3'h6;
- assign mem_fencei_MPORT_24_mask = 1'h1;
- assign mem_fencei_MPORT_24_en = ivalid & valid_6[0];
- assign mem_fencei_MPORT_25_data = io_in_bits_1_bits_fencei;
- assign mem_fencei_MPORT_25_addr = 3'h6;
- assign mem_fencei_MPORT_25_mask = 1'h1;
- assign mem_fencei_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_fencei_MPORT_26_data = io_in_bits_2_bits_fencei;
- assign mem_fencei_MPORT_26_addr = 3'h6;
- assign mem_fencei_MPORT_26_mask = 1'h1;
- assign mem_fencei_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_fencei_MPORT_27_data = io_in_bits_3_bits_fencei;
- assign mem_fencei_MPORT_27_addr = 3'h6;
- assign mem_fencei_MPORT_27_mask = 1'h1;
- assign mem_fencei_MPORT_27_en = ivalid & _GEN_1668;
- assign mem_flushat_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_flushat_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_flushat_mslice_io_in_bits_MPORT_data = mem_flushat[mem_flushat_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_flushat_mslice_io_in_bits_MPORT_data = mem_flushat_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_19[0:0] :
- mem_flushat[mem_flushat_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_flushat_MPORT_data = io_in_bits_0_bits_flushat;
- assign mem_flushat_MPORT_addr = 3'h0;
- assign mem_flushat_MPORT_mask = 1'h1;
- assign mem_flushat_MPORT_en = ivalid & valid[0];
- assign mem_flushat_MPORT_1_data = io_in_bits_1_bits_flushat;
- assign mem_flushat_MPORT_1_addr = 3'h0;
- assign mem_flushat_MPORT_1_mask = 1'h1;
- assign mem_flushat_MPORT_1_en = ivalid & _GEN_134;
- assign mem_flushat_MPORT_2_data = io_in_bits_2_bits_flushat;
- assign mem_flushat_MPORT_2_addr = 3'h0;
- assign mem_flushat_MPORT_2_mask = 1'h1;
- assign mem_flushat_MPORT_2_en = ivalid & _GEN_152;
- assign mem_flushat_MPORT_3_data = io_in_bits_3_bits_flushat;
- assign mem_flushat_MPORT_3_addr = 3'h0;
- assign mem_flushat_MPORT_3_mask = 1'h1;
- assign mem_flushat_MPORT_3_en = ivalid & _GEN_170;
- assign mem_flushat_MPORT_4_data = io_in_bits_0_bits_flushat;
- assign mem_flushat_MPORT_4_addr = 3'h1;
- assign mem_flushat_MPORT_4_mask = 1'h1;
- assign mem_flushat_MPORT_4_en = ivalid & valid_1[0];
- assign mem_flushat_MPORT_5_data = io_in_bits_1_bits_flushat;
- assign mem_flushat_MPORT_5_addr = 3'h1;
- assign mem_flushat_MPORT_5_mask = 1'h1;
- assign mem_flushat_MPORT_5_en = ivalid & _GEN_379;
- assign mem_flushat_MPORT_6_data = io_in_bits_2_bits_flushat;
- assign mem_flushat_MPORT_6_addr = 3'h1;
- assign mem_flushat_MPORT_6_mask = 1'h1;
- assign mem_flushat_MPORT_6_en = ivalid & _GEN_396;
- assign mem_flushat_MPORT_7_data = io_in_bits_3_bits_flushat;
- assign mem_flushat_MPORT_7_addr = 3'h1;
- assign mem_flushat_MPORT_7_mask = 1'h1;
- assign mem_flushat_MPORT_7_en = ivalid & _GEN_413;
- assign mem_flushat_MPORT_8_data = io_in_bits_0_bits_flushat;
- assign mem_flushat_MPORT_8_addr = 3'h2;
- assign mem_flushat_MPORT_8_mask = 1'h1;
- assign mem_flushat_MPORT_8_en = ivalid & valid_2[0];
- assign mem_flushat_MPORT_9_data = io_in_bits_1_bits_flushat;
- assign mem_flushat_MPORT_9_addr = 3'h2;
- assign mem_flushat_MPORT_9_mask = 1'h1;
- assign mem_flushat_MPORT_9_en = ivalid & _GEN_624;
- assign mem_flushat_MPORT_10_data = io_in_bits_2_bits_flushat;
- assign mem_flushat_MPORT_10_addr = 3'h2;
- assign mem_flushat_MPORT_10_mask = 1'h1;
- assign mem_flushat_MPORT_10_en = ivalid & _GEN_642;
- assign mem_flushat_MPORT_11_data = io_in_bits_3_bits_flushat;
- assign mem_flushat_MPORT_11_addr = 3'h2;
- assign mem_flushat_MPORT_11_mask = 1'h1;
- assign mem_flushat_MPORT_11_en = ivalid & _GEN_660;
- assign mem_flushat_MPORT_12_data = io_in_bits_0_bits_flushat;
- assign mem_flushat_MPORT_12_addr = 3'h3;
- assign mem_flushat_MPORT_12_mask = 1'h1;
- assign mem_flushat_MPORT_12_en = ivalid & valid_3[0];
- assign mem_flushat_MPORT_13_data = io_in_bits_1_bits_flushat;
- assign mem_flushat_MPORT_13_addr = 3'h3;
- assign mem_flushat_MPORT_13_mask = 1'h1;
- assign mem_flushat_MPORT_13_en = ivalid & _GEN_876;
- assign mem_flushat_MPORT_14_data = io_in_bits_2_bits_flushat;
- assign mem_flushat_MPORT_14_addr = 3'h3;
- assign mem_flushat_MPORT_14_mask = 1'h1;
- assign mem_flushat_MPORT_14_en = ivalid & _GEN_894;
- assign mem_flushat_MPORT_15_data = io_in_bits_3_bits_flushat;
- assign mem_flushat_MPORT_15_addr = 3'h3;
- assign mem_flushat_MPORT_15_mask = 1'h1;
- assign mem_flushat_MPORT_15_en = ivalid & _GEN_912;
- assign mem_flushat_MPORT_16_data = io_in_bits_0_bits_flushat;
- assign mem_flushat_MPORT_16_addr = 3'h4;
- assign mem_flushat_MPORT_16_mask = 1'h1;
- assign mem_flushat_MPORT_16_en = ivalid & valid_4[0];
- assign mem_flushat_MPORT_17_data = io_in_bits_1_bits_flushat;
- assign mem_flushat_MPORT_17_addr = 3'h4;
- assign mem_flushat_MPORT_17_mask = 1'h1;
- assign mem_flushat_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_flushat_MPORT_18_data = io_in_bits_2_bits_flushat;
- assign mem_flushat_MPORT_18_addr = 3'h4;
- assign mem_flushat_MPORT_18_mask = 1'h1;
- assign mem_flushat_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_flushat_MPORT_19_data = io_in_bits_3_bits_flushat;
- assign mem_flushat_MPORT_19_addr = 3'h4;
- assign mem_flushat_MPORT_19_mask = 1'h1;
- assign mem_flushat_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_flushat_MPORT_20_data = io_in_bits_0_bits_flushat;
- assign mem_flushat_MPORT_20_addr = 3'h5;
- assign mem_flushat_MPORT_20_mask = 1'h1;
- assign mem_flushat_MPORT_20_en = ivalid & valid_5[0];
- assign mem_flushat_MPORT_21_data = io_in_bits_1_bits_flushat;
- assign mem_flushat_MPORT_21_addr = 3'h5;
- assign mem_flushat_MPORT_21_mask = 1'h1;
- assign mem_flushat_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_flushat_MPORT_22_data = io_in_bits_2_bits_flushat;
- assign mem_flushat_MPORT_22_addr = 3'h5;
- assign mem_flushat_MPORT_22_mask = 1'h1;
- assign mem_flushat_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_flushat_MPORT_23_data = io_in_bits_3_bits_flushat;
- assign mem_flushat_MPORT_23_addr = 3'h5;
- assign mem_flushat_MPORT_23_mask = 1'h1;
- assign mem_flushat_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_flushat_MPORT_24_data = io_in_bits_0_bits_flushat;
- assign mem_flushat_MPORT_24_addr = 3'h6;
- assign mem_flushat_MPORT_24_mask = 1'h1;
- assign mem_flushat_MPORT_24_en = ivalid & valid_6[0];
- assign mem_flushat_MPORT_25_data = io_in_bits_1_bits_flushat;
- assign mem_flushat_MPORT_25_addr = 3'h6;
- assign mem_flushat_MPORT_25_mask = 1'h1;
- assign mem_flushat_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_flushat_MPORT_26_data = io_in_bits_2_bits_flushat;
- assign mem_flushat_MPORT_26_addr = 3'h6;
- assign mem_flushat_MPORT_26_mask = 1'h1;
- assign mem_flushat_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_flushat_MPORT_27_data = io_in_bits_3_bits_flushat;
- assign mem_flushat_MPORT_27_addr = 3'h6;
- assign mem_flushat_MPORT_27_mask = 1'h1;
- assign mem_flushat_MPORT_27_en = ivalid & _GEN_1668;
- assign mem_flushall_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_flushall_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_flushall_mslice_io_in_bits_MPORT_data = mem_flushall[mem_flushall_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_flushall_mslice_io_in_bits_MPORT_data = mem_flushall_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_21[0:0]
- : mem_flushall[mem_flushall_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_flushall_MPORT_data = io_in_bits_0_bits_flushall;
- assign mem_flushall_MPORT_addr = 3'h0;
- assign mem_flushall_MPORT_mask = 1'h1;
- assign mem_flushall_MPORT_en = ivalid & valid[0];
- assign mem_flushall_MPORT_1_data = io_in_bits_1_bits_flushall;
- assign mem_flushall_MPORT_1_addr = 3'h0;
- assign mem_flushall_MPORT_1_mask = 1'h1;
- assign mem_flushall_MPORT_1_en = ivalid & _GEN_134;
- assign mem_flushall_MPORT_2_data = io_in_bits_2_bits_flushall;
- assign mem_flushall_MPORT_2_addr = 3'h0;
- assign mem_flushall_MPORT_2_mask = 1'h1;
- assign mem_flushall_MPORT_2_en = ivalid & _GEN_152;
- assign mem_flushall_MPORT_3_data = io_in_bits_3_bits_flushall;
- assign mem_flushall_MPORT_3_addr = 3'h0;
- assign mem_flushall_MPORT_3_mask = 1'h1;
- assign mem_flushall_MPORT_3_en = ivalid & _GEN_170;
- assign mem_flushall_MPORT_4_data = io_in_bits_0_bits_flushall;
- assign mem_flushall_MPORT_4_addr = 3'h1;
- assign mem_flushall_MPORT_4_mask = 1'h1;
- assign mem_flushall_MPORT_4_en = ivalid & valid_1[0];
- assign mem_flushall_MPORT_5_data = io_in_bits_1_bits_flushall;
- assign mem_flushall_MPORT_5_addr = 3'h1;
- assign mem_flushall_MPORT_5_mask = 1'h1;
- assign mem_flushall_MPORT_5_en = ivalid & _GEN_379;
- assign mem_flushall_MPORT_6_data = io_in_bits_2_bits_flushall;
- assign mem_flushall_MPORT_6_addr = 3'h1;
- assign mem_flushall_MPORT_6_mask = 1'h1;
- assign mem_flushall_MPORT_6_en = ivalid & _GEN_396;
- assign mem_flushall_MPORT_7_data = io_in_bits_3_bits_flushall;
- assign mem_flushall_MPORT_7_addr = 3'h1;
- assign mem_flushall_MPORT_7_mask = 1'h1;
- assign mem_flushall_MPORT_7_en = ivalid & _GEN_413;
- assign mem_flushall_MPORT_8_data = io_in_bits_0_bits_flushall;
- assign mem_flushall_MPORT_8_addr = 3'h2;
- assign mem_flushall_MPORT_8_mask = 1'h1;
- assign mem_flushall_MPORT_8_en = ivalid & valid_2[0];
- assign mem_flushall_MPORT_9_data = io_in_bits_1_bits_flushall;
- assign mem_flushall_MPORT_9_addr = 3'h2;
- assign mem_flushall_MPORT_9_mask = 1'h1;
- assign mem_flushall_MPORT_9_en = ivalid & _GEN_624;
- assign mem_flushall_MPORT_10_data = io_in_bits_2_bits_flushall;
- assign mem_flushall_MPORT_10_addr = 3'h2;
- assign mem_flushall_MPORT_10_mask = 1'h1;
- assign mem_flushall_MPORT_10_en = ivalid & _GEN_642;
- assign mem_flushall_MPORT_11_data = io_in_bits_3_bits_flushall;
- assign mem_flushall_MPORT_11_addr = 3'h2;
- assign mem_flushall_MPORT_11_mask = 1'h1;
- assign mem_flushall_MPORT_11_en = ivalid & _GEN_660;
- assign mem_flushall_MPORT_12_data = io_in_bits_0_bits_flushall;
- assign mem_flushall_MPORT_12_addr = 3'h3;
- assign mem_flushall_MPORT_12_mask = 1'h1;
- assign mem_flushall_MPORT_12_en = ivalid & valid_3[0];
- assign mem_flushall_MPORT_13_data = io_in_bits_1_bits_flushall;
- assign mem_flushall_MPORT_13_addr = 3'h3;
- assign mem_flushall_MPORT_13_mask = 1'h1;
- assign mem_flushall_MPORT_13_en = ivalid & _GEN_876;
- assign mem_flushall_MPORT_14_data = io_in_bits_2_bits_flushall;
- assign mem_flushall_MPORT_14_addr = 3'h3;
- assign mem_flushall_MPORT_14_mask = 1'h1;
- assign mem_flushall_MPORT_14_en = ivalid & _GEN_894;
- assign mem_flushall_MPORT_15_data = io_in_bits_3_bits_flushall;
- assign mem_flushall_MPORT_15_addr = 3'h3;
- assign mem_flushall_MPORT_15_mask = 1'h1;
- assign mem_flushall_MPORT_15_en = ivalid & _GEN_912;
- assign mem_flushall_MPORT_16_data = io_in_bits_0_bits_flushall;
- assign mem_flushall_MPORT_16_addr = 3'h4;
- assign mem_flushall_MPORT_16_mask = 1'h1;
- assign mem_flushall_MPORT_16_en = ivalid & valid_4[0];
- assign mem_flushall_MPORT_17_data = io_in_bits_1_bits_flushall;
- assign mem_flushall_MPORT_17_addr = 3'h4;
- assign mem_flushall_MPORT_17_mask = 1'h1;
- assign mem_flushall_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_flushall_MPORT_18_data = io_in_bits_2_bits_flushall;
- assign mem_flushall_MPORT_18_addr = 3'h4;
- assign mem_flushall_MPORT_18_mask = 1'h1;
- assign mem_flushall_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_flushall_MPORT_19_data = io_in_bits_3_bits_flushall;
- assign mem_flushall_MPORT_19_addr = 3'h4;
- assign mem_flushall_MPORT_19_mask = 1'h1;
- assign mem_flushall_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_flushall_MPORT_20_data = io_in_bits_0_bits_flushall;
- assign mem_flushall_MPORT_20_addr = 3'h5;
- assign mem_flushall_MPORT_20_mask = 1'h1;
- assign mem_flushall_MPORT_20_en = ivalid & valid_5[0];
- assign mem_flushall_MPORT_21_data = io_in_bits_1_bits_flushall;
- assign mem_flushall_MPORT_21_addr = 3'h5;
- assign mem_flushall_MPORT_21_mask = 1'h1;
- assign mem_flushall_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_flushall_MPORT_22_data = io_in_bits_2_bits_flushall;
- assign mem_flushall_MPORT_22_addr = 3'h5;
- assign mem_flushall_MPORT_22_mask = 1'h1;
- assign mem_flushall_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_flushall_MPORT_23_data = io_in_bits_3_bits_flushall;
- assign mem_flushall_MPORT_23_addr = 3'h5;
- assign mem_flushall_MPORT_23_mask = 1'h1;
- assign mem_flushall_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_flushall_MPORT_24_data = io_in_bits_0_bits_flushall;
- assign mem_flushall_MPORT_24_addr = 3'h6;
- assign mem_flushall_MPORT_24_mask = 1'h1;
- assign mem_flushall_MPORT_24_en = ivalid & valid_6[0];
- assign mem_flushall_MPORT_25_data = io_in_bits_1_bits_flushall;
- assign mem_flushall_MPORT_25_addr = 3'h6;
- assign mem_flushall_MPORT_25_mask = 1'h1;
- assign mem_flushall_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_flushall_MPORT_26_data = io_in_bits_2_bits_flushall;
- assign mem_flushall_MPORT_26_addr = 3'h6;
- assign mem_flushall_MPORT_26_mask = 1'h1;
- assign mem_flushall_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_flushall_MPORT_27_data = io_in_bits_3_bits_flushall;
- assign mem_flushall_MPORT_27_addr = 3'h6;
- assign mem_flushall_MPORT_27_mask = 1'h1;
- assign mem_flushall_MPORT_27_en = ivalid & _GEN_1668;
- assign mem_sldst_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_sldst_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_sldst_mslice_io_in_bits_MPORT_data = mem_sldst[mem_sldst_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_sldst_mslice_io_in_bits_MPORT_data = mem_sldst_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_23[0:0] :
- mem_sldst[mem_sldst_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_sldst_MPORT_data = io_in_bits_0_bits_sldst;
- assign mem_sldst_MPORT_addr = 3'h0;
- assign mem_sldst_MPORT_mask = 1'h1;
- assign mem_sldst_MPORT_en = ivalid & valid[0];
- assign mem_sldst_MPORT_1_data = io_in_bits_1_bits_sldst;
- assign mem_sldst_MPORT_1_addr = 3'h0;
- assign mem_sldst_MPORT_1_mask = 1'h1;
- assign mem_sldst_MPORT_1_en = ivalid & _GEN_134;
- assign mem_sldst_MPORT_2_data = io_in_bits_2_bits_sldst;
- assign mem_sldst_MPORT_2_addr = 3'h0;
- assign mem_sldst_MPORT_2_mask = 1'h1;
- assign mem_sldst_MPORT_2_en = ivalid & _GEN_152;
- assign mem_sldst_MPORT_3_data = io_in_bits_3_bits_sldst;
- assign mem_sldst_MPORT_3_addr = 3'h0;
- assign mem_sldst_MPORT_3_mask = 1'h1;
- assign mem_sldst_MPORT_3_en = ivalid & _GEN_170;
- assign mem_sldst_MPORT_4_data = io_in_bits_0_bits_sldst;
- assign mem_sldst_MPORT_4_addr = 3'h1;
- assign mem_sldst_MPORT_4_mask = 1'h1;
- assign mem_sldst_MPORT_4_en = ivalid & valid_1[0];
- assign mem_sldst_MPORT_5_data = io_in_bits_1_bits_sldst;
- assign mem_sldst_MPORT_5_addr = 3'h1;
- assign mem_sldst_MPORT_5_mask = 1'h1;
- assign mem_sldst_MPORT_5_en = ivalid & _GEN_379;
- assign mem_sldst_MPORT_6_data = io_in_bits_2_bits_sldst;
- assign mem_sldst_MPORT_6_addr = 3'h1;
- assign mem_sldst_MPORT_6_mask = 1'h1;
- assign mem_sldst_MPORT_6_en = ivalid & _GEN_396;
- assign mem_sldst_MPORT_7_data = io_in_bits_3_bits_sldst;
- assign mem_sldst_MPORT_7_addr = 3'h1;
- assign mem_sldst_MPORT_7_mask = 1'h1;
- assign mem_sldst_MPORT_7_en = ivalid & _GEN_413;
- assign mem_sldst_MPORT_8_data = io_in_bits_0_bits_sldst;
- assign mem_sldst_MPORT_8_addr = 3'h2;
- assign mem_sldst_MPORT_8_mask = 1'h1;
- assign mem_sldst_MPORT_8_en = ivalid & valid_2[0];
- assign mem_sldst_MPORT_9_data = io_in_bits_1_bits_sldst;
- assign mem_sldst_MPORT_9_addr = 3'h2;
- assign mem_sldst_MPORT_9_mask = 1'h1;
- assign mem_sldst_MPORT_9_en = ivalid & _GEN_624;
- assign mem_sldst_MPORT_10_data = io_in_bits_2_bits_sldst;
- assign mem_sldst_MPORT_10_addr = 3'h2;
- assign mem_sldst_MPORT_10_mask = 1'h1;
- assign mem_sldst_MPORT_10_en = ivalid & _GEN_642;
- assign mem_sldst_MPORT_11_data = io_in_bits_3_bits_sldst;
- assign mem_sldst_MPORT_11_addr = 3'h2;
- assign mem_sldst_MPORT_11_mask = 1'h1;
- assign mem_sldst_MPORT_11_en = ivalid & _GEN_660;
- assign mem_sldst_MPORT_12_data = io_in_bits_0_bits_sldst;
- assign mem_sldst_MPORT_12_addr = 3'h3;
- assign mem_sldst_MPORT_12_mask = 1'h1;
- assign mem_sldst_MPORT_12_en = ivalid & valid_3[0];
- assign mem_sldst_MPORT_13_data = io_in_bits_1_bits_sldst;
- assign mem_sldst_MPORT_13_addr = 3'h3;
- assign mem_sldst_MPORT_13_mask = 1'h1;
- assign mem_sldst_MPORT_13_en = ivalid & _GEN_876;
- assign mem_sldst_MPORT_14_data = io_in_bits_2_bits_sldst;
- assign mem_sldst_MPORT_14_addr = 3'h3;
- assign mem_sldst_MPORT_14_mask = 1'h1;
- assign mem_sldst_MPORT_14_en = ivalid & _GEN_894;
- assign mem_sldst_MPORT_15_data = io_in_bits_3_bits_sldst;
- assign mem_sldst_MPORT_15_addr = 3'h3;
- assign mem_sldst_MPORT_15_mask = 1'h1;
- assign mem_sldst_MPORT_15_en = ivalid & _GEN_912;
- assign mem_sldst_MPORT_16_data = io_in_bits_0_bits_sldst;
- assign mem_sldst_MPORT_16_addr = 3'h4;
- assign mem_sldst_MPORT_16_mask = 1'h1;
- assign mem_sldst_MPORT_16_en = ivalid & valid_4[0];
- assign mem_sldst_MPORT_17_data = io_in_bits_1_bits_sldst;
- assign mem_sldst_MPORT_17_addr = 3'h4;
- assign mem_sldst_MPORT_17_mask = 1'h1;
- assign mem_sldst_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_sldst_MPORT_18_data = io_in_bits_2_bits_sldst;
- assign mem_sldst_MPORT_18_addr = 3'h4;
- assign mem_sldst_MPORT_18_mask = 1'h1;
- assign mem_sldst_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_sldst_MPORT_19_data = io_in_bits_3_bits_sldst;
- assign mem_sldst_MPORT_19_addr = 3'h4;
- assign mem_sldst_MPORT_19_mask = 1'h1;
- assign mem_sldst_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_sldst_MPORT_20_data = io_in_bits_0_bits_sldst;
- assign mem_sldst_MPORT_20_addr = 3'h5;
- assign mem_sldst_MPORT_20_mask = 1'h1;
- assign mem_sldst_MPORT_20_en = ivalid & valid_5[0];
- assign mem_sldst_MPORT_21_data = io_in_bits_1_bits_sldst;
- assign mem_sldst_MPORT_21_addr = 3'h5;
- assign mem_sldst_MPORT_21_mask = 1'h1;
- assign mem_sldst_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_sldst_MPORT_22_data = io_in_bits_2_bits_sldst;
- assign mem_sldst_MPORT_22_addr = 3'h5;
- assign mem_sldst_MPORT_22_mask = 1'h1;
- assign mem_sldst_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_sldst_MPORT_23_data = io_in_bits_3_bits_sldst;
- assign mem_sldst_MPORT_23_addr = 3'h5;
- assign mem_sldst_MPORT_23_mask = 1'h1;
- assign mem_sldst_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_sldst_MPORT_24_data = io_in_bits_0_bits_sldst;
- assign mem_sldst_MPORT_24_addr = 3'h6;
- assign mem_sldst_MPORT_24_mask = 1'h1;
- assign mem_sldst_MPORT_24_en = ivalid & valid_6[0];
- assign mem_sldst_MPORT_25_data = io_in_bits_1_bits_sldst;
- assign mem_sldst_MPORT_25_addr = 3'h6;
- assign mem_sldst_MPORT_25_mask = 1'h1;
- assign mem_sldst_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_sldst_MPORT_26_data = io_in_bits_2_bits_sldst;
- assign mem_sldst_MPORT_26_addr = 3'h6;
- assign mem_sldst_MPORT_26_mask = 1'h1;
- assign mem_sldst_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_sldst_MPORT_27_data = io_in_bits_3_bits_sldst;
- assign mem_sldst_MPORT_27_addr = 3'h6;
- assign mem_sldst_MPORT_27_mask = 1'h1;
- assign mem_sldst_MPORT_27_en = ivalid & _GEN_1668;
- assign mem_vldst_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_vldst_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_vldst_mslice_io_in_bits_MPORT_data = mem_vldst[mem_vldst_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_vldst_mslice_io_in_bits_MPORT_data = mem_vldst_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_25[0:0] :
- mem_vldst[mem_vldst_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_vldst_MPORT_data = io_in_bits_0_bits_vldst;
- assign mem_vldst_MPORT_addr = 3'h0;
- assign mem_vldst_MPORT_mask = 1'h1;
- assign mem_vldst_MPORT_en = ivalid & valid[0];
- assign mem_vldst_MPORT_1_data = io_in_bits_1_bits_vldst;
- assign mem_vldst_MPORT_1_addr = 3'h0;
- assign mem_vldst_MPORT_1_mask = 1'h1;
- assign mem_vldst_MPORT_1_en = ivalid & _GEN_134;
- assign mem_vldst_MPORT_2_data = io_in_bits_2_bits_vldst;
- assign mem_vldst_MPORT_2_addr = 3'h0;
- assign mem_vldst_MPORT_2_mask = 1'h1;
- assign mem_vldst_MPORT_2_en = ivalid & _GEN_152;
- assign mem_vldst_MPORT_3_data = io_in_bits_3_bits_vldst;
- assign mem_vldst_MPORT_3_addr = 3'h0;
- assign mem_vldst_MPORT_3_mask = 1'h1;
- assign mem_vldst_MPORT_3_en = ivalid & _GEN_170;
- assign mem_vldst_MPORT_4_data = io_in_bits_0_bits_vldst;
- assign mem_vldst_MPORT_4_addr = 3'h1;
- assign mem_vldst_MPORT_4_mask = 1'h1;
- assign mem_vldst_MPORT_4_en = ivalid & valid_1[0];
- assign mem_vldst_MPORT_5_data = io_in_bits_1_bits_vldst;
- assign mem_vldst_MPORT_5_addr = 3'h1;
- assign mem_vldst_MPORT_5_mask = 1'h1;
- assign mem_vldst_MPORT_5_en = ivalid & _GEN_379;
- assign mem_vldst_MPORT_6_data = io_in_bits_2_bits_vldst;
- assign mem_vldst_MPORT_6_addr = 3'h1;
- assign mem_vldst_MPORT_6_mask = 1'h1;
- assign mem_vldst_MPORT_6_en = ivalid & _GEN_396;
- assign mem_vldst_MPORT_7_data = io_in_bits_3_bits_vldst;
- assign mem_vldst_MPORT_7_addr = 3'h1;
- assign mem_vldst_MPORT_7_mask = 1'h1;
- assign mem_vldst_MPORT_7_en = ivalid & _GEN_413;
- assign mem_vldst_MPORT_8_data = io_in_bits_0_bits_vldst;
- assign mem_vldst_MPORT_8_addr = 3'h2;
- assign mem_vldst_MPORT_8_mask = 1'h1;
- assign mem_vldst_MPORT_8_en = ivalid & valid_2[0];
- assign mem_vldst_MPORT_9_data = io_in_bits_1_bits_vldst;
- assign mem_vldst_MPORT_9_addr = 3'h2;
- assign mem_vldst_MPORT_9_mask = 1'h1;
- assign mem_vldst_MPORT_9_en = ivalid & _GEN_624;
- assign mem_vldst_MPORT_10_data = io_in_bits_2_bits_vldst;
- assign mem_vldst_MPORT_10_addr = 3'h2;
- assign mem_vldst_MPORT_10_mask = 1'h1;
- assign mem_vldst_MPORT_10_en = ivalid & _GEN_642;
- assign mem_vldst_MPORT_11_data = io_in_bits_3_bits_vldst;
- assign mem_vldst_MPORT_11_addr = 3'h2;
- assign mem_vldst_MPORT_11_mask = 1'h1;
- assign mem_vldst_MPORT_11_en = ivalid & _GEN_660;
- assign mem_vldst_MPORT_12_data = io_in_bits_0_bits_vldst;
- assign mem_vldst_MPORT_12_addr = 3'h3;
- assign mem_vldst_MPORT_12_mask = 1'h1;
- assign mem_vldst_MPORT_12_en = ivalid & valid_3[0];
- assign mem_vldst_MPORT_13_data = io_in_bits_1_bits_vldst;
- assign mem_vldst_MPORT_13_addr = 3'h3;
- assign mem_vldst_MPORT_13_mask = 1'h1;
- assign mem_vldst_MPORT_13_en = ivalid & _GEN_876;
- assign mem_vldst_MPORT_14_data = io_in_bits_2_bits_vldst;
- assign mem_vldst_MPORT_14_addr = 3'h3;
- assign mem_vldst_MPORT_14_mask = 1'h1;
- assign mem_vldst_MPORT_14_en = ivalid & _GEN_894;
- assign mem_vldst_MPORT_15_data = io_in_bits_3_bits_vldst;
- assign mem_vldst_MPORT_15_addr = 3'h3;
- assign mem_vldst_MPORT_15_mask = 1'h1;
- assign mem_vldst_MPORT_15_en = ivalid & _GEN_912;
- assign mem_vldst_MPORT_16_data = io_in_bits_0_bits_vldst;
- assign mem_vldst_MPORT_16_addr = 3'h4;
- assign mem_vldst_MPORT_16_mask = 1'h1;
- assign mem_vldst_MPORT_16_en = ivalid & valid_4[0];
- assign mem_vldst_MPORT_17_data = io_in_bits_1_bits_vldst;
- assign mem_vldst_MPORT_17_addr = 3'h4;
- assign mem_vldst_MPORT_17_mask = 1'h1;
- assign mem_vldst_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_vldst_MPORT_18_data = io_in_bits_2_bits_vldst;
- assign mem_vldst_MPORT_18_addr = 3'h4;
- assign mem_vldst_MPORT_18_mask = 1'h1;
- assign mem_vldst_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_vldst_MPORT_19_data = io_in_bits_3_bits_vldst;
- assign mem_vldst_MPORT_19_addr = 3'h4;
- assign mem_vldst_MPORT_19_mask = 1'h1;
- assign mem_vldst_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_vldst_MPORT_20_data = io_in_bits_0_bits_vldst;
- assign mem_vldst_MPORT_20_addr = 3'h5;
- assign mem_vldst_MPORT_20_mask = 1'h1;
- assign mem_vldst_MPORT_20_en = ivalid & valid_5[0];
- assign mem_vldst_MPORT_21_data = io_in_bits_1_bits_vldst;
- assign mem_vldst_MPORT_21_addr = 3'h5;
- assign mem_vldst_MPORT_21_mask = 1'h1;
- assign mem_vldst_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_vldst_MPORT_22_data = io_in_bits_2_bits_vldst;
- assign mem_vldst_MPORT_22_addr = 3'h5;
- assign mem_vldst_MPORT_22_mask = 1'h1;
- assign mem_vldst_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_vldst_MPORT_23_data = io_in_bits_3_bits_vldst;
- assign mem_vldst_MPORT_23_addr = 3'h5;
- assign mem_vldst_MPORT_23_mask = 1'h1;
- assign mem_vldst_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_vldst_MPORT_24_data = io_in_bits_0_bits_vldst;
- assign mem_vldst_MPORT_24_addr = 3'h6;
- assign mem_vldst_MPORT_24_mask = 1'h1;
- assign mem_vldst_MPORT_24_en = ivalid & valid_6[0];
- assign mem_vldst_MPORT_25_data = io_in_bits_1_bits_vldst;
- assign mem_vldst_MPORT_25_addr = 3'h6;
- assign mem_vldst_MPORT_25_mask = 1'h1;
- assign mem_vldst_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_vldst_MPORT_26_data = io_in_bits_2_bits_vldst;
- assign mem_vldst_MPORT_26_addr = 3'h6;
- assign mem_vldst_MPORT_26_mask = 1'h1;
- assign mem_vldst_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_vldst_MPORT_27_data = io_in_bits_3_bits_vldst;
- assign mem_vldst_MPORT_27_addr = 3'h6;
- assign mem_vldst_MPORT_27_mask = 1'h1;
- assign mem_vldst_MPORT_27_en = ivalid & _GEN_1668;
- assign mem_suncd_mslice_io_in_bits_MPORT_en = mcount > 4'h0;
- assign mem_suncd_mslice_io_in_bits_MPORT_addr = outpos;
- `ifndef RANDOMIZE_GARBAGE_ASSIGN
- assign mem_suncd_mslice_io_in_bits_MPORT_data = mem_suncd[mem_suncd_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `else
- assign mem_suncd_mslice_io_in_bits_MPORT_data = mem_suncd_mslice_io_in_bits_MPORT_addr >= 3'h7 ? _RAND_27[0:0] :
- mem_suncd[mem_suncd_mslice_io_in_bits_MPORT_addr]; // @[Fifo4.scala 73:16]
- `endif // RANDOMIZE_GARBAGE_ASSIGN
- assign mem_suncd_MPORT_data = io_in_bits_0_bits_suncd;
- assign mem_suncd_MPORT_addr = 3'h0;
- assign mem_suncd_MPORT_mask = 1'h1;
- assign mem_suncd_MPORT_en = ivalid & valid[0];
- assign mem_suncd_MPORT_1_data = io_in_bits_1_bits_suncd;
- assign mem_suncd_MPORT_1_addr = 3'h0;
- assign mem_suncd_MPORT_1_mask = 1'h1;
- assign mem_suncd_MPORT_1_en = ivalid & _GEN_134;
- assign mem_suncd_MPORT_2_data = io_in_bits_2_bits_suncd;
- assign mem_suncd_MPORT_2_addr = 3'h0;
- assign mem_suncd_MPORT_2_mask = 1'h1;
- assign mem_suncd_MPORT_2_en = ivalid & _GEN_152;
- assign mem_suncd_MPORT_3_data = io_in_bits_3_bits_suncd;
- assign mem_suncd_MPORT_3_addr = 3'h0;
- assign mem_suncd_MPORT_3_mask = 1'h1;
- assign mem_suncd_MPORT_3_en = ivalid & _GEN_170;
- assign mem_suncd_MPORT_4_data = io_in_bits_0_bits_suncd;
- assign mem_suncd_MPORT_4_addr = 3'h1;
- assign mem_suncd_MPORT_4_mask = 1'h1;
- assign mem_suncd_MPORT_4_en = ivalid & valid_1[0];
- assign mem_suncd_MPORT_5_data = io_in_bits_1_bits_suncd;
- assign mem_suncd_MPORT_5_addr = 3'h1;
- assign mem_suncd_MPORT_5_mask = 1'h1;
- assign mem_suncd_MPORT_5_en = ivalid & _GEN_379;
- assign mem_suncd_MPORT_6_data = io_in_bits_2_bits_suncd;
- assign mem_suncd_MPORT_6_addr = 3'h1;
- assign mem_suncd_MPORT_6_mask = 1'h1;
- assign mem_suncd_MPORT_6_en = ivalid & _GEN_396;
- assign mem_suncd_MPORT_7_data = io_in_bits_3_bits_suncd;
- assign mem_suncd_MPORT_7_addr = 3'h1;
- assign mem_suncd_MPORT_7_mask = 1'h1;
- assign mem_suncd_MPORT_7_en = ivalid & _GEN_413;
- assign mem_suncd_MPORT_8_data = io_in_bits_0_bits_suncd;
- assign mem_suncd_MPORT_8_addr = 3'h2;
- assign mem_suncd_MPORT_8_mask = 1'h1;
- assign mem_suncd_MPORT_8_en = ivalid & valid_2[0];
- assign mem_suncd_MPORT_9_data = io_in_bits_1_bits_suncd;
- assign mem_suncd_MPORT_9_addr = 3'h2;
- assign mem_suncd_MPORT_9_mask = 1'h1;
- assign mem_suncd_MPORT_9_en = ivalid & _GEN_624;
- assign mem_suncd_MPORT_10_data = io_in_bits_2_bits_suncd;
- assign mem_suncd_MPORT_10_addr = 3'h2;
- assign mem_suncd_MPORT_10_mask = 1'h1;
- assign mem_suncd_MPORT_10_en = ivalid & _GEN_642;
- assign mem_suncd_MPORT_11_data = io_in_bits_3_bits_suncd;
- assign mem_suncd_MPORT_11_addr = 3'h2;
- assign mem_suncd_MPORT_11_mask = 1'h1;
- assign mem_suncd_MPORT_11_en = ivalid & _GEN_660;
- assign mem_suncd_MPORT_12_data = io_in_bits_0_bits_suncd;
- assign mem_suncd_MPORT_12_addr = 3'h3;
- assign mem_suncd_MPORT_12_mask = 1'h1;
- assign mem_suncd_MPORT_12_en = ivalid & valid_3[0];
- assign mem_suncd_MPORT_13_data = io_in_bits_1_bits_suncd;
- assign mem_suncd_MPORT_13_addr = 3'h3;
- assign mem_suncd_MPORT_13_mask = 1'h1;
- assign mem_suncd_MPORT_13_en = ivalid & _GEN_876;
- assign mem_suncd_MPORT_14_data = io_in_bits_2_bits_suncd;
- assign mem_suncd_MPORT_14_addr = 3'h3;
- assign mem_suncd_MPORT_14_mask = 1'h1;
- assign mem_suncd_MPORT_14_en = ivalid & _GEN_894;
- assign mem_suncd_MPORT_15_data = io_in_bits_3_bits_suncd;
- assign mem_suncd_MPORT_15_addr = 3'h3;
- assign mem_suncd_MPORT_15_mask = 1'h1;
- assign mem_suncd_MPORT_15_en = ivalid & _GEN_912;
- assign mem_suncd_MPORT_16_data = io_in_bits_0_bits_suncd;
- assign mem_suncd_MPORT_16_addr = 3'h4;
- assign mem_suncd_MPORT_16_mask = 1'h1;
- assign mem_suncd_MPORT_16_en = ivalid & valid_4[0];
- assign mem_suncd_MPORT_17_data = io_in_bits_1_bits_suncd;
- assign mem_suncd_MPORT_17_addr = 3'h4;
- assign mem_suncd_MPORT_17_mask = 1'h1;
- assign mem_suncd_MPORT_17_en = ivalid & _GEN_1128;
- assign mem_suncd_MPORT_18_data = io_in_bits_2_bits_suncd;
- assign mem_suncd_MPORT_18_addr = 3'h4;
- assign mem_suncd_MPORT_18_mask = 1'h1;
- assign mem_suncd_MPORT_18_en = ivalid & _GEN_1146;
- assign mem_suncd_MPORT_19_data = io_in_bits_3_bits_suncd;
- assign mem_suncd_MPORT_19_addr = 3'h4;
- assign mem_suncd_MPORT_19_mask = 1'h1;
- assign mem_suncd_MPORT_19_en = ivalid & _GEN_1164;
- assign mem_suncd_MPORT_20_data = io_in_bits_0_bits_suncd;
- assign mem_suncd_MPORT_20_addr = 3'h5;
- assign mem_suncd_MPORT_20_mask = 1'h1;
- assign mem_suncd_MPORT_20_en = ivalid & valid_5[0];
- assign mem_suncd_MPORT_21_data = io_in_bits_1_bits_suncd;
- assign mem_suncd_MPORT_21_addr = 3'h5;
- assign mem_suncd_MPORT_21_mask = 1'h1;
- assign mem_suncd_MPORT_21_en = ivalid & _GEN_1380;
- assign mem_suncd_MPORT_22_data = io_in_bits_2_bits_suncd;
- assign mem_suncd_MPORT_22_addr = 3'h5;
- assign mem_suncd_MPORT_22_mask = 1'h1;
- assign mem_suncd_MPORT_22_en = ivalid & _GEN_1398;
- assign mem_suncd_MPORT_23_data = io_in_bits_3_bits_suncd;
- assign mem_suncd_MPORT_23_addr = 3'h5;
- assign mem_suncd_MPORT_23_mask = 1'h1;
- assign mem_suncd_MPORT_23_en = ivalid & _GEN_1416;
- assign mem_suncd_MPORT_24_data = io_in_bits_0_bits_suncd;
- assign mem_suncd_MPORT_24_addr = 3'h6;
- assign mem_suncd_MPORT_24_mask = 1'h1;
- assign mem_suncd_MPORT_24_en = ivalid & valid_6[0];
- assign mem_suncd_MPORT_25_data = io_in_bits_1_bits_suncd;
- assign mem_suncd_MPORT_25_addr = 3'h6;
- assign mem_suncd_MPORT_25_mask = 1'h1;
- assign mem_suncd_MPORT_25_en = ivalid & _GEN_1632;
- assign mem_suncd_MPORT_26_data = io_in_bits_2_bits_suncd;
- assign mem_suncd_MPORT_26_addr = 3'h6;
- assign mem_suncd_MPORT_26_mask = 1'h1;
- assign mem_suncd_MPORT_26_en = ivalid & _GEN_1650;
- assign mem_suncd_MPORT_27_data = io_in_bits_3_bits_suncd;
- assign mem_suncd_MPORT_27_addr = 3'h6;
- assign mem_suncd_MPORT_27_mask = 1'h1;
- assign mem_suncd_MPORT_27_en = ivalid & _GEN_1668;
- assign io_in_ready = mcount <= _GEN_1853; // @[Fifo4.scala 184:25]
- assign io_out_valid = mslice_io_out_valid; // @[Fifo4.scala 185:10]
- assign io_out_bits_addr = mslice_io_out_bits_addr; // @[Fifo4.scala 185:10]
- assign io_out_bits_adrx = mslice_io_out_bits_adrx; // @[Fifo4.scala 185:10]
- assign io_out_bits_data = mslice_io_out_bits_data; // @[Fifo4.scala 185:10]
- assign io_out_bits_index = mslice_io_out_bits_index; // @[Fifo4.scala 185:10]
- assign io_out_bits_size = mslice_io_out_bits_size; // @[Fifo4.scala 185:10]
- assign io_out_bits_write = mslice_io_out_bits_write; // @[Fifo4.scala 185:10]
- assign io_out_bits_sext = mslice_io_out_bits_sext; // @[Fifo4.scala 185:10]
- assign io_out_bits_iload = mslice_io_out_bits_iload; // @[Fifo4.scala 185:10]
- assign io_out_bits_fencei = mslice_io_out_bits_fencei; // @[Fifo4.scala 185:10]
- assign io_out_bits_flushat = mslice_io_out_bits_flushat; // @[Fifo4.scala 185:10]
- assign io_out_bits_flushall = mslice_io_out_bits_flushall; // @[Fifo4.scala 185:10]
- assign io_out_bits_sldst = mslice_io_out_bits_sldst; // @[Fifo4.scala 185:10]
- assign io_out_bits_vldst = mslice_io_out_bits_vldst; // @[Fifo4.scala 185:10]
- assign io_out_bits_suncd = mslice_io_out_bits_suncd; // @[Fifo4.scala 185:10]
- assign io_count = mcount + _GEN_1846; // @[Fifo4.scala 83:22]
- assign mslice_clock = clock;
- assign mslice_reset = reset;
- assign mslice_io_in_valid = mcount > 4'h0 ? io_out_ready : _T_31; // @[Fifo4.scala 146:23]
- assign mslice_io_in_bits_addr = _T_29 ? mem_addr_mslice_io_in_bits_MPORT_data : _GEN_1828; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_in_bits_adrx = _T_29 ? mem_adrx_mslice_io_in_bits_MPORT_data : _GEN_1827; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_in_bits_data = _T_29 ? mem_data_mslice_io_in_bits_MPORT_data : _GEN_1826; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_in_bits_index = _T_29 ? mem_index_mslice_io_in_bits_MPORT_data : _GEN_1825; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_in_bits_size = _T_29 ? mem_size_mslice_io_in_bits_MPORT_data : _GEN_1824; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_in_bits_write = _T_29 ? mem_write_mslice_io_in_bits_MPORT_data : _GEN_1823; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_in_bits_sext = _T_29 ? mem_sext_mslice_io_in_bits_MPORT_data : _GEN_1822; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_in_bits_iload = _T_29 ? mem_iload_mslice_io_in_bits_MPORT_data : _GEN_1821; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_in_bits_fencei = _T_29 ? mem_fencei_mslice_io_in_bits_MPORT_data : _GEN_1820; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_in_bits_flushat = _T_29 ? mem_flushat_mslice_io_in_bits_MPORT_data : _GEN_1819; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_in_bits_flushall = _T_29 ? mem_flushall_mslice_io_in_bits_MPORT_data : _GEN_1818; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_in_bits_sldst = _T_29 ? mem_sldst_mslice_io_in_bits_MPORT_data : _GEN_1817; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_in_bits_vldst = _T_29 ? mem_vldst_mslice_io_in_bits_MPORT_data : _GEN_1816; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_in_bits_suncd = _T_29 ? mem_suncd_mslice_io_in_bits_MPORT_data : _GEN_1815; // @[Fifo4.scala 156:23 157:23]
- assign mslice_io_out_ready = io_out_ready; // @[Fifo4.scala 185:10]
- always @(posedge clock) begin
- if (mem_addr_MPORT_en & mem_addr_MPORT_mask) begin
- mem_addr[mem_addr_MPORT_addr] <= mem_addr_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_1_en & mem_addr_MPORT_1_mask) begin
- mem_addr[mem_addr_MPORT_1_addr] <= mem_addr_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_2_en & mem_addr_MPORT_2_mask) begin
- mem_addr[mem_addr_MPORT_2_addr] <= mem_addr_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_3_en & mem_addr_MPORT_3_mask) begin
- mem_addr[mem_addr_MPORT_3_addr] <= mem_addr_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_4_en & mem_addr_MPORT_4_mask) begin
- mem_addr[mem_addr_MPORT_4_addr] <= mem_addr_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_5_en & mem_addr_MPORT_5_mask) begin
- mem_addr[mem_addr_MPORT_5_addr] <= mem_addr_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_6_en & mem_addr_MPORT_6_mask) begin
- mem_addr[mem_addr_MPORT_6_addr] <= mem_addr_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_7_en & mem_addr_MPORT_7_mask) begin
- mem_addr[mem_addr_MPORT_7_addr] <= mem_addr_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_8_en & mem_addr_MPORT_8_mask) begin
- mem_addr[mem_addr_MPORT_8_addr] <= mem_addr_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_9_en & mem_addr_MPORT_9_mask) begin
- mem_addr[mem_addr_MPORT_9_addr] <= mem_addr_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_10_en & mem_addr_MPORT_10_mask) begin
- mem_addr[mem_addr_MPORT_10_addr] <= mem_addr_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_11_en & mem_addr_MPORT_11_mask) begin
- mem_addr[mem_addr_MPORT_11_addr] <= mem_addr_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_12_en & mem_addr_MPORT_12_mask) begin
- mem_addr[mem_addr_MPORT_12_addr] <= mem_addr_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_13_en & mem_addr_MPORT_13_mask) begin
- mem_addr[mem_addr_MPORT_13_addr] <= mem_addr_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_14_en & mem_addr_MPORT_14_mask) begin
- mem_addr[mem_addr_MPORT_14_addr] <= mem_addr_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_15_en & mem_addr_MPORT_15_mask) begin
- mem_addr[mem_addr_MPORT_15_addr] <= mem_addr_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_16_en & mem_addr_MPORT_16_mask) begin
- mem_addr[mem_addr_MPORT_16_addr] <= mem_addr_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_17_en & mem_addr_MPORT_17_mask) begin
- mem_addr[mem_addr_MPORT_17_addr] <= mem_addr_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_18_en & mem_addr_MPORT_18_mask) begin
- mem_addr[mem_addr_MPORT_18_addr] <= mem_addr_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_19_en & mem_addr_MPORT_19_mask) begin
- mem_addr[mem_addr_MPORT_19_addr] <= mem_addr_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_20_en & mem_addr_MPORT_20_mask) begin
- mem_addr[mem_addr_MPORT_20_addr] <= mem_addr_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_21_en & mem_addr_MPORT_21_mask) begin
- mem_addr[mem_addr_MPORT_21_addr] <= mem_addr_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_22_en & mem_addr_MPORT_22_mask) begin
- mem_addr[mem_addr_MPORT_22_addr] <= mem_addr_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_23_en & mem_addr_MPORT_23_mask) begin
- mem_addr[mem_addr_MPORT_23_addr] <= mem_addr_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_24_en & mem_addr_MPORT_24_mask) begin
- mem_addr[mem_addr_MPORT_24_addr] <= mem_addr_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_25_en & mem_addr_MPORT_25_mask) begin
- mem_addr[mem_addr_MPORT_25_addr] <= mem_addr_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_26_en & mem_addr_MPORT_26_mask) begin
- mem_addr[mem_addr_MPORT_26_addr] <= mem_addr_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_addr_MPORT_27_en & mem_addr_MPORT_27_mask) begin
- mem_addr[mem_addr_MPORT_27_addr] <= mem_addr_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_en & mem_adrx_MPORT_mask) begin
- mem_adrx[mem_adrx_MPORT_addr] <= mem_adrx_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_1_en & mem_adrx_MPORT_1_mask) begin
- mem_adrx[mem_adrx_MPORT_1_addr] <= mem_adrx_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_2_en & mem_adrx_MPORT_2_mask) begin
- mem_adrx[mem_adrx_MPORT_2_addr] <= mem_adrx_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_3_en & mem_adrx_MPORT_3_mask) begin
- mem_adrx[mem_adrx_MPORT_3_addr] <= mem_adrx_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_4_en & mem_adrx_MPORT_4_mask) begin
- mem_adrx[mem_adrx_MPORT_4_addr] <= mem_adrx_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_5_en & mem_adrx_MPORT_5_mask) begin
- mem_adrx[mem_adrx_MPORT_5_addr] <= mem_adrx_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_6_en & mem_adrx_MPORT_6_mask) begin
- mem_adrx[mem_adrx_MPORT_6_addr] <= mem_adrx_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_7_en & mem_adrx_MPORT_7_mask) begin
- mem_adrx[mem_adrx_MPORT_7_addr] <= mem_adrx_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_8_en & mem_adrx_MPORT_8_mask) begin
- mem_adrx[mem_adrx_MPORT_8_addr] <= mem_adrx_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_9_en & mem_adrx_MPORT_9_mask) begin
- mem_adrx[mem_adrx_MPORT_9_addr] <= mem_adrx_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_10_en & mem_adrx_MPORT_10_mask) begin
- mem_adrx[mem_adrx_MPORT_10_addr] <= mem_adrx_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_11_en & mem_adrx_MPORT_11_mask) begin
- mem_adrx[mem_adrx_MPORT_11_addr] <= mem_adrx_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_12_en & mem_adrx_MPORT_12_mask) begin
- mem_adrx[mem_adrx_MPORT_12_addr] <= mem_adrx_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_13_en & mem_adrx_MPORT_13_mask) begin
- mem_adrx[mem_adrx_MPORT_13_addr] <= mem_adrx_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_14_en & mem_adrx_MPORT_14_mask) begin
- mem_adrx[mem_adrx_MPORT_14_addr] <= mem_adrx_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_15_en & mem_adrx_MPORT_15_mask) begin
- mem_adrx[mem_adrx_MPORT_15_addr] <= mem_adrx_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_16_en & mem_adrx_MPORT_16_mask) begin
- mem_adrx[mem_adrx_MPORT_16_addr] <= mem_adrx_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_17_en & mem_adrx_MPORT_17_mask) begin
- mem_adrx[mem_adrx_MPORT_17_addr] <= mem_adrx_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_18_en & mem_adrx_MPORT_18_mask) begin
- mem_adrx[mem_adrx_MPORT_18_addr] <= mem_adrx_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_19_en & mem_adrx_MPORT_19_mask) begin
- mem_adrx[mem_adrx_MPORT_19_addr] <= mem_adrx_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_20_en & mem_adrx_MPORT_20_mask) begin
- mem_adrx[mem_adrx_MPORT_20_addr] <= mem_adrx_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_21_en & mem_adrx_MPORT_21_mask) begin
- mem_adrx[mem_adrx_MPORT_21_addr] <= mem_adrx_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_22_en & mem_adrx_MPORT_22_mask) begin
- mem_adrx[mem_adrx_MPORT_22_addr] <= mem_adrx_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_23_en & mem_adrx_MPORT_23_mask) begin
- mem_adrx[mem_adrx_MPORT_23_addr] <= mem_adrx_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_24_en & mem_adrx_MPORT_24_mask) begin
- mem_adrx[mem_adrx_MPORT_24_addr] <= mem_adrx_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_25_en & mem_adrx_MPORT_25_mask) begin
- mem_adrx[mem_adrx_MPORT_25_addr] <= mem_adrx_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_26_en & mem_adrx_MPORT_26_mask) begin
- mem_adrx[mem_adrx_MPORT_26_addr] <= mem_adrx_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_adrx_MPORT_27_en & mem_adrx_MPORT_27_mask) begin
- mem_adrx[mem_adrx_MPORT_27_addr] <= mem_adrx_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_en & mem_data_MPORT_mask) begin
- mem_data[mem_data_MPORT_addr] <= mem_data_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_1_en & mem_data_MPORT_1_mask) begin
- mem_data[mem_data_MPORT_1_addr] <= mem_data_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_2_en & mem_data_MPORT_2_mask) begin
- mem_data[mem_data_MPORT_2_addr] <= mem_data_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_3_en & mem_data_MPORT_3_mask) begin
- mem_data[mem_data_MPORT_3_addr] <= mem_data_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_4_en & mem_data_MPORT_4_mask) begin
- mem_data[mem_data_MPORT_4_addr] <= mem_data_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_5_en & mem_data_MPORT_5_mask) begin
- mem_data[mem_data_MPORT_5_addr] <= mem_data_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_6_en & mem_data_MPORT_6_mask) begin
- mem_data[mem_data_MPORT_6_addr] <= mem_data_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_7_en & mem_data_MPORT_7_mask) begin
- mem_data[mem_data_MPORT_7_addr] <= mem_data_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_8_en & mem_data_MPORT_8_mask) begin
- mem_data[mem_data_MPORT_8_addr] <= mem_data_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_9_en & mem_data_MPORT_9_mask) begin
- mem_data[mem_data_MPORT_9_addr] <= mem_data_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_10_en & mem_data_MPORT_10_mask) begin
- mem_data[mem_data_MPORT_10_addr] <= mem_data_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_11_en & mem_data_MPORT_11_mask) begin
- mem_data[mem_data_MPORT_11_addr] <= mem_data_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_12_en & mem_data_MPORT_12_mask) begin
- mem_data[mem_data_MPORT_12_addr] <= mem_data_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_13_en & mem_data_MPORT_13_mask) begin
- mem_data[mem_data_MPORT_13_addr] <= mem_data_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_14_en & mem_data_MPORT_14_mask) begin
- mem_data[mem_data_MPORT_14_addr] <= mem_data_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_15_en & mem_data_MPORT_15_mask) begin
- mem_data[mem_data_MPORT_15_addr] <= mem_data_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_16_en & mem_data_MPORT_16_mask) begin
- mem_data[mem_data_MPORT_16_addr] <= mem_data_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_17_en & mem_data_MPORT_17_mask) begin
- mem_data[mem_data_MPORT_17_addr] <= mem_data_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_18_en & mem_data_MPORT_18_mask) begin
- mem_data[mem_data_MPORT_18_addr] <= mem_data_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_19_en & mem_data_MPORT_19_mask) begin
- mem_data[mem_data_MPORT_19_addr] <= mem_data_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_20_en & mem_data_MPORT_20_mask) begin
- mem_data[mem_data_MPORT_20_addr] <= mem_data_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_21_en & mem_data_MPORT_21_mask) begin
- mem_data[mem_data_MPORT_21_addr] <= mem_data_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_22_en & mem_data_MPORT_22_mask) begin
- mem_data[mem_data_MPORT_22_addr] <= mem_data_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_23_en & mem_data_MPORT_23_mask) begin
- mem_data[mem_data_MPORT_23_addr] <= mem_data_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_24_en & mem_data_MPORT_24_mask) begin
- mem_data[mem_data_MPORT_24_addr] <= mem_data_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_25_en & mem_data_MPORT_25_mask) begin
- mem_data[mem_data_MPORT_25_addr] <= mem_data_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_26_en & mem_data_MPORT_26_mask) begin
- mem_data[mem_data_MPORT_26_addr] <= mem_data_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_data_MPORT_27_en & mem_data_MPORT_27_mask) begin
- mem_data[mem_data_MPORT_27_addr] <= mem_data_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_en & mem_index_MPORT_mask) begin
- mem_index[mem_index_MPORT_addr] <= mem_index_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_1_en & mem_index_MPORT_1_mask) begin
- mem_index[mem_index_MPORT_1_addr] <= mem_index_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_2_en & mem_index_MPORT_2_mask) begin
- mem_index[mem_index_MPORT_2_addr] <= mem_index_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_3_en & mem_index_MPORT_3_mask) begin
- mem_index[mem_index_MPORT_3_addr] <= mem_index_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_4_en & mem_index_MPORT_4_mask) begin
- mem_index[mem_index_MPORT_4_addr] <= mem_index_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_5_en & mem_index_MPORT_5_mask) begin
- mem_index[mem_index_MPORT_5_addr] <= mem_index_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_6_en & mem_index_MPORT_6_mask) begin
- mem_index[mem_index_MPORT_6_addr] <= mem_index_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_7_en & mem_index_MPORT_7_mask) begin
- mem_index[mem_index_MPORT_7_addr] <= mem_index_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_8_en & mem_index_MPORT_8_mask) begin
- mem_index[mem_index_MPORT_8_addr] <= mem_index_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_9_en & mem_index_MPORT_9_mask) begin
- mem_index[mem_index_MPORT_9_addr] <= mem_index_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_10_en & mem_index_MPORT_10_mask) begin
- mem_index[mem_index_MPORT_10_addr] <= mem_index_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_11_en & mem_index_MPORT_11_mask) begin
- mem_index[mem_index_MPORT_11_addr] <= mem_index_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_12_en & mem_index_MPORT_12_mask) begin
- mem_index[mem_index_MPORT_12_addr] <= mem_index_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_13_en & mem_index_MPORT_13_mask) begin
- mem_index[mem_index_MPORT_13_addr] <= mem_index_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_14_en & mem_index_MPORT_14_mask) begin
- mem_index[mem_index_MPORT_14_addr] <= mem_index_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_15_en & mem_index_MPORT_15_mask) begin
- mem_index[mem_index_MPORT_15_addr] <= mem_index_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_16_en & mem_index_MPORT_16_mask) begin
- mem_index[mem_index_MPORT_16_addr] <= mem_index_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_17_en & mem_index_MPORT_17_mask) begin
- mem_index[mem_index_MPORT_17_addr] <= mem_index_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_18_en & mem_index_MPORT_18_mask) begin
- mem_index[mem_index_MPORT_18_addr] <= mem_index_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_19_en & mem_index_MPORT_19_mask) begin
- mem_index[mem_index_MPORT_19_addr] <= mem_index_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_20_en & mem_index_MPORT_20_mask) begin
- mem_index[mem_index_MPORT_20_addr] <= mem_index_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_21_en & mem_index_MPORT_21_mask) begin
- mem_index[mem_index_MPORT_21_addr] <= mem_index_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_22_en & mem_index_MPORT_22_mask) begin
- mem_index[mem_index_MPORT_22_addr] <= mem_index_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_23_en & mem_index_MPORT_23_mask) begin
- mem_index[mem_index_MPORT_23_addr] <= mem_index_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_24_en & mem_index_MPORT_24_mask) begin
- mem_index[mem_index_MPORT_24_addr] <= mem_index_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_25_en & mem_index_MPORT_25_mask) begin
- mem_index[mem_index_MPORT_25_addr] <= mem_index_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_26_en & mem_index_MPORT_26_mask) begin
- mem_index[mem_index_MPORT_26_addr] <= mem_index_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_index_MPORT_27_en & mem_index_MPORT_27_mask) begin
- mem_index[mem_index_MPORT_27_addr] <= mem_index_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_en & mem_size_MPORT_mask) begin
- mem_size[mem_size_MPORT_addr] <= mem_size_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_1_en & mem_size_MPORT_1_mask) begin
- mem_size[mem_size_MPORT_1_addr] <= mem_size_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_2_en & mem_size_MPORT_2_mask) begin
- mem_size[mem_size_MPORT_2_addr] <= mem_size_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_3_en & mem_size_MPORT_3_mask) begin
- mem_size[mem_size_MPORT_3_addr] <= mem_size_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_4_en & mem_size_MPORT_4_mask) begin
- mem_size[mem_size_MPORT_4_addr] <= mem_size_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_5_en & mem_size_MPORT_5_mask) begin
- mem_size[mem_size_MPORT_5_addr] <= mem_size_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_6_en & mem_size_MPORT_6_mask) begin
- mem_size[mem_size_MPORT_6_addr] <= mem_size_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_7_en & mem_size_MPORT_7_mask) begin
- mem_size[mem_size_MPORT_7_addr] <= mem_size_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_8_en & mem_size_MPORT_8_mask) begin
- mem_size[mem_size_MPORT_8_addr] <= mem_size_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_9_en & mem_size_MPORT_9_mask) begin
- mem_size[mem_size_MPORT_9_addr] <= mem_size_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_10_en & mem_size_MPORT_10_mask) begin
- mem_size[mem_size_MPORT_10_addr] <= mem_size_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_11_en & mem_size_MPORT_11_mask) begin
- mem_size[mem_size_MPORT_11_addr] <= mem_size_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_12_en & mem_size_MPORT_12_mask) begin
- mem_size[mem_size_MPORT_12_addr] <= mem_size_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_13_en & mem_size_MPORT_13_mask) begin
- mem_size[mem_size_MPORT_13_addr] <= mem_size_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_14_en & mem_size_MPORT_14_mask) begin
- mem_size[mem_size_MPORT_14_addr] <= mem_size_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_15_en & mem_size_MPORT_15_mask) begin
- mem_size[mem_size_MPORT_15_addr] <= mem_size_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_16_en & mem_size_MPORT_16_mask) begin
- mem_size[mem_size_MPORT_16_addr] <= mem_size_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_17_en & mem_size_MPORT_17_mask) begin
- mem_size[mem_size_MPORT_17_addr] <= mem_size_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_18_en & mem_size_MPORT_18_mask) begin
- mem_size[mem_size_MPORT_18_addr] <= mem_size_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_19_en & mem_size_MPORT_19_mask) begin
- mem_size[mem_size_MPORT_19_addr] <= mem_size_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_20_en & mem_size_MPORT_20_mask) begin
- mem_size[mem_size_MPORT_20_addr] <= mem_size_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_21_en & mem_size_MPORT_21_mask) begin
- mem_size[mem_size_MPORT_21_addr] <= mem_size_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_22_en & mem_size_MPORT_22_mask) begin
- mem_size[mem_size_MPORT_22_addr] <= mem_size_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_23_en & mem_size_MPORT_23_mask) begin
- mem_size[mem_size_MPORT_23_addr] <= mem_size_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_24_en & mem_size_MPORT_24_mask) begin
- mem_size[mem_size_MPORT_24_addr] <= mem_size_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_25_en & mem_size_MPORT_25_mask) begin
- mem_size[mem_size_MPORT_25_addr] <= mem_size_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_26_en & mem_size_MPORT_26_mask) begin
- mem_size[mem_size_MPORT_26_addr] <= mem_size_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_size_MPORT_27_en & mem_size_MPORT_27_mask) begin
- mem_size[mem_size_MPORT_27_addr] <= mem_size_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_en & mem_write_MPORT_mask) begin
- mem_write[mem_write_MPORT_addr] <= mem_write_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_1_en & mem_write_MPORT_1_mask) begin
- mem_write[mem_write_MPORT_1_addr] <= mem_write_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_2_en & mem_write_MPORT_2_mask) begin
- mem_write[mem_write_MPORT_2_addr] <= mem_write_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_3_en & mem_write_MPORT_3_mask) begin
- mem_write[mem_write_MPORT_3_addr] <= mem_write_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_4_en & mem_write_MPORT_4_mask) begin
- mem_write[mem_write_MPORT_4_addr] <= mem_write_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_5_en & mem_write_MPORT_5_mask) begin
- mem_write[mem_write_MPORT_5_addr] <= mem_write_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_6_en & mem_write_MPORT_6_mask) begin
- mem_write[mem_write_MPORT_6_addr] <= mem_write_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_7_en & mem_write_MPORT_7_mask) begin
- mem_write[mem_write_MPORT_7_addr] <= mem_write_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_8_en & mem_write_MPORT_8_mask) begin
- mem_write[mem_write_MPORT_8_addr] <= mem_write_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_9_en & mem_write_MPORT_9_mask) begin
- mem_write[mem_write_MPORT_9_addr] <= mem_write_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_10_en & mem_write_MPORT_10_mask) begin
- mem_write[mem_write_MPORT_10_addr] <= mem_write_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_11_en & mem_write_MPORT_11_mask) begin
- mem_write[mem_write_MPORT_11_addr] <= mem_write_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_12_en & mem_write_MPORT_12_mask) begin
- mem_write[mem_write_MPORT_12_addr] <= mem_write_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_13_en & mem_write_MPORT_13_mask) begin
- mem_write[mem_write_MPORT_13_addr] <= mem_write_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_14_en & mem_write_MPORT_14_mask) begin
- mem_write[mem_write_MPORT_14_addr] <= mem_write_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_15_en & mem_write_MPORT_15_mask) begin
- mem_write[mem_write_MPORT_15_addr] <= mem_write_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_16_en & mem_write_MPORT_16_mask) begin
- mem_write[mem_write_MPORT_16_addr] <= mem_write_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_17_en & mem_write_MPORT_17_mask) begin
- mem_write[mem_write_MPORT_17_addr] <= mem_write_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_18_en & mem_write_MPORT_18_mask) begin
- mem_write[mem_write_MPORT_18_addr] <= mem_write_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_19_en & mem_write_MPORT_19_mask) begin
- mem_write[mem_write_MPORT_19_addr] <= mem_write_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_20_en & mem_write_MPORT_20_mask) begin
- mem_write[mem_write_MPORT_20_addr] <= mem_write_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_21_en & mem_write_MPORT_21_mask) begin
- mem_write[mem_write_MPORT_21_addr] <= mem_write_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_22_en & mem_write_MPORT_22_mask) begin
- mem_write[mem_write_MPORT_22_addr] <= mem_write_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_23_en & mem_write_MPORT_23_mask) begin
- mem_write[mem_write_MPORT_23_addr] <= mem_write_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_24_en & mem_write_MPORT_24_mask) begin
- mem_write[mem_write_MPORT_24_addr] <= mem_write_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_25_en & mem_write_MPORT_25_mask) begin
- mem_write[mem_write_MPORT_25_addr] <= mem_write_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_26_en & mem_write_MPORT_26_mask) begin
- mem_write[mem_write_MPORT_26_addr] <= mem_write_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_write_MPORT_27_en & mem_write_MPORT_27_mask) begin
- mem_write[mem_write_MPORT_27_addr] <= mem_write_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_en & mem_sext_MPORT_mask) begin
- mem_sext[mem_sext_MPORT_addr] <= mem_sext_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_1_en & mem_sext_MPORT_1_mask) begin
- mem_sext[mem_sext_MPORT_1_addr] <= mem_sext_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_2_en & mem_sext_MPORT_2_mask) begin
- mem_sext[mem_sext_MPORT_2_addr] <= mem_sext_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_3_en & mem_sext_MPORT_3_mask) begin
- mem_sext[mem_sext_MPORT_3_addr] <= mem_sext_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_4_en & mem_sext_MPORT_4_mask) begin
- mem_sext[mem_sext_MPORT_4_addr] <= mem_sext_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_5_en & mem_sext_MPORT_5_mask) begin
- mem_sext[mem_sext_MPORT_5_addr] <= mem_sext_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_6_en & mem_sext_MPORT_6_mask) begin
- mem_sext[mem_sext_MPORT_6_addr] <= mem_sext_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_7_en & mem_sext_MPORT_7_mask) begin
- mem_sext[mem_sext_MPORT_7_addr] <= mem_sext_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_8_en & mem_sext_MPORT_8_mask) begin
- mem_sext[mem_sext_MPORT_8_addr] <= mem_sext_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_9_en & mem_sext_MPORT_9_mask) begin
- mem_sext[mem_sext_MPORT_9_addr] <= mem_sext_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_10_en & mem_sext_MPORT_10_mask) begin
- mem_sext[mem_sext_MPORT_10_addr] <= mem_sext_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_11_en & mem_sext_MPORT_11_mask) begin
- mem_sext[mem_sext_MPORT_11_addr] <= mem_sext_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_12_en & mem_sext_MPORT_12_mask) begin
- mem_sext[mem_sext_MPORT_12_addr] <= mem_sext_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_13_en & mem_sext_MPORT_13_mask) begin
- mem_sext[mem_sext_MPORT_13_addr] <= mem_sext_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_14_en & mem_sext_MPORT_14_mask) begin
- mem_sext[mem_sext_MPORT_14_addr] <= mem_sext_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_15_en & mem_sext_MPORT_15_mask) begin
- mem_sext[mem_sext_MPORT_15_addr] <= mem_sext_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_16_en & mem_sext_MPORT_16_mask) begin
- mem_sext[mem_sext_MPORT_16_addr] <= mem_sext_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_17_en & mem_sext_MPORT_17_mask) begin
- mem_sext[mem_sext_MPORT_17_addr] <= mem_sext_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_18_en & mem_sext_MPORT_18_mask) begin
- mem_sext[mem_sext_MPORT_18_addr] <= mem_sext_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_19_en & mem_sext_MPORT_19_mask) begin
- mem_sext[mem_sext_MPORT_19_addr] <= mem_sext_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_20_en & mem_sext_MPORT_20_mask) begin
- mem_sext[mem_sext_MPORT_20_addr] <= mem_sext_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_21_en & mem_sext_MPORT_21_mask) begin
- mem_sext[mem_sext_MPORT_21_addr] <= mem_sext_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_22_en & mem_sext_MPORT_22_mask) begin
- mem_sext[mem_sext_MPORT_22_addr] <= mem_sext_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_23_en & mem_sext_MPORT_23_mask) begin
- mem_sext[mem_sext_MPORT_23_addr] <= mem_sext_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_24_en & mem_sext_MPORT_24_mask) begin
- mem_sext[mem_sext_MPORT_24_addr] <= mem_sext_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_25_en & mem_sext_MPORT_25_mask) begin
- mem_sext[mem_sext_MPORT_25_addr] <= mem_sext_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_26_en & mem_sext_MPORT_26_mask) begin
- mem_sext[mem_sext_MPORT_26_addr] <= mem_sext_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sext_MPORT_27_en & mem_sext_MPORT_27_mask) begin
- mem_sext[mem_sext_MPORT_27_addr] <= mem_sext_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_en & mem_iload_MPORT_mask) begin
- mem_iload[mem_iload_MPORT_addr] <= mem_iload_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_1_en & mem_iload_MPORT_1_mask) begin
- mem_iload[mem_iload_MPORT_1_addr] <= mem_iload_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_2_en & mem_iload_MPORT_2_mask) begin
- mem_iload[mem_iload_MPORT_2_addr] <= mem_iload_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_3_en & mem_iload_MPORT_3_mask) begin
- mem_iload[mem_iload_MPORT_3_addr] <= mem_iload_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_4_en & mem_iload_MPORT_4_mask) begin
- mem_iload[mem_iload_MPORT_4_addr] <= mem_iload_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_5_en & mem_iload_MPORT_5_mask) begin
- mem_iload[mem_iload_MPORT_5_addr] <= mem_iload_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_6_en & mem_iload_MPORT_6_mask) begin
- mem_iload[mem_iload_MPORT_6_addr] <= mem_iload_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_7_en & mem_iload_MPORT_7_mask) begin
- mem_iload[mem_iload_MPORT_7_addr] <= mem_iload_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_8_en & mem_iload_MPORT_8_mask) begin
- mem_iload[mem_iload_MPORT_8_addr] <= mem_iload_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_9_en & mem_iload_MPORT_9_mask) begin
- mem_iload[mem_iload_MPORT_9_addr] <= mem_iload_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_10_en & mem_iload_MPORT_10_mask) begin
- mem_iload[mem_iload_MPORT_10_addr] <= mem_iload_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_11_en & mem_iload_MPORT_11_mask) begin
- mem_iload[mem_iload_MPORT_11_addr] <= mem_iload_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_12_en & mem_iload_MPORT_12_mask) begin
- mem_iload[mem_iload_MPORT_12_addr] <= mem_iload_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_13_en & mem_iload_MPORT_13_mask) begin
- mem_iload[mem_iload_MPORT_13_addr] <= mem_iload_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_14_en & mem_iload_MPORT_14_mask) begin
- mem_iload[mem_iload_MPORT_14_addr] <= mem_iload_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_15_en & mem_iload_MPORT_15_mask) begin
- mem_iload[mem_iload_MPORT_15_addr] <= mem_iload_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_16_en & mem_iload_MPORT_16_mask) begin
- mem_iload[mem_iload_MPORT_16_addr] <= mem_iload_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_17_en & mem_iload_MPORT_17_mask) begin
- mem_iload[mem_iload_MPORT_17_addr] <= mem_iload_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_18_en & mem_iload_MPORT_18_mask) begin
- mem_iload[mem_iload_MPORT_18_addr] <= mem_iload_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_19_en & mem_iload_MPORT_19_mask) begin
- mem_iload[mem_iload_MPORT_19_addr] <= mem_iload_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_20_en & mem_iload_MPORT_20_mask) begin
- mem_iload[mem_iload_MPORT_20_addr] <= mem_iload_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_21_en & mem_iload_MPORT_21_mask) begin
- mem_iload[mem_iload_MPORT_21_addr] <= mem_iload_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_22_en & mem_iload_MPORT_22_mask) begin
- mem_iload[mem_iload_MPORT_22_addr] <= mem_iload_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_23_en & mem_iload_MPORT_23_mask) begin
- mem_iload[mem_iload_MPORT_23_addr] <= mem_iload_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_24_en & mem_iload_MPORT_24_mask) begin
- mem_iload[mem_iload_MPORT_24_addr] <= mem_iload_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_25_en & mem_iload_MPORT_25_mask) begin
- mem_iload[mem_iload_MPORT_25_addr] <= mem_iload_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_26_en & mem_iload_MPORT_26_mask) begin
- mem_iload[mem_iload_MPORT_26_addr] <= mem_iload_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_iload_MPORT_27_en & mem_iload_MPORT_27_mask) begin
- mem_iload[mem_iload_MPORT_27_addr] <= mem_iload_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_en & mem_fencei_MPORT_mask) begin
- mem_fencei[mem_fencei_MPORT_addr] <= mem_fencei_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_1_en & mem_fencei_MPORT_1_mask) begin
- mem_fencei[mem_fencei_MPORT_1_addr] <= mem_fencei_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_2_en & mem_fencei_MPORT_2_mask) begin
- mem_fencei[mem_fencei_MPORT_2_addr] <= mem_fencei_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_3_en & mem_fencei_MPORT_3_mask) begin
- mem_fencei[mem_fencei_MPORT_3_addr] <= mem_fencei_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_4_en & mem_fencei_MPORT_4_mask) begin
- mem_fencei[mem_fencei_MPORT_4_addr] <= mem_fencei_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_5_en & mem_fencei_MPORT_5_mask) begin
- mem_fencei[mem_fencei_MPORT_5_addr] <= mem_fencei_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_6_en & mem_fencei_MPORT_6_mask) begin
- mem_fencei[mem_fencei_MPORT_6_addr] <= mem_fencei_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_7_en & mem_fencei_MPORT_7_mask) begin
- mem_fencei[mem_fencei_MPORT_7_addr] <= mem_fencei_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_8_en & mem_fencei_MPORT_8_mask) begin
- mem_fencei[mem_fencei_MPORT_8_addr] <= mem_fencei_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_9_en & mem_fencei_MPORT_9_mask) begin
- mem_fencei[mem_fencei_MPORT_9_addr] <= mem_fencei_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_10_en & mem_fencei_MPORT_10_mask) begin
- mem_fencei[mem_fencei_MPORT_10_addr] <= mem_fencei_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_11_en & mem_fencei_MPORT_11_mask) begin
- mem_fencei[mem_fencei_MPORT_11_addr] <= mem_fencei_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_12_en & mem_fencei_MPORT_12_mask) begin
- mem_fencei[mem_fencei_MPORT_12_addr] <= mem_fencei_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_13_en & mem_fencei_MPORT_13_mask) begin
- mem_fencei[mem_fencei_MPORT_13_addr] <= mem_fencei_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_14_en & mem_fencei_MPORT_14_mask) begin
- mem_fencei[mem_fencei_MPORT_14_addr] <= mem_fencei_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_15_en & mem_fencei_MPORT_15_mask) begin
- mem_fencei[mem_fencei_MPORT_15_addr] <= mem_fencei_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_16_en & mem_fencei_MPORT_16_mask) begin
- mem_fencei[mem_fencei_MPORT_16_addr] <= mem_fencei_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_17_en & mem_fencei_MPORT_17_mask) begin
- mem_fencei[mem_fencei_MPORT_17_addr] <= mem_fencei_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_18_en & mem_fencei_MPORT_18_mask) begin
- mem_fencei[mem_fencei_MPORT_18_addr] <= mem_fencei_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_19_en & mem_fencei_MPORT_19_mask) begin
- mem_fencei[mem_fencei_MPORT_19_addr] <= mem_fencei_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_20_en & mem_fencei_MPORT_20_mask) begin
- mem_fencei[mem_fencei_MPORT_20_addr] <= mem_fencei_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_21_en & mem_fencei_MPORT_21_mask) begin
- mem_fencei[mem_fencei_MPORT_21_addr] <= mem_fencei_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_22_en & mem_fencei_MPORT_22_mask) begin
- mem_fencei[mem_fencei_MPORT_22_addr] <= mem_fencei_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_23_en & mem_fencei_MPORT_23_mask) begin
- mem_fencei[mem_fencei_MPORT_23_addr] <= mem_fencei_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_24_en & mem_fencei_MPORT_24_mask) begin
- mem_fencei[mem_fencei_MPORT_24_addr] <= mem_fencei_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_25_en & mem_fencei_MPORT_25_mask) begin
- mem_fencei[mem_fencei_MPORT_25_addr] <= mem_fencei_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_26_en & mem_fencei_MPORT_26_mask) begin
- mem_fencei[mem_fencei_MPORT_26_addr] <= mem_fencei_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_fencei_MPORT_27_en & mem_fencei_MPORT_27_mask) begin
- mem_fencei[mem_fencei_MPORT_27_addr] <= mem_fencei_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_en & mem_flushat_MPORT_mask) begin
- mem_flushat[mem_flushat_MPORT_addr] <= mem_flushat_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_1_en & mem_flushat_MPORT_1_mask) begin
- mem_flushat[mem_flushat_MPORT_1_addr] <= mem_flushat_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_2_en & mem_flushat_MPORT_2_mask) begin
- mem_flushat[mem_flushat_MPORT_2_addr] <= mem_flushat_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_3_en & mem_flushat_MPORT_3_mask) begin
- mem_flushat[mem_flushat_MPORT_3_addr] <= mem_flushat_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_4_en & mem_flushat_MPORT_4_mask) begin
- mem_flushat[mem_flushat_MPORT_4_addr] <= mem_flushat_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_5_en & mem_flushat_MPORT_5_mask) begin
- mem_flushat[mem_flushat_MPORT_5_addr] <= mem_flushat_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_6_en & mem_flushat_MPORT_6_mask) begin
- mem_flushat[mem_flushat_MPORT_6_addr] <= mem_flushat_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_7_en & mem_flushat_MPORT_7_mask) begin
- mem_flushat[mem_flushat_MPORT_7_addr] <= mem_flushat_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_8_en & mem_flushat_MPORT_8_mask) begin
- mem_flushat[mem_flushat_MPORT_8_addr] <= mem_flushat_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_9_en & mem_flushat_MPORT_9_mask) begin
- mem_flushat[mem_flushat_MPORT_9_addr] <= mem_flushat_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_10_en & mem_flushat_MPORT_10_mask) begin
- mem_flushat[mem_flushat_MPORT_10_addr] <= mem_flushat_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_11_en & mem_flushat_MPORT_11_mask) begin
- mem_flushat[mem_flushat_MPORT_11_addr] <= mem_flushat_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_12_en & mem_flushat_MPORT_12_mask) begin
- mem_flushat[mem_flushat_MPORT_12_addr] <= mem_flushat_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_13_en & mem_flushat_MPORT_13_mask) begin
- mem_flushat[mem_flushat_MPORT_13_addr] <= mem_flushat_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_14_en & mem_flushat_MPORT_14_mask) begin
- mem_flushat[mem_flushat_MPORT_14_addr] <= mem_flushat_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_15_en & mem_flushat_MPORT_15_mask) begin
- mem_flushat[mem_flushat_MPORT_15_addr] <= mem_flushat_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_16_en & mem_flushat_MPORT_16_mask) begin
- mem_flushat[mem_flushat_MPORT_16_addr] <= mem_flushat_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_17_en & mem_flushat_MPORT_17_mask) begin
- mem_flushat[mem_flushat_MPORT_17_addr] <= mem_flushat_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_18_en & mem_flushat_MPORT_18_mask) begin
- mem_flushat[mem_flushat_MPORT_18_addr] <= mem_flushat_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_19_en & mem_flushat_MPORT_19_mask) begin
- mem_flushat[mem_flushat_MPORT_19_addr] <= mem_flushat_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_20_en & mem_flushat_MPORT_20_mask) begin
- mem_flushat[mem_flushat_MPORT_20_addr] <= mem_flushat_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_21_en & mem_flushat_MPORT_21_mask) begin
- mem_flushat[mem_flushat_MPORT_21_addr] <= mem_flushat_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_22_en & mem_flushat_MPORT_22_mask) begin
- mem_flushat[mem_flushat_MPORT_22_addr] <= mem_flushat_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_23_en & mem_flushat_MPORT_23_mask) begin
- mem_flushat[mem_flushat_MPORT_23_addr] <= mem_flushat_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_24_en & mem_flushat_MPORT_24_mask) begin
- mem_flushat[mem_flushat_MPORT_24_addr] <= mem_flushat_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_25_en & mem_flushat_MPORT_25_mask) begin
- mem_flushat[mem_flushat_MPORT_25_addr] <= mem_flushat_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_26_en & mem_flushat_MPORT_26_mask) begin
- mem_flushat[mem_flushat_MPORT_26_addr] <= mem_flushat_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushat_MPORT_27_en & mem_flushat_MPORT_27_mask) begin
- mem_flushat[mem_flushat_MPORT_27_addr] <= mem_flushat_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_en & mem_flushall_MPORT_mask) begin
- mem_flushall[mem_flushall_MPORT_addr] <= mem_flushall_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_1_en & mem_flushall_MPORT_1_mask) begin
- mem_flushall[mem_flushall_MPORT_1_addr] <= mem_flushall_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_2_en & mem_flushall_MPORT_2_mask) begin
- mem_flushall[mem_flushall_MPORT_2_addr] <= mem_flushall_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_3_en & mem_flushall_MPORT_3_mask) begin
- mem_flushall[mem_flushall_MPORT_3_addr] <= mem_flushall_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_4_en & mem_flushall_MPORT_4_mask) begin
- mem_flushall[mem_flushall_MPORT_4_addr] <= mem_flushall_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_5_en & mem_flushall_MPORT_5_mask) begin
- mem_flushall[mem_flushall_MPORT_5_addr] <= mem_flushall_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_6_en & mem_flushall_MPORT_6_mask) begin
- mem_flushall[mem_flushall_MPORT_6_addr] <= mem_flushall_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_7_en & mem_flushall_MPORT_7_mask) begin
- mem_flushall[mem_flushall_MPORT_7_addr] <= mem_flushall_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_8_en & mem_flushall_MPORT_8_mask) begin
- mem_flushall[mem_flushall_MPORT_8_addr] <= mem_flushall_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_9_en & mem_flushall_MPORT_9_mask) begin
- mem_flushall[mem_flushall_MPORT_9_addr] <= mem_flushall_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_10_en & mem_flushall_MPORT_10_mask) begin
- mem_flushall[mem_flushall_MPORT_10_addr] <= mem_flushall_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_11_en & mem_flushall_MPORT_11_mask) begin
- mem_flushall[mem_flushall_MPORT_11_addr] <= mem_flushall_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_12_en & mem_flushall_MPORT_12_mask) begin
- mem_flushall[mem_flushall_MPORT_12_addr] <= mem_flushall_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_13_en & mem_flushall_MPORT_13_mask) begin
- mem_flushall[mem_flushall_MPORT_13_addr] <= mem_flushall_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_14_en & mem_flushall_MPORT_14_mask) begin
- mem_flushall[mem_flushall_MPORT_14_addr] <= mem_flushall_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_15_en & mem_flushall_MPORT_15_mask) begin
- mem_flushall[mem_flushall_MPORT_15_addr] <= mem_flushall_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_16_en & mem_flushall_MPORT_16_mask) begin
- mem_flushall[mem_flushall_MPORT_16_addr] <= mem_flushall_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_17_en & mem_flushall_MPORT_17_mask) begin
- mem_flushall[mem_flushall_MPORT_17_addr] <= mem_flushall_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_18_en & mem_flushall_MPORT_18_mask) begin
- mem_flushall[mem_flushall_MPORT_18_addr] <= mem_flushall_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_19_en & mem_flushall_MPORT_19_mask) begin
- mem_flushall[mem_flushall_MPORT_19_addr] <= mem_flushall_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_20_en & mem_flushall_MPORT_20_mask) begin
- mem_flushall[mem_flushall_MPORT_20_addr] <= mem_flushall_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_21_en & mem_flushall_MPORT_21_mask) begin
- mem_flushall[mem_flushall_MPORT_21_addr] <= mem_flushall_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_22_en & mem_flushall_MPORT_22_mask) begin
- mem_flushall[mem_flushall_MPORT_22_addr] <= mem_flushall_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_23_en & mem_flushall_MPORT_23_mask) begin
- mem_flushall[mem_flushall_MPORT_23_addr] <= mem_flushall_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_24_en & mem_flushall_MPORT_24_mask) begin
- mem_flushall[mem_flushall_MPORT_24_addr] <= mem_flushall_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_25_en & mem_flushall_MPORT_25_mask) begin
- mem_flushall[mem_flushall_MPORT_25_addr] <= mem_flushall_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_26_en & mem_flushall_MPORT_26_mask) begin
- mem_flushall[mem_flushall_MPORT_26_addr] <= mem_flushall_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_flushall_MPORT_27_en & mem_flushall_MPORT_27_mask) begin
- mem_flushall[mem_flushall_MPORT_27_addr] <= mem_flushall_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_en & mem_sldst_MPORT_mask) begin
- mem_sldst[mem_sldst_MPORT_addr] <= mem_sldst_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_1_en & mem_sldst_MPORT_1_mask) begin
- mem_sldst[mem_sldst_MPORT_1_addr] <= mem_sldst_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_2_en & mem_sldst_MPORT_2_mask) begin
- mem_sldst[mem_sldst_MPORT_2_addr] <= mem_sldst_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_3_en & mem_sldst_MPORT_3_mask) begin
- mem_sldst[mem_sldst_MPORT_3_addr] <= mem_sldst_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_4_en & mem_sldst_MPORT_4_mask) begin
- mem_sldst[mem_sldst_MPORT_4_addr] <= mem_sldst_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_5_en & mem_sldst_MPORT_5_mask) begin
- mem_sldst[mem_sldst_MPORT_5_addr] <= mem_sldst_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_6_en & mem_sldst_MPORT_6_mask) begin
- mem_sldst[mem_sldst_MPORT_6_addr] <= mem_sldst_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_7_en & mem_sldst_MPORT_7_mask) begin
- mem_sldst[mem_sldst_MPORT_7_addr] <= mem_sldst_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_8_en & mem_sldst_MPORT_8_mask) begin
- mem_sldst[mem_sldst_MPORT_8_addr] <= mem_sldst_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_9_en & mem_sldst_MPORT_9_mask) begin
- mem_sldst[mem_sldst_MPORT_9_addr] <= mem_sldst_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_10_en & mem_sldst_MPORT_10_mask) begin
- mem_sldst[mem_sldst_MPORT_10_addr] <= mem_sldst_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_11_en & mem_sldst_MPORT_11_mask) begin
- mem_sldst[mem_sldst_MPORT_11_addr] <= mem_sldst_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_12_en & mem_sldst_MPORT_12_mask) begin
- mem_sldst[mem_sldst_MPORT_12_addr] <= mem_sldst_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_13_en & mem_sldst_MPORT_13_mask) begin
- mem_sldst[mem_sldst_MPORT_13_addr] <= mem_sldst_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_14_en & mem_sldst_MPORT_14_mask) begin
- mem_sldst[mem_sldst_MPORT_14_addr] <= mem_sldst_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_15_en & mem_sldst_MPORT_15_mask) begin
- mem_sldst[mem_sldst_MPORT_15_addr] <= mem_sldst_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_16_en & mem_sldst_MPORT_16_mask) begin
- mem_sldst[mem_sldst_MPORT_16_addr] <= mem_sldst_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_17_en & mem_sldst_MPORT_17_mask) begin
- mem_sldst[mem_sldst_MPORT_17_addr] <= mem_sldst_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_18_en & mem_sldst_MPORT_18_mask) begin
- mem_sldst[mem_sldst_MPORT_18_addr] <= mem_sldst_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_19_en & mem_sldst_MPORT_19_mask) begin
- mem_sldst[mem_sldst_MPORT_19_addr] <= mem_sldst_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_20_en & mem_sldst_MPORT_20_mask) begin
- mem_sldst[mem_sldst_MPORT_20_addr] <= mem_sldst_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_21_en & mem_sldst_MPORT_21_mask) begin
- mem_sldst[mem_sldst_MPORT_21_addr] <= mem_sldst_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_22_en & mem_sldst_MPORT_22_mask) begin
- mem_sldst[mem_sldst_MPORT_22_addr] <= mem_sldst_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_23_en & mem_sldst_MPORT_23_mask) begin
- mem_sldst[mem_sldst_MPORT_23_addr] <= mem_sldst_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_24_en & mem_sldst_MPORT_24_mask) begin
- mem_sldst[mem_sldst_MPORT_24_addr] <= mem_sldst_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_25_en & mem_sldst_MPORT_25_mask) begin
- mem_sldst[mem_sldst_MPORT_25_addr] <= mem_sldst_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_26_en & mem_sldst_MPORT_26_mask) begin
- mem_sldst[mem_sldst_MPORT_26_addr] <= mem_sldst_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_sldst_MPORT_27_en & mem_sldst_MPORT_27_mask) begin
- mem_sldst[mem_sldst_MPORT_27_addr] <= mem_sldst_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_en & mem_vldst_MPORT_mask) begin
- mem_vldst[mem_vldst_MPORT_addr] <= mem_vldst_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_1_en & mem_vldst_MPORT_1_mask) begin
- mem_vldst[mem_vldst_MPORT_1_addr] <= mem_vldst_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_2_en & mem_vldst_MPORT_2_mask) begin
- mem_vldst[mem_vldst_MPORT_2_addr] <= mem_vldst_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_3_en & mem_vldst_MPORT_3_mask) begin
- mem_vldst[mem_vldst_MPORT_3_addr] <= mem_vldst_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_4_en & mem_vldst_MPORT_4_mask) begin
- mem_vldst[mem_vldst_MPORT_4_addr] <= mem_vldst_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_5_en & mem_vldst_MPORT_5_mask) begin
- mem_vldst[mem_vldst_MPORT_5_addr] <= mem_vldst_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_6_en & mem_vldst_MPORT_6_mask) begin
- mem_vldst[mem_vldst_MPORT_6_addr] <= mem_vldst_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_7_en & mem_vldst_MPORT_7_mask) begin
- mem_vldst[mem_vldst_MPORT_7_addr] <= mem_vldst_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_8_en & mem_vldst_MPORT_8_mask) begin
- mem_vldst[mem_vldst_MPORT_8_addr] <= mem_vldst_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_9_en & mem_vldst_MPORT_9_mask) begin
- mem_vldst[mem_vldst_MPORT_9_addr] <= mem_vldst_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_10_en & mem_vldst_MPORT_10_mask) begin
- mem_vldst[mem_vldst_MPORT_10_addr] <= mem_vldst_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_11_en & mem_vldst_MPORT_11_mask) begin
- mem_vldst[mem_vldst_MPORT_11_addr] <= mem_vldst_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_12_en & mem_vldst_MPORT_12_mask) begin
- mem_vldst[mem_vldst_MPORT_12_addr] <= mem_vldst_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_13_en & mem_vldst_MPORT_13_mask) begin
- mem_vldst[mem_vldst_MPORT_13_addr] <= mem_vldst_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_14_en & mem_vldst_MPORT_14_mask) begin
- mem_vldst[mem_vldst_MPORT_14_addr] <= mem_vldst_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_15_en & mem_vldst_MPORT_15_mask) begin
- mem_vldst[mem_vldst_MPORT_15_addr] <= mem_vldst_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_16_en & mem_vldst_MPORT_16_mask) begin
- mem_vldst[mem_vldst_MPORT_16_addr] <= mem_vldst_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_17_en & mem_vldst_MPORT_17_mask) begin
- mem_vldst[mem_vldst_MPORT_17_addr] <= mem_vldst_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_18_en & mem_vldst_MPORT_18_mask) begin
- mem_vldst[mem_vldst_MPORT_18_addr] <= mem_vldst_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_19_en & mem_vldst_MPORT_19_mask) begin
- mem_vldst[mem_vldst_MPORT_19_addr] <= mem_vldst_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_20_en & mem_vldst_MPORT_20_mask) begin
- mem_vldst[mem_vldst_MPORT_20_addr] <= mem_vldst_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_21_en & mem_vldst_MPORT_21_mask) begin
- mem_vldst[mem_vldst_MPORT_21_addr] <= mem_vldst_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_22_en & mem_vldst_MPORT_22_mask) begin
- mem_vldst[mem_vldst_MPORT_22_addr] <= mem_vldst_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_23_en & mem_vldst_MPORT_23_mask) begin
- mem_vldst[mem_vldst_MPORT_23_addr] <= mem_vldst_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_24_en & mem_vldst_MPORT_24_mask) begin
- mem_vldst[mem_vldst_MPORT_24_addr] <= mem_vldst_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_25_en & mem_vldst_MPORT_25_mask) begin
- mem_vldst[mem_vldst_MPORT_25_addr] <= mem_vldst_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_26_en & mem_vldst_MPORT_26_mask) begin
- mem_vldst[mem_vldst_MPORT_26_addr] <= mem_vldst_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_vldst_MPORT_27_en & mem_vldst_MPORT_27_mask) begin
- mem_vldst[mem_vldst_MPORT_27_addr] <= mem_vldst_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_en & mem_suncd_MPORT_mask) begin
- mem_suncd[mem_suncd_MPORT_addr] <= mem_suncd_MPORT_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_1_en & mem_suncd_MPORT_1_mask) begin
- mem_suncd[mem_suncd_MPORT_1_addr] <= mem_suncd_MPORT_1_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_2_en & mem_suncd_MPORT_2_mask) begin
- mem_suncd[mem_suncd_MPORT_2_addr] <= mem_suncd_MPORT_2_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_3_en & mem_suncd_MPORT_3_mask) begin
- mem_suncd[mem_suncd_MPORT_3_addr] <= mem_suncd_MPORT_3_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_4_en & mem_suncd_MPORT_4_mask) begin
- mem_suncd[mem_suncd_MPORT_4_addr] <= mem_suncd_MPORT_4_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_5_en & mem_suncd_MPORT_5_mask) begin
- mem_suncd[mem_suncd_MPORT_5_addr] <= mem_suncd_MPORT_5_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_6_en & mem_suncd_MPORT_6_mask) begin
- mem_suncd[mem_suncd_MPORT_6_addr] <= mem_suncd_MPORT_6_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_7_en & mem_suncd_MPORT_7_mask) begin
- mem_suncd[mem_suncd_MPORT_7_addr] <= mem_suncd_MPORT_7_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_8_en & mem_suncd_MPORT_8_mask) begin
- mem_suncd[mem_suncd_MPORT_8_addr] <= mem_suncd_MPORT_8_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_9_en & mem_suncd_MPORT_9_mask) begin
- mem_suncd[mem_suncd_MPORT_9_addr] <= mem_suncd_MPORT_9_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_10_en & mem_suncd_MPORT_10_mask) begin
- mem_suncd[mem_suncd_MPORT_10_addr] <= mem_suncd_MPORT_10_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_11_en & mem_suncd_MPORT_11_mask) begin
- mem_suncd[mem_suncd_MPORT_11_addr] <= mem_suncd_MPORT_11_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_12_en & mem_suncd_MPORT_12_mask) begin
- mem_suncd[mem_suncd_MPORT_12_addr] <= mem_suncd_MPORT_12_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_13_en & mem_suncd_MPORT_13_mask) begin
- mem_suncd[mem_suncd_MPORT_13_addr] <= mem_suncd_MPORT_13_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_14_en & mem_suncd_MPORT_14_mask) begin
- mem_suncd[mem_suncd_MPORT_14_addr] <= mem_suncd_MPORT_14_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_15_en & mem_suncd_MPORT_15_mask) begin
- mem_suncd[mem_suncd_MPORT_15_addr] <= mem_suncd_MPORT_15_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_16_en & mem_suncd_MPORT_16_mask) begin
- mem_suncd[mem_suncd_MPORT_16_addr] <= mem_suncd_MPORT_16_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_17_en & mem_suncd_MPORT_17_mask) begin
- mem_suncd[mem_suncd_MPORT_17_addr] <= mem_suncd_MPORT_17_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_18_en & mem_suncd_MPORT_18_mask) begin
- mem_suncd[mem_suncd_MPORT_18_addr] <= mem_suncd_MPORT_18_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_19_en & mem_suncd_MPORT_19_mask) begin
- mem_suncd[mem_suncd_MPORT_19_addr] <= mem_suncd_MPORT_19_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_20_en & mem_suncd_MPORT_20_mask) begin
- mem_suncd[mem_suncd_MPORT_20_addr] <= mem_suncd_MPORT_20_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_21_en & mem_suncd_MPORT_21_mask) begin
- mem_suncd[mem_suncd_MPORT_21_addr] <= mem_suncd_MPORT_21_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_22_en & mem_suncd_MPORT_22_mask) begin
- mem_suncd[mem_suncd_MPORT_22_addr] <= mem_suncd_MPORT_22_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_23_en & mem_suncd_MPORT_23_mask) begin
- mem_suncd[mem_suncd_MPORT_23_addr] <= mem_suncd_MPORT_23_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_24_en & mem_suncd_MPORT_24_mask) begin
- mem_suncd[mem_suncd_MPORT_24_addr] <= mem_suncd_MPORT_24_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_25_en & mem_suncd_MPORT_25_mask) begin
- mem_suncd[mem_suncd_MPORT_25_addr] <= mem_suncd_MPORT_25_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_26_en & mem_suncd_MPORT_26_mask) begin
- mem_suncd[mem_suncd_MPORT_26_addr] <= mem_suncd_MPORT_26_data; // @[Fifo4.scala 73:16]
- end
- if (mem_suncd_MPORT_27_en & mem_suncd_MPORT_27_mask) begin
- mem_suncd[mem_suncd_MPORT_27_addr] <= mem_suncd_MPORT_27_data; // @[Fifo4.scala 73:16]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(mcount <= 4'h7)) begin
- $fatal; // @[Fifo4.scala 187:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(mcount <= 4'h7)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Fifo4.scala:187 assert(mcount <= m.U)\n"); // @[Fifo4.scala 187:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4.scala 96:17]
- in0pos <= 3'h0; // @[Fifo4.scala 97:12]
- end else if (ivalid) begin // @[Fifo4.scala 76:23]
- in0pos <= in0pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4.scala 96:17]
- in1pos <= 3'h1; // @[Fifo4.scala 98:12]
- end else if (ivalid) begin // @[Fifo4.scala 77:23]
- in1pos <= in1pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4.scala 96:17]
- in2pos <= 3'h2; // @[Fifo4.scala 99:12]
- end else if (ivalid) begin // @[Fifo4.scala 78:23]
- in2pos <= in2pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4.scala 96:17]
- in3pos <= 3'h3; // @[Fifo4.scala 100:12]
- end else if (ivalid) begin // @[Fifo4.scala 79:23]
- in3pos <= in3pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4.scala 103:17]
- outpos <= 3'h0; // @[Fifo4.scala 104:12]
- end else if (ovalid) begin // @[Fifo4.scala 80:23]
- outpos <= outpos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4.scala 110:27]
- mcount <= 4'h0; // @[Fifo4.scala 111:12]
- end else if (ivalid | ovalid) begin // @[Fifo4.scala 81:23]
- mcount <= _mcount_T_3;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
- _RAND_1 = {1{`RANDOM}};
- _RAND_3 = {1{`RANDOM}};
- _RAND_5 = {1{`RANDOM}};
- _RAND_7 = {1{`RANDOM}};
- _RAND_9 = {1{`RANDOM}};
- _RAND_11 = {1{`RANDOM}};
- _RAND_13 = {1{`RANDOM}};
- _RAND_15 = {1{`RANDOM}};
- _RAND_17 = {1{`RANDOM}};
- _RAND_19 = {1{`RANDOM}};
- _RAND_21 = {1{`RANDOM}};
- _RAND_23 = {1{`RANDOM}};
- _RAND_25 = {1{`RANDOM}};
- _RAND_27 = {1{`RANDOM}};
-`endif // RANDOMIZE_GARBAGE_ASSIGN
-`ifdef RANDOMIZE_MEM_INIT
- _RAND_0 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_addr[initvar] = _RAND_0[31:0];
- _RAND_2 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_adrx[initvar] = _RAND_2[31:0];
- _RAND_4 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_data[initvar] = _RAND_4[31:0];
- _RAND_6 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_index[initvar] = _RAND_6[4:0];
- _RAND_8 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_size[initvar] = _RAND_8[5:0];
- _RAND_10 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_write[initvar] = _RAND_10[0:0];
- _RAND_12 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_sext[initvar] = _RAND_12[0:0];
- _RAND_14 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_iload[initvar] = _RAND_14[0:0];
- _RAND_16 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_fencei[initvar] = _RAND_16[0:0];
- _RAND_18 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_flushat[initvar] = _RAND_18[0:0];
- _RAND_20 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_flushall[initvar] = _RAND_20[0:0];
- _RAND_22 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_sldst[initvar] = _RAND_22[0:0];
- _RAND_24 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_vldst[initvar] = _RAND_24[0:0];
- _RAND_26 = {1{`RANDOM}};
- for (initvar = 0; initvar < 7; initvar = initvar+1)
- mem_suncd[initvar] = _RAND_26[0:0];
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- _RAND_28 = {1{`RANDOM}};
- in0pos = _RAND_28[2:0];
- _RAND_29 = {1{`RANDOM}};
- in1pos = _RAND_29[2:0];
- _RAND_30 = {1{`RANDOM}};
- in2pos = _RAND_30[2:0];
- _RAND_31 = {1{`RANDOM}};
- in3pos = _RAND_31[2:0];
- _RAND_32 = {1{`RANDOM}};
- outpos = _RAND_32[2:0];
- _RAND_33 = {1{`RANDOM}};
- mcount = _RAND_33[3:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- in0pos = 3'h0;
- end
- if (reset) begin
- in1pos = 3'h1;
- end
- if (reset) begin
- in2pos = 3'h2;
- end
- if (reset) begin
- in3pos = 3'h3;
- end
- if (reset) begin
- outpos = 3'h0;
- end
- if (reset) begin
- mcount = 4'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Slice_2(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input [31:0] io_in_bits_addr,
- input [4:0] io_in_bits_index,
- input [5:0] io_in_bits_size,
- input io_in_bits_sext,
- input io_in_bits_iload,
- input io_in_bits_sldst,
- input io_in_bits_suncd,
- output io_out_valid,
- output [31:0] io_out_bits_addr,
- output [4:0] io_out_bits_index,
- output [5:0] io_out_bits_size,
- output io_out_bits_sext,
- output io_out_bits_iload,
- output io_out_bits_sldst,
- output io_out_bits_suncd
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
-`endif // RANDOMIZE_REG_INIT
- reg [1:0] ipos; // @[Slice.scala 38:21]
- reg [1:0] opos; // @[Slice.scala 39:21]
- reg [31:0] mem_0_addr; // @[Slice.scala 41:16]
- reg [4:0] mem_0_index; // @[Slice.scala 41:16]
- reg [5:0] mem_0_size; // @[Slice.scala 41:16]
- reg mem_0_sext; // @[Slice.scala 41:16]
- reg mem_0_iload; // @[Slice.scala 41:16]
- reg mem_0_sldst; // @[Slice.scala 41:16]
- reg mem_0_suncd; // @[Slice.scala 41:16]
- reg [31:0] mem_1_addr; // @[Slice.scala 41:16]
- reg [4:0] mem_1_index; // @[Slice.scala 41:16]
- reg [5:0] mem_1_size; // @[Slice.scala 41:16]
- reg mem_1_sext; // @[Slice.scala 41:16]
- reg mem_1_iload; // @[Slice.scala 41:16]
- reg mem_1_sldst; // @[Slice.scala 41:16]
- reg mem_1_suncd; // @[Slice.scala 41:16]
- wire empty = ipos == opos; // @[Slice.scala 43:20]
- wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 45:28]
- wire [1:0] _ipos_T_1 = ipos + 2'h1; // @[Slice.scala 49:18]
- wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 53:18]
- wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 61:36]
- wire _io_in_ready_T = ~full; // @[Slice.scala 63:22]
- wire _T_3 = ivalid & ~io_out_valid; // @[Slice.scala 72:18]
- wire _T_5 = ivalid & io_out_valid; // @[Slice.scala 73:18]
- wire _T_7 = ivalid & io_out_valid & _io_in_ready_T; // @[Slice.scala 73:28]
- wire _T_8 = ivalid & ~io_out_valid & empty | _T_7; // @[Slice.scala 72:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 78:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 77:39]
- assign io_in_ready = 1'h1; // @[Slice.scala 63:28]
- assign io_out_valid = ~empty; // @[Slice.scala 102:21]
- assign io_out_bits_addr = mem_0_addr; // @[Slice.scala 103:18]
- assign io_out_bits_index = mem_0_index; // @[Slice.scala 103:18]
- assign io_out_bits_size = mem_0_size; // @[Slice.scala 103:18]
- assign io_out_bits_sext = mem_0_sext; // @[Slice.scala 103:18]
- assign io_out_bits_iload = mem_0_iload; // @[Slice.scala 103:18]
- assign io_out_bits_sldst = mem_0_sldst; // @[Slice.scala 103:18]
- assign io_out_bits_suncd = mem_0_suncd; // @[Slice.scala 103:18]
- always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_addr <= io_in_bits_addr; // @[Slice.scala 74:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 68:27]
- mem_0_addr <= mem_1_addr; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_index <= io_in_bits_index; // @[Slice.scala 74:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 68:27]
- mem_0_index <= mem_1_index; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_size <= io_in_bits_size; // @[Slice.scala 74:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 68:27]
- mem_0_size <= mem_1_size; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_sext <= io_in_bits_sext; // @[Slice.scala 74:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 68:27]
- mem_0_sext <= mem_1_sext; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_iload <= io_in_bits_iload; // @[Slice.scala 74:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 68:27]
- mem_0_iload <= mem_1_iload; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_sldst <= io_in_bits_sldst; // @[Slice.scala 74:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 68:27]
- mem_0_sldst <= mem_1_sldst; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_suncd <= io_in_bits_suncd; // @[Slice.scala 74:14]
- end else if (io_out_valid & full) begin // @[Slice.scala 68:27]
- mem_0_suncd <= mem_1_suncd; // @[Slice.scala 69:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_addr <= io_in_bits_addr; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_index <= io_in_bits_index; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_size <= io_in_bits_size; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_sext <= io_in_bits_sext; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_iload <= io_in_bits_iload; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_sldst <= io_in_bits_sldst; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_suncd <= io_in_bits_suncd; // @[Slice.scala 79:14]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 48:17]
- ipos <= 2'h0; // @[Slice.scala 49:10]
- end else if (ivalid) begin // @[Slice.scala 38:21]
- ipos <= _ipos_T_1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 52:17]
- opos <= 2'h0; // @[Slice.scala 53:10]
- end else if (io_out_valid) begin // @[Slice.scala 39:21]
- opos <= _opos_T_1;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- ipos = _RAND_0[1:0];
- _RAND_1 = {1{`RANDOM}};
- opos = _RAND_1[1:0];
- _RAND_2 = {1{`RANDOM}};
- mem_0_addr = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- mem_0_index = _RAND_3[4:0];
- _RAND_4 = {1{`RANDOM}};
- mem_0_size = _RAND_4[5:0];
- _RAND_5 = {1{`RANDOM}};
- mem_0_sext = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- mem_0_iload = _RAND_6[0:0];
- _RAND_7 = {1{`RANDOM}};
- mem_0_sldst = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- mem_0_suncd = _RAND_8[0:0];
- _RAND_9 = {1{`RANDOM}};
- mem_1_addr = _RAND_9[31:0];
- _RAND_10 = {1{`RANDOM}};
- mem_1_index = _RAND_10[4:0];
- _RAND_11 = {1{`RANDOM}};
- mem_1_size = _RAND_11[5:0];
- _RAND_12 = {1{`RANDOM}};
- mem_1_sext = _RAND_12[0:0];
- _RAND_13 = {1{`RANDOM}};
- mem_1_iload = _RAND_13[0:0];
- _RAND_14 = {1{`RANDOM}};
- mem_1_sldst = _RAND_14[0:0];
- _RAND_15 = {1{`RANDOM}};
- mem_1_suncd = _RAND_15[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- ipos = 2'h0;
- end
- if (reset) begin
- opos = 2'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Lsu(
- input clock,
- input reset,
- input io_req_0_valid,
- output io_req_0_ready,
- input [4:0] io_req_0_addr,
- input [11:0] io_req_0_op,
- input io_req_1_valid,
- output io_req_1_ready,
- input [4:0] io_req_1_addr,
- input [11:0] io_req_1_op,
- input io_req_2_valid,
- output io_req_2_ready,
- input [4:0] io_req_2_addr,
- input [11:0] io_req_2_op,
- input io_req_3_valid,
- output io_req_3_ready,
- input [4:0] io_req_3_addr,
- input [11:0] io_req_3_op,
- input [31:0] io_busPort_addr_0,
- input [31:0] io_busPort_addr_1,
- input [31:0] io_busPort_addr_2,
- input [31:0] io_busPort_addr_3,
- input [31:0] io_busPort_data_0,
- input [31:0] io_busPort_data_1,
- input [31:0] io_busPort_data_2,
- input [31:0] io_busPort_data_3,
- output io_rd_valid,
- output [4:0] io_rd_addr,
- output [31:0] io_rd_data,
- output io_dbus_valid,
- input io_dbus_ready,
- output io_dbus_write,
- output [31:0] io_dbus_addr,
- output [31:0] io_dbus_adrx,
- output [5:0] io_dbus_size,
- output [255:0] io_dbus_wdata,
- output [31:0] io_dbus_wmask,
- input [255:0] io_dbus_rdata,
- output io_flush_valid,
- input io_flush_ready,
- output io_flush_all,
- output io_flush_fencei,
- output io_ubus_valid,
- input io_ubus_ready,
- output io_ubus_write,
- output [31:0] io_ubus_addr,
- output [255:0] io_ubus_wdata,
- output [31:0] io_ubus_wmask,
- input [255:0] io_ubus_rdata,
- output io_vldst
-);
- wire ctrl_clock; // @[Fifo4.scala 22:11]
- wire ctrl_reset; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_ready; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_valid; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_0_valid; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_in_bits_0_bits_addr; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_in_bits_0_bits_adrx; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_in_bits_0_bits_data; // @[Fifo4.scala 22:11]
- wire [4:0] ctrl_io_in_bits_0_bits_index; // @[Fifo4.scala 22:11]
- wire [5:0] ctrl_io_in_bits_0_bits_size; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_0_bits_write; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_0_bits_sext; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_0_bits_iload; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_0_bits_fencei; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_0_bits_flushat; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_0_bits_flushall; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_0_bits_sldst; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_0_bits_vldst; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_0_bits_suncd; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_1_valid; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_in_bits_1_bits_addr; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_in_bits_1_bits_adrx; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_in_bits_1_bits_data; // @[Fifo4.scala 22:11]
- wire [4:0] ctrl_io_in_bits_1_bits_index; // @[Fifo4.scala 22:11]
- wire [5:0] ctrl_io_in_bits_1_bits_size; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_1_bits_write; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_1_bits_sext; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_1_bits_iload; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_1_bits_fencei; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_1_bits_flushat; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_1_bits_flushall; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_1_bits_sldst; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_1_bits_vldst; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_1_bits_suncd; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_2_valid; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_in_bits_2_bits_addr; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_in_bits_2_bits_adrx; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_in_bits_2_bits_data; // @[Fifo4.scala 22:11]
- wire [4:0] ctrl_io_in_bits_2_bits_index; // @[Fifo4.scala 22:11]
- wire [5:0] ctrl_io_in_bits_2_bits_size; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_2_bits_write; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_2_bits_sext; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_2_bits_iload; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_2_bits_fencei; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_2_bits_flushat; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_2_bits_flushall; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_2_bits_sldst; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_2_bits_vldst; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_2_bits_suncd; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_3_valid; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_in_bits_3_bits_addr; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_in_bits_3_bits_adrx; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_in_bits_3_bits_data; // @[Fifo4.scala 22:11]
- wire [4:0] ctrl_io_in_bits_3_bits_index; // @[Fifo4.scala 22:11]
- wire [5:0] ctrl_io_in_bits_3_bits_size; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_3_bits_write; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_3_bits_sext; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_3_bits_iload; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_3_bits_fencei; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_3_bits_flushat; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_3_bits_flushall; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_3_bits_sldst; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_3_bits_vldst; // @[Fifo4.scala 22:11]
- wire ctrl_io_in_bits_3_bits_suncd; // @[Fifo4.scala 22:11]
- wire ctrl_io_out_ready; // @[Fifo4.scala 22:11]
- wire ctrl_io_out_valid; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_out_bits_addr; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_out_bits_adrx; // @[Fifo4.scala 22:11]
- wire [31:0] ctrl_io_out_bits_data; // @[Fifo4.scala 22:11]
- wire [4:0] ctrl_io_out_bits_index; // @[Fifo4.scala 22:11]
- wire [5:0] ctrl_io_out_bits_size; // @[Fifo4.scala 22:11]
- wire ctrl_io_out_bits_write; // @[Fifo4.scala 22:11]
- wire ctrl_io_out_bits_sext; // @[Fifo4.scala 22:11]
- wire ctrl_io_out_bits_iload; // @[Fifo4.scala 22:11]
- wire ctrl_io_out_bits_fencei; // @[Fifo4.scala 22:11]
- wire ctrl_io_out_bits_flushat; // @[Fifo4.scala 22:11]
- wire ctrl_io_out_bits_flushall; // @[Fifo4.scala 22:11]
- wire ctrl_io_out_bits_sldst; // @[Fifo4.scala 22:11]
- wire ctrl_io_out_bits_vldst; // @[Fifo4.scala 22:11]
- wire ctrl_io_out_bits_suncd; // @[Fifo4.scala 22:11]
- wire [3:0] ctrl_io_count; // @[Fifo4.scala 22:11]
- wire data_clock; // @[Slice.scala 23:11]
- wire data_reset; // @[Slice.scala 23:11]
- wire data_io_in_ready; // @[Slice.scala 23:11]
- wire data_io_in_valid; // @[Slice.scala 23:11]
- wire [31:0] data_io_in_bits_addr; // @[Slice.scala 23:11]
- wire [4:0] data_io_in_bits_index; // @[Slice.scala 23:11]
- wire [5:0] data_io_in_bits_size; // @[Slice.scala 23:11]
- wire data_io_in_bits_sext; // @[Slice.scala 23:11]
- wire data_io_in_bits_iload; // @[Slice.scala 23:11]
- wire data_io_in_bits_sldst; // @[Slice.scala 23:11]
- wire data_io_in_bits_suncd; // @[Slice.scala 23:11]
- wire data_io_out_valid; // @[Slice.scala 23:11]
- wire [31:0] data_io_out_bits_addr; // @[Slice.scala 23:11]
- wire [4:0] data_io_out_bits_index; // @[Slice.scala 23:11]
- wire [5:0] data_io_out_bits_size; // @[Slice.scala 23:11]
- wire data_io_out_bits_sext; // @[Slice.scala 23:11]
- wire data_io_out_bits_iload; // @[Slice.scala 23:11]
- wire data_io_out_bits_sldst; // @[Slice.scala 23:11]
- wire data_io_out_bits_suncd; // @[Slice.scala 23:11]
- wire _ctrlready_T = ctrl_io_count <= 4'h4; // @[Lsu.scala 120:37]
- wire _ctrlready_T_1 = ctrl_io_count <= 4'h5; // @[Lsu.scala 121:37]
- wire _ctrlready_T_2 = ctrl_io_count <= 4'h6; // @[Lsu.scala 122:37]
- wire _ctrlready_T_3 = ctrl_io_count <= 4'h7; // @[Lsu.scala 123:37]
- wire [3:0] ctrlready = {_ctrlready_T,_ctrlready_T_1,_ctrlready_T_2,_ctrlready_T_3}; // @[Cat.scala 31:58]
- wire _ctrl_io_in_valid_T_1 = io_req_0_valid | io_req_1_valid | io_req_2_valid; // @[Lsu.scala 136:58]
- wire uncached = io_busPort_addr_0[31]; // @[Lsu.scala 140:38]
- wire opstore = io_req_0_op[7] | io_req_0_op[6] | io_req_0_op[5]; // @[Lsu.scala 142:64]
- wire opiload = io_req_0_op[2] | io_req_0_op[1] | io_req_0_op[0] | io_req_0_op[4] | io_req_0_op[3]; // @[Lsu.scala 143:113]
- wire opsldst = opstore | opiload; // @[Lsu.scala 148:27]
- wire opvldst = io_req_0_op[11]; // @[Lsu.scala 149:31]
- wire _opsize_T_2 = io_req_0_op[2] | io_req_0_op[7]; // @[Lsu.scala 151:43]
- wire _opsize_T_7 = io_req_0_op[1] | io_req_0_op[4] | io_req_0_op[6]; // @[Lsu.scala 152:68]
- wire _opsize_T_12 = io_req_0_op[0] | io_req_0_op[3] | io_req_0_op[5]; // @[Lsu.scala 153:68]
- wire [2:0] opsize = {_opsize_T_2,_opsize_T_7,_opsize_T_12}; // @[Cat.scala 31:58]
- wire uncached_1 = io_busPort_addr_1[31]; // @[Lsu.scala 140:38]
- wire opstore_1 = io_req_1_op[7] | io_req_1_op[6] | io_req_1_op[5]; // @[Lsu.scala 142:64]
- wire opiload_1 = io_req_1_op[2] | io_req_1_op[1] | io_req_1_op[0] | io_req_1_op[4] | io_req_1_op[3]; // @[Lsu.scala 143:113]
- wire opsldst_1 = opstore_1 | opiload_1; // @[Lsu.scala 148:27]
- wire opvldst_1 = io_req_1_op[11]; // @[Lsu.scala 149:31]
- wire _opsize_T_15 = io_req_1_op[2] | io_req_1_op[7]; // @[Lsu.scala 151:43]
- wire _opsize_T_20 = io_req_1_op[1] | io_req_1_op[4] | io_req_1_op[6]; // @[Lsu.scala 152:68]
- wire _opsize_T_25 = io_req_1_op[0] | io_req_1_op[3] | io_req_1_op[5]; // @[Lsu.scala 153:68]
- wire [2:0] opsize_1 = {_opsize_T_15,_opsize_T_20,_opsize_T_25}; // @[Cat.scala 31:58]
- wire uncached_2 = io_busPort_addr_2[31]; // @[Lsu.scala 140:38]
- wire opstore_2 = io_req_2_op[7] | io_req_2_op[6] | io_req_2_op[5]; // @[Lsu.scala 142:64]
- wire opiload_2 = io_req_2_op[2] | io_req_2_op[1] | io_req_2_op[0] | io_req_2_op[4] | io_req_2_op[3]; // @[Lsu.scala 143:113]
- wire opsldst_2 = opstore_2 | opiload_2; // @[Lsu.scala 148:27]
- wire opvldst_2 = io_req_2_op[11]; // @[Lsu.scala 149:31]
- wire _opsize_T_28 = io_req_2_op[2] | io_req_2_op[7]; // @[Lsu.scala 151:43]
- wire _opsize_T_33 = io_req_2_op[1] | io_req_2_op[4] | io_req_2_op[6]; // @[Lsu.scala 152:68]
- wire _opsize_T_38 = io_req_2_op[0] | io_req_2_op[3] | io_req_2_op[5]; // @[Lsu.scala 153:68]
- wire [2:0] opsize_2 = {_opsize_T_28,_opsize_T_33,_opsize_T_38}; // @[Cat.scala 31:58]
- wire uncached_3 = io_busPort_addr_3[31]; // @[Lsu.scala 140:38]
- wire opstore_3 = io_req_3_op[7] | io_req_3_op[6] | io_req_3_op[5]; // @[Lsu.scala 142:64]
- wire opiload_3 = io_req_3_op[2] | io_req_3_op[1] | io_req_3_op[0] | io_req_3_op[4] | io_req_3_op[3]; // @[Lsu.scala 143:113]
- wire opsldst_3 = opstore_3 | opiload_3; // @[Lsu.scala 148:27]
- wire opvldst_3 = io_req_3_op[11]; // @[Lsu.scala 149:31]
- wire _opsize_T_41 = io_req_3_op[2] | io_req_3_op[7]; // @[Lsu.scala 151:43]
- wire _opsize_T_46 = io_req_3_op[1] | io_req_3_op[4] | io_req_3_op[6]; // @[Lsu.scala 152:68]
- wire _opsize_T_51 = io_req_3_op[0] | io_req_3_op[3] | io_req_3_op[5]; // @[Lsu.scala 153:68]
- wire [2:0] opsize_3 = {_opsize_T_41,_opsize_T_46,_opsize_T_51}; // @[Cat.scala 31:58]
- wire [1:0] wsel = ctrl_io_out_bits_addr[1:0]; // @[Lsu.scala 175:35]
- wire _wdataS_T = wsel == 2'h0; // @[Lsu.scala 178:16]
- wire [31:0] _wdataS_T_1 = ctrl_io_out_bits_data; // @[Lsu.scala 178:28]
- wire [31:0] _wdataS_T_2 = _wdataS_T ? _wdataS_T_1 : 32'h0; // @[Library.scala 22:8]
- wire _wdataS_T_3 = wsel == 2'h1; // @[Lsu.scala 179:16]
- wire [31:0] _wdataS_T_8 = {ctrl_io_out_bits_data[23:16],ctrl_io_out_bits_data[15:8],ctrl_io_out_bits_data[7:0],
- ctrl_io_out_bits_data[31:24]}; // @[Cat.scala 31:58]
- wire [31:0] _wdataS_T_9 = _wdataS_T_3 ? _wdataS_T_8 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _wdataS_T_10 = _wdataS_T_2 | _wdataS_T_9; // @[Lsu.scala 178:36]
- wire _wdataS_T_11 = wsel == 2'h2; // @[Lsu.scala 180:16]
- wire [31:0] _wdataS_T_16 = {ctrl_io_out_bits_data[15:8],ctrl_io_out_bits_data[7:0],ctrl_io_out_bits_data[31:24],
- ctrl_io_out_bits_data[23:16]}; // @[Cat.scala 31:58]
- wire [31:0] _wdataS_T_17 = _wdataS_T_11 ? _wdataS_T_16 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _wdataS_T_18 = _wdataS_T_10 | _wdataS_T_17; // @[Lsu.scala 179:75]
- wire _wdataS_T_19 = wsel == 2'h3; // @[Lsu.scala 181:16]
- wire [31:0] _wdataS_T_24 = {ctrl_io_out_bits_data[7:0],ctrl_io_out_bits_data[31:24],ctrl_io_out_bits_data[23:16],
- ctrl_io_out_bits_data[15:8]}; // @[Cat.scala 31:58]
- wire [31:0] _wdataS_T_25 = _wdataS_T_19 ? _wdataS_T_24 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] wdataS = _wdataS_T_18 | _wdataS_T_25; // @[Lsu.scala 180:75]
- wire [5:0] _wmaskT_T_2 = 6'h20 - ctrl_io_out_bits_size; // @[Lsu.scala 183:46]
- wire [31:0] wmaskT = 32'hffffffff >> _wmaskT_T_2; // @[Lsu.scala 183:33]
- wire [62:0] _GEN_34 = {{31'd0}, wmaskT}; // @[Lsu.scala 184:24]
- wire [62:0] _wmaskS_T_1 = _GEN_34 << ctrl_io_out_bits_addr[4:0]; // @[Lsu.scala 184:24]
- wire [5:0] _GEN_0 = {{1'd0}, ctrl_io_out_bits_addr[4:0]}; // @[Lsu.scala 185:41]
- wire [5:0] _wmaskS_T_4 = 6'h20 - _GEN_0; // @[Lsu.scala 185:41]
- wire [31:0] _wmaskS_T_5 = wmaskT >> _wmaskS_T_4; // @[Lsu.scala 185:24]
- wire [62:0] _GEN_1 = {{31'd0}, _wmaskS_T_5}; // @[Lsu.scala 184:63]
- wire [62:0] wmaskS = _wmaskS_T_1 | _GEN_1; // @[Lsu.scala 184:63]
- wire [127:0] wdata_lo = {wdataS,wdataS,wdataS,wdataS}; // @[Cat.scala 31:58]
- wire _T_4 = ~reset; // @[Lsu.scala 210:9]
- wire _ctrl_io_out_ready_T_1 = io_dbus_valid & io_dbus_ready; // @[Lsu.scala 231:38]
- wire _ctrl_io_out_ready_T_2 = io_flush_valid & io_flush_ready | _ctrl_io_out_ready_T_1; // @[Lsu.scala 230:57]
- wire _ctrl_io_out_ready_T_3 = io_ubus_valid & io_ubus_ready; // @[Lsu.scala 232:38]
- wire _ctrl_io_out_ready_T_4 = _ctrl_io_out_ready_T_2 | _ctrl_io_out_ready_T_3; // @[Lsu.scala 231:55]
- wire _ctrl_io_out_ready_T_5 = ctrl_io_out_bits_vldst & io_dbus_ready; // @[Lsu.scala 233:47]
- wire _data_io_in_valid_T_5 = _ctrl_io_out_ready_T_3 & ~io_ubus_write; // @[Lsu.scala 240:54]
- wire [4:0] rsel = data_io_out_bits_addr[4:0]; // @[Lsu.scala 259:36]
- wire [255:0] _rdata_T = data_io_out_bits_sldst ? io_dbus_rdata : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _rdata_T_1 = data_io_out_bits_suncd ? io_ubus_rdata : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _rdata_T_2 = _rdata_T | _rdata_T_1; // @[Lsu.scala 292:71]
- wire [31:0] rdata_rdata = {_rdata_T_2[31:24],_rdata_T_2[23:16],_rdata_T_2[15:8],_rdata_T_2[7:0]}; // @[Cat.scala 31:58]
- wire _rdata_sizeMask_T_2 = data_io_out_bits_size == 6'h2; // @[Lsu.scala 275:32]
- wire [31:0] _rdata_sizeMask_T_3 = data_io_out_bits_size == 6'h2 ? 32'hffff : 32'hff; // @[Lsu.scala 275:25]
- wire [31:0] rdata_sizeMask = data_io_out_bits_size == 6'h4 ? 32'hffffffff : _rdata_sizeMask_T_3; // @[Lsu.scala 274:25]
- wire [31:0] _rdata_signExtend_T_3 = rdata_rdata[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_6 = rdata_rdata[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_7 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_3 : _rdata_signExtend_T_6; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend = data_io_out_bits_sext ? _rdata_signExtend_T_7 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T = rsel == 5'h0; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_1 = rdata_rdata & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_2 = _rdata_sdata_T_1 | rdata_signExtend; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata = _rdata_sdata_T ? _rdata_sdata_T_2 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _rdata_T_3 = {{224'd0}, rdata_sdata}; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_1 = {_rdata_T_2[39:32],_rdata_T_2[31:24],_rdata_T_2[23:16],_rdata_T_2[15:8]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_11 = rdata_rdata_1[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_14 = rdata_rdata_1[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_15 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_11 : _rdata_signExtend_T_14; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_1 = data_io_out_bits_sext ? _rdata_signExtend_T_15 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_3 = rsel == 5'h1; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_4 = rdata_rdata_1 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_5 = _rdata_sdata_T_4 | rdata_signExtend_1; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_1 = _rdata_sdata_T_3 ? _rdata_sdata_T_5 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_2 = {{224'd0}, rdata_sdata_1}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_4 = _rdata_T_3 | _GEN_2; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_2 = {_rdata_T_2[47:40],_rdata_T_2[39:32],_rdata_T_2[31:24],_rdata_T_2[23:16]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_19 = rdata_rdata_2[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_22 = rdata_rdata_2[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_23 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_19 : _rdata_signExtend_T_22; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_2 = data_io_out_bits_sext ? _rdata_signExtend_T_23 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_6 = rsel == 5'h2; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_7 = rdata_rdata_2 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_8 = _rdata_sdata_T_7 | rdata_signExtend_2; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_2 = _rdata_sdata_T_6 ? _rdata_sdata_T_8 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_3 = {{224'd0}, rdata_sdata_2}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_5 = _rdata_T_4 | _GEN_3; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_3 = {_rdata_T_2[55:48],_rdata_T_2[47:40],_rdata_T_2[39:32],_rdata_T_2[31:24]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_27 = rdata_rdata_3[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_30 = rdata_rdata_3[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_31 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_27 : _rdata_signExtend_T_30; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_3 = data_io_out_bits_sext ? _rdata_signExtend_T_31 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_9 = rsel == 5'h3; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_10 = rdata_rdata_3 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_11 = _rdata_sdata_T_10 | rdata_signExtend_3; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_3 = _rdata_sdata_T_9 ? _rdata_sdata_T_11 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_4 = {{224'd0}, rdata_sdata_3}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_6 = _rdata_T_5 | _GEN_4; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_4 = {_rdata_T_2[63:56],_rdata_T_2[55:48],_rdata_T_2[47:40],_rdata_T_2[39:32]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_35 = rdata_rdata_4[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_38 = rdata_rdata_4[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_39 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_35 : _rdata_signExtend_T_38; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_4 = data_io_out_bits_sext ? _rdata_signExtend_T_39 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_12 = rsel == 5'h4; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_13 = rdata_rdata_4 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_14 = _rdata_sdata_T_13 | rdata_signExtend_4; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_4 = _rdata_sdata_T_12 ? _rdata_sdata_T_14 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_5 = {{224'd0}, rdata_sdata_4}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_7 = _rdata_T_6 | _GEN_5; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_5 = {_rdata_T_2[71:64],_rdata_T_2[63:56],_rdata_T_2[55:48],_rdata_T_2[47:40]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_43 = rdata_rdata_5[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_46 = rdata_rdata_5[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_47 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_43 : _rdata_signExtend_T_46; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_5 = data_io_out_bits_sext ? _rdata_signExtend_T_47 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_15 = rsel == 5'h5; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_16 = rdata_rdata_5 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_17 = _rdata_sdata_T_16 | rdata_signExtend_5; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_5 = _rdata_sdata_T_15 ? _rdata_sdata_T_17 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_6 = {{224'd0}, rdata_sdata_5}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_8 = _rdata_T_7 | _GEN_6; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_6 = {_rdata_T_2[79:72],_rdata_T_2[71:64],_rdata_T_2[63:56],_rdata_T_2[55:48]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_51 = rdata_rdata_6[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_54 = rdata_rdata_6[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_55 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_51 : _rdata_signExtend_T_54; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_6 = data_io_out_bits_sext ? _rdata_signExtend_T_55 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_18 = rsel == 5'h6; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_19 = rdata_rdata_6 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_20 = _rdata_sdata_T_19 | rdata_signExtend_6; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_6 = _rdata_sdata_T_18 ? _rdata_sdata_T_20 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_7 = {{224'd0}, rdata_sdata_6}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_9 = _rdata_T_8 | _GEN_7; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_7 = {_rdata_T_2[87:80],_rdata_T_2[79:72],_rdata_T_2[71:64],_rdata_T_2[63:56]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_59 = rdata_rdata_7[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_62 = rdata_rdata_7[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_63 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_59 : _rdata_signExtend_T_62; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_7 = data_io_out_bits_sext ? _rdata_signExtend_T_63 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_21 = rsel == 5'h7; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_22 = rdata_rdata_7 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_23 = _rdata_sdata_T_22 | rdata_signExtend_7; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_7 = _rdata_sdata_T_21 ? _rdata_sdata_T_23 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_8 = {{224'd0}, rdata_sdata_7}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_10 = _rdata_T_9 | _GEN_8; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_8 = {_rdata_T_2[95:88],_rdata_T_2[87:80],_rdata_T_2[79:72],_rdata_T_2[71:64]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_67 = rdata_rdata_8[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_70 = rdata_rdata_8[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_71 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_67 : _rdata_signExtend_T_70; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_8 = data_io_out_bits_sext ? _rdata_signExtend_T_71 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_24 = rsel == 5'h8; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_25 = rdata_rdata_8 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_26 = _rdata_sdata_T_25 | rdata_signExtend_8; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_8 = _rdata_sdata_T_24 ? _rdata_sdata_T_26 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_9 = {{224'd0}, rdata_sdata_8}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_11 = _rdata_T_10 | _GEN_9; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_9 = {_rdata_T_2[103:96],_rdata_T_2[95:88],_rdata_T_2[87:80],_rdata_T_2[79:72]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_75 = rdata_rdata_9[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_78 = rdata_rdata_9[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_79 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_75 : _rdata_signExtend_T_78; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_9 = data_io_out_bits_sext ? _rdata_signExtend_T_79 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_27 = rsel == 5'h9; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_28 = rdata_rdata_9 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_29 = _rdata_sdata_T_28 | rdata_signExtend_9; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_9 = _rdata_sdata_T_27 ? _rdata_sdata_T_29 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_10 = {{224'd0}, rdata_sdata_9}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_12 = _rdata_T_11 | _GEN_10; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_10 = {_rdata_T_2[111:104],_rdata_T_2[103:96],_rdata_T_2[95:88],_rdata_T_2[87:80]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_83 = rdata_rdata_10[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_86 = rdata_rdata_10[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_87 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_83 : _rdata_signExtend_T_86; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_10 = data_io_out_bits_sext ? _rdata_signExtend_T_87 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_30 = rsel == 5'ha; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_31 = rdata_rdata_10 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_32 = _rdata_sdata_T_31 | rdata_signExtend_10; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_10 = _rdata_sdata_T_30 ? _rdata_sdata_T_32 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_11 = {{224'd0}, rdata_sdata_10}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_13 = _rdata_T_12 | _GEN_11; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_11 = {_rdata_T_2[119:112],_rdata_T_2[111:104],_rdata_T_2[103:96],_rdata_T_2[95:88]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_91 = rdata_rdata_11[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_94 = rdata_rdata_11[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_95 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_91 : _rdata_signExtend_T_94; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_11 = data_io_out_bits_sext ? _rdata_signExtend_T_95 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_33 = rsel == 5'hb; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_34 = rdata_rdata_11 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_35 = _rdata_sdata_T_34 | rdata_signExtend_11; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_11 = _rdata_sdata_T_33 ? _rdata_sdata_T_35 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_12 = {{224'd0}, rdata_sdata_11}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_14 = _rdata_T_13 | _GEN_12; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_12 = {_rdata_T_2[127:120],_rdata_T_2[119:112],_rdata_T_2[111:104],_rdata_T_2[103:96]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_99 = rdata_rdata_12[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_102 = rdata_rdata_12[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_103 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_99 : _rdata_signExtend_T_102; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_12 = data_io_out_bits_sext ? _rdata_signExtend_T_103 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_36 = rsel == 5'hc; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_37 = rdata_rdata_12 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_38 = _rdata_sdata_T_37 | rdata_signExtend_12; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_12 = _rdata_sdata_T_36 ? _rdata_sdata_T_38 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_13 = {{224'd0}, rdata_sdata_12}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_15 = _rdata_T_14 | _GEN_13; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_13 = {_rdata_T_2[135:128],_rdata_T_2[127:120],_rdata_T_2[119:112],_rdata_T_2[111:104]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_107 = rdata_rdata_13[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_110 = rdata_rdata_13[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_111 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_107 : _rdata_signExtend_T_110; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_13 = data_io_out_bits_sext ? _rdata_signExtend_T_111 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_39 = rsel == 5'hd; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_40 = rdata_rdata_13 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_41 = _rdata_sdata_T_40 | rdata_signExtend_13; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_13 = _rdata_sdata_T_39 ? _rdata_sdata_T_41 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_14 = {{224'd0}, rdata_sdata_13}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_16 = _rdata_T_15 | _GEN_14; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_14 = {_rdata_T_2[143:136],_rdata_T_2[135:128],_rdata_T_2[127:120],_rdata_T_2[119:112]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_115 = rdata_rdata_14[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_118 = rdata_rdata_14[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_119 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_115 : _rdata_signExtend_T_118; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_14 = data_io_out_bits_sext ? _rdata_signExtend_T_119 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_42 = rsel == 5'he; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_43 = rdata_rdata_14 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_44 = _rdata_sdata_T_43 | rdata_signExtend_14; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_14 = _rdata_sdata_T_42 ? _rdata_sdata_T_44 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_15 = {{224'd0}, rdata_sdata_14}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_17 = _rdata_T_16 | _GEN_15; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_15 = {_rdata_T_2[151:144],_rdata_T_2[143:136],_rdata_T_2[135:128],_rdata_T_2[127:120]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_123 = rdata_rdata_15[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_126 = rdata_rdata_15[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_127 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_123 : _rdata_signExtend_T_126; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_15 = data_io_out_bits_sext ? _rdata_signExtend_T_127 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_45 = rsel == 5'hf; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_46 = rdata_rdata_15 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_47 = _rdata_sdata_T_46 | rdata_signExtend_15; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_15 = _rdata_sdata_T_45 ? _rdata_sdata_T_47 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_16 = {{224'd0}, rdata_sdata_15}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_18 = _rdata_T_17 | _GEN_16; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_16 = {_rdata_T_2[159:152],_rdata_T_2[151:144],_rdata_T_2[143:136],_rdata_T_2[135:128]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_131 = rdata_rdata_16[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_134 = rdata_rdata_16[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_135 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_131 : _rdata_signExtend_T_134; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_16 = data_io_out_bits_sext ? _rdata_signExtend_T_135 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_48 = rsel == 5'h10; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_49 = rdata_rdata_16 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_50 = _rdata_sdata_T_49 | rdata_signExtend_16; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_16 = _rdata_sdata_T_48 ? _rdata_sdata_T_50 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_17 = {{224'd0}, rdata_sdata_16}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_19 = _rdata_T_18 | _GEN_17; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_17 = {_rdata_T_2[167:160],_rdata_T_2[159:152],_rdata_T_2[151:144],_rdata_T_2[143:136]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_139 = rdata_rdata_17[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_142 = rdata_rdata_17[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_143 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_139 : _rdata_signExtend_T_142; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_17 = data_io_out_bits_sext ? _rdata_signExtend_T_143 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_51 = rsel == 5'h11; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_52 = rdata_rdata_17 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_53 = _rdata_sdata_T_52 | rdata_signExtend_17; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_17 = _rdata_sdata_T_51 ? _rdata_sdata_T_53 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_18 = {{224'd0}, rdata_sdata_17}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_20 = _rdata_T_19 | _GEN_18; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_18 = {_rdata_T_2[175:168],_rdata_T_2[167:160],_rdata_T_2[159:152],_rdata_T_2[151:144]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_147 = rdata_rdata_18[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_150 = rdata_rdata_18[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_151 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_147 : _rdata_signExtend_T_150; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_18 = data_io_out_bits_sext ? _rdata_signExtend_T_151 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_54 = rsel == 5'h12; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_55 = rdata_rdata_18 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_56 = _rdata_sdata_T_55 | rdata_signExtend_18; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_18 = _rdata_sdata_T_54 ? _rdata_sdata_T_56 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_19 = {{224'd0}, rdata_sdata_18}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_21 = _rdata_T_20 | _GEN_19; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_19 = {_rdata_T_2[183:176],_rdata_T_2[175:168],_rdata_T_2[167:160],_rdata_T_2[159:152]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_155 = rdata_rdata_19[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_158 = rdata_rdata_19[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_159 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_155 : _rdata_signExtend_T_158; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_19 = data_io_out_bits_sext ? _rdata_signExtend_T_159 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_57 = rsel == 5'h13; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_58 = rdata_rdata_19 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_59 = _rdata_sdata_T_58 | rdata_signExtend_19; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_19 = _rdata_sdata_T_57 ? _rdata_sdata_T_59 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_20 = {{224'd0}, rdata_sdata_19}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_22 = _rdata_T_21 | _GEN_20; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_20 = {_rdata_T_2[191:184],_rdata_T_2[183:176],_rdata_T_2[175:168],_rdata_T_2[167:160]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_163 = rdata_rdata_20[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_166 = rdata_rdata_20[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_167 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_163 : _rdata_signExtend_T_166; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_20 = data_io_out_bits_sext ? _rdata_signExtend_T_167 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_60 = rsel == 5'h14; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_61 = rdata_rdata_20 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_62 = _rdata_sdata_T_61 | rdata_signExtend_20; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_20 = _rdata_sdata_T_60 ? _rdata_sdata_T_62 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_21 = {{224'd0}, rdata_sdata_20}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_23 = _rdata_T_22 | _GEN_21; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_21 = {_rdata_T_2[199:192],_rdata_T_2[191:184],_rdata_T_2[183:176],_rdata_T_2[175:168]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_171 = rdata_rdata_21[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_174 = rdata_rdata_21[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_175 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_171 : _rdata_signExtend_T_174; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_21 = data_io_out_bits_sext ? _rdata_signExtend_T_175 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_63 = rsel == 5'h15; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_64 = rdata_rdata_21 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_65 = _rdata_sdata_T_64 | rdata_signExtend_21; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_21 = _rdata_sdata_T_63 ? _rdata_sdata_T_65 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_22 = {{224'd0}, rdata_sdata_21}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_24 = _rdata_T_23 | _GEN_22; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_22 = {_rdata_T_2[207:200],_rdata_T_2[199:192],_rdata_T_2[191:184],_rdata_T_2[183:176]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_179 = rdata_rdata_22[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_182 = rdata_rdata_22[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_183 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_179 : _rdata_signExtend_T_182; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_22 = data_io_out_bits_sext ? _rdata_signExtend_T_183 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_66 = rsel == 5'h16; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_67 = rdata_rdata_22 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_68 = _rdata_sdata_T_67 | rdata_signExtend_22; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_22 = _rdata_sdata_T_66 ? _rdata_sdata_T_68 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_23 = {{224'd0}, rdata_sdata_22}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_25 = _rdata_T_24 | _GEN_23; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_23 = {_rdata_T_2[215:208],_rdata_T_2[207:200],_rdata_T_2[199:192],_rdata_T_2[191:184]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_187 = rdata_rdata_23[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_190 = rdata_rdata_23[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_191 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_187 : _rdata_signExtend_T_190; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_23 = data_io_out_bits_sext ? _rdata_signExtend_T_191 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_69 = rsel == 5'h17; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_70 = rdata_rdata_23 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_71 = _rdata_sdata_T_70 | rdata_signExtend_23; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_23 = _rdata_sdata_T_69 ? _rdata_sdata_T_71 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_24 = {{224'd0}, rdata_sdata_23}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_26 = _rdata_T_25 | _GEN_24; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_24 = {_rdata_T_2[223:216],_rdata_T_2[215:208],_rdata_T_2[207:200],_rdata_T_2[199:192]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_195 = rdata_rdata_24[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_198 = rdata_rdata_24[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_199 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_195 : _rdata_signExtend_T_198; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_24 = data_io_out_bits_sext ? _rdata_signExtend_T_199 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_72 = rsel == 5'h18; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_73 = rdata_rdata_24 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_74 = _rdata_sdata_T_73 | rdata_signExtend_24; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_24 = _rdata_sdata_T_72 ? _rdata_sdata_T_74 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_25 = {{224'd0}, rdata_sdata_24}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_27 = _rdata_T_26 | _GEN_25; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_25 = {_rdata_T_2[231:224],_rdata_T_2[223:216],_rdata_T_2[215:208],_rdata_T_2[207:200]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_203 = rdata_rdata_25[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_206 = rdata_rdata_25[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_207 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_203 : _rdata_signExtend_T_206; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_25 = data_io_out_bits_sext ? _rdata_signExtend_T_207 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_75 = rsel == 5'h19; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_76 = rdata_rdata_25 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_77 = _rdata_sdata_T_76 | rdata_signExtend_25; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_25 = _rdata_sdata_T_75 ? _rdata_sdata_T_77 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_26 = {{224'd0}, rdata_sdata_25}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_28 = _rdata_T_27 | _GEN_26; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_26 = {_rdata_T_2[239:232],_rdata_T_2[231:224],_rdata_T_2[223:216],_rdata_T_2[215:208]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_211 = rdata_rdata_26[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_214 = rdata_rdata_26[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_215 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_211 : _rdata_signExtend_T_214; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_26 = data_io_out_bits_sext ? _rdata_signExtend_T_215 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_78 = rsel == 5'h1a; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_79 = rdata_rdata_26 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_80 = _rdata_sdata_T_79 | rdata_signExtend_26; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_26 = _rdata_sdata_T_78 ? _rdata_sdata_T_80 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_27 = {{224'd0}, rdata_sdata_26}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_29 = _rdata_T_28 | _GEN_27; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_27 = {_rdata_T_2[247:240],_rdata_T_2[239:232],_rdata_T_2[231:224],_rdata_T_2[223:216]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_219 = rdata_rdata_27[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_222 = rdata_rdata_27[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_223 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_219 : _rdata_signExtend_T_222; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_27 = data_io_out_bits_sext ? _rdata_signExtend_T_223 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_81 = rsel == 5'h1b; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_82 = rdata_rdata_27 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_83 = _rdata_sdata_T_82 | rdata_signExtend_27; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_27 = _rdata_sdata_T_81 ? _rdata_sdata_T_83 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_28 = {{224'd0}, rdata_sdata_27}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_30 = _rdata_T_29 | _GEN_28; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_28 = {_rdata_T_2[255:248],_rdata_T_2[247:240],_rdata_T_2[239:232],_rdata_T_2[231:224]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_227 = rdata_rdata_28[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_230 = rdata_rdata_28[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_231 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_227 : _rdata_signExtend_T_230; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_28 = data_io_out_bits_sext ? _rdata_signExtend_T_231 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_84 = rsel == 5'h1c; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_85 = rdata_rdata_28 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_86 = _rdata_sdata_T_85 | rdata_signExtend_28; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_28 = _rdata_sdata_T_84 ? _rdata_sdata_T_86 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_29 = {{224'd0}, rdata_sdata_28}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_31 = _rdata_T_30 | _GEN_29; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_29 = {_rdata_T_2[7:0],_rdata_T_2[255:248],_rdata_T_2[247:240],_rdata_T_2[239:232]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_235 = rdata_rdata_29[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_238 = rdata_rdata_29[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_239 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_235 : _rdata_signExtend_T_238; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_29 = data_io_out_bits_sext ? _rdata_signExtend_T_239 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_87 = rsel == 5'h1d; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_88 = rdata_rdata_29 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_89 = _rdata_sdata_T_88 | rdata_signExtend_29; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_29 = _rdata_sdata_T_87 ? _rdata_sdata_T_89 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_30 = {{224'd0}, rdata_sdata_29}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_32 = _rdata_T_31 | _GEN_30; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_30 = {_rdata_T_2[15:8],_rdata_T_2[7:0],_rdata_T_2[255:248],_rdata_T_2[247:240]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_243 = rdata_rdata_30[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_246 = rdata_rdata_30[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_247 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_243 : _rdata_signExtend_T_246; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_30 = data_io_out_bits_sext ? _rdata_signExtend_T_247 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_90 = rsel == 5'h1e; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_91 = rdata_rdata_30 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_92 = _rdata_sdata_T_91 | rdata_signExtend_30; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_30 = _rdata_sdata_T_90 ? _rdata_sdata_T_92 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_31 = {{224'd0}, rdata_sdata_30}; // @[Lsu.scala 286:34]
- wire [255:0] _rdata_T_33 = _rdata_T_32 | _GEN_31; // @[Lsu.scala 286:34]
- wire [31:0] rdata_rdata_31 = {_rdata_T_2[23:16],_rdata_T_2[15:8],_rdata_T_2[7:0],_rdata_T_2[255:248]}; // @[Cat.scala 31:58]
- wire [31:0] _rdata_signExtend_T_251 = rdata_rdata_31[15] ? 32'hffff0000 : 32'h0; // @[Lsu.scala 279:31]
- wire [31:0] _rdata_signExtend_T_254 = rdata_rdata_31[7] ? 32'hffffff00 : 32'h0; // @[Lsu.scala 280:31]
- wire [31:0] _rdata_signExtend_T_255 = _rdata_sizeMask_T_2 ? _rdata_signExtend_T_251 : _rdata_signExtend_T_254; // @[Lsu.scala 278:29]
- wire [31:0] rdata_signExtend_31 = data_io_out_bits_sext ? _rdata_signExtend_T_255 : 32'h0; // @[Lsu.scala 277:27]
- wire _rdata_sdata_T_93 = rsel == 5'h1f; // @[Lsu.scala 285:30]
- wire [31:0] _rdata_sdata_T_94 = rdata_rdata_31 & rdata_sizeMask; // @[Lsu.scala 285:45]
- wire [31:0] _rdata_sdata_T_95 = _rdata_sdata_T_94 | rdata_signExtend_31; // @[Lsu.scala 285:56]
- wire [31:0] rdata_sdata_31 = _rdata_sdata_T_93 ? _rdata_sdata_T_95 : 32'h0; // @[Library.scala 22:8]
- wire [255:0] _GEN_32 = {{224'd0}, rdata_sdata_31}; // @[Lsu.scala 286:34]
- wire [255:0] rdata = _rdata_T_33 | _GEN_32; // @[Lsu.scala 286:34]
- wire [2:0] _T_44 = {ctrl_io_out_bits_sldst,ctrl_io_out_bits_vldst,ctrl_io_out_bits_suncd}; // @[Cat.scala 31:58]
- wire [1:0] _T_48 = _T_44[1] + _T_44[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_33 = {{1'd0}, _T_44[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_50 = _GEN_33 + _T_48; // @[Bitwise.scala 48:55]
- wire [1:0] _T_58 = {data_io_out_bits_sldst,data_io_out_bits_suncd}; // @[Cat.scala 31:58]
- wire [1:0] _T_61 = _T_58[0] + _T_58[1]; // @[Bitwise.scala 48:55]
- Fifo4 ctrl ( // @[Fifo4.scala 22:11]
- .clock(ctrl_clock),
- .reset(ctrl_reset),
- .io_in_ready(ctrl_io_in_ready),
- .io_in_valid(ctrl_io_in_valid),
- .io_in_bits_0_valid(ctrl_io_in_bits_0_valid),
- .io_in_bits_0_bits_addr(ctrl_io_in_bits_0_bits_addr),
- .io_in_bits_0_bits_adrx(ctrl_io_in_bits_0_bits_adrx),
- .io_in_bits_0_bits_data(ctrl_io_in_bits_0_bits_data),
- .io_in_bits_0_bits_index(ctrl_io_in_bits_0_bits_index),
- .io_in_bits_0_bits_size(ctrl_io_in_bits_0_bits_size),
- .io_in_bits_0_bits_write(ctrl_io_in_bits_0_bits_write),
- .io_in_bits_0_bits_sext(ctrl_io_in_bits_0_bits_sext),
- .io_in_bits_0_bits_iload(ctrl_io_in_bits_0_bits_iload),
- .io_in_bits_0_bits_fencei(ctrl_io_in_bits_0_bits_fencei),
- .io_in_bits_0_bits_flushat(ctrl_io_in_bits_0_bits_flushat),
- .io_in_bits_0_bits_flushall(ctrl_io_in_bits_0_bits_flushall),
- .io_in_bits_0_bits_sldst(ctrl_io_in_bits_0_bits_sldst),
- .io_in_bits_0_bits_vldst(ctrl_io_in_bits_0_bits_vldst),
- .io_in_bits_0_bits_suncd(ctrl_io_in_bits_0_bits_suncd),
- .io_in_bits_1_valid(ctrl_io_in_bits_1_valid),
- .io_in_bits_1_bits_addr(ctrl_io_in_bits_1_bits_addr),
- .io_in_bits_1_bits_adrx(ctrl_io_in_bits_1_bits_adrx),
- .io_in_bits_1_bits_data(ctrl_io_in_bits_1_bits_data),
- .io_in_bits_1_bits_index(ctrl_io_in_bits_1_bits_index),
- .io_in_bits_1_bits_size(ctrl_io_in_bits_1_bits_size),
- .io_in_bits_1_bits_write(ctrl_io_in_bits_1_bits_write),
- .io_in_bits_1_bits_sext(ctrl_io_in_bits_1_bits_sext),
- .io_in_bits_1_bits_iload(ctrl_io_in_bits_1_bits_iload),
- .io_in_bits_1_bits_fencei(ctrl_io_in_bits_1_bits_fencei),
- .io_in_bits_1_bits_flushat(ctrl_io_in_bits_1_bits_flushat),
- .io_in_bits_1_bits_flushall(ctrl_io_in_bits_1_bits_flushall),
- .io_in_bits_1_bits_sldst(ctrl_io_in_bits_1_bits_sldst),
- .io_in_bits_1_bits_vldst(ctrl_io_in_bits_1_bits_vldst),
- .io_in_bits_1_bits_suncd(ctrl_io_in_bits_1_bits_suncd),
- .io_in_bits_2_valid(ctrl_io_in_bits_2_valid),
- .io_in_bits_2_bits_addr(ctrl_io_in_bits_2_bits_addr),
- .io_in_bits_2_bits_adrx(ctrl_io_in_bits_2_bits_adrx),
- .io_in_bits_2_bits_data(ctrl_io_in_bits_2_bits_data),
- .io_in_bits_2_bits_index(ctrl_io_in_bits_2_bits_index),
- .io_in_bits_2_bits_size(ctrl_io_in_bits_2_bits_size),
- .io_in_bits_2_bits_write(ctrl_io_in_bits_2_bits_write),
- .io_in_bits_2_bits_sext(ctrl_io_in_bits_2_bits_sext),
- .io_in_bits_2_bits_iload(ctrl_io_in_bits_2_bits_iload),
- .io_in_bits_2_bits_fencei(ctrl_io_in_bits_2_bits_fencei),
- .io_in_bits_2_bits_flushat(ctrl_io_in_bits_2_bits_flushat),
- .io_in_bits_2_bits_flushall(ctrl_io_in_bits_2_bits_flushall),
- .io_in_bits_2_bits_sldst(ctrl_io_in_bits_2_bits_sldst),
- .io_in_bits_2_bits_vldst(ctrl_io_in_bits_2_bits_vldst),
- .io_in_bits_2_bits_suncd(ctrl_io_in_bits_2_bits_suncd),
- .io_in_bits_3_valid(ctrl_io_in_bits_3_valid),
- .io_in_bits_3_bits_addr(ctrl_io_in_bits_3_bits_addr),
- .io_in_bits_3_bits_adrx(ctrl_io_in_bits_3_bits_adrx),
- .io_in_bits_3_bits_data(ctrl_io_in_bits_3_bits_data),
- .io_in_bits_3_bits_index(ctrl_io_in_bits_3_bits_index),
- .io_in_bits_3_bits_size(ctrl_io_in_bits_3_bits_size),
- .io_in_bits_3_bits_write(ctrl_io_in_bits_3_bits_write),
- .io_in_bits_3_bits_sext(ctrl_io_in_bits_3_bits_sext),
- .io_in_bits_3_bits_iload(ctrl_io_in_bits_3_bits_iload),
- .io_in_bits_3_bits_fencei(ctrl_io_in_bits_3_bits_fencei),
- .io_in_bits_3_bits_flushat(ctrl_io_in_bits_3_bits_flushat),
- .io_in_bits_3_bits_flushall(ctrl_io_in_bits_3_bits_flushall),
- .io_in_bits_3_bits_sldst(ctrl_io_in_bits_3_bits_sldst),
- .io_in_bits_3_bits_vldst(ctrl_io_in_bits_3_bits_vldst),
- .io_in_bits_3_bits_suncd(ctrl_io_in_bits_3_bits_suncd),
- .io_out_ready(ctrl_io_out_ready),
- .io_out_valid(ctrl_io_out_valid),
- .io_out_bits_addr(ctrl_io_out_bits_addr),
- .io_out_bits_adrx(ctrl_io_out_bits_adrx),
- .io_out_bits_data(ctrl_io_out_bits_data),
- .io_out_bits_index(ctrl_io_out_bits_index),
- .io_out_bits_size(ctrl_io_out_bits_size),
- .io_out_bits_write(ctrl_io_out_bits_write),
- .io_out_bits_sext(ctrl_io_out_bits_sext),
- .io_out_bits_iload(ctrl_io_out_bits_iload),
- .io_out_bits_fencei(ctrl_io_out_bits_fencei),
- .io_out_bits_flushat(ctrl_io_out_bits_flushat),
- .io_out_bits_flushall(ctrl_io_out_bits_flushall),
- .io_out_bits_sldst(ctrl_io_out_bits_sldst),
- .io_out_bits_vldst(ctrl_io_out_bits_vldst),
- .io_out_bits_suncd(ctrl_io_out_bits_suncd),
- .io_count(ctrl_io_count)
- );
- Slice_2 data ( // @[Slice.scala 23:11]
- .clock(data_clock),
- .reset(data_reset),
- .io_in_ready(data_io_in_ready),
- .io_in_valid(data_io_in_valid),
- .io_in_bits_addr(data_io_in_bits_addr),
- .io_in_bits_index(data_io_in_bits_index),
- .io_in_bits_size(data_io_in_bits_size),
- .io_in_bits_sext(data_io_in_bits_sext),
- .io_in_bits_iload(data_io_in_bits_iload),
- .io_in_bits_sldst(data_io_in_bits_sldst),
- .io_in_bits_suncd(data_io_in_bits_suncd),
- .io_out_valid(data_io_out_valid),
- .io_out_bits_addr(data_io_out_bits_addr),
- .io_out_bits_index(data_io_out_bits_index),
- .io_out_bits_size(data_io_out_bits_size),
- .io_out_bits_sext(data_io_out_bits_sext),
- .io_out_bits_iload(data_io_out_bits_iload),
- .io_out_bits_sldst(data_io_out_bits_sldst),
- .io_out_bits_suncd(data_io_out_bits_suncd)
- );
- assign io_req_0_ready = ctrlready[0]; // @[Lsu.scala 125:31]
- assign io_req_1_ready = ctrlready[1]; // @[Lsu.scala 126:31]
- assign io_req_2_ready = ctrlready[2]; // @[Lsu.scala 127:31]
- assign io_req_3_ready = ctrlready[3]; // @[Lsu.scala 128:31]
- assign io_rd_valid = data_io_out_valid & data_io_out_bits_iload; // @[Lsu.scala 296:25]
- assign io_rd_addr = data_io_out_bits_index; // @[Lsu.scala 297:15]
- assign io_rd_data = rdata[31:0]; // @[Lsu.scala 298:15]
- assign io_dbus_valid = ctrl_io_out_valid & ctrl_io_out_bits_sldst; // @[Lsu.scala 203:38]
- assign io_dbus_write = ctrl_io_out_bits_write; // @[Lsu.scala 204:17]
- assign io_dbus_addr = {1'h0,ctrl_io_out_bits_addr[30:0]}; // @[Cat.scala 31:58]
- assign io_dbus_adrx = {1'h0,ctrl_io_out_bits_adrx[30:0]}; // @[Cat.scala 31:58]
- assign io_dbus_size = ctrl_io_out_bits_size; // @[Lsu.scala 207:17]
- assign io_dbus_wdata = {wdata_lo,wdata_lo}; // @[Cat.scala 31:58]
- assign io_dbus_wmask = wmaskS[31:0]; // @[Lsu.scala 187:21]
- assign io_flush_valid = ctrl_io_out_valid & (ctrl_io_out_bits_fencei | ctrl_io_out_bits_flushat |
- ctrl_io_out_bits_flushall); // @[Lsu.scala 225:40]
- assign io_flush_all = ctrl_io_out_bits_fencei | ctrl_io_out_bits_flushall; // @[Lsu.scala 226:46]
- assign io_flush_fencei = ctrl_io_out_bits_fencei; // @[Lsu.scala 228:19]
- assign io_ubus_valid = ctrl_io_out_valid & ctrl_io_out_bits_suncd; // @[Lsu.scala 214:38]
- assign io_ubus_write = ctrl_io_out_bits_write; // @[Lsu.scala 215:17]
- assign io_ubus_addr = {1'h0,ctrl_io_out_bits_addr[30:0]}; // @[Cat.scala 31:58]
- assign io_ubus_wdata = {wdata_lo,wdata_lo}; // @[Cat.scala 31:58]
- assign io_ubus_wmask = wmaskS[31:0]; // @[Lsu.scala 187:21]
- assign io_vldst = ctrl_io_out_valid & ctrl_io_out_bits_vldst; // @[Lsu.scala 235:33]
- assign ctrl_clock = clock;
- assign ctrl_reset = reset;
- assign ctrl_io_in_valid = _ctrl_io_in_valid_T_1 | io_req_3_valid; // @[Lsu.scala 137:39]
- assign ctrl_io_in_bits_0_valid = io_req_0_valid & ctrlready[0] & ~(opvldst & uncached); // @[Lsu.scala 155:65]
- assign ctrl_io_in_bits_0_bits_addr = io_busPort_addr_0; // @[Lsu.scala 157:34]
- assign ctrl_io_in_bits_0_bits_adrx = io_busPort_addr_0 + 32'h20; // @[Lsu.scala 158:56]
- assign ctrl_io_in_bits_0_bits_data = io_busPort_data_0; // @[Lsu.scala 159:34]
- assign ctrl_io_in_bits_0_bits_index = io_req_0_addr; // @[Lsu.scala 160:35]
- assign ctrl_io_in_bits_0_bits_size = {{3'd0}, opsize}; // @[Lsu.scala 162:34]
- assign ctrl_io_in_bits_0_bits_write = ~opiload; // @[Lsu.scala 170:38]
- assign ctrl_io_in_bits_0_bits_sext = io_req_0_op[0] | io_req_0_op[1]; // @[Lsu.scala 150:39]
- assign ctrl_io_in_bits_0_bits_iload = io_req_0_op[2] | io_req_0_op[1] | io_req_0_op[0] | io_req_0_op[4] | io_req_0_op[
- 3]; // @[Lsu.scala 143:113]
- assign ctrl_io_in_bits_0_bits_fencei = io_req_0_op[8]; // @[Lsu.scala 145:34]
- assign ctrl_io_in_bits_0_bits_flushat = io_req_0_op[9]; // @[Lsu.scala 146:34]
- assign ctrl_io_in_bits_0_bits_flushall = io_req_0_op[10]; // @[Lsu.scala 147:34]
- assign ctrl_io_in_bits_0_bits_sldst = opsldst & ~uncached; // @[Lsu.scala 167:46]
- assign ctrl_io_in_bits_0_bits_vldst = io_req_0_op[11]; // @[Lsu.scala 149:31]
- assign ctrl_io_in_bits_0_bits_suncd = opsldst & uncached; // @[Lsu.scala 169:46]
- assign ctrl_io_in_bits_1_valid = io_req_1_valid & ctrlready[1] & ~(opvldst_1 & uncached_1); // @[Lsu.scala 155:65]
- assign ctrl_io_in_bits_1_bits_addr = io_busPort_addr_1; // @[Lsu.scala 157:34]
- assign ctrl_io_in_bits_1_bits_adrx = io_busPort_addr_1 + 32'h20; // @[Lsu.scala 158:56]
- assign ctrl_io_in_bits_1_bits_data = io_busPort_data_1; // @[Lsu.scala 159:34]
- assign ctrl_io_in_bits_1_bits_index = io_req_1_addr; // @[Lsu.scala 160:35]
- assign ctrl_io_in_bits_1_bits_size = {{3'd0}, opsize_1}; // @[Lsu.scala 162:34]
- assign ctrl_io_in_bits_1_bits_write = ~opiload_1; // @[Lsu.scala 170:38]
- assign ctrl_io_in_bits_1_bits_sext = io_req_1_op[0] | io_req_1_op[1]; // @[Lsu.scala 150:39]
- assign ctrl_io_in_bits_1_bits_iload = io_req_1_op[2] | io_req_1_op[1] | io_req_1_op[0] | io_req_1_op[4] | io_req_1_op[
- 3]; // @[Lsu.scala 143:113]
- assign ctrl_io_in_bits_1_bits_fencei = io_req_1_op[8]; // @[Lsu.scala 145:34]
- assign ctrl_io_in_bits_1_bits_flushat = io_req_1_op[9]; // @[Lsu.scala 146:34]
- assign ctrl_io_in_bits_1_bits_flushall = io_req_1_op[10]; // @[Lsu.scala 147:34]
- assign ctrl_io_in_bits_1_bits_sldst = opsldst_1 & ~uncached_1; // @[Lsu.scala 167:46]
- assign ctrl_io_in_bits_1_bits_vldst = io_req_1_op[11]; // @[Lsu.scala 149:31]
- assign ctrl_io_in_bits_1_bits_suncd = opsldst_1 & uncached_1; // @[Lsu.scala 169:46]
- assign ctrl_io_in_bits_2_valid = io_req_2_valid & ctrlready[2] & ~(opvldst_2 & uncached_2); // @[Lsu.scala 155:65]
- assign ctrl_io_in_bits_2_bits_addr = io_busPort_addr_2; // @[Lsu.scala 157:34]
- assign ctrl_io_in_bits_2_bits_adrx = io_busPort_addr_2 + 32'h20; // @[Lsu.scala 158:56]
- assign ctrl_io_in_bits_2_bits_data = io_busPort_data_2; // @[Lsu.scala 159:34]
- assign ctrl_io_in_bits_2_bits_index = io_req_2_addr; // @[Lsu.scala 160:35]
- assign ctrl_io_in_bits_2_bits_size = {{3'd0}, opsize_2}; // @[Lsu.scala 162:34]
- assign ctrl_io_in_bits_2_bits_write = ~opiload_2; // @[Lsu.scala 170:38]
- assign ctrl_io_in_bits_2_bits_sext = io_req_2_op[0] | io_req_2_op[1]; // @[Lsu.scala 150:39]
- assign ctrl_io_in_bits_2_bits_iload = io_req_2_op[2] | io_req_2_op[1] | io_req_2_op[0] | io_req_2_op[4] | io_req_2_op[
- 3]; // @[Lsu.scala 143:113]
- assign ctrl_io_in_bits_2_bits_fencei = io_req_2_op[8]; // @[Lsu.scala 145:34]
- assign ctrl_io_in_bits_2_bits_flushat = io_req_2_op[9]; // @[Lsu.scala 146:34]
- assign ctrl_io_in_bits_2_bits_flushall = io_req_2_op[10]; // @[Lsu.scala 147:34]
- assign ctrl_io_in_bits_2_bits_sldst = opsldst_2 & ~uncached_2; // @[Lsu.scala 167:46]
- assign ctrl_io_in_bits_2_bits_vldst = io_req_2_op[11]; // @[Lsu.scala 149:31]
- assign ctrl_io_in_bits_2_bits_suncd = opsldst_2 & uncached_2; // @[Lsu.scala 169:46]
- assign ctrl_io_in_bits_3_valid = io_req_3_valid & ctrlready[3] & ~(opvldst_3 & uncached_3); // @[Lsu.scala 155:65]
- assign ctrl_io_in_bits_3_bits_addr = io_busPort_addr_3; // @[Lsu.scala 157:34]
- assign ctrl_io_in_bits_3_bits_adrx = io_busPort_addr_3 + 32'h20; // @[Lsu.scala 158:56]
- assign ctrl_io_in_bits_3_bits_data = io_busPort_data_3; // @[Lsu.scala 159:34]
- assign ctrl_io_in_bits_3_bits_index = io_req_3_addr; // @[Lsu.scala 160:35]
- assign ctrl_io_in_bits_3_bits_size = {{3'd0}, opsize_3}; // @[Lsu.scala 162:34]
- assign ctrl_io_in_bits_3_bits_write = ~opiload_3; // @[Lsu.scala 170:38]
- assign ctrl_io_in_bits_3_bits_sext = io_req_3_op[0] | io_req_3_op[1]; // @[Lsu.scala 150:39]
- assign ctrl_io_in_bits_3_bits_iload = io_req_3_op[2] | io_req_3_op[1] | io_req_3_op[0] | io_req_3_op[4] | io_req_3_op[
- 3]; // @[Lsu.scala 143:113]
- assign ctrl_io_in_bits_3_bits_fencei = io_req_3_op[8]; // @[Lsu.scala 145:34]
- assign ctrl_io_in_bits_3_bits_flushat = io_req_3_op[9]; // @[Lsu.scala 146:34]
- assign ctrl_io_in_bits_3_bits_flushall = io_req_3_op[10]; // @[Lsu.scala 147:34]
- assign ctrl_io_in_bits_3_bits_sldst = opsldst_3 & ~uncached_3; // @[Lsu.scala 167:46]
- assign ctrl_io_in_bits_3_bits_vldst = io_req_3_op[11]; // @[Lsu.scala 149:31]
- assign ctrl_io_in_bits_3_bits_suncd = opsldst_3 & uncached_3; // @[Lsu.scala 169:46]
- assign ctrl_io_out_ready = _ctrl_io_out_ready_T_4 | _ctrl_io_out_ready_T_5; // @[Lsu.scala 232:55]
- assign data_clock = clock;
- assign data_reset = reset;
- assign data_io_in_valid = _ctrl_io_out_ready_T_1 & ~io_dbus_write | _data_io_in_valid_T_5; // @[Lsu.scala 239:72]
- assign data_io_in_bits_addr = ctrl_io_out_bits_addr; // @[Lsu.scala 242:25]
- assign data_io_in_bits_index = ctrl_io_out_bits_index; // @[Lsu.scala 243:25]
- assign data_io_in_bits_size = ctrl_io_out_bits_size; // @[Lsu.scala 245:25]
- assign data_io_in_bits_sext = ctrl_io_out_bits_sext; // @[Lsu.scala 244:25]
- assign data_io_in_bits_iload = ctrl_io_out_bits_iload; // @[Lsu.scala 246:25]
- assign data_io_in_bits_sldst = ctrl_io_out_bits_sldst; // @[Lsu.scala 247:25]
- assign data_io_in_bits_suncd = ctrl_io_out_bits_suncd; // @[Lsu.scala 248:25]
- always @(posedge clock) begin
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(io_dbus_valid & ctrl_io_out_bits_addr[31]))) begin
- $fatal; // @[Lsu.scala 210:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(io_dbus_valid & ctrl_io_out_bits_addr[31]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Lsu.scala:210 assert(!(io.dbus.valid && ctrl.io.out.bits.addr(31)))\n"); // @[Lsu.scala 210:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
- $fatal; // @[Lsu.scala 211:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
- $fwrite(32'h80000002,"Assertion failed\n at Lsu.scala:211 assert(!(io.dbus.valid && io.dbus.addr(31)))\n"); // @[Lsu.scala 211:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(io_dbus_valid & io_dbus_adrx[31]))) begin
- $fatal; // @[Lsu.scala 212:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(io_dbus_valid & io_dbus_adrx[31]))) begin
- $fwrite(32'h80000002,"Assertion failed\n at Lsu.scala:212 assert(!(io.dbus.valid && io.dbus.adrx(31)))\n"); // @[Lsu.scala 212:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(io_ubus_valid & ~ctrl_io_out_bits_addr[31]))) begin
- $fatal; // @[Lsu.scala 221:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(io_ubus_valid & ~ctrl_io_out_bits_addr[31]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Lsu.scala:221 assert(!(io.ubus.valid && !ctrl.io.out.bits.addr(31)))\n"); // @[Lsu.scala 221:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(io_ubus_valid & io_dbus_addr[31]))) begin
- $fatal; // @[Lsu.scala 222:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(io_ubus_valid & io_dbus_addr[31]))) begin
- $fwrite(32'h80000002,"Assertion failed\n at Lsu.scala:222 assert(!(io.ubus.valid && io.dbus.addr(31)))\n"); // @[Lsu.scala 222:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(io_ubus_valid & io_dbus_adrx[31]))) begin
- $fatal; // @[Lsu.scala 223:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(io_ubus_valid & io_dbus_adrx[31]))) begin
- $fwrite(32'h80000002,"Assertion failed\n at Lsu.scala:223 assert(!(io.ubus.valid && io.dbus.adrx(31)))\n"); // @[Lsu.scala 223:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~ctrl_io_out_valid | _T_50[1:0] <= 2'h1)) begin
- $fatal; // @[Lsu.scala 300:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~ctrl_io_out_valid | _T_50[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Lsu.scala:300 assert(!ctrl.io.out.valid || PopCount(Cat(ctrl.io.out.bits.sldst, ctrl.io.out.bits.vldst, ctrl.io.out.bits.suncd)) <= 1.U)\n"
- ); // @[Lsu.scala 300:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~data_io_out_valid | _T_61 <= 2'h1)) begin
- $fatal; // @[Lsu.scala 301:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~data_io_out_valid | _T_61 <= 2'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Lsu.scala:301 assert(!data.io.out.valid || PopCount(Cat(data.io.out.bits.sldst, data.io.out.bits.suncd)) <= 1.U)\n"
- ); // @[Lsu.scala 301:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
-endmodule
-module Mlu(
- input clock,
- input reset,
- input io_req_0_valid,
- input [4:0] io_req_0_addr,
- input [8:0] io_req_0_op,
- input io_req_1_valid,
- input [4:0] io_req_1_addr,
- input [8:0] io_req_1_op,
- input io_req_2_valid,
- input [4:0] io_req_2_addr,
- input [8:0] io_req_2_op,
- input io_req_3_valid,
- input [4:0] io_req_3_addr,
- input [8:0] io_req_3_op,
- input io_rs1_0_valid,
- input [31:0] io_rs1_0_data,
- input io_rs1_1_valid,
- input [31:0] io_rs1_1_data,
- input io_rs1_2_valid,
- input [31:0] io_rs1_2_data,
- input io_rs1_3_valid,
- input [31:0] io_rs1_3_data,
- input io_rs2_0_valid,
- input [31:0] io_rs2_0_data,
- input io_rs2_1_valid,
- input [31:0] io_rs2_1_data,
- input io_rs2_2_valid,
- input [31:0] io_rs2_2_data,
- input io_rs2_3_valid,
- input [31:0] io_rs2_3_data,
- output io_rd_valid,
- output [4:0] io_rd_addr,
- output [31:0] io_rd_data
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
-`endif // RANDOMIZE_REG_INIT
- reg [8:0] op; // @[Mlu.scala 59:19]
- reg valid1; // @[Mlu.scala 60:23]
- reg valid2; // @[Mlu.scala 61:23]
- reg [4:0] addr1; // @[Mlu.scala 62:18]
- reg [4:0] addr2; // @[Mlu.scala 63:18]
- reg [3:0] sel; // @[Mlu.scala 64:16]
- wire _valid1_T_1 = io_req_0_valid | io_req_1_valid | io_req_2_valid; // @[Mlu.scala 66:48]
- wire _rs1_T_1 = valid1 & sel[0]; // @[Mlu.scala 91:26]
- wire [31:0] _rs1_T_2 = _rs1_T_1 ? io_rs1_0_data : 32'h0; // @[Library.scala 22:8]
- wire _rs1_T_4 = valid1 & sel[1]; // @[Mlu.scala 92:26]
- wire [31:0] _rs1_T_5 = _rs1_T_4 ? io_rs1_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rs1_T_6 = _rs1_T_2 | _rs1_T_5; // @[Mlu.scala 91:52]
- wire _rs1_T_8 = valid1 & sel[2]; // @[Mlu.scala 93:26]
- wire [31:0] _rs1_T_9 = _rs1_T_8 ? io_rs1_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rs1_T_10 = _rs1_T_6 | _rs1_T_9; // @[Mlu.scala 92:52]
- wire _rs1_T_12 = valid1 & sel[3]; // @[Mlu.scala 94:26]
- wire [31:0] _rs1_T_13 = _rs1_T_12 ? io_rs1_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] rs1 = _rs1_T_10 | _rs1_T_13; // @[Mlu.scala 93:52]
- wire [31:0] _rs2_T_2 = _rs1_T_1 ? io_rs2_0_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rs2_T_5 = _rs1_T_4 ? io_rs2_1_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rs2_T_6 = _rs2_T_2 | _rs2_T_5; // @[Mlu.scala 96:52]
- wire [31:0] _rs2_T_9 = _rs1_T_8 ? io_rs2_2_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _rs2_T_10 = _rs2_T_6 | _rs2_T_9; // @[Mlu.scala 97:52]
- wire [31:0] _rs2_T_13 = _rs1_T_12 ? io_rs2_3_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] rs2 = _rs2_T_10 | _rs2_T_13; // @[Mlu.scala 98:52]
- reg [31:0] mul2; // @[Mlu.scala 102:17]
- reg round2; // @[Mlu.scala 103:19]
- wire rs2signed = op[1] | op[4] | op[7] | op[8]; // @[Mlu.scala 106:68]
- wire rs1signed = op[2] | op[5] | rs2signed; // @[Mlu.scala 107:55]
- wire _rs1s_T_1 = rs1signed & rs1[31]; // @[Mlu.scala 108:30]
- wire [32:0] rs1s = {_rs1s_T_1,rs1}; // @[Mlu.scala 108:47]
- wire _rs2s_T_1 = rs2signed & rs2[31]; // @[Mlu.scala 109:30]
- wire [32:0] rs2s = {_rs2s_T_1,rs2}; // @[Mlu.scala 109:47]
- wire [65:0] prod = $signed(rs1s) * $signed(rs2s); // @[Mlu.scala 110:28]
- wire _round2_T_9 = prod[31] & (op[4] | op[5] | op[6]); // @[Mlu.scala 115:24]
- wire _sat_T_6 = rs1[31:30] == 2'h2; // @[Mlu.scala 125:29]
- wire _sat_T_8 = rs2[31:30] == 2'h2; // @[Mlu.scala 125:54]
- wire _sat_T_14 = _sat_T_6 & rs2[31:30] == 2'h1; // @[Mlu.scala 126:40]
- wire _sat_T_15 = rs1[31:30] == 2'h2 & rs2[31:30] == 2'h2 | _sat_T_14; // @[Mlu.scala 125:65]
- wire _sat_T_20 = _sat_T_8 & rs1[31:30] == 2'h1; // @[Mlu.scala 127:40]
- wire _sat_T_21 = _sat_T_15 | _sat_T_20; // @[Mlu.scala 126:66]
- wire sat = rs1[29:0] == 30'h0 & rs2[29:0] == 30'h0 & _sat_T_21; // @[Mlu.scala 124:56]
- wire [31:0] _GEN_12 = prod[65] ? 32'h7fffffff : 32'h80000000; // @[Mlu.scala 129:25 130:16 132:16]
- wire [31:0] _GEN_13 = sat ? _GEN_12 : prod[62:31]; // @[Mlu.scala 128:18 135:14]
- wire [31:0] _GEN_20 = {{31'd0}, round2}; // @[Mlu.scala 142:23]
- wire _T_22 = ~reset; // @[Mlu.scala 146:11]
- assign io_rd_valid = valid2; // @[Mlu.scala 140:15]
- assign io_rd_addr = addr2; // @[Mlu.scala 141:15]
- assign io_rd_data = mul2 + _GEN_20; // @[Mlu.scala 142:23]
- always @(posedge clock) begin
- if (io_req_0_valid) begin // @[Mlu.scala 70:26]
- addr1 <= io_req_0_addr; // @[Mlu.scala 72:11]
- end else if (io_req_1_valid) begin // @[Mlu.scala 74:33]
- addr1 <= io_req_1_addr; // @[Mlu.scala 76:11]
- end else if (io_req_2_valid) begin // @[Mlu.scala 78:33]
- addr1 <= io_req_2_addr; // @[Mlu.scala 80:11]
- end else if (io_req_3_valid) begin // @[Mlu.scala 82:33]
- addr1 <= io_req_3_addr; // @[Mlu.scala 84:11]
- end
- if (valid1) begin // @[Mlu.scala 105:17]
- addr2 <= addr1; // @[Mlu.scala 113:11]
- end
- if (io_req_0_valid) begin // @[Mlu.scala 70:26]
- sel <= 4'h1; // @[Mlu.scala 73:9]
- end else if (io_req_1_valid) begin // @[Mlu.scala 74:33]
- sel <= 4'h2; // @[Mlu.scala 77:9]
- end else if (io_req_2_valid) begin // @[Mlu.scala 78:33]
- sel <= 4'h4; // @[Mlu.scala 81:9]
- end else if (io_req_3_valid) begin // @[Mlu.scala 82:33]
- sel <= 4'h8; // @[Mlu.scala 85:9]
- end else begin
- sel <= 4'h0; // @[Mlu.scala 88:9]
- end
- if (valid1) begin // @[Mlu.scala 105:17]
- if (op[0]) begin // @[Mlu.scala 117:24]
- mul2 <= prod[31:0]; // @[Mlu.scala 118:12]
- end else if (op[1] | op[2] | op[3] | op[4] | op[5] | op[6]) begin // @[Mlu.scala 119:121]
- mul2 <= prod[63:32]; // @[Mlu.scala 120:12]
- end else if (op[7] | op[8]) begin // @[Mlu.scala 121:51]
- mul2 <= _GEN_13;
- end
- end
- if (valid1) begin // @[Mlu.scala 105:17]
- round2 <= prod[30] & op[8] | _round2_T_9; // @[Mlu.scala 114:12]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(_rs1_T_1 & ~io_rs1_0_valid))) begin
- $fatal; // @[Mlu.scala 146:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(_rs1_T_1 & ~io_rs1_0_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Mlu.scala:146 assert(!(valid1 && sel(i) && !io.rs1(i).valid))\n"); // @[Mlu.scala 146:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_22 & ~(~(_rs1_T_1 & ~io_rs2_0_valid))) begin
- $fatal; // @[Mlu.scala 147:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_22 & ~(~(_rs1_T_1 & ~io_rs2_0_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Mlu.scala:147 assert(!(valid1 && sel(i) && !io.rs2(i).valid))\n"); // @[Mlu.scala 147:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(_rs1_T_4 & ~io_rs1_1_valid))) begin
- $fatal; // @[Mlu.scala 146:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(_rs1_T_4 & ~io_rs1_1_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Mlu.scala:146 assert(!(valid1 && sel(i) && !io.rs1(i).valid))\n"); // @[Mlu.scala 146:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_22 & ~(~(_rs1_T_4 & ~io_rs2_1_valid))) begin
- $fatal; // @[Mlu.scala 147:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_22 & ~(~(_rs1_T_4 & ~io_rs2_1_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Mlu.scala:147 assert(!(valid1 && sel(i) && !io.rs2(i).valid))\n"); // @[Mlu.scala 147:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(_rs1_T_8 & ~io_rs1_2_valid))) begin
- $fatal; // @[Mlu.scala 146:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(_rs1_T_8 & ~io_rs1_2_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Mlu.scala:146 assert(!(valid1 && sel(i) && !io.rs1(i).valid))\n"); // @[Mlu.scala 146:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_22 & ~(~(_rs1_T_8 & ~io_rs2_2_valid))) begin
- $fatal; // @[Mlu.scala 147:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_22 & ~(~(_rs1_T_8 & ~io_rs2_2_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Mlu.scala:147 assert(!(valid1 && sel(i) && !io.rs2(i).valid))\n"); // @[Mlu.scala 147:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(_rs1_T_12 & ~io_rs1_3_valid))) begin
- $fatal; // @[Mlu.scala 146:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(_rs1_T_12 & ~io_rs1_3_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Mlu.scala:146 assert(!(valid1 && sel(i) && !io.rs1(i).valid))\n"); // @[Mlu.scala 146:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_22 & ~(~(_rs1_T_12 & ~io_rs2_3_valid))) begin
- $fatal; // @[Mlu.scala 147:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_22 & ~(~(_rs1_T_12 & ~io_rs2_3_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Mlu.scala:147 assert(!(valid1 && sel(i) && !io.rs2(i).valid))\n"); // @[Mlu.scala 147:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Mlu.scala 70:26]
- op <= 9'h0; // @[Mlu.scala 71:8]
- end else if (io_req_0_valid) begin // @[Mlu.scala 74:33]
- op <= io_req_0_op; // @[Mlu.scala 75:8]
- end else if (io_req_1_valid) begin // @[Mlu.scala 78:33]
- op <= io_req_1_op; // @[Mlu.scala 79:8]
- end else if (io_req_2_valid) begin // @[Mlu.scala 82:33]
- op <= io_req_2_op; // @[Mlu.scala 83:8]
- end else if (io_req_3_valid) begin // @[Mlu.scala 87:8]
- op <= io_req_3_op;
- end else begin
- op <= 9'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Mlu.scala 67:29]
- valid1 <= 1'h0;
- end else begin
- valid1 <= _valid1_T_1 | io_req_3_valid;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Mlu.scala 61:23]
- valid2 <= 1'h0; // @[Mlu.scala 61:23]
- end else begin
- valid2 <= valid1; // @[Mlu.scala 68:10]
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- op = _RAND_0[8:0];
- _RAND_1 = {1{`RANDOM}};
- valid1 = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- valid2 = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- addr1 = _RAND_3[4:0];
- _RAND_4 = {1{`RANDOM}};
- addr2 = _RAND_4[4:0];
- _RAND_5 = {1{`RANDOM}};
- sel = _RAND_5[3:0];
- _RAND_6 = {1{`RANDOM}};
- mul2 = _RAND_6[31:0];
- _RAND_7 = {1{`RANDOM}};
- round2 = _RAND_7[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- op = 9'h0;
- end
- if (reset) begin
- valid1 = 1'h0;
- end
- if (reset) begin
- valid2 = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Dvu(
- input clock,
- input reset,
- input io_req_valid,
- output io_req_ready,
- input [4:0] io_req_addr,
- input [3:0] io_req_op,
- input [31:0] io_rs1_data,
- input [31:0] io_rs2_data,
- output io_rd_valid,
- input io_rd_ready,
- output [4:0] io_rd_addr,
- output [31:0] io_rd_data
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
-`endif // RANDOMIZE_REG_INIT
- reg active; // @[Dvu.scala 80:23]
- reg compute; // @[Dvu.scala 81:24]
- reg [4:0] addr1; // @[Dvu.scala 83:21]
- reg signed1; // @[Dvu.scala 84:21]
- reg divide1; // @[Dvu.scala 85:21]
- reg [4:0] addr2; // @[Dvu.scala 86:21]
- reg signed2d; // @[Dvu.scala 87:21]
- reg signed2r; // @[Dvu.scala 88:21]
- reg divide2; // @[Dvu.scala 89:21]
- reg [5:0] count; // @[Dvu.scala 91:23]
- reg [31:0] divide; // @[Dvu.scala 93:19]
- reg [31:0] remain; // @[Dvu.scala 94:19]
- reg [31:0] denom; // @[Dvu.scala 95:19]
- wire divByZero = io_rs2_data == 32'h0; // @[Dvu.scala 97:31]
- wire _io_req_ready_T_1 = ~compute; // @[Dvu.scala 99:30]
- wire _T = io_req_valid & io_req_ready; // @[Dvu.scala 108:22]
- wire _GEN_0 = count == 6'h1e ? 1'h0 : active; // @[Dvu.scala 110:32 111:12 80:23]
- wire _signed2r_T_1 = signed1 & io_rs1_data[31]; // @[Dvu.scala 126:25]
- wire [31:0] _inp_T_2 = ~io_rs1_data; // @[Dvu.scala 129:47]
- wire [31:0] _inp_T_4 = _inp_T_2 + 32'h1; // @[Dvu.scala 129:60]
- wire [31:0] inp = _signed2r_T_1 ? _inp_T_4 : io_rs1_data; // @[Dvu.scala 129:18]
- wire [15:0] _GEN_19 = {{8'd0}, inp[15:8]}; // @[Bitwise.scala 105:31]
- wire [15:0] _clz_T_7 = _GEN_19 & 16'hff; // @[Bitwise.scala 105:31]
- wire [15:0] _clz_T_9 = {inp[7:0], 8'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _clz_T_11 = _clz_T_9 & 16'hff00; // @[Bitwise.scala 105:80]
- wire [15:0] _clz_T_12 = _clz_T_7 | _clz_T_11; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_20 = {{4'd0}, _clz_T_12[15:4]}; // @[Bitwise.scala 105:31]
- wire [15:0] _clz_T_17 = _GEN_20 & 16'hf0f; // @[Bitwise.scala 105:31]
- wire [15:0] _clz_T_19 = {_clz_T_12[11:0], 4'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _clz_T_21 = _clz_T_19 & 16'hf0f0; // @[Bitwise.scala 105:80]
- wire [15:0] _clz_T_22 = _clz_T_17 | _clz_T_21; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_21 = {{2'd0}, _clz_T_22[15:2]}; // @[Bitwise.scala 105:31]
- wire [15:0] _clz_T_27 = _GEN_21 & 16'h3333; // @[Bitwise.scala 105:31]
- wire [15:0] _clz_T_29 = {_clz_T_22[13:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _clz_T_31 = _clz_T_29 & 16'hcccc; // @[Bitwise.scala 105:80]
- wire [15:0] _clz_T_32 = _clz_T_27 | _clz_T_31; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_22 = {{1'd0}, _clz_T_32[15:1]}; // @[Bitwise.scala 105:31]
- wire [15:0] _clz_T_37 = _GEN_22 & 16'h5555; // @[Bitwise.scala 105:31]
- wire [15:0] _clz_T_39 = {_clz_T_32[14:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _clz_T_41 = _clz_T_39 & 16'haaaa; // @[Bitwise.scala 105:80]
- wire [15:0] _clz_T_42 = _clz_T_37 | _clz_T_41; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_23 = {{4'd0}, inp[23:20]}; // @[Bitwise.scala 105:31]
- wire [7:0] _clz_T_48 = _GEN_23 & 8'hf; // @[Bitwise.scala 105:31]
- wire [7:0] _clz_T_50 = {inp[19:16], 4'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _clz_T_52 = _clz_T_50 & 8'hf0; // @[Bitwise.scala 105:80]
- wire [7:0] _clz_T_53 = _clz_T_48 | _clz_T_52; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_24 = {{2'd0}, _clz_T_53[7:2]}; // @[Bitwise.scala 105:31]
- wire [7:0] _clz_T_58 = _GEN_24 & 8'h33; // @[Bitwise.scala 105:31]
- wire [7:0] _clz_T_60 = {_clz_T_53[5:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _clz_T_62 = _clz_T_60 & 8'hcc; // @[Bitwise.scala 105:80]
- wire [7:0] _clz_T_63 = _clz_T_58 | _clz_T_62; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_25 = {{1'd0}, _clz_T_63[7:1]}; // @[Bitwise.scala 105:31]
- wire [7:0] _clz_T_68 = _GEN_25 & 8'h55; // @[Bitwise.scala 105:31]
- wire [7:0] _clz_T_70 = {_clz_T_63[6:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _clz_T_72 = _clz_T_70 & 8'haa; // @[Bitwise.scala 105:80]
- wire [7:0] _clz_T_73 = _clz_T_68 | _clz_T_72; // @[Bitwise.scala 105:39]
- wire [30:0] _clz_T_94 = {_clz_T_42,_clz_T_73,inp[24],inp[25],inp[26],inp[27],inp[28],inp[29],inp[30]}; // @[Cat.scala 31:58]
- wire [4:0] _clz_T_126 = _clz_T_94[29] ? 5'h1d : 5'h1e; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_127 = _clz_T_94[28] ? 5'h1c : _clz_T_126; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_128 = _clz_T_94[27] ? 5'h1b : _clz_T_127; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_129 = _clz_T_94[26] ? 5'h1a : _clz_T_128; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_130 = _clz_T_94[25] ? 5'h19 : _clz_T_129; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_131 = _clz_T_94[24] ? 5'h18 : _clz_T_130; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_132 = _clz_T_94[23] ? 5'h17 : _clz_T_131; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_133 = _clz_T_94[22] ? 5'h16 : _clz_T_132; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_134 = _clz_T_94[21] ? 5'h15 : _clz_T_133; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_135 = _clz_T_94[20] ? 5'h14 : _clz_T_134; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_136 = _clz_T_94[19] ? 5'h13 : _clz_T_135; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_137 = _clz_T_94[18] ? 5'h12 : _clz_T_136; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_138 = _clz_T_94[17] ? 5'h11 : _clz_T_137; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_139 = _clz_T_94[16] ? 5'h10 : _clz_T_138; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_140 = _clz_T_94[15] ? 5'hf : _clz_T_139; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_141 = _clz_T_94[14] ? 5'he : _clz_T_140; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_142 = _clz_T_94[13] ? 5'hd : _clz_T_141; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_143 = _clz_T_94[12] ? 5'hc : _clz_T_142; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_144 = _clz_T_94[11] ? 5'hb : _clz_T_143; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_145 = _clz_T_94[10] ? 5'ha : _clz_T_144; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_146 = _clz_T_94[9] ? 5'h9 : _clz_T_145; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_147 = _clz_T_94[8] ? 5'h8 : _clz_T_146; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_148 = _clz_T_94[7] ? 5'h7 : _clz_T_147; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_149 = _clz_T_94[6] ? 5'h6 : _clz_T_148; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_150 = _clz_T_94[5] ? 5'h5 : _clz_T_149; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_151 = _clz_T_94[4] ? 5'h4 : _clz_T_150; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_152 = _clz_T_94[3] ? 5'h3 : _clz_T_151; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_153 = _clz_T_94[2] ? 5'h2 : _clz_T_152; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_154 = _clz_T_94[1] ? 5'h1 : _clz_T_153; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_155 = _clz_T_94[0] ? 5'h0 : _clz_T_154; // @[Mux.scala 47:70]
- wire [4:0] _clz_T_156 = inp[31] ? 5'h0 : _clz_T_155; // @[Dvu.scala 104:8]
- wire [4:0] clz = divByZero ? 5'h0 : _clz_T_156; // @[Dvu.scala 133:18]
- wire [31:0] _denom_T_2 = ~io_rs2_data; // @[Dvu.scala 135:47]
- wire [31:0] _denom_T_4 = _denom_T_2 + 32'h1; // @[Dvu.scala 135:60]
- wire [62:0] _GEN_1 = {{31'd0}, inp}; // @[Dvu.scala 136:19]
- wire [62:0] _divide_T = _GEN_1 << clz; // @[Dvu.scala 136:19]
- wire [31:0] shfRemain = {remain[30:0],divide[31]}; // @[Cat.scala 31:58]
- wire [32:0] subtract = shfRemain - denom; // @[Dvu.scala 64:30]
- wire [31:0] _divDivide_T_1 = {divide[30:0],1'h1}; // @[Cat.scala 31:58]
- wire [31:0] _divDivide_T_3 = {divide[30:0],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] div = ~subtract[32] ? _divDivide_T_1 : _divDivide_T_3; // @[Dvu.scala 69:26 70:17 73:17]
- wire [5:0] _count_T_1 = count + 6'h1; // @[Dvu.scala 143:20]
- wire [31:0] _GEN_8 = compute & count < 6'h20 ? div : divide; // @[Dvu.scala 139:41 141:12 93:19]
- wire [62:0] _GEN_16 = active & _io_req_ready_T_1 ? _divide_T : {{31'd0}, _GEN_8}; // @[Dvu.scala 123:29 136:12]
- wire [31:0] _div_T = ~divide; // @[Dvu.scala 148:27]
- wire [31:0] _div_T_2 = _div_T + 32'h1; // @[Dvu.scala 148:35]
- wire [31:0] div_1 = signed2d ? _div_T_2 : divide; // @[Dvu.scala 148:16]
- wire [31:0] _rem_T = ~remain; // @[Dvu.scala 149:27]
- wire [31:0] _rem_T_2 = _rem_T + 32'h1; // @[Dvu.scala 149:35]
- wire [31:0] rem_1 = signed2r ? _rem_T_2 : remain; // @[Dvu.scala 149:16]
- assign io_req_ready = ~active & ~compute & ~count[5]; // @[Dvu.scala 99:39]
- assign io_rd_valid = count[5]; // @[Dvu.scala 151:23]
- assign io_rd_addr = addr2; // @[Dvu.scala 152:14]
- assign io_rd_data = divide2 ? div_1 : rem_1; // @[Dvu.scala 153:20]
- always @(posedge clock) begin
- if (_T) begin // @[Dvu.scala 117:39]
- addr1 <= io_req_addr; // @[Dvu.scala 118:13]
- end
- if (_T) begin // @[Dvu.scala 117:39]
- signed1 <= io_req_op[0] | io_req_op[2]; // @[Dvu.scala 119:13]
- end
- if (_T) begin // @[Dvu.scala 117:39]
- divide1 <= io_req_op[0] | io_req_op[1]; // @[Dvu.scala 120:13]
- end
- if (active & _io_req_ready_T_1) begin // @[Dvu.scala 123:29]
- addr2 <= addr1; // @[Dvu.scala 124:14]
- end
- if (active & _io_req_ready_T_1) begin // @[Dvu.scala 123:29]
- signed2d <= signed1 & io_rs1_data[31] != io_rs2_data[31] & ~divByZero; // @[Dvu.scala 125:14]
- end
- if (active & _io_req_ready_T_1) begin // @[Dvu.scala 123:29]
- signed2r <= signed1 & io_rs1_data[31]; // @[Dvu.scala 126:14]
- end
- if (active & _io_req_ready_T_1) begin // @[Dvu.scala 123:29]
- divide2 <= divide1; // @[Dvu.scala 127:14]
- end
- divide <= _GEN_16[31:0];
- if (active & _io_req_ready_T_1) begin // @[Dvu.scala 123:29]
- remain <= 32'h0; // @[Dvu.scala 137:12]
- end else if (compute & count < 6'h20) begin // @[Dvu.scala 139:41]
- if (~subtract[32]) begin // @[Dvu.scala 69:26]
- remain <= subtract[31:0]; // @[Dvu.scala 71:17]
- end else begin
- remain <= shfRemain; // @[Dvu.scala 74:17]
- end
- end
- if (active & _io_req_ready_T_1) begin // @[Dvu.scala 123:29]
- if (signed1 & io_rs2_data[31]) begin // @[Dvu.scala 135:18]
- denom <= _denom_T_4;
- end else begin
- denom <= io_rs2_data;
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Dvu.scala 108:39]
- active <= 1'h0; // @[Dvu.scala 109:12]
- end else begin
- active <= io_req_valid & io_req_ready | _GEN_0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Dvu.scala 81:24]
- compute <= 1'h0; // @[Dvu.scala 81:24]
- end else begin
- compute <= active; // @[Dvu.scala 115:11]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Dvu.scala 123:29]
- count <= 6'h0; // @[Dvu.scala 138:12]
- end else if (active & _io_req_ready_T_1) begin // @[Dvu.scala 139:41]
- count <= {{1'd0}, clz}; // @[Dvu.scala 143:11]
- end else if (compute & count < 6'h20) begin // @[Dvu.scala 144:44]
- count <= _count_T_1; // @[Dvu.scala 145:11]
- end else if (io_rd_valid & io_rd_ready) begin // @[Dvu.scala 91:23]
- count <= 6'h0;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- active = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- compute = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- addr1 = _RAND_2[4:0];
- _RAND_3 = {1{`RANDOM}};
- signed1 = _RAND_3[0:0];
- _RAND_4 = {1{`RANDOM}};
- divide1 = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- addr2 = _RAND_5[4:0];
- _RAND_6 = {1{`RANDOM}};
- signed2d = _RAND_6[0:0];
- _RAND_7 = {1{`RANDOM}};
- signed2r = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- divide2 = _RAND_8[0:0];
- _RAND_9 = {1{`RANDOM}};
- count = _RAND_9[5:0];
- _RAND_10 = {1{`RANDOM}};
- divide = _RAND_10[31:0];
- _RAND_11 = {1{`RANDOM}};
- remain = _RAND_11[31:0];
- _RAND_12 = {1{`RANDOM}};
- denom = _RAND_12[31:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- active = 1'h0;
- end
- if (reset) begin
- compute = 1'h0;
- end
- if (reset) begin
- count = 6'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module SCore(
- input clock,
- input reset,
- input [31:0] io_csr_in_value_0,
- output io_halted,
- output io_fault,
- output io_ibus_valid,
- input io_ibus_ready,
- output [31:0] io_ibus_addr,
- input [255:0] io_ibus_rdata,
- output io_dbus_valid,
- input io_dbus_ready,
- output io_dbus_write,
- output [31:0] io_dbus_addr,
- output [31:0] io_dbus_adrx,
- output [5:0] io_dbus_size,
- output [255:0] io_dbus_wdata,
- output [31:0] io_dbus_wmask,
- input [255:0] io_dbus_rdata,
- output io_ubus_valid,
- input io_ubus_ready,
- output io_ubus_write,
- output [31:0] io_ubus_addr,
- output [255:0] io_ubus_wdata,
- output [31:0] io_ubus_wmask,
- input [255:0] io_ubus_rdata,
- output io_vldst,
- output io_vcore_vinst_0_valid,
- input io_vcore_vinst_0_ready,
- output [4:0] io_vcore_vinst_0_addr,
- output [31:0] io_vcore_vinst_0_inst,
- output [4:0] io_vcore_vinst_0_op,
- output io_vcore_vinst_1_valid,
- input io_vcore_vinst_1_ready,
- output [4:0] io_vcore_vinst_1_addr,
- output [31:0] io_vcore_vinst_1_inst,
- output [4:0] io_vcore_vinst_1_op,
- output io_vcore_vinst_2_valid,
- input io_vcore_vinst_2_ready,
- output [4:0] io_vcore_vinst_2_addr,
- output [31:0] io_vcore_vinst_2_inst,
- output [4:0] io_vcore_vinst_2_op,
- output io_vcore_vinst_3_valid,
- input io_vcore_vinst_3_ready,
- output [4:0] io_vcore_vinst_3_addr,
- output [31:0] io_vcore_vinst_3_inst,
- output [4:0] io_vcore_vinst_3_op,
- output [31:0] io_vcore_rs_0_data,
- output [31:0] io_vcore_rs_1_data,
- output [31:0] io_vcore_rs_2_data,
- output [31:0] io_vcore_rs_3_data,
- output [31:0] io_vcore_rs_4_data,
- output [31:0] io_vcore_rs_5_data,
- output [31:0] io_vcore_rs_6_data,
- output [31:0] io_vcore_rs_7_data,
- input io_vcore_rd_0_valid,
- input [4:0] io_vcore_rd_0_addr,
- input [31:0] io_vcore_rd_0_data,
- input io_vcore_rd_1_valid,
- input [4:0] io_vcore_rd_1_addr,
- input [31:0] io_vcore_rd_1_data,
- input io_vcore_rd_2_valid,
- input [4:0] io_vcore_rd_2_addr,
- input [31:0] io_vcore_rd_2_data,
- input io_vcore_rd_3_valid,
- input [4:0] io_vcore_rd_3_addr,
- input [31:0] io_vcore_rd_3_data,
- input io_vcore_mactive,
- input io_vcore_undef,
- output io_iflush_valid,
- output io_dflush_valid,
- input io_dflush_ready,
- output io_dflush_all,
- output io_slog_valid,
- output [4:0] io_slog_addr,
- output [31:0] io_slog_data
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
-`endif // RANDOMIZE_REG_INIT
- wire regfile_clock; // @[Regfile.scala 27:18]
- wire regfile_reset; // @[Regfile.scala 27:18]
- wire regfile_io_readAddr_0_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_readAddr_0_addr; // @[Regfile.scala 27:18]
- wire regfile_io_readAddr_1_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_readAddr_1_addr; // @[Regfile.scala 27:18]
- wire regfile_io_readAddr_2_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_readAddr_2_addr; // @[Regfile.scala 27:18]
- wire regfile_io_readAddr_3_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_readAddr_3_addr; // @[Regfile.scala 27:18]
- wire regfile_io_readAddr_4_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_readAddr_4_addr; // @[Regfile.scala 27:18]
- wire regfile_io_readAddr_5_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_readAddr_5_addr; // @[Regfile.scala 27:18]
- wire regfile_io_readAddr_6_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_readAddr_6_addr; // @[Regfile.scala 27:18]
- wire regfile_io_readAddr_7_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_readAddr_7_addr; // @[Regfile.scala 27:18]
- wire regfile_io_readSet_0_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readSet_0_value; // @[Regfile.scala 27:18]
- wire regfile_io_readSet_1_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readSet_1_value; // @[Regfile.scala 27:18]
- wire regfile_io_readSet_2_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readSet_2_value; // @[Regfile.scala 27:18]
- wire regfile_io_readSet_3_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readSet_3_value; // @[Regfile.scala 27:18]
- wire regfile_io_readSet_4_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readSet_4_value; // @[Regfile.scala 27:18]
- wire regfile_io_readSet_5_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readSet_5_value; // @[Regfile.scala 27:18]
- wire regfile_io_readSet_6_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readSet_6_value; // @[Regfile.scala 27:18]
- wire regfile_io_readSet_7_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readSet_7_value; // @[Regfile.scala 27:18]
- wire regfile_io_writeAddr_0_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_writeAddr_0_addr; // @[Regfile.scala 27:18]
- wire regfile_io_writeAddr_1_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_writeAddr_1_addr; // @[Regfile.scala 27:18]
- wire regfile_io_writeAddr_2_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_writeAddr_2_addr; // @[Regfile.scala 27:18]
- wire regfile_io_writeAddr_3_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_writeAddr_3_addr; // @[Regfile.scala 27:18]
- wire regfile_io_busAddr_0_bypass; // @[Regfile.scala 27:18]
- wire regfile_io_busAddr_0_immen; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_busAddr_0_immed; // @[Regfile.scala 27:18]
- wire regfile_io_busAddr_1_bypass; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_busAddr_1_immed; // @[Regfile.scala 27:18]
- wire regfile_io_busAddr_2_bypass; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_busAddr_2_immed; // @[Regfile.scala 27:18]
- wire regfile_io_busAddr_3_bypass; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_busAddr_3_immed; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_target_0_data; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_target_1_data; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_target_2_data; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_target_3_data; // @[Regfile.scala 27:18]
- wire regfile_io_linkPort_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_linkPort_value; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_busPort_addr_0; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_busPort_addr_1; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_busPort_addr_2; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_busPort_addr_3; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_busPort_data_0; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_busPort_data_1; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_busPort_data_2; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_busPort_data_3; // @[Regfile.scala 27:18]
- wire regfile_io_readData_0_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readData_0_data; // @[Regfile.scala 27:18]
- wire regfile_io_readData_1_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readData_1_data; // @[Regfile.scala 27:18]
- wire regfile_io_readData_2_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readData_2_data; // @[Regfile.scala 27:18]
- wire regfile_io_readData_3_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readData_3_data; // @[Regfile.scala 27:18]
- wire regfile_io_readData_4_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readData_4_data; // @[Regfile.scala 27:18]
- wire regfile_io_readData_5_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readData_5_data; // @[Regfile.scala 27:18]
- wire regfile_io_readData_6_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readData_6_data; // @[Regfile.scala 27:18]
- wire regfile_io_readData_7_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_readData_7_data; // @[Regfile.scala 27:18]
- wire regfile_io_writeData_0_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_writeData_0_addr; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_writeData_0_data; // @[Regfile.scala 27:18]
- wire regfile_io_writeData_1_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_writeData_1_addr; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_writeData_1_data; // @[Regfile.scala 27:18]
- wire regfile_io_writeData_2_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_writeData_2_addr; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_writeData_2_data; // @[Regfile.scala 27:18]
- wire regfile_io_writeData_3_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_writeData_3_addr; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_writeData_3_data; // @[Regfile.scala 27:18]
- wire regfile_io_writeData_4_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_writeData_4_addr; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_writeData_4_data; // @[Regfile.scala 27:18]
- wire regfile_io_writeData_5_valid; // @[Regfile.scala 27:18]
- wire [4:0] regfile_io_writeData_5_addr; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_writeData_5_data; // @[Regfile.scala 27:18]
- wire regfile_io_writeMask_0_valid; // @[Regfile.scala 27:18]
- wire regfile_io_writeMask_1_valid; // @[Regfile.scala 27:18]
- wire regfile_io_writeMask_2_valid; // @[Regfile.scala 27:18]
- wire regfile_io_writeMask_3_valid; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_scoreboard_regd; // @[Regfile.scala 27:18]
- wire [31:0] regfile_io_scoreboard_comb; // @[Regfile.scala 27:18]
- wire fetch_clock; // @[Fetch.scala 28:18]
- wire fetch_reset; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_csr_value_0; // @[Fetch.scala 28:18]
- wire fetch_io_ibus_valid; // @[Fetch.scala 28:18]
- wire fetch_io_ibus_ready; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_ibus_addr; // @[Fetch.scala 28:18]
- wire [255:0] fetch_io_ibus_rdata; // @[Fetch.scala 28:18]
- wire fetch_io_inst_lanes_0_valid; // @[Fetch.scala 28:18]
- wire fetch_io_inst_lanes_0_ready; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_inst_lanes_0_addr; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_inst_lanes_0_inst; // @[Fetch.scala 28:18]
- wire fetch_io_inst_lanes_0_brchFwd; // @[Fetch.scala 28:18]
- wire fetch_io_inst_lanes_1_valid; // @[Fetch.scala 28:18]
- wire fetch_io_inst_lanes_1_ready; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_inst_lanes_1_addr; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_inst_lanes_1_inst; // @[Fetch.scala 28:18]
- wire fetch_io_inst_lanes_1_brchFwd; // @[Fetch.scala 28:18]
- wire fetch_io_inst_lanes_2_valid; // @[Fetch.scala 28:18]
- wire fetch_io_inst_lanes_2_ready; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_inst_lanes_2_addr; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_inst_lanes_2_inst; // @[Fetch.scala 28:18]
- wire fetch_io_inst_lanes_2_brchFwd; // @[Fetch.scala 28:18]
- wire fetch_io_inst_lanes_3_valid; // @[Fetch.scala 28:18]
- wire fetch_io_inst_lanes_3_ready; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_inst_lanes_3_addr; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_inst_lanes_3_inst; // @[Fetch.scala 28:18]
- wire fetch_io_inst_lanes_3_brchFwd; // @[Fetch.scala 28:18]
- wire fetch_io_branch_0_valid; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_branch_0_value; // @[Fetch.scala 28:18]
- wire fetch_io_branch_1_valid; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_branch_1_value; // @[Fetch.scala 28:18]
- wire fetch_io_branch_2_valid; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_branch_2_value; // @[Fetch.scala 28:18]
- wire fetch_io_branch_3_valid; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_branch_3_value; // @[Fetch.scala 28:18]
- wire fetch_io_linkPort_valid; // @[Fetch.scala 28:18]
- wire [31:0] fetch_io_linkPort_value; // @[Fetch.scala 28:18]
- wire fetch_io_iflush_valid; // @[Fetch.scala 28:18]
- wire fetch_io_iflush_ready; // @[Fetch.scala 28:18]
- wire decode_0_clock; // @[Decode.scala 29:18]
- wire decode_0_reset; // @[Decode.scala 29:18]
- wire decode_0_io_halted; // @[Decode.scala 29:18]
- wire decode_0_io_inst_valid; // @[Decode.scala 29:18]
- wire decode_0_io_inst_ready; // @[Decode.scala 29:18]
- wire [31:0] decode_0_io_inst_addr; // @[Decode.scala 29:18]
- wire [31:0] decode_0_io_inst_inst; // @[Decode.scala 29:18]
- wire decode_0_io_inst_brchFwd; // @[Decode.scala 29:18]
- wire [31:0] decode_0_io_scoreboard_regd; // @[Decode.scala 29:18]
- wire [31:0] decode_0_io_scoreboard_comb; // @[Decode.scala 29:18]
- wire [31:0] decode_0_io_scoreboard_spec; // @[Decode.scala 29:18]
- wire decode_0_io_mactive; // @[Decode.scala 29:18]
- wire decode_0_io_rs1Read_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_0_io_rs1Read_addr; // @[Decode.scala 29:18]
- wire decode_0_io_rs1Set_valid; // @[Decode.scala 29:18]
- wire [31:0] decode_0_io_rs1Set_value; // @[Decode.scala 29:18]
- wire decode_0_io_rs2Read_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_0_io_rs2Read_addr; // @[Decode.scala 29:18]
- wire decode_0_io_rs2Set_valid; // @[Decode.scala 29:18]
- wire [31:0] decode_0_io_rs2Set_value; // @[Decode.scala 29:18]
- wire decode_0_io_rdMark_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_0_io_rdMark_addr; // @[Decode.scala 29:18]
- wire decode_0_io_busRead_bypass; // @[Decode.scala 29:18]
- wire decode_0_io_busRead_immen; // @[Decode.scala 29:18]
- wire [31:0] decode_0_io_busRead_immed; // @[Decode.scala 29:18]
- wire decode_0_io_alu_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_0_io_alu_addr; // @[Decode.scala 29:18]
- wire [17:0] decode_0_io_alu_op; // @[Decode.scala 29:18]
- wire decode_0_io_bru_valid; // @[Decode.scala 29:18]
- wire decode_0_io_bru_fwd; // @[Decode.scala 29:18]
- wire [16:0] decode_0_io_bru_op; // @[Decode.scala 29:18]
- wire [31:0] decode_0_io_bru_pc; // @[Decode.scala 29:18]
- wire [31:0] decode_0_io_bru_target; // @[Decode.scala 29:18]
- wire [4:0] decode_0_io_bru_link; // @[Decode.scala 29:18]
- wire decode_0_io_csr_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_0_io_csr_addr; // @[Decode.scala 29:18]
- wire [11:0] decode_0_io_csr_index; // @[Decode.scala 29:18]
- wire [2:0] decode_0_io_csr_op; // @[Decode.scala 29:18]
- wire decode_0_io_lsu_valid; // @[Decode.scala 29:18]
- wire decode_0_io_lsu_ready; // @[Decode.scala 29:18]
- wire [4:0] decode_0_io_lsu_addr; // @[Decode.scala 29:18]
- wire [11:0] decode_0_io_lsu_op; // @[Decode.scala 29:18]
- wire decode_0_io_mlu_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_0_io_mlu_addr; // @[Decode.scala 29:18]
- wire [8:0] decode_0_io_mlu_op; // @[Decode.scala 29:18]
- wire decode_0_io_dvu_valid; // @[Decode.scala 29:18]
- wire decode_0_io_dvu_ready; // @[Decode.scala 29:18]
- wire [4:0] decode_0_io_dvu_addr; // @[Decode.scala 29:18]
- wire [3:0] decode_0_io_dvu_op; // @[Decode.scala 29:18]
- wire decode_0_io_vinst_valid; // @[Decode.scala 29:18]
- wire decode_0_io_vinst_ready; // @[Decode.scala 29:18]
- wire [4:0] decode_0_io_vinst_addr; // @[Decode.scala 29:18]
- wire [31:0] decode_0_io_vinst_inst; // @[Decode.scala 29:18]
- wire [4:0] decode_0_io_vinst_op; // @[Decode.scala 29:18]
- wire decode_0_io_branchTaken; // @[Decode.scala 29:18]
- wire decode_0_io_interlock; // @[Decode.scala 29:18]
- wire decode_0_io_serializeOut_mul; // @[Decode.scala 29:18]
- wire decode_0_io_serializeOut_jump; // @[Decode.scala 29:18]
- wire decode_0_io_serializeOut_brcond; // @[Decode.scala 29:18]
- wire decode_0_io_slog; // @[Decode.scala 29:18]
- wire decode_1_clock; // @[Decode.scala 29:18]
- wire decode_1_reset; // @[Decode.scala 29:18]
- wire decode_1_io_halted; // @[Decode.scala 29:18]
- wire decode_1_io_inst_valid; // @[Decode.scala 29:18]
- wire decode_1_io_inst_ready; // @[Decode.scala 29:18]
- wire [31:0] decode_1_io_inst_addr; // @[Decode.scala 29:18]
- wire [31:0] decode_1_io_inst_inst; // @[Decode.scala 29:18]
- wire decode_1_io_inst_brchFwd; // @[Decode.scala 29:18]
- wire [31:0] decode_1_io_scoreboard_regd; // @[Decode.scala 29:18]
- wire [31:0] decode_1_io_scoreboard_comb; // @[Decode.scala 29:18]
- wire [31:0] decode_1_io_scoreboard_spec; // @[Decode.scala 29:18]
- wire decode_1_io_rs1Read_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_1_io_rs1Read_addr; // @[Decode.scala 29:18]
- wire decode_1_io_rs1Set_valid; // @[Decode.scala 29:18]
- wire [31:0] decode_1_io_rs1Set_value; // @[Decode.scala 29:18]
- wire decode_1_io_rs2Read_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_1_io_rs2Read_addr; // @[Decode.scala 29:18]
- wire decode_1_io_rs2Set_valid; // @[Decode.scala 29:18]
- wire [31:0] decode_1_io_rs2Set_value; // @[Decode.scala 29:18]
- wire decode_1_io_rdMark_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_1_io_rdMark_addr; // @[Decode.scala 29:18]
- wire decode_1_io_busRead_bypass; // @[Decode.scala 29:18]
- wire [31:0] decode_1_io_busRead_immed; // @[Decode.scala 29:18]
- wire decode_1_io_alu_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_1_io_alu_addr; // @[Decode.scala 29:18]
- wire [17:0] decode_1_io_alu_op; // @[Decode.scala 29:18]
- wire decode_1_io_bru_valid; // @[Decode.scala 29:18]
- wire decode_1_io_bru_fwd; // @[Decode.scala 29:18]
- wire [16:0] decode_1_io_bru_op; // @[Decode.scala 29:18]
- wire [31:0] decode_1_io_bru_pc; // @[Decode.scala 29:18]
- wire [31:0] decode_1_io_bru_target; // @[Decode.scala 29:18]
- wire [4:0] decode_1_io_bru_link; // @[Decode.scala 29:18]
- wire [2:0] decode_1_io_csr_op; // @[Decode.scala 29:18]
- wire decode_1_io_lsu_valid; // @[Decode.scala 29:18]
- wire decode_1_io_lsu_ready; // @[Decode.scala 29:18]
- wire [4:0] decode_1_io_lsu_addr; // @[Decode.scala 29:18]
- wire [11:0] decode_1_io_lsu_op; // @[Decode.scala 29:18]
- wire decode_1_io_mlu_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_1_io_mlu_addr; // @[Decode.scala 29:18]
- wire [8:0] decode_1_io_mlu_op; // @[Decode.scala 29:18]
- wire [3:0] decode_1_io_dvu_op; // @[Decode.scala 29:18]
- wire decode_1_io_vinst_valid; // @[Decode.scala 29:18]
- wire decode_1_io_vinst_ready; // @[Decode.scala 29:18]
- wire [4:0] decode_1_io_vinst_addr; // @[Decode.scala 29:18]
- wire [31:0] decode_1_io_vinst_inst; // @[Decode.scala 29:18]
- wire [4:0] decode_1_io_vinst_op; // @[Decode.scala 29:18]
- wire decode_1_io_branchTaken; // @[Decode.scala 29:18]
- wire decode_1_io_interlock; // @[Decode.scala 29:18]
- wire decode_1_io_serializeIn_mul; // @[Decode.scala 29:18]
- wire decode_1_io_serializeIn_jump; // @[Decode.scala 29:18]
- wire decode_1_io_serializeIn_brcond; // @[Decode.scala 29:18]
- wire decode_1_io_serializeOut_mul; // @[Decode.scala 29:18]
- wire decode_1_io_serializeOut_jump; // @[Decode.scala 29:18]
- wire decode_1_io_serializeOut_brcond; // @[Decode.scala 29:18]
- wire decode_2_clock; // @[Decode.scala 29:18]
- wire decode_2_reset; // @[Decode.scala 29:18]
- wire decode_2_io_halted; // @[Decode.scala 29:18]
- wire decode_2_io_inst_valid; // @[Decode.scala 29:18]
- wire decode_2_io_inst_ready; // @[Decode.scala 29:18]
- wire [31:0] decode_2_io_inst_addr; // @[Decode.scala 29:18]
- wire [31:0] decode_2_io_inst_inst; // @[Decode.scala 29:18]
- wire decode_2_io_inst_brchFwd; // @[Decode.scala 29:18]
- wire [31:0] decode_2_io_scoreboard_regd; // @[Decode.scala 29:18]
- wire [31:0] decode_2_io_scoreboard_comb; // @[Decode.scala 29:18]
- wire [31:0] decode_2_io_scoreboard_spec; // @[Decode.scala 29:18]
- wire decode_2_io_rs1Read_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_2_io_rs1Read_addr; // @[Decode.scala 29:18]
- wire decode_2_io_rs1Set_valid; // @[Decode.scala 29:18]
- wire [31:0] decode_2_io_rs1Set_value; // @[Decode.scala 29:18]
- wire decode_2_io_rs2Read_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_2_io_rs2Read_addr; // @[Decode.scala 29:18]
- wire decode_2_io_rs2Set_valid; // @[Decode.scala 29:18]
- wire [31:0] decode_2_io_rs2Set_value; // @[Decode.scala 29:18]
- wire decode_2_io_rdMark_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_2_io_rdMark_addr; // @[Decode.scala 29:18]
- wire decode_2_io_busRead_bypass; // @[Decode.scala 29:18]
- wire [31:0] decode_2_io_busRead_immed; // @[Decode.scala 29:18]
- wire decode_2_io_alu_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_2_io_alu_addr; // @[Decode.scala 29:18]
- wire [17:0] decode_2_io_alu_op; // @[Decode.scala 29:18]
- wire decode_2_io_bru_valid; // @[Decode.scala 29:18]
- wire decode_2_io_bru_fwd; // @[Decode.scala 29:18]
- wire [16:0] decode_2_io_bru_op; // @[Decode.scala 29:18]
- wire [31:0] decode_2_io_bru_pc; // @[Decode.scala 29:18]
- wire [31:0] decode_2_io_bru_target; // @[Decode.scala 29:18]
- wire [4:0] decode_2_io_bru_link; // @[Decode.scala 29:18]
- wire [2:0] decode_2_io_csr_op; // @[Decode.scala 29:18]
- wire decode_2_io_lsu_valid; // @[Decode.scala 29:18]
- wire decode_2_io_lsu_ready; // @[Decode.scala 29:18]
- wire [4:0] decode_2_io_lsu_addr; // @[Decode.scala 29:18]
- wire [11:0] decode_2_io_lsu_op; // @[Decode.scala 29:18]
- wire decode_2_io_mlu_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_2_io_mlu_addr; // @[Decode.scala 29:18]
- wire [8:0] decode_2_io_mlu_op; // @[Decode.scala 29:18]
- wire [3:0] decode_2_io_dvu_op; // @[Decode.scala 29:18]
- wire decode_2_io_vinst_valid; // @[Decode.scala 29:18]
- wire decode_2_io_vinst_ready; // @[Decode.scala 29:18]
- wire [4:0] decode_2_io_vinst_addr; // @[Decode.scala 29:18]
- wire [31:0] decode_2_io_vinst_inst; // @[Decode.scala 29:18]
- wire [4:0] decode_2_io_vinst_op; // @[Decode.scala 29:18]
- wire decode_2_io_branchTaken; // @[Decode.scala 29:18]
- wire decode_2_io_interlock; // @[Decode.scala 29:18]
- wire decode_2_io_serializeIn_mul; // @[Decode.scala 29:18]
- wire decode_2_io_serializeIn_jump; // @[Decode.scala 29:18]
- wire decode_2_io_serializeIn_brcond; // @[Decode.scala 29:18]
- wire decode_2_io_serializeOut_mul; // @[Decode.scala 29:18]
- wire decode_2_io_serializeOut_jump; // @[Decode.scala 29:18]
- wire decode_2_io_serializeOut_brcond; // @[Decode.scala 29:18]
- wire decode_3_clock; // @[Decode.scala 29:18]
- wire decode_3_reset; // @[Decode.scala 29:18]
- wire decode_3_io_halted; // @[Decode.scala 29:18]
- wire decode_3_io_inst_valid; // @[Decode.scala 29:18]
- wire decode_3_io_inst_ready; // @[Decode.scala 29:18]
- wire [31:0] decode_3_io_inst_addr; // @[Decode.scala 29:18]
- wire [31:0] decode_3_io_inst_inst; // @[Decode.scala 29:18]
- wire decode_3_io_inst_brchFwd; // @[Decode.scala 29:18]
- wire [31:0] decode_3_io_scoreboard_regd; // @[Decode.scala 29:18]
- wire [31:0] decode_3_io_scoreboard_comb; // @[Decode.scala 29:18]
- wire decode_3_io_rs1Read_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_3_io_rs1Read_addr; // @[Decode.scala 29:18]
- wire decode_3_io_rs1Set_valid; // @[Decode.scala 29:18]
- wire [31:0] decode_3_io_rs1Set_value; // @[Decode.scala 29:18]
- wire decode_3_io_rs2Read_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_3_io_rs2Read_addr; // @[Decode.scala 29:18]
- wire decode_3_io_rs2Set_valid; // @[Decode.scala 29:18]
- wire [31:0] decode_3_io_rs2Set_value; // @[Decode.scala 29:18]
- wire decode_3_io_rdMark_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_3_io_rdMark_addr; // @[Decode.scala 29:18]
- wire decode_3_io_busRead_bypass; // @[Decode.scala 29:18]
- wire [31:0] decode_3_io_busRead_immed; // @[Decode.scala 29:18]
- wire decode_3_io_alu_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_3_io_alu_addr; // @[Decode.scala 29:18]
- wire [17:0] decode_3_io_alu_op; // @[Decode.scala 29:18]
- wire decode_3_io_bru_valid; // @[Decode.scala 29:18]
- wire decode_3_io_bru_fwd; // @[Decode.scala 29:18]
- wire [16:0] decode_3_io_bru_op; // @[Decode.scala 29:18]
- wire [31:0] decode_3_io_bru_pc; // @[Decode.scala 29:18]
- wire [31:0] decode_3_io_bru_target; // @[Decode.scala 29:18]
- wire [4:0] decode_3_io_bru_link; // @[Decode.scala 29:18]
- wire [2:0] decode_3_io_csr_op; // @[Decode.scala 29:18]
- wire decode_3_io_lsu_valid; // @[Decode.scala 29:18]
- wire decode_3_io_lsu_ready; // @[Decode.scala 29:18]
- wire [4:0] decode_3_io_lsu_addr; // @[Decode.scala 29:18]
- wire [11:0] decode_3_io_lsu_op; // @[Decode.scala 29:18]
- wire decode_3_io_mlu_valid; // @[Decode.scala 29:18]
- wire [4:0] decode_3_io_mlu_addr; // @[Decode.scala 29:18]
- wire [8:0] decode_3_io_mlu_op; // @[Decode.scala 29:18]
- wire [3:0] decode_3_io_dvu_op; // @[Decode.scala 29:18]
- wire decode_3_io_vinst_valid; // @[Decode.scala 29:18]
- wire decode_3_io_vinst_ready; // @[Decode.scala 29:18]
- wire [4:0] decode_3_io_vinst_addr; // @[Decode.scala 29:18]
- wire [31:0] decode_3_io_vinst_inst; // @[Decode.scala 29:18]
- wire [4:0] decode_3_io_vinst_op; // @[Decode.scala 29:18]
- wire decode_3_io_branchTaken; // @[Decode.scala 29:18]
- wire decode_3_io_interlock; // @[Decode.scala 29:18]
- wire decode_3_io_serializeIn_mul; // @[Decode.scala 29:18]
- wire decode_3_io_serializeIn_jump; // @[Decode.scala 29:18]
- wire decode_3_io_serializeIn_brcond; // @[Decode.scala 29:18]
- wire alu_0_clock; // @[Alu.scala 23:18]
- wire alu_0_reset; // @[Alu.scala 23:18]
- wire alu_0_io_req_valid; // @[Alu.scala 23:18]
- wire [4:0] alu_0_io_req_addr; // @[Alu.scala 23:18]
- wire [17:0] alu_0_io_req_op; // @[Alu.scala 23:18]
- wire alu_0_io_rs1_valid; // @[Alu.scala 23:18]
- wire [31:0] alu_0_io_rs1_data; // @[Alu.scala 23:18]
- wire alu_0_io_rs2_valid; // @[Alu.scala 23:18]
- wire [31:0] alu_0_io_rs2_data; // @[Alu.scala 23:18]
- wire alu_0_io_rd_valid; // @[Alu.scala 23:18]
- wire [4:0] alu_0_io_rd_addr; // @[Alu.scala 23:18]
- wire [31:0] alu_0_io_rd_data; // @[Alu.scala 23:18]
- wire alu_1_clock; // @[Alu.scala 23:18]
- wire alu_1_reset; // @[Alu.scala 23:18]
- wire alu_1_io_req_valid; // @[Alu.scala 23:18]
- wire [4:0] alu_1_io_req_addr; // @[Alu.scala 23:18]
- wire [17:0] alu_1_io_req_op; // @[Alu.scala 23:18]
- wire alu_1_io_rs1_valid; // @[Alu.scala 23:18]
- wire [31:0] alu_1_io_rs1_data; // @[Alu.scala 23:18]
- wire alu_1_io_rs2_valid; // @[Alu.scala 23:18]
- wire [31:0] alu_1_io_rs2_data; // @[Alu.scala 23:18]
- wire alu_1_io_rd_valid; // @[Alu.scala 23:18]
- wire [4:0] alu_1_io_rd_addr; // @[Alu.scala 23:18]
- wire [31:0] alu_1_io_rd_data; // @[Alu.scala 23:18]
- wire alu_2_clock; // @[Alu.scala 23:18]
- wire alu_2_reset; // @[Alu.scala 23:18]
- wire alu_2_io_req_valid; // @[Alu.scala 23:18]
- wire [4:0] alu_2_io_req_addr; // @[Alu.scala 23:18]
- wire [17:0] alu_2_io_req_op; // @[Alu.scala 23:18]
- wire alu_2_io_rs1_valid; // @[Alu.scala 23:18]
- wire [31:0] alu_2_io_rs1_data; // @[Alu.scala 23:18]
- wire alu_2_io_rs2_valid; // @[Alu.scala 23:18]
- wire [31:0] alu_2_io_rs2_data; // @[Alu.scala 23:18]
- wire alu_2_io_rd_valid; // @[Alu.scala 23:18]
- wire [4:0] alu_2_io_rd_addr; // @[Alu.scala 23:18]
- wire [31:0] alu_2_io_rd_data; // @[Alu.scala 23:18]
- wire alu_3_clock; // @[Alu.scala 23:18]
- wire alu_3_reset; // @[Alu.scala 23:18]
- wire alu_3_io_req_valid; // @[Alu.scala 23:18]
- wire [4:0] alu_3_io_req_addr; // @[Alu.scala 23:18]
- wire [17:0] alu_3_io_req_op; // @[Alu.scala 23:18]
- wire alu_3_io_rs1_valid; // @[Alu.scala 23:18]
- wire [31:0] alu_3_io_rs1_data; // @[Alu.scala 23:18]
- wire alu_3_io_rs2_valid; // @[Alu.scala 23:18]
- wire [31:0] alu_3_io_rs2_data; // @[Alu.scala 23:18]
- wire alu_3_io_rd_valid; // @[Alu.scala 23:18]
- wire [4:0] alu_3_io_rd_addr; // @[Alu.scala 23:18]
- wire [31:0] alu_3_io_rd_data; // @[Alu.scala 23:18]
- wire bru_0_clock; // @[Bru.scala 23:18]
- wire bru_0_reset; // @[Bru.scala 23:18]
- wire bru_0_io_req_valid; // @[Bru.scala 23:18]
- wire bru_0_io_req_fwd; // @[Bru.scala 23:18]
- wire [16:0] bru_0_io_req_op; // @[Bru.scala 23:18]
- wire [31:0] bru_0_io_req_pc; // @[Bru.scala 23:18]
- wire [31:0] bru_0_io_req_target; // @[Bru.scala 23:18]
- wire [4:0] bru_0_io_req_link; // @[Bru.scala 23:18]
- wire bru_0_io_csr_in_mode_valid; // @[Bru.scala 23:18]
- wire bru_0_io_csr_in_mode_bits; // @[Bru.scala 23:18]
- wire bru_0_io_csr_in_mcause_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_0_io_csr_in_mcause_bits; // @[Bru.scala 23:18]
- wire bru_0_io_csr_in_mepc_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_0_io_csr_in_mepc_bits; // @[Bru.scala 23:18]
- wire bru_0_io_csr_in_mtval_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_0_io_csr_in_mtval_bits; // @[Bru.scala 23:18]
- wire bru_0_io_csr_in_halt; // @[Bru.scala 23:18]
- wire bru_0_io_csr_in_fault; // @[Bru.scala 23:18]
- wire bru_0_io_csr_out_mode; // @[Bru.scala 23:18]
- wire [31:0] bru_0_io_csr_out_mepc; // @[Bru.scala 23:18]
- wire [31:0] bru_0_io_csr_out_mtvec; // @[Bru.scala 23:18]
- wire bru_0_io_rs1_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_0_io_rs1_data; // @[Bru.scala 23:18]
- wire bru_0_io_rs2_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_0_io_rs2_data; // @[Bru.scala 23:18]
- wire bru_0_io_rd_valid; // @[Bru.scala 23:18]
- wire [4:0] bru_0_io_rd_addr; // @[Bru.scala 23:18]
- wire [31:0] bru_0_io_rd_data; // @[Bru.scala 23:18]
- wire bru_0_io_taken_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_0_io_taken_value; // @[Bru.scala 23:18]
- wire [31:0] bru_0_io_target_data; // @[Bru.scala 23:18]
- wire bru_0_io_interlock; // @[Bru.scala 23:18]
- wire bru_0_io_iflush; // @[Bru.scala 23:18]
- wire bru_1_clock; // @[Bru.scala 23:18]
- wire bru_1_reset; // @[Bru.scala 23:18]
- wire bru_1_io_req_valid; // @[Bru.scala 23:18]
- wire bru_1_io_req_fwd; // @[Bru.scala 23:18]
- wire [16:0] bru_1_io_req_op; // @[Bru.scala 23:18]
- wire [31:0] bru_1_io_req_pc; // @[Bru.scala 23:18]
- wire [31:0] bru_1_io_req_target; // @[Bru.scala 23:18]
- wire [4:0] bru_1_io_req_link; // @[Bru.scala 23:18]
- wire bru_1_io_csr_in_mode_valid; // @[Bru.scala 23:18]
- wire bru_1_io_csr_in_mode_bits; // @[Bru.scala 23:18]
- wire bru_1_io_csr_in_mcause_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_1_io_csr_in_mcause_bits; // @[Bru.scala 23:18]
- wire bru_1_io_csr_in_mepc_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_1_io_csr_in_mepc_bits; // @[Bru.scala 23:18]
- wire bru_1_io_csr_in_mtval_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_1_io_csr_in_mtval_bits; // @[Bru.scala 23:18]
- wire bru_1_io_csr_in_halt; // @[Bru.scala 23:18]
- wire bru_1_io_csr_in_fault; // @[Bru.scala 23:18]
- wire bru_1_io_csr_out_mode; // @[Bru.scala 23:18]
- wire [31:0] bru_1_io_csr_out_mepc; // @[Bru.scala 23:18]
- wire [31:0] bru_1_io_csr_out_mtvec; // @[Bru.scala 23:18]
- wire bru_1_io_rs1_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_1_io_rs1_data; // @[Bru.scala 23:18]
- wire bru_1_io_rs2_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_1_io_rs2_data; // @[Bru.scala 23:18]
- wire bru_1_io_rd_valid; // @[Bru.scala 23:18]
- wire [4:0] bru_1_io_rd_addr; // @[Bru.scala 23:18]
- wire [31:0] bru_1_io_rd_data; // @[Bru.scala 23:18]
- wire bru_1_io_taken_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_1_io_taken_value; // @[Bru.scala 23:18]
- wire [31:0] bru_1_io_target_data; // @[Bru.scala 23:18]
- wire bru_1_io_interlock; // @[Bru.scala 23:18]
- wire bru_1_io_iflush; // @[Bru.scala 23:18]
- wire bru_2_clock; // @[Bru.scala 23:18]
- wire bru_2_reset; // @[Bru.scala 23:18]
- wire bru_2_io_req_valid; // @[Bru.scala 23:18]
- wire bru_2_io_req_fwd; // @[Bru.scala 23:18]
- wire [16:0] bru_2_io_req_op; // @[Bru.scala 23:18]
- wire [31:0] bru_2_io_req_pc; // @[Bru.scala 23:18]
- wire [31:0] bru_2_io_req_target; // @[Bru.scala 23:18]
- wire [4:0] bru_2_io_req_link; // @[Bru.scala 23:18]
- wire bru_2_io_csr_in_mode_valid; // @[Bru.scala 23:18]
- wire bru_2_io_csr_in_mode_bits; // @[Bru.scala 23:18]
- wire bru_2_io_csr_in_mcause_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_2_io_csr_in_mcause_bits; // @[Bru.scala 23:18]
- wire bru_2_io_csr_in_mepc_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_2_io_csr_in_mepc_bits; // @[Bru.scala 23:18]
- wire bru_2_io_csr_in_mtval_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_2_io_csr_in_mtval_bits; // @[Bru.scala 23:18]
- wire bru_2_io_csr_in_halt; // @[Bru.scala 23:18]
- wire bru_2_io_csr_in_fault; // @[Bru.scala 23:18]
- wire bru_2_io_csr_out_mode; // @[Bru.scala 23:18]
- wire [31:0] bru_2_io_csr_out_mepc; // @[Bru.scala 23:18]
- wire [31:0] bru_2_io_csr_out_mtvec; // @[Bru.scala 23:18]
- wire bru_2_io_rs1_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_2_io_rs1_data; // @[Bru.scala 23:18]
- wire bru_2_io_rs2_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_2_io_rs2_data; // @[Bru.scala 23:18]
- wire bru_2_io_rd_valid; // @[Bru.scala 23:18]
- wire [4:0] bru_2_io_rd_addr; // @[Bru.scala 23:18]
- wire [31:0] bru_2_io_rd_data; // @[Bru.scala 23:18]
- wire bru_2_io_taken_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_2_io_taken_value; // @[Bru.scala 23:18]
- wire [31:0] bru_2_io_target_data; // @[Bru.scala 23:18]
- wire bru_2_io_interlock; // @[Bru.scala 23:18]
- wire bru_2_io_iflush; // @[Bru.scala 23:18]
- wire bru_3_clock; // @[Bru.scala 23:18]
- wire bru_3_reset; // @[Bru.scala 23:18]
- wire bru_3_io_req_valid; // @[Bru.scala 23:18]
- wire bru_3_io_req_fwd; // @[Bru.scala 23:18]
- wire [16:0] bru_3_io_req_op; // @[Bru.scala 23:18]
- wire [31:0] bru_3_io_req_pc; // @[Bru.scala 23:18]
- wire [31:0] bru_3_io_req_target; // @[Bru.scala 23:18]
- wire [4:0] bru_3_io_req_link; // @[Bru.scala 23:18]
- wire bru_3_io_csr_in_mode_valid; // @[Bru.scala 23:18]
- wire bru_3_io_csr_in_mode_bits; // @[Bru.scala 23:18]
- wire bru_3_io_csr_in_mcause_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_3_io_csr_in_mcause_bits; // @[Bru.scala 23:18]
- wire bru_3_io_csr_in_mepc_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_3_io_csr_in_mepc_bits; // @[Bru.scala 23:18]
- wire bru_3_io_csr_in_mtval_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_3_io_csr_in_mtval_bits; // @[Bru.scala 23:18]
- wire bru_3_io_csr_in_halt; // @[Bru.scala 23:18]
- wire bru_3_io_csr_in_fault; // @[Bru.scala 23:18]
- wire bru_3_io_csr_out_mode; // @[Bru.scala 23:18]
- wire [31:0] bru_3_io_csr_out_mepc; // @[Bru.scala 23:18]
- wire [31:0] bru_3_io_csr_out_mtvec; // @[Bru.scala 23:18]
- wire bru_3_io_rs1_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_3_io_rs1_data; // @[Bru.scala 23:18]
- wire bru_3_io_rs2_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_3_io_rs2_data; // @[Bru.scala 23:18]
- wire bru_3_io_rd_valid; // @[Bru.scala 23:18]
- wire [4:0] bru_3_io_rd_addr; // @[Bru.scala 23:18]
- wire [31:0] bru_3_io_rd_data; // @[Bru.scala 23:18]
- wire bru_3_io_taken_valid; // @[Bru.scala 23:18]
- wire [31:0] bru_3_io_taken_value; // @[Bru.scala 23:18]
- wire [31:0] bru_3_io_target_data; // @[Bru.scala 23:18]
- wire bru_3_io_interlock; // @[Bru.scala 23:18]
- wire bru_3_io_iflush; // @[Bru.scala 23:18]
- wire csr_clock; // @[Csr.scala 23:18]
- wire csr_reset; // @[Csr.scala 23:18]
- wire [31:0] csr_io_csr_in_value_0; // @[Csr.scala 23:18]
- wire csr_io_req_valid; // @[Csr.scala 23:18]
- wire [4:0] csr_io_req_addr; // @[Csr.scala 23:18]
- wire [11:0] csr_io_req_index; // @[Csr.scala 23:18]
- wire [2:0] csr_io_req_op; // @[Csr.scala 23:18]
- wire csr_io_rs1_valid; // @[Csr.scala 23:18]
- wire [31:0] csr_io_rs1_data; // @[Csr.scala 23:18]
- wire csr_io_rd_valid; // @[Csr.scala 23:18]
- wire [4:0] csr_io_rd_addr; // @[Csr.scala 23:18]
- wire [31:0] csr_io_rd_data; // @[Csr.scala 23:18]
- wire csr_io_bru_in_mode_valid; // @[Csr.scala 23:18]
- wire csr_io_bru_in_mode_bits; // @[Csr.scala 23:18]
- wire csr_io_bru_in_mcause_valid; // @[Csr.scala 23:18]
- wire [31:0] csr_io_bru_in_mcause_bits; // @[Csr.scala 23:18]
- wire csr_io_bru_in_mepc_valid; // @[Csr.scala 23:18]
- wire [31:0] csr_io_bru_in_mepc_bits; // @[Csr.scala 23:18]
- wire csr_io_bru_in_mtval_valid; // @[Csr.scala 23:18]
- wire [31:0] csr_io_bru_in_mtval_bits; // @[Csr.scala 23:18]
- wire csr_io_bru_in_halt; // @[Csr.scala 23:18]
- wire csr_io_bru_in_fault; // @[Csr.scala 23:18]
- wire csr_io_bru_out_mode; // @[Csr.scala 23:18]
- wire [31:0] csr_io_bru_out_mepc; // @[Csr.scala 23:18]
- wire [31:0] csr_io_bru_out_mtvec; // @[Csr.scala 23:18]
- wire csr_io_vcore_undef; // @[Csr.scala 23:18]
- wire csr_io_halted; // @[Csr.scala 23:18]
- wire csr_io_fault; // @[Csr.scala 23:18]
- wire lsu_clock; // @[Lsu.scala 23:18]
- wire lsu_reset; // @[Lsu.scala 23:18]
- wire lsu_io_req_0_valid; // @[Lsu.scala 23:18]
- wire lsu_io_req_0_ready; // @[Lsu.scala 23:18]
- wire [4:0] lsu_io_req_0_addr; // @[Lsu.scala 23:18]
- wire [11:0] lsu_io_req_0_op; // @[Lsu.scala 23:18]
- wire lsu_io_req_1_valid; // @[Lsu.scala 23:18]
- wire lsu_io_req_1_ready; // @[Lsu.scala 23:18]
- wire [4:0] lsu_io_req_1_addr; // @[Lsu.scala 23:18]
- wire [11:0] lsu_io_req_1_op; // @[Lsu.scala 23:18]
- wire lsu_io_req_2_valid; // @[Lsu.scala 23:18]
- wire lsu_io_req_2_ready; // @[Lsu.scala 23:18]
- wire [4:0] lsu_io_req_2_addr; // @[Lsu.scala 23:18]
- wire [11:0] lsu_io_req_2_op; // @[Lsu.scala 23:18]
- wire lsu_io_req_3_valid; // @[Lsu.scala 23:18]
- wire lsu_io_req_3_ready; // @[Lsu.scala 23:18]
- wire [4:0] lsu_io_req_3_addr; // @[Lsu.scala 23:18]
- wire [11:0] lsu_io_req_3_op; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_busPort_addr_0; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_busPort_addr_1; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_busPort_addr_2; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_busPort_addr_3; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_busPort_data_0; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_busPort_data_1; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_busPort_data_2; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_busPort_data_3; // @[Lsu.scala 23:18]
- wire lsu_io_rd_valid; // @[Lsu.scala 23:18]
- wire [4:0] lsu_io_rd_addr; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_rd_data; // @[Lsu.scala 23:18]
- wire lsu_io_dbus_valid; // @[Lsu.scala 23:18]
- wire lsu_io_dbus_ready; // @[Lsu.scala 23:18]
- wire lsu_io_dbus_write; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_dbus_addr; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_dbus_adrx; // @[Lsu.scala 23:18]
- wire [5:0] lsu_io_dbus_size; // @[Lsu.scala 23:18]
- wire [255:0] lsu_io_dbus_wdata; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_dbus_wmask; // @[Lsu.scala 23:18]
- wire [255:0] lsu_io_dbus_rdata; // @[Lsu.scala 23:18]
- wire lsu_io_flush_valid; // @[Lsu.scala 23:18]
- wire lsu_io_flush_ready; // @[Lsu.scala 23:18]
- wire lsu_io_flush_all; // @[Lsu.scala 23:18]
- wire lsu_io_flush_fencei; // @[Lsu.scala 23:18]
- wire lsu_io_ubus_valid; // @[Lsu.scala 23:18]
- wire lsu_io_ubus_ready; // @[Lsu.scala 23:18]
- wire lsu_io_ubus_write; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_ubus_addr; // @[Lsu.scala 23:18]
- wire [255:0] lsu_io_ubus_wdata; // @[Lsu.scala 23:18]
- wire [31:0] lsu_io_ubus_wmask; // @[Lsu.scala 23:18]
- wire [255:0] lsu_io_ubus_rdata; // @[Lsu.scala 23:18]
- wire lsu_io_vldst; // @[Lsu.scala 23:18]
- wire mlu_clock; // @[Mlu.scala 23:18]
- wire mlu_reset; // @[Mlu.scala 23:18]
- wire mlu_io_req_0_valid; // @[Mlu.scala 23:18]
- wire [4:0] mlu_io_req_0_addr; // @[Mlu.scala 23:18]
- wire [8:0] mlu_io_req_0_op; // @[Mlu.scala 23:18]
- wire mlu_io_req_1_valid; // @[Mlu.scala 23:18]
- wire [4:0] mlu_io_req_1_addr; // @[Mlu.scala 23:18]
- wire [8:0] mlu_io_req_1_op; // @[Mlu.scala 23:18]
- wire mlu_io_req_2_valid; // @[Mlu.scala 23:18]
- wire [4:0] mlu_io_req_2_addr; // @[Mlu.scala 23:18]
- wire [8:0] mlu_io_req_2_op; // @[Mlu.scala 23:18]
- wire mlu_io_req_3_valid; // @[Mlu.scala 23:18]
- wire [4:0] mlu_io_req_3_addr; // @[Mlu.scala 23:18]
- wire [8:0] mlu_io_req_3_op; // @[Mlu.scala 23:18]
- wire mlu_io_rs1_0_valid; // @[Mlu.scala 23:18]
- wire [31:0] mlu_io_rs1_0_data; // @[Mlu.scala 23:18]
- wire mlu_io_rs1_1_valid; // @[Mlu.scala 23:18]
- wire [31:0] mlu_io_rs1_1_data; // @[Mlu.scala 23:18]
- wire mlu_io_rs1_2_valid; // @[Mlu.scala 23:18]
- wire [31:0] mlu_io_rs1_2_data; // @[Mlu.scala 23:18]
- wire mlu_io_rs1_3_valid; // @[Mlu.scala 23:18]
- wire [31:0] mlu_io_rs1_3_data; // @[Mlu.scala 23:18]
- wire mlu_io_rs2_0_valid; // @[Mlu.scala 23:18]
- wire [31:0] mlu_io_rs2_0_data; // @[Mlu.scala 23:18]
- wire mlu_io_rs2_1_valid; // @[Mlu.scala 23:18]
- wire [31:0] mlu_io_rs2_1_data; // @[Mlu.scala 23:18]
- wire mlu_io_rs2_2_valid; // @[Mlu.scala 23:18]
- wire [31:0] mlu_io_rs2_2_data; // @[Mlu.scala 23:18]
- wire mlu_io_rs2_3_valid; // @[Mlu.scala 23:18]
- wire [31:0] mlu_io_rs2_3_data; // @[Mlu.scala 23:18]
- wire mlu_io_rd_valid; // @[Mlu.scala 23:18]
- wire [4:0] mlu_io_rd_addr; // @[Mlu.scala 23:18]
- wire [31:0] mlu_io_rd_data; // @[Mlu.scala 23:18]
- wire dvu_clock; // @[Dvu.scala 23:18]
- wire dvu_reset; // @[Dvu.scala 23:18]
- wire dvu_io_req_valid; // @[Dvu.scala 23:18]
- wire dvu_io_req_ready; // @[Dvu.scala 23:18]
- wire [4:0] dvu_io_req_addr; // @[Dvu.scala 23:18]
- wire [3:0] dvu_io_req_op; // @[Dvu.scala 23:18]
- wire [31:0] dvu_io_rs1_data; // @[Dvu.scala 23:18]
- wire [31:0] dvu_io_rs2_data; // @[Dvu.scala 23:18]
- wire dvu_io_rd_valid; // @[Dvu.scala 23:18]
- wire dvu_io_rd_ready; // @[Dvu.scala 23:18]
- wire [4:0] dvu_io_rd_addr; // @[Dvu.scala 23:18]
- wire [31:0] dvu_io_rd_data; // @[Dvu.scala 23:18]
- wire _branchTaken_T_1 = bru_0_io_taken_valid | bru_1_io_taken_valid | bru_2_io_taken_valid; // @[SCore.scala 61:68]
- reg iflush; // @[SCore.scala 66:23]
- wire _T_1 = fetch_io_iflush_ready & lsu_io_flush_ready; // @[SCore.scala 70:57]
- wire _GEN_0 = _T_1 & lsu_io_flush_fencei ? 1'h0 : iflush; // @[SCore.scala 71:59 72:12 66:23]
- wire _T_5 = ~reset; // @[SCore.scala 80:9]
- wire mask_2 = decode_0_io_inst_ready & decode_1_io_inst_ready; // @[SCore.scala 100:46]
- wire mask_3 = mask_2 & decode_2_io_inst_ready; // @[SCore.scala 101:73]
- wire _fetch_io_inst_lanes_0_ready_T = decode_0_io_inst_ready; // @[SCore.scala 106:61]
- wire [31:0] scoreboard_spec2 = decode_1_io_scoreboard_spec | decode_0_io_scoreboard_spec; // @[SCore.scala 129:55]
- wire [31:0] scoreboard_spec3 = decode_2_io_scoreboard_spec | scoreboard_spec2; // @[SCore.scala 130:55]
- wire _regfile_io_writeData_0_valid_T = csr_io_rd_valid | alu_0_io_rd_valid; // @[SCore.scala 242:48]
- wire [4:0] _regfile_io_writeData_0_addr_T = csr_io_rd_valid ? csr_io_rd_addr : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _regfile_io_writeData_0_addr_T_1 = alu_0_io_rd_valid ? alu_0_io_rd_addr : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _regfile_io_writeData_0_addr_T_2 = _regfile_io_writeData_0_addr_T | _regfile_io_writeData_0_addr_T_1; // @[SCore.scala 247:36]
- wire [4:0] _regfile_io_writeData_0_addr_T_3 = bru_0_io_rd_valid ? bru_0_io_rd_addr : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _regfile_io_writeData_0_addr_T_4 = _regfile_io_writeData_0_addr_T_2 | _regfile_io_writeData_0_addr_T_3; // @[SCore.scala 248:54]
- wire [4:0] _regfile_io_writeData_0_addr_T_5 = io_vcore_rd_0_valid ? io_vcore_rd_0_addr : 5'h0; // @[Library.scala 22:8]
- wire [31:0] _regfile_io_writeData_0_data_T = csr_io_rd_valid ? csr_io_rd_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _regfile_io_writeData_0_data_T_1 = alu_0_io_rd_valid ? alu_0_io_rd_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _regfile_io_writeData_0_data_T_2 = _regfile_io_writeData_0_data_T | _regfile_io_writeData_0_data_T_1; // @[SCore.scala 253:36]
- wire [31:0] _regfile_io_writeData_0_data_T_3 = bru_0_io_rd_valid ? bru_0_io_rd_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _regfile_io_writeData_0_data_T_4 = _regfile_io_writeData_0_data_T_2 | _regfile_io_writeData_0_data_T_3; // @[SCore.scala 254:54]
- wire [31:0] _regfile_io_writeData_0_data_T_5 = io_vcore_rd_0_valid ? io_vcore_rd_0_data : 32'h0; // @[Library.scala 22:8]
- wire [1:0] _T_15 = csr_io_rd_valid + alu_0_io_rd_valid; // @[SCore.scala 258:23]
- wire [1:0] _GEN_3 = {{1'd0}, bru_0_io_rd_valid}; // @[SCore.scala 259:32]
- wire [2:0] _T_16 = _T_15 + _GEN_3; // @[SCore.scala 259:32]
- wire [2:0] _GEN_4 = {{2'd0}, io_vcore_rd_0_valid}; // @[SCore.scala 259:54]
- wire [3:0] _T_17 = _T_16 + _GEN_4; // @[SCore.scala 259:54]
- wire _T_18 = _T_17 <= 4'h1; // @[SCore.scala 260:35]
- wire _regfile_io_writeData_1_valid_T = alu_1_io_rd_valid; // @[SCore.scala 242:48]
- wire [4:0] _regfile_io_writeData_1_addr_T_1 = alu_1_io_rd_valid ? alu_1_io_rd_addr : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _regfile_io_writeData_1_addr_T_3 = bru_1_io_rd_valid ? bru_1_io_rd_addr : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _regfile_io_writeData_1_addr_T_4 = _regfile_io_writeData_1_addr_T_1 | _regfile_io_writeData_1_addr_T_3; // @[SCore.scala 248:54]
- wire [4:0] _regfile_io_writeData_1_addr_T_5 = io_vcore_rd_1_valid ? io_vcore_rd_1_addr : 5'h0; // @[Library.scala 22:8]
- wire [31:0] _regfile_io_writeData_1_data_T_1 = alu_1_io_rd_valid ? alu_1_io_rd_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _regfile_io_writeData_1_data_T_3 = bru_1_io_rd_valid ? bru_1_io_rd_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _regfile_io_writeData_1_data_T_4 = _regfile_io_writeData_1_data_T_1 | _regfile_io_writeData_1_data_T_3; // @[SCore.scala 254:54]
- wire [31:0] _regfile_io_writeData_1_data_T_5 = io_vcore_rd_1_valid ? io_vcore_rd_1_data : 32'h0; // @[Library.scala 22:8]
- wire [1:0] _T_22 = {{1'd0}, alu_1_io_rd_valid}; // @[SCore.scala 258:23]
- wire [1:0] _GEN_5 = {{1'd0}, bru_1_io_rd_valid}; // @[SCore.scala 259:32]
- wire [2:0] _T_23 = _T_22 + _GEN_5; // @[SCore.scala 259:32]
- wire [2:0] _GEN_6 = {{2'd0}, io_vcore_rd_1_valid}; // @[SCore.scala 259:54]
- wire [3:0] _T_24 = _T_23 + _GEN_6; // @[SCore.scala 259:54]
- wire _T_25 = _T_24 <= 4'h1; // @[SCore.scala 260:35]
- wire _regfile_io_writeData_2_valid_T = alu_2_io_rd_valid; // @[SCore.scala 242:48]
- wire [4:0] _regfile_io_writeData_2_addr_T_1 = alu_2_io_rd_valid ? alu_2_io_rd_addr : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _regfile_io_writeData_2_addr_T_3 = bru_2_io_rd_valid ? bru_2_io_rd_addr : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _regfile_io_writeData_2_addr_T_4 = _regfile_io_writeData_2_addr_T_1 | _regfile_io_writeData_2_addr_T_3; // @[SCore.scala 248:54]
- wire [4:0] _regfile_io_writeData_2_addr_T_5 = io_vcore_rd_2_valid ? io_vcore_rd_2_addr : 5'h0; // @[Library.scala 22:8]
- wire [31:0] _regfile_io_writeData_2_data_T_1 = alu_2_io_rd_valid ? alu_2_io_rd_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _regfile_io_writeData_2_data_T_3 = bru_2_io_rd_valid ? bru_2_io_rd_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _regfile_io_writeData_2_data_T_4 = _regfile_io_writeData_2_data_T_1 | _regfile_io_writeData_2_data_T_3; // @[SCore.scala 254:54]
- wire [31:0] _regfile_io_writeData_2_data_T_5 = io_vcore_rd_2_valid ? io_vcore_rd_2_data : 32'h0; // @[Library.scala 22:8]
- wire [1:0] _T_29 = {{1'd0}, alu_2_io_rd_valid}; // @[SCore.scala 258:23]
- wire [1:0] _GEN_7 = {{1'd0}, bru_2_io_rd_valid}; // @[SCore.scala 259:32]
- wire [2:0] _T_30 = _T_29 + _GEN_7; // @[SCore.scala 259:32]
- wire [2:0] _GEN_8 = {{2'd0}, io_vcore_rd_2_valid}; // @[SCore.scala 259:54]
- wire [3:0] _T_31 = _T_30 + _GEN_8; // @[SCore.scala 259:54]
- wire _T_32 = _T_31 <= 4'h1; // @[SCore.scala 260:35]
- wire _regfile_io_writeData_3_valid_T = alu_3_io_rd_valid; // @[SCore.scala 242:48]
- wire [4:0] _regfile_io_writeData_3_addr_T_1 = alu_3_io_rd_valid ? alu_3_io_rd_addr : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _regfile_io_writeData_3_addr_T_3 = bru_3_io_rd_valid ? bru_3_io_rd_addr : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _regfile_io_writeData_3_addr_T_4 = _regfile_io_writeData_3_addr_T_1 | _regfile_io_writeData_3_addr_T_3; // @[SCore.scala 248:54]
- wire [4:0] _regfile_io_writeData_3_addr_T_5 = io_vcore_rd_3_valid ? io_vcore_rd_3_addr : 5'h0; // @[Library.scala 22:8]
- wire [31:0] _regfile_io_writeData_3_data_T_1 = alu_3_io_rd_valid ? alu_3_io_rd_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _regfile_io_writeData_3_data_T_3 = bru_3_io_rd_valid ? bru_3_io_rd_data : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _regfile_io_writeData_3_data_T_4 = _regfile_io_writeData_3_data_T_1 | _regfile_io_writeData_3_data_T_3; // @[SCore.scala 254:54]
- wire [31:0] _regfile_io_writeData_3_data_T_5 = io_vcore_rd_3_valid ? io_vcore_rd_3_data : 32'h0; // @[Library.scala 22:8]
- wire [1:0] _T_36 = {{1'd0}, alu_3_io_rd_valid}; // @[SCore.scala 258:23]
- wire [1:0] _GEN_9 = {{1'd0}, bru_3_io_rd_valid}; // @[SCore.scala 259:32]
- wire [2:0] _T_37 = _T_36 + _GEN_9; // @[SCore.scala 259:32]
- wire [2:0] _GEN_10 = {{2'd0}, io_vcore_rd_3_valid}; // @[SCore.scala 259:54]
- wire [3:0] _T_38 = _T_37 + _GEN_10; // @[SCore.scala 259:54]
- wire _T_39 = _T_38 <= 4'h1; // @[SCore.scala 260:35]
- reg slogValid; // @[SCore.scala 303:26]
- reg [1:0] slogAddr; // @[SCore.scala 304:21]
- wire [2:0] _GEN_2 = decode_0_io_slog ? decode_0_io_inst_inst[14:12] : {{1'd0}, slogAddr}; // @[SCore.scala 308:17 309:14 304:21]
- wire [1:0] _io_slog_addr_T = slogValid ? slogAddr : 2'h0; // @[Library.scala 22:8]
- Regfile regfile ( // @[Regfile.scala 27:18]
- .clock(regfile_clock),
- .reset(regfile_reset),
- .io_readAddr_0_valid(regfile_io_readAddr_0_valid),
- .io_readAddr_0_addr(regfile_io_readAddr_0_addr),
- .io_readAddr_1_valid(regfile_io_readAddr_1_valid),
- .io_readAddr_1_addr(regfile_io_readAddr_1_addr),
- .io_readAddr_2_valid(regfile_io_readAddr_2_valid),
- .io_readAddr_2_addr(regfile_io_readAddr_2_addr),
- .io_readAddr_3_valid(regfile_io_readAddr_3_valid),
- .io_readAddr_3_addr(regfile_io_readAddr_3_addr),
- .io_readAddr_4_valid(regfile_io_readAddr_4_valid),
- .io_readAddr_4_addr(regfile_io_readAddr_4_addr),
- .io_readAddr_5_valid(regfile_io_readAddr_5_valid),
- .io_readAddr_5_addr(regfile_io_readAddr_5_addr),
- .io_readAddr_6_valid(regfile_io_readAddr_6_valid),
- .io_readAddr_6_addr(regfile_io_readAddr_6_addr),
- .io_readAddr_7_valid(regfile_io_readAddr_7_valid),
- .io_readAddr_7_addr(regfile_io_readAddr_7_addr),
- .io_readSet_0_valid(regfile_io_readSet_0_valid),
- .io_readSet_0_value(regfile_io_readSet_0_value),
- .io_readSet_1_valid(regfile_io_readSet_1_valid),
- .io_readSet_1_value(regfile_io_readSet_1_value),
- .io_readSet_2_valid(regfile_io_readSet_2_valid),
- .io_readSet_2_value(regfile_io_readSet_2_value),
- .io_readSet_3_valid(regfile_io_readSet_3_valid),
- .io_readSet_3_value(regfile_io_readSet_3_value),
- .io_readSet_4_valid(regfile_io_readSet_4_valid),
- .io_readSet_4_value(regfile_io_readSet_4_value),
- .io_readSet_5_valid(regfile_io_readSet_5_valid),
- .io_readSet_5_value(regfile_io_readSet_5_value),
- .io_readSet_6_valid(regfile_io_readSet_6_valid),
- .io_readSet_6_value(regfile_io_readSet_6_value),
- .io_readSet_7_valid(regfile_io_readSet_7_valid),
- .io_readSet_7_value(regfile_io_readSet_7_value),
- .io_writeAddr_0_valid(regfile_io_writeAddr_0_valid),
- .io_writeAddr_0_addr(regfile_io_writeAddr_0_addr),
- .io_writeAddr_1_valid(regfile_io_writeAddr_1_valid),
- .io_writeAddr_1_addr(regfile_io_writeAddr_1_addr),
- .io_writeAddr_2_valid(regfile_io_writeAddr_2_valid),
- .io_writeAddr_2_addr(regfile_io_writeAddr_2_addr),
- .io_writeAddr_3_valid(regfile_io_writeAddr_3_valid),
- .io_writeAddr_3_addr(regfile_io_writeAddr_3_addr),
- .io_busAddr_0_bypass(regfile_io_busAddr_0_bypass),
- .io_busAddr_0_immen(regfile_io_busAddr_0_immen),
- .io_busAddr_0_immed(regfile_io_busAddr_0_immed),
- .io_busAddr_1_bypass(regfile_io_busAddr_1_bypass),
- .io_busAddr_1_immed(regfile_io_busAddr_1_immed),
- .io_busAddr_2_bypass(regfile_io_busAddr_2_bypass),
- .io_busAddr_2_immed(regfile_io_busAddr_2_immed),
- .io_busAddr_3_bypass(regfile_io_busAddr_3_bypass),
- .io_busAddr_3_immed(regfile_io_busAddr_3_immed),
- .io_target_0_data(regfile_io_target_0_data),
- .io_target_1_data(regfile_io_target_1_data),
- .io_target_2_data(regfile_io_target_2_data),
- .io_target_3_data(regfile_io_target_3_data),
- .io_linkPort_valid(regfile_io_linkPort_valid),
- .io_linkPort_value(regfile_io_linkPort_value),
- .io_busPort_addr_0(regfile_io_busPort_addr_0),
- .io_busPort_addr_1(regfile_io_busPort_addr_1),
- .io_busPort_addr_2(regfile_io_busPort_addr_2),
- .io_busPort_addr_3(regfile_io_busPort_addr_3),
- .io_busPort_data_0(regfile_io_busPort_data_0),
- .io_busPort_data_1(regfile_io_busPort_data_1),
- .io_busPort_data_2(regfile_io_busPort_data_2),
- .io_busPort_data_3(regfile_io_busPort_data_3),
- .io_readData_0_valid(regfile_io_readData_0_valid),
- .io_readData_0_data(regfile_io_readData_0_data),
- .io_readData_1_valid(regfile_io_readData_1_valid),
- .io_readData_1_data(regfile_io_readData_1_data),
- .io_readData_2_valid(regfile_io_readData_2_valid),
- .io_readData_2_data(regfile_io_readData_2_data),
- .io_readData_3_valid(regfile_io_readData_3_valid),
- .io_readData_3_data(regfile_io_readData_3_data),
- .io_readData_4_valid(regfile_io_readData_4_valid),
- .io_readData_4_data(regfile_io_readData_4_data),
- .io_readData_5_valid(regfile_io_readData_5_valid),
- .io_readData_5_data(regfile_io_readData_5_data),
- .io_readData_6_valid(regfile_io_readData_6_valid),
- .io_readData_6_data(regfile_io_readData_6_data),
- .io_readData_7_valid(regfile_io_readData_7_valid),
- .io_readData_7_data(regfile_io_readData_7_data),
- .io_writeData_0_valid(regfile_io_writeData_0_valid),
- .io_writeData_0_addr(regfile_io_writeData_0_addr),
- .io_writeData_0_data(regfile_io_writeData_0_data),
- .io_writeData_1_valid(regfile_io_writeData_1_valid),
- .io_writeData_1_addr(regfile_io_writeData_1_addr),
- .io_writeData_1_data(regfile_io_writeData_1_data),
- .io_writeData_2_valid(regfile_io_writeData_2_valid),
- .io_writeData_2_addr(regfile_io_writeData_2_addr),
- .io_writeData_2_data(regfile_io_writeData_2_data),
- .io_writeData_3_valid(regfile_io_writeData_3_valid),
- .io_writeData_3_addr(regfile_io_writeData_3_addr),
- .io_writeData_3_data(regfile_io_writeData_3_data),
- .io_writeData_4_valid(regfile_io_writeData_4_valid),
- .io_writeData_4_addr(regfile_io_writeData_4_addr),
- .io_writeData_4_data(regfile_io_writeData_4_data),
- .io_writeData_5_valid(regfile_io_writeData_5_valid),
- .io_writeData_5_addr(regfile_io_writeData_5_addr),
- .io_writeData_5_data(regfile_io_writeData_5_data),
- .io_writeMask_0_valid(regfile_io_writeMask_0_valid),
- .io_writeMask_1_valid(regfile_io_writeMask_1_valid),
- .io_writeMask_2_valid(regfile_io_writeMask_2_valid),
- .io_writeMask_3_valid(regfile_io_writeMask_3_valid),
- .io_scoreboard_regd(regfile_io_scoreboard_regd),
- .io_scoreboard_comb(regfile_io_scoreboard_comb)
- );
- Fetch fetch ( // @[Fetch.scala 28:18]
- .clock(fetch_clock),
- .reset(fetch_reset),
- .io_csr_value_0(fetch_io_csr_value_0),
- .io_ibus_valid(fetch_io_ibus_valid),
- .io_ibus_ready(fetch_io_ibus_ready),
- .io_ibus_addr(fetch_io_ibus_addr),
- .io_ibus_rdata(fetch_io_ibus_rdata),
- .io_inst_lanes_0_valid(fetch_io_inst_lanes_0_valid),
- .io_inst_lanes_0_ready(fetch_io_inst_lanes_0_ready),
- .io_inst_lanes_0_addr(fetch_io_inst_lanes_0_addr),
- .io_inst_lanes_0_inst(fetch_io_inst_lanes_0_inst),
- .io_inst_lanes_0_brchFwd(fetch_io_inst_lanes_0_brchFwd),
- .io_inst_lanes_1_valid(fetch_io_inst_lanes_1_valid),
- .io_inst_lanes_1_ready(fetch_io_inst_lanes_1_ready),
- .io_inst_lanes_1_addr(fetch_io_inst_lanes_1_addr),
- .io_inst_lanes_1_inst(fetch_io_inst_lanes_1_inst),
- .io_inst_lanes_1_brchFwd(fetch_io_inst_lanes_1_brchFwd),
- .io_inst_lanes_2_valid(fetch_io_inst_lanes_2_valid),
- .io_inst_lanes_2_ready(fetch_io_inst_lanes_2_ready),
- .io_inst_lanes_2_addr(fetch_io_inst_lanes_2_addr),
- .io_inst_lanes_2_inst(fetch_io_inst_lanes_2_inst),
- .io_inst_lanes_2_brchFwd(fetch_io_inst_lanes_2_brchFwd),
- .io_inst_lanes_3_valid(fetch_io_inst_lanes_3_valid),
- .io_inst_lanes_3_ready(fetch_io_inst_lanes_3_ready),
- .io_inst_lanes_3_addr(fetch_io_inst_lanes_3_addr),
- .io_inst_lanes_3_inst(fetch_io_inst_lanes_3_inst),
- .io_inst_lanes_3_brchFwd(fetch_io_inst_lanes_3_brchFwd),
- .io_branch_0_valid(fetch_io_branch_0_valid),
- .io_branch_0_value(fetch_io_branch_0_value),
- .io_branch_1_valid(fetch_io_branch_1_valid),
- .io_branch_1_value(fetch_io_branch_1_value),
- .io_branch_2_valid(fetch_io_branch_2_valid),
- .io_branch_2_value(fetch_io_branch_2_value),
- .io_branch_3_valid(fetch_io_branch_3_valid),
- .io_branch_3_value(fetch_io_branch_3_value),
- .io_linkPort_valid(fetch_io_linkPort_valid),
- .io_linkPort_value(fetch_io_linkPort_value),
- .io_iflush_valid(fetch_io_iflush_valid),
- .io_iflush_ready(fetch_io_iflush_ready)
- );
- Decode decode_0 ( // @[Decode.scala 29:18]
- .clock(decode_0_clock),
- .reset(decode_0_reset),
- .io_halted(decode_0_io_halted),
- .io_inst_valid(decode_0_io_inst_valid),
- .io_inst_ready(decode_0_io_inst_ready),
- .io_inst_addr(decode_0_io_inst_addr),
- .io_inst_inst(decode_0_io_inst_inst),
- .io_inst_brchFwd(decode_0_io_inst_brchFwd),
- .io_scoreboard_regd(decode_0_io_scoreboard_regd),
- .io_scoreboard_comb(decode_0_io_scoreboard_comb),
- .io_scoreboard_spec(decode_0_io_scoreboard_spec),
- .io_mactive(decode_0_io_mactive),
- .io_rs1Read_valid(decode_0_io_rs1Read_valid),
- .io_rs1Read_addr(decode_0_io_rs1Read_addr),
- .io_rs1Set_valid(decode_0_io_rs1Set_valid),
- .io_rs1Set_value(decode_0_io_rs1Set_value),
- .io_rs2Read_valid(decode_0_io_rs2Read_valid),
- .io_rs2Read_addr(decode_0_io_rs2Read_addr),
- .io_rs2Set_valid(decode_0_io_rs2Set_valid),
- .io_rs2Set_value(decode_0_io_rs2Set_value),
- .io_rdMark_valid(decode_0_io_rdMark_valid),
- .io_rdMark_addr(decode_0_io_rdMark_addr),
- .io_busRead_bypass(decode_0_io_busRead_bypass),
- .io_busRead_immen(decode_0_io_busRead_immen),
- .io_busRead_immed(decode_0_io_busRead_immed),
- .io_alu_valid(decode_0_io_alu_valid),
- .io_alu_addr(decode_0_io_alu_addr),
- .io_alu_op(decode_0_io_alu_op),
- .io_bru_valid(decode_0_io_bru_valid),
- .io_bru_fwd(decode_0_io_bru_fwd),
- .io_bru_op(decode_0_io_bru_op),
- .io_bru_pc(decode_0_io_bru_pc),
- .io_bru_target(decode_0_io_bru_target),
- .io_bru_link(decode_0_io_bru_link),
- .io_csr_valid(decode_0_io_csr_valid),
- .io_csr_addr(decode_0_io_csr_addr),
- .io_csr_index(decode_0_io_csr_index),
- .io_csr_op(decode_0_io_csr_op),
- .io_lsu_valid(decode_0_io_lsu_valid),
- .io_lsu_ready(decode_0_io_lsu_ready),
- .io_lsu_addr(decode_0_io_lsu_addr),
- .io_lsu_op(decode_0_io_lsu_op),
- .io_mlu_valid(decode_0_io_mlu_valid),
- .io_mlu_addr(decode_0_io_mlu_addr),
- .io_mlu_op(decode_0_io_mlu_op),
- .io_dvu_valid(decode_0_io_dvu_valid),
- .io_dvu_ready(decode_0_io_dvu_ready),
- .io_dvu_addr(decode_0_io_dvu_addr),
- .io_dvu_op(decode_0_io_dvu_op),
- .io_vinst_valid(decode_0_io_vinst_valid),
- .io_vinst_ready(decode_0_io_vinst_ready),
- .io_vinst_addr(decode_0_io_vinst_addr),
- .io_vinst_inst(decode_0_io_vinst_inst),
- .io_vinst_op(decode_0_io_vinst_op),
- .io_branchTaken(decode_0_io_branchTaken),
- .io_interlock(decode_0_io_interlock),
- .io_serializeOut_mul(decode_0_io_serializeOut_mul),
- .io_serializeOut_jump(decode_0_io_serializeOut_jump),
- .io_serializeOut_brcond(decode_0_io_serializeOut_brcond),
- .io_slog(decode_0_io_slog)
- );
- Decode_1 decode_1 ( // @[Decode.scala 29:18]
- .clock(decode_1_clock),
- .reset(decode_1_reset),
- .io_halted(decode_1_io_halted),
- .io_inst_valid(decode_1_io_inst_valid),
- .io_inst_ready(decode_1_io_inst_ready),
- .io_inst_addr(decode_1_io_inst_addr),
- .io_inst_inst(decode_1_io_inst_inst),
- .io_inst_brchFwd(decode_1_io_inst_brchFwd),
- .io_scoreboard_regd(decode_1_io_scoreboard_regd),
- .io_scoreboard_comb(decode_1_io_scoreboard_comb),
- .io_scoreboard_spec(decode_1_io_scoreboard_spec),
- .io_rs1Read_valid(decode_1_io_rs1Read_valid),
- .io_rs1Read_addr(decode_1_io_rs1Read_addr),
- .io_rs1Set_valid(decode_1_io_rs1Set_valid),
- .io_rs1Set_value(decode_1_io_rs1Set_value),
- .io_rs2Read_valid(decode_1_io_rs2Read_valid),
- .io_rs2Read_addr(decode_1_io_rs2Read_addr),
- .io_rs2Set_valid(decode_1_io_rs2Set_valid),
- .io_rs2Set_value(decode_1_io_rs2Set_value),
- .io_rdMark_valid(decode_1_io_rdMark_valid),
- .io_rdMark_addr(decode_1_io_rdMark_addr),
- .io_busRead_bypass(decode_1_io_busRead_bypass),
- .io_busRead_immed(decode_1_io_busRead_immed),
- .io_alu_valid(decode_1_io_alu_valid),
- .io_alu_addr(decode_1_io_alu_addr),
- .io_alu_op(decode_1_io_alu_op),
- .io_bru_valid(decode_1_io_bru_valid),
- .io_bru_fwd(decode_1_io_bru_fwd),
- .io_bru_op(decode_1_io_bru_op),
- .io_bru_pc(decode_1_io_bru_pc),
- .io_bru_target(decode_1_io_bru_target),
- .io_bru_link(decode_1_io_bru_link),
- .io_csr_op(decode_1_io_csr_op),
- .io_lsu_valid(decode_1_io_lsu_valid),
- .io_lsu_ready(decode_1_io_lsu_ready),
- .io_lsu_addr(decode_1_io_lsu_addr),
- .io_lsu_op(decode_1_io_lsu_op),
- .io_mlu_valid(decode_1_io_mlu_valid),
- .io_mlu_addr(decode_1_io_mlu_addr),
- .io_mlu_op(decode_1_io_mlu_op),
- .io_dvu_op(decode_1_io_dvu_op),
- .io_vinst_valid(decode_1_io_vinst_valid),
- .io_vinst_ready(decode_1_io_vinst_ready),
- .io_vinst_addr(decode_1_io_vinst_addr),
- .io_vinst_inst(decode_1_io_vinst_inst),
- .io_vinst_op(decode_1_io_vinst_op),
- .io_branchTaken(decode_1_io_branchTaken),
- .io_interlock(decode_1_io_interlock),
- .io_serializeIn_mul(decode_1_io_serializeIn_mul),
- .io_serializeIn_jump(decode_1_io_serializeIn_jump),
- .io_serializeIn_brcond(decode_1_io_serializeIn_brcond),
- .io_serializeOut_mul(decode_1_io_serializeOut_mul),
- .io_serializeOut_jump(decode_1_io_serializeOut_jump),
- .io_serializeOut_brcond(decode_1_io_serializeOut_brcond)
- );
- Decode_2 decode_2 ( // @[Decode.scala 29:18]
- .clock(decode_2_clock),
- .reset(decode_2_reset),
- .io_halted(decode_2_io_halted),
- .io_inst_valid(decode_2_io_inst_valid),
- .io_inst_ready(decode_2_io_inst_ready),
- .io_inst_addr(decode_2_io_inst_addr),
- .io_inst_inst(decode_2_io_inst_inst),
- .io_inst_brchFwd(decode_2_io_inst_brchFwd),
- .io_scoreboard_regd(decode_2_io_scoreboard_regd),
- .io_scoreboard_comb(decode_2_io_scoreboard_comb),
- .io_scoreboard_spec(decode_2_io_scoreboard_spec),
- .io_rs1Read_valid(decode_2_io_rs1Read_valid),
- .io_rs1Read_addr(decode_2_io_rs1Read_addr),
- .io_rs1Set_valid(decode_2_io_rs1Set_valid),
- .io_rs1Set_value(decode_2_io_rs1Set_value),
- .io_rs2Read_valid(decode_2_io_rs2Read_valid),
- .io_rs2Read_addr(decode_2_io_rs2Read_addr),
- .io_rs2Set_valid(decode_2_io_rs2Set_valid),
- .io_rs2Set_value(decode_2_io_rs2Set_value),
- .io_rdMark_valid(decode_2_io_rdMark_valid),
- .io_rdMark_addr(decode_2_io_rdMark_addr),
- .io_busRead_bypass(decode_2_io_busRead_bypass),
- .io_busRead_immed(decode_2_io_busRead_immed),
- .io_alu_valid(decode_2_io_alu_valid),
- .io_alu_addr(decode_2_io_alu_addr),
- .io_alu_op(decode_2_io_alu_op),
- .io_bru_valid(decode_2_io_bru_valid),
- .io_bru_fwd(decode_2_io_bru_fwd),
- .io_bru_op(decode_2_io_bru_op),
- .io_bru_pc(decode_2_io_bru_pc),
- .io_bru_target(decode_2_io_bru_target),
- .io_bru_link(decode_2_io_bru_link),
- .io_csr_op(decode_2_io_csr_op),
- .io_lsu_valid(decode_2_io_lsu_valid),
- .io_lsu_ready(decode_2_io_lsu_ready),
- .io_lsu_addr(decode_2_io_lsu_addr),
- .io_lsu_op(decode_2_io_lsu_op),
- .io_mlu_valid(decode_2_io_mlu_valid),
- .io_mlu_addr(decode_2_io_mlu_addr),
- .io_mlu_op(decode_2_io_mlu_op),
- .io_dvu_op(decode_2_io_dvu_op),
- .io_vinst_valid(decode_2_io_vinst_valid),
- .io_vinst_ready(decode_2_io_vinst_ready),
- .io_vinst_addr(decode_2_io_vinst_addr),
- .io_vinst_inst(decode_2_io_vinst_inst),
- .io_vinst_op(decode_2_io_vinst_op),
- .io_branchTaken(decode_2_io_branchTaken),
- .io_interlock(decode_2_io_interlock),
- .io_serializeIn_mul(decode_2_io_serializeIn_mul),
- .io_serializeIn_jump(decode_2_io_serializeIn_jump),
- .io_serializeIn_brcond(decode_2_io_serializeIn_brcond),
- .io_serializeOut_mul(decode_2_io_serializeOut_mul),
- .io_serializeOut_jump(decode_2_io_serializeOut_jump),
- .io_serializeOut_brcond(decode_2_io_serializeOut_brcond)
- );
- Decode_3 decode_3 ( // @[Decode.scala 29:18]
- .clock(decode_3_clock),
- .reset(decode_3_reset),
- .io_halted(decode_3_io_halted),
- .io_inst_valid(decode_3_io_inst_valid),
- .io_inst_ready(decode_3_io_inst_ready),
- .io_inst_addr(decode_3_io_inst_addr),
- .io_inst_inst(decode_3_io_inst_inst),
- .io_inst_brchFwd(decode_3_io_inst_brchFwd),
- .io_scoreboard_regd(decode_3_io_scoreboard_regd),
- .io_scoreboard_comb(decode_3_io_scoreboard_comb),
- .io_rs1Read_valid(decode_3_io_rs1Read_valid),
- .io_rs1Read_addr(decode_3_io_rs1Read_addr),
- .io_rs1Set_valid(decode_3_io_rs1Set_valid),
- .io_rs1Set_value(decode_3_io_rs1Set_value),
- .io_rs2Read_valid(decode_3_io_rs2Read_valid),
- .io_rs2Read_addr(decode_3_io_rs2Read_addr),
- .io_rs2Set_valid(decode_3_io_rs2Set_valid),
- .io_rs2Set_value(decode_3_io_rs2Set_value),
- .io_rdMark_valid(decode_3_io_rdMark_valid),
- .io_rdMark_addr(decode_3_io_rdMark_addr),
- .io_busRead_bypass(decode_3_io_busRead_bypass),
- .io_busRead_immed(decode_3_io_busRead_immed),
- .io_alu_valid(decode_3_io_alu_valid),
- .io_alu_addr(decode_3_io_alu_addr),
- .io_alu_op(decode_3_io_alu_op),
- .io_bru_valid(decode_3_io_bru_valid),
- .io_bru_fwd(decode_3_io_bru_fwd),
- .io_bru_op(decode_3_io_bru_op),
- .io_bru_pc(decode_3_io_bru_pc),
- .io_bru_target(decode_3_io_bru_target),
- .io_bru_link(decode_3_io_bru_link),
- .io_csr_op(decode_3_io_csr_op),
- .io_lsu_valid(decode_3_io_lsu_valid),
- .io_lsu_ready(decode_3_io_lsu_ready),
- .io_lsu_addr(decode_3_io_lsu_addr),
- .io_lsu_op(decode_3_io_lsu_op),
- .io_mlu_valid(decode_3_io_mlu_valid),
- .io_mlu_addr(decode_3_io_mlu_addr),
- .io_mlu_op(decode_3_io_mlu_op),
- .io_dvu_op(decode_3_io_dvu_op),
- .io_vinst_valid(decode_3_io_vinst_valid),
- .io_vinst_ready(decode_3_io_vinst_ready),
- .io_vinst_addr(decode_3_io_vinst_addr),
- .io_vinst_inst(decode_3_io_vinst_inst),
- .io_vinst_op(decode_3_io_vinst_op),
- .io_branchTaken(decode_3_io_branchTaken),
- .io_interlock(decode_3_io_interlock),
- .io_serializeIn_mul(decode_3_io_serializeIn_mul),
- .io_serializeIn_jump(decode_3_io_serializeIn_jump),
- .io_serializeIn_brcond(decode_3_io_serializeIn_brcond)
- );
- Alu alu_0 ( // @[Alu.scala 23:18]
- .clock(alu_0_clock),
- .reset(alu_0_reset),
- .io_req_valid(alu_0_io_req_valid),
- .io_req_addr(alu_0_io_req_addr),
- .io_req_op(alu_0_io_req_op),
- .io_rs1_valid(alu_0_io_rs1_valid),
- .io_rs1_data(alu_0_io_rs1_data),
- .io_rs2_valid(alu_0_io_rs2_valid),
- .io_rs2_data(alu_0_io_rs2_data),
- .io_rd_valid(alu_0_io_rd_valid),
- .io_rd_addr(alu_0_io_rd_addr),
- .io_rd_data(alu_0_io_rd_data)
- );
- Alu alu_1 ( // @[Alu.scala 23:18]
- .clock(alu_1_clock),
- .reset(alu_1_reset),
- .io_req_valid(alu_1_io_req_valid),
- .io_req_addr(alu_1_io_req_addr),
- .io_req_op(alu_1_io_req_op),
- .io_rs1_valid(alu_1_io_rs1_valid),
- .io_rs1_data(alu_1_io_rs1_data),
- .io_rs2_valid(alu_1_io_rs2_valid),
- .io_rs2_data(alu_1_io_rs2_data),
- .io_rd_valid(alu_1_io_rd_valid),
- .io_rd_addr(alu_1_io_rd_addr),
- .io_rd_data(alu_1_io_rd_data)
- );
- Alu alu_2 ( // @[Alu.scala 23:18]
- .clock(alu_2_clock),
- .reset(alu_2_reset),
- .io_req_valid(alu_2_io_req_valid),
- .io_req_addr(alu_2_io_req_addr),
- .io_req_op(alu_2_io_req_op),
- .io_rs1_valid(alu_2_io_rs1_valid),
- .io_rs1_data(alu_2_io_rs1_data),
- .io_rs2_valid(alu_2_io_rs2_valid),
- .io_rs2_data(alu_2_io_rs2_data),
- .io_rd_valid(alu_2_io_rd_valid),
- .io_rd_addr(alu_2_io_rd_addr),
- .io_rd_data(alu_2_io_rd_data)
- );
- Alu alu_3 ( // @[Alu.scala 23:18]
- .clock(alu_3_clock),
- .reset(alu_3_reset),
- .io_req_valid(alu_3_io_req_valid),
- .io_req_addr(alu_3_io_req_addr),
- .io_req_op(alu_3_io_req_op),
- .io_rs1_valid(alu_3_io_rs1_valid),
- .io_rs1_data(alu_3_io_rs1_data),
- .io_rs2_valid(alu_3_io_rs2_valid),
- .io_rs2_data(alu_3_io_rs2_data),
- .io_rd_valid(alu_3_io_rd_valid),
- .io_rd_addr(alu_3_io_rd_addr),
- .io_rd_data(alu_3_io_rd_data)
- );
- Bru bru_0 ( // @[Bru.scala 23:18]
- .clock(bru_0_clock),
- .reset(bru_0_reset),
- .io_req_valid(bru_0_io_req_valid),
- .io_req_fwd(bru_0_io_req_fwd),
- .io_req_op(bru_0_io_req_op),
- .io_req_pc(bru_0_io_req_pc),
- .io_req_target(bru_0_io_req_target),
- .io_req_link(bru_0_io_req_link),
- .io_csr_in_mode_valid(bru_0_io_csr_in_mode_valid),
- .io_csr_in_mode_bits(bru_0_io_csr_in_mode_bits),
- .io_csr_in_mcause_valid(bru_0_io_csr_in_mcause_valid),
- .io_csr_in_mcause_bits(bru_0_io_csr_in_mcause_bits),
- .io_csr_in_mepc_valid(bru_0_io_csr_in_mepc_valid),
- .io_csr_in_mepc_bits(bru_0_io_csr_in_mepc_bits),
- .io_csr_in_mtval_valid(bru_0_io_csr_in_mtval_valid),
- .io_csr_in_mtval_bits(bru_0_io_csr_in_mtval_bits),
- .io_csr_in_halt(bru_0_io_csr_in_halt),
- .io_csr_in_fault(bru_0_io_csr_in_fault),
- .io_csr_out_mode(bru_0_io_csr_out_mode),
- .io_csr_out_mepc(bru_0_io_csr_out_mepc),
- .io_csr_out_mtvec(bru_0_io_csr_out_mtvec),
- .io_rs1_valid(bru_0_io_rs1_valid),
- .io_rs1_data(bru_0_io_rs1_data),
- .io_rs2_valid(bru_0_io_rs2_valid),
- .io_rs2_data(bru_0_io_rs2_data),
- .io_rd_valid(bru_0_io_rd_valid),
- .io_rd_addr(bru_0_io_rd_addr),
- .io_rd_data(bru_0_io_rd_data),
- .io_taken_valid(bru_0_io_taken_valid),
- .io_taken_value(bru_0_io_taken_value),
- .io_target_data(bru_0_io_target_data),
- .io_interlock(bru_0_io_interlock),
- .io_iflush(bru_0_io_iflush)
- );
- Bru bru_1 ( // @[Bru.scala 23:18]
- .clock(bru_1_clock),
- .reset(bru_1_reset),
- .io_req_valid(bru_1_io_req_valid),
- .io_req_fwd(bru_1_io_req_fwd),
- .io_req_op(bru_1_io_req_op),
- .io_req_pc(bru_1_io_req_pc),
- .io_req_target(bru_1_io_req_target),
- .io_req_link(bru_1_io_req_link),
- .io_csr_in_mode_valid(bru_1_io_csr_in_mode_valid),
- .io_csr_in_mode_bits(bru_1_io_csr_in_mode_bits),
- .io_csr_in_mcause_valid(bru_1_io_csr_in_mcause_valid),
- .io_csr_in_mcause_bits(bru_1_io_csr_in_mcause_bits),
- .io_csr_in_mepc_valid(bru_1_io_csr_in_mepc_valid),
- .io_csr_in_mepc_bits(bru_1_io_csr_in_mepc_bits),
- .io_csr_in_mtval_valid(bru_1_io_csr_in_mtval_valid),
- .io_csr_in_mtval_bits(bru_1_io_csr_in_mtval_bits),
- .io_csr_in_halt(bru_1_io_csr_in_halt),
- .io_csr_in_fault(bru_1_io_csr_in_fault),
- .io_csr_out_mode(bru_1_io_csr_out_mode),
- .io_csr_out_mepc(bru_1_io_csr_out_mepc),
- .io_csr_out_mtvec(bru_1_io_csr_out_mtvec),
- .io_rs1_valid(bru_1_io_rs1_valid),
- .io_rs1_data(bru_1_io_rs1_data),
- .io_rs2_valid(bru_1_io_rs2_valid),
- .io_rs2_data(bru_1_io_rs2_data),
- .io_rd_valid(bru_1_io_rd_valid),
- .io_rd_addr(bru_1_io_rd_addr),
- .io_rd_data(bru_1_io_rd_data),
- .io_taken_valid(bru_1_io_taken_valid),
- .io_taken_value(bru_1_io_taken_value),
- .io_target_data(bru_1_io_target_data),
- .io_interlock(bru_1_io_interlock),
- .io_iflush(bru_1_io_iflush)
- );
- Bru bru_2 ( // @[Bru.scala 23:18]
- .clock(bru_2_clock),
- .reset(bru_2_reset),
- .io_req_valid(bru_2_io_req_valid),
- .io_req_fwd(bru_2_io_req_fwd),
- .io_req_op(bru_2_io_req_op),
- .io_req_pc(bru_2_io_req_pc),
- .io_req_target(bru_2_io_req_target),
- .io_req_link(bru_2_io_req_link),
- .io_csr_in_mode_valid(bru_2_io_csr_in_mode_valid),
- .io_csr_in_mode_bits(bru_2_io_csr_in_mode_bits),
- .io_csr_in_mcause_valid(bru_2_io_csr_in_mcause_valid),
- .io_csr_in_mcause_bits(bru_2_io_csr_in_mcause_bits),
- .io_csr_in_mepc_valid(bru_2_io_csr_in_mepc_valid),
- .io_csr_in_mepc_bits(bru_2_io_csr_in_mepc_bits),
- .io_csr_in_mtval_valid(bru_2_io_csr_in_mtval_valid),
- .io_csr_in_mtval_bits(bru_2_io_csr_in_mtval_bits),
- .io_csr_in_halt(bru_2_io_csr_in_halt),
- .io_csr_in_fault(bru_2_io_csr_in_fault),
- .io_csr_out_mode(bru_2_io_csr_out_mode),
- .io_csr_out_mepc(bru_2_io_csr_out_mepc),
- .io_csr_out_mtvec(bru_2_io_csr_out_mtvec),
- .io_rs1_valid(bru_2_io_rs1_valid),
- .io_rs1_data(bru_2_io_rs1_data),
- .io_rs2_valid(bru_2_io_rs2_valid),
- .io_rs2_data(bru_2_io_rs2_data),
- .io_rd_valid(bru_2_io_rd_valid),
- .io_rd_addr(bru_2_io_rd_addr),
- .io_rd_data(bru_2_io_rd_data),
- .io_taken_valid(bru_2_io_taken_valid),
- .io_taken_value(bru_2_io_taken_value),
- .io_target_data(bru_2_io_target_data),
- .io_interlock(bru_2_io_interlock),
- .io_iflush(bru_2_io_iflush)
- );
- Bru bru_3 ( // @[Bru.scala 23:18]
- .clock(bru_3_clock),
- .reset(bru_3_reset),
- .io_req_valid(bru_3_io_req_valid),
- .io_req_fwd(bru_3_io_req_fwd),
- .io_req_op(bru_3_io_req_op),
- .io_req_pc(bru_3_io_req_pc),
- .io_req_target(bru_3_io_req_target),
- .io_req_link(bru_3_io_req_link),
- .io_csr_in_mode_valid(bru_3_io_csr_in_mode_valid),
- .io_csr_in_mode_bits(bru_3_io_csr_in_mode_bits),
- .io_csr_in_mcause_valid(bru_3_io_csr_in_mcause_valid),
- .io_csr_in_mcause_bits(bru_3_io_csr_in_mcause_bits),
- .io_csr_in_mepc_valid(bru_3_io_csr_in_mepc_valid),
- .io_csr_in_mepc_bits(bru_3_io_csr_in_mepc_bits),
- .io_csr_in_mtval_valid(bru_3_io_csr_in_mtval_valid),
- .io_csr_in_mtval_bits(bru_3_io_csr_in_mtval_bits),
- .io_csr_in_halt(bru_3_io_csr_in_halt),
- .io_csr_in_fault(bru_3_io_csr_in_fault),
- .io_csr_out_mode(bru_3_io_csr_out_mode),
- .io_csr_out_mepc(bru_3_io_csr_out_mepc),
- .io_csr_out_mtvec(bru_3_io_csr_out_mtvec),
- .io_rs1_valid(bru_3_io_rs1_valid),
- .io_rs1_data(bru_3_io_rs1_data),
- .io_rs2_valid(bru_3_io_rs2_valid),
- .io_rs2_data(bru_3_io_rs2_data),
- .io_rd_valid(bru_3_io_rd_valid),
- .io_rd_addr(bru_3_io_rd_addr),
- .io_rd_data(bru_3_io_rd_data),
- .io_taken_valid(bru_3_io_taken_valid),
- .io_taken_value(bru_3_io_taken_value),
- .io_target_data(bru_3_io_target_data),
- .io_interlock(bru_3_io_interlock),
- .io_iflush(bru_3_io_iflush)
- );
- Csr csr ( // @[Csr.scala 23:18]
- .clock(csr_clock),
- .reset(csr_reset),
- .io_csr_in_value_0(csr_io_csr_in_value_0),
- .io_req_valid(csr_io_req_valid),
- .io_req_addr(csr_io_req_addr),
- .io_req_index(csr_io_req_index),
- .io_req_op(csr_io_req_op),
- .io_rs1_valid(csr_io_rs1_valid),
- .io_rs1_data(csr_io_rs1_data),
- .io_rd_valid(csr_io_rd_valid),
- .io_rd_addr(csr_io_rd_addr),
- .io_rd_data(csr_io_rd_data),
- .io_bru_in_mode_valid(csr_io_bru_in_mode_valid),
- .io_bru_in_mode_bits(csr_io_bru_in_mode_bits),
- .io_bru_in_mcause_valid(csr_io_bru_in_mcause_valid),
- .io_bru_in_mcause_bits(csr_io_bru_in_mcause_bits),
- .io_bru_in_mepc_valid(csr_io_bru_in_mepc_valid),
- .io_bru_in_mepc_bits(csr_io_bru_in_mepc_bits),
- .io_bru_in_mtval_valid(csr_io_bru_in_mtval_valid),
- .io_bru_in_mtval_bits(csr_io_bru_in_mtval_bits),
- .io_bru_in_halt(csr_io_bru_in_halt),
- .io_bru_in_fault(csr_io_bru_in_fault),
- .io_bru_out_mode(csr_io_bru_out_mode),
- .io_bru_out_mepc(csr_io_bru_out_mepc),
- .io_bru_out_mtvec(csr_io_bru_out_mtvec),
- .io_vcore_undef(csr_io_vcore_undef),
- .io_halted(csr_io_halted),
- .io_fault(csr_io_fault)
- );
- Lsu lsu ( // @[Lsu.scala 23:18]
- .clock(lsu_clock),
- .reset(lsu_reset),
- .io_req_0_valid(lsu_io_req_0_valid),
- .io_req_0_ready(lsu_io_req_0_ready),
- .io_req_0_addr(lsu_io_req_0_addr),
- .io_req_0_op(lsu_io_req_0_op),
- .io_req_1_valid(lsu_io_req_1_valid),
- .io_req_1_ready(lsu_io_req_1_ready),
- .io_req_1_addr(lsu_io_req_1_addr),
- .io_req_1_op(lsu_io_req_1_op),
- .io_req_2_valid(lsu_io_req_2_valid),
- .io_req_2_ready(lsu_io_req_2_ready),
- .io_req_2_addr(lsu_io_req_2_addr),
- .io_req_2_op(lsu_io_req_2_op),
- .io_req_3_valid(lsu_io_req_3_valid),
- .io_req_3_ready(lsu_io_req_3_ready),
- .io_req_3_addr(lsu_io_req_3_addr),
- .io_req_3_op(lsu_io_req_3_op),
- .io_busPort_addr_0(lsu_io_busPort_addr_0),
- .io_busPort_addr_1(lsu_io_busPort_addr_1),
- .io_busPort_addr_2(lsu_io_busPort_addr_2),
- .io_busPort_addr_3(lsu_io_busPort_addr_3),
- .io_busPort_data_0(lsu_io_busPort_data_0),
- .io_busPort_data_1(lsu_io_busPort_data_1),
- .io_busPort_data_2(lsu_io_busPort_data_2),
- .io_busPort_data_3(lsu_io_busPort_data_3),
- .io_rd_valid(lsu_io_rd_valid),
- .io_rd_addr(lsu_io_rd_addr),
- .io_rd_data(lsu_io_rd_data),
- .io_dbus_valid(lsu_io_dbus_valid),
- .io_dbus_ready(lsu_io_dbus_ready),
- .io_dbus_write(lsu_io_dbus_write),
- .io_dbus_addr(lsu_io_dbus_addr),
- .io_dbus_adrx(lsu_io_dbus_adrx),
- .io_dbus_size(lsu_io_dbus_size),
- .io_dbus_wdata(lsu_io_dbus_wdata),
- .io_dbus_wmask(lsu_io_dbus_wmask),
- .io_dbus_rdata(lsu_io_dbus_rdata),
- .io_flush_valid(lsu_io_flush_valid),
- .io_flush_ready(lsu_io_flush_ready),
- .io_flush_all(lsu_io_flush_all),
- .io_flush_fencei(lsu_io_flush_fencei),
- .io_ubus_valid(lsu_io_ubus_valid),
- .io_ubus_ready(lsu_io_ubus_ready),
- .io_ubus_write(lsu_io_ubus_write),
- .io_ubus_addr(lsu_io_ubus_addr),
- .io_ubus_wdata(lsu_io_ubus_wdata),
- .io_ubus_wmask(lsu_io_ubus_wmask),
- .io_ubus_rdata(lsu_io_ubus_rdata),
- .io_vldst(lsu_io_vldst)
- );
- Mlu mlu ( // @[Mlu.scala 23:18]
- .clock(mlu_clock),
- .reset(mlu_reset),
- .io_req_0_valid(mlu_io_req_0_valid),
- .io_req_0_addr(mlu_io_req_0_addr),
- .io_req_0_op(mlu_io_req_0_op),
- .io_req_1_valid(mlu_io_req_1_valid),
- .io_req_1_addr(mlu_io_req_1_addr),
- .io_req_1_op(mlu_io_req_1_op),
- .io_req_2_valid(mlu_io_req_2_valid),
- .io_req_2_addr(mlu_io_req_2_addr),
- .io_req_2_op(mlu_io_req_2_op),
- .io_req_3_valid(mlu_io_req_3_valid),
- .io_req_3_addr(mlu_io_req_3_addr),
- .io_req_3_op(mlu_io_req_3_op),
- .io_rs1_0_valid(mlu_io_rs1_0_valid),
- .io_rs1_0_data(mlu_io_rs1_0_data),
- .io_rs1_1_valid(mlu_io_rs1_1_valid),
- .io_rs1_1_data(mlu_io_rs1_1_data),
- .io_rs1_2_valid(mlu_io_rs1_2_valid),
- .io_rs1_2_data(mlu_io_rs1_2_data),
- .io_rs1_3_valid(mlu_io_rs1_3_valid),
- .io_rs1_3_data(mlu_io_rs1_3_data),
- .io_rs2_0_valid(mlu_io_rs2_0_valid),
- .io_rs2_0_data(mlu_io_rs2_0_data),
- .io_rs2_1_valid(mlu_io_rs2_1_valid),
- .io_rs2_1_data(mlu_io_rs2_1_data),
- .io_rs2_2_valid(mlu_io_rs2_2_valid),
- .io_rs2_2_data(mlu_io_rs2_2_data),
- .io_rs2_3_valid(mlu_io_rs2_3_valid),
- .io_rs2_3_data(mlu_io_rs2_3_data),
- .io_rd_valid(mlu_io_rd_valid),
- .io_rd_addr(mlu_io_rd_addr),
- .io_rd_data(mlu_io_rd_data)
- );
- Dvu dvu ( // @[Dvu.scala 23:18]
- .clock(dvu_clock),
- .reset(dvu_reset),
- .io_req_valid(dvu_io_req_valid),
- .io_req_ready(dvu_io_req_ready),
- .io_req_addr(dvu_io_req_addr),
- .io_req_op(dvu_io_req_op),
- .io_rs1_data(dvu_io_rs1_data),
- .io_rs2_data(dvu_io_rs2_data),
- .io_rd_valid(dvu_io_rd_valid),
- .io_rd_ready(dvu_io_rd_ready),
- .io_rd_addr(dvu_io_rd_addr),
- .io_rd_data(dvu_io_rd_data)
- );
- assign io_halted = csr_io_halted; // @[SCore.scala 185:13]
- assign io_fault = csr_io_fault; // @[SCore.scala 186:13]
- assign io_ibus_valid = fetch_io_ibus_valid; // @[SCore.scala 292:11]
- assign io_ibus_addr = fetch_io_ibus_addr; // @[SCore.scala 292:11]
- assign io_dbus_valid = lsu_io_dbus_valid; // @[SCore.scala 296:11]
- assign io_dbus_write = lsu_io_dbus_write; // @[SCore.scala 296:11]
- assign io_dbus_addr = lsu_io_dbus_addr; // @[SCore.scala 296:11]
- assign io_dbus_adrx = lsu_io_dbus_adrx; // @[SCore.scala 296:11]
- assign io_dbus_size = lsu_io_dbus_size; // @[SCore.scala 296:11]
- assign io_dbus_wdata = lsu_io_dbus_wdata; // @[SCore.scala 296:11]
- assign io_dbus_wmask = lsu_io_dbus_wmask; // @[SCore.scala 296:11]
- assign io_ubus_valid = lsu_io_ubus_valid; // @[SCore.scala 297:11]
- assign io_ubus_write = lsu_io_ubus_write; // @[SCore.scala 297:11]
- assign io_ubus_addr = lsu_io_ubus_addr; // @[SCore.scala 297:11]
- assign io_ubus_wdata = lsu_io_ubus_wdata; // @[SCore.scala 297:11]
- assign io_ubus_wmask = lsu_io_ubus_wmask; // @[SCore.scala 297:11]
- assign io_vldst = lsu_io_vldst; // @[SCore.scala 299:12]
- assign io_vcore_vinst_0_valid = decode_0_io_vinst_valid; // @[SCore.scala 283:23]
- assign io_vcore_vinst_0_addr = decode_0_io_vinst_addr; // @[SCore.scala 283:23]
- assign io_vcore_vinst_0_inst = decode_0_io_vinst_inst; // @[SCore.scala 283:23]
- assign io_vcore_vinst_0_op = decode_0_io_vinst_op; // @[SCore.scala 283:23]
- assign io_vcore_vinst_1_valid = decode_1_io_vinst_valid; // @[SCore.scala 283:23]
- assign io_vcore_vinst_1_addr = decode_1_io_vinst_addr; // @[SCore.scala 283:23]
- assign io_vcore_vinst_1_inst = decode_1_io_vinst_inst; // @[SCore.scala 283:23]
- assign io_vcore_vinst_1_op = decode_1_io_vinst_op; // @[SCore.scala 283:23]
- assign io_vcore_vinst_2_valid = decode_2_io_vinst_valid; // @[SCore.scala 283:23]
- assign io_vcore_vinst_2_addr = decode_2_io_vinst_addr; // @[SCore.scala 283:23]
- assign io_vcore_vinst_2_inst = decode_2_io_vinst_inst; // @[SCore.scala 283:23]
- assign io_vcore_vinst_2_op = decode_2_io_vinst_op; // @[SCore.scala 283:23]
- assign io_vcore_vinst_3_valid = decode_3_io_vinst_valid; // @[SCore.scala 283:23]
- assign io_vcore_vinst_3_addr = decode_3_io_vinst_addr; // @[SCore.scala 283:23]
- assign io_vcore_vinst_3_inst = decode_3_io_vinst_inst; // @[SCore.scala 283:23]
- assign io_vcore_vinst_3_op = decode_3_io_vinst_op; // @[SCore.scala 283:23]
- assign io_vcore_rs_0_data = regfile_io_readData_0_data; // @[SCore.scala 287:20]
- assign io_vcore_rs_1_data = regfile_io_readData_1_data; // @[SCore.scala 287:20]
- assign io_vcore_rs_2_data = regfile_io_readData_2_data; // @[SCore.scala 287:20]
- assign io_vcore_rs_3_data = regfile_io_readData_3_data; // @[SCore.scala 287:20]
- assign io_vcore_rs_4_data = regfile_io_readData_4_data; // @[SCore.scala 287:20]
- assign io_vcore_rs_5_data = regfile_io_readData_5_data; // @[SCore.scala 287:20]
- assign io_vcore_rs_6_data = regfile_io_readData_6_data; // @[SCore.scala 287:20]
- assign io_vcore_rs_7_data = regfile_io_readData_7_data; // @[SCore.scala 287:20]
- assign io_iflush_valid = iflush; // @[SCore.scala 172:19]
- assign io_dflush_valid = lsu_io_flush_valid; // @[SCore.scala 75:19]
- assign io_dflush_all = lsu_io_flush_all; // @[SCore.scala 76:19]
- assign io_slog_valid = slogValid; // @[SCore.scala 312:17]
- assign io_slog_addr = {{3'd0}, _io_slog_addr_T}; // @[SCore.scala 313:17]
- assign io_slog_data = slogValid ? regfile_io_readData_0_data : 32'h0; // @[Library.scala 22:8]
- assign regfile_clock = clock;
- assign regfile_reset = reset;
- assign regfile_io_readAddr_0_valid = decode_0_io_rs1Read_valid; // @[SCore.scala 230:36]
- assign regfile_io_readAddr_0_addr = decode_0_io_rs1Read_addr; // @[SCore.scala 230:36]
- assign regfile_io_readAddr_1_valid = decode_0_io_rs2Read_valid; // @[SCore.scala 231:36]
- assign regfile_io_readAddr_1_addr = decode_0_io_rs2Read_addr; // @[SCore.scala 231:36]
- assign regfile_io_readAddr_2_valid = decode_1_io_rs1Read_valid; // @[SCore.scala 230:36]
- assign regfile_io_readAddr_2_addr = decode_1_io_rs1Read_addr; // @[SCore.scala 230:36]
- assign regfile_io_readAddr_3_valid = decode_1_io_rs2Read_valid; // @[SCore.scala 231:36]
- assign regfile_io_readAddr_3_addr = decode_1_io_rs2Read_addr; // @[SCore.scala 231:36]
- assign regfile_io_readAddr_4_valid = decode_2_io_rs1Read_valid; // @[SCore.scala 230:36]
- assign regfile_io_readAddr_4_addr = decode_2_io_rs1Read_addr; // @[SCore.scala 230:36]
- assign regfile_io_readAddr_5_valid = decode_2_io_rs2Read_valid; // @[SCore.scala 231:36]
- assign regfile_io_readAddr_5_addr = decode_2_io_rs2Read_addr; // @[SCore.scala 231:36]
- assign regfile_io_readAddr_6_valid = decode_3_io_rs1Read_valid; // @[SCore.scala 230:36]
- assign regfile_io_readAddr_6_addr = decode_3_io_rs1Read_addr; // @[SCore.scala 230:36]
- assign regfile_io_readAddr_7_valid = decode_3_io_rs2Read_valid; // @[SCore.scala 231:36]
- assign regfile_io_readAddr_7_addr = decode_3_io_rs2Read_addr; // @[SCore.scala 231:36]
- assign regfile_io_readSet_0_valid = decode_0_io_rs1Set_valid; // @[SCore.scala 232:35]
- assign regfile_io_readSet_0_value = decode_0_io_rs1Set_value; // @[SCore.scala 232:35]
- assign regfile_io_readSet_1_valid = decode_0_io_rs2Set_valid; // @[SCore.scala 233:35]
- assign regfile_io_readSet_1_value = decode_0_io_rs2Set_value; // @[SCore.scala 233:35]
- assign regfile_io_readSet_2_valid = decode_1_io_rs1Set_valid; // @[SCore.scala 232:35]
- assign regfile_io_readSet_2_value = decode_1_io_rs1Set_value; // @[SCore.scala 232:35]
- assign regfile_io_readSet_3_valid = decode_1_io_rs2Set_valid; // @[SCore.scala 233:35]
- assign regfile_io_readSet_3_value = decode_1_io_rs2Set_value; // @[SCore.scala 233:35]
- assign regfile_io_readSet_4_valid = decode_2_io_rs1Set_valid; // @[SCore.scala 232:35]
- assign regfile_io_readSet_4_value = decode_2_io_rs1Set_value; // @[SCore.scala 232:35]
- assign regfile_io_readSet_5_valid = decode_2_io_rs2Set_valid; // @[SCore.scala 233:35]
- assign regfile_io_readSet_5_value = decode_2_io_rs2Set_value; // @[SCore.scala 233:35]
- assign regfile_io_readSet_6_valid = decode_3_io_rs1Set_valid; // @[SCore.scala 232:35]
- assign regfile_io_readSet_6_value = decode_3_io_rs1Set_value; // @[SCore.scala 232:35]
- assign regfile_io_readSet_7_valid = decode_3_io_rs2Set_valid; // @[SCore.scala 233:35]
- assign regfile_io_readSet_7_value = decode_3_io_rs2Set_value; // @[SCore.scala 233:35]
- assign regfile_io_writeAddr_0_valid = decode_0_io_rdMark_valid; // @[SCore.scala 234:29]
- assign regfile_io_writeAddr_0_addr = decode_0_io_rdMark_addr; // @[SCore.scala 234:29]
- assign regfile_io_writeAddr_1_valid = decode_1_io_rdMark_valid; // @[SCore.scala 234:29]
- assign regfile_io_writeAddr_1_addr = decode_1_io_rdMark_addr; // @[SCore.scala 234:29]
- assign regfile_io_writeAddr_2_valid = decode_2_io_rdMark_valid; // @[SCore.scala 234:29]
- assign regfile_io_writeAddr_2_addr = decode_2_io_rdMark_addr; // @[SCore.scala 234:29]
- assign regfile_io_writeAddr_3_valid = decode_3_io_rdMark_valid; // @[SCore.scala 234:29]
- assign regfile_io_writeAddr_3_addr = decode_3_io_rdMark_addr; // @[SCore.scala 234:29]
- assign regfile_io_busAddr_0_bypass = decode_0_io_busRead_bypass; // @[SCore.scala 235:27]
- assign regfile_io_busAddr_0_immen = decode_0_io_busRead_immen; // @[SCore.scala 235:27]
- assign regfile_io_busAddr_0_immed = decode_0_io_busRead_immed; // @[SCore.scala 235:27]
- assign regfile_io_busAddr_1_bypass = decode_1_io_busRead_bypass; // @[SCore.scala 235:27]
- assign regfile_io_busAddr_1_immed = decode_1_io_busRead_immed; // @[SCore.scala 235:27]
- assign regfile_io_busAddr_2_bypass = decode_2_io_busRead_bypass; // @[SCore.scala 235:27]
- assign regfile_io_busAddr_2_immed = decode_2_io_busRead_immed; // @[SCore.scala 235:27]
- assign regfile_io_busAddr_3_bypass = decode_3_io_busRead_bypass; // @[SCore.scala 235:27]
- assign regfile_io_busAddr_3_immed = decode_3_io_busRead_immed; // @[SCore.scala 235:27]
- assign regfile_io_writeData_0_valid = _regfile_io_writeData_0_valid_T | bru_0_io_rd_valid | io_vcore_rd_0_valid; // @[SCore.scala 243:79]
- assign regfile_io_writeData_0_addr = _regfile_io_writeData_0_addr_T_4 | _regfile_io_writeData_0_addr_T_5; // @[SCore.scala 249:54]
- assign regfile_io_writeData_0_data = _regfile_io_writeData_0_data_T_4 | _regfile_io_writeData_0_data_T_5; // @[SCore.scala 255:54]
- assign regfile_io_writeData_1_valid = _regfile_io_writeData_1_valid_T | bru_1_io_rd_valid | io_vcore_rd_1_valid; // @[SCore.scala 243:79]
- assign regfile_io_writeData_1_addr = _regfile_io_writeData_1_addr_T_4 | _regfile_io_writeData_1_addr_T_5; // @[SCore.scala 249:54]
- assign regfile_io_writeData_1_data = _regfile_io_writeData_1_data_T_4 | _regfile_io_writeData_1_data_T_5; // @[SCore.scala 255:54]
- assign regfile_io_writeData_2_valid = _regfile_io_writeData_2_valid_T | bru_2_io_rd_valid | io_vcore_rd_2_valid; // @[SCore.scala 243:79]
- assign regfile_io_writeData_2_addr = _regfile_io_writeData_2_addr_T_4 | _regfile_io_writeData_2_addr_T_5; // @[SCore.scala 249:54]
- assign regfile_io_writeData_2_data = _regfile_io_writeData_2_data_T_4 | _regfile_io_writeData_2_data_T_5; // @[SCore.scala 255:54]
- assign regfile_io_writeData_3_valid = _regfile_io_writeData_3_valid_T | bru_3_io_rd_valid | io_vcore_rd_3_valid; // @[SCore.scala 243:79]
- assign regfile_io_writeData_3_addr = _regfile_io_writeData_3_addr_T_4 | _regfile_io_writeData_3_addr_T_5; // @[SCore.scala 249:54]
- assign regfile_io_writeData_3_data = _regfile_io_writeData_3_data_T_4 | _regfile_io_writeData_3_data_T_5; // @[SCore.scala 255:54]
- assign regfile_io_writeData_4_valid = mlu_io_rd_valid | dvu_io_rd_valid; // @[SCore.scala 263:52]
- assign regfile_io_writeData_4_addr = mlu_io_rd_valid ? mlu_io_rd_addr : dvu_io_rd_addr; // @[SCore.scala 264:38]
- assign regfile_io_writeData_4_data = mlu_io_rd_valid ? mlu_io_rd_data : dvu_io_rd_data; // @[SCore.scala 265:38]
- assign regfile_io_writeData_5_valid = lsu_io_rd_valid; // @[SCore.scala 268:33]
- assign regfile_io_writeData_5_addr = lsu_io_rd_addr; // @[SCore.scala 269:33]
- assign regfile_io_writeData_5_data = lsu_io_rd_data; // @[SCore.scala 270:33]
- assign regfile_io_writeMask_0_valid = 1'h0; // @[SCore.scala 272:33]
- assign regfile_io_writeMask_1_valid = regfile_io_writeMask_0_valid | bru_0_io_taken_valid; // @[SCore.scala 273:66]
- assign regfile_io_writeMask_2_valid = regfile_io_writeMask_1_valid | bru_1_io_taken_valid; // @[SCore.scala 275:66]
- assign regfile_io_writeMask_3_valid = regfile_io_writeMask_2_valid | bru_2_io_taken_valid; // @[SCore.scala 277:66]
- assign fetch_clock = clock;
- assign fetch_reset = reset;
- assign fetch_io_csr_value_0 = io_csr_in_value_0; // @[SCore.scala 86:16]
- assign fetch_io_ibus_ready = io_ibus_ready; // @[SCore.scala 292:11]
- assign fetch_io_ibus_rdata = io_ibus_rdata; // @[SCore.scala 292:11]
- assign fetch_io_inst_lanes_0_ready = decode_0_io_inst_ready; // @[SCore.scala 106:61]
- assign fetch_io_inst_lanes_1_ready = decode_1_io_inst_ready & decode_0_io_inst_ready; // @[SCore.scala 106:61]
- assign fetch_io_inst_lanes_2_ready = decode_2_io_inst_ready & mask_2; // @[SCore.scala 106:61]
- assign fetch_io_inst_lanes_3_ready = decode_3_io_inst_ready & mask_3; // @[SCore.scala 106:61]
- assign fetch_io_branch_0_valid = bru_0_io_taken_valid; // @[SCore.scala 89:24]
- assign fetch_io_branch_0_value = bru_0_io_taken_value; // @[SCore.scala 89:24]
- assign fetch_io_branch_1_valid = bru_1_io_taken_valid; // @[SCore.scala 89:24]
- assign fetch_io_branch_1_value = bru_1_io_taken_value; // @[SCore.scala 89:24]
- assign fetch_io_branch_2_valid = bru_2_io_taken_valid; // @[SCore.scala 89:24]
- assign fetch_io_branch_2_value = bru_2_io_taken_value; // @[SCore.scala 89:24]
- assign fetch_io_branch_3_valid = bru_3_io_taken_valid; // @[SCore.scala 89:24]
- assign fetch_io_branch_3_value = bru_3_io_taken_value; // @[SCore.scala 89:24]
- assign fetch_io_linkPort_valid = regfile_io_linkPort_valid; // @[SCore.scala 92:21]
- assign fetch_io_linkPort_value = regfile_io_linkPort_value; // @[SCore.scala 92:21]
- assign fetch_io_iflush_valid = iflush; // @[SCore.scala 94:25]
- assign decode_0_clock = clock;
- assign decode_0_reset = reset;
- assign decode_0_io_halted = csr_io_halted; // @[SCore.scala 112:25]
- assign decode_0_io_inst_valid = fetch_io_inst_lanes_0_valid; // @[SCore.scala 105:61]
- assign decode_0_io_inst_addr = fetch_io_inst_lanes_0_addr; // @[SCore.scala 107:28]
- assign decode_0_io_inst_inst = fetch_io_inst_lanes_0_inst; // @[SCore.scala 108:28]
- assign decode_0_io_inst_brchFwd = fetch_io_inst_lanes_0_brchFwd; // @[SCore.scala 109:31]
- assign decode_0_io_scoreboard_regd = regfile_io_scoreboard_regd; // @[SCore.scala 136:32]
- assign decode_0_io_scoreboard_comb = regfile_io_scoreboard_comb; // @[SCore.scala 135:32]
- assign decode_0_io_mactive = io_vcore_mactive; // @[SCore.scala 145:24]
- assign decode_0_io_lsu_ready = lsu_io_req_0_ready; // @[SCore.scala 197:28]
- assign decode_0_io_dvu_ready = dvu_io_req_ready; // @[SCore.scala 217:14]
- assign decode_0_io_vinst_ready = io_vcore_vinst_0_ready; // @[SCore.scala 283:23]
- assign decode_0_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 62:43]
- assign decode_0_io_interlock = bru_0_io_interlock; // @[SCore.scala 116:26]
- assign decode_1_clock = clock;
- assign decode_1_reset = reset;
- assign decode_1_io_halted = csr_io_halted; // @[SCore.scala 112:25]
- assign decode_1_io_inst_valid = fetch_io_inst_lanes_1_valid & _fetch_io_inst_lanes_0_ready_T; // @[SCore.scala 105:61]
- assign decode_1_io_inst_addr = fetch_io_inst_lanes_1_addr; // @[SCore.scala 107:28]
- assign decode_1_io_inst_inst = fetch_io_inst_lanes_1_inst; // @[SCore.scala 108:28]
- assign decode_1_io_inst_brchFwd = fetch_io_inst_lanes_1_brchFwd; // @[SCore.scala 109:31]
- assign decode_1_io_scoreboard_regd = regfile_io_scoreboard_regd | decode_0_io_scoreboard_spec; // @[SCore.scala 138:62]
- assign decode_1_io_scoreboard_comb = regfile_io_scoreboard_comb | decode_0_io_scoreboard_spec; // @[SCore.scala 137:62]
- assign decode_1_io_lsu_ready = lsu_io_req_1_ready; // @[SCore.scala 197:28]
- assign decode_1_io_vinst_ready = io_vcore_vinst_1_ready; // @[SCore.scala 283:23]
- assign decode_1_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 62:43]
- assign decode_1_io_interlock = decode_0_io_interlock; // @[SCore.scala 117:26]
- assign decode_1_io_serializeIn_mul = decode_0_io_serializeOut_mul; // @[SCore.scala 123:28]
- assign decode_1_io_serializeIn_jump = decode_0_io_serializeOut_jump; // @[SCore.scala 123:28]
- assign decode_1_io_serializeIn_brcond = decode_0_io_serializeOut_brcond; // @[SCore.scala 123:28]
- assign decode_2_clock = clock;
- assign decode_2_reset = reset;
- assign decode_2_io_halted = csr_io_halted; // @[SCore.scala 112:25]
- assign decode_2_io_inst_valid = fetch_io_inst_lanes_2_valid & mask_2; // @[SCore.scala 105:61]
- assign decode_2_io_inst_addr = fetch_io_inst_lanes_2_addr; // @[SCore.scala 107:28]
- assign decode_2_io_inst_inst = fetch_io_inst_lanes_2_inst; // @[SCore.scala 108:28]
- assign decode_2_io_inst_brchFwd = fetch_io_inst_lanes_2_brchFwd; // @[SCore.scala 109:31]
- assign decode_2_io_scoreboard_regd = regfile_io_scoreboard_regd | scoreboard_spec2; // @[SCore.scala 140:62]
- assign decode_2_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec2; // @[SCore.scala 139:62]
- assign decode_2_io_lsu_ready = lsu_io_req_2_ready; // @[SCore.scala 197:28]
- assign decode_2_io_vinst_ready = io_vcore_vinst_2_ready; // @[SCore.scala 283:23]
- assign decode_2_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 62:43]
- assign decode_2_io_interlock = decode_1_io_interlock; // @[SCore.scala 118:26]
- assign decode_2_io_serializeIn_mul = decode_1_io_serializeOut_mul; // @[SCore.scala 124:28]
- assign decode_2_io_serializeIn_jump = decode_1_io_serializeOut_jump; // @[SCore.scala 124:28]
- assign decode_2_io_serializeIn_brcond = decode_1_io_serializeOut_brcond; // @[SCore.scala 124:28]
- assign decode_3_clock = clock;
- assign decode_3_reset = reset;
- assign decode_3_io_halted = csr_io_halted; // @[SCore.scala 112:25]
- assign decode_3_io_inst_valid = fetch_io_inst_lanes_3_valid & mask_3; // @[SCore.scala 105:61]
- assign decode_3_io_inst_addr = fetch_io_inst_lanes_3_addr; // @[SCore.scala 107:28]
- assign decode_3_io_inst_inst = fetch_io_inst_lanes_3_inst; // @[SCore.scala 108:28]
- assign decode_3_io_inst_brchFwd = fetch_io_inst_lanes_3_brchFwd; // @[SCore.scala 109:31]
- assign decode_3_io_scoreboard_regd = regfile_io_scoreboard_regd | scoreboard_spec3; // @[SCore.scala 142:62]
- assign decode_3_io_scoreboard_comb = regfile_io_scoreboard_comb | scoreboard_spec3; // @[SCore.scala 141:62]
- assign decode_3_io_lsu_ready = lsu_io_req_3_ready; // @[SCore.scala 197:28]
- assign decode_3_io_vinst_ready = io_vcore_vinst_3_ready; // @[SCore.scala 283:23]
- assign decode_3_io_branchTaken = _branchTaken_T_1 | bru_3_io_taken_valid; // @[SCore.scala 62:43]
- assign decode_3_io_interlock = decode_2_io_interlock; // @[SCore.scala 119:26]
- assign decode_3_io_serializeIn_mul = decode_2_io_serializeOut_mul; // @[SCore.scala 125:28]
- assign decode_3_io_serializeIn_jump = decode_2_io_serializeOut_jump; // @[SCore.scala 125:28]
- assign decode_3_io_serializeIn_brcond = decode_2_io_serializeOut_brcond; // @[SCore.scala 125:28]
- assign alu_0_clock = clock;
- assign alu_0_reset = reset;
- assign alu_0_io_req_valid = decode_0_io_alu_valid; // @[SCore.scala 153:19]
- assign alu_0_io_req_addr = decode_0_io_alu_addr; // @[SCore.scala 153:19]
- assign alu_0_io_req_op = decode_0_io_alu_op; // @[SCore.scala 153:19]
- assign alu_0_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 154:19]
- assign alu_0_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 154:19]
- assign alu_0_io_rs2_valid = regfile_io_readData_1_valid; // @[SCore.scala 155:19]
- assign alu_0_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 155:19]
- assign alu_1_clock = clock;
- assign alu_1_reset = reset;
- assign alu_1_io_req_valid = decode_1_io_alu_valid; // @[SCore.scala 153:19]
- assign alu_1_io_req_addr = decode_1_io_alu_addr; // @[SCore.scala 153:19]
- assign alu_1_io_req_op = decode_1_io_alu_op; // @[SCore.scala 153:19]
- assign alu_1_io_rs1_valid = regfile_io_readData_2_valid; // @[SCore.scala 154:19]
- assign alu_1_io_rs1_data = regfile_io_readData_2_data; // @[SCore.scala 154:19]
- assign alu_1_io_rs2_valid = regfile_io_readData_3_valid; // @[SCore.scala 155:19]
- assign alu_1_io_rs2_data = regfile_io_readData_3_data; // @[SCore.scala 155:19]
- assign alu_2_clock = clock;
- assign alu_2_reset = reset;
- assign alu_2_io_req_valid = decode_2_io_alu_valid; // @[SCore.scala 153:19]
- assign alu_2_io_req_addr = decode_2_io_alu_addr; // @[SCore.scala 153:19]
- assign alu_2_io_req_op = decode_2_io_alu_op; // @[SCore.scala 153:19]
- assign alu_2_io_rs1_valid = regfile_io_readData_4_valid; // @[SCore.scala 154:19]
- assign alu_2_io_rs1_data = regfile_io_readData_4_data; // @[SCore.scala 154:19]
- assign alu_2_io_rs2_valid = regfile_io_readData_5_valid; // @[SCore.scala 155:19]
- assign alu_2_io_rs2_data = regfile_io_readData_5_data; // @[SCore.scala 155:19]
- assign alu_3_clock = clock;
- assign alu_3_reset = reset;
- assign alu_3_io_req_valid = decode_3_io_alu_valid; // @[SCore.scala 153:19]
- assign alu_3_io_req_addr = decode_3_io_alu_addr; // @[SCore.scala 153:19]
- assign alu_3_io_req_op = decode_3_io_alu_op; // @[SCore.scala 153:19]
- assign alu_3_io_rs1_valid = regfile_io_readData_6_valid; // @[SCore.scala 154:19]
- assign alu_3_io_rs1_data = regfile_io_readData_6_data; // @[SCore.scala 154:19]
- assign alu_3_io_rs2_valid = regfile_io_readData_7_valid; // @[SCore.scala 155:19]
- assign alu_3_io_rs2_data = regfile_io_readData_7_data; // @[SCore.scala 155:19]
- assign bru_0_clock = clock;
- assign bru_0_reset = reset;
- assign bru_0_io_req_valid = decode_0_io_bru_valid; // @[SCore.scala 161:19]
- assign bru_0_io_req_fwd = decode_0_io_bru_fwd; // @[SCore.scala 161:19]
- assign bru_0_io_req_op = decode_0_io_bru_op; // @[SCore.scala 161:19]
- assign bru_0_io_req_pc = decode_0_io_bru_pc; // @[SCore.scala 161:19]
- assign bru_0_io_req_target = decode_0_io_bru_target; // @[SCore.scala 161:19]
- assign bru_0_io_req_link = decode_0_io_bru_link; // @[SCore.scala 161:19]
- assign bru_0_io_csr_out_mode = csr_io_bru_out_mode; // @[SCore.scala 167:17]
- assign bru_0_io_csr_out_mepc = csr_io_bru_out_mepc; // @[SCore.scala 167:17]
- assign bru_0_io_csr_out_mtvec = csr_io_bru_out_mtvec; // @[SCore.scala 167:17]
- assign bru_0_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 162:19]
- assign bru_0_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 162:19]
- assign bru_0_io_rs2_valid = regfile_io_readData_1_valid; // @[SCore.scala 163:19]
- assign bru_0_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 163:19]
- assign bru_0_io_target_data = regfile_io_target_0_data; // @[SCore.scala 164:22]
- assign bru_1_clock = clock;
- assign bru_1_reset = reset;
- assign bru_1_io_req_valid = decode_1_io_bru_valid; // @[SCore.scala 161:19]
- assign bru_1_io_req_fwd = decode_1_io_bru_fwd; // @[SCore.scala 161:19]
- assign bru_1_io_req_op = decode_1_io_bru_op; // @[SCore.scala 161:19]
- assign bru_1_io_req_pc = decode_1_io_bru_pc; // @[SCore.scala 161:19]
- assign bru_1_io_req_target = decode_1_io_bru_target; // @[SCore.scala 161:19]
- assign bru_1_io_req_link = decode_1_io_bru_link; // @[SCore.scala 161:19]
- assign bru_1_io_csr_out_mode = 1'h0; // @[Csr.scala 62:14]
- assign bru_1_io_csr_out_mepc = 32'h0; // @[Csr.scala 63:14]
- assign bru_1_io_csr_out_mtvec = 32'h0; // @[Csr.scala 64:15]
- assign bru_1_io_rs1_valid = regfile_io_readData_2_valid; // @[SCore.scala 162:19]
- assign bru_1_io_rs1_data = regfile_io_readData_2_data; // @[SCore.scala 162:19]
- assign bru_1_io_rs2_valid = regfile_io_readData_3_valid; // @[SCore.scala 163:19]
- assign bru_1_io_rs2_data = regfile_io_readData_3_data; // @[SCore.scala 163:19]
- assign bru_1_io_target_data = regfile_io_target_1_data; // @[SCore.scala 164:22]
- assign bru_2_clock = clock;
- assign bru_2_reset = reset;
- assign bru_2_io_req_valid = decode_2_io_bru_valid; // @[SCore.scala 161:19]
- assign bru_2_io_req_fwd = decode_2_io_bru_fwd; // @[SCore.scala 161:19]
- assign bru_2_io_req_op = decode_2_io_bru_op; // @[SCore.scala 161:19]
- assign bru_2_io_req_pc = decode_2_io_bru_pc; // @[SCore.scala 161:19]
- assign bru_2_io_req_target = decode_2_io_bru_target; // @[SCore.scala 161:19]
- assign bru_2_io_req_link = decode_2_io_bru_link; // @[SCore.scala 161:19]
- assign bru_2_io_csr_out_mode = 1'h0; // @[Csr.scala 62:14]
- assign bru_2_io_csr_out_mepc = 32'h0; // @[Csr.scala 63:14]
- assign bru_2_io_csr_out_mtvec = 32'h0; // @[Csr.scala 64:15]
- assign bru_2_io_rs1_valid = regfile_io_readData_4_valid; // @[SCore.scala 162:19]
- assign bru_2_io_rs1_data = regfile_io_readData_4_data; // @[SCore.scala 162:19]
- assign bru_2_io_rs2_valid = regfile_io_readData_5_valid; // @[SCore.scala 163:19]
- assign bru_2_io_rs2_data = regfile_io_readData_5_data; // @[SCore.scala 163:19]
- assign bru_2_io_target_data = regfile_io_target_2_data; // @[SCore.scala 164:22]
- assign bru_3_clock = clock;
- assign bru_3_reset = reset;
- assign bru_3_io_req_valid = decode_3_io_bru_valid; // @[SCore.scala 161:19]
- assign bru_3_io_req_fwd = decode_3_io_bru_fwd; // @[SCore.scala 161:19]
- assign bru_3_io_req_op = decode_3_io_bru_op; // @[SCore.scala 161:19]
- assign bru_3_io_req_pc = decode_3_io_bru_pc; // @[SCore.scala 161:19]
- assign bru_3_io_req_target = decode_3_io_bru_target; // @[SCore.scala 161:19]
- assign bru_3_io_req_link = decode_3_io_bru_link; // @[SCore.scala 161:19]
- assign bru_3_io_csr_out_mode = 1'h0; // @[Csr.scala 62:14]
- assign bru_3_io_csr_out_mepc = 32'h0; // @[Csr.scala 63:14]
- assign bru_3_io_csr_out_mtvec = 32'h0; // @[Csr.scala 64:15]
- assign bru_3_io_rs1_valid = regfile_io_readData_6_valid; // @[SCore.scala 162:19]
- assign bru_3_io_rs1_data = regfile_io_readData_6_data; // @[SCore.scala 162:19]
- assign bru_3_io_rs2_valid = regfile_io_readData_7_valid; // @[SCore.scala 163:19]
- assign bru_3_io_rs2_data = regfile_io_readData_7_data; // @[SCore.scala 163:19]
- assign bru_3_io_target_data = regfile_io_target_3_data; // @[SCore.scala 164:22]
- assign csr_clock = clock;
- assign csr_reset = reset;
- assign csr_io_csr_in_value_0 = io_csr_in_value_0; // @[SCore.scala 176:14]
- assign csr_io_req_valid = decode_0_io_csr_valid; // @[SCore.scala 178:14]
- assign csr_io_req_addr = decode_0_io_csr_addr; // @[SCore.scala 178:14]
- assign csr_io_req_index = decode_0_io_csr_index; // @[SCore.scala 178:14]
- assign csr_io_req_op = decode_0_io_csr_op; // @[SCore.scala 178:14]
- assign csr_io_rs1_valid = regfile_io_readData_0_valid; // @[SCore.scala 179:14]
- assign csr_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 179:14]
- assign csr_io_bru_in_mode_valid = bru_0_io_csr_in_mode_valid; // @[SCore.scala 167:17]
- assign csr_io_bru_in_mode_bits = bru_0_io_csr_in_mode_bits; // @[SCore.scala 167:17]
- assign csr_io_bru_in_mcause_valid = bru_0_io_csr_in_mcause_valid; // @[SCore.scala 167:17]
- assign csr_io_bru_in_mcause_bits = bru_0_io_csr_in_mcause_bits; // @[SCore.scala 167:17]
- assign csr_io_bru_in_mepc_valid = bru_0_io_csr_in_mepc_valid; // @[SCore.scala 167:17]
- assign csr_io_bru_in_mepc_bits = bru_0_io_csr_in_mepc_bits; // @[SCore.scala 167:17]
- assign csr_io_bru_in_mtval_valid = bru_0_io_csr_in_mtval_valid; // @[SCore.scala 167:17]
- assign csr_io_bru_in_mtval_bits = bru_0_io_csr_in_mtval_bits; // @[SCore.scala 167:17]
- assign csr_io_bru_in_halt = bru_0_io_csr_in_halt; // @[SCore.scala 167:17]
- assign csr_io_bru_in_fault = bru_0_io_csr_in_fault; // @[SCore.scala 167:17]
- assign csr_io_vcore_undef = io_vcore_undef; // @[SCore.scala 181:22]
- assign lsu_clock = clock;
- assign lsu_reset = reset;
- assign lsu_io_req_0_valid = decode_0_io_lsu_valid; // @[SCore.scala 193:25]
- assign lsu_io_req_0_addr = decode_0_io_lsu_addr; // @[SCore.scala 195:25]
- assign lsu_io_req_0_op = decode_0_io_lsu_op; // @[SCore.scala 196:25]
- assign lsu_io_req_1_valid = decode_1_io_lsu_valid; // @[SCore.scala 193:25]
- assign lsu_io_req_1_addr = decode_1_io_lsu_addr; // @[SCore.scala 195:25]
- assign lsu_io_req_1_op = decode_1_io_lsu_op; // @[SCore.scala 196:25]
- assign lsu_io_req_2_valid = decode_2_io_lsu_valid; // @[SCore.scala 193:25]
- assign lsu_io_req_2_addr = decode_2_io_lsu_addr; // @[SCore.scala 195:25]
- assign lsu_io_req_2_op = decode_2_io_lsu_op; // @[SCore.scala 196:25]
- assign lsu_io_req_3_valid = decode_3_io_lsu_valid; // @[SCore.scala 193:25]
- assign lsu_io_req_3_addr = decode_3_io_lsu_addr; // @[SCore.scala 195:25]
- assign lsu_io_req_3_op = decode_3_io_lsu_op; // @[SCore.scala 196:25]
- assign lsu_io_busPort_addr_0 = regfile_io_busPort_addr_0; // @[SCore.scala 190:18]
- assign lsu_io_busPort_addr_1 = regfile_io_busPort_addr_1; // @[SCore.scala 190:18]
- assign lsu_io_busPort_addr_2 = regfile_io_busPort_addr_2; // @[SCore.scala 190:18]
- assign lsu_io_busPort_addr_3 = regfile_io_busPort_addr_3; // @[SCore.scala 190:18]
- assign lsu_io_busPort_data_0 = regfile_io_busPort_data_0; // @[SCore.scala 190:18]
- assign lsu_io_busPort_data_1 = regfile_io_busPort_data_1; // @[SCore.scala 190:18]
- assign lsu_io_busPort_data_2 = regfile_io_busPort_data_2; // @[SCore.scala 190:18]
- assign lsu_io_busPort_data_3 = regfile_io_busPort_data_3; // @[SCore.scala 190:18]
- assign lsu_io_dbus_ready = io_dbus_ready; // @[SCore.scala 296:11]
- assign lsu_io_dbus_rdata = io_dbus_rdata; // @[SCore.scala 296:11]
- assign lsu_io_flush_ready = io_dflush_ready; // @[SCore.scala 78:22]
- assign lsu_io_ubus_ready = io_ubus_ready; // @[SCore.scala 297:11]
- assign lsu_io_ubus_rdata = io_ubus_rdata; // @[SCore.scala 297:11]
- assign mlu_clock = clock;
- assign mlu_reset = reset;
- assign mlu_io_req_0_valid = decode_0_io_mlu_valid; // @[SCore.scala 202:17]
- assign mlu_io_req_0_addr = decode_0_io_mlu_addr; // @[SCore.scala 202:17]
- assign mlu_io_req_0_op = decode_0_io_mlu_op; // @[SCore.scala 202:17]
- assign mlu_io_req_1_valid = decode_1_io_mlu_valid; // @[SCore.scala 203:17]
- assign mlu_io_req_1_addr = decode_1_io_mlu_addr; // @[SCore.scala 203:17]
- assign mlu_io_req_1_op = decode_1_io_mlu_op; // @[SCore.scala 203:17]
- assign mlu_io_req_2_valid = decode_2_io_mlu_valid; // @[SCore.scala 204:17]
- assign mlu_io_req_2_addr = decode_2_io_mlu_addr; // @[SCore.scala 204:17]
- assign mlu_io_req_2_op = decode_2_io_mlu_op; // @[SCore.scala 204:17]
- assign mlu_io_req_3_valid = decode_3_io_mlu_valid; // @[SCore.scala 205:17]
- assign mlu_io_req_3_addr = decode_3_io_mlu_addr; // @[SCore.scala 205:17]
- assign mlu_io_req_3_op = decode_3_io_mlu_op; // @[SCore.scala 205:17]
- assign mlu_io_rs1_0_valid = regfile_io_readData_0_valid; // @[SCore.scala 206:17]
- assign mlu_io_rs1_0_data = regfile_io_readData_0_data; // @[SCore.scala 206:17]
- assign mlu_io_rs1_1_valid = regfile_io_readData_2_valid; // @[SCore.scala 207:17]
- assign mlu_io_rs1_1_data = regfile_io_readData_2_data; // @[SCore.scala 207:17]
- assign mlu_io_rs1_2_valid = regfile_io_readData_4_valid; // @[SCore.scala 208:17]
- assign mlu_io_rs1_2_data = regfile_io_readData_4_data; // @[SCore.scala 208:17]
- assign mlu_io_rs1_3_valid = regfile_io_readData_6_valid; // @[SCore.scala 209:17]
- assign mlu_io_rs1_3_data = regfile_io_readData_6_data; // @[SCore.scala 209:17]
- assign mlu_io_rs2_0_valid = regfile_io_readData_1_valid; // @[SCore.scala 210:17]
- assign mlu_io_rs2_0_data = regfile_io_readData_1_data; // @[SCore.scala 210:17]
- assign mlu_io_rs2_1_valid = regfile_io_readData_3_valid; // @[SCore.scala 211:17]
- assign mlu_io_rs2_1_data = regfile_io_readData_3_data; // @[SCore.scala 211:17]
- assign mlu_io_rs2_2_valid = regfile_io_readData_5_valid; // @[SCore.scala 212:17]
- assign mlu_io_rs2_2_data = regfile_io_readData_5_data; // @[SCore.scala 212:17]
- assign mlu_io_rs2_3_valid = regfile_io_readData_7_valid; // @[SCore.scala 213:17]
- assign mlu_io_rs2_3_data = regfile_io_readData_7_data; // @[SCore.scala 213:17]
- assign dvu_clock = clock;
- assign dvu_reset = reset;
- assign dvu_io_req_valid = decode_0_io_dvu_valid; // @[SCore.scala 217:14]
- assign dvu_io_req_addr = decode_0_io_dvu_addr; // @[SCore.scala 217:14]
- assign dvu_io_req_op = decode_0_io_dvu_op; // @[SCore.scala 217:14]
- assign dvu_io_rs1_data = regfile_io_readData_0_data; // @[SCore.scala 218:14]
- assign dvu_io_rs2_data = regfile_io_readData_1_data; // @[SCore.scala 219:14]
- assign dvu_io_rd_ready = ~mlu_io_rd_valid; // @[SCore.scala 220:22]
- always @(posedge clock) begin
- slogAddr <= _GEN_2[1:0];
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~bru_1_io_iflush)) begin
- $fatal; // @[SCore.scala 80:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~bru_1_io_iflush)) begin
- $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:80 assert(!bru(1).io.iflush)\n"); // @[SCore.scala 80:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_5 & ~(~bru_2_io_iflush)) begin
- $fatal; // @[SCore.scala 81:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_5 & ~(~bru_2_io_iflush)) begin
- $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:81 assert(!bru(2).io.iflush)\n"); // @[SCore.scala 81:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_5 & ~(~bru_3_io_iflush)) begin
- $fatal; // @[SCore.scala 82:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_5 & ~(~bru_3_io_iflush)) begin
- $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:82 assert(!bru(3).io.iflush)\n"); // @[SCore.scala 82:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_5 & ~_T_18) begin
- $fatal; // @[SCore.scala 258:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_5 & ~_T_18) begin
- $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:258 assert((csr0Valid +&\n"); // @[SCore.scala 258:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_5 & ~_T_25) begin
- $fatal; // @[SCore.scala 258:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_5 & ~_T_25) begin
- $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:258 assert((csr0Valid +&\n"); // @[SCore.scala 258:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_5 & ~_T_32) begin
- $fatal; // @[SCore.scala 258:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_5 & ~_T_32) begin
- $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:258 assert((csr0Valid +&\n"); // @[SCore.scala 258:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_5 & ~_T_39) begin
- $fatal; // @[SCore.scala 258:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_5 & ~_T_39) begin
- $fwrite(32'h80000002,"Assertion failed\n at SCore.scala:258 assert((csr0Valid +&\n"); // @[SCore.scala 258:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_5 & ~(~(mlu_io_rd_valid & (dvu_io_rd_valid & dvu_io_rd_ready)))) begin
- $fatal; // @[SCore.scala 266:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_5 & ~(~(mlu_io_rd_valid & (dvu_io_rd_valid & dvu_io_rd_ready)))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at SCore.scala:266 assert(!(mlu.io.rd.valid && (dvu.io.rd.valid && dvu.io.rd.ready))) // TODO: stall dvu on mlu write\n"
- ); // @[SCore.scala 266:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[SCore.scala 68:27]
- iflush <= 1'h0; // @[SCore.scala 69:12]
- end else begin
- iflush <= bru_0_io_iflush | _GEN_0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[SCore.scala 303:26]
- slogValid <= 1'h0; // @[SCore.scala 303:26]
- end else begin
- slogValid <= decode_0_io_slog; // @[SCore.scala 307:13]
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- iflush = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- slogValid = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- slogAddr = _RAND_2[1:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- iflush = 1'h0;
- end
- if (reset) begin
- slogValid = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Slice_3(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_lane_valid,
- input [31:0] io_in_bits_0_lane_bits_inst,
- input [31:0] io_in_bits_0_lane_bits_addr,
- input [31:0] io_in_bits_0_lane_bits_data,
- input io_in_bits_1_lane_valid,
- input [31:0] io_in_bits_1_lane_bits_inst,
- input [31:0] io_in_bits_1_lane_bits_addr,
- input [31:0] io_in_bits_1_lane_bits_data,
- input io_in_bits_2_lane_valid,
- input [31:0] io_in_bits_2_lane_bits_inst,
- input [31:0] io_in_bits_2_lane_bits_addr,
- input [31:0] io_in_bits_2_lane_bits_data,
- input io_in_bits_3_lane_valid,
- input [31:0] io_in_bits_3_lane_bits_inst,
- input [31:0] io_in_bits_3_lane_bits_addr,
- input [31:0] io_in_bits_3_lane_bits_data,
- input io_out_ready,
- output io_out_valid,
- output io_out_bits_0_lane_valid,
- output [31:0] io_out_bits_0_lane_bits_inst,
- output [31:0] io_out_bits_0_lane_bits_addr,
- output [31:0] io_out_bits_0_lane_bits_data,
- output io_out_bits_1_lane_valid,
- output [31:0] io_out_bits_1_lane_bits_inst,
- output [31:0] io_out_bits_1_lane_bits_addr,
- output [31:0] io_out_bits_1_lane_bits_data,
- output io_out_bits_2_lane_valid,
- output [31:0] io_out_bits_2_lane_bits_inst,
- output [31:0] io_out_bits_2_lane_bits_addr,
- output [31:0] io_out_bits_2_lane_bits_data,
- output io_out_bits_3_lane_valid,
- output [31:0] io_out_bits_3_lane_bits_inst,
- output [31:0] io_out_bits_3_lane_bits_addr,
- output [31:0] io_out_bits_3_lane_bits_data
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
-`endif // RANDOMIZE_REG_INIT
- reg [1:0] ipos; // @[Slice.scala 38:21]
- reg [1:0] opos; // @[Slice.scala 39:21]
- reg mem_0_0_lane_valid; // @[Slice.scala 41:16]
- reg [31:0] mem_0_0_lane_bits_inst; // @[Slice.scala 41:16]
- reg [31:0] mem_0_0_lane_bits_addr; // @[Slice.scala 41:16]
- reg [31:0] mem_0_0_lane_bits_data; // @[Slice.scala 41:16]
- reg mem_0_1_lane_valid; // @[Slice.scala 41:16]
- reg [31:0] mem_0_1_lane_bits_inst; // @[Slice.scala 41:16]
- reg [31:0] mem_0_1_lane_bits_addr; // @[Slice.scala 41:16]
- reg [31:0] mem_0_1_lane_bits_data; // @[Slice.scala 41:16]
- reg mem_0_2_lane_valid; // @[Slice.scala 41:16]
- reg [31:0] mem_0_2_lane_bits_inst; // @[Slice.scala 41:16]
- reg [31:0] mem_0_2_lane_bits_addr; // @[Slice.scala 41:16]
- reg [31:0] mem_0_2_lane_bits_data; // @[Slice.scala 41:16]
- reg mem_0_3_lane_valid; // @[Slice.scala 41:16]
- reg [31:0] mem_0_3_lane_bits_inst; // @[Slice.scala 41:16]
- reg [31:0] mem_0_3_lane_bits_addr; // @[Slice.scala 41:16]
- reg [31:0] mem_0_3_lane_bits_data; // @[Slice.scala 41:16]
- reg mem_1_0_lane_valid; // @[Slice.scala 41:16]
- reg [31:0] mem_1_0_lane_bits_inst; // @[Slice.scala 41:16]
- reg [31:0] mem_1_0_lane_bits_addr; // @[Slice.scala 41:16]
- reg [31:0] mem_1_0_lane_bits_data; // @[Slice.scala 41:16]
- reg mem_1_1_lane_valid; // @[Slice.scala 41:16]
- reg [31:0] mem_1_1_lane_bits_inst; // @[Slice.scala 41:16]
- reg [31:0] mem_1_1_lane_bits_addr; // @[Slice.scala 41:16]
- reg [31:0] mem_1_1_lane_bits_data; // @[Slice.scala 41:16]
- reg mem_1_2_lane_valid; // @[Slice.scala 41:16]
- reg [31:0] mem_1_2_lane_bits_inst; // @[Slice.scala 41:16]
- reg [31:0] mem_1_2_lane_bits_addr; // @[Slice.scala 41:16]
- reg [31:0] mem_1_2_lane_bits_data; // @[Slice.scala 41:16]
- reg mem_1_3_lane_valid; // @[Slice.scala 41:16]
- reg [31:0] mem_1_3_lane_bits_inst; // @[Slice.scala 41:16]
- reg [31:0] mem_1_3_lane_bits_addr; // @[Slice.scala 41:16]
- reg [31:0] mem_1_3_lane_bits_data; // @[Slice.scala 41:16]
- wire empty = ipos == opos; // @[Slice.scala 43:20]
- wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 45:28]
- wire ovalid = io_out_valid & io_out_ready; // @[Slice.scala 46:29]
- wire [1:0] _ipos_T_1 = ipos + 2'h1; // @[Slice.scala 49:18]
- wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 53:18]
- wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 61:36]
- wire _io_in_ready_T = ~full; // @[Slice.scala 65:22]
- wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 72:18]
- wire _T_5 = ivalid & ovalid; // @[Slice.scala 73:18]
- wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 73:28]
- wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 72:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 78:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 77:39]
- assign io_in_ready = ~full; // @[Slice.scala 65:22]
- assign io_out_valid = ~empty; // @[Slice.scala 102:21]
- assign io_out_bits_0_lane_valid = mem_0_0_lane_valid; // @[Slice.scala 103:18]
- assign io_out_bits_0_lane_bits_inst = mem_0_0_lane_bits_inst; // @[Slice.scala 103:18]
- assign io_out_bits_0_lane_bits_addr = mem_0_0_lane_bits_addr; // @[Slice.scala 103:18]
- assign io_out_bits_0_lane_bits_data = mem_0_0_lane_bits_data; // @[Slice.scala 103:18]
- assign io_out_bits_1_lane_valid = mem_0_1_lane_valid; // @[Slice.scala 103:18]
- assign io_out_bits_1_lane_bits_inst = mem_0_1_lane_bits_inst; // @[Slice.scala 103:18]
- assign io_out_bits_1_lane_bits_addr = mem_0_1_lane_bits_addr; // @[Slice.scala 103:18]
- assign io_out_bits_1_lane_bits_data = mem_0_1_lane_bits_data; // @[Slice.scala 103:18]
- assign io_out_bits_2_lane_valid = mem_0_2_lane_valid; // @[Slice.scala 103:18]
- assign io_out_bits_2_lane_bits_inst = mem_0_2_lane_bits_inst; // @[Slice.scala 103:18]
- assign io_out_bits_2_lane_bits_addr = mem_0_2_lane_bits_addr; // @[Slice.scala 103:18]
- assign io_out_bits_2_lane_bits_data = mem_0_2_lane_bits_data; // @[Slice.scala 103:18]
- assign io_out_bits_3_lane_valid = mem_0_3_lane_valid; // @[Slice.scala 103:18]
- assign io_out_bits_3_lane_bits_inst = mem_0_3_lane_bits_inst; // @[Slice.scala 103:18]
- assign io_out_bits_3_lane_bits_addr = mem_0_3_lane_bits_addr; // @[Slice.scala 103:18]
- assign io_out_bits_3_lane_bits_data = mem_0_3_lane_bits_data; // @[Slice.scala 103:18]
- always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_0_lane_valid <= io_in_bits_0_lane_valid; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_0_lane_valid <= mem_1_0_lane_valid; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_0_lane_bits_inst <= io_in_bits_0_lane_bits_inst; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_0_lane_bits_inst <= mem_1_0_lane_bits_inst; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_0_lane_bits_addr <= io_in_bits_0_lane_bits_addr; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_0_lane_bits_addr <= mem_1_0_lane_bits_addr; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_0_lane_bits_data <= io_in_bits_0_lane_bits_data; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_0_lane_bits_data <= mem_1_0_lane_bits_data; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_1_lane_valid <= io_in_bits_1_lane_valid; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_1_lane_valid <= mem_1_1_lane_valid; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_1_lane_bits_inst <= io_in_bits_1_lane_bits_inst; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_1_lane_bits_inst <= mem_1_1_lane_bits_inst; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_1_lane_bits_addr <= io_in_bits_1_lane_bits_addr; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_1_lane_bits_addr <= mem_1_1_lane_bits_addr; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_1_lane_bits_data <= io_in_bits_1_lane_bits_data; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_1_lane_bits_data <= mem_1_1_lane_bits_data; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_2_lane_valid <= io_in_bits_2_lane_valid; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_2_lane_valid <= mem_1_2_lane_valid; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_2_lane_bits_inst <= io_in_bits_2_lane_bits_inst; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_2_lane_bits_inst <= mem_1_2_lane_bits_inst; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_2_lane_bits_addr <= io_in_bits_2_lane_bits_addr; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_2_lane_bits_addr <= mem_1_2_lane_bits_addr; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_2_lane_bits_data <= io_in_bits_2_lane_bits_data; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_2_lane_bits_data <= mem_1_2_lane_bits_data; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_3_lane_valid <= io_in_bits_3_lane_valid; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_3_lane_valid <= mem_1_3_lane_valid; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_3_lane_bits_inst <= io_in_bits_3_lane_bits_inst; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_3_lane_bits_inst <= mem_1_3_lane_bits_inst; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_3_lane_bits_addr <= io_in_bits_3_lane_bits_addr; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_3_lane_bits_addr <= mem_1_3_lane_bits_addr; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_3_lane_bits_data <= io_in_bits_3_lane_bits_data; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_3_lane_bits_data <= mem_1_3_lane_bits_data; // @[Slice.scala 69:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_0_lane_valid <= io_in_bits_0_lane_valid; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_0_lane_bits_inst <= io_in_bits_0_lane_bits_inst; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_0_lane_bits_addr <= io_in_bits_0_lane_bits_addr; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_0_lane_bits_data <= io_in_bits_0_lane_bits_data; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_1_lane_valid <= io_in_bits_1_lane_valid; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_1_lane_bits_inst <= io_in_bits_1_lane_bits_inst; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_1_lane_bits_addr <= io_in_bits_1_lane_bits_addr; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_1_lane_bits_data <= io_in_bits_1_lane_bits_data; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_2_lane_valid <= io_in_bits_2_lane_valid; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_2_lane_bits_inst <= io_in_bits_2_lane_bits_inst; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_2_lane_bits_addr <= io_in_bits_2_lane_bits_addr; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_2_lane_bits_data <= io_in_bits_2_lane_bits_data; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_3_lane_valid <= io_in_bits_3_lane_valid; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_3_lane_bits_inst <= io_in_bits_3_lane_bits_inst; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_3_lane_bits_addr <= io_in_bits_3_lane_bits_addr; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_3_lane_bits_data <= io_in_bits_3_lane_bits_data; // @[Slice.scala 79:14]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 48:17]
- ipos <= 2'h0; // @[Slice.scala 49:10]
- end else if (ivalid) begin // @[Slice.scala 38:21]
- ipos <= _ipos_T_1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 52:17]
- opos <= 2'h0; // @[Slice.scala 53:10]
- end else if (ovalid) begin // @[Slice.scala 39:21]
- opos <= _opos_T_1;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- ipos = _RAND_0[1:0];
- _RAND_1 = {1{`RANDOM}};
- opos = _RAND_1[1:0];
- _RAND_2 = {1{`RANDOM}};
- mem_0_0_lane_valid = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- mem_0_0_lane_bits_inst = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- mem_0_0_lane_bits_addr = _RAND_4[31:0];
- _RAND_5 = {1{`RANDOM}};
- mem_0_0_lane_bits_data = _RAND_5[31:0];
- _RAND_6 = {1{`RANDOM}};
- mem_0_1_lane_valid = _RAND_6[0:0];
- _RAND_7 = {1{`RANDOM}};
- mem_0_1_lane_bits_inst = _RAND_7[31:0];
- _RAND_8 = {1{`RANDOM}};
- mem_0_1_lane_bits_addr = _RAND_8[31:0];
- _RAND_9 = {1{`RANDOM}};
- mem_0_1_lane_bits_data = _RAND_9[31:0];
- _RAND_10 = {1{`RANDOM}};
- mem_0_2_lane_valid = _RAND_10[0:0];
- _RAND_11 = {1{`RANDOM}};
- mem_0_2_lane_bits_inst = _RAND_11[31:0];
- _RAND_12 = {1{`RANDOM}};
- mem_0_2_lane_bits_addr = _RAND_12[31:0];
- _RAND_13 = {1{`RANDOM}};
- mem_0_2_lane_bits_data = _RAND_13[31:0];
- _RAND_14 = {1{`RANDOM}};
- mem_0_3_lane_valid = _RAND_14[0:0];
- _RAND_15 = {1{`RANDOM}};
- mem_0_3_lane_bits_inst = _RAND_15[31:0];
- _RAND_16 = {1{`RANDOM}};
- mem_0_3_lane_bits_addr = _RAND_16[31:0];
- _RAND_17 = {1{`RANDOM}};
- mem_0_3_lane_bits_data = _RAND_17[31:0];
- _RAND_18 = {1{`RANDOM}};
- mem_1_0_lane_valid = _RAND_18[0:0];
- _RAND_19 = {1{`RANDOM}};
- mem_1_0_lane_bits_inst = _RAND_19[31:0];
- _RAND_20 = {1{`RANDOM}};
- mem_1_0_lane_bits_addr = _RAND_20[31:0];
- _RAND_21 = {1{`RANDOM}};
- mem_1_0_lane_bits_data = _RAND_21[31:0];
- _RAND_22 = {1{`RANDOM}};
- mem_1_1_lane_valid = _RAND_22[0:0];
- _RAND_23 = {1{`RANDOM}};
- mem_1_1_lane_bits_inst = _RAND_23[31:0];
- _RAND_24 = {1{`RANDOM}};
- mem_1_1_lane_bits_addr = _RAND_24[31:0];
- _RAND_25 = {1{`RANDOM}};
- mem_1_1_lane_bits_data = _RAND_25[31:0];
- _RAND_26 = {1{`RANDOM}};
- mem_1_2_lane_valid = _RAND_26[0:0];
- _RAND_27 = {1{`RANDOM}};
- mem_1_2_lane_bits_inst = _RAND_27[31:0];
- _RAND_28 = {1{`RANDOM}};
- mem_1_2_lane_bits_addr = _RAND_28[31:0];
- _RAND_29 = {1{`RANDOM}};
- mem_1_2_lane_bits_data = _RAND_29[31:0];
- _RAND_30 = {1{`RANDOM}};
- mem_1_3_lane_valid = _RAND_30[0:0];
- _RAND_31 = {1{`RANDOM}};
- mem_1_3_lane_bits_inst = _RAND_31[31:0];
- _RAND_32 = {1{`RANDOM}};
- mem_1_3_lane_bits_addr = _RAND_32[31:0];
- _RAND_33 = {1{`RANDOM}};
- mem_1_3_lane_bits_data = _RAND_33[31:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- ipos = 2'h0;
- end
- if (reset) begin
- opos = 2'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VInst(
- input clock,
- input reset,
- input io_in_0_valid,
- output io_in_0_ready,
- input [4:0] io_in_0_addr,
- input [31:0] io_in_0_inst,
- input [4:0] io_in_0_op,
- input io_in_1_valid,
- output io_in_1_ready,
- input [4:0] io_in_1_addr,
- input [31:0] io_in_1_inst,
- input [4:0] io_in_1_op,
- input io_in_2_valid,
- output io_in_2_ready,
- input [4:0] io_in_2_addr,
- input [31:0] io_in_2_inst,
- input [4:0] io_in_2_op,
- input io_in_3_valid,
- output io_in_3_ready,
- input [4:0] io_in_3_addr,
- input [31:0] io_in_3_inst,
- input [4:0] io_in_3_op,
- input [31:0] io_rs_0_data,
- input [31:0] io_rs_1_data,
- input [31:0] io_rs_2_data,
- input [31:0] io_rs_3_data,
- input [31:0] io_rs_4_data,
- input [31:0] io_rs_5_data,
- input [31:0] io_rs_6_data,
- input [31:0] io_rs_7_data,
- output io_rd_0_valid,
- output [4:0] io_rd_0_addr,
- output [31:0] io_rd_0_data,
- output io_rd_1_valid,
- output [4:0] io_rd_1_addr,
- output [31:0] io_rd_1_data,
- output io_rd_2_valid,
- output [4:0] io_rd_2_addr,
- output [31:0] io_rd_2_data,
- output io_rd_3_valid,
- output [4:0] io_rd_3_addr,
- output [31:0] io_rd_3_data,
- output io_out_valid,
- input io_out_ready,
- input io_out_stall,
- output io_out_lane_0_valid,
- output [31:0] io_out_lane_0_bits_inst,
- output [31:0] io_out_lane_0_bits_addr,
- output [31:0] io_out_lane_0_bits_data,
- output io_out_lane_1_valid,
- output [31:0] io_out_lane_1_bits_inst,
- output [31:0] io_out_lane_1_bits_addr,
- output [31:0] io_out_lane_1_bits_data,
- output io_out_lane_2_valid,
- output [31:0] io_out_lane_2_bits_inst,
- output [31:0] io_out_lane_2_bits_addr,
- output [31:0] io_out_lane_2_bits_data,
- output io_out_lane_3_valid,
- output [31:0] io_out_lane_3_bits_inst,
- output [31:0] io_out_lane_3_bits_addr,
- output [31:0] io_out_lane_3_bits_data,
- output io_nempty
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
-`endif // RANDOMIZE_REG_INIT
- wire slice_clock; // @[Slice.scala 23:11]
- wire slice_reset; // @[Slice.scala 23:11]
- wire slice_io_in_ready; // @[Slice.scala 23:11]
- wire slice_io_in_valid; // @[Slice.scala 23:11]
- wire slice_io_in_bits_0_lane_valid; // @[Slice.scala 23:11]
- wire [31:0] slice_io_in_bits_0_lane_bits_inst; // @[Slice.scala 23:11]
- wire [31:0] slice_io_in_bits_0_lane_bits_addr; // @[Slice.scala 23:11]
- wire [31:0] slice_io_in_bits_0_lane_bits_data; // @[Slice.scala 23:11]
- wire slice_io_in_bits_1_lane_valid; // @[Slice.scala 23:11]
- wire [31:0] slice_io_in_bits_1_lane_bits_inst; // @[Slice.scala 23:11]
- wire [31:0] slice_io_in_bits_1_lane_bits_addr; // @[Slice.scala 23:11]
- wire [31:0] slice_io_in_bits_1_lane_bits_data; // @[Slice.scala 23:11]
- wire slice_io_in_bits_2_lane_valid; // @[Slice.scala 23:11]
- wire [31:0] slice_io_in_bits_2_lane_bits_inst; // @[Slice.scala 23:11]
- wire [31:0] slice_io_in_bits_2_lane_bits_addr; // @[Slice.scala 23:11]
- wire [31:0] slice_io_in_bits_2_lane_bits_data; // @[Slice.scala 23:11]
- wire slice_io_in_bits_3_lane_valid; // @[Slice.scala 23:11]
- wire [31:0] slice_io_in_bits_3_lane_bits_inst; // @[Slice.scala 23:11]
- wire [31:0] slice_io_in_bits_3_lane_bits_addr; // @[Slice.scala 23:11]
- wire [31:0] slice_io_in_bits_3_lane_bits_data; // @[Slice.scala 23:11]
- wire slice_io_out_ready; // @[Slice.scala 23:11]
- wire slice_io_out_valid; // @[Slice.scala 23:11]
- wire slice_io_out_bits_0_lane_valid; // @[Slice.scala 23:11]
- wire [31:0] slice_io_out_bits_0_lane_bits_inst; // @[Slice.scala 23:11]
- wire [31:0] slice_io_out_bits_0_lane_bits_addr; // @[Slice.scala 23:11]
- wire [31:0] slice_io_out_bits_0_lane_bits_data; // @[Slice.scala 23:11]
- wire slice_io_out_bits_1_lane_valid; // @[Slice.scala 23:11]
- wire [31:0] slice_io_out_bits_1_lane_bits_inst; // @[Slice.scala 23:11]
- wire [31:0] slice_io_out_bits_1_lane_bits_addr; // @[Slice.scala 23:11]
- wire [31:0] slice_io_out_bits_1_lane_bits_data; // @[Slice.scala 23:11]
- wire slice_io_out_bits_2_lane_valid; // @[Slice.scala 23:11]
- wire [31:0] slice_io_out_bits_2_lane_bits_inst; // @[Slice.scala 23:11]
- wire [31:0] slice_io_out_bits_2_lane_bits_addr; // @[Slice.scala 23:11]
- wire [31:0] slice_io_out_bits_2_lane_bits_data; // @[Slice.scala 23:11]
- wire slice_io_out_bits_3_lane_valid; // @[Slice.scala 23:11]
- wire [31:0] slice_io_out_bits_3_lane_bits_inst; // @[Slice.scala 23:11]
- wire [31:0] slice_io_out_bits_3_lane_bits_addr; // @[Slice.scala 23:11]
- wire [31:0] slice_io_out_bits_3_lane_bits_data; // @[Slice.scala 23:11]
- wire _T_2 = ~reset; // @[VInst.scala 92:9]
- wire reqvalid_0 = io_in_0_valid & io_in_0_ready; // @[VInst.scala 100:41]
- wire reqvalid_1 = io_in_1_valid & io_in_1_ready; // @[VInst.scala 101:41]
- wire reqvalid_2 = io_in_2_valid & io_in_2_ready; // @[VInst.scala 102:41]
- wire reqvalid_3 = io_in_3_valid & io_in_3_ready; // @[VInst.scala 103:41]
- reg vld_u_0; // @[VInst.scala 119:22]
- reg vld_u_1; // @[VInst.scala 119:22]
- reg vld_u_2; // @[VInst.scala 119:22]
- reg vld_u_3; // @[VInst.scala 119:22]
- reg vst_u_0; // @[VInst.scala 121:22]
- reg vst_u_1; // @[VInst.scala 121:22]
- reg vst_u_2; // @[VInst.scala 121:22]
- reg vst_u_3; // @[VInst.scala 121:22]
- reg vst_q_0; // @[VInst.scala 122:22]
- reg vst_q_1; // @[VInst.scala 122:22]
- reg vst_q_2; // @[VInst.scala 122:22]
- reg vst_q_3; // @[VInst.scala 122:22]
- reg getvl_0; // @[VInst.scala 123:22]
- reg getvl_1; // @[VInst.scala 123:22]
- reg getvl_2; // @[VInst.scala 123:22]
- reg getvl_3; // @[VInst.scala 123:22]
- reg getmaxvl_0; // @[VInst.scala 124:25]
- reg getmaxvl_1; // @[VInst.scala 124:25]
- reg getmaxvl_2; // @[VInst.scala 124:25]
- reg getmaxvl_3; // @[VInst.scala 124:25]
- reg [4:0] rdAddr_0; // @[VInst.scala 126:19]
- reg [4:0] rdAddr_1; // @[VInst.scala 126:19]
- reg [4:0] rdAddr_2; // @[VInst.scala 126:19]
- reg [4:0] rdAddr_3; // @[VInst.scala 126:19]
- reg vvalid; // @[VInst.scala 136:23]
- reg vinstValid_0; // @[VInst.scala 137:27]
- reg vinstValid_1; // @[VInst.scala 137:27]
- reg vinstValid_2; // @[VInst.scala 137:27]
- reg vinstValid_3; // @[VInst.scala 137:27]
- reg [31:0] vinstInst_0; // @[VInst.scala 138:22]
- reg [31:0] vinstInst_1; // @[VInst.scala 138:22]
- reg [31:0] vinstInst_2; // @[VInst.scala 138:22]
- reg [31:0] vinstInst_3; // @[VInst.scala 138:22]
- wire _nxtVinstValid_1_T_2 = io_in_1_op[2] | io_in_1_op[3]; // @[VInst.scala 144:64]
- wire _nxtVinstValid_1_T_4 = _nxtVinstValid_1_T_2 | io_in_1_op[4]; // @[VInst.scala 145:64]
- wire nxtVinstValid_1 = reqvalid_1 & _nxtVinstValid_1_T_4; // @[VInst.scala 144:37]
- wire _nxtVinstValid_0_T_2 = io_in_0_op[2] | io_in_0_op[3]; // @[VInst.scala 144:64]
- wire _nxtVinstValid_0_T_4 = _nxtVinstValid_0_T_2 | io_in_0_op[4]; // @[VInst.scala 145:64]
- wire nxtVinstValid_0 = reqvalid_0 & _nxtVinstValid_0_T_4; // @[VInst.scala 144:37]
- wire _nxtVinstValid_3_T_2 = io_in_3_op[2] | io_in_3_op[3]; // @[VInst.scala 144:64]
- wire _nxtVinstValid_3_T_4 = _nxtVinstValid_3_T_2 | io_in_3_op[4]; // @[VInst.scala 145:64]
- wire nxtVinstValid_3 = reqvalid_3 & _nxtVinstValid_3_T_4; // @[VInst.scala 144:37]
- wire _nxtVinstValid_2_T_2 = io_in_2_op[2] | io_in_2_op[3]; // @[VInst.scala 144:64]
- wire _nxtVinstValid_2_T_4 = _nxtVinstValid_2_T_2 | io_in_2_op[4]; // @[VInst.scala 145:64]
- wire nxtVinstValid_2 = reqvalid_2 & _nxtVinstValid_2_T_4; // @[VInst.scala 144:37]
- wire [3:0] _vvalid_T = {nxtVinstValid_3,nxtVinstValid_2,nxtVinstValid_1,nxtVinstValid_0}; // @[VInst.scala 141:27]
- wire p = io_in_0_inst[28]; // @[VInst.scala 152:26]
- wire q = io_in_0_inst[30]; // @[VInst.scala 153:26]
- wire _vld_o_0_T_1 = reqvalid_0 & io_in_0_op[2]; // @[VInst.scala 154:29]
- wire _vst_o_0_T_1 = reqvalid_0 & io_in_0_op[3]; // @[VInst.scala 156:29]
- wire _vst_u_0_T_2 = _vst_o_0_T_1 & p; // @[VInst.scala 157:55]
- wire p_1 = io_in_1_inst[28]; // @[VInst.scala 152:26]
- wire q_1 = io_in_1_inst[30]; // @[VInst.scala 153:26]
- wire _vld_o_1_T_1 = reqvalid_1 & io_in_1_op[2]; // @[VInst.scala 154:29]
- wire _vst_o_1_T_1 = reqvalid_1 & io_in_1_op[3]; // @[VInst.scala 156:29]
- wire _vst_u_1_T_2 = _vst_o_1_T_1 & p_1; // @[VInst.scala 157:55]
- wire p_2 = io_in_2_inst[28]; // @[VInst.scala 152:26]
- wire q_2 = io_in_2_inst[30]; // @[VInst.scala 153:26]
- wire _vld_o_2_T_1 = reqvalid_2 & io_in_2_op[2]; // @[VInst.scala 154:29]
- wire _vst_o_2_T_1 = reqvalid_2 & io_in_2_op[3]; // @[VInst.scala 156:29]
- wire _vst_u_2_T_2 = _vst_o_2_T_1 & p_2; // @[VInst.scala 157:55]
- wire p_3 = io_in_3_inst[28]; // @[VInst.scala 152:26]
- wire q_3 = io_in_3_inst[30]; // @[VInst.scala 153:26]
- wire _vld_o_3_T_1 = reqvalid_3 & io_in_3_op[2]; // @[VInst.scala 154:29]
- wire _vst_o_3_T_1 = reqvalid_3 & io_in_3_op[3]; // @[VInst.scala 156:29]
- wire _vst_u_3_T_2 = _vst_o_3_T_1 & p_3; // @[VInst.scala 157:55]
- wire m = vinstInst_0[5]; // @[VInst.scala 172:26]
- wire [1:0] sz = vinstInst_0[13:12]; // @[VInst.scala 173:26]
- wire [1:0] sl = vinstInst_0[27:26]; // @[VInst.scala 174:26]
- wire q_4 = vinstInst_0[30]; // @[VInst.scala 175:26]
- wire xs2zero = vinstInst_0[24:20] == 5'h0; // @[VInst.scala 177:39]
- wire _max_T = sz == 2'h0; // @[VInst.scala 179:24]
- wire _max_T_1 = ~m; // @[VInst.scala 179:35]
- wire _max_T_2 = sz == 2'h0 & ~m; // @[VInst.scala 179:32]
- wire [7:0] _max_T_3 = _max_T_2 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire _max_T_4 = sz == 2'h1; // @[VInst.scala 180:24]
- wire _max_T_6 = sz == 2'h1 & _max_T_1; // @[VInst.scala 180:32]
- wire [7:0] _max_T_7 = _max_T_6 ? 8'h10 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_8 = _max_T_3 | _max_T_7; // @[VInst.scala 179:47]
- wire _max_T_9 = sz == 2'h2; // @[VInst.scala 181:24]
- wire _max_T_11 = sz == 2'h2 & _max_T_1; // @[VInst.scala 181:32]
- wire [7:0] _max_T_12 = _max_T_11 ? 8'h8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_13 = _max_T_8 | _max_T_12; // @[VInst.scala 180:47]
- wire _max_T_15 = _max_T & m; // @[VInst.scala 182:32]
- wire [7:0] _max_T_16 = _max_T_15 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_17 = _max_T_13 | _max_T_16; // @[VInst.scala 181:47]
- wire _max_T_19 = _max_T_4 & m; // @[VInst.scala 183:32]
- wire [7:0] _max_T_20 = _max_T_19 ? 8'h40 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_21 = _max_T_17 | _max_T_20; // @[VInst.scala 182:47]
- wire _max_T_23 = _max_T_9 & m; // @[VInst.scala 184:32]
- wire [7:0] _max_T_24 = _max_T_23 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] max = _max_T_21 | _max_T_24; // @[VInst.scala 183:47]
- wire [31:0] _GEN_12 = {{24'd0}, max}; // @[VInst.scala 186:25]
- wire [31:0] cmp = io_rs_1_data < _GEN_12 ? io_rs_1_data : {{24'd0}, max}; // @[VInst.scala 186:18]
- wire _bytes_T_2 = _max_T & sl[0]; // @[VInst.scala 188:35]
- wire [31:0] _bytes_T_3 = _bytes_T_2 ? cmp : 32'h0; // @[Library.scala 22:8]
- wire _bytes_T_6 = _max_T_4 & sl[0]; // @[VInst.scala 189:35]
- wire [32:0] _bytes_T_7 = {cmp,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _bytes_T_8 = _bytes_T_6 ? _bytes_T_7 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_13 = {{1'd0}, _bytes_T_3}; // @[VInst.scala 188:50]
- wire [32:0] _bytes_T_9 = _GEN_13 | _bytes_T_8; // @[VInst.scala 188:50]
- wire _bytes_T_12 = _max_T_9 & sl[0]; // @[VInst.scala 190:35]
- wire [33:0] _bytes_T_13 = {cmp,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _bytes_T_14 = _bytes_T_12 ? _bytes_T_13 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_14 = {{1'd0}, _bytes_T_9}; // @[VInst.scala 189:65]
- wire [33:0] _bytes_T_15 = _GEN_14 | _bytes_T_14; // @[VInst.scala 189:65]
- wire _bytes_T_17 = ~sl[0]; // @[VInst.scala 191:24]
- wire _bytes_T_19 = ~sl[0] & _max_T_1; // @[VInst.scala 191:31]
- wire [7:0] _bytes_T_20 = _bytes_T_19 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_15 = {{26'd0}, _bytes_T_20}; // @[VInst.scala 190:65]
- wire [33:0] _bytes_T_21 = _bytes_T_15 | _GEN_15; // @[VInst.scala 190:65]
- wire _bytes_T_24 = _bytes_T_17 & m; // @[VInst.scala 192:31]
- wire [7:0] _bytes_T_25 = _bytes_T_24 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_16 = {{26'd0}, _bytes_T_25}; // @[VInst.scala 191:46]
- wire [33:0] _bytes_T_26 = _bytes_T_21 | _GEN_16; // @[VInst.scala 191:46]
- wire [31:0] bytes = _bytes_T_26[31:0]; // @[VInst.scala 193:18]
- wire [31:0] _rt_T_1 = _max_T ? io_rs_1_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _rt_T_3 = {io_rs_1_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _rt_T_4 = _max_T_4 ? _rt_T_3 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_17 = {{1'd0}, _rt_T_1}; // @[VInst.scala 196:38]
- wire [32:0] _rt_T_5 = _GEN_17 | _rt_T_4; // @[VInst.scala 196:38]
- wire [33:0] _rt_T_7 = {io_rs_1_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _rt_T_8 = _max_T_9 ? _rt_T_7 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_18 = {{1'd0}, _rt_T_5}; // @[VInst.scala 197:53]
- wire [33:0] _rt_T_9 = _GEN_18 | _rt_T_8; // @[VInst.scala 197:53]
- wire [31:0] rt = _rt_T_9[31:0]; // @[VInst.scala 199:15]
- wire [33:0] _rtm_T = {rt,2'h0}; // @[Cat.scala 31:58]
- wire [31:0] rtm = _rtm_T[31:0]; // @[VInst.scala 201:34]
- wire [35:0] _rtq_T = {rt,4'h0}; // @[Cat.scala 31:58]
- wire [31:0] rtq = _rtq_T[31:0]; // @[VInst.scala 202:34]
- wire _p_x_T = sl == 2'h0; // @[VInst.scala 204:20]
- wire p_x = sl == 2'h0 & xs2zero; // @[VInst.scala 204:28]
- wire p_xx = _p_x_T & ~xs2zero; // @[VInst.scala 205:28]
- wire lp_xx = sl == 2'h1; // @[VInst.scala 206:20]
- wire _sp_xx_T = sl == 2'h2; // @[VInst.scala 207:20]
- wire sp_xx = sl == 2'h2 & ~q_4; // @[VInst.scala 207:28]
- wire qp_xx = _sp_xx_T & q_4; // @[VInst.scala 208:28]
- wire tp_xx = sl == 2'h3; // @[VInst.scala 209:20]
- wire [5:0] _T_4 = {p_x,p_xx,lp_xx,sp_xx,qp_xx,tp_xx}; // @[Cat.scala 31:58]
- wire [1:0] _T_11 = _T_4[1] + _T_4[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_19 = {{1'd0}, _T_4[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_13 = _GEN_19 + _T_11; // @[Bitwise.scala 48:55]
- wire [1:0] _T_15 = _T_4[4] + _T_4[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_20 = {{1'd0}, _T_4[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_17 = _GEN_20 + _T_15; // @[Bitwise.scala 48:55]
- wire [2:0] _T_19 = _T_13[1:0] + _T_17[1:0]; // @[Bitwise.scala 48:55]
- wire [7:0] _offset_T = m ? 8'h80 : 8'h20; // @[VInst.scala 212:34]
- wire [7:0] _offset_T_1 = p_x ? _offset_T : 8'h0; // @[Library.scala 22:8]
- wire [31:0] _offset_T_2 = p_xx ? rt : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _GEN_21 = {{24'd0}, _offset_T_1}; // @[VInst.scala 212:56]
- wire [31:0] _offset_T_3 = _GEN_21 | _offset_T_2; // @[VInst.scala 212:56]
- wire [31:0] _offset_T_4 = lp_xx ? bytes : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _offset_T_5 = _offset_T_3 | _offset_T_4; // @[VInst.scala 213:35]
- wire [31:0] _offset_T_6 = m ? rtm : rt; // @[VInst.scala 215:34]
- wire [31:0] _offset_T_7 = sp_xx ? _offset_T_6 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _offset_T_8 = _offset_T_5 | _offset_T_7; // @[VInst.scala 214:38]
- wire [7:0] _offset_T_9 = tp_xx ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [31:0] _GEN_22 = {{24'd0}, _offset_T_9}; // @[VInst.scala 215:48]
- wire [31:0] _offset_T_10 = _offset_T_8 | _GEN_22; // @[VInst.scala 215:48]
- wire [31:0] _offset_T_11 = m ? rtq : rtm; // @[VInst.scala 217:34]
- wire [31:0] _offset_T_12 = qp_xx ? _offset_T_11 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] offset = _offset_T_10 | _offset_T_12; // @[VInst.scala 216:39]
- wire [31:0] lsuAdder_0 = io_rs_0_data + offset; // @[VInst.scala 220:24]
- wire m_1 = vinstInst_1[5]; // @[VInst.scala 172:26]
- wire [1:0] sz_1 = vinstInst_1[13:12]; // @[VInst.scala 173:26]
- wire [1:0] sl_1 = vinstInst_1[27:26]; // @[VInst.scala 174:26]
- wire q_5 = vinstInst_1[30]; // @[VInst.scala 175:26]
- wire xs2zero_1 = vinstInst_1[24:20] == 5'h0; // @[VInst.scala 177:39]
- wire _max_T_25 = sz_1 == 2'h0; // @[VInst.scala 179:24]
- wire _max_T_26 = ~m_1; // @[VInst.scala 179:35]
- wire _max_T_27 = sz_1 == 2'h0 & ~m_1; // @[VInst.scala 179:32]
- wire [7:0] _max_T_28 = _max_T_27 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire _max_T_29 = sz_1 == 2'h1; // @[VInst.scala 180:24]
- wire _max_T_31 = sz_1 == 2'h1 & _max_T_26; // @[VInst.scala 180:32]
- wire [7:0] _max_T_32 = _max_T_31 ? 8'h10 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_33 = _max_T_28 | _max_T_32; // @[VInst.scala 179:47]
- wire _max_T_34 = sz_1 == 2'h2; // @[VInst.scala 181:24]
- wire _max_T_36 = sz_1 == 2'h2 & _max_T_26; // @[VInst.scala 181:32]
- wire [7:0] _max_T_37 = _max_T_36 ? 8'h8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_38 = _max_T_33 | _max_T_37; // @[VInst.scala 180:47]
- wire _max_T_40 = _max_T_25 & m_1; // @[VInst.scala 182:32]
- wire [7:0] _max_T_41 = _max_T_40 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_42 = _max_T_38 | _max_T_41; // @[VInst.scala 181:47]
- wire _max_T_44 = _max_T_29 & m_1; // @[VInst.scala 183:32]
- wire [7:0] _max_T_45 = _max_T_44 ? 8'h40 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_46 = _max_T_42 | _max_T_45; // @[VInst.scala 182:47]
- wire _max_T_48 = _max_T_34 & m_1; // @[VInst.scala 184:32]
- wire [7:0] _max_T_49 = _max_T_48 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] max_1 = _max_T_46 | _max_T_49; // @[VInst.scala 183:47]
- wire [31:0] _GEN_23 = {{24'd0}, max_1}; // @[VInst.scala 186:25]
- wire [31:0] cmp_1 = io_rs_3_data < _GEN_23 ? io_rs_3_data : {{24'd0}, max_1}; // @[VInst.scala 186:18]
- wire _bytes_T_29 = _max_T_25 & sl_1[0]; // @[VInst.scala 188:35]
- wire [31:0] _bytes_T_30 = _bytes_T_29 ? cmp_1 : 32'h0; // @[Library.scala 22:8]
- wire _bytes_T_33 = _max_T_29 & sl_1[0]; // @[VInst.scala 189:35]
- wire [32:0] _bytes_T_34 = {cmp_1,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _bytes_T_35 = _bytes_T_33 ? _bytes_T_34 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_24 = {{1'd0}, _bytes_T_30}; // @[VInst.scala 188:50]
- wire [32:0] _bytes_T_36 = _GEN_24 | _bytes_T_35; // @[VInst.scala 188:50]
- wire _bytes_T_39 = _max_T_34 & sl_1[0]; // @[VInst.scala 190:35]
- wire [33:0] _bytes_T_40 = {cmp_1,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _bytes_T_41 = _bytes_T_39 ? _bytes_T_40 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_25 = {{1'd0}, _bytes_T_36}; // @[VInst.scala 189:65]
- wire [33:0] _bytes_T_42 = _GEN_25 | _bytes_T_41; // @[VInst.scala 189:65]
- wire _bytes_T_44 = ~sl_1[0]; // @[VInst.scala 191:24]
- wire _bytes_T_46 = ~sl_1[0] & _max_T_26; // @[VInst.scala 191:31]
- wire [7:0] _bytes_T_47 = _bytes_T_46 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_26 = {{26'd0}, _bytes_T_47}; // @[VInst.scala 190:65]
- wire [33:0] _bytes_T_48 = _bytes_T_42 | _GEN_26; // @[VInst.scala 190:65]
- wire _bytes_T_51 = _bytes_T_44 & m_1; // @[VInst.scala 192:31]
- wire [7:0] _bytes_T_52 = _bytes_T_51 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_27 = {{26'd0}, _bytes_T_52}; // @[VInst.scala 191:46]
- wire [33:0] _bytes_T_53 = _bytes_T_48 | _GEN_27; // @[VInst.scala 191:46]
- wire [31:0] bytes_1 = _bytes_T_53[31:0]; // @[VInst.scala 193:18]
- wire [31:0] _rt_T_11 = _max_T_25 ? io_rs_3_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _rt_T_13 = {io_rs_3_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _rt_T_14 = _max_T_29 ? _rt_T_13 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_28 = {{1'd0}, _rt_T_11}; // @[VInst.scala 196:38]
- wire [32:0] _rt_T_15 = _GEN_28 | _rt_T_14; // @[VInst.scala 196:38]
- wire [33:0] _rt_T_17 = {io_rs_3_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _rt_T_18 = _max_T_34 ? _rt_T_17 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_29 = {{1'd0}, _rt_T_15}; // @[VInst.scala 197:53]
- wire [33:0] _rt_T_19 = _GEN_29 | _rt_T_18; // @[VInst.scala 197:53]
- wire [31:0] rt_1 = _rt_T_19[31:0]; // @[VInst.scala 199:15]
- wire [33:0] _rtm_T_1 = {rt_1,2'h0}; // @[Cat.scala 31:58]
- wire [31:0] rtm_1 = _rtm_T_1[31:0]; // @[VInst.scala 201:34]
- wire [35:0] _rtq_T_1 = {rt_1,4'h0}; // @[Cat.scala 31:58]
- wire [31:0] rtq_1 = _rtq_T_1[31:0]; // @[VInst.scala 202:34]
- wire _p_x_T_1 = sl_1 == 2'h0; // @[VInst.scala 204:20]
- wire p_x_1 = sl_1 == 2'h0 & xs2zero_1; // @[VInst.scala 204:28]
- wire p_xx_1 = _p_x_T_1 & ~xs2zero_1; // @[VInst.scala 205:28]
- wire lp_xx_1 = sl_1 == 2'h1; // @[VInst.scala 206:20]
- wire _sp_xx_T_2 = sl_1 == 2'h2; // @[VInst.scala 207:20]
- wire sp_xx_1 = sl_1 == 2'h2 & ~q_5; // @[VInst.scala 207:28]
- wire qp_xx_1 = _sp_xx_T_2 & q_5; // @[VInst.scala 208:28]
- wire tp_xx_1 = sl_1 == 2'h3; // @[VInst.scala 209:20]
- wire [5:0] _T_25 = {p_x_1,p_xx_1,lp_xx_1,sp_xx_1,qp_xx_1,tp_xx_1}; // @[Cat.scala 31:58]
- wire [1:0] _T_32 = _T_25[1] + _T_25[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_30 = {{1'd0}, _T_25[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_34 = _GEN_30 + _T_32; // @[Bitwise.scala 48:55]
- wire [1:0] _T_36 = _T_25[4] + _T_25[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_31 = {{1'd0}, _T_25[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_38 = _GEN_31 + _T_36; // @[Bitwise.scala 48:55]
- wire [2:0] _T_40 = _T_34[1:0] + _T_38[1:0]; // @[Bitwise.scala 48:55]
- wire [7:0] _offset_T_13 = m_1 ? 8'h80 : 8'h20; // @[VInst.scala 212:34]
- wire [7:0] _offset_T_14 = p_x_1 ? _offset_T_13 : 8'h0; // @[Library.scala 22:8]
- wire [31:0] _offset_T_15 = p_xx_1 ? rt_1 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _GEN_32 = {{24'd0}, _offset_T_14}; // @[VInst.scala 212:56]
- wire [31:0] _offset_T_16 = _GEN_32 | _offset_T_15; // @[VInst.scala 212:56]
- wire [31:0] _offset_T_17 = lp_xx_1 ? bytes_1 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _offset_T_18 = _offset_T_16 | _offset_T_17; // @[VInst.scala 213:35]
- wire [31:0] _offset_T_19 = m_1 ? rtm_1 : rt_1; // @[VInst.scala 215:34]
- wire [31:0] _offset_T_20 = sp_xx_1 ? _offset_T_19 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _offset_T_21 = _offset_T_18 | _offset_T_20; // @[VInst.scala 214:38]
- wire [7:0] _offset_T_22 = tp_xx_1 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [31:0] _GEN_33 = {{24'd0}, _offset_T_22}; // @[VInst.scala 215:48]
- wire [31:0] _offset_T_23 = _offset_T_21 | _GEN_33; // @[VInst.scala 215:48]
- wire [31:0] _offset_T_24 = m_1 ? rtq_1 : rtm_1; // @[VInst.scala 217:34]
- wire [31:0] _offset_T_25 = qp_xx_1 ? _offset_T_24 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] offset_1 = _offset_T_23 | _offset_T_25; // @[VInst.scala 216:39]
- wire [31:0] lsuAdder_1 = io_rs_2_data + offset_1; // @[VInst.scala 220:24]
- wire m_2 = vinstInst_2[5]; // @[VInst.scala 172:26]
- wire [1:0] sz_2 = vinstInst_2[13:12]; // @[VInst.scala 173:26]
- wire [1:0] sl_2 = vinstInst_2[27:26]; // @[VInst.scala 174:26]
- wire q_6 = vinstInst_2[30]; // @[VInst.scala 175:26]
- wire xs2zero_2 = vinstInst_2[24:20] == 5'h0; // @[VInst.scala 177:39]
- wire _max_T_50 = sz_2 == 2'h0; // @[VInst.scala 179:24]
- wire _max_T_51 = ~m_2; // @[VInst.scala 179:35]
- wire _max_T_52 = sz_2 == 2'h0 & ~m_2; // @[VInst.scala 179:32]
- wire [7:0] _max_T_53 = _max_T_52 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire _max_T_54 = sz_2 == 2'h1; // @[VInst.scala 180:24]
- wire _max_T_56 = sz_2 == 2'h1 & _max_T_51; // @[VInst.scala 180:32]
- wire [7:0] _max_T_57 = _max_T_56 ? 8'h10 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_58 = _max_T_53 | _max_T_57; // @[VInst.scala 179:47]
- wire _max_T_59 = sz_2 == 2'h2; // @[VInst.scala 181:24]
- wire _max_T_61 = sz_2 == 2'h2 & _max_T_51; // @[VInst.scala 181:32]
- wire [7:0] _max_T_62 = _max_T_61 ? 8'h8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_63 = _max_T_58 | _max_T_62; // @[VInst.scala 180:47]
- wire _max_T_65 = _max_T_50 & m_2; // @[VInst.scala 182:32]
- wire [7:0] _max_T_66 = _max_T_65 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_67 = _max_T_63 | _max_T_66; // @[VInst.scala 181:47]
- wire _max_T_69 = _max_T_54 & m_2; // @[VInst.scala 183:32]
- wire [7:0] _max_T_70 = _max_T_69 ? 8'h40 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_71 = _max_T_67 | _max_T_70; // @[VInst.scala 182:47]
- wire _max_T_73 = _max_T_59 & m_2; // @[VInst.scala 184:32]
- wire [7:0] _max_T_74 = _max_T_73 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] max_2 = _max_T_71 | _max_T_74; // @[VInst.scala 183:47]
- wire [31:0] _GEN_34 = {{24'd0}, max_2}; // @[VInst.scala 186:25]
- wire [31:0] cmp_2 = io_rs_5_data < _GEN_34 ? io_rs_5_data : {{24'd0}, max_2}; // @[VInst.scala 186:18]
- wire _bytes_T_56 = _max_T_50 & sl_2[0]; // @[VInst.scala 188:35]
- wire [31:0] _bytes_T_57 = _bytes_T_56 ? cmp_2 : 32'h0; // @[Library.scala 22:8]
- wire _bytes_T_60 = _max_T_54 & sl_2[0]; // @[VInst.scala 189:35]
- wire [32:0] _bytes_T_61 = {cmp_2,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _bytes_T_62 = _bytes_T_60 ? _bytes_T_61 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_35 = {{1'd0}, _bytes_T_57}; // @[VInst.scala 188:50]
- wire [32:0] _bytes_T_63 = _GEN_35 | _bytes_T_62; // @[VInst.scala 188:50]
- wire _bytes_T_66 = _max_T_59 & sl_2[0]; // @[VInst.scala 190:35]
- wire [33:0] _bytes_T_67 = {cmp_2,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _bytes_T_68 = _bytes_T_66 ? _bytes_T_67 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_36 = {{1'd0}, _bytes_T_63}; // @[VInst.scala 189:65]
- wire [33:0] _bytes_T_69 = _GEN_36 | _bytes_T_68; // @[VInst.scala 189:65]
- wire _bytes_T_71 = ~sl_2[0]; // @[VInst.scala 191:24]
- wire _bytes_T_73 = ~sl_2[0] & _max_T_51; // @[VInst.scala 191:31]
- wire [7:0] _bytes_T_74 = _bytes_T_73 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_37 = {{26'd0}, _bytes_T_74}; // @[VInst.scala 190:65]
- wire [33:0] _bytes_T_75 = _bytes_T_69 | _GEN_37; // @[VInst.scala 190:65]
- wire _bytes_T_78 = _bytes_T_71 & m_2; // @[VInst.scala 192:31]
- wire [7:0] _bytes_T_79 = _bytes_T_78 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_38 = {{26'd0}, _bytes_T_79}; // @[VInst.scala 191:46]
- wire [33:0] _bytes_T_80 = _bytes_T_75 | _GEN_38; // @[VInst.scala 191:46]
- wire [31:0] bytes_2 = _bytes_T_80[31:0]; // @[VInst.scala 193:18]
- wire [31:0] _rt_T_21 = _max_T_50 ? io_rs_5_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _rt_T_23 = {io_rs_5_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _rt_T_24 = _max_T_54 ? _rt_T_23 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_39 = {{1'd0}, _rt_T_21}; // @[VInst.scala 196:38]
- wire [32:0] _rt_T_25 = _GEN_39 | _rt_T_24; // @[VInst.scala 196:38]
- wire [33:0] _rt_T_27 = {io_rs_5_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _rt_T_28 = _max_T_59 ? _rt_T_27 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_40 = {{1'd0}, _rt_T_25}; // @[VInst.scala 197:53]
- wire [33:0] _rt_T_29 = _GEN_40 | _rt_T_28; // @[VInst.scala 197:53]
- wire [31:0] rt_2 = _rt_T_29[31:0]; // @[VInst.scala 199:15]
- wire [33:0] _rtm_T_2 = {rt_2,2'h0}; // @[Cat.scala 31:58]
- wire [31:0] rtm_2 = _rtm_T_2[31:0]; // @[VInst.scala 201:34]
- wire [35:0] _rtq_T_2 = {rt_2,4'h0}; // @[Cat.scala 31:58]
- wire [31:0] rtq_2 = _rtq_T_2[31:0]; // @[VInst.scala 202:34]
- wire _p_x_T_2 = sl_2 == 2'h0; // @[VInst.scala 204:20]
- wire p_x_2 = sl_2 == 2'h0 & xs2zero_2; // @[VInst.scala 204:28]
- wire p_xx_2 = _p_x_T_2 & ~xs2zero_2; // @[VInst.scala 205:28]
- wire lp_xx_2 = sl_2 == 2'h1; // @[VInst.scala 206:20]
- wire _sp_xx_T_4 = sl_2 == 2'h2; // @[VInst.scala 207:20]
- wire sp_xx_2 = sl_2 == 2'h2 & ~q_6; // @[VInst.scala 207:28]
- wire qp_xx_2 = _sp_xx_T_4 & q_6; // @[VInst.scala 208:28]
- wire tp_xx_2 = sl_2 == 2'h3; // @[VInst.scala 209:20]
- wire [5:0] _T_46 = {p_x_2,p_xx_2,lp_xx_2,sp_xx_2,qp_xx_2,tp_xx_2}; // @[Cat.scala 31:58]
- wire [1:0] _T_53 = _T_46[1] + _T_46[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_41 = {{1'd0}, _T_46[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_55 = _GEN_41 + _T_53; // @[Bitwise.scala 48:55]
- wire [1:0] _T_57 = _T_46[4] + _T_46[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_42 = {{1'd0}, _T_46[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_59 = _GEN_42 + _T_57; // @[Bitwise.scala 48:55]
- wire [2:0] _T_61 = _T_55[1:0] + _T_59[1:0]; // @[Bitwise.scala 48:55]
- wire [7:0] _offset_T_26 = m_2 ? 8'h80 : 8'h20; // @[VInst.scala 212:34]
- wire [7:0] _offset_T_27 = p_x_2 ? _offset_T_26 : 8'h0; // @[Library.scala 22:8]
- wire [31:0] _offset_T_28 = p_xx_2 ? rt_2 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _GEN_43 = {{24'd0}, _offset_T_27}; // @[VInst.scala 212:56]
- wire [31:0] _offset_T_29 = _GEN_43 | _offset_T_28; // @[VInst.scala 212:56]
- wire [31:0] _offset_T_30 = lp_xx_2 ? bytes_2 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _offset_T_31 = _offset_T_29 | _offset_T_30; // @[VInst.scala 213:35]
- wire [31:0] _offset_T_32 = m_2 ? rtm_2 : rt_2; // @[VInst.scala 215:34]
- wire [31:0] _offset_T_33 = sp_xx_2 ? _offset_T_32 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _offset_T_34 = _offset_T_31 | _offset_T_33; // @[VInst.scala 214:38]
- wire [7:0] _offset_T_35 = tp_xx_2 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [31:0] _GEN_44 = {{24'd0}, _offset_T_35}; // @[VInst.scala 215:48]
- wire [31:0] _offset_T_36 = _offset_T_34 | _GEN_44; // @[VInst.scala 215:48]
- wire [31:0] _offset_T_37 = m_2 ? rtq_2 : rtm_2; // @[VInst.scala 217:34]
- wire [31:0] _offset_T_38 = qp_xx_2 ? _offset_T_37 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] offset_2 = _offset_T_36 | _offset_T_38; // @[VInst.scala 216:39]
- wire [31:0] lsuAdder_2 = io_rs_4_data + offset_2; // @[VInst.scala 220:24]
- wire m_3 = vinstInst_3[5]; // @[VInst.scala 172:26]
- wire [1:0] sz_3 = vinstInst_3[13:12]; // @[VInst.scala 173:26]
- wire [1:0] sl_3 = vinstInst_3[27:26]; // @[VInst.scala 174:26]
- wire q_7 = vinstInst_3[30]; // @[VInst.scala 175:26]
- wire xs2zero_3 = vinstInst_3[24:20] == 5'h0; // @[VInst.scala 177:39]
- wire _max_T_75 = sz_3 == 2'h0; // @[VInst.scala 179:24]
- wire _max_T_76 = ~m_3; // @[VInst.scala 179:35]
- wire _max_T_77 = sz_3 == 2'h0 & ~m_3; // @[VInst.scala 179:32]
- wire [7:0] _max_T_78 = _max_T_77 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire _max_T_79 = sz_3 == 2'h1; // @[VInst.scala 180:24]
- wire _max_T_81 = sz_3 == 2'h1 & _max_T_76; // @[VInst.scala 180:32]
- wire [7:0] _max_T_82 = _max_T_81 ? 8'h10 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_83 = _max_T_78 | _max_T_82; // @[VInst.scala 179:47]
- wire _max_T_84 = sz_3 == 2'h2; // @[VInst.scala 181:24]
- wire _max_T_86 = sz_3 == 2'h2 & _max_T_76; // @[VInst.scala 181:32]
- wire [7:0] _max_T_87 = _max_T_86 ? 8'h8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_88 = _max_T_83 | _max_T_87; // @[VInst.scala 180:47]
- wire _max_T_90 = _max_T_75 & m_3; // @[VInst.scala 182:32]
- wire [7:0] _max_T_91 = _max_T_90 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_92 = _max_T_88 | _max_T_91; // @[VInst.scala 181:47]
- wire _max_T_94 = _max_T_79 & m_3; // @[VInst.scala 183:32]
- wire [7:0] _max_T_95 = _max_T_94 ? 8'h40 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _max_T_96 = _max_T_92 | _max_T_95; // @[VInst.scala 182:47]
- wire _max_T_98 = _max_T_84 & m_3; // @[VInst.scala 184:32]
- wire [7:0] _max_T_99 = _max_T_98 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] max_3 = _max_T_96 | _max_T_99; // @[VInst.scala 183:47]
- wire [31:0] _GEN_45 = {{24'd0}, max_3}; // @[VInst.scala 186:25]
- wire [31:0] cmp_3 = io_rs_7_data < _GEN_45 ? io_rs_7_data : {{24'd0}, max_3}; // @[VInst.scala 186:18]
- wire _bytes_T_83 = _max_T_75 & sl_3[0]; // @[VInst.scala 188:35]
- wire [31:0] _bytes_T_84 = _bytes_T_83 ? cmp_3 : 32'h0; // @[Library.scala 22:8]
- wire _bytes_T_87 = _max_T_79 & sl_3[0]; // @[VInst.scala 189:35]
- wire [32:0] _bytes_T_88 = {cmp_3,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _bytes_T_89 = _bytes_T_87 ? _bytes_T_88 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_46 = {{1'd0}, _bytes_T_84}; // @[VInst.scala 188:50]
- wire [32:0] _bytes_T_90 = _GEN_46 | _bytes_T_89; // @[VInst.scala 188:50]
- wire _bytes_T_93 = _max_T_84 & sl_3[0]; // @[VInst.scala 190:35]
- wire [33:0] _bytes_T_94 = {cmp_3,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _bytes_T_95 = _bytes_T_93 ? _bytes_T_94 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_47 = {{1'd0}, _bytes_T_90}; // @[VInst.scala 189:65]
- wire [33:0] _bytes_T_96 = _GEN_47 | _bytes_T_95; // @[VInst.scala 189:65]
- wire _bytes_T_98 = ~sl_3[0]; // @[VInst.scala 191:24]
- wire _bytes_T_100 = ~sl_3[0] & _max_T_76; // @[VInst.scala 191:31]
- wire [7:0] _bytes_T_101 = _bytes_T_100 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_48 = {{26'd0}, _bytes_T_101}; // @[VInst.scala 190:65]
- wire [33:0] _bytes_T_102 = _bytes_T_96 | _GEN_48; // @[VInst.scala 190:65]
- wire _bytes_T_105 = _bytes_T_98 & m_3; // @[VInst.scala 192:31]
- wire [7:0] _bytes_T_106 = _bytes_T_105 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_49 = {{26'd0}, _bytes_T_106}; // @[VInst.scala 191:46]
- wire [33:0] _bytes_T_107 = _bytes_T_102 | _GEN_49; // @[VInst.scala 191:46]
- wire [31:0] bytes_3 = _bytes_T_107[31:0]; // @[VInst.scala 193:18]
- wire [31:0] _rt_T_31 = _max_T_75 ? io_rs_7_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _rt_T_33 = {io_rs_7_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _rt_T_34 = _max_T_79 ? _rt_T_33 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_50 = {{1'd0}, _rt_T_31}; // @[VInst.scala 196:38]
- wire [32:0] _rt_T_35 = _GEN_50 | _rt_T_34; // @[VInst.scala 196:38]
- wire [33:0] _rt_T_37 = {io_rs_7_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _rt_T_38 = _max_T_84 ? _rt_T_37 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_51 = {{1'd0}, _rt_T_35}; // @[VInst.scala 197:53]
- wire [33:0] _rt_T_39 = _GEN_51 | _rt_T_38; // @[VInst.scala 197:53]
- wire [31:0] rt_3 = _rt_T_39[31:0]; // @[VInst.scala 199:15]
- wire [33:0] _rtm_T_3 = {rt_3,2'h0}; // @[Cat.scala 31:58]
- wire [31:0] rtm_3 = _rtm_T_3[31:0]; // @[VInst.scala 201:34]
- wire [35:0] _rtq_T_3 = {rt_3,4'h0}; // @[Cat.scala 31:58]
- wire [31:0] rtq_3 = _rtq_T_3[31:0]; // @[VInst.scala 202:34]
- wire _p_x_T_3 = sl_3 == 2'h0; // @[VInst.scala 204:20]
- wire p_x_3 = sl_3 == 2'h0 & xs2zero_3; // @[VInst.scala 204:28]
- wire p_xx_3 = _p_x_T_3 & ~xs2zero_3; // @[VInst.scala 205:28]
- wire lp_xx_3 = sl_3 == 2'h1; // @[VInst.scala 206:20]
- wire _sp_xx_T_6 = sl_3 == 2'h2; // @[VInst.scala 207:20]
- wire sp_xx_3 = sl_3 == 2'h2 & ~q_7; // @[VInst.scala 207:28]
- wire qp_xx_3 = _sp_xx_T_6 & q_7; // @[VInst.scala 208:28]
- wire tp_xx_3 = sl_3 == 2'h3; // @[VInst.scala 209:20]
- wire [5:0] _T_67 = {p_x_3,p_xx_3,lp_xx_3,sp_xx_3,qp_xx_3,tp_xx_3}; // @[Cat.scala 31:58]
- wire [1:0] _T_74 = _T_67[1] + _T_67[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_52 = {{1'd0}, _T_67[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_76 = _GEN_52 + _T_74; // @[Bitwise.scala 48:55]
- wire [1:0] _T_78 = _T_67[4] + _T_67[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_53 = {{1'd0}, _T_67[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_80 = _GEN_53 + _T_78; // @[Bitwise.scala 48:55]
- wire [2:0] _T_82 = _T_76[1:0] + _T_80[1:0]; // @[Bitwise.scala 48:55]
- wire [7:0] _offset_T_39 = m_3 ? 8'h80 : 8'h20; // @[VInst.scala 212:34]
- wire [7:0] _offset_T_40 = p_x_3 ? _offset_T_39 : 8'h0; // @[Library.scala 22:8]
- wire [31:0] _offset_T_41 = p_xx_3 ? rt_3 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _GEN_54 = {{24'd0}, _offset_T_40}; // @[VInst.scala 212:56]
- wire [31:0] _offset_T_42 = _GEN_54 | _offset_T_41; // @[VInst.scala 212:56]
- wire [31:0] _offset_T_43 = lp_xx_3 ? bytes_3 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _offset_T_44 = _offset_T_42 | _offset_T_43; // @[VInst.scala 213:35]
- wire [31:0] _offset_T_45 = m_3 ? rtm_3 : rt_3; // @[VInst.scala 215:34]
- wire [31:0] _offset_T_46 = sp_xx_3 ? _offset_T_45 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _offset_T_47 = _offset_T_44 | _offset_T_46; // @[VInst.scala 214:38]
- wire [7:0] _offset_T_48 = tp_xx_3 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [31:0] _GEN_55 = {{24'd0}, _offset_T_48}; // @[VInst.scala 215:48]
- wire [31:0] _offset_T_49 = _offset_T_47 | _GEN_55; // @[VInst.scala 215:48]
- wire [31:0] _offset_T_50 = m_3 ? rtq_3 : rtm_3; // @[VInst.scala 217:34]
- wire [31:0] _offset_T_51 = qp_xx_3 ? _offset_T_50 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] offset_3 = _offset_T_49 | _offset_T_51; // @[VInst.scala 216:39]
- wire [31:0] lsuAdder_3 = io_rs_6_data + offset_3; // @[VInst.scala 220:24]
- wire [1:0] getvlsz = vinstInst_0[26:25]; // @[VInst.scala 227:31]
- wire getvlm = vinstInst_0[27]; // @[VInst.scala 228:31]
- wire _maxvl_T = getvlsz == 2'h0; // @[VInst.scala 229:31]
- wire _maxvl_T_1 = ~getvlm; // @[VInst.scala 229:42]
- wire _maxvl_T_2 = getvlsz == 2'h0 & ~getvlm; // @[VInst.scala 229:39]
- wire [7:0] _maxvl_T_3 = _maxvl_T_2 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire _maxvl_T_4 = getvlsz == 2'h1; // @[VInst.scala 230:31]
- wire _maxvl_T_6 = getvlsz == 2'h1 & _maxvl_T_1; // @[VInst.scala 230:39]
- wire [7:0] _maxvl_T_7 = _maxvl_T_6 ? 8'h10 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_8 = _maxvl_T_3 | _maxvl_T_7; // @[VInst.scala 229:59]
- wire _maxvl_T_9 = getvlsz == 2'h2; // @[VInst.scala 231:31]
- wire _maxvl_T_11 = getvlsz == 2'h2 & _maxvl_T_1; // @[VInst.scala 231:39]
- wire [7:0] _maxvl_T_12 = _maxvl_T_11 ? 8'h8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_13 = _maxvl_T_8 | _maxvl_T_12; // @[VInst.scala 230:59]
- wire _maxvl_T_15 = _maxvl_T & getvlm; // @[VInst.scala 232:39]
- wire [7:0] _maxvl_T_16 = _maxvl_T_15 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_17 = _maxvl_T_13 | _maxvl_T_16; // @[VInst.scala 231:59]
- wire _maxvl_T_19 = _maxvl_T_4 & getvlm; // @[VInst.scala 233:39]
- wire [7:0] _maxvl_T_20 = _maxvl_T_19 ? 8'h40 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_21 = _maxvl_T_17 | _maxvl_T_20; // @[VInst.scala 232:60]
- wire _maxvl_T_23 = _maxvl_T_9 & getvlm; // @[VInst.scala 234:39]
- wire [7:0] _maxvl_T_24 = _maxvl_T_23 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] maxvl = _maxvl_T_21 | _maxvl_T_24; // @[VInst.scala 233:60]
- wire rs2nonzero = vinstInst_0[24:20] != 5'h0; // @[VInst.scala 236:42]
- wire [31:0] _GEN_56 = {{24'd0}, maxvl}; // @[VInst.scala 238:15]
- wire [31:0] _GEN_4 = io_rs_0_data < _GEN_56 ? io_rs_0_data : {{24'd0}, maxvl}; // @[VInst.scala 240:31 241:11 243:11]
- wire [31:0] _GEN_5 = io_rs_1_data < _GEN_56 & io_rs_1_data < io_rs_0_data & rs2nonzero ? io_rs_1_data : _GEN_4; // @[VInst.scala 238:51 239:11]
- wire [1:0] getvlsz_1 = vinstInst_1[26:25]; // @[VInst.scala 227:31]
- wire getvlm_1 = vinstInst_1[27]; // @[VInst.scala 228:31]
- wire _maxvl_T_25 = getvlsz_1 == 2'h0; // @[VInst.scala 229:31]
- wire _maxvl_T_26 = ~getvlm_1; // @[VInst.scala 229:42]
- wire _maxvl_T_27 = getvlsz_1 == 2'h0 & ~getvlm_1; // @[VInst.scala 229:39]
- wire [7:0] _maxvl_T_28 = _maxvl_T_27 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire _maxvl_T_29 = getvlsz_1 == 2'h1; // @[VInst.scala 230:31]
- wire _maxvl_T_31 = getvlsz_1 == 2'h1 & _maxvl_T_26; // @[VInst.scala 230:39]
- wire [7:0] _maxvl_T_32 = _maxvl_T_31 ? 8'h10 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_33 = _maxvl_T_28 | _maxvl_T_32; // @[VInst.scala 229:59]
- wire _maxvl_T_34 = getvlsz_1 == 2'h2; // @[VInst.scala 231:31]
- wire _maxvl_T_36 = getvlsz_1 == 2'h2 & _maxvl_T_26; // @[VInst.scala 231:39]
- wire [7:0] _maxvl_T_37 = _maxvl_T_36 ? 8'h8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_38 = _maxvl_T_33 | _maxvl_T_37; // @[VInst.scala 230:59]
- wire _maxvl_T_40 = _maxvl_T_25 & getvlm_1; // @[VInst.scala 232:39]
- wire [7:0] _maxvl_T_41 = _maxvl_T_40 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_42 = _maxvl_T_38 | _maxvl_T_41; // @[VInst.scala 231:59]
- wire _maxvl_T_44 = _maxvl_T_29 & getvlm_1; // @[VInst.scala 233:39]
- wire [7:0] _maxvl_T_45 = _maxvl_T_44 ? 8'h40 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_46 = _maxvl_T_42 | _maxvl_T_45; // @[VInst.scala 232:60]
- wire _maxvl_T_48 = _maxvl_T_34 & getvlm_1; // @[VInst.scala 234:39]
- wire [7:0] _maxvl_T_49 = _maxvl_T_48 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] maxvl_1 = _maxvl_T_46 | _maxvl_T_49; // @[VInst.scala 233:60]
- wire rs2nonzero_1 = vinstInst_1[24:20] != 5'h0; // @[VInst.scala 236:42]
- wire [31:0] _GEN_58 = {{24'd0}, maxvl_1}; // @[VInst.scala 238:15]
- wire [31:0] _GEN_6 = io_rs_2_data < _GEN_58 ? io_rs_2_data : {{24'd0}, maxvl_1}; // @[VInst.scala 240:31 241:11 243:11]
- wire [31:0] _GEN_7 = io_rs_3_data < _GEN_58 & io_rs_3_data < io_rs_2_data & rs2nonzero_1 ? io_rs_3_data : _GEN_6; // @[VInst.scala 238:51 239:11]
- wire [1:0] getvlsz_2 = vinstInst_2[26:25]; // @[VInst.scala 227:31]
- wire getvlm_2 = vinstInst_2[27]; // @[VInst.scala 228:31]
- wire _maxvl_T_50 = getvlsz_2 == 2'h0; // @[VInst.scala 229:31]
- wire _maxvl_T_51 = ~getvlm_2; // @[VInst.scala 229:42]
- wire _maxvl_T_52 = getvlsz_2 == 2'h0 & ~getvlm_2; // @[VInst.scala 229:39]
- wire [7:0] _maxvl_T_53 = _maxvl_T_52 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire _maxvl_T_54 = getvlsz_2 == 2'h1; // @[VInst.scala 230:31]
- wire _maxvl_T_56 = getvlsz_2 == 2'h1 & _maxvl_T_51; // @[VInst.scala 230:39]
- wire [7:0] _maxvl_T_57 = _maxvl_T_56 ? 8'h10 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_58 = _maxvl_T_53 | _maxvl_T_57; // @[VInst.scala 229:59]
- wire _maxvl_T_59 = getvlsz_2 == 2'h2; // @[VInst.scala 231:31]
- wire _maxvl_T_61 = getvlsz_2 == 2'h2 & _maxvl_T_51; // @[VInst.scala 231:39]
- wire [7:0] _maxvl_T_62 = _maxvl_T_61 ? 8'h8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_63 = _maxvl_T_58 | _maxvl_T_62; // @[VInst.scala 230:59]
- wire _maxvl_T_65 = _maxvl_T_50 & getvlm_2; // @[VInst.scala 232:39]
- wire [7:0] _maxvl_T_66 = _maxvl_T_65 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_67 = _maxvl_T_63 | _maxvl_T_66; // @[VInst.scala 231:59]
- wire _maxvl_T_69 = _maxvl_T_54 & getvlm_2; // @[VInst.scala 233:39]
- wire [7:0] _maxvl_T_70 = _maxvl_T_69 ? 8'h40 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_71 = _maxvl_T_67 | _maxvl_T_70; // @[VInst.scala 232:60]
- wire _maxvl_T_73 = _maxvl_T_59 & getvlm_2; // @[VInst.scala 234:39]
- wire [7:0] _maxvl_T_74 = _maxvl_T_73 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] maxvl_2 = _maxvl_T_71 | _maxvl_T_74; // @[VInst.scala 233:60]
- wire rs2nonzero_2 = vinstInst_2[24:20] != 5'h0; // @[VInst.scala 236:42]
- wire [31:0] _GEN_60 = {{24'd0}, maxvl_2}; // @[VInst.scala 238:15]
- wire [31:0] _GEN_8 = io_rs_4_data < _GEN_60 ? io_rs_4_data : {{24'd0}, maxvl_2}; // @[VInst.scala 240:31 241:11 243:11]
- wire [31:0] _GEN_9 = io_rs_5_data < _GEN_60 & io_rs_5_data < io_rs_4_data & rs2nonzero_2 ? io_rs_5_data : _GEN_8; // @[VInst.scala 238:51 239:11]
- wire [1:0] getvlsz_3 = vinstInst_3[26:25]; // @[VInst.scala 227:31]
- wire getvlm_3 = vinstInst_3[27]; // @[VInst.scala 228:31]
- wire _maxvl_T_75 = getvlsz_3 == 2'h0; // @[VInst.scala 229:31]
- wire _maxvl_T_76 = ~getvlm_3; // @[VInst.scala 229:42]
- wire _maxvl_T_77 = getvlsz_3 == 2'h0 & ~getvlm_3; // @[VInst.scala 229:39]
- wire [7:0] _maxvl_T_78 = _maxvl_T_77 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire _maxvl_T_79 = getvlsz_3 == 2'h1; // @[VInst.scala 230:31]
- wire _maxvl_T_81 = getvlsz_3 == 2'h1 & _maxvl_T_76; // @[VInst.scala 230:39]
- wire [7:0] _maxvl_T_82 = _maxvl_T_81 ? 8'h10 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_83 = _maxvl_T_78 | _maxvl_T_82; // @[VInst.scala 229:59]
- wire _maxvl_T_84 = getvlsz_3 == 2'h2; // @[VInst.scala 231:31]
- wire _maxvl_T_86 = getvlsz_3 == 2'h2 & _maxvl_T_76; // @[VInst.scala 231:39]
- wire [7:0] _maxvl_T_87 = _maxvl_T_86 ? 8'h8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_88 = _maxvl_T_83 | _maxvl_T_87; // @[VInst.scala 230:59]
- wire _maxvl_T_90 = _maxvl_T_75 & getvlm_3; // @[VInst.scala 232:39]
- wire [7:0] _maxvl_T_91 = _maxvl_T_90 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_92 = _maxvl_T_88 | _maxvl_T_91; // @[VInst.scala 231:59]
- wire _maxvl_T_94 = _maxvl_T_79 & getvlm_3; // @[VInst.scala 233:39]
- wire [7:0] _maxvl_T_95 = _maxvl_T_94 ? 8'h40 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _maxvl_T_96 = _maxvl_T_92 | _maxvl_T_95; // @[VInst.scala 232:60]
- wire _maxvl_T_98 = _maxvl_T_84 & getvlm_3; // @[VInst.scala 234:39]
- wire [7:0] _maxvl_T_99 = _maxvl_T_98 ? 8'h20 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] maxvl_3 = _maxvl_T_96 | _maxvl_T_99; // @[VInst.scala 233:60]
- wire rs2nonzero_3 = vinstInst_3[24:20] != 5'h0; // @[VInst.scala 236:42]
- wire [31:0] _GEN_62 = {{24'd0}, maxvl_3}; // @[VInst.scala 238:15]
- wire [31:0] _GEN_10 = io_rs_6_data < _GEN_62 ? io_rs_6_data : {{24'd0}, maxvl_3}; // @[VInst.scala 240:31 241:11 243:11]
- wire [31:0] _GEN_11 = io_rs_7_data < _GEN_62 & io_rs_7_data < io_rs_6_data & rs2nonzero_3 ? io_rs_7_data : _GEN_10; // @[VInst.scala 238:51 239:11]
- wire [7:0] len = _GEN_5[7:0]; // @[VInst.scala 224:19]
- wire [7:0] _io_rd_0_data_T = getvl_0 ? len : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _io_rd_0_data_T_1 = getmaxvl_0 ? maxvl : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _io_rd_0_data_T_2 = _io_rd_0_data_T | _io_rd_0_data_T_1; // @[VInst.scala 255:40]
- wire _io_rd_0_data_T_4 = vld_u_0 | vst_u_0 | vst_q_0; // @[VInst.scala 257:36]
- wire [31:0] _io_rd_0_data_T_5 = _io_rd_0_data_T_4 ? lsuAdder_0 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _GEN_64 = {{24'd0}, _io_rd_0_data_T_2}; // @[VInst.scala 256:46]
- wire [7:0] len_1 = _GEN_7[7:0]; // @[VInst.scala 224:19]
- wire [7:0] _io_rd_1_data_T = getvl_1 ? len_1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _io_rd_1_data_T_1 = getmaxvl_1 ? maxvl_1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _io_rd_1_data_T_2 = _io_rd_1_data_T | _io_rd_1_data_T_1; // @[VInst.scala 255:40]
- wire _io_rd_1_data_T_4 = vld_u_1 | vst_u_1 | vst_q_1; // @[VInst.scala 257:36]
- wire [31:0] _io_rd_1_data_T_5 = _io_rd_1_data_T_4 ? lsuAdder_1 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _GEN_65 = {{24'd0}, _io_rd_1_data_T_2}; // @[VInst.scala 256:46]
- wire [7:0] len_2 = _GEN_9[7:0]; // @[VInst.scala 224:19]
- wire [7:0] _io_rd_2_data_T = getvl_2 ? len_2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _io_rd_2_data_T_1 = getmaxvl_2 ? maxvl_2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _io_rd_2_data_T_2 = _io_rd_2_data_T | _io_rd_2_data_T_1; // @[VInst.scala 255:40]
- wire _io_rd_2_data_T_4 = vld_u_2 | vst_u_2 | vst_q_2; // @[VInst.scala 257:36]
- wire [31:0] _io_rd_2_data_T_5 = _io_rd_2_data_T_4 ? lsuAdder_2 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _GEN_66 = {{24'd0}, _io_rd_2_data_T_2}; // @[VInst.scala 256:46]
- wire [7:0] len_3 = _GEN_11[7:0]; // @[VInst.scala 224:19]
- wire [7:0] _io_rd_3_data_T = getvl_3 ? len_3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _io_rd_3_data_T_1 = getmaxvl_3 ? maxvl_3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _io_rd_3_data_T_2 = _io_rd_3_data_T | _io_rd_3_data_T_1; // @[VInst.scala 255:40]
- wire _io_rd_3_data_T_4 = vld_u_3 | vst_u_3 | vst_q_3; // @[VInst.scala 257:36]
- wire [31:0] _io_rd_3_data_T_5 = _io_rd_3_data_T_4 ? lsuAdder_3 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _GEN_67 = {{24'd0}, _io_rd_3_data_T_2}; // @[VInst.scala 256:46]
- wire _T_108 = ~slice_io_in_ready; // @[VInst.scala 268:33]
- reg nempty; // @[VInst.scala 290:23]
- wire _nempty_T_2 = io_in_0_valid | io_in_1_valid | io_in_2_valid | io_in_3_valid; // @[VInst.scala 293:64]
- Slice_3 slice ( // @[Slice.scala 23:11]
- .clock(slice_clock),
- .reset(slice_reset),
- .io_in_ready(slice_io_in_ready),
- .io_in_valid(slice_io_in_valid),
- .io_in_bits_0_lane_valid(slice_io_in_bits_0_lane_valid),
- .io_in_bits_0_lane_bits_inst(slice_io_in_bits_0_lane_bits_inst),
- .io_in_bits_0_lane_bits_addr(slice_io_in_bits_0_lane_bits_addr),
- .io_in_bits_0_lane_bits_data(slice_io_in_bits_0_lane_bits_data),
- .io_in_bits_1_lane_valid(slice_io_in_bits_1_lane_valid),
- .io_in_bits_1_lane_bits_inst(slice_io_in_bits_1_lane_bits_inst),
- .io_in_bits_1_lane_bits_addr(slice_io_in_bits_1_lane_bits_addr),
- .io_in_bits_1_lane_bits_data(slice_io_in_bits_1_lane_bits_data),
- .io_in_bits_2_lane_valid(slice_io_in_bits_2_lane_valid),
- .io_in_bits_2_lane_bits_inst(slice_io_in_bits_2_lane_bits_inst),
- .io_in_bits_2_lane_bits_addr(slice_io_in_bits_2_lane_bits_addr),
- .io_in_bits_2_lane_bits_data(slice_io_in_bits_2_lane_bits_data),
- .io_in_bits_3_lane_valid(slice_io_in_bits_3_lane_valid),
- .io_in_bits_3_lane_bits_inst(slice_io_in_bits_3_lane_bits_inst),
- .io_in_bits_3_lane_bits_addr(slice_io_in_bits_3_lane_bits_addr),
- .io_in_bits_3_lane_bits_data(slice_io_in_bits_3_lane_bits_data),
- .io_out_ready(slice_io_out_ready),
- .io_out_valid(slice_io_out_valid),
- .io_out_bits_0_lane_valid(slice_io_out_bits_0_lane_valid),
- .io_out_bits_0_lane_bits_inst(slice_io_out_bits_0_lane_bits_inst),
- .io_out_bits_0_lane_bits_addr(slice_io_out_bits_0_lane_bits_addr),
- .io_out_bits_0_lane_bits_data(slice_io_out_bits_0_lane_bits_data),
- .io_out_bits_1_lane_valid(slice_io_out_bits_1_lane_valid),
- .io_out_bits_1_lane_bits_inst(slice_io_out_bits_1_lane_bits_inst),
- .io_out_bits_1_lane_bits_addr(slice_io_out_bits_1_lane_bits_addr),
- .io_out_bits_1_lane_bits_data(slice_io_out_bits_1_lane_bits_data),
- .io_out_bits_2_lane_valid(slice_io_out_bits_2_lane_valid),
- .io_out_bits_2_lane_bits_inst(slice_io_out_bits_2_lane_bits_inst),
- .io_out_bits_2_lane_bits_addr(slice_io_out_bits_2_lane_bits_addr),
- .io_out_bits_2_lane_bits_data(slice_io_out_bits_2_lane_bits_data),
- .io_out_bits_3_lane_valid(slice_io_out_bits_3_lane_valid),
- .io_out_bits_3_lane_bits_inst(slice_io_out_bits_3_lane_bits_inst),
- .io_out_bits_3_lane_bits_addr(slice_io_out_bits_3_lane_bits_addr),
- .io_out_bits_3_lane_bits_data(slice_io_out_bits_3_lane_bits_data)
- );
- assign io_in_0_ready = ~io_out_stall; // @[VInst.scala 113:23]
- assign io_in_1_ready = ~io_out_stall; // @[VInst.scala 113:23]
- assign io_in_2_ready = ~io_out_stall; // @[VInst.scala 113:23]
- assign io_in_3_ready = ~io_out_stall; // @[VInst.scala 113:23]
- assign io_rd_0_valid = getvl_0 | getmaxvl_0 | vld_u_0 | vst_u_0 | vst_q_0; // @[VInst.scala 251:71]
- assign io_rd_0_addr = rdAddr_0; // @[VInst.scala 252:19]
- assign io_rd_0_data = _GEN_64 | _io_rd_0_data_T_5; // @[VInst.scala 256:46]
- assign io_rd_1_valid = getvl_1 | getmaxvl_1 | vld_u_1 | vst_u_1 | vst_q_1; // @[VInst.scala 251:71]
- assign io_rd_1_addr = rdAddr_1; // @[VInst.scala 252:19]
- assign io_rd_1_data = _GEN_65 | _io_rd_1_data_T_5; // @[VInst.scala 256:46]
- assign io_rd_2_valid = getvl_2 | getmaxvl_2 | vld_u_2 | vst_u_2 | vst_q_2; // @[VInst.scala 251:71]
- assign io_rd_2_addr = rdAddr_2; // @[VInst.scala 252:19]
- assign io_rd_2_data = _GEN_66 | _io_rd_2_data_T_5; // @[VInst.scala 256:46]
- assign io_rd_3_valid = getvl_3 | getmaxvl_3 | vld_u_3 | vst_u_3 | vst_q_3; // @[VInst.scala 251:71]
- assign io_rd_3_addr = rdAddr_3; // @[VInst.scala 252:19]
- assign io_rd_3_data = _GEN_67 | _io_rd_3_data_T_5; // @[VInst.scala 256:46]
- assign io_out_valid = slice_io_out_valid; // @[VInst.scala 264:16]
- assign io_out_lane_0_valid = slice_io_out_bits_0_lane_valid; // @[VInst.scala 280:20]
- assign io_out_lane_0_bits_inst = slice_io_out_bits_0_lane_bits_inst; // @[VInst.scala 280:20]
- assign io_out_lane_0_bits_addr = slice_io_out_bits_0_lane_bits_addr; // @[VInst.scala 280:20]
- assign io_out_lane_0_bits_data = slice_io_out_bits_0_lane_bits_data; // @[VInst.scala 280:20]
- assign io_out_lane_1_valid = slice_io_out_bits_1_lane_valid; // @[VInst.scala 280:20]
- assign io_out_lane_1_bits_inst = slice_io_out_bits_1_lane_bits_inst; // @[VInst.scala 280:20]
- assign io_out_lane_1_bits_addr = slice_io_out_bits_1_lane_bits_addr; // @[VInst.scala 280:20]
- assign io_out_lane_1_bits_data = slice_io_out_bits_1_lane_bits_data; // @[VInst.scala 280:20]
- assign io_out_lane_2_valid = slice_io_out_bits_2_lane_valid; // @[VInst.scala 280:20]
- assign io_out_lane_2_bits_inst = slice_io_out_bits_2_lane_bits_inst; // @[VInst.scala 280:20]
- assign io_out_lane_2_bits_addr = slice_io_out_bits_2_lane_bits_addr; // @[VInst.scala 280:20]
- assign io_out_lane_2_bits_data = slice_io_out_bits_2_lane_bits_data; // @[VInst.scala 280:20]
- assign io_out_lane_3_valid = slice_io_out_bits_3_lane_valid; // @[VInst.scala 280:20]
- assign io_out_lane_3_bits_inst = slice_io_out_bits_3_lane_bits_inst; // @[VInst.scala 280:20]
- assign io_out_lane_3_bits_addr = slice_io_out_bits_3_lane_bits_addr; // @[VInst.scala 280:20]
- assign io_out_lane_3_bits_data = slice_io_out_bits_3_lane_bits_data; // @[VInst.scala 280:20]
- assign io_nempty = nempty; // @[VInst.scala 296:13]
- assign slice_clock = clock;
- assign slice_reset = reset;
- assign slice_io_in_valid = vvalid; // @[VInst.scala 262:21]
- assign slice_io_in_bits_0_lane_valid = vinstValid_0; // @[VInst.scala 273:36]
- assign slice_io_in_bits_0_lane_bits_inst = vinstInst_0; // @[VInst.scala 274:40]
- assign slice_io_in_bits_0_lane_bits_addr = io_rs_0_data; // @[VInst.scala 275:40]
- assign slice_io_in_bits_0_lane_bits_data = io_rs_1_data; // @[VInst.scala 276:40]
- assign slice_io_in_bits_1_lane_valid = vinstValid_1; // @[VInst.scala 273:36]
- assign slice_io_in_bits_1_lane_bits_inst = vinstInst_1; // @[VInst.scala 274:40]
- assign slice_io_in_bits_1_lane_bits_addr = io_rs_2_data; // @[VInst.scala 275:40]
- assign slice_io_in_bits_1_lane_bits_data = io_rs_3_data; // @[VInst.scala 276:40]
- assign slice_io_in_bits_2_lane_valid = vinstValid_2; // @[VInst.scala 273:36]
- assign slice_io_in_bits_2_lane_bits_inst = vinstInst_2; // @[VInst.scala 274:40]
- assign slice_io_in_bits_2_lane_bits_addr = io_rs_4_data; // @[VInst.scala 275:40]
- assign slice_io_in_bits_2_lane_bits_data = io_rs_5_data; // @[VInst.scala 276:40]
- assign slice_io_in_bits_3_lane_valid = vinstValid_3; // @[VInst.scala 273:36]
- assign slice_io_in_bits_3_lane_bits_inst = vinstInst_3; // @[VInst.scala 274:40]
- assign slice_io_in_bits_3_lane_bits_addr = io_rs_6_data; // @[VInst.scala 275:40]
- assign slice_io_in_bits_3_lane_bits_data = io_rs_7_data; // @[VInst.scala 276:40]
- assign slice_io_out_ready = io_out_ready; // @[VInst.scala 263:22]
- always @(posedge clock) begin
- if (reqvalid_0) begin // @[VInst.scala 129:24]
- rdAddr_0 <= io_in_0_addr; // @[VInst.scala 130:17]
- end
- if (reqvalid_1) begin // @[VInst.scala 129:24]
- rdAddr_1 <= io_in_1_addr; // @[VInst.scala 130:17]
- end
- if (reqvalid_2) begin // @[VInst.scala 129:24]
- rdAddr_2 <= io_in_2_addr; // @[VInst.scala 130:17]
- end
- if (reqvalid_3) begin // @[VInst.scala 129:24]
- rdAddr_3 <= io_in_3_addr; // @[VInst.scala 130:17]
- end
- vinstInst_0 <= io_in_0_inst; // @[VInst.scala 148:18]
- vinstInst_1 <= io_in_1_inst; // @[VInst.scala 148:18]
- vinstInst_2 <= io_in_2_inst; // @[VInst.scala 148:18]
- vinstInst_3 <= io_in_3_inst; // @[VInst.scala 148:18]
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_T_19 <= 3'h1)) begin
- $fatal; // @[VInst.scala 210:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_T_19 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VInst.scala:210 assert(PopCount(Cat(p_x, p_xx, lp_xx, sp_xx, qp_xx, tp_xx)) <= 1.U)\n"
- ); // @[VInst.scala 210:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_T_40 <= 3'h1)) begin
- $fatal; // @[VInst.scala 210:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_T_40 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VInst.scala:210 assert(PopCount(Cat(p_x, p_xx, lp_xx, sp_xx, qp_xx, tp_xx)) <= 1.U)\n"
- ); // @[VInst.scala 210:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_T_61 <= 3'h1)) begin
- $fatal; // @[VInst.scala 210:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_T_61 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VInst.scala:210 assert(PopCount(Cat(p_x, p_xx, lp_xx, sp_xx, qp_xx, tp_xx)) <= 1.U)\n"
- ); // @[VInst.scala 210:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_T_82 <= 3'h1)) begin
- $fatal; // @[VInst.scala 210:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_T_82 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VInst.scala:210 assert(PopCount(Cat(p_x, p_xx, lp_xx, sp_xx, qp_xx, tp_xx)) <= 1.U)\n"
- ); // @[VInst.scala 210:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(slice_io_in_valid & ~slice_io_in_ready))) begin
- $fatal; // @[VInst.scala 268:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(slice_io_in_valid & ~slice_io_in_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VInst.scala:268 assert(!(slice.io.in.valid && !slice.io.in.ready))\n"); // @[VInst.scala 268:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(vvalid & _T_108))) begin
- $fatal; // @[VInst.scala 286:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(vvalid & _T_108))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VInst.scala:286 assert(!(vvalid && !slice.io.in.ready))\n"); // @[VInst.scala 286:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 155:55]
- vld_u_0 <= 1'h0;
- end else begin
- vld_u_0 <= _vld_o_0_T_1 & p;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 155:55]
- vld_u_1 <= 1'h0;
- end else begin
- vld_u_1 <= _vld_o_1_T_1 & p_1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 155:55]
- vld_u_2 <= 1'h0;
- end else begin
- vld_u_2 <= _vld_o_2_T_1 & p_2;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 155:55]
- vld_u_3 <= 1'h0;
- end else begin
- vld_u_3 <= _vld_o_3_T_1 & p_3;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 157:61]
- vst_u_0 <= 1'h0;
- end else begin
- vst_u_0 <= _vst_o_0_T_1 & p & ~q;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 157:61]
- vst_u_1 <= 1'h0;
- end else begin
- vst_u_1 <= _vst_o_1_T_1 & p_1 & ~q_1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 157:61]
- vst_u_2 <= 1'h0;
- end else begin
- vst_u_2 <= _vst_o_2_T_1 & p_2 & ~q_2;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 157:61]
- vst_u_3 <= 1'h0;
- end else begin
- vst_u_3 <= _vst_o_3_T_1 & p_3 & ~q_3;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 158:61]
- vst_q_0 <= 1'h0;
- end else begin
- vst_q_0 <= _vst_u_0_T_2 & q;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 158:61]
- vst_q_1 <= 1'h0;
- end else begin
- vst_q_1 <= _vst_u_1_T_2 & q_1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 158:61]
- vst_q_2 <= 1'h0;
- end else begin
- vst_q_2 <= _vst_u_2_T_2 & q_2;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 158:61]
- vst_q_3 <= 1'h0;
- end else begin
- vst_q_3 <= _vst_u_3_T_2 & q_3;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 159:29]
- getvl_0 <= 1'h0;
- end else begin
- getvl_0 <= reqvalid_0 & io_in_0_op[0];
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 159:29]
- getvl_1 <= 1'h0;
- end else begin
- getvl_1 <= reqvalid_1 & io_in_1_op[0];
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 159:29]
- getvl_2 <= 1'h0;
- end else begin
- getvl_2 <= reqvalid_2 & io_in_2_op[0];
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 159:29]
- getvl_3 <= 1'h0;
- end else begin
- getvl_3 <= reqvalid_3 & io_in_3_op[0];
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 160:32]
- getmaxvl_0 <= 1'h0;
- end else begin
- getmaxvl_0 <= reqvalid_0 & io_in_0_op[1];
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 160:32]
- getmaxvl_1 <= 1'h0;
- end else begin
- getmaxvl_1 <= reqvalid_1 & io_in_1_op[1];
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 160:32]
- getmaxvl_2 <= 1'h0;
- end else begin
- getmaxvl_2 <= reqvalid_2 & io_in_2_op[1];
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 160:32]
- getmaxvl_3 <= 1'h0;
- end else begin
- getmaxvl_3 <= reqvalid_3 & io_in_3_op[1];
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 141:34]
- vvalid <= 1'h0;
- end else begin
- vvalid <= _vvalid_T != 4'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 144:37]
- vinstValid_0 <= 1'h0;
- end else begin
- vinstValid_0 <= reqvalid_0 & _nxtVinstValid_0_T_4;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 144:37]
- vinstValid_1 <= 1'h0;
- end else begin
- vinstValid_1 <= reqvalid_1 & _nxtVinstValid_1_T_4;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 144:37]
- vinstValid_2 <= 1'h0;
- end else begin
- vinstValid_2 <= reqvalid_2 & _nxtVinstValid_2_T_4;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 144:37]
- vinstValid_3 <= 1'h0;
- end else begin
- vinstValid_3 <= reqvalid_3 & _nxtVinstValid_3_T_4;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VInst.scala 294:38]
- nempty <= 1'h0;
- end else begin
- nempty <= _nempty_T_2 | vvalid | io_out_valid;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- vld_u_0 = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- vld_u_1 = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- vld_u_2 = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- vld_u_3 = _RAND_3[0:0];
- _RAND_4 = {1{`RANDOM}};
- vst_u_0 = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- vst_u_1 = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- vst_u_2 = _RAND_6[0:0];
- _RAND_7 = {1{`RANDOM}};
- vst_u_3 = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- vst_q_0 = _RAND_8[0:0];
- _RAND_9 = {1{`RANDOM}};
- vst_q_1 = _RAND_9[0:0];
- _RAND_10 = {1{`RANDOM}};
- vst_q_2 = _RAND_10[0:0];
- _RAND_11 = {1{`RANDOM}};
- vst_q_3 = _RAND_11[0:0];
- _RAND_12 = {1{`RANDOM}};
- getvl_0 = _RAND_12[0:0];
- _RAND_13 = {1{`RANDOM}};
- getvl_1 = _RAND_13[0:0];
- _RAND_14 = {1{`RANDOM}};
- getvl_2 = _RAND_14[0:0];
- _RAND_15 = {1{`RANDOM}};
- getvl_3 = _RAND_15[0:0];
- _RAND_16 = {1{`RANDOM}};
- getmaxvl_0 = _RAND_16[0:0];
- _RAND_17 = {1{`RANDOM}};
- getmaxvl_1 = _RAND_17[0:0];
- _RAND_18 = {1{`RANDOM}};
- getmaxvl_2 = _RAND_18[0:0];
- _RAND_19 = {1{`RANDOM}};
- getmaxvl_3 = _RAND_19[0:0];
- _RAND_20 = {1{`RANDOM}};
- rdAddr_0 = _RAND_20[4:0];
- _RAND_21 = {1{`RANDOM}};
- rdAddr_1 = _RAND_21[4:0];
- _RAND_22 = {1{`RANDOM}};
- rdAddr_2 = _RAND_22[4:0];
- _RAND_23 = {1{`RANDOM}};
- rdAddr_3 = _RAND_23[4:0];
- _RAND_24 = {1{`RANDOM}};
- vvalid = _RAND_24[0:0];
- _RAND_25 = {1{`RANDOM}};
- vinstValid_0 = _RAND_25[0:0];
- _RAND_26 = {1{`RANDOM}};
- vinstValid_1 = _RAND_26[0:0];
- _RAND_27 = {1{`RANDOM}};
- vinstValid_2 = _RAND_27[0:0];
- _RAND_28 = {1{`RANDOM}};
- vinstValid_3 = _RAND_28[0:0];
- _RAND_29 = {1{`RANDOM}};
- vinstInst_0 = _RAND_29[31:0];
- _RAND_30 = {1{`RANDOM}};
- vinstInst_1 = _RAND_30[31:0];
- _RAND_31 = {1{`RANDOM}};
- vinstInst_2 = _RAND_31[31:0];
- _RAND_32 = {1{`RANDOM}};
- vinstInst_3 = _RAND_32[31:0];
- _RAND_33 = {1{`RANDOM}};
- nempty = _RAND_33[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- vld_u_0 = 1'h0;
- end
- if (reset) begin
- vld_u_1 = 1'h0;
- end
- if (reset) begin
- vld_u_2 = 1'h0;
- end
- if (reset) begin
- vld_u_3 = 1'h0;
- end
- if (reset) begin
- vst_u_0 = 1'h0;
- end
- if (reset) begin
- vst_u_1 = 1'h0;
- end
- if (reset) begin
- vst_u_2 = 1'h0;
- end
- if (reset) begin
- vst_u_3 = 1'h0;
- end
- if (reset) begin
- vst_q_0 = 1'h0;
- end
- if (reset) begin
- vst_q_1 = 1'h0;
- end
- if (reset) begin
- vst_q_2 = 1'h0;
- end
- if (reset) begin
- vst_q_3 = 1'h0;
- end
- if (reset) begin
- getvl_0 = 1'h0;
- end
- if (reset) begin
- getvl_1 = 1'h0;
- end
- if (reset) begin
- getvl_2 = 1'h0;
- end
- if (reset) begin
- getvl_3 = 1'h0;
- end
- if (reset) begin
- getmaxvl_0 = 1'h0;
- end
- if (reset) begin
- getmaxvl_1 = 1'h0;
- end
- if (reset) begin
- getmaxvl_2 = 1'h0;
- end
- if (reset) begin
- getmaxvl_3 = 1'h0;
- end
- if (reset) begin
- vvalid = 1'h0;
- end
- if (reset) begin
- vinstValid_0 = 1'h0;
- end
- if (reset) begin
- vinstValid_1 = 1'h0;
- end
- if (reset) begin
- vinstValid_2 = 1'h0;
- end
- if (reset) begin
- vinstValid_3 = 1'h0;
- end
- if (reset) begin
- nempty = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Fifo4x4(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [31:0] io_in_bits_0_bits_inst,
- input [31:0] io_in_bits_0_bits_addr,
- input [31:0] io_in_bits_0_bits_data,
- input io_in_bits_1_valid,
- input [31:0] io_in_bits_1_bits_inst,
- input [31:0] io_in_bits_1_bits_addr,
- input [31:0] io_in_bits_1_bits_data,
- input io_in_bits_2_valid,
- input [31:0] io_in_bits_2_bits_inst,
- input [31:0] io_in_bits_2_bits_addr,
- input [31:0] io_in_bits_2_bits_data,
- input io_in_bits_3_valid,
- input [31:0] io_in_bits_3_bits_inst,
- input [31:0] io_in_bits_3_bits_addr,
- input [31:0] io_in_bits_3_bits_data,
- input io_out_0_ready,
- output io_out_0_valid,
- output [31:0] io_out_0_bits_inst,
- output [31:0] io_out_0_bits_addr,
- output [31:0] io_out_0_bits_data,
- input io_out_1_ready,
- output io_out_1_valid,
- output [31:0] io_out_1_bits_inst,
- output [31:0] io_out_1_bits_addr,
- output [31:0] io_out_1_bits_data,
- input io_out_2_ready,
- output io_out_2_valid,
- output [31:0] io_out_2_bits_inst,
- output [31:0] io_out_2_bits_addr,
- output [31:0] io_out_2_bits_data,
- input io_out_3_ready,
- output io_out_3_valid,
- output [31:0] io_out_3_bits_inst,
- output [31:0] io_out_3_bits_addr,
- output [31:0] io_out_3_bits_data,
- output [4:0] io_count,
- output io_nempty
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
- reg [31:0] _RAND_34;
- reg [31:0] _RAND_35;
- reg [31:0] _RAND_36;
- reg [31:0] _RAND_37;
- reg [31:0] _RAND_38;
- reg [31:0] _RAND_39;
- reg [31:0] _RAND_40;
- reg [31:0] _RAND_41;
- reg [31:0] _RAND_42;
- reg [31:0] _RAND_43;
- reg [31:0] _RAND_44;
- reg [31:0] _RAND_45;
- reg [31:0] _RAND_46;
- reg [31:0] _RAND_47;
- reg [31:0] _RAND_48;
- reg [31:0] _RAND_49;
- reg [31:0] _RAND_50;
- reg [31:0] _RAND_51;
- reg [31:0] _RAND_52;
- reg [31:0] _RAND_53;
- reg [31:0] _RAND_54;
- reg [31:0] _RAND_55;
- reg [31:0] _RAND_56;
- reg [31:0] _RAND_57;
- reg [31:0] _RAND_58;
- reg [31:0] _RAND_59;
- reg [31:0] _RAND_60;
- reg [31:0] _RAND_61;
- reg [31:0] _RAND_62;
- reg [31:0] _RAND_63;
- reg [31:0] _RAND_64;
- reg [31:0] _RAND_65;
- reg [31:0] _RAND_66;
- reg [31:0] _RAND_67;
- reg [31:0] _RAND_68;
- reg [31:0] _RAND_69;
- reg [31:0] _RAND_70;
- reg [31:0] _RAND_71;
- reg [31:0] _RAND_72;
- reg [31:0] _RAND_73;
- reg [31:0] _RAND_74;
- reg [31:0] _RAND_75;
- reg [31:0] _RAND_76;
- reg [31:0] _RAND_77;
- reg [31:0] _RAND_78;
- reg [31:0] _RAND_79;
- reg [31:0] _RAND_80;
- reg [31:0] _RAND_81;
- reg [31:0] _RAND_82;
- reg [31:0] _RAND_83;
-`endif // RANDOMIZE_REG_INIT
- reg [31:0] mem_0_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_0_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_0_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_1_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_1_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_1_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_2_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_2_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_2_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_3_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_3_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_3_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_4_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_4_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_4_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_5_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_5_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_5_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_6_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_6_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_6_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_7_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_7_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_7_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_8_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_8_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_8_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_9_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_9_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_9_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_10_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_10_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_10_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_11_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_11_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_11_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_12_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_12_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_12_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_13_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_13_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_13_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_14_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_14_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_14_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_15_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_15_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_15_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_16_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_16_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_16_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_17_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_17_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_17_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_18_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_18_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_18_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_19_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_19_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_19_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_20_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_20_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_20_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_21_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_21_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_21_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_22_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_22_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_22_data; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_23_inst; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_23_addr; // @[Fifo4x4.scala 48:16]
- reg [31:0] mem_23_data; // @[Fifo4x4.scala 48:16]
- reg [4:0] inpos_0; // @[Fifo4x4.scala 50:19]
- reg [4:0] inpos_1; // @[Fifo4x4.scala 50:19]
- reg [4:0] inpos_2; // @[Fifo4x4.scala 50:19]
- reg [4:0] inpos_3; // @[Fifo4x4.scala 50:19]
- reg [4:0] outpos_0; // @[Fifo4x4.scala 51:19]
- reg [4:0] outpos_1; // @[Fifo4x4.scala 51:19]
- reg [4:0] outpos_2; // @[Fifo4x4.scala 51:19]
- reg [4:0] outpos_3; // @[Fifo4x4.scala 51:19]
- reg [4:0] mcount; // @[Fifo4x4.scala 53:23]
- reg nempty; // @[Fifo4x4.scala 54:23]
- reg inready; // @[Fifo4x4.scala 55:24]
- reg [3:0] outvalid; // @[Fifo4x4.scala 56:25]
- wire ivalid = io_in_valid & io_in_ready; // @[Fifo4x4.scala 58:28]
- wire [3:0] iactive = {io_in_bits_3_valid,io_in_bits_2_valid,io_in_bits_1_valid,io_in_bits_0_valid}; // @[Cat.scala 31:58]
- wire [1:0] _icount_T = io_in_bits_0_valid + io_in_bits_1_valid; // @[Fifo4x4.scala 63:37]
- wire [1:0] _GEN_380 = {{1'd0}, io_in_bits_2_valid}; // @[Fifo4x4.scala 63:60]
- wire [2:0] _icount_T_1 = _icount_T + _GEN_380; // @[Fifo4x4.scala 63:60]
- wire [2:0] _GEN_381 = {{2'd0}, io_in_bits_3_valid}; // @[Fifo4x4.scala 64:37]
- wire [3:0] _icount_T_2 = _icount_T_1 + _GEN_381; // @[Fifo4x4.scala 64:37]
- wire [2:0] icount = _icount_T_2[2:0]; // @[Fifo4x4.scala 64:60]
- wire _oactiveBits_T = io_out_3_valid & io_out_3_ready; // @[Fifo4x4.scala 66:41]
- wire _oactiveBits_T_1 = io_out_2_valid & io_out_2_ready; // @[Fifo4x4.scala 67:41]
- wire _oactiveBits_T_2 = io_out_1_valid & io_out_1_ready; // @[Fifo4x4.scala 68:41]
- wire _oactiveBits_T_3 = io_out_0_valid & io_out_0_ready; // @[Fifo4x4.scala 69:41]
- wire [3:0] oactiveBits = {_oactiveBits_T,_oactiveBits_T_1,_oactiveBits_T_2,_oactiveBits_T_3}; // @[Cat.scala 31:58]
- wire ovalid = oactiveBits != 4'h0; // @[Fifo4x4.scala 71:28]
- wire [1:0] _ocount_T_2 = oactiveBits[0] + oactiveBits[1]; // @[Fifo4x4.scala 73:32]
- wire [1:0] _GEN_382 = {{1'd0}, oactiveBits[2]}; // @[Fifo4x4.scala 73:50]
- wire [2:0] _ocount_T_4 = _ocount_T_2 + _GEN_382; // @[Fifo4x4.scala 73:50]
- wire [2:0] _GEN_383 = {{2'd0}, oactiveBits[3]}; // @[Fifo4x4.scala 74:32]
- wire [3:0] _ocount_T_6 = _ocount_T_4 + _GEN_383; // @[Fifo4x4.scala 74:32]
- wire [2:0] ocount = _ocount_T_6[2:0]; // @[Fifo4x4.scala 74:50]
- wire _T_7 = ~reset; // @[Fifo4x4.scala 76:9]
- wire [3:0] ovalidBits = {io_out_3_valid,io_out_2_valid,io_out_1_valid,io_out_0_valid}; // @[Cat.scala 31:58]
- wire [3:0] oreadyBits = {io_out_3_ready,io_out_2_ready,io_out_1_ready,io_out_0_ready}; // @[Cat.scala 31:58]
- wire [4:0] _GEN_384 = {{2'd0}, icount}; // @[Fifo4x4.scala 43:15]
- wire [5:0] inpos_0_c = inpos_0 + _GEN_384; // @[Fifo4x4.scala 43:15]
- wire [5:0] _inpos_0_d_T_2 = inpos_0_c - 6'h18; // @[Fifo4x4.scala 44:31]
- wire [5:0] _inpos_0_d_T_3 = inpos_0_c < 6'h18 ? inpos_0_c : _inpos_0_d_T_2; // @[Fifo4x4.scala 44:16]
- wire [4:0] inpos_0_d = _inpos_0_d_T_3[4:0]; // @[Fifo4x4.scala 44:37]
- wire [5:0] inpos_1_c = inpos_1 + _GEN_384; // @[Fifo4x4.scala 43:15]
- wire [5:0] _inpos_1_d_T_2 = inpos_1_c - 6'h18; // @[Fifo4x4.scala 44:31]
- wire [5:0] _inpos_1_d_T_3 = inpos_1_c < 6'h18 ? inpos_1_c : _inpos_1_d_T_2; // @[Fifo4x4.scala 44:16]
- wire [4:0] inpos_1_d = _inpos_1_d_T_3[4:0]; // @[Fifo4x4.scala 44:37]
- wire [5:0] inpos_2_c = inpos_2 + _GEN_384; // @[Fifo4x4.scala 43:15]
- wire [5:0] _inpos_2_d_T_2 = inpos_2_c - 6'h18; // @[Fifo4x4.scala 44:31]
- wire [5:0] _inpos_2_d_T_3 = inpos_2_c < 6'h18 ? inpos_2_c : _inpos_2_d_T_2; // @[Fifo4x4.scala 44:16]
- wire [4:0] inpos_2_d = _inpos_2_d_T_3[4:0]; // @[Fifo4x4.scala 44:37]
- wire [5:0] inpos_3_c = inpos_3 + _GEN_384; // @[Fifo4x4.scala 43:15]
- wire [5:0] _inpos_3_d_T_2 = inpos_3_c - 6'h18; // @[Fifo4x4.scala 44:31]
- wire [5:0] _inpos_3_d_T_3 = inpos_3_c < 6'h18 ? inpos_3_c : _inpos_3_d_T_2; // @[Fifo4x4.scala 44:16]
- wire [4:0] inpos_3_d = _inpos_3_d_T_3[4:0]; // @[Fifo4x4.scala 44:37]
- wire [4:0] _GEN_388 = {{2'd0}, ocount}; // @[Fifo4x4.scala 43:15]
- wire [5:0] outpos_0_c = outpos_0 + _GEN_388; // @[Fifo4x4.scala 43:15]
- wire [5:0] _outpos_0_d_T_2 = outpos_0_c - 6'h18; // @[Fifo4x4.scala 44:31]
- wire [5:0] _outpos_0_d_T_3 = outpos_0_c < 6'h18 ? outpos_0_c : _outpos_0_d_T_2; // @[Fifo4x4.scala 44:16]
- wire [4:0] outpos_0_d = _outpos_0_d_T_3[4:0]; // @[Fifo4x4.scala 44:37]
- wire [5:0] outpos_1_c = outpos_1 + _GEN_388; // @[Fifo4x4.scala 43:15]
- wire [5:0] _outpos_1_d_T_2 = outpos_1_c - 6'h18; // @[Fifo4x4.scala 44:31]
- wire [5:0] _outpos_1_d_T_3 = outpos_1_c < 6'h18 ? outpos_1_c : _outpos_1_d_T_2; // @[Fifo4x4.scala 44:16]
- wire [4:0] outpos_1_d = _outpos_1_d_T_3[4:0]; // @[Fifo4x4.scala 44:37]
- wire [5:0] outpos_2_c = outpos_2 + _GEN_388; // @[Fifo4x4.scala 43:15]
- wire [5:0] _outpos_2_d_T_2 = outpos_2_c - 6'h18; // @[Fifo4x4.scala 44:31]
- wire [5:0] _outpos_2_d_T_3 = outpos_2_c < 6'h18 ? outpos_2_c : _outpos_2_d_T_2; // @[Fifo4x4.scala 44:16]
- wire [4:0] outpos_2_d = _outpos_2_d_T_3[4:0]; // @[Fifo4x4.scala 44:37]
- wire [5:0] outpos_3_c = outpos_3 + _GEN_388; // @[Fifo4x4.scala 43:15]
- wire [5:0] _outpos_3_d_T_2 = outpos_3_c - 6'h18; // @[Fifo4x4.scala 44:31]
- wire [5:0] _outpos_3_d_T_3 = outpos_3_c < 6'h18 ? outpos_3_c : _outpos_3_d_T_2; // @[Fifo4x4.scala 44:16]
- wire [4:0] outpos_3_d = _outpos_3_d_T_3[4:0]; // @[Fifo4x4.scala 44:37]
- wire [2:0] inc = ivalid ? icount : 3'h0; // @[Library.scala 22:8]
- wire [2:0] dec = ovalid ? ocount : 3'h0; // @[Library.scala 22:8]
- wire [4:0] _GEN_392 = {{2'd0}, inc}; // @[Fifo4x4.scala 120:28]
- wire [4:0] _nxtmcount_T_1 = mcount + _GEN_392; // @[Fifo4x4.scala 120:28]
- wire [4:0] _GEN_393 = {{2'd0}, dec}; // @[Fifo4x4.scala 120:34]
- wire [4:0] nxtmcount = _nxtmcount_T_1 - _GEN_393; // @[Fifo4x4.scala 120:34]
- wire [4:0] _inready_T_1 = 5'h18 - 5'h4; // @[Fifo4x4.scala 121:34]
- wire _outvalid_T = nxtmcount >= 5'h4; // @[Fifo4x4.scala 124:31]
- wire _outvalid_T_1 = nxtmcount >= 5'h3; // @[Fifo4x4.scala 125:31]
- wire _outvalid_T_2 = nxtmcount >= 5'h2; // @[Fifo4x4.scala 126:31]
- wire _outvalid_T_3 = nxtmcount >= 5'h1; // @[Fifo4x4.scala 127:31]
- wire [3:0] _outvalid_T_4 = {_outvalid_T,_outvalid_T_1,_outvalid_T_2,_outvalid_T_3}; // @[Cat.scala 31:58]
- wire _outvalid_T_5 = mcount >= 5'h4; // @[Fifo4x4.scala 130:28]
- wire _outvalid_T_6 = mcount >= 5'h3; // @[Fifo4x4.scala 131:28]
- wire _outvalid_T_7 = mcount >= 5'h2; // @[Fifo4x4.scala 132:28]
- wire _outvalid_T_8 = mcount >= 5'h1; // @[Fifo4x4.scala 133:28]
- wire [3:0] _outvalid_T_9 = {_outvalid_T_5,_outvalid_T_6,_outvalid_T_7,_outvalid_T_8}; // @[Cat.scala 31:58]
- wire _in0_T_1 = iactive == 4'h8; // @[Fifo4.scala 31:27]
- wire _in0_T_3 = iactive[2:0] == 3'h4; // @[Fifo4.scala 32:27]
- wire _in0_T_5 = iactive[1:0] == 2'h2; // @[Fifo4.scala 33:27]
- wire [3:0] in0valid = {_in0_T_1,_in0_T_3,_in0_T_5,iactive[0]}; // @[Cat.scala 31:58]
- wire _in1_T_3 = iactive == 4'ha; // @[Fifo4.scala 37:27]
- wire _in1_T_4 = iactive == 4'hc | _in1_T_3; // @[Fifo4.scala 36:36]
- wire _in1_T_6 = iactive == 4'h9; // @[Fifo4.scala 38:27]
- wire _in1_T_7 = _in1_T_4 | _in1_T_6; // @[Fifo4.scala 37:36]
- wire _in1_T_11 = iactive[2:0] == 3'h5; // @[Fifo4.scala 40:27]
- wire _in1_T_12 = iactive[2:0] == 3'h6 | _in1_T_11; // @[Fifo4.scala 39:35]
- wire _in1_T_14 = iactive[1:0] == 2'h3; // @[Fifo4.scala 41:27]
- wire [3:0] in1valid = {_in1_T_7,_in1_T_12,_in1_T_14,1'h0}; // @[Cat.scala 31:58]
- wire _in2_T_3 = iactive == 4'hd; // @[Fifo4.scala 45:27]
- wire _in2_T_4 = iactive == 4'he | _in2_T_3; // @[Fifo4.scala 44:36]
- wire _in2_T_6 = iactive == 4'hb; // @[Fifo4.scala 46:27]
- wire _in2_T_7 = _in2_T_4 | _in2_T_6; // @[Fifo4.scala 45:36]
- wire [3:0] _GEN_394 = {{1'd0}, iactive[2:0]}; // @[Fifo4.scala 47:27]
- wire _in2_T_11 = iactive[2:0] == 3'h7; // @[Fifo4.scala 48:27]
- wire _in2_T_12 = _GEN_394 == 4'hf | _in2_T_11; // @[Fifo4.scala 47:36]
- wire [3:0] in2valid = {_in2_T_7,_in2_T_12,2'h0}; // @[Cat.scala 31:58]
- wire _in3_T_1 = iactive == 4'hf; // @[Fifo4.scala 51:27]
- wire [3:0] in3valid = {_in3_T_1,1'h0,2'h0}; // @[Cat.scala 31:58]
- wire _valid_T = inpos_0 == 5'h0; // @[Fifo4x4.scala 141:30]
- wire _valid_T_3 = inpos_1 == 5'h0; // @[Fifo4x4.scala 142:30]
- wire _valid_T_5 = inpos_1 == 5'h0 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_6 = inpos_0 == 5'h0 & in0valid[3] | _valid_T_5; // @[Fifo4x4.scala 141:53]
- wire _valid_T_7 = inpos_2 == 5'h0; // @[Fifo4x4.scala 143:30]
- wire _valid_T_9 = inpos_2 == 5'h0 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_10 = _valid_T_6 | _valid_T_9; // @[Fifo4x4.scala 142:53]
- wire _valid_T_13 = inpos_3 == 5'h0 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_14 = _valid_T_10 | _valid_T_13; // @[Fifo4x4.scala 143:53]
- wire _valid_T_20 = _valid_T_3 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_21 = _valid_T & in0valid[2] | _valid_T_20; // @[Fifo4x4.scala 146:53]
- wire _valid_T_24 = _valid_T_7 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_25 = _valid_T_21 | _valid_T_24; // @[Fifo4x4.scala 147:53]
- wire _valid_T_31 = _valid_T_3 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_32 = _valid_T & in0valid[1] | _valid_T_31; // @[Fifo4x4.scala 150:53]
- wire _valid_T_35 = _valid_T & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid = {_valid_T_14,_valid_T_25,_valid_T_32,_valid_T_35}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_1 = {io_in_bits_0_bits_inst,io_in_bits_0_bits_addr,io_in_bits_0_bits_data}; // @[Fifo4x4.scala 156:53]
- wire [95:0] _data_T_2 = valid[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_4 = {io_in_bits_1_bits_inst,io_in_bits_1_bits_addr,io_in_bits_1_bits_data}; // @[Fifo4x4.scala 157:53]
- wire [95:0] _data_T_5 = valid[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_6 = _data_T_2 | _data_T_5; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_8 = {io_in_bits_2_bits_inst,io_in_bits_2_bits_addr,io_in_bits_2_bits_data}; // @[Fifo4x4.scala 158:53]
- wire [95:0] _data_T_9 = valid[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_10 = _data_T_6 | _data_T_9; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_12 = {io_in_bits_3_bits_inst,io_in_bits_3_bits_addr,io_in_bits_3_bits_data}; // @[Fifo4x4.scala 159:53]
- wire [95:0] _data_T_13 = valid[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data = _data_T_10 | _data_T_13; // @[Fifo4x4.scala 158:61]
- wire _valid_T_36 = inpos_0 == 5'h1; // @[Fifo4x4.scala 141:30]
- wire _valid_T_39 = inpos_1 == 5'h1; // @[Fifo4x4.scala 142:30]
- wire _valid_T_41 = inpos_1 == 5'h1 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_42 = inpos_0 == 5'h1 & in0valid[3] | _valid_T_41; // @[Fifo4x4.scala 141:53]
- wire _valid_T_43 = inpos_2 == 5'h1; // @[Fifo4x4.scala 143:30]
- wire _valid_T_45 = inpos_2 == 5'h1 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_46 = _valid_T_42 | _valid_T_45; // @[Fifo4x4.scala 142:53]
- wire _valid_T_49 = inpos_3 == 5'h1 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_50 = _valid_T_46 | _valid_T_49; // @[Fifo4x4.scala 143:53]
- wire _valid_T_56 = _valid_T_39 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_57 = _valid_T_36 & in0valid[2] | _valid_T_56; // @[Fifo4x4.scala 146:53]
- wire _valid_T_60 = _valid_T_43 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_61 = _valid_T_57 | _valid_T_60; // @[Fifo4x4.scala 147:53]
- wire _valid_T_67 = _valid_T_39 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_68 = _valid_T_36 & in0valid[1] | _valid_T_67; // @[Fifo4x4.scala 150:53]
- wire _valid_T_71 = _valid_T_36 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_1 = {_valid_T_50,_valid_T_61,_valid_T_68,_valid_T_71}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_16 = valid_1[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_19 = valid_1[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_20 = _data_T_16 | _data_T_19; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_23 = valid_1[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_24 = _data_T_20 | _data_T_23; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_27 = valid_1[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_1 = _data_T_24 | _data_T_27; // @[Fifo4x4.scala 158:61]
- wire _valid_T_72 = inpos_0 == 5'h2; // @[Fifo4x4.scala 141:30]
- wire _valid_T_75 = inpos_1 == 5'h2; // @[Fifo4x4.scala 142:30]
- wire _valid_T_77 = inpos_1 == 5'h2 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_78 = inpos_0 == 5'h2 & in0valid[3] | _valid_T_77; // @[Fifo4x4.scala 141:53]
- wire _valid_T_79 = inpos_2 == 5'h2; // @[Fifo4x4.scala 143:30]
- wire _valid_T_81 = inpos_2 == 5'h2 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_82 = _valid_T_78 | _valid_T_81; // @[Fifo4x4.scala 142:53]
- wire _valid_T_85 = inpos_3 == 5'h2 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_86 = _valid_T_82 | _valid_T_85; // @[Fifo4x4.scala 143:53]
- wire _valid_T_92 = _valid_T_75 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_93 = _valid_T_72 & in0valid[2] | _valid_T_92; // @[Fifo4x4.scala 146:53]
- wire _valid_T_96 = _valid_T_79 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_97 = _valid_T_93 | _valid_T_96; // @[Fifo4x4.scala 147:53]
- wire _valid_T_103 = _valid_T_75 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_104 = _valid_T_72 & in0valid[1] | _valid_T_103; // @[Fifo4x4.scala 150:53]
- wire _valid_T_107 = _valid_T_72 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_2 = {_valid_T_86,_valid_T_97,_valid_T_104,_valid_T_107}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_30 = valid_2[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_33 = valid_2[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_34 = _data_T_30 | _data_T_33; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_37 = valid_2[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_38 = _data_T_34 | _data_T_37; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_41 = valid_2[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_2 = _data_T_38 | _data_T_41; // @[Fifo4x4.scala 158:61]
- wire _valid_T_108 = inpos_0 == 5'h3; // @[Fifo4x4.scala 141:30]
- wire _valid_T_111 = inpos_1 == 5'h3; // @[Fifo4x4.scala 142:30]
- wire _valid_T_113 = inpos_1 == 5'h3 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_114 = inpos_0 == 5'h3 & in0valid[3] | _valid_T_113; // @[Fifo4x4.scala 141:53]
- wire _valid_T_115 = inpos_2 == 5'h3; // @[Fifo4x4.scala 143:30]
- wire _valid_T_117 = inpos_2 == 5'h3 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_118 = _valid_T_114 | _valid_T_117; // @[Fifo4x4.scala 142:53]
- wire _valid_T_121 = inpos_3 == 5'h3 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_122 = _valid_T_118 | _valid_T_121; // @[Fifo4x4.scala 143:53]
- wire _valid_T_128 = _valid_T_111 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_129 = _valid_T_108 & in0valid[2] | _valid_T_128; // @[Fifo4x4.scala 146:53]
- wire _valid_T_132 = _valid_T_115 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_133 = _valid_T_129 | _valid_T_132; // @[Fifo4x4.scala 147:53]
- wire _valid_T_139 = _valid_T_111 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_140 = _valid_T_108 & in0valid[1] | _valid_T_139; // @[Fifo4x4.scala 150:53]
- wire _valid_T_143 = _valid_T_108 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_3 = {_valid_T_122,_valid_T_133,_valid_T_140,_valid_T_143}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_44 = valid_3[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_47 = valid_3[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_48 = _data_T_44 | _data_T_47; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_51 = valid_3[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_52 = _data_T_48 | _data_T_51; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_55 = valid_3[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_3 = _data_T_52 | _data_T_55; // @[Fifo4x4.scala 158:61]
- wire _valid_T_144 = inpos_0 == 5'h4; // @[Fifo4x4.scala 141:30]
- wire _valid_T_147 = inpos_1 == 5'h4; // @[Fifo4x4.scala 142:30]
- wire _valid_T_149 = inpos_1 == 5'h4 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_150 = inpos_0 == 5'h4 & in0valid[3] | _valid_T_149; // @[Fifo4x4.scala 141:53]
- wire _valid_T_151 = inpos_2 == 5'h4; // @[Fifo4x4.scala 143:30]
- wire _valid_T_153 = inpos_2 == 5'h4 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_154 = _valid_T_150 | _valid_T_153; // @[Fifo4x4.scala 142:53]
- wire _valid_T_157 = inpos_3 == 5'h4 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_158 = _valid_T_154 | _valid_T_157; // @[Fifo4x4.scala 143:53]
- wire _valid_T_164 = _valid_T_147 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_165 = _valid_T_144 & in0valid[2] | _valid_T_164; // @[Fifo4x4.scala 146:53]
- wire _valid_T_168 = _valid_T_151 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_169 = _valid_T_165 | _valid_T_168; // @[Fifo4x4.scala 147:53]
- wire _valid_T_175 = _valid_T_147 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_176 = _valid_T_144 & in0valid[1] | _valid_T_175; // @[Fifo4x4.scala 150:53]
- wire _valid_T_179 = _valid_T_144 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_4 = {_valid_T_158,_valid_T_169,_valid_T_176,_valid_T_179}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_58 = valid_4[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_61 = valid_4[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_62 = _data_T_58 | _data_T_61; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_65 = valid_4[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_66 = _data_T_62 | _data_T_65; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_69 = valid_4[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_4 = _data_T_66 | _data_T_69; // @[Fifo4x4.scala 158:61]
- wire _valid_T_180 = inpos_0 == 5'h5; // @[Fifo4x4.scala 141:30]
- wire _valid_T_183 = inpos_1 == 5'h5; // @[Fifo4x4.scala 142:30]
- wire _valid_T_185 = inpos_1 == 5'h5 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_186 = inpos_0 == 5'h5 & in0valid[3] | _valid_T_185; // @[Fifo4x4.scala 141:53]
- wire _valid_T_187 = inpos_2 == 5'h5; // @[Fifo4x4.scala 143:30]
- wire _valid_T_189 = inpos_2 == 5'h5 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_190 = _valid_T_186 | _valid_T_189; // @[Fifo4x4.scala 142:53]
- wire _valid_T_193 = inpos_3 == 5'h5 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_194 = _valid_T_190 | _valid_T_193; // @[Fifo4x4.scala 143:53]
- wire _valid_T_200 = _valid_T_183 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_201 = _valid_T_180 & in0valid[2] | _valid_T_200; // @[Fifo4x4.scala 146:53]
- wire _valid_T_204 = _valid_T_187 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_205 = _valid_T_201 | _valid_T_204; // @[Fifo4x4.scala 147:53]
- wire _valid_T_211 = _valid_T_183 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_212 = _valid_T_180 & in0valid[1] | _valid_T_211; // @[Fifo4x4.scala 150:53]
- wire _valid_T_215 = _valid_T_180 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_5 = {_valid_T_194,_valid_T_205,_valid_T_212,_valid_T_215}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_72 = valid_5[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_75 = valid_5[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_76 = _data_T_72 | _data_T_75; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_79 = valid_5[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_80 = _data_T_76 | _data_T_79; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_83 = valid_5[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_5 = _data_T_80 | _data_T_83; // @[Fifo4x4.scala 158:61]
- wire _valid_T_216 = inpos_0 == 5'h6; // @[Fifo4x4.scala 141:30]
- wire _valid_T_219 = inpos_1 == 5'h6; // @[Fifo4x4.scala 142:30]
- wire _valid_T_221 = inpos_1 == 5'h6 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_222 = inpos_0 == 5'h6 & in0valid[3] | _valid_T_221; // @[Fifo4x4.scala 141:53]
- wire _valid_T_223 = inpos_2 == 5'h6; // @[Fifo4x4.scala 143:30]
- wire _valid_T_225 = inpos_2 == 5'h6 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_226 = _valid_T_222 | _valid_T_225; // @[Fifo4x4.scala 142:53]
- wire _valid_T_229 = inpos_3 == 5'h6 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_230 = _valid_T_226 | _valid_T_229; // @[Fifo4x4.scala 143:53]
- wire _valid_T_236 = _valid_T_219 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_237 = _valid_T_216 & in0valid[2] | _valid_T_236; // @[Fifo4x4.scala 146:53]
- wire _valid_T_240 = _valid_T_223 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_241 = _valid_T_237 | _valid_T_240; // @[Fifo4x4.scala 147:53]
- wire _valid_T_247 = _valid_T_219 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_248 = _valid_T_216 & in0valid[1] | _valid_T_247; // @[Fifo4x4.scala 150:53]
- wire _valid_T_251 = _valid_T_216 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_6 = {_valid_T_230,_valid_T_241,_valid_T_248,_valid_T_251}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_86 = valid_6[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_89 = valid_6[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_90 = _data_T_86 | _data_T_89; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_93 = valid_6[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_94 = _data_T_90 | _data_T_93; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_97 = valid_6[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_6 = _data_T_94 | _data_T_97; // @[Fifo4x4.scala 158:61]
- wire _valid_T_252 = inpos_0 == 5'h7; // @[Fifo4x4.scala 141:30]
- wire _valid_T_255 = inpos_1 == 5'h7; // @[Fifo4x4.scala 142:30]
- wire _valid_T_257 = inpos_1 == 5'h7 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_258 = inpos_0 == 5'h7 & in0valid[3] | _valid_T_257; // @[Fifo4x4.scala 141:53]
- wire _valid_T_259 = inpos_2 == 5'h7; // @[Fifo4x4.scala 143:30]
- wire _valid_T_261 = inpos_2 == 5'h7 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_262 = _valid_T_258 | _valid_T_261; // @[Fifo4x4.scala 142:53]
- wire _valid_T_265 = inpos_3 == 5'h7 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_266 = _valid_T_262 | _valid_T_265; // @[Fifo4x4.scala 143:53]
- wire _valid_T_272 = _valid_T_255 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_273 = _valid_T_252 & in0valid[2] | _valid_T_272; // @[Fifo4x4.scala 146:53]
- wire _valid_T_276 = _valid_T_259 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_277 = _valid_T_273 | _valid_T_276; // @[Fifo4x4.scala 147:53]
- wire _valid_T_283 = _valid_T_255 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_284 = _valid_T_252 & in0valid[1] | _valid_T_283; // @[Fifo4x4.scala 150:53]
- wire _valid_T_287 = _valid_T_252 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_7 = {_valid_T_266,_valid_T_277,_valid_T_284,_valid_T_287}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_100 = valid_7[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_103 = valid_7[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_104 = _data_T_100 | _data_T_103; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_107 = valid_7[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_108 = _data_T_104 | _data_T_107; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_111 = valid_7[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_7 = _data_T_108 | _data_T_111; // @[Fifo4x4.scala 158:61]
- wire _valid_T_288 = inpos_0 == 5'h8; // @[Fifo4x4.scala 141:30]
- wire _valid_T_291 = inpos_1 == 5'h8; // @[Fifo4x4.scala 142:30]
- wire _valid_T_293 = inpos_1 == 5'h8 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_294 = inpos_0 == 5'h8 & in0valid[3] | _valid_T_293; // @[Fifo4x4.scala 141:53]
- wire _valid_T_295 = inpos_2 == 5'h8; // @[Fifo4x4.scala 143:30]
- wire _valid_T_297 = inpos_2 == 5'h8 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_298 = _valid_T_294 | _valid_T_297; // @[Fifo4x4.scala 142:53]
- wire _valid_T_301 = inpos_3 == 5'h8 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_302 = _valid_T_298 | _valid_T_301; // @[Fifo4x4.scala 143:53]
- wire _valid_T_308 = _valid_T_291 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_309 = _valid_T_288 & in0valid[2] | _valid_T_308; // @[Fifo4x4.scala 146:53]
- wire _valid_T_312 = _valid_T_295 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_313 = _valid_T_309 | _valid_T_312; // @[Fifo4x4.scala 147:53]
- wire _valid_T_319 = _valid_T_291 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_320 = _valid_T_288 & in0valid[1] | _valid_T_319; // @[Fifo4x4.scala 150:53]
- wire _valid_T_323 = _valid_T_288 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_8 = {_valid_T_302,_valid_T_313,_valid_T_320,_valid_T_323}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_114 = valid_8[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_117 = valid_8[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_118 = _data_T_114 | _data_T_117; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_121 = valid_8[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_122 = _data_T_118 | _data_T_121; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_125 = valid_8[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_8 = _data_T_122 | _data_T_125; // @[Fifo4x4.scala 158:61]
- wire _valid_T_324 = inpos_0 == 5'h9; // @[Fifo4x4.scala 141:30]
- wire _valid_T_327 = inpos_1 == 5'h9; // @[Fifo4x4.scala 142:30]
- wire _valid_T_329 = inpos_1 == 5'h9 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_330 = inpos_0 == 5'h9 & in0valid[3] | _valid_T_329; // @[Fifo4x4.scala 141:53]
- wire _valid_T_331 = inpos_2 == 5'h9; // @[Fifo4x4.scala 143:30]
- wire _valid_T_333 = inpos_2 == 5'h9 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_334 = _valid_T_330 | _valid_T_333; // @[Fifo4x4.scala 142:53]
- wire _valid_T_337 = inpos_3 == 5'h9 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_338 = _valid_T_334 | _valid_T_337; // @[Fifo4x4.scala 143:53]
- wire _valid_T_344 = _valid_T_327 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_345 = _valid_T_324 & in0valid[2] | _valid_T_344; // @[Fifo4x4.scala 146:53]
- wire _valid_T_348 = _valid_T_331 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_349 = _valid_T_345 | _valid_T_348; // @[Fifo4x4.scala 147:53]
- wire _valid_T_355 = _valid_T_327 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_356 = _valid_T_324 & in0valid[1] | _valid_T_355; // @[Fifo4x4.scala 150:53]
- wire _valid_T_359 = _valid_T_324 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_9 = {_valid_T_338,_valid_T_349,_valid_T_356,_valid_T_359}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_128 = valid_9[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_131 = valid_9[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_132 = _data_T_128 | _data_T_131; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_135 = valid_9[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_136 = _data_T_132 | _data_T_135; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_139 = valid_9[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_9 = _data_T_136 | _data_T_139; // @[Fifo4x4.scala 158:61]
- wire _valid_T_360 = inpos_0 == 5'ha; // @[Fifo4x4.scala 141:30]
- wire _valid_T_363 = inpos_1 == 5'ha; // @[Fifo4x4.scala 142:30]
- wire _valid_T_365 = inpos_1 == 5'ha & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_366 = inpos_0 == 5'ha & in0valid[3] | _valid_T_365; // @[Fifo4x4.scala 141:53]
- wire _valid_T_367 = inpos_2 == 5'ha; // @[Fifo4x4.scala 143:30]
- wire _valid_T_369 = inpos_2 == 5'ha & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_370 = _valid_T_366 | _valid_T_369; // @[Fifo4x4.scala 142:53]
- wire _valid_T_373 = inpos_3 == 5'ha & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_374 = _valid_T_370 | _valid_T_373; // @[Fifo4x4.scala 143:53]
- wire _valid_T_380 = _valid_T_363 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_381 = _valid_T_360 & in0valid[2] | _valid_T_380; // @[Fifo4x4.scala 146:53]
- wire _valid_T_384 = _valid_T_367 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_385 = _valid_T_381 | _valid_T_384; // @[Fifo4x4.scala 147:53]
- wire _valid_T_391 = _valid_T_363 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_392 = _valid_T_360 & in0valid[1] | _valid_T_391; // @[Fifo4x4.scala 150:53]
- wire _valid_T_395 = _valid_T_360 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_10 = {_valid_T_374,_valid_T_385,_valid_T_392,_valid_T_395}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_142 = valid_10[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_145 = valid_10[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_146 = _data_T_142 | _data_T_145; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_149 = valid_10[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_150 = _data_T_146 | _data_T_149; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_153 = valid_10[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_10 = _data_T_150 | _data_T_153; // @[Fifo4x4.scala 158:61]
- wire _valid_T_396 = inpos_0 == 5'hb; // @[Fifo4x4.scala 141:30]
- wire _valid_T_399 = inpos_1 == 5'hb; // @[Fifo4x4.scala 142:30]
- wire _valid_T_401 = inpos_1 == 5'hb & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_402 = inpos_0 == 5'hb & in0valid[3] | _valid_T_401; // @[Fifo4x4.scala 141:53]
- wire _valid_T_403 = inpos_2 == 5'hb; // @[Fifo4x4.scala 143:30]
- wire _valid_T_405 = inpos_2 == 5'hb & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_406 = _valid_T_402 | _valid_T_405; // @[Fifo4x4.scala 142:53]
- wire _valid_T_409 = inpos_3 == 5'hb & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_410 = _valid_T_406 | _valid_T_409; // @[Fifo4x4.scala 143:53]
- wire _valid_T_416 = _valid_T_399 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_417 = _valid_T_396 & in0valid[2] | _valid_T_416; // @[Fifo4x4.scala 146:53]
- wire _valid_T_420 = _valid_T_403 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_421 = _valid_T_417 | _valid_T_420; // @[Fifo4x4.scala 147:53]
- wire _valid_T_427 = _valid_T_399 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_428 = _valid_T_396 & in0valid[1] | _valid_T_427; // @[Fifo4x4.scala 150:53]
- wire _valid_T_431 = _valid_T_396 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_11 = {_valid_T_410,_valid_T_421,_valid_T_428,_valid_T_431}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_156 = valid_11[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_159 = valid_11[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_160 = _data_T_156 | _data_T_159; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_163 = valid_11[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_164 = _data_T_160 | _data_T_163; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_167 = valid_11[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_11 = _data_T_164 | _data_T_167; // @[Fifo4x4.scala 158:61]
- wire _valid_T_432 = inpos_0 == 5'hc; // @[Fifo4x4.scala 141:30]
- wire _valid_T_435 = inpos_1 == 5'hc; // @[Fifo4x4.scala 142:30]
- wire _valid_T_437 = inpos_1 == 5'hc & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_438 = inpos_0 == 5'hc & in0valid[3] | _valid_T_437; // @[Fifo4x4.scala 141:53]
- wire _valid_T_439 = inpos_2 == 5'hc; // @[Fifo4x4.scala 143:30]
- wire _valid_T_441 = inpos_2 == 5'hc & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_442 = _valid_T_438 | _valid_T_441; // @[Fifo4x4.scala 142:53]
- wire _valid_T_445 = inpos_3 == 5'hc & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_446 = _valid_T_442 | _valid_T_445; // @[Fifo4x4.scala 143:53]
- wire _valid_T_452 = _valid_T_435 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_453 = _valid_T_432 & in0valid[2] | _valid_T_452; // @[Fifo4x4.scala 146:53]
- wire _valid_T_456 = _valid_T_439 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_457 = _valid_T_453 | _valid_T_456; // @[Fifo4x4.scala 147:53]
- wire _valid_T_463 = _valid_T_435 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_464 = _valid_T_432 & in0valid[1] | _valid_T_463; // @[Fifo4x4.scala 150:53]
- wire _valid_T_467 = _valid_T_432 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_12 = {_valid_T_446,_valid_T_457,_valid_T_464,_valid_T_467}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_170 = valid_12[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_173 = valid_12[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_174 = _data_T_170 | _data_T_173; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_177 = valid_12[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_178 = _data_T_174 | _data_T_177; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_181 = valid_12[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_12 = _data_T_178 | _data_T_181; // @[Fifo4x4.scala 158:61]
- wire _valid_T_468 = inpos_0 == 5'hd; // @[Fifo4x4.scala 141:30]
- wire _valid_T_471 = inpos_1 == 5'hd; // @[Fifo4x4.scala 142:30]
- wire _valid_T_473 = inpos_1 == 5'hd & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_474 = inpos_0 == 5'hd & in0valid[3] | _valid_T_473; // @[Fifo4x4.scala 141:53]
- wire _valid_T_475 = inpos_2 == 5'hd; // @[Fifo4x4.scala 143:30]
- wire _valid_T_477 = inpos_2 == 5'hd & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_478 = _valid_T_474 | _valid_T_477; // @[Fifo4x4.scala 142:53]
- wire _valid_T_481 = inpos_3 == 5'hd & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_482 = _valid_T_478 | _valid_T_481; // @[Fifo4x4.scala 143:53]
- wire _valid_T_488 = _valid_T_471 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_489 = _valid_T_468 & in0valid[2] | _valid_T_488; // @[Fifo4x4.scala 146:53]
- wire _valid_T_492 = _valid_T_475 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_493 = _valid_T_489 | _valid_T_492; // @[Fifo4x4.scala 147:53]
- wire _valid_T_499 = _valid_T_471 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_500 = _valid_T_468 & in0valid[1] | _valid_T_499; // @[Fifo4x4.scala 150:53]
- wire _valid_T_503 = _valid_T_468 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_13 = {_valid_T_482,_valid_T_493,_valid_T_500,_valid_T_503}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_184 = valid_13[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_187 = valid_13[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_188 = _data_T_184 | _data_T_187; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_191 = valid_13[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_192 = _data_T_188 | _data_T_191; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_195 = valid_13[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_13 = _data_T_192 | _data_T_195; // @[Fifo4x4.scala 158:61]
- wire _valid_T_504 = inpos_0 == 5'he; // @[Fifo4x4.scala 141:30]
- wire _valid_T_507 = inpos_1 == 5'he; // @[Fifo4x4.scala 142:30]
- wire _valid_T_509 = inpos_1 == 5'he & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_510 = inpos_0 == 5'he & in0valid[3] | _valid_T_509; // @[Fifo4x4.scala 141:53]
- wire _valid_T_511 = inpos_2 == 5'he; // @[Fifo4x4.scala 143:30]
- wire _valid_T_513 = inpos_2 == 5'he & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_514 = _valid_T_510 | _valid_T_513; // @[Fifo4x4.scala 142:53]
- wire _valid_T_517 = inpos_3 == 5'he & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_518 = _valid_T_514 | _valid_T_517; // @[Fifo4x4.scala 143:53]
- wire _valid_T_524 = _valid_T_507 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_525 = _valid_T_504 & in0valid[2] | _valid_T_524; // @[Fifo4x4.scala 146:53]
- wire _valid_T_528 = _valid_T_511 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_529 = _valid_T_525 | _valid_T_528; // @[Fifo4x4.scala 147:53]
- wire _valid_T_535 = _valid_T_507 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_536 = _valid_T_504 & in0valid[1] | _valid_T_535; // @[Fifo4x4.scala 150:53]
- wire _valid_T_539 = _valid_T_504 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_14 = {_valid_T_518,_valid_T_529,_valid_T_536,_valid_T_539}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_198 = valid_14[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_201 = valid_14[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_202 = _data_T_198 | _data_T_201; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_205 = valid_14[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_206 = _data_T_202 | _data_T_205; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_209 = valid_14[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_14 = _data_T_206 | _data_T_209; // @[Fifo4x4.scala 158:61]
- wire _valid_T_540 = inpos_0 == 5'hf; // @[Fifo4x4.scala 141:30]
- wire _valid_T_543 = inpos_1 == 5'hf; // @[Fifo4x4.scala 142:30]
- wire _valid_T_545 = inpos_1 == 5'hf & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_546 = inpos_0 == 5'hf & in0valid[3] | _valid_T_545; // @[Fifo4x4.scala 141:53]
- wire _valid_T_547 = inpos_2 == 5'hf; // @[Fifo4x4.scala 143:30]
- wire _valid_T_549 = inpos_2 == 5'hf & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_550 = _valid_T_546 | _valid_T_549; // @[Fifo4x4.scala 142:53]
- wire _valid_T_553 = inpos_3 == 5'hf & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_554 = _valid_T_550 | _valid_T_553; // @[Fifo4x4.scala 143:53]
- wire _valid_T_560 = _valid_T_543 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_561 = _valid_T_540 & in0valid[2] | _valid_T_560; // @[Fifo4x4.scala 146:53]
- wire _valid_T_564 = _valid_T_547 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_565 = _valid_T_561 | _valid_T_564; // @[Fifo4x4.scala 147:53]
- wire _valid_T_571 = _valid_T_543 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_572 = _valid_T_540 & in0valid[1] | _valid_T_571; // @[Fifo4x4.scala 150:53]
- wire _valid_T_575 = _valid_T_540 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_15 = {_valid_T_554,_valid_T_565,_valid_T_572,_valid_T_575}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_212 = valid_15[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_215 = valid_15[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_216 = _data_T_212 | _data_T_215; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_219 = valid_15[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_220 = _data_T_216 | _data_T_219; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_223 = valid_15[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_15 = _data_T_220 | _data_T_223; // @[Fifo4x4.scala 158:61]
- wire _valid_T_576 = inpos_0 == 5'h10; // @[Fifo4x4.scala 141:30]
- wire _valid_T_579 = inpos_1 == 5'h10; // @[Fifo4x4.scala 142:30]
- wire _valid_T_581 = inpos_1 == 5'h10 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_582 = inpos_0 == 5'h10 & in0valid[3] | _valid_T_581; // @[Fifo4x4.scala 141:53]
- wire _valid_T_583 = inpos_2 == 5'h10; // @[Fifo4x4.scala 143:30]
- wire _valid_T_585 = inpos_2 == 5'h10 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_586 = _valid_T_582 | _valid_T_585; // @[Fifo4x4.scala 142:53]
- wire _valid_T_589 = inpos_3 == 5'h10 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_590 = _valid_T_586 | _valid_T_589; // @[Fifo4x4.scala 143:53]
- wire _valid_T_596 = _valid_T_579 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_597 = _valid_T_576 & in0valid[2] | _valid_T_596; // @[Fifo4x4.scala 146:53]
- wire _valid_T_600 = _valid_T_583 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_601 = _valid_T_597 | _valid_T_600; // @[Fifo4x4.scala 147:53]
- wire _valid_T_607 = _valid_T_579 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_608 = _valid_T_576 & in0valid[1] | _valid_T_607; // @[Fifo4x4.scala 150:53]
- wire _valid_T_611 = _valid_T_576 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_16 = {_valid_T_590,_valid_T_601,_valid_T_608,_valid_T_611}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_226 = valid_16[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_229 = valid_16[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_230 = _data_T_226 | _data_T_229; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_233 = valid_16[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_234 = _data_T_230 | _data_T_233; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_237 = valid_16[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_16 = _data_T_234 | _data_T_237; // @[Fifo4x4.scala 158:61]
- wire _valid_T_612 = inpos_0 == 5'h11; // @[Fifo4x4.scala 141:30]
- wire _valid_T_615 = inpos_1 == 5'h11; // @[Fifo4x4.scala 142:30]
- wire _valid_T_617 = inpos_1 == 5'h11 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_618 = inpos_0 == 5'h11 & in0valid[3] | _valid_T_617; // @[Fifo4x4.scala 141:53]
- wire _valid_T_619 = inpos_2 == 5'h11; // @[Fifo4x4.scala 143:30]
- wire _valid_T_621 = inpos_2 == 5'h11 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_622 = _valid_T_618 | _valid_T_621; // @[Fifo4x4.scala 142:53]
- wire _valid_T_625 = inpos_3 == 5'h11 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_626 = _valid_T_622 | _valid_T_625; // @[Fifo4x4.scala 143:53]
- wire _valid_T_632 = _valid_T_615 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_633 = _valid_T_612 & in0valid[2] | _valid_T_632; // @[Fifo4x4.scala 146:53]
- wire _valid_T_636 = _valid_T_619 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_637 = _valid_T_633 | _valid_T_636; // @[Fifo4x4.scala 147:53]
- wire _valid_T_643 = _valid_T_615 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_644 = _valid_T_612 & in0valid[1] | _valid_T_643; // @[Fifo4x4.scala 150:53]
- wire _valid_T_647 = _valid_T_612 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_17 = {_valid_T_626,_valid_T_637,_valid_T_644,_valid_T_647}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_240 = valid_17[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_243 = valid_17[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_244 = _data_T_240 | _data_T_243; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_247 = valid_17[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_248 = _data_T_244 | _data_T_247; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_251 = valid_17[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_17 = _data_T_248 | _data_T_251; // @[Fifo4x4.scala 158:61]
- wire _valid_T_648 = inpos_0 == 5'h12; // @[Fifo4x4.scala 141:30]
- wire _valid_T_651 = inpos_1 == 5'h12; // @[Fifo4x4.scala 142:30]
- wire _valid_T_653 = inpos_1 == 5'h12 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_654 = inpos_0 == 5'h12 & in0valid[3] | _valid_T_653; // @[Fifo4x4.scala 141:53]
- wire _valid_T_655 = inpos_2 == 5'h12; // @[Fifo4x4.scala 143:30]
- wire _valid_T_657 = inpos_2 == 5'h12 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_658 = _valid_T_654 | _valid_T_657; // @[Fifo4x4.scala 142:53]
- wire _valid_T_661 = inpos_3 == 5'h12 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_662 = _valid_T_658 | _valid_T_661; // @[Fifo4x4.scala 143:53]
- wire _valid_T_668 = _valid_T_651 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_669 = _valid_T_648 & in0valid[2] | _valid_T_668; // @[Fifo4x4.scala 146:53]
- wire _valid_T_672 = _valid_T_655 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_673 = _valid_T_669 | _valid_T_672; // @[Fifo4x4.scala 147:53]
- wire _valid_T_679 = _valid_T_651 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_680 = _valid_T_648 & in0valid[1] | _valid_T_679; // @[Fifo4x4.scala 150:53]
- wire _valid_T_683 = _valid_T_648 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_18 = {_valid_T_662,_valid_T_673,_valid_T_680,_valid_T_683}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_254 = valid_18[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_257 = valid_18[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_258 = _data_T_254 | _data_T_257; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_261 = valid_18[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_262 = _data_T_258 | _data_T_261; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_265 = valid_18[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_18 = _data_T_262 | _data_T_265; // @[Fifo4x4.scala 158:61]
- wire _valid_T_684 = inpos_0 == 5'h13; // @[Fifo4x4.scala 141:30]
- wire _valid_T_687 = inpos_1 == 5'h13; // @[Fifo4x4.scala 142:30]
- wire _valid_T_689 = inpos_1 == 5'h13 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_690 = inpos_0 == 5'h13 & in0valid[3] | _valid_T_689; // @[Fifo4x4.scala 141:53]
- wire _valid_T_691 = inpos_2 == 5'h13; // @[Fifo4x4.scala 143:30]
- wire _valid_T_693 = inpos_2 == 5'h13 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_694 = _valid_T_690 | _valid_T_693; // @[Fifo4x4.scala 142:53]
- wire _valid_T_697 = inpos_3 == 5'h13 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_698 = _valid_T_694 | _valid_T_697; // @[Fifo4x4.scala 143:53]
- wire _valid_T_704 = _valid_T_687 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_705 = _valid_T_684 & in0valid[2] | _valid_T_704; // @[Fifo4x4.scala 146:53]
- wire _valid_T_708 = _valid_T_691 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_709 = _valid_T_705 | _valid_T_708; // @[Fifo4x4.scala 147:53]
- wire _valid_T_715 = _valid_T_687 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_716 = _valid_T_684 & in0valid[1] | _valid_T_715; // @[Fifo4x4.scala 150:53]
- wire _valid_T_719 = _valid_T_684 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_19 = {_valid_T_698,_valid_T_709,_valid_T_716,_valid_T_719}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_268 = valid_19[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_271 = valid_19[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_272 = _data_T_268 | _data_T_271; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_275 = valid_19[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_276 = _data_T_272 | _data_T_275; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_279 = valid_19[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_19 = _data_T_276 | _data_T_279; // @[Fifo4x4.scala 158:61]
- wire _valid_T_720 = inpos_0 == 5'h14; // @[Fifo4x4.scala 141:30]
- wire _valid_T_723 = inpos_1 == 5'h14; // @[Fifo4x4.scala 142:30]
- wire _valid_T_725 = inpos_1 == 5'h14 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_726 = inpos_0 == 5'h14 & in0valid[3] | _valid_T_725; // @[Fifo4x4.scala 141:53]
- wire _valid_T_727 = inpos_2 == 5'h14; // @[Fifo4x4.scala 143:30]
- wire _valid_T_729 = inpos_2 == 5'h14 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_730 = _valid_T_726 | _valid_T_729; // @[Fifo4x4.scala 142:53]
- wire _valid_T_733 = inpos_3 == 5'h14 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_734 = _valid_T_730 | _valid_T_733; // @[Fifo4x4.scala 143:53]
- wire _valid_T_740 = _valid_T_723 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_741 = _valid_T_720 & in0valid[2] | _valid_T_740; // @[Fifo4x4.scala 146:53]
- wire _valid_T_744 = _valid_T_727 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_745 = _valid_T_741 | _valid_T_744; // @[Fifo4x4.scala 147:53]
- wire _valid_T_751 = _valid_T_723 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_752 = _valid_T_720 & in0valid[1] | _valid_T_751; // @[Fifo4x4.scala 150:53]
- wire _valid_T_755 = _valid_T_720 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_20 = {_valid_T_734,_valid_T_745,_valid_T_752,_valid_T_755}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_282 = valid_20[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_285 = valid_20[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_286 = _data_T_282 | _data_T_285; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_289 = valid_20[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_290 = _data_T_286 | _data_T_289; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_293 = valid_20[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_20 = _data_T_290 | _data_T_293; // @[Fifo4x4.scala 158:61]
- wire _valid_T_756 = inpos_0 == 5'h15; // @[Fifo4x4.scala 141:30]
- wire _valid_T_759 = inpos_1 == 5'h15; // @[Fifo4x4.scala 142:30]
- wire _valid_T_761 = inpos_1 == 5'h15 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_762 = inpos_0 == 5'h15 & in0valid[3] | _valid_T_761; // @[Fifo4x4.scala 141:53]
- wire _valid_T_763 = inpos_2 == 5'h15; // @[Fifo4x4.scala 143:30]
- wire _valid_T_765 = inpos_2 == 5'h15 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_766 = _valid_T_762 | _valid_T_765; // @[Fifo4x4.scala 142:53]
- wire _valid_T_769 = inpos_3 == 5'h15 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_770 = _valid_T_766 | _valid_T_769; // @[Fifo4x4.scala 143:53]
- wire _valid_T_776 = _valid_T_759 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_777 = _valid_T_756 & in0valid[2] | _valid_T_776; // @[Fifo4x4.scala 146:53]
- wire _valid_T_780 = _valid_T_763 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_781 = _valid_T_777 | _valid_T_780; // @[Fifo4x4.scala 147:53]
- wire _valid_T_787 = _valid_T_759 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_788 = _valid_T_756 & in0valid[1] | _valid_T_787; // @[Fifo4x4.scala 150:53]
- wire _valid_T_791 = _valid_T_756 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_21 = {_valid_T_770,_valid_T_781,_valid_T_788,_valid_T_791}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_296 = valid_21[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_299 = valid_21[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_300 = _data_T_296 | _data_T_299; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_303 = valid_21[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_304 = _data_T_300 | _data_T_303; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_307 = valid_21[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_21 = _data_T_304 | _data_T_307; // @[Fifo4x4.scala 158:61]
- wire _valid_T_792 = inpos_0 == 5'h16; // @[Fifo4x4.scala 141:30]
- wire _valid_T_795 = inpos_1 == 5'h16; // @[Fifo4x4.scala 142:30]
- wire _valid_T_797 = inpos_1 == 5'h16 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_798 = inpos_0 == 5'h16 & in0valid[3] | _valid_T_797; // @[Fifo4x4.scala 141:53]
- wire _valid_T_799 = inpos_2 == 5'h16; // @[Fifo4x4.scala 143:30]
- wire _valid_T_801 = inpos_2 == 5'h16 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_802 = _valid_T_798 | _valid_T_801; // @[Fifo4x4.scala 142:53]
- wire _valid_T_805 = inpos_3 == 5'h16 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_806 = _valid_T_802 | _valid_T_805; // @[Fifo4x4.scala 143:53]
- wire _valid_T_812 = _valid_T_795 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_813 = _valid_T_792 & in0valid[2] | _valid_T_812; // @[Fifo4x4.scala 146:53]
- wire _valid_T_816 = _valid_T_799 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_817 = _valid_T_813 | _valid_T_816; // @[Fifo4x4.scala 147:53]
- wire _valid_T_823 = _valid_T_795 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_824 = _valid_T_792 & in0valid[1] | _valid_T_823; // @[Fifo4x4.scala 150:53]
- wire _valid_T_827 = _valid_T_792 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_22 = {_valid_T_806,_valid_T_817,_valid_T_824,_valid_T_827}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_310 = valid_22[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_313 = valid_22[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_314 = _data_T_310 | _data_T_313; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_317 = valid_22[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_318 = _data_T_314 | _data_T_317; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_321 = valid_22[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_22 = _data_T_318 | _data_T_321; // @[Fifo4x4.scala 158:61]
- wire _valid_T_828 = inpos_0 == 5'h17; // @[Fifo4x4.scala 141:30]
- wire _valid_T_831 = inpos_1 == 5'h17; // @[Fifo4x4.scala 142:30]
- wire _valid_T_833 = inpos_1 == 5'h17 & in1valid[3]; // @[Fifo4x4.scala 142:38]
- wire _valid_T_834 = inpos_0 == 5'h17 & in0valid[3] | _valid_T_833; // @[Fifo4x4.scala 141:53]
- wire _valid_T_835 = inpos_2 == 5'h17; // @[Fifo4x4.scala 143:30]
- wire _valid_T_837 = inpos_2 == 5'h17 & in2valid[3]; // @[Fifo4x4.scala 143:38]
- wire _valid_T_838 = _valid_T_834 | _valid_T_837; // @[Fifo4x4.scala 142:53]
- wire _valid_T_841 = inpos_3 == 5'h17 & in3valid[3]; // @[Fifo4x4.scala 144:38]
- wire _valid_T_842 = _valid_T_838 | _valid_T_841; // @[Fifo4x4.scala 143:53]
- wire _valid_T_848 = _valid_T_831 & in1valid[2]; // @[Fifo4x4.scala 147:38]
- wire _valid_T_849 = _valid_T_828 & in0valid[2] | _valid_T_848; // @[Fifo4x4.scala 146:53]
- wire _valid_T_852 = _valid_T_835 & in2valid[2]; // @[Fifo4x4.scala 148:38]
- wire _valid_T_853 = _valid_T_849 | _valid_T_852; // @[Fifo4x4.scala 147:53]
- wire _valid_T_859 = _valid_T_831 & in1valid[1]; // @[Fifo4x4.scala 151:38]
- wire _valid_T_860 = _valid_T_828 & in0valid[1] | _valid_T_859; // @[Fifo4x4.scala 150:53]
- wire _valid_T_863 = _valid_T_828 & in0valid[0]; // @[Fifo4x4.scala 153:38]
- wire [3:0] valid_23 = {_valid_T_842,_valid_T_853,_valid_T_860,_valid_T_863}; // @[Cat.scala 31:58]
- wire [95:0] _data_T_324 = valid_23[0] ? _data_T_1 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_327 = valid_23[1] ? _data_T_4 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_328 = _data_T_324 | _data_T_327; // @[Fifo4x4.scala 156:61]
- wire [95:0] _data_T_331 = valid_23[2] ? _data_T_8 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] _data_T_332 = _data_T_328 | _data_T_331; // @[Fifo4x4.scala 157:61]
- wire [95:0] _data_T_335 = valid_23[3] ? _data_T_12 : 96'h0; // @[Library.scala 22:8]
- wire [95:0] data_23 = _data_T_332 | _data_T_335; // @[Fifo4x4.scala 158:61]
- wire [31:0] _GEN_93 = 5'h1 == outpos_0 ? mem_1_data : mem_0_data; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_94 = 5'h2 == outpos_0 ? mem_2_data : _GEN_93; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_95 = 5'h3 == outpos_0 ? mem_3_data : _GEN_94; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_96 = 5'h4 == outpos_0 ? mem_4_data : _GEN_95; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_97 = 5'h5 == outpos_0 ? mem_5_data : _GEN_96; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_98 = 5'h6 == outpos_0 ? mem_6_data : _GEN_97; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_99 = 5'h7 == outpos_0 ? mem_7_data : _GEN_98; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_100 = 5'h8 == outpos_0 ? mem_8_data : _GEN_99; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_101 = 5'h9 == outpos_0 ? mem_9_data : _GEN_100; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_102 = 5'ha == outpos_0 ? mem_10_data : _GEN_101; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_103 = 5'hb == outpos_0 ? mem_11_data : _GEN_102; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_104 = 5'hc == outpos_0 ? mem_12_data : _GEN_103; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_105 = 5'hd == outpos_0 ? mem_13_data : _GEN_104; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_106 = 5'he == outpos_0 ? mem_14_data : _GEN_105; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_107 = 5'hf == outpos_0 ? mem_15_data : _GEN_106; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_108 = 5'h10 == outpos_0 ? mem_16_data : _GEN_107; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_109 = 5'h11 == outpos_0 ? mem_17_data : _GEN_108; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_110 = 5'h12 == outpos_0 ? mem_18_data : _GEN_109; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_111 = 5'h13 == outpos_0 ? mem_19_data : _GEN_110; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_112 = 5'h14 == outpos_0 ? mem_20_data : _GEN_111; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_113 = 5'h15 == outpos_0 ? mem_21_data : _GEN_112; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_114 = 5'h16 == outpos_0 ? mem_22_data : _GEN_113; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_117 = 5'h1 == outpos_0 ? mem_1_addr : mem_0_addr; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_118 = 5'h2 == outpos_0 ? mem_2_addr : _GEN_117; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_119 = 5'h3 == outpos_0 ? mem_3_addr : _GEN_118; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_120 = 5'h4 == outpos_0 ? mem_4_addr : _GEN_119; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_121 = 5'h5 == outpos_0 ? mem_5_addr : _GEN_120; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_122 = 5'h6 == outpos_0 ? mem_6_addr : _GEN_121; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_123 = 5'h7 == outpos_0 ? mem_7_addr : _GEN_122; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_124 = 5'h8 == outpos_0 ? mem_8_addr : _GEN_123; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_125 = 5'h9 == outpos_0 ? mem_9_addr : _GEN_124; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_126 = 5'ha == outpos_0 ? mem_10_addr : _GEN_125; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_127 = 5'hb == outpos_0 ? mem_11_addr : _GEN_126; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_128 = 5'hc == outpos_0 ? mem_12_addr : _GEN_127; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_129 = 5'hd == outpos_0 ? mem_13_addr : _GEN_128; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_130 = 5'he == outpos_0 ? mem_14_addr : _GEN_129; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_131 = 5'hf == outpos_0 ? mem_15_addr : _GEN_130; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_132 = 5'h10 == outpos_0 ? mem_16_addr : _GEN_131; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_133 = 5'h11 == outpos_0 ? mem_17_addr : _GEN_132; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_134 = 5'h12 == outpos_0 ? mem_18_addr : _GEN_133; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_135 = 5'h13 == outpos_0 ? mem_19_addr : _GEN_134; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_136 = 5'h14 == outpos_0 ? mem_20_addr : _GEN_135; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_137 = 5'h15 == outpos_0 ? mem_21_addr : _GEN_136; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_138 = 5'h16 == outpos_0 ? mem_22_addr : _GEN_137; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_141 = 5'h1 == outpos_0 ? mem_1_inst : mem_0_inst; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_142 = 5'h2 == outpos_0 ? mem_2_inst : _GEN_141; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_143 = 5'h3 == outpos_0 ? mem_3_inst : _GEN_142; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_144 = 5'h4 == outpos_0 ? mem_4_inst : _GEN_143; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_145 = 5'h5 == outpos_0 ? mem_5_inst : _GEN_144; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_146 = 5'h6 == outpos_0 ? mem_6_inst : _GEN_145; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_147 = 5'h7 == outpos_0 ? mem_7_inst : _GEN_146; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_148 = 5'h8 == outpos_0 ? mem_8_inst : _GEN_147; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_149 = 5'h9 == outpos_0 ? mem_9_inst : _GEN_148; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_150 = 5'ha == outpos_0 ? mem_10_inst : _GEN_149; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_151 = 5'hb == outpos_0 ? mem_11_inst : _GEN_150; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_152 = 5'hc == outpos_0 ? mem_12_inst : _GEN_151; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_153 = 5'hd == outpos_0 ? mem_13_inst : _GEN_152; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_154 = 5'he == outpos_0 ? mem_14_inst : _GEN_153; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_155 = 5'hf == outpos_0 ? mem_15_inst : _GEN_154; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_156 = 5'h10 == outpos_0 ? mem_16_inst : _GEN_155; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_157 = 5'h11 == outpos_0 ? mem_17_inst : _GEN_156; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_158 = 5'h12 == outpos_0 ? mem_18_inst : _GEN_157; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_159 = 5'h13 == outpos_0 ? mem_19_inst : _GEN_158; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_160 = 5'h14 == outpos_0 ? mem_20_inst : _GEN_159; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_161 = 5'h15 == outpos_0 ? mem_21_inst : _GEN_160; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_162 = 5'h16 == outpos_0 ? mem_22_inst : _GEN_161; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_165 = 5'h1 == outpos_1 ? mem_1_data : mem_0_data; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_166 = 5'h2 == outpos_1 ? mem_2_data : _GEN_165; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_167 = 5'h3 == outpos_1 ? mem_3_data : _GEN_166; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_168 = 5'h4 == outpos_1 ? mem_4_data : _GEN_167; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_169 = 5'h5 == outpos_1 ? mem_5_data : _GEN_168; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_170 = 5'h6 == outpos_1 ? mem_6_data : _GEN_169; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_171 = 5'h7 == outpos_1 ? mem_7_data : _GEN_170; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_172 = 5'h8 == outpos_1 ? mem_8_data : _GEN_171; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_173 = 5'h9 == outpos_1 ? mem_9_data : _GEN_172; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_174 = 5'ha == outpos_1 ? mem_10_data : _GEN_173; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_175 = 5'hb == outpos_1 ? mem_11_data : _GEN_174; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_176 = 5'hc == outpos_1 ? mem_12_data : _GEN_175; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_177 = 5'hd == outpos_1 ? mem_13_data : _GEN_176; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_178 = 5'he == outpos_1 ? mem_14_data : _GEN_177; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_179 = 5'hf == outpos_1 ? mem_15_data : _GEN_178; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_180 = 5'h10 == outpos_1 ? mem_16_data : _GEN_179; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_181 = 5'h11 == outpos_1 ? mem_17_data : _GEN_180; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_182 = 5'h12 == outpos_1 ? mem_18_data : _GEN_181; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_183 = 5'h13 == outpos_1 ? mem_19_data : _GEN_182; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_184 = 5'h14 == outpos_1 ? mem_20_data : _GEN_183; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_185 = 5'h15 == outpos_1 ? mem_21_data : _GEN_184; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_186 = 5'h16 == outpos_1 ? mem_22_data : _GEN_185; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_189 = 5'h1 == outpos_1 ? mem_1_addr : mem_0_addr; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_190 = 5'h2 == outpos_1 ? mem_2_addr : _GEN_189; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_191 = 5'h3 == outpos_1 ? mem_3_addr : _GEN_190; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_192 = 5'h4 == outpos_1 ? mem_4_addr : _GEN_191; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_193 = 5'h5 == outpos_1 ? mem_5_addr : _GEN_192; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_194 = 5'h6 == outpos_1 ? mem_6_addr : _GEN_193; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_195 = 5'h7 == outpos_1 ? mem_7_addr : _GEN_194; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_196 = 5'h8 == outpos_1 ? mem_8_addr : _GEN_195; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_197 = 5'h9 == outpos_1 ? mem_9_addr : _GEN_196; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_198 = 5'ha == outpos_1 ? mem_10_addr : _GEN_197; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_199 = 5'hb == outpos_1 ? mem_11_addr : _GEN_198; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_200 = 5'hc == outpos_1 ? mem_12_addr : _GEN_199; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_201 = 5'hd == outpos_1 ? mem_13_addr : _GEN_200; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_202 = 5'he == outpos_1 ? mem_14_addr : _GEN_201; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_203 = 5'hf == outpos_1 ? mem_15_addr : _GEN_202; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_204 = 5'h10 == outpos_1 ? mem_16_addr : _GEN_203; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_205 = 5'h11 == outpos_1 ? mem_17_addr : _GEN_204; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_206 = 5'h12 == outpos_1 ? mem_18_addr : _GEN_205; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_207 = 5'h13 == outpos_1 ? mem_19_addr : _GEN_206; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_208 = 5'h14 == outpos_1 ? mem_20_addr : _GEN_207; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_209 = 5'h15 == outpos_1 ? mem_21_addr : _GEN_208; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_210 = 5'h16 == outpos_1 ? mem_22_addr : _GEN_209; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_213 = 5'h1 == outpos_1 ? mem_1_inst : mem_0_inst; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_214 = 5'h2 == outpos_1 ? mem_2_inst : _GEN_213; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_215 = 5'h3 == outpos_1 ? mem_3_inst : _GEN_214; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_216 = 5'h4 == outpos_1 ? mem_4_inst : _GEN_215; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_217 = 5'h5 == outpos_1 ? mem_5_inst : _GEN_216; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_218 = 5'h6 == outpos_1 ? mem_6_inst : _GEN_217; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_219 = 5'h7 == outpos_1 ? mem_7_inst : _GEN_218; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_220 = 5'h8 == outpos_1 ? mem_8_inst : _GEN_219; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_221 = 5'h9 == outpos_1 ? mem_9_inst : _GEN_220; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_222 = 5'ha == outpos_1 ? mem_10_inst : _GEN_221; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_223 = 5'hb == outpos_1 ? mem_11_inst : _GEN_222; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_224 = 5'hc == outpos_1 ? mem_12_inst : _GEN_223; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_225 = 5'hd == outpos_1 ? mem_13_inst : _GEN_224; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_226 = 5'he == outpos_1 ? mem_14_inst : _GEN_225; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_227 = 5'hf == outpos_1 ? mem_15_inst : _GEN_226; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_228 = 5'h10 == outpos_1 ? mem_16_inst : _GEN_227; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_229 = 5'h11 == outpos_1 ? mem_17_inst : _GEN_228; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_230 = 5'h12 == outpos_1 ? mem_18_inst : _GEN_229; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_231 = 5'h13 == outpos_1 ? mem_19_inst : _GEN_230; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_232 = 5'h14 == outpos_1 ? mem_20_inst : _GEN_231; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_233 = 5'h15 == outpos_1 ? mem_21_inst : _GEN_232; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_234 = 5'h16 == outpos_1 ? mem_22_inst : _GEN_233; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_237 = 5'h1 == outpos_2 ? mem_1_data : mem_0_data; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_238 = 5'h2 == outpos_2 ? mem_2_data : _GEN_237; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_239 = 5'h3 == outpos_2 ? mem_3_data : _GEN_238; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_240 = 5'h4 == outpos_2 ? mem_4_data : _GEN_239; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_241 = 5'h5 == outpos_2 ? mem_5_data : _GEN_240; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_242 = 5'h6 == outpos_2 ? mem_6_data : _GEN_241; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_243 = 5'h7 == outpos_2 ? mem_7_data : _GEN_242; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_244 = 5'h8 == outpos_2 ? mem_8_data : _GEN_243; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_245 = 5'h9 == outpos_2 ? mem_9_data : _GEN_244; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_246 = 5'ha == outpos_2 ? mem_10_data : _GEN_245; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_247 = 5'hb == outpos_2 ? mem_11_data : _GEN_246; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_248 = 5'hc == outpos_2 ? mem_12_data : _GEN_247; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_249 = 5'hd == outpos_2 ? mem_13_data : _GEN_248; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_250 = 5'he == outpos_2 ? mem_14_data : _GEN_249; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_251 = 5'hf == outpos_2 ? mem_15_data : _GEN_250; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_252 = 5'h10 == outpos_2 ? mem_16_data : _GEN_251; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_253 = 5'h11 == outpos_2 ? mem_17_data : _GEN_252; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_254 = 5'h12 == outpos_2 ? mem_18_data : _GEN_253; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_255 = 5'h13 == outpos_2 ? mem_19_data : _GEN_254; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_256 = 5'h14 == outpos_2 ? mem_20_data : _GEN_255; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_257 = 5'h15 == outpos_2 ? mem_21_data : _GEN_256; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_258 = 5'h16 == outpos_2 ? mem_22_data : _GEN_257; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_261 = 5'h1 == outpos_2 ? mem_1_addr : mem_0_addr; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_262 = 5'h2 == outpos_2 ? mem_2_addr : _GEN_261; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_263 = 5'h3 == outpos_2 ? mem_3_addr : _GEN_262; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_264 = 5'h4 == outpos_2 ? mem_4_addr : _GEN_263; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_265 = 5'h5 == outpos_2 ? mem_5_addr : _GEN_264; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_266 = 5'h6 == outpos_2 ? mem_6_addr : _GEN_265; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_267 = 5'h7 == outpos_2 ? mem_7_addr : _GEN_266; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_268 = 5'h8 == outpos_2 ? mem_8_addr : _GEN_267; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_269 = 5'h9 == outpos_2 ? mem_9_addr : _GEN_268; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_270 = 5'ha == outpos_2 ? mem_10_addr : _GEN_269; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_271 = 5'hb == outpos_2 ? mem_11_addr : _GEN_270; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_272 = 5'hc == outpos_2 ? mem_12_addr : _GEN_271; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_273 = 5'hd == outpos_2 ? mem_13_addr : _GEN_272; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_274 = 5'he == outpos_2 ? mem_14_addr : _GEN_273; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_275 = 5'hf == outpos_2 ? mem_15_addr : _GEN_274; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_276 = 5'h10 == outpos_2 ? mem_16_addr : _GEN_275; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_277 = 5'h11 == outpos_2 ? mem_17_addr : _GEN_276; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_278 = 5'h12 == outpos_2 ? mem_18_addr : _GEN_277; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_279 = 5'h13 == outpos_2 ? mem_19_addr : _GEN_278; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_280 = 5'h14 == outpos_2 ? mem_20_addr : _GEN_279; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_281 = 5'h15 == outpos_2 ? mem_21_addr : _GEN_280; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_282 = 5'h16 == outpos_2 ? mem_22_addr : _GEN_281; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_285 = 5'h1 == outpos_2 ? mem_1_inst : mem_0_inst; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_286 = 5'h2 == outpos_2 ? mem_2_inst : _GEN_285; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_287 = 5'h3 == outpos_2 ? mem_3_inst : _GEN_286; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_288 = 5'h4 == outpos_2 ? mem_4_inst : _GEN_287; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_289 = 5'h5 == outpos_2 ? mem_5_inst : _GEN_288; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_290 = 5'h6 == outpos_2 ? mem_6_inst : _GEN_289; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_291 = 5'h7 == outpos_2 ? mem_7_inst : _GEN_290; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_292 = 5'h8 == outpos_2 ? mem_8_inst : _GEN_291; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_293 = 5'h9 == outpos_2 ? mem_9_inst : _GEN_292; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_294 = 5'ha == outpos_2 ? mem_10_inst : _GEN_293; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_295 = 5'hb == outpos_2 ? mem_11_inst : _GEN_294; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_296 = 5'hc == outpos_2 ? mem_12_inst : _GEN_295; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_297 = 5'hd == outpos_2 ? mem_13_inst : _GEN_296; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_298 = 5'he == outpos_2 ? mem_14_inst : _GEN_297; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_299 = 5'hf == outpos_2 ? mem_15_inst : _GEN_298; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_300 = 5'h10 == outpos_2 ? mem_16_inst : _GEN_299; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_301 = 5'h11 == outpos_2 ? mem_17_inst : _GEN_300; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_302 = 5'h12 == outpos_2 ? mem_18_inst : _GEN_301; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_303 = 5'h13 == outpos_2 ? mem_19_inst : _GEN_302; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_304 = 5'h14 == outpos_2 ? mem_20_inst : _GEN_303; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_305 = 5'h15 == outpos_2 ? mem_21_inst : _GEN_304; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_306 = 5'h16 == outpos_2 ? mem_22_inst : _GEN_305; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_309 = 5'h1 == outpos_3 ? mem_1_data : mem_0_data; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_310 = 5'h2 == outpos_3 ? mem_2_data : _GEN_309; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_311 = 5'h3 == outpos_3 ? mem_3_data : _GEN_310; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_312 = 5'h4 == outpos_3 ? mem_4_data : _GEN_311; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_313 = 5'h5 == outpos_3 ? mem_5_data : _GEN_312; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_314 = 5'h6 == outpos_3 ? mem_6_data : _GEN_313; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_315 = 5'h7 == outpos_3 ? mem_7_data : _GEN_314; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_316 = 5'h8 == outpos_3 ? mem_8_data : _GEN_315; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_317 = 5'h9 == outpos_3 ? mem_9_data : _GEN_316; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_318 = 5'ha == outpos_3 ? mem_10_data : _GEN_317; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_319 = 5'hb == outpos_3 ? mem_11_data : _GEN_318; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_320 = 5'hc == outpos_3 ? mem_12_data : _GEN_319; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_321 = 5'hd == outpos_3 ? mem_13_data : _GEN_320; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_322 = 5'he == outpos_3 ? mem_14_data : _GEN_321; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_323 = 5'hf == outpos_3 ? mem_15_data : _GEN_322; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_324 = 5'h10 == outpos_3 ? mem_16_data : _GEN_323; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_325 = 5'h11 == outpos_3 ? mem_17_data : _GEN_324; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_326 = 5'h12 == outpos_3 ? mem_18_data : _GEN_325; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_327 = 5'h13 == outpos_3 ? mem_19_data : _GEN_326; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_328 = 5'h14 == outpos_3 ? mem_20_data : _GEN_327; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_329 = 5'h15 == outpos_3 ? mem_21_data : _GEN_328; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_330 = 5'h16 == outpos_3 ? mem_22_data : _GEN_329; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_333 = 5'h1 == outpos_3 ? mem_1_addr : mem_0_addr; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_334 = 5'h2 == outpos_3 ? mem_2_addr : _GEN_333; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_335 = 5'h3 == outpos_3 ? mem_3_addr : _GEN_334; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_336 = 5'h4 == outpos_3 ? mem_4_addr : _GEN_335; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_337 = 5'h5 == outpos_3 ? mem_5_addr : _GEN_336; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_338 = 5'h6 == outpos_3 ? mem_6_addr : _GEN_337; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_339 = 5'h7 == outpos_3 ? mem_7_addr : _GEN_338; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_340 = 5'h8 == outpos_3 ? mem_8_addr : _GEN_339; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_341 = 5'h9 == outpos_3 ? mem_9_addr : _GEN_340; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_342 = 5'ha == outpos_3 ? mem_10_addr : _GEN_341; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_343 = 5'hb == outpos_3 ? mem_11_addr : _GEN_342; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_344 = 5'hc == outpos_3 ? mem_12_addr : _GEN_343; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_345 = 5'hd == outpos_3 ? mem_13_addr : _GEN_344; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_346 = 5'he == outpos_3 ? mem_14_addr : _GEN_345; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_347 = 5'hf == outpos_3 ? mem_15_addr : _GEN_346; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_348 = 5'h10 == outpos_3 ? mem_16_addr : _GEN_347; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_349 = 5'h11 == outpos_3 ? mem_17_addr : _GEN_348; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_350 = 5'h12 == outpos_3 ? mem_18_addr : _GEN_349; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_351 = 5'h13 == outpos_3 ? mem_19_addr : _GEN_350; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_352 = 5'h14 == outpos_3 ? mem_20_addr : _GEN_351; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_353 = 5'h15 == outpos_3 ? mem_21_addr : _GEN_352; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_354 = 5'h16 == outpos_3 ? mem_22_addr : _GEN_353; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_357 = 5'h1 == outpos_3 ? mem_1_inst : mem_0_inst; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_358 = 5'h2 == outpos_3 ? mem_2_inst : _GEN_357; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_359 = 5'h3 == outpos_3 ? mem_3_inst : _GEN_358; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_360 = 5'h4 == outpos_3 ? mem_4_inst : _GEN_359; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_361 = 5'h5 == outpos_3 ? mem_5_inst : _GEN_360; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_362 = 5'h6 == outpos_3 ? mem_6_inst : _GEN_361; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_363 = 5'h7 == outpos_3 ? mem_7_inst : _GEN_362; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_364 = 5'h8 == outpos_3 ? mem_8_inst : _GEN_363; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_365 = 5'h9 == outpos_3 ? mem_9_inst : _GEN_364; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_366 = 5'ha == outpos_3 ? mem_10_inst : _GEN_365; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_367 = 5'hb == outpos_3 ? mem_11_inst : _GEN_366; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_368 = 5'hc == outpos_3 ? mem_12_inst : _GEN_367; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_369 = 5'hd == outpos_3 ? mem_13_inst : _GEN_368; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_370 = 5'he == outpos_3 ? mem_14_inst : _GEN_369; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_371 = 5'hf == outpos_3 ? mem_15_inst : _GEN_370; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_372 = 5'h10 == outpos_3 ? mem_16_inst : _GEN_371; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_373 = 5'h11 == outpos_3 ? mem_17_inst : _GEN_372; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_374 = 5'h12 == outpos_3 ? mem_18_inst : _GEN_373; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_375 = 5'h13 == outpos_3 ? mem_19_inst : _GEN_374; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_376 = 5'h14 == outpos_3 ? mem_20_inst : _GEN_375; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_377 = 5'h15 == outpos_3 ? mem_21_inst : _GEN_376; // @[Fifo4x4.scala 185:{20,20}]
- wire [31:0] _GEN_378 = 5'h16 == outpos_3 ? mem_22_inst : _GEN_377; // @[Fifo4x4.scala 185:{20,20}]
- assign io_in_ready = inready; // @[Fifo4x4.scala 181:15]
- assign io_out_0_valid = outvalid[0]; // @[Fifo4x4.scala 184:32]
- assign io_out_0_bits_inst = 5'h17 == outpos_0 ? mem_23_inst : _GEN_162; // @[Fifo4x4.scala 185:{20,20}]
- assign io_out_0_bits_addr = 5'h17 == outpos_0 ? mem_23_addr : _GEN_138; // @[Fifo4x4.scala 185:{20,20}]
- assign io_out_0_bits_data = 5'h17 == outpos_0 ? mem_23_data : _GEN_114; // @[Fifo4x4.scala 185:{20,20}]
- assign io_out_1_valid = outvalid[1]; // @[Fifo4x4.scala 184:32]
- assign io_out_1_bits_inst = 5'h17 == outpos_1 ? mem_23_inst : _GEN_234; // @[Fifo4x4.scala 185:{20,20}]
- assign io_out_1_bits_addr = 5'h17 == outpos_1 ? mem_23_addr : _GEN_210; // @[Fifo4x4.scala 185:{20,20}]
- assign io_out_1_bits_data = 5'h17 == outpos_1 ? mem_23_data : _GEN_186; // @[Fifo4x4.scala 185:{20,20}]
- assign io_out_2_valid = outvalid[2]; // @[Fifo4x4.scala 184:32]
- assign io_out_2_bits_inst = 5'h17 == outpos_2 ? mem_23_inst : _GEN_306; // @[Fifo4x4.scala 185:{20,20}]
- assign io_out_2_bits_addr = 5'h17 == outpos_2 ? mem_23_addr : _GEN_282; // @[Fifo4x4.scala 185:{20,20}]
- assign io_out_2_bits_data = 5'h17 == outpos_2 ? mem_23_data : _GEN_258; // @[Fifo4x4.scala 185:{20,20}]
- assign io_out_3_valid = outvalid[3]; // @[Fifo4x4.scala 184:32]
- assign io_out_3_bits_inst = 5'h17 == outpos_3 ? mem_23_inst : _GEN_378; // @[Fifo4x4.scala 185:{20,20}]
- assign io_out_3_bits_addr = 5'h17 == outpos_3 ? mem_23_addr : _GEN_354; // @[Fifo4x4.scala 185:{20,20}]
- assign io_out_3_bits_data = 5'h17 == outpos_3 ? mem_23_data : _GEN_330; // @[Fifo4x4.scala 185:{20,20}]
- assign io_count = mcount; // @[Fifo4x4.scala 188:12]
- assign io_nempty = nempty; // @[Fifo4x4.scala 190:13]
- always @(posedge clock) begin
- if (ivalid & valid != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_0_inst <= data[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_0_addr <= data[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_0_data <= data[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_1 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_1_inst <= data_1[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_1 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_1_addr <= data_1[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_1 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_1_data <= data_1[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_2 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_2_inst <= data_2[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_2 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_2_addr <= data_2[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_2 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_2_data <= data_2[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_3 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_3_inst <= data_3[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_3 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_3_addr <= data_3[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_3 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_3_data <= data_3[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_4 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_4_inst <= data_4[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_4 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_4_addr <= data_4[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_4 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_4_data <= data_4[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_5 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_5_inst <= data_5[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_5 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_5_addr <= data_5[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_5 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_5_data <= data_5[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_6 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_6_inst <= data_6[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_6 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_6_addr <= data_6[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_6 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_6_data <= data_6[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_7 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_7_inst <= data_7[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_7 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_7_addr <= data_7[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_7 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_7_data <= data_7[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_8 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_8_inst <= data_8[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_8 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_8_addr <= data_8[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_8 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_8_data <= data_8[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_9 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_9_inst <= data_9[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_9 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_9_addr <= data_9[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_9 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_9_data <= data_9[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_10 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_10_inst <= data_10[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_10 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_10_addr <= data_10[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_10 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_10_data <= data_10[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_11 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_11_inst <= data_11[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_11 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_11_addr <= data_11[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_11 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_11_data <= data_11[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_12 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_12_inst <= data_12[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_12 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_12_addr <= data_12[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_12 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_12_data <= data_12[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_13 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_13_inst <= data_13[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_13 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_13_addr <= data_13[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_13 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_13_data <= data_13[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_14 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_14_inst <= data_14[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_14 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_14_addr <= data_14[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_14 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_14_data <= data_14[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_15 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_15_inst <= data_15[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_15 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_15_addr <= data_15[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_15 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_15_data <= data_15[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_16 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_16_inst <= data_16[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_16 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_16_addr <= data_16[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_16 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_16_data <= data_16[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_17 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_17_inst <= data_17[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_17 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_17_addr <= data_17[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_17 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_17_data <= data_17[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_18 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_18_inst <= data_18[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_18 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_18_addr <= data_18[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_18 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_18_data <= data_18[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_19 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_19_inst <= data_19[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_19 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_19_addr <= data_19[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_19 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_19_data <= data_19[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_20 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_20_inst <= data_20[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_20 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_20_addr <= data_20[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_20 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_20_data <= data_20[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_21 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_21_inst <= data_21[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_21 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_21_addr <= data_21[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_21 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_21_data <= data_21[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_22 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_22_inst <= data_22[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_22 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_22_addr <= data_22[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_22 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_22_data <= data_22[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_23 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_23_inst <= data_23[95:64]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_23 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_23_addr <= data_23[63:32]; // @[Fifo4x4.scala 162:16]
- end
- if (ivalid & valid_23 != 4'h0) begin // @[Fifo4x4.scala 161:38]
- mem_23_data <= data_23[31:0]; // @[Fifo4x4.scala 162:16]
- end
- if (reset) begin // @[Fifo4x4.scala 96:23]
- inpos_0 <= 5'h0; // @[Fifo4x4.scala 98:16]
- end else if (ivalid) begin // @[Fifo4x4.scala 100:24]
- inpos_0 <= inpos_0_d; // @[Fifo4x4.scala 102:16]
- end
- if (reset) begin // @[Fifo4x4.scala 96:23]
- inpos_1 <= 5'h1; // @[Fifo4x4.scala 98:16]
- end else if (ivalid) begin // @[Fifo4x4.scala 100:24]
- inpos_1 <= inpos_1_d; // @[Fifo4x4.scala 102:16]
- end
- if (reset) begin // @[Fifo4x4.scala 96:23]
- inpos_2 <= 5'h2; // @[Fifo4x4.scala 98:16]
- end else if (ivalid) begin // @[Fifo4x4.scala 100:24]
- inpos_2 <= inpos_2_d; // @[Fifo4x4.scala 102:16]
- end
- if (reset) begin // @[Fifo4x4.scala 96:23]
- inpos_3 <= 5'h3; // @[Fifo4x4.scala 98:16]
- end else if (ivalid) begin // @[Fifo4x4.scala 100:24]
- inpos_3 <= inpos_3_d; // @[Fifo4x4.scala 102:16]
- end
- if (reset) begin // @[Fifo4x4.scala 106:23]
- outpos_0 <= 5'h0; // @[Fifo4x4.scala 108:17]
- end else if (ovalid) begin // @[Fifo4x4.scala 110:24]
- outpos_0 <= outpos_0_d; // @[Fifo4x4.scala 112:17]
- end
- if (reset) begin // @[Fifo4x4.scala 106:23]
- outpos_1 <= 5'h1; // @[Fifo4x4.scala 108:17]
- end else if (ovalid) begin // @[Fifo4x4.scala 110:24]
- outpos_1 <= outpos_1_d; // @[Fifo4x4.scala 112:17]
- end
- if (reset) begin // @[Fifo4x4.scala 106:23]
- outpos_2 <= 5'h2; // @[Fifo4x4.scala 108:17]
- end else if (ovalid) begin // @[Fifo4x4.scala 110:24]
- outpos_2 <= outpos_2_d; // @[Fifo4x4.scala 112:17]
- end
- if (reset) begin // @[Fifo4x4.scala 106:23]
- outpos_3 <= 5'h3; // @[Fifo4x4.scala 108:17]
- end else if (ovalid) begin // @[Fifo4x4.scala 110:24]
- outpos_3 <= outpos_3_d; // @[Fifo4x4.scala 112:17]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(oactiveBits[1] & ~oactiveBits[0]))) begin
- $fatal; // @[Fifo4x4.scala 76:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(oactiveBits[1] & ~oactiveBits[0]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fifo4x4.scala:76 assert(!(oactiveBits(1) === 1.U && oactiveBits(0,0) =/= 1.U))\n"
- ); // @[Fifo4x4.scala 76:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(oactiveBits[2] & oactiveBits[1:0] != 2'h3))) begin
- $fatal; // @[Fifo4x4.scala 77:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(oactiveBits[2] & oactiveBits[1:0] != 2'h3))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fifo4x4.scala:77 assert(!(oactiveBits(2) === 1.U && oactiveBits(1,0) =/= 3.U))\n"
- ); // @[Fifo4x4.scala 77:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(oactiveBits[3] & oactiveBits[2:0] != 3'h7))) begin
- $fatal; // @[Fifo4x4.scala 78:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(oactiveBits[3] & oactiveBits[2:0] != 3'h7))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fifo4x4.scala:78 assert(!(oactiveBits(3) === 1.U && oactiveBits(2,0) =/= 7.U))\n"
- ); // @[Fifo4x4.scala 78:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(ovalidBits[1] & ~ovalidBits[0]))) begin
- $fatal; // @[Fifo4x4.scala 83:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(ovalidBits[1] & ~ovalidBits[0]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fifo4x4.scala:83 assert(!(ovalidBits(1) === 1.U && ovalidBits(0,0) =/= 1.U))\n"); // @[Fifo4x4.scala 83:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(ovalidBits[2] & ovalidBits[1:0] != 2'h3))) begin
- $fatal; // @[Fifo4x4.scala 84:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(ovalidBits[2] & ovalidBits[1:0] != 2'h3))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fifo4x4.scala:84 assert(!(ovalidBits(2) === 1.U && ovalidBits(1,0) =/= 3.U))\n"); // @[Fifo4x4.scala 84:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(ovalidBits[3] & ovalidBits[2:0] != 3'h7))) begin
- $fatal; // @[Fifo4x4.scala 85:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(ovalidBits[3] & ovalidBits[2:0] != 3'h7))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fifo4x4.scala:85 assert(!(ovalidBits(3) === 1.U && ovalidBits(2,0) =/= 7.U))\n"); // @[Fifo4x4.scala 85:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(oreadyBits[1] & ~oreadyBits[0]))) begin
- $fatal; // @[Fifo4x4.scala 90:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(oreadyBits[1] & ~oreadyBits[0]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fifo4x4.scala:90 assert(!(oreadyBits(1) === 1.U && oreadyBits(0,0) =/= 1.U))\n"); // @[Fifo4x4.scala 90:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(oreadyBits[2] & oreadyBits[1:0] != 2'h3))) begin
- $fatal; // @[Fifo4x4.scala 91:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(oreadyBits[2] & oreadyBits[1:0] != 2'h3))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fifo4x4.scala:91 assert(!(oreadyBits(2) === 1.U && oreadyBits(1,0) =/= 3.U))\n"); // @[Fifo4x4.scala 91:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(oreadyBits[3] & oreadyBits[2:0] != 3'h7))) begin
- $fatal; // @[Fifo4x4.scala 92:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(oreadyBits[3] & oreadyBits[2:0] != 3'h7))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fifo4x4.scala:92 assert(!(oreadyBits(3) === 1.U && oreadyBits(2,0) =/= 7.U))\n"); // @[Fifo4x4.scala 92:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(io_count <= 5'h18)) begin
- $fatal; // @[Fifo4x4.scala 192:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(io_count <= 5'h18)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Fifo4x4.scala:192 assert(io.count <= m.U)\n"); // @[Fifo4x4.scala 192:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4x4.scala 119:27]
- mcount <= 5'h0; // @[Fifo4x4.scala 122:12]
- end else if (ivalid | ovalid) begin // @[Fifo4x4.scala 53:23]
- mcount <= nxtmcount;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4x4.scala 119:27]
- nempty <= 1'h0; // @[Fifo4x4.scala 123:12]
- end else if (ivalid | ovalid) begin // @[Fifo4x4.scala 54:23]
- nempty <= nxtmcount != 5'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4x4.scala 119:27]
- inready <= 1'h0; // @[Fifo4x4.scala 121:13]
- end else if (ivalid | ovalid) begin // @[Fifo4x4.scala 129:13]
- inready <= nxtmcount <= _inready_T_1;
- end else begin
- inready <= mcount <= _inready_T_1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4x4.scala 119:27]
- outvalid <= 4'h0; // @[Fifo4x4.scala 124:14]
- end else if (ivalid | ovalid) begin // @[Fifo4x4.scala 130:14]
- outvalid <= _outvalid_T_4;
- end else begin
- outvalid <= _outvalid_T_9;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- mem_0_inst = _RAND_0[31:0];
- _RAND_1 = {1{`RANDOM}};
- mem_0_addr = _RAND_1[31:0];
- _RAND_2 = {1{`RANDOM}};
- mem_0_data = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- mem_1_inst = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- mem_1_addr = _RAND_4[31:0];
- _RAND_5 = {1{`RANDOM}};
- mem_1_data = _RAND_5[31:0];
- _RAND_6 = {1{`RANDOM}};
- mem_2_inst = _RAND_6[31:0];
- _RAND_7 = {1{`RANDOM}};
- mem_2_addr = _RAND_7[31:0];
- _RAND_8 = {1{`RANDOM}};
- mem_2_data = _RAND_8[31:0];
- _RAND_9 = {1{`RANDOM}};
- mem_3_inst = _RAND_9[31:0];
- _RAND_10 = {1{`RANDOM}};
- mem_3_addr = _RAND_10[31:0];
- _RAND_11 = {1{`RANDOM}};
- mem_3_data = _RAND_11[31:0];
- _RAND_12 = {1{`RANDOM}};
- mem_4_inst = _RAND_12[31:0];
- _RAND_13 = {1{`RANDOM}};
- mem_4_addr = _RAND_13[31:0];
- _RAND_14 = {1{`RANDOM}};
- mem_4_data = _RAND_14[31:0];
- _RAND_15 = {1{`RANDOM}};
- mem_5_inst = _RAND_15[31:0];
- _RAND_16 = {1{`RANDOM}};
- mem_5_addr = _RAND_16[31:0];
- _RAND_17 = {1{`RANDOM}};
- mem_5_data = _RAND_17[31:0];
- _RAND_18 = {1{`RANDOM}};
- mem_6_inst = _RAND_18[31:0];
- _RAND_19 = {1{`RANDOM}};
- mem_6_addr = _RAND_19[31:0];
- _RAND_20 = {1{`RANDOM}};
- mem_6_data = _RAND_20[31:0];
- _RAND_21 = {1{`RANDOM}};
- mem_7_inst = _RAND_21[31:0];
- _RAND_22 = {1{`RANDOM}};
- mem_7_addr = _RAND_22[31:0];
- _RAND_23 = {1{`RANDOM}};
- mem_7_data = _RAND_23[31:0];
- _RAND_24 = {1{`RANDOM}};
- mem_8_inst = _RAND_24[31:0];
- _RAND_25 = {1{`RANDOM}};
- mem_8_addr = _RAND_25[31:0];
- _RAND_26 = {1{`RANDOM}};
- mem_8_data = _RAND_26[31:0];
- _RAND_27 = {1{`RANDOM}};
- mem_9_inst = _RAND_27[31:0];
- _RAND_28 = {1{`RANDOM}};
- mem_9_addr = _RAND_28[31:0];
- _RAND_29 = {1{`RANDOM}};
- mem_9_data = _RAND_29[31:0];
- _RAND_30 = {1{`RANDOM}};
- mem_10_inst = _RAND_30[31:0];
- _RAND_31 = {1{`RANDOM}};
- mem_10_addr = _RAND_31[31:0];
- _RAND_32 = {1{`RANDOM}};
- mem_10_data = _RAND_32[31:0];
- _RAND_33 = {1{`RANDOM}};
- mem_11_inst = _RAND_33[31:0];
- _RAND_34 = {1{`RANDOM}};
- mem_11_addr = _RAND_34[31:0];
- _RAND_35 = {1{`RANDOM}};
- mem_11_data = _RAND_35[31:0];
- _RAND_36 = {1{`RANDOM}};
- mem_12_inst = _RAND_36[31:0];
- _RAND_37 = {1{`RANDOM}};
- mem_12_addr = _RAND_37[31:0];
- _RAND_38 = {1{`RANDOM}};
- mem_12_data = _RAND_38[31:0];
- _RAND_39 = {1{`RANDOM}};
- mem_13_inst = _RAND_39[31:0];
- _RAND_40 = {1{`RANDOM}};
- mem_13_addr = _RAND_40[31:0];
- _RAND_41 = {1{`RANDOM}};
- mem_13_data = _RAND_41[31:0];
- _RAND_42 = {1{`RANDOM}};
- mem_14_inst = _RAND_42[31:0];
- _RAND_43 = {1{`RANDOM}};
- mem_14_addr = _RAND_43[31:0];
- _RAND_44 = {1{`RANDOM}};
- mem_14_data = _RAND_44[31:0];
- _RAND_45 = {1{`RANDOM}};
- mem_15_inst = _RAND_45[31:0];
- _RAND_46 = {1{`RANDOM}};
- mem_15_addr = _RAND_46[31:0];
- _RAND_47 = {1{`RANDOM}};
- mem_15_data = _RAND_47[31:0];
- _RAND_48 = {1{`RANDOM}};
- mem_16_inst = _RAND_48[31:0];
- _RAND_49 = {1{`RANDOM}};
- mem_16_addr = _RAND_49[31:0];
- _RAND_50 = {1{`RANDOM}};
- mem_16_data = _RAND_50[31:0];
- _RAND_51 = {1{`RANDOM}};
- mem_17_inst = _RAND_51[31:0];
- _RAND_52 = {1{`RANDOM}};
- mem_17_addr = _RAND_52[31:0];
- _RAND_53 = {1{`RANDOM}};
- mem_17_data = _RAND_53[31:0];
- _RAND_54 = {1{`RANDOM}};
- mem_18_inst = _RAND_54[31:0];
- _RAND_55 = {1{`RANDOM}};
- mem_18_addr = _RAND_55[31:0];
- _RAND_56 = {1{`RANDOM}};
- mem_18_data = _RAND_56[31:0];
- _RAND_57 = {1{`RANDOM}};
- mem_19_inst = _RAND_57[31:0];
- _RAND_58 = {1{`RANDOM}};
- mem_19_addr = _RAND_58[31:0];
- _RAND_59 = {1{`RANDOM}};
- mem_19_data = _RAND_59[31:0];
- _RAND_60 = {1{`RANDOM}};
- mem_20_inst = _RAND_60[31:0];
- _RAND_61 = {1{`RANDOM}};
- mem_20_addr = _RAND_61[31:0];
- _RAND_62 = {1{`RANDOM}};
- mem_20_data = _RAND_62[31:0];
- _RAND_63 = {1{`RANDOM}};
- mem_21_inst = _RAND_63[31:0];
- _RAND_64 = {1{`RANDOM}};
- mem_21_addr = _RAND_64[31:0];
- _RAND_65 = {1{`RANDOM}};
- mem_21_data = _RAND_65[31:0];
- _RAND_66 = {1{`RANDOM}};
- mem_22_inst = _RAND_66[31:0];
- _RAND_67 = {1{`RANDOM}};
- mem_22_addr = _RAND_67[31:0];
- _RAND_68 = {1{`RANDOM}};
- mem_22_data = _RAND_68[31:0];
- _RAND_69 = {1{`RANDOM}};
- mem_23_inst = _RAND_69[31:0];
- _RAND_70 = {1{`RANDOM}};
- mem_23_addr = _RAND_70[31:0];
- _RAND_71 = {1{`RANDOM}};
- mem_23_data = _RAND_71[31:0];
- _RAND_72 = {1{`RANDOM}};
- inpos_0 = _RAND_72[4:0];
- _RAND_73 = {1{`RANDOM}};
- inpos_1 = _RAND_73[4:0];
- _RAND_74 = {1{`RANDOM}};
- inpos_2 = _RAND_74[4:0];
- _RAND_75 = {1{`RANDOM}};
- inpos_3 = _RAND_75[4:0];
- _RAND_76 = {1{`RANDOM}};
- outpos_0 = _RAND_76[4:0];
- _RAND_77 = {1{`RANDOM}};
- outpos_1 = _RAND_77[4:0];
- _RAND_78 = {1{`RANDOM}};
- outpos_2 = _RAND_78[4:0];
- _RAND_79 = {1{`RANDOM}};
- outpos_3 = _RAND_79[4:0];
- _RAND_80 = {1{`RANDOM}};
- mcount = _RAND_80[4:0];
- _RAND_81 = {1{`RANDOM}};
- nempty = _RAND_81[0:0];
- _RAND_82 = {1{`RANDOM}};
- inready = _RAND_82[0:0];
- _RAND_83 = {1{`RANDOM}};
- outvalid = _RAND_83[3:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- mcount = 5'h0;
- end
- if (reset) begin
- nempty = 1'h0;
- end
- if (reset) begin
- inready = 1'h0;
- end
- if (reset) begin
- outvalid = 4'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VDecodeInstruction(
- input clock,
- input reset,
- input [31:0] io_in_inst,
- input [31:0] io_in_addr,
- input [31:0] io_in_data,
- output [6:0] io_out_op,
- output [2:0] io_out_f2,
- output [2:0] io_out_sz,
- output io_out_m,
- output io_out_vd_valid,
- output [5:0] io_out_vd_addr,
- output [5:0] io_out_ve_addr,
- output [5:0] io_out_vf_addr,
- output [5:0] io_out_vg_addr,
- output io_out_vs_valid,
- output [5:0] io_out_vs_addr,
- output io_out_vt_valid,
- output [5:0] io_out_vt_addr,
- output io_out_vu_valid,
- output [5:0] io_out_vu_addr,
- output io_out_vx_valid,
- output [5:0] io_out_vx_addr,
- output io_out_vy_valid,
- output [5:0] io_out_vy_addr,
- output io_out_vz_valid,
- output [5:0] io_out_vz_addr,
- output io_out_sv_valid,
- output [31:0] io_out_sv_addr,
- output [31:0] io_out_sv_data,
- output io_out_cmdsync,
- output io_cmdq_alu,
- output io_cmdq_conv,
- output io_cmdq_ldst,
- output io_cmdq_ld,
- output io_cmdq_st,
- output [63:0] io_actv_ractive,
- output [63:0] io_actv_wactive,
- output io_undef
-);
- wire v = io_in_inst[0]; // @[VDecodeInstruction.scala 42:19]
- wire x = io_in_inst[1]; // @[VDecodeInstruction.scala 43:19]
- wire x3 = io_in_inst[2]; // @[VDecodeInstruction.scala 44:19]
- wire [2:0] func1 = io_in_inst[4:2]; // @[VDecodeInstruction.scala 45:19]
- wire m = io_in_inst[5]; // @[VDecodeInstruction.scala 46:19]
- wire [1:0] sz = io_in_inst[13:12]; // @[VDecodeInstruction.scala 47:19]
- wire [5:0] func2 = io_in_inst[31:26]; // @[VDecodeInstruction.scala 48:19]
- wire [5:0] vdbits = io_in_inst[11:6]; // @[VDecodeInstruction.scala 50:20]
- wire [5:0] vsbits = io_in_inst[19:14]; // @[VDecodeInstruction.scala 51:20]
- wire [5:0] vtbits = io_in_inst[25:20]; // @[VDecodeInstruction.scala 52:20]
- wire quad = m & x; // @[VDecodeInstruction.scala 55:16]
- wire uncached = io_in_addr[31]; // @[VDecodeInstruction.scala 57:22]
- wire vdup_bit = ~io_in_inst[31]; // @[Library.scala 326:19]
- wire vdup_bit_1 = io_in_inst[30]; // @[Library.scala 329:23]
- wire _vdup_T_1 = vdup_bit & vdup_bit_1; // @[Library.scala 330:48]
- wire vdup_bit_2 = ~io_in_inst[29]; // @[Library.scala 326:19]
- wire _vdup_T_2 = _vdup_T_1 & vdup_bit_2; // @[Library.scala 327:48]
- wire vdup_bit_3 = ~io_in_inst[28]; // @[Library.scala 326:19]
- wire vdup_bit_4 = ~io_in_inst[27]; // @[Library.scala 326:19]
- wire vdup_bit_5 = io_in_inst[26]; // @[Library.scala 332:23]
- wire vdup_bit_6 = ~io_in_inst[25]; // @[Library.scala 326:19]
- wire vdup_bit_7 = io_in_inst[24]; // @[Library.scala 332:23]
- wire vdup_bit_8 = io_in_inst[23]; // @[Library.scala 332:23]
- wire vdup_bit_9 = io_in_inst[22]; // @[Library.scala 332:23]
- wire vdup_bit_10 = io_in_inst[21]; // @[Library.scala 332:23]
- wire vdup_bit_11 = io_in_inst[20]; // @[Library.scala 332:23]
- wire vdup_bit_12 = ~io_in_inst[19]; // @[Library.scala 326:19]
- wire vdup_bit_13 = ~io_in_inst[18]; // @[Library.scala 326:19]
- wire vdup_bit_14 = ~io_in_inst[17]; // @[Library.scala 326:19]
- wire vdup_bit_15 = ~io_in_inst[16]; // @[Library.scala 326:19]
- wire vdup_bit_16 = ~io_in_inst[15]; // @[Library.scala 326:19]
- wire vdup_bit_17 = ~io_in_inst[14]; // @[Library.scala 326:19]
- wire _vdup_T_11 = _vdup_T_1 & vdup_bit_2 & vdup_bit_3 & vdup_bit_4 & vdup_bit_6 & vdup_bit_12 & vdup_bit_13 &
- vdup_bit_14 & vdup_bit_15 & vdup_bit_16 & vdup_bit_17; // @[Library.scala 327:48]
- wire vdup_bit_18 = io_in_inst[13]; // @[Library.scala 332:23]
- wire vdup_bit_19 = io_in_inst[12]; // @[Library.scala 332:23]
- wire vdup_bit_27 = io_in_inst[4]; // @[Library.scala 329:23]
- wire vdup_bit_28 = io_in_inst[3]; // @[Library.scala 329:23]
- wire _vdup_T_16 = _vdup_T_11 & vdup_bit_27 & vdup_bit_28 & x3 & x & v; // @[Library.scala 330:48]
- wire _vdup_T_17 = sz < 2'h3; // @[VDecodeInstruction.scala 244:80]
- wire vdup = _vdup_T_16 & sz < 2'h3; // @[VDecodeInstruction.scala 244:74]
- wire vdupf2 = io_in_inst[31:27] == 5'h8; // @[VDecodeInstruction.scala 245:28]
- wire _vldstdec_T_1 = vdup_bit_6 & vdup_bit_17; // @[Library.scala 327:48]
- wire _vldstdec_T_6 = _vldstdec_T_1 & vdup_bit_27 & vdup_bit_28 & x3 & x & v; // @[Library.scala 330:48]
- wire vldstdec = _vldstdec_T_6 & _vdup_T_17 & ~vdupf2; // @[VDecodeInstruction.scala 248:90]
- wire _T_3 = ~reset; // @[VDecodeInstruction.scala 249:9]
- wire _vld_T = func2 == 6'h0; // @[VDecodeInstruction.scala 251:33]
- wire _vld_T_1 = func2 == 6'h1; // @[VDecodeInstruction.scala 251:50]
- wire _vld_T_3 = func2 == 6'h2; // @[VDecodeInstruction.scala 251:67]
- wire _vld_T_5 = func2 == 6'h4; // @[VDecodeInstruction.scala 252:33]
- wire _vld_T_6 = func2 == 6'h0 | func2 == 6'h1 | func2 == 6'h2 | _vld_T_5; // @[VDecodeInstruction.scala 251:75]
- wire _vld_T_7 = func2 == 6'h5; // @[VDecodeInstruction.scala 252:50]
- wire _vld_T_9 = func2 == 6'h6; // @[VDecodeInstruction.scala 252:67]
- wire _vld_T_11 = func2 == 6'h7; // @[VDecodeInstruction.scala 253:33]
- wire _vld_T_12 = _vld_T_6 | func2 == 6'h5 | func2 == 6'h6 | _vld_T_11; // @[VDecodeInstruction.scala 252:75]
- wire vld = vldstdec & _vld_T_12; // @[VDecodeInstruction.scala 251:23]
- wire _vst_T = func2 == 6'h8; // @[VDecodeInstruction.scala 255:33]
- wire _vst_T_1 = func2 == 6'h9; // @[VDecodeInstruction.scala 255:50]
- wire _vst_T_3 = func2 == 6'ha; // @[VDecodeInstruction.scala 255:67]
- wire _vst_T_5 = func2 == 6'hc; // @[VDecodeInstruction.scala 256:33]
- wire _vst_T_6 = func2 == 6'h8 | func2 == 6'h9 | func2 == 6'ha | _vst_T_5; // @[VDecodeInstruction.scala 255:76]
- wire _vst_T_7 = func2 == 6'hd; // @[VDecodeInstruction.scala 256:51]
- wire _vst_T_11 = func2 == 6'hf; // @[VDecodeInstruction.scala 257:33]
- wire _vst_T_12 = _vst_T_6 | func2 == 6'hd | func2 == 6'he | _vst_T_11; // @[VDecodeInstruction.scala 256:78]
- wire vst = vldstdec & _vst_T_12; // @[VDecodeInstruction.scala 255:23]
- wire _vstq_T = func2 == 6'h1a; // @[VDecodeInstruction.scala 259:33]
- wire vstq = vldstdec & (func2 == 6'h1a | func2 == 6'h1e); // @[VDecodeInstruction.scala 259:23]
- wire vldst = vld | vst | vstq; // @[VDecodeInstruction.scala 261:26]
- wire vadd = ~v & func1 == 3'h0 & _vld_T & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vsub = ~v & func1 == 3'h0 & _vld_T_1 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vrsub = ~v & func1 == 3'h0 & _vld_T_3 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire veq = ~v & func1 == 3'h0 & _vld_T_9 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vne = ~v & func1 == 3'h0 & _vld_T_11 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire [5:0] _vlt_T_3 = func2 & 6'h3e; // @[VDecodeInstruction.scala 62:43]
- wire vlt = ~v & func1 == 3'h0 & _vlt_T_3 == 6'h8 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vle = ~v & func1 == 3'h0 & _vlt_T_3 == 6'ha & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vgt = ~v & func1 == 3'h0 & _vlt_T_3 == 6'hc & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vge = ~v & func1 == 3'h0 & _vlt_T_3 == 6'he & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vabsd = ~v & func1 == 3'h0 & _vlt_T_3 == 6'h10 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vmax = ~v & func1 == 3'h0 & _vlt_T_3 == 6'h12 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vmin = ~v & func1 == 3'h0 & _vlt_T_3 == 6'h14 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vadd3 = ~v & func1 == 3'h0 & func2 == 6'h18 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vfmt0 = vadd | vsub | vrsub | veq | vne | vlt | vle | vgt | vge | vabsd | vmax | vmin | vadd3; // @[VDecodeInstruction.scala 278:104]
- wire vand = ~v & func1 == 3'h1 & _vld_T & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vor = ~v & func1 == 3'h1 & _vld_T_1 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vxor = ~v & func1 == 3'h1 & _vld_T_3 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vnot = ~v & func1 == 3'h1 & func2 == 6'h3 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vrev = ~v & func1 == 3'h1 & _vld_T_5 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vror = ~v & func1 == 3'h1 & _vld_T_7 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vclb = ~v & func1 == 3'h1 & _vst_T & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vclz = ~v & func1 == 3'h1 & _vst_T_1 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vcpop = ~v & func1 == 3'h1 & _vst_T_3 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire _vmv_T_8 = ~v & func1 == 3'h1 & _vst_T_5 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire _vmv_T_9 = ~quad; // @[VDecodeInstruction.scala 290:40]
- wire vmv = _vmv_T_8 & ~quad; // @[VDecodeInstruction.scala 290:37]
- wire vmv2 = _vmv_T_8 & quad; // @[VDecodeInstruction.scala 291:37]
- wire vmvp = ~v & func1 == 3'h1 & _vst_T_7 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vfmt1 = vand | vor | vxor | vnot | vrev | vror | vclb | vclz | vcpop | vmv | vmv2 | vmvp; // @[VDecodeInstruction.scala 294:99]
- wire _acset_T_8 = ~v & func1 == 3'h1 & func2 == 6'h10 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire _acset_T_10 = ~m; // @[VDecodeInstruction.scala 297:49]
- wire _acset_T_12 = vtbits == 6'h0; // @[VDecodeInstruction.scala 297:62]
- wire acset = _acset_T_8 & x & ~m & vtbits == 6'h0; // @[VDecodeInstruction.scala 297:52]
- wire _actr_T_8 = ~v & func1 == 3'h1 & func2 == 6'h11 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire actr = _actr_T_8 & x & _acset_T_10 & _acset_T_12; // @[VDecodeInstruction.scala 298:52]
- wire adwinit = ~v & func1 == 3'h1 & func2 == 6'h12 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vsll = ~v & func1 == 3'h2 & _vld_T_1 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vsra = ~v & func1 == 3'h2 & _vld_T_3 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vsrl = ~v & func1 == 3'h2 & func2 == 6'h3 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire [5:0] _vsha_T_3 = func2 & 6'h3d; // @[VDecodeInstruction.scala 62:43]
- wire vsha = ~v & func1 == 3'h2 & _vsha_T_3 == 6'h8 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vshl = ~v & func1 == 3'h2 & _vsha_T_3 == 6'h9 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire [5:0] _vsrans_T_3 = func2 & 6'h3c; // @[VDecodeInstruction.scala 62:43]
- wire vsrans = ~v & func1 == 3'h2 & _vsrans_T_3 == 6'h10 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vsraqs = ~v & func1 == 3'h2 & _vsrans_T_3 == 6'h18 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vfmt2 = vsll | vsra | vsrl | vsha | vshl | vsrans | vsraqs; // @[VDecodeInstruction.scala 310:62]
- wire _vmul_T_8 = ~v & func1 == 3'h3 & _vld_T & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vmul = _vmul_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 313:40]
- wire vmul2 = _vmul_T_8 & quad; // @[VDecodeInstruction.scala 314:40]
- wire _vmuls_T_8 = ~v & func1 == 3'h3 & _vlt_T_3 == 6'h2 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vmuls = _vmuls_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 315:44]
- wire vmuls2 = _vmuls_T_8 & quad; // @[VDecodeInstruction.scala 316:44]
- wire _vmulh_T_8 = ~v & func1 == 3'h3 & _vsha_T_3 == 6'h8 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vmulh = _vmulh_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 317:44]
- wire vmulh2 = _vmulh_T_8 & quad; // @[VDecodeInstruction.scala 318:44]
- wire _vmulhu_T_8 = ~v & func1 == 3'h3 & _vsha_T_3 == 6'h9 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vmulhu = _vmulhu_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 319:45]
- wire vmulhu2 = _vmulhu_T_8 & quad; // @[VDecodeInstruction.scala 320:45]
- wire _vdmulh_T_8 = ~v & func1 == 3'h3 & _vsrans_T_3 == 6'h10 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vdmulh = _vdmulh_T_8 & _vmv_T_9; // @[VDecodeInstruction.scala 321:45]
- wire vdmulh2 = _vdmulh_T_8 & quad; // @[VDecodeInstruction.scala 322:45]
- wire vmulw = ~v & func1 == 3'h3 & _vlt_T_3 == 6'h4 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vmacc = ~v & func1 == 3'h3 & func2 == 6'h14 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vmadd = ~v & func1 == 3'h3 & func2 == 6'h15 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vfmt3 = vmul | vmul2 | vmuls | vmuls2 | vmulh | vmulh2 | vmulhu | vmulhu2 | vdmulh | vdmulh2 | vmulw | vmacc |
- vmadd; // @[VDecodeInstruction.scala 327:127]
- wire vadds = ~v & func1 == 3'h4 & _vlt_T_3 == 6'h0 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vsubs = ~v & func1 == 3'h4 & _vlt_T_3 == 6'h2 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vaddw = ~v & func1 == 3'h4 & _vlt_T_3 == 6'h4 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vsubw = ~v & func1 == 3'h4 & _vlt_T_3 == 6'h6 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vacc = ~v & func1 == 3'h4 & _vlt_T_3 == 6'ha & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vpadd = ~v & func1 == 3'h4 & _vlt_T_3 == 6'hc & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vpsub = ~v & func1 == 3'h4 & _vlt_T_3 == 6'he & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vhadd = ~v & func1 == 3'h4 & _vsrans_T_3 == 6'h10 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vhsub = ~v & func1 == 3'h4 & _vsrans_T_3 == 6'h14 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vfmt4 = vadds | vsubs | vaddw | vsubw | vacc | vpadd | vpsub | vhadd | vhsub; // @[VDecodeInstruction.scala 340:83]
- wire vslidevn = ~v & func1 == 3'h6 & _vsrans_T_3 == 6'h0 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire _vslidehn_T_8 = ~v & func1 == 3'h6 & _vsrans_T_3 == 6'h4 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vslidehn = _vslidehn_T_8 & _acset_T_10; // @[VDecodeInstruction.scala 344:49]
- wire vslidehn2 = _vslidehn_T_8 & m; // @[VDecodeInstruction.scala 345:49]
- wire vslidevp = ~v & func1 == 3'h6 & _vsrans_T_3 == 6'h8 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire _vslidehp_T_8 = ~v & func1 == 3'h6 & _vsrans_T_3 == 6'hc & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vslidehp = _vslidehp_T_8 & _acset_T_10; // @[VDecodeInstruction.scala 347:49]
- wire vslidehp2 = _vslidehp_T_8 & m; // @[VDecodeInstruction.scala 348:49]
- wire vsel = ~v & func1 == 3'h6 & func2 == 6'h10 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vevn = ~v & func1 == 3'h6 & func2 == 6'h18 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vodd = ~v & func1 == 3'h6 & func2 == 6'h19 & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vevnodd = ~v & func1 == 3'h6 & _vstq_T & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vzip = ~v & func1 == 3'h6 & func2 == 6'h1c & _vdup_T_17; // @[VDecodeInstruction.scala 62:65]
- wire vslideh2 = vslidehn2 | vslidehp2; // @[VDecodeInstruction.scala 355:28]
- wire vevn3 = vevn | vevnodd | vodd; // @[VDecodeInstruction.scala 356:31]
- wire vfmt6 = vslidevn | vslidehn | vslidehn2 | vslidevp | vslidehp | vslidehp2 | vsel | vevn | vodd | vevnodd | vzip; // @[VDecodeInstruction.scala 358:112]
- wire _aconv_T_1 = io_in_inst[25] & vdup_bit_18; // @[Library.scala 330:48]
- wire aconv_bit_19 = ~vdup_bit_19; // @[Library.scala 326:19]
- wire _aconv_T_2 = _aconv_T_1 & aconv_bit_19; // @[Library.scala 327:48]
- wire aconv_bit_27 = ~vdup_bit_27; // @[Library.scala 326:19]
- wire aconv_bit_28 = ~vdup_bit_28; // @[Library.scala 326:19]
- wire _aconv_T_5 = _aconv_T_1 & aconv_bit_19 & _acset_T_10 & aconv_bit_27 & aconv_bit_28; // @[Library.scala 327:48]
- wire _aconv_T_6 = _aconv_T_5 & x3; // @[Library.scala 330:48]
- wire aconv_bit_30 = ~x; // @[Library.scala 326:19]
- wire _aconv_T_7 = _aconv_T_6 & aconv_bit_30; // @[Library.scala 327:48]
- wire aconv = _aconv_T_7 & v; // @[Library.scala 330:48]
- wire _vcget_T_3 = _vdup_T_2 & io_in_inst[28]; // @[Library.scala 330:48]
- wire vcget_bit_5 = ~vdup_bit_5; // @[Library.scala 326:19]
- wire vcget_bit_7 = ~vdup_bit_7; // @[Library.scala 326:19]
- wire vcget_bit_8 = ~vdup_bit_8; // @[Library.scala 326:19]
- wire vcget_bit_9 = ~vdup_bit_9; // @[Library.scala 326:19]
- wire vcget_bit_10 = ~vdup_bit_10; // @[Library.scala 326:19]
- wire vcget_bit_11 = ~vdup_bit_11; // @[Library.scala 326:19]
- wire _vcget_T_17 = _vcget_T_3 & vdup_bit_4 & vcget_bit_5 & vdup_bit_6 & vcget_bit_7 & vcget_bit_8 & vcget_bit_9 &
- vcget_bit_10 & vcget_bit_11 & vdup_bit_12 & vdup_bit_13 & vdup_bit_14 & vdup_bit_15 & vdup_bit_16 & vdup_bit_17; // @[Library.scala 327:48]
- wire vcget = _vcget_T_17 & vdup_bit_27 & vdup_bit_28 & x3 & x & v; // @[Library.scala 330:48]
- wire _vdwconv_T_1 = vdup_bit_6 & vdup_bit_18; // @[Library.scala 330:48]
- wire _vdwconv_T_2 = _vdwconv_T_1 & aconv_bit_19; // @[Library.scala 327:48]
- wire _vdwconv_T_3 = _vdwconv_T_2 & vdup_bit_27; // @[Library.scala 330:48]
- wire _vdwconv_T_4 = _vdwconv_T_3 & aconv_bit_28; // @[Library.scala 327:48]
- wire _vdwconv_T_5 = _vdwconv_T_4 & x3; // @[Library.scala 330:48]
- wire _vdwconv_T_6 = _vdwconv_T_5 & aconv_bit_30; // @[Library.scala 327:48]
- wire vdwconv = _vdwconv_T_6 & v; // @[Library.scala 330:48]
- wire _adwconv_T_3 = _aconv_T_2 & vdup_bit_27; // @[Library.scala 330:48]
- wire _adwconv_T_4 = _adwconv_T_3 & aconv_bit_28; // @[Library.scala 327:48]
- wire _adwconv_T_5 = _adwconv_T_4 & x3; // @[Library.scala 330:48]
- wire _adwconv_T_6 = _adwconv_T_5 & aconv_bit_30; // @[Library.scala 327:48]
- wire adwconv = _adwconv_T_6 & v; // @[Library.scala 330:48]
- wire vadwconv = vdwconv | adwconv; // @[VDecodeInstruction.scala 366:26]
- wire [9:0] vopbits_lo_lo_hi = {vacc,vpadd,vpsub,vhadd,vhsub,vslidevn,vslidehn,vslidehn2,vslidevp,vslidehp}; // @[Cat.scala 31:58]
- wire [18:0] vopbits_lo_lo = {vopbits_lo_lo_hi,vslidehp2,vsel,vevn,vodd,vevnodd,vzip,aconv,vdwconv,adwconv}; // @[Cat.scala 31:58]
- wire [9:0] vopbits_lo_hi_hi = {vsrans,vsraqs,vmul,vmul2,vmuls,vmuls2,vmulh,vmulh2,vmulhu,vmulhu2}; // @[Cat.scala 31:58]
- wire [18:0] vopbits_lo_hi = {vopbits_lo_hi_hi,vdmulh,vdmulh2,vmulw,vmacc,vmadd,vadds,vsubs,vaddw,vsubw}; // @[Cat.scala 31:58]
- wire [9:0] vopbits_hi_lo_hi = {vor,vxor,vnot,vrev,vror,vclb,vclz,vcpop,vmv,vmv2}; // @[Cat.scala 31:58]
- wire [18:0] vopbits_hi_lo = {vopbits_hi_lo_hi,vmvp,acset,actr,adwinit,vsll,vsra,vsrl,vsha,vshl}; // @[Cat.scala 31:58]
- wire [9:0] vopbits_hi_hi_hi = {vdup,vld,vst,vstq,vcget,vadd,vsub,vrsub,veq,vne}; // @[Cat.scala 31:58]
- wire [18:0] vopbits_hi_hi = {vopbits_hi_hi_hi,vlt,vle,vgt,vge,vabsd,vmax,vmin,vadd3,vand}; // @[Cat.scala 31:58]
- wire [75:0] vopbits = {vopbits_hi_hi,vopbits_hi_lo,vopbits_lo_hi,vopbits_lo_lo}; // @[Cat.scala 31:58]
- wire undef_value__0 = vopbits[0] | vopbits[1]; // @[Library.scala 208:39]
- wire undef_value__1 = vopbits[2] | vopbits[3]; // @[Library.scala 208:39]
- wire undef_value__2 = vopbits[4] | vopbits[5]; // @[Library.scala 208:39]
- wire undef_value__3 = vopbits[6] | vopbits[7]; // @[Library.scala 208:39]
- wire undef_value__4 = vopbits[8] | vopbits[9]; // @[Library.scala 208:39]
- wire undef_value__5 = vopbits[10] | vopbits[11]; // @[Library.scala 208:39]
- wire undef_value__6 = vopbits[12] | vopbits[13]; // @[Library.scala 208:39]
- wire undef_value__7 = vopbits[14] | vopbits[15]; // @[Library.scala 208:39]
- wire undef_value__8 = vopbits[16] | vopbits[17]; // @[Library.scala 208:39]
- wire undef_value__9 = vopbits[18] | vopbits[19]; // @[Library.scala 208:39]
- wire undef_value__10 = vopbits[20] | vopbits[21]; // @[Library.scala 208:39]
- wire undef_value__11 = vopbits[22] | vopbits[23]; // @[Library.scala 208:39]
- wire undef_value__12 = vopbits[24] | vopbits[25]; // @[Library.scala 208:39]
- wire undef_value__13 = vopbits[26] | vopbits[27]; // @[Library.scala 208:39]
- wire undef_value__14 = vopbits[28] | vopbits[29]; // @[Library.scala 208:39]
- wire undef_value__15 = vopbits[30] | vopbits[31]; // @[Library.scala 208:39]
- wire undef_value__16 = vopbits[32] | vopbits[33]; // @[Library.scala 208:39]
- wire undef_value__17 = vopbits[34] | vopbits[35]; // @[Library.scala 208:39]
- wire undef_value__18 = vopbits[36] | vopbits[37]; // @[Library.scala 208:39]
- wire undef_value__19 = vopbits[38] | vopbits[39]; // @[Library.scala 208:39]
- wire undef_value__20 = vopbits[40] | vopbits[41]; // @[Library.scala 208:39]
- wire undef_value__21 = vopbits[42] | vopbits[43]; // @[Library.scala 208:39]
- wire undef_value__22 = vopbits[44] | vopbits[45]; // @[Library.scala 208:39]
- wire undef_value__23 = vopbits[46] | vopbits[47]; // @[Library.scala 208:39]
- wire undef_value__24 = vopbits[48] | vopbits[49]; // @[Library.scala 208:39]
- wire undef_value__25 = vopbits[50] | vopbits[51]; // @[Library.scala 208:39]
- wire undef_value__26 = vopbits[52] | vopbits[53]; // @[Library.scala 208:39]
- wire undef_value__27 = vopbits[54] | vopbits[55]; // @[Library.scala 208:39]
- wire undef_value__28 = vopbits[56] | vopbits[57]; // @[Library.scala 208:39]
- wire undef_value__29 = vopbits[58] | vopbits[59]; // @[Library.scala 208:39]
- wire undef_value__30 = vopbits[60] | vopbits[61]; // @[Library.scala 208:39]
- wire undef_value__31 = vopbits[62] | vopbits[63]; // @[Library.scala 208:39]
- wire undef_value__32 = vopbits[64] | vopbits[65]; // @[Library.scala 208:39]
- wire undef_value__33 = vopbits[66] | vopbits[67]; // @[Library.scala 208:39]
- wire undef_value__34 = vopbits[68] | vopbits[69]; // @[Library.scala 208:39]
- wire undef_value__35 = vopbits[70] | vopbits[71]; // @[Library.scala 208:39]
- wire undef_value__36 = vopbits[72] | vopbits[73]; // @[Library.scala 208:39]
- wire undef_value__37 = vopbits[74] | vopbits[75]; // @[Library.scala 208:39]
- wire undef_value_1_0 = undef_value__0 | undef_value__1; // @[Library.scala 208:39]
- wire undef_value_1_1 = undef_value__2 | undef_value__3; // @[Library.scala 208:39]
- wire undef_value_1_2 = undef_value__4 | undef_value__5; // @[Library.scala 208:39]
- wire undef_value_1_3 = undef_value__6 | undef_value__7; // @[Library.scala 208:39]
- wire undef_value_1_4 = undef_value__8 | undef_value__9; // @[Library.scala 208:39]
- wire undef_value_1_5 = undef_value__10 | undef_value__11; // @[Library.scala 208:39]
- wire undef_value_1_6 = undef_value__12 | undef_value__13; // @[Library.scala 208:39]
- wire undef_value_1_7 = undef_value__14 | undef_value__15; // @[Library.scala 208:39]
- wire undef_value_1_8 = undef_value__16 | undef_value__17; // @[Library.scala 208:39]
- wire undef_value_1_9 = undef_value__18 | undef_value__19; // @[Library.scala 208:39]
- wire undef_value_1_10 = undef_value__20 | undef_value__21; // @[Library.scala 208:39]
- wire undef_value_1_11 = undef_value__22 | undef_value__23; // @[Library.scala 208:39]
- wire undef_value_1_12 = undef_value__24 | undef_value__25; // @[Library.scala 208:39]
- wire undef_value_1_13 = undef_value__26 | undef_value__27; // @[Library.scala 208:39]
- wire undef_value_1_14 = undef_value__28 | undef_value__29; // @[Library.scala 208:39]
- wire undef_value_1_15 = undef_value__30 | undef_value__31; // @[Library.scala 208:39]
- wire undef_value_1_16 = undef_value__32 | undef_value__33; // @[Library.scala 208:39]
- wire undef_value_1_17 = undef_value__34 | undef_value__35; // @[Library.scala 208:39]
- wire undef_value_1_18 = undef_value__36 | undef_value__37; // @[Library.scala 208:39]
- wire undef_value_2_0 = undef_value_1_0 | undef_value_1_1; // @[Library.scala 208:39]
- wire undef_value_2_1 = undef_value_1_2 | undef_value_1_3; // @[Library.scala 208:39]
- wire undef_value_2_2 = undef_value_1_4 | undef_value_1_5; // @[Library.scala 208:39]
- wire undef_value_2_3 = undef_value_1_6 | undef_value_1_7; // @[Library.scala 208:39]
- wire undef_value_2_4 = undef_value_1_8 | undef_value_1_9; // @[Library.scala 208:39]
- wire undef_value_2_5 = undef_value_1_10 | undef_value_1_11; // @[Library.scala 208:39]
- wire undef_value_2_6 = undef_value_1_12 | undef_value_1_13; // @[Library.scala 208:39]
- wire undef_value_2_7 = undef_value_1_14 | undef_value_1_15; // @[Library.scala 208:39]
- wire undef_value_2_8 = undef_value_1_16 | undef_value_1_17; // @[Library.scala 208:39]
- wire undef_value_3_0 = undef_value_2_0 | undef_value_2_1; // @[Library.scala 208:39]
- wire undef_value_3_1 = undef_value_2_2 | undef_value_2_3; // @[Library.scala 208:39]
- wire undef_value_3_2 = undef_value_2_4 | undef_value_2_5; // @[Library.scala 208:39]
- wire undef_value_3_3 = undef_value_2_6 | undef_value_2_7; // @[Library.scala 208:39]
- wire undef_value_3_4 = undef_value_2_8 | undef_value_1_18; // @[Library.scala 208:39]
- wire undef_value_4_0 = undef_value_3_0 | undef_value_3_1; // @[Library.scala 208:39]
- wire undef_value_4_1 = undef_value_3_2 | undef_value_3_3; // @[Library.scala 208:39]
- wire undef_value_5_0 = undef_value_4_0 | undef_value_4_1; // @[Library.scala 208:39]
- wire undef_value_6_0 = undef_value_5_0 | undef_value_3_4; // @[Library.scala 208:39]
- wire undef = ~undef_value_6_0; // @[VDecodeInstruction.scala 391:15]
- wire [76:0] _T_5 = {vopbits_hi_hi,vopbits_hi_lo,vopbits_lo_hi,vopbits_lo_lo,undef}; // @[Cat.scala 31:58]
- wire [1:0] _T_83 = _T_5[0] + _T_5[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_85 = _T_5[2] + _T_5[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_87 = _T_83 + _T_85; // @[Bitwise.scala 48:55]
- wire [1:0] _T_89 = _T_5[4] + _T_5[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_91 = _T_5[7] + _T_5[8]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_48 = {{1'd0}, _T_5[6]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_93 = _GEN_48 + _T_91; // @[Bitwise.scala 48:55]
- wire [2:0] _T_95 = _T_89 + _T_93[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _T_97 = _T_87 + _T_95; // @[Bitwise.scala 48:55]
- wire [1:0] _T_99 = _T_5[9] + _T_5[10]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_101 = _T_5[12] + _T_5[13]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_49 = {{1'd0}, _T_5[11]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_103 = _GEN_49 + _T_101; // @[Bitwise.scala 48:55]
- wire [2:0] _T_105 = _T_99 + _T_103[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_107 = _T_5[14] + _T_5[15]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_109 = _T_5[17] + _T_5[18]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_50 = {{1'd0}, _T_5[16]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_111 = _GEN_50 + _T_109; // @[Bitwise.scala 48:55]
- wire [2:0] _T_113 = _T_107 + _T_111[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _T_115 = _T_105 + _T_113; // @[Bitwise.scala 48:55]
- wire [4:0] _T_117 = _T_97 + _T_115; // @[Bitwise.scala 48:55]
- wire [1:0] _T_119 = _T_5[19] + _T_5[20]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_121 = _T_5[21] + _T_5[22]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_123 = _T_119 + _T_121; // @[Bitwise.scala 48:55]
- wire [1:0] _T_125 = _T_5[23] + _T_5[24]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_127 = _T_5[26] + _T_5[27]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_51 = {{1'd0}, _T_5[25]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_129 = _GEN_51 + _T_127; // @[Bitwise.scala 48:55]
- wire [2:0] _T_131 = _T_125 + _T_129[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _T_133 = _T_123 + _T_131; // @[Bitwise.scala 48:55]
- wire [1:0] _T_135 = _T_5[28] + _T_5[29]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_137 = _T_5[31] + _T_5[32]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_52 = {{1'd0}, _T_5[30]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_139 = _GEN_52 + _T_137; // @[Bitwise.scala 48:55]
- wire [2:0] _T_141 = _T_135 + _T_139[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_143 = _T_5[33] + _T_5[34]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_145 = _T_5[36] + _T_5[37]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_53 = {{1'd0}, _T_5[35]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_147 = _GEN_53 + _T_145; // @[Bitwise.scala 48:55]
- wire [2:0] _T_149 = _T_143 + _T_147[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _T_151 = _T_141 + _T_149; // @[Bitwise.scala 48:55]
- wire [4:0] _T_153 = _T_133 + _T_151; // @[Bitwise.scala 48:55]
- wire [5:0] _T_155 = _T_117 + _T_153; // @[Bitwise.scala 48:55]
- wire [1:0] _T_157 = _T_5[38] + _T_5[39]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_159 = _T_5[40] + _T_5[41]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_161 = _T_157 + _T_159; // @[Bitwise.scala 48:55]
- wire [1:0] _T_163 = _T_5[42] + _T_5[43]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_165 = _T_5[45] + _T_5[46]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_54 = {{1'd0}, _T_5[44]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_167 = _GEN_54 + _T_165; // @[Bitwise.scala 48:55]
- wire [2:0] _T_169 = _T_163 + _T_167[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _T_171 = _T_161 + _T_169; // @[Bitwise.scala 48:55]
- wire [1:0] _T_173 = _T_5[47] + _T_5[48]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_175 = _T_5[50] + _T_5[51]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_55 = {{1'd0}, _T_5[49]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_177 = _GEN_55 + _T_175; // @[Bitwise.scala 48:55]
- wire [2:0] _T_179 = _T_173 + _T_177[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_181 = _T_5[52] + _T_5[53]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_183 = _T_5[55] + _T_5[56]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_56 = {{1'd0}, _T_5[54]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_185 = _GEN_56 + _T_183; // @[Bitwise.scala 48:55]
- wire [2:0] _T_187 = _T_181 + _T_185[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _T_189 = _T_179 + _T_187; // @[Bitwise.scala 48:55]
- wire [4:0] _T_191 = _T_171 + _T_189; // @[Bitwise.scala 48:55]
- wire [1:0] _T_193 = _T_5[57] + _T_5[58]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_195 = _T_5[60] + _T_5[61]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_57 = {{1'd0}, _T_5[59]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_197 = _GEN_57 + _T_195; // @[Bitwise.scala 48:55]
- wire [2:0] _T_199 = _T_193 + _T_197[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_201 = _T_5[62] + _T_5[63]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_203 = _T_5[65] + _T_5[66]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_58 = {{1'd0}, _T_5[64]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_205 = _GEN_58 + _T_203; // @[Bitwise.scala 48:55]
- wire [2:0] _T_207 = _T_201 + _T_205[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _T_209 = _T_199 + _T_207; // @[Bitwise.scala 48:55]
- wire [1:0] _T_211 = _T_5[67] + _T_5[68]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_213 = _T_5[70] + _T_5[71]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_59 = {{1'd0}, _T_5[69]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_215 = _GEN_59 + _T_213; // @[Bitwise.scala 48:55]
- wire [2:0] _T_217 = _T_211 + _T_215[1:0]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_219 = _T_5[72] + _T_5[73]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_221 = _T_5[75] + _T_5[76]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_60 = {{1'd0}, _T_5[74]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_223 = _GEN_60 + _T_221; // @[Bitwise.scala 48:55]
- wire [2:0] _T_225 = _T_219 + _T_223[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _T_227 = _T_217 + _T_225; // @[Bitwise.scala 48:55]
- wire [4:0] _T_229 = _T_209 + _T_227; // @[Bitwise.scala 48:55]
- wire [5:0] _T_231 = _T_191 + _T_229; // @[Bitwise.scala 48:55]
- wire [6:0] _T_233 = _T_155 + _T_231; // @[Bitwise.scala 48:55]
- wire [1:0] _op_T_1 = vld ? 2'h2 : 2'h0; // @[Library.scala 32:8]
- wire [1:0] _GEN_61 = {{1'd0}, vdup}; // @[VDecodeInstruction.scala 397:31]
- wire [1:0] _op_T_2 = _GEN_61 | _op_T_1; // @[VDecodeInstruction.scala 397:31]
- wire [1:0] _op_T_3 = vst ? 2'h3 : 2'h0; // @[Library.scala 32:8]
- wire [1:0] _op_T_4 = _op_T_2 | _op_T_3; // @[VDecodeInstruction.scala 399:30]
- wire [2:0] _op_T_5 = vstq ? 3'h4 : 3'h0; // @[Library.scala 32:8]
- wire [2:0] _GEN_62 = {{1'd0}, _op_T_4}; // @[VDecodeInstruction.scala 400:30]
- wire [2:0] _op_T_6 = _GEN_62 | _op_T_5; // @[VDecodeInstruction.scala 400:30]
- wire [2:0] _op_T_7 = vcget ? 3'h5 : 3'h0; // @[Library.scala 32:8]
- wire [2:0] _op_T_8 = _op_T_6 | _op_T_7; // @[VDecodeInstruction.scala 401:31]
- wire [2:0] _op_T_9 = vadd ? 3'h6 : 3'h0; // @[Library.scala 32:8]
- wire [2:0] _op_T_10 = _op_T_8 | _op_T_9; // @[VDecodeInstruction.scala 403:33]
- wire [2:0] _op_T_11 = vsub ? 3'h7 : 3'h0; // @[Library.scala 32:8]
- wire [2:0] _op_T_12 = _op_T_10 | _op_T_11; // @[VDecodeInstruction.scala 405:32]
- wire [3:0] _op_T_13 = vrsub ? 4'h8 : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _GEN_63 = {{1'd0}, _op_T_12}; // @[VDecodeInstruction.scala 406:32]
- wire [3:0] _op_T_14 = _GEN_63 | _op_T_13; // @[VDecodeInstruction.scala 406:32]
- wire [3:0] _op_T_15 = veq ? 4'h9 : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _op_T_16 = _op_T_14 | _op_T_15; // @[VDecodeInstruction.scala 407:33]
- wire [3:0] _op_T_17 = vne ? 4'ha : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _op_T_18 = _op_T_16 | _op_T_17; // @[VDecodeInstruction.scala 408:31]
- wire [3:0] _op_T_19 = vlt ? 4'hb : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _op_T_20 = _op_T_18 | _op_T_19; // @[VDecodeInstruction.scala 409:31]
- wire [3:0] _op_T_21 = vle ? 4'hc : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _op_T_22 = _op_T_20 | _op_T_21; // @[VDecodeInstruction.scala 410:31]
- wire [3:0] _op_T_23 = vgt ? 4'hd : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _op_T_24 = _op_T_22 | _op_T_23; // @[VDecodeInstruction.scala 411:31]
- wire [3:0] _op_T_25 = vge ? 4'he : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _op_T_26 = _op_T_24 | _op_T_25; // @[VDecodeInstruction.scala 412:31]
- wire [3:0] _op_T_27 = vabsd ? 4'hf : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _op_T_28 = _op_T_26 | _op_T_27; // @[VDecodeInstruction.scala 413:31]
- wire [4:0] _op_T_29 = vmax ? 5'h10 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _GEN_64 = {{1'd0}, _op_T_28}; // @[VDecodeInstruction.scala 414:33]
- wire [4:0] _op_T_30 = _GEN_64 | _op_T_29; // @[VDecodeInstruction.scala 414:33]
- wire [4:0] _op_T_31 = vmin ? 5'h11 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_32 = _op_T_30 | _op_T_31; // @[VDecodeInstruction.scala 415:32]
- wire [4:0] _op_T_33 = vadd3 ? 5'h12 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_34 = _op_T_32 | _op_T_33; // @[VDecodeInstruction.scala 416:32]
- wire [4:0] _op_T_35 = vand ? 5'h13 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_36 = _op_T_34 | _op_T_35; // @[VDecodeInstruction.scala 417:33]
- wire [4:0] _op_T_37 = vor ? 5'h14 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_38 = _op_T_36 | _op_T_37; // @[VDecodeInstruction.scala 419:32]
- wire [4:0] _op_T_39 = vxor ? 5'h15 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_40 = _op_T_38 | _op_T_39; // @[VDecodeInstruction.scala 420:31]
- wire [4:0] _op_T_41 = vnot ? 5'h16 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_42 = _op_T_40 | _op_T_41; // @[VDecodeInstruction.scala 421:32]
- wire [4:0] _op_T_43 = vrev ? 5'h17 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_44 = _op_T_42 | _op_T_43; // @[VDecodeInstruction.scala 422:32]
- wire [4:0] _op_T_45 = vror ? 5'h18 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_46 = _op_T_44 | _op_T_45; // @[VDecodeInstruction.scala 423:32]
- wire [4:0] _op_T_47 = vclb ? 5'h19 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_48 = _op_T_46 | _op_T_47; // @[VDecodeInstruction.scala 424:32]
- wire [4:0] _op_T_49 = vclz ? 5'h1a : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_50 = _op_T_48 | _op_T_49; // @[VDecodeInstruction.scala 425:32]
- wire [4:0] _op_T_51 = vcpop ? 5'h1b : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_52 = _op_T_50 | _op_T_51; // @[VDecodeInstruction.scala 426:32]
- wire [4:0] _op_T_53 = vmv ? 5'h1c : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_54 = _op_T_52 | _op_T_53; // @[VDecodeInstruction.scala 427:33]
- wire [4:0] _op_T_55 = vmv2 ? 5'h1d : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_56 = _op_T_54 | _op_T_55; // @[VDecodeInstruction.scala 428:31]
- wire [4:0] _op_T_57 = vmvp ? 5'h1e : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_58 = _op_T_56 | _op_T_57; // @[VDecodeInstruction.scala 429:32]
- wire [4:0] _op_T_59 = acset ? 5'h1f : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _op_T_60 = _op_T_58 | _op_T_59; // @[VDecodeInstruction.scala 430:32]
- wire [5:0] _op_T_61 = actr ? 6'h20 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _GEN_65 = {{1'd0}, _op_T_60}; // @[VDecodeInstruction.scala 431:33]
- wire [5:0] _op_T_62 = _GEN_65 | _op_T_61; // @[VDecodeInstruction.scala 431:33]
- wire [5:0] _op_T_63 = adwinit ? 6'h21 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_64 = _op_T_62 | _op_T_63; // @[VDecodeInstruction.scala 432:32]
- wire [5:0] _op_T_65 = vsll ? 6'h22 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_66 = _op_T_64 | _op_T_65; // @[VDecodeInstruction.scala 433:37]
- wire [5:0] _op_T_67 = vsra ? 6'h23 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_68 = _op_T_66 | _op_T_67; // @[VDecodeInstruction.scala 435:33]
- wire [5:0] _op_T_69 = vsrl ? 6'h23 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_70 = _op_T_68 | _op_T_69; // @[VDecodeInstruction.scala 436:33]
- wire [5:0] _op_T_71 = vsha ? 6'h24 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_72 = _op_T_70 | _op_T_71; // @[VDecodeInstruction.scala 437:33]
- wire [5:0] _op_T_73 = vshl ? 6'h24 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_74 = _op_T_72 | _op_T_73; // @[VDecodeInstruction.scala 438:33]
- wire [5:0] _op_T_75 = vsrans ? 6'h25 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_76 = _op_T_74 | _op_T_75; // @[VDecodeInstruction.scala 439:33]
- wire [5:0] _op_T_77 = vsraqs ? 6'h26 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_78 = _op_T_76 | _op_T_77; // @[VDecodeInstruction.scala 440:35]
- wire [5:0] _op_T_79 = vmul ? 6'h27 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_80 = _op_T_78 | _op_T_79; // @[VDecodeInstruction.scala 441:35]
- wire [5:0] _op_T_81 = vmul2 ? 6'h28 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_82 = _op_T_80 | _op_T_81; // @[VDecodeInstruction.scala 443:34]
- wire [5:0] _op_T_83 = vmuls ? 6'h29 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_84 = _op_T_82 | _op_T_83; // @[VDecodeInstruction.scala 444:35]
- wire [5:0] _op_T_85 = vmuls2 ? 6'h2a : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_86 = _op_T_84 | _op_T_85; // @[VDecodeInstruction.scala 445:35]
- wire [5:0] _op_T_87 = vmulh ? 6'h2b : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_88 = _op_T_86 | _op_T_87; // @[VDecodeInstruction.scala 446:36]
- wire [5:0] _op_T_89 = vmulh2 ? 6'h2c : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_90 = _op_T_88 | _op_T_89; // @[VDecodeInstruction.scala 447:35]
- wire [5:0] _op_T_91 = vmulhu ? 6'h2b : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_92 = _op_T_90 | _op_T_91; // @[VDecodeInstruction.scala 448:36]
- wire [5:0] _op_T_93 = vmulhu2 ? 6'h2c : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_94 = _op_T_92 | _op_T_93; // @[VDecodeInstruction.scala 449:35]
- wire [5:0] _op_T_95 = vdmulh ? 6'h2d : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_96 = _op_T_94 | _op_T_95; // @[VDecodeInstruction.scala 450:36]
- wire [5:0] _op_T_97 = vdmulh2 ? 6'h2e : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_98 = _op_T_96 | _op_T_97; // @[VDecodeInstruction.scala 451:36]
- wire [5:0] _op_T_99 = vmulw ? 6'h2f : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_100 = _op_T_98 | _op_T_99; // @[VDecodeInstruction.scala 452:37]
- wire [5:0] _op_T_101 = vmacc ? 6'h30 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_102 = _op_T_100 | _op_T_101; // @[VDecodeInstruction.scala 453:35]
- wire [5:0] _op_T_103 = vmadd ? 6'h30 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_104 = _op_T_102 | _op_T_103; // @[VDecodeInstruction.scala 454:35]
- wire [5:0] _op_T_105 = vadds ? 6'h31 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_106 = _op_T_104 | _op_T_105; // @[VDecodeInstruction.scala 455:35]
- wire [5:0] _op_T_107 = vsubs ? 6'h32 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_108 = _op_T_106 | _op_T_107; // @[VDecodeInstruction.scala 457:34]
- wire [5:0] _op_T_109 = vaddw ? 6'h33 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_110 = _op_T_108 | _op_T_109; // @[VDecodeInstruction.scala 458:34]
- wire [5:0] _op_T_111 = vsubw ? 6'h34 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_112 = _op_T_110 | _op_T_111; // @[VDecodeInstruction.scala 459:34]
- wire [5:0] _op_T_113 = vacc ? 6'h35 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_114 = _op_T_112 | _op_T_113; // @[VDecodeInstruction.scala 460:34]
- wire [5:0] _op_T_115 = vpadd ? 6'h36 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_116 = _op_T_114 | _op_T_115; // @[VDecodeInstruction.scala 461:33]
- wire [5:0] _op_T_117 = vpsub ? 6'h37 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_118 = _op_T_116 | _op_T_117; // @[VDecodeInstruction.scala 462:34]
- wire [5:0] _op_T_119 = vhadd ? 6'h38 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_120 = _op_T_118 | _op_T_119; // @[VDecodeInstruction.scala 463:34]
- wire [5:0] _op_T_121 = vhsub ? 6'h39 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_122 = _op_T_120 | _op_T_121; // @[VDecodeInstruction.scala 464:34]
- wire [5:0] _op_T_123 = vslidevn ? 6'h3a : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_124 = _op_T_122 | _op_T_123; // @[VDecodeInstruction.scala 465:34]
- wire [5:0] _op_T_125 = vslidehn ? 6'h3b : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_126 = _op_T_124 | _op_T_125; // @[VDecodeInstruction.scala 467:40]
- wire [5:0] _op_T_127 = vslidehn2 ? 6'h3c : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_128 = _op_T_126 | _op_T_127; // @[VDecodeInstruction.scala 468:40]
- wire [5:0] _op_T_129 = vslidevp ? 6'h3d : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_130 = _op_T_128 | _op_T_129; // @[VDecodeInstruction.scala 469:41]
- wire [5:0] _op_T_131 = vslidehp ? 6'h3e : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_132 = _op_T_130 | _op_T_131; // @[VDecodeInstruction.scala 470:40]
- wire [5:0] _op_T_133 = vslidehp2 ? 6'h3f : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _op_T_134 = _op_T_132 | _op_T_133; // @[VDecodeInstruction.scala 471:40]
- wire [6:0] _op_T_135 = vsel ? 7'h40 : 7'h0; // @[Library.scala 32:8]
- wire [6:0] _GEN_66 = {{1'd0}, _op_T_134}; // @[VDecodeInstruction.scala 472:41]
- wire [6:0] _op_T_136 = _GEN_66 | _op_T_135; // @[VDecodeInstruction.scala 472:41]
- wire [6:0] _op_T_137 = vevn ? 7'h41 : 7'h0; // @[Library.scala 32:8]
- wire [6:0] _op_T_138 = _op_T_136 | _op_T_137; // @[VDecodeInstruction.scala 473:35]
- wire [6:0] _op_T_139 = vodd ? 7'h42 : 7'h0; // @[Library.scala 32:8]
- wire [6:0] _op_T_140 = _op_T_138 | _op_T_139; // @[VDecodeInstruction.scala 474:35]
- wire [6:0] _op_T_141 = vevnodd ? 7'h43 : 7'h0; // @[Library.scala 32:8]
- wire [6:0] _op_T_142 = _op_T_140 | _op_T_141; // @[VDecodeInstruction.scala 475:35]
- wire [6:0] _op_T_143 = vzip ? 7'h44 : 7'h0; // @[Library.scala 32:8]
- wire [6:0] _op_T_144 = _op_T_142 | _op_T_143; // @[VDecodeInstruction.scala 476:38]
- wire [6:0] _op_T_145 = aconv ? 7'h45 : 7'h0; // @[Library.scala 32:8]
- wire [6:0] _op_T_146 = _op_T_144 | _op_T_145; // @[VDecodeInstruction.scala 477:35]
- wire [6:0] _op_T_147 = vdwconv ? 7'h46 : 7'h0; // @[Library.scala 32:8]
- wire [6:0] _op_T_148 = _op_T_146 | _op_T_147; // @[VDecodeInstruction.scala 479:36]
- wire [6:0] _op_T_149 = adwconv ? 7'h47 : 7'h0; // @[Library.scala 32:8]
- wire [3:0] regbase = io_in_data[7:4]; // @[VDecodeInstruction.scala 165:23]
- wire [3:0] _GEN_1 = 4'h1 == regbase ? 4'h1 : 4'h0; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_2 = 4'h2 == regbase ? 4'h2 : _GEN_1; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_3 = 4'h3 == regbase ? 4'h3 : _GEN_2; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_4 = 4'h4 == regbase ? 4'h4 : _GEN_3; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_5 = 4'h5 == regbase ? 4'h5 : _GEN_4; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_6 = 4'h6 == regbase ? 4'h6 : _GEN_5; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_7 = 4'h7 == regbase ? 4'h1 : _GEN_6; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_8 = 4'h8 == regbase ? 4'h1 : _GEN_7; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_9 = 4'h9 == regbase ? 4'h3 : _GEN_8; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_10 = 4'ha == regbase ? 4'h5 : _GEN_9; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_11 = 4'hb == regbase ? 4'h7 : _GEN_10; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_12 = 4'hc == regbase ? 4'h2 : _GEN_11; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_13 = 4'hd == regbase ? 4'h4 : _GEN_12; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_14 = 4'he == regbase ? 4'h6 : _GEN_13; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [3:0] _GEN_15 = 4'hf == regbase ? 4'h8 : _GEN_14; // @[VDecodeInstruction.scala 167:{21,21}]
- wire [5:0] _GEN_67 = {{2'd0}, _GEN_15}; // @[VDecodeInstruction.scala 167:21]
- wire [5:0] vsdw = vsbits + _GEN_67; // @[VDecodeInstruction.scala 167:21]
- wire [3:0] _GEN_17 = 4'h1 == regbase ? 4'h2 : 4'h1; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_18 = 4'h2 == regbase ? 4'h3 : _GEN_17; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_19 = 4'h3 == regbase ? 4'h4 : _GEN_18; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_20 = 4'h4 == regbase ? 4'h5 : _GEN_19; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_21 = 4'h5 == regbase ? 4'h6 : _GEN_20; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_22 = 4'h6 == regbase ? 4'h7 : _GEN_21; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_23 = 4'h7 == regbase ? 4'h0 : _GEN_22; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_24 = 4'h8 == regbase ? 4'h2 : _GEN_23; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_25 = 4'h9 == regbase ? 4'h4 : _GEN_24; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_26 = 4'ha == regbase ? 4'h6 : _GEN_25; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_27 = 4'hb == regbase ? 4'h8 : _GEN_26; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_28 = 4'hc == regbase ? 4'h0 : _GEN_27; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_29 = 4'hd == regbase ? 4'h0 : _GEN_28; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_30 = 4'he == regbase ? 4'h0 : _GEN_29; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [3:0] _GEN_31 = 4'hf == regbase ? 4'h0 : _GEN_30; // @[VDecodeInstruction.scala 168:{21,21}]
- wire [5:0] _GEN_68 = {{2'd0}, _GEN_31}; // @[VDecodeInstruction.scala 168:21]
- wire [5:0] vtdw = vsbits + _GEN_68; // @[VDecodeInstruction.scala 168:21]
- wire [3:0] _GEN_33 = 4'h1 == regbase ? 4'h3 : 4'h2; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_34 = 4'h2 == regbase ? 4'h4 : _GEN_33; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_35 = 4'h3 == regbase ? 4'h5 : _GEN_34; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_36 = 4'h4 == regbase ? 4'h6 : _GEN_35; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_37 = 4'h5 == regbase ? 4'h7 : _GEN_36; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_38 = 4'h6 == regbase ? 4'h8 : _GEN_37; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_39 = 4'h7 == regbase ? 4'h2 : _GEN_38; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_40 = 4'h8 == regbase ? 4'h0 : _GEN_39; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_41 = 4'h9 == regbase ? 4'h0 : _GEN_40; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_42 = 4'ha == regbase ? 4'h0 : _GEN_41; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_43 = 4'hb == regbase ? 4'h0 : _GEN_42; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_44 = 4'hc == regbase ? 4'h1 : _GEN_43; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_45 = 4'hd == regbase ? 4'h1 : _GEN_44; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_46 = 4'he == regbase ? 4'h1 : _GEN_45; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [3:0] _GEN_47 = 4'hf == regbase ? 4'h1 : _GEN_46; // @[VDecodeInstruction.scala 169:{21,21}]
- wire [5:0] _GEN_69 = {{2'd0}, _GEN_47}; // @[VDecodeInstruction.scala 169:21]
- wire [5:0] vudw = vsbits + _GEN_69; // @[VDecodeInstruction.scala 169:21]
- wire [2:0] _vy_T = m ? 3'h4 : 3'h1; // @[VDecodeInstruction.scala 175:26]
- wire [5:0] _GEN_70 = {{3'd0}, _vy_T}; // @[VDecodeInstruction.scala 175:21]
- wire [5:0] vydw = func2 + _GEN_70; // @[VDecodeInstruction.scala 175:21]
- wire [3:0] _vz_T = m ? 4'h8 : 4'h2; // @[VDecodeInstruction.scala 176:26]
- wire [5:0] _GEN_71 = {{2'd0}, _vz_T}; // @[VDecodeInstruction.scala 176:21]
- wire [5:0] vzdw = func2 + _GEN_71; // @[VDecodeInstruction.scala 176:21]
- wire [63:0] ra_vs = 64'h1 << vsdw; // @[OneHot.scala 64:12]
- wire [63:0] ra_vt = 64'h1 << vtdw; // @[OneHot.scala 64:12]
- wire [63:0] ra_vu = 64'h1 << vudw; // @[OneHot.scala 64:12]
- wire [63:0] ra_vx = 64'h1 << func2; // @[OneHot.scala 64:12]
- wire [63:0] ra_vy = 64'h1 << vydw; // @[OneHot.scala 64:12]
- wire [63:0] ra_vz = 64'h1 << vzdw; // @[OneHot.scala 64:12]
- wire [3:0] ra_vxm_shiftAmount = func2[5:2]; // @[VDecodeInstruction.scala 187:40]
- wire [15:0] _ra_vxm_T_1 = 16'h1 << ra_vxm_shiftAmount; // @[OneHot.scala 64:12]
- wire ra_vxm_v = _ra_vxm_T_1[0]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_1 = _ra_vxm_T_1[1]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_2 = _ra_vxm_T_1[2]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_3 = _ra_vxm_T_1[3]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_4 = _ra_vxm_T_1[4]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_5 = _ra_vxm_T_1[5]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_6 = _ra_vxm_T_1[6]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_7 = _ra_vxm_T_1[7]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_8 = _ra_vxm_T_1[8]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_9 = _ra_vxm_T_1[9]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_10 = _ra_vxm_T_1[10]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_11 = _ra_vxm_T_1[11]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_12 = _ra_vxm_T_1[12]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_13 = _ra_vxm_T_1[13]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_14 = _ra_vxm_T_1[14]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vxm_v_15 = _ra_vxm_T_1[15]; // @[VDecodeInstruction.scala 68:16]
- wire [7:0] ra_vxm_b_lo_lo_lo = {ra_vxm_v_1,ra_vxm_v_1,ra_vxm_v_1,ra_vxm_v_1,ra_vxm_v,ra_vxm_v,ra_vxm_v,ra_vxm_v}; // @[VDecodeInstruction.scala 71:19]
- wire [15:0] ra_vxm_b_lo_lo = {ra_vxm_v_3,ra_vxm_v_3,ra_vxm_v_3,ra_vxm_v_3,ra_vxm_v_2,ra_vxm_v_2,ra_vxm_v_2,ra_vxm_v_2,
- ra_vxm_b_lo_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] ra_vxm_b_lo_hi_lo = {ra_vxm_v_5,ra_vxm_v_5,ra_vxm_v_5,ra_vxm_v_5,ra_vxm_v_4,ra_vxm_v_4,ra_vxm_v_4,
- ra_vxm_v_4}; // @[VDecodeInstruction.scala 71:19]
- wire [31:0] ra_vxm_b_lo = {ra_vxm_v_7,ra_vxm_v_7,ra_vxm_v_7,ra_vxm_v_7,ra_vxm_v_6,ra_vxm_v_6,ra_vxm_v_6,ra_vxm_v_6,
- ra_vxm_b_lo_hi_lo,ra_vxm_b_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] ra_vxm_b_hi_lo_lo = {ra_vxm_v_9,ra_vxm_v_9,ra_vxm_v_9,ra_vxm_v_9,ra_vxm_v_8,ra_vxm_v_8,ra_vxm_v_8,
- ra_vxm_v_8}; // @[VDecodeInstruction.scala 71:19]
- wire [15:0] ra_vxm_b_hi_lo = {ra_vxm_v_11,ra_vxm_v_11,ra_vxm_v_11,ra_vxm_v_11,ra_vxm_v_10,ra_vxm_v_10,ra_vxm_v_10,
- ra_vxm_v_10,ra_vxm_b_hi_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] ra_vxm_b_hi_hi_lo = {ra_vxm_v_13,ra_vxm_v_13,ra_vxm_v_13,ra_vxm_v_13,ra_vxm_v_12,ra_vxm_v_12,ra_vxm_v_12,
- ra_vxm_v_12}; // @[VDecodeInstruction.scala 71:19]
- wire [31:0] ra_vxm_b_hi = {ra_vxm_v_15,ra_vxm_v_15,ra_vxm_v_15,ra_vxm_v_15,ra_vxm_v_14,ra_vxm_v_14,ra_vxm_v_14,
- ra_vxm_v_14,ra_vxm_b_hi_hi_lo,ra_vxm_b_hi_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [63:0] ra_vxm_b = {ra_vxm_b_hi,ra_vxm_b_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [63:0] ra_vxm = m ? ra_vxm_b : 64'h0; // @[Library.scala 32:8]
- wire [3:0] ra_vym_shiftAmount = vydw[5:2]; // @[VDecodeInstruction.scala 188:40]
- wire [15:0] _ra_vym_T_1 = 16'h1 << ra_vym_shiftAmount; // @[OneHot.scala 64:12]
- wire ra_vym_v = _ra_vym_T_1[0]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_1 = _ra_vym_T_1[1]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_2 = _ra_vym_T_1[2]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_3 = _ra_vym_T_1[3]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_4 = _ra_vym_T_1[4]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_5 = _ra_vym_T_1[5]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_6 = _ra_vym_T_1[6]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_7 = _ra_vym_T_1[7]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_8 = _ra_vym_T_1[8]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_9 = _ra_vym_T_1[9]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_10 = _ra_vym_T_1[10]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_11 = _ra_vym_T_1[11]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_12 = _ra_vym_T_1[12]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_13 = _ra_vym_T_1[13]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_14 = _ra_vym_T_1[14]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vym_v_15 = _ra_vym_T_1[15]; // @[VDecodeInstruction.scala 68:16]
- wire [7:0] ra_vym_b_lo_lo_lo = {ra_vym_v_1,ra_vym_v_1,ra_vym_v_1,ra_vym_v_1,ra_vym_v,ra_vym_v,ra_vym_v,ra_vym_v}; // @[VDecodeInstruction.scala 71:19]
- wire [15:0] ra_vym_b_lo_lo = {ra_vym_v_3,ra_vym_v_3,ra_vym_v_3,ra_vym_v_3,ra_vym_v_2,ra_vym_v_2,ra_vym_v_2,ra_vym_v_2,
- ra_vym_b_lo_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] ra_vym_b_lo_hi_lo = {ra_vym_v_5,ra_vym_v_5,ra_vym_v_5,ra_vym_v_5,ra_vym_v_4,ra_vym_v_4,ra_vym_v_4,
- ra_vym_v_4}; // @[VDecodeInstruction.scala 71:19]
- wire [31:0] ra_vym_b_lo = {ra_vym_v_7,ra_vym_v_7,ra_vym_v_7,ra_vym_v_7,ra_vym_v_6,ra_vym_v_6,ra_vym_v_6,ra_vym_v_6,
- ra_vym_b_lo_hi_lo,ra_vym_b_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] ra_vym_b_hi_lo_lo = {ra_vym_v_9,ra_vym_v_9,ra_vym_v_9,ra_vym_v_9,ra_vym_v_8,ra_vym_v_8,ra_vym_v_8,
- ra_vym_v_8}; // @[VDecodeInstruction.scala 71:19]
- wire [15:0] ra_vym_b_hi_lo = {ra_vym_v_11,ra_vym_v_11,ra_vym_v_11,ra_vym_v_11,ra_vym_v_10,ra_vym_v_10,ra_vym_v_10,
- ra_vym_v_10,ra_vym_b_hi_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] ra_vym_b_hi_hi_lo = {ra_vym_v_13,ra_vym_v_13,ra_vym_v_13,ra_vym_v_13,ra_vym_v_12,ra_vym_v_12,ra_vym_v_12,
- ra_vym_v_12}; // @[VDecodeInstruction.scala 71:19]
- wire [31:0] ra_vym_b_hi = {ra_vym_v_15,ra_vym_v_15,ra_vym_v_15,ra_vym_v_15,ra_vym_v_14,ra_vym_v_14,ra_vym_v_14,
- ra_vym_v_14,ra_vym_b_hi_hi_lo,ra_vym_b_hi_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [63:0] ra_vym_b = {ra_vym_b_hi,ra_vym_b_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [63:0] ra_vym = m ? ra_vym_b : 64'h0; // @[Library.scala 32:8]
- wire [3:0] ra_vzm_shiftAmount = vzdw[5:2]; // @[VDecodeInstruction.scala 189:40]
- wire [15:0] _ra_vzm_T_1 = 16'h1 << ra_vzm_shiftAmount; // @[OneHot.scala 64:12]
- wire ra_vzm_v = _ra_vzm_T_1[0]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_1 = _ra_vzm_T_1[1]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_2 = _ra_vzm_T_1[2]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_3 = _ra_vzm_T_1[3]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_4 = _ra_vzm_T_1[4]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_5 = _ra_vzm_T_1[5]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_6 = _ra_vzm_T_1[6]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_7 = _ra_vzm_T_1[7]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_8 = _ra_vzm_T_1[8]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_9 = _ra_vzm_T_1[9]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_10 = _ra_vzm_T_1[10]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_11 = _ra_vzm_T_1[11]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_12 = _ra_vzm_T_1[12]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_13 = _ra_vzm_T_1[13]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_14 = _ra_vzm_T_1[14]; // @[VDecodeInstruction.scala 68:16]
- wire ra_vzm_v_15 = _ra_vzm_T_1[15]; // @[VDecodeInstruction.scala 68:16]
- wire [7:0] ra_vzm_b_lo_lo_lo = {ra_vzm_v_1,ra_vzm_v_1,ra_vzm_v_1,ra_vzm_v_1,ra_vzm_v,ra_vzm_v,ra_vzm_v,ra_vzm_v}; // @[VDecodeInstruction.scala 71:19]
- wire [15:0] ra_vzm_b_lo_lo = {ra_vzm_v_3,ra_vzm_v_3,ra_vzm_v_3,ra_vzm_v_3,ra_vzm_v_2,ra_vzm_v_2,ra_vzm_v_2,ra_vzm_v_2,
- ra_vzm_b_lo_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] ra_vzm_b_lo_hi_lo = {ra_vzm_v_5,ra_vzm_v_5,ra_vzm_v_5,ra_vzm_v_5,ra_vzm_v_4,ra_vzm_v_4,ra_vzm_v_4,
- ra_vzm_v_4}; // @[VDecodeInstruction.scala 71:19]
- wire [31:0] ra_vzm_b_lo = {ra_vzm_v_7,ra_vzm_v_7,ra_vzm_v_7,ra_vzm_v_7,ra_vzm_v_6,ra_vzm_v_6,ra_vzm_v_6,ra_vzm_v_6,
- ra_vzm_b_lo_hi_lo,ra_vzm_b_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] ra_vzm_b_hi_lo_lo = {ra_vzm_v_9,ra_vzm_v_9,ra_vzm_v_9,ra_vzm_v_9,ra_vzm_v_8,ra_vzm_v_8,ra_vzm_v_8,
- ra_vzm_v_8}; // @[VDecodeInstruction.scala 71:19]
- wire [15:0] ra_vzm_b_hi_lo = {ra_vzm_v_11,ra_vzm_v_11,ra_vzm_v_11,ra_vzm_v_11,ra_vzm_v_10,ra_vzm_v_10,ra_vzm_v_10,
- ra_vzm_v_10,ra_vzm_b_hi_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] ra_vzm_b_hi_hi_lo = {ra_vzm_v_13,ra_vzm_v_13,ra_vzm_v_13,ra_vzm_v_13,ra_vzm_v_12,ra_vzm_v_12,ra_vzm_v_12,
- ra_vzm_v_12}; // @[VDecodeInstruction.scala 71:19]
- wire [31:0] ra_vzm_b_hi = {ra_vzm_v_15,ra_vzm_v_15,ra_vzm_v_15,ra_vzm_v_15,ra_vzm_v_14,ra_vzm_v_14,ra_vzm_v_14,
- ra_vzm_v_14,ra_vzm_b_hi_hi_lo,ra_vzm_b_hi_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [63:0] ra_vzm_b = {ra_vzm_b_hi,ra_vzm_b_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [63:0] ra_vzm = m ? ra_vzm_b : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _ractive_T = ra_vs | ra_vt; // @[VDecodeInstruction.scala 200:25]
- wire [63:0] _ractive_T_1 = _ractive_T | ra_vu; // @[VDecodeInstruction.scala 200:33]
- wire [63:0] _ractive_T_2 = _ractive_T_1 | ra_vx; // @[VDecodeInstruction.scala 200:41]
- wire [63:0] _ractive_T_3 = _ractive_T_2 | ra_vy; // @[VDecodeInstruction.scala 200:49]
- wire [63:0] _ractive_T_4 = _ractive_T_3 | ra_vz; // @[VDecodeInstruction.scala 200:57]
- wire [63:0] _ractive_T_5 = _ractive_T_4 | ra_vxm; // @[VDecodeInstruction.scala 200:65]
- wire [63:0] _ractive_T_6 = _ractive_T_5 | ra_vym; // @[VDecodeInstruction.scala 200:74]
- wire [63:0] ractivedw = _ractive_T_6 | ra_vzm; // @[VDecodeInstruction.scala 200:83]
- wire [3:0] ractivedi_shiftAmount = vsbits[5:2]; // @[VDecodeInstruction.scala 495:36]
- wire [15:0] _ractivedi_T_1 = 16'h1 << ractivedi_shiftAmount; // @[OneHot.scala 64:12]
- wire ractivedi_v = _ractivedi_T_1[0]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_1 = _ractivedi_T_1[1]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_2 = _ractivedi_T_1[2]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_3 = _ractivedi_T_1[3]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_4 = _ractivedi_T_1[4]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_5 = _ractivedi_T_1[5]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_6 = _ractivedi_T_1[6]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_7 = _ractivedi_T_1[7]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_8 = _ractivedi_T_1[8]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_9 = _ractivedi_T_1[9]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_10 = _ractivedi_T_1[10]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_11 = _ractivedi_T_1[11]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_12 = _ractivedi_T_1[12]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_13 = _ractivedi_T_1[13]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_14 = _ractivedi_T_1[14]; // @[VDecodeInstruction.scala 68:16]
- wire ractivedi_v_15 = _ractivedi_T_1[15]; // @[VDecodeInstruction.scala 68:16]
- wire [7:0] ractivedi_b_lo_lo_lo = {ractivedi_v_1,ractivedi_v_1,ractivedi_v_1,ractivedi_v_1,ractivedi_v,ractivedi_v,
- ractivedi_v,ractivedi_v}; // @[VDecodeInstruction.scala 71:19]
- wire [15:0] ractivedi_b_lo_lo = {ractivedi_v_3,ractivedi_v_3,ractivedi_v_3,ractivedi_v_3,ractivedi_v_2,ractivedi_v_2,
- ractivedi_v_2,ractivedi_v_2,ractivedi_b_lo_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] ractivedi_b_lo_hi_lo = {ractivedi_v_5,ractivedi_v_5,ractivedi_v_5,ractivedi_v_5,ractivedi_v_4,ractivedi_v_4
- ,ractivedi_v_4,ractivedi_v_4}; // @[VDecodeInstruction.scala 71:19]
- wire [31:0] ractivedi_b_lo = {ractivedi_v_7,ractivedi_v_7,ractivedi_v_7,ractivedi_v_7,ractivedi_v_6,ractivedi_v_6,
- ractivedi_v_6,ractivedi_v_6,ractivedi_b_lo_hi_lo,ractivedi_b_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] ractivedi_b_hi_lo_lo = {ractivedi_v_9,ractivedi_v_9,ractivedi_v_9,ractivedi_v_9,ractivedi_v_8,ractivedi_v_8
- ,ractivedi_v_8,ractivedi_v_8}; // @[VDecodeInstruction.scala 71:19]
- wire [15:0] ractivedi_b_hi_lo = {ractivedi_v_11,ractivedi_v_11,ractivedi_v_11,ractivedi_v_11,ractivedi_v_10,
- ractivedi_v_10,ractivedi_v_10,ractivedi_v_10,ractivedi_b_hi_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] ractivedi_b_hi_hi_lo = {ractivedi_v_13,ractivedi_v_13,ractivedi_v_13,ractivedi_v_13,ractivedi_v_12,
- ractivedi_v_12,ractivedi_v_12,ractivedi_v_12}; // @[VDecodeInstruction.scala 71:19]
- wire [31:0] ractivedi_b_hi = {ractivedi_v_15,ractivedi_v_15,ractivedi_v_15,ractivedi_v_15,ractivedi_v_14,
- ractivedi_v_14,ractivedi_v_14,ractivedi_v_14,ractivedi_b_hi_hi_lo,ractivedi_b_hi_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [63:0] ractivedi = {ractivedi_b_hi,ractivedi_b_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [3:0] wactivedw_shiftAmount = vdbits[5:2]; // @[VDecodeInstruction.scala 496:36]
- wire [15:0] _wactivedw_T_1 = 16'h1 << wactivedw_shiftAmount; // @[OneHot.scala 64:12]
- wire wactivedw_v = _wactivedw_T_1[0]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_1 = _wactivedw_T_1[1]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_2 = _wactivedw_T_1[2]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_3 = _wactivedw_T_1[3]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_4 = _wactivedw_T_1[4]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_5 = _wactivedw_T_1[5]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_6 = _wactivedw_T_1[6]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_7 = _wactivedw_T_1[7]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_8 = _wactivedw_T_1[8]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_9 = _wactivedw_T_1[9]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_10 = _wactivedw_T_1[10]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_11 = _wactivedw_T_1[11]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_12 = _wactivedw_T_1[12]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_13 = _wactivedw_T_1[13]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_14 = _wactivedw_T_1[14]; // @[VDecodeInstruction.scala 68:16]
- wire wactivedw_v_15 = _wactivedw_T_1[15]; // @[VDecodeInstruction.scala 68:16]
- wire [7:0] wactivedw_b_lo_lo_lo = {wactivedw_v_1,wactivedw_v_1,wactivedw_v_1,wactivedw_v_1,wactivedw_v,wactivedw_v,
- wactivedw_v,wactivedw_v}; // @[VDecodeInstruction.scala 71:19]
- wire [15:0] wactivedw_b_lo_lo = {wactivedw_v_3,wactivedw_v_3,wactivedw_v_3,wactivedw_v_3,wactivedw_v_2,wactivedw_v_2,
- wactivedw_v_2,wactivedw_v_2,wactivedw_b_lo_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] wactivedw_b_lo_hi_lo = {wactivedw_v_5,wactivedw_v_5,wactivedw_v_5,wactivedw_v_5,wactivedw_v_4,wactivedw_v_4
- ,wactivedw_v_4,wactivedw_v_4}; // @[VDecodeInstruction.scala 71:19]
- wire [31:0] wactivedw_b_lo = {wactivedw_v_7,wactivedw_v_7,wactivedw_v_7,wactivedw_v_7,wactivedw_v_6,wactivedw_v_6,
- wactivedw_v_6,wactivedw_v_6,wactivedw_b_lo_hi_lo,wactivedw_b_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] wactivedw_b_hi_lo_lo = {wactivedw_v_9,wactivedw_v_9,wactivedw_v_9,wactivedw_v_9,wactivedw_v_8,wactivedw_v_8
- ,wactivedw_v_8,wactivedw_v_8}; // @[VDecodeInstruction.scala 71:19]
- wire [15:0] wactivedw_b_hi_lo = {wactivedw_v_11,wactivedw_v_11,wactivedw_v_11,wactivedw_v_11,wactivedw_v_10,
- wactivedw_v_10,wactivedw_v_10,wactivedw_v_10,wactivedw_b_hi_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] wactivedw_b_hi_hi_lo = {wactivedw_v_13,wactivedw_v_13,wactivedw_v_13,wactivedw_v_13,wactivedw_v_12,
- wactivedw_v_12,wactivedw_v_12,wactivedw_v_12}; // @[VDecodeInstruction.scala 71:19]
- wire [31:0] wactivedw_b_hi = {wactivedw_v_15,wactivedw_v_15,wactivedw_v_15,wactivedw_v_15,wactivedw_v_14,
- wactivedw_v_14,wactivedw_v_14,wactivedw_v_14,wactivedw_b_hi_hi_lo,wactivedw_b_hi_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [63:0] wactivedw = {wactivedw_b_hi,wactivedw_b_lo}; // @[VDecodeInstruction.scala 71:19]
- wire s = func2[3]; // @[VDecodeInstruction.scala 207:18]
- wire [5:0] _vs_T_2 = vsbits + 6'h3; // @[VDecodeInstruction.scala 208:28]
- wire [6:0] _vs_T_3 = {{1'd0}, vsbits}; // @[VDecodeInstruction.scala 208:42]
- wire [5:0] vssl = s ? _vs_T_2 : _vs_T_3[5:0]; // @[VDecodeInstruction.scala 208:17]
- wire [6:0] _vt_T_1 = {{1'd0}, vtbits}; // @[VDecodeInstruction.scala 209:28]
- wire [5:0] _vt_T_4 = vsbits + 6'h1; // @[VDecodeInstruction.scala 209:42]
- wire [5:0] vtsl = s ? _vt_T_1[5:0] : _vt_T_4; // @[VDecodeInstruction.scala 209:17]
- wire [5:0] _vu_T_2 = vtbits + 6'h1; // @[VDecodeInstruction.scala 210:28]
- wire [5:0] _vu_T_4 = vsbits + 6'h2; // @[VDecodeInstruction.scala 210:42]
- wire [5:0] vusl = s ? _vu_T_2 : _vu_T_4; // @[VDecodeInstruction.scala 210:17]
- wire [5:0] _vy_T_3 = vtbits + 6'h2; // @[VDecodeInstruction.scala 212:28]
- wire [5:0] vysl = s ? _vy_T_3 : _vs_T_2; // @[VDecodeInstruction.scala 212:17]
- wire [5:0] _vz_T_3 = vtbits + 6'h3; // @[VDecodeInstruction.scala 213:28]
- wire [5:0] vzsl = s ? _vz_T_3 : _vt_T_1[5:0]; // @[VDecodeInstruction.scala 213:17]
- wire [63:0] ra_vs_1 = 64'h1 << vssl; // @[OneHot.scala 64:12]
- wire _ra_vt_T_3 = aconv_bit_30 | ~s; // @[VDecodeInstruction.scala 222:27]
- wire [63:0] _ra_vt_T_4 = 64'h1 << vtsl; // @[OneHot.scala 64:12]
- wire [63:0] ra_vt_1 = _ra_vt_T_3 ? _ra_vt_T_4 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _ra_vu_T_4 = 64'h1 << vusl; // @[OneHot.scala 64:12]
- wire [63:0] ra_vu_1 = _ra_vt_T_3 ? _ra_vu_T_4 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _ra_vy_T_4 = 64'h1 << vysl; // @[OneHot.scala 64:12]
- wire [63:0] ra_vy_1 = _ra_vt_T_3 ? _ra_vy_T_4 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _ra_vz_T_2 = 64'h1 << vzsl; // @[OneHot.scala 64:12]
- wire [63:0] ra_vz_1 = aconv_bit_30 ? _ra_vz_T_2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _ractive_T_7 = ra_vs_1 | ra_vt_1; // @[VDecodeInstruction.scala 234:25]
- wire [63:0] _ractive_T_8 = _ractive_T_7 | ra_vu_1; // @[VDecodeInstruction.scala 234:33]
- wire [63:0] _ractive_T_9 = _ractive_T_8 | ra_vu_1; // @[VDecodeInstruction.scala 234:41]
- wire [63:0] _ractive_T_10 = _ractive_T_9 | ra_vy_1; // @[VDecodeInstruction.scala 234:49]
- wire [63:0] ractivesl = _ractive_T_10 | ra_vz_1; // @[VDecodeInstruction.scala 234:57]
- wire [5:0] _ractiveconv1_T_1 = {vsbits[5:4],4'h0}; // @[Cat.scala 31:58]
- wire [70:0] _ractiveconv1_T_2 = 71'hff << _ractiveconv1_T_1; // @[VDecodeInstruction.scala 516:30]
- wire [5:0] _ractiveconv2_T_1 = {func2[5:3],3'h0}; // @[Cat.scala 31:58]
- wire [70:0] _ractiveconv2_T_2 = 71'hff << _ractiveconv2_T_1; // @[VDecodeInstruction.scala 517:30]
- wire [5:0] _ractiveaset_T_1 = {vsbits[5:3],3'h0}; // @[Cat.scala 31:58]
- wire [70:0] _ractiveaset_T_2 = 71'hff << _ractiveaset_T_1; // @[VDecodeInstruction.scala 518:30]
- wire [5:0] _wactiveconv_T_1 = {vdbits[5:4],4'h0}; // @[Cat.scala 31:58]
- wire [70:0] _wactiveconv_T_2 = 71'hff << _wactiveconv_T_1; // @[VDecodeInstruction.scala 519:30]
- wire _io_out_sz_T = sz == 2'h2; // @[VDecodeInstruction.scala 534:23]
- wire _io_out_sz_T_1 = sz == 2'h1; // @[VDecodeInstruction.scala 534:35]
- wire _io_out_sz_T_2 = sz == 2'h0; // @[VDecodeInstruction.scala 534:47]
- wire [1:0] io_out_sz_hi = {_io_out_sz_T,_io_out_sz_T_1}; // @[Cat.scala 31:58]
- wire _io_out_vs_valid_T = vadwconv | adwinit; // @[VDecodeInstruction.scala 542:31]
- wire _io_out_vt_valid_T_5 = vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4; // @[VDecodeInstruction.scala 543:85]
- wire _io_out_vt_valid_T_6 = vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt6; // @[VDecodeInstruction.scala 543:94]
- wire _io_out_vu_valid_T_5 = vadwconv | vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2; // @[VDecodeInstruction.scala 544:82]
- wire _io_out_vu_valid_T_15 = m & vevn3; // @[VDecodeInstruction.scala 544:179]
- wire _io_out_vz_valid_T_6 = _io_out_vu_valid_T_5 | vslideh2; // @[VDecodeInstruction.scala 547:90]
- wire _io_out_sv_valid_T_5 = vdup | vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt6; // @[VDecodeInstruction.scala 548:78]
- wire [5:0] _io_out_ve_addr_T_9 = vdbits + 6'h1; // @[VDecodeInstruction.scala 552:121]
- wire [5:0] _io_out_ve_addr_T_11 = vdbits + 6'h4; // @[VDecodeInstruction.scala 553:35]
- wire [5:0] _io_out_ve_addr_T_14 = m ? _io_out_ve_addr_T_11 : _io_out_ve_addr_T_9; // @[VDecodeInstruction.scala 553:24]
- wire [5:0] _io_out_ve_addr_T_15 = _io_out_vz_valid_T_6 | vzip ? _io_out_ve_addr_T_9 : _io_out_ve_addr_T_14; // @[VDecodeInstruction.scala 552:24]
- wire [5:0] _io_out_vs_addr_T_2 = vmadd | vst | vstq ? vdbits : vsbits; // @[VDecodeInstruction.scala 558:24]
- wire [5:0] _io_out_vs_addr_T_3 = vslideh2 ? vssl : _io_out_vs_addr_T_2; // @[VDecodeInstruction.scala 557:24]
- wire [5:0] _io_out_vt_addr_T_5 = _io_out_vu_valid_T_15 ? _vt_T_4 : vtbits; // @[VDecodeInstruction.scala 563:24]
- wire [5:0] _io_out_vt_addr_T_6 = vslideh2 ? vtsl : _io_out_vt_addr_T_5; // @[VDecodeInstruction.scala 562:24]
- wire [5:0] _io_out_vt_addr_T_7 = adwinit ? _vt_T_4 : _io_out_vt_addr_T_6; // @[VDecodeInstruction.scala 561:24]
- wire _io_out_vu_addr_T_4 = vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2; // @[VDecodeInstruction.scala 566:73]
- wire [5:0] _io_out_vu_addr_T_9 = vsbits + 6'h4; // @[VDecodeInstruction.scala 568:55]
- wire [5:0] _io_out_vu_addr_T_12 = m ? _io_out_vu_addr_T_9 : _vt_T_4; // @[VDecodeInstruction.scala 568:44]
- wire [5:0] _io_out_vu_addr_T_20 = vevn3 ? vtbits : func2; // @[VDecodeInstruction.scala 572:24]
- wire [5:0] _io_out_vu_addr_T_21 = vmadd ? vsbits : _io_out_vu_addr_T_20; // @[VDecodeInstruction.scala 571:24]
- wire [5:0] _io_out_vu_addr_T_22 = vmacc | vadd3 | vsel ? vdbits : _io_out_vu_addr_T_21; // @[VDecodeInstruction.scala 570:24]
- wire [5:0] _io_out_vu_addr_T_23 = vsraqs ? _io_out_vu_addr_T_12 : _io_out_vu_addr_T_22; // @[VDecodeInstruction.scala 569:24]
- wire [5:0] _io_out_vu_addr_T_24 = vacc | vsrans ? _io_out_vu_addr_T_12 : _io_out_vu_addr_T_23; // @[VDecodeInstruction.scala 568:24]
- wire [5:0] _io_out_vu_addr_T_25 = vslideh2 ? vusl : _io_out_vu_addr_T_24; // @[VDecodeInstruction.scala 567:24]
- wire [5:0] _io_out_vu_addr_T_26 = vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2 ? _vt_T_4 : _io_out_vu_addr_T_25; // @[VDecodeInstruction.scala 566:24]
- wire [5:0] _io_out_vx_addr_T_9 = vsbits + 6'h8; // @[VDecodeInstruction.scala 576:47]
- wire [5:0] _io_out_vx_addr_T_12 = m ? _io_out_vx_addr_T_9 : _vu_T_4; // @[VDecodeInstruction.scala 576:36]
- wire [5:0] _io_out_vx_addr_T_13 = vsraqs ? _io_out_vx_addr_T_12 : vusl; // @[VDecodeInstruction.scala 576:24]
- wire [5:0] _io_out_vx_addr_T_14 = adwinit | vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2 ? _vu_T_4 :
- _io_out_vx_addr_T_13; // @[VDecodeInstruction.scala 575:24]
- wire [5:0] _io_out_vy_addr_T_2 = vsraqs ? vtbits : vysl; // @[VDecodeInstruction.scala 580:24]
- wire [5:0] _io_out_vy_addr_T_3 = adwinit ? _vs_T_2 : _io_out_vy_addr_T_2; // @[VDecodeInstruction.scala 579:24]
- wire [5:0] _io_out_vz_addr_T_8 = vsbits + 6'hc; // @[VDecodeInstruction.scala 584:47]
- wire [5:0] _io_out_vz_addr_T_11 = m ? _io_out_vz_addr_T_8 : _vs_T_2; // @[VDecodeInstruction.scala 584:36]
- wire [5:0] _io_out_vz_addr_T_12 = vsraqs ? _io_out_vz_addr_T_11 : vzsl; // @[VDecodeInstruction.scala 584:24]
- wire [5:0] _io_out_vz_addr_T_13 = _io_out_vu_addr_T_4 ? _vs_T_2 : _io_out_vz_addr_T_12; // @[VDecodeInstruction.scala 583:24]
- wire [1:0] _io_out_sv_data_T_3 = sz - 2'h1; // @[VDecodeInstruction.scala 596:64]
- wire _io_out_sv_data_T_4 = _io_out_sv_data_T_3 == 2'h0; // @[VDecodeInstruction.scala 487:14]
- wire [31:0] _io_out_sv_data_T_9 = {io_in_data[7:0],io_in_data[7:0],io_in_data[7:0],io_in_data[7:0]}; // @[Cat.scala 31:58]
- wire [31:0] _io_out_sv_data_T_10 = _io_out_sv_data_T_4 ? _io_out_sv_data_T_9 : 32'h0; // @[Library.scala 32:8]
- wire _io_out_sv_data_T_11 = _io_out_sv_data_T_3 == 2'h1; // @[VDecodeInstruction.scala 488:20]
- wire [31:0] _io_out_sv_data_T_14 = {io_in_data[15:0],io_in_data[15:0]}; // @[Cat.scala 31:58]
- wire [31:0] _io_out_sv_data_T_15 = _io_out_sv_data_T_11 ? _io_out_sv_data_T_14 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _io_out_sv_data_T_16 = _io_out_sv_data_T_10 | _io_out_sv_data_T_15; // @[VDecodeInstruction.scala 487:72]
- wire _io_out_sv_data_T_17 = _io_out_sv_data_T_3 == 2'h2; // @[VDecodeInstruction.scala 489:20]
- wire [31:0] _io_out_sv_data_T_19 = _io_out_sv_data_T_17 ? io_in_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _io_out_sv_data_T_20 = _io_out_sv_data_T_16 | _io_out_sv_data_T_19; // @[VDecodeInstruction.scala 488:58]
- wire [31:0] _io_out_sv_data_T_27 = _io_out_sz_T_2 ? _io_out_sv_data_T_9 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _io_out_sv_data_T_32 = _io_out_sz_T_1 ? _io_out_sv_data_T_14 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _io_out_sv_data_T_33 = _io_out_sv_data_T_27 | _io_out_sv_data_T_32; // @[VDecodeInstruction.scala 487:72]
- wire [31:0] _io_out_sv_data_T_36 = _io_out_sz_T ? io_in_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _io_out_sv_data_T_37 = _io_out_sv_data_T_33 | _io_out_sv_data_T_36; // @[VDecodeInstruction.scala 488:58]
- wire [31:0] _io_out_sv_data_T_38 = vaddw | vmulw | vsubw ? _io_out_sv_data_T_20 : _io_out_sv_data_T_37; // @[VDecodeInstruction.scala 596:24]
- wire [1:0] _T_242 = io_out_sz[1] + io_out_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_72 = {{1'd0}, io_out_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_244 = _GEN_72 + _T_242; // @[Bitwise.scala 48:55]
- wire _T_250 = ~io_out_cmdsync; // @[VDecodeInstruction.scala 600:31]
- wire [5:0] cmdqchk = {io_undef,io_cmdq_alu,io_cmdq_conv,io_cmdq_ldst,io_cmdq_ld,io_cmdq_st}; // @[Cat.scala 31:58]
- wire [1:0] _T_274 = cmdqchk[1] + cmdqchk[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_73 = {{1'd0}, cmdqchk[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_276 = _GEN_73 + _T_274; // @[Bitwise.scala 48:55]
- wire [1:0] _T_278 = cmdqchk[4] + cmdqchk[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_74 = {{1'd0}, cmdqchk[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_280 = _GEN_74 + _T_278; // @[Bitwise.scala 48:55]
- wire [2:0] _T_282 = _T_276[1:0] + _T_280[1:0]; // @[Bitwise.scala 48:55]
- wire _io_actv_ractive_T_5 = vfmt6 & ~vslideh2; // @[VDecodeInstruction.scala 615:17]
- wire _io_actv_ractive_T_6 = _io_out_vt_valid_T_5 | _io_actv_ractive_T_5; // @[VDecodeInstruction.scala 614:53]
- wire [63:0] io_actv_ractive_vs = 64'h1 << vsbits; // @[OneHot.scala 64:12]
- wire [63:0] io_actv_ractive_vsm = m ? ractivedi : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_vt_T_1 = 64'h1 << vtbits; // @[OneHot.scala 64:12]
- wire [63:0] io_actv_ractive_vt = aconv_bit_30 ? _io_actv_ractive_vt_T_1 : 64'h0; // @[Library.scala 32:8]
- wire _io_actv_ractive_vtm_T_1 = m & aconv_bit_30; // @[VDecodeInstruction.scala 89:17]
- wire [3:0] io_actv_ractive_vtm_shiftAmount = vtbits[5:2]; // @[VDecodeInstruction.scala 89:41]
- wire [15:0] _io_actv_ractive_vtm_T_3 = 16'h1 << io_actv_ractive_vtm_shiftAmount; // @[OneHot.scala 64:12]
- wire io_actv_ractive_vtm_v = _io_actv_ractive_vtm_T_3[0]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_1 = _io_actv_ractive_vtm_T_3[1]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_2 = _io_actv_ractive_vtm_T_3[2]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_3 = _io_actv_ractive_vtm_T_3[3]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_4 = _io_actv_ractive_vtm_T_3[4]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_5 = _io_actv_ractive_vtm_T_3[5]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_6 = _io_actv_ractive_vtm_T_3[6]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_7 = _io_actv_ractive_vtm_T_3[7]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_8 = _io_actv_ractive_vtm_T_3[8]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_9 = _io_actv_ractive_vtm_T_3[9]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_10 = _io_actv_ractive_vtm_T_3[10]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_11 = _io_actv_ractive_vtm_T_3[11]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_12 = _io_actv_ractive_vtm_T_3[12]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_13 = _io_actv_ractive_vtm_T_3[13]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_14 = _io_actv_ractive_vtm_T_3[14]; // @[VDecodeInstruction.scala 68:16]
- wire io_actv_ractive_vtm_v_15 = _io_actv_ractive_vtm_T_3[15]; // @[VDecodeInstruction.scala 68:16]
- wire [7:0] io_actv_ractive_vtm_b_lo_lo_lo = {io_actv_ractive_vtm_v_1,io_actv_ractive_vtm_v_1,io_actv_ractive_vtm_v_1,
- io_actv_ractive_vtm_v_1,io_actv_ractive_vtm_v,io_actv_ractive_vtm_v,io_actv_ractive_vtm_v,io_actv_ractive_vtm_v}; // @[VDecodeInstruction.scala 71:19]
- wire [15:0] io_actv_ractive_vtm_b_lo_lo = {io_actv_ractive_vtm_v_3,io_actv_ractive_vtm_v_3,io_actv_ractive_vtm_v_3,
- io_actv_ractive_vtm_v_3,io_actv_ractive_vtm_v_2,io_actv_ractive_vtm_v_2,io_actv_ractive_vtm_v_2,
- io_actv_ractive_vtm_v_2,io_actv_ractive_vtm_b_lo_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] io_actv_ractive_vtm_b_lo_hi_lo = {io_actv_ractive_vtm_v_5,io_actv_ractive_vtm_v_5,io_actv_ractive_vtm_v_5,
- io_actv_ractive_vtm_v_5,io_actv_ractive_vtm_v_4,io_actv_ractive_vtm_v_4,io_actv_ractive_vtm_v_4,
- io_actv_ractive_vtm_v_4}; // @[VDecodeInstruction.scala 71:19]
- wire [31:0] io_actv_ractive_vtm_b_lo = {io_actv_ractive_vtm_v_7,io_actv_ractive_vtm_v_7,io_actv_ractive_vtm_v_7,
- io_actv_ractive_vtm_v_7,io_actv_ractive_vtm_v_6,io_actv_ractive_vtm_v_6,io_actv_ractive_vtm_v_6,
- io_actv_ractive_vtm_v_6,io_actv_ractive_vtm_b_lo_hi_lo,io_actv_ractive_vtm_b_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] io_actv_ractive_vtm_b_hi_lo_lo = {io_actv_ractive_vtm_v_9,io_actv_ractive_vtm_v_9,io_actv_ractive_vtm_v_9,
- io_actv_ractive_vtm_v_9,io_actv_ractive_vtm_v_8,io_actv_ractive_vtm_v_8,io_actv_ractive_vtm_v_8,
- io_actv_ractive_vtm_v_8}; // @[VDecodeInstruction.scala 71:19]
- wire [15:0] io_actv_ractive_vtm_b_hi_lo = {io_actv_ractive_vtm_v_11,io_actv_ractive_vtm_v_11,io_actv_ractive_vtm_v_11,
- io_actv_ractive_vtm_v_11,io_actv_ractive_vtm_v_10,io_actv_ractive_vtm_v_10,io_actv_ractive_vtm_v_10,
- io_actv_ractive_vtm_v_10,io_actv_ractive_vtm_b_hi_lo_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [7:0] io_actv_ractive_vtm_b_hi_hi_lo = {io_actv_ractive_vtm_v_13,io_actv_ractive_vtm_v_13,
- io_actv_ractive_vtm_v_13,io_actv_ractive_vtm_v_13,io_actv_ractive_vtm_v_12,io_actv_ractive_vtm_v_12,
- io_actv_ractive_vtm_v_12,io_actv_ractive_vtm_v_12}; // @[VDecodeInstruction.scala 71:19]
- wire [31:0] io_actv_ractive_vtm_b_hi = {io_actv_ractive_vtm_v_15,io_actv_ractive_vtm_v_15,io_actv_ractive_vtm_v_15,
- io_actv_ractive_vtm_v_15,io_actv_ractive_vtm_v_14,io_actv_ractive_vtm_v_14,io_actv_ractive_vtm_v_14,
- io_actv_ractive_vtm_v_14,io_actv_ractive_vtm_b_hi_hi_lo,io_actv_ractive_vtm_b_hi_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [63:0] io_actv_ractive_vtm_b = {io_actv_ractive_vtm_b_hi,io_actv_ractive_vtm_b_lo}; // @[VDecodeInstruction.scala 71:19]
- wire [63:0] io_actv_ractive_vtm = _io_actv_ractive_vtm_T_1 ? io_actv_ractive_vtm_b : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_7 = io_actv_ractive_vs | io_actv_ractive_vsm; // @[VDecodeInstruction.scala 97:8]
- wire [63:0] _io_actv_ractive_T_8 = _io_actv_ractive_T_7 | io_actv_ractive_vt; // @[VDecodeInstruction.scala 97:14]
- wire [63:0] _io_actv_ractive_T_9 = _io_actv_ractive_T_8 | io_actv_ractive_vtm; // @[VDecodeInstruction.scala 97:19]
- wire [63:0] _io_actv_ractive_T_10 = _io_actv_ractive_T_6 ? _io_actv_ractive_T_9 : 64'h0; // @[Library.scala 32:8]
- wire _io_actv_ractive_T_11 = vsraqs | vsrans; // @[VDecodeInstruction.scala 616:18]
- wire [64:0] _io_actv_ractive_vs_T_3 = {io_actv_ractive_vs,1'h0}; // @[Cat.scala 31:58]
- wire [63:0] io_actv_ractive_vs_1 = _io_actv_ractive_vs_T_3[63:0]; // @[VDecodeInstruction.scala 102:48]
- wire [67:0] _io_actv_ractive_vsm_T_6 = {ractivedi_b_hi,ractivedi_b_lo,4'h0}; // @[Cat.scala 31:58]
- wire [63:0] io_actv_ractive_vsm_1 = m ? _io_actv_ractive_vsm_T_6[63:0] : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_12 = io_actv_ractive_vs_1 | io_actv_ractive_vsm_1; // @[VDecodeInstruction.scala 106:8]
- wire [63:0] _io_actv_ractive_T_13 = _io_actv_ractive_T_11 ? _io_actv_ractive_T_12 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_14 = _io_actv_ractive_T_10 | _io_actv_ractive_T_13; // @[VDecodeInstruction.scala 615:80]
- wire [65:0] _io_actv_ractive_vs_T_6 = {io_actv_ractive_vs,2'h0}; // @[Cat.scala 31:58]
- wire [63:0] io_actv_ractive_vs_2 = _io_actv_ractive_vs_T_6[63:0]; // @[VDecodeInstruction.scala 111:48]
- wire [71:0] _io_actv_ractive_vsm_T_11 = {ractivedi_b_hi,ractivedi_b_lo,8'h0}; // @[Cat.scala 31:58]
- wire [63:0] io_actv_ractive_vsm_2 = m ? _io_actv_ractive_vsm_T_11[63:0] : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_15 = io_actv_ractive_vs_2 | io_actv_ractive_vsm_2; // @[VDecodeInstruction.scala 115:8]
- wire [63:0] _io_actv_ractive_T_16 = vsraqs ? _io_actv_ractive_T_15 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_17 = _io_actv_ractive_T_14 | _io_actv_ractive_T_16; // @[VDecodeInstruction.scala 616:80]
- wire [66:0] _io_actv_ractive_vs_T_9 = {io_actv_ractive_vs,3'h0}; // @[Cat.scala 31:58]
- wire [63:0] io_actv_ractive_vs_3 = _io_actv_ractive_vs_T_9[63:0]; // @[VDecodeInstruction.scala 120:48]
- wire [75:0] _io_actv_ractive_vsm_T_16 = {ractivedi_b_hi,ractivedi_b_lo,12'h0}; // @[Cat.scala 31:58]
- wire [63:0] io_actv_ractive_vsm_3 = m ? _io_actv_ractive_vsm_T_16[63:0] : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_18 = io_actv_ractive_vs_3 | io_actv_ractive_vsm_3; // @[VDecodeInstruction.scala 124:8]
- wire [63:0] _io_actv_ractive_T_19 = vsraqs ? _io_actv_ractive_T_18 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_20 = _io_actv_ractive_T_17 | _io_actv_ractive_T_19; // @[VDecodeInstruction.scala 617:80]
- wire _io_actv_ractive_T_23 = vmacc | vmadd | vst | vstq; // @[VDecodeInstruction.scala 619:33]
- wire [63:0] io_actv_ractive_vd = 64'h1 << vdbits; // @[OneHot.scala 64:12]
- wire [63:0] io_actv_ractive_vdm = m ? wactivedw : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_24 = io_actv_ractive_vd | io_actv_ractive_vdm; // @[VDecodeInstruction.scala 132:8]
- wire [63:0] _io_actv_ractive_T_25 = _io_actv_ractive_T_23 ? _io_actv_ractive_T_24 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_26 = _io_actv_ractive_T_20 | _io_actv_ractive_T_25; // @[VDecodeInstruction.scala 618:80]
- wire [63:0] _io_actv_ractive_T_27 = vadwconv ? ractivedw : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_28 = _io_actv_ractive_T_26 | _io_actv_ractive_T_27; // @[VDecodeInstruction.scala 619:80]
- wire [63:0] _io_actv_ractive_T_29 = adwinit ? ractivedi : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_30 = _io_actv_ractive_T_28 | _io_actv_ractive_T_29; // @[VDecodeInstruction.scala 620:80]
- wire [63:0] _io_actv_ractive_T_31 = vslideh2 ? ractivesl : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_32 = _io_actv_ractive_T_30 | _io_actv_ractive_T_31; // @[VDecodeInstruction.scala 621:80]
- wire _io_actv_ractive_T_33 = aconv | actr; // @[VDecodeInstruction.scala 623:17]
- wire [63:0] ractiveconv1 = _ractiveconv1_T_2[63:0]; // @[VDecodeInstruction.scala 502:26 516:18]
- wire [63:0] _io_actv_ractive_T_34 = _io_actv_ractive_T_33 ? ractiveconv1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_35 = _io_actv_ractive_T_32 | _io_actv_ractive_T_34; // @[VDecodeInstruction.scala 622:80]
- wire [63:0] ractiveconv2 = _ractiveconv2_T_2[63:0]; // @[VDecodeInstruction.scala 503:26 517:18]
- wire [63:0] _io_actv_ractive_T_36 = aconv ? ractiveconv2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_ractive_T_37 = _io_actv_ractive_T_35 | _io_actv_ractive_T_36; // @[VDecodeInstruction.scala 623:80]
- wire [63:0] ractiveaset = _ractiveaset_T_2[63:0]; // @[VDecodeInstruction.scala 504:26 518:18]
- wire [63:0] _io_actv_ractive_T_38 = acset ? ractiveaset : 64'h0; // @[Library.scala 32:8]
- wire _io_actv_wactive_T_5 = _io_out_vt_valid_T_6 | vdup; // @[VDecodeInstruction.scala 628:62]
- wire _io_actv_wactive_T_6 = _io_actv_wactive_T_5 | vld; // @[VDecodeInstruction.scala 629:16]
- wire [63:0] _io_actv_wactive_T_8 = _io_actv_wactive_T_6 ? _io_actv_ractive_T_24 : 64'h0; // @[Library.scala 32:8]
- wire _io_actv_wactive_T_14 = vmvp | vmulw | vacc | vaddw | vsubw | vevnodd | vzip; // @[VDecodeInstruction.scala 630:62]
- wire [64:0] _io_actv_wactive_vd_T_3 = {io_actv_ractive_vd,1'h0}; // @[Cat.scala 31:58]
- wire [63:0] io_actv_wactive_vd_1 = _io_actv_wactive_vd_T_3[63:0]; // @[VDecodeInstruction.scala 153:48]
- wire [67:0] _io_actv_wactive_vdm_T_6 = {wactivedw_b_hi,wactivedw_b_lo,4'h0}; // @[Cat.scala 31:58]
- wire [63:0] io_actv_wactive_vdm_1 = m ? _io_actv_wactive_vdm_T_6[63:0] : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_wactive_T_15 = io_actv_wactive_vd_1 | io_actv_wactive_vdm_1; // @[VDecodeInstruction.scala 157:8]
- wire [63:0] _io_actv_wactive_T_16 = _io_actv_wactive_T_14 ? _io_actv_wactive_T_15 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_wactive_T_17 = _io_actv_wactive_T_8 | _io_actv_wactive_T_16; // @[VDecodeInstruction.scala 629:80]
- wire [63:0] _io_actv_wactive_T_18 = vdwconv ? wactivedw : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _io_actv_wactive_T_19 = _io_actv_wactive_T_17 | _io_actv_wactive_T_18; // @[VDecodeInstruction.scala 631:80]
- wire [63:0] wactiveconv = _wactiveconv_T_2[63:0]; // @[VDecodeInstruction.scala 505:26 519:18]
- wire [63:0] _io_actv_wactive_T_20 = vcget ? wactiveconv : 64'h0; // @[Library.scala 32:8]
- assign io_out_op = _op_T_148 | _op_T_149; // @[VDecodeInstruction.scala 480:38]
- assign io_out_f2 = func2[2:0]; // @[VDecodeInstruction.scala 533:21]
- assign io_out_sz = {io_out_sz_hi,_io_out_sz_T_2}; // @[Cat.scala 31:58]
- assign io_out_m = m & ~vdmulh2 & ~vmul2 & ~vmulh2 & ~vmulhu2 & ~vmuls2 & ~vmv2 & ~vslidehn2 & ~vslidehp2; // @[VDecodeInstruction.scala 535:97]
- assign io_out_vd_valid = vdwconv | vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt6 | vld | vdup | vcget; // @[VDecodeInstruction.scala 538:99]
- assign io_out_vd_addr = io_in_inst[11:6]; // @[VDecodeInstruction.scala 50:20]
- assign io_out_ve_addr = vodd ? vdbits : _io_out_ve_addr_T_15; // @[VDecodeInstruction.scala 551:24]
- assign io_out_vf_addr = vdbits + 6'h2; // @[VDecodeInstruction.scala 554:28]
- assign io_out_vg_addr = vdbits + 6'h3; // @[VDecodeInstruction.scala 555:28]
- assign io_out_vs_valid = vadwconv | adwinit | vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt6 | vst | vstq | aconv; // @[VDecodeInstruction.scala 542:111]
- assign io_out_vs_addr = vadwconv ? vsdw : _io_out_vs_addr_T_3; // @[VDecodeInstruction.scala 556:24]
- assign io_out_vt_valid = _io_out_vs_valid_T | aconv_bit_30 & (vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt6); // @[VDecodeInstruction.scala 543:42]
- assign io_out_vt_addr = vadwconv ? vtdw : _io_out_vt_addr_T_7; // @[VDecodeInstruction.scala 560:24]
- assign io_out_vu_valid = vadwconv | vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2 | vacc | vadd3 | vmacc | vmadd
- | aconv | vsrans | vsraqs | vsel | vslideh2 | m & vevn3; // @[VDecodeInstruction.scala 544:174]
- assign io_out_vu_addr = vadwconv ? vudw : _io_out_vu_addr_T_26; // @[VDecodeInstruction.scala 565:24]
- assign io_out_vx_valid = _io_out_vs_valid_T | vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2 | vslideh2 | vsraqs; // @[VDecodeInstruction.scala 545:113]
- assign io_out_vx_addr = vadwconv ? func2 : _io_out_vx_addr_T_14; // @[VDecodeInstruction.scala 574:24]
- assign io_out_vy_valid = _io_out_vs_valid_T | vslideh2 | aconv_bit_30 & vsraqs; // @[VDecodeInstruction.scala 546:54]
- assign io_out_vy_addr = vadwconv ? vydw : _io_out_vy_addr_T_3; // @[VDecodeInstruction.scala 578:24]
- assign io_out_vz_valid = _io_out_vu_valid_T_5 | vslideh2 | vsraqs; // @[VDecodeInstruction.scala 547:102]
- assign io_out_vz_addr = vadwconv ? vzdw : _io_out_vz_addr_T_13; // @[VDecodeInstruction.scala 582:24]
- assign io_out_sv_valid = x & (vdup | vfmt0 | vfmt1 | vfmt2 | vfmt3 | vfmt4 | vfmt6); // @[VDecodeInstruction.scala 548:24]
- assign io_out_sv_addr = io_in_addr; // @[VDecodeInstruction.scala 594:18]
- assign io_out_sv_data = vldstdec ? io_in_data : _io_out_sv_data_T_38; // @[VDecodeInstruction.scala 595:24]
- assign io_out_cmdsync = adwinit | vadwconv | vdmulh2 | vmul2 | vmulh2 | vmulhu2 | vmuls2 | vmv2 | vslideh2 | vsraqs; // @[VDecodeInstruction.scala 536:112]
- assign io_cmdq_alu = _io_out_sv_valid_T_5 | vadwconv | adwinit; // @[VDecodeInstruction.scala 604:90]
- assign io_cmdq_conv = aconv | vcget | acset | actr; // @[VDecodeInstruction.scala 605:43]
- assign io_cmdq_ldst = vldst & ~uncached; // @[VDecodeInstruction.scala 606:25]
- assign io_cmdq_ld = vld & uncached; // @[VDecodeInstruction.scala 607:21]
- assign io_cmdq_st = (vst | vstq) & uncached; // @[VDecodeInstruction.scala 608:31]
- assign io_actv_ractive = _io_actv_ractive_T_37 | _io_actv_ractive_T_38; // @[VDecodeInstruction.scala 624:80]
- assign io_actv_wactive = _io_actv_wactive_T_19 | _io_actv_wactive_T_20; // @[VDecodeInstruction.scala 632:80]
- assign io_undef = ~undef_value_6_0; // @[VDecodeInstruction.scala 391:15]
- always @(posedge clock) begin
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(vdup & vldstdec))) begin
- $fatal; // @[VDecodeInstruction.scala 249:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(vdup & vldstdec))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VDecodeInstruction.scala:249 assert(!(vdup && vldstdec))\n"); // @[VDecodeInstruction.scala 249:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_233 == 7'h1)) begin
- $fatal; // @[VDecodeInstruction.scala 392:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_233 == 7'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VDecodeInstruction.scala:392 assert(PopCount(Cat(vopbits, undef)) === 1.U)\n"); // @[VDecodeInstruction.scala 392:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_244[1:0] <= 2'h1)) begin
- $fatal; // @[VDecodeInstruction.scala 599:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_244[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VDecodeInstruction.scala:599 assert(PopCount(io.out.sz) <= 1.U)\n"); // @[VDecodeInstruction.scala 599:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(~(io_out_vx_valid & ~io_out_cmdsync))) begin
- $fatal; // @[VDecodeInstruction.scala 600:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(~(io_out_vx_valid & ~io_out_cmdsync))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VDecodeInstruction.scala:600 assert(!(io.out.vx.valid && !io.out.cmdsync))\n"); // @[VDecodeInstruction.scala 600:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(~(io_out_vy_valid & _T_250))) begin
- $fatal; // @[VDecodeInstruction.scala 601:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(~(io_out_vy_valid & _T_250))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VDecodeInstruction.scala:601 assert(!(io.out.vy.valid && !io.out.cmdsync))\n"); // @[VDecodeInstruction.scala 601:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(~(io_out_vz_valid & _T_250))) begin
- $fatal; // @[VDecodeInstruction.scala 602:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(~(io_out_vz_valid & _T_250))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VDecodeInstruction.scala:602 assert(!(io.out.vz.valid && !io.out.cmdsync))\n"); // @[VDecodeInstruction.scala 602:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_282 == 3'h1)) begin
- $fatal; // @[VDecodeInstruction.scala 611:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_282 == 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VDecodeInstruction.scala:611 assert(PopCount(cmdqchk) === 1.U)\n"); // @[VDecodeInstruction.scala 611:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
-endmodule
-module VDecode(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [31:0] io_in_bits_0_bits_inst,
- input [31:0] io_in_bits_0_bits_addr,
- input [31:0] io_in_bits_0_bits_data,
- input io_in_bits_1_valid,
- input [31:0] io_in_bits_1_bits_inst,
- input [31:0] io_in_bits_1_bits_addr,
- input [31:0] io_in_bits_1_bits_data,
- input io_in_bits_2_valid,
- input [31:0] io_in_bits_2_bits_inst,
- input [31:0] io_in_bits_2_bits_addr,
- input [31:0] io_in_bits_2_bits_data,
- input io_in_bits_3_valid,
- input [31:0] io_in_bits_3_bits_inst,
- input [31:0] io_in_bits_3_bits_addr,
- input [31:0] io_in_bits_3_bits_data,
- input io_out_0_ready,
- output io_out_0_valid,
- output [6:0] io_out_0_bits_op,
- output [2:0] io_out_0_bits_f2,
- output [2:0] io_out_0_bits_sz,
- output io_out_0_bits_m,
- output io_out_0_bits_vd_valid,
- output [5:0] io_out_0_bits_vd_addr,
- output [5:0] io_out_0_bits_ve_addr,
- output [5:0] io_out_0_bits_vf_addr,
- output [5:0] io_out_0_bits_vg_addr,
- output io_out_0_bits_vs_valid,
- output [5:0] io_out_0_bits_vs_addr,
- output [3:0] io_out_0_bits_vs_tag,
- output io_out_0_bits_vt_valid,
- output [5:0] io_out_0_bits_vt_addr,
- output [3:0] io_out_0_bits_vt_tag,
- output io_out_0_bits_vu_valid,
- output [5:0] io_out_0_bits_vu_addr,
- output [3:0] io_out_0_bits_vu_tag,
- output io_out_0_bits_vx_valid,
- output [5:0] io_out_0_bits_vx_addr,
- output [3:0] io_out_0_bits_vx_tag,
- output io_out_0_bits_vy_valid,
- output [5:0] io_out_0_bits_vy_addr,
- output [3:0] io_out_0_bits_vy_tag,
- output io_out_0_bits_vz_valid,
- output [5:0] io_out_0_bits_vz_addr,
- output [3:0] io_out_0_bits_vz_tag,
- output io_out_0_bits_sv_valid,
- output [31:0] io_out_0_bits_sv_addr,
- output [31:0] io_out_0_bits_sv_data,
- output io_out_0_bits_cmdsync,
- input io_out_1_ready,
- output io_out_1_valid,
- output [6:0] io_out_1_bits_op,
- output [2:0] io_out_1_bits_f2,
- output [2:0] io_out_1_bits_sz,
- output io_out_1_bits_m,
- output io_out_1_bits_vd_valid,
- output [5:0] io_out_1_bits_vd_addr,
- output [5:0] io_out_1_bits_ve_addr,
- output [5:0] io_out_1_bits_vf_addr,
- output [5:0] io_out_1_bits_vg_addr,
- output io_out_1_bits_vs_valid,
- output [5:0] io_out_1_bits_vs_addr,
- output [3:0] io_out_1_bits_vs_tag,
- output io_out_1_bits_vt_valid,
- output [5:0] io_out_1_bits_vt_addr,
- output [3:0] io_out_1_bits_vt_tag,
- output io_out_1_bits_vu_valid,
- output [5:0] io_out_1_bits_vu_addr,
- output [3:0] io_out_1_bits_vu_tag,
- output io_out_1_bits_vx_valid,
- output [5:0] io_out_1_bits_vx_addr,
- output [3:0] io_out_1_bits_vx_tag,
- output io_out_1_bits_vy_valid,
- output [5:0] io_out_1_bits_vy_addr,
- output [3:0] io_out_1_bits_vy_tag,
- output io_out_1_bits_vz_valid,
- output [5:0] io_out_1_bits_vz_addr,
- output [3:0] io_out_1_bits_vz_tag,
- output io_out_1_bits_sv_valid,
- output [31:0] io_out_1_bits_sv_addr,
- output [31:0] io_out_1_bits_sv_data,
- output io_out_1_bits_cmdsync,
- input io_out_2_ready,
- output io_out_2_valid,
- output [6:0] io_out_2_bits_op,
- output [2:0] io_out_2_bits_f2,
- output [2:0] io_out_2_bits_sz,
- output io_out_2_bits_m,
- output io_out_2_bits_vd_valid,
- output [5:0] io_out_2_bits_vd_addr,
- output [5:0] io_out_2_bits_ve_addr,
- output [5:0] io_out_2_bits_vf_addr,
- output [5:0] io_out_2_bits_vg_addr,
- output io_out_2_bits_vs_valid,
- output [5:0] io_out_2_bits_vs_addr,
- output [3:0] io_out_2_bits_vs_tag,
- output io_out_2_bits_vt_valid,
- output [5:0] io_out_2_bits_vt_addr,
- output [3:0] io_out_2_bits_vt_tag,
- output io_out_2_bits_vu_valid,
- output [5:0] io_out_2_bits_vu_addr,
- output [3:0] io_out_2_bits_vu_tag,
- output io_out_2_bits_vx_valid,
- output [5:0] io_out_2_bits_vx_addr,
- output [3:0] io_out_2_bits_vx_tag,
- output io_out_2_bits_vy_valid,
- output [5:0] io_out_2_bits_vy_addr,
- output [3:0] io_out_2_bits_vy_tag,
- output io_out_2_bits_vz_valid,
- output [5:0] io_out_2_bits_vz_addr,
- output [3:0] io_out_2_bits_vz_tag,
- output io_out_2_bits_sv_valid,
- output [31:0] io_out_2_bits_sv_addr,
- output [31:0] io_out_2_bits_sv_data,
- output io_out_2_bits_cmdsync,
- input io_out_3_ready,
- output io_out_3_valid,
- output [6:0] io_out_3_bits_op,
- output [2:0] io_out_3_bits_f2,
- output [2:0] io_out_3_bits_sz,
- output io_out_3_bits_m,
- output io_out_3_bits_vd_valid,
- output [5:0] io_out_3_bits_vd_addr,
- output [5:0] io_out_3_bits_ve_addr,
- output [5:0] io_out_3_bits_vf_addr,
- output [5:0] io_out_3_bits_vg_addr,
- output io_out_3_bits_vs_valid,
- output [5:0] io_out_3_bits_vs_addr,
- output [3:0] io_out_3_bits_vs_tag,
- output io_out_3_bits_vt_valid,
- output [5:0] io_out_3_bits_vt_addr,
- output [3:0] io_out_3_bits_vt_tag,
- output io_out_3_bits_vu_valid,
- output [5:0] io_out_3_bits_vu_addr,
- output [3:0] io_out_3_bits_vu_tag,
- output io_out_3_bits_vx_valid,
- output [5:0] io_out_3_bits_vx_addr,
- output [3:0] io_out_3_bits_vx_tag,
- output io_out_3_bits_vy_valid,
- output [5:0] io_out_3_bits_vy_addr,
- output [3:0] io_out_3_bits_vy_tag,
- output io_out_3_bits_vz_valid,
- output [5:0] io_out_3_bits_vz_addr,
- output [3:0] io_out_3_bits_vz_tag,
- output io_out_3_bits_sv_valid,
- output [31:0] io_out_3_bits_sv_addr,
- output [31:0] io_out_3_bits_sv_data,
- output io_out_3_bits_cmdsync,
- output io_cmdq_0_alu,
- output io_cmdq_0_conv,
- output io_cmdq_0_ldst,
- output io_cmdq_0_ld,
- output io_cmdq_0_st,
- output io_cmdq_1_alu,
- output io_cmdq_1_conv,
- output io_cmdq_1_ldst,
- output io_cmdq_1_ld,
- output io_cmdq_1_st,
- output io_cmdq_2_alu,
- output io_cmdq_2_conv,
- output io_cmdq_2_ldst,
- output io_cmdq_2_ld,
- output io_cmdq_2_st,
- output io_cmdq_3_alu,
- output io_cmdq_3_conv,
- output io_cmdq_3_ldst,
- output io_cmdq_3_ld,
- output io_cmdq_3_st,
- output io_stall,
- input [63:0] io_active,
- output io_vrfsb_set_valid,
- output [127:0] io_vrfsb_set_bits,
- input [127:0] io_vrfsb_data,
- output io_undef,
- output io_nempty
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
- reg [31:0] _RAND_34;
- reg [31:0] _RAND_35;
- reg [31:0] _RAND_36;
- reg [31:0] _RAND_37;
- reg [31:0] _RAND_38;
- reg [31:0] _RAND_39;
- reg [31:0] _RAND_40;
- reg [31:0] _RAND_41;
- reg [31:0] _RAND_42;
- reg [31:0] _RAND_43;
- reg [31:0] _RAND_44;
- reg [31:0] _RAND_45;
- reg [31:0] _RAND_46;
- reg [31:0] _RAND_47;
- reg [31:0] _RAND_48;
- reg [31:0] _RAND_49;
- reg [31:0] _RAND_50;
- reg [31:0] _RAND_51;
- reg [31:0] _RAND_52;
- reg [31:0] _RAND_53;
- reg [31:0] _RAND_54;
- reg [31:0] _RAND_55;
- reg [31:0] _RAND_56;
- reg [31:0] _RAND_57;
- reg [31:0] _RAND_58;
- reg [31:0] _RAND_59;
- reg [31:0] _RAND_60;
- reg [31:0] _RAND_61;
- reg [31:0] _RAND_62;
- reg [31:0] _RAND_63;
- reg [31:0] _RAND_64;
- reg [31:0] _RAND_65;
- reg [31:0] _RAND_66;
- reg [31:0] _RAND_67;
- reg [31:0] _RAND_68;
- reg [31:0] _RAND_69;
- reg [31:0] _RAND_70;
- reg [31:0] _RAND_71;
- reg [31:0] _RAND_72;
- reg [31:0] _RAND_73;
- reg [31:0] _RAND_74;
- reg [31:0] _RAND_75;
- reg [31:0] _RAND_76;
- reg [31:0] _RAND_77;
- reg [31:0] _RAND_78;
- reg [31:0] _RAND_79;
- reg [31:0] _RAND_80;
- reg [31:0] _RAND_81;
- reg [31:0] _RAND_82;
- reg [31:0] _RAND_83;
- reg [31:0] _RAND_84;
- reg [31:0] _RAND_85;
- reg [31:0] _RAND_86;
- reg [31:0] _RAND_87;
- reg [31:0] _RAND_88;
- reg [31:0] _RAND_89;
- reg [31:0] _RAND_90;
- reg [31:0] _RAND_91;
- reg [31:0] _RAND_92;
- reg [31:0] _RAND_93;
- reg [31:0] _RAND_94;
- reg [31:0] _RAND_95;
- reg [31:0] _RAND_96;
- reg [31:0] _RAND_97;
- reg [31:0] _RAND_98;
- reg [31:0] _RAND_99;
- reg [31:0] _RAND_100;
- reg [31:0] _RAND_101;
- reg [31:0] _RAND_102;
- reg [31:0] _RAND_103;
- reg [31:0] _RAND_104;
- reg [31:0] _RAND_105;
- reg [31:0] _RAND_106;
- reg [31:0] _RAND_107;
- reg [31:0] _RAND_108;
- reg [31:0] _RAND_109;
- reg [31:0] _RAND_110;
- reg [31:0] _RAND_111;
- reg [31:0] _RAND_112;
- reg [31:0] _RAND_113;
- reg [31:0] _RAND_114;
- reg [31:0] _RAND_115;
- reg [31:0] _RAND_116;
- reg [31:0] _RAND_117;
- reg [31:0] _RAND_118;
- reg [31:0] _RAND_119;
- reg [31:0] _RAND_120;
- reg [31:0] _RAND_121;
- reg [31:0] _RAND_122;
- reg [31:0] _RAND_123;
- reg [31:0] _RAND_124;
- reg [31:0] _RAND_125;
- reg [31:0] _RAND_126;
- reg [31:0] _RAND_127;
- reg [31:0] _RAND_128;
- reg [31:0] _RAND_129;
- reg [31:0] _RAND_130;
- reg [31:0] _RAND_131;
- reg [31:0] _RAND_132;
- reg [31:0] _RAND_133;
- reg [31:0] _RAND_134;
- reg [31:0] _RAND_135;
- reg [31:0] _RAND_136;
- reg [31:0] _RAND_137;
- reg [31:0] _RAND_138;
- reg [31:0] _RAND_139;
- reg [31:0] _RAND_140;
- reg [31:0] _RAND_141;
- reg [31:0] _RAND_142;
- reg [31:0] _RAND_143;
- reg [31:0] _RAND_144;
- reg [31:0] _RAND_145;
- reg [31:0] _RAND_146;
- reg [31:0] _RAND_147;
- reg [63:0] _RAND_148;
- reg [127:0] _RAND_149;
- reg [63:0] _RAND_150;
- reg [127:0] _RAND_151;
- reg [63:0] _RAND_152;
- reg [127:0] _RAND_153;
- reg [63:0] _RAND_154;
- reg [127:0] _RAND_155;
- reg [63:0] _RAND_156;
- reg [31:0] _RAND_157;
-`endif // RANDOMIZE_REG_INIT
- wire f_clock; // @[Fifo4x4.scala 22:11]
- wire f_reset; // @[Fifo4x4.scala 22:11]
- wire f_io_in_ready; // @[Fifo4x4.scala 22:11]
- wire f_io_in_valid; // @[Fifo4x4.scala 22:11]
- wire f_io_in_bits_0_valid; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_in_bits_0_bits_inst; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_in_bits_0_bits_addr; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_in_bits_0_bits_data; // @[Fifo4x4.scala 22:11]
- wire f_io_in_bits_1_valid; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_in_bits_1_bits_inst; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_in_bits_1_bits_addr; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_in_bits_1_bits_data; // @[Fifo4x4.scala 22:11]
- wire f_io_in_bits_2_valid; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_in_bits_2_bits_inst; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_in_bits_2_bits_addr; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_in_bits_2_bits_data; // @[Fifo4x4.scala 22:11]
- wire f_io_in_bits_3_valid; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_in_bits_3_bits_inst; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_in_bits_3_bits_addr; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_in_bits_3_bits_data; // @[Fifo4x4.scala 22:11]
- wire f_io_out_0_ready; // @[Fifo4x4.scala 22:11]
- wire f_io_out_0_valid; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_out_0_bits_inst; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_out_0_bits_addr; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_out_0_bits_data; // @[Fifo4x4.scala 22:11]
- wire f_io_out_1_ready; // @[Fifo4x4.scala 22:11]
- wire f_io_out_1_valid; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_out_1_bits_inst; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_out_1_bits_addr; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_out_1_bits_data; // @[Fifo4x4.scala 22:11]
- wire f_io_out_2_ready; // @[Fifo4x4.scala 22:11]
- wire f_io_out_2_valid; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_out_2_bits_inst; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_out_2_bits_addr; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_out_2_bits_data; // @[Fifo4x4.scala 22:11]
- wire f_io_out_3_ready; // @[Fifo4x4.scala 22:11]
- wire f_io_out_3_valid; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_out_3_bits_inst; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_out_3_bits_addr; // @[Fifo4x4.scala 22:11]
- wire [31:0] f_io_out_3_bits_data; // @[Fifo4x4.scala 22:11]
- wire [4:0] f_io_count; // @[Fifo4x4.scala 22:11]
- wire f_io_nempty; // @[Fifo4x4.scala 22:11]
- wire d_0_clock; // @[VDecode.scala 49:21]
- wire d_0_reset; // @[VDecode.scala 49:21]
- wire [31:0] d_0_io_in_inst; // @[VDecode.scala 49:21]
- wire [31:0] d_0_io_in_addr; // @[VDecode.scala 49:21]
- wire [31:0] d_0_io_in_data; // @[VDecode.scala 49:21]
- wire [6:0] d_0_io_out_op; // @[VDecode.scala 49:21]
- wire [2:0] d_0_io_out_f2; // @[VDecode.scala 49:21]
- wire [2:0] d_0_io_out_sz; // @[VDecode.scala 49:21]
- wire d_0_io_out_m; // @[VDecode.scala 49:21]
- wire d_0_io_out_vd_valid; // @[VDecode.scala 49:21]
- wire [5:0] d_0_io_out_vd_addr; // @[VDecode.scala 49:21]
- wire [5:0] d_0_io_out_ve_addr; // @[VDecode.scala 49:21]
- wire [5:0] d_0_io_out_vf_addr; // @[VDecode.scala 49:21]
- wire [5:0] d_0_io_out_vg_addr; // @[VDecode.scala 49:21]
- wire d_0_io_out_vs_valid; // @[VDecode.scala 49:21]
- wire [5:0] d_0_io_out_vs_addr; // @[VDecode.scala 49:21]
- wire d_0_io_out_vt_valid; // @[VDecode.scala 49:21]
- wire [5:0] d_0_io_out_vt_addr; // @[VDecode.scala 49:21]
- wire d_0_io_out_vu_valid; // @[VDecode.scala 49:21]
- wire [5:0] d_0_io_out_vu_addr; // @[VDecode.scala 49:21]
- wire d_0_io_out_vx_valid; // @[VDecode.scala 49:21]
- wire [5:0] d_0_io_out_vx_addr; // @[VDecode.scala 49:21]
- wire d_0_io_out_vy_valid; // @[VDecode.scala 49:21]
- wire [5:0] d_0_io_out_vy_addr; // @[VDecode.scala 49:21]
- wire d_0_io_out_vz_valid; // @[VDecode.scala 49:21]
- wire [5:0] d_0_io_out_vz_addr; // @[VDecode.scala 49:21]
- wire d_0_io_out_sv_valid; // @[VDecode.scala 49:21]
- wire [31:0] d_0_io_out_sv_addr; // @[VDecode.scala 49:21]
- wire [31:0] d_0_io_out_sv_data; // @[VDecode.scala 49:21]
- wire d_0_io_out_cmdsync; // @[VDecode.scala 49:21]
- wire d_0_io_cmdq_alu; // @[VDecode.scala 49:21]
- wire d_0_io_cmdq_conv; // @[VDecode.scala 49:21]
- wire d_0_io_cmdq_ldst; // @[VDecode.scala 49:21]
- wire d_0_io_cmdq_ld; // @[VDecode.scala 49:21]
- wire d_0_io_cmdq_st; // @[VDecode.scala 49:21]
- wire [63:0] d_0_io_actv_ractive; // @[VDecode.scala 49:21]
- wire [63:0] d_0_io_actv_wactive; // @[VDecode.scala 49:21]
- wire d_0_io_undef; // @[VDecode.scala 49:21]
- wire d_1_clock; // @[VDecode.scala 50:21]
- wire d_1_reset; // @[VDecode.scala 50:21]
- wire [31:0] d_1_io_in_inst; // @[VDecode.scala 50:21]
- wire [31:0] d_1_io_in_addr; // @[VDecode.scala 50:21]
- wire [31:0] d_1_io_in_data; // @[VDecode.scala 50:21]
- wire [6:0] d_1_io_out_op; // @[VDecode.scala 50:21]
- wire [2:0] d_1_io_out_f2; // @[VDecode.scala 50:21]
- wire [2:0] d_1_io_out_sz; // @[VDecode.scala 50:21]
- wire d_1_io_out_m; // @[VDecode.scala 50:21]
- wire d_1_io_out_vd_valid; // @[VDecode.scala 50:21]
- wire [5:0] d_1_io_out_vd_addr; // @[VDecode.scala 50:21]
- wire [5:0] d_1_io_out_ve_addr; // @[VDecode.scala 50:21]
- wire [5:0] d_1_io_out_vf_addr; // @[VDecode.scala 50:21]
- wire [5:0] d_1_io_out_vg_addr; // @[VDecode.scala 50:21]
- wire d_1_io_out_vs_valid; // @[VDecode.scala 50:21]
- wire [5:0] d_1_io_out_vs_addr; // @[VDecode.scala 50:21]
- wire d_1_io_out_vt_valid; // @[VDecode.scala 50:21]
- wire [5:0] d_1_io_out_vt_addr; // @[VDecode.scala 50:21]
- wire d_1_io_out_vu_valid; // @[VDecode.scala 50:21]
- wire [5:0] d_1_io_out_vu_addr; // @[VDecode.scala 50:21]
- wire d_1_io_out_vx_valid; // @[VDecode.scala 50:21]
- wire [5:0] d_1_io_out_vx_addr; // @[VDecode.scala 50:21]
- wire d_1_io_out_vy_valid; // @[VDecode.scala 50:21]
- wire [5:0] d_1_io_out_vy_addr; // @[VDecode.scala 50:21]
- wire d_1_io_out_vz_valid; // @[VDecode.scala 50:21]
- wire [5:0] d_1_io_out_vz_addr; // @[VDecode.scala 50:21]
- wire d_1_io_out_sv_valid; // @[VDecode.scala 50:21]
- wire [31:0] d_1_io_out_sv_addr; // @[VDecode.scala 50:21]
- wire [31:0] d_1_io_out_sv_data; // @[VDecode.scala 50:21]
- wire d_1_io_out_cmdsync; // @[VDecode.scala 50:21]
- wire d_1_io_cmdq_alu; // @[VDecode.scala 50:21]
- wire d_1_io_cmdq_conv; // @[VDecode.scala 50:21]
- wire d_1_io_cmdq_ldst; // @[VDecode.scala 50:21]
- wire d_1_io_cmdq_ld; // @[VDecode.scala 50:21]
- wire d_1_io_cmdq_st; // @[VDecode.scala 50:21]
- wire [63:0] d_1_io_actv_ractive; // @[VDecode.scala 50:21]
- wire [63:0] d_1_io_actv_wactive; // @[VDecode.scala 50:21]
- wire d_1_io_undef; // @[VDecode.scala 50:21]
- wire d_2_clock; // @[VDecode.scala 51:21]
- wire d_2_reset; // @[VDecode.scala 51:21]
- wire [31:0] d_2_io_in_inst; // @[VDecode.scala 51:21]
- wire [31:0] d_2_io_in_addr; // @[VDecode.scala 51:21]
- wire [31:0] d_2_io_in_data; // @[VDecode.scala 51:21]
- wire [6:0] d_2_io_out_op; // @[VDecode.scala 51:21]
- wire [2:0] d_2_io_out_f2; // @[VDecode.scala 51:21]
- wire [2:0] d_2_io_out_sz; // @[VDecode.scala 51:21]
- wire d_2_io_out_m; // @[VDecode.scala 51:21]
- wire d_2_io_out_vd_valid; // @[VDecode.scala 51:21]
- wire [5:0] d_2_io_out_vd_addr; // @[VDecode.scala 51:21]
- wire [5:0] d_2_io_out_ve_addr; // @[VDecode.scala 51:21]
- wire [5:0] d_2_io_out_vf_addr; // @[VDecode.scala 51:21]
- wire [5:0] d_2_io_out_vg_addr; // @[VDecode.scala 51:21]
- wire d_2_io_out_vs_valid; // @[VDecode.scala 51:21]
- wire [5:0] d_2_io_out_vs_addr; // @[VDecode.scala 51:21]
- wire d_2_io_out_vt_valid; // @[VDecode.scala 51:21]
- wire [5:0] d_2_io_out_vt_addr; // @[VDecode.scala 51:21]
- wire d_2_io_out_vu_valid; // @[VDecode.scala 51:21]
- wire [5:0] d_2_io_out_vu_addr; // @[VDecode.scala 51:21]
- wire d_2_io_out_vx_valid; // @[VDecode.scala 51:21]
- wire [5:0] d_2_io_out_vx_addr; // @[VDecode.scala 51:21]
- wire d_2_io_out_vy_valid; // @[VDecode.scala 51:21]
- wire [5:0] d_2_io_out_vy_addr; // @[VDecode.scala 51:21]
- wire d_2_io_out_vz_valid; // @[VDecode.scala 51:21]
- wire [5:0] d_2_io_out_vz_addr; // @[VDecode.scala 51:21]
- wire d_2_io_out_sv_valid; // @[VDecode.scala 51:21]
- wire [31:0] d_2_io_out_sv_addr; // @[VDecode.scala 51:21]
- wire [31:0] d_2_io_out_sv_data; // @[VDecode.scala 51:21]
- wire d_2_io_out_cmdsync; // @[VDecode.scala 51:21]
- wire d_2_io_cmdq_alu; // @[VDecode.scala 51:21]
- wire d_2_io_cmdq_conv; // @[VDecode.scala 51:21]
- wire d_2_io_cmdq_ldst; // @[VDecode.scala 51:21]
- wire d_2_io_cmdq_ld; // @[VDecode.scala 51:21]
- wire d_2_io_cmdq_st; // @[VDecode.scala 51:21]
- wire [63:0] d_2_io_actv_ractive; // @[VDecode.scala 51:21]
- wire [63:0] d_2_io_actv_wactive; // @[VDecode.scala 51:21]
- wire d_2_io_undef; // @[VDecode.scala 51:21]
- wire d_3_clock; // @[VDecode.scala 52:21]
- wire d_3_reset; // @[VDecode.scala 52:21]
- wire [31:0] d_3_io_in_inst; // @[VDecode.scala 52:21]
- wire [31:0] d_3_io_in_addr; // @[VDecode.scala 52:21]
- wire [31:0] d_3_io_in_data; // @[VDecode.scala 52:21]
- wire [6:0] d_3_io_out_op; // @[VDecode.scala 52:21]
- wire [2:0] d_3_io_out_f2; // @[VDecode.scala 52:21]
- wire [2:0] d_3_io_out_sz; // @[VDecode.scala 52:21]
- wire d_3_io_out_m; // @[VDecode.scala 52:21]
- wire d_3_io_out_vd_valid; // @[VDecode.scala 52:21]
- wire [5:0] d_3_io_out_vd_addr; // @[VDecode.scala 52:21]
- wire [5:0] d_3_io_out_ve_addr; // @[VDecode.scala 52:21]
- wire [5:0] d_3_io_out_vf_addr; // @[VDecode.scala 52:21]
- wire [5:0] d_3_io_out_vg_addr; // @[VDecode.scala 52:21]
- wire d_3_io_out_vs_valid; // @[VDecode.scala 52:21]
- wire [5:0] d_3_io_out_vs_addr; // @[VDecode.scala 52:21]
- wire d_3_io_out_vt_valid; // @[VDecode.scala 52:21]
- wire [5:0] d_3_io_out_vt_addr; // @[VDecode.scala 52:21]
- wire d_3_io_out_vu_valid; // @[VDecode.scala 52:21]
- wire [5:0] d_3_io_out_vu_addr; // @[VDecode.scala 52:21]
- wire d_3_io_out_vx_valid; // @[VDecode.scala 52:21]
- wire [5:0] d_3_io_out_vx_addr; // @[VDecode.scala 52:21]
- wire d_3_io_out_vy_valid; // @[VDecode.scala 52:21]
- wire [5:0] d_3_io_out_vy_addr; // @[VDecode.scala 52:21]
- wire d_3_io_out_vz_valid; // @[VDecode.scala 52:21]
- wire [5:0] d_3_io_out_vz_addr; // @[VDecode.scala 52:21]
- wire d_3_io_out_sv_valid; // @[VDecode.scala 52:21]
- wire [31:0] d_3_io_out_sv_addr; // @[VDecode.scala 52:21]
- wire [31:0] d_3_io_out_sv_data; // @[VDecode.scala 52:21]
- wire d_3_io_out_cmdsync; // @[VDecode.scala 52:21]
- wire d_3_io_cmdq_alu; // @[VDecode.scala 52:21]
- wire d_3_io_cmdq_conv; // @[VDecode.scala 52:21]
- wire d_3_io_cmdq_ldst; // @[VDecode.scala 52:21]
- wire d_3_io_cmdq_ld; // @[VDecode.scala 52:21]
- wire d_3_io_cmdq_st; // @[VDecode.scala 52:21]
- wire [63:0] d_3_io_actv_ractive; // @[VDecode.scala 52:21]
- wire [63:0] d_3_io_actv_wactive; // @[VDecode.scala 52:21]
- wire d_3_io_undef; // @[VDecode.scala 52:21]
- reg valid_0; // @[VDecode.scala 56:22]
- reg valid_1; // @[VDecode.scala 56:22]
- reg valid_2; // @[VDecode.scala 56:22]
- reg valid_3; // @[VDecode.scala 56:22]
- reg [6:0] data_0_op; // @[VDecode.scala 57:17]
- reg [2:0] data_0_f2; // @[VDecode.scala 57:17]
- reg [2:0] data_0_sz; // @[VDecode.scala 57:17]
- reg data_0_m; // @[VDecode.scala 57:17]
- reg data_0_vd_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_0_vd_addr; // @[VDecode.scala 57:17]
- reg [5:0] data_0_ve_addr; // @[VDecode.scala 57:17]
- reg [5:0] data_0_vf_addr; // @[VDecode.scala 57:17]
- reg [5:0] data_0_vg_addr; // @[VDecode.scala 57:17]
- reg data_0_vs_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_0_vs_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_0_vs_tag; // @[VDecode.scala 57:17]
- reg data_0_vt_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_0_vt_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_0_vt_tag; // @[VDecode.scala 57:17]
- reg data_0_vu_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_0_vu_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_0_vu_tag; // @[VDecode.scala 57:17]
- reg data_0_vx_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_0_vx_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_0_vx_tag; // @[VDecode.scala 57:17]
- reg data_0_vy_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_0_vy_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_0_vy_tag; // @[VDecode.scala 57:17]
- reg data_0_vz_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_0_vz_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_0_vz_tag; // @[VDecode.scala 57:17]
- reg data_0_sv_valid; // @[VDecode.scala 57:17]
- reg [31:0] data_0_sv_addr; // @[VDecode.scala 57:17]
- reg [31:0] data_0_sv_data; // @[VDecode.scala 57:17]
- reg data_0_cmdsync; // @[VDecode.scala 57:17]
- reg [6:0] data_1_op; // @[VDecode.scala 57:17]
- reg [2:0] data_1_f2; // @[VDecode.scala 57:17]
- reg [2:0] data_1_sz; // @[VDecode.scala 57:17]
- reg data_1_m; // @[VDecode.scala 57:17]
- reg data_1_vd_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_1_vd_addr; // @[VDecode.scala 57:17]
- reg [5:0] data_1_ve_addr; // @[VDecode.scala 57:17]
- reg [5:0] data_1_vf_addr; // @[VDecode.scala 57:17]
- reg [5:0] data_1_vg_addr; // @[VDecode.scala 57:17]
- reg data_1_vs_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_1_vs_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_1_vs_tag; // @[VDecode.scala 57:17]
- reg data_1_vt_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_1_vt_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_1_vt_tag; // @[VDecode.scala 57:17]
- reg data_1_vu_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_1_vu_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_1_vu_tag; // @[VDecode.scala 57:17]
- reg data_1_vx_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_1_vx_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_1_vx_tag; // @[VDecode.scala 57:17]
- reg data_1_vy_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_1_vy_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_1_vy_tag; // @[VDecode.scala 57:17]
- reg data_1_vz_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_1_vz_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_1_vz_tag; // @[VDecode.scala 57:17]
- reg data_1_sv_valid; // @[VDecode.scala 57:17]
- reg [31:0] data_1_sv_addr; // @[VDecode.scala 57:17]
- reg [31:0] data_1_sv_data; // @[VDecode.scala 57:17]
- reg data_1_cmdsync; // @[VDecode.scala 57:17]
- reg [6:0] data_2_op; // @[VDecode.scala 57:17]
- reg [2:0] data_2_f2; // @[VDecode.scala 57:17]
- reg [2:0] data_2_sz; // @[VDecode.scala 57:17]
- reg data_2_m; // @[VDecode.scala 57:17]
- reg data_2_vd_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_2_vd_addr; // @[VDecode.scala 57:17]
- reg [5:0] data_2_ve_addr; // @[VDecode.scala 57:17]
- reg [5:0] data_2_vf_addr; // @[VDecode.scala 57:17]
- reg [5:0] data_2_vg_addr; // @[VDecode.scala 57:17]
- reg data_2_vs_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_2_vs_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_2_vs_tag; // @[VDecode.scala 57:17]
- reg data_2_vt_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_2_vt_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_2_vt_tag; // @[VDecode.scala 57:17]
- reg data_2_vu_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_2_vu_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_2_vu_tag; // @[VDecode.scala 57:17]
- reg data_2_vx_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_2_vx_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_2_vx_tag; // @[VDecode.scala 57:17]
- reg data_2_vy_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_2_vy_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_2_vy_tag; // @[VDecode.scala 57:17]
- reg data_2_vz_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_2_vz_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_2_vz_tag; // @[VDecode.scala 57:17]
- reg data_2_sv_valid; // @[VDecode.scala 57:17]
- reg [31:0] data_2_sv_addr; // @[VDecode.scala 57:17]
- reg [31:0] data_2_sv_data; // @[VDecode.scala 57:17]
- reg data_2_cmdsync; // @[VDecode.scala 57:17]
- reg [6:0] data_3_op; // @[VDecode.scala 57:17]
- reg [2:0] data_3_f2; // @[VDecode.scala 57:17]
- reg [2:0] data_3_sz; // @[VDecode.scala 57:17]
- reg data_3_m; // @[VDecode.scala 57:17]
- reg data_3_vd_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_3_vd_addr; // @[VDecode.scala 57:17]
- reg [5:0] data_3_ve_addr; // @[VDecode.scala 57:17]
- reg [5:0] data_3_vf_addr; // @[VDecode.scala 57:17]
- reg [5:0] data_3_vg_addr; // @[VDecode.scala 57:17]
- reg data_3_vs_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_3_vs_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_3_vs_tag; // @[VDecode.scala 57:17]
- reg data_3_vt_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_3_vt_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_3_vt_tag; // @[VDecode.scala 57:17]
- reg data_3_vu_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_3_vu_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_3_vu_tag; // @[VDecode.scala 57:17]
- reg data_3_vx_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_3_vx_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_3_vx_tag; // @[VDecode.scala 57:17]
- reg data_3_vy_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_3_vy_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_3_vy_tag; // @[VDecode.scala 57:17]
- reg data_3_vz_valid; // @[VDecode.scala 57:17]
- reg [5:0] data_3_vz_addr; // @[VDecode.scala 57:17]
- reg [3:0] data_3_vz_tag; // @[VDecode.scala 57:17]
- reg data_3_sv_valid; // @[VDecode.scala 57:17]
- reg [31:0] data_3_sv_addr; // @[VDecode.scala 57:17]
- reg [31:0] data_3_sv_data; // @[VDecode.scala 57:17]
- reg data_3_cmdsync; // @[VDecode.scala 57:17]
- reg cmdq_0_alu; // @[VDecode.scala 58:17]
- reg cmdq_0_conv; // @[VDecode.scala 58:17]
- reg cmdq_0_ldst; // @[VDecode.scala 58:17]
- reg cmdq_0_ld; // @[VDecode.scala 58:17]
- reg cmdq_0_st; // @[VDecode.scala 58:17]
- reg cmdq_1_alu; // @[VDecode.scala 58:17]
- reg cmdq_1_conv; // @[VDecode.scala 58:17]
- reg cmdq_1_ldst; // @[VDecode.scala 58:17]
- reg cmdq_1_ld; // @[VDecode.scala 58:17]
- reg cmdq_1_st; // @[VDecode.scala 58:17]
- reg cmdq_2_alu; // @[VDecode.scala 58:17]
- reg cmdq_2_conv; // @[VDecode.scala 58:17]
- reg cmdq_2_ldst; // @[VDecode.scala 58:17]
- reg cmdq_2_ld; // @[VDecode.scala 58:17]
- reg cmdq_2_st; // @[VDecode.scala 58:17]
- reg cmdq_3_alu; // @[VDecode.scala 58:17]
- reg cmdq_3_conv; // @[VDecode.scala 58:17]
- reg cmdq_3_ldst; // @[VDecode.scala 58:17]
- reg cmdq_3_ld; // @[VDecode.scala 58:17]
- reg cmdq_3_st; // @[VDecode.scala 58:17]
- reg [63:0] actv2_0_ractive; // @[VDecode.scala 60:18]
- reg [127:0] actv2_0_wactive; // @[VDecode.scala 60:18]
- reg [63:0] actv2_1_ractive; // @[VDecode.scala 60:18]
- reg [127:0] actv2_1_wactive; // @[VDecode.scala 60:18]
- reg [63:0] actv2_2_ractive; // @[VDecode.scala 60:18]
- reg [127:0] actv2_2_wactive; // @[VDecode.scala 60:18]
- reg [63:0] actv2_3_ractive; // @[VDecode.scala 60:18]
- reg [127:0] actv2_3_wactive; // @[VDecode.scala 60:18]
- reg [63:0] tag0; // @[VDecode.scala 75:23]
- wire [63:0] tag1 = tag0 ^ d_0_io_actv_wactive; // @[VDecode.scala 78:19]
- wire [63:0] tag2 = tag1 ^ d_1_io_actv_wactive; // @[VDecode.scala 79:19]
- wire [63:0] tag3 = tag2 ^ d_2_io_actv_wactive; // @[VDecode.scala 80:19]
- wire [63:0] tag4 = tag3 ^ d_3_io_actv_wactive; // @[VDecode.scala 81:19]
- wire _T = f_io_out_3_valid & f_io_out_3_ready; // @[VDecode.scala 86:26]
- wire _T_1 = f_io_out_2_valid & f_io_out_2_ready; // @[VDecode.scala 88:33]
- wire _T_2 = f_io_out_1_valid & f_io_out_1_ready; // @[VDecode.scala 90:33]
- wire _T_3 = f_io_out_0_valid & f_io_out_0_ready; // @[VDecode.scala 92:33]
- wire _e_0_vs_T_2 = ~reset; // @[VDecode.scala 99:11]
- wire [3:0] e_0_vs_addrm = d_0_io_out_vs_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_0_vs_tagm_0 = tag0[3:0]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_1 = tag0[7:4]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_2 = tag0[11:8]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_3 = tag0[15:12]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_4 = tag0[19:16]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_5 = tag0[23:20]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_6 = tag0[27:24]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_7 = tag0[31:28]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_8 = tag0[35:32]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_9 = tag0[39:36]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_10 = tag0[43:40]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_11 = tag0[47:44]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_12 = tag0[51:48]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_13 = tag0[55:52]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_14 = tag0[59:56]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_tagm_15 = tag0[63:60]; // @[VDecode.scala 104:21]
- wire [3:0] e_0_vs_r_tag_value__0 = 4'h0 == e_0_vs_addrm ? e_0_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__1 = 4'h1 == e_0_vs_addrm ? e_0_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__2 = 4'h2 == e_0_vs_addrm ? e_0_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__3 = 4'h3 == e_0_vs_addrm ? e_0_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__4 = 4'h4 == e_0_vs_addrm ? e_0_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__5 = 4'h5 == e_0_vs_addrm ? e_0_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__6 = 4'h6 == e_0_vs_addrm ? e_0_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__7 = 4'h7 == e_0_vs_addrm ? e_0_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__8 = 4'h8 == e_0_vs_addrm ? e_0_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__9 = 4'h9 == e_0_vs_addrm ? e_0_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__10 = 4'ha == e_0_vs_addrm ? e_0_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__11 = 4'hb == e_0_vs_addrm ? e_0_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__12 = 4'hc == e_0_vs_addrm ? e_0_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__13 = 4'hd == e_0_vs_addrm ? e_0_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__14 = 4'he == e_0_vs_addrm ? e_0_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value__15 = 4'hf == e_0_vs_addrm ? e_0_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vs_r_tag_value_1_0 = e_0_vs_r_tag_value__0 | e_0_vs_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_1_1 = e_0_vs_r_tag_value__2 | e_0_vs_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_1_2 = e_0_vs_r_tag_value__4 | e_0_vs_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_1_3 = e_0_vs_r_tag_value__6 | e_0_vs_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_1_4 = e_0_vs_r_tag_value__8 | e_0_vs_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_1_5 = e_0_vs_r_tag_value__10 | e_0_vs_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_1_6 = e_0_vs_r_tag_value__12 | e_0_vs_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_1_7 = e_0_vs_r_tag_value__14 | e_0_vs_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_2_0 = e_0_vs_r_tag_value_1_0 | e_0_vs_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_2_1 = e_0_vs_r_tag_value_1_2 | e_0_vs_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_2_2 = e_0_vs_r_tag_value_1_4 | e_0_vs_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_2_3 = e_0_vs_r_tag_value_1_6 | e_0_vs_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_3_0 = e_0_vs_r_tag_value_2_0 | e_0_vs_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_3_1 = e_0_vs_r_tag_value_2_2 | e_0_vs_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_0_vs_r_tag_value_4_0 = e_0_vs_r_tag_value_3_0 | e_0_vs_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_addrm = d_0_io_out_vt_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_0_vt_r_tag_value__0 = 4'h0 == e_0_vt_addrm ? e_0_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__1 = 4'h1 == e_0_vt_addrm ? e_0_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__2 = 4'h2 == e_0_vt_addrm ? e_0_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__3 = 4'h3 == e_0_vt_addrm ? e_0_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__4 = 4'h4 == e_0_vt_addrm ? e_0_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__5 = 4'h5 == e_0_vt_addrm ? e_0_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__6 = 4'h6 == e_0_vt_addrm ? e_0_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__7 = 4'h7 == e_0_vt_addrm ? e_0_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__8 = 4'h8 == e_0_vt_addrm ? e_0_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__9 = 4'h9 == e_0_vt_addrm ? e_0_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__10 = 4'ha == e_0_vt_addrm ? e_0_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__11 = 4'hb == e_0_vt_addrm ? e_0_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__12 = 4'hc == e_0_vt_addrm ? e_0_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__13 = 4'hd == e_0_vt_addrm ? e_0_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__14 = 4'he == e_0_vt_addrm ? e_0_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value__15 = 4'hf == e_0_vt_addrm ? e_0_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vt_r_tag_value_1_0 = e_0_vt_r_tag_value__0 | e_0_vt_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_1_1 = e_0_vt_r_tag_value__2 | e_0_vt_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_1_2 = e_0_vt_r_tag_value__4 | e_0_vt_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_1_3 = e_0_vt_r_tag_value__6 | e_0_vt_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_1_4 = e_0_vt_r_tag_value__8 | e_0_vt_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_1_5 = e_0_vt_r_tag_value__10 | e_0_vt_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_1_6 = e_0_vt_r_tag_value__12 | e_0_vt_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_1_7 = e_0_vt_r_tag_value__14 | e_0_vt_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_2_0 = e_0_vt_r_tag_value_1_0 | e_0_vt_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_2_1 = e_0_vt_r_tag_value_1_2 | e_0_vt_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_2_2 = e_0_vt_r_tag_value_1_4 | e_0_vt_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_2_3 = e_0_vt_r_tag_value_1_6 | e_0_vt_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_3_0 = e_0_vt_r_tag_value_2_0 | e_0_vt_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_3_1 = e_0_vt_r_tag_value_2_2 | e_0_vt_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_0_vt_r_tag_value_4_0 = e_0_vt_r_tag_value_3_0 | e_0_vt_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_addrm = d_0_io_out_vu_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_0_vu_r_tag_value__0 = 4'h0 == e_0_vu_addrm ? e_0_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__1 = 4'h1 == e_0_vu_addrm ? e_0_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__2 = 4'h2 == e_0_vu_addrm ? e_0_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__3 = 4'h3 == e_0_vu_addrm ? e_0_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__4 = 4'h4 == e_0_vu_addrm ? e_0_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__5 = 4'h5 == e_0_vu_addrm ? e_0_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__6 = 4'h6 == e_0_vu_addrm ? e_0_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__7 = 4'h7 == e_0_vu_addrm ? e_0_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__8 = 4'h8 == e_0_vu_addrm ? e_0_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__9 = 4'h9 == e_0_vu_addrm ? e_0_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__10 = 4'ha == e_0_vu_addrm ? e_0_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__11 = 4'hb == e_0_vu_addrm ? e_0_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__12 = 4'hc == e_0_vu_addrm ? e_0_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__13 = 4'hd == e_0_vu_addrm ? e_0_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__14 = 4'he == e_0_vu_addrm ? e_0_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value__15 = 4'hf == e_0_vu_addrm ? e_0_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vu_r_tag_value_1_0 = e_0_vu_r_tag_value__0 | e_0_vu_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_1_1 = e_0_vu_r_tag_value__2 | e_0_vu_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_1_2 = e_0_vu_r_tag_value__4 | e_0_vu_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_1_3 = e_0_vu_r_tag_value__6 | e_0_vu_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_1_4 = e_0_vu_r_tag_value__8 | e_0_vu_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_1_5 = e_0_vu_r_tag_value__10 | e_0_vu_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_1_6 = e_0_vu_r_tag_value__12 | e_0_vu_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_1_7 = e_0_vu_r_tag_value__14 | e_0_vu_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_2_0 = e_0_vu_r_tag_value_1_0 | e_0_vu_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_2_1 = e_0_vu_r_tag_value_1_2 | e_0_vu_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_2_2 = e_0_vu_r_tag_value_1_4 | e_0_vu_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_2_3 = e_0_vu_r_tag_value_1_6 | e_0_vu_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_3_0 = e_0_vu_r_tag_value_2_0 | e_0_vu_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_3_1 = e_0_vu_r_tag_value_2_2 | e_0_vu_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_0_vu_r_tag_value_4_0 = e_0_vu_r_tag_value_3_0 | e_0_vu_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_addrm = d_0_io_out_vx_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_0_vx_r_tag_value__0 = 4'h0 == e_0_vx_addrm ? e_0_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__1 = 4'h1 == e_0_vx_addrm ? e_0_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__2 = 4'h2 == e_0_vx_addrm ? e_0_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__3 = 4'h3 == e_0_vx_addrm ? e_0_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__4 = 4'h4 == e_0_vx_addrm ? e_0_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__5 = 4'h5 == e_0_vx_addrm ? e_0_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__6 = 4'h6 == e_0_vx_addrm ? e_0_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__7 = 4'h7 == e_0_vx_addrm ? e_0_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__8 = 4'h8 == e_0_vx_addrm ? e_0_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__9 = 4'h9 == e_0_vx_addrm ? e_0_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__10 = 4'ha == e_0_vx_addrm ? e_0_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__11 = 4'hb == e_0_vx_addrm ? e_0_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__12 = 4'hc == e_0_vx_addrm ? e_0_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__13 = 4'hd == e_0_vx_addrm ? e_0_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__14 = 4'he == e_0_vx_addrm ? e_0_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value__15 = 4'hf == e_0_vx_addrm ? e_0_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vx_r_tag_value_1_0 = e_0_vx_r_tag_value__0 | e_0_vx_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_1_1 = e_0_vx_r_tag_value__2 | e_0_vx_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_1_2 = e_0_vx_r_tag_value__4 | e_0_vx_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_1_3 = e_0_vx_r_tag_value__6 | e_0_vx_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_1_4 = e_0_vx_r_tag_value__8 | e_0_vx_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_1_5 = e_0_vx_r_tag_value__10 | e_0_vx_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_1_6 = e_0_vx_r_tag_value__12 | e_0_vx_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_1_7 = e_0_vx_r_tag_value__14 | e_0_vx_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_2_0 = e_0_vx_r_tag_value_1_0 | e_0_vx_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_2_1 = e_0_vx_r_tag_value_1_2 | e_0_vx_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_2_2 = e_0_vx_r_tag_value_1_4 | e_0_vx_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_2_3 = e_0_vx_r_tag_value_1_6 | e_0_vx_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_3_0 = e_0_vx_r_tag_value_2_0 | e_0_vx_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_3_1 = e_0_vx_r_tag_value_2_2 | e_0_vx_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_0_vx_r_tag_value_4_0 = e_0_vx_r_tag_value_3_0 | e_0_vx_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_addrm = d_0_io_out_vy_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_0_vy_r_tag_value__0 = 4'h0 == e_0_vy_addrm ? e_0_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__1 = 4'h1 == e_0_vy_addrm ? e_0_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__2 = 4'h2 == e_0_vy_addrm ? e_0_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__3 = 4'h3 == e_0_vy_addrm ? e_0_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__4 = 4'h4 == e_0_vy_addrm ? e_0_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__5 = 4'h5 == e_0_vy_addrm ? e_0_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__6 = 4'h6 == e_0_vy_addrm ? e_0_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__7 = 4'h7 == e_0_vy_addrm ? e_0_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__8 = 4'h8 == e_0_vy_addrm ? e_0_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__9 = 4'h9 == e_0_vy_addrm ? e_0_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__10 = 4'ha == e_0_vy_addrm ? e_0_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__11 = 4'hb == e_0_vy_addrm ? e_0_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__12 = 4'hc == e_0_vy_addrm ? e_0_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__13 = 4'hd == e_0_vy_addrm ? e_0_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__14 = 4'he == e_0_vy_addrm ? e_0_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value__15 = 4'hf == e_0_vy_addrm ? e_0_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vy_r_tag_value_1_0 = e_0_vy_r_tag_value__0 | e_0_vy_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_1_1 = e_0_vy_r_tag_value__2 | e_0_vy_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_1_2 = e_0_vy_r_tag_value__4 | e_0_vy_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_1_3 = e_0_vy_r_tag_value__6 | e_0_vy_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_1_4 = e_0_vy_r_tag_value__8 | e_0_vy_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_1_5 = e_0_vy_r_tag_value__10 | e_0_vy_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_1_6 = e_0_vy_r_tag_value__12 | e_0_vy_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_1_7 = e_0_vy_r_tag_value__14 | e_0_vy_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_2_0 = e_0_vy_r_tag_value_1_0 | e_0_vy_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_2_1 = e_0_vy_r_tag_value_1_2 | e_0_vy_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_2_2 = e_0_vy_r_tag_value_1_4 | e_0_vy_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_2_3 = e_0_vy_r_tag_value_1_6 | e_0_vy_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_3_0 = e_0_vy_r_tag_value_2_0 | e_0_vy_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_3_1 = e_0_vy_r_tag_value_2_2 | e_0_vy_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_0_vy_r_tag_value_4_0 = e_0_vy_r_tag_value_3_0 | e_0_vy_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_addrm = d_0_io_out_vz_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_0_vz_r_tag_value__0 = 4'h0 == e_0_vz_addrm ? e_0_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__1 = 4'h1 == e_0_vz_addrm ? e_0_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__2 = 4'h2 == e_0_vz_addrm ? e_0_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__3 = 4'h3 == e_0_vz_addrm ? e_0_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__4 = 4'h4 == e_0_vz_addrm ? e_0_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__5 = 4'h5 == e_0_vz_addrm ? e_0_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__6 = 4'h6 == e_0_vz_addrm ? e_0_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__7 = 4'h7 == e_0_vz_addrm ? e_0_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__8 = 4'h8 == e_0_vz_addrm ? e_0_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__9 = 4'h9 == e_0_vz_addrm ? e_0_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__10 = 4'ha == e_0_vz_addrm ? e_0_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__11 = 4'hb == e_0_vz_addrm ? e_0_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__12 = 4'hc == e_0_vz_addrm ? e_0_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__13 = 4'hd == e_0_vz_addrm ? e_0_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__14 = 4'he == e_0_vz_addrm ? e_0_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value__15 = 4'hf == e_0_vz_addrm ? e_0_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_0_vz_r_tag_value_1_0 = e_0_vz_r_tag_value__0 | e_0_vz_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_1_1 = e_0_vz_r_tag_value__2 | e_0_vz_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_1_2 = e_0_vz_r_tag_value__4 | e_0_vz_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_1_3 = e_0_vz_r_tag_value__6 | e_0_vz_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_1_4 = e_0_vz_r_tag_value__8 | e_0_vz_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_1_5 = e_0_vz_r_tag_value__10 | e_0_vz_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_1_6 = e_0_vz_r_tag_value__12 | e_0_vz_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_1_7 = e_0_vz_r_tag_value__14 | e_0_vz_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_2_0 = e_0_vz_r_tag_value_1_0 | e_0_vz_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_2_1 = e_0_vz_r_tag_value_1_2 | e_0_vz_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_2_2 = e_0_vz_r_tag_value_1_4 | e_0_vz_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_2_3 = e_0_vz_r_tag_value_1_6 | e_0_vz_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_3_0 = e_0_vz_r_tag_value_2_0 | e_0_vz_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_3_1 = e_0_vz_r_tag_value_2_2 | e_0_vz_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_0_vz_r_tag_value_4_0 = e_0_vz_r_tag_value_3_0 | e_0_vz_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_addrm = d_1_io_out_vs_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_1_vs_tagm_0 = tag1[3:0]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_1 = tag1[7:4]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_2 = tag1[11:8]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_3 = tag1[15:12]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_4 = tag1[19:16]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_5 = tag1[23:20]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_6 = tag1[27:24]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_7 = tag1[31:28]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_8 = tag1[35:32]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_9 = tag1[39:36]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_10 = tag1[43:40]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_11 = tag1[47:44]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_12 = tag1[51:48]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_13 = tag1[55:52]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_14 = tag1[59:56]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_tagm_15 = tag1[63:60]; // @[VDecode.scala 104:21]
- wire [3:0] e_1_vs_r_tag_value__0 = 4'h0 == e_1_vs_addrm ? e_1_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__1 = 4'h1 == e_1_vs_addrm ? e_1_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__2 = 4'h2 == e_1_vs_addrm ? e_1_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__3 = 4'h3 == e_1_vs_addrm ? e_1_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__4 = 4'h4 == e_1_vs_addrm ? e_1_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__5 = 4'h5 == e_1_vs_addrm ? e_1_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__6 = 4'h6 == e_1_vs_addrm ? e_1_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__7 = 4'h7 == e_1_vs_addrm ? e_1_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__8 = 4'h8 == e_1_vs_addrm ? e_1_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__9 = 4'h9 == e_1_vs_addrm ? e_1_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__10 = 4'ha == e_1_vs_addrm ? e_1_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__11 = 4'hb == e_1_vs_addrm ? e_1_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__12 = 4'hc == e_1_vs_addrm ? e_1_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__13 = 4'hd == e_1_vs_addrm ? e_1_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__14 = 4'he == e_1_vs_addrm ? e_1_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value__15 = 4'hf == e_1_vs_addrm ? e_1_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vs_r_tag_value_1_0 = e_1_vs_r_tag_value__0 | e_1_vs_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_1_1 = e_1_vs_r_tag_value__2 | e_1_vs_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_1_2 = e_1_vs_r_tag_value__4 | e_1_vs_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_1_3 = e_1_vs_r_tag_value__6 | e_1_vs_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_1_4 = e_1_vs_r_tag_value__8 | e_1_vs_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_1_5 = e_1_vs_r_tag_value__10 | e_1_vs_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_1_6 = e_1_vs_r_tag_value__12 | e_1_vs_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_1_7 = e_1_vs_r_tag_value__14 | e_1_vs_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_2_0 = e_1_vs_r_tag_value_1_0 | e_1_vs_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_2_1 = e_1_vs_r_tag_value_1_2 | e_1_vs_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_2_2 = e_1_vs_r_tag_value_1_4 | e_1_vs_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_2_3 = e_1_vs_r_tag_value_1_6 | e_1_vs_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_3_0 = e_1_vs_r_tag_value_2_0 | e_1_vs_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_3_1 = e_1_vs_r_tag_value_2_2 | e_1_vs_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_1_vs_r_tag_value_4_0 = e_1_vs_r_tag_value_3_0 | e_1_vs_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_addrm = d_1_io_out_vt_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_1_vt_r_tag_value__0 = 4'h0 == e_1_vt_addrm ? e_1_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__1 = 4'h1 == e_1_vt_addrm ? e_1_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__2 = 4'h2 == e_1_vt_addrm ? e_1_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__3 = 4'h3 == e_1_vt_addrm ? e_1_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__4 = 4'h4 == e_1_vt_addrm ? e_1_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__5 = 4'h5 == e_1_vt_addrm ? e_1_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__6 = 4'h6 == e_1_vt_addrm ? e_1_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__7 = 4'h7 == e_1_vt_addrm ? e_1_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__8 = 4'h8 == e_1_vt_addrm ? e_1_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__9 = 4'h9 == e_1_vt_addrm ? e_1_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__10 = 4'ha == e_1_vt_addrm ? e_1_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__11 = 4'hb == e_1_vt_addrm ? e_1_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__12 = 4'hc == e_1_vt_addrm ? e_1_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__13 = 4'hd == e_1_vt_addrm ? e_1_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__14 = 4'he == e_1_vt_addrm ? e_1_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value__15 = 4'hf == e_1_vt_addrm ? e_1_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vt_r_tag_value_1_0 = e_1_vt_r_tag_value__0 | e_1_vt_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_1_1 = e_1_vt_r_tag_value__2 | e_1_vt_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_1_2 = e_1_vt_r_tag_value__4 | e_1_vt_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_1_3 = e_1_vt_r_tag_value__6 | e_1_vt_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_1_4 = e_1_vt_r_tag_value__8 | e_1_vt_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_1_5 = e_1_vt_r_tag_value__10 | e_1_vt_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_1_6 = e_1_vt_r_tag_value__12 | e_1_vt_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_1_7 = e_1_vt_r_tag_value__14 | e_1_vt_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_2_0 = e_1_vt_r_tag_value_1_0 | e_1_vt_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_2_1 = e_1_vt_r_tag_value_1_2 | e_1_vt_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_2_2 = e_1_vt_r_tag_value_1_4 | e_1_vt_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_2_3 = e_1_vt_r_tag_value_1_6 | e_1_vt_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_3_0 = e_1_vt_r_tag_value_2_0 | e_1_vt_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_3_1 = e_1_vt_r_tag_value_2_2 | e_1_vt_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_1_vt_r_tag_value_4_0 = e_1_vt_r_tag_value_3_0 | e_1_vt_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_addrm = d_1_io_out_vu_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_1_vu_r_tag_value__0 = 4'h0 == e_1_vu_addrm ? e_1_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__1 = 4'h1 == e_1_vu_addrm ? e_1_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__2 = 4'h2 == e_1_vu_addrm ? e_1_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__3 = 4'h3 == e_1_vu_addrm ? e_1_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__4 = 4'h4 == e_1_vu_addrm ? e_1_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__5 = 4'h5 == e_1_vu_addrm ? e_1_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__6 = 4'h6 == e_1_vu_addrm ? e_1_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__7 = 4'h7 == e_1_vu_addrm ? e_1_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__8 = 4'h8 == e_1_vu_addrm ? e_1_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__9 = 4'h9 == e_1_vu_addrm ? e_1_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__10 = 4'ha == e_1_vu_addrm ? e_1_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__11 = 4'hb == e_1_vu_addrm ? e_1_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__12 = 4'hc == e_1_vu_addrm ? e_1_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__13 = 4'hd == e_1_vu_addrm ? e_1_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__14 = 4'he == e_1_vu_addrm ? e_1_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value__15 = 4'hf == e_1_vu_addrm ? e_1_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vu_r_tag_value_1_0 = e_1_vu_r_tag_value__0 | e_1_vu_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_1_1 = e_1_vu_r_tag_value__2 | e_1_vu_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_1_2 = e_1_vu_r_tag_value__4 | e_1_vu_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_1_3 = e_1_vu_r_tag_value__6 | e_1_vu_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_1_4 = e_1_vu_r_tag_value__8 | e_1_vu_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_1_5 = e_1_vu_r_tag_value__10 | e_1_vu_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_1_6 = e_1_vu_r_tag_value__12 | e_1_vu_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_1_7 = e_1_vu_r_tag_value__14 | e_1_vu_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_2_0 = e_1_vu_r_tag_value_1_0 | e_1_vu_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_2_1 = e_1_vu_r_tag_value_1_2 | e_1_vu_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_2_2 = e_1_vu_r_tag_value_1_4 | e_1_vu_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_2_3 = e_1_vu_r_tag_value_1_6 | e_1_vu_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_3_0 = e_1_vu_r_tag_value_2_0 | e_1_vu_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_3_1 = e_1_vu_r_tag_value_2_2 | e_1_vu_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_1_vu_r_tag_value_4_0 = e_1_vu_r_tag_value_3_0 | e_1_vu_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_addrm = d_1_io_out_vx_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_1_vx_r_tag_value__0 = 4'h0 == e_1_vx_addrm ? e_1_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__1 = 4'h1 == e_1_vx_addrm ? e_1_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__2 = 4'h2 == e_1_vx_addrm ? e_1_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__3 = 4'h3 == e_1_vx_addrm ? e_1_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__4 = 4'h4 == e_1_vx_addrm ? e_1_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__5 = 4'h5 == e_1_vx_addrm ? e_1_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__6 = 4'h6 == e_1_vx_addrm ? e_1_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__7 = 4'h7 == e_1_vx_addrm ? e_1_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__8 = 4'h8 == e_1_vx_addrm ? e_1_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__9 = 4'h9 == e_1_vx_addrm ? e_1_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__10 = 4'ha == e_1_vx_addrm ? e_1_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__11 = 4'hb == e_1_vx_addrm ? e_1_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__12 = 4'hc == e_1_vx_addrm ? e_1_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__13 = 4'hd == e_1_vx_addrm ? e_1_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__14 = 4'he == e_1_vx_addrm ? e_1_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value__15 = 4'hf == e_1_vx_addrm ? e_1_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vx_r_tag_value_1_0 = e_1_vx_r_tag_value__0 | e_1_vx_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_1_1 = e_1_vx_r_tag_value__2 | e_1_vx_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_1_2 = e_1_vx_r_tag_value__4 | e_1_vx_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_1_3 = e_1_vx_r_tag_value__6 | e_1_vx_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_1_4 = e_1_vx_r_tag_value__8 | e_1_vx_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_1_5 = e_1_vx_r_tag_value__10 | e_1_vx_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_1_6 = e_1_vx_r_tag_value__12 | e_1_vx_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_1_7 = e_1_vx_r_tag_value__14 | e_1_vx_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_2_0 = e_1_vx_r_tag_value_1_0 | e_1_vx_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_2_1 = e_1_vx_r_tag_value_1_2 | e_1_vx_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_2_2 = e_1_vx_r_tag_value_1_4 | e_1_vx_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_2_3 = e_1_vx_r_tag_value_1_6 | e_1_vx_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_3_0 = e_1_vx_r_tag_value_2_0 | e_1_vx_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_3_1 = e_1_vx_r_tag_value_2_2 | e_1_vx_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_1_vx_r_tag_value_4_0 = e_1_vx_r_tag_value_3_0 | e_1_vx_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_addrm = d_1_io_out_vy_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_1_vy_r_tag_value__0 = 4'h0 == e_1_vy_addrm ? e_1_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__1 = 4'h1 == e_1_vy_addrm ? e_1_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__2 = 4'h2 == e_1_vy_addrm ? e_1_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__3 = 4'h3 == e_1_vy_addrm ? e_1_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__4 = 4'h4 == e_1_vy_addrm ? e_1_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__5 = 4'h5 == e_1_vy_addrm ? e_1_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__6 = 4'h6 == e_1_vy_addrm ? e_1_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__7 = 4'h7 == e_1_vy_addrm ? e_1_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__8 = 4'h8 == e_1_vy_addrm ? e_1_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__9 = 4'h9 == e_1_vy_addrm ? e_1_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__10 = 4'ha == e_1_vy_addrm ? e_1_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__11 = 4'hb == e_1_vy_addrm ? e_1_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__12 = 4'hc == e_1_vy_addrm ? e_1_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__13 = 4'hd == e_1_vy_addrm ? e_1_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__14 = 4'he == e_1_vy_addrm ? e_1_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value__15 = 4'hf == e_1_vy_addrm ? e_1_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vy_r_tag_value_1_0 = e_1_vy_r_tag_value__0 | e_1_vy_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_1_1 = e_1_vy_r_tag_value__2 | e_1_vy_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_1_2 = e_1_vy_r_tag_value__4 | e_1_vy_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_1_3 = e_1_vy_r_tag_value__6 | e_1_vy_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_1_4 = e_1_vy_r_tag_value__8 | e_1_vy_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_1_5 = e_1_vy_r_tag_value__10 | e_1_vy_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_1_6 = e_1_vy_r_tag_value__12 | e_1_vy_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_1_7 = e_1_vy_r_tag_value__14 | e_1_vy_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_2_0 = e_1_vy_r_tag_value_1_0 | e_1_vy_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_2_1 = e_1_vy_r_tag_value_1_2 | e_1_vy_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_2_2 = e_1_vy_r_tag_value_1_4 | e_1_vy_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_2_3 = e_1_vy_r_tag_value_1_6 | e_1_vy_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_3_0 = e_1_vy_r_tag_value_2_0 | e_1_vy_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_3_1 = e_1_vy_r_tag_value_2_2 | e_1_vy_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_1_vy_r_tag_value_4_0 = e_1_vy_r_tag_value_3_0 | e_1_vy_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_addrm = d_1_io_out_vz_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_1_vz_r_tag_value__0 = 4'h0 == e_1_vz_addrm ? e_1_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__1 = 4'h1 == e_1_vz_addrm ? e_1_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__2 = 4'h2 == e_1_vz_addrm ? e_1_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__3 = 4'h3 == e_1_vz_addrm ? e_1_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__4 = 4'h4 == e_1_vz_addrm ? e_1_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__5 = 4'h5 == e_1_vz_addrm ? e_1_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__6 = 4'h6 == e_1_vz_addrm ? e_1_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__7 = 4'h7 == e_1_vz_addrm ? e_1_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__8 = 4'h8 == e_1_vz_addrm ? e_1_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__9 = 4'h9 == e_1_vz_addrm ? e_1_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__10 = 4'ha == e_1_vz_addrm ? e_1_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__11 = 4'hb == e_1_vz_addrm ? e_1_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__12 = 4'hc == e_1_vz_addrm ? e_1_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__13 = 4'hd == e_1_vz_addrm ? e_1_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__14 = 4'he == e_1_vz_addrm ? e_1_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value__15 = 4'hf == e_1_vz_addrm ? e_1_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_1_vz_r_tag_value_1_0 = e_1_vz_r_tag_value__0 | e_1_vz_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_1_1 = e_1_vz_r_tag_value__2 | e_1_vz_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_1_2 = e_1_vz_r_tag_value__4 | e_1_vz_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_1_3 = e_1_vz_r_tag_value__6 | e_1_vz_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_1_4 = e_1_vz_r_tag_value__8 | e_1_vz_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_1_5 = e_1_vz_r_tag_value__10 | e_1_vz_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_1_6 = e_1_vz_r_tag_value__12 | e_1_vz_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_1_7 = e_1_vz_r_tag_value__14 | e_1_vz_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_2_0 = e_1_vz_r_tag_value_1_0 | e_1_vz_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_2_1 = e_1_vz_r_tag_value_1_2 | e_1_vz_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_2_2 = e_1_vz_r_tag_value_1_4 | e_1_vz_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_2_3 = e_1_vz_r_tag_value_1_6 | e_1_vz_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_3_0 = e_1_vz_r_tag_value_2_0 | e_1_vz_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_3_1 = e_1_vz_r_tag_value_2_2 | e_1_vz_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_1_vz_r_tag_value_4_0 = e_1_vz_r_tag_value_3_0 | e_1_vz_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_addrm = d_2_io_out_vs_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_2_vs_tagm_0 = tag2[3:0]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_1 = tag2[7:4]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_2 = tag2[11:8]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_3 = tag2[15:12]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_4 = tag2[19:16]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_5 = tag2[23:20]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_6 = tag2[27:24]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_7 = tag2[31:28]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_8 = tag2[35:32]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_9 = tag2[39:36]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_10 = tag2[43:40]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_11 = tag2[47:44]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_12 = tag2[51:48]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_13 = tag2[55:52]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_14 = tag2[59:56]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_tagm_15 = tag2[63:60]; // @[VDecode.scala 104:21]
- wire [3:0] e_2_vs_r_tag_value__0 = 4'h0 == e_2_vs_addrm ? e_2_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__1 = 4'h1 == e_2_vs_addrm ? e_2_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__2 = 4'h2 == e_2_vs_addrm ? e_2_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__3 = 4'h3 == e_2_vs_addrm ? e_2_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__4 = 4'h4 == e_2_vs_addrm ? e_2_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__5 = 4'h5 == e_2_vs_addrm ? e_2_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__6 = 4'h6 == e_2_vs_addrm ? e_2_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__7 = 4'h7 == e_2_vs_addrm ? e_2_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__8 = 4'h8 == e_2_vs_addrm ? e_2_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__9 = 4'h9 == e_2_vs_addrm ? e_2_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__10 = 4'ha == e_2_vs_addrm ? e_2_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__11 = 4'hb == e_2_vs_addrm ? e_2_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__12 = 4'hc == e_2_vs_addrm ? e_2_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__13 = 4'hd == e_2_vs_addrm ? e_2_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__14 = 4'he == e_2_vs_addrm ? e_2_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value__15 = 4'hf == e_2_vs_addrm ? e_2_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vs_r_tag_value_1_0 = e_2_vs_r_tag_value__0 | e_2_vs_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_1_1 = e_2_vs_r_tag_value__2 | e_2_vs_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_1_2 = e_2_vs_r_tag_value__4 | e_2_vs_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_1_3 = e_2_vs_r_tag_value__6 | e_2_vs_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_1_4 = e_2_vs_r_tag_value__8 | e_2_vs_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_1_5 = e_2_vs_r_tag_value__10 | e_2_vs_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_1_6 = e_2_vs_r_tag_value__12 | e_2_vs_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_1_7 = e_2_vs_r_tag_value__14 | e_2_vs_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_2_0 = e_2_vs_r_tag_value_1_0 | e_2_vs_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_2_1 = e_2_vs_r_tag_value_1_2 | e_2_vs_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_2_2 = e_2_vs_r_tag_value_1_4 | e_2_vs_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_2_3 = e_2_vs_r_tag_value_1_6 | e_2_vs_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_3_0 = e_2_vs_r_tag_value_2_0 | e_2_vs_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_3_1 = e_2_vs_r_tag_value_2_2 | e_2_vs_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_2_vs_r_tag_value_4_0 = e_2_vs_r_tag_value_3_0 | e_2_vs_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_addrm = d_2_io_out_vt_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_2_vt_r_tag_value__0 = 4'h0 == e_2_vt_addrm ? e_2_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__1 = 4'h1 == e_2_vt_addrm ? e_2_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__2 = 4'h2 == e_2_vt_addrm ? e_2_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__3 = 4'h3 == e_2_vt_addrm ? e_2_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__4 = 4'h4 == e_2_vt_addrm ? e_2_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__5 = 4'h5 == e_2_vt_addrm ? e_2_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__6 = 4'h6 == e_2_vt_addrm ? e_2_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__7 = 4'h7 == e_2_vt_addrm ? e_2_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__8 = 4'h8 == e_2_vt_addrm ? e_2_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__9 = 4'h9 == e_2_vt_addrm ? e_2_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__10 = 4'ha == e_2_vt_addrm ? e_2_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__11 = 4'hb == e_2_vt_addrm ? e_2_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__12 = 4'hc == e_2_vt_addrm ? e_2_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__13 = 4'hd == e_2_vt_addrm ? e_2_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__14 = 4'he == e_2_vt_addrm ? e_2_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value__15 = 4'hf == e_2_vt_addrm ? e_2_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vt_r_tag_value_1_0 = e_2_vt_r_tag_value__0 | e_2_vt_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_1_1 = e_2_vt_r_tag_value__2 | e_2_vt_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_1_2 = e_2_vt_r_tag_value__4 | e_2_vt_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_1_3 = e_2_vt_r_tag_value__6 | e_2_vt_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_1_4 = e_2_vt_r_tag_value__8 | e_2_vt_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_1_5 = e_2_vt_r_tag_value__10 | e_2_vt_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_1_6 = e_2_vt_r_tag_value__12 | e_2_vt_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_1_7 = e_2_vt_r_tag_value__14 | e_2_vt_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_2_0 = e_2_vt_r_tag_value_1_0 | e_2_vt_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_2_1 = e_2_vt_r_tag_value_1_2 | e_2_vt_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_2_2 = e_2_vt_r_tag_value_1_4 | e_2_vt_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_2_3 = e_2_vt_r_tag_value_1_6 | e_2_vt_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_3_0 = e_2_vt_r_tag_value_2_0 | e_2_vt_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_3_1 = e_2_vt_r_tag_value_2_2 | e_2_vt_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_2_vt_r_tag_value_4_0 = e_2_vt_r_tag_value_3_0 | e_2_vt_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_addrm = d_2_io_out_vu_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_2_vu_r_tag_value__0 = 4'h0 == e_2_vu_addrm ? e_2_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__1 = 4'h1 == e_2_vu_addrm ? e_2_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__2 = 4'h2 == e_2_vu_addrm ? e_2_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__3 = 4'h3 == e_2_vu_addrm ? e_2_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__4 = 4'h4 == e_2_vu_addrm ? e_2_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__5 = 4'h5 == e_2_vu_addrm ? e_2_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__6 = 4'h6 == e_2_vu_addrm ? e_2_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__7 = 4'h7 == e_2_vu_addrm ? e_2_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__8 = 4'h8 == e_2_vu_addrm ? e_2_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__9 = 4'h9 == e_2_vu_addrm ? e_2_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__10 = 4'ha == e_2_vu_addrm ? e_2_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__11 = 4'hb == e_2_vu_addrm ? e_2_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__12 = 4'hc == e_2_vu_addrm ? e_2_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__13 = 4'hd == e_2_vu_addrm ? e_2_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__14 = 4'he == e_2_vu_addrm ? e_2_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value__15 = 4'hf == e_2_vu_addrm ? e_2_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vu_r_tag_value_1_0 = e_2_vu_r_tag_value__0 | e_2_vu_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_1_1 = e_2_vu_r_tag_value__2 | e_2_vu_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_1_2 = e_2_vu_r_tag_value__4 | e_2_vu_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_1_3 = e_2_vu_r_tag_value__6 | e_2_vu_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_1_4 = e_2_vu_r_tag_value__8 | e_2_vu_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_1_5 = e_2_vu_r_tag_value__10 | e_2_vu_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_1_6 = e_2_vu_r_tag_value__12 | e_2_vu_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_1_7 = e_2_vu_r_tag_value__14 | e_2_vu_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_2_0 = e_2_vu_r_tag_value_1_0 | e_2_vu_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_2_1 = e_2_vu_r_tag_value_1_2 | e_2_vu_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_2_2 = e_2_vu_r_tag_value_1_4 | e_2_vu_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_2_3 = e_2_vu_r_tag_value_1_6 | e_2_vu_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_3_0 = e_2_vu_r_tag_value_2_0 | e_2_vu_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_3_1 = e_2_vu_r_tag_value_2_2 | e_2_vu_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_2_vu_r_tag_value_4_0 = e_2_vu_r_tag_value_3_0 | e_2_vu_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_addrm = d_2_io_out_vx_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_2_vx_r_tag_value__0 = 4'h0 == e_2_vx_addrm ? e_2_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__1 = 4'h1 == e_2_vx_addrm ? e_2_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__2 = 4'h2 == e_2_vx_addrm ? e_2_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__3 = 4'h3 == e_2_vx_addrm ? e_2_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__4 = 4'h4 == e_2_vx_addrm ? e_2_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__5 = 4'h5 == e_2_vx_addrm ? e_2_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__6 = 4'h6 == e_2_vx_addrm ? e_2_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__7 = 4'h7 == e_2_vx_addrm ? e_2_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__8 = 4'h8 == e_2_vx_addrm ? e_2_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__9 = 4'h9 == e_2_vx_addrm ? e_2_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__10 = 4'ha == e_2_vx_addrm ? e_2_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__11 = 4'hb == e_2_vx_addrm ? e_2_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__12 = 4'hc == e_2_vx_addrm ? e_2_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__13 = 4'hd == e_2_vx_addrm ? e_2_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__14 = 4'he == e_2_vx_addrm ? e_2_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value__15 = 4'hf == e_2_vx_addrm ? e_2_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vx_r_tag_value_1_0 = e_2_vx_r_tag_value__0 | e_2_vx_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_1_1 = e_2_vx_r_tag_value__2 | e_2_vx_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_1_2 = e_2_vx_r_tag_value__4 | e_2_vx_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_1_3 = e_2_vx_r_tag_value__6 | e_2_vx_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_1_4 = e_2_vx_r_tag_value__8 | e_2_vx_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_1_5 = e_2_vx_r_tag_value__10 | e_2_vx_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_1_6 = e_2_vx_r_tag_value__12 | e_2_vx_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_1_7 = e_2_vx_r_tag_value__14 | e_2_vx_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_2_0 = e_2_vx_r_tag_value_1_0 | e_2_vx_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_2_1 = e_2_vx_r_tag_value_1_2 | e_2_vx_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_2_2 = e_2_vx_r_tag_value_1_4 | e_2_vx_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_2_3 = e_2_vx_r_tag_value_1_6 | e_2_vx_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_3_0 = e_2_vx_r_tag_value_2_0 | e_2_vx_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_3_1 = e_2_vx_r_tag_value_2_2 | e_2_vx_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_2_vx_r_tag_value_4_0 = e_2_vx_r_tag_value_3_0 | e_2_vx_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_addrm = d_2_io_out_vy_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_2_vy_r_tag_value__0 = 4'h0 == e_2_vy_addrm ? e_2_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__1 = 4'h1 == e_2_vy_addrm ? e_2_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__2 = 4'h2 == e_2_vy_addrm ? e_2_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__3 = 4'h3 == e_2_vy_addrm ? e_2_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__4 = 4'h4 == e_2_vy_addrm ? e_2_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__5 = 4'h5 == e_2_vy_addrm ? e_2_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__6 = 4'h6 == e_2_vy_addrm ? e_2_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__7 = 4'h7 == e_2_vy_addrm ? e_2_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__8 = 4'h8 == e_2_vy_addrm ? e_2_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__9 = 4'h9 == e_2_vy_addrm ? e_2_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__10 = 4'ha == e_2_vy_addrm ? e_2_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__11 = 4'hb == e_2_vy_addrm ? e_2_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__12 = 4'hc == e_2_vy_addrm ? e_2_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__13 = 4'hd == e_2_vy_addrm ? e_2_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__14 = 4'he == e_2_vy_addrm ? e_2_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value__15 = 4'hf == e_2_vy_addrm ? e_2_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vy_r_tag_value_1_0 = e_2_vy_r_tag_value__0 | e_2_vy_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_1_1 = e_2_vy_r_tag_value__2 | e_2_vy_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_1_2 = e_2_vy_r_tag_value__4 | e_2_vy_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_1_3 = e_2_vy_r_tag_value__6 | e_2_vy_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_1_4 = e_2_vy_r_tag_value__8 | e_2_vy_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_1_5 = e_2_vy_r_tag_value__10 | e_2_vy_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_1_6 = e_2_vy_r_tag_value__12 | e_2_vy_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_1_7 = e_2_vy_r_tag_value__14 | e_2_vy_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_2_0 = e_2_vy_r_tag_value_1_0 | e_2_vy_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_2_1 = e_2_vy_r_tag_value_1_2 | e_2_vy_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_2_2 = e_2_vy_r_tag_value_1_4 | e_2_vy_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_2_3 = e_2_vy_r_tag_value_1_6 | e_2_vy_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_3_0 = e_2_vy_r_tag_value_2_0 | e_2_vy_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_3_1 = e_2_vy_r_tag_value_2_2 | e_2_vy_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_2_vy_r_tag_value_4_0 = e_2_vy_r_tag_value_3_0 | e_2_vy_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_addrm = d_2_io_out_vz_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_2_vz_r_tag_value__0 = 4'h0 == e_2_vz_addrm ? e_2_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__1 = 4'h1 == e_2_vz_addrm ? e_2_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__2 = 4'h2 == e_2_vz_addrm ? e_2_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__3 = 4'h3 == e_2_vz_addrm ? e_2_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__4 = 4'h4 == e_2_vz_addrm ? e_2_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__5 = 4'h5 == e_2_vz_addrm ? e_2_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__6 = 4'h6 == e_2_vz_addrm ? e_2_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__7 = 4'h7 == e_2_vz_addrm ? e_2_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__8 = 4'h8 == e_2_vz_addrm ? e_2_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__9 = 4'h9 == e_2_vz_addrm ? e_2_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__10 = 4'ha == e_2_vz_addrm ? e_2_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__11 = 4'hb == e_2_vz_addrm ? e_2_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__12 = 4'hc == e_2_vz_addrm ? e_2_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__13 = 4'hd == e_2_vz_addrm ? e_2_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__14 = 4'he == e_2_vz_addrm ? e_2_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value__15 = 4'hf == e_2_vz_addrm ? e_2_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_2_vz_r_tag_value_1_0 = e_2_vz_r_tag_value__0 | e_2_vz_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_1_1 = e_2_vz_r_tag_value__2 | e_2_vz_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_1_2 = e_2_vz_r_tag_value__4 | e_2_vz_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_1_3 = e_2_vz_r_tag_value__6 | e_2_vz_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_1_4 = e_2_vz_r_tag_value__8 | e_2_vz_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_1_5 = e_2_vz_r_tag_value__10 | e_2_vz_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_1_6 = e_2_vz_r_tag_value__12 | e_2_vz_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_1_7 = e_2_vz_r_tag_value__14 | e_2_vz_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_2_0 = e_2_vz_r_tag_value_1_0 | e_2_vz_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_2_1 = e_2_vz_r_tag_value_1_2 | e_2_vz_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_2_2 = e_2_vz_r_tag_value_1_4 | e_2_vz_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_2_3 = e_2_vz_r_tag_value_1_6 | e_2_vz_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_3_0 = e_2_vz_r_tag_value_2_0 | e_2_vz_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_3_1 = e_2_vz_r_tag_value_2_2 | e_2_vz_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_2_vz_r_tag_value_4_0 = e_2_vz_r_tag_value_3_0 | e_2_vz_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_addrm = d_3_io_out_vs_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_3_vs_tagm_0 = tag3[3:0]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_1 = tag3[7:4]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_2 = tag3[11:8]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_3 = tag3[15:12]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_4 = tag3[19:16]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_5 = tag3[23:20]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_6 = tag3[27:24]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_7 = tag3[31:28]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_8 = tag3[35:32]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_9 = tag3[39:36]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_10 = tag3[43:40]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_11 = tag3[47:44]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_12 = tag3[51:48]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_13 = tag3[55:52]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_14 = tag3[59:56]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_tagm_15 = tag3[63:60]; // @[VDecode.scala 104:21]
- wire [3:0] e_3_vs_r_tag_value__0 = 4'h0 == e_3_vs_addrm ? e_3_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__1 = 4'h1 == e_3_vs_addrm ? e_3_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__2 = 4'h2 == e_3_vs_addrm ? e_3_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__3 = 4'h3 == e_3_vs_addrm ? e_3_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__4 = 4'h4 == e_3_vs_addrm ? e_3_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__5 = 4'h5 == e_3_vs_addrm ? e_3_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__6 = 4'h6 == e_3_vs_addrm ? e_3_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__7 = 4'h7 == e_3_vs_addrm ? e_3_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__8 = 4'h8 == e_3_vs_addrm ? e_3_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__9 = 4'h9 == e_3_vs_addrm ? e_3_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__10 = 4'ha == e_3_vs_addrm ? e_3_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__11 = 4'hb == e_3_vs_addrm ? e_3_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__12 = 4'hc == e_3_vs_addrm ? e_3_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__13 = 4'hd == e_3_vs_addrm ? e_3_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__14 = 4'he == e_3_vs_addrm ? e_3_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value__15 = 4'hf == e_3_vs_addrm ? e_3_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vs_r_tag_value_1_0 = e_3_vs_r_tag_value__0 | e_3_vs_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_1_1 = e_3_vs_r_tag_value__2 | e_3_vs_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_1_2 = e_3_vs_r_tag_value__4 | e_3_vs_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_1_3 = e_3_vs_r_tag_value__6 | e_3_vs_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_1_4 = e_3_vs_r_tag_value__8 | e_3_vs_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_1_5 = e_3_vs_r_tag_value__10 | e_3_vs_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_1_6 = e_3_vs_r_tag_value__12 | e_3_vs_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_1_7 = e_3_vs_r_tag_value__14 | e_3_vs_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_2_0 = e_3_vs_r_tag_value_1_0 | e_3_vs_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_2_1 = e_3_vs_r_tag_value_1_2 | e_3_vs_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_2_2 = e_3_vs_r_tag_value_1_4 | e_3_vs_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_2_3 = e_3_vs_r_tag_value_1_6 | e_3_vs_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_3_0 = e_3_vs_r_tag_value_2_0 | e_3_vs_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_3_1 = e_3_vs_r_tag_value_2_2 | e_3_vs_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_3_vs_r_tag_value_4_0 = e_3_vs_r_tag_value_3_0 | e_3_vs_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_addrm = d_3_io_out_vt_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_3_vt_r_tag_value__0 = 4'h0 == e_3_vt_addrm ? e_3_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__1 = 4'h1 == e_3_vt_addrm ? e_3_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__2 = 4'h2 == e_3_vt_addrm ? e_3_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__3 = 4'h3 == e_3_vt_addrm ? e_3_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__4 = 4'h4 == e_3_vt_addrm ? e_3_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__5 = 4'h5 == e_3_vt_addrm ? e_3_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__6 = 4'h6 == e_3_vt_addrm ? e_3_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__7 = 4'h7 == e_3_vt_addrm ? e_3_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__8 = 4'h8 == e_3_vt_addrm ? e_3_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__9 = 4'h9 == e_3_vt_addrm ? e_3_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__10 = 4'ha == e_3_vt_addrm ? e_3_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__11 = 4'hb == e_3_vt_addrm ? e_3_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__12 = 4'hc == e_3_vt_addrm ? e_3_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__13 = 4'hd == e_3_vt_addrm ? e_3_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__14 = 4'he == e_3_vt_addrm ? e_3_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value__15 = 4'hf == e_3_vt_addrm ? e_3_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vt_r_tag_value_1_0 = e_3_vt_r_tag_value__0 | e_3_vt_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_1_1 = e_3_vt_r_tag_value__2 | e_3_vt_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_1_2 = e_3_vt_r_tag_value__4 | e_3_vt_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_1_3 = e_3_vt_r_tag_value__6 | e_3_vt_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_1_4 = e_3_vt_r_tag_value__8 | e_3_vt_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_1_5 = e_3_vt_r_tag_value__10 | e_3_vt_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_1_6 = e_3_vt_r_tag_value__12 | e_3_vt_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_1_7 = e_3_vt_r_tag_value__14 | e_3_vt_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_2_0 = e_3_vt_r_tag_value_1_0 | e_3_vt_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_2_1 = e_3_vt_r_tag_value_1_2 | e_3_vt_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_2_2 = e_3_vt_r_tag_value_1_4 | e_3_vt_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_2_3 = e_3_vt_r_tag_value_1_6 | e_3_vt_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_3_0 = e_3_vt_r_tag_value_2_0 | e_3_vt_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_3_1 = e_3_vt_r_tag_value_2_2 | e_3_vt_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_3_vt_r_tag_value_4_0 = e_3_vt_r_tag_value_3_0 | e_3_vt_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_addrm = d_3_io_out_vu_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_3_vu_r_tag_value__0 = 4'h0 == e_3_vu_addrm ? e_3_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__1 = 4'h1 == e_3_vu_addrm ? e_3_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__2 = 4'h2 == e_3_vu_addrm ? e_3_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__3 = 4'h3 == e_3_vu_addrm ? e_3_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__4 = 4'h4 == e_3_vu_addrm ? e_3_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__5 = 4'h5 == e_3_vu_addrm ? e_3_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__6 = 4'h6 == e_3_vu_addrm ? e_3_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__7 = 4'h7 == e_3_vu_addrm ? e_3_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__8 = 4'h8 == e_3_vu_addrm ? e_3_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__9 = 4'h9 == e_3_vu_addrm ? e_3_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__10 = 4'ha == e_3_vu_addrm ? e_3_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__11 = 4'hb == e_3_vu_addrm ? e_3_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__12 = 4'hc == e_3_vu_addrm ? e_3_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__13 = 4'hd == e_3_vu_addrm ? e_3_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__14 = 4'he == e_3_vu_addrm ? e_3_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value__15 = 4'hf == e_3_vu_addrm ? e_3_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vu_r_tag_value_1_0 = e_3_vu_r_tag_value__0 | e_3_vu_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_1_1 = e_3_vu_r_tag_value__2 | e_3_vu_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_1_2 = e_3_vu_r_tag_value__4 | e_3_vu_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_1_3 = e_3_vu_r_tag_value__6 | e_3_vu_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_1_4 = e_3_vu_r_tag_value__8 | e_3_vu_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_1_5 = e_3_vu_r_tag_value__10 | e_3_vu_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_1_6 = e_3_vu_r_tag_value__12 | e_3_vu_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_1_7 = e_3_vu_r_tag_value__14 | e_3_vu_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_2_0 = e_3_vu_r_tag_value_1_0 | e_3_vu_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_2_1 = e_3_vu_r_tag_value_1_2 | e_3_vu_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_2_2 = e_3_vu_r_tag_value_1_4 | e_3_vu_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_2_3 = e_3_vu_r_tag_value_1_6 | e_3_vu_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_3_0 = e_3_vu_r_tag_value_2_0 | e_3_vu_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_3_1 = e_3_vu_r_tag_value_2_2 | e_3_vu_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_3_vu_r_tag_value_4_0 = e_3_vu_r_tag_value_3_0 | e_3_vu_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_addrm = d_3_io_out_vx_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_3_vx_r_tag_value__0 = 4'h0 == e_3_vx_addrm ? e_3_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__1 = 4'h1 == e_3_vx_addrm ? e_3_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__2 = 4'h2 == e_3_vx_addrm ? e_3_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__3 = 4'h3 == e_3_vx_addrm ? e_3_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__4 = 4'h4 == e_3_vx_addrm ? e_3_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__5 = 4'h5 == e_3_vx_addrm ? e_3_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__6 = 4'h6 == e_3_vx_addrm ? e_3_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__7 = 4'h7 == e_3_vx_addrm ? e_3_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__8 = 4'h8 == e_3_vx_addrm ? e_3_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__9 = 4'h9 == e_3_vx_addrm ? e_3_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__10 = 4'ha == e_3_vx_addrm ? e_3_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__11 = 4'hb == e_3_vx_addrm ? e_3_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__12 = 4'hc == e_3_vx_addrm ? e_3_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__13 = 4'hd == e_3_vx_addrm ? e_3_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__14 = 4'he == e_3_vx_addrm ? e_3_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value__15 = 4'hf == e_3_vx_addrm ? e_3_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vx_r_tag_value_1_0 = e_3_vx_r_tag_value__0 | e_3_vx_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_1_1 = e_3_vx_r_tag_value__2 | e_3_vx_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_1_2 = e_3_vx_r_tag_value__4 | e_3_vx_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_1_3 = e_3_vx_r_tag_value__6 | e_3_vx_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_1_4 = e_3_vx_r_tag_value__8 | e_3_vx_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_1_5 = e_3_vx_r_tag_value__10 | e_3_vx_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_1_6 = e_3_vx_r_tag_value__12 | e_3_vx_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_1_7 = e_3_vx_r_tag_value__14 | e_3_vx_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_2_0 = e_3_vx_r_tag_value_1_0 | e_3_vx_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_2_1 = e_3_vx_r_tag_value_1_2 | e_3_vx_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_2_2 = e_3_vx_r_tag_value_1_4 | e_3_vx_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_2_3 = e_3_vx_r_tag_value_1_6 | e_3_vx_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_3_0 = e_3_vx_r_tag_value_2_0 | e_3_vx_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_3_1 = e_3_vx_r_tag_value_2_2 | e_3_vx_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_3_vx_r_tag_value_4_0 = e_3_vx_r_tag_value_3_0 | e_3_vx_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_addrm = d_3_io_out_vy_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_3_vy_r_tag_value__0 = 4'h0 == e_3_vy_addrm ? e_3_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__1 = 4'h1 == e_3_vy_addrm ? e_3_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__2 = 4'h2 == e_3_vy_addrm ? e_3_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__3 = 4'h3 == e_3_vy_addrm ? e_3_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__4 = 4'h4 == e_3_vy_addrm ? e_3_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__5 = 4'h5 == e_3_vy_addrm ? e_3_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__6 = 4'h6 == e_3_vy_addrm ? e_3_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__7 = 4'h7 == e_3_vy_addrm ? e_3_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__8 = 4'h8 == e_3_vy_addrm ? e_3_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__9 = 4'h9 == e_3_vy_addrm ? e_3_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__10 = 4'ha == e_3_vy_addrm ? e_3_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__11 = 4'hb == e_3_vy_addrm ? e_3_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__12 = 4'hc == e_3_vy_addrm ? e_3_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__13 = 4'hd == e_3_vy_addrm ? e_3_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__14 = 4'he == e_3_vy_addrm ? e_3_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value__15 = 4'hf == e_3_vy_addrm ? e_3_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vy_r_tag_value_1_0 = e_3_vy_r_tag_value__0 | e_3_vy_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_1_1 = e_3_vy_r_tag_value__2 | e_3_vy_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_1_2 = e_3_vy_r_tag_value__4 | e_3_vy_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_1_3 = e_3_vy_r_tag_value__6 | e_3_vy_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_1_4 = e_3_vy_r_tag_value__8 | e_3_vy_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_1_5 = e_3_vy_r_tag_value__10 | e_3_vy_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_1_6 = e_3_vy_r_tag_value__12 | e_3_vy_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_1_7 = e_3_vy_r_tag_value__14 | e_3_vy_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_2_0 = e_3_vy_r_tag_value_1_0 | e_3_vy_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_2_1 = e_3_vy_r_tag_value_1_2 | e_3_vy_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_2_2 = e_3_vy_r_tag_value_1_4 | e_3_vy_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_2_3 = e_3_vy_r_tag_value_1_6 | e_3_vy_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_3_0 = e_3_vy_r_tag_value_2_0 | e_3_vy_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_3_1 = e_3_vy_r_tag_value_2_2 | e_3_vy_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_3_vy_r_tag_value_4_0 = e_3_vy_r_tag_value_3_0 | e_3_vy_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_addrm = d_3_io_out_vz_addr[5:2]; // @[VDecode.scala 101:21]
- wire [3:0] e_3_vz_r_tag_value__0 = 4'h0 == e_3_vz_addrm ? e_3_vs_tagm_0 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__1 = 4'h1 == e_3_vz_addrm ? e_3_vs_tagm_1 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__2 = 4'h2 == e_3_vz_addrm ? e_3_vs_tagm_2 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__3 = 4'h3 == e_3_vz_addrm ? e_3_vs_tagm_3 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__4 = 4'h4 == e_3_vz_addrm ? e_3_vs_tagm_4 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__5 = 4'h5 == e_3_vz_addrm ? e_3_vs_tagm_5 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__6 = 4'h6 == e_3_vz_addrm ? e_3_vs_tagm_6 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__7 = 4'h7 == e_3_vz_addrm ? e_3_vs_tagm_7 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__8 = 4'h8 == e_3_vz_addrm ? e_3_vs_tagm_8 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__9 = 4'h9 == e_3_vz_addrm ? e_3_vs_tagm_9 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__10 = 4'ha == e_3_vz_addrm ? e_3_vs_tagm_10 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__11 = 4'hb == e_3_vz_addrm ? e_3_vs_tagm_11 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__12 = 4'hc == e_3_vz_addrm ? e_3_vs_tagm_12 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__13 = 4'hd == e_3_vz_addrm ? e_3_vs_tagm_13 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__14 = 4'he == e_3_vz_addrm ? e_3_vs_tagm_14 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value__15 = 4'hf == e_3_vz_addrm ? e_3_vs_tagm_15 : 4'h0; // @[Library.scala 115:22]
- wire [3:0] e_3_vz_r_tag_value_1_0 = e_3_vz_r_tag_value__0 | e_3_vz_r_tag_value__1; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_1_1 = e_3_vz_r_tag_value__2 | e_3_vz_r_tag_value__3; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_1_2 = e_3_vz_r_tag_value__4 | e_3_vz_r_tag_value__5; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_1_3 = e_3_vz_r_tag_value__6 | e_3_vz_r_tag_value__7; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_1_4 = e_3_vz_r_tag_value__8 | e_3_vz_r_tag_value__9; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_1_5 = e_3_vz_r_tag_value__10 | e_3_vz_r_tag_value__11; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_1_6 = e_3_vz_r_tag_value__12 | e_3_vz_r_tag_value__13; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_1_7 = e_3_vz_r_tag_value__14 | e_3_vz_r_tag_value__15; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_2_0 = e_3_vz_r_tag_value_1_0 | e_3_vz_r_tag_value_1_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_2_1 = e_3_vz_r_tag_value_1_2 | e_3_vz_r_tag_value_1_3; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_2_2 = e_3_vz_r_tag_value_1_4 | e_3_vz_r_tag_value_1_5; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_2_3 = e_3_vz_r_tag_value_1_6 | e_3_vz_r_tag_value_1_7; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_3_0 = e_3_vz_r_tag_value_2_0 | e_3_vz_r_tag_value_2_1; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_3_1 = e_3_vz_r_tag_value_2_2 | e_3_vz_r_tag_value_2_3; // @[Library.scala 129:37]
- wire [3:0] e_3_vz_r_tag_value_4_0 = e_3_vz_r_tag_value_3_0 | e_3_vz_r_tag_value_3_1; // @[Library.scala 129:37]
- wire [3:0] _icount_T = {io_in_bits_0_valid,io_in_bits_1_valid,io_in_bits_2_valid,io_in_bits_3_valid}; // @[Cat.scala 31:58]
- wire [1:0] _icount_T_5 = _icount_T[0] + _icount_T[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _icount_T_7 = _icount_T[2] + _icount_T[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _icount_T_9 = _icount_T_5 + _icount_T_7; // @[Bitwise.scala 48:55]
- wire [2:0] icount = io_in_valid ? _icount_T_9 : 3'h0; // @[Library.scala 32:8]
- wire _ocount_T = io_out_0_valid & io_out_0_ready; // @[VDecode.scala 134:59]
- wire _ocount_T_2 = valid_0 & ~(io_out_0_valid & io_out_0_ready); // @[VDecode.scala 134:38]
- wire _ocount_T_3 = io_out_1_valid & io_out_1_ready; // @[VDecode.scala 135:59]
- wire _ocount_T_5 = valid_1 & ~(io_out_1_valid & io_out_1_ready); // @[VDecode.scala 135:38]
- wire _ocount_T_6 = io_out_2_valid & io_out_2_ready; // @[VDecode.scala 136:59]
- wire _ocount_T_8 = valid_2 & ~(io_out_2_valid & io_out_2_ready); // @[VDecode.scala 136:38]
- wire _ocount_T_9 = io_out_3_valid & io_out_3_ready; // @[VDecode.scala 137:59]
- wire _ocount_T_11 = valid_3 & ~(io_out_3_valid & io_out_3_ready); // @[VDecode.scala 137:38]
- wire [3:0] _ocount_T_12 = {_ocount_T_2,_ocount_T_5,_ocount_T_8,_ocount_T_11}; // @[Cat.scala 31:58]
- wire [1:0] _ocount_T_17 = _ocount_T_12[0] + _ocount_T_12[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _ocount_T_19 = _ocount_T_12[2] + _ocount_T_12[3]; // @[Bitwise.scala 48:55]
- wire [2:0] ocount = _ocount_T_17 + _ocount_T_19; // @[Bitwise.scala 48:55]
- wire [3:0] _f_io_out_0_ready_T = {{1'd0}, ocount}; // @[VDecode.scala 141:31]
- wire [2:0] _f_io_out_1_ready_T_1 = 3'h1 + ocount; // @[VDecode.scala 141:31]
- wire [2:0] _f_io_out_2_ready_T_1 = 3'h2 + ocount; // @[VDecode.scala 141:31]
- wire [2:0] _f_io_out_3_ready_T_1 = 3'h3 + ocount; // @[VDecode.scala 141:31]
- wire [3:0] _fcount_T_4 = {_T_3,_T_2,_T_1,_T}; // @[Cat.scala 31:58]
- wire [1:0] _fcount_T_9 = _fcount_T_4[0] + _fcount_T_4[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _fcount_T_11 = _fcount_T_4[2] + _fcount_T_4[3]; // @[Bitwise.scala 48:55]
- wire [2:0] fcount = _fcount_T_9 + _fcount_T_11; // @[Bitwise.scala 48:55]
- wire [2:0] _valid_0_T_1 = ocount + fcount; // @[VDecode.scala 153:25]
- wire [4:0] _GEN_836 = {{2'd0}, icount}; // @[VDecode.scala 158:27]
- wire [4:0] _io_stall_T_1 = f_io_count + _GEN_836; // @[VDecode.scala 158:27]
- wire [63:0] _wactive0_T_2 = io_vrfsb_data[63:0] | io_vrfsb_data[127:64]; // @[VDecode.scala 166:39]
- wire [63:0] wactive0 = _wactive0_T_2 | io_active; // @[VDecode.scala 166:64]
- wire [63:0] actv_0_wactive = actv2_0_wactive[63:0] | actv2_0_wactive[127:64]; // @[VDecode.scala 205:48]
- wire [63:0] _wactive1_T = actv2_0_ractive | actv_0_wactive; // @[VDecode.scala 167:34]
- wire [63:0] wactive1 = _wactive1_T | wactive0; // @[VDecode.scala 167:52]
- wire [63:0] actv_1_wactive = actv2_1_wactive[63:0] | actv2_1_wactive[127:64]; // @[VDecode.scala 205:48]
- wire [63:0] _wactive2_T = actv2_1_ractive | actv_1_wactive; // @[VDecode.scala 168:34]
- wire [63:0] wactive2 = _wactive2_T | wactive1; // @[VDecode.scala 168:52]
- wire [63:0] actv_2_wactive = actv2_2_wactive[63:0] | actv2_2_wactive[127:64]; // @[VDecode.scala 205:48]
- wire [63:0] _wactive3_T = actv2_2_ractive | actv_2_wactive; // @[VDecode.scala 169:34]
- wire [63:0] wactive3 = _wactive3_T | wactive2; // @[VDecode.scala 169:52]
- wire [63:0] ractive2 = actv_1_wactive | actv_0_wactive; // @[VDecode.scala 175:34]
- wire [63:0] ractive3 = actv_2_wactive | ractive2; // @[VDecode.scala 176:34]
- wire [63:0] _depends_0_T = wactive0 & actv_0_wactive; // @[VDecode.scala 180:31]
- wire depends_0 = _depends_0_T != 64'h0; // @[VDecode.scala 180:50]
- wire [63:0] _depends_1_T = wactive1 & actv_1_wactive; // @[VDecode.scala 180:31]
- wire [63:0] _depends_1_T_2 = actv_0_wactive & actv2_1_ractive; // @[VDecode.scala 181:31]
- wire _depends_1_T_3 = _depends_1_T_2 != 64'h0; // @[VDecode.scala 181:50]
- wire depends_1 = _depends_1_T != 64'h0 | _depends_1_T_3; // @[VDecode.scala 180:58]
- wire [63:0] _depends_2_T = wactive2 & actv_2_wactive; // @[VDecode.scala 180:31]
- wire [63:0] _depends_2_T_2 = ractive2 & actv2_2_ractive; // @[VDecode.scala 181:31]
- wire _depends_2_T_3 = _depends_2_T_2 != 64'h0; // @[VDecode.scala 181:50]
- wire depends_2 = _depends_2_T != 64'h0 | _depends_2_T_3; // @[VDecode.scala 180:58]
- wire [63:0] actv_3_wactive = actv2_3_wactive[63:0] | actv2_3_wactive[127:64]; // @[VDecode.scala 205:48]
- wire [63:0] _depends_3_T = wactive3 & actv_3_wactive; // @[VDecode.scala 180:31]
- wire [63:0] _depends_3_T_2 = ractive3 & actv2_3_ractive; // @[VDecode.scala 181:31]
- wire _depends_3_T_3 = _depends_3_T_2 != 64'h0; // @[VDecode.scala 181:50]
- wire depends_3 = _depends_3_T != 64'h0 | _depends_3_T_3; // @[VDecode.scala 180:58]
- wire _fvalid_WIRE_1 = f_io_out_1_valid; // @[VDecode.scala 186:{23,23}]
- wire _fvalid_WIRE_0 = f_io_out_0_valid; // @[VDecode.scala 186:{23,23}]
- wire _fvalid_WIRE_3 = f_io_out_3_valid; // @[VDecode.scala 186:{23,23}]
- wire _fvalid_WIRE_2 = f_io_out_2_valid; // @[VDecode.scala 186:{23,23}]
- wire [3:0] fvalid = {_fvalid_WIRE_3,_fvalid_WIRE_2,_fvalid_WIRE_1,_fvalid_WIRE_0}; // @[VDecode.scala 187:62]
- wire [3:0] _dataEn_T_1 = {valid_3,valid_2,valid_1,valid_0}; // @[VDecode.scala 193:35]
- wire _dataEn_T_2 = _dataEn_T_1 != 4'h0; // @[VDecode.scala 193:42]
- wire dataEn = fvalid[0] | _dataEn_T_1 != 4'h0; // @[VDecode.scala 193:26]
- wire [3:0] output_ = {_ocount_T_9,_ocount_T_6,_ocount_T_3,_ocount_T}; // @[Cat.scala 31:58]
- wire _T_47 = ~output_[1]; // @[VDecode.scala 246:28]
- wire _T_50 = ~output_[2]; // @[VDecode.scala 251:28]
- wire _T_53 = ~output_[3]; // @[VDecode.scala 256:28]
- wire e_0_cmdsync = d_0_io_out_cmdsync; // @[VDecode.scala 114:10 54:15]
- wire _GEN_168 = valid_3 & ~output_[3] ? data_3_cmdsync : e_0_cmdsync; // @[VDecode.scala 256:40 257:16 262:16]
- wire [31:0] e_0_sv_data = d_0_io_out_sv_data; // @[VDecode.scala 114:10 54:15]
- wire [31:0] _GEN_169 = valid_3 & ~output_[3] ? data_3_sv_data : e_0_sv_data; // @[VDecode.scala 256:40 257:16 262:16]
- wire [31:0] e_0_sv_addr = d_0_io_out_sv_addr; // @[VDecode.scala 114:10 54:15]
- wire [31:0] _GEN_170 = valid_3 & ~output_[3] ? data_3_sv_addr : e_0_sv_addr; // @[VDecode.scala 256:40 257:16 262:16]
- wire e_0_sv_valid = d_0_io_out_sv_valid; // @[VDecode.scala 114:10 54:15]
- wire _GEN_171 = valid_3 & ~output_[3] ? data_3_sv_valid : e_0_sv_valid; // @[VDecode.scala 256:40 257:16 262:16]
- wire [3:0] _GEN_172 = valid_3 & ~output_[3] ? data_3_vz_tag : e_0_vz_r_tag_value_4_0; // @[VDecode.scala 256:40 257:16 262:16]
- wire [5:0] e_0_vz_r_addr = d_0_io_out_vz_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_173 = valid_3 & ~output_[3] ? data_3_vz_addr : e_0_vz_r_addr; // @[VDecode.scala 256:40 257:16 262:16]
- wire e_0_vz_r_valid = d_0_io_out_vz_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_174 = valid_3 & ~output_[3] ? data_3_vz_valid : e_0_vz_r_valid; // @[VDecode.scala 256:40 257:16 262:16]
- wire [3:0] _GEN_175 = valid_3 & ~output_[3] ? data_3_vy_tag : e_0_vy_r_tag_value_4_0; // @[VDecode.scala 256:40 257:16 262:16]
- wire [5:0] e_0_vy_r_addr = d_0_io_out_vy_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_176 = valid_3 & ~output_[3] ? data_3_vy_addr : e_0_vy_r_addr; // @[VDecode.scala 256:40 257:16 262:16]
- wire e_0_vy_r_valid = d_0_io_out_vy_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_177 = valid_3 & ~output_[3] ? data_3_vy_valid : e_0_vy_r_valid; // @[VDecode.scala 256:40 257:16 262:16]
- wire [3:0] _GEN_178 = valid_3 & ~output_[3] ? data_3_vx_tag : e_0_vx_r_tag_value_4_0; // @[VDecode.scala 256:40 257:16 262:16]
- wire [5:0] e_0_vx_r_addr = d_0_io_out_vx_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_179 = valid_3 & ~output_[3] ? data_3_vx_addr : e_0_vx_r_addr; // @[VDecode.scala 256:40 257:16 262:16]
- wire e_0_vx_r_valid = d_0_io_out_vx_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_180 = valid_3 & ~output_[3] ? data_3_vx_valid : e_0_vx_r_valid; // @[VDecode.scala 256:40 257:16 262:16]
- wire [3:0] _GEN_181 = valid_3 & ~output_[3] ? data_3_vu_tag : e_0_vu_r_tag_value_4_0; // @[VDecode.scala 256:40 257:16 262:16]
- wire [5:0] e_0_vu_r_addr = d_0_io_out_vu_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_182 = valid_3 & ~output_[3] ? data_3_vu_addr : e_0_vu_r_addr; // @[VDecode.scala 256:40 257:16 262:16]
- wire e_0_vu_r_valid = d_0_io_out_vu_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_183 = valid_3 & ~output_[3] ? data_3_vu_valid : e_0_vu_r_valid; // @[VDecode.scala 256:40 257:16 262:16]
- wire [3:0] _GEN_184 = valid_3 & ~output_[3] ? data_3_vt_tag : e_0_vt_r_tag_value_4_0; // @[VDecode.scala 256:40 257:16 262:16]
- wire [5:0] e_0_vt_r_addr = d_0_io_out_vt_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_185 = valid_3 & ~output_[3] ? data_3_vt_addr : e_0_vt_r_addr; // @[VDecode.scala 256:40 257:16 262:16]
- wire e_0_vt_r_valid = d_0_io_out_vt_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_186 = valid_3 & ~output_[3] ? data_3_vt_valid : e_0_vt_r_valid; // @[VDecode.scala 256:40 257:16 262:16]
- wire [3:0] _GEN_187 = valid_3 & ~output_[3] ? data_3_vs_tag : e_0_vs_r_tag_value_4_0; // @[VDecode.scala 256:40 257:16 262:16]
- wire [5:0] e_0_vs_r_addr = d_0_io_out_vs_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_188 = valid_3 & ~output_[3] ? data_3_vs_addr : e_0_vs_r_addr; // @[VDecode.scala 256:40 257:16 262:16]
- wire e_0_vs_r_valid = d_0_io_out_vs_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_189 = valid_3 & ~output_[3] ? data_3_vs_valid : e_0_vs_r_valid; // @[VDecode.scala 256:40 257:16 262:16]
- wire [5:0] e_0_vg_addr = d_0_io_out_vg_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_190 = valid_3 & ~output_[3] ? data_3_vg_addr : e_0_vg_addr; // @[VDecode.scala 256:40 257:16 262:16]
- wire [5:0] e_0_vf_addr = d_0_io_out_vf_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_192 = valid_3 & ~output_[3] ? data_3_vf_addr : e_0_vf_addr; // @[VDecode.scala 256:40 257:16 262:16]
- wire [5:0] e_0_ve_addr = d_0_io_out_ve_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_194 = valid_3 & ~output_[3] ? data_3_ve_addr : e_0_ve_addr; // @[VDecode.scala 256:40 257:16 262:16]
- wire [5:0] e_0_vd_addr = d_0_io_out_vd_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_196 = valid_3 & ~output_[3] ? data_3_vd_addr : e_0_vd_addr; // @[VDecode.scala 256:40 257:16 262:16]
- wire e_0_vd_valid = d_0_io_out_vd_valid; // @[VDecode.scala 114:10 54:15]
- wire _GEN_197 = valid_3 & ~output_[3] ? data_3_vd_valid : e_0_vd_valid; // @[VDecode.scala 256:40 257:16 262:16]
- wire e_0_m = d_0_io_out_m; // @[VDecode.scala 114:10 54:15]
- wire _GEN_198 = valid_3 & ~output_[3] ? data_3_m : e_0_m; // @[VDecode.scala 256:40 257:16 262:16]
- wire [2:0] e_0_sz = d_0_io_out_sz; // @[VDecode.scala 114:10 54:15]
- wire [2:0] _GEN_199 = valid_3 & ~output_[3] ? data_3_sz : e_0_sz; // @[VDecode.scala 256:40 257:16 262:16]
- wire [2:0] e_0_f2 = d_0_io_out_f2; // @[VDecode.scala 114:10 54:15]
- wire [2:0] _GEN_200 = valid_3 & ~output_[3] ? data_3_f2 : e_0_f2; // @[VDecode.scala 256:40 257:16 262:16]
- wire [6:0] e_0_op = d_0_io_out_op; // @[VDecode.scala 114:10 54:15]
- wire [6:0] _GEN_201 = valid_3 & ~output_[3] ? data_3_op : e_0_op; // @[VDecode.scala 256:40 257:16 262:16]
- wire cmdqMux_4_st = d_0_io_cmdq_st; // @[VDecode.scala 221:{24,24}]
- wire _GEN_202 = valid_3 & ~output_[3] ? cmdq_3_st : cmdqMux_4_st; // @[VDecode.scala 256:40 258:16 263:16]
- wire cmdqMux_4_ld = d_0_io_cmdq_ld; // @[VDecode.scala 221:{24,24}]
- wire _GEN_203 = valid_3 & ~output_[3] ? cmdq_3_ld : cmdqMux_4_ld; // @[VDecode.scala 256:40 258:16 263:16]
- wire cmdqMux_4_ldst = d_0_io_cmdq_ldst; // @[VDecode.scala 221:{24,24}]
- wire _GEN_204 = valid_3 & ~output_[3] ? cmdq_3_ldst : cmdqMux_4_ldst; // @[VDecode.scala 256:40 258:16 263:16]
- wire cmdqMux_4_conv = d_0_io_cmdq_conv; // @[VDecode.scala 221:{24,24}]
- wire _GEN_205 = valid_3 & ~output_[3] ? cmdq_3_conv : cmdqMux_4_conv; // @[VDecode.scala 256:40 258:16 263:16]
- wire cmdqMux_4_alu = d_0_io_cmdq_alu; // @[VDecode.scala 221:{24,24}]
- wire _GEN_206 = valid_3 & ~output_[3] ? cmdq_3_alu : cmdqMux_4_alu; // @[VDecode.scala 256:40 258:16 263:16]
- wire [63:0] w1 = d_0_io_actv_wactive & tag1; // @[VDecode.scala 212:35]
- wire [63:0] _w0_T = ~tag1; // @[VDecode.scala 211:37]
- wire [63:0] w0 = d_0_io_actv_wactive & _w0_T; // @[VDecode.scala 211:35]
- wire [127:0] dactv_0_wactive = {w1,w0}; // @[Cat.scala 31:58]
- wire [127:0] _GEN_207 = valid_3 & ~output_[3] ? actv2_3_wactive : dactv_0_wactive; // @[VDecode.scala 256:40 259:16 264:16]
- wire [63:0] dactv_0_ractive = d_0_io_actv_ractive; // @[VDecode.scala 209:19 213:22]
- wire [63:0] _GEN_208 = valid_3 & ~output_[3] ? actv2_3_ractive : dactv_0_ractive; // @[VDecode.scala 256:40 259:16 264:16]
- wire [4:0] _GEN_209 = valid_3 & ~output_[3] ? 5'hf : 5'h1f; // @[VDecode.scala 256:40 260:13 265:13]
- wire [4:0] _GEN_251 = valid_2 & ~output_[2] ? 5'h7 : _GEN_209; // @[VDecode.scala 251:40 255:13]
- wire [4:0] _GEN_293 = valid_1 & ~output_[1] ? 5'h3 : _GEN_251; // @[VDecode.scala 246:40 250:13]
- wire [4:0] marked0 = valid_0 & ~output_[0] ? 5'h1 : _GEN_293; // @[VDecode.scala 241:33 245:13]
- wire e_1_cmdsync = d_1_io_out_cmdsync; // @[VDecode.scala 114:10 54:15]
- wire _GEN_336 = ~marked0[4] ? e_0_cmdsync : e_1_cmdsync; // @[VDecode.scala 283:29 284:16 289:16]
- wire [31:0] e_1_sv_data = d_1_io_out_sv_data; // @[VDecode.scala 114:10 54:15]
- wire [31:0] _GEN_337 = ~marked0[4] ? e_0_sv_data : e_1_sv_data; // @[VDecode.scala 283:29 284:16 289:16]
- wire [31:0] e_1_sv_addr = d_1_io_out_sv_addr; // @[VDecode.scala 114:10 54:15]
- wire [31:0] _GEN_338 = ~marked0[4] ? e_0_sv_addr : e_1_sv_addr; // @[VDecode.scala 283:29 284:16 289:16]
- wire e_1_sv_valid = d_1_io_out_sv_valid; // @[VDecode.scala 114:10 54:15]
- wire _GEN_339 = ~marked0[4] ? e_0_sv_valid : e_1_sv_valid; // @[VDecode.scala 283:29 284:16 289:16]
- wire [3:0] _GEN_340 = ~marked0[4] ? e_0_vz_r_tag_value_4_0 : e_1_vz_r_tag_value_4_0; // @[VDecode.scala 283:29 284:16 289:16]
- wire [5:0] e_1_vz_r_addr = d_1_io_out_vz_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_341 = ~marked0[4] ? e_0_vz_r_addr : e_1_vz_r_addr; // @[VDecode.scala 283:29 284:16 289:16]
- wire e_1_vz_r_valid = d_1_io_out_vz_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_342 = ~marked0[4] ? e_0_vz_r_valid : e_1_vz_r_valid; // @[VDecode.scala 283:29 284:16 289:16]
- wire [3:0] _GEN_343 = ~marked0[4] ? e_0_vy_r_tag_value_4_0 : e_1_vy_r_tag_value_4_0; // @[VDecode.scala 283:29 284:16 289:16]
- wire [5:0] e_1_vy_r_addr = d_1_io_out_vy_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_344 = ~marked0[4] ? e_0_vy_r_addr : e_1_vy_r_addr; // @[VDecode.scala 283:29 284:16 289:16]
- wire e_1_vy_r_valid = d_1_io_out_vy_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_345 = ~marked0[4] ? e_0_vy_r_valid : e_1_vy_r_valid; // @[VDecode.scala 283:29 284:16 289:16]
- wire [3:0] _GEN_346 = ~marked0[4] ? e_0_vx_r_tag_value_4_0 : e_1_vx_r_tag_value_4_0; // @[VDecode.scala 283:29 284:16 289:16]
- wire [5:0] e_1_vx_r_addr = d_1_io_out_vx_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_347 = ~marked0[4] ? e_0_vx_r_addr : e_1_vx_r_addr; // @[VDecode.scala 283:29 284:16 289:16]
- wire e_1_vx_r_valid = d_1_io_out_vx_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_348 = ~marked0[4] ? e_0_vx_r_valid : e_1_vx_r_valid; // @[VDecode.scala 283:29 284:16 289:16]
- wire [3:0] _GEN_349 = ~marked0[4] ? e_0_vu_r_tag_value_4_0 : e_1_vu_r_tag_value_4_0; // @[VDecode.scala 283:29 284:16 289:16]
- wire [5:0] e_1_vu_r_addr = d_1_io_out_vu_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_350 = ~marked0[4] ? e_0_vu_r_addr : e_1_vu_r_addr; // @[VDecode.scala 283:29 284:16 289:16]
- wire e_1_vu_r_valid = d_1_io_out_vu_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_351 = ~marked0[4] ? e_0_vu_r_valid : e_1_vu_r_valid; // @[VDecode.scala 283:29 284:16 289:16]
- wire [3:0] _GEN_352 = ~marked0[4] ? e_0_vt_r_tag_value_4_0 : e_1_vt_r_tag_value_4_0; // @[VDecode.scala 283:29 284:16 289:16]
- wire [5:0] e_1_vt_r_addr = d_1_io_out_vt_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_353 = ~marked0[4] ? e_0_vt_r_addr : e_1_vt_r_addr; // @[VDecode.scala 283:29 284:16 289:16]
- wire e_1_vt_r_valid = d_1_io_out_vt_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_354 = ~marked0[4] ? e_0_vt_r_valid : e_1_vt_r_valid; // @[VDecode.scala 283:29 284:16 289:16]
- wire [3:0] _GEN_355 = ~marked0[4] ? e_0_vs_r_tag_value_4_0 : e_1_vs_r_tag_value_4_0; // @[VDecode.scala 283:29 284:16 289:16]
- wire [5:0] e_1_vs_r_addr = d_1_io_out_vs_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_356 = ~marked0[4] ? e_0_vs_r_addr : e_1_vs_r_addr; // @[VDecode.scala 283:29 284:16 289:16]
- wire e_1_vs_r_valid = d_1_io_out_vs_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_357 = ~marked0[4] ? e_0_vs_r_valid : e_1_vs_r_valid; // @[VDecode.scala 283:29 284:16 289:16]
- wire [5:0] e_1_vg_addr = d_1_io_out_vg_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_358 = ~marked0[4] ? e_0_vg_addr : e_1_vg_addr; // @[VDecode.scala 283:29 284:16 289:16]
- wire [5:0] e_1_vf_addr = d_1_io_out_vf_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_360 = ~marked0[4] ? e_0_vf_addr : e_1_vf_addr; // @[VDecode.scala 283:29 284:16 289:16]
- wire [5:0] e_1_ve_addr = d_1_io_out_ve_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_362 = ~marked0[4] ? e_0_ve_addr : e_1_ve_addr; // @[VDecode.scala 283:29 284:16 289:16]
- wire [5:0] e_1_vd_addr = d_1_io_out_vd_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_364 = ~marked0[4] ? e_0_vd_addr : e_1_vd_addr; // @[VDecode.scala 283:29 284:16 289:16]
- wire e_1_vd_valid = d_1_io_out_vd_valid; // @[VDecode.scala 114:10 54:15]
- wire _GEN_365 = ~marked0[4] ? e_0_vd_valid : e_1_vd_valid; // @[VDecode.scala 283:29 284:16 289:16]
- wire e_1_m = d_1_io_out_m; // @[VDecode.scala 114:10 54:15]
- wire _GEN_366 = ~marked0[4] ? e_0_m : e_1_m; // @[VDecode.scala 283:29 284:16 289:16]
- wire [2:0] e_1_sz = d_1_io_out_sz; // @[VDecode.scala 114:10 54:15]
- wire [2:0] _GEN_367 = ~marked0[4] ? e_0_sz : e_1_sz; // @[VDecode.scala 283:29 284:16 289:16]
- wire [2:0] e_1_f2 = d_1_io_out_f2; // @[VDecode.scala 114:10 54:15]
- wire [2:0] _GEN_368 = ~marked0[4] ? e_0_f2 : e_1_f2; // @[VDecode.scala 283:29 284:16 289:16]
- wire [6:0] e_1_op = d_1_io_out_op; // @[VDecode.scala 114:10 54:15]
- wire [6:0] _GEN_369 = ~marked0[4] ? e_0_op : e_1_op; // @[VDecode.scala 283:29 284:16 289:16]
- wire cmdqMux_5_st = d_1_io_cmdq_st; // @[VDecode.scala 221:{24,24}]
- wire _GEN_370 = ~marked0[4] ? cmdqMux_4_st : cmdqMux_5_st; // @[VDecode.scala 283:29 285:16 290:16]
- wire cmdqMux_5_ld = d_1_io_cmdq_ld; // @[VDecode.scala 221:{24,24}]
- wire _GEN_371 = ~marked0[4] ? cmdqMux_4_ld : cmdqMux_5_ld; // @[VDecode.scala 283:29 285:16 290:16]
- wire cmdqMux_5_ldst = d_1_io_cmdq_ldst; // @[VDecode.scala 221:{24,24}]
- wire _GEN_372 = ~marked0[4] ? cmdqMux_4_ldst : cmdqMux_5_ldst; // @[VDecode.scala 283:29 285:16 290:16]
- wire cmdqMux_5_conv = d_1_io_cmdq_conv; // @[VDecode.scala 221:{24,24}]
- wire _GEN_373 = ~marked0[4] ? cmdqMux_4_conv : cmdqMux_5_conv; // @[VDecode.scala 283:29 285:16 290:16]
- wire cmdqMux_5_alu = d_1_io_cmdq_alu; // @[VDecode.scala 221:{24,24}]
- wire _GEN_374 = ~marked0[4] ? cmdqMux_4_alu : cmdqMux_5_alu; // @[VDecode.scala 283:29 285:16 290:16]
- wire [63:0] w1_1 = d_1_io_actv_wactive & tag2; // @[VDecode.scala 212:35]
- wire [63:0] _w0_T_1 = ~tag2; // @[VDecode.scala 211:37]
- wire [63:0] w0_1 = d_1_io_actv_wactive & _w0_T_1; // @[VDecode.scala 211:35]
- wire [127:0] dactv_1_wactive = {w1_1,w0_1}; // @[Cat.scala 31:58]
- wire [127:0] _GEN_375 = ~marked0[4] ? dactv_0_wactive : dactv_1_wactive; // @[VDecode.scala 283:29 286:16 291:16]
- wire [63:0] dactv_1_ractive = d_1_io_actv_ractive; // @[VDecode.scala 209:19 213:22]
- wire [63:0] _GEN_376 = ~marked0[4] ? dactv_0_ractive : dactv_1_ractive; // @[VDecode.scala 283:29 286:16 291:16]
- wire [5:0] _GEN_377 = ~marked0[4] ? 6'h1f : 6'h3f; // @[VDecode.scala 283:29 287:13 292:13]
- wire [5:0] _GEN_419 = ~marked0[3] & valid_3 & _T_53 ? 6'hf : _GEN_377; // @[VDecode.scala 278:55 282:13]
- wire [5:0] _GEN_461 = ~marked0[2] & valid_2 & _T_50 ? 6'h7 : _GEN_419; // @[VDecode.scala 273:55 277:13]
- wire [5:0] marked1 = ~marked0[1] & valid_1 & _T_47 ? 6'h3 : _GEN_461; // @[VDecode.scala 268:48 272:13]
- wire e_2_cmdsync = d_2_io_out_cmdsync; // @[VDecode.scala 114:10 54:15]
- wire _GEN_504 = ~marked1[5] ? e_1_cmdsync : e_2_cmdsync; // @[VDecode.scala 310:29 311:16 316:16]
- wire [31:0] e_2_sv_data = d_2_io_out_sv_data; // @[VDecode.scala 114:10 54:15]
- wire [31:0] _GEN_505 = ~marked1[5] ? e_1_sv_data : e_2_sv_data; // @[VDecode.scala 310:29 311:16 316:16]
- wire [31:0] e_2_sv_addr = d_2_io_out_sv_addr; // @[VDecode.scala 114:10 54:15]
- wire [31:0] _GEN_506 = ~marked1[5] ? e_1_sv_addr : e_2_sv_addr; // @[VDecode.scala 310:29 311:16 316:16]
- wire e_2_sv_valid = d_2_io_out_sv_valid; // @[VDecode.scala 114:10 54:15]
- wire _GEN_507 = ~marked1[5] ? e_1_sv_valid : e_2_sv_valid; // @[VDecode.scala 310:29 311:16 316:16]
- wire [3:0] _GEN_508 = ~marked1[5] ? e_1_vz_r_tag_value_4_0 : e_2_vz_r_tag_value_4_0; // @[VDecode.scala 310:29 311:16 316:16]
- wire [5:0] e_2_vz_r_addr = d_2_io_out_vz_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_509 = ~marked1[5] ? e_1_vz_r_addr : e_2_vz_r_addr; // @[VDecode.scala 310:29 311:16 316:16]
- wire e_2_vz_r_valid = d_2_io_out_vz_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_510 = ~marked1[5] ? e_1_vz_r_valid : e_2_vz_r_valid; // @[VDecode.scala 310:29 311:16 316:16]
- wire [3:0] _GEN_511 = ~marked1[5] ? e_1_vy_r_tag_value_4_0 : e_2_vy_r_tag_value_4_0; // @[VDecode.scala 310:29 311:16 316:16]
- wire [5:0] e_2_vy_r_addr = d_2_io_out_vy_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_512 = ~marked1[5] ? e_1_vy_r_addr : e_2_vy_r_addr; // @[VDecode.scala 310:29 311:16 316:16]
- wire e_2_vy_r_valid = d_2_io_out_vy_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_513 = ~marked1[5] ? e_1_vy_r_valid : e_2_vy_r_valid; // @[VDecode.scala 310:29 311:16 316:16]
- wire [3:0] _GEN_514 = ~marked1[5] ? e_1_vx_r_tag_value_4_0 : e_2_vx_r_tag_value_4_0; // @[VDecode.scala 310:29 311:16 316:16]
- wire [5:0] e_2_vx_r_addr = d_2_io_out_vx_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_515 = ~marked1[5] ? e_1_vx_r_addr : e_2_vx_r_addr; // @[VDecode.scala 310:29 311:16 316:16]
- wire e_2_vx_r_valid = d_2_io_out_vx_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_516 = ~marked1[5] ? e_1_vx_r_valid : e_2_vx_r_valid; // @[VDecode.scala 310:29 311:16 316:16]
- wire [3:0] _GEN_517 = ~marked1[5] ? e_1_vu_r_tag_value_4_0 : e_2_vu_r_tag_value_4_0; // @[VDecode.scala 310:29 311:16 316:16]
- wire [5:0] e_2_vu_r_addr = d_2_io_out_vu_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_518 = ~marked1[5] ? e_1_vu_r_addr : e_2_vu_r_addr; // @[VDecode.scala 310:29 311:16 316:16]
- wire e_2_vu_r_valid = d_2_io_out_vu_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_519 = ~marked1[5] ? e_1_vu_r_valid : e_2_vu_r_valid; // @[VDecode.scala 310:29 311:16 316:16]
- wire [3:0] _GEN_520 = ~marked1[5] ? e_1_vt_r_tag_value_4_0 : e_2_vt_r_tag_value_4_0; // @[VDecode.scala 310:29 311:16 316:16]
- wire [5:0] e_2_vt_r_addr = d_2_io_out_vt_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_521 = ~marked1[5] ? e_1_vt_r_addr : e_2_vt_r_addr; // @[VDecode.scala 310:29 311:16 316:16]
- wire e_2_vt_r_valid = d_2_io_out_vt_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_522 = ~marked1[5] ? e_1_vt_r_valid : e_2_vt_r_valid; // @[VDecode.scala 310:29 311:16 316:16]
- wire [3:0] _GEN_523 = ~marked1[5] ? e_1_vs_r_tag_value_4_0 : e_2_vs_r_tag_value_4_0; // @[VDecode.scala 310:29 311:16 316:16]
- wire [5:0] e_2_vs_r_addr = d_2_io_out_vs_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_524 = ~marked1[5] ? e_1_vs_r_addr : e_2_vs_r_addr; // @[VDecode.scala 310:29 311:16 316:16]
- wire e_2_vs_r_valid = d_2_io_out_vs_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_525 = ~marked1[5] ? e_1_vs_r_valid : e_2_vs_r_valid; // @[VDecode.scala 310:29 311:16 316:16]
- wire [5:0] e_2_vg_addr = d_2_io_out_vg_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_526 = ~marked1[5] ? e_1_vg_addr : e_2_vg_addr; // @[VDecode.scala 310:29 311:16 316:16]
- wire [5:0] e_2_vf_addr = d_2_io_out_vf_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_528 = ~marked1[5] ? e_1_vf_addr : e_2_vf_addr; // @[VDecode.scala 310:29 311:16 316:16]
- wire [5:0] e_2_ve_addr = d_2_io_out_ve_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_530 = ~marked1[5] ? e_1_ve_addr : e_2_ve_addr; // @[VDecode.scala 310:29 311:16 316:16]
- wire [5:0] e_2_vd_addr = d_2_io_out_vd_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_532 = ~marked1[5] ? e_1_vd_addr : e_2_vd_addr; // @[VDecode.scala 310:29 311:16 316:16]
- wire e_2_vd_valid = d_2_io_out_vd_valid; // @[VDecode.scala 114:10 54:15]
- wire _GEN_533 = ~marked1[5] ? e_1_vd_valid : e_2_vd_valid; // @[VDecode.scala 310:29 311:16 316:16]
- wire e_2_m = d_2_io_out_m; // @[VDecode.scala 114:10 54:15]
- wire _GEN_534 = ~marked1[5] ? e_1_m : e_2_m; // @[VDecode.scala 310:29 311:16 316:16]
- wire [2:0] e_2_sz = d_2_io_out_sz; // @[VDecode.scala 114:10 54:15]
- wire [2:0] _GEN_535 = ~marked1[5] ? e_1_sz : e_2_sz; // @[VDecode.scala 310:29 311:16 316:16]
- wire [2:0] e_2_f2 = d_2_io_out_f2; // @[VDecode.scala 114:10 54:15]
- wire [2:0] _GEN_536 = ~marked1[5] ? e_1_f2 : e_2_f2; // @[VDecode.scala 310:29 311:16 316:16]
- wire [6:0] e_2_op = d_2_io_out_op; // @[VDecode.scala 114:10 54:15]
- wire [6:0] _GEN_537 = ~marked1[5] ? e_1_op : e_2_op; // @[VDecode.scala 310:29 311:16 316:16]
- wire cmdqMux_6_st = d_2_io_cmdq_st; // @[VDecode.scala 221:{24,24}]
- wire _GEN_538 = ~marked1[5] ? cmdqMux_5_st : cmdqMux_6_st; // @[VDecode.scala 310:29 312:16 317:16]
- wire cmdqMux_6_ld = d_2_io_cmdq_ld; // @[VDecode.scala 221:{24,24}]
- wire _GEN_539 = ~marked1[5] ? cmdqMux_5_ld : cmdqMux_6_ld; // @[VDecode.scala 310:29 312:16 317:16]
- wire cmdqMux_6_ldst = d_2_io_cmdq_ldst; // @[VDecode.scala 221:{24,24}]
- wire _GEN_540 = ~marked1[5] ? cmdqMux_5_ldst : cmdqMux_6_ldst; // @[VDecode.scala 310:29 312:16 317:16]
- wire cmdqMux_6_conv = d_2_io_cmdq_conv; // @[VDecode.scala 221:{24,24}]
- wire _GEN_541 = ~marked1[5] ? cmdqMux_5_conv : cmdqMux_6_conv; // @[VDecode.scala 310:29 312:16 317:16]
- wire cmdqMux_6_alu = d_2_io_cmdq_alu; // @[VDecode.scala 221:{24,24}]
- wire _GEN_542 = ~marked1[5] ? cmdqMux_5_alu : cmdqMux_6_alu; // @[VDecode.scala 310:29 312:16 317:16]
- wire [63:0] w1_2 = d_2_io_actv_wactive & tag3; // @[VDecode.scala 212:35]
- wire [63:0] _w0_T_2 = ~tag3; // @[VDecode.scala 211:37]
- wire [63:0] w0_2 = d_2_io_actv_wactive & _w0_T_2; // @[VDecode.scala 211:35]
- wire [127:0] dactv_2_wactive = {w1_2,w0_2}; // @[Cat.scala 31:58]
- wire [127:0] _GEN_543 = ~marked1[5] ? dactv_1_wactive : dactv_2_wactive; // @[VDecode.scala 310:29 313:16 318:16]
- wire [63:0] dactv_2_ractive = d_2_io_actv_ractive; // @[VDecode.scala 209:19 213:22]
- wire [63:0] _GEN_544 = ~marked1[5] ? dactv_1_ractive : dactv_2_ractive; // @[VDecode.scala 310:29 313:16 318:16]
- wire [6:0] _GEN_545 = ~marked1[5] ? 7'h3f : 7'h7f; // @[VDecode.scala 310:29 314:13 319:13]
- wire [6:0] _GEN_587 = ~marked1[4] ? 7'h1f : _GEN_545; // @[VDecode.scala 305:29 309:13]
- wire [6:0] _GEN_629 = ~marked1[3] & valid_3 & _T_53 ? 7'hf : _GEN_587; // @[VDecode.scala 300:55 304:13]
- wire [6:0] marked2 = ~marked1[2] & valid_2 & _T_50 ? 7'h7 : _GEN_629; // @[VDecode.scala 295:48 299:13]
- wire e_3_cmdsync = d_3_io_out_cmdsync; // @[VDecode.scala 114:10 54:15]
- wire _GEN_672 = ~marked2[6] ? e_2_cmdsync : e_3_cmdsync; // @[VDecode.scala 334:29 335:16 339:16]
- wire [31:0] e_3_sv_data = d_3_io_out_sv_data; // @[VDecode.scala 114:10 54:15]
- wire [31:0] _GEN_673 = ~marked2[6] ? e_2_sv_data : e_3_sv_data; // @[VDecode.scala 334:29 335:16 339:16]
- wire [31:0] e_3_sv_addr = d_3_io_out_sv_addr; // @[VDecode.scala 114:10 54:15]
- wire [31:0] _GEN_674 = ~marked2[6] ? e_2_sv_addr : e_3_sv_addr; // @[VDecode.scala 334:29 335:16 339:16]
- wire e_3_sv_valid = d_3_io_out_sv_valid; // @[VDecode.scala 114:10 54:15]
- wire _GEN_675 = ~marked2[6] ? e_2_sv_valid : e_3_sv_valid; // @[VDecode.scala 334:29 335:16 339:16]
- wire [3:0] _GEN_676 = ~marked2[6] ? e_2_vz_r_tag_value_4_0 : e_3_vz_r_tag_value_4_0; // @[VDecode.scala 334:29 335:16 339:16]
- wire [5:0] e_3_vz_r_addr = d_3_io_out_vz_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_677 = ~marked2[6] ? e_2_vz_r_addr : e_3_vz_r_addr; // @[VDecode.scala 334:29 335:16 339:16]
- wire e_3_vz_r_valid = d_3_io_out_vz_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_678 = ~marked2[6] ? e_2_vz_r_valid : e_3_vz_r_valid; // @[VDecode.scala 334:29 335:16 339:16]
- wire [3:0] _GEN_679 = ~marked2[6] ? e_2_vy_r_tag_value_4_0 : e_3_vy_r_tag_value_4_0; // @[VDecode.scala 334:29 335:16 339:16]
- wire [5:0] e_3_vy_r_addr = d_3_io_out_vy_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_680 = ~marked2[6] ? e_2_vy_r_addr : e_3_vy_r_addr; // @[VDecode.scala 334:29 335:16 339:16]
- wire e_3_vy_r_valid = d_3_io_out_vy_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_681 = ~marked2[6] ? e_2_vy_r_valid : e_3_vy_r_valid; // @[VDecode.scala 334:29 335:16 339:16]
- wire [3:0] _GEN_682 = ~marked2[6] ? e_2_vx_r_tag_value_4_0 : e_3_vx_r_tag_value_4_0; // @[VDecode.scala 334:29 335:16 339:16]
- wire [5:0] e_3_vx_r_addr = d_3_io_out_vx_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_683 = ~marked2[6] ? e_2_vx_r_addr : e_3_vx_r_addr; // @[VDecode.scala 334:29 335:16 339:16]
- wire e_3_vx_r_valid = d_3_io_out_vx_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_684 = ~marked2[6] ? e_2_vx_r_valid : e_3_vx_r_valid; // @[VDecode.scala 334:29 335:16 339:16]
- wire [3:0] _GEN_685 = ~marked2[6] ? e_2_vu_r_tag_value_4_0 : e_3_vu_r_tag_value_4_0; // @[VDecode.scala 334:29 335:16 339:16]
- wire [5:0] e_3_vu_r_addr = d_3_io_out_vu_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_686 = ~marked2[6] ? e_2_vu_r_addr : e_3_vu_r_addr; // @[VDecode.scala 334:29 335:16 339:16]
- wire e_3_vu_r_valid = d_3_io_out_vu_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_687 = ~marked2[6] ? e_2_vu_r_valid : e_3_vu_r_valid; // @[VDecode.scala 334:29 335:16 339:16]
- wire [3:0] _GEN_688 = ~marked2[6] ? e_2_vt_r_tag_value_4_0 : e_3_vt_r_tag_value_4_0; // @[VDecode.scala 334:29 335:16 339:16]
- wire [5:0] e_3_vt_r_addr = d_3_io_out_vt_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_689 = ~marked2[6] ? e_2_vt_r_addr : e_3_vt_r_addr; // @[VDecode.scala 334:29 335:16 339:16]
- wire e_3_vt_r_valid = d_3_io_out_vt_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_690 = ~marked2[6] ? e_2_vt_r_valid : e_3_vt_r_valid; // @[VDecode.scala 334:29 335:16 339:16]
- wire [3:0] _GEN_691 = ~marked2[6] ? e_2_vs_r_tag_value_4_0 : e_3_vs_r_tag_value_4_0; // @[VDecode.scala 334:29 335:16 339:16]
- wire [5:0] e_3_vs_r_addr = d_3_io_out_vs_addr; // @[VDecode.scala 106:17 108:12]
- wire [5:0] _GEN_692 = ~marked2[6] ? e_2_vs_r_addr : e_3_vs_r_addr; // @[VDecode.scala 334:29 335:16 339:16]
- wire e_3_vs_r_valid = d_3_io_out_vs_valid; // @[VDecode.scala 106:17 107:13]
- wire _GEN_693 = ~marked2[6] ? e_2_vs_r_valid : e_3_vs_r_valid; // @[VDecode.scala 334:29 335:16 339:16]
- wire [5:0] e_3_vg_addr = d_3_io_out_vg_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_694 = ~marked2[6] ? e_2_vg_addr : e_3_vg_addr; // @[VDecode.scala 334:29 335:16 339:16]
- wire [5:0] e_3_vf_addr = d_3_io_out_vf_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_696 = ~marked2[6] ? e_2_vf_addr : e_3_vf_addr; // @[VDecode.scala 334:29 335:16 339:16]
- wire [5:0] e_3_ve_addr = d_3_io_out_ve_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_698 = ~marked2[6] ? e_2_ve_addr : e_3_ve_addr; // @[VDecode.scala 334:29 335:16 339:16]
- wire [5:0] e_3_vd_addr = d_3_io_out_vd_addr; // @[VDecode.scala 114:10 54:15]
- wire [5:0] _GEN_700 = ~marked2[6] ? e_2_vd_addr : e_3_vd_addr; // @[VDecode.scala 334:29 335:16 339:16]
- wire e_3_vd_valid = d_3_io_out_vd_valid; // @[VDecode.scala 114:10 54:15]
- wire _GEN_701 = ~marked2[6] ? e_2_vd_valid : e_3_vd_valid; // @[VDecode.scala 334:29 335:16 339:16]
- wire e_3_m = d_3_io_out_m; // @[VDecode.scala 114:10 54:15]
- wire _GEN_702 = ~marked2[6] ? e_2_m : e_3_m; // @[VDecode.scala 334:29 335:16 339:16]
- wire [2:0] e_3_sz = d_3_io_out_sz; // @[VDecode.scala 114:10 54:15]
- wire [2:0] _GEN_703 = ~marked2[6] ? e_2_sz : e_3_sz; // @[VDecode.scala 334:29 335:16 339:16]
- wire [2:0] e_3_f2 = d_3_io_out_f2; // @[VDecode.scala 114:10 54:15]
- wire [2:0] _GEN_704 = ~marked2[6] ? e_2_f2 : e_3_f2; // @[VDecode.scala 334:29 335:16 339:16]
- wire [6:0] e_3_op = d_3_io_out_op; // @[VDecode.scala 114:10 54:15]
- wire [6:0] _GEN_705 = ~marked2[6] ? e_2_op : e_3_op; // @[VDecode.scala 334:29 335:16 339:16]
- wire cmdqMux_7_st = d_3_io_cmdq_st; // @[VDecode.scala 221:{24,24}]
- wire _GEN_706 = ~marked2[6] ? cmdqMux_6_st : cmdqMux_7_st; // @[VDecode.scala 334:29 336:16 340:16]
- wire cmdqMux_7_ld = d_3_io_cmdq_ld; // @[VDecode.scala 221:{24,24}]
- wire _GEN_707 = ~marked2[6] ? cmdqMux_6_ld : cmdqMux_7_ld; // @[VDecode.scala 334:29 336:16 340:16]
- wire cmdqMux_7_ldst = d_3_io_cmdq_ldst; // @[VDecode.scala 221:{24,24}]
- wire _GEN_708 = ~marked2[6] ? cmdqMux_6_ldst : cmdqMux_7_ldst; // @[VDecode.scala 334:29 336:16 340:16]
- wire cmdqMux_7_conv = d_3_io_cmdq_conv; // @[VDecode.scala 221:{24,24}]
- wire _GEN_709 = ~marked2[6] ? cmdqMux_6_conv : cmdqMux_7_conv; // @[VDecode.scala 334:29 336:16 340:16]
- wire cmdqMux_7_alu = d_3_io_cmdq_alu; // @[VDecode.scala 221:{24,24}]
- wire _GEN_710 = ~marked2[6] ? cmdqMux_6_alu : cmdqMux_7_alu; // @[VDecode.scala 334:29 336:16 340:16]
- wire [63:0] w1_3 = d_3_io_actv_wactive & tag4; // @[VDecode.scala 212:35]
- wire [63:0] _w0_T_3 = ~tag4; // @[VDecode.scala 211:37]
- wire [63:0] w0_3 = d_3_io_actv_wactive & _w0_T_3; // @[VDecode.scala 211:35]
- wire [127:0] dactv_3_wactive = {w1_3,w0_3}; // @[Cat.scala 31:58]
- wire [127:0] _GEN_711 = ~marked2[6] ? dactv_2_wactive : dactv_3_wactive; // @[VDecode.scala 334:29 337:16 341:16]
- wire [63:0] dactv_3_ractive = d_3_io_actv_ractive; // @[VDecode.scala 209:19 213:22]
- wire [63:0] _GEN_712 = ~marked2[6] ? dactv_2_ractive : dactv_3_ractive; // @[VDecode.scala 334:29 337:16 341:16]
- wire [5:0] _GEN_837 = {{1'd0}, marked0}; // @[VDecode.scala 232:19]
- wire [5:0] _T_28 = marked1 & _GEN_837; // @[VDecode.scala 232:19]
- wire [6:0] _GEN_839 = {{2'd0}, marked0}; // @[VDecode.scala 233:19]
- wire [6:0] _T_33 = marked2 & _GEN_839; // @[VDecode.scala 233:19]
- wire [6:0] _GEN_841 = {{1'd0}, marked1}; // @[VDecode.scala 234:19]
- wire [6:0] _T_38 = marked2 & _GEN_841; // @[VDecode.scala 234:19]
- wire [127:0] _io_vrfsb_set_bits_T_1 = output_[0] ? actv2_0_wactive : 128'h0; // @[Library.scala 32:8]
- wire [127:0] _io_vrfsb_set_bits_T_3 = output_[1] ? actv2_1_wactive : 128'h0; // @[Library.scala 32:8]
- wire [127:0] _io_vrfsb_set_bits_T_4 = _io_vrfsb_set_bits_T_1 | _io_vrfsb_set_bits_T_3; // @[VDecode.scala 348:60]
- wire [127:0] _io_vrfsb_set_bits_T_6 = output_[2] ? actv2_2_wactive : 128'h0; // @[Library.scala 32:8]
- wire [127:0] _io_vrfsb_set_bits_T_7 = _io_vrfsb_set_bits_T_4 | _io_vrfsb_set_bits_T_6; // @[VDecode.scala 349:60]
- wire [127:0] _io_vrfsb_set_bits_T_9 = output_[3] ? actv2_3_wactive : 128'h0; // @[Library.scala 32:8]
- wire [63:0] _T_105 = io_vrfsb_set_bits[63:0] & io_vrfsb_set_bits[127:64]; // @[VDecode.scala 353:36]
- wire [63:0] _T_115 = io_vrfsb_set_bits[63:0] | io_vrfsb_set_bits[127:64]; // @[VDecode.scala 354:87]
- wire [63:0] _T_116 = _wactive0_T_2 & _T_115; // @[VDecode.scala 354:59]
- wire outvalid_0 = valid_0 & ~depends_0; // @[VDecode.scala 362:29]
- wire outvalid_1 = valid_1 & ~depends_1; // @[VDecode.scala 362:29]
- wire outvalid_2 = valid_2 & ~depends_2; // @[VDecode.scala 362:29]
- wire outvalid_3 = valid_3 & ~depends_3; // @[VDecode.scala 362:29]
- wire [3:0] _ordered_T = {outvalid_3,outvalid_2,outvalid_1,outvalid_0}; // @[VDecode.scala 370:30]
- wire [1:0] _ordered_T_5 = ~_ordered_T[1:0]; // @[VDecode.scala 370:20]
- wire [2:0] _ordered_T_8 = ~_ordered_T[2:0]; // @[VDecode.scala 370:20]
- wire [3:0] _ordered_T_11 = ~_ordered_T; // @[VDecode.scala 370:20]
- reg nempty; // @[VDecode.scala 384:23]
- Fifo4x4 f ( // @[Fifo4x4.scala 22:11]
- .clock(f_clock),
- .reset(f_reset),
- .io_in_ready(f_io_in_ready),
- .io_in_valid(f_io_in_valid),
- .io_in_bits_0_valid(f_io_in_bits_0_valid),
- .io_in_bits_0_bits_inst(f_io_in_bits_0_bits_inst),
- .io_in_bits_0_bits_addr(f_io_in_bits_0_bits_addr),
- .io_in_bits_0_bits_data(f_io_in_bits_0_bits_data),
- .io_in_bits_1_valid(f_io_in_bits_1_valid),
- .io_in_bits_1_bits_inst(f_io_in_bits_1_bits_inst),
- .io_in_bits_1_bits_addr(f_io_in_bits_1_bits_addr),
- .io_in_bits_1_bits_data(f_io_in_bits_1_bits_data),
- .io_in_bits_2_valid(f_io_in_bits_2_valid),
- .io_in_bits_2_bits_inst(f_io_in_bits_2_bits_inst),
- .io_in_bits_2_bits_addr(f_io_in_bits_2_bits_addr),
- .io_in_bits_2_bits_data(f_io_in_bits_2_bits_data),
- .io_in_bits_3_valid(f_io_in_bits_3_valid),
- .io_in_bits_3_bits_inst(f_io_in_bits_3_bits_inst),
- .io_in_bits_3_bits_addr(f_io_in_bits_3_bits_addr),
- .io_in_bits_3_bits_data(f_io_in_bits_3_bits_data),
- .io_out_0_ready(f_io_out_0_ready),
- .io_out_0_valid(f_io_out_0_valid),
- .io_out_0_bits_inst(f_io_out_0_bits_inst),
- .io_out_0_bits_addr(f_io_out_0_bits_addr),
- .io_out_0_bits_data(f_io_out_0_bits_data),
- .io_out_1_ready(f_io_out_1_ready),
- .io_out_1_valid(f_io_out_1_valid),
- .io_out_1_bits_inst(f_io_out_1_bits_inst),
- .io_out_1_bits_addr(f_io_out_1_bits_addr),
- .io_out_1_bits_data(f_io_out_1_bits_data),
- .io_out_2_ready(f_io_out_2_ready),
- .io_out_2_valid(f_io_out_2_valid),
- .io_out_2_bits_inst(f_io_out_2_bits_inst),
- .io_out_2_bits_addr(f_io_out_2_bits_addr),
- .io_out_2_bits_data(f_io_out_2_bits_data),
- .io_out_3_ready(f_io_out_3_ready),
- .io_out_3_valid(f_io_out_3_valid),
- .io_out_3_bits_inst(f_io_out_3_bits_inst),
- .io_out_3_bits_addr(f_io_out_3_bits_addr),
- .io_out_3_bits_data(f_io_out_3_bits_data),
- .io_count(f_io_count),
- .io_nempty(f_io_nempty)
- );
- VDecodeInstruction d_0 ( // @[VDecode.scala 49:21]
- .clock(d_0_clock),
- .reset(d_0_reset),
- .io_in_inst(d_0_io_in_inst),
- .io_in_addr(d_0_io_in_addr),
- .io_in_data(d_0_io_in_data),
- .io_out_op(d_0_io_out_op),
- .io_out_f2(d_0_io_out_f2),
- .io_out_sz(d_0_io_out_sz),
- .io_out_m(d_0_io_out_m),
- .io_out_vd_valid(d_0_io_out_vd_valid),
- .io_out_vd_addr(d_0_io_out_vd_addr),
- .io_out_ve_addr(d_0_io_out_ve_addr),
- .io_out_vf_addr(d_0_io_out_vf_addr),
- .io_out_vg_addr(d_0_io_out_vg_addr),
- .io_out_vs_valid(d_0_io_out_vs_valid),
- .io_out_vs_addr(d_0_io_out_vs_addr),
- .io_out_vt_valid(d_0_io_out_vt_valid),
- .io_out_vt_addr(d_0_io_out_vt_addr),
- .io_out_vu_valid(d_0_io_out_vu_valid),
- .io_out_vu_addr(d_0_io_out_vu_addr),
- .io_out_vx_valid(d_0_io_out_vx_valid),
- .io_out_vx_addr(d_0_io_out_vx_addr),
- .io_out_vy_valid(d_0_io_out_vy_valid),
- .io_out_vy_addr(d_0_io_out_vy_addr),
- .io_out_vz_valid(d_0_io_out_vz_valid),
- .io_out_vz_addr(d_0_io_out_vz_addr),
- .io_out_sv_valid(d_0_io_out_sv_valid),
- .io_out_sv_addr(d_0_io_out_sv_addr),
- .io_out_sv_data(d_0_io_out_sv_data),
- .io_out_cmdsync(d_0_io_out_cmdsync),
- .io_cmdq_alu(d_0_io_cmdq_alu),
- .io_cmdq_conv(d_0_io_cmdq_conv),
- .io_cmdq_ldst(d_0_io_cmdq_ldst),
- .io_cmdq_ld(d_0_io_cmdq_ld),
- .io_cmdq_st(d_0_io_cmdq_st),
- .io_actv_ractive(d_0_io_actv_ractive),
- .io_actv_wactive(d_0_io_actv_wactive),
- .io_undef(d_0_io_undef)
- );
- VDecodeInstruction d_1 ( // @[VDecode.scala 50:21]
- .clock(d_1_clock),
- .reset(d_1_reset),
- .io_in_inst(d_1_io_in_inst),
- .io_in_addr(d_1_io_in_addr),
- .io_in_data(d_1_io_in_data),
- .io_out_op(d_1_io_out_op),
- .io_out_f2(d_1_io_out_f2),
- .io_out_sz(d_1_io_out_sz),
- .io_out_m(d_1_io_out_m),
- .io_out_vd_valid(d_1_io_out_vd_valid),
- .io_out_vd_addr(d_1_io_out_vd_addr),
- .io_out_ve_addr(d_1_io_out_ve_addr),
- .io_out_vf_addr(d_1_io_out_vf_addr),
- .io_out_vg_addr(d_1_io_out_vg_addr),
- .io_out_vs_valid(d_1_io_out_vs_valid),
- .io_out_vs_addr(d_1_io_out_vs_addr),
- .io_out_vt_valid(d_1_io_out_vt_valid),
- .io_out_vt_addr(d_1_io_out_vt_addr),
- .io_out_vu_valid(d_1_io_out_vu_valid),
- .io_out_vu_addr(d_1_io_out_vu_addr),
- .io_out_vx_valid(d_1_io_out_vx_valid),
- .io_out_vx_addr(d_1_io_out_vx_addr),
- .io_out_vy_valid(d_1_io_out_vy_valid),
- .io_out_vy_addr(d_1_io_out_vy_addr),
- .io_out_vz_valid(d_1_io_out_vz_valid),
- .io_out_vz_addr(d_1_io_out_vz_addr),
- .io_out_sv_valid(d_1_io_out_sv_valid),
- .io_out_sv_addr(d_1_io_out_sv_addr),
- .io_out_sv_data(d_1_io_out_sv_data),
- .io_out_cmdsync(d_1_io_out_cmdsync),
- .io_cmdq_alu(d_1_io_cmdq_alu),
- .io_cmdq_conv(d_1_io_cmdq_conv),
- .io_cmdq_ldst(d_1_io_cmdq_ldst),
- .io_cmdq_ld(d_1_io_cmdq_ld),
- .io_cmdq_st(d_1_io_cmdq_st),
- .io_actv_ractive(d_1_io_actv_ractive),
- .io_actv_wactive(d_1_io_actv_wactive),
- .io_undef(d_1_io_undef)
- );
- VDecodeInstruction d_2 ( // @[VDecode.scala 51:21]
- .clock(d_2_clock),
- .reset(d_2_reset),
- .io_in_inst(d_2_io_in_inst),
- .io_in_addr(d_2_io_in_addr),
- .io_in_data(d_2_io_in_data),
- .io_out_op(d_2_io_out_op),
- .io_out_f2(d_2_io_out_f2),
- .io_out_sz(d_2_io_out_sz),
- .io_out_m(d_2_io_out_m),
- .io_out_vd_valid(d_2_io_out_vd_valid),
- .io_out_vd_addr(d_2_io_out_vd_addr),
- .io_out_ve_addr(d_2_io_out_ve_addr),
- .io_out_vf_addr(d_2_io_out_vf_addr),
- .io_out_vg_addr(d_2_io_out_vg_addr),
- .io_out_vs_valid(d_2_io_out_vs_valid),
- .io_out_vs_addr(d_2_io_out_vs_addr),
- .io_out_vt_valid(d_2_io_out_vt_valid),
- .io_out_vt_addr(d_2_io_out_vt_addr),
- .io_out_vu_valid(d_2_io_out_vu_valid),
- .io_out_vu_addr(d_2_io_out_vu_addr),
- .io_out_vx_valid(d_2_io_out_vx_valid),
- .io_out_vx_addr(d_2_io_out_vx_addr),
- .io_out_vy_valid(d_2_io_out_vy_valid),
- .io_out_vy_addr(d_2_io_out_vy_addr),
- .io_out_vz_valid(d_2_io_out_vz_valid),
- .io_out_vz_addr(d_2_io_out_vz_addr),
- .io_out_sv_valid(d_2_io_out_sv_valid),
- .io_out_sv_addr(d_2_io_out_sv_addr),
- .io_out_sv_data(d_2_io_out_sv_data),
- .io_out_cmdsync(d_2_io_out_cmdsync),
- .io_cmdq_alu(d_2_io_cmdq_alu),
- .io_cmdq_conv(d_2_io_cmdq_conv),
- .io_cmdq_ldst(d_2_io_cmdq_ldst),
- .io_cmdq_ld(d_2_io_cmdq_ld),
- .io_cmdq_st(d_2_io_cmdq_st),
- .io_actv_ractive(d_2_io_actv_ractive),
- .io_actv_wactive(d_2_io_actv_wactive),
- .io_undef(d_2_io_undef)
- );
- VDecodeInstruction d_3 ( // @[VDecode.scala 52:21]
- .clock(d_3_clock),
- .reset(d_3_reset),
- .io_in_inst(d_3_io_in_inst),
- .io_in_addr(d_3_io_in_addr),
- .io_in_data(d_3_io_in_data),
- .io_out_op(d_3_io_out_op),
- .io_out_f2(d_3_io_out_f2),
- .io_out_sz(d_3_io_out_sz),
- .io_out_m(d_3_io_out_m),
- .io_out_vd_valid(d_3_io_out_vd_valid),
- .io_out_vd_addr(d_3_io_out_vd_addr),
- .io_out_ve_addr(d_3_io_out_ve_addr),
- .io_out_vf_addr(d_3_io_out_vf_addr),
- .io_out_vg_addr(d_3_io_out_vg_addr),
- .io_out_vs_valid(d_3_io_out_vs_valid),
- .io_out_vs_addr(d_3_io_out_vs_addr),
- .io_out_vt_valid(d_3_io_out_vt_valid),
- .io_out_vt_addr(d_3_io_out_vt_addr),
- .io_out_vu_valid(d_3_io_out_vu_valid),
- .io_out_vu_addr(d_3_io_out_vu_addr),
- .io_out_vx_valid(d_3_io_out_vx_valid),
- .io_out_vx_addr(d_3_io_out_vx_addr),
- .io_out_vy_valid(d_3_io_out_vy_valid),
- .io_out_vy_addr(d_3_io_out_vy_addr),
- .io_out_vz_valid(d_3_io_out_vz_valid),
- .io_out_vz_addr(d_3_io_out_vz_addr),
- .io_out_sv_valid(d_3_io_out_sv_valid),
- .io_out_sv_addr(d_3_io_out_sv_addr),
- .io_out_sv_data(d_3_io_out_sv_data),
- .io_out_cmdsync(d_3_io_out_cmdsync),
- .io_cmdq_alu(d_3_io_cmdq_alu),
- .io_cmdq_conv(d_3_io_cmdq_conv),
- .io_cmdq_ldst(d_3_io_cmdq_ldst),
- .io_cmdq_ld(d_3_io_cmdq_ld),
- .io_cmdq_st(d_3_io_cmdq_st),
- .io_actv_ractive(d_3_io_actv_ractive),
- .io_actv_wactive(d_3_io_actv_wactive),
- .io_undef(d_3_io_undef)
- );
- assign io_in_ready = f_io_in_ready; // @[VDecode.scala 129:11]
- assign io_out_0_valid = ~(~_ordered_T[0]); // @[VDecode.scala 370:43]
- assign io_out_0_bits_op = data_0_op; // @[VDecode.scala 377:20]
- assign io_out_0_bits_f2 = data_0_f2; // @[VDecode.scala 377:20]
- assign io_out_0_bits_sz = data_0_sz; // @[VDecode.scala 377:20]
- assign io_out_0_bits_m = data_0_m; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vd_valid = data_0_vd_valid; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vd_addr = data_0_vd_addr; // @[VDecode.scala 377:20]
- assign io_out_0_bits_ve_addr = data_0_ve_addr; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vf_addr = data_0_vf_addr; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vg_addr = data_0_vg_addr; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vs_valid = data_0_vs_valid; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vs_addr = data_0_vs_addr; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vs_tag = data_0_vs_tag; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vt_valid = data_0_vt_valid; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vt_addr = data_0_vt_addr; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vt_tag = data_0_vt_tag; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vu_valid = data_0_vu_valid; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vu_addr = data_0_vu_addr; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vu_tag = data_0_vu_tag; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vx_valid = data_0_vx_valid; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vx_addr = data_0_vx_addr; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vx_tag = data_0_vx_tag; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vy_valid = data_0_vy_valid; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vy_addr = data_0_vy_addr; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vy_tag = data_0_vy_tag; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vz_valid = data_0_vz_valid; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vz_addr = data_0_vz_addr; // @[VDecode.scala 377:20]
- assign io_out_0_bits_vz_tag = data_0_vz_tag; // @[VDecode.scala 377:20]
- assign io_out_0_bits_sv_valid = data_0_sv_valid; // @[VDecode.scala 377:20]
- assign io_out_0_bits_sv_addr = data_0_sv_addr; // @[VDecode.scala 377:20]
- assign io_out_0_bits_sv_data = data_0_sv_data; // @[VDecode.scala 377:20]
- assign io_out_0_bits_cmdsync = data_0_cmdsync; // @[VDecode.scala 377:20]
- assign io_out_1_valid = _ordered_T_5 == 2'h0; // @[VDecode.scala 370:43]
- assign io_out_1_bits_op = data_1_op; // @[VDecode.scala 377:20]
- assign io_out_1_bits_f2 = data_1_f2; // @[VDecode.scala 377:20]
- assign io_out_1_bits_sz = data_1_sz; // @[VDecode.scala 377:20]
- assign io_out_1_bits_m = data_1_m; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vd_valid = data_1_vd_valid; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vd_addr = data_1_vd_addr; // @[VDecode.scala 377:20]
- assign io_out_1_bits_ve_addr = data_1_ve_addr; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vf_addr = data_1_vf_addr; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vg_addr = data_1_vg_addr; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vs_valid = data_1_vs_valid; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vs_addr = data_1_vs_addr; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vs_tag = data_1_vs_tag; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vt_valid = data_1_vt_valid; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vt_addr = data_1_vt_addr; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vt_tag = data_1_vt_tag; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vu_valid = data_1_vu_valid; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vu_addr = data_1_vu_addr; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vu_tag = data_1_vu_tag; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vx_valid = data_1_vx_valid; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vx_addr = data_1_vx_addr; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vx_tag = data_1_vx_tag; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vy_valid = data_1_vy_valid; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vy_addr = data_1_vy_addr; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vy_tag = data_1_vy_tag; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vz_valid = data_1_vz_valid; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vz_addr = data_1_vz_addr; // @[VDecode.scala 377:20]
- assign io_out_1_bits_vz_tag = data_1_vz_tag; // @[VDecode.scala 377:20]
- assign io_out_1_bits_sv_valid = data_1_sv_valid; // @[VDecode.scala 377:20]
- assign io_out_1_bits_sv_addr = data_1_sv_addr; // @[VDecode.scala 377:20]
- assign io_out_1_bits_sv_data = data_1_sv_data; // @[VDecode.scala 377:20]
- assign io_out_1_bits_cmdsync = data_1_cmdsync; // @[VDecode.scala 377:20]
- assign io_out_2_valid = _ordered_T_8 == 3'h0; // @[VDecode.scala 370:43]
- assign io_out_2_bits_op = data_2_op; // @[VDecode.scala 377:20]
- assign io_out_2_bits_f2 = data_2_f2; // @[VDecode.scala 377:20]
- assign io_out_2_bits_sz = data_2_sz; // @[VDecode.scala 377:20]
- assign io_out_2_bits_m = data_2_m; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vd_valid = data_2_vd_valid; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vd_addr = data_2_vd_addr; // @[VDecode.scala 377:20]
- assign io_out_2_bits_ve_addr = data_2_ve_addr; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vf_addr = data_2_vf_addr; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vg_addr = data_2_vg_addr; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vs_valid = data_2_vs_valid; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vs_addr = data_2_vs_addr; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vs_tag = data_2_vs_tag; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vt_valid = data_2_vt_valid; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vt_addr = data_2_vt_addr; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vt_tag = data_2_vt_tag; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vu_valid = data_2_vu_valid; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vu_addr = data_2_vu_addr; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vu_tag = data_2_vu_tag; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vx_valid = data_2_vx_valid; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vx_addr = data_2_vx_addr; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vx_tag = data_2_vx_tag; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vy_valid = data_2_vy_valid; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vy_addr = data_2_vy_addr; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vy_tag = data_2_vy_tag; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vz_valid = data_2_vz_valid; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vz_addr = data_2_vz_addr; // @[VDecode.scala 377:20]
- assign io_out_2_bits_vz_tag = data_2_vz_tag; // @[VDecode.scala 377:20]
- assign io_out_2_bits_sv_valid = data_2_sv_valid; // @[VDecode.scala 377:20]
- assign io_out_2_bits_sv_addr = data_2_sv_addr; // @[VDecode.scala 377:20]
- assign io_out_2_bits_sv_data = data_2_sv_data; // @[VDecode.scala 377:20]
- assign io_out_2_bits_cmdsync = data_2_cmdsync; // @[VDecode.scala 377:20]
- assign io_out_3_valid = _ordered_T_11 == 4'h0; // @[VDecode.scala 370:43]
- assign io_out_3_bits_op = data_3_op; // @[VDecode.scala 377:20]
- assign io_out_3_bits_f2 = data_3_f2; // @[VDecode.scala 377:20]
- assign io_out_3_bits_sz = data_3_sz; // @[VDecode.scala 377:20]
- assign io_out_3_bits_m = data_3_m; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vd_valid = data_3_vd_valid; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vd_addr = data_3_vd_addr; // @[VDecode.scala 377:20]
- assign io_out_3_bits_ve_addr = data_3_ve_addr; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vf_addr = data_3_vf_addr; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vg_addr = data_3_vg_addr; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vs_valid = data_3_vs_valid; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vs_addr = data_3_vs_addr; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vs_tag = data_3_vs_tag; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vt_valid = data_3_vt_valid; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vt_addr = data_3_vt_addr; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vt_tag = data_3_vt_tag; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vu_valid = data_3_vu_valid; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vu_addr = data_3_vu_addr; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vu_tag = data_3_vu_tag; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vx_valid = data_3_vx_valid; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vx_addr = data_3_vx_addr; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vx_tag = data_3_vx_tag; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vy_valid = data_3_vy_valid; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vy_addr = data_3_vy_addr; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vy_tag = data_3_vy_tag; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vz_valid = data_3_vz_valid; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vz_addr = data_3_vz_addr; // @[VDecode.scala 377:20]
- assign io_out_3_bits_vz_tag = data_3_vz_tag; // @[VDecode.scala 377:20]
- assign io_out_3_bits_sv_valid = data_3_sv_valid; // @[VDecode.scala 377:20]
- assign io_out_3_bits_sv_addr = data_3_sv_addr; // @[VDecode.scala 377:20]
- assign io_out_3_bits_sv_data = data_3_sv_data; // @[VDecode.scala 377:20]
- assign io_out_3_bits_cmdsync = data_3_cmdsync; // @[VDecode.scala 377:20]
- assign io_cmdq_0_alu = cmdq_0_alu; // @[VDecode.scala 378:16]
- assign io_cmdq_0_conv = cmdq_0_conv; // @[VDecode.scala 378:16]
- assign io_cmdq_0_ldst = cmdq_0_ldst; // @[VDecode.scala 378:16]
- assign io_cmdq_0_ld = cmdq_0_ld; // @[VDecode.scala 378:16]
- assign io_cmdq_0_st = cmdq_0_st; // @[VDecode.scala 378:16]
- assign io_cmdq_1_alu = cmdq_1_alu; // @[VDecode.scala 378:16]
- assign io_cmdq_1_conv = cmdq_1_conv; // @[VDecode.scala 378:16]
- assign io_cmdq_1_ldst = cmdq_1_ldst; // @[VDecode.scala 378:16]
- assign io_cmdq_1_ld = cmdq_1_ld; // @[VDecode.scala 378:16]
- assign io_cmdq_1_st = cmdq_1_st; // @[VDecode.scala 378:16]
- assign io_cmdq_2_alu = cmdq_2_alu; // @[VDecode.scala 378:16]
- assign io_cmdq_2_conv = cmdq_2_conv; // @[VDecode.scala 378:16]
- assign io_cmdq_2_ldst = cmdq_2_ldst; // @[VDecode.scala 378:16]
- assign io_cmdq_2_ld = cmdq_2_ld; // @[VDecode.scala 378:16]
- assign io_cmdq_2_st = cmdq_2_st; // @[VDecode.scala 378:16]
- assign io_cmdq_3_alu = cmdq_3_alu; // @[VDecode.scala 378:16]
- assign io_cmdq_3_conv = cmdq_3_conv; // @[VDecode.scala 378:16]
- assign io_cmdq_3_ldst = cmdq_3_ldst; // @[VDecode.scala 378:16]
- assign io_cmdq_3_ld = cmdq_3_ld; // @[VDecode.scala 378:16]
- assign io_cmdq_3_st = cmdq_3_st; // @[VDecode.scala 378:16]
- assign io_stall = _io_stall_T_1 > 5'h10; // @[VDecode.scala 158:37]
- assign io_vrfsb_set_valid = output_[0] | output_[1] | output_[2] | output_[3]; // @[VDecode.scala 346:61]
- assign io_vrfsb_set_bits = _io_vrfsb_set_bits_T_7 | _io_vrfsb_set_bits_T_9; // @[VDecode.scala 350:60]
- assign io_undef = io_in_valid & (d_0_io_undef | d_1_io_undef | d_2_io_undef | d_3_io_undef); // @[VDecode.scala 125:27]
- assign io_nempty = nempty; // @[VDecode.scala 389:13]
- assign f_clock = clock;
- assign f_reset = reset;
- assign f_io_in_valid = io_in_valid; // @[VDecode.scala 129:11]
- assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VDecode.scala 129:11]
- assign f_io_in_bits_0_bits_inst = io_in_bits_0_bits_inst; // @[VDecode.scala 129:11]
- assign f_io_in_bits_0_bits_addr = io_in_bits_0_bits_addr; // @[VDecode.scala 129:11]
- assign f_io_in_bits_0_bits_data = io_in_bits_0_bits_data; // @[VDecode.scala 129:11]
- assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VDecode.scala 129:11]
- assign f_io_in_bits_1_bits_inst = io_in_bits_1_bits_inst; // @[VDecode.scala 129:11]
- assign f_io_in_bits_1_bits_addr = io_in_bits_1_bits_addr; // @[VDecode.scala 129:11]
- assign f_io_in_bits_1_bits_data = io_in_bits_1_bits_data; // @[VDecode.scala 129:11]
- assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VDecode.scala 129:11]
- assign f_io_in_bits_2_bits_inst = io_in_bits_2_bits_inst; // @[VDecode.scala 129:11]
- assign f_io_in_bits_2_bits_addr = io_in_bits_2_bits_addr; // @[VDecode.scala 129:11]
- assign f_io_in_bits_2_bits_data = io_in_bits_2_bits_data; // @[VDecode.scala 129:11]
- assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VDecode.scala 129:11]
- assign f_io_in_bits_3_bits_inst = io_in_bits_3_bits_inst; // @[VDecode.scala 129:11]
- assign f_io_in_bits_3_bits_addr = io_in_bits_3_bits_addr; // @[VDecode.scala 129:11]
- assign f_io_in_bits_3_bits_data = io_in_bits_3_bits_data; // @[VDecode.scala 129:11]
- assign f_io_out_0_ready = _f_io_out_0_ready_T[2:0] < 3'h4; // @[VDecode.scala 141:41]
- assign f_io_out_1_ready = _f_io_out_1_ready_T_1 < 3'h4; // @[VDecode.scala 141:41]
- assign f_io_out_2_ready = _f_io_out_2_ready_T_1 < 3'h4; // @[VDecode.scala 141:41]
- assign f_io_out_3_ready = _f_io_out_3_ready_T_1 < 3'h4; // @[VDecode.scala 141:41]
- assign d_0_clock = clock;
- assign d_0_reset = reset;
- assign d_0_io_in_inst = f_io_out_0_bits_inst; // @[VDecode.scala 68:16]
- assign d_0_io_in_addr = f_io_out_0_bits_addr; // @[VDecode.scala 68:16]
- assign d_0_io_in_data = f_io_out_0_bits_data; // @[VDecode.scala 68:16]
- assign d_1_clock = clock;
- assign d_1_reset = reset;
- assign d_1_io_in_inst = f_io_out_1_bits_inst; // @[VDecode.scala 68:16]
- assign d_1_io_in_addr = f_io_out_1_bits_addr; // @[VDecode.scala 68:16]
- assign d_1_io_in_data = f_io_out_1_bits_data; // @[VDecode.scala 68:16]
- assign d_2_clock = clock;
- assign d_2_reset = reset;
- assign d_2_io_in_inst = f_io_out_2_bits_inst; // @[VDecode.scala 68:16]
- assign d_2_io_in_addr = f_io_out_2_bits_addr; // @[VDecode.scala 68:16]
- assign d_2_io_in_data = f_io_out_2_bits_data; // @[VDecode.scala 68:16]
- assign d_3_clock = clock;
- assign d_3_reset = reset;
- assign d_3_io_in_inst = f_io_out_3_bits_inst; // @[VDecode.scala 68:16]
- assign d_3_io_in_addr = f_io_out_3_bits_addr; // @[VDecode.scala 68:16]
- assign d_3_io_in_data = f_io_out_3_bits_data; // @[VDecode.scala 68:16]
- always @(posedge clock) begin
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_op <= data_1_op; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_op <= data_2_op; // @[VDecode.scala 252:16]
- end else begin
- data_0_op <= _GEN_201;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_f2 <= data_1_f2; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_f2 <= data_2_f2; // @[VDecode.scala 252:16]
- end else begin
- data_0_f2 <= _GEN_200;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_sz <= data_1_sz; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_sz <= data_2_sz; // @[VDecode.scala 252:16]
- end else begin
- data_0_sz <= _GEN_199;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_m <= data_1_m; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_m <= data_2_m; // @[VDecode.scala 252:16]
- end else begin
- data_0_m <= _GEN_198;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vd_valid <= data_1_vd_valid; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vd_valid <= data_2_vd_valid; // @[VDecode.scala 252:16]
- end else begin
- data_0_vd_valid <= _GEN_197;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vd_addr <= data_1_vd_addr; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vd_addr <= data_2_vd_addr; // @[VDecode.scala 252:16]
- end else begin
- data_0_vd_addr <= _GEN_196;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_ve_addr <= data_1_ve_addr; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_ve_addr <= data_2_ve_addr; // @[VDecode.scala 252:16]
- end else begin
- data_0_ve_addr <= _GEN_194;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vf_addr <= data_1_vf_addr; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vf_addr <= data_2_vf_addr; // @[VDecode.scala 252:16]
- end else begin
- data_0_vf_addr <= _GEN_192;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vg_addr <= data_1_vg_addr; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vg_addr <= data_2_vg_addr; // @[VDecode.scala 252:16]
- end else begin
- data_0_vg_addr <= _GEN_190;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vs_valid <= data_1_vs_valid; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vs_valid <= data_2_vs_valid; // @[VDecode.scala 252:16]
- end else begin
- data_0_vs_valid <= _GEN_189;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vs_addr <= data_1_vs_addr; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vs_addr <= data_2_vs_addr; // @[VDecode.scala 252:16]
- end else begin
- data_0_vs_addr <= _GEN_188;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vs_tag <= data_1_vs_tag; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vs_tag <= data_2_vs_tag; // @[VDecode.scala 252:16]
- end else begin
- data_0_vs_tag <= _GEN_187;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vt_valid <= data_1_vt_valid; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vt_valid <= data_2_vt_valid; // @[VDecode.scala 252:16]
- end else begin
- data_0_vt_valid <= _GEN_186;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vt_addr <= data_1_vt_addr; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vt_addr <= data_2_vt_addr; // @[VDecode.scala 252:16]
- end else begin
- data_0_vt_addr <= _GEN_185;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vt_tag <= data_1_vt_tag; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vt_tag <= data_2_vt_tag; // @[VDecode.scala 252:16]
- end else begin
- data_0_vt_tag <= _GEN_184;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vu_valid <= data_1_vu_valid; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vu_valid <= data_2_vu_valid; // @[VDecode.scala 252:16]
- end else begin
- data_0_vu_valid <= _GEN_183;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vu_addr <= data_1_vu_addr; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vu_addr <= data_2_vu_addr; // @[VDecode.scala 252:16]
- end else begin
- data_0_vu_addr <= _GEN_182;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vu_tag <= data_1_vu_tag; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vu_tag <= data_2_vu_tag; // @[VDecode.scala 252:16]
- end else begin
- data_0_vu_tag <= _GEN_181;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vx_valid <= data_1_vx_valid; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vx_valid <= data_2_vx_valid; // @[VDecode.scala 252:16]
- end else begin
- data_0_vx_valid <= _GEN_180;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vx_addr <= data_1_vx_addr; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vx_addr <= data_2_vx_addr; // @[VDecode.scala 252:16]
- end else begin
- data_0_vx_addr <= _GEN_179;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vx_tag <= data_1_vx_tag; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vx_tag <= data_2_vx_tag; // @[VDecode.scala 252:16]
- end else begin
- data_0_vx_tag <= _GEN_178;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vy_valid <= data_1_vy_valid; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vy_valid <= data_2_vy_valid; // @[VDecode.scala 252:16]
- end else begin
- data_0_vy_valid <= _GEN_177;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vy_addr <= data_1_vy_addr; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vy_addr <= data_2_vy_addr; // @[VDecode.scala 252:16]
- end else begin
- data_0_vy_addr <= _GEN_176;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vy_tag <= data_1_vy_tag; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vy_tag <= data_2_vy_tag; // @[VDecode.scala 252:16]
- end else begin
- data_0_vy_tag <= _GEN_175;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vz_valid <= data_1_vz_valid; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vz_valid <= data_2_vz_valid; // @[VDecode.scala 252:16]
- end else begin
- data_0_vz_valid <= _GEN_174;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vz_addr <= data_1_vz_addr; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vz_addr <= data_2_vz_addr; // @[VDecode.scala 252:16]
- end else begin
- data_0_vz_addr <= _GEN_173;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_vz_tag <= data_1_vz_tag; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_vz_tag <= data_2_vz_tag; // @[VDecode.scala 252:16]
- end else begin
- data_0_vz_tag <= _GEN_172;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_sv_valid <= data_1_sv_valid; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_sv_valid <= data_2_sv_valid; // @[VDecode.scala 252:16]
- end else begin
- data_0_sv_valid <= _GEN_171;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_sv_addr <= data_1_sv_addr; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_sv_addr <= data_2_sv_addr; // @[VDecode.scala 252:16]
- end else begin
- data_0_sv_addr <= _GEN_170;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_sv_data <= data_1_sv_data; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_sv_data <= data_2_sv_data; // @[VDecode.scala 252:16]
- end else begin
- data_0_sv_data <= _GEN_169;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- data_0_cmdsync <= data_1_cmdsync; // @[VDecode.scala 247:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- data_0_cmdsync <= data_2_cmdsync; // @[VDecode.scala 252:16]
- end else begin
- data_0_cmdsync <= _GEN_168;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_op <= data_2_op; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_op <= data_3_op; // @[VDecode.scala 279:16]
- end else begin
- data_1_op <= _GEN_369;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_f2 <= data_2_f2; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_f2 <= data_3_f2; // @[VDecode.scala 279:16]
- end else begin
- data_1_f2 <= _GEN_368;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_sz <= data_2_sz; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_sz <= data_3_sz; // @[VDecode.scala 279:16]
- end else begin
- data_1_sz <= _GEN_367;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_m <= data_2_m; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_m <= data_3_m; // @[VDecode.scala 279:16]
- end else begin
- data_1_m <= _GEN_366;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vd_valid <= data_2_vd_valid; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vd_valid <= data_3_vd_valid; // @[VDecode.scala 279:16]
- end else begin
- data_1_vd_valid <= _GEN_365;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vd_addr <= data_2_vd_addr; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vd_addr <= data_3_vd_addr; // @[VDecode.scala 279:16]
- end else begin
- data_1_vd_addr <= _GEN_364;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_ve_addr <= data_2_ve_addr; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_ve_addr <= data_3_ve_addr; // @[VDecode.scala 279:16]
- end else begin
- data_1_ve_addr <= _GEN_362;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vf_addr <= data_2_vf_addr; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vf_addr <= data_3_vf_addr; // @[VDecode.scala 279:16]
- end else begin
- data_1_vf_addr <= _GEN_360;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vg_addr <= data_2_vg_addr; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vg_addr <= data_3_vg_addr; // @[VDecode.scala 279:16]
- end else begin
- data_1_vg_addr <= _GEN_358;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vs_valid <= data_2_vs_valid; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vs_valid <= data_3_vs_valid; // @[VDecode.scala 279:16]
- end else begin
- data_1_vs_valid <= _GEN_357;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vs_addr <= data_2_vs_addr; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vs_addr <= data_3_vs_addr; // @[VDecode.scala 279:16]
- end else begin
- data_1_vs_addr <= _GEN_356;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vs_tag <= data_2_vs_tag; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vs_tag <= data_3_vs_tag; // @[VDecode.scala 279:16]
- end else begin
- data_1_vs_tag <= _GEN_355;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vt_valid <= data_2_vt_valid; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vt_valid <= data_3_vt_valid; // @[VDecode.scala 279:16]
- end else begin
- data_1_vt_valid <= _GEN_354;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vt_addr <= data_2_vt_addr; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vt_addr <= data_3_vt_addr; // @[VDecode.scala 279:16]
- end else begin
- data_1_vt_addr <= _GEN_353;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vt_tag <= data_2_vt_tag; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vt_tag <= data_3_vt_tag; // @[VDecode.scala 279:16]
- end else begin
- data_1_vt_tag <= _GEN_352;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vu_valid <= data_2_vu_valid; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vu_valid <= data_3_vu_valid; // @[VDecode.scala 279:16]
- end else begin
- data_1_vu_valid <= _GEN_351;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vu_addr <= data_2_vu_addr; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vu_addr <= data_3_vu_addr; // @[VDecode.scala 279:16]
- end else begin
- data_1_vu_addr <= _GEN_350;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vu_tag <= data_2_vu_tag; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vu_tag <= data_3_vu_tag; // @[VDecode.scala 279:16]
- end else begin
- data_1_vu_tag <= _GEN_349;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vx_valid <= data_2_vx_valid; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vx_valid <= data_3_vx_valid; // @[VDecode.scala 279:16]
- end else begin
- data_1_vx_valid <= _GEN_348;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vx_addr <= data_2_vx_addr; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vx_addr <= data_3_vx_addr; // @[VDecode.scala 279:16]
- end else begin
- data_1_vx_addr <= _GEN_347;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vx_tag <= data_2_vx_tag; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vx_tag <= data_3_vx_tag; // @[VDecode.scala 279:16]
- end else begin
- data_1_vx_tag <= _GEN_346;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vy_valid <= data_2_vy_valid; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vy_valid <= data_3_vy_valid; // @[VDecode.scala 279:16]
- end else begin
- data_1_vy_valid <= _GEN_345;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vy_addr <= data_2_vy_addr; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vy_addr <= data_3_vy_addr; // @[VDecode.scala 279:16]
- end else begin
- data_1_vy_addr <= _GEN_344;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vy_tag <= data_2_vy_tag; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vy_tag <= data_3_vy_tag; // @[VDecode.scala 279:16]
- end else begin
- data_1_vy_tag <= _GEN_343;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vz_valid <= data_2_vz_valid; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vz_valid <= data_3_vz_valid; // @[VDecode.scala 279:16]
- end else begin
- data_1_vz_valid <= _GEN_342;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vz_addr <= data_2_vz_addr; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vz_addr <= data_3_vz_addr; // @[VDecode.scala 279:16]
- end else begin
- data_1_vz_addr <= _GEN_341;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_vz_tag <= data_2_vz_tag; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_vz_tag <= data_3_vz_tag; // @[VDecode.scala 279:16]
- end else begin
- data_1_vz_tag <= _GEN_340;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_sv_valid <= data_2_sv_valid; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_sv_valid <= data_3_sv_valid; // @[VDecode.scala 279:16]
- end else begin
- data_1_sv_valid <= _GEN_339;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_sv_addr <= data_2_sv_addr; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_sv_addr <= data_3_sv_addr; // @[VDecode.scala 279:16]
- end else begin
- data_1_sv_addr <= _GEN_338;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_sv_data <= data_2_sv_data; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_sv_data <= data_3_sv_data; // @[VDecode.scala 279:16]
- end else begin
- data_1_sv_data <= _GEN_337;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- data_1_cmdsync <= data_2_cmdsync; // @[VDecode.scala 274:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- data_1_cmdsync <= data_3_cmdsync; // @[VDecode.scala 279:16]
- end else begin
- data_1_cmdsync <= _GEN_336;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_op <= data_3_op; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_op <= e_0_op; // @[VDecode.scala 306:16]
- end else begin
- data_2_op <= _GEN_537;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_f2 <= data_3_f2; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_f2 <= e_0_f2; // @[VDecode.scala 306:16]
- end else begin
- data_2_f2 <= _GEN_536;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_sz <= data_3_sz; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_sz <= e_0_sz; // @[VDecode.scala 306:16]
- end else begin
- data_2_sz <= _GEN_535;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_m <= data_3_m; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_m <= e_0_m; // @[VDecode.scala 306:16]
- end else begin
- data_2_m <= _GEN_534;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vd_valid <= data_3_vd_valid; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vd_valid <= e_0_vd_valid; // @[VDecode.scala 306:16]
- end else begin
- data_2_vd_valid <= _GEN_533;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vd_addr <= data_3_vd_addr; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vd_addr <= e_0_vd_addr; // @[VDecode.scala 306:16]
- end else begin
- data_2_vd_addr <= _GEN_532;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_ve_addr <= data_3_ve_addr; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_ve_addr <= e_0_ve_addr; // @[VDecode.scala 306:16]
- end else begin
- data_2_ve_addr <= _GEN_530;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vf_addr <= data_3_vf_addr; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vf_addr <= e_0_vf_addr; // @[VDecode.scala 306:16]
- end else begin
- data_2_vf_addr <= _GEN_528;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vg_addr <= data_3_vg_addr; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vg_addr <= e_0_vg_addr; // @[VDecode.scala 306:16]
- end else begin
- data_2_vg_addr <= _GEN_526;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vs_valid <= data_3_vs_valid; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vs_valid <= e_0_vs_r_valid; // @[VDecode.scala 306:16]
- end else begin
- data_2_vs_valid <= _GEN_525;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vs_addr <= data_3_vs_addr; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vs_addr <= e_0_vs_r_addr; // @[VDecode.scala 306:16]
- end else begin
- data_2_vs_addr <= _GEN_524;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vs_tag <= data_3_vs_tag; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vs_tag <= e_0_vs_r_tag_value_4_0; // @[VDecode.scala 306:16]
- end else begin
- data_2_vs_tag <= _GEN_523;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vt_valid <= data_3_vt_valid; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vt_valid <= e_0_vt_r_valid; // @[VDecode.scala 306:16]
- end else begin
- data_2_vt_valid <= _GEN_522;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vt_addr <= data_3_vt_addr; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vt_addr <= e_0_vt_r_addr; // @[VDecode.scala 306:16]
- end else begin
- data_2_vt_addr <= _GEN_521;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vt_tag <= data_3_vt_tag; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vt_tag <= e_0_vt_r_tag_value_4_0; // @[VDecode.scala 306:16]
- end else begin
- data_2_vt_tag <= _GEN_520;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vu_valid <= data_3_vu_valid; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vu_valid <= e_0_vu_r_valid; // @[VDecode.scala 306:16]
- end else begin
- data_2_vu_valid <= _GEN_519;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vu_addr <= data_3_vu_addr; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vu_addr <= e_0_vu_r_addr; // @[VDecode.scala 306:16]
- end else begin
- data_2_vu_addr <= _GEN_518;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vu_tag <= data_3_vu_tag; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vu_tag <= e_0_vu_r_tag_value_4_0; // @[VDecode.scala 306:16]
- end else begin
- data_2_vu_tag <= _GEN_517;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vx_valid <= data_3_vx_valid; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vx_valid <= e_0_vx_r_valid; // @[VDecode.scala 306:16]
- end else begin
- data_2_vx_valid <= _GEN_516;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vx_addr <= data_3_vx_addr; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vx_addr <= e_0_vx_r_addr; // @[VDecode.scala 306:16]
- end else begin
- data_2_vx_addr <= _GEN_515;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vx_tag <= data_3_vx_tag; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vx_tag <= e_0_vx_r_tag_value_4_0; // @[VDecode.scala 306:16]
- end else begin
- data_2_vx_tag <= _GEN_514;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vy_valid <= data_3_vy_valid; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vy_valid <= e_0_vy_r_valid; // @[VDecode.scala 306:16]
- end else begin
- data_2_vy_valid <= _GEN_513;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vy_addr <= data_3_vy_addr; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vy_addr <= e_0_vy_r_addr; // @[VDecode.scala 306:16]
- end else begin
- data_2_vy_addr <= _GEN_512;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vy_tag <= data_3_vy_tag; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vy_tag <= e_0_vy_r_tag_value_4_0; // @[VDecode.scala 306:16]
- end else begin
- data_2_vy_tag <= _GEN_511;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vz_valid <= data_3_vz_valid; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vz_valid <= e_0_vz_r_valid; // @[VDecode.scala 306:16]
- end else begin
- data_2_vz_valid <= _GEN_510;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vz_addr <= data_3_vz_addr; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vz_addr <= e_0_vz_r_addr; // @[VDecode.scala 306:16]
- end else begin
- data_2_vz_addr <= _GEN_509;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_vz_tag <= data_3_vz_tag; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_vz_tag <= e_0_vz_r_tag_value_4_0; // @[VDecode.scala 306:16]
- end else begin
- data_2_vz_tag <= _GEN_508;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_sv_valid <= data_3_sv_valid; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_sv_valid <= e_0_sv_valid; // @[VDecode.scala 306:16]
- end else begin
- data_2_sv_valid <= _GEN_507;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_sv_addr <= data_3_sv_addr; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_sv_addr <= e_0_sv_addr; // @[VDecode.scala 306:16]
- end else begin
- data_2_sv_addr <= _GEN_506;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_sv_data <= data_3_sv_data; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_sv_data <= e_0_sv_data; // @[VDecode.scala 306:16]
- end else begin
- data_2_sv_data <= _GEN_505;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- data_2_cmdsync <= data_3_cmdsync; // @[VDecode.scala 301:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- data_2_cmdsync <= e_0_cmdsync; // @[VDecode.scala 306:16]
- end else begin
- data_2_cmdsync <= _GEN_504;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_op <= e_0_op; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_op <= e_1_op; // @[VDecode.scala 331:16]
- end else begin
- data_3_op <= _GEN_705;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_f2 <= e_0_f2; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_f2 <= e_1_f2; // @[VDecode.scala 331:16]
- end else begin
- data_3_f2 <= _GEN_704;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_sz <= e_0_sz; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_sz <= e_1_sz; // @[VDecode.scala 331:16]
- end else begin
- data_3_sz <= _GEN_703;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_m <= e_0_m; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_m <= e_1_m; // @[VDecode.scala 331:16]
- end else begin
- data_3_m <= _GEN_702;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vd_valid <= e_0_vd_valid; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vd_valid <= e_1_vd_valid; // @[VDecode.scala 331:16]
- end else begin
- data_3_vd_valid <= _GEN_701;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vd_addr <= e_0_vd_addr; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vd_addr <= e_1_vd_addr; // @[VDecode.scala 331:16]
- end else begin
- data_3_vd_addr <= _GEN_700;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_ve_addr <= e_0_ve_addr; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_ve_addr <= e_1_ve_addr; // @[VDecode.scala 331:16]
- end else begin
- data_3_ve_addr <= _GEN_698;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vf_addr <= e_0_vf_addr; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vf_addr <= e_1_vf_addr; // @[VDecode.scala 331:16]
- end else begin
- data_3_vf_addr <= _GEN_696;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vg_addr <= e_0_vg_addr; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vg_addr <= e_1_vg_addr; // @[VDecode.scala 331:16]
- end else begin
- data_3_vg_addr <= _GEN_694;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vs_valid <= e_0_vs_r_valid; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vs_valid <= e_1_vs_r_valid; // @[VDecode.scala 331:16]
- end else begin
- data_3_vs_valid <= _GEN_693;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vs_addr <= e_0_vs_r_addr; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vs_addr <= e_1_vs_r_addr; // @[VDecode.scala 331:16]
- end else begin
- data_3_vs_addr <= _GEN_692;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vs_tag <= e_0_vs_r_tag_value_4_0; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vs_tag <= e_1_vs_r_tag_value_4_0; // @[VDecode.scala 331:16]
- end else begin
- data_3_vs_tag <= _GEN_691;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vt_valid <= e_0_vt_r_valid; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vt_valid <= e_1_vt_r_valid; // @[VDecode.scala 331:16]
- end else begin
- data_3_vt_valid <= _GEN_690;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vt_addr <= e_0_vt_r_addr; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vt_addr <= e_1_vt_r_addr; // @[VDecode.scala 331:16]
- end else begin
- data_3_vt_addr <= _GEN_689;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vt_tag <= e_0_vt_r_tag_value_4_0; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vt_tag <= e_1_vt_r_tag_value_4_0; // @[VDecode.scala 331:16]
- end else begin
- data_3_vt_tag <= _GEN_688;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vu_valid <= e_0_vu_r_valid; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vu_valid <= e_1_vu_r_valid; // @[VDecode.scala 331:16]
- end else begin
- data_3_vu_valid <= _GEN_687;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vu_addr <= e_0_vu_r_addr; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vu_addr <= e_1_vu_r_addr; // @[VDecode.scala 331:16]
- end else begin
- data_3_vu_addr <= _GEN_686;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vu_tag <= e_0_vu_r_tag_value_4_0; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vu_tag <= e_1_vu_r_tag_value_4_0; // @[VDecode.scala 331:16]
- end else begin
- data_3_vu_tag <= _GEN_685;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vx_valid <= e_0_vx_r_valid; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vx_valid <= e_1_vx_r_valid; // @[VDecode.scala 331:16]
- end else begin
- data_3_vx_valid <= _GEN_684;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vx_addr <= e_0_vx_r_addr; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vx_addr <= e_1_vx_r_addr; // @[VDecode.scala 331:16]
- end else begin
- data_3_vx_addr <= _GEN_683;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vx_tag <= e_0_vx_r_tag_value_4_0; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vx_tag <= e_1_vx_r_tag_value_4_0; // @[VDecode.scala 331:16]
- end else begin
- data_3_vx_tag <= _GEN_682;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vy_valid <= e_0_vy_r_valid; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vy_valid <= e_1_vy_r_valid; // @[VDecode.scala 331:16]
- end else begin
- data_3_vy_valid <= _GEN_681;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vy_addr <= e_0_vy_r_addr; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vy_addr <= e_1_vy_r_addr; // @[VDecode.scala 331:16]
- end else begin
- data_3_vy_addr <= _GEN_680;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vy_tag <= e_0_vy_r_tag_value_4_0; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vy_tag <= e_1_vy_r_tag_value_4_0; // @[VDecode.scala 331:16]
- end else begin
- data_3_vy_tag <= _GEN_679;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vz_valid <= e_0_vz_r_valid; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vz_valid <= e_1_vz_r_valid; // @[VDecode.scala 331:16]
- end else begin
- data_3_vz_valid <= _GEN_678;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vz_addr <= e_0_vz_r_addr; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vz_addr <= e_1_vz_r_addr; // @[VDecode.scala 331:16]
- end else begin
- data_3_vz_addr <= _GEN_677;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_vz_tag <= e_0_vz_r_tag_value_4_0; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_vz_tag <= e_1_vz_r_tag_value_4_0; // @[VDecode.scala 331:16]
- end else begin
- data_3_vz_tag <= _GEN_676;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_sv_valid <= e_0_sv_valid; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_sv_valid <= e_1_sv_valid; // @[VDecode.scala 331:16]
- end else begin
- data_3_sv_valid <= _GEN_675;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_sv_addr <= e_0_sv_addr; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_sv_addr <= e_1_sv_addr; // @[VDecode.scala 331:16]
- end else begin
- data_3_sv_addr <= _GEN_674;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_sv_data <= e_0_sv_data; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_sv_data <= e_1_sv_data; // @[VDecode.scala 331:16]
- end else begin
- data_3_sv_data <= _GEN_673;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- data_3_cmdsync <= e_0_cmdsync; // @[VDecode.scala 327:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- data_3_cmdsync <= e_1_cmdsync; // @[VDecode.scala 331:16]
- end else begin
- data_3_cmdsync <= _GEN_672;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- cmdq_0_alu <= cmdq_1_alu; // @[VDecode.scala 248:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- cmdq_0_alu <= cmdq_2_alu; // @[VDecode.scala 253:16]
- end else begin
- cmdq_0_alu <= _GEN_206;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- cmdq_0_conv <= cmdq_1_conv; // @[VDecode.scala 248:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- cmdq_0_conv <= cmdq_2_conv; // @[VDecode.scala 253:16]
- end else begin
- cmdq_0_conv <= _GEN_205;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- cmdq_0_ldst <= cmdq_1_ldst; // @[VDecode.scala 248:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- cmdq_0_ldst <= cmdq_2_ldst; // @[VDecode.scala 253:16]
- end else begin
- cmdq_0_ldst <= _GEN_204;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- cmdq_0_ld <= cmdq_1_ld; // @[VDecode.scala 248:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- cmdq_0_ld <= cmdq_2_ld; // @[VDecode.scala 253:16]
- end else begin
- cmdq_0_ld <= _GEN_203;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- cmdq_0_st <= cmdq_1_st; // @[VDecode.scala 248:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- cmdq_0_st <= cmdq_2_st; // @[VDecode.scala 253:16]
- end else begin
- cmdq_0_st <= _GEN_202;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- cmdq_1_alu <= cmdq_2_alu; // @[VDecode.scala 275:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- cmdq_1_alu <= cmdq_3_alu; // @[VDecode.scala 280:16]
- end else begin
- cmdq_1_alu <= _GEN_374;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- cmdq_1_conv <= cmdq_2_conv; // @[VDecode.scala 275:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- cmdq_1_conv <= cmdq_3_conv; // @[VDecode.scala 280:16]
- end else begin
- cmdq_1_conv <= _GEN_373;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- cmdq_1_ldst <= cmdq_2_ldst; // @[VDecode.scala 275:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- cmdq_1_ldst <= cmdq_3_ldst; // @[VDecode.scala 280:16]
- end else begin
- cmdq_1_ldst <= _GEN_372;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- cmdq_1_ld <= cmdq_2_ld; // @[VDecode.scala 275:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- cmdq_1_ld <= cmdq_3_ld; // @[VDecode.scala 280:16]
- end else begin
- cmdq_1_ld <= _GEN_371;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- cmdq_1_st <= cmdq_2_st; // @[VDecode.scala 275:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- cmdq_1_st <= cmdq_3_st; // @[VDecode.scala 280:16]
- end else begin
- cmdq_1_st <= _GEN_370;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- cmdq_2_alu <= cmdq_3_alu; // @[VDecode.scala 302:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- cmdq_2_alu <= cmdqMux_4_alu; // @[VDecode.scala 307:16]
- end else begin
- cmdq_2_alu <= _GEN_542;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- cmdq_2_conv <= cmdq_3_conv; // @[VDecode.scala 302:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- cmdq_2_conv <= cmdqMux_4_conv; // @[VDecode.scala 307:16]
- end else begin
- cmdq_2_conv <= _GEN_541;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- cmdq_2_ldst <= cmdq_3_ldst; // @[VDecode.scala 302:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- cmdq_2_ldst <= cmdqMux_4_ldst; // @[VDecode.scala 307:16]
- end else begin
- cmdq_2_ldst <= _GEN_540;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- cmdq_2_ld <= cmdq_3_ld; // @[VDecode.scala 302:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- cmdq_2_ld <= cmdqMux_4_ld; // @[VDecode.scala 307:16]
- end else begin
- cmdq_2_ld <= _GEN_539;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- cmdq_2_st <= cmdq_3_st; // @[VDecode.scala 302:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- cmdq_2_st <= cmdqMux_4_st; // @[VDecode.scala 307:16]
- end else begin
- cmdq_2_st <= _GEN_538;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- cmdq_3_alu <= cmdqMux_4_alu; // @[VDecode.scala 328:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- cmdq_3_alu <= cmdqMux_5_alu; // @[VDecode.scala 332:16]
- end else begin
- cmdq_3_alu <= _GEN_710;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- cmdq_3_conv <= cmdqMux_4_conv; // @[VDecode.scala 328:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- cmdq_3_conv <= cmdqMux_5_conv; // @[VDecode.scala 332:16]
- end else begin
- cmdq_3_conv <= _GEN_709;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- cmdq_3_ldst <= cmdqMux_4_ldst; // @[VDecode.scala 328:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- cmdq_3_ldst <= cmdqMux_5_ldst; // @[VDecode.scala 332:16]
- end else begin
- cmdq_3_ldst <= _GEN_708;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- cmdq_3_ld <= cmdqMux_4_ld; // @[VDecode.scala 328:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- cmdq_3_ld <= cmdqMux_5_ld; // @[VDecode.scala 332:16]
- end else begin
- cmdq_3_ld <= _GEN_707;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- cmdq_3_st <= cmdqMux_4_st; // @[VDecode.scala 328:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- cmdq_3_st <= cmdqMux_5_st; // @[VDecode.scala 332:16]
- end else begin
- cmdq_3_st <= _GEN_706;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- actv2_0_ractive <= actv2_1_ractive; // @[VDecode.scala 249:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- actv2_0_ractive <= actv2_2_ractive; // @[VDecode.scala 254:16]
- end else begin
- actv2_0_ractive <= _GEN_208;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(valid_0 & ~output_[0])) begin // @[VDecode.scala 241:33]
- if (valid_1 & ~output_[1]) begin // @[VDecode.scala 246:40]
- actv2_0_wactive <= actv2_1_wactive; // @[VDecode.scala 249:16]
- end else if (valid_2 & ~output_[2]) begin // @[VDecode.scala 251:40]
- actv2_0_wactive <= actv2_2_wactive; // @[VDecode.scala 254:16]
- end else begin
- actv2_0_wactive <= _GEN_207;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- actv2_1_ractive <= actv2_2_ractive; // @[VDecode.scala 276:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- actv2_1_ractive <= actv2_3_ractive; // @[VDecode.scala 281:16]
- end else begin
- actv2_1_ractive <= _GEN_376;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked0[1] & valid_1 & _T_47)) begin // @[VDecode.scala 268:48]
- if (~marked0[2] & valid_2 & _T_50) begin // @[VDecode.scala 273:55]
- actv2_1_wactive <= actv2_2_wactive; // @[VDecode.scala 276:16]
- end else if (~marked0[3] & valid_3 & _T_53) begin // @[VDecode.scala 278:55]
- actv2_1_wactive <= actv2_3_wactive; // @[VDecode.scala 281:16]
- end else begin
- actv2_1_wactive <= _GEN_375;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- actv2_2_ractive <= actv2_3_ractive; // @[VDecode.scala 303:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- actv2_2_ractive <= dactv_0_ractive; // @[VDecode.scala 308:16]
- end else begin
- actv2_2_ractive <= _GEN_544;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked1[2] & valid_2 & _T_50)) begin // @[VDecode.scala 295:48]
- if (~marked1[3] & valid_3 & _T_53) begin // @[VDecode.scala 300:55]
- actv2_2_wactive <= actv2_3_wactive; // @[VDecode.scala 303:16]
- end else if (~marked1[4]) begin // @[VDecode.scala 305:29]
- actv2_2_wactive <= dactv_0_wactive; // @[VDecode.scala 308:16]
- end else begin
- actv2_2_wactive <= _GEN_543;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- actv2_3_ractive <= dactv_0_ractive; // @[VDecode.scala 329:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- actv2_3_ractive <= dactv_1_ractive; // @[VDecode.scala 333:16]
- end else begin
- actv2_3_ractive <= _GEN_712;
- end
- end
- end
- if (dataEn) begin // @[VDecode.scala 196:19]
- if (!(~marked2[3] & valid_3 & _T_53)) begin // @[VDecode.scala 322:48]
- if (~marked2[4]) begin // @[VDecode.scala 326:29]
- actv2_3_wactive <= dactv_0_wactive; // @[VDecode.scala 329:16]
- end else if (~marked2[5]) begin // @[VDecode.scala 330:29]
- actv2_3_wactive <= dactv_1_wactive; // @[VDecode.scala 333:16]
- end else begin
- actv2_3_wactive <= _GEN_711;
- end
- end
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(~(fvalid[1] & ~fvalid[0]))) begin
- $fatal; // @[VDecode.scala 188:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(~(fvalid[1] & ~fvalid[0]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VDecode.scala:188 assert(!(fvalid(1) && fvalid(0,0) =/= 1.U))\n"); // @[VDecode.scala 188:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(~(fvalid[2] & fvalid[1:0] != 2'h3))) begin
- $fatal; // @[VDecode.scala 189:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(~(fvalid[2] & fvalid[1:0] != 2'h3))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VDecode.scala:189 assert(!(fvalid(2) && fvalid(1,0) =/= 3.U))\n"); // @[VDecode.scala 189:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(~(fvalid[3] & fvalid[2:0] != 3'h7))) begin
- $fatal; // @[VDecode.scala 190:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(~(fvalid[3] & fvalid[2:0] != 3'h7))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VDecode.scala:190 assert(!(fvalid(3) && fvalid(2,0) =/= 7.U))\n"); // @[VDecode.scala 190:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(_T_28 == _GEN_837)) begin
- $fatal; // @[VDecode.scala 232:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(_T_28 == _GEN_837)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VDecode.scala:232 assert((marked1 & marked0) === marked0)\n"); // @[VDecode.scala 232:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(_T_33 == _GEN_839)) begin
- $fatal; // @[VDecode.scala 233:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(_T_33 == _GEN_839)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VDecode.scala:233 assert((marked2 & marked0) === marked0)\n"); // @[VDecode.scala 233:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(_T_38 == _GEN_841)) begin
- $fatal; // @[VDecode.scala 234:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(_T_38 == _GEN_841)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VDecode.scala:234 assert((marked2 & marked1) === marked1)\n"); // @[VDecode.scala 234:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(_T_105 == 64'h0)) begin
- $fatal; // @[VDecode.scala 353:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(_T_105 == 64'h0)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VDecode.scala:353 assert((io.vrfsb.set.bits(63, 0) & io.vrfsb.set.bits(127, 64)) === 0.U)\n"
- ); // @[VDecode.scala 353:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(_T_116 == 64'h0)) begin
- $fatal; // @[VDecode.scala 354:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_e_0_vs_T_2 & ~(_T_116 == 64'h0)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VDecode.scala:354 assert(((io.vrfsb.data(63, 0) | io.vrfsb.data(127, 64)) & (io.vrfsb.set.bits(63, 0) | io.vrfsb.set.bits(127, 64))) === 0.U)\n"
- ); // @[VDecode.scala 354:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VDecode.scala 153:35]
- valid_0 <= 1'h0;
- end else begin
- valid_0 <= _valid_0_T_1 > 3'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VDecode.scala 153:35]
- valid_1 <= 1'h0;
- end else begin
- valid_1 <= _valid_0_T_1 > 3'h1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VDecode.scala 153:35]
- valid_2 <= 1'h0;
- end else begin
- valid_2 <= _valid_0_T_1 > 3'h2;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VDecode.scala 153:35]
- valid_3 <= 1'h0;
- end else begin
- valid_3 <= _valid_0_T_1 > 3'h3;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VDecode.scala 86:48]
- tag0 <= 64'h0; // @[VDecode.scala 87:12]
- end else if (f_io_out_3_valid & f_io_out_3_ready) begin // @[VDecode.scala 88:55]
- tag0 <= tag4; // @[VDecode.scala 89:12]
- end else if (f_io_out_2_valid & f_io_out_2_ready) begin // @[VDecode.scala 90:55]
- tag0 <= tag3; // @[VDecode.scala 91:12]
- end else if (f_io_out_1_valid & f_io_out_1_ready) begin // @[VDecode.scala 92:55]
- tag0 <= tag2; // @[VDecode.scala 93:12]
- end else if (f_io_out_0_valid & f_io_out_0_ready) begin // @[VDecode.scala 75:23]
- tag0 <= tag1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VDecode.scala 387:40]
- nempty <= 1'h0;
- end else begin
- nempty <= io_in_valid | f_io_nempty | _dataEn_T_2;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- valid_0 = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- valid_1 = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- valid_2 = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- valid_3 = _RAND_3[0:0];
- _RAND_4 = {1{`RANDOM}};
- data_0_op = _RAND_4[6:0];
- _RAND_5 = {1{`RANDOM}};
- data_0_f2 = _RAND_5[2:0];
- _RAND_6 = {1{`RANDOM}};
- data_0_sz = _RAND_6[2:0];
- _RAND_7 = {1{`RANDOM}};
- data_0_m = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- data_0_vd_valid = _RAND_8[0:0];
- _RAND_9 = {1{`RANDOM}};
- data_0_vd_addr = _RAND_9[5:0];
- _RAND_10 = {1{`RANDOM}};
- data_0_ve_addr = _RAND_10[5:0];
- _RAND_11 = {1{`RANDOM}};
- data_0_vf_addr = _RAND_11[5:0];
- _RAND_12 = {1{`RANDOM}};
- data_0_vg_addr = _RAND_12[5:0];
- _RAND_13 = {1{`RANDOM}};
- data_0_vs_valid = _RAND_13[0:0];
- _RAND_14 = {1{`RANDOM}};
- data_0_vs_addr = _RAND_14[5:0];
- _RAND_15 = {1{`RANDOM}};
- data_0_vs_tag = _RAND_15[3:0];
- _RAND_16 = {1{`RANDOM}};
- data_0_vt_valid = _RAND_16[0:0];
- _RAND_17 = {1{`RANDOM}};
- data_0_vt_addr = _RAND_17[5:0];
- _RAND_18 = {1{`RANDOM}};
- data_0_vt_tag = _RAND_18[3:0];
- _RAND_19 = {1{`RANDOM}};
- data_0_vu_valid = _RAND_19[0:0];
- _RAND_20 = {1{`RANDOM}};
- data_0_vu_addr = _RAND_20[5:0];
- _RAND_21 = {1{`RANDOM}};
- data_0_vu_tag = _RAND_21[3:0];
- _RAND_22 = {1{`RANDOM}};
- data_0_vx_valid = _RAND_22[0:0];
- _RAND_23 = {1{`RANDOM}};
- data_0_vx_addr = _RAND_23[5:0];
- _RAND_24 = {1{`RANDOM}};
- data_0_vx_tag = _RAND_24[3:0];
- _RAND_25 = {1{`RANDOM}};
- data_0_vy_valid = _RAND_25[0:0];
- _RAND_26 = {1{`RANDOM}};
- data_0_vy_addr = _RAND_26[5:0];
- _RAND_27 = {1{`RANDOM}};
- data_0_vy_tag = _RAND_27[3:0];
- _RAND_28 = {1{`RANDOM}};
- data_0_vz_valid = _RAND_28[0:0];
- _RAND_29 = {1{`RANDOM}};
- data_0_vz_addr = _RAND_29[5:0];
- _RAND_30 = {1{`RANDOM}};
- data_0_vz_tag = _RAND_30[3:0];
- _RAND_31 = {1{`RANDOM}};
- data_0_sv_valid = _RAND_31[0:0];
- _RAND_32 = {1{`RANDOM}};
- data_0_sv_addr = _RAND_32[31:0];
- _RAND_33 = {1{`RANDOM}};
- data_0_sv_data = _RAND_33[31:0];
- _RAND_34 = {1{`RANDOM}};
- data_0_cmdsync = _RAND_34[0:0];
- _RAND_35 = {1{`RANDOM}};
- data_1_op = _RAND_35[6:0];
- _RAND_36 = {1{`RANDOM}};
- data_1_f2 = _RAND_36[2:0];
- _RAND_37 = {1{`RANDOM}};
- data_1_sz = _RAND_37[2:0];
- _RAND_38 = {1{`RANDOM}};
- data_1_m = _RAND_38[0:0];
- _RAND_39 = {1{`RANDOM}};
- data_1_vd_valid = _RAND_39[0:0];
- _RAND_40 = {1{`RANDOM}};
- data_1_vd_addr = _RAND_40[5:0];
- _RAND_41 = {1{`RANDOM}};
- data_1_ve_addr = _RAND_41[5:0];
- _RAND_42 = {1{`RANDOM}};
- data_1_vf_addr = _RAND_42[5:0];
- _RAND_43 = {1{`RANDOM}};
- data_1_vg_addr = _RAND_43[5:0];
- _RAND_44 = {1{`RANDOM}};
- data_1_vs_valid = _RAND_44[0:0];
- _RAND_45 = {1{`RANDOM}};
- data_1_vs_addr = _RAND_45[5:0];
- _RAND_46 = {1{`RANDOM}};
- data_1_vs_tag = _RAND_46[3:0];
- _RAND_47 = {1{`RANDOM}};
- data_1_vt_valid = _RAND_47[0:0];
- _RAND_48 = {1{`RANDOM}};
- data_1_vt_addr = _RAND_48[5:0];
- _RAND_49 = {1{`RANDOM}};
- data_1_vt_tag = _RAND_49[3:0];
- _RAND_50 = {1{`RANDOM}};
- data_1_vu_valid = _RAND_50[0:0];
- _RAND_51 = {1{`RANDOM}};
- data_1_vu_addr = _RAND_51[5:0];
- _RAND_52 = {1{`RANDOM}};
- data_1_vu_tag = _RAND_52[3:0];
- _RAND_53 = {1{`RANDOM}};
- data_1_vx_valid = _RAND_53[0:0];
- _RAND_54 = {1{`RANDOM}};
- data_1_vx_addr = _RAND_54[5:0];
- _RAND_55 = {1{`RANDOM}};
- data_1_vx_tag = _RAND_55[3:0];
- _RAND_56 = {1{`RANDOM}};
- data_1_vy_valid = _RAND_56[0:0];
- _RAND_57 = {1{`RANDOM}};
- data_1_vy_addr = _RAND_57[5:0];
- _RAND_58 = {1{`RANDOM}};
- data_1_vy_tag = _RAND_58[3:0];
- _RAND_59 = {1{`RANDOM}};
- data_1_vz_valid = _RAND_59[0:0];
- _RAND_60 = {1{`RANDOM}};
- data_1_vz_addr = _RAND_60[5:0];
- _RAND_61 = {1{`RANDOM}};
- data_1_vz_tag = _RAND_61[3:0];
- _RAND_62 = {1{`RANDOM}};
- data_1_sv_valid = _RAND_62[0:0];
- _RAND_63 = {1{`RANDOM}};
- data_1_sv_addr = _RAND_63[31:0];
- _RAND_64 = {1{`RANDOM}};
- data_1_sv_data = _RAND_64[31:0];
- _RAND_65 = {1{`RANDOM}};
- data_1_cmdsync = _RAND_65[0:0];
- _RAND_66 = {1{`RANDOM}};
- data_2_op = _RAND_66[6:0];
- _RAND_67 = {1{`RANDOM}};
- data_2_f2 = _RAND_67[2:0];
- _RAND_68 = {1{`RANDOM}};
- data_2_sz = _RAND_68[2:0];
- _RAND_69 = {1{`RANDOM}};
- data_2_m = _RAND_69[0:0];
- _RAND_70 = {1{`RANDOM}};
- data_2_vd_valid = _RAND_70[0:0];
- _RAND_71 = {1{`RANDOM}};
- data_2_vd_addr = _RAND_71[5:0];
- _RAND_72 = {1{`RANDOM}};
- data_2_ve_addr = _RAND_72[5:0];
- _RAND_73 = {1{`RANDOM}};
- data_2_vf_addr = _RAND_73[5:0];
- _RAND_74 = {1{`RANDOM}};
- data_2_vg_addr = _RAND_74[5:0];
- _RAND_75 = {1{`RANDOM}};
- data_2_vs_valid = _RAND_75[0:0];
- _RAND_76 = {1{`RANDOM}};
- data_2_vs_addr = _RAND_76[5:0];
- _RAND_77 = {1{`RANDOM}};
- data_2_vs_tag = _RAND_77[3:0];
- _RAND_78 = {1{`RANDOM}};
- data_2_vt_valid = _RAND_78[0:0];
- _RAND_79 = {1{`RANDOM}};
- data_2_vt_addr = _RAND_79[5:0];
- _RAND_80 = {1{`RANDOM}};
- data_2_vt_tag = _RAND_80[3:0];
- _RAND_81 = {1{`RANDOM}};
- data_2_vu_valid = _RAND_81[0:0];
- _RAND_82 = {1{`RANDOM}};
- data_2_vu_addr = _RAND_82[5:0];
- _RAND_83 = {1{`RANDOM}};
- data_2_vu_tag = _RAND_83[3:0];
- _RAND_84 = {1{`RANDOM}};
- data_2_vx_valid = _RAND_84[0:0];
- _RAND_85 = {1{`RANDOM}};
- data_2_vx_addr = _RAND_85[5:0];
- _RAND_86 = {1{`RANDOM}};
- data_2_vx_tag = _RAND_86[3:0];
- _RAND_87 = {1{`RANDOM}};
- data_2_vy_valid = _RAND_87[0:0];
- _RAND_88 = {1{`RANDOM}};
- data_2_vy_addr = _RAND_88[5:0];
- _RAND_89 = {1{`RANDOM}};
- data_2_vy_tag = _RAND_89[3:0];
- _RAND_90 = {1{`RANDOM}};
- data_2_vz_valid = _RAND_90[0:0];
- _RAND_91 = {1{`RANDOM}};
- data_2_vz_addr = _RAND_91[5:0];
- _RAND_92 = {1{`RANDOM}};
- data_2_vz_tag = _RAND_92[3:0];
- _RAND_93 = {1{`RANDOM}};
- data_2_sv_valid = _RAND_93[0:0];
- _RAND_94 = {1{`RANDOM}};
- data_2_sv_addr = _RAND_94[31:0];
- _RAND_95 = {1{`RANDOM}};
- data_2_sv_data = _RAND_95[31:0];
- _RAND_96 = {1{`RANDOM}};
- data_2_cmdsync = _RAND_96[0:0];
- _RAND_97 = {1{`RANDOM}};
- data_3_op = _RAND_97[6:0];
- _RAND_98 = {1{`RANDOM}};
- data_3_f2 = _RAND_98[2:0];
- _RAND_99 = {1{`RANDOM}};
- data_3_sz = _RAND_99[2:0];
- _RAND_100 = {1{`RANDOM}};
- data_3_m = _RAND_100[0:0];
- _RAND_101 = {1{`RANDOM}};
- data_3_vd_valid = _RAND_101[0:0];
- _RAND_102 = {1{`RANDOM}};
- data_3_vd_addr = _RAND_102[5:0];
- _RAND_103 = {1{`RANDOM}};
- data_3_ve_addr = _RAND_103[5:0];
- _RAND_104 = {1{`RANDOM}};
- data_3_vf_addr = _RAND_104[5:0];
- _RAND_105 = {1{`RANDOM}};
- data_3_vg_addr = _RAND_105[5:0];
- _RAND_106 = {1{`RANDOM}};
- data_3_vs_valid = _RAND_106[0:0];
- _RAND_107 = {1{`RANDOM}};
- data_3_vs_addr = _RAND_107[5:0];
- _RAND_108 = {1{`RANDOM}};
- data_3_vs_tag = _RAND_108[3:0];
- _RAND_109 = {1{`RANDOM}};
- data_3_vt_valid = _RAND_109[0:0];
- _RAND_110 = {1{`RANDOM}};
- data_3_vt_addr = _RAND_110[5:0];
- _RAND_111 = {1{`RANDOM}};
- data_3_vt_tag = _RAND_111[3:0];
- _RAND_112 = {1{`RANDOM}};
- data_3_vu_valid = _RAND_112[0:0];
- _RAND_113 = {1{`RANDOM}};
- data_3_vu_addr = _RAND_113[5:0];
- _RAND_114 = {1{`RANDOM}};
- data_3_vu_tag = _RAND_114[3:0];
- _RAND_115 = {1{`RANDOM}};
- data_3_vx_valid = _RAND_115[0:0];
- _RAND_116 = {1{`RANDOM}};
- data_3_vx_addr = _RAND_116[5:0];
- _RAND_117 = {1{`RANDOM}};
- data_3_vx_tag = _RAND_117[3:0];
- _RAND_118 = {1{`RANDOM}};
- data_3_vy_valid = _RAND_118[0:0];
- _RAND_119 = {1{`RANDOM}};
- data_3_vy_addr = _RAND_119[5:0];
- _RAND_120 = {1{`RANDOM}};
- data_3_vy_tag = _RAND_120[3:0];
- _RAND_121 = {1{`RANDOM}};
- data_3_vz_valid = _RAND_121[0:0];
- _RAND_122 = {1{`RANDOM}};
- data_3_vz_addr = _RAND_122[5:0];
- _RAND_123 = {1{`RANDOM}};
- data_3_vz_tag = _RAND_123[3:0];
- _RAND_124 = {1{`RANDOM}};
- data_3_sv_valid = _RAND_124[0:0];
- _RAND_125 = {1{`RANDOM}};
- data_3_sv_addr = _RAND_125[31:0];
- _RAND_126 = {1{`RANDOM}};
- data_3_sv_data = _RAND_126[31:0];
- _RAND_127 = {1{`RANDOM}};
- data_3_cmdsync = _RAND_127[0:0];
- _RAND_128 = {1{`RANDOM}};
- cmdq_0_alu = _RAND_128[0:0];
- _RAND_129 = {1{`RANDOM}};
- cmdq_0_conv = _RAND_129[0:0];
- _RAND_130 = {1{`RANDOM}};
- cmdq_0_ldst = _RAND_130[0:0];
- _RAND_131 = {1{`RANDOM}};
- cmdq_0_ld = _RAND_131[0:0];
- _RAND_132 = {1{`RANDOM}};
- cmdq_0_st = _RAND_132[0:0];
- _RAND_133 = {1{`RANDOM}};
- cmdq_1_alu = _RAND_133[0:0];
- _RAND_134 = {1{`RANDOM}};
- cmdq_1_conv = _RAND_134[0:0];
- _RAND_135 = {1{`RANDOM}};
- cmdq_1_ldst = _RAND_135[0:0];
- _RAND_136 = {1{`RANDOM}};
- cmdq_1_ld = _RAND_136[0:0];
- _RAND_137 = {1{`RANDOM}};
- cmdq_1_st = _RAND_137[0:0];
- _RAND_138 = {1{`RANDOM}};
- cmdq_2_alu = _RAND_138[0:0];
- _RAND_139 = {1{`RANDOM}};
- cmdq_2_conv = _RAND_139[0:0];
- _RAND_140 = {1{`RANDOM}};
- cmdq_2_ldst = _RAND_140[0:0];
- _RAND_141 = {1{`RANDOM}};
- cmdq_2_ld = _RAND_141[0:0];
- _RAND_142 = {1{`RANDOM}};
- cmdq_2_st = _RAND_142[0:0];
- _RAND_143 = {1{`RANDOM}};
- cmdq_3_alu = _RAND_143[0:0];
- _RAND_144 = {1{`RANDOM}};
- cmdq_3_conv = _RAND_144[0:0];
- _RAND_145 = {1{`RANDOM}};
- cmdq_3_ldst = _RAND_145[0:0];
- _RAND_146 = {1{`RANDOM}};
- cmdq_3_ld = _RAND_146[0:0];
- _RAND_147 = {1{`RANDOM}};
- cmdq_3_st = _RAND_147[0:0];
- _RAND_148 = {2{`RANDOM}};
- actv2_0_ractive = _RAND_148[63:0];
- _RAND_149 = {4{`RANDOM}};
- actv2_0_wactive = _RAND_149[127:0];
- _RAND_150 = {2{`RANDOM}};
- actv2_1_ractive = _RAND_150[63:0];
- _RAND_151 = {4{`RANDOM}};
- actv2_1_wactive = _RAND_151[127:0];
- _RAND_152 = {2{`RANDOM}};
- actv2_2_ractive = _RAND_152[63:0];
- _RAND_153 = {4{`RANDOM}};
- actv2_2_wactive = _RAND_153[127:0];
- _RAND_154 = {2{`RANDOM}};
- actv2_3_ractive = _RAND_154[63:0];
- _RAND_155 = {4{`RANDOM}};
- actv2_3_wactive = _RAND_155[127:0];
- _RAND_156 = {2{`RANDOM}};
- tag0 = _RAND_156[63:0];
- _RAND_157 = {1{`RANDOM}};
- nempty = _RAND_157[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- valid_0 = 1'h0;
- end
- if (reset) begin
- valid_1 = 1'h0;
- end
- if (reset) begin
- valid_2 = 1'h0;
- end
- if (reset) begin
- valid_3 = 1'h0;
- end
- if (reset) begin
- tag0 = 64'h0;
- end
- if (reset) begin
- nempty = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Fifo4e(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_tin_op,
- input [2:0] io_in_bits_0_bits_tin_f2,
- input [2:0] io_in_bits_0_bits_tin_sz,
- input [5:0] io_in_bits_0_bits_tin_vd_addr,
- input [5:0] io_in_bits_0_bits_tin_ve_addr,
- input io_in_bits_0_bits_tin_vs_valid,
- input [5:0] io_in_bits_0_bits_tin_vs_addr,
- input [3:0] io_in_bits_0_bits_tin_vs_tag,
- input io_in_bits_0_bits_tin_vt_valid,
- input [5:0] io_in_bits_0_bits_tin_vt_addr,
- input [3:0] io_in_bits_0_bits_tin_vt_tag,
- input io_in_bits_0_bits_tin_vu_valid,
- input [5:0] io_in_bits_0_bits_tin_vu_addr,
- input [3:0] io_in_bits_0_bits_tin_vu_tag,
- input io_in_bits_0_bits_tin_sv_valid,
- input [31:0] io_in_bits_0_bits_tin_sv_data,
- input io_in_bits_0_bits_tin_cmdsync,
- input io_in_bits_0_bits_m,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_tin_op,
- input [2:0] io_in_bits_1_bits_tin_f2,
- input [2:0] io_in_bits_1_bits_tin_sz,
- input [5:0] io_in_bits_1_bits_tin_vd_addr,
- input [5:0] io_in_bits_1_bits_tin_ve_addr,
- input io_in_bits_1_bits_tin_vs_valid,
- input [5:0] io_in_bits_1_bits_tin_vs_addr,
- input [3:0] io_in_bits_1_bits_tin_vs_tag,
- input io_in_bits_1_bits_tin_vt_valid,
- input [5:0] io_in_bits_1_bits_tin_vt_addr,
- input [3:0] io_in_bits_1_bits_tin_vt_tag,
- input io_in_bits_1_bits_tin_vu_valid,
- input [5:0] io_in_bits_1_bits_tin_vu_addr,
- input [3:0] io_in_bits_1_bits_tin_vu_tag,
- input io_in_bits_1_bits_tin_sv_valid,
- input [31:0] io_in_bits_1_bits_tin_sv_data,
- input io_in_bits_1_bits_tin_cmdsync,
- input io_in_bits_1_bits_m,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_tin_op,
- input [2:0] io_in_bits_2_bits_tin_f2,
- input [2:0] io_in_bits_2_bits_tin_sz,
- input [5:0] io_in_bits_2_bits_tin_vd_addr,
- input [5:0] io_in_bits_2_bits_tin_ve_addr,
- input io_in_bits_2_bits_tin_vs_valid,
- input [5:0] io_in_bits_2_bits_tin_vs_addr,
- input [3:0] io_in_bits_2_bits_tin_vs_tag,
- input io_in_bits_2_bits_tin_vt_valid,
- input [5:0] io_in_bits_2_bits_tin_vt_addr,
- input [3:0] io_in_bits_2_bits_tin_vt_tag,
- input io_in_bits_2_bits_tin_vu_valid,
- input [5:0] io_in_bits_2_bits_tin_vu_addr,
- input [3:0] io_in_bits_2_bits_tin_vu_tag,
- input io_in_bits_2_bits_tin_sv_valid,
- input [31:0] io_in_bits_2_bits_tin_sv_data,
- input io_in_bits_2_bits_tin_cmdsync,
- input io_in_bits_2_bits_m,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_tin_op,
- input [2:0] io_in_bits_3_bits_tin_f2,
- input [2:0] io_in_bits_3_bits_tin_sz,
- input [5:0] io_in_bits_3_bits_tin_vd_addr,
- input [5:0] io_in_bits_3_bits_tin_ve_addr,
- input io_in_bits_3_bits_tin_vs_valid,
- input [5:0] io_in_bits_3_bits_tin_vs_addr,
- input [3:0] io_in_bits_3_bits_tin_vs_tag,
- input io_in_bits_3_bits_tin_vt_valid,
- input [5:0] io_in_bits_3_bits_tin_vt_addr,
- input [3:0] io_in_bits_3_bits_tin_vt_tag,
- input io_in_bits_3_bits_tin_vu_valid,
- input [5:0] io_in_bits_3_bits_tin_vu_addr,
- input [3:0] io_in_bits_3_bits_tin_vu_tag,
- input io_in_bits_3_bits_tin_sv_valid,
- input [31:0] io_in_bits_3_bits_tin_sv_data,
- input io_in_bits_3_bits_tin_cmdsync,
- input io_in_bits_3_bits_m,
- input io_out_ready,
- output io_out_valid,
- output [6:0] io_out_bits_tin_op,
- output [2:0] io_out_bits_tin_f2,
- output [2:0] io_out_bits_tin_sz,
- output [5:0] io_out_bits_tin_vd_addr,
- output [5:0] io_out_bits_tin_ve_addr,
- output io_out_bits_tin_vs_valid,
- output [5:0] io_out_bits_tin_vs_addr,
- output [3:0] io_out_bits_tin_vs_tag,
- output io_out_bits_tin_vt_valid,
- output [5:0] io_out_bits_tin_vt_addr,
- output [3:0] io_out_bits_tin_vt_tag,
- output io_out_bits_tin_vu_valid,
- output [5:0] io_out_bits_tin_vu_addr,
- output [3:0] io_out_bits_tin_vu_tag,
- output io_out_bits_tin_sv_valid,
- output [31:0] io_out_bits_tin_sv_data,
- output io_out_bits_tin_cmdsync,
- output io_out_bits_m,
- output io_entry_0_valid,
- output io_entry_0_bits_tin_vs_valid,
- output [5:0] io_entry_0_bits_tin_vs_addr,
- output io_entry_0_bits_tin_vt_valid,
- output [5:0] io_entry_0_bits_tin_vt_addr,
- output io_entry_0_bits_tin_vu_valid,
- output [5:0] io_entry_0_bits_tin_vu_addr,
- output io_entry_0_bits_m,
- output io_entry_1_valid,
- output io_entry_1_bits_tin_vs_valid,
- output [5:0] io_entry_1_bits_tin_vs_addr,
- output io_entry_1_bits_tin_vt_valid,
- output [5:0] io_entry_1_bits_tin_vt_addr,
- output io_entry_1_bits_tin_vu_valid,
- output [5:0] io_entry_1_bits_tin_vu_addr,
- output io_entry_1_bits_m,
- output io_entry_2_valid,
- output io_entry_2_bits_tin_vs_valid,
- output [5:0] io_entry_2_bits_tin_vs_addr,
- output io_entry_2_bits_tin_vt_valid,
- output [5:0] io_entry_2_bits_tin_vt_addr,
- output io_entry_2_bits_tin_vu_valid,
- output [5:0] io_entry_2_bits_tin_vu_addr,
- output io_entry_2_bits_m,
- output io_entry_3_valid,
- output io_entry_3_bits_tin_vs_valid,
- output [5:0] io_entry_3_bits_tin_vs_addr,
- output io_entry_3_bits_tin_vt_valid,
- output [5:0] io_entry_3_bits_tin_vt_addr,
- output io_entry_3_bits_tin_vu_valid,
- output [5:0] io_entry_3_bits_tin_vu_addr,
- output io_entry_3_bits_m,
- output io_entry_4_valid,
- output io_entry_4_bits_tin_vs_valid,
- output [5:0] io_entry_4_bits_tin_vs_addr,
- output io_entry_4_bits_tin_vt_valid,
- output [5:0] io_entry_4_bits_tin_vt_addr,
- output io_entry_4_bits_tin_vu_valid,
- output [5:0] io_entry_4_bits_tin_vu_addr,
- output io_entry_4_bits_m,
- output io_entry_5_valid,
- output io_entry_5_bits_tin_vs_valid,
- output [5:0] io_entry_5_bits_tin_vs_addr,
- output io_entry_5_bits_tin_vt_valid,
- output [5:0] io_entry_5_bits_tin_vt_addr,
- output io_entry_5_bits_tin_vu_valid,
- output [5:0] io_entry_5_bits_tin_vu_addr,
- output io_entry_5_bits_m,
- output io_entry_6_valid,
- output io_entry_6_bits_tin_vs_valid,
- output [5:0] io_entry_6_bits_tin_vs_addr,
- output io_entry_6_bits_tin_vt_valid,
- output [5:0] io_entry_6_bits_tin_vt_addr,
- output io_entry_6_bits_tin_vu_valid,
- output [5:0] io_entry_6_bits_tin_vu_addr,
- output io_entry_6_bits_m,
- output io_entry_7_valid,
- output io_entry_7_bits_tin_vs_valid,
- output [5:0] io_entry_7_bits_tin_vs_addr,
- output io_entry_7_bits_tin_vt_valid,
- output [5:0] io_entry_7_bits_tin_vt_addr,
- output io_entry_7_bits_tin_vu_valid,
- output [5:0] io_entry_7_bits_tin_vu_addr,
- output io_entry_7_bits_m
-);
-`ifdef RANDOMIZE_MEM_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
-`endif // RANDOMIZE_REG_INIT
- reg [6:0] mem_tin_op [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [2:0] mem_tin_f2 [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_f2_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_f2_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [2:0] mem_tin_sz [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sz_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sz_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [5:0] mem_tin_vd_addr [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [5:0] mem_tin_ve_addr [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_ve_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_ve_addr_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_ve_addr_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg mem_tin_vs_valid [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [5:0] mem_tin_vs_addr [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [3:0] mem_tin_vs_tag [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg mem_tin_vt_valid [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_valid_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_valid_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [5:0] mem_tin_vt_addr [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vt_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_addr_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_addr_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [3:0] mem_tin_vt_tag [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vt_tag_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vt_tag_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vt_tag_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg mem_tin_vu_valid [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_valid_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_valid_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [5:0] mem_tin_vu_addr [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vu_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_addr_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_addr_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [3:0] mem_tin_vu_tag [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vu_tag_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vu_tag_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vu_tag_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg mem_tin_sv_valid [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_valid_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_valid_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [31:0] mem_tin_sv_data [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_sv_data_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_sv_data_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_sv_data_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg mem_tin_cmdsync [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_cmdsync_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_cmdsync_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg mem_m [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_m_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [2:0] in0pos; // @[Fifo4e.scala 45:23]
- reg [2:0] in1pos; // @[Fifo4e.scala 46:23]
- reg [2:0] in2pos; // @[Fifo4e.scala 47:23]
- reg [2:0] in3pos; // @[Fifo4e.scala 48:23]
- reg [2:0] outpos; // @[Fifo4e.scala 49:23]
- reg [3:0] mcount; // @[Fifo4e.scala 50:23]
- wire ivalid = io_in_valid & io_in_ready; // @[Fifo4e.scala 56:28]
- wire dec = io_out_valid & io_out_ready; // @[Fifo4e.scala 57:29]
- wire [3:0] iactive = {io_in_bits_3_valid,io_in_bits_2_valid,io_in_bits_1_valid,io_in_bits_0_valid}; // @[Cat.scala 31:58]
- wire [1:0] _icount_T = io_in_bits_0_valid + io_in_bits_1_valid; // @[Fifo4e.scala 62:36]
- wire [1:0] _GEN_2682 = {{1'd0}, io_in_bits_2_valid}; // @[Fifo4e.scala 62:59]
- wire [1:0] _icount_T_2 = _icount_T + _GEN_2682; // @[Fifo4e.scala 62:59]
- wire [1:0] _GEN_2683 = {{1'd0}, io_in_bits_3_valid}; // @[Fifo4e.scala 63:36]
- wire [2:0] icount = _icount_T_2 + _GEN_2683; // @[Fifo4e.scala 63:36]
- wire [3:0] in0pos_c = in0pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in0pos_d_T_2 = in0pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in0pos_d_T_3 = in0pos_c < 4'h8 ? in0pos_c : _in0pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in0pos_d = _in0pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] in1pos_c = in1pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in1pos_d_T_2 = in1pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in1pos_d_T_3 = in1pos_c < 4'h8 ? in1pos_c : _in1pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in1pos_d = _in1pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] in2pos_c = in2pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in2pos_d_T_2 = in2pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in2pos_d_T_3 = in2pos_c < 4'h8 ? in2pos_c : _in2pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in2pos_d = _in2pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] in3pos_c = in3pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in3pos_d_T_2 = in3pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in3pos_d_T_3 = in3pos_c < 4'h8 ? in3pos_c : _in3pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in3pos_d = _in3pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] outpos_c = outpos + 3'h1; // @[Fifo4e.scala 38:15]
- wire [3:0] _outpos_d_T_2 = outpos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _outpos_d_T_3 = outpos_c < 4'h8 ? outpos_c : _outpos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] outpos_d = _outpos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [2:0] inc = ivalid ? icount : 3'h0; // @[Library.scala 22:8]
- wire _T = ivalid | dec; // @[Fifo4e.scala 81:16]
- wire [3:0] _GEN_2684 = {{1'd0}, inc}; // @[Fifo4e.scala 82:27]
- wire [3:0] _nxtcount_T_1 = mcount + _GEN_2684; // @[Fifo4e.scala 82:27]
- wire [3:0] _GEN_2685 = {{3'd0}, dec}; // @[Fifo4e.scala 82:33]
- wire [3:0] nxtcount = _nxtcount_T_1 - _GEN_2685; // @[Fifo4e.scala 82:33]
- wire _in0_T_1 = iactive == 4'h8; // @[Fifo4.scala 31:27]
- wire _in0_T_3 = iactive[2:0] == 3'h4; // @[Fifo4.scala 32:27]
- wire _in0_T_5 = iactive[1:0] == 2'h2; // @[Fifo4.scala 33:27]
- wire [3:0] in0valid = {_in0_T_1,_in0_T_3,_in0_T_5,iactive[0]}; // @[Cat.scala 31:58]
- wire _in1_T_3 = iactive == 4'ha; // @[Fifo4.scala 37:27]
- wire _in1_T_4 = iactive == 4'hc | _in1_T_3; // @[Fifo4.scala 36:36]
- wire _in1_T_6 = iactive == 4'h9; // @[Fifo4.scala 38:27]
- wire _in1_T_7 = _in1_T_4 | _in1_T_6; // @[Fifo4.scala 37:36]
- wire _in1_T_11 = iactive[2:0] == 3'h5; // @[Fifo4.scala 40:27]
- wire _in1_T_12 = iactive[2:0] == 3'h6 | _in1_T_11; // @[Fifo4.scala 39:35]
- wire _in1_T_14 = iactive[1:0] == 2'h3; // @[Fifo4.scala 41:27]
- wire [3:0] in1valid = {_in1_T_7,_in1_T_12,_in1_T_14,1'h0}; // @[Cat.scala 31:58]
- wire _in2_T_3 = iactive == 4'hd; // @[Fifo4.scala 45:27]
- wire _in2_T_4 = iactive == 4'he | _in2_T_3; // @[Fifo4.scala 44:36]
- wire _in2_T_6 = iactive == 4'hb; // @[Fifo4.scala 46:27]
- wire _in2_T_7 = _in2_T_4 | _in2_T_6; // @[Fifo4.scala 45:36]
- wire [3:0] _GEN_2686 = {{1'd0}, iactive[2:0]}; // @[Fifo4.scala 47:27]
- wire _in2_T_11 = iactive[2:0] == 3'h7; // @[Fifo4.scala 48:27]
- wire _in2_T_12 = _GEN_2686 == 4'hf | _in2_T_11; // @[Fifo4.scala 47:36]
- wire [3:0] in2valid = {_in2_T_7,_in2_T_12,2'h0}; // @[Cat.scala 31:58]
- wire _in3_T_1 = iactive == 4'hf; // @[Fifo4.scala 51:27]
- wire [3:0] in3valid = {_in3_T_1,1'h0,2'h0}; // @[Cat.scala 31:58]
- wire _valid_T = in0pos == 3'h0; // @[Fifo4e.scala 92:28]
- wire _valid_T_3 = in1pos == 3'h0; // @[Fifo4e.scala 93:28]
- wire _valid_T_5 = in1pos == 3'h0 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_6 = in0pos == 3'h0 & in0valid[3] | _valid_T_5; // @[Fifo4e.scala 92:51]
- wire _valid_T_7 = in2pos == 3'h0; // @[Fifo4e.scala 94:28]
- wire _valid_T_9 = in2pos == 3'h0 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_10 = _valid_T_6 | _valid_T_9; // @[Fifo4e.scala 93:51]
- wire _valid_T_13 = in3pos == 3'h0 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_14 = _valid_T_10 | _valid_T_13; // @[Fifo4e.scala 94:51]
- wire _valid_T_20 = _valid_T_3 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_21 = _valid_T & in0valid[2] | _valid_T_20; // @[Fifo4e.scala 96:51]
- wire _valid_T_24 = _valid_T_7 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_25 = _valid_T_21 | _valid_T_24; // @[Fifo4e.scala 97:51]
- wire _valid_T_31 = _valid_T_3 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_32 = _valid_T & in0valid[1] | _valid_T_31; // @[Fifo4e.scala 99:51]
- wire _valid_T_35 = _valid_T & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid = {_valid_T_14,_valid_T_25,_valid_T_32,_valid_T_35}; // @[Cat.scala 31:58]
- wire _GEN_57 = valid[2] ? 1'h0 : valid[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_105 = valid[1] ? 1'h0 : valid[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_129 = valid[1] ? 1'h0 : _GEN_57; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_177 = valid[0] ? 1'h0 : valid[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_201 = valid[0] ? 1'h0 : _GEN_105; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_225 = valid[0] ? 1'h0 : _GEN_129; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_36 = in0pos == 3'h1; // @[Fifo4e.scala 92:28]
- wire _valid_T_39 = in1pos == 3'h1; // @[Fifo4e.scala 93:28]
- wire _valid_T_41 = in1pos == 3'h1 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_42 = in0pos == 3'h1 & in0valid[3] | _valid_T_41; // @[Fifo4e.scala 92:51]
- wire _valid_T_43 = in2pos == 3'h1; // @[Fifo4e.scala 94:28]
- wire _valid_T_45 = in2pos == 3'h1 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_46 = _valid_T_42 | _valid_T_45; // @[Fifo4e.scala 93:51]
- wire _valid_T_49 = in3pos == 3'h1 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_50 = _valid_T_46 | _valid_T_49; // @[Fifo4e.scala 94:51]
- wire _valid_T_56 = _valid_T_39 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_57 = _valid_T_36 & in0valid[2] | _valid_T_56; // @[Fifo4e.scala 96:51]
- wire _valid_T_60 = _valid_T_43 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_61 = _valid_T_57 | _valid_T_60; // @[Fifo4e.scala 97:51]
- wire _valid_T_67 = _valid_T_39 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_68 = _valid_T_36 & in0valid[1] | _valid_T_67; // @[Fifo4e.scala 99:51]
- wire _valid_T_71 = _valid_T_36 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_1 = {_valid_T_50,_valid_T_61,_valid_T_68,_valid_T_71}; // @[Cat.scala 31:58]
- wire _GEN_391 = valid_1[2] ? 1'h0 : valid_1[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_437 = valid_1[1] ? 1'h0 : valid_1[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_460 = valid_1[1] ? 1'h0 : _GEN_391; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_506 = valid_1[0] ? 1'h0 : valid_1[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_529 = valid_1[0] ? 1'h0 : _GEN_437; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_552 = valid_1[0] ? 1'h0 : _GEN_460; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_72 = in0pos == 3'h2; // @[Fifo4e.scala 92:28]
- wire _valid_T_75 = in1pos == 3'h2; // @[Fifo4e.scala 93:28]
- wire _valid_T_77 = in1pos == 3'h2 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_78 = in0pos == 3'h2 & in0valid[3] | _valid_T_77; // @[Fifo4e.scala 92:51]
- wire _valid_T_79 = in2pos == 3'h2; // @[Fifo4e.scala 94:28]
- wire _valid_T_81 = in2pos == 3'h2 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_82 = _valid_T_78 | _valid_T_81; // @[Fifo4e.scala 93:51]
- wire _valid_T_85 = in3pos == 3'h2 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_86 = _valid_T_82 | _valid_T_85; // @[Fifo4e.scala 94:51]
- wire _valid_T_92 = _valid_T_75 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_93 = _valid_T_72 & in0valid[2] | _valid_T_92; // @[Fifo4e.scala 96:51]
- wire _valid_T_96 = _valid_T_79 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_97 = _valid_T_93 | _valid_T_96; // @[Fifo4e.scala 97:51]
- wire _valid_T_103 = _valid_T_75 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_104 = _valid_T_72 & in0valid[1] | _valid_T_103; // @[Fifo4e.scala 99:51]
- wire _valid_T_107 = _valid_T_72 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_2 = {_valid_T_86,_valid_T_97,_valid_T_104,_valid_T_107}; // @[Cat.scala 31:58]
- wire _GEN_715 = valid_2[2] ? 1'h0 : valid_2[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_763 = valid_2[1] ? 1'h0 : valid_2[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_787 = valid_2[1] ? 1'h0 : _GEN_715; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_835 = valid_2[0] ? 1'h0 : valid_2[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_859 = valid_2[0] ? 1'h0 : _GEN_763; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_883 = valid_2[0] ? 1'h0 : _GEN_787; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_108 = in0pos == 3'h3; // @[Fifo4e.scala 92:28]
- wire _valid_T_111 = in1pos == 3'h3; // @[Fifo4e.scala 93:28]
- wire _valid_T_113 = in1pos == 3'h3 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_114 = in0pos == 3'h3 & in0valid[3] | _valid_T_113; // @[Fifo4e.scala 92:51]
- wire _valid_T_115 = in2pos == 3'h3; // @[Fifo4e.scala 94:28]
- wire _valid_T_117 = in2pos == 3'h3 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_118 = _valid_T_114 | _valid_T_117; // @[Fifo4e.scala 93:51]
- wire _valid_T_121 = in3pos == 3'h3 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_122 = _valid_T_118 | _valid_T_121; // @[Fifo4e.scala 94:51]
- wire _valid_T_128 = _valid_T_111 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_129 = _valid_T_108 & in0valid[2] | _valid_T_128; // @[Fifo4e.scala 96:51]
- wire _valid_T_132 = _valid_T_115 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_133 = _valid_T_129 | _valid_T_132; // @[Fifo4e.scala 97:51]
- wire _valid_T_139 = _valid_T_111 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_140 = _valid_T_108 & in0valid[1] | _valid_T_139; // @[Fifo4e.scala 99:51]
- wire _valid_T_143 = _valid_T_108 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_3 = {_valid_T_122,_valid_T_133,_valid_T_140,_valid_T_143}; // @[Cat.scala 31:58]
- wire _GEN_1051 = valid_3[2] ? 1'h0 : valid_3[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_1099 = valid_3[1] ? 1'h0 : valid_3[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1123 = valid_3[1] ? 1'h0 : _GEN_1051; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1171 = valid_3[0] ? 1'h0 : valid_3[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1195 = valid_3[0] ? 1'h0 : _GEN_1099; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1219 = valid_3[0] ? 1'h0 : _GEN_1123; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_144 = in0pos == 3'h4; // @[Fifo4e.scala 92:28]
- wire _valid_T_147 = in1pos == 3'h4; // @[Fifo4e.scala 93:28]
- wire _valid_T_149 = in1pos == 3'h4 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_150 = in0pos == 3'h4 & in0valid[3] | _valid_T_149; // @[Fifo4e.scala 92:51]
- wire _valid_T_151 = in2pos == 3'h4; // @[Fifo4e.scala 94:28]
- wire _valid_T_153 = in2pos == 3'h4 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_154 = _valid_T_150 | _valid_T_153; // @[Fifo4e.scala 93:51]
- wire _valid_T_157 = in3pos == 3'h4 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_158 = _valid_T_154 | _valid_T_157; // @[Fifo4e.scala 94:51]
- wire _valid_T_164 = _valid_T_147 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_165 = _valid_T_144 & in0valid[2] | _valid_T_164; // @[Fifo4e.scala 96:51]
- wire _valid_T_168 = _valid_T_151 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_169 = _valid_T_165 | _valid_T_168; // @[Fifo4e.scala 97:51]
- wire _valid_T_175 = _valid_T_147 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_176 = _valid_T_144 & in0valid[1] | _valid_T_175; // @[Fifo4e.scala 99:51]
- wire _valid_T_179 = _valid_T_144 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_4 = {_valid_T_158,_valid_T_169,_valid_T_176,_valid_T_179}; // @[Cat.scala 31:58]
- wire _GEN_1387 = valid_4[2] ? 1'h0 : valid_4[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_1435 = valid_4[1] ? 1'h0 : valid_4[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1459 = valid_4[1] ? 1'h0 : _GEN_1387; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1507 = valid_4[0] ? 1'h0 : valid_4[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1531 = valid_4[0] ? 1'h0 : _GEN_1435; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1555 = valid_4[0] ? 1'h0 : _GEN_1459; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_180 = in0pos == 3'h5; // @[Fifo4e.scala 92:28]
- wire _valid_T_183 = in1pos == 3'h5; // @[Fifo4e.scala 93:28]
- wire _valid_T_185 = in1pos == 3'h5 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_186 = in0pos == 3'h5 & in0valid[3] | _valid_T_185; // @[Fifo4e.scala 92:51]
- wire _valid_T_187 = in2pos == 3'h5; // @[Fifo4e.scala 94:28]
- wire _valid_T_189 = in2pos == 3'h5 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_190 = _valid_T_186 | _valid_T_189; // @[Fifo4e.scala 93:51]
- wire _valid_T_193 = in3pos == 3'h5 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_194 = _valid_T_190 | _valid_T_193; // @[Fifo4e.scala 94:51]
- wire _valid_T_200 = _valid_T_183 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_201 = _valid_T_180 & in0valid[2] | _valid_T_200; // @[Fifo4e.scala 96:51]
- wire _valid_T_204 = _valid_T_187 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_205 = _valid_T_201 | _valid_T_204; // @[Fifo4e.scala 97:51]
- wire _valid_T_211 = _valid_T_183 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_212 = _valid_T_180 & in0valid[1] | _valid_T_211; // @[Fifo4e.scala 99:51]
- wire _valid_T_215 = _valid_T_180 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_5 = {_valid_T_194,_valid_T_205,_valid_T_212,_valid_T_215}; // @[Cat.scala 31:58]
- wire _GEN_1723 = valid_5[2] ? 1'h0 : valid_5[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_1771 = valid_5[1] ? 1'h0 : valid_5[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1795 = valid_5[1] ? 1'h0 : _GEN_1723; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1843 = valid_5[0] ? 1'h0 : valid_5[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1867 = valid_5[0] ? 1'h0 : _GEN_1771; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1891 = valid_5[0] ? 1'h0 : _GEN_1795; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_216 = in0pos == 3'h6; // @[Fifo4e.scala 92:28]
- wire _valid_T_219 = in1pos == 3'h6; // @[Fifo4e.scala 93:28]
- wire _valid_T_221 = in1pos == 3'h6 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_222 = in0pos == 3'h6 & in0valid[3] | _valid_T_221; // @[Fifo4e.scala 92:51]
- wire _valid_T_223 = in2pos == 3'h6; // @[Fifo4e.scala 94:28]
- wire _valid_T_225 = in2pos == 3'h6 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_226 = _valid_T_222 | _valid_T_225; // @[Fifo4e.scala 93:51]
- wire _valid_T_229 = in3pos == 3'h6 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_230 = _valid_T_226 | _valid_T_229; // @[Fifo4e.scala 94:51]
- wire _valid_T_236 = _valid_T_219 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_237 = _valid_T_216 & in0valid[2] | _valid_T_236; // @[Fifo4e.scala 96:51]
- wire _valid_T_240 = _valid_T_223 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_241 = _valid_T_237 | _valid_T_240; // @[Fifo4e.scala 97:51]
- wire _valid_T_247 = _valid_T_219 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_248 = _valid_T_216 & in0valid[1] | _valid_T_247; // @[Fifo4e.scala 99:51]
- wire _valid_T_251 = _valid_T_216 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_6 = {_valid_T_230,_valid_T_241,_valid_T_248,_valid_T_251}; // @[Cat.scala 31:58]
- wire _GEN_2059 = valid_6[2] ? 1'h0 : valid_6[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_2107 = valid_6[1] ? 1'h0 : valid_6[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_2131 = valid_6[1] ? 1'h0 : _GEN_2059; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_2179 = valid_6[0] ? 1'h0 : valid_6[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_2203 = valid_6[0] ? 1'h0 : _GEN_2107; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_2227 = valid_6[0] ? 1'h0 : _GEN_2131; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_252 = in0pos == 3'h7; // @[Fifo4e.scala 92:28]
- wire _valid_T_255 = in1pos == 3'h7; // @[Fifo4e.scala 93:28]
- wire _valid_T_257 = in1pos == 3'h7 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_258 = in0pos == 3'h7 & in0valid[3] | _valid_T_257; // @[Fifo4e.scala 92:51]
- wire _valid_T_259 = in2pos == 3'h7; // @[Fifo4e.scala 94:28]
- wire _valid_T_261 = in2pos == 3'h7 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_262 = _valid_T_258 | _valid_T_261; // @[Fifo4e.scala 93:51]
- wire _valid_T_265 = in3pos == 3'h7 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_266 = _valid_T_262 | _valid_T_265; // @[Fifo4e.scala 94:51]
- wire _valid_T_272 = _valid_T_255 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_273 = _valid_T_252 & in0valid[2] | _valid_T_272; // @[Fifo4e.scala 96:51]
- wire _valid_T_276 = _valid_T_259 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_277 = _valid_T_273 | _valid_T_276; // @[Fifo4e.scala 97:51]
- wire _valid_T_283 = _valid_T_255 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_284 = _valid_T_252 & in0valid[1] | _valid_T_283; // @[Fifo4e.scala 99:51]
- wire _valid_T_287 = _valid_T_252 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_7 = {_valid_T_266,_valid_T_277,_valid_T_284,_valid_T_287}; // @[Cat.scala 31:58]
- wire _GEN_2395 = valid_7[2] ? 1'h0 : valid_7[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_2443 = valid_7[1] ? 1'h0 : valid_7[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_2467 = valid_7[1] ? 1'h0 : _GEN_2395; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_2515 = valid_7[0] ? 1'h0 : valid_7[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_2539 = valid_7[0] ? 1'h0 : _GEN_2443; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_2563 = valid_7[0] ? 1'h0 : _GEN_2467; // @[Fifo4e.scala 104:23 43:16]
- reg [7:0] active; // @[Fifo4e.scala 118:23]
- wire [7:0] _GEN_0 = {{7'd0}, icount >= 3'h1}; // @[Fifo4e.scala 121:24]
- wire [7:0] _activeSet_T_1 = _GEN_0 << in0pos; // @[Fifo4e.scala 121:24]
- wire [7:0] _GEN_1 = {{7'd0}, icount >= 3'h2}; // @[Fifo4e.scala 121:54]
- wire [7:0] _activeSet_T_3 = _GEN_1 << in1pos; // @[Fifo4e.scala 121:54]
- wire [7:0] _activeSet_T_4 = _activeSet_T_1 | _activeSet_T_3; // @[Fifo4e.scala 121:35]
- wire [7:0] _GEN_2 = {{7'd0}, icount >= 3'h3}; // @[Fifo4e.scala 122:24]
- wire [7:0] _activeSet_T_6 = _GEN_2 << in2pos; // @[Fifo4e.scala 122:24]
- wire [7:0] _activeSet_T_7 = _activeSet_T_4 | _activeSet_T_6; // @[Fifo4e.scala 121:65]
- wire [7:0] _GEN_3 = {{7'd0}, icount >= 3'h4}; // @[Fifo4e.scala 122:54]
- wire [7:0] _activeSet_T_9 = _GEN_3 << in3pos; // @[Fifo4e.scala 122:54]
- wire [7:0] _activeSet_T_10 = _activeSet_T_7 | _activeSet_T_9; // @[Fifo4e.scala 122:35]
- wire [7:0] activeSet = ivalid ? _activeSet_T_10 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _activeClr_T_1 = 8'h1 << outpos; // @[Fifo4e.scala 124:59]
- wire [7:0] activeClr = dec ? _activeClr_T_1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _active_T = active | activeSet; // @[Fifo4e.scala 127:23]
- wire [7:0] _active_T_1 = ~activeClr; // @[Fifo4e.scala 127:38]
- wire [7:0] _active_T_2 = _active_T & _active_T_1; // @[Fifo4e.scala 127:36]
- wire [3:0] _GEN_2687 = {{1'd0}, icount}; // @[Fifo4e.scala 132:33]
- wire [3:0] _io_in_ready_T_1 = 4'h8 - _GEN_2687; // @[Fifo4e.scala 132:33]
- assign mem_tin_op_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_op_io_out_bits_MPORT_data = mem_tin_op[mem_tin_op_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_op_io_entry_0_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_op_io_entry_1_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_op_io_entry_2_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_op_io_entry_3_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_op_io_entry_4_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_op_io_entry_5_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_op_io_entry_6_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_op_io_entry_7_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_MPORT_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_addr = 3'h0;
- assign mem_tin_op_MPORT_mask = 1'h1;
- assign mem_tin_op_MPORT_en = ivalid & valid[0];
- assign mem_tin_op_MPORT_1_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_1_addr = 3'h0;
- assign mem_tin_op_MPORT_1_mask = 1'h1;
- assign mem_tin_op_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_op_MPORT_2_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_2_addr = 3'h0;
- assign mem_tin_op_MPORT_2_mask = 1'h1;
- assign mem_tin_op_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_op_MPORT_3_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_3_addr = 3'h0;
- assign mem_tin_op_MPORT_3_mask = 1'h1;
- assign mem_tin_op_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_op_MPORT_4_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_4_addr = 3'h1;
- assign mem_tin_op_MPORT_4_mask = 1'h1;
- assign mem_tin_op_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_op_MPORT_5_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_5_addr = 3'h1;
- assign mem_tin_op_MPORT_5_mask = 1'h1;
- assign mem_tin_op_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_op_MPORT_6_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_6_addr = 3'h1;
- assign mem_tin_op_MPORT_6_mask = 1'h1;
- assign mem_tin_op_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_op_MPORT_7_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_7_addr = 3'h1;
- assign mem_tin_op_MPORT_7_mask = 1'h1;
- assign mem_tin_op_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_op_MPORT_8_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_8_addr = 3'h2;
- assign mem_tin_op_MPORT_8_mask = 1'h1;
- assign mem_tin_op_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_op_MPORT_9_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_9_addr = 3'h2;
- assign mem_tin_op_MPORT_9_mask = 1'h1;
- assign mem_tin_op_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_op_MPORT_10_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_10_addr = 3'h2;
- assign mem_tin_op_MPORT_10_mask = 1'h1;
- assign mem_tin_op_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_op_MPORT_11_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_11_addr = 3'h2;
- assign mem_tin_op_MPORT_11_mask = 1'h1;
- assign mem_tin_op_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_op_MPORT_12_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_12_addr = 3'h3;
- assign mem_tin_op_MPORT_12_mask = 1'h1;
- assign mem_tin_op_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_op_MPORT_13_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_13_addr = 3'h3;
- assign mem_tin_op_MPORT_13_mask = 1'h1;
- assign mem_tin_op_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_op_MPORT_14_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_14_addr = 3'h3;
- assign mem_tin_op_MPORT_14_mask = 1'h1;
- assign mem_tin_op_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_op_MPORT_15_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_15_addr = 3'h3;
- assign mem_tin_op_MPORT_15_mask = 1'h1;
- assign mem_tin_op_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_op_MPORT_16_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_16_addr = 3'h4;
- assign mem_tin_op_MPORT_16_mask = 1'h1;
- assign mem_tin_op_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_op_MPORT_17_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_17_addr = 3'h4;
- assign mem_tin_op_MPORT_17_mask = 1'h1;
- assign mem_tin_op_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_op_MPORT_18_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_18_addr = 3'h4;
- assign mem_tin_op_MPORT_18_mask = 1'h1;
- assign mem_tin_op_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_op_MPORT_19_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_19_addr = 3'h4;
- assign mem_tin_op_MPORT_19_mask = 1'h1;
- assign mem_tin_op_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_op_MPORT_20_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_20_addr = 3'h5;
- assign mem_tin_op_MPORT_20_mask = 1'h1;
- assign mem_tin_op_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_op_MPORT_21_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_21_addr = 3'h5;
- assign mem_tin_op_MPORT_21_mask = 1'h1;
- assign mem_tin_op_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_op_MPORT_22_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_22_addr = 3'h5;
- assign mem_tin_op_MPORT_22_mask = 1'h1;
- assign mem_tin_op_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_op_MPORT_23_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_23_addr = 3'h5;
- assign mem_tin_op_MPORT_23_mask = 1'h1;
- assign mem_tin_op_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_op_MPORT_24_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_24_addr = 3'h6;
- assign mem_tin_op_MPORT_24_mask = 1'h1;
- assign mem_tin_op_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_op_MPORT_25_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_25_addr = 3'h6;
- assign mem_tin_op_MPORT_25_mask = 1'h1;
- assign mem_tin_op_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_op_MPORT_26_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_26_addr = 3'h6;
- assign mem_tin_op_MPORT_26_mask = 1'h1;
- assign mem_tin_op_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_op_MPORT_27_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_27_addr = 3'h6;
- assign mem_tin_op_MPORT_27_mask = 1'h1;
- assign mem_tin_op_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_op_MPORT_28_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_28_addr = 3'h7;
- assign mem_tin_op_MPORT_28_mask = 1'h1;
- assign mem_tin_op_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_op_MPORT_29_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_29_addr = 3'h7;
- assign mem_tin_op_MPORT_29_mask = 1'h1;
- assign mem_tin_op_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_op_MPORT_30_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_30_addr = 3'h7;
- assign mem_tin_op_MPORT_30_mask = 1'h1;
- assign mem_tin_op_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_op_MPORT_31_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_31_addr = 3'h7;
- assign mem_tin_op_MPORT_31_mask = 1'h1;
- assign mem_tin_op_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_f2_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_f2_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_f2_io_out_bits_MPORT_data = mem_tin_f2[mem_tin_f2_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_f2_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_f2_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_f2_io_entry_0_bits_MPORT_data = mem_tin_f2[mem_tin_f2_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_f2_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_f2_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_f2_io_entry_1_bits_MPORT_data = mem_tin_f2[mem_tin_f2_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_f2_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_f2_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_f2_io_entry_2_bits_MPORT_data = mem_tin_f2[mem_tin_f2_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_f2_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_f2_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_f2_io_entry_3_bits_MPORT_data = mem_tin_f2[mem_tin_f2_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_f2_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_f2_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_f2_io_entry_4_bits_MPORT_data = mem_tin_f2[mem_tin_f2_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_f2_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_f2_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_f2_io_entry_5_bits_MPORT_data = mem_tin_f2[mem_tin_f2_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_f2_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_f2_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_f2_io_entry_6_bits_MPORT_data = mem_tin_f2[mem_tin_f2_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_f2_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_f2_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_f2_io_entry_7_bits_MPORT_data = mem_tin_f2[mem_tin_f2_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_f2_MPORT_data = io_in_bits_0_bits_tin_f2;
- assign mem_tin_f2_MPORT_addr = 3'h0;
- assign mem_tin_f2_MPORT_mask = 1'h1;
- assign mem_tin_f2_MPORT_en = ivalid & valid[0];
- assign mem_tin_f2_MPORT_1_data = io_in_bits_1_bits_tin_f2;
- assign mem_tin_f2_MPORT_1_addr = 3'h0;
- assign mem_tin_f2_MPORT_1_mask = 1'h1;
- assign mem_tin_f2_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_f2_MPORT_2_data = io_in_bits_2_bits_tin_f2;
- assign mem_tin_f2_MPORT_2_addr = 3'h0;
- assign mem_tin_f2_MPORT_2_mask = 1'h1;
- assign mem_tin_f2_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_f2_MPORT_3_data = io_in_bits_3_bits_tin_f2;
- assign mem_tin_f2_MPORT_3_addr = 3'h0;
- assign mem_tin_f2_MPORT_3_mask = 1'h1;
- assign mem_tin_f2_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_f2_MPORT_4_data = io_in_bits_0_bits_tin_f2;
- assign mem_tin_f2_MPORT_4_addr = 3'h1;
- assign mem_tin_f2_MPORT_4_mask = 1'h1;
- assign mem_tin_f2_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_f2_MPORT_5_data = io_in_bits_1_bits_tin_f2;
- assign mem_tin_f2_MPORT_5_addr = 3'h1;
- assign mem_tin_f2_MPORT_5_mask = 1'h1;
- assign mem_tin_f2_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_f2_MPORT_6_data = io_in_bits_2_bits_tin_f2;
- assign mem_tin_f2_MPORT_6_addr = 3'h1;
- assign mem_tin_f2_MPORT_6_mask = 1'h1;
- assign mem_tin_f2_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_f2_MPORT_7_data = io_in_bits_3_bits_tin_f2;
- assign mem_tin_f2_MPORT_7_addr = 3'h1;
- assign mem_tin_f2_MPORT_7_mask = 1'h1;
- assign mem_tin_f2_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_f2_MPORT_8_data = io_in_bits_0_bits_tin_f2;
- assign mem_tin_f2_MPORT_8_addr = 3'h2;
- assign mem_tin_f2_MPORT_8_mask = 1'h1;
- assign mem_tin_f2_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_f2_MPORT_9_data = io_in_bits_1_bits_tin_f2;
- assign mem_tin_f2_MPORT_9_addr = 3'h2;
- assign mem_tin_f2_MPORT_9_mask = 1'h1;
- assign mem_tin_f2_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_f2_MPORT_10_data = io_in_bits_2_bits_tin_f2;
- assign mem_tin_f2_MPORT_10_addr = 3'h2;
- assign mem_tin_f2_MPORT_10_mask = 1'h1;
- assign mem_tin_f2_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_f2_MPORT_11_data = io_in_bits_3_bits_tin_f2;
- assign mem_tin_f2_MPORT_11_addr = 3'h2;
- assign mem_tin_f2_MPORT_11_mask = 1'h1;
- assign mem_tin_f2_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_f2_MPORT_12_data = io_in_bits_0_bits_tin_f2;
- assign mem_tin_f2_MPORT_12_addr = 3'h3;
- assign mem_tin_f2_MPORT_12_mask = 1'h1;
- assign mem_tin_f2_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_f2_MPORT_13_data = io_in_bits_1_bits_tin_f2;
- assign mem_tin_f2_MPORT_13_addr = 3'h3;
- assign mem_tin_f2_MPORT_13_mask = 1'h1;
- assign mem_tin_f2_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_f2_MPORT_14_data = io_in_bits_2_bits_tin_f2;
- assign mem_tin_f2_MPORT_14_addr = 3'h3;
- assign mem_tin_f2_MPORT_14_mask = 1'h1;
- assign mem_tin_f2_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_f2_MPORT_15_data = io_in_bits_3_bits_tin_f2;
- assign mem_tin_f2_MPORT_15_addr = 3'h3;
- assign mem_tin_f2_MPORT_15_mask = 1'h1;
- assign mem_tin_f2_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_f2_MPORT_16_data = io_in_bits_0_bits_tin_f2;
- assign mem_tin_f2_MPORT_16_addr = 3'h4;
- assign mem_tin_f2_MPORT_16_mask = 1'h1;
- assign mem_tin_f2_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_f2_MPORT_17_data = io_in_bits_1_bits_tin_f2;
- assign mem_tin_f2_MPORT_17_addr = 3'h4;
- assign mem_tin_f2_MPORT_17_mask = 1'h1;
- assign mem_tin_f2_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_f2_MPORT_18_data = io_in_bits_2_bits_tin_f2;
- assign mem_tin_f2_MPORT_18_addr = 3'h4;
- assign mem_tin_f2_MPORT_18_mask = 1'h1;
- assign mem_tin_f2_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_f2_MPORT_19_data = io_in_bits_3_bits_tin_f2;
- assign mem_tin_f2_MPORT_19_addr = 3'h4;
- assign mem_tin_f2_MPORT_19_mask = 1'h1;
- assign mem_tin_f2_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_f2_MPORT_20_data = io_in_bits_0_bits_tin_f2;
- assign mem_tin_f2_MPORT_20_addr = 3'h5;
- assign mem_tin_f2_MPORT_20_mask = 1'h1;
- assign mem_tin_f2_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_f2_MPORT_21_data = io_in_bits_1_bits_tin_f2;
- assign mem_tin_f2_MPORT_21_addr = 3'h5;
- assign mem_tin_f2_MPORT_21_mask = 1'h1;
- assign mem_tin_f2_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_f2_MPORT_22_data = io_in_bits_2_bits_tin_f2;
- assign mem_tin_f2_MPORT_22_addr = 3'h5;
- assign mem_tin_f2_MPORT_22_mask = 1'h1;
- assign mem_tin_f2_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_f2_MPORT_23_data = io_in_bits_3_bits_tin_f2;
- assign mem_tin_f2_MPORT_23_addr = 3'h5;
- assign mem_tin_f2_MPORT_23_mask = 1'h1;
- assign mem_tin_f2_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_f2_MPORT_24_data = io_in_bits_0_bits_tin_f2;
- assign mem_tin_f2_MPORT_24_addr = 3'h6;
- assign mem_tin_f2_MPORT_24_mask = 1'h1;
- assign mem_tin_f2_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_f2_MPORT_25_data = io_in_bits_1_bits_tin_f2;
- assign mem_tin_f2_MPORT_25_addr = 3'h6;
- assign mem_tin_f2_MPORT_25_mask = 1'h1;
- assign mem_tin_f2_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_f2_MPORT_26_data = io_in_bits_2_bits_tin_f2;
- assign mem_tin_f2_MPORT_26_addr = 3'h6;
- assign mem_tin_f2_MPORT_26_mask = 1'h1;
- assign mem_tin_f2_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_f2_MPORT_27_data = io_in_bits_3_bits_tin_f2;
- assign mem_tin_f2_MPORT_27_addr = 3'h6;
- assign mem_tin_f2_MPORT_27_mask = 1'h1;
- assign mem_tin_f2_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_f2_MPORT_28_data = io_in_bits_0_bits_tin_f2;
- assign mem_tin_f2_MPORT_28_addr = 3'h7;
- assign mem_tin_f2_MPORT_28_mask = 1'h1;
- assign mem_tin_f2_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_f2_MPORT_29_data = io_in_bits_1_bits_tin_f2;
- assign mem_tin_f2_MPORT_29_addr = 3'h7;
- assign mem_tin_f2_MPORT_29_mask = 1'h1;
- assign mem_tin_f2_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_f2_MPORT_30_data = io_in_bits_2_bits_tin_f2;
- assign mem_tin_f2_MPORT_30_addr = 3'h7;
- assign mem_tin_f2_MPORT_30_mask = 1'h1;
- assign mem_tin_f2_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_f2_MPORT_31_data = io_in_bits_3_bits_tin_f2;
- assign mem_tin_f2_MPORT_31_addr = 3'h7;
- assign mem_tin_f2_MPORT_31_mask = 1'h1;
- assign mem_tin_f2_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_sz_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_sz_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_sz_io_out_bits_MPORT_data = mem_tin_sz[mem_tin_sz_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sz_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_sz_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_sz_io_entry_0_bits_MPORT_data = mem_tin_sz[mem_tin_sz_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sz_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_sz_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_sz_io_entry_1_bits_MPORT_data = mem_tin_sz[mem_tin_sz_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sz_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_sz_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_sz_io_entry_2_bits_MPORT_data = mem_tin_sz[mem_tin_sz_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sz_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_sz_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_sz_io_entry_3_bits_MPORT_data = mem_tin_sz[mem_tin_sz_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sz_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_sz_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_sz_io_entry_4_bits_MPORT_data = mem_tin_sz[mem_tin_sz_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sz_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_sz_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_sz_io_entry_5_bits_MPORT_data = mem_tin_sz[mem_tin_sz_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sz_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_sz_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_sz_io_entry_6_bits_MPORT_data = mem_tin_sz[mem_tin_sz_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sz_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_sz_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_sz_io_entry_7_bits_MPORT_data = mem_tin_sz[mem_tin_sz_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sz_MPORT_data = io_in_bits_0_bits_tin_sz;
- assign mem_tin_sz_MPORT_addr = 3'h0;
- assign mem_tin_sz_MPORT_mask = 1'h1;
- assign mem_tin_sz_MPORT_en = ivalid & valid[0];
- assign mem_tin_sz_MPORT_1_data = io_in_bits_1_bits_tin_sz;
- assign mem_tin_sz_MPORT_1_addr = 3'h0;
- assign mem_tin_sz_MPORT_1_mask = 1'h1;
- assign mem_tin_sz_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_sz_MPORT_2_data = io_in_bits_2_bits_tin_sz;
- assign mem_tin_sz_MPORT_2_addr = 3'h0;
- assign mem_tin_sz_MPORT_2_mask = 1'h1;
- assign mem_tin_sz_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_sz_MPORT_3_data = io_in_bits_3_bits_tin_sz;
- assign mem_tin_sz_MPORT_3_addr = 3'h0;
- assign mem_tin_sz_MPORT_3_mask = 1'h1;
- assign mem_tin_sz_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_sz_MPORT_4_data = io_in_bits_0_bits_tin_sz;
- assign mem_tin_sz_MPORT_4_addr = 3'h1;
- assign mem_tin_sz_MPORT_4_mask = 1'h1;
- assign mem_tin_sz_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_sz_MPORT_5_data = io_in_bits_1_bits_tin_sz;
- assign mem_tin_sz_MPORT_5_addr = 3'h1;
- assign mem_tin_sz_MPORT_5_mask = 1'h1;
- assign mem_tin_sz_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_sz_MPORT_6_data = io_in_bits_2_bits_tin_sz;
- assign mem_tin_sz_MPORT_6_addr = 3'h1;
- assign mem_tin_sz_MPORT_6_mask = 1'h1;
- assign mem_tin_sz_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_sz_MPORT_7_data = io_in_bits_3_bits_tin_sz;
- assign mem_tin_sz_MPORT_7_addr = 3'h1;
- assign mem_tin_sz_MPORT_7_mask = 1'h1;
- assign mem_tin_sz_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_sz_MPORT_8_data = io_in_bits_0_bits_tin_sz;
- assign mem_tin_sz_MPORT_8_addr = 3'h2;
- assign mem_tin_sz_MPORT_8_mask = 1'h1;
- assign mem_tin_sz_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_sz_MPORT_9_data = io_in_bits_1_bits_tin_sz;
- assign mem_tin_sz_MPORT_9_addr = 3'h2;
- assign mem_tin_sz_MPORT_9_mask = 1'h1;
- assign mem_tin_sz_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_sz_MPORT_10_data = io_in_bits_2_bits_tin_sz;
- assign mem_tin_sz_MPORT_10_addr = 3'h2;
- assign mem_tin_sz_MPORT_10_mask = 1'h1;
- assign mem_tin_sz_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_sz_MPORT_11_data = io_in_bits_3_bits_tin_sz;
- assign mem_tin_sz_MPORT_11_addr = 3'h2;
- assign mem_tin_sz_MPORT_11_mask = 1'h1;
- assign mem_tin_sz_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_sz_MPORT_12_data = io_in_bits_0_bits_tin_sz;
- assign mem_tin_sz_MPORT_12_addr = 3'h3;
- assign mem_tin_sz_MPORT_12_mask = 1'h1;
- assign mem_tin_sz_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_sz_MPORT_13_data = io_in_bits_1_bits_tin_sz;
- assign mem_tin_sz_MPORT_13_addr = 3'h3;
- assign mem_tin_sz_MPORT_13_mask = 1'h1;
- assign mem_tin_sz_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_sz_MPORT_14_data = io_in_bits_2_bits_tin_sz;
- assign mem_tin_sz_MPORT_14_addr = 3'h3;
- assign mem_tin_sz_MPORT_14_mask = 1'h1;
- assign mem_tin_sz_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_sz_MPORT_15_data = io_in_bits_3_bits_tin_sz;
- assign mem_tin_sz_MPORT_15_addr = 3'h3;
- assign mem_tin_sz_MPORT_15_mask = 1'h1;
- assign mem_tin_sz_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_sz_MPORT_16_data = io_in_bits_0_bits_tin_sz;
- assign mem_tin_sz_MPORT_16_addr = 3'h4;
- assign mem_tin_sz_MPORT_16_mask = 1'h1;
- assign mem_tin_sz_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_sz_MPORT_17_data = io_in_bits_1_bits_tin_sz;
- assign mem_tin_sz_MPORT_17_addr = 3'h4;
- assign mem_tin_sz_MPORT_17_mask = 1'h1;
- assign mem_tin_sz_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_sz_MPORT_18_data = io_in_bits_2_bits_tin_sz;
- assign mem_tin_sz_MPORT_18_addr = 3'h4;
- assign mem_tin_sz_MPORT_18_mask = 1'h1;
- assign mem_tin_sz_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_sz_MPORT_19_data = io_in_bits_3_bits_tin_sz;
- assign mem_tin_sz_MPORT_19_addr = 3'h4;
- assign mem_tin_sz_MPORT_19_mask = 1'h1;
- assign mem_tin_sz_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_sz_MPORT_20_data = io_in_bits_0_bits_tin_sz;
- assign mem_tin_sz_MPORT_20_addr = 3'h5;
- assign mem_tin_sz_MPORT_20_mask = 1'h1;
- assign mem_tin_sz_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_sz_MPORT_21_data = io_in_bits_1_bits_tin_sz;
- assign mem_tin_sz_MPORT_21_addr = 3'h5;
- assign mem_tin_sz_MPORT_21_mask = 1'h1;
- assign mem_tin_sz_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_sz_MPORT_22_data = io_in_bits_2_bits_tin_sz;
- assign mem_tin_sz_MPORT_22_addr = 3'h5;
- assign mem_tin_sz_MPORT_22_mask = 1'h1;
- assign mem_tin_sz_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_sz_MPORT_23_data = io_in_bits_3_bits_tin_sz;
- assign mem_tin_sz_MPORT_23_addr = 3'h5;
- assign mem_tin_sz_MPORT_23_mask = 1'h1;
- assign mem_tin_sz_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_sz_MPORT_24_data = io_in_bits_0_bits_tin_sz;
- assign mem_tin_sz_MPORT_24_addr = 3'h6;
- assign mem_tin_sz_MPORT_24_mask = 1'h1;
- assign mem_tin_sz_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_sz_MPORT_25_data = io_in_bits_1_bits_tin_sz;
- assign mem_tin_sz_MPORT_25_addr = 3'h6;
- assign mem_tin_sz_MPORT_25_mask = 1'h1;
- assign mem_tin_sz_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_sz_MPORT_26_data = io_in_bits_2_bits_tin_sz;
- assign mem_tin_sz_MPORT_26_addr = 3'h6;
- assign mem_tin_sz_MPORT_26_mask = 1'h1;
- assign mem_tin_sz_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_sz_MPORT_27_data = io_in_bits_3_bits_tin_sz;
- assign mem_tin_sz_MPORT_27_addr = 3'h6;
- assign mem_tin_sz_MPORT_27_mask = 1'h1;
- assign mem_tin_sz_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_sz_MPORT_28_data = io_in_bits_0_bits_tin_sz;
- assign mem_tin_sz_MPORT_28_addr = 3'h7;
- assign mem_tin_sz_MPORT_28_mask = 1'h1;
- assign mem_tin_sz_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_sz_MPORT_29_data = io_in_bits_1_bits_tin_sz;
- assign mem_tin_sz_MPORT_29_addr = 3'h7;
- assign mem_tin_sz_MPORT_29_mask = 1'h1;
- assign mem_tin_sz_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_sz_MPORT_30_data = io_in_bits_2_bits_tin_sz;
- assign mem_tin_sz_MPORT_30_addr = 3'h7;
- assign mem_tin_sz_MPORT_30_mask = 1'h1;
- assign mem_tin_sz_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_sz_MPORT_31_data = io_in_bits_3_bits_tin_sz;
- assign mem_tin_sz_MPORT_31_addr = 3'h7;
- assign mem_tin_sz_MPORT_31_mask = 1'h1;
- assign mem_tin_sz_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_vd_addr_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vd_addr_io_out_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vd_addr_io_entry_0_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vd_addr_io_entry_1_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vd_addr_io_entry_2_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vd_addr_io_entry_3_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vd_addr_io_entry_4_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vd_addr_io_entry_5_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vd_addr_io_entry_6_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vd_addr_io_entry_7_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_MPORT_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_addr = 3'h0;
- assign mem_tin_vd_addr_MPORT_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_en = ivalid & valid[0];
- assign mem_tin_vd_addr_MPORT_1_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_1_addr = 3'h0;
- assign mem_tin_vd_addr_MPORT_1_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_vd_addr_MPORT_2_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_2_addr = 3'h0;
- assign mem_tin_vd_addr_MPORT_2_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_vd_addr_MPORT_3_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_3_addr = 3'h0;
- assign mem_tin_vd_addr_MPORT_3_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_vd_addr_MPORT_4_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_4_addr = 3'h1;
- assign mem_tin_vd_addr_MPORT_4_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vd_addr_MPORT_5_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_5_addr = 3'h1;
- assign mem_tin_vd_addr_MPORT_5_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_vd_addr_MPORT_6_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_6_addr = 3'h1;
- assign mem_tin_vd_addr_MPORT_6_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_vd_addr_MPORT_7_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_7_addr = 3'h1;
- assign mem_tin_vd_addr_MPORT_7_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_vd_addr_MPORT_8_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_8_addr = 3'h2;
- assign mem_tin_vd_addr_MPORT_8_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vd_addr_MPORT_9_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_9_addr = 3'h2;
- assign mem_tin_vd_addr_MPORT_9_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_vd_addr_MPORT_10_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_10_addr = 3'h2;
- assign mem_tin_vd_addr_MPORT_10_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_vd_addr_MPORT_11_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_11_addr = 3'h2;
- assign mem_tin_vd_addr_MPORT_11_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_vd_addr_MPORT_12_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_12_addr = 3'h3;
- assign mem_tin_vd_addr_MPORT_12_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vd_addr_MPORT_13_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_13_addr = 3'h3;
- assign mem_tin_vd_addr_MPORT_13_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_vd_addr_MPORT_14_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_14_addr = 3'h3;
- assign mem_tin_vd_addr_MPORT_14_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_vd_addr_MPORT_15_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_15_addr = 3'h3;
- assign mem_tin_vd_addr_MPORT_15_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_vd_addr_MPORT_16_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_16_addr = 3'h4;
- assign mem_tin_vd_addr_MPORT_16_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vd_addr_MPORT_17_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_17_addr = 3'h4;
- assign mem_tin_vd_addr_MPORT_17_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_vd_addr_MPORT_18_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_18_addr = 3'h4;
- assign mem_tin_vd_addr_MPORT_18_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_vd_addr_MPORT_19_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_19_addr = 3'h4;
- assign mem_tin_vd_addr_MPORT_19_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_vd_addr_MPORT_20_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_20_addr = 3'h5;
- assign mem_tin_vd_addr_MPORT_20_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vd_addr_MPORT_21_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_21_addr = 3'h5;
- assign mem_tin_vd_addr_MPORT_21_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_vd_addr_MPORT_22_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_22_addr = 3'h5;
- assign mem_tin_vd_addr_MPORT_22_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_vd_addr_MPORT_23_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_23_addr = 3'h5;
- assign mem_tin_vd_addr_MPORT_23_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_vd_addr_MPORT_24_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_24_addr = 3'h6;
- assign mem_tin_vd_addr_MPORT_24_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vd_addr_MPORT_25_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_25_addr = 3'h6;
- assign mem_tin_vd_addr_MPORT_25_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_vd_addr_MPORT_26_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_26_addr = 3'h6;
- assign mem_tin_vd_addr_MPORT_26_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_vd_addr_MPORT_27_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_27_addr = 3'h6;
- assign mem_tin_vd_addr_MPORT_27_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_vd_addr_MPORT_28_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_28_addr = 3'h7;
- assign mem_tin_vd_addr_MPORT_28_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vd_addr_MPORT_29_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_29_addr = 3'h7;
- assign mem_tin_vd_addr_MPORT_29_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_vd_addr_MPORT_30_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_30_addr = 3'h7;
- assign mem_tin_vd_addr_MPORT_30_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_vd_addr_MPORT_31_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_31_addr = 3'h7;
- assign mem_tin_vd_addr_MPORT_31_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_ve_addr_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_ve_addr_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_ve_addr_io_out_bits_MPORT_data = mem_tin_ve_addr[mem_tin_ve_addr_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_ve_addr_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_ve_addr_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_ve_addr_io_entry_0_bits_MPORT_data = mem_tin_ve_addr[mem_tin_ve_addr_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_ve_addr_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_ve_addr_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_ve_addr_io_entry_1_bits_MPORT_data = mem_tin_ve_addr[mem_tin_ve_addr_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_ve_addr_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_ve_addr_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_ve_addr_io_entry_2_bits_MPORT_data = mem_tin_ve_addr[mem_tin_ve_addr_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_ve_addr_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_ve_addr_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_ve_addr_io_entry_3_bits_MPORT_data = mem_tin_ve_addr[mem_tin_ve_addr_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_ve_addr_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_ve_addr_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_ve_addr_io_entry_4_bits_MPORT_data = mem_tin_ve_addr[mem_tin_ve_addr_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_ve_addr_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_ve_addr_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_ve_addr_io_entry_5_bits_MPORT_data = mem_tin_ve_addr[mem_tin_ve_addr_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_ve_addr_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_ve_addr_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_ve_addr_io_entry_6_bits_MPORT_data = mem_tin_ve_addr[mem_tin_ve_addr_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_ve_addr_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_ve_addr_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_ve_addr_io_entry_7_bits_MPORT_data = mem_tin_ve_addr[mem_tin_ve_addr_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_ve_addr_MPORT_data = io_in_bits_0_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_addr = 3'h0;
- assign mem_tin_ve_addr_MPORT_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_en = ivalid & valid[0];
- assign mem_tin_ve_addr_MPORT_1_data = io_in_bits_1_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_1_addr = 3'h0;
- assign mem_tin_ve_addr_MPORT_1_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_ve_addr_MPORT_2_data = io_in_bits_2_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_2_addr = 3'h0;
- assign mem_tin_ve_addr_MPORT_2_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_ve_addr_MPORT_3_data = io_in_bits_3_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_3_addr = 3'h0;
- assign mem_tin_ve_addr_MPORT_3_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_ve_addr_MPORT_4_data = io_in_bits_0_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_4_addr = 3'h1;
- assign mem_tin_ve_addr_MPORT_4_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_ve_addr_MPORT_5_data = io_in_bits_1_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_5_addr = 3'h1;
- assign mem_tin_ve_addr_MPORT_5_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_ve_addr_MPORT_6_data = io_in_bits_2_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_6_addr = 3'h1;
- assign mem_tin_ve_addr_MPORT_6_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_ve_addr_MPORT_7_data = io_in_bits_3_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_7_addr = 3'h1;
- assign mem_tin_ve_addr_MPORT_7_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_ve_addr_MPORT_8_data = io_in_bits_0_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_8_addr = 3'h2;
- assign mem_tin_ve_addr_MPORT_8_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_ve_addr_MPORT_9_data = io_in_bits_1_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_9_addr = 3'h2;
- assign mem_tin_ve_addr_MPORT_9_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_ve_addr_MPORT_10_data = io_in_bits_2_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_10_addr = 3'h2;
- assign mem_tin_ve_addr_MPORT_10_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_ve_addr_MPORT_11_data = io_in_bits_3_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_11_addr = 3'h2;
- assign mem_tin_ve_addr_MPORT_11_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_ve_addr_MPORT_12_data = io_in_bits_0_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_12_addr = 3'h3;
- assign mem_tin_ve_addr_MPORT_12_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_ve_addr_MPORT_13_data = io_in_bits_1_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_13_addr = 3'h3;
- assign mem_tin_ve_addr_MPORT_13_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_ve_addr_MPORT_14_data = io_in_bits_2_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_14_addr = 3'h3;
- assign mem_tin_ve_addr_MPORT_14_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_ve_addr_MPORT_15_data = io_in_bits_3_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_15_addr = 3'h3;
- assign mem_tin_ve_addr_MPORT_15_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_ve_addr_MPORT_16_data = io_in_bits_0_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_16_addr = 3'h4;
- assign mem_tin_ve_addr_MPORT_16_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_ve_addr_MPORT_17_data = io_in_bits_1_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_17_addr = 3'h4;
- assign mem_tin_ve_addr_MPORT_17_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_ve_addr_MPORT_18_data = io_in_bits_2_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_18_addr = 3'h4;
- assign mem_tin_ve_addr_MPORT_18_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_ve_addr_MPORT_19_data = io_in_bits_3_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_19_addr = 3'h4;
- assign mem_tin_ve_addr_MPORT_19_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_ve_addr_MPORT_20_data = io_in_bits_0_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_20_addr = 3'h5;
- assign mem_tin_ve_addr_MPORT_20_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_ve_addr_MPORT_21_data = io_in_bits_1_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_21_addr = 3'h5;
- assign mem_tin_ve_addr_MPORT_21_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_ve_addr_MPORT_22_data = io_in_bits_2_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_22_addr = 3'h5;
- assign mem_tin_ve_addr_MPORT_22_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_ve_addr_MPORT_23_data = io_in_bits_3_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_23_addr = 3'h5;
- assign mem_tin_ve_addr_MPORT_23_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_ve_addr_MPORT_24_data = io_in_bits_0_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_24_addr = 3'h6;
- assign mem_tin_ve_addr_MPORT_24_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_ve_addr_MPORT_25_data = io_in_bits_1_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_25_addr = 3'h6;
- assign mem_tin_ve_addr_MPORT_25_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_ve_addr_MPORT_26_data = io_in_bits_2_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_26_addr = 3'h6;
- assign mem_tin_ve_addr_MPORT_26_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_ve_addr_MPORT_27_data = io_in_bits_3_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_27_addr = 3'h6;
- assign mem_tin_ve_addr_MPORT_27_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_ve_addr_MPORT_28_data = io_in_bits_0_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_28_addr = 3'h7;
- assign mem_tin_ve_addr_MPORT_28_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_ve_addr_MPORT_29_data = io_in_bits_1_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_29_addr = 3'h7;
- assign mem_tin_ve_addr_MPORT_29_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_ve_addr_MPORT_30_data = io_in_bits_2_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_30_addr = 3'h7;
- assign mem_tin_ve_addr_MPORT_30_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_ve_addr_MPORT_31_data = io_in_bits_3_bits_tin_ve_addr;
- assign mem_tin_ve_addr_MPORT_31_addr = 3'h7;
- assign mem_tin_ve_addr_MPORT_31_mask = 1'h1;
- assign mem_tin_ve_addr_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_vs_valid_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vs_valid_io_out_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vs_valid_io_entry_0_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vs_valid_io_entry_1_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vs_valid_io_entry_2_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vs_valid_io_entry_3_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vs_valid_io_entry_4_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vs_valid_io_entry_5_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vs_valid_io_entry_6_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vs_valid_io_entry_7_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_MPORT_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_addr = 3'h0;
- assign mem_tin_vs_valid_MPORT_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_en = ivalid & valid[0];
- assign mem_tin_vs_valid_MPORT_1_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_1_addr = 3'h0;
- assign mem_tin_vs_valid_MPORT_1_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_vs_valid_MPORT_2_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_2_addr = 3'h0;
- assign mem_tin_vs_valid_MPORT_2_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_vs_valid_MPORT_3_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_3_addr = 3'h0;
- assign mem_tin_vs_valid_MPORT_3_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_vs_valid_MPORT_4_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_4_addr = 3'h1;
- assign mem_tin_vs_valid_MPORT_4_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vs_valid_MPORT_5_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_5_addr = 3'h1;
- assign mem_tin_vs_valid_MPORT_5_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_vs_valid_MPORT_6_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_6_addr = 3'h1;
- assign mem_tin_vs_valid_MPORT_6_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_vs_valid_MPORT_7_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_7_addr = 3'h1;
- assign mem_tin_vs_valid_MPORT_7_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_vs_valid_MPORT_8_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_8_addr = 3'h2;
- assign mem_tin_vs_valid_MPORT_8_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vs_valid_MPORT_9_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_9_addr = 3'h2;
- assign mem_tin_vs_valid_MPORT_9_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_vs_valid_MPORT_10_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_10_addr = 3'h2;
- assign mem_tin_vs_valid_MPORT_10_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_vs_valid_MPORT_11_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_11_addr = 3'h2;
- assign mem_tin_vs_valid_MPORT_11_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_vs_valid_MPORT_12_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_12_addr = 3'h3;
- assign mem_tin_vs_valid_MPORT_12_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vs_valid_MPORT_13_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_13_addr = 3'h3;
- assign mem_tin_vs_valid_MPORT_13_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_vs_valid_MPORT_14_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_14_addr = 3'h3;
- assign mem_tin_vs_valid_MPORT_14_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_vs_valid_MPORT_15_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_15_addr = 3'h3;
- assign mem_tin_vs_valid_MPORT_15_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_vs_valid_MPORT_16_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_16_addr = 3'h4;
- assign mem_tin_vs_valid_MPORT_16_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vs_valid_MPORT_17_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_17_addr = 3'h4;
- assign mem_tin_vs_valid_MPORT_17_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_vs_valid_MPORT_18_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_18_addr = 3'h4;
- assign mem_tin_vs_valid_MPORT_18_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_vs_valid_MPORT_19_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_19_addr = 3'h4;
- assign mem_tin_vs_valid_MPORT_19_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_vs_valid_MPORT_20_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_20_addr = 3'h5;
- assign mem_tin_vs_valid_MPORT_20_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vs_valid_MPORT_21_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_21_addr = 3'h5;
- assign mem_tin_vs_valid_MPORT_21_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_vs_valid_MPORT_22_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_22_addr = 3'h5;
- assign mem_tin_vs_valid_MPORT_22_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_vs_valid_MPORT_23_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_23_addr = 3'h5;
- assign mem_tin_vs_valid_MPORT_23_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_vs_valid_MPORT_24_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_24_addr = 3'h6;
- assign mem_tin_vs_valid_MPORT_24_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vs_valid_MPORT_25_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_25_addr = 3'h6;
- assign mem_tin_vs_valid_MPORT_25_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_vs_valid_MPORT_26_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_26_addr = 3'h6;
- assign mem_tin_vs_valid_MPORT_26_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_vs_valid_MPORT_27_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_27_addr = 3'h6;
- assign mem_tin_vs_valid_MPORT_27_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_vs_valid_MPORT_28_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_28_addr = 3'h7;
- assign mem_tin_vs_valid_MPORT_28_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vs_valid_MPORT_29_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_29_addr = 3'h7;
- assign mem_tin_vs_valid_MPORT_29_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_vs_valid_MPORT_30_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_30_addr = 3'h7;
- assign mem_tin_vs_valid_MPORT_30_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_vs_valid_MPORT_31_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_31_addr = 3'h7;
- assign mem_tin_vs_valid_MPORT_31_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_vs_addr_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vs_addr_io_out_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vs_addr_io_entry_0_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vs_addr_io_entry_1_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vs_addr_io_entry_2_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vs_addr_io_entry_3_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vs_addr_io_entry_4_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vs_addr_io_entry_5_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vs_addr_io_entry_6_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vs_addr_io_entry_7_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_MPORT_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_addr = 3'h0;
- assign mem_tin_vs_addr_MPORT_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_en = ivalid & valid[0];
- assign mem_tin_vs_addr_MPORT_1_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_1_addr = 3'h0;
- assign mem_tin_vs_addr_MPORT_1_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_vs_addr_MPORT_2_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_2_addr = 3'h0;
- assign mem_tin_vs_addr_MPORT_2_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_vs_addr_MPORT_3_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_3_addr = 3'h0;
- assign mem_tin_vs_addr_MPORT_3_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_vs_addr_MPORT_4_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_4_addr = 3'h1;
- assign mem_tin_vs_addr_MPORT_4_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vs_addr_MPORT_5_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_5_addr = 3'h1;
- assign mem_tin_vs_addr_MPORT_5_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_vs_addr_MPORT_6_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_6_addr = 3'h1;
- assign mem_tin_vs_addr_MPORT_6_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_vs_addr_MPORT_7_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_7_addr = 3'h1;
- assign mem_tin_vs_addr_MPORT_7_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_vs_addr_MPORT_8_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_8_addr = 3'h2;
- assign mem_tin_vs_addr_MPORT_8_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vs_addr_MPORT_9_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_9_addr = 3'h2;
- assign mem_tin_vs_addr_MPORT_9_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_vs_addr_MPORT_10_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_10_addr = 3'h2;
- assign mem_tin_vs_addr_MPORT_10_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_vs_addr_MPORT_11_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_11_addr = 3'h2;
- assign mem_tin_vs_addr_MPORT_11_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_vs_addr_MPORT_12_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_12_addr = 3'h3;
- assign mem_tin_vs_addr_MPORT_12_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vs_addr_MPORT_13_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_13_addr = 3'h3;
- assign mem_tin_vs_addr_MPORT_13_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_vs_addr_MPORT_14_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_14_addr = 3'h3;
- assign mem_tin_vs_addr_MPORT_14_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_vs_addr_MPORT_15_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_15_addr = 3'h3;
- assign mem_tin_vs_addr_MPORT_15_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_vs_addr_MPORT_16_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_16_addr = 3'h4;
- assign mem_tin_vs_addr_MPORT_16_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vs_addr_MPORT_17_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_17_addr = 3'h4;
- assign mem_tin_vs_addr_MPORT_17_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_vs_addr_MPORT_18_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_18_addr = 3'h4;
- assign mem_tin_vs_addr_MPORT_18_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_vs_addr_MPORT_19_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_19_addr = 3'h4;
- assign mem_tin_vs_addr_MPORT_19_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_vs_addr_MPORT_20_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_20_addr = 3'h5;
- assign mem_tin_vs_addr_MPORT_20_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vs_addr_MPORT_21_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_21_addr = 3'h5;
- assign mem_tin_vs_addr_MPORT_21_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_vs_addr_MPORT_22_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_22_addr = 3'h5;
- assign mem_tin_vs_addr_MPORT_22_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_vs_addr_MPORT_23_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_23_addr = 3'h5;
- assign mem_tin_vs_addr_MPORT_23_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_vs_addr_MPORT_24_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_24_addr = 3'h6;
- assign mem_tin_vs_addr_MPORT_24_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vs_addr_MPORT_25_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_25_addr = 3'h6;
- assign mem_tin_vs_addr_MPORT_25_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_vs_addr_MPORT_26_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_26_addr = 3'h6;
- assign mem_tin_vs_addr_MPORT_26_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_vs_addr_MPORT_27_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_27_addr = 3'h6;
- assign mem_tin_vs_addr_MPORT_27_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_vs_addr_MPORT_28_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_28_addr = 3'h7;
- assign mem_tin_vs_addr_MPORT_28_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vs_addr_MPORT_29_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_29_addr = 3'h7;
- assign mem_tin_vs_addr_MPORT_29_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_vs_addr_MPORT_30_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_30_addr = 3'h7;
- assign mem_tin_vs_addr_MPORT_30_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_vs_addr_MPORT_31_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_31_addr = 3'h7;
- assign mem_tin_vs_addr_MPORT_31_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_vs_tag_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vs_tag_io_out_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vs_tag_io_entry_0_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vs_tag_io_entry_1_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vs_tag_io_entry_2_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vs_tag_io_entry_3_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vs_tag_io_entry_4_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vs_tag_io_entry_5_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vs_tag_io_entry_6_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vs_tag_io_entry_7_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_MPORT_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_addr = 3'h0;
- assign mem_tin_vs_tag_MPORT_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_en = ivalid & valid[0];
- assign mem_tin_vs_tag_MPORT_1_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_1_addr = 3'h0;
- assign mem_tin_vs_tag_MPORT_1_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_vs_tag_MPORT_2_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_2_addr = 3'h0;
- assign mem_tin_vs_tag_MPORT_2_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_vs_tag_MPORT_3_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_3_addr = 3'h0;
- assign mem_tin_vs_tag_MPORT_3_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_vs_tag_MPORT_4_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_4_addr = 3'h1;
- assign mem_tin_vs_tag_MPORT_4_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vs_tag_MPORT_5_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_5_addr = 3'h1;
- assign mem_tin_vs_tag_MPORT_5_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_vs_tag_MPORT_6_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_6_addr = 3'h1;
- assign mem_tin_vs_tag_MPORT_6_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_vs_tag_MPORT_7_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_7_addr = 3'h1;
- assign mem_tin_vs_tag_MPORT_7_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_vs_tag_MPORT_8_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_8_addr = 3'h2;
- assign mem_tin_vs_tag_MPORT_8_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vs_tag_MPORT_9_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_9_addr = 3'h2;
- assign mem_tin_vs_tag_MPORT_9_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_vs_tag_MPORT_10_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_10_addr = 3'h2;
- assign mem_tin_vs_tag_MPORT_10_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_vs_tag_MPORT_11_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_11_addr = 3'h2;
- assign mem_tin_vs_tag_MPORT_11_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_vs_tag_MPORT_12_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_12_addr = 3'h3;
- assign mem_tin_vs_tag_MPORT_12_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vs_tag_MPORT_13_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_13_addr = 3'h3;
- assign mem_tin_vs_tag_MPORT_13_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_vs_tag_MPORT_14_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_14_addr = 3'h3;
- assign mem_tin_vs_tag_MPORT_14_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_vs_tag_MPORT_15_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_15_addr = 3'h3;
- assign mem_tin_vs_tag_MPORT_15_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_vs_tag_MPORT_16_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_16_addr = 3'h4;
- assign mem_tin_vs_tag_MPORT_16_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vs_tag_MPORT_17_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_17_addr = 3'h4;
- assign mem_tin_vs_tag_MPORT_17_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_vs_tag_MPORT_18_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_18_addr = 3'h4;
- assign mem_tin_vs_tag_MPORT_18_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_vs_tag_MPORT_19_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_19_addr = 3'h4;
- assign mem_tin_vs_tag_MPORT_19_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_vs_tag_MPORT_20_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_20_addr = 3'h5;
- assign mem_tin_vs_tag_MPORT_20_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vs_tag_MPORT_21_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_21_addr = 3'h5;
- assign mem_tin_vs_tag_MPORT_21_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_vs_tag_MPORT_22_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_22_addr = 3'h5;
- assign mem_tin_vs_tag_MPORT_22_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_vs_tag_MPORT_23_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_23_addr = 3'h5;
- assign mem_tin_vs_tag_MPORT_23_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_vs_tag_MPORT_24_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_24_addr = 3'h6;
- assign mem_tin_vs_tag_MPORT_24_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vs_tag_MPORT_25_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_25_addr = 3'h6;
- assign mem_tin_vs_tag_MPORT_25_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_vs_tag_MPORT_26_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_26_addr = 3'h6;
- assign mem_tin_vs_tag_MPORT_26_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_vs_tag_MPORT_27_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_27_addr = 3'h6;
- assign mem_tin_vs_tag_MPORT_27_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_vs_tag_MPORT_28_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_28_addr = 3'h7;
- assign mem_tin_vs_tag_MPORT_28_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vs_tag_MPORT_29_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_29_addr = 3'h7;
- assign mem_tin_vs_tag_MPORT_29_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_vs_tag_MPORT_30_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_30_addr = 3'h7;
- assign mem_tin_vs_tag_MPORT_30_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_vs_tag_MPORT_31_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_31_addr = 3'h7;
- assign mem_tin_vs_tag_MPORT_31_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_vt_valid_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_valid_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vt_valid_io_out_bits_MPORT_data = mem_tin_vt_valid[mem_tin_vt_valid_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_valid_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_valid_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vt_valid_io_entry_0_bits_MPORT_data = mem_tin_vt_valid[mem_tin_vt_valid_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_valid_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_valid_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vt_valid_io_entry_1_bits_MPORT_data = mem_tin_vt_valid[mem_tin_vt_valid_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_valid_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_valid_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vt_valid_io_entry_2_bits_MPORT_data = mem_tin_vt_valid[mem_tin_vt_valid_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_valid_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_valid_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vt_valid_io_entry_3_bits_MPORT_data = mem_tin_vt_valid[mem_tin_vt_valid_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_valid_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_valid_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vt_valid_io_entry_4_bits_MPORT_data = mem_tin_vt_valid[mem_tin_vt_valid_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_valid_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_valid_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vt_valid_io_entry_5_bits_MPORT_data = mem_tin_vt_valid[mem_tin_vt_valid_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_valid_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_valid_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vt_valid_io_entry_6_bits_MPORT_data = mem_tin_vt_valid[mem_tin_vt_valid_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_valid_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_valid_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vt_valid_io_entry_7_bits_MPORT_data = mem_tin_vt_valid[mem_tin_vt_valid_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_valid_MPORT_data = io_in_bits_0_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_addr = 3'h0;
- assign mem_tin_vt_valid_MPORT_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_en = ivalid & valid[0];
- assign mem_tin_vt_valid_MPORT_1_data = io_in_bits_1_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_1_addr = 3'h0;
- assign mem_tin_vt_valid_MPORT_1_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_vt_valid_MPORT_2_data = io_in_bits_2_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_2_addr = 3'h0;
- assign mem_tin_vt_valid_MPORT_2_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_vt_valid_MPORT_3_data = io_in_bits_3_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_3_addr = 3'h0;
- assign mem_tin_vt_valid_MPORT_3_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_vt_valid_MPORT_4_data = io_in_bits_0_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_4_addr = 3'h1;
- assign mem_tin_vt_valid_MPORT_4_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vt_valid_MPORT_5_data = io_in_bits_1_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_5_addr = 3'h1;
- assign mem_tin_vt_valid_MPORT_5_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_vt_valid_MPORT_6_data = io_in_bits_2_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_6_addr = 3'h1;
- assign mem_tin_vt_valid_MPORT_6_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_vt_valid_MPORT_7_data = io_in_bits_3_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_7_addr = 3'h1;
- assign mem_tin_vt_valid_MPORT_7_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_vt_valid_MPORT_8_data = io_in_bits_0_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_8_addr = 3'h2;
- assign mem_tin_vt_valid_MPORT_8_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vt_valid_MPORT_9_data = io_in_bits_1_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_9_addr = 3'h2;
- assign mem_tin_vt_valid_MPORT_9_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_vt_valid_MPORT_10_data = io_in_bits_2_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_10_addr = 3'h2;
- assign mem_tin_vt_valid_MPORT_10_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_vt_valid_MPORT_11_data = io_in_bits_3_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_11_addr = 3'h2;
- assign mem_tin_vt_valid_MPORT_11_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_vt_valid_MPORT_12_data = io_in_bits_0_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_12_addr = 3'h3;
- assign mem_tin_vt_valid_MPORT_12_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vt_valid_MPORT_13_data = io_in_bits_1_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_13_addr = 3'h3;
- assign mem_tin_vt_valid_MPORT_13_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_vt_valid_MPORT_14_data = io_in_bits_2_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_14_addr = 3'h3;
- assign mem_tin_vt_valid_MPORT_14_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_vt_valid_MPORT_15_data = io_in_bits_3_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_15_addr = 3'h3;
- assign mem_tin_vt_valid_MPORT_15_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_vt_valid_MPORT_16_data = io_in_bits_0_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_16_addr = 3'h4;
- assign mem_tin_vt_valid_MPORT_16_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vt_valid_MPORT_17_data = io_in_bits_1_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_17_addr = 3'h4;
- assign mem_tin_vt_valid_MPORT_17_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_vt_valid_MPORT_18_data = io_in_bits_2_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_18_addr = 3'h4;
- assign mem_tin_vt_valid_MPORT_18_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_vt_valid_MPORT_19_data = io_in_bits_3_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_19_addr = 3'h4;
- assign mem_tin_vt_valid_MPORT_19_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_vt_valid_MPORT_20_data = io_in_bits_0_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_20_addr = 3'h5;
- assign mem_tin_vt_valid_MPORT_20_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vt_valid_MPORT_21_data = io_in_bits_1_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_21_addr = 3'h5;
- assign mem_tin_vt_valid_MPORT_21_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_vt_valid_MPORT_22_data = io_in_bits_2_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_22_addr = 3'h5;
- assign mem_tin_vt_valid_MPORT_22_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_vt_valid_MPORT_23_data = io_in_bits_3_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_23_addr = 3'h5;
- assign mem_tin_vt_valid_MPORT_23_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_vt_valid_MPORT_24_data = io_in_bits_0_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_24_addr = 3'h6;
- assign mem_tin_vt_valid_MPORT_24_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vt_valid_MPORT_25_data = io_in_bits_1_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_25_addr = 3'h6;
- assign mem_tin_vt_valid_MPORT_25_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_vt_valid_MPORT_26_data = io_in_bits_2_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_26_addr = 3'h6;
- assign mem_tin_vt_valid_MPORT_26_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_vt_valid_MPORT_27_data = io_in_bits_3_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_27_addr = 3'h6;
- assign mem_tin_vt_valid_MPORT_27_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_vt_valid_MPORT_28_data = io_in_bits_0_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_28_addr = 3'h7;
- assign mem_tin_vt_valid_MPORT_28_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vt_valid_MPORT_29_data = io_in_bits_1_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_29_addr = 3'h7;
- assign mem_tin_vt_valid_MPORT_29_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_vt_valid_MPORT_30_data = io_in_bits_2_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_30_addr = 3'h7;
- assign mem_tin_vt_valid_MPORT_30_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_vt_valid_MPORT_31_data = io_in_bits_3_bits_tin_vt_valid;
- assign mem_tin_vt_valid_MPORT_31_addr = 3'h7;
- assign mem_tin_vt_valid_MPORT_31_mask = 1'h1;
- assign mem_tin_vt_valid_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_vt_addr_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_addr_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vt_addr_io_out_bits_MPORT_data = mem_tin_vt_addr[mem_tin_vt_addr_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_addr_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_addr_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vt_addr_io_entry_0_bits_MPORT_data = mem_tin_vt_addr[mem_tin_vt_addr_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_addr_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_addr_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vt_addr_io_entry_1_bits_MPORT_data = mem_tin_vt_addr[mem_tin_vt_addr_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_addr_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_addr_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vt_addr_io_entry_2_bits_MPORT_data = mem_tin_vt_addr[mem_tin_vt_addr_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_addr_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_addr_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vt_addr_io_entry_3_bits_MPORT_data = mem_tin_vt_addr[mem_tin_vt_addr_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_addr_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_addr_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vt_addr_io_entry_4_bits_MPORT_data = mem_tin_vt_addr[mem_tin_vt_addr_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_addr_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_addr_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vt_addr_io_entry_5_bits_MPORT_data = mem_tin_vt_addr[mem_tin_vt_addr_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_addr_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_addr_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vt_addr_io_entry_6_bits_MPORT_data = mem_tin_vt_addr[mem_tin_vt_addr_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_addr_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_addr_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vt_addr_io_entry_7_bits_MPORT_data = mem_tin_vt_addr[mem_tin_vt_addr_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_addr_MPORT_data = io_in_bits_0_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_addr = 3'h0;
- assign mem_tin_vt_addr_MPORT_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_en = ivalid & valid[0];
- assign mem_tin_vt_addr_MPORT_1_data = io_in_bits_1_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_1_addr = 3'h0;
- assign mem_tin_vt_addr_MPORT_1_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_vt_addr_MPORT_2_data = io_in_bits_2_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_2_addr = 3'h0;
- assign mem_tin_vt_addr_MPORT_2_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_vt_addr_MPORT_3_data = io_in_bits_3_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_3_addr = 3'h0;
- assign mem_tin_vt_addr_MPORT_3_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_vt_addr_MPORT_4_data = io_in_bits_0_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_4_addr = 3'h1;
- assign mem_tin_vt_addr_MPORT_4_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vt_addr_MPORT_5_data = io_in_bits_1_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_5_addr = 3'h1;
- assign mem_tin_vt_addr_MPORT_5_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_vt_addr_MPORT_6_data = io_in_bits_2_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_6_addr = 3'h1;
- assign mem_tin_vt_addr_MPORT_6_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_vt_addr_MPORT_7_data = io_in_bits_3_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_7_addr = 3'h1;
- assign mem_tin_vt_addr_MPORT_7_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_vt_addr_MPORT_8_data = io_in_bits_0_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_8_addr = 3'h2;
- assign mem_tin_vt_addr_MPORT_8_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vt_addr_MPORT_9_data = io_in_bits_1_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_9_addr = 3'h2;
- assign mem_tin_vt_addr_MPORT_9_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_vt_addr_MPORT_10_data = io_in_bits_2_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_10_addr = 3'h2;
- assign mem_tin_vt_addr_MPORT_10_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_vt_addr_MPORT_11_data = io_in_bits_3_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_11_addr = 3'h2;
- assign mem_tin_vt_addr_MPORT_11_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_vt_addr_MPORT_12_data = io_in_bits_0_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_12_addr = 3'h3;
- assign mem_tin_vt_addr_MPORT_12_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vt_addr_MPORT_13_data = io_in_bits_1_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_13_addr = 3'h3;
- assign mem_tin_vt_addr_MPORT_13_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_vt_addr_MPORT_14_data = io_in_bits_2_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_14_addr = 3'h3;
- assign mem_tin_vt_addr_MPORT_14_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_vt_addr_MPORT_15_data = io_in_bits_3_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_15_addr = 3'h3;
- assign mem_tin_vt_addr_MPORT_15_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_vt_addr_MPORT_16_data = io_in_bits_0_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_16_addr = 3'h4;
- assign mem_tin_vt_addr_MPORT_16_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vt_addr_MPORT_17_data = io_in_bits_1_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_17_addr = 3'h4;
- assign mem_tin_vt_addr_MPORT_17_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_vt_addr_MPORT_18_data = io_in_bits_2_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_18_addr = 3'h4;
- assign mem_tin_vt_addr_MPORT_18_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_vt_addr_MPORT_19_data = io_in_bits_3_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_19_addr = 3'h4;
- assign mem_tin_vt_addr_MPORT_19_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_vt_addr_MPORT_20_data = io_in_bits_0_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_20_addr = 3'h5;
- assign mem_tin_vt_addr_MPORT_20_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vt_addr_MPORT_21_data = io_in_bits_1_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_21_addr = 3'h5;
- assign mem_tin_vt_addr_MPORT_21_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_vt_addr_MPORT_22_data = io_in_bits_2_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_22_addr = 3'h5;
- assign mem_tin_vt_addr_MPORT_22_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_vt_addr_MPORT_23_data = io_in_bits_3_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_23_addr = 3'h5;
- assign mem_tin_vt_addr_MPORT_23_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_vt_addr_MPORT_24_data = io_in_bits_0_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_24_addr = 3'h6;
- assign mem_tin_vt_addr_MPORT_24_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vt_addr_MPORT_25_data = io_in_bits_1_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_25_addr = 3'h6;
- assign mem_tin_vt_addr_MPORT_25_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_vt_addr_MPORT_26_data = io_in_bits_2_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_26_addr = 3'h6;
- assign mem_tin_vt_addr_MPORT_26_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_vt_addr_MPORT_27_data = io_in_bits_3_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_27_addr = 3'h6;
- assign mem_tin_vt_addr_MPORT_27_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_vt_addr_MPORT_28_data = io_in_bits_0_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_28_addr = 3'h7;
- assign mem_tin_vt_addr_MPORT_28_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vt_addr_MPORT_29_data = io_in_bits_1_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_29_addr = 3'h7;
- assign mem_tin_vt_addr_MPORT_29_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_vt_addr_MPORT_30_data = io_in_bits_2_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_30_addr = 3'h7;
- assign mem_tin_vt_addr_MPORT_30_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_vt_addr_MPORT_31_data = io_in_bits_3_bits_tin_vt_addr;
- assign mem_tin_vt_addr_MPORT_31_addr = 3'h7;
- assign mem_tin_vt_addr_MPORT_31_mask = 1'h1;
- assign mem_tin_vt_addr_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_vt_tag_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_tag_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vt_tag_io_out_bits_MPORT_data = mem_tin_vt_tag[mem_tin_vt_tag_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_tag_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_tag_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vt_tag_io_entry_0_bits_MPORT_data = mem_tin_vt_tag[mem_tin_vt_tag_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_tag_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_tag_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vt_tag_io_entry_1_bits_MPORT_data = mem_tin_vt_tag[mem_tin_vt_tag_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_tag_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_tag_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vt_tag_io_entry_2_bits_MPORT_data = mem_tin_vt_tag[mem_tin_vt_tag_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_tag_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_tag_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vt_tag_io_entry_3_bits_MPORT_data = mem_tin_vt_tag[mem_tin_vt_tag_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_tag_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_tag_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vt_tag_io_entry_4_bits_MPORT_data = mem_tin_vt_tag[mem_tin_vt_tag_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_tag_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_tag_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vt_tag_io_entry_5_bits_MPORT_data = mem_tin_vt_tag[mem_tin_vt_tag_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_tag_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_tag_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vt_tag_io_entry_6_bits_MPORT_data = mem_tin_vt_tag[mem_tin_vt_tag_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_tag_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vt_tag_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vt_tag_io_entry_7_bits_MPORT_data = mem_tin_vt_tag[mem_tin_vt_tag_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vt_tag_MPORT_data = io_in_bits_0_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_addr = 3'h0;
- assign mem_tin_vt_tag_MPORT_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_en = ivalid & valid[0];
- assign mem_tin_vt_tag_MPORT_1_data = io_in_bits_1_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_1_addr = 3'h0;
- assign mem_tin_vt_tag_MPORT_1_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_vt_tag_MPORT_2_data = io_in_bits_2_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_2_addr = 3'h0;
- assign mem_tin_vt_tag_MPORT_2_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_vt_tag_MPORT_3_data = io_in_bits_3_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_3_addr = 3'h0;
- assign mem_tin_vt_tag_MPORT_3_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_vt_tag_MPORT_4_data = io_in_bits_0_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_4_addr = 3'h1;
- assign mem_tin_vt_tag_MPORT_4_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vt_tag_MPORT_5_data = io_in_bits_1_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_5_addr = 3'h1;
- assign mem_tin_vt_tag_MPORT_5_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_vt_tag_MPORT_6_data = io_in_bits_2_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_6_addr = 3'h1;
- assign mem_tin_vt_tag_MPORT_6_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_vt_tag_MPORT_7_data = io_in_bits_3_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_7_addr = 3'h1;
- assign mem_tin_vt_tag_MPORT_7_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_vt_tag_MPORT_8_data = io_in_bits_0_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_8_addr = 3'h2;
- assign mem_tin_vt_tag_MPORT_8_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vt_tag_MPORT_9_data = io_in_bits_1_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_9_addr = 3'h2;
- assign mem_tin_vt_tag_MPORT_9_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_vt_tag_MPORT_10_data = io_in_bits_2_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_10_addr = 3'h2;
- assign mem_tin_vt_tag_MPORT_10_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_vt_tag_MPORT_11_data = io_in_bits_3_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_11_addr = 3'h2;
- assign mem_tin_vt_tag_MPORT_11_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_vt_tag_MPORT_12_data = io_in_bits_0_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_12_addr = 3'h3;
- assign mem_tin_vt_tag_MPORT_12_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vt_tag_MPORT_13_data = io_in_bits_1_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_13_addr = 3'h3;
- assign mem_tin_vt_tag_MPORT_13_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_vt_tag_MPORT_14_data = io_in_bits_2_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_14_addr = 3'h3;
- assign mem_tin_vt_tag_MPORT_14_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_vt_tag_MPORT_15_data = io_in_bits_3_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_15_addr = 3'h3;
- assign mem_tin_vt_tag_MPORT_15_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_vt_tag_MPORT_16_data = io_in_bits_0_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_16_addr = 3'h4;
- assign mem_tin_vt_tag_MPORT_16_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vt_tag_MPORT_17_data = io_in_bits_1_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_17_addr = 3'h4;
- assign mem_tin_vt_tag_MPORT_17_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_vt_tag_MPORT_18_data = io_in_bits_2_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_18_addr = 3'h4;
- assign mem_tin_vt_tag_MPORT_18_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_vt_tag_MPORT_19_data = io_in_bits_3_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_19_addr = 3'h4;
- assign mem_tin_vt_tag_MPORT_19_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_vt_tag_MPORT_20_data = io_in_bits_0_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_20_addr = 3'h5;
- assign mem_tin_vt_tag_MPORT_20_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vt_tag_MPORT_21_data = io_in_bits_1_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_21_addr = 3'h5;
- assign mem_tin_vt_tag_MPORT_21_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_vt_tag_MPORT_22_data = io_in_bits_2_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_22_addr = 3'h5;
- assign mem_tin_vt_tag_MPORT_22_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_vt_tag_MPORT_23_data = io_in_bits_3_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_23_addr = 3'h5;
- assign mem_tin_vt_tag_MPORT_23_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_vt_tag_MPORT_24_data = io_in_bits_0_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_24_addr = 3'h6;
- assign mem_tin_vt_tag_MPORT_24_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vt_tag_MPORT_25_data = io_in_bits_1_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_25_addr = 3'h6;
- assign mem_tin_vt_tag_MPORT_25_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_vt_tag_MPORT_26_data = io_in_bits_2_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_26_addr = 3'h6;
- assign mem_tin_vt_tag_MPORT_26_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_vt_tag_MPORT_27_data = io_in_bits_3_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_27_addr = 3'h6;
- assign mem_tin_vt_tag_MPORT_27_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_vt_tag_MPORT_28_data = io_in_bits_0_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_28_addr = 3'h7;
- assign mem_tin_vt_tag_MPORT_28_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vt_tag_MPORT_29_data = io_in_bits_1_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_29_addr = 3'h7;
- assign mem_tin_vt_tag_MPORT_29_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_vt_tag_MPORT_30_data = io_in_bits_2_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_30_addr = 3'h7;
- assign mem_tin_vt_tag_MPORT_30_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_vt_tag_MPORT_31_data = io_in_bits_3_bits_tin_vt_tag;
- assign mem_tin_vt_tag_MPORT_31_addr = 3'h7;
- assign mem_tin_vt_tag_MPORT_31_mask = 1'h1;
- assign mem_tin_vt_tag_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_vu_valid_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_valid_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vu_valid_io_out_bits_MPORT_data = mem_tin_vu_valid[mem_tin_vu_valid_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_valid_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_valid_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vu_valid_io_entry_0_bits_MPORT_data = mem_tin_vu_valid[mem_tin_vu_valid_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_valid_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_valid_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vu_valid_io_entry_1_bits_MPORT_data = mem_tin_vu_valid[mem_tin_vu_valid_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_valid_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_valid_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vu_valid_io_entry_2_bits_MPORT_data = mem_tin_vu_valid[mem_tin_vu_valid_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_valid_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_valid_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vu_valid_io_entry_3_bits_MPORT_data = mem_tin_vu_valid[mem_tin_vu_valid_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_valid_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_valid_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vu_valid_io_entry_4_bits_MPORT_data = mem_tin_vu_valid[mem_tin_vu_valid_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_valid_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_valid_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vu_valid_io_entry_5_bits_MPORT_data = mem_tin_vu_valid[mem_tin_vu_valid_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_valid_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_valid_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vu_valid_io_entry_6_bits_MPORT_data = mem_tin_vu_valid[mem_tin_vu_valid_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_valid_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_valid_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vu_valid_io_entry_7_bits_MPORT_data = mem_tin_vu_valid[mem_tin_vu_valid_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_valid_MPORT_data = io_in_bits_0_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_addr = 3'h0;
- assign mem_tin_vu_valid_MPORT_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_en = ivalid & valid[0];
- assign mem_tin_vu_valid_MPORT_1_data = io_in_bits_1_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_1_addr = 3'h0;
- assign mem_tin_vu_valid_MPORT_1_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_vu_valid_MPORT_2_data = io_in_bits_2_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_2_addr = 3'h0;
- assign mem_tin_vu_valid_MPORT_2_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_vu_valid_MPORT_3_data = io_in_bits_3_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_3_addr = 3'h0;
- assign mem_tin_vu_valid_MPORT_3_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_vu_valid_MPORT_4_data = io_in_bits_0_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_4_addr = 3'h1;
- assign mem_tin_vu_valid_MPORT_4_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vu_valid_MPORT_5_data = io_in_bits_1_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_5_addr = 3'h1;
- assign mem_tin_vu_valid_MPORT_5_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_vu_valid_MPORT_6_data = io_in_bits_2_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_6_addr = 3'h1;
- assign mem_tin_vu_valid_MPORT_6_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_vu_valid_MPORT_7_data = io_in_bits_3_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_7_addr = 3'h1;
- assign mem_tin_vu_valid_MPORT_7_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_vu_valid_MPORT_8_data = io_in_bits_0_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_8_addr = 3'h2;
- assign mem_tin_vu_valid_MPORT_8_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vu_valid_MPORT_9_data = io_in_bits_1_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_9_addr = 3'h2;
- assign mem_tin_vu_valid_MPORT_9_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_vu_valid_MPORT_10_data = io_in_bits_2_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_10_addr = 3'h2;
- assign mem_tin_vu_valid_MPORT_10_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_vu_valid_MPORT_11_data = io_in_bits_3_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_11_addr = 3'h2;
- assign mem_tin_vu_valid_MPORT_11_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_vu_valid_MPORT_12_data = io_in_bits_0_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_12_addr = 3'h3;
- assign mem_tin_vu_valid_MPORT_12_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vu_valid_MPORT_13_data = io_in_bits_1_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_13_addr = 3'h3;
- assign mem_tin_vu_valid_MPORT_13_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_vu_valid_MPORT_14_data = io_in_bits_2_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_14_addr = 3'h3;
- assign mem_tin_vu_valid_MPORT_14_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_vu_valid_MPORT_15_data = io_in_bits_3_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_15_addr = 3'h3;
- assign mem_tin_vu_valid_MPORT_15_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_vu_valid_MPORT_16_data = io_in_bits_0_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_16_addr = 3'h4;
- assign mem_tin_vu_valid_MPORT_16_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vu_valid_MPORT_17_data = io_in_bits_1_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_17_addr = 3'h4;
- assign mem_tin_vu_valid_MPORT_17_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_vu_valid_MPORT_18_data = io_in_bits_2_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_18_addr = 3'h4;
- assign mem_tin_vu_valid_MPORT_18_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_vu_valid_MPORT_19_data = io_in_bits_3_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_19_addr = 3'h4;
- assign mem_tin_vu_valid_MPORT_19_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_vu_valid_MPORT_20_data = io_in_bits_0_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_20_addr = 3'h5;
- assign mem_tin_vu_valid_MPORT_20_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vu_valid_MPORT_21_data = io_in_bits_1_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_21_addr = 3'h5;
- assign mem_tin_vu_valid_MPORT_21_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_vu_valid_MPORT_22_data = io_in_bits_2_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_22_addr = 3'h5;
- assign mem_tin_vu_valid_MPORT_22_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_vu_valid_MPORT_23_data = io_in_bits_3_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_23_addr = 3'h5;
- assign mem_tin_vu_valid_MPORT_23_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_vu_valid_MPORT_24_data = io_in_bits_0_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_24_addr = 3'h6;
- assign mem_tin_vu_valid_MPORT_24_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vu_valid_MPORT_25_data = io_in_bits_1_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_25_addr = 3'h6;
- assign mem_tin_vu_valid_MPORT_25_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_vu_valid_MPORT_26_data = io_in_bits_2_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_26_addr = 3'h6;
- assign mem_tin_vu_valid_MPORT_26_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_vu_valid_MPORT_27_data = io_in_bits_3_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_27_addr = 3'h6;
- assign mem_tin_vu_valid_MPORT_27_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_vu_valid_MPORT_28_data = io_in_bits_0_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_28_addr = 3'h7;
- assign mem_tin_vu_valid_MPORT_28_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vu_valid_MPORT_29_data = io_in_bits_1_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_29_addr = 3'h7;
- assign mem_tin_vu_valid_MPORT_29_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_vu_valid_MPORT_30_data = io_in_bits_2_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_30_addr = 3'h7;
- assign mem_tin_vu_valid_MPORT_30_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_vu_valid_MPORT_31_data = io_in_bits_3_bits_tin_vu_valid;
- assign mem_tin_vu_valid_MPORT_31_addr = 3'h7;
- assign mem_tin_vu_valid_MPORT_31_mask = 1'h1;
- assign mem_tin_vu_valid_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_vu_addr_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_addr_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vu_addr_io_out_bits_MPORT_data = mem_tin_vu_addr[mem_tin_vu_addr_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_addr_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_addr_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vu_addr_io_entry_0_bits_MPORT_data = mem_tin_vu_addr[mem_tin_vu_addr_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_addr_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_addr_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vu_addr_io_entry_1_bits_MPORT_data = mem_tin_vu_addr[mem_tin_vu_addr_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_addr_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_addr_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vu_addr_io_entry_2_bits_MPORT_data = mem_tin_vu_addr[mem_tin_vu_addr_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_addr_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_addr_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vu_addr_io_entry_3_bits_MPORT_data = mem_tin_vu_addr[mem_tin_vu_addr_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_addr_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_addr_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vu_addr_io_entry_4_bits_MPORT_data = mem_tin_vu_addr[mem_tin_vu_addr_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_addr_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_addr_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vu_addr_io_entry_5_bits_MPORT_data = mem_tin_vu_addr[mem_tin_vu_addr_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_addr_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_addr_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vu_addr_io_entry_6_bits_MPORT_data = mem_tin_vu_addr[mem_tin_vu_addr_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_addr_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_addr_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vu_addr_io_entry_7_bits_MPORT_data = mem_tin_vu_addr[mem_tin_vu_addr_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_addr_MPORT_data = io_in_bits_0_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_addr = 3'h0;
- assign mem_tin_vu_addr_MPORT_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_en = ivalid & valid[0];
- assign mem_tin_vu_addr_MPORT_1_data = io_in_bits_1_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_1_addr = 3'h0;
- assign mem_tin_vu_addr_MPORT_1_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_vu_addr_MPORT_2_data = io_in_bits_2_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_2_addr = 3'h0;
- assign mem_tin_vu_addr_MPORT_2_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_vu_addr_MPORT_3_data = io_in_bits_3_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_3_addr = 3'h0;
- assign mem_tin_vu_addr_MPORT_3_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_vu_addr_MPORT_4_data = io_in_bits_0_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_4_addr = 3'h1;
- assign mem_tin_vu_addr_MPORT_4_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vu_addr_MPORT_5_data = io_in_bits_1_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_5_addr = 3'h1;
- assign mem_tin_vu_addr_MPORT_5_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_vu_addr_MPORT_6_data = io_in_bits_2_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_6_addr = 3'h1;
- assign mem_tin_vu_addr_MPORT_6_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_vu_addr_MPORT_7_data = io_in_bits_3_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_7_addr = 3'h1;
- assign mem_tin_vu_addr_MPORT_7_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_vu_addr_MPORT_8_data = io_in_bits_0_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_8_addr = 3'h2;
- assign mem_tin_vu_addr_MPORT_8_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vu_addr_MPORT_9_data = io_in_bits_1_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_9_addr = 3'h2;
- assign mem_tin_vu_addr_MPORT_9_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_vu_addr_MPORT_10_data = io_in_bits_2_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_10_addr = 3'h2;
- assign mem_tin_vu_addr_MPORT_10_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_vu_addr_MPORT_11_data = io_in_bits_3_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_11_addr = 3'h2;
- assign mem_tin_vu_addr_MPORT_11_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_vu_addr_MPORT_12_data = io_in_bits_0_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_12_addr = 3'h3;
- assign mem_tin_vu_addr_MPORT_12_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vu_addr_MPORT_13_data = io_in_bits_1_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_13_addr = 3'h3;
- assign mem_tin_vu_addr_MPORT_13_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_vu_addr_MPORT_14_data = io_in_bits_2_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_14_addr = 3'h3;
- assign mem_tin_vu_addr_MPORT_14_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_vu_addr_MPORT_15_data = io_in_bits_3_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_15_addr = 3'h3;
- assign mem_tin_vu_addr_MPORT_15_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_vu_addr_MPORT_16_data = io_in_bits_0_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_16_addr = 3'h4;
- assign mem_tin_vu_addr_MPORT_16_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vu_addr_MPORT_17_data = io_in_bits_1_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_17_addr = 3'h4;
- assign mem_tin_vu_addr_MPORT_17_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_vu_addr_MPORT_18_data = io_in_bits_2_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_18_addr = 3'h4;
- assign mem_tin_vu_addr_MPORT_18_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_vu_addr_MPORT_19_data = io_in_bits_3_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_19_addr = 3'h4;
- assign mem_tin_vu_addr_MPORT_19_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_vu_addr_MPORT_20_data = io_in_bits_0_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_20_addr = 3'h5;
- assign mem_tin_vu_addr_MPORT_20_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vu_addr_MPORT_21_data = io_in_bits_1_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_21_addr = 3'h5;
- assign mem_tin_vu_addr_MPORT_21_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_vu_addr_MPORT_22_data = io_in_bits_2_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_22_addr = 3'h5;
- assign mem_tin_vu_addr_MPORT_22_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_vu_addr_MPORT_23_data = io_in_bits_3_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_23_addr = 3'h5;
- assign mem_tin_vu_addr_MPORT_23_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_vu_addr_MPORT_24_data = io_in_bits_0_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_24_addr = 3'h6;
- assign mem_tin_vu_addr_MPORT_24_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vu_addr_MPORT_25_data = io_in_bits_1_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_25_addr = 3'h6;
- assign mem_tin_vu_addr_MPORT_25_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_vu_addr_MPORT_26_data = io_in_bits_2_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_26_addr = 3'h6;
- assign mem_tin_vu_addr_MPORT_26_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_vu_addr_MPORT_27_data = io_in_bits_3_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_27_addr = 3'h6;
- assign mem_tin_vu_addr_MPORT_27_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_vu_addr_MPORT_28_data = io_in_bits_0_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_28_addr = 3'h7;
- assign mem_tin_vu_addr_MPORT_28_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vu_addr_MPORT_29_data = io_in_bits_1_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_29_addr = 3'h7;
- assign mem_tin_vu_addr_MPORT_29_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_vu_addr_MPORT_30_data = io_in_bits_2_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_30_addr = 3'h7;
- assign mem_tin_vu_addr_MPORT_30_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_vu_addr_MPORT_31_data = io_in_bits_3_bits_tin_vu_addr;
- assign mem_tin_vu_addr_MPORT_31_addr = 3'h7;
- assign mem_tin_vu_addr_MPORT_31_mask = 1'h1;
- assign mem_tin_vu_addr_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_vu_tag_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_tag_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vu_tag_io_out_bits_MPORT_data = mem_tin_vu_tag[mem_tin_vu_tag_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_tag_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_tag_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vu_tag_io_entry_0_bits_MPORT_data = mem_tin_vu_tag[mem_tin_vu_tag_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_tag_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_tag_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vu_tag_io_entry_1_bits_MPORT_data = mem_tin_vu_tag[mem_tin_vu_tag_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_tag_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_tag_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vu_tag_io_entry_2_bits_MPORT_data = mem_tin_vu_tag[mem_tin_vu_tag_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_tag_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_tag_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vu_tag_io_entry_3_bits_MPORT_data = mem_tin_vu_tag[mem_tin_vu_tag_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_tag_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_tag_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vu_tag_io_entry_4_bits_MPORT_data = mem_tin_vu_tag[mem_tin_vu_tag_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_tag_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_tag_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vu_tag_io_entry_5_bits_MPORT_data = mem_tin_vu_tag[mem_tin_vu_tag_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_tag_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_tag_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vu_tag_io_entry_6_bits_MPORT_data = mem_tin_vu_tag[mem_tin_vu_tag_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_tag_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vu_tag_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vu_tag_io_entry_7_bits_MPORT_data = mem_tin_vu_tag[mem_tin_vu_tag_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vu_tag_MPORT_data = io_in_bits_0_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_addr = 3'h0;
- assign mem_tin_vu_tag_MPORT_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_en = ivalid & valid[0];
- assign mem_tin_vu_tag_MPORT_1_data = io_in_bits_1_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_1_addr = 3'h0;
- assign mem_tin_vu_tag_MPORT_1_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_vu_tag_MPORT_2_data = io_in_bits_2_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_2_addr = 3'h0;
- assign mem_tin_vu_tag_MPORT_2_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_vu_tag_MPORT_3_data = io_in_bits_3_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_3_addr = 3'h0;
- assign mem_tin_vu_tag_MPORT_3_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_vu_tag_MPORT_4_data = io_in_bits_0_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_4_addr = 3'h1;
- assign mem_tin_vu_tag_MPORT_4_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vu_tag_MPORT_5_data = io_in_bits_1_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_5_addr = 3'h1;
- assign mem_tin_vu_tag_MPORT_5_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_vu_tag_MPORT_6_data = io_in_bits_2_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_6_addr = 3'h1;
- assign mem_tin_vu_tag_MPORT_6_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_vu_tag_MPORT_7_data = io_in_bits_3_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_7_addr = 3'h1;
- assign mem_tin_vu_tag_MPORT_7_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_vu_tag_MPORT_8_data = io_in_bits_0_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_8_addr = 3'h2;
- assign mem_tin_vu_tag_MPORT_8_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vu_tag_MPORT_9_data = io_in_bits_1_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_9_addr = 3'h2;
- assign mem_tin_vu_tag_MPORT_9_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_vu_tag_MPORT_10_data = io_in_bits_2_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_10_addr = 3'h2;
- assign mem_tin_vu_tag_MPORT_10_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_vu_tag_MPORT_11_data = io_in_bits_3_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_11_addr = 3'h2;
- assign mem_tin_vu_tag_MPORT_11_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_vu_tag_MPORT_12_data = io_in_bits_0_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_12_addr = 3'h3;
- assign mem_tin_vu_tag_MPORT_12_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vu_tag_MPORT_13_data = io_in_bits_1_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_13_addr = 3'h3;
- assign mem_tin_vu_tag_MPORT_13_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_vu_tag_MPORT_14_data = io_in_bits_2_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_14_addr = 3'h3;
- assign mem_tin_vu_tag_MPORT_14_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_vu_tag_MPORT_15_data = io_in_bits_3_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_15_addr = 3'h3;
- assign mem_tin_vu_tag_MPORT_15_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_vu_tag_MPORT_16_data = io_in_bits_0_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_16_addr = 3'h4;
- assign mem_tin_vu_tag_MPORT_16_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vu_tag_MPORT_17_data = io_in_bits_1_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_17_addr = 3'h4;
- assign mem_tin_vu_tag_MPORT_17_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_vu_tag_MPORT_18_data = io_in_bits_2_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_18_addr = 3'h4;
- assign mem_tin_vu_tag_MPORT_18_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_vu_tag_MPORT_19_data = io_in_bits_3_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_19_addr = 3'h4;
- assign mem_tin_vu_tag_MPORT_19_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_vu_tag_MPORT_20_data = io_in_bits_0_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_20_addr = 3'h5;
- assign mem_tin_vu_tag_MPORT_20_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vu_tag_MPORT_21_data = io_in_bits_1_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_21_addr = 3'h5;
- assign mem_tin_vu_tag_MPORT_21_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_vu_tag_MPORT_22_data = io_in_bits_2_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_22_addr = 3'h5;
- assign mem_tin_vu_tag_MPORT_22_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_vu_tag_MPORT_23_data = io_in_bits_3_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_23_addr = 3'h5;
- assign mem_tin_vu_tag_MPORT_23_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_vu_tag_MPORT_24_data = io_in_bits_0_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_24_addr = 3'h6;
- assign mem_tin_vu_tag_MPORT_24_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vu_tag_MPORT_25_data = io_in_bits_1_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_25_addr = 3'h6;
- assign mem_tin_vu_tag_MPORT_25_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_vu_tag_MPORT_26_data = io_in_bits_2_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_26_addr = 3'h6;
- assign mem_tin_vu_tag_MPORT_26_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_vu_tag_MPORT_27_data = io_in_bits_3_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_27_addr = 3'h6;
- assign mem_tin_vu_tag_MPORT_27_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_vu_tag_MPORT_28_data = io_in_bits_0_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_28_addr = 3'h7;
- assign mem_tin_vu_tag_MPORT_28_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vu_tag_MPORT_29_data = io_in_bits_1_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_29_addr = 3'h7;
- assign mem_tin_vu_tag_MPORT_29_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_vu_tag_MPORT_30_data = io_in_bits_2_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_30_addr = 3'h7;
- assign mem_tin_vu_tag_MPORT_30_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_vu_tag_MPORT_31_data = io_in_bits_3_bits_tin_vu_tag;
- assign mem_tin_vu_tag_MPORT_31_addr = 3'h7;
- assign mem_tin_vu_tag_MPORT_31_mask = 1'h1;
- assign mem_tin_vu_tag_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_sv_valid_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_valid_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_sv_valid_io_out_bits_MPORT_data = mem_tin_sv_valid[mem_tin_sv_valid_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_valid_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_valid_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_sv_valid_io_entry_0_bits_MPORT_data = mem_tin_sv_valid[mem_tin_sv_valid_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_valid_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_valid_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_sv_valid_io_entry_1_bits_MPORT_data = mem_tin_sv_valid[mem_tin_sv_valid_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_valid_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_valid_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_sv_valid_io_entry_2_bits_MPORT_data = mem_tin_sv_valid[mem_tin_sv_valid_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_valid_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_valid_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_sv_valid_io_entry_3_bits_MPORT_data = mem_tin_sv_valid[mem_tin_sv_valid_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_valid_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_valid_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_sv_valid_io_entry_4_bits_MPORT_data = mem_tin_sv_valid[mem_tin_sv_valid_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_valid_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_valid_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_sv_valid_io_entry_5_bits_MPORT_data = mem_tin_sv_valid[mem_tin_sv_valid_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_valid_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_valid_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_sv_valid_io_entry_6_bits_MPORT_data = mem_tin_sv_valid[mem_tin_sv_valid_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_valid_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_valid_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_sv_valid_io_entry_7_bits_MPORT_data = mem_tin_sv_valid[mem_tin_sv_valid_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_valid_MPORT_data = io_in_bits_0_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_addr = 3'h0;
- assign mem_tin_sv_valid_MPORT_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_en = ivalid & valid[0];
- assign mem_tin_sv_valid_MPORT_1_data = io_in_bits_1_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_1_addr = 3'h0;
- assign mem_tin_sv_valid_MPORT_1_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_sv_valid_MPORT_2_data = io_in_bits_2_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_2_addr = 3'h0;
- assign mem_tin_sv_valid_MPORT_2_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_sv_valid_MPORT_3_data = io_in_bits_3_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_3_addr = 3'h0;
- assign mem_tin_sv_valid_MPORT_3_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_sv_valid_MPORT_4_data = io_in_bits_0_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_4_addr = 3'h1;
- assign mem_tin_sv_valid_MPORT_4_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_sv_valid_MPORT_5_data = io_in_bits_1_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_5_addr = 3'h1;
- assign mem_tin_sv_valid_MPORT_5_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_sv_valid_MPORT_6_data = io_in_bits_2_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_6_addr = 3'h1;
- assign mem_tin_sv_valid_MPORT_6_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_sv_valid_MPORT_7_data = io_in_bits_3_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_7_addr = 3'h1;
- assign mem_tin_sv_valid_MPORT_7_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_sv_valid_MPORT_8_data = io_in_bits_0_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_8_addr = 3'h2;
- assign mem_tin_sv_valid_MPORT_8_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_sv_valid_MPORT_9_data = io_in_bits_1_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_9_addr = 3'h2;
- assign mem_tin_sv_valid_MPORT_9_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_sv_valid_MPORT_10_data = io_in_bits_2_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_10_addr = 3'h2;
- assign mem_tin_sv_valid_MPORT_10_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_sv_valid_MPORT_11_data = io_in_bits_3_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_11_addr = 3'h2;
- assign mem_tin_sv_valid_MPORT_11_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_sv_valid_MPORT_12_data = io_in_bits_0_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_12_addr = 3'h3;
- assign mem_tin_sv_valid_MPORT_12_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_sv_valid_MPORT_13_data = io_in_bits_1_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_13_addr = 3'h3;
- assign mem_tin_sv_valid_MPORT_13_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_sv_valid_MPORT_14_data = io_in_bits_2_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_14_addr = 3'h3;
- assign mem_tin_sv_valid_MPORT_14_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_sv_valid_MPORT_15_data = io_in_bits_3_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_15_addr = 3'h3;
- assign mem_tin_sv_valid_MPORT_15_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_sv_valid_MPORT_16_data = io_in_bits_0_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_16_addr = 3'h4;
- assign mem_tin_sv_valid_MPORT_16_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_sv_valid_MPORT_17_data = io_in_bits_1_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_17_addr = 3'h4;
- assign mem_tin_sv_valid_MPORT_17_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_sv_valid_MPORT_18_data = io_in_bits_2_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_18_addr = 3'h4;
- assign mem_tin_sv_valid_MPORT_18_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_sv_valid_MPORT_19_data = io_in_bits_3_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_19_addr = 3'h4;
- assign mem_tin_sv_valid_MPORT_19_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_sv_valid_MPORT_20_data = io_in_bits_0_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_20_addr = 3'h5;
- assign mem_tin_sv_valid_MPORT_20_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_sv_valid_MPORT_21_data = io_in_bits_1_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_21_addr = 3'h5;
- assign mem_tin_sv_valid_MPORT_21_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_sv_valid_MPORT_22_data = io_in_bits_2_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_22_addr = 3'h5;
- assign mem_tin_sv_valid_MPORT_22_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_sv_valid_MPORT_23_data = io_in_bits_3_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_23_addr = 3'h5;
- assign mem_tin_sv_valid_MPORT_23_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_sv_valid_MPORT_24_data = io_in_bits_0_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_24_addr = 3'h6;
- assign mem_tin_sv_valid_MPORT_24_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_sv_valid_MPORT_25_data = io_in_bits_1_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_25_addr = 3'h6;
- assign mem_tin_sv_valid_MPORT_25_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_sv_valid_MPORT_26_data = io_in_bits_2_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_26_addr = 3'h6;
- assign mem_tin_sv_valid_MPORT_26_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_sv_valid_MPORT_27_data = io_in_bits_3_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_27_addr = 3'h6;
- assign mem_tin_sv_valid_MPORT_27_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_sv_valid_MPORT_28_data = io_in_bits_0_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_28_addr = 3'h7;
- assign mem_tin_sv_valid_MPORT_28_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_sv_valid_MPORT_29_data = io_in_bits_1_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_29_addr = 3'h7;
- assign mem_tin_sv_valid_MPORT_29_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_sv_valid_MPORT_30_data = io_in_bits_2_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_30_addr = 3'h7;
- assign mem_tin_sv_valid_MPORT_30_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_sv_valid_MPORT_31_data = io_in_bits_3_bits_tin_sv_valid;
- assign mem_tin_sv_valid_MPORT_31_addr = 3'h7;
- assign mem_tin_sv_valid_MPORT_31_mask = 1'h1;
- assign mem_tin_sv_valid_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_sv_data_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_data_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_sv_data_io_out_bits_MPORT_data = mem_tin_sv_data[mem_tin_sv_data_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_data_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_data_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_sv_data_io_entry_0_bits_MPORT_data = mem_tin_sv_data[mem_tin_sv_data_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_data_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_data_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_sv_data_io_entry_1_bits_MPORT_data = mem_tin_sv_data[mem_tin_sv_data_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_data_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_data_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_sv_data_io_entry_2_bits_MPORT_data = mem_tin_sv_data[mem_tin_sv_data_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_data_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_data_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_sv_data_io_entry_3_bits_MPORT_data = mem_tin_sv_data[mem_tin_sv_data_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_data_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_data_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_sv_data_io_entry_4_bits_MPORT_data = mem_tin_sv_data[mem_tin_sv_data_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_data_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_data_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_sv_data_io_entry_5_bits_MPORT_data = mem_tin_sv_data[mem_tin_sv_data_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_data_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_data_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_sv_data_io_entry_6_bits_MPORT_data = mem_tin_sv_data[mem_tin_sv_data_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_data_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_sv_data_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_sv_data_io_entry_7_bits_MPORT_data = mem_tin_sv_data[mem_tin_sv_data_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_sv_data_MPORT_data = io_in_bits_0_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_addr = 3'h0;
- assign mem_tin_sv_data_MPORT_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_en = ivalid & valid[0];
- assign mem_tin_sv_data_MPORT_1_data = io_in_bits_1_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_1_addr = 3'h0;
- assign mem_tin_sv_data_MPORT_1_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_sv_data_MPORT_2_data = io_in_bits_2_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_2_addr = 3'h0;
- assign mem_tin_sv_data_MPORT_2_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_sv_data_MPORT_3_data = io_in_bits_3_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_3_addr = 3'h0;
- assign mem_tin_sv_data_MPORT_3_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_sv_data_MPORT_4_data = io_in_bits_0_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_4_addr = 3'h1;
- assign mem_tin_sv_data_MPORT_4_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_sv_data_MPORT_5_data = io_in_bits_1_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_5_addr = 3'h1;
- assign mem_tin_sv_data_MPORT_5_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_sv_data_MPORT_6_data = io_in_bits_2_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_6_addr = 3'h1;
- assign mem_tin_sv_data_MPORT_6_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_sv_data_MPORT_7_data = io_in_bits_3_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_7_addr = 3'h1;
- assign mem_tin_sv_data_MPORT_7_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_sv_data_MPORT_8_data = io_in_bits_0_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_8_addr = 3'h2;
- assign mem_tin_sv_data_MPORT_8_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_sv_data_MPORT_9_data = io_in_bits_1_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_9_addr = 3'h2;
- assign mem_tin_sv_data_MPORT_9_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_sv_data_MPORT_10_data = io_in_bits_2_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_10_addr = 3'h2;
- assign mem_tin_sv_data_MPORT_10_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_sv_data_MPORT_11_data = io_in_bits_3_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_11_addr = 3'h2;
- assign mem_tin_sv_data_MPORT_11_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_sv_data_MPORT_12_data = io_in_bits_0_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_12_addr = 3'h3;
- assign mem_tin_sv_data_MPORT_12_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_sv_data_MPORT_13_data = io_in_bits_1_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_13_addr = 3'h3;
- assign mem_tin_sv_data_MPORT_13_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_sv_data_MPORT_14_data = io_in_bits_2_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_14_addr = 3'h3;
- assign mem_tin_sv_data_MPORT_14_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_sv_data_MPORT_15_data = io_in_bits_3_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_15_addr = 3'h3;
- assign mem_tin_sv_data_MPORT_15_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_sv_data_MPORT_16_data = io_in_bits_0_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_16_addr = 3'h4;
- assign mem_tin_sv_data_MPORT_16_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_sv_data_MPORT_17_data = io_in_bits_1_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_17_addr = 3'h4;
- assign mem_tin_sv_data_MPORT_17_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_sv_data_MPORT_18_data = io_in_bits_2_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_18_addr = 3'h4;
- assign mem_tin_sv_data_MPORT_18_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_sv_data_MPORT_19_data = io_in_bits_3_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_19_addr = 3'h4;
- assign mem_tin_sv_data_MPORT_19_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_sv_data_MPORT_20_data = io_in_bits_0_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_20_addr = 3'h5;
- assign mem_tin_sv_data_MPORT_20_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_sv_data_MPORT_21_data = io_in_bits_1_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_21_addr = 3'h5;
- assign mem_tin_sv_data_MPORT_21_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_sv_data_MPORT_22_data = io_in_bits_2_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_22_addr = 3'h5;
- assign mem_tin_sv_data_MPORT_22_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_sv_data_MPORT_23_data = io_in_bits_3_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_23_addr = 3'h5;
- assign mem_tin_sv_data_MPORT_23_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_sv_data_MPORT_24_data = io_in_bits_0_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_24_addr = 3'h6;
- assign mem_tin_sv_data_MPORT_24_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_sv_data_MPORT_25_data = io_in_bits_1_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_25_addr = 3'h6;
- assign mem_tin_sv_data_MPORT_25_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_sv_data_MPORT_26_data = io_in_bits_2_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_26_addr = 3'h6;
- assign mem_tin_sv_data_MPORT_26_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_sv_data_MPORT_27_data = io_in_bits_3_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_27_addr = 3'h6;
- assign mem_tin_sv_data_MPORT_27_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_sv_data_MPORT_28_data = io_in_bits_0_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_28_addr = 3'h7;
- assign mem_tin_sv_data_MPORT_28_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_sv_data_MPORT_29_data = io_in_bits_1_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_29_addr = 3'h7;
- assign mem_tin_sv_data_MPORT_29_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_sv_data_MPORT_30_data = io_in_bits_2_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_30_addr = 3'h7;
- assign mem_tin_sv_data_MPORT_30_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_sv_data_MPORT_31_data = io_in_bits_3_bits_tin_sv_data;
- assign mem_tin_sv_data_MPORT_31_addr = 3'h7;
- assign mem_tin_sv_data_MPORT_31_mask = 1'h1;
- assign mem_tin_sv_data_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_tin_cmdsync_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_cmdsync_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_cmdsync_io_out_bits_MPORT_data = mem_tin_cmdsync[mem_tin_cmdsync_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_cmdsync_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_cmdsync_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_cmdsync_io_entry_0_bits_MPORT_data = mem_tin_cmdsync[mem_tin_cmdsync_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_cmdsync_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_cmdsync_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_cmdsync_io_entry_1_bits_MPORT_data = mem_tin_cmdsync[mem_tin_cmdsync_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_cmdsync_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_cmdsync_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_cmdsync_io_entry_2_bits_MPORT_data = mem_tin_cmdsync[mem_tin_cmdsync_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_cmdsync_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_cmdsync_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_cmdsync_io_entry_3_bits_MPORT_data = mem_tin_cmdsync[mem_tin_cmdsync_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_cmdsync_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_cmdsync_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_cmdsync_io_entry_4_bits_MPORT_data = mem_tin_cmdsync[mem_tin_cmdsync_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_cmdsync_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_cmdsync_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_cmdsync_io_entry_5_bits_MPORT_data = mem_tin_cmdsync[mem_tin_cmdsync_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_cmdsync_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_cmdsync_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_cmdsync_io_entry_6_bits_MPORT_data = mem_tin_cmdsync[mem_tin_cmdsync_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_cmdsync_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_cmdsync_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_cmdsync_io_entry_7_bits_MPORT_data = mem_tin_cmdsync[mem_tin_cmdsync_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_cmdsync_MPORT_data = io_in_bits_0_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_addr = 3'h0;
- assign mem_tin_cmdsync_MPORT_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_en = ivalid & valid[0];
- assign mem_tin_cmdsync_MPORT_1_data = io_in_bits_1_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_1_addr = 3'h0;
- assign mem_tin_cmdsync_MPORT_1_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_1_en = ivalid & _GEN_177;
- assign mem_tin_cmdsync_MPORT_2_data = io_in_bits_2_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_2_addr = 3'h0;
- assign mem_tin_cmdsync_MPORT_2_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_2_en = ivalid & _GEN_201;
- assign mem_tin_cmdsync_MPORT_3_data = io_in_bits_3_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_3_addr = 3'h0;
- assign mem_tin_cmdsync_MPORT_3_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_3_en = ivalid & _GEN_225;
- assign mem_tin_cmdsync_MPORT_4_data = io_in_bits_0_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_4_addr = 3'h1;
- assign mem_tin_cmdsync_MPORT_4_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_cmdsync_MPORT_5_data = io_in_bits_1_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_5_addr = 3'h1;
- assign mem_tin_cmdsync_MPORT_5_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_5_en = ivalid & _GEN_506;
- assign mem_tin_cmdsync_MPORT_6_data = io_in_bits_2_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_6_addr = 3'h1;
- assign mem_tin_cmdsync_MPORT_6_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_6_en = ivalid & _GEN_529;
- assign mem_tin_cmdsync_MPORT_7_data = io_in_bits_3_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_7_addr = 3'h1;
- assign mem_tin_cmdsync_MPORT_7_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_7_en = ivalid & _GEN_552;
- assign mem_tin_cmdsync_MPORT_8_data = io_in_bits_0_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_8_addr = 3'h2;
- assign mem_tin_cmdsync_MPORT_8_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_cmdsync_MPORT_9_data = io_in_bits_1_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_9_addr = 3'h2;
- assign mem_tin_cmdsync_MPORT_9_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_9_en = ivalid & _GEN_835;
- assign mem_tin_cmdsync_MPORT_10_data = io_in_bits_2_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_10_addr = 3'h2;
- assign mem_tin_cmdsync_MPORT_10_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_10_en = ivalid & _GEN_859;
- assign mem_tin_cmdsync_MPORT_11_data = io_in_bits_3_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_11_addr = 3'h2;
- assign mem_tin_cmdsync_MPORT_11_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_11_en = ivalid & _GEN_883;
- assign mem_tin_cmdsync_MPORT_12_data = io_in_bits_0_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_12_addr = 3'h3;
- assign mem_tin_cmdsync_MPORT_12_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_cmdsync_MPORT_13_data = io_in_bits_1_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_13_addr = 3'h3;
- assign mem_tin_cmdsync_MPORT_13_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_tin_cmdsync_MPORT_14_data = io_in_bits_2_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_14_addr = 3'h3;
- assign mem_tin_cmdsync_MPORT_14_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_tin_cmdsync_MPORT_15_data = io_in_bits_3_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_15_addr = 3'h3;
- assign mem_tin_cmdsync_MPORT_15_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_tin_cmdsync_MPORT_16_data = io_in_bits_0_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_16_addr = 3'h4;
- assign mem_tin_cmdsync_MPORT_16_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_cmdsync_MPORT_17_data = io_in_bits_1_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_17_addr = 3'h4;
- assign mem_tin_cmdsync_MPORT_17_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_tin_cmdsync_MPORT_18_data = io_in_bits_2_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_18_addr = 3'h4;
- assign mem_tin_cmdsync_MPORT_18_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_tin_cmdsync_MPORT_19_data = io_in_bits_3_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_19_addr = 3'h4;
- assign mem_tin_cmdsync_MPORT_19_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_tin_cmdsync_MPORT_20_data = io_in_bits_0_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_20_addr = 3'h5;
- assign mem_tin_cmdsync_MPORT_20_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_cmdsync_MPORT_21_data = io_in_bits_1_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_21_addr = 3'h5;
- assign mem_tin_cmdsync_MPORT_21_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_tin_cmdsync_MPORT_22_data = io_in_bits_2_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_22_addr = 3'h5;
- assign mem_tin_cmdsync_MPORT_22_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_tin_cmdsync_MPORT_23_data = io_in_bits_3_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_23_addr = 3'h5;
- assign mem_tin_cmdsync_MPORT_23_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_tin_cmdsync_MPORT_24_data = io_in_bits_0_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_24_addr = 3'h6;
- assign mem_tin_cmdsync_MPORT_24_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_cmdsync_MPORT_25_data = io_in_bits_1_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_25_addr = 3'h6;
- assign mem_tin_cmdsync_MPORT_25_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_tin_cmdsync_MPORT_26_data = io_in_bits_2_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_26_addr = 3'h6;
- assign mem_tin_cmdsync_MPORT_26_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_tin_cmdsync_MPORT_27_data = io_in_bits_3_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_27_addr = 3'h6;
- assign mem_tin_cmdsync_MPORT_27_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_tin_cmdsync_MPORT_28_data = io_in_bits_0_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_28_addr = 3'h7;
- assign mem_tin_cmdsync_MPORT_28_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_cmdsync_MPORT_29_data = io_in_bits_1_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_29_addr = 3'h7;
- assign mem_tin_cmdsync_MPORT_29_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_tin_cmdsync_MPORT_30_data = io_in_bits_2_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_30_addr = 3'h7;
- assign mem_tin_cmdsync_MPORT_30_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_tin_cmdsync_MPORT_31_data = io_in_bits_3_bits_tin_cmdsync;
- assign mem_tin_cmdsync_MPORT_31_addr = 3'h7;
- assign mem_tin_cmdsync_MPORT_31_mask = 1'h1;
- assign mem_tin_cmdsync_MPORT_31_en = ivalid & _GEN_2563;
- assign mem_m_io_out_bits_MPORT_en = 1'h1;
- assign mem_m_io_out_bits_MPORT_addr = outpos;
- assign mem_m_io_out_bits_MPORT_data = mem_m[mem_m_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_m_io_entry_0_bits_MPORT_data = mem_m[mem_m_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_m_io_entry_1_bits_MPORT_data = mem_m[mem_m_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_m_io_entry_2_bits_MPORT_data = mem_m[mem_m_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_m_io_entry_3_bits_MPORT_data = mem_m[mem_m_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_m_io_entry_4_bits_MPORT_data = mem_m[mem_m_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_m_io_entry_5_bits_MPORT_data = mem_m[mem_m_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_m_io_entry_6_bits_MPORT_data = mem_m[mem_m_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_m_io_entry_7_bits_MPORT_data = mem_m[mem_m_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_MPORT_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_addr = 3'h0;
- assign mem_m_MPORT_mask = 1'h1;
- assign mem_m_MPORT_en = ivalid & valid[0];
- assign mem_m_MPORT_1_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_1_addr = 3'h0;
- assign mem_m_MPORT_1_mask = 1'h1;
- assign mem_m_MPORT_1_en = ivalid & _GEN_177;
- assign mem_m_MPORT_2_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_2_addr = 3'h0;
- assign mem_m_MPORT_2_mask = 1'h1;
- assign mem_m_MPORT_2_en = ivalid & _GEN_201;
- assign mem_m_MPORT_3_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_3_addr = 3'h0;
- assign mem_m_MPORT_3_mask = 1'h1;
- assign mem_m_MPORT_3_en = ivalid & _GEN_225;
- assign mem_m_MPORT_4_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_4_addr = 3'h1;
- assign mem_m_MPORT_4_mask = 1'h1;
- assign mem_m_MPORT_4_en = ivalid & valid_1[0];
- assign mem_m_MPORT_5_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_5_addr = 3'h1;
- assign mem_m_MPORT_5_mask = 1'h1;
- assign mem_m_MPORT_5_en = ivalid & _GEN_506;
- assign mem_m_MPORT_6_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_6_addr = 3'h1;
- assign mem_m_MPORT_6_mask = 1'h1;
- assign mem_m_MPORT_6_en = ivalid & _GEN_529;
- assign mem_m_MPORT_7_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_7_addr = 3'h1;
- assign mem_m_MPORT_7_mask = 1'h1;
- assign mem_m_MPORT_7_en = ivalid & _GEN_552;
- assign mem_m_MPORT_8_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_8_addr = 3'h2;
- assign mem_m_MPORT_8_mask = 1'h1;
- assign mem_m_MPORT_8_en = ivalid & valid_2[0];
- assign mem_m_MPORT_9_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_9_addr = 3'h2;
- assign mem_m_MPORT_9_mask = 1'h1;
- assign mem_m_MPORT_9_en = ivalid & _GEN_835;
- assign mem_m_MPORT_10_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_10_addr = 3'h2;
- assign mem_m_MPORT_10_mask = 1'h1;
- assign mem_m_MPORT_10_en = ivalid & _GEN_859;
- assign mem_m_MPORT_11_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_11_addr = 3'h2;
- assign mem_m_MPORT_11_mask = 1'h1;
- assign mem_m_MPORT_11_en = ivalid & _GEN_883;
- assign mem_m_MPORT_12_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_12_addr = 3'h3;
- assign mem_m_MPORT_12_mask = 1'h1;
- assign mem_m_MPORT_12_en = ivalid & valid_3[0];
- assign mem_m_MPORT_13_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_13_addr = 3'h3;
- assign mem_m_MPORT_13_mask = 1'h1;
- assign mem_m_MPORT_13_en = ivalid & _GEN_1171;
- assign mem_m_MPORT_14_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_14_addr = 3'h3;
- assign mem_m_MPORT_14_mask = 1'h1;
- assign mem_m_MPORT_14_en = ivalid & _GEN_1195;
- assign mem_m_MPORT_15_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_15_addr = 3'h3;
- assign mem_m_MPORT_15_mask = 1'h1;
- assign mem_m_MPORT_15_en = ivalid & _GEN_1219;
- assign mem_m_MPORT_16_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_16_addr = 3'h4;
- assign mem_m_MPORT_16_mask = 1'h1;
- assign mem_m_MPORT_16_en = ivalid & valid_4[0];
- assign mem_m_MPORT_17_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_17_addr = 3'h4;
- assign mem_m_MPORT_17_mask = 1'h1;
- assign mem_m_MPORT_17_en = ivalid & _GEN_1507;
- assign mem_m_MPORT_18_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_18_addr = 3'h4;
- assign mem_m_MPORT_18_mask = 1'h1;
- assign mem_m_MPORT_18_en = ivalid & _GEN_1531;
- assign mem_m_MPORT_19_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_19_addr = 3'h4;
- assign mem_m_MPORT_19_mask = 1'h1;
- assign mem_m_MPORT_19_en = ivalid & _GEN_1555;
- assign mem_m_MPORT_20_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_20_addr = 3'h5;
- assign mem_m_MPORT_20_mask = 1'h1;
- assign mem_m_MPORT_20_en = ivalid & valid_5[0];
- assign mem_m_MPORT_21_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_21_addr = 3'h5;
- assign mem_m_MPORT_21_mask = 1'h1;
- assign mem_m_MPORT_21_en = ivalid & _GEN_1843;
- assign mem_m_MPORT_22_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_22_addr = 3'h5;
- assign mem_m_MPORT_22_mask = 1'h1;
- assign mem_m_MPORT_22_en = ivalid & _GEN_1867;
- assign mem_m_MPORT_23_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_23_addr = 3'h5;
- assign mem_m_MPORT_23_mask = 1'h1;
- assign mem_m_MPORT_23_en = ivalid & _GEN_1891;
- assign mem_m_MPORT_24_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_24_addr = 3'h6;
- assign mem_m_MPORT_24_mask = 1'h1;
- assign mem_m_MPORT_24_en = ivalid & valid_6[0];
- assign mem_m_MPORT_25_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_25_addr = 3'h6;
- assign mem_m_MPORT_25_mask = 1'h1;
- assign mem_m_MPORT_25_en = ivalid & _GEN_2179;
- assign mem_m_MPORT_26_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_26_addr = 3'h6;
- assign mem_m_MPORT_26_mask = 1'h1;
- assign mem_m_MPORT_26_en = ivalid & _GEN_2203;
- assign mem_m_MPORT_27_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_27_addr = 3'h6;
- assign mem_m_MPORT_27_mask = 1'h1;
- assign mem_m_MPORT_27_en = ivalid & _GEN_2227;
- assign mem_m_MPORT_28_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_28_addr = 3'h7;
- assign mem_m_MPORT_28_mask = 1'h1;
- assign mem_m_MPORT_28_en = ivalid & valid_7[0];
- assign mem_m_MPORT_29_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_29_addr = 3'h7;
- assign mem_m_MPORT_29_mask = 1'h1;
- assign mem_m_MPORT_29_en = ivalid & _GEN_2515;
- assign mem_m_MPORT_30_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_30_addr = 3'h7;
- assign mem_m_MPORT_30_mask = 1'h1;
- assign mem_m_MPORT_30_en = ivalid & _GEN_2539;
- assign mem_m_MPORT_31_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_31_addr = 3'h7;
- assign mem_m_MPORT_31_mask = 1'h1;
- assign mem_m_MPORT_31_en = ivalid & _GEN_2563;
- assign io_in_ready = mcount <= _io_in_ready_T_1; // @[Fifo4e.scala 132:25]
- assign io_out_valid = mcount != 4'h0; // @[Fifo4e.scala 134:26]
- assign io_out_bits_tin_op = mem_tin_op_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_f2 = mem_tin_f2_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_sz = mem_tin_sz_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vd_addr = mem_tin_vd_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_ve_addr = mem_tin_ve_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vs_valid = mem_tin_vs_valid_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vs_addr = mem_tin_vs_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vs_tag = mem_tin_vs_tag_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vt_valid = mem_tin_vt_valid_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vt_addr = mem_tin_vt_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vt_tag = mem_tin_vt_tag_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vu_valid = mem_tin_vu_valid_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vu_addr = mem_tin_vu_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vu_tag = mem_tin_vu_tag_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_sv_valid = mem_tin_sv_valid_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_sv_data = mem_tin_sv_data_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_cmdsync = mem_tin_cmdsync_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_m = mem_m_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_entry_0_valid = active[0]; // @[Fifo4e.scala 140:32]
- assign io_entry_0_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_tin_vt_valid = mem_tin_vt_valid_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_tin_vt_addr = mem_tin_vt_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_tin_vu_valid = mem_tin_vu_valid_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_tin_vu_addr = mem_tin_vu_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_m = mem_m_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_valid = active[1]; // @[Fifo4e.scala 140:32]
- assign io_entry_1_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_tin_vt_valid = mem_tin_vt_valid_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_tin_vt_addr = mem_tin_vt_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_tin_vu_valid = mem_tin_vu_valid_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_tin_vu_addr = mem_tin_vu_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_m = mem_m_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_valid = active[2]; // @[Fifo4e.scala 140:32]
- assign io_entry_2_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_tin_vt_valid = mem_tin_vt_valid_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_tin_vt_addr = mem_tin_vt_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_tin_vu_valid = mem_tin_vu_valid_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_tin_vu_addr = mem_tin_vu_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_m = mem_m_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_valid = active[3]; // @[Fifo4e.scala 140:32]
- assign io_entry_3_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_tin_vt_valid = mem_tin_vt_valid_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_tin_vt_addr = mem_tin_vt_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_tin_vu_valid = mem_tin_vu_valid_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_tin_vu_addr = mem_tin_vu_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_m = mem_m_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_4_valid = active[4]; // @[Fifo4e.scala 140:32]
- assign io_entry_4_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_4_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_4_bits_tin_vt_valid = mem_tin_vt_valid_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_4_bits_tin_vt_addr = mem_tin_vt_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_4_bits_tin_vu_valid = mem_tin_vu_valid_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_4_bits_tin_vu_addr = mem_tin_vu_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_4_bits_m = mem_m_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_5_valid = active[5]; // @[Fifo4e.scala 140:32]
- assign io_entry_5_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_5_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_5_bits_tin_vt_valid = mem_tin_vt_valid_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_5_bits_tin_vt_addr = mem_tin_vt_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_5_bits_tin_vu_valid = mem_tin_vu_valid_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_5_bits_tin_vu_addr = mem_tin_vu_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_5_bits_m = mem_m_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_6_valid = active[6]; // @[Fifo4e.scala 140:32]
- assign io_entry_6_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_6_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_6_bits_tin_vt_valid = mem_tin_vt_valid_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_6_bits_tin_vt_addr = mem_tin_vt_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_6_bits_tin_vu_valid = mem_tin_vu_valid_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_6_bits_tin_vu_addr = mem_tin_vu_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_6_bits_m = mem_m_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_7_valid = active[7]; // @[Fifo4e.scala 140:32]
- assign io_entry_7_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_7_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_7_bits_tin_vt_valid = mem_tin_vt_valid_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_7_bits_tin_vt_addr = mem_tin_vt_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_7_bits_tin_vu_valid = mem_tin_vu_valid_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_7_bits_tin_vu_addr = mem_tin_vu_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_7_bits_m = mem_m_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- always @(posedge clock) begin
- if (mem_tin_op_MPORT_en & mem_tin_op_MPORT_mask) begin
- mem_tin_op[mem_tin_op_MPORT_addr] <= mem_tin_op_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_1_en & mem_tin_op_MPORT_1_mask) begin
- mem_tin_op[mem_tin_op_MPORT_1_addr] <= mem_tin_op_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_2_en & mem_tin_op_MPORT_2_mask) begin
- mem_tin_op[mem_tin_op_MPORT_2_addr] <= mem_tin_op_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_3_en & mem_tin_op_MPORT_3_mask) begin
- mem_tin_op[mem_tin_op_MPORT_3_addr] <= mem_tin_op_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_4_en & mem_tin_op_MPORT_4_mask) begin
- mem_tin_op[mem_tin_op_MPORT_4_addr] <= mem_tin_op_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_5_en & mem_tin_op_MPORT_5_mask) begin
- mem_tin_op[mem_tin_op_MPORT_5_addr] <= mem_tin_op_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_6_en & mem_tin_op_MPORT_6_mask) begin
- mem_tin_op[mem_tin_op_MPORT_6_addr] <= mem_tin_op_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_7_en & mem_tin_op_MPORT_7_mask) begin
- mem_tin_op[mem_tin_op_MPORT_7_addr] <= mem_tin_op_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_8_en & mem_tin_op_MPORT_8_mask) begin
- mem_tin_op[mem_tin_op_MPORT_8_addr] <= mem_tin_op_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_9_en & mem_tin_op_MPORT_9_mask) begin
- mem_tin_op[mem_tin_op_MPORT_9_addr] <= mem_tin_op_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_10_en & mem_tin_op_MPORT_10_mask) begin
- mem_tin_op[mem_tin_op_MPORT_10_addr] <= mem_tin_op_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_11_en & mem_tin_op_MPORT_11_mask) begin
- mem_tin_op[mem_tin_op_MPORT_11_addr] <= mem_tin_op_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_12_en & mem_tin_op_MPORT_12_mask) begin
- mem_tin_op[mem_tin_op_MPORT_12_addr] <= mem_tin_op_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_13_en & mem_tin_op_MPORT_13_mask) begin
- mem_tin_op[mem_tin_op_MPORT_13_addr] <= mem_tin_op_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_14_en & mem_tin_op_MPORT_14_mask) begin
- mem_tin_op[mem_tin_op_MPORT_14_addr] <= mem_tin_op_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_15_en & mem_tin_op_MPORT_15_mask) begin
- mem_tin_op[mem_tin_op_MPORT_15_addr] <= mem_tin_op_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_16_en & mem_tin_op_MPORT_16_mask) begin
- mem_tin_op[mem_tin_op_MPORT_16_addr] <= mem_tin_op_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_17_en & mem_tin_op_MPORT_17_mask) begin
- mem_tin_op[mem_tin_op_MPORT_17_addr] <= mem_tin_op_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_18_en & mem_tin_op_MPORT_18_mask) begin
- mem_tin_op[mem_tin_op_MPORT_18_addr] <= mem_tin_op_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_19_en & mem_tin_op_MPORT_19_mask) begin
- mem_tin_op[mem_tin_op_MPORT_19_addr] <= mem_tin_op_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_20_en & mem_tin_op_MPORT_20_mask) begin
- mem_tin_op[mem_tin_op_MPORT_20_addr] <= mem_tin_op_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_21_en & mem_tin_op_MPORT_21_mask) begin
- mem_tin_op[mem_tin_op_MPORT_21_addr] <= mem_tin_op_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_22_en & mem_tin_op_MPORT_22_mask) begin
- mem_tin_op[mem_tin_op_MPORT_22_addr] <= mem_tin_op_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_23_en & mem_tin_op_MPORT_23_mask) begin
- mem_tin_op[mem_tin_op_MPORT_23_addr] <= mem_tin_op_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_24_en & mem_tin_op_MPORT_24_mask) begin
- mem_tin_op[mem_tin_op_MPORT_24_addr] <= mem_tin_op_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_25_en & mem_tin_op_MPORT_25_mask) begin
- mem_tin_op[mem_tin_op_MPORT_25_addr] <= mem_tin_op_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_26_en & mem_tin_op_MPORT_26_mask) begin
- mem_tin_op[mem_tin_op_MPORT_26_addr] <= mem_tin_op_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_27_en & mem_tin_op_MPORT_27_mask) begin
- mem_tin_op[mem_tin_op_MPORT_27_addr] <= mem_tin_op_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_28_en & mem_tin_op_MPORT_28_mask) begin
- mem_tin_op[mem_tin_op_MPORT_28_addr] <= mem_tin_op_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_29_en & mem_tin_op_MPORT_29_mask) begin
- mem_tin_op[mem_tin_op_MPORT_29_addr] <= mem_tin_op_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_30_en & mem_tin_op_MPORT_30_mask) begin
- mem_tin_op[mem_tin_op_MPORT_30_addr] <= mem_tin_op_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_31_en & mem_tin_op_MPORT_31_mask) begin
- mem_tin_op[mem_tin_op_MPORT_31_addr] <= mem_tin_op_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_en & mem_tin_f2_MPORT_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_addr] <= mem_tin_f2_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_1_en & mem_tin_f2_MPORT_1_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_1_addr] <= mem_tin_f2_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_2_en & mem_tin_f2_MPORT_2_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_2_addr] <= mem_tin_f2_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_3_en & mem_tin_f2_MPORT_3_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_3_addr] <= mem_tin_f2_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_4_en & mem_tin_f2_MPORT_4_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_4_addr] <= mem_tin_f2_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_5_en & mem_tin_f2_MPORT_5_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_5_addr] <= mem_tin_f2_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_6_en & mem_tin_f2_MPORT_6_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_6_addr] <= mem_tin_f2_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_7_en & mem_tin_f2_MPORT_7_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_7_addr] <= mem_tin_f2_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_8_en & mem_tin_f2_MPORT_8_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_8_addr] <= mem_tin_f2_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_9_en & mem_tin_f2_MPORT_9_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_9_addr] <= mem_tin_f2_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_10_en & mem_tin_f2_MPORT_10_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_10_addr] <= mem_tin_f2_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_11_en & mem_tin_f2_MPORT_11_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_11_addr] <= mem_tin_f2_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_12_en & mem_tin_f2_MPORT_12_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_12_addr] <= mem_tin_f2_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_13_en & mem_tin_f2_MPORT_13_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_13_addr] <= mem_tin_f2_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_14_en & mem_tin_f2_MPORT_14_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_14_addr] <= mem_tin_f2_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_15_en & mem_tin_f2_MPORT_15_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_15_addr] <= mem_tin_f2_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_16_en & mem_tin_f2_MPORT_16_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_16_addr] <= mem_tin_f2_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_17_en & mem_tin_f2_MPORT_17_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_17_addr] <= mem_tin_f2_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_18_en & mem_tin_f2_MPORT_18_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_18_addr] <= mem_tin_f2_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_19_en & mem_tin_f2_MPORT_19_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_19_addr] <= mem_tin_f2_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_20_en & mem_tin_f2_MPORT_20_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_20_addr] <= mem_tin_f2_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_21_en & mem_tin_f2_MPORT_21_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_21_addr] <= mem_tin_f2_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_22_en & mem_tin_f2_MPORT_22_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_22_addr] <= mem_tin_f2_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_23_en & mem_tin_f2_MPORT_23_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_23_addr] <= mem_tin_f2_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_24_en & mem_tin_f2_MPORT_24_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_24_addr] <= mem_tin_f2_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_25_en & mem_tin_f2_MPORT_25_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_25_addr] <= mem_tin_f2_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_26_en & mem_tin_f2_MPORT_26_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_26_addr] <= mem_tin_f2_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_27_en & mem_tin_f2_MPORT_27_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_27_addr] <= mem_tin_f2_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_28_en & mem_tin_f2_MPORT_28_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_28_addr] <= mem_tin_f2_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_29_en & mem_tin_f2_MPORT_29_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_29_addr] <= mem_tin_f2_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_30_en & mem_tin_f2_MPORT_30_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_30_addr] <= mem_tin_f2_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_f2_MPORT_31_en & mem_tin_f2_MPORT_31_mask) begin
- mem_tin_f2[mem_tin_f2_MPORT_31_addr] <= mem_tin_f2_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_en & mem_tin_sz_MPORT_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_addr] <= mem_tin_sz_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_1_en & mem_tin_sz_MPORT_1_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_1_addr] <= mem_tin_sz_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_2_en & mem_tin_sz_MPORT_2_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_2_addr] <= mem_tin_sz_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_3_en & mem_tin_sz_MPORT_3_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_3_addr] <= mem_tin_sz_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_4_en & mem_tin_sz_MPORT_4_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_4_addr] <= mem_tin_sz_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_5_en & mem_tin_sz_MPORT_5_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_5_addr] <= mem_tin_sz_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_6_en & mem_tin_sz_MPORT_6_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_6_addr] <= mem_tin_sz_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_7_en & mem_tin_sz_MPORT_7_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_7_addr] <= mem_tin_sz_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_8_en & mem_tin_sz_MPORT_8_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_8_addr] <= mem_tin_sz_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_9_en & mem_tin_sz_MPORT_9_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_9_addr] <= mem_tin_sz_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_10_en & mem_tin_sz_MPORT_10_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_10_addr] <= mem_tin_sz_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_11_en & mem_tin_sz_MPORT_11_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_11_addr] <= mem_tin_sz_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_12_en & mem_tin_sz_MPORT_12_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_12_addr] <= mem_tin_sz_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_13_en & mem_tin_sz_MPORT_13_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_13_addr] <= mem_tin_sz_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_14_en & mem_tin_sz_MPORT_14_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_14_addr] <= mem_tin_sz_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_15_en & mem_tin_sz_MPORT_15_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_15_addr] <= mem_tin_sz_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_16_en & mem_tin_sz_MPORT_16_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_16_addr] <= mem_tin_sz_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_17_en & mem_tin_sz_MPORT_17_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_17_addr] <= mem_tin_sz_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_18_en & mem_tin_sz_MPORT_18_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_18_addr] <= mem_tin_sz_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_19_en & mem_tin_sz_MPORT_19_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_19_addr] <= mem_tin_sz_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_20_en & mem_tin_sz_MPORT_20_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_20_addr] <= mem_tin_sz_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_21_en & mem_tin_sz_MPORT_21_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_21_addr] <= mem_tin_sz_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_22_en & mem_tin_sz_MPORT_22_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_22_addr] <= mem_tin_sz_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_23_en & mem_tin_sz_MPORT_23_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_23_addr] <= mem_tin_sz_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_24_en & mem_tin_sz_MPORT_24_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_24_addr] <= mem_tin_sz_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_25_en & mem_tin_sz_MPORT_25_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_25_addr] <= mem_tin_sz_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_26_en & mem_tin_sz_MPORT_26_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_26_addr] <= mem_tin_sz_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_27_en & mem_tin_sz_MPORT_27_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_27_addr] <= mem_tin_sz_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_28_en & mem_tin_sz_MPORT_28_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_28_addr] <= mem_tin_sz_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_29_en & mem_tin_sz_MPORT_29_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_29_addr] <= mem_tin_sz_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_30_en & mem_tin_sz_MPORT_30_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_30_addr] <= mem_tin_sz_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sz_MPORT_31_en & mem_tin_sz_MPORT_31_mask) begin
- mem_tin_sz[mem_tin_sz_MPORT_31_addr] <= mem_tin_sz_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_en & mem_tin_vd_addr_MPORT_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_addr] <= mem_tin_vd_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_1_en & mem_tin_vd_addr_MPORT_1_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_1_addr] <= mem_tin_vd_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_2_en & mem_tin_vd_addr_MPORT_2_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_2_addr] <= mem_tin_vd_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_3_en & mem_tin_vd_addr_MPORT_3_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_3_addr] <= mem_tin_vd_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_4_en & mem_tin_vd_addr_MPORT_4_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_4_addr] <= mem_tin_vd_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_5_en & mem_tin_vd_addr_MPORT_5_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_5_addr] <= mem_tin_vd_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_6_en & mem_tin_vd_addr_MPORT_6_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_6_addr] <= mem_tin_vd_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_7_en & mem_tin_vd_addr_MPORT_7_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_7_addr] <= mem_tin_vd_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_8_en & mem_tin_vd_addr_MPORT_8_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_8_addr] <= mem_tin_vd_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_9_en & mem_tin_vd_addr_MPORT_9_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_9_addr] <= mem_tin_vd_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_10_en & mem_tin_vd_addr_MPORT_10_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_10_addr] <= mem_tin_vd_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_11_en & mem_tin_vd_addr_MPORT_11_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_11_addr] <= mem_tin_vd_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_12_en & mem_tin_vd_addr_MPORT_12_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_12_addr] <= mem_tin_vd_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_13_en & mem_tin_vd_addr_MPORT_13_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_13_addr] <= mem_tin_vd_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_14_en & mem_tin_vd_addr_MPORT_14_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_14_addr] <= mem_tin_vd_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_15_en & mem_tin_vd_addr_MPORT_15_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_15_addr] <= mem_tin_vd_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_16_en & mem_tin_vd_addr_MPORT_16_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_16_addr] <= mem_tin_vd_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_17_en & mem_tin_vd_addr_MPORT_17_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_17_addr] <= mem_tin_vd_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_18_en & mem_tin_vd_addr_MPORT_18_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_18_addr] <= mem_tin_vd_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_19_en & mem_tin_vd_addr_MPORT_19_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_19_addr] <= mem_tin_vd_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_20_en & mem_tin_vd_addr_MPORT_20_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_20_addr] <= mem_tin_vd_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_21_en & mem_tin_vd_addr_MPORT_21_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_21_addr] <= mem_tin_vd_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_22_en & mem_tin_vd_addr_MPORT_22_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_22_addr] <= mem_tin_vd_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_23_en & mem_tin_vd_addr_MPORT_23_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_23_addr] <= mem_tin_vd_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_24_en & mem_tin_vd_addr_MPORT_24_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_24_addr] <= mem_tin_vd_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_25_en & mem_tin_vd_addr_MPORT_25_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_25_addr] <= mem_tin_vd_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_26_en & mem_tin_vd_addr_MPORT_26_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_26_addr] <= mem_tin_vd_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_27_en & mem_tin_vd_addr_MPORT_27_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_27_addr] <= mem_tin_vd_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_28_en & mem_tin_vd_addr_MPORT_28_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_28_addr] <= mem_tin_vd_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_29_en & mem_tin_vd_addr_MPORT_29_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_29_addr] <= mem_tin_vd_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_30_en & mem_tin_vd_addr_MPORT_30_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_30_addr] <= mem_tin_vd_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_31_en & mem_tin_vd_addr_MPORT_31_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_31_addr] <= mem_tin_vd_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_en & mem_tin_ve_addr_MPORT_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_addr] <= mem_tin_ve_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_1_en & mem_tin_ve_addr_MPORT_1_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_1_addr] <= mem_tin_ve_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_2_en & mem_tin_ve_addr_MPORT_2_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_2_addr] <= mem_tin_ve_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_3_en & mem_tin_ve_addr_MPORT_3_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_3_addr] <= mem_tin_ve_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_4_en & mem_tin_ve_addr_MPORT_4_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_4_addr] <= mem_tin_ve_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_5_en & mem_tin_ve_addr_MPORT_5_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_5_addr] <= mem_tin_ve_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_6_en & mem_tin_ve_addr_MPORT_6_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_6_addr] <= mem_tin_ve_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_7_en & mem_tin_ve_addr_MPORT_7_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_7_addr] <= mem_tin_ve_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_8_en & mem_tin_ve_addr_MPORT_8_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_8_addr] <= mem_tin_ve_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_9_en & mem_tin_ve_addr_MPORT_9_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_9_addr] <= mem_tin_ve_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_10_en & mem_tin_ve_addr_MPORT_10_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_10_addr] <= mem_tin_ve_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_11_en & mem_tin_ve_addr_MPORT_11_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_11_addr] <= mem_tin_ve_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_12_en & mem_tin_ve_addr_MPORT_12_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_12_addr] <= mem_tin_ve_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_13_en & mem_tin_ve_addr_MPORT_13_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_13_addr] <= mem_tin_ve_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_14_en & mem_tin_ve_addr_MPORT_14_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_14_addr] <= mem_tin_ve_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_15_en & mem_tin_ve_addr_MPORT_15_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_15_addr] <= mem_tin_ve_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_16_en & mem_tin_ve_addr_MPORT_16_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_16_addr] <= mem_tin_ve_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_17_en & mem_tin_ve_addr_MPORT_17_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_17_addr] <= mem_tin_ve_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_18_en & mem_tin_ve_addr_MPORT_18_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_18_addr] <= mem_tin_ve_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_19_en & mem_tin_ve_addr_MPORT_19_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_19_addr] <= mem_tin_ve_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_20_en & mem_tin_ve_addr_MPORT_20_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_20_addr] <= mem_tin_ve_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_21_en & mem_tin_ve_addr_MPORT_21_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_21_addr] <= mem_tin_ve_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_22_en & mem_tin_ve_addr_MPORT_22_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_22_addr] <= mem_tin_ve_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_23_en & mem_tin_ve_addr_MPORT_23_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_23_addr] <= mem_tin_ve_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_24_en & mem_tin_ve_addr_MPORT_24_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_24_addr] <= mem_tin_ve_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_25_en & mem_tin_ve_addr_MPORT_25_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_25_addr] <= mem_tin_ve_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_26_en & mem_tin_ve_addr_MPORT_26_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_26_addr] <= mem_tin_ve_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_27_en & mem_tin_ve_addr_MPORT_27_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_27_addr] <= mem_tin_ve_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_28_en & mem_tin_ve_addr_MPORT_28_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_28_addr] <= mem_tin_ve_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_29_en & mem_tin_ve_addr_MPORT_29_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_29_addr] <= mem_tin_ve_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_30_en & mem_tin_ve_addr_MPORT_30_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_30_addr] <= mem_tin_ve_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_ve_addr_MPORT_31_en & mem_tin_ve_addr_MPORT_31_mask) begin
- mem_tin_ve_addr[mem_tin_ve_addr_MPORT_31_addr] <= mem_tin_ve_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_en & mem_tin_vs_valid_MPORT_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_addr] <= mem_tin_vs_valid_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_1_en & mem_tin_vs_valid_MPORT_1_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_1_addr] <= mem_tin_vs_valid_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_2_en & mem_tin_vs_valid_MPORT_2_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_2_addr] <= mem_tin_vs_valid_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_3_en & mem_tin_vs_valid_MPORT_3_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_3_addr] <= mem_tin_vs_valid_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_4_en & mem_tin_vs_valid_MPORT_4_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_4_addr] <= mem_tin_vs_valid_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_5_en & mem_tin_vs_valid_MPORT_5_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_5_addr] <= mem_tin_vs_valid_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_6_en & mem_tin_vs_valid_MPORT_6_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_6_addr] <= mem_tin_vs_valid_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_7_en & mem_tin_vs_valid_MPORT_7_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_7_addr] <= mem_tin_vs_valid_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_8_en & mem_tin_vs_valid_MPORT_8_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_8_addr] <= mem_tin_vs_valid_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_9_en & mem_tin_vs_valid_MPORT_9_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_9_addr] <= mem_tin_vs_valid_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_10_en & mem_tin_vs_valid_MPORT_10_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_10_addr] <= mem_tin_vs_valid_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_11_en & mem_tin_vs_valid_MPORT_11_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_11_addr] <= mem_tin_vs_valid_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_12_en & mem_tin_vs_valid_MPORT_12_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_12_addr] <= mem_tin_vs_valid_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_13_en & mem_tin_vs_valid_MPORT_13_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_13_addr] <= mem_tin_vs_valid_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_14_en & mem_tin_vs_valid_MPORT_14_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_14_addr] <= mem_tin_vs_valid_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_15_en & mem_tin_vs_valid_MPORT_15_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_15_addr] <= mem_tin_vs_valid_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_16_en & mem_tin_vs_valid_MPORT_16_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_16_addr] <= mem_tin_vs_valid_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_17_en & mem_tin_vs_valid_MPORT_17_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_17_addr] <= mem_tin_vs_valid_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_18_en & mem_tin_vs_valid_MPORT_18_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_18_addr] <= mem_tin_vs_valid_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_19_en & mem_tin_vs_valid_MPORT_19_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_19_addr] <= mem_tin_vs_valid_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_20_en & mem_tin_vs_valid_MPORT_20_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_20_addr] <= mem_tin_vs_valid_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_21_en & mem_tin_vs_valid_MPORT_21_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_21_addr] <= mem_tin_vs_valid_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_22_en & mem_tin_vs_valid_MPORT_22_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_22_addr] <= mem_tin_vs_valid_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_23_en & mem_tin_vs_valid_MPORT_23_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_23_addr] <= mem_tin_vs_valid_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_24_en & mem_tin_vs_valid_MPORT_24_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_24_addr] <= mem_tin_vs_valid_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_25_en & mem_tin_vs_valid_MPORT_25_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_25_addr] <= mem_tin_vs_valid_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_26_en & mem_tin_vs_valid_MPORT_26_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_26_addr] <= mem_tin_vs_valid_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_27_en & mem_tin_vs_valid_MPORT_27_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_27_addr] <= mem_tin_vs_valid_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_28_en & mem_tin_vs_valid_MPORT_28_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_28_addr] <= mem_tin_vs_valid_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_29_en & mem_tin_vs_valid_MPORT_29_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_29_addr] <= mem_tin_vs_valid_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_30_en & mem_tin_vs_valid_MPORT_30_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_30_addr] <= mem_tin_vs_valid_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_31_en & mem_tin_vs_valid_MPORT_31_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_31_addr] <= mem_tin_vs_valid_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_en & mem_tin_vs_addr_MPORT_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_addr] <= mem_tin_vs_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_1_en & mem_tin_vs_addr_MPORT_1_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_1_addr] <= mem_tin_vs_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_2_en & mem_tin_vs_addr_MPORT_2_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_2_addr] <= mem_tin_vs_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_3_en & mem_tin_vs_addr_MPORT_3_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_3_addr] <= mem_tin_vs_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_4_en & mem_tin_vs_addr_MPORT_4_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_4_addr] <= mem_tin_vs_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_5_en & mem_tin_vs_addr_MPORT_5_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_5_addr] <= mem_tin_vs_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_6_en & mem_tin_vs_addr_MPORT_6_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_6_addr] <= mem_tin_vs_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_7_en & mem_tin_vs_addr_MPORT_7_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_7_addr] <= mem_tin_vs_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_8_en & mem_tin_vs_addr_MPORT_8_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_8_addr] <= mem_tin_vs_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_9_en & mem_tin_vs_addr_MPORT_9_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_9_addr] <= mem_tin_vs_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_10_en & mem_tin_vs_addr_MPORT_10_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_10_addr] <= mem_tin_vs_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_11_en & mem_tin_vs_addr_MPORT_11_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_11_addr] <= mem_tin_vs_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_12_en & mem_tin_vs_addr_MPORT_12_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_12_addr] <= mem_tin_vs_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_13_en & mem_tin_vs_addr_MPORT_13_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_13_addr] <= mem_tin_vs_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_14_en & mem_tin_vs_addr_MPORT_14_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_14_addr] <= mem_tin_vs_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_15_en & mem_tin_vs_addr_MPORT_15_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_15_addr] <= mem_tin_vs_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_16_en & mem_tin_vs_addr_MPORT_16_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_16_addr] <= mem_tin_vs_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_17_en & mem_tin_vs_addr_MPORT_17_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_17_addr] <= mem_tin_vs_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_18_en & mem_tin_vs_addr_MPORT_18_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_18_addr] <= mem_tin_vs_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_19_en & mem_tin_vs_addr_MPORT_19_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_19_addr] <= mem_tin_vs_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_20_en & mem_tin_vs_addr_MPORT_20_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_20_addr] <= mem_tin_vs_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_21_en & mem_tin_vs_addr_MPORT_21_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_21_addr] <= mem_tin_vs_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_22_en & mem_tin_vs_addr_MPORT_22_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_22_addr] <= mem_tin_vs_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_23_en & mem_tin_vs_addr_MPORT_23_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_23_addr] <= mem_tin_vs_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_24_en & mem_tin_vs_addr_MPORT_24_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_24_addr] <= mem_tin_vs_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_25_en & mem_tin_vs_addr_MPORT_25_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_25_addr] <= mem_tin_vs_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_26_en & mem_tin_vs_addr_MPORT_26_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_26_addr] <= mem_tin_vs_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_27_en & mem_tin_vs_addr_MPORT_27_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_27_addr] <= mem_tin_vs_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_28_en & mem_tin_vs_addr_MPORT_28_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_28_addr] <= mem_tin_vs_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_29_en & mem_tin_vs_addr_MPORT_29_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_29_addr] <= mem_tin_vs_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_30_en & mem_tin_vs_addr_MPORT_30_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_30_addr] <= mem_tin_vs_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_31_en & mem_tin_vs_addr_MPORT_31_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_31_addr] <= mem_tin_vs_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_en & mem_tin_vs_tag_MPORT_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_addr] <= mem_tin_vs_tag_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_1_en & mem_tin_vs_tag_MPORT_1_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_1_addr] <= mem_tin_vs_tag_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_2_en & mem_tin_vs_tag_MPORT_2_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_2_addr] <= mem_tin_vs_tag_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_3_en & mem_tin_vs_tag_MPORT_3_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_3_addr] <= mem_tin_vs_tag_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_4_en & mem_tin_vs_tag_MPORT_4_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_4_addr] <= mem_tin_vs_tag_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_5_en & mem_tin_vs_tag_MPORT_5_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_5_addr] <= mem_tin_vs_tag_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_6_en & mem_tin_vs_tag_MPORT_6_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_6_addr] <= mem_tin_vs_tag_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_7_en & mem_tin_vs_tag_MPORT_7_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_7_addr] <= mem_tin_vs_tag_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_8_en & mem_tin_vs_tag_MPORT_8_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_8_addr] <= mem_tin_vs_tag_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_9_en & mem_tin_vs_tag_MPORT_9_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_9_addr] <= mem_tin_vs_tag_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_10_en & mem_tin_vs_tag_MPORT_10_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_10_addr] <= mem_tin_vs_tag_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_11_en & mem_tin_vs_tag_MPORT_11_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_11_addr] <= mem_tin_vs_tag_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_12_en & mem_tin_vs_tag_MPORT_12_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_12_addr] <= mem_tin_vs_tag_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_13_en & mem_tin_vs_tag_MPORT_13_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_13_addr] <= mem_tin_vs_tag_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_14_en & mem_tin_vs_tag_MPORT_14_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_14_addr] <= mem_tin_vs_tag_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_15_en & mem_tin_vs_tag_MPORT_15_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_15_addr] <= mem_tin_vs_tag_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_16_en & mem_tin_vs_tag_MPORT_16_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_16_addr] <= mem_tin_vs_tag_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_17_en & mem_tin_vs_tag_MPORT_17_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_17_addr] <= mem_tin_vs_tag_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_18_en & mem_tin_vs_tag_MPORT_18_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_18_addr] <= mem_tin_vs_tag_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_19_en & mem_tin_vs_tag_MPORT_19_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_19_addr] <= mem_tin_vs_tag_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_20_en & mem_tin_vs_tag_MPORT_20_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_20_addr] <= mem_tin_vs_tag_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_21_en & mem_tin_vs_tag_MPORT_21_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_21_addr] <= mem_tin_vs_tag_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_22_en & mem_tin_vs_tag_MPORT_22_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_22_addr] <= mem_tin_vs_tag_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_23_en & mem_tin_vs_tag_MPORT_23_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_23_addr] <= mem_tin_vs_tag_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_24_en & mem_tin_vs_tag_MPORT_24_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_24_addr] <= mem_tin_vs_tag_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_25_en & mem_tin_vs_tag_MPORT_25_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_25_addr] <= mem_tin_vs_tag_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_26_en & mem_tin_vs_tag_MPORT_26_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_26_addr] <= mem_tin_vs_tag_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_27_en & mem_tin_vs_tag_MPORT_27_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_27_addr] <= mem_tin_vs_tag_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_28_en & mem_tin_vs_tag_MPORT_28_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_28_addr] <= mem_tin_vs_tag_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_29_en & mem_tin_vs_tag_MPORT_29_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_29_addr] <= mem_tin_vs_tag_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_30_en & mem_tin_vs_tag_MPORT_30_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_30_addr] <= mem_tin_vs_tag_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_31_en & mem_tin_vs_tag_MPORT_31_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_31_addr] <= mem_tin_vs_tag_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_en & mem_tin_vt_valid_MPORT_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_addr] <= mem_tin_vt_valid_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_1_en & mem_tin_vt_valid_MPORT_1_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_1_addr] <= mem_tin_vt_valid_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_2_en & mem_tin_vt_valid_MPORT_2_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_2_addr] <= mem_tin_vt_valid_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_3_en & mem_tin_vt_valid_MPORT_3_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_3_addr] <= mem_tin_vt_valid_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_4_en & mem_tin_vt_valid_MPORT_4_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_4_addr] <= mem_tin_vt_valid_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_5_en & mem_tin_vt_valid_MPORT_5_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_5_addr] <= mem_tin_vt_valid_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_6_en & mem_tin_vt_valid_MPORT_6_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_6_addr] <= mem_tin_vt_valid_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_7_en & mem_tin_vt_valid_MPORT_7_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_7_addr] <= mem_tin_vt_valid_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_8_en & mem_tin_vt_valid_MPORT_8_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_8_addr] <= mem_tin_vt_valid_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_9_en & mem_tin_vt_valid_MPORT_9_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_9_addr] <= mem_tin_vt_valid_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_10_en & mem_tin_vt_valid_MPORT_10_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_10_addr] <= mem_tin_vt_valid_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_11_en & mem_tin_vt_valid_MPORT_11_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_11_addr] <= mem_tin_vt_valid_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_12_en & mem_tin_vt_valid_MPORT_12_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_12_addr] <= mem_tin_vt_valid_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_13_en & mem_tin_vt_valid_MPORT_13_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_13_addr] <= mem_tin_vt_valid_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_14_en & mem_tin_vt_valid_MPORT_14_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_14_addr] <= mem_tin_vt_valid_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_15_en & mem_tin_vt_valid_MPORT_15_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_15_addr] <= mem_tin_vt_valid_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_16_en & mem_tin_vt_valid_MPORT_16_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_16_addr] <= mem_tin_vt_valid_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_17_en & mem_tin_vt_valid_MPORT_17_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_17_addr] <= mem_tin_vt_valid_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_18_en & mem_tin_vt_valid_MPORT_18_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_18_addr] <= mem_tin_vt_valid_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_19_en & mem_tin_vt_valid_MPORT_19_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_19_addr] <= mem_tin_vt_valid_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_20_en & mem_tin_vt_valid_MPORT_20_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_20_addr] <= mem_tin_vt_valid_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_21_en & mem_tin_vt_valid_MPORT_21_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_21_addr] <= mem_tin_vt_valid_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_22_en & mem_tin_vt_valid_MPORT_22_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_22_addr] <= mem_tin_vt_valid_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_23_en & mem_tin_vt_valid_MPORT_23_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_23_addr] <= mem_tin_vt_valid_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_24_en & mem_tin_vt_valid_MPORT_24_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_24_addr] <= mem_tin_vt_valid_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_25_en & mem_tin_vt_valid_MPORT_25_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_25_addr] <= mem_tin_vt_valid_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_26_en & mem_tin_vt_valid_MPORT_26_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_26_addr] <= mem_tin_vt_valid_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_27_en & mem_tin_vt_valid_MPORT_27_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_27_addr] <= mem_tin_vt_valid_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_28_en & mem_tin_vt_valid_MPORT_28_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_28_addr] <= mem_tin_vt_valid_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_29_en & mem_tin_vt_valid_MPORT_29_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_29_addr] <= mem_tin_vt_valid_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_30_en & mem_tin_vt_valid_MPORT_30_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_30_addr] <= mem_tin_vt_valid_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_valid_MPORT_31_en & mem_tin_vt_valid_MPORT_31_mask) begin
- mem_tin_vt_valid[mem_tin_vt_valid_MPORT_31_addr] <= mem_tin_vt_valid_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_en & mem_tin_vt_addr_MPORT_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_addr] <= mem_tin_vt_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_1_en & mem_tin_vt_addr_MPORT_1_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_1_addr] <= mem_tin_vt_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_2_en & mem_tin_vt_addr_MPORT_2_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_2_addr] <= mem_tin_vt_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_3_en & mem_tin_vt_addr_MPORT_3_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_3_addr] <= mem_tin_vt_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_4_en & mem_tin_vt_addr_MPORT_4_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_4_addr] <= mem_tin_vt_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_5_en & mem_tin_vt_addr_MPORT_5_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_5_addr] <= mem_tin_vt_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_6_en & mem_tin_vt_addr_MPORT_6_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_6_addr] <= mem_tin_vt_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_7_en & mem_tin_vt_addr_MPORT_7_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_7_addr] <= mem_tin_vt_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_8_en & mem_tin_vt_addr_MPORT_8_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_8_addr] <= mem_tin_vt_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_9_en & mem_tin_vt_addr_MPORT_9_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_9_addr] <= mem_tin_vt_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_10_en & mem_tin_vt_addr_MPORT_10_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_10_addr] <= mem_tin_vt_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_11_en & mem_tin_vt_addr_MPORT_11_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_11_addr] <= mem_tin_vt_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_12_en & mem_tin_vt_addr_MPORT_12_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_12_addr] <= mem_tin_vt_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_13_en & mem_tin_vt_addr_MPORT_13_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_13_addr] <= mem_tin_vt_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_14_en & mem_tin_vt_addr_MPORT_14_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_14_addr] <= mem_tin_vt_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_15_en & mem_tin_vt_addr_MPORT_15_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_15_addr] <= mem_tin_vt_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_16_en & mem_tin_vt_addr_MPORT_16_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_16_addr] <= mem_tin_vt_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_17_en & mem_tin_vt_addr_MPORT_17_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_17_addr] <= mem_tin_vt_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_18_en & mem_tin_vt_addr_MPORT_18_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_18_addr] <= mem_tin_vt_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_19_en & mem_tin_vt_addr_MPORT_19_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_19_addr] <= mem_tin_vt_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_20_en & mem_tin_vt_addr_MPORT_20_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_20_addr] <= mem_tin_vt_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_21_en & mem_tin_vt_addr_MPORT_21_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_21_addr] <= mem_tin_vt_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_22_en & mem_tin_vt_addr_MPORT_22_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_22_addr] <= mem_tin_vt_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_23_en & mem_tin_vt_addr_MPORT_23_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_23_addr] <= mem_tin_vt_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_24_en & mem_tin_vt_addr_MPORT_24_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_24_addr] <= mem_tin_vt_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_25_en & mem_tin_vt_addr_MPORT_25_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_25_addr] <= mem_tin_vt_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_26_en & mem_tin_vt_addr_MPORT_26_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_26_addr] <= mem_tin_vt_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_27_en & mem_tin_vt_addr_MPORT_27_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_27_addr] <= mem_tin_vt_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_28_en & mem_tin_vt_addr_MPORT_28_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_28_addr] <= mem_tin_vt_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_29_en & mem_tin_vt_addr_MPORT_29_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_29_addr] <= mem_tin_vt_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_30_en & mem_tin_vt_addr_MPORT_30_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_30_addr] <= mem_tin_vt_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_addr_MPORT_31_en & mem_tin_vt_addr_MPORT_31_mask) begin
- mem_tin_vt_addr[mem_tin_vt_addr_MPORT_31_addr] <= mem_tin_vt_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_en & mem_tin_vt_tag_MPORT_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_addr] <= mem_tin_vt_tag_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_1_en & mem_tin_vt_tag_MPORT_1_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_1_addr] <= mem_tin_vt_tag_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_2_en & mem_tin_vt_tag_MPORT_2_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_2_addr] <= mem_tin_vt_tag_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_3_en & mem_tin_vt_tag_MPORT_3_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_3_addr] <= mem_tin_vt_tag_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_4_en & mem_tin_vt_tag_MPORT_4_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_4_addr] <= mem_tin_vt_tag_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_5_en & mem_tin_vt_tag_MPORT_5_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_5_addr] <= mem_tin_vt_tag_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_6_en & mem_tin_vt_tag_MPORT_6_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_6_addr] <= mem_tin_vt_tag_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_7_en & mem_tin_vt_tag_MPORT_7_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_7_addr] <= mem_tin_vt_tag_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_8_en & mem_tin_vt_tag_MPORT_8_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_8_addr] <= mem_tin_vt_tag_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_9_en & mem_tin_vt_tag_MPORT_9_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_9_addr] <= mem_tin_vt_tag_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_10_en & mem_tin_vt_tag_MPORT_10_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_10_addr] <= mem_tin_vt_tag_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_11_en & mem_tin_vt_tag_MPORT_11_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_11_addr] <= mem_tin_vt_tag_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_12_en & mem_tin_vt_tag_MPORT_12_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_12_addr] <= mem_tin_vt_tag_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_13_en & mem_tin_vt_tag_MPORT_13_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_13_addr] <= mem_tin_vt_tag_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_14_en & mem_tin_vt_tag_MPORT_14_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_14_addr] <= mem_tin_vt_tag_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_15_en & mem_tin_vt_tag_MPORT_15_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_15_addr] <= mem_tin_vt_tag_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_16_en & mem_tin_vt_tag_MPORT_16_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_16_addr] <= mem_tin_vt_tag_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_17_en & mem_tin_vt_tag_MPORT_17_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_17_addr] <= mem_tin_vt_tag_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_18_en & mem_tin_vt_tag_MPORT_18_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_18_addr] <= mem_tin_vt_tag_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_19_en & mem_tin_vt_tag_MPORT_19_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_19_addr] <= mem_tin_vt_tag_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_20_en & mem_tin_vt_tag_MPORT_20_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_20_addr] <= mem_tin_vt_tag_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_21_en & mem_tin_vt_tag_MPORT_21_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_21_addr] <= mem_tin_vt_tag_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_22_en & mem_tin_vt_tag_MPORT_22_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_22_addr] <= mem_tin_vt_tag_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_23_en & mem_tin_vt_tag_MPORT_23_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_23_addr] <= mem_tin_vt_tag_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_24_en & mem_tin_vt_tag_MPORT_24_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_24_addr] <= mem_tin_vt_tag_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_25_en & mem_tin_vt_tag_MPORT_25_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_25_addr] <= mem_tin_vt_tag_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_26_en & mem_tin_vt_tag_MPORT_26_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_26_addr] <= mem_tin_vt_tag_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_27_en & mem_tin_vt_tag_MPORT_27_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_27_addr] <= mem_tin_vt_tag_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_28_en & mem_tin_vt_tag_MPORT_28_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_28_addr] <= mem_tin_vt_tag_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_29_en & mem_tin_vt_tag_MPORT_29_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_29_addr] <= mem_tin_vt_tag_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_30_en & mem_tin_vt_tag_MPORT_30_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_30_addr] <= mem_tin_vt_tag_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vt_tag_MPORT_31_en & mem_tin_vt_tag_MPORT_31_mask) begin
- mem_tin_vt_tag[mem_tin_vt_tag_MPORT_31_addr] <= mem_tin_vt_tag_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_en & mem_tin_vu_valid_MPORT_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_addr] <= mem_tin_vu_valid_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_1_en & mem_tin_vu_valid_MPORT_1_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_1_addr] <= mem_tin_vu_valid_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_2_en & mem_tin_vu_valid_MPORT_2_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_2_addr] <= mem_tin_vu_valid_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_3_en & mem_tin_vu_valid_MPORT_3_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_3_addr] <= mem_tin_vu_valid_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_4_en & mem_tin_vu_valid_MPORT_4_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_4_addr] <= mem_tin_vu_valid_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_5_en & mem_tin_vu_valid_MPORT_5_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_5_addr] <= mem_tin_vu_valid_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_6_en & mem_tin_vu_valid_MPORT_6_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_6_addr] <= mem_tin_vu_valid_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_7_en & mem_tin_vu_valid_MPORT_7_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_7_addr] <= mem_tin_vu_valid_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_8_en & mem_tin_vu_valid_MPORT_8_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_8_addr] <= mem_tin_vu_valid_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_9_en & mem_tin_vu_valid_MPORT_9_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_9_addr] <= mem_tin_vu_valid_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_10_en & mem_tin_vu_valid_MPORT_10_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_10_addr] <= mem_tin_vu_valid_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_11_en & mem_tin_vu_valid_MPORT_11_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_11_addr] <= mem_tin_vu_valid_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_12_en & mem_tin_vu_valid_MPORT_12_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_12_addr] <= mem_tin_vu_valid_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_13_en & mem_tin_vu_valid_MPORT_13_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_13_addr] <= mem_tin_vu_valid_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_14_en & mem_tin_vu_valid_MPORT_14_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_14_addr] <= mem_tin_vu_valid_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_15_en & mem_tin_vu_valid_MPORT_15_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_15_addr] <= mem_tin_vu_valid_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_16_en & mem_tin_vu_valid_MPORT_16_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_16_addr] <= mem_tin_vu_valid_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_17_en & mem_tin_vu_valid_MPORT_17_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_17_addr] <= mem_tin_vu_valid_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_18_en & mem_tin_vu_valid_MPORT_18_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_18_addr] <= mem_tin_vu_valid_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_19_en & mem_tin_vu_valid_MPORT_19_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_19_addr] <= mem_tin_vu_valid_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_20_en & mem_tin_vu_valid_MPORT_20_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_20_addr] <= mem_tin_vu_valid_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_21_en & mem_tin_vu_valid_MPORT_21_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_21_addr] <= mem_tin_vu_valid_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_22_en & mem_tin_vu_valid_MPORT_22_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_22_addr] <= mem_tin_vu_valid_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_23_en & mem_tin_vu_valid_MPORT_23_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_23_addr] <= mem_tin_vu_valid_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_24_en & mem_tin_vu_valid_MPORT_24_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_24_addr] <= mem_tin_vu_valid_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_25_en & mem_tin_vu_valid_MPORT_25_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_25_addr] <= mem_tin_vu_valid_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_26_en & mem_tin_vu_valid_MPORT_26_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_26_addr] <= mem_tin_vu_valid_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_27_en & mem_tin_vu_valid_MPORT_27_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_27_addr] <= mem_tin_vu_valid_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_28_en & mem_tin_vu_valid_MPORT_28_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_28_addr] <= mem_tin_vu_valid_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_29_en & mem_tin_vu_valid_MPORT_29_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_29_addr] <= mem_tin_vu_valid_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_30_en & mem_tin_vu_valid_MPORT_30_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_30_addr] <= mem_tin_vu_valid_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_valid_MPORT_31_en & mem_tin_vu_valid_MPORT_31_mask) begin
- mem_tin_vu_valid[mem_tin_vu_valid_MPORT_31_addr] <= mem_tin_vu_valid_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_en & mem_tin_vu_addr_MPORT_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_addr] <= mem_tin_vu_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_1_en & mem_tin_vu_addr_MPORT_1_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_1_addr] <= mem_tin_vu_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_2_en & mem_tin_vu_addr_MPORT_2_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_2_addr] <= mem_tin_vu_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_3_en & mem_tin_vu_addr_MPORT_3_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_3_addr] <= mem_tin_vu_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_4_en & mem_tin_vu_addr_MPORT_4_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_4_addr] <= mem_tin_vu_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_5_en & mem_tin_vu_addr_MPORT_5_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_5_addr] <= mem_tin_vu_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_6_en & mem_tin_vu_addr_MPORT_6_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_6_addr] <= mem_tin_vu_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_7_en & mem_tin_vu_addr_MPORT_7_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_7_addr] <= mem_tin_vu_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_8_en & mem_tin_vu_addr_MPORT_8_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_8_addr] <= mem_tin_vu_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_9_en & mem_tin_vu_addr_MPORT_9_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_9_addr] <= mem_tin_vu_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_10_en & mem_tin_vu_addr_MPORT_10_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_10_addr] <= mem_tin_vu_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_11_en & mem_tin_vu_addr_MPORT_11_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_11_addr] <= mem_tin_vu_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_12_en & mem_tin_vu_addr_MPORT_12_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_12_addr] <= mem_tin_vu_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_13_en & mem_tin_vu_addr_MPORT_13_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_13_addr] <= mem_tin_vu_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_14_en & mem_tin_vu_addr_MPORT_14_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_14_addr] <= mem_tin_vu_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_15_en & mem_tin_vu_addr_MPORT_15_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_15_addr] <= mem_tin_vu_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_16_en & mem_tin_vu_addr_MPORT_16_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_16_addr] <= mem_tin_vu_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_17_en & mem_tin_vu_addr_MPORT_17_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_17_addr] <= mem_tin_vu_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_18_en & mem_tin_vu_addr_MPORT_18_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_18_addr] <= mem_tin_vu_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_19_en & mem_tin_vu_addr_MPORT_19_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_19_addr] <= mem_tin_vu_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_20_en & mem_tin_vu_addr_MPORT_20_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_20_addr] <= mem_tin_vu_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_21_en & mem_tin_vu_addr_MPORT_21_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_21_addr] <= mem_tin_vu_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_22_en & mem_tin_vu_addr_MPORT_22_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_22_addr] <= mem_tin_vu_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_23_en & mem_tin_vu_addr_MPORT_23_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_23_addr] <= mem_tin_vu_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_24_en & mem_tin_vu_addr_MPORT_24_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_24_addr] <= mem_tin_vu_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_25_en & mem_tin_vu_addr_MPORT_25_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_25_addr] <= mem_tin_vu_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_26_en & mem_tin_vu_addr_MPORT_26_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_26_addr] <= mem_tin_vu_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_27_en & mem_tin_vu_addr_MPORT_27_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_27_addr] <= mem_tin_vu_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_28_en & mem_tin_vu_addr_MPORT_28_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_28_addr] <= mem_tin_vu_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_29_en & mem_tin_vu_addr_MPORT_29_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_29_addr] <= mem_tin_vu_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_30_en & mem_tin_vu_addr_MPORT_30_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_30_addr] <= mem_tin_vu_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_addr_MPORT_31_en & mem_tin_vu_addr_MPORT_31_mask) begin
- mem_tin_vu_addr[mem_tin_vu_addr_MPORT_31_addr] <= mem_tin_vu_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_en & mem_tin_vu_tag_MPORT_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_addr] <= mem_tin_vu_tag_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_1_en & mem_tin_vu_tag_MPORT_1_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_1_addr] <= mem_tin_vu_tag_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_2_en & mem_tin_vu_tag_MPORT_2_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_2_addr] <= mem_tin_vu_tag_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_3_en & mem_tin_vu_tag_MPORT_3_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_3_addr] <= mem_tin_vu_tag_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_4_en & mem_tin_vu_tag_MPORT_4_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_4_addr] <= mem_tin_vu_tag_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_5_en & mem_tin_vu_tag_MPORT_5_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_5_addr] <= mem_tin_vu_tag_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_6_en & mem_tin_vu_tag_MPORT_6_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_6_addr] <= mem_tin_vu_tag_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_7_en & mem_tin_vu_tag_MPORT_7_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_7_addr] <= mem_tin_vu_tag_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_8_en & mem_tin_vu_tag_MPORT_8_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_8_addr] <= mem_tin_vu_tag_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_9_en & mem_tin_vu_tag_MPORT_9_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_9_addr] <= mem_tin_vu_tag_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_10_en & mem_tin_vu_tag_MPORT_10_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_10_addr] <= mem_tin_vu_tag_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_11_en & mem_tin_vu_tag_MPORT_11_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_11_addr] <= mem_tin_vu_tag_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_12_en & mem_tin_vu_tag_MPORT_12_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_12_addr] <= mem_tin_vu_tag_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_13_en & mem_tin_vu_tag_MPORT_13_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_13_addr] <= mem_tin_vu_tag_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_14_en & mem_tin_vu_tag_MPORT_14_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_14_addr] <= mem_tin_vu_tag_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_15_en & mem_tin_vu_tag_MPORT_15_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_15_addr] <= mem_tin_vu_tag_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_16_en & mem_tin_vu_tag_MPORT_16_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_16_addr] <= mem_tin_vu_tag_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_17_en & mem_tin_vu_tag_MPORT_17_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_17_addr] <= mem_tin_vu_tag_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_18_en & mem_tin_vu_tag_MPORT_18_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_18_addr] <= mem_tin_vu_tag_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_19_en & mem_tin_vu_tag_MPORT_19_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_19_addr] <= mem_tin_vu_tag_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_20_en & mem_tin_vu_tag_MPORT_20_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_20_addr] <= mem_tin_vu_tag_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_21_en & mem_tin_vu_tag_MPORT_21_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_21_addr] <= mem_tin_vu_tag_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_22_en & mem_tin_vu_tag_MPORT_22_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_22_addr] <= mem_tin_vu_tag_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_23_en & mem_tin_vu_tag_MPORT_23_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_23_addr] <= mem_tin_vu_tag_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_24_en & mem_tin_vu_tag_MPORT_24_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_24_addr] <= mem_tin_vu_tag_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_25_en & mem_tin_vu_tag_MPORT_25_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_25_addr] <= mem_tin_vu_tag_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_26_en & mem_tin_vu_tag_MPORT_26_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_26_addr] <= mem_tin_vu_tag_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_27_en & mem_tin_vu_tag_MPORT_27_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_27_addr] <= mem_tin_vu_tag_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_28_en & mem_tin_vu_tag_MPORT_28_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_28_addr] <= mem_tin_vu_tag_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_29_en & mem_tin_vu_tag_MPORT_29_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_29_addr] <= mem_tin_vu_tag_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_30_en & mem_tin_vu_tag_MPORT_30_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_30_addr] <= mem_tin_vu_tag_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vu_tag_MPORT_31_en & mem_tin_vu_tag_MPORT_31_mask) begin
- mem_tin_vu_tag[mem_tin_vu_tag_MPORT_31_addr] <= mem_tin_vu_tag_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_en & mem_tin_sv_valid_MPORT_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_addr] <= mem_tin_sv_valid_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_1_en & mem_tin_sv_valid_MPORT_1_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_1_addr] <= mem_tin_sv_valid_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_2_en & mem_tin_sv_valid_MPORT_2_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_2_addr] <= mem_tin_sv_valid_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_3_en & mem_tin_sv_valid_MPORT_3_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_3_addr] <= mem_tin_sv_valid_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_4_en & mem_tin_sv_valid_MPORT_4_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_4_addr] <= mem_tin_sv_valid_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_5_en & mem_tin_sv_valid_MPORT_5_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_5_addr] <= mem_tin_sv_valid_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_6_en & mem_tin_sv_valid_MPORT_6_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_6_addr] <= mem_tin_sv_valid_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_7_en & mem_tin_sv_valid_MPORT_7_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_7_addr] <= mem_tin_sv_valid_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_8_en & mem_tin_sv_valid_MPORT_8_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_8_addr] <= mem_tin_sv_valid_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_9_en & mem_tin_sv_valid_MPORT_9_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_9_addr] <= mem_tin_sv_valid_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_10_en & mem_tin_sv_valid_MPORT_10_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_10_addr] <= mem_tin_sv_valid_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_11_en & mem_tin_sv_valid_MPORT_11_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_11_addr] <= mem_tin_sv_valid_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_12_en & mem_tin_sv_valid_MPORT_12_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_12_addr] <= mem_tin_sv_valid_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_13_en & mem_tin_sv_valid_MPORT_13_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_13_addr] <= mem_tin_sv_valid_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_14_en & mem_tin_sv_valid_MPORT_14_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_14_addr] <= mem_tin_sv_valid_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_15_en & mem_tin_sv_valid_MPORT_15_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_15_addr] <= mem_tin_sv_valid_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_16_en & mem_tin_sv_valid_MPORT_16_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_16_addr] <= mem_tin_sv_valid_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_17_en & mem_tin_sv_valid_MPORT_17_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_17_addr] <= mem_tin_sv_valid_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_18_en & mem_tin_sv_valid_MPORT_18_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_18_addr] <= mem_tin_sv_valid_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_19_en & mem_tin_sv_valid_MPORT_19_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_19_addr] <= mem_tin_sv_valid_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_20_en & mem_tin_sv_valid_MPORT_20_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_20_addr] <= mem_tin_sv_valid_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_21_en & mem_tin_sv_valid_MPORT_21_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_21_addr] <= mem_tin_sv_valid_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_22_en & mem_tin_sv_valid_MPORT_22_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_22_addr] <= mem_tin_sv_valid_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_23_en & mem_tin_sv_valid_MPORT_23_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_23_addr] <= mem_tin_sv_valid_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_24_en & mem_tin_sv_valid_MPORT_24_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_24_addr] <= mem_tin_sv_valid_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_25_en & mem_tin_sv_valid_MPORT_25_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_25_addr] <= mem_tin_sv_valid_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_26_en & mem_tin_sv_valid_MPORT_26_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_26_addr] <= mem_tin_sv_valid_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_27_en & mem_tin_sv_valid_MPORT_27_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_27_addr] <= mem_tin_sv_valid_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_28_en & mem_tin_sv_valid_MPORT_28_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_28_addr] <= mem_tin_sv_valid_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_29_en & mem_tin_sv_valid_MPORT_29_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_29_addr] <= mem_tin_sv_valid_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_30_en & mem_tin_sv_valid_MPORT_30_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_30_addr] <= mem_tin_sv_valid_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_valid_MPORT_31_en & mem_tin_sv_valid_MPORT_31_mask) begin
- mem_tin_sv_valid[mem_tin_sv_valid_MPORT_31_addr] <= mem_tin_sv_valid_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_en & mem_tin_sv_data_MPORT_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_addr] <= mem_tin_sv_data_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_1_en & mem_tin_sv_data_MPORT_1_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_1_addr] <= mem_tin_sv_data_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_2_en & mem_tin_sv_data_MPORT_2_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_2_addr] <= mem_tin_sv_data_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_3_en & mem_tin_sv_data_MPORT_3_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_3_addr] <= mem_tin_sv_data_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_4_en & mem_tin_sv_data_MPORT_4_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_4_addr] <= mem_tin_sv_data_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_5_en & mem_tin_sv_data_MPORT_5_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_5_addr] <= mem_tin_sv_data_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_6_en & mem_tin_sv_data_MPORT_6_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_6_addr] <= mem_tin_sv_data_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_7_en & mem_tin_sv_data_MPORT_7_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_7_addr] <= mem_tin_sv_data_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_8_en & mem_tin_sv_data_MPORT_8_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_8_addr] <= mem_tin_sv_data_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_9_en & mem_tin_sv_data_MPORT_9_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_9_addr] <= mem_tin_sv_data_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_10_en & mem_tin_sv_data_MPORT_10_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_10_addr] <= mem_tin_sv_data_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_11_en & mem_tin_sv_data_MPORT_11_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_11_addr] <= mem_tin_sv_data_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_12_en & mem_tin_sv_data_MPORT_12_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_12_addr] <= mem_tin_sv_data_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_13_en & mem_tin_sv_data_MPORT_13_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_13_addr] <= mem_tin_sv_data_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_14_en & mem_tin_sv_data_MPORT_14_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_14_addr] <= mem_tin_sv_data_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_15_en & mem_tin_sv_data_MPORT_15_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_15_addr] <= mem_tin_sv_data_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_16_en & mem_tin_sv_data_MPORT_16_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_16_addr] <= mem_tin_sv_data_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_17_en & mem_tin_sv_data_MPORT_17_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_17_addr] <= mem_tin_sv_data_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_18_en & mem_tin_sv_data_MPORT_18_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_18_addr] <= mem_tin_sv_data_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_19_en & mem_tin_sv_data_MPORT_19_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_19_addr] <= mem_tin_sv_data_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_20_en & mem_tin_sv_data_MPORT_20_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_20_addr] <= mem_tin_sv_data_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_21_en & mem_tin_sv_data_MPORT_21_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_21_addr] <= mem_tin_sv_data_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_22_en & mem_tin_sv_data_MPORT_22_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_22_addr] <= mem_tin_sv_data_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_23_en & mem_tin_sv_data_MPORT_23_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_23_addr] <= mem_tin_sv_data_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_24_en & mem_tin_sv_data_MPORT_24_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_24_addr] <= mem_tin_sv_data_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_25_en & mem_tin_sv_data_MPORT_25_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_25_addr] <= mem_tin_sv_data_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_26_en & mem_tin_sv_data_MPORT_26_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_26_addr] <= mem_tin_sv_data_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_27_en & mem_tin_sv_data_MPORT_27_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_27_addr] <= mem_tin_sv_data_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_28_en & mem_tin_sv_data_MPORT_28_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_28_addr] <= mem_tin_sv_data_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_29_en & mem_tin_sv_data_MPORT_29_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_29_addr] <= mem_tin_sv_data_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_30_en & mem_tin_sv_data_MPORT_30_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_30_addr] <= mem_tin_sv_data_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_sv_data_MPORT_31_en & mem_tin_sv_data_MPORT_31_mask) begin
- mem_tin_sv_data[mem_tin_sv_data_MPORT_31_addr] <= mem_tin_sv_data_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_en & mem_tin_cmdsync_MPORT_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_addr] <= mem_tin_cmdsync_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_1_en & mem_tin_cmdsync_MPORT_1_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_1_addr] <= mem_tin_cmdsync_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_2_en & mem_tin_cmdsync_MPORT_2_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_2_addr] <= mem_tin_cmdsync_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_3_en & mem_tin_cmdsync_MPORT_3_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_3_addr] <= mem_tin_cmdsync_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_4_en & mem_tin_cmdsync_MPORT_4_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_4_addr] <= mem_tin_cmdsync_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_5_en & mem_tin_cmdsync_MPORT_5_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_5_addr] <= mem_tin_cmdsync_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_6_en & mem_tin_cmdsync_MPORT_6_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_6_addr] <= mem_tin_cmdsync_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_7_en & mem_tin_cmdsync_MPORT_7_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_7_addr] <= mem_tin_cmdsync_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_8_en & mem_tin_cmdsync_MPORT_8_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_8_addr] <= mem_tin_cmdsync_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_9_en & mem_tin_cmdsync_MPORT_9_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_9_addr] <= mem_tin_cmdsync_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_10_en & mem_tin_cmdsync_MPORT_10_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_10_addr] <= mem_tin_cmdsync_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_11_en & mem_tin_cmdsync_MPORT_11_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_11_addr] <= mem_tin_cmdsync_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_12_en & mem_tin_cmdsync_MPORT_12_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_12_addr] <= mem_tin_cmdsync_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_13_en & mem_tin_cmdsync_MPORT_13_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_13_addr] <= mem_tin_cmdsync_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_14_en & mem_tin_cmdsync_MPORT_14_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_14_addr] <= mem_tin_cmdsync_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_15_en & mem_tin_cmdsync_MPORT_15_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_15_addr] <= mem_tin_cmdsync_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_16_en & mem_tin_cmdsync_MPORT_16_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_16_addr] <= mem_tin_cmdsync_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_17_en & mem_tin_cmdsync_MPORT_17_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_17_addr] <= mem_tin_cmdsync_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_18_en & mem_tin_cmdsync_MPORT_18_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_18_addr] <= mem_tin_cmdsync_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_19_en & mem_tin_cmdsync_MPORT_19_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_19_addr] <= mem_tin_cmdsync_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_20_en & mem_tin_cmdsync_MPORT_20_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_20_addr] <= mem_tin_cmdsync_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_21_en & mem_tin_cmdsync_MPORT_21_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_21_addr] <= mem_tin_cmdsync_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_22_en & mem_tin_cmdsync_MPORT_22_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_22_addr] <= mem_tin_cmdsync_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_23_en & mem_tin_cmdsync_MPORT_23_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_23_addr] <= mem_tin_cmdsync_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_24_en & mem_tin_cmdsync_MPORT_24_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_24_addr] <= mem_tin_cmdsync_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_25_en & mem_tin_cmdsync_MPORT_25_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_25_addr] <= mem_tin_cmdsync_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_26_en & mem_tin_cmdsync_MPORT_26_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_26_addr] <= mem_tin_cmdsync_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_27_en & mem_tin_cmdsync_MPORT_27_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_27_addr] <= mem_tin_cmdsync_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_28_en & mem_tin_cmdsync_MPORT_28_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_28_addr] <= mem_tin_cmdsync_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_29_en & mem_tin_cmdsync_MPORT_29_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_29_addr] <= mem_tin_cmdsync_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_30_en & mem_tin_cmdsync_MPORT_30_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_30_addr] <= mem_tin_cmdsync_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_cmdsync_MPORT_31_en & mem_tin_cmdsync_MPORT_31_mask) begin
- mem_tin_cmdsync[mem_tin_cmdsync_MPORT_31_addr] <= mem_tin_cmdsync_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_en & mem_m_MPORT_mask) begin
- mem_m[mem_m_MPORT_addr] <= mem_m_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_1_en & mem_m_MPORT_1_mask) begin
- mem_m[mem_m_MPORT_1_addr] <= mem_m_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_2_en & mem_m_MPORT_2_mask) begin
- mem_m[mem_m_MPORT_2_addr] <= mem_m_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_3_en & mem_m_MPORT_3_mask) begin
- mem_m[mem_m_MPORT_3_addr] <= mem_m_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_4_en & mem_m_MPORT_4_mask) begin
- mem_m[mem_m_MPORT_4_addr] <= mem_m_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_5_en & mem_m_MPORT_5_mask) begin
- mem_m[mem_m_MPORT_5_addr] <= mem_m_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_6_en & mem_m_MPORT_6_mask) begin
- mem_m[mem_m_MPORT_6_addr] <= mem_m_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_7_en & mem_m_MPORT_7_mask) begin
- mem_m[mem_m_MPORT_7_addr] <= mem_m_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_8_en & mem_m_MPORT_8_mask) begin
- mem_m[mem_m_MPORT_8_addr] <= mem_m_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_9_en & mem_m_MPORT_9_mask) begin
- mem_m[mem_m_MPORT_9_addr] <= mem_m_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_10_en & mem_m_MPORT_10_mask) begin
- mem_m[mem_m_MPORT_10_addr] <= mem_m_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_11_en & mem_m_MPORT_11_mask) begin
- mem_m[mem_m_MPORT_11_addr] <= mem_m_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_12_en & mem_m_MPORT_12_mask) begin
- mem_m[mem_m_MPORT_12_addr] <= mem_m_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_13_en & mem_m_MPORT_13_mask) begin
- mem_m[mem_m_MPORT_13_addr] <= mem_m_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_14_en & mem_m_MPORT_14_mask) begin
- mem_m[mem_m_MPORT_14_addr] <= mem_m_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_15_en & mem_m_MPORT_15_mask) begin
- mem_m[mem_m_MPORT_15_addr] <= mem_m_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_16_en & mem_m_MPORT_16_mask) begin
- mem_m[mem_m_MPORT_16_addr] <= mem_m_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_17_en & mem_m_MPORT_17_mask) begin
- mem_m[mem_m_MPORT_17_addr] <= mem_m_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_18_en & mem_m_MPORT_18_mask) begin
- mem_m[mem_m_MPORT_18_addr] <= mem_m_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_19_en & mem_m_MPORT_19_mask) begin
- mem_m[mem_m_MPORT_19_addr] <= mem_m_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_20_en & mem_m_MPORT_20_mask) begin
- mem_m[mem_m_MPORT_20_addr] <= mem_m_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_21_en & mem_m_MPORT_21_mask) begin
- mem_m[mem_m_MPORT_21_addr] <= mem_m_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_22_en & mem_m_MPORT_22_mask) begin
- mem_m[mem_m_MPORT_22_addr] <= mem_m_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_23_en & mem_m_MPORT_23_mask) begin
- mem_m[mem_m_MPORT_23_addr] <= mem_m_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_24_en & mem_m_MPORT_24_mask) begin
- mem_m[mem_m_MPORT_24_addr] <= mem_m_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_25_en & mem_m_MPORT_25_mask) begin
- mem_m[mem_m_MPORT_25_addr] <= mem_m_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_26_en & mem_m_MPORT_26_mask) begin
- mem_m[mem_m_MPORT_26_addr] <= mem_m_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_27_en & mem_m_MPORT_27_mask) begin
- mem_m[mem_m_MPORT_27_addr] <= mem_m_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_28_en & mem_m_MPORT_28_mask) begin
- mem_m[mem_m_MPORT_28_addr] <= mem_m_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_29_en & mem_m_MPORT_29_mask) begin
- mem_m[mem_m_MPORT_29_addr] <= mem_m_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_30_en & mem_m_MPORT_30_mask) begin
- mem_m[mem_m_MPORT_30_addr] <= mem_m_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_31_en & mem_m_MPORT_31_mask) begin
- mem_m[mem_m_MPORT_31_addr] <= mem_m_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(mcount <= 4'h8)) begin
- $fatal; // @[Fifo4e.scala 137:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(mcount <= 4'h8)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Fifo4e.scala:137 assert(mcount <= n.U)\n"); // @[Fifo4e.scala 137:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in0pos <= 3'h0; // @[Fifo4e.scala 68:12]
- end else if (ivalid) begin // @[Fifo4e.scala 45:23]
- in0pos <= in0pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in1pos <= 3'h1; // @[Fifo4e.scala 69:12]
- end else if (ivalid) begin // @[Fifo4e.scala 46:23]
- in1pos <= in1pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in2pos <= 3'h2; // @[Fifo4e.scala 70:12]
- end else if (ivalid) begin // @[Fifo4e.scala 47:23]
- in2pos <= in2pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in3pos <= 3'h3; // @[Fifo4e.scala 71:12]
- end else if (ivalid) begin // @[Fifo4e.scala 48:23]
- in3pos <= in3pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 74:17]
- outpos <= 3'h0; // @[Fifo4e.scala 75:12]
- end else if (dec) begin // @[Fifo4e.scala 49:23]
- outpos <= outpos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 81:27]
- mcount <= 4'h0; // @[Fifo4e.scala 83:12]
- end else if (ivalid | dec) begin // @[Fifo4e.scala 50:23]
- mcount <= nxtcount;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 126:69]
- active <= 8'h0; // @[Fifo4e.scala 127:12]
- end else if (_T) begin // @[Fifo4e.scala 118:23]
- active <= _active_T_2;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_MEM_INIT
- _RAND_0 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_op[initvar] = _RAND_0[6:0];
- _RAND_1 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_f2[initvar] = _RAND_1[2:0];
- _RAND_2 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_sz[initvar] = _RAND_2[2:0];
- _RAND_3 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vd_addr[initvar] = _RAND_3[5:0];
- _RAND_4 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_ve_addr[initvar] = _RAND_4[5:0];
- _RAND_5 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vs_valid[initvar] = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vs_addr[initvar] = _RAND_6[5:0];
- _RAND_7 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vs_tag[initvar] = _RAND_7[3:0];
- _RAND_8 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vt_valid[initvar] = _RAND_8[0:0];
- _RAND_9 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vt_addr[initvar] = _RAND_9[5:0];
- _RAND_10 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vt_tag[initvar] = _RAND_10[3:0];
- _RAND_11 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vu_valid[initvar] = _RAND_11[0:0];
- _RAND_12 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vu_addr[initvar] = _RAND_12[5:0];
- _RAND_13 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vu_tag[initvar] = _RAND_13[3:0];
- _RAND_14 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_sv_valid[initvar] = _RAND_14[0:0];
- _RAND_15 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_sv_data[initvar] = _RAND_15[31:0];
- _RAND_16 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_cmdsync[initvar] = _RAND_16[0:0];
- _RAND_17 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_m[initvar] = _RAND_17[0:0];
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- _RAND_18 = {1{`RANDOM}};
- in0pos = _RAND_18[2:0];
- _RAND_19 = {1{`RANDOM}};
- in1pos = _RAND_19[2:0];
- _RAND_20 = {1{`RANDOM}};
- in2pos = _RAND_20[2:0];
- _RAND_21 = {1{`RANDOM}};
- in3pos = _RAND_21[2:0];
- _RAND_22 = {1{`RANDOM}};
- outpos = _RAND_22[2:0];
- _RAND_23 = {1{`RANDOM}};
- mcount = _RAND_23[3:0];
- _RAND_24 = {1{`RANDOM}};
- active = _RAND_24[7:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- in0pos = 3'h0;
- end
- if (reset) begin
- in1pos = 3'h1;
- end
- if (reset) begin
- in2pos = 3'h2;
- end
- if (reset) begin
- in3pos = 3'h3;
- end
- if (reset) begin
- outpos = 3'h0;
- end
- if (reset) begin
- mcount = 4'h0;
- end
- if (reset) begin
- active = 8'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VCmdq(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_op,
- input [2:0] io_in_bits_0_bits_f2,
- input [2:0] io_in_bits_0_bits_sz,
- input io_in_bits_0_bits_m,
- input [5:0] io_in_bits_0_bits_vd_addr,
- input [5:0] io_in_bits_0_bits_ve_addr,
- input io_in_bits_0_bits_vs_valid,
- input [5:0] io_in_bits_0_bits_vs_addr,
- input [3:0] io_in_bits_0_bits_vs_tag,
- input io_in_bits_0_bits_vt_valid,
- input [5:0] io_in_bits_0_bits_vt_addr,
- input [3:0] io_in_bits_0_bits_vt_tag,
- input io_in_bits_0_bits_vu_valid,
- input [5:0] io_in_bits_0_bits_vu_addr,
- input [3:0] io_in_bits_0_bits_vu_tag,
- input io_in_bits_0_bits_sv_valid,
- input [31:0] io_in_bits_0_bits_sv_data,
- input io_in_bits_0_bits_cmdsync,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_op,
- input [2:0] io_in_bits_1_bits_f2,
- input [2:0] io_in_bits_1_bits_sz,
- input io_in_bits_1_bits_m,
- input [5:0] io_in_bits_1_bits_vd_addr,
- input [5:0] io_in_bits_1_bits_ve_addr,
- input io_in_bits_1_bits_vs_valid,
- input [5:0] io_in_bits_1_bits_vs_addr,
- input [3:0] io_in_bits_1_bits_vs_tag,
- input io_in_bits_1_bits_vt_valid,
- input [5:0] io_in_bits_1_bits_vt_addr,
- input [3:0] io_in_bits_1_bits_vt_tag,
- input io_in_bits_1_bits_vu_valid,
- input [5:0] io_in_bits_1_bits_vu_addr,
- input [3:0] io_in_bits_1_bits_vu_tag,
- input io_in_bits_1_bits_sv_valid,
- input [31:0] io_in_bits_1_bits_sv_data,
- input io_in_bits_1_bits_cmdsync,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_op,
- input [2:0] io_in_bits_2_bits_f2,
- input [2:0] io_in_bits_2_bits_sz,
- input io_in_bits_2_bits_m,
- input [5:0] io_in_bits_2_bits_vd_addr,
- input [5:0] io_in_bits_2_bits_ve_addr,
- input io_in_bits_2_bits_vs_valid,
- input [5:0] io_in_bits_2_bits_vs_addr,
- input [3:0] io_in_bits_2_bits_vs_tag,
- input io_in_bits_2_bits_vt_valid,
- input [5:0] io_in_bits_2_bits_vt_addr,
- input [3:0] io_in_bits_2_bits_vt_tag,
- input io_in_bits_2_bits_vu_valid,
- input [5:0] io_in_bits_2_bits_vu_addr,
- input [3:0] io_in_bits_2_bits_vu_tag,
- input io_in_bits_2_bits_sv_valid,
- input [31:0] io_in_bits_2_bits_sv_data,
- input io_in_bits_2_bits_cmdsync,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_op,
- input [2:0] io_in_bits_3_bits_f2,
- input [2:0] io_in_bits_3_bits_sz,
- input io_in_bits_3_bits_m,
- input [5:0] io_in_bits_3_bits_vd_addr,
- input [5:0] io_in_bits_3_bits_ve_addr,
- input io_in_bits_3_bits_vs_valid,
- input [5:0] io_in_bits_3_bits_vs_addr,
- input [3:0] io_in_bits_3_bits_vs_tag,
- input io_in_bits_3_bits_vt_valid,
- input [5:0] io_in_bits_3_bits_vt_addr,
- input [3:0] io_in_bits_3_bits_vt_tag,
- input io_in_bits_3_bits_vu_valid,
- input [5:0] io_in_bits_3_bits_vu_addr,
- input [3:0] io_in_bits_3_bits_vu_tag,
- input io_in_bits_3_bits_sv_valid,
- input [31:0] io_in_bits_3_bits_sv_data,
- input io_in_bits_3_bits_cmdsync,
- input io_out_ready,
- output io_out_valid,
- output [6:0] io_out_bits_op,
- output [2:0] io_out_bits_f2,
- output [2:0] io_out_bits_sz,
- output [5:0] io_out_bits_vd_addr,
- output [5:0] io_out_bits_ve_addr,
- output io_out_bits_vs_valid,
- output [5:0] io_out_bits_vs_addr,
- output [3:0] io_out_bits_vs_tag,
- output io_out_bits_vt_valid,
- output [5:0] io_out_bits_vt_addr,
- output [3:0] io_out_bits_vt_tag,
- output io_out_bits_vu_valid,
- output [5:0] io_out_bits_vu_addr,
- output [3:0] io_out_bits_vu_tag,
- output io_out_bits_sv_valid,
- output [31:0] io_out_bits_sv_data,
- output io_out_bits_cmdsync,
- output [63:0] io_active
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [63:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
-`endif // RANDOMIZE_REG_INIT
- wire f_clock; // @[Fifo4e.scala 24:11]
- wire f_reset; // @[Fifo4e.scala 24:11]
- wire f_io_in_ready; // @[Fifo4e.scala 24:11]
- wire f_io_in_valid; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_0_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_0_bits_tin_f2; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_0_bits_tin_sz; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_ve_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_0_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_0_bits_tin_vt_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_0_bits_tin_vu_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_tin_sv_valid; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_0_bits_tin_sv_data; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_tin_cmdsync; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_1_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_1_bits_tin_f2; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_1_bits_tin_sz; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_ve_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_1_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_1_bits_tin_vt_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_1_bits_tin_vu_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_tin_sv_valid; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_1_bits_tin_sv_data; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_tin_cmdsync; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_2_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_2_bits_tin_f2; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_2_bits_tin_sz; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_ve_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_2_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_2_bits_tin_vt_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_2_bits_tin_vu_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_tin_sv_valid; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_2_bits_tin_sv_data; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_tin_cmdsync; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_3_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_3_bits_tin_f2; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_3_bits_tin_sz; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_ve_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_3_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_3_bits_tin_vt_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_3_bits_tin_vu_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_tin_sv_valid; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_3_bits_tin_sv_data; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_tin_cmdsync; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_out_ready; // @[Fifo4e.scala 24:11]
- wire f_io_out_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_out_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_out_bits_tin_f2; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_out_bits_tin_sz; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_ve_addr; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_out_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_out_bits_tin_vt_tag; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_out_bits_tin_vu_tag; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_tin_sv_valid; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_out_bits_tin_sv_data; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_tin_cmdsync; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_0_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_0_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_0_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_1_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_1_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_1_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_2_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_2_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_2_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_3_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_3_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_3_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_4_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_4_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_4_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_5_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_5_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_5_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_6_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_6_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_6_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_7_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_7_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_7_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_bits_m; // @[Fifo4e.scala 24:11]
- reg [63:0] active; // @[VCmdq.scala 49:23]
- reg valid; // @[VCmdq.scala 51:22]
- reg [6:0] value_tin_op; // @[VCmdq.scala 53:18]
- reg [2:0] value_tin_f2; // @[VCmdq.scala 53:18]
- reg [2:0] value_tin_sz; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_vd_addr; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_ve_addr; // @[VCmdq.scala 53:18]
- reg value_tin_vs_valid; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_vs_addr; // @[VCmdq.scala 53:18]
- reg [3:0] value_tin_vs_tag; // @[VCmdq.scala 53:18]
- reg value_tin_vt_valid; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_vt_addr; // @[VCmdq.scala 53:18]
- reg [3:0] value_tin_vt_tag; // @[VCmdq.scala 53:18]
- reg value_tin_vu_valid; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_vu_addr; // @[VCmdq.scala 53:18]
- reg [3:0] value_tin_vu_tag; // @[VCmdq.scala 53:18]
- reg value_tin_sv_valid; // @[VCmdq.scala 53:18]
- reg [31:0] value_tin_sv_data; // @[VCmdq.scala 53:18]
- reg value_tin_cmdsync; // @[VCmdq.scala 53:18]
- reg value_m; // @[VCmdq.scala 53:18]
- reg [4:0] step; // @[VCmdq.scala 58:21]
- wire vevnodd = value_tin_op == 7'h41 | value_tin_op == 7'h42 | value_tin_op == 7'h43; // @[VAlu.scala 217:60]
- wire vzip = value_tin_op == 7'h44; // @[VAlu.scala 218:22]
- wire _last_T = ~value_m; // @[VAlu.scala 220:16]
- wire last = ~value_m | step == 5'h3; // @[VAlu.scala 220:19]
- wire [5:0] _out_vd_addr_T_1 = value_tin_vd_addr + 6'h1; // @[VAlu.scala 222:31]
- wire [5:0] _out_ve_addr_T_1 = value_tin_ve_addr + 6'h1; // @[VAlu.scala 223:31]
- wire [5:0] _out_vs_addr_T_1 = value_tin_vs_addr + 6'h1; // @[VAlu.scala 224:31]
- wire [5:0] _out_vt_addr_T_1 = value_tin_vt_addr + 6'h1; // @[VAlu.scala 225:31]
- wire [5:0] _out_vu_addr_T_1 = value_tin_vu_addr + 6'h1; // @[VAlu.scala 226:31]
- wire [6:0] _out_vs_addr_T_2 = {{1'd0}, value_tin_vu_addr}; // @[VAlu.scala 230:35]
- wire [5:0] _out_vs_addr_T_5 = value_tin_vs_addr + 6'h2; // @[VAlu.scala 233:35]
- wire [5:0] _out_vt_addr_T_5 = value_tin_vt_addr + 6'h2; // @[VAlu.scala 234:35]
- wire [5:0] _GEN_0 = step == 5'h1 ? _out_vs_addr_T_2[5:0] : _out_vs_addr_T_5; // @[VAlu.scala 229:27 230:21 233:21]
- wire [5:0] _GEN_1 = step == 5'h1 ? _out_vu_addr_T_1 : _out_vt_addr_T_5; // @[VAlu.scala 229:27 231:21 234:21]
- wire [5:0] tin_vu_addr = value_m & vevnodd ? value_tin_vu_addr : _out_vu_addr_T_1; // @[VAlu.scala 226:17 227:25 228:19]
- wire [5:0] tin_vs_addr = value_m & vevnodd ? _GEN_0 : _out_vs_addr_T_1; // @[VAlu.scala 224:17 227:25]
- wire [5:0] tin_vt_addr = value_m & vevnodd ? _GEN_1 : _out_vt_addr_T_1; // @[VAlu.scala 225:17 227:25]
- wire _T_6 = ~reset; // @[VAlu.scala 238:13]
- wire [5:0] _out_vd_addr_T_3 = value_tin_vd_addr + 6'h2; // @[VAlu.scala 239:33]
- wire [5:0] _out_ve_addr_T_3 = value_tin_ve_addr + 6'h2; // @[VAlu.scala 240:33]
- wire [5:0] tin_vd_addr = vzip ? _out_vd_addr_T_3 : _out_vd_addr_T_1; // @[VAlu.scala 222:17 237:17 239:19]
- wire [5:0] tin_ve_addr = vzip ? _out_ve_addr_T_3 : _out_ve_addr_T_1; // @[VAlu.scala 223:17 237:17 240:19]
- wire _T_9 = io_out_valid & io_out_ready; // @[VCmdq.scala 81:29]
- wire _T_10 = ~last; // @[VCmdq.scala 82:11]
- wire [4:0] _step_T_1 = step + 5'h1; // @[VCmdq.scala 86:20]
- wire _GEN_60 = ~last & value_tin_cmdsync; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_62 = ~last & value_tin_sv_valid; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_65 = ~last & value_tin_vu_valid; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_68 = ~last & value_tin_vt_valid; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_71 = ~last & value_tin_vs_valid; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_79 = ~last & value_m; // @[VCmdq.scala 82:18 85:15 91:15]
- wire _GEN_81 = io_out_valid & io_out_ready ? _T_10 : valid; // @[VCmdq.scala 51:22 81:46]
- wire _T_14 = io_in_valid & io_in_ready | _T_9; // @[VCmdq.scala 118:36]
- wire _fvalid_T = f_io_in_valid & f_io_in_ready; // @[VCmdq.scala 119:38]
- wire [3:0] _fvalid_T_1 = {f_io_in_bits_3_valid,f_io_in_bits_2_valid,f_io_in_bits_1_valid,f_io_in_bits_0_valid}; // @[Cat.scala 31:58]
- wire [3:0] fvalid = _fvalid_T ? _fvalid_T_1 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount = f_io_in_bits_0_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh = 16'h1 << active_active_oh_shiftAmount; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo = {3'h0,active_active_oh[3],3'h0,active_active_oh[2],3'h0,active_active_oh[1],3'h0
- ,active_active_oh[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo = {3'h0,active_active_oh[7],3'h0,active_active_oh[6],3'h0,active_active_oh[5],3'h0,
- active_active_oh[4],active_active_oh0_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo = {3'h0,active_active_oh[11],3'h0,active_active_oh[10],3'h0,active_active_oh[9],3'h0
- ,active_active_oh[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0 = {3'h0,active_active_oh[15],3'h0,active_active_oh[14],3'h0,active_active_oh[13],3'h0,
- active_active_oh[12],active_active_oh0_hi_lo,active_active_oh0_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo = {2'h0,active_active_oh[1],1'h0,2'h0,active_active_oh[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo = {2'h0,active_active_oh[3],1'h0,2'h0,active_active_oh[2],1'h0,
- active_active_oh1_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo = {2'h0,active_active_oh[5],1'h0,2'h0,active_active_oh[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo = {2'h0,active_active_oh[7],1'h0,2'h0,active_active_oh[6],1'h0,
- active_active_oh1_lo_hi_lo,active_active_oh1_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo = {2'h0,active_active_oh[9],1'h0,2'h0,active_active_oh[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo = {2'h0,active_active_oh[11],1'h0,2'h0,active_active_oh[10],1'h0,
- active_active_oh1_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo = {2'h0,active_active_oh[13],1'h0,2'h0,active_active_oh[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1 = {2'h0,active_active_oh[15],1'h0,2'h0,active_active_oh[14],1'h0,
- active_active_oh1_hi_hi_lo,active_active_oh1_hi_lo,active_active_oh1_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo = {1'h0,active_active_oh[1],2'h0,1'h0,active_active_oh[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo = {1'h0,active_active_oh[3],2'h0,1'h0,active_active_oh[2],2'h0,
- active_active_oh2_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo = {1'h0,active_active_oh[5],2'h0,1'h0,active_active_oh[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo = {1'h0,active_active_oh[7],2'h0,1'h0,active_active_oh[6],2'h0,
- active_active_oh2_lo_hi_lo,active_active_oh2_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo = {1'h0,active_active_oh[9],2'h0,1'h0,active_active_oh[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo = {1'h0,active_active_oh[11],2'h0,1'h0,active_active_oh[10],2'h0,
- active_active_oh2_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo = {1'h0,active_active_oh[13],2'h0,1'h0,active_active_oh[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2 = {1'h0,active_active_oh[15],2'h0,1'h0,active_active_oh[14],2'h0,
- active_active_oh2_hi_hi_lo,active_active_oh2_hi_lo,active_active_oh2_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo = {active_active_oh[3],3'h0,active_active_oh[2],3'h0,active_active_oh[1],3'h0,
- active_active_oh[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo = {active_active_oh[7],3'h0,active_active_oh[6],3'h0,active_active_oh[5],3'h0,
- active_active_oh[4],3'h0,active_active_oh3_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo = {active_active_oh[11],3'h0,active_active_oh[10],3'h0,active_active_oh[9],3'h0,
- active_active_oh[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3 = {active_active_oh[15],3'h0,active_active_oh[14],3'h0,active_active_oh[13],3'h0,
- active_active_oh[12],3'h0,active_active_oh3_hi_lo,active_active_oh3_lo}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx = f_io_in_bits_0_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T = ~f_io_in_bits_0_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_4 = f_io_in_bits_0_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_5 = ~f_io_in_bits_0_bits_m & active_active_idx == 2'h0 | f_io_in_bits_0_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_6 = _active_active_active_T_5 ? active_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_12 = _active_active_active_T & active_active_idx == 2'h1 | _active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_13 = _active_active_active_T_12 ? active_active_oh1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_14 = _active_active_active_T_6 | _active_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active_active_T_20 = _active_active_active_T & active_active_idx == 2'h2 | _active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_21 = _active_active_active_T_20 ? active_active_oh2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_22 = _active_active_active_T_14 | _active_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active_active_T_28 = _active_active_active_T & active_active_idx == 2'h3 | _active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_29 = _active_active_active_T_28 ? active_active_oh3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active = _active_active_active_T_22 | _active_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_4 = f_io_in_bits_0_bits_tin_vs_valid ? active_active_active : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount_1 = f_io_in_bits_0_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_1 = 16'h1 << active_active_oh_shiftAmount_1; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_1 = {3'h0,active_active_oh_1[3],3'h0,active_active_oh_1[2],3'h0,active_active_oh_1
- [1],3'h0,active_active_oh_1[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_1 = {3'h0,active_active_oh_1[7],3'h0,active_active_oh_1[6],3'h0,active_active_oh_1[5]
- ,3'h0,active_active_oh_1[4],active_active_oh0_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_1 = {3'h0,active_active_oh_1[11],3'h0,active_active_oh_1[10],3'h0,
- active_active_oh_1[9],3'h0,active_active_oh_1[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_1 = {3'h0,active_active_oh_1[15],3'h0,active_active_oh_1[14],3'h0,active_active_oh_1[13]
- ,3'h0,active_active_oh_1[12],active_active_oh0_hi_lo_1,active_active_oh0_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_1 = {2'h0,active_active_oh_1[1],1'h0,2'h0,active_active_oh_1[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_1 = {2'h0,active_active_oh_1[3],1'h0,2'h0,active_active_oh_1[2],1'h0,
- active_active_oh1_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_1 = {2'h0,active_active_oh_1[5],1'h0,2'h0,active_active_oh_1[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_1 = {2'h0,active_active_oh_1[7],1'h0,2'h0,active_active_oh_1[6],1'h0,
- active_active_oh1_lo_hi_lo_1,active_active_oh1_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_1 = {2'h0,active_active_oh_1[9],1'h0,2'h0,active_active_oh_1[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_1 = {2'h0,active_active_oh_1[11],1'h0,2'h0,active_active_oh_1[10],1'h0,
- active_active_oh1_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_1 = {2'h0,active_active_oh_1[13],1'h0,2'h0,active_active_oh_1[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_1 = {2'h0,active_active_oh_1[15],1'h0,2'h0,active_active_oh_1[14],1'h0,
- active_active_oh1_hi_hi_lo_1,active_active_oh1_hi_lo_1,active_active_oh1_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_1 = {1'h0,active_active_oh_1[1],2'h0,1'h0,active_active_oh_1[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_1 = {1'h0,active_active_oh_1[3],2'h0,1'h0,active_active_oh_1[2],2'h0,
- active_active_oh2_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_1 = {1'h0,active_active_oh_1[5],2'h0,1'h0,active_active_oh_1[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_1 = {1'h0,active_active_oh_1[7],2'h0,1'h0,active_active_oh_1[6],2'h0,
- active_active_oh2_lo_hi_lo_1,active_active_oh2_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_1 = {1'h0,active_active_oh_1[9],2'h0,1'h0,active_active_oh_1[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_1 = {1'h0,active_active_oh_1[11],2'h0,1'h0,active_active_oh_1[10],2'h0,
- active_active_oh2_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_1 = {1'h0,active_active_oh_1[13],2'h0,1'h0,active_active_oh_1[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_1 = {1'h0,active_active_oh_1[15],2'h0,1'h0,active_active_oh_1[14],2'h0,
- active_active_oh2_hi_hi_lo_1,active_active_oh2_hi_lo_1,active_active_oh2_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_1 = {active_active_oh_1[3],3'h0,active_active_oh_1[2],3'h0,active_active_oh_1[1],3'h0
- ,active_active_oh_1[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_1 = {active_active_oh_1[7],3'h0,active_active_oh_1[6],3'h0,active_active_oh_1[5],3'h0
- ,active_active_oh_1[4],3'h0,active_active_oh3_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_1 = {active_active_oh_1[11],3'h0,active_active_oh_1[10],3'h0,active_active_oh_1[9]
- ,3'h0,active_active_oh_1[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_1 = {active_active_oh_1[15],3'h0,active_active_oh_1[14],3'h0,active_active_oh_1[13],3'h0
- ,active_active_oh_1[12],3'h0,active_active_oh3_hi_lo_1,active_active_oh3_lo_1}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_1 = f_io_in_bits_0_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_35 = ~f_io_in_bits_0_bits_m & active_active_idx_1 == 2'h0 | f_io_in_bits_0_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_36 = _active_active_active_T_35 ? active_active_oh0_1 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_42 = _active_active_active_T & active_active_idx_1 == 2'h1 | _active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_43 = _active_active_active_T_42 ? active_active_oh1_1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_44 = _active_active_active_T_36 | _active_active_active_T_43; // @[VCommon.scala 107:68]
- wire _active_active_active_T_50 = _active_active_active_T & active_active_idx_1 == 2'h2 | _active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_51 = _active_active_active_T_50 ? active_active_oh2_1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_52 = _active_active_active_T_44 | _active_active_active_T_51; // @[VCommon.scala 108:68]
- wire _active_active_active_T_58 = _active_active_active_T & active_active_idx_1 == 2'h3 | _active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_59 = _active_active_active_T_58 ? active_active_oh3_1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_1 = _active_active_active_T_52 | _active_active_active_T_59; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_9 = f_io_in_bits_0_bits_tin_vt_valid ? active_active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_T_10 = _active_active_T_4 | _active_active_T_9; // @[VAlu.scala 249:74]
- wire [3:0] active_active_oh_shiftAmount_2 = f_io_in_bits_0_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_2 = 16'h1 << active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_2 = {3'h0,active_active_oh_2[3],3'h0,active_active_oh_2[2],3'h0,active_active_oh_2
- [1],3'h0,active_active_oh_2[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_2 = {3'h0,active_active_oh_2[7],3'h0,active_active_oh_2[6],3'h0,active_active_oh_2[5]
- ,3'h0,active_active_oh_2[4],active_active_oh0_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_2 = {3'h0,active_active_oh_2[11],3'h0,active_active_oh_2[10],3'h0,
- active_active_oh_2[9],3'h0,active_active_oh_2[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_2 = {3'h0,active_active_oh_2[15],3'h0,active_active_oh_2[14],3'h0,active_active_oh_2[13]
- ,3'h0,active_active_oh_2[12],active_active_oh0_hi_lo_2,active_active_oh0_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_2 = {2'h0,active_active_oh_2[1],1'h0,2'h0,active_active_oh_2[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_2 = {2'h0,active_active_oh_2[3],1'h0,2'h0,active_active_oh_2[2],1'h0,
- active_active_oh1_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_2 = {2'h0,active_active_oh_2[5],1'h0,2'h0,active_active_oh_2[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_2 = {2'h0,active_active_oh_2[7],1'h0,2'h0,active_active_oh_2[6],1'h0,
- active_active_oh1_lo_hi_lo_2,active_active_oh1_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_2 = {2'h0,active_active_oh_2[9],1'h0,2'h0,active_active_oh_2[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_2 = {2'h0,active_active_oh_2[11],1'h0,2'h0,active_active_oh_2[10],1'h0,
- active_active_oh1_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_2 = {2'h0,active_active_oh_2[13],1'h0,2'h0,active_active_oh_2[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_2 = {2'h0,active_active_oh_2[15],1'h0,2'h0,active_active_oh_2[14],1'h0,
- active_active_oh1_hi_hi_lo_2,active_active_oh1_hi_lo_2,active_active_oh1_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_2 = {1'h0,active_active_oh_2[1],2'h0,1'h0,active_active_oh_2[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_2 = {1'h0,active_active_oh_2[3],2'h0,1'h0,active_active_oh_2[2],2'h0,
- active_active_oh2_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_2 = {1'h0,active_active_oh_2[5],2'h0,1'h0,active_active_oh_2[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_2 = {1'h0,active_active_oh_2[7],2'h0,1'h0,active_active_oh_2[6],2'h0,
- active_active_oh2_lo_hi_lo_2,active_active_oh2_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_2 = {1'h0,active_active_oh_2[9],2'h0,1'h0,active_active_oh_2[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_2 = {1'h0,active_active_oh_2[11],2'h0,1'h0,active_active_oh_2[10],2'h0,
- active_active_oh2_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_2 = {1'h0,active_active_oh_2[13],2'h0,1'h0,active_active_oh_2[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_2 = {1'h0,active_active_oh_2[15],2'h0,1'h0,active_active_oh_2[14],2'h0,
- active_active_oh2_hi_hi_lo_2,active_active_oh2_hi_lo_2,active_active_oh2_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_2 = {active_active_oh_2[3],3'h0,active_active_oh_2[2],3'h0,active_active_oh_2[1],3'h0
- ,active_active_oh_2[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_2 = {active_active_oh_2[7],3'h0,active_active_oh_2[6],3'h0,active_active_oh_2[5],3'h0
- ,active_active_oh_2[4],3'h0,active_active_oh3_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_2 = {active_active_oh_2[11],3'h0,active_active_oh_2[10],3'h0,active_active_oh_2[9]
- ,3'h0,active_active_oh_2[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_2 = {active_active_oh_2[15],3'h0,active_active_oh_2[14],3'h0,active_active_oh_2[13],3'h0
- ,active_active_oh_2[12],3'h0,active_active_oh3_hi_lo_2,active_active_oh3_lo_2}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_2 = f_io_in_bits_0_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_65 = ~f_io_in_bits_0_bits_m & active_active_idx_2 == 2'h0 | f_io_in_bits_0_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_66 = _active_active_active_T_65 ? active_active_oh0_2 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_72 = _active_active_active_T & active_active_idx_2 == 2'h1 | _active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_73 = _active_active_active_T_72 ? active_active_oh1_2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_74 = _active_active_active_T_66 | _active_active_active_T_73; // @[VCommon.scala 107:68]
- wire _active_active_active_T_80 = _active_active_active_T & active_active_idx_2 == 2'h2 | _active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_81 = _active_active_active_T_80 ? active_active_oh2_2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_82 = _active_active_active_T_74 | _active_active_active_T_81; // @[VCommon.scala 108:68]
- wire _active_active_active_T_88 = _active_active_active_T & active_active_idx_2 == 2'h3 | _active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_89 = _active_active_active_T_88 ? active_active_oh3_2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_2 = _active_active_active_T_82 | _active_active_active_T_89; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_15 = f_io_in_bits_0_bits_tin_vu_valid ? active_active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active = _active_active_T_10 | _active_active_T_15; // @[VAlu.scala 250:74]
- wire [63:0] _active_T_5 = fvalid[0] ? active_active : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount_3 = f_io_in_bits_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_3 = 16'h1 << active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_3 = {3'h0,active_active_oh_3[3],3'h0,active_active_oh_3[2],3'h0,active_active_oh_3
- [1],3'h0,active_active_oh_3[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_3 = {3'h0,active_active_oh_3[7],3'h0,active_active_oh_3[6],3'h0,active_active_oh_3[5]
- ,3'h0,active_active_oh_3[4],active_active_oh0_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_3 = {3'h0,active_active_oh_3[11],3'h0,active_active_oh_3[10],3'h0,
- active_active_oh_3[9],3'h0,active_active_oh_3[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_3 = {3'h0,active_active_oh_3[15],3'h0,active_active_oh_3[14],3'h0,active_active_oh_3[13]
- ,3'h0,active_active_oh_3[12],active_active_oh0_hi_lo_3,active_active_oh0_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_3 = {2'h0,active_active_oh_3[1],1'h0,2'h0,active_active_oh_3[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_3 = {2'h0,active_active_oh_3[3],1'h0,2'h0,active_active_oh_3[2],1'h0,
- active_active_oh1_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_3 = {2'h0,active_active_oh_3[5],1'h0,2'h0,active_active_oh_3[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_3 = {2'h0,active_active_oh_3[7],1'h0,2'h0,active_active_oh_3[6],1'h0,
- active_active_oh1_lo_hi_lo_3,active_active_oh1_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_3 = {2'h0,active_active_oh_3[9],1'h0,2'h0,active_active_oh_3[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_3 = {2'h0,active_active_oh_3[11],1'h0,2'h0,active_active_oh_3[10],1'h0,
- active_active_oh1_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_3 = {2'h0,active_active_oh_3[13],1'h0,2'h0,active_active_oh_3[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_3 = {2'h0,active_active_oh_3[15],1'h0,2'h0,active_active_oh_3[14],1'h0,
- active_active_oh1_hi_hi_lo_3,active_active_oh1_hi_lo_3,active_active_oh1_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_3 = {1'h0,active_active_oh_3[1],2'h0,1'h0,active_active_oh_3[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_3 = {1'h0,active_active_oh_3[3],2'h0,1'h0,active_active_oh_3[2],2'h0,
- active_active_oh2_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_3 = {1'h0,active_active_oh_3[5],2'h0,1'h0,active_active_oh_3[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_3 = {1'h0,active_active_oh_3[7],2'h0,1'h0,active_active_oh_3[6],2'h0,
- active_active_oh2_lo_hi_lo_3,active_active_oh2_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_3 = {1'h0,active_active_oh_3[9],2'h0,1'h0,active_active_oh_3[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_3 = {1'h0,active_active_oh_3[11],2'h0,1'h0,active_active_oh_3[10],2'h0,
- active_active_oh2_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_3 = {1'h0,active_active_oh_3[13],2'h0,1'h0,active_active_oh_3[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_3 = {1'h0,active_active_oh_3[15],2'h0,1'h0,active_active_oh_3[14],2'h0,
- active_active_oh2_hi_hi_lo_3,active_active_oh2_hi_lo_3,active_active_oh2_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_3 = {active_active_oh_3[3],3'h0,active_active_oh_3[2],3'h0,active_active_oh_3[1],3'h0
- ,active_active_oh_3[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_3 = {active_active_oh_3[7],3'h0,active_active_oh_3[6],3'h0,active_active_oh_3[5],3'h0
- ,active_active_oh_3[4],3'h0,active_active_oh3_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_3 = {active_active_oh_3[11],3'h0,active_active_oh_3[10],3'h0,active_active_oh_3[9]
- ,3'h0,active_active_oh_3[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_3 = {active_active_oh_3[15],3'h0,active_active_oh_3[14],3'h0,active_active_oh_3[13],3'h0
- ,active_active_oh_3[12],3'h0,active_active_oh3_hi_lo_3,active_active_oh3_lo_3}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_3 = f_io_in_bits_1_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_90 = ~f_io_in_bits_1_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_94 = f_io_in_bits_1_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_95 = ~f_io_in_bits_1_bits_m & active_active_idx_3 == 2'h0 | f_io_in_bits_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_96 = _active_active_active_T_95 ? active_active_oh0_3 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_102 = _active_active_active_T_90 & active_active_idx_3 == 2'h1 |
- _active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_103 = _active_active_active_T_102 ? active_active_oh1_3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_104 = _active_active_active_T_96 | _active_active_active_T_103; // @[VCommon.scala 107:68]
- wire _active_active_active_T_110 = _active_active_active_T_90 & active_active_idx_3 == 2'h2 |
- _active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_111 = _active_active_active_T_110 ? active_active_oh2_3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_112 = _active_active_active_T_104 | _active_active_active_T_111; // @[VCommon.scala 108:68]
- wire _active_active_active_T_118 = _active_active_active_T_90 & active_active_idx_3 == 2'h3 |
- _active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_119 = _active_active_active_T_118 ? active_active_oh3_3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_3 = _active_active_active_T_112 | _active_active_active_T_119; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_20 = f_io_in_bits_1_bits_tin_vs_valid ? active_active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount_4 = f_io_in_bits_1_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_4 = 16'h1 << active_active_oh_shiftAmount_4; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_4 = {3'h0,active_active_oh_4[3],3'h0,active_active_oh_4[2],3'h0,active_active_oh_4
- [1],3'h0,active_active_oh_4[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_4 = {3'h0,active_active_oh_4[7],3'h0,active_active_oh_4[6],3'h0,active_active_oh_4[5]
- ,3'h0,active_active_oh_4[4],active_active_oh0_lo_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_4 = {3'h0,active_active_oh_4[11],3'h0,active_active_oh_4[10],3'h0,
- active_active_oh_4[9],3'h0,active_active_oh_4[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_4 = {3'h0,active_active_oh_4[15],3'h0,active_active_oh_4[14],3'h0,active_active_oh_4[13]
- ,3'h0,active_active_oh_4[12],active_active_oh0_hi_lo_4,active_active_oh0_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_4 = {2'h0,active_active_oh_4[1],1'h0,2'h0,active_active_oh_4[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_4 = {2'h0,active_active_oh_4[3],1'h0,2'h0,active_active_oh_4[2],1'h0,
- active_active_oh1_lo_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_4 = {2'h0,active_active_oh_4[5],1'h0,2'h0,active_active_oh_4[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_4 = {2'h0,active_active_oh_4[7],1'h0,2'h0,active_active_oh_4[6],1'h0,
- active_active_oh1_lo_hi_lo_4,active_active_oh1_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_4 = {2'h0,active_active_oh_4[9],1'h0,2'h0,active_active_oh_4[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_4 = {2'h0,active_active_oh_4[11],1'h0,2'h0,active_active_oh_4[10],1'h0,
- active_active_oh1_hi_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_4 = {2'h0,active_active_oh_4[13],1'h0,2'h0,active_active_oh_4[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_4 = {2'h0,active_active_oh_4[15],1'h0,2'h0,active_active_oh_4[14],1'h0,
- active_active_oh1_hi_hi_lo_4,active_active_oh1_hi_lo_4,active_active_oh1_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_4 = {1'h0,active_active_oh_4[1],2'h0,1'h0,active_active_oh_4[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_4 = {1'h0,active_active_oh_4[3],2'h0,1'h0,active_active_oh_4[2],2'h0,
- active_active_oh2_lo_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_4 = {1'h0,active_active_oh_4[5],2'h0,1'h0,active_active_oh_4[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_4 = {1'h0,active_active_oh_4[7],2'h0,1'h0,active_active_oh_4[6],2'h0,
- active_active_oh2_lo_hi_lo_4,active_active_oh2_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_4 = {1'h0,active_active_oh_4[9],2'h0,1'h0,active_active_oh_4[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_4 = {1'h0,active_active_oh_4[11],2'h0,1'h0,active_active_oh_4[10],2'h0,
- active_active_oh2_hi_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_4 = {1'h0,active_active_oh_4[13],2'h0,1'h0,active_active_oh_4[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_4 = {1'h0,active_active_oh_4[15],2'h0,1'h0,active_active_oh_4[14],2'h0,
- active_active_oh2_hi_hi_lo_4,active_active_oh2_hi_lo_4,active_active_oh2_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_4 = {active_active_oh_4[3],3'h0,active_active_oh_4[2],3'h0,active_active_oh_4[1],3'h0
- ,active_active_oh_4[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_4 = {active_active_oh_4[7],3'h0,active_active_oh_4[6],3'h0,active_active_oh_4[5],3'h0
- ,active_active_oh_4[4],3'h0,active_active_oh3_lo_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_4 = {active_active_oh_4[11],3'h0,active_active_oh_4[10],3'h0,active_active_oh_4[9]
- ,3'h0,active_active_oh_4[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_4 = {active_active_oh_4[15],3'h0,active_active_oh_4[14],3'h0,active_active_oh_4[13],3'h0
- ,active_active_oh_4[12],3'h0,active_active_oh3_hi_lo_4,active_active_oh3_lo_4}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_4 = f_io_in_bits_1_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_125 = ~f_io_in_bits_1_bits_m & active_active_idx_4 == 2'h0 | f_io_in_bits_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_126 = _active_active_active_T_125 ? active_active_oh0_4 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_132 = _active_active_active_T_90 & active_active_idx_4 == 2'h1 |
- _active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_133 = _active_active_active_T_132 ? active_active_oh1_4 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_134 = _active_active_active_T_126 | _active_active_active_T_133; // @[VCommon.scala 107:68]
- wire _active_active_active_T_140 = _active_active_active_T_90 & active_active_idx_4 == 2'h2 |
- _active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_141 = _active_active_active_T_140 ? active_active_oh2_4 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_142 = _active_active_active_T_134 | _active_active_active_T_141; // @[VCommon.scala 108:68]
- wire _active_active_active_T_148 = _active_active_active_T_90 & active_active_idx_4 == 2'h3 |
- _active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_149 = _active_active_active_T_148 ? active_active_oh3_4 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_4 = _active_active_active_T_142 | _active_active_active_T_149; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_25 = f_io_in_bits_1_bits_tin_vt_valid ? active_active_active_4 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_T_26 = _active_active_T_20 | _active_active_T_25; // @[VAlu.scala 249:74]
- wire [3:0] active_active_oh_shiftAmount_5 = f_io_in_bits_1_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_5 = 16'h1 << active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_5 = {3'h0,active_active_oh_5[3],3'h0,active_active_oh_5[2],3'h0,active_active_oh_5
- [1],3'h0,active_active_oh_5[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_5 = {3'h0,active_active_oh_5[7],3'h0,active_active_oh_5[6],3'h0,active_active_oh_5[5]
- ,3'h0,active_active_oh_5[4],active_active_oh0_lo_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_5 = {3'h0,active_active_oh_5[11],3'h0,active_active_oh_5[10],3'h0,
- active_active_oh_5[9],3'h0,active_active_oh_5[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_5 = {3'h0,active_active_oh_5[15],3'h0,active_active_oh_5[14],3'h0,active_active_oh_5[13]
- ,3'h0,active_active_oh_5[12],active_active_oh0_hi_lo_5,active_active_oh0_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_5 = {2'h0,active_active_oh_5[1],1'h0,2'h0,active_active_oh_5[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_5 = {2'h0,active_active_oh_5[3],1'h0,2'h0,active_active_oh_5[2],1'h0,
- active_active_oh1_lo_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_5 = {2'h0,active_active_oh_5[5],1'h0,2'h0,active_active_oh_5[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_5 = {2'h0,active_active_oh_5[7],1'h0,2'h0,active_active_oh_5[6],1'h0,
- active_active_oh1_lo_hi_lo_5,active_active_oh1_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_5 = {2'h0,active_active_oh_5[9],1'h0,2'h0,active_active_oh_5[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_5 = {2'h0,active_active_oh_5[11],1'h0,2'h0,active_active_oh_5[10],1'h0,
- active_active_oh1_hi_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_5 = {2'h0,active_active_oh_5[13],1'h0,2'h0,active_active_oh_5[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_5 = {2'h0,active_active_oh_5[15],1'h0,2'h0,active_active_oh_5[14],1'h0,
- active_active_oh1_hi_hi_lo_5,active_active_oh1_hi_lo_5,active_active_oh1_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_5 = {1'h0,active_active_oh_5[1],2'h0,1'h0,active_active_oh_5[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_5 = {1'h0,active_active_oh_5[3],2'h0,1'h0,active_active_oh_5[2],2'h0,
- active_active_oh2_lo_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_5 = {1'h0,active_active_oh_5[5],2'h0,1'h0,active_active_oh_5[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_5 = {1'h0,active_active_oh_5[7],2'h0,1'h0,active_active_oh_5[6],2'h0,
- active_active_oh2_lo_hi_lo_5,active_active_oh2_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_5 = {1'h0,active_active_oh_5[9],2'h0,1'h0,active_active_oh_5[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_5 = {1'h0,active_active_oh_5[11],2'h0,1'h0,active_active_oh_5[10],2'h0,
- active_active_oh2_hi_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_5 = {1'h0,active_active_oh_5[13],2'h0,1'h0,active_active_oh_5[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_5 = {1'h0,active_active_oh_5[15],2'h0,1'h0,active_active_oh_5[14],2'h0,
- active_active_oh2_hi_hi_lo_5,active_active_oh2_hi_lo_5,active_active_oh2_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_5 = {active_active_oh_5[3],3'h0,active_active_oh_5[2],3'h0,active_active_oh_5[1],3'h0
- ,active_active_oh_5[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_5 = {active_active_oh_5[7],3'h0,active_active_oh_5[6],3'h0,active_active_oh_5[5],3'h0
- ,active_active_oh_5[4],3'h0,active_active_oh3_lo_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_5 = {active_active_oh_5[11],3'h0,active_active_oh_5[10],3'h0,active_active_oh_5[9]
- ,3'h0,active_active_oh_5[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_5 = {active_active_oh_5[15],3'h0,active_active_oh_5[14],3'h0,active_active_oh_5[13],3'h0
- ,active_active_oh_5[12],3'h0,active_active_oh3_hi_lo_5,active_active_oh3_lo_5}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_5 = f_io_in_bits_1_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_155 = ~f_io_in_bits_1_bits_m & active_active_idx_5 == 2'h0 | f_io_in_bits_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_156 = _active_active_active_T_155 ? active_active_oh0_5 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_162 = _active_active_active_T_90 & active_active_idx_5 == 2'h1 |
- _active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_163 = _active_active_active_T_162 ? active_active_oh1_5 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_164 = _active_active_active_T_156 | _active_active_active_T_163; // @[VCommon.scala 107:68]
- wire _active_active_active_T_170 = _active_active_active_T_90 & active_active_idx_5 == 2'h2 |
- _active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_171 = _active_active_active_T_170 ? active_active_oh2_5 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_172 = _active_active_active_T_164 | _active_active_active_T_171; // @[VCommon.scala 108:68]
- wire _active_active_active_T_178 = _active_active_active_T_90 & active_active_idx_5 == 2'h3 |
- _active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_179 = _active_active_active_T_178 ? active_active_oh3_5 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_5 = _active_active_active_T_172 | _active_active_active_T_179; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_31 = f_io_in_bits_1_bits_tin_vu_valid ? active_active_active_5 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_1 = _active_active_T_26 | _active_active_T_31; // @[VAlu.scala 250:74]
- wire [63:0] _active_T_11 = fvalid[1] ? active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_12 = _active_T_5 | _active_T_11; // @[VCmdq.scala 124:90]
- wire [3:0] active_active_oh_shiftAmount_6 = f_io_in_bits_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_6 = 16'h1 << active_active_oh_shiftAmount_6; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_6 = {3'h0,active_active_oh_6[3],3'h0,active_active_oh_6[2],3'h0,active_active_oh_6
- [1],3'h0,active_active_oh_6[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_6 = {3'h0,active_active_oh_6[7],3'h0,active_active_oh_6[6],3'h0,active_active_oh_6[5]
- ,3'h0,active_active_oh_6[4],active_active_oh0_lo_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_6 = {3'h0,active_active_oh_6[11],3'h0,active_active_oh_6[10],3'h0,
- active_active_oh_6[9],3'h0,active_active_oh_6[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_6 = {3'h0,active_active_oh_6[15],3'h0,active_active_oh_6[14],3'h0,active_active_oh_6[13]
- ,3'h0,active_active_oh_6[12],active_active_oh0_hi_lo_6,active_active_oh0_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_6 = {2'h0,active_active_oh_6[1],1'h0,2'h0,active_active_oh_6[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_6 = {2'h0,active_active_oh_6[3],1'h0,2'h0,active_active_oh_6[2],1'h0,
- active_active_oh1_lo_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_6 = {2'h0,active_active_oh_6[5],1'h0,2'h0,active_active_oh_6[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_6 = {2'h0,active_active_oh_6[7],1'h0,2'h0,active_active_oh_6[6],1'h0,
- active_active_oh1_lo_hi_lo_6,active_active_oh1_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_6 = {2'h0,active_active_oh_6[9],1'h0,2'h0,active_active_oh_6[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_6 = {2'h0,active_active_oh_6[11],1'h0,2'h0,active_active_oh_6[10],1'h0,
- active_active_oh1_hi_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_6 = {2'h0,active_active_oh_6[13],1'h0,2'h0,active_active_oh_6[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_6 = {2'h0,active_active_oh_6[15],1'h0,2'h0,active_active_oh_6[14],1'h0,
- active_active_oh1_hi_hi_lo_6,active_active_oh1_hi_lo_6,active_active_oh1_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_6 = {1'h0,active_active_oh_6[1],2'h0,1'h0,active_active_oh_6[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_6 = {1'h0,active_active_oh_6[3],2'h0,1'h0,active_active_oh_6[2],2'h0,
- active_active_oh2_lo_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_6 = {1'h0,active_active_oh_6[5],2'h0,1'h0,active_active_oh_6[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_6 = {1'h0,active_active_oh_6[7],2'h0,1'h0,active_active_oh_6[6],2'h0,
- active_active_oh2_lo_hi_lo_6,active_active_oh2_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_6 = {1'h0,active_active_oh_6[9],2'h0,1'h0,active_active_oh_6[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_6 = {1'h0,active_active_oh_6[11],2'h0,1'h0,active_active_oh_6[10],2'h0,
- active_active_oh2_hi_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_6 = {1'h0,active_active_oh_6[13],2'h0,1'h0,active_active_oh_6[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_6 = {1'h0,active_active_oh_6[15],2'h0,1'h0,active_active_oh_6[14],2'h0,
- active_active_oh2_hi_hi_lo_6,active_active_oh2_hi_lo_6,active_active_oh2_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_6 = {active_active_oh_6[3],3'h0,active_active_oh_6[2],3'h0,active_active_oh_6[1],3'h0
- ,active_active_oh_6[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_6 = {active_active_oh_6[7],3'h0,active_active_oh_6[6],3'h0,active_active_oh_6[5],3'h0
- ,active_active_oh_6[4],3'h0,active_active_oh3_lo_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_6 = {active_active_oh_6[11],3'h0,active_active_oh_6[10],3'h0,active_active_oh_6[9]
- ,3'h0,active_active_oh_6[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_6 = {active_active_oh_6[15],3'h0,active_active_oh_6[14],3'h0,active_active_oh_6[13],3'h0
- ,active_active_oh_6[12],3'h0,active_active_oh3_hi_lo_6,active_active_oh3_lo_6}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_6 = f_io_in_bits_2_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_180 = ~f_io_in_bits_2_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_184 = f_io_in_bits_2_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_185 = ~f_io_in_bits_2_bits_m & active_active_idx_6 == 2'h0 | f_io_in_bits_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_186 = _active_active_active_T_185 ? active_active_oh0_6 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_192 = _active_active_active_T_180 & active_active_idx_6 == 2'h1 |
- _active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_193 = _active_active_active_T_192 ? active_active_oh1_6 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_194 = _active_active_active_T_186 | _active_active_active_T_193; // @[VCommon.scala 107:68]
- wire _active_active_active_T_200 = _active_active_active_T_180 & active_active_idx_6 == 2'h2 |
- _active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_201 = _active_active_active_T_200 ? active_active_oh2_6 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_202 = _active_active_active_T_194 | _active_active_active_T_201; // @[VCommon.scala 108:68]
- wire _active_active_active_T_208 = _active_active_active_T_180 & active_active_idx_6 == 2'h3 |
- _active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_209 = _active_active_active_T_208 ? active_active_oh3_6 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_6 = _active_active_active_T_202 | _active_active_active_T_209; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_36 = f_io_in_bits_2_bits_tin_vs_valid ? active_active_active_6 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount_7 = f_io_in_bits_2_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_7 = 16'h1 << active_active_oh_shiftAmount_7; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_7 = {3'h0,active_active_oh_7[3],3'h0,active_active_oh_7[2],3'h0,active_active_oh_7
- [1],3'h0,active_active_oh_7[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_7 = {3'h0,active_active_oh_7[7],3'h0,active_active_oh_7[6],3'h0,active_active_oh_7[5]
- ,3'h0,active_active_oh_7[4],active_active_oh0_lo_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_7 = {3'h0,active_active_oh_7[11],3'h0,active_active_oh_7[10],3'h0,
- active_active_oh_7[9],3'h0,active_active_oh_7[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_7 = {3'h0,active_active_oh_7[15],3'h0,active_active_oh_7[14],3'h0,active_active_oh_7[13]
- ,3'h0,active_active_oh_7[12],active_active_oh0_hi_lo_7,active_active_oh0_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_7 = {2'h0,active_active_oh_7[1],1'h0,2'h0,active_active_oh_7[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_7 = {2'h0,active_active_oh_7[3],1'h0,2'h0,active_active_oh_7[2],1'h0,
- active_active_oh1_lo_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_7 = {2'h0,active_active_oh_7[5],1'h0,2'h0,active_active_oh_7[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_7 = {2'h0,active_active_oh_7[7],1'h0,2'h0,active_active_oh_7[6],1'h0,
- active_active_oh1_lo_hi_lo_7,active_active_oh1_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_7 = {2'h0,active_active_oh_7[9],1'h0,2'h0,active_active_oh_7[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_7 = {2'h0,active_active_oh_7[11],1'h0,2'h0,active_active_oh_7[10],1'h0,
- active_active_oh1_hi_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_7 = {2'h0,active_active_oh_7[13],1'h0,2'h0,active_active_oh_7[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_7 = {2'h0,active_active_oh_7[15],1'h0,2'h0,active_active_oh_7[14],1'h0,
- active_active_oh1_hi_hi_lo_7,active_active_oh1_hi_lo_7,active_active_oh1_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_7 = {1'h0,active_active_oh_7[1],2'h0,1'h0,active_active_oh_7[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_7 = {1'h0,active_active_oh_7[3],2'h0,1'h0,active_active_oh_7[2],2'h0,
- active_active_oh2_lo_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_7 = {1'h0,active_active_oh_7[5],2'h0,1'h0,active_active_oh_7[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_7 = {1'h0,active_active_oh_7[7],2'h0,1'h0,active_active_oh_7[6],2'h0,
- active_active_oh2_lo_hi_lo_7,active_active_oh2_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_7 = {1'h0,active_active_oh_7[9],2'h0,1'h0,active_active_oh_7[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_7 = {1'h0,active_active_oh_7[11],2'h0,1'h0,active_active_oh_7[10],2'h0,
- active_active_oh2_hi_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_7 = {1'h0,active_active_oh_7[13],2'h0,1'h0,active_active_oh_7[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_7 = {1'h0,active_active_oh_7[15],2'h0,1'h0,active_active_oh_7[14],2'h0,
- active_active_oh2_hi_hi_lo_7,active_active_oh2_hi_lo_7,active_active_oh2_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_7 = {active_active_oh_7[3],3'h0,active_active_oh_7[2],3'h0,active_active_oh_7[1],3'h0
- ,active_active_oh_7[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_7 = {active_active_oh_7[7],3'h0,active_active_oh_7[6],3'h0,active_active_oh_7[5],3'h0
- ,active_active_oh_7[4],3'h0,active_active_oh3_lo_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_7 = {active_active_oh_7[11],3'h0,active_active_oh_7[10],3'h0,active_active_oh_7[9]
- ,3'h0,active_active_oh_7[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_7 = {active_active_oh_7[15],3'h0,active_active_oh_7[14],3'h0,active_active_oh_7[13],3'h0
- ,active_active_oh_7[12],3'h0,active_active_oh3_hi_lo_7,active_active_oh3_lo_7}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_7 = f_io_in_bits_2_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_215 = ~f_io_in_bits_2_bits_m & active_active_idx_7 == 2'h0 | f_io_in_bits_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_216 = _active_active_active_T_215 ? active_active_oh0_7 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_222 = _active_active_active_T_180 & active_active_idx_7 == 2'h1 |
- _active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_223 = _active_active_active_T_222 ? active_active_oh1_7 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_224 = _active_active_active_T_216 | _active_active_active_T_223; // @[VCommon.scala 107:68]
- wire _active_active_active_T_230 = _active_active_active_T_180 & active_active_idx_7 == 2'h2 |
- _active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_231 = _active_active_active_T_230 ? active_active_oh2_7 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_232 = _active_active_active_T_224 | _active_active_active_T_231; // @[VCommon.scala 108:68]
- wire _active_active_active_T_238 = _active_active_active_T_180 & active_active_idx_7 == 2'h3 |
- _active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_239 = _active_active_active_T_238 ? active_active_oh3_7 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_7 = _active_active_active_T_232 | _active_active_active_T_239; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_41 = f_io_in_bits_2_bits_tin_vt_valid ? active_active_active_7 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_T_42 = _active_active_T_36 | _active_active_T_41; // @[VAlu.scala 249:74]
- wire [3:0] active_active_oh_shiftAmount_8 = f_io_in_bits_2_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_8 = 16'h1 << active_active_oh_shiftAmount_8; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_8 = {3'h0,active_active_oh_8[3],3'h0,active_active_oh_8[2],3'h0,active_active_oh_8
- [1],3'h0,active_active_oh_8[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_8 = {3'h0,active_active_oh_8[7],3'h0,active_active_oh_8[6],3'h0,active_active_oh_8[5]
- ,3'h0,active_active_oh_8[4],active_active_oh0_lo_lo_8}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_8 = {3'h0,active_active_oh_8[11],3'h0,active_active_oh_8[10],3'h0,
- active_active_oh_8[9],3'h0,active_active_oh_8[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_8 = {3'h0,active_active_oh_8[15],3'h0,active_active_oh_8[14],3'h0,active_active_oh_8[13]
- ,3'h0,active_active_oh_8[12],active_active_oh0_hi_lo_8,active_active_oh0_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_8 = {2'h0,active_active_oh_8[1],1'h0,2'h0,active_active_oh_8[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_8 = {2'h0,active_active_oh_8[3],1'h0,2'h0,active_active_oh_8[2],1'h0,
- active_active_oh1_lo_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_8 = {2'h0,active_active_oh_8[5],1'h0,2'h0,active_active_oh_8[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_8 = {2'h0,active_active_oh_8[7],1'h0,2'h0,active_active_oh_8[6],1'h0,
- active_active_oh1_lo_hi_lo_8,active_active_oh1_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_8 = {2'h0,active_active_oh_8[9],1'h0,2'h0,active_active_oh_8[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_8 = {2'h0,active_active_oh_8[11],1'h0,2'h0,active_active_oh_8[10],1'h0,
- active_active_oh1_hi_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_8 = {2'h0,active_active_oh_8[13],1'h0,2'h0,active_active_oh_8[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_8 = {2'h0,active_active_oh_8[15],1'h0,2'h0,active_active_oh_8[14],1'h0,
- active_active_oh1_hi_hi_lo_8,active_active_oh1_hi_lo_8,active_active_oh1_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_8 = {1'h0,active_active_oh_8[1],2'h0,1'h0,active_active_oh_8[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_8 = {1'h0,active_active_oh_8[3],2'h0,1'h0,active_active_oh_8[2],2'h0,
- active_active_oh2_lo_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_8 = {1'h0,active_active_oh_8[5],2'h0,1'h0,active_active_oh_8[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_8 = {1'h0,active_active_oh_8[7],2'h0,1'h0,active_active_oh_8[6],2'h0,
- active_active_oh2_lo_hi_lo_8,active_active_oh2_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_8 = {1'h0,active_active_oh_8[9],2'h0,1'h0,active_active_oh_8[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_8 = {1'h0,active_active_oh_8[11],2'h0,1'h0,active_active_oh_8[10],2'h0,
- active_active_oh2_hi_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_8 = {1'h0,active_active_oh_8[13],2'h0,1'h0,active_active_oh_8[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_8 = {1'h0,active_active_oh_8[15],2'h0,1'h0,active_active_oh_8[14],2'h0,
- active_active_oh2_hi_hi_lo_8,active_active_oh2_hi_lo_8,active_active_oh2_lo_8}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_8 = {active_active_oh_8[3],3'h0,active_active_oh_8[2],3'h0,active_active_oh_8[1],3'h0
- ,active_active_oh_8[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_8 = {active_active_oh_8[7],3'h0,active_active_oh_8[6],3'h0,active_active_oh_8[5],3'h0
- ,active_active_oh_8[4],3'h0,active_active_oh3_lo_lo_8}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_8 = {active_active_oh_8[11],3'h0,active_active_oh_8[10],3'h0,active_active_oh_8[9]
- ,3'h0,active_active_oh_8[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_8 = {active_active_oh_8[15],3'h0,active_active_oh_8[14],3'h0,active_active_oh_8[13],3'h0
- ,active_active_oh_8[12],3'h0,active_active_oh3_hi_lo_8,active_active_oh3_lo_8}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_8 = f_io_in_bits_2_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_245 = ~f_io_in_bits_2_bits_m & active_active_idx_8 == 2'h0 | f_io_in_bits_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_246 = _active_active_active_T_245 ? active_active_oh0_8 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_252 = _active_active_active_T_180 & active_active_idx_8 == 2'h1 |
- _active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_253 = _active_active_active_T_252 ? active_active_oh1_8 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_254 = _active_active_active_T_246 | _active_active_active_T_253; // @[VCommon.scala 107:68]
- wire _active_active_active_T_260 = _active_active_active_T_180 & active_active_idx_8 == 2'h2 |
- _active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_261 = _active_active_active_T_260 ? active_active_oh2_8 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_262 = _active_active_active_T_254 | _active_active_active_T_261; // @[VCommon.scala 108:68]
- wire _active_active_active_T_268 = _active_active_active_T_180 & active_active_idx_8 == 2'h3 |
- _active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_269 = _active_active_active_T_268 ? active_active_oh3_8 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_8 = _active_active_active_T_262 | _active_active_active_T_269; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_47 = f_io_in_bits_2_bits_tin_vu_valid ? active_active_active_8 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_2 = _active_active_T_42 | _active_active_T_47; // @[VAlu.scala 250:74]
- wire [63:0] _active_T_18 = fvalid[2] ? active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_19 = _active_T_12 | _active_T_18; // @[VCmdq.scala 125:90]
- wire [3:0] active_active_oh_shiftAmount_9 = f_io_in_bits_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_9 = 16'h1 << active_active_oh_shiftAmount_9; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_9 = {3'h0,active_active_oh_9[3],3'h0,active_active_oh_9[2],3'h0,active_active_oh_9
- [1],3'h0,active_active_oh_9[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_9 = {3'h0,active_active_oh_9[7],3'h0,active_active_oh_9[6],3'h0,active_active_oh_9[5]
- ,3'h0,active_active_oh_9[4],active_active_oh0_lo_lo_9}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_9 = {3'h0,active_active_oh_9[11],3'h0,active_active_oh_9[10],3'h0,
- active_active_oh_9[9],3'h0,active_active_oh_9[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_9 = {3'h0,active_active_oh_9[15],3'h0,active_active_oh_9[14],3'h0,active_active_oh_9[13]
- ,3'h0,active_active_oh_9[12],active_active_oh0_hi_lo_9,active_active_oh0_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_9 = {2'h0,active_active_oh_9[1],1'h0,2'h0,active_active_oh_9[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_9 = {2'h0,active_active_oh_9[3],1'h0,2'h0,active_active_oh_9[2],1'h0,
- active_active_oh1_lo_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_9 = {2'h0,active_active_oh_9[5],1'h0,2'h0,active_active_oh_9[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_9 = {2'h0,active_active_oh_9[7],1'h0,2'h0,active_active_oh_9[6],1'h0,
- active_active_oh1_lo_hi_lo_9,active_active_oh1_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_9 = {2'h0,active_active_oh_9[9],1'h0,2'h0,active_active_oh_9[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_9 = {2'h0,active_active_oh_9[11],1'h0,2'h0,active_active_oh_9[10],1'h0,
- active_active_oh1_hi_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_9 = {2'h0,active_active_oh_9[13],1'h0,2'h0,active_active_oh_9[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_9 = {2'h0,active_active_oh_9[15],1'h0,2'h0,active_active_oh_9[14],1'h0,
- active_active_oh1_hi_hi_lo_9,active_active_oh1_hi_lo_9,active_active_oh1_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_9 = {1'h0,active_active_oh_9[1],2'h0,1'h0,active_active_oh_9[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_9 = {1'h0,active_active_oh_9[3],2'h0,1'h0,active_active_oh_9[2],2'h0,
- active_active_oh2_lo_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_9 = {1'h0,active_active_oh_9[5],2'h0,1'h0,active_active_oh_9[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_9 = {1'h0,active_active_oh_9[7],2'h0,1'h0,active_active_oh_9[6],2'h0,
- active_active_oh2_lo_hi_lo_9,active_active_oh2_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_9 = {1'h0,active_active_oh_9[9],2'h0,1'h0,active_active_oh_9[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_9 = {1'h0,active_active_oh_9[11],2'h0,1'h0,active_active_oh_9[10],2'h0,
- active_active_oh2_hi_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_9 = {1'h0,active_active_oh_9[13],2'h0,1'h0,active_active_oh_9[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_9 = {1'h0,active_active_oh_9[15],2'h0,1'h0,active_active_oh_9[14],2'h0,
- active_active_oh2_hi_hi_lo_9,active_active_oh2_hi_lo_9,active_active_oh2_lo_9}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_9 = {active_active_oh_9[3],3'h0,active_active_oh_9[2],3'h0,active_active_oh_9[1],3'h0
- ,active_active_oh_9[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_9 = {active_active_oh_9[7],3'h0,active_active_oh_9[6],3'h0,active_active_oh_9[5],3'h0
- ,active_active_oh_9[4],3'h0,active_active_oh3_lo_lo_9}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_9 = {active_active_oh_9[11],3'h0,active_active_oh_9[10],3'h0,active_active_oh_9[9]
- ,3'h0,active_active_oh_9[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_9 = {active_active_oh_9[15],3'h0,active_active_oh_9[14],3'h0,active_active_oh_9[13],3'h0
- ,active_active_oh_9[12],3'h0,active_active_oh3_hi_lo_9,active_active_oh3_lo_9}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_9 = f_io_in_bits_3_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_270 = ~f_io_in_bits_3_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_274 = f_io_in_bits_3_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_275 = ~f_io_in_bits_3_bits_m & active_active_idx_9 == 2'h0 | f_io_in_bits_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_276 = _active_active_active_T_275 ? active_active_oh0_9 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_282 = _active_active_active_T_270 & active_active_idx_9 == 2'h1 |
- _active_active_active_T_274; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_283 = _active_active_active_T_282 ? active_active_oh1_9 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_284 = _active_active_active_T_276 | _active_active_active_T_283; // @[VCommon.scala 107:68]
- wire _active_active_active_T_290 = _active_active_active_T_270 & active_active_idx_9 == 2'h2 |
- _active_active_active_T_274; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_291 = _active_active_active_T_290 ? active_active_oh2_9 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_292 = _active_active_active_T_284 | _active_active_active_T_291; // @[VCommon.scala 108:68]
- wire _active_active_active_T_298 = _active_active_active_T_270 & active_active_idx_9 == 2'h3 |
- _active_active_active_T_274; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_299 = _active_active_active_T_298 ? active_active_oh3_9 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_9 = _active_active_active_T_292 | _active_active_active_T_299; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_52 = f_io_in_bits_3_bits_tin_vs_valid ? active_active_active_9 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount_10 = f_io_in_bits_3_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_10 = 16'h1 << active_active_oh_shiftAmount_10; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_10 = {3'h0,active_active_oh_10[3],3'h0,active_active_oh_10[2],3'h0,
- active_active_oh_10[1],3'h0,active_active_oh_10[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_10 = {3'h0,active_active_oh_10[7],3'h0,active_active_oh_10[6],3'h0,
- active_active_oh_10[5],3'h0,active_active_oh_10[4],active_active_oh0_lo_lo_10}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_10 = {3'h0,active_active_oh_10[11],3'h0,active_active_oh_10[10],3'h0,
- active_active_oh_10[9],3'h0,active_active_oh_10[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_10 = {3'h0,active_active_oh_10[15],3'h0,active_active_oh_10[14],3'h0,active_active_oh_10
- [13],3'h0,active_active_oh_10[12],active_active_oh0_hi_lo_10,active_active_oh0_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_10 = {2'h0,active_active_oh_10[1],1'h0,2'h0,active_active_oh_10[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_10 = {2'h0,active_active_oh_10[3],1'h0,2'h0,active_active_oh_10[2],1'h0,
- active_active_oh1_lo_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_10 = {2'h0,active_active_oh_10[5],1'h0,2'h0,active_active_oh_10[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_10 = {2'h0,active_active_oh_10[7],1'h0,2'h0,active_active_oh_10[6],1'h0,
- active_active_oh1_lo_hi_lo_10,active_active_oh1_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_10 = {2'h0,active_active_oh_10[9],1'h0,2'h0,active_active_oh_10[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_10 = {2'h0,active_active_oh_10[11],1'h0,2'h0,active_active_oh_10[10],1'h0,
- active_active_oh1_hi_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_10 = {2'h0,active_active_oh_10[13],1'h0,2'h0,active_active_oh_10[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_10 = {2'h0,active_active_oh_10[15],1'h0,2'h0,active_active_oh_10[14],1'h0,
- active_active_oh1_hi_hi_lo_10,active_active_oh1_hi_lo_10,active_active_oh1_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_10 = {1'h0,active_active_oh_10[1],2'h0,1'h0,active_active_oh_10[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_10 = {1'h0,active_active_oh_10[3],2'h0,1'h0,active_active_oh_10[2],2'h0,
- active_active_oh2_lo_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_10 = {1'h0,active_active_oh_10[5],2'h0,1'h0,active_active_oh_10[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_10 = {1'h0,active_active_oh_10[7],2'h0,1'h0,active_active_oh_10[6],2'h0,
- active_active_oh2_lo_hi_lo_10,active_active_oh2_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_10 = {1'h0,active_active_oh_10[9],2'h0,1'h0,active_active_oh_10[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_10 = {1'h0,active_active_oh_10[11],2'h0,1'h0,active_active_oh_10[10],2'h0,
- active_active_oh2_hi_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_10 = {1'h0,active_active_oh_10[13],2'h0,1'h0,active_active_oh_10[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_10 = {1'h0,active_active_oh_10[15],2'h0,1'h0,active_active_oh_10[14],2'h0,
- active_active_oh2_hi_hi_lo_10,active_active_oh2_hi_lo_10,active_active_oh2_lo_10}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_10 = {active_active_oh_10[3],3'h0,active_active_oh_10[2],3'h0,active_active_oh_10[
- 1],3'h0,active_active_oh_10[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_10 = {active_active_oh_10[7],3'h0,active_active_oh_10[6],3'h0,active_active_oh_10[5],3'h0
- ,active_active_oh_10[4],3'h0,active_active_oh3_lo_lo_10}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_10 = {active_active_oh_10[11],3'h0,active_active_oh_10[10],3'h0,
- active_active_oh_10[9],3'h0,active_active_oh_10[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_10 = {active_active_oh_10[15],3'h0,active_active_oh_10[14],3'h0,active_active_oh_10[13],3'h0
- ,active_active_oh_10[12],3'h0,active_active_oh3_hi_lo_10,active_active_oh3_lo_10}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_10 = f_io_in_bits_3_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_305 = ~f_io_in_bits_3_bits_m & active_active_idx_10 == 2'h0 | f_io_in_bits_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_306 = _active_active_active_T_305 ? active_active_oh0_10 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_312 = _active_active_active_T_270 & active_active_idx_10 == 2'h1 |
- _active_active_active_T_274; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_313 = _active_active_active_T_312 ? active_active_oh1_10 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_314 = _active_active_active_T_306 | _active_active_active_T_313; // @[VCommon.scala 107:68]
- wire _active_active_active_T_320 = _active_active_active_T_270 & active_active_idx_10 == 2'h2 |
- _active_active_active_T_274; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_321 = _active_active_active_T_320 ? active_active_oh2_10 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_322 = _active_active_active_T_314 | _active_active_active_T_321; // @[VCommon.scala 108:68]
- wire _active_active_active_T_328 = _active_active_active_T_270 & active_active_idx_10 == 2'h3 |
- _active_active_active_T_274; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_329 = _active_active_active_T_328 ? active_active_oh3_10 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_10 = _active_active_active_T_322 | _active_active_active_T_329; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_57 = f_io_in_bits_3_bits_tin_vt_valid ? active_active_active_10 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_T_58 = _active_active_T_52 | _active_active_T_57; // @[VAlu.scala 249:74]
- wire [3:0] active_active_oh_shiftAmount_11 = f_io_in_bits_3_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_11 = 16'h1 << active_active_oh_shiftAmount_11; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_11 = {3'h0,active_active_oh_11[3],3'h0,active_active_oh_11[2],3'h0,
- active_active_oh_11[1],3'h0,active_active_oh_11[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_11 = {3'h0,active_active_oh_11[7],3'h0,active_active_oh_11[6],3'h0,
- active_active_oh_11[5],3'h0,active_active_oh_11[4],active_active_oh0_lo_lo_11}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_11 = {3'h0,active_active_oh_11[11],3'h0,active_active_oh_11[10],3'h0,
- active_active_oh_11[9],3'h0,active_active_oh_11[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_11 = {3'h0,active_active_oh_11[15],3'h0,active_active_oh_11[14],3'h0,active_active_oh_11
- [13],3'h0,active_active_oh_11[12],active_active_oh0_hi_lo_11,active_active_oh0_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_11 = {2'h0,active_active_oh_11[1],1'h0,2'h0,active_active_oh_11[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_11 = {2'h0,active_active_oh_11[3],1'h0,2'h0,active_active_oh_11[2],1'h0,
- active_active_oh1_lo_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_11 = {2'h0,active_active_oh_11[5],1'h0,2'h0,active_active_oh_11[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_11 = {2'h0,active_active_oh_11[7],1'h0,2'h0,active_active_oh_11[6],1'h0,
- active_active_oh1_lo_hi_lo_11,active_active_oh1_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_11 = {2'h0,active_active_oh_11[9],1'h0,2'h0,active_active_oh_11[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_11 = {2'h0,active_active_oh_11[11],1'h0,2'h0,active_active_oh_11[10],1'h0,
- active_active_oh1_hi_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_11 = {2'h0,active_active_oh_11[13],1'h0,2'h0,active_active_oh_11[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_11 = {2'h0,active_active_oh_11[15],1'h0,2'h0,active_active_oh_11[14],1'h0,
- active_active_oh1_hi_hi_lo_11,active_active_oh1_hi_lo_11,active_active_oh1_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_11 = {1'h0,active_active_oh_11[1],2'h0,1'h0,active_active_oh_11[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_11 = {1'h0,active_active_oh_11[3],2'h0,1'h0,active_active_oh_11[2],2'h0,
- active_active_oh2_lo_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_11 = {1'h0,active_active_oh_11[5],2'h0,1'h0,active_active_oh_11[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_11 = {1'h0,active_active_oh_11[7],2'h0,1'h0,active_active_oh_11[6],2'h0,
- active_active_oh2_lo_hi_lo_11,active_active_oh2_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_11 = {1'h0,active_active_oh_11[9],2'h0,1'h0,active_active_oh_11[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_11 = {1'h0,active_active_oh_11[11],2'h0,1'h0,active_active_oh_11[10],2'h0,
- active_active_oh2_hi_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_11 = {1'h0,active_active_oh_11[13],2'h0,1'h0,active_active_oh_11[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_11 = {1'h0,active_active_oh_11[15],2'h0,1'h0,active_active_oh_11[14],2'h0,
- active_active_oh2_hi_hi_lo_11,active_active_oh2_hi_lo_11,active_active_oh2_lo_11}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_11 = {active_active_oh_11[3],3'h0,active_active_oh_11[2],3'h0,active_active_oh_11[
- 1],3'h0,active_active_oh_11[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_11 = {active_active_oh_11[7],3'h0,active_active_oh_11[6],3'h0,active_active_oh_11[5],3'h0
- ,active_active_oh_11[4],3'h0,active_active_oh3_lo_lo_11}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_11 = {active_active_oh_11[11],3'h0,active_active_oh_11[10],3'h0,
- active_active_oh_11[9],3'h0,active_active_oh_11[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_11 = {active_active_oh_11[15],3'h0,active_active_oh_11[14],3'h0,active_active_oh_11[13],3'h0
- ,active_active_oh_11[12],3'h0,active_active_oh3_hi_lo_11,active_active_oh3_lo_11}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_11 = f_io_in_bits_3_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_335 = ~f_io_in_bits_3_bits_m & active_active_idx_11 == 2'h0 | f_io_in_bits_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_336 = _active_active_active_T_335 ? active_active_oh0_11 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_342 = _active_active_active_T_270 & active_active_idx_11 == 2'h1 |
- _active_active_active_T_274; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_343 = _active_active_active_T_342 ? active_active_oh1_11 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_344 = _active_active_active_T_336 | _active_active_active_T_343; // @[VCommon.scala 107:68]
- wire _active_active_active_T_350 = _active_active_active_T_270 & active_active_idx_11 == 2'h2 |
- _active_active_active_T_274; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_351 = _active_active_active_T_350 ? active_active_oh2_11 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_352 = _active_active_active_T_344 | _active_active_active_T_351; // @[VCommon.scala 108:68]
- wire _active_active_active_T_358 = _active_active_active_T_270 & active_active_idx_11 == 2'h3 |
- _active_active_active_T_274; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_359 = _active_active_active_T_358 ? active_active_oh3_11 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_11 = _active_active_active_T_352 | _active_active_active_T_359; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_63 = f_io_in_bits_3_bits_tin_vu_valid ? active_active_active_11 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_3 = _active_active_T_58 | _active_active_T_63; // @[VAlu.scala 250:74]
- wire [63:0] _active_T_25 = fvalid[3] ? active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_26 = _active_T_19 | _active_T_25; // @[VCmdq.scala 126:90]
- wire [3:0] active_active_active_oh_shiftAmount = f_io_entry_0_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh = 16'h1 << active_active_active_oh_shiftAmount; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo = {3'h0,active_active_active_oh[3],3'h0,active_active_active_oh[2],3'h0,
- active_active_active_oh[1],3'h0,active_active_active_oh[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo = {3'h0,active_active_active_oh[7],3'h0,active_active_active_oh[6],3'h0,
- active_active_active_oh[5],3'h0,active_active_active_oh[4],active_active_active_oh0_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo = {3'h0,active_active_active_oh[11],3'h0,active_active_active_oh[10],3'h0,
- active_active_active_oh[9],3'h0,active_active_active_oh[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0 = {3'h0,active_active_active_oh[15],3'h0,active_active_active_oh[14],3'h0,
- active_active_active_oh[13],3'h0,active_active_active_oh[12],active_active_active_oh0_hi_lo,
- active_active_active_oh0_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo = {2'h0,active_active_active_oh[1],1'h0,2'h0,active_active_active_oh[0],1'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo = {2'h0,active_active_active_oh[3],1'h0,2'h0,active_active_active_oh[2],1'h0
- ,active_active_active_oh1_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo = {2'h0,active_active_active_oh[5],1'h0,2'h0,active_active_active_oh[4],1'h0
- }; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo = {2'h0,active_active_active_oh[7],1'h0,2'h0,active_active_active_oh[6],1'h0,
- active_active_active_oh1_lo_hi_lo,active_active_active_oh1_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo = {2'h0,active_active_active_oh[9],1'h0,2'h0,active_active_active_oh[8],1'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo = {2'h0,active_active_active_oh[11],1'h0,2'h0,active_active_active_oh[10],1'h0
- ,active_active_active_oh1_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo = {2'h0,active_active_active_oh[13],1'h0,2'h0,active_active_active_oh[12]
- ,1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1 = {2'h0,active_active_active_oh[15],1'h0,2'h0,active_active_active_oh[14],1'h0,
- active_active_active_oh1_hi_hi_lo,active_active_active_oh1_hi_lo,active_active_active_oh1_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo = {1'h0,active_active_active_oh[1],2'h0,1'h0,active_active_active_oh[0],2'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo = {1'h0,active_active_active_oh[3],2'h0,1'h0,active_active_active_oh[2],2'h0
- ,active_active_active_oh2_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo = {1'h0,active_active_active_oh[5],2'h0,1'h0,active_active_active_oh[4],2'h0
- }; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo = {1'h0,active_active_active_oh[7],2'h0,1'h0,active_active_active_oh[6],2'h0,
- active_active_active_oh2_lo_hi_lo,active_active_active_oh2_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo = {1'h0,active_active_active_oh[9],2'h0,1'h0,active_active_active_oh[8],2'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo = {1'h0,active_active_active_oh[11],2'h0,1'h0,active_active_active_oh[10],2'h0
- ,active_active_active_oh2_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo = {1'h0,active_active_active_oh[13],2'h0,1'h0,active_active_active_oh[12]
- ,2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2 = {1'h0,active_active_active_oh[15],2'h0,1'h0,active_active_active_oh[14],2'h0,
- active_active_active_oh2_hi_hi_lo,active_active_active_oh2_hi_lo,active_active_active_oh2_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo = {active_active_active_oh[3],3'h0,active_active_active_oh[2],3'h0,
- active_active_active_oh[1],3'h0,active_active_active_oh[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo = {active_active_active_oh[7],3'h0,active_active_active_oh[6],3'h0,
- active_active_active_oh[5],3'h0,active_active_active_oh[4],3'h0,active_active_active_oh3_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo = {active_active_active_oh[11],3'h0,active_active_active_oh[10],3'h0,
- active_active_active_oh[9],3'h0,active_active_active_oh[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3 = {active_active_active_oh[15],3'h0,active_active_active_oh[14],3'h0,
- active_active_active_oh[13],3'h0,active_active_active_oh[12],3'h0,active_active_active_oh3_hi_lo,
- active_active_active_oh3_lo}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx = f_io_entry_0_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T = ~f_io_entry_0_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_4 = f_io_entry_0_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_5 = ~f_io_entry_0_bits_m & active_active_active_idx == 2'h0 | f_io_entry_0_bits_m
- ; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_6 = _active_active_active_active_T_5 ? active_active_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_active_T_12 = _active_active_active_active_T & active_active_active_idx == 2'h1 |
- _active_active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_13 = _active_active_active_active_T_12 ? active_active_active_oh1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_14 = _active_active_active_active_T_6 | _active_active_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_20 = _active_active_active_active_T & active_active_active_idx == 2'h2 |
- _active_active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_21 = _active_active_active_active_T_20 ? active_active_active_oh2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_22 = _active_active_active_active_T_14 | _active_active_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_28 = _active_active_active_active_T & active_active_active_idx == 2'h3 |
- _active_active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_29 = _active_active_active_active_T_28 ? active_active_active_oh3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active = _active_active_active_active_T_22 | _active_active_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_364 = f_io_entry_0_bits_tin_vs_valid ? active_active_active_active : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_1 = f_io_entry_0_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_1 = 16'h1 << active_active_active_oh_shiftAmount_1; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_1 = {3'h0,active_active_active_oh_1[3],3'h0,active_active_active_oh_1[2],3'h0
- ,active_active_active_oh_1[1],3'h0,active_active_active_oh_1[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_1 = {3'h0,active_active_active_oh_1[7],3'h0,active_active_active_oh_1[6],3'h0,
- active_active_active_oh_1[5],3'h0,active_active_active_oh_1[4],active_active_active_oh0_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_1 = {3'h0,active_active_active_oh_1[11],3'h0,active_active_active_oh_1[10],3'h0
- ,active_active_active_oh_1[9],3'h0,active_active_active_oh_1[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_1 = {3'h0,active_active_active_oh_1[15],3'h0,active_active_active_oh_1[14],3'h0,
- active_active_active_oh_1[13],3'h0,active_active_active_oh_1[12],active_active_active_oh0_hi_lo_1,
- active_active_active_oh0_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_1 = {2'h0,active_active_active_oh_1[1],1'h0,2'h0,
- active_active_active_oh_1[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_1 = {2'h0,active_active_active_oh_1[3],1'h0,2'h0,active_active_active_oh_1[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_1 = {2'h0,active_active_active_oh_1[5],1'h0,2'h0,
- active_active_active_oh_1[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_1 = {2'h0,active_active_active_oh_1[7],1'h0,2'h0,active_active_active_oh_1[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_1,active_active_active_oh1_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_1 = {2'h0,active_active_active_oh_1[9],1'h0,2'h0,
- active_active_active_oh_1[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_1 = {2'h0,active_active_active_oh_1[11],1'h0,2'h0,active_active_active_oh_1
- [10],1'h0,active_active_active_oh1_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_1 = {2'h0,active_active_active_oh_1[13],1'h0,2'h0,
- active_active_active_oh_1[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_1 = {2'h0,active_active_active_oh_1[15],1'h0,2'h0,active_active_active_oh_1[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_1,active_active_active_oh1_hi_lo_1,active_active_active_oh1_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_1 = {1'h0,active_active_active_oh_1[1],2'h0,1'h0,
- active_active_active_oh_1[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_1 = {1'h0,active_active_active_oh_1[3],2'h0,1'h0,active_active_active_oh_1[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_1 = {1'h0,active_active_active_oh_1[5],2'h0,1'h0,
- active_active_active_oh_1[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_1 = {1'h0,active_active_active_oh_1[7],2'h0,1'h0,active_active_active_oh_1[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_1,active_active_active_oh2_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_1 = {1'h0,active_active_active_oh_1[9],2'h0,1'h0,
- active_active_active_oh_1[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_1 = {1'h0,active_active_active_oh_1[11],2'h0,1'h0,active_active_active_oh_1
- [10],2'h0,active_active_active_oh2_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_1 = {1'h0,active_active_active_oh_1[13],2'h0,1'h0,
- active_active_active_oh_1[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_1 = {1'h0,active_active_active_oh_1[15],2'h0,1'h0,active_active_active_oh_1[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_1,active_active_active_oh2_hi_lo_1,active_active_active_oh2_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_1 = {active_active_active_oh_1[3],3'h0,active_active_active_oh_1[2],3'h0,
- active_active_active_oh_1[1],3'h0,active_active_active_oh_1[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_1 = {active_active_active_oh_1[7],3'h0,active_active_active_oh_1[6],3'h0,
- active_active_active_oh_1[5],3'h0,active_active_active_oh_1[4],3'h0,active_active_active_oh3_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_1 = {active_active_active_oh_1[11],3'h0,active_active_active_oh_1[10],3'h0,
- active_active_active_oh_1[9],3'h0,active_active_active_oh_1[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_1 = {active_active_active_oh_1[15],3'h0,active_active_active_oh_1[14],3'h0,
- active_active_active_oh_1[13],3'h0,active_active_active_oh_1[12],3'h0,active_active_active_oh3_hi_lo_1,
- active_active_active_oh3_lo_1}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_1 = f_io_entry_0_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_35 = ~f_io_entry_0_bits_m & active_active_active_idx_1 == 2'h0 |
- f_io_entry_0_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_36 = _active_active_active_active_T_35 ? active_active_active_oh0_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_42 = _active_active_active_active_T & active_active_active_idx_1 == 2'h1 |
- _active_active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_43 = _active_active_active_active_T_42 ? active_active_active_oh1_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_44 = _active_active_active_active_T_36 | _active_active_active_active_T_43; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_50 = _active_active_active_active_T & active_active_active_idx_1 == 2'h2 |
- _active_active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_51 = _active_active_active_active_T_50 ? active_active_active_oh2_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_52 = _active_active_active_active_T_44 | _active_active_active_active_T_51; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_58 = _active_active_active_active_T & active_active_active_idx_1 == 2'h3 |
- _active_active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_59 = _active_active_active_active_T_58 ? active_active_active_oh3_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_1 = _active_active_active_active_T_52 | _active_active_active_active_T_59; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_369 = f_io_entry_0_bits_tin_vt_valid ? active_active_active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_370 = _active_active_active_T_364 | _active_active_active_T_369; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_2 = f_io_entry_0_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_2 = 16'h1 << active_active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_2 = {3'h0,active_active_active_oh_2[3],3'h0,active_active_active_oh_2[2],3'h0
- ,active_active_active_oh_2[1],3'h0,active_active_active_oh_2[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_2 = {3'h0,active_active_active_oh_2[7],3'h0,active_active_active_oh_2[6],3'h0,
- active_active_active_oh_2[5],3'h0,active_active_active_oh_2[4],active_active_active_oh0_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_2 = {3'h0,active_active_active_oh_2[11],3'h0,active_active_active_oh_2[10],3'h0
- ,active_active_active_oh_2[9],3'h0,active_active_active_oh_2[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_2 = {3'h0,active_active_active_oh_2[15],3'h0,active_active_active_oh_2[14],3'h0,
- active_active_active_oh_2[13],3'h0,active_active_active_oh_2[12],active_active_active_oh0_hi_lo_2,
- active_active_active_oh0_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_2 = {2'h0,active_active_active_oh_2[1],1'h0,2'h0,
- active_active_active_oh_2[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_2 = {2'h0,active_active_active_oh_2[3],1'h0,2'h0,active_active_active_oh_2[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_2 = {2'h0,active_active_active_oh_2[5],1'h0,2'h0,
- active_active_active_oh_2[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_2 = {2'h0,active_active_active_oh_2[7],1'h0,2'h0,active_active_active_oh_2[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_2,active_active_active_oh1_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_2 = {2'h0,active_active_active_oh_2[9],1'h0,2'h0,
- active_active_active_oh_2[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_2 = {2'h0,active_active_active_oh_2[11],1'h0,2'h0,active_active_active_oh_2
- [10],1'h0,active_active_active_oh1_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_2 = {2'h0,active_active_active_oh_2[13],1'h0,2'h0,
- active_active_active_oh_2[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_2 = {2'h0,active_active_active_oh_2[15],1'h0,2'h0,active_active_active_oh_2[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_2,active_active_active_oh1_hi_lo_2,active_active_active_oh1_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_2 = {1'h0,active_active_active_oh_2[1],2'h0,1'h0,
- active_active_active_oh_2[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_2 = {1'h0,active_active_active_oh_2[3],2'h0,1'h0,active_active_active_oh_2[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_2 = {1'h0,active_active_active_oh_2[5],2'h0,1'h0,
- active_active_active_oh_2[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_2 = {1'h0,active_active_active_oh_2[7],2'h0,1'h0,active_active_active_oh_2[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_2,active_active_active_oh2_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_2 = {1'h0,active_active_active_oh_2[9],2'h0,1'h0,
- active_active_active_oh_2[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_2 = {1'h0,active_active_active_oh_2[11],2'h0,1'h0,active_active_active_oh_2
- [10],2'h0,active_active_active_oh2_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_2 = {1'h0,active_active_active_oh_2[13],2'h0,1'h0,
- active_active_active_oh_2[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_2 = {1'h0,active_active_active_oh_2[15],2'h0,1'h0,active_active_active_oh_2[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_2,active_active_active_oh2_hi_lo_2,active_active_active_oh2_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_2 = {active_active_active_oh_2[3],3'h0,active_active_active_oh_2[2],3'h0,
- active_active_active_oh_2[1],3'h0,active_active_active_oh_2[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_2 = {active_active_active_oh_2[7],3'h0,active_active_active_oh_2[6],3'h0,
- active_active_active_oh_2[5],3'h0,active_active_active_oh_2[4],3'h0,active_active_active_oh3_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_2 = {active_active_active_oh_2[11],3'h0,active_active_active_oh_2[10],3'h0,
- active_active_active_oh_2[9],3'h0,active_active_active_oh_2[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_2 = {active_active_active_oh_2[15],3'h0,active_active_active_oh_2[14],3'h0,
- active_active_active_oh_2[13],3'h0,active_active_active_oh_2[12],3'h0,active_active_active_oh3_hi_lo_2,
- active_active_active_oh3_lo_2}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_2 = f_io_entry_0_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_65 = ~f_io_entry_0_bits_m & active_active_active_idx_2 == 2'h0 |
- f_io_entry_0_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_66 = _active_active_active_active_T_65 ? active_active_active_oh0_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_72 = _active_active_active_active_T & active_active_active_idx_2 == 2'h1 |
- _active_active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_73 = _active_active_active_active_T_72 ? active_active_active_oh1_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_74 = _active_active_active_active_T_66 | _active_active_active_active_T_73; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_80 = _active_active_active_active_T & active_active_active_idx_2 == 2'h2 |
- _active_active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_81 = _active_active_active_active_T_80 ? active_active_active_oh2_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_82 = _active_active_active_active_T_74 | _active_active_active_active_T_81; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_88 = _active_active_active_active_T & active_active_active_idx_2 == 2'h3 |
- _active_active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_89 = _active_active_active_active_T_88 ? active_active_active_oh3_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_2 = _active_active_active_active_T_82 | _active_active_active_active_T_89; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_375 = f_io_entry_0_bits_tin_vu_valid ? active_active_active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_12 = _active_active_active_T_370 | _active_active_active_T_375; // @[VAlu.scala 250:74]
- wire [63:0] active_active_4 = f_io_entry_0_valid ? active_active_active_12 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_3 = f_io_entry_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_3 = 16'h1 << active_active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_3 = {3'h0,active_active_active_oh_3[3],3'h0,active_active_active_oh_3[2],3'h0
- ,active_active_active_oh_3[1],3'h0,active_active_active_oh_3[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_3 = {3'h0,active_active_active_oh_3[7],3'h0,active_active_active_oh_3[6],3'h0,
- active_active_active_oh_3[5],3'h0,active_active_active_oh_3[4],active_active_active_oh0_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_3 = {3'h0,active_active_active_oh_3[11],3'h0,active_active_active_oh_3[10],3'h0
- ,active_active_active_oh_3[9],3'h0,active_active_active_oh_3[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_3 = {3'h0,active_active_active_oh_3[15],3'h0,active_active_active_oh_3[14],3'h0,
- active_active_active_oh_3[13],3'h0,active_active_active_oh_3[12],active_active_active_oh0_hi_lo_3,
- active_active_active_oh0_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_3 = {2'h0,active_active_active_oh_3[1],1'h0,2'h0,
- active_active_active_oh_3[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_3 = {2'h0,active_active_active_oh_3[3],1'h0,2'h0,active_active_active_oh_3[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_3 = {2'h0,active_active_active_oh_3[5],1'h0,2'h0,
- active_active_active_oh_3[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_3 = {2'h0,active_active_active_oh_3[7],1'h0,2'h0,active_active_active_oh_3[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_3,active_active_active_oh1_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_3 = {2'h0,active_active_active_oh_3[9],1'h0,2'h0,
- active_active_active_oh_3[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_3 = {2'h0,active_active_active_oh_3[11],1'h0,2'h0,active_active_active_oh_3
- [10],1'h0,active_active_active_oh1_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_3 = {2'h0,active_active_active_oh_3[13],1'h0,2'h0,
- active_active_active_oh_3[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_3 = {2'h0,active_active_active_oh_3[15],1'h0,2'h0,active_active_active_oh_3[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_3,active_active_active_oh1_hi_lo_3,active_active_active_oh1_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_3 = {1'h0,active_active_active_oh_3[1],2'h0,1'h0,
- active_active_active_oh_3[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_3 = {1'h0,active_active_active_oh_3[3],2'h0,1'h0,active_active_active_oh_3[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_3 = {1'h0,active_active_active_oh_3[5],2'h0,1'h0,
- active_active_active_oh_3[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_3 = {1'h0,active_active_active_oh_3[7],2'h0,1'h0,active_active_active_oh_3[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_3,active_active_active_oh2_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_3 = {1'h0,active_active_active_oh_3[9],2'h0,1'h0,
- active_active_active_oh_3[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_3 = {1'h0,active_active_active_oh_3[11],2'h0,1'h0,active_active_active_oh_3
- [10],2'h0,active_active_active_oh2_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_3 = {1'h0,active_active_active_oh_3[13],2'h0,1'h0,
- active_active_active_oh_3[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_3 = {1'h0,active_active_active_oh_3[15],2'h0,1'h0,active_active_active_oh_3[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_3,active_active_active_oh2_hi_lo_3,active_active_active_oh2_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_3 = {active_active_active_oh_3[3],3'h0,active_active_active_oh_3[2],3'h0,
- active_active_active_oh_3[1],3'h0,active_active_active_oh_3[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_3 = {active_active_active_oh_3[7],3'h0,active_active_active_oh_3[6],3'h0,
- active_active_active_oh_3[5],3'h0,active_active_active_oh_3[4],3'h0,active_active_active_oh3_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_3 = {active_active_active_oh_3[11],3'h0,active_active_active_oh_3[10],3'h0,
- active_active_active_oh_3[9],3'h0,active_active_active_oh_3[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_3 = {active_active_active_oh_3[15],3'h0,active_active_active_oh_3[14],3'h0,
- active_active_active_oh_3[13],3'h0,active_active_active_oh_3[12],3'h0,active_active_active_oh3_hi_lo_3,
- active_active_active_oh3_lo_3}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_3 = f_io_entry_1_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_90 = ~f_io_entry_1_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_94 = f_io_entry_1_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_95 = ~f_io_entry_1_bits_m & active_active_active_idx_3 == 2'h0 |
- f_io_entry_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_96 = _active_active_active_active_T_95 ? active_active_active_oh0_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_102 = _active_active_active_active_T_90 & active_active_active_idx_3 == 2'h1 |
- _active_active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_103 = _active_active_active_active_T_102 ? active_active_active_oh1_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_104 = _active_active_active_active_T_96 |
- _active_active_active_active_T_103; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_110 = _active_active_active_active_T_90 & active_active_active_idx_3 == 2'h2 |
- _active_active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_111 = _active_active_active_active_T_110 ? active_active_active_oh2_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_112 = _active_active_active_active_T_104 |
- _active_active_active_active_T_111; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_118 = _active_active_active_active_T_90 & active_active_active_idx_3 == 2'h3 |
- _active_active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_119 = _active_active_active_active_T_118 ? active_active_active_oh3_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_3 = _active_active_active_active_T_112 | _active_active_active_active_T_119; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_380 = f_io_entry_1_bits_tin_vs_valid ? active_active_active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_4 = f_io_entry_1_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_4 = 16'h1 << active_active_active_oh_shiftAmount_4; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_4 = {3'h0,active_active_active_oh_4[3],3'h0,active_active_active_oh_4[2],3'h0
- ,active_active_active_oh_4[1],3'h0,active_active_active_oh_4[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_4 = {3'h0,active_active_active_oh_4[7],3'h0,active_active_active_oh_4[6],3'h0,
- active_active_active_oh_4[5],3'h0,active_active_active_oh_4[4],active_active_active_oh0_lo_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_4 = {3'h0,active_active_active_oh_4[11],3'h0,active_active_active_oh_4[10],3'h0
- ,active_active_active_oh_4[9],3'h0,active_active_active_oh_4[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_4 = {3'h0,active_active_active_oh_4[15],3'h0,active_active_active_oh_4[14],3'h0,
- active_active_active_oh_4[13],3'h0,active_active_active_oh_4[12],active_active_active_oh0_hi_lo_4,
- active_active_active_oh0_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_4 = {2'h0,active_active_active_oh_4[1],1'h0,2'h0,
- active_active_active_oh_4[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_4 = {2'h0,active_active_active_oh_4[3],1'h0,2'h0,active_active_active_oh_4[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_4 = {2'h0,active_active_active_oh_4[5],1'h0,2'h0,
- active_active_active_oh_4[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_4 = {2'h0,active_active_active_oh_4[7],1'h0,2'h0,active_active_active_oh_4[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_4,active_active_active_oh1_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_4 = {2'h0,active_active_active_oh_4[9],1'h0,2'h0,
- active_active_active_oh_4[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_4 = {2'h0,active_active_active_oh_4[11],1'h0,2'h0,active_active_active_oh_4
- [10],1'h0,active_active_active_oh1_hi_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_4 = {2'h0,active_active_active_oh_4[13],1'h0,2'h0,
- active_active_active_oh_4[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_4 = {2'h0,active_active_active_oh_4[15],1'h0,2'h0,active_active_active_oh_4[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_4,active_active_active_oh1_hi_lo_4,active_active_active_oh1_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_4 = {1'h0,active_active_active_oh_4[1],2'h0,1'h0,
- active_active_active_oh_4[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_4 = {1'h0,active_active_active_oh_4[3],2'h0,1'h0,active_active_active_oh_4[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_4 = {1'h0,active_active_active_oh_4[5],2'h0,1'h0,
- active_active_active_oh_4[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_4 = {1'h0,active_active_active_oh_4[7],2'h0,1'h0,active_active_active_oh_4[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_4,active_active_active_oh2_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_4 = {1'h0,active_active_active_oh_4[9],2'h0,1'h0,
- active_active_active_oh_4[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_4 = {1'h0,active_active_active_oh_4[11],2'h0,1'h0,active_active_active_oh_4
- [10],2'h0,active_active_active_oh2_hi_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_4 = {1'h0,active_active_active_oh_4[13],2'h0,1'h0,
- active_active_active_oh_4[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_4 = {1'h0,active_active_active_oh_4[15],2'h0,1'h0,active_active_active_oh_4[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_4,active_active_active_oh2_hi_lo_4,active_active_active_oh2_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_4 = {active_active_active_oh_4[3],3'h0,active_active_active_oh_4[2],3'h0,
- active_active_active_oh_4[1],3'h0,active_active_active_oh_4[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_4 = {active_active_active_oh_4[7],3'h0,active_active_active_oh_4[6],3'h0,
- active_active_active_oh_4[5],3'h0,active_active_active_oh_4[4],3'h0,active_active_active_oh3_lo_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_4 = {active_active_active_oh_4[11],3'h0,active_active_active_oh_4[10],3'h0,
- active_active_active_oh_4[9],3'h0,active_active_active_oh_4[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_4 = {active_active_active_oh_4[15],3'h0,active_active_active_oh_4[14],3'h0,
- active_active_active_oh_4[13],3'h0,active_active_active_oh_4[12],3'h0,active_active_active_oh3_hi_lo_4,
- active_active_active_oh3_lo_4}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_4 = f_io_entry_1_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_125 = ~f_io_entry_1_bits_m & active_active_active_idx_4 == 2'h0 |
- f_io_entry_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_126 = _active_active_active_active_T_125 ? active_active_active_oh0_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_132 = _active_active_active_active_T_90 & active_active_active_idx_4 == 2'h1 |
- _active_active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_133 = _active_active_active_active_T_132 ? active_active_active_oh1_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_134 = _active_active_active_active_T_126 |
- _active_active_active_active_T_133; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_140 = _active_active_active_active_T_90 & active_active_active_idx_4 == 2'h2 |
- _active_active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_141 = _active_active_active_active_T_140 ? active_active_active_oh2_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_142 = _active_active_active_active_T_134 |
- _active_active_active_active_T_141; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_148 = _active_active_active_active_T_90 & active_active_active_idx_4 == 2'h3 |
- _active_active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_149 = _active_active_active_active_T_148 ? active_active_active_oh3_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_4 = _active_active_active_active_T_142 | _active_active_active_active_T_149; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_385 = f_io_entry_1_bits_tin_vt_valid ? active_active_active_active_4 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_386 = _active_active_active_T_380 | _active_active_active_T_385; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_5 = f_io_entry_1_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_5 = 16'h1 << active_active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_5 = {3'h0,active_active_active_oh_5[3],3'h0,active_active_active_oh_5[2],3'h0
- ,active_active_active_oh_5[1],3'h0,active_active_active_oh_5[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_5 = {3'h0,active_active_active_oh_5[7],3'h0,active_active_active_oh_5[6],3'h0,
- active_active_active_oh_5[5],3'h0,active_active_active_oh_5[4],active_active_active_oh0_lo_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_5 = {3'h0,active_active_active_oh_5[11],3'h0,active_active_active_oh_5[10],3'h0
- ,active_active_active_oh_5[9],3'h0,active_active_active_oh_5[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_5 = {3'h0,active_active_active_oh_5[15],3'h0,active_active_active_oh_5[14],3'h0,
- active_active_active_oh_5[13],3'h0,active_active_active_oh_5[12],active_active_active_oh0_hi_lo_5,
- active_active_active_oh0_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_5 = {2'h0,active_active_active_oh_5[1],1'h0,2'h0,
- active_active_active_oh_5[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_5 = {2'h0,active_active_active_oh_5[3],1'h0,2'h0,active_active_active_oh_5[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_5 = {2'h0,active_active_active_oh_5[5],1'h0,2'h0,
- active_active_active_oh_5[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_5 = {2'h0,active_active_active_oh_5[7],1'h0,2'h0,active_active_active_oh_5[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_5,active_active_active_oh1_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_5 = {2'h0,active_active_active_oh_5[9],1'h0,2'h0,
- active_active_active_oh_5[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_5 = {2'h0,active_active_active_oh_5[11],1'h0,2'h0,active_active_active_oh_5
- [10],1'h0,active_active_active_oh1_hi_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_5 = {2'h0,active_active_active_oh_5[13],1'h0,2'h0,
- active_active_active_oh_5[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_5 = {2'h0,active_active_active_oh_5[15],1'h0,2'h0,active_active_active_oh_5[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_5,active_active_active_oh1_hi_lo_5,active_active_active_oh1_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_5 = {1'h0,active_active_active_oh_5[1],2'h0,1'h0,
- active_active_active_oh_5[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_5 = {1'h0,active_active_active_oh_5[3],2'h0,1'h0,active_active_active_oh_5[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_5 = {1'h0,active_active_active_oh_5[5],2'h0,1'h0,
- active_active_active_oh_5[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_5 = {1'h0,active_active_active_oh_5[7],2'h0,1'h0,active_active_active_oh_5[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_5,active_active_active_oh2_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_5 = {1'h0,active_active_active_oh_5[9],2'h0,1'h0,
- active_active_active_oh_5[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_5 = {1'h0,active_active_active_oh_5[11],2'h0,1'h0,active_active_active_oh_5
- [10],2'h0,active_active_active_oh2_hi_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_5 = {1'h0,active_active_active_oh_5[13],2'h0,1'h0,
- active_active_active_oh_5[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_5 = {1'h0,active_active_active_oh_5[15],2'h0,1'h0,active_active_active_oh_5[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_5,active_active_active_oh2_hi_lo_5,active_active_active_oh2_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_5 = {active_active_active_oh_5[3],3'h0,active_active_active_oh_5[2],3'h0,
- active_active_active_oh_5[1],3'h0,active_active_active_oh_5[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_5 = {active_active_active_oh_5[7],3'h0,active_active_active_oh_5[6],3'h0,
- active_active_active_oh_5[5],3'h0,active_active_active_oh_5[4],3'h0,active_active_active_oh3_lo_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_5 = {active_active_active_oh_5[11],3'h0,active_active_active_oh_5[10],3'h0,
- active_active_active_oh_5[9],3'h0,active_active_active_oh_5[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_5 = {active_active_active_oh_5[15],3'h0,active_active_active_oh_5[14],3'h0,
- active_active_active_oh_5[13],3'h0,active_active_active_oh_5[12],3'h0,active_active_active_oh3_hi_lo_5,
- active_active_active_oh3_lo_5}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_5 = f_io_entry_1_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_155 = ~f_io_entry_1_bits_m & active_active_active_idx_5 == 2'h0 |
- f_io_entry_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_156 = _active_active_active_active_T_155 ? active_active_active_oh0_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_162 = _active_active_active_active_T_90 & active_active_active_idx_5 == 2'h1 |
- _active_active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_163 = _active_active_active_active_T_162 ? active_active_active_oh1_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_164 = _active_active_active_active_T_156 |
- _active_active_active_active_T_163; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_170 = _active_active_active_active_T_90 & active_active_active_idx_5 == 2'h2 |
- _active_active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_171 = _active_active_active_active_T_170 ? active_active_active_oh2_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_172 = _active_active_active_active_T_164 |
- _active_active_active_active_T_171; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_178 = _active_active_active_active_T_90 & active_active_active_idx_5 == 2'h3 |
- _active_active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_179 = _active_active_active_active_T_178 ? active_active_active_oh3_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_5 = _active_active_active_active_T_172 | _active_active_active_active_T_179; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_391 = f_io_entry_1_bits_tin_vu_valid ? active_active_active_active_5 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_13 = _active_active_active_T_386 | _active_active_active_T_391; // @[VAlu.scala 250:74]
- wire [63:0] active_active_5 = f_io_entry_1_valid ? active_active_active_13 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_28 = active_active_4 | active_active_5; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_6 = f_io_entry_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_6 = 16'h1 << active_active_active_oh_shiftAmount_6; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_6 = {3'h0,active_active_active_oh_6[3],3'h0,active_active_active_oh_6[2],3'h0
- ,active_active_active_oh_6[1],3'h0,active_active_active_oh_6[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_6 = {3'h0,active_active_active_oh_6[7],3'h0,active_active_active_oh_6[6],3'h0,
- active_active_active_oh_6[5],3'h0,active_active_active_oh_6[4],active_active_active_oh0_lo_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_6 = {3'h0,active_active_active_oh_6[11],3'h0,active_active_active_oh_6[10],3'h0
- ,active_active_active_oh_6[9],3'h0,active_active_active_oh_6[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_6 = {3'h0,active_active_active_oh_6[15],3'h0,active_active_active_oh_6[14],3'h0,
- active_active_active_oh_6[13],3'h0,active_active_active_oh_6[12],active_active_active_oh0_hi_lo_6,
- active_active_active_oh0_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_6 = {2'h0,active_active_active_oh_6[1],1'h0,2'h0,
- active_active_active_oh_6[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_6 = {2'h0,active_active_active_oh_6[3],1'h0,2'h0,active_active_active_oh_6[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_6 = {2'h0,active_active_active_oh_6[5],1'h0,2'h0,
- active_active_active_oh_6[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_6 = {2'h0,active_active_active_oh_6[7],1'h0,2'h0,active_active_active_oh_6[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_6,active_active_active_oh1_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_6 = {2'h0,active_active_active_oh_6[9],1'h0,2'h0,
- active_active_active_oh_6[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_6 = {2'h0,active_active_active_oh_6[11],1'h0,2'h0,active_active_active_oh_6
- [10],1'h0,active_active_active_oh1_hi_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_6 = {2'h0,active_active_active_oh_6[13],1'h0,2'h0,
- active_active_active_oh_6[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_6 = {2'h0,active_active_active_oh_6[15],1'h0,2'h0,active_active_active_oh_6[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_6,active_active_active_oh1_hi_lo_6,active_active_active_oh1_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_6 = {1'h0,active_active_active_oh_6[1],2'h0,1'h0,
- active_active_active_oh_6[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_6 = {1'h0,active_active_active_oh_6[3],2'h0,1'h0,active_active_active_oh_6[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_6 = {1'h0,active_active_active_oh_6[5],2'h0,1'h0,
- active_active_active_oh_6[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_6 = {1'h0,active_active_active_oh_6[7],2'h0,1'h0,active_active_active_oh_6[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_6,active_active_active_oh2_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_6 = {1'h0,active_active_active_oh_6[9],2'h0,1'h0,
- active_active_active_oh_6[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_6 = {1'h0,active_active_active_oh_6[11],2'h0,1'h0,active_active_active_oh_6
- [10],2'h0,active_active_active_oh2_hi_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_6 = {1'h0,active_active_active_oh_6[13],2'h0,1'h0,
- active_active_active_oh_6[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_6 = {1'h0,active_active_active_oh_6[15],2'h0,1'h0,active_active_active_oh_6[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_6,active_active_active_oh2_hi_lo_6,active_active_active_oh2_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_6 = {active_active_active_oh_6[3],3'h0,active_active_active_oh_6[2],3'h0,
- active_active_active_oh_6[1],3'h0,active_active_active_oh_6[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_6 = {active_active_active_oh_6[7],3'h0,active_active_active_oh_6[6],3'h0,
- active_active_active_oh_6[5],3'h0,active_active_active_oh_6[4],3'h0,active_active_active_oh3_lo_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_6 = {active_active_active_oh_6[11],3'h0,active_active_active_oh_6[10],3'h0,
- active_active_active_oh_6[9],3'h0,active_active_active_oh_6[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_6 = {active_active_active_oh_6[15],3'h0,active_active_active_oh_6[14],3'h0,
- active_active_active_oh_6[13],3'h0,active_active_active_oh_6[12],3'h0,active_active_active_oh3_hi_lo_6,
- active_active_active_oh3_lo_6}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_6 = f_io_entry_2_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_180 = ~f_io_entry_2_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_184 = f_io_entry_2_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_185 = ~f_io_entry_2_bits_m & active_active_active_idx_6 == 2'h0 |
- f_io_entry_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_186 = _active_active_active_active_T_185 ? active_active_active_oh0_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_192 = _active_active_active_active_T_180 & active_active_active_idx_6 == 2'h1 |
- _active_active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_193 = _active_active_active_active_T_192 ? active_active_active_oh1_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_194 = _active_active_active_active_T_186 |
- _active_active_active_active_T_193; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_200 = _active_active_active_active_T_180 & active_active_active_idx_6 == 2'h2 |
- _active_active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_201 = _active_active_active_active_T_200 ? active_active_active_oh2_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_202 = _active_active_active_active_T_194 |
- _active_active_active_active_T_201; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_208 = _active_active_active_active_T_180 & active_active_active_idx_6 == 2'h3 |
- _active_active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_209 = _active_active_active_active_T_208 ? active_active_active_oh3_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_6 = _active_active_active_active_T_202 | _active_active_active_active_T_209; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_396 = f_io_entry_2_bits_tin_vs_valid ? active_active_active_active_6 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_7 = f_io_entry_2_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_7 = 16'h1 << active_active_active_oh_shiftAmount_7; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_7 = {3'h0,active_active_active_oh_7[3],3'h0,active_active_active_oh_7[2],3'h0
- ,active_active_active_oh_7[1],3'h0,active_active_active_oh_7[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_7 = {3'h0,active_active_active_oh_7[7],3'h0,active_active_active_oh_7[6],3'h0,
- active_active_active_oh_7[5],3'h0,active_active_active_oh_7[4],active_active_active_oh0_lo_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_7 = {3'h0,active_active_active_oh_7[11],3'h0,active_active_active_oh_7[10],3'h0
- ,active_active_active_oh_7[9],3'h0,active_active_active_oh_7[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_7 = {3'h0,active_active_active_oh_7[15],3'h0,active_active_active_oh_7[14],3'h0,
- active_active_active_oh_7[13],3'h0,active_active_active_oh_7[12],active_active_active_oh0_hi_lo_7,
- active_active_active_oh0_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_7 = {2'h0,active_active_active_oh_7[1],1'h0,2'h0,
- active_active_active_oh_7[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_7 = {2'h0,active_active_active_oh_7[3],1'h0,2'h0,active_active_active_oh_7[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_7 = {2'h0,active_active_active_oh_7[5],1'h0,2'h0,
- active_active_active_oh_7[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_7 = {2'h0,active_active_active_oh_7[7],1'h0,2'h0,active_active_active_oh_7[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_7,active_active_active_oh1_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_7 = {2'h0,active_active_active_oh_7[9],1'h0,2'h0,
- active_active_active_oh_7[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_7 = {2'h0,active_active_active_oh_7[11],1'h0,2'h0,active_active_active_oh_7
- [10],1'h0,active_active_active_oh1_hi_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_7 = {2'h0,active_active_active_oh_7[13],1'h0,2'h0,
- active_active_active_oh_7[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_7 = {2'h0,active_active_active_oh_7[15],1'h0,2'h0,active_active_active_oh_7[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_7,active_active_active_oh1_hi_lo_7,active_active_active_oh1_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_7 = {1'h0,active_active_active_oh_7[1],2'h0,1'h0,
- active_active_active_oh_7[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_7 = {1'h0,active_active_active_oh_7[3],2'h0,1'h0,active_active_active_oh_7[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_7 = {1'h0,active_active_active_oh_7[5],2'h0,1'h0,
- active_active_active_oh_7[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_7 = {1'h0,active_active_active_oh_7[7],2'h0,1'h0,active_active_active_oh_7[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_7,active_active_active_oh2_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_7 = {1'h0,active_active_active_oh_7[9],2'h0,1'h0,
- active_active_active_oh_7[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_7 = {1'h0,active_active_active_oh_7[11],2'h0,1'h0,active_active_active_oh_7
- [10],2'h0,active_active_active_oh2_hi_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_7 = {1'h0,active_active_active_oh_7[13],2'h0,1'h0,
- active_active_active_oh_7[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_7 = {1'h0,active_active_active_oh_7[15],2'h0,1'h0,active_active_active_oh_7[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_7,active_active_active_oh2_hi_lo_7,active_active_active_oh2_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_7 = {active_active_active_oh_7[3],3'h0,active_active_active_oh_7[2],3'h0,
- active_active_active_oh_7[1],3'h0,active_active_active_oh_7[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_7 = {active_active_active_oh_7[7],3'h0,active_active_active_oh_7[6],3'h0,
- active_active_active_oh_7[5],3'h0,active_active_active_oh_7[4],3'h0,active_active_active_oh3_lo_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_7 = {active_active_active_oh_7[11],3'h0,active_active_active_oh_7[10],3'h0,
- active_active_active_oh_7[9],3'h0,active_active_active_oh_7[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_7 = {active_active_active_oh_7[15],3'h0,active_active_active_oh_7[14],3'h0,
- active_active_active_oh_7[13],3'h0,active_active_active_oh_7[12],3'h0,active_active_active_oh3_hi_lo_7,
- active_active_active_oh3_lo_7}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_7 = f_io_entry_2_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_215 = ~f_io_entry_2_bits_m & active_active_active_idx_7 == 2'h0 |
- f_io_entry_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_216 = _active_active_active_active_T_215 ? active_active_active_oh0_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_222 = _active_active_active_active_T_180 & active_active_active_idx_7 == 2'h1 |
- _active_active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_223 = _active_active_active_active_T_222 ? active_active_active_oh1_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_224 = _active_active_active_active_T_216 |
- _active_active_active_active_T_223; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_230 = _active_active_active_active_T_180 & active_active_active_idx_7 == 2'h2 |
- _active_active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_231 = _active_active_active_active_T_230 ? active_active_active_oh2_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_232 = _active_active_active_active_T_224 |
- _active_active_active_active_T_231; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_238 = _active_active_active_active_T_180 & active_active_active_idx_7 == 2'h3 |
- _active_active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_239 = _active_active_active_active_T_238 ? active_active_active_oh3_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_7 = _active_active_active_active_T_232 | _active_active_active_active_T_239; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_401 = f_io_entry_2_bits_tin_vt_valid ? active_active_active_active_7 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_402 = _active_active_active_T_396 | _active_active_active_T_401; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_8 = f_io_entry_2_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_8 = 16'h1 << active_active_active_oh_shiftAmount_8; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_8 = {3'h0,active_active_active_oh_8[3],3'h0,active_active_active_oh_8[2],3'h0
- ,active_active_active_oh_8[1],3'h0,active_active_active_oh_8[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_8 = {3'h0,active_active_active_oh_8[7],3'h0,active_active_active_oh_8[6],3'h0,
- active_active_active_oh_8[5],3'h0,active_active_active_oh_8[4],active_active_active_oh0_lo_lo_8}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_8 = {3'h0,active_active_active_oh_8[11],3'h0,active_active_active_oh_8[10],3'h0
- ,active_active_active_oh_8[9],3'h0,active_active_active_oh_8[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_8 = {3'h0,active_active_active_oh_8[15],3'h0,active_active_active_oh_8[14],3'h0,
- active_active_active_oh_8[13],3'h0,active_active_active_oh_8[12],active_active_active_oh0_hi_lo_8,
- active_active_active_oh0_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_8 = {2'h0,active_active_active_oh_8[1],1'h0,2'h0,
- active_active_active_oh_8[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_8 = {2'h0,active_active_active_oh_8[3],1'h0,2'h0,active_active_active_oh_8[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_8 = {2'h0,active_active_active_oh_8[5],1'h0,2'h0,
- active_active_active_oh_8[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_8 = {2'h0,active_active_active_oh_8[7],1'h0,2'h0,active_active_active_oh_8[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_8,active_active_active_oh1_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_8 = {2'h0,active_active_active_oh_8[9],1'h0,2'h0,
- active_active_active_oh_8[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_8 = {2'h0,active_active_active_oh_8[11],1'h0,2'h0,active_active_active_oh_8
- [10],1'h0,active_active_active_oh1_hi_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_8 = {2'h0,active_active_active_oh_8[13],1'h0,2'h0,
- active_active_active_oh_8[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_8 = {2'h0,active_active_active_oh_8[15],1'h0,2'h0,active_active_active_oh_8[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_8,active_active_active_oh1_hi_lo_8,active_active_active_oh1_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_8 = {1'h0,active_active_active_oh_8[1],2'h0,1'h0,
- active_active_active_oh_8[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_8 = {1'h0,active_active_active_oh_8[3],2'h0,1'h0,active_active_active_oh_8[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_8 = {1'h0,active_active_active_oh_8[5],2'h0,1'h0,
- active_active_active_oh_8[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_8 = {1'h0,active_active_active_oh_8[7],2'h0,1'h0,active_active_active_oh_8[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_8,active_active_active_oh2_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_8 = {1'h0,active_active_active_oh_8[9],2'h0,1'h0,
- active_active_active_oh_8[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_8 = {1'h0,active_active_active_oh_8[11],2'h0,1'h0,active_active_active_oh_8
- [10],2'h0,active_active_active_oh2_hi_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_8 = {1'h0,active_active_active_oh_8[13],2'h0,1'h0,
- active_active_active_oh_8[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_8 = {1'h0,active_active_active_oh_8[15],2'h0,1'h0,active_active_active_oh_8[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_8,active_active_active_oh2_hi_lo_8,active_active_active_oh2_lo_8}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_8 = {active_active_active_oh_8[3],3'h0,active_active_active_oh_8[2],3'h0,
- active_active_active_oh_8[1],3'h0,active_active_active_oh_8[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_8 = {active_active_active_oh_8[7],3'h0,active_active_active_oh_8[6],3'h0,
- active_active_active_oh_8[5],3'h0,active_active_active_oh_8[4],3'h0,active_active_active_oh3_lo_lo_8}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_8 = {active_active_active_oh_8[11],3'h0,active_active_active_oh_8[10],3'h0,
- active_active_active_oh_8[9],3'h0,active_active_active_oh_8[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_8 = {active_active_active_oh_8[15],3'h0,active_active_active_oh_8[14],3'h0,
- active_active_active_oh_8[13],3'h0,active_active_active_oh_8[12],3'h0,active_active_active_oh3_hi_lo_8,
- active_active_active_oh3_lo_8}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_8 = f_io_entry_2_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_245 = ~f_io_entry_2_bits_m & active_active_active_idx_8 == 2'h0 |
- f_io_entry_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_246 = _active_active_active_active_T_245 ? active_active_active_oh0_8 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_252 = _active_active_active_active_T_180 & active_active_active_idx_8 == 2'h1 |
- _active_active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_253 = _active_active_active_active_T_252 ? active_active_active_oh1_8 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_254 = _active_active_active_active_T_246 |
- _active_active_active_active_T_253; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_260 = _active_active_active_active_T_180 & active_active_active_idx_8 == 2'h2 |
- _active_active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_261 = _active_active_active_active_T_260 ? active_active_active_oh2_8 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_262 = _active_active_active_active_T_254 |
- _active_active_active_active_T_261; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_268 = _active_active_active_active_T_180 & active_active_active_idx_8 == 2'h3 |
- _active_active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_269 = _active_active_active_active_T_268 ? active_active_active_oh3_8 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_8 = _active_active_active_active_T_262 | _active_active_active_active_T_269; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_407 = f_io_entry_2_bits_tin_vu_valid ? active_active_active_active_8 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_14 = _active_active_active_T_402 | _active_active_active_T_407; // @[VAlu.scala 250:74]
- wire [63:0] active_active_6 = f_io_entry_2_valid ? active_active_active_14 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_29 = _active_T_28 | active_active_6; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_9 = f_io_entry_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_9 = 16'h1 << active_active_active_oh_shiftAmount_9; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_9 = {3'h0,active_active_active_oh_9[3],3'h0,active_active_active_oh_9[2],3'h0
- ,active_active_active_oh_9[1],3'h0,active_active_active_oh_9[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_9 = {3'h0,active_active_active_oh_9[7],3'h0,active_active_active_oh_9[6],3'h0,
- active_active_active_oh_9[5],3'h0,active_active_active_oh_9[4],active_active_active_oh0_lo_lo_9}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_9 = {3'h0,active_active_active_oh_9[11],3'h0,active_active_active_oh_9[10],3'h0
- ,active_active_active_oh_9[9],3'h0,active_active_active_oh_9[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_9 = {3'h0,active_active_active_oh_9[15],3'h0,active_active_active_oh_9[14],3'h0,
- active_active_active_oh_9[13],3'h0,active_active_active_oh_9[12],active_active_active_oh0_hi_lo_9,
- active_active_active_oh0_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_9 = {2'h0,active_active_active_oh_9[1],1'h0,2'h0,
- active_active_active_oh_9[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_9 = {2'h0,active_active_active_oh_9[3],1'h0,2'h0,active_active_active_oh_9[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_9 = {2'h0,active_active_active_oh_9[5],1'h0,2'h0,
- active_active_active_oh_9[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_9 = {2'h0,active_active_active_oh_9[7],1'h0,2'h0,active_active_active_oh_9[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_9,active_active_active_oh1_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_9 = {2'h0,active_active_active_oh_9[9],1'h0,2'h0,
- active_active_active_oh_9[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_9 = {2'h0,active_active_active_oh_9[11],1'h0,2'h0,active_active_active_oh_9
- [10],1'h0,active_active_active_oh1_hi_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_9 = {2'h0,active_active_active_oh_9[13],1'h0,2'h0,
- active_active_active_oh_9[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_9 = {2'h0,active_active_active_oh_9[15],1'h0,2'h0,active_active_active_oh_9[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_9,active_active_active_oh1_hi_lo_9,active_active_active_oh1_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_9 = {1'h0,active_active_active_oh_9[1],2'h0,1'h0,
- active_active_active_oh_9[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_9 = {1'h0,active_active_active_oh_9[3],2'h0,1'h0,active_active_active_oh_9[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_9 = {1'h0,active_active_active_oh_9[5],2'h0,1'h0,
- active_active_active_oh_9[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_9 = {1'h0,active_active_active_oh_9[7],2'h0,1'h0,active_active_active_oh_9[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_9,active_active_active_oh2_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_9 = {1'h0,active_active_active_oh_9[9],2'h0,1'h0,
- active_active_active_oh_9[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_9 = {1'h0,active_active_active_oh_9[11],2'h0,1'h0,active_active_active_oh_9
- [10],2'h0,active_active_active_oh2_hi_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_9 = {1'h0,active_active_active_oh_9[13],2'h0,1'h0,
- active_active_active_oh_9[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_9 = {1'h0,active_active_active_oh_9[15],2'h0,1'h0,active_active_active_oh_9[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_9,active_active_active_oh2_hi_lo_9,active_active_active_oh2_lo_9}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_9 = {active_active_active_oh_9[3],3'h0,active_active_active_oh_9[2],3'h0,
- active_active_active_oh_9[1],3'h0,active_active_active_oh_9[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_9 = {active_active_active_oh_9[7],3'h0,active_active_active_oh_9[6],3'h0,
- active_active_active_oh_9[5],3'h0,active_active_active_oh_9[4],3'h0,active_active_active_oh3_lo_lo_9}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_9 = {active_active_active_oh_9[11],3'h0,active_active_active_oh_9[10],3'h0,
- active_active_active_oh_9[9],3'h0,active_active_active_oh_9[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_9 = {active_active_active_oh_9[15],3'h0,active_active_active_oh_9[14],3'h0,
- active_active_active_oh_9[13],3'h0,active_active_active_oh_9[12],3'h0,active_active_active_oh3_hi_lo_9,
- active_active_active_oh3_lo_9}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_9 = f_io_entry_3_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_270 = ~f_io_entry_3_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_274 = f_io_entry_3_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_275 = ~f_io_entry_3_bits_m & active_active_active_idx_9 == 2'h0 |
- f_io_entry_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_276 = _active_active_active_active_T_275 ? active_active_active_oh0_9 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_282 = _active_active_active_active_T_270 & active_active_active_idx_9 == 2'h1 |
- _active_active_active_active_T_274; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_283 = _active_active_active_active_T_282 ? active_active_active_oh1_9 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_284 = _active_active_active_active_T_276 |
- _active_active_active_active_T_283; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_290 = _active_active_active_active_T_270 & active_active_active_idx_9 == 2'h2 |
- _active_active_active_active_T_274; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_291 = _active_active_active_active_T_290 ? active_active_active_oh2_9 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_292 = _active_active_active_active_T_284 |
- _active_active_active_active_T_291; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_298 = _active_active_active_active_T_270 & active_active_active_idx_9 == 2'h3 |
- _active_active_active_active_T_274; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_299 = _active_active_active_active_T_298 ? active_active_active_oh3_9 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_9 = _active_active_active_active_T_292 | _active_active_active_active_T_299; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_412 = f_io_entry_3_bits_tin_vs_valid ? active_active_active_active_9 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_10 = f_io_entry_3_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_10 = 16'h1 << active_active_active_oh_shiftAmount_10; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_10 = {3'h0,active_active_active_oh_10[3],3'h0,active_active_active_oh_10[2]
- ,3'h0,active_active_active_oh_10[1],3'h0,active_active_active_oh_10[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_10 = {3'h0,active_active_active_oh_10[7],3'h0,active_active_active_oh_10[6],3'h0
- ,active_active_active_oh_10[5],3'h0,active_active_active_oh_10[4],active_active_active_oh0_lo_lo_10}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_10 = {3'h0,active_active_active_oh_10[11],3'h0,active_active_active_oh_10[
- 10],3'h0,active_active_active_oh_10[9],3'h0,active_active_active_oh_10[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_10 = {3'h0,active_active_active_oh_10[15],3'h0,active_active_active_oh_10[14],3'h0
- ,active_active_active_oh_10[13],3'h0,active_active_active_oh_10[12],active_active_active_oh0_hi_lo_10,
- active_active_active_oh0_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_10 = {2'h0,active_active_active_oh_10[1],1'h0,2'h0,
- active_active_active_oh_10[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_10 = {2'h0,active_active_active_oh_10[3],1'h0,2'h0,
- active_active_active_oh_10[2],1'h0,active_active_active_oh1_lo_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_10 = {2'h0,active_active_active_oh_10[5],1'h0,2'h0,
- active_active_active_oh_10[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_10 = {2'h0,active_active_active_oh_10[7],1'h0,2'h0,active_active_active_oh_10[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_10,active_active_active_oh1_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_10 = {2'h0,active_active_active_oh_10[9],1'h0,2'h0,
- active_active_active_oh_10[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_10 = {2'h0,active_active_active_oh_10[11],1'h0,2'h0,
- active_active_active_oh_10[10],1'h0,active_active_active_oh1_hi_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_10 = {2'h0,active_active_active_oh_10[13],1'h0,2'h0,
- active_active_active_oh_10[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_10 = {2'h0,active_active_active_oh_10[15],1'h0,2'h0,active_active_active_oh_10[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_10,active_active_active_oh1_hi_lo_10,active_active_active_oh1_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_10 = {1'h0,active_active_active_oh_10[1],2'h0,1'h0,
- active_active_active_oh_10[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_10 = {1'h0,active_active_active_oh_10[3],2'h0,1'h0,
- active_active_active_oh_10[2],2'h0,active_active_active_oh2_lo_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_10 = {1'h0,active_active_active_oh_10[5],2'h0,1'h0,
- active_active_active_oh_10[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_10 = {1'h0,active_active_active_oh_10[7],2'h0,1'h0,active_active_active_oh_10[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_10,active_active_active_oh2_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_10 = {1'h0,active_active_active_oh_10[9],2'h0,1'h0,
- active_active_active_oh_10[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_10 = {1'h0,active_active_active_oh_10[11],2'h0,1'h0,
- active_active_active_oh_10[10],2'h0,active_active_active_oh2_hi_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_10 = {1'h0,active_active_active_oh_10[13],2'h0,1'h0,
- active_active_active_oh_10[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_10 = {1'h0,active_active_active_oh_10[15],2'h0,1'h0,active_active_active_oh_10[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_10,active_active_active_oh2_hi_lo_10,active_active_active_oh2_lo_10}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_10 = {active_active_active_oh_10[3],3'h0,active_active_active_oh_10[2],3'h0
- ,active_active_active_oh_10[1],3'h0,active_active_active_oh_10[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_10 = {active_active_active_oh_10[7],3'h0,active_active_active_oh_10[6],3'h0,
- active_active_active_oh_10[5],3'h0,active_active_active_oh_10[4],3'h0,active_active_active_oh3_lo_lo_10}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_10 = {active_active_active_oh_10[11],3'h0,active_active_active_oh_10[10],3'h0
- ,active_active_active_oh_10[9],3'h0,active_active_active_oh_10[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_10 = {active_active_active_oh_10[15],3'h0,active_active_active_oh_10[14],3'h0,
- active_active_active_oh_10[13],3'h0,active_active_active_oh_10[12],3'h0,active_active_active_oh3_hi_lo_10,
- active_active_active_oh3_lo_10}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_10 = f_io_entry_3_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_305 = ~f_io_entry_3_bits_m & active_active_active_idx_10 == 2'h0 |
- f_io_entry_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_306 = _active_active_active_active_T_305 ? active_active_active_oh0_10 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_312 = _active_active_active_active_T_270 & active_active_active_idx_10 == 2'h1 |
- _active_active_active_active_T_274; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_313 = _active_active_active_active_T_312 ? active_active_active_oh1_10 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_314 = _active_active_active_active_T_306 |
- _active_active_active_active_T_313; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_320 = _active_active_active_active_T_270 & active_active_active_idx_10 == 2'h2 |
- _active_active_active_active_T_274; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_321 = _active_active_active_active_T_320 ? active_active_active_oh2_10 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_322 = _active_active_active_active_T_314 |
- _active_active_active_active_T_321; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_328 = _active_active_active_active_T_270 & active_active_active_idx_10 == 2'h3 |
- _active_active_active_active_T_274; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_329 = _active_active_active_active_T_328 ? active_active_active_oh3_10 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_10 = _active_active_active_active_T_322 | _active_active_active_active_T_329; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_417 = f_io_entry_3_bits_tin_vt_valid ? active_active_active_active_10 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_418 = _active_active_active_T_412 | _active_active_active_T_417; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_11 = f_io_entry_3_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_11 = 16'h1 << active_active_active_oh_shiftAmount_11; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_11 = {3'h0,active_active_active_oh_11[3],3'h0,active_active_active_oh_11[2]
- ,3'h0,active_active_active_oh_11[1],3'h0,active_active_active_oh_11[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_11 = {3'h0,active_active_active_oh_11[7],3'h0,active_active_active_oh_11[6],3'h0
- ,active_active_active_oh_11[5],3'h0,active_active_active_oh_11[4],active_active_active_oh0_lo_lo_11}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_11 = {3'h0,active_active_active_oh_11[11],3'h0,active_active_active_oh_11[
- 10],3'h0,active_active_active_oh_11[9],3'h0,active_active_active_oh_11[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_11 = {3'h0,active_active_active_oh_11[15],3'h0,active_active_active_oh_11[14],3'h0
- ,active_active_active_oh_11[13],3'h0,active_active_active_oh_11[12],active_active_active_oh0_hi_lo_11,
- active_active_active_oh0_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_11 = {2'h0,active_active_active_oh_11[1],1'h0,2'h0,
- active_active_active_oh_11[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_11 = {2'h0,active_active_active_oh_11[3],1'h0,2'h0,
- active_active_active_oh_11[2],1'h0,active_active_active_oh1_lo_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_11 = {2'h0,active_active_active_oh_11[5],1'h0,2'h0,
- active_active_active_oh_11[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_11 = {2'h0,active_active_active_oh_11[7],1'h0,2'h0,active_active_active_oh_11[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_11,active_active_active_oh1_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_11 = {2'h0,active_active_active_oh_11[9],1'h0,2'h0,
- active_active_active_oh_11[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_11 = {2'h0,active_active_active_oh_11[11],1'h0,2'h0,
- active_active_active_oh_11[10],1'h0,active_active_active_oh1_hi_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_11 = {2'h0,active_active_active_oh_11[13],1'h0,2'h0,
- active_active_active_oh_11[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_11 = {2'h0,active_active_active_oh_11[15],1'h0,2'h0,active_active_active_oh_11[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_11,active_active_active_oh1_hi_lo_11,active_active_active_oh1_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_11 = {1'h0,active_active_active_oh_11[1],2'h0,1'h0,
- active_active_active_oh_11[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_11 = {1'h0,active_active_active_oh_11[3],2'h0,1'h0,
- active_active_active_oh_11[2],2'h0,active_active_active_oh2_lo_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_11 = {1'h0,active_active_active_oh_11[5],2'h0,1'h0,
- active_active_active_oh_11[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_11 = {1'h0,active_active_active_oh_11[7],2'h0,1'h0,active_active_active_oh_11[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_11,active_active_active_oh2_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_11 = {1'h0,active_active_active_oh_11[9],2'h0,1'h0,
- active_active_active_oh_11[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_11 = {1'h0,active_active_active_oh_11[11],2'h0,1'h0,
- active_active_active_oh_11[10],2'h0,active_active_active_oh2_hi_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_11 = {1'h0,active_active_active_oh_11[13],2'h0,1'h0,
- active_active_active_oh_11[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_11 = {1'h0,active_active_active_oh_11[15],2'h0,1'h0,active_active_active_oh_11[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_11,active_active_active_oh2_hi_lo_11,active_active_active_oh2_lo_11}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_11 = {active_active_active_oh_11[3],3'h0,active_active_active_oh_11[2],3'h0
- ,active_active_active_oh_11[1],3'h0,active_active_active_oh_11[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_11 = {active_active_active_oh_11[7],3'h0,active_active_active_oh_11[6],3'h0,
- active_active_active_oh_11[5],3'h0,active_active_active_oh_11[4],3'h0,active_active_active_oh3_lo_lo_11}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_11 = {active_active_active_oh_11[11],3'h0,active_active_active_oh_11[10],3'h0
- ,active_active_active_oh_11[9],3'h0,active_active_active_oh_11[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_11 = {active_active_active_oh_11[15],3'h0,active_active_active_oh_11[14],3'h0,
- active_active_active_oh_11[13],3'h0,active_active_active_oh_11[12],3'h0,active_active_active_oh3_hi_lo_11,
- active_active_active_oh3_lo_11}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_11 = f_io_entry_3_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_335 = ~f_io_entry_3_bits_m & active_active_active_idx_11 == 2'h0 |
- f_io_entry_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_336 = _active_active_active_active_T_335 ? active_active_active_oh0_11 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_342 = _active_active_active_active_T_270 & active_active_active_idx_11 == 2'h1 |
- _active_active_active_active_T_274; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_343 = _active_active_active_active_T_342 ? active_active_active_oh1_11 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_344 = _active_active_active_active_T_336 |
- _active_active_active_active_T_343; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_350 = _active_active_active_active_T_270 & active_active_active_idx_11 == 2'h2 |
- _active_active_active_active_T_274; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_351 = _active_active_active_active_T_350 ? active_active_active_oh2_11 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_352 = _active_active_active_active_T_344 |
- _active_active_active_active_T_351; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_358 = _active_active_active_active_T_270 & active_active_active_idx_11 == 2'h3 |
- _active_active_active_active_T_274; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_359 = _active_active_active_active_T_358 ? active_active_active_oh3_11 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_11 = _active_active_active_active_T_352 | _active_active_active_active_T_359; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_423 = f_io_entry_3_bits_tin_vu_valid ? active_active_active_active_11 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_15 = _active_active_active_T_418 | _active_active_active_T_423; // @[VAlu.scala 250:74]
- wire [63:0] active_active_7 = f_io_entry_3_valid ? active_active_active_15 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_30 = _active_T_29 | active_active_7; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_12 = f_io_entry_4_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_12 = 16'h1 << active_active_active_oh_shiftAmount_12; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_12 = {3'h0,active_active_active_oh_12[3],3'h0,active_active_active_oh_12[2]
- ,3'h0,active_active_active_oh_12[1],3'h0,active_active_active_oh_12[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_12 = {3'h0,active_active_active_oh_12[7],3'h0,active_active_active_oh_12[6],3'h0
- ,active_active_active_oh_12[5],3'h0,active_active_active_oh_12[4],active_active_active_oh0_lo_lo_12}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_12 = {3'h0,active_active_active_oh_12[11],3'h0,active_active_active_oh_12[
- 10],3'h0,active_active_active_oh_12[9],3'h0,active_active_active_oh_12[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_12 = {3'h0,active_active_active_oh_12[15],3'h0,active_active_active_oh_12[14],3'h0
- ,active_active_active_oh_12[13],3'h0,active_active_active_oh_12[12],active_active_active_oh0_hi_lo_12,
- active_active_active_oh0_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_12 = {2'h0,active_active_active_oh_12[1],1'h0,2'h0,
- active_active_active_oh_12[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_12 = {2'h0,active_active_active_oh_12[3],1'h0,2'h0,
- active_active_active_oh_12[2],1'h0,active_active_active_oh1_lo_lo_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_12 = {2'h0,active_active_active_oh_12[5],1'h0,2'h0,
- active_active_active_oh_12[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_12 = {2'h0,active_active_active_oh_12[7],1'h0,2'h0,active_active_active_oh_12[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_12,active_active_active_oh1_lo_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_12 = {2'h0,active_active_active_oh_12[9],1'h0,2'h0,
- active_active_active_oh_12[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_12 = {2'h0,active_active_active_oh_12[11],1'h0,2'h0,
- active_active_active_oh_12[10],1'h0,active_active_active_oh1_hi_lo_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_12 = {2'h0,active_active_active_oh_12[13],1'h0,2'h0,
- active_active_active_oh_12[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_12 = {2'h0,active_active_active_oh_12[15],1'h0,2'h0,active_active_active_oh_12[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_12,active_active_active_oh1_hi_lo_12,active_active_active_oh1_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_12 = {1'h0,active_active_active_oh_12[1],2'h0,1'h0,
- active_active_active_oh_12[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_12 = {1'h0,active_active_active_oh_12[3],2'h0,1'h0,
- active_active_active_oh_12[2],2'h0,active_active_active_oh2_lo_lo_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_12 = {1'h0,active_active_active_oh_12[5],2'h0,1'h0,
- active_active_active_oh_12[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_12 = {1'h0,active_active_active_oh_12[7],2'h0,1'h0,active_active_active_oh_12[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_12,active_active_active_oh2_lo_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_12 = {1'h0,active_active_active_oh_12[9],2'h0,1'h0,
- active_active_active_oh_12[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_12 = {1'h0,active_active_active_oh_12[11],2'h0,1'h0,
- active_active_active_oh_12[10],2'h0,active_active_active_oh2_hi_lo_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_12 = {1'h0,active_active_active_oh_12[13],2'h0,1'h0,
- active_active_active_oh_12[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_12 = {1'h0,active_active_active_oh_12[15],2'h0,1'h0,active_active_active_oh_12[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_12,active_active_active_oh2_hi_lo_12,active_active_active_oh2_lo_12}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_12 = {active_active_active_oh_12[3],3'h0,active_active_active_oh_12[2],3'h0
- ,active_active_active_oh_12[1],3'h0,active_active_active_oh_12[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_12 = {active_active_active_oh_12[7],3'h0,active_active_active_oh_12[6],3'h0,
- active_active_active_oh_12[5],3'h0,active_active_active_oh_12[4],3'h0,active_active_active_oh3_lo_lo_12}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_12 = {active_active_active_oh_12[11],3'h0,active_active_active_oh_12[10],3'h0
- ,active_active_active_oh_12[9],3'h0,active_active_active_oh_12[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_12 = {active_active_active_oh_12[15],3'h0,active_active_active_oh_12[14],3'h0,
- active_active_active_oh_12[13],3'h0,active_active_active_oh_12[12],3'h0,active_active_active_oh3_hi_lo_12,
- active_active_active_oh3_lo_12}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_12 = f_io_entry_4_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_360 = ~f_io_entry_4_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_364 = f_io_entry_4_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_365 = ~f_io_entry_4_bits_m & active_active_active_idx_12 == 2'h0 |
- f_io_entry_4_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_366 = _active_active_active_active_T_365 ? active_active_active_oh0_12 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_372 = _active_active_active_active_T_360 & active_active_active_idx_12 == 2'h1 |
- _active_active_active_active_T_364; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_373 = _active_active_active_active_T_372 ? active_active_active_oh1_12 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_374 = _active_active_active_active_T_366 |
- _active_active_active_active_T_373; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_380 = _active_active_active_active_T_360 & active_active_active_idx_12 == 2'h2 |
- _active_active_active_active_T_364; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_381 = _active_active_active_active_T_380 ? active_active_active_oh2_12 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_382 = _active_active_active_active_T_374 |
- _active_active_active_active_T_381; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_388 = _active_active_active_active_T_360 & active_active_active_idx_12 == 2'h3 |
- _active_active_active_active_T_364; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_389 = _active_active_active_active_T_388 ? active_active_active_oh3_12 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_12 = _active_active_active_active_T_382 | _active_active_active_active_T_389; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_428 = f_io_entry_4_bits_tin_vs_valid ? active_active_active_active_12 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_13 = f_io_entry_4_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_13 = 16'h1 << active_active_active_oh_shiftAmount_13; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_13 = {3'h0,active_active_active_oh_13[3],3'h0,active_active_active_oh_13[2]
- ,3'h0,active_active_active_oh_13[1],3'h0,active_active_active_oh_13[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_13 = {3'h0,active_active_active_oh_13[7],3'h0,active_active_active_oh_13[6],3'h0
- ,active_active_active_oh_13[5],3'h0,active_active_active_oh_13[4],active_active_active_oh0_lo_lo_13}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_13 = {3'h0,active_active_active_oh_13[11],3'h0,active_active_active_oh_13[
- 10],3'h0,active_active_active_oh_13[9],3'h0,active_active_active_oh_13[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_13 = {3'h0,active_active_active_oh_13[15],3'h0,active_active_active_oh_13[14],3'h0
- ,active_active_active_oh_13[13],3'h0,active_active_active_oh_13[12],active_active_active_oh0_hi_lo_13,
- active_active_active_oh0_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_13 = {2'h0,active_active_active_oh_13[1],1'h0,2'h0,
- active_active_active_oh_13[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_13 = {2'h0,active_active_active_oh_13[3],1'h0,2'h0,
- active_active_active_oh_13[2],1'h0,active_active_active_oh1_lo_lo_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_13 = {2'h0,active_active_active_oh_13[5],1'h0,2'h0,
- active_active_active_oh_13[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_13 = {2'h0,active_active_active_oh_13[7],1'h0,2'h0,active_active_active_oh_13[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_13,active_active_active_oh1_lo_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_13 = {2'h0,active_active_active_oh_13[9],1'h0,2'h0,
- active_active_active_oh_13[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_13 = {2'h0,active_active_active_oh_13[11],1'h0,2'h0,
- active_active_active_oh_13[10],1'h0,active_active_active_oh1_hi_lo_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_13 = {2'h0,active_active_active_oh_13[13],1'h0,2'h0,
- active_active_active_oh_13[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_13 = {2'h0,active_active_active_oh_13[15],1'h0,2'h0,active_active_active_oh_13[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_13,active_active_active_oh1_hi_lo_13,active_active_active_oh1_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_13 = {1'h0,active_active_active_oh_13[1],2'h0,1'h0,
- active_active_active_oh_13[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_13 = {1'h0,active_active_active_oh_13[3],2'h0,1'h0,
- active_active_active_oh_13[2],2'h0,active_active_active_oh2_lo_lo_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_13 = {1'h0,active_active_active_oh_13[5],2'h0,1'h0,
- active_active_active_oh_13[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_13 = {1'h0,active_active_active_oh_13[7],2'h0,1'h0,active_active_active_oh_13[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_13,active_active_active_oh2_lo_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_13 = {1'h0,active_active_active_oh_13[9],2'h0,1'h0,
- active_active_active_oh_13[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_13 = {1'h0,active_active_active_oh_13[11],2'h0,1'h0,
- active_active_active_oh_13[10],2'h0,active_active_active_oh2_hi_lo_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_13 = {1'h0,active_active_active_oh_13[13],2'h0,1'h0,
- active_active_active_oh_13[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_13 = {1'h0,active_active_active_oh_13[15],2'h0,1'h0,active_active_active_oh_13[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_13,active_active_active_oh2_hi_lo_13,active_active_active_oh2_lo_13}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_13 = {active_active_active_oh_13[3],3'h0,active_active_active_oh_13[2],3'h0
- ,active_active_active_oh_13[1],3'h0,active_active_active_oh_13[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_13 = {active_active_active_oh_13[7],3'h0,active_active_active_oh_13[6],3'h0,
- active_active_active_oh_13[5],3'h0,active_active_active_oh_13[4],3'h0,active_active_active_oh3_lo_lo_13}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_13 = {active_active_active_oh_13[11],3'h0,active_active_active_oh_13[10],3'h0
- ,active_active_active_oh_13[9],3'h0,active_active_active_oh_13[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_13 = {active_active_active_oh_13[15],3'h0,active_active_active_oh_13[14],3'h0,
- active_active_active_oh_13[13],3'h0,active_active_active_oh_13[12],3'h0,active_active_active_oh3_hi_lo_13,
- active_active_active_oh3_lo_13}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_13 = f_io_entry_4_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_395 = ~f_io_entry_4_bits_m & active_active_active_idx_13 == 2'h0 |
- f_io_entry_4_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_396 = _active_active_active_active_T_395 ? active_active_active_oh0_13 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_402 = _active_active_active_active_T_360 & active_active_active_idx_13 == 2'h1 |
- _active_active_active_active_T_364; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_403 = _active_active_active_active_T_402 ? active_active_active_oh1_13 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_404 = _active_active_active_active_T_396 |
- _active_active_active_active_T_403; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_410 = _active_active_active_active_T_360 & active_active_active_idx_13 == 2'h2 |
- _active_active_active_active_T_364; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_411 = _active_active_active_active_T_410 ? active_active_active_oh2_13 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_412 = _active_active_active_active_T_404 |
- _active_active_active_active_T_411; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_418 = _active_active_active_active_T_360 & active_active_active_idx_13 == 2'h3 |
- _active_active_active_active_T_364; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_419 = _active_active_active_active_T_418 ? active_active_active_oh3_13 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_13 = _active_active_active_active_T_412 | _active_active_active_active_T_419; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_433 = f_io_entry_4_bits_tin_vt_valid ? active_active_active_active_13 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_434 = _active_active_active_T_428 | _active_active_active_T_433; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_14 = f_io_entry_4_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_14 = 16'h1 << active_active_active_oh_shiftAmount_14; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_14 = {3'h0,active_active_active_oh_14[3],3'h0,active_active_active_oh_14[2]
- ,3'h0,active_active_active_oh_14[1],3'h0,active_active_active_oh_14[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_14 = {3'h0,active_active_active_oh_14[7],3'h0,active_active_active_oh_14[6],3'h0
- ,active_active_active_oh_14[5],3'h0,active_active_active_oh_14[4],active_active_active_oh0_lo_lo_14}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_14 = {3'h0,active_active_active_oh_14[11],3'h0,active_active_active_oh_14[
- 10],3'h0,active_active_active_oh_14[9],3'h0,active_active_active_oh_14[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_14 = {3'h0,active_active_active_oh_14[15],3'h0,active_active_active_oh_14[14],3'h0
- ,active_active_active_oh_14[13],3'h0,active_active_active_oh_14[12],active_active_active_oh0_hi_lo_14,
- active_active_active_oh0_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_14 = {2'h0,active_active_active_oh_14[1],1'h0,2'h0,
- active_active_active_oh_14[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_14 = {2'h0,active_active_active_oh_14[3],1'h0,2'h0,
- active_active_active_oh_14[2],1'h0,active_active_active_oh1_lo_lo_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_14 = {2'h0,active_active_active_oh_14[5],1'h0,2'h0,
- active_active_active_oh_14[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_14 = {2'h0,active_active_active_oh_14[7],1'h0,2'h0,active_active_active_oh_14[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_14,active_active_active_oh1_lo_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_14 = {2'h0,active_active_active_oh_14[9],1'h0,2'h0,
- active_active_active_oh_14[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_14 = {2'h0,active_active_active_oh_14[11],1'h0,2'h0,
- active_active_active_oh_14[10],1'h0,active_active_active_oh1_hi_lo_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_14 = {2'h0,active_active_active_oh_14[13],1'h0,2'h0,
- active_active_active_oh_14[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_14 = {2'h0,active_active_active_oh_14[15],1'h0,2'h0,active_active_active_oh_14[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_14,active_active_active_oh1_hi_lo_14,active_active_active_oh1_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_14 = {1'h0,active_active_active_oh_14[1],2'h0,1'h0,
- active_active_active_oh_14[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_14 = {1'h0,active_active_active_oh_14[3],2'h0,1'h0,
- active_active_active_oh_14[2],2'h0,active_active_active_oh2_lo_lo_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_14 = {1'h0,active_active_active_oh_14[5],2'h0,1'h0,
- active_active_active_oh_14[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_14 = {1'h0,active_active_active_oh_14[7],2'h0,1'h0,active_active_active_oh_14[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_14,active_active_active_oh2_lo_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_14 = {1'h0,active_active_active_oh_14[9],2'h0,1'h0,
- active_active_active_oh_14[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_14 = {1'h0,active_active_active_oh_14[11],2'h0,1'h0,
- active_active_active_oh_14[10],2'h0,active_active_active_oh2_hi_lo_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_14 = {1'h0,active_active_active_oh_14[13],2'h0,1'h0,
- active_active_active_oh_14[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_14 = {1'h0,active_active_active_oh_14[15],2'h0,1'h0,active_active_active_oh_14[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_14,active_active_active_oh2_hi_lo_14,active_active_active_oh2_lo_14}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_14 = {active_active_active_oh_14[3],3'h0,active_active_active_oh_14[2],3'h0
- ,active_active_active_oh_14[1],3'h0,active_active_active_oh_14[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_14 = {active_active_active_oh_14[7],3'h0,active_active_active_oh_14[6],3'h0,
- active_active_active_oh_14[5],3'h0,active_active_active_oh_14[4],3'h0,active_active_active_oh3_lo_lo_14}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_14 = {active_active_active_oh_14[11],3'h0,active_active_active_oh_14[10],3'h0
- ,active_active_active_oh_14[9],3'h0,active_active_active_oh_14[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_14 = {active_active_active_oh_14[15],3'h0,active_active_active_oh_14[14],3'h0,
- active_active_active_oh_14[13],3'h0,active_active_active_oh_14[12],3'h0,active_active_active_oh3_hi_lo_14,
- active_active_active_oh3_lo_14}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_14 = f_io_entry_4_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_425 = ~f_io_entry_4_bits_m & active_active_active_idx_14 == 2'h0 |
- f_io_entry_4_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_426 = _active_active_active_active_T_425 ? active_active_active_oh0_14 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_432 = _active_active_active_active_T_360 & active_active_active_idx_14 == 2'h1 |
- _active_active_active_active_T_364; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_433 = _active_active_active_active_T_432 ? active_active_active_oh1_14 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_434 = _active_active_active_active_T_426 |
- _active_active_active_active_T_433; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_440 = _active_active_active_active_T_360 & active_active_active_idx_14 == 2'h2 |
- _active_active_active_active_T_364; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_441 = _active_active_active_active_T_440 ? active_active_active_oh2_14 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_442 = _active_active_active_active_T_434 |
- _active_active_active_active_T_441; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_448 = _active_active_active_active_T_360 & active_active_active_idx_14 == 2'h3 |
- _active_active_active_active_T_364; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_449 = _active_active_active_active_T_448 ? active_active_active_oh3_14 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_14 = _active_active_active_active_T_442 | _active_active_active_active_T_449; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_439 = f_io_entry_4_bits_tin_vu_valid ? active_active_active_active_14 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_16 = _active_active_active_T_434 | _active_active_active_T_439; // @[VAlu.scala 250:74]
- wire [63:0] active_active_8 = f_io_entry_4_valid ? active_active_active_16 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_31 = _active_T_30 | active_active_8; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_15 = f_io_entry_5_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_15 = 16'h1 << active_active_active_oh_shiftAmount_15; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_15 = {3'h0,active_active_active_oh_15[3],3'h0,active_active_active_oh_15[2]
- ,3'h0,active_active_active_oh_15[1],3'h0,active_active_active_oh_15[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_15 = {3'h0,active_active_active_oh_15[7],3'h0,active_active_active_oh_15[6],3'h0
- ,active_active_active_oh_15[5],3'h0,active_active_active_oh_15[4],active_active_active_oh0_lo_lo_15}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_15 = {3'h0,active_active_active_oh_15[11],3'h0,active_active_active_oh_15[
- 10],3'h0,active_active_active_oh_15[9],3'h0,active_active_active_oh_15[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_15 = {3'h0,active_active_active_oh_15[15],3'h0,active_active_active_oh_15[14],3'h0
- ,active_active_active_oh_15[13],3'h0,active_active_active_oh_15[12],active_active_active_oh0_hi_lo_15,
- active_active_active_oh0_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_15 = {2'h0,active_active_active_oh_15[1],1'h0,2'h0,
- active_active_active_oh_15[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_15 = {2'h0,active_active_active_oh_15[3],1'h0,2'h0,
- active_active_active_oh_15[2],1'h0,active_active_active_oh1_lo_lo_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_15 = {2'h0,active_active_active_oh_15[5],1'h0,2'h0,
- active_active_active_oh_15[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_15 = {2'h0,active_active_active_oh_15[7],1'h0,2'h0,active_active_active_oh_15[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_15,active_active_active_oh1_lo_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_15 = {2'h0,active_active_active_oh_15[9],1'h0,2'h0,
- active_active_active_oh_15[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_15 = {2'h0,active_active_active_oh_15[11],1'h0,2'h0,
- active_active_active_oh_15[10],1'h0,active_active_active_oh1_hi_lo_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_15 = {2'h0,active_active_active_oh_15[13],1'h0,2'h0,
- active_active_active_oh_15[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_15 = {2'h0,active_active_active_oh_15[15],1'h0,2'h0,active_active_active_oh_15[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_15,active_active_active_oh1_hi_lo_15,active_active_active_oh1_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_15 = {1'h0,active_active_active_oh_15[1],2'h0,1'h0,
- active_active_active_oh_15[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_15 = {1'h0,active_active_active_oh_15[3],2'h0,1'h0,
- active_active_active_oh_15[2],2'h0,active_active_active_oh2_lo_lo_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_15 = {1'h0,active_active_active_oh_15[5],2'h0,1'h0,
- active_active_active_oh_15[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_15 = {1'h0,active_active_active_oh_15[7],2'h0,1'h0,active_active_active_oh_15[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_15,active_active_active_oh2_lo_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_15 = {1'h0,active_active_active_oh_15[9],2'h0,1'h0,
- active_active_active_oh_15[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_15 = {1'h0,active_active_active_oh_15[11],2'h0,1'h0,
- active_active_active_oh_15[10],2'h0,active_active_active_oh2_hi_lo_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_15 = {1'h0,active_active_active_oh_15[13],2'h0,1'h0,
- active_active_active_oh_15[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_15 = {1'h0,active_active_active_oh_15[15],2'h0,1'h0,active_active_active_oh_15[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_15,active_active_active_oh2_hi_lo_15,active_active_active_oh2_lo_15}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_15 = {active_active_active_oh_15[3],3'h0,active_active_active_oh_15[2],3'h0
- ,active_active_active_oh_15[1],3'h0,active_active_active_oh_15[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_15 = {active_active_active_oh_15[7],3'h0,active_active_active_oh_15[6],3'h0,
- active_active_active_oh_15[5],3'h0,active_active_active_oh_15[4],3'h0,active_active_active_oh3_lo_lo_15}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_15 = {active_active_active_oh_15[11],3'h0,active_active_active_oh_15[10],3'h0
- ,active_active_active_oh_15[9],3'h0,active_active_active_oh_15[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_15 = {active_active_active_oh_15[15],3'h0,active_active_active_oh_15[14],3'h0,
- active_active_active_oh_15[13],3'h0,active_active_active_oh_15[12],3'h0,active_active_active_oh3_hi_lo_15,
- active_active_active_oh3_lo_15}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_15 = f_io_entry_5_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_450 = ~f_io_entry_5_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_454 = f_io_entry_5_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_455 = ~f_io_entry_5_bits_m & active_active_active_idx_15 == 2'h0 |
- f_io_entry_5_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_456 = _active_active_active_active_T_455 ? active_active_active_oh0_15 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_462 = _active_active_active_active_T_450 & active_active_active_idx_15 == 2'h1 |
- _active_active_active_active_T_454; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_463 = _active_active_active_active_T_462 ? active_active_active_oh1_15 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_464 = _active_active_active_active_T_456 |
- _active_active_active_active_T_463; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_470 = _active_active_active_active_T_450 & active_active_active_idx_15 == 2'h2 |
- _active_active_active_active_T_454; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_471 = _active_active_active_active_T_470 ? active_active_active_oh2_15 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_472 = _active_active_active_active_T_464 |
- _active_active_active_active_T_471; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_478 = _active_active_active_active_T_450 & active_active_active_idx_15 == 2'h3 |
- _active_active_active_active_T_454; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_479 = _active_active_active_active_T_478 ? active_active_active_oh3_15 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_15 = _active_active_active_active_T_472 | _active_active_active_active_T_479; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_444 = f_io_entry_5_bits_tin_vs_valid ? active_active_active_active_15 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_16 = f_io_entry_5_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_16 = 16'h1 << active_active_active_oh_shiftAmount_16; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_16 = {3'h0,active_active_active_oh_16[3],3'h0,active_active_active_oh_16[2]
- ,3'h0,active_active_active_oh_16[1],3'h0,active_active_active_oh_16[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_16 = {3'h0,active_active_active_oh_16[7],3'h0,active_active_active_oh_16[6],3'h0
- ,active_active_active_oh_16[5],3'h0,active_active_active_oh_16[4],active_active_active_oh0_lo_lo_16}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_16 = {3'h0,active_active_active_oh_16[11],3'h0,active_active_active_oh_16[
- 10],3'h0,active_active_active_oh_16[9],3'h0,active_active_active_oh_16[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_16 = {3'h0,active_active_active_oh_16[15],3'h0,active_active_active_oh_16[14],3'h0
- ,active_active_active_oh_16[13],3'h0,active_active_active_oh_16[12],active_active_active_oh0_hi_lo_16,
- active_active_active_oh0_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_16 = {2'h0,active_active_active_oh_16[1],1'h0,2'h0,
- active_active_active_oh_16[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_16 = {2'h0,active_active_active_oh_16[3],1'h0,2'h0,
- active_active_active_oh_16[2],1'h0,active_active_active_oh1_lo_lo_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_16 = {2'h0,active_active_active_oh_16[5],1'h0,2'h0,
- active_active_active_oh_16[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_16 = {2'h0,active_active_active_oh_16[7],1'h0,2'h0,active_active_active_oh_16[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_16,active_active_active_oh1_lo_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_16 = {2'h0,active_active_active_oh_16[9],1'h0,2'h0,
- active_active_active_oh_16[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_16 = {2'h0,active_active_active_oh_16[11],1'h0,2'h0,
- active_active_active_oh_16[10],1'h0,active_active_active_oh1_hi_lo_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_16 = {2'h0,active_active_active_oh_16[13],1'h0,2'h0,
- active_active_active_oh_16[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_16 = {2'h0,active_active_active_oh_16[15],1'h0,2'h0,active_active_active_oh_16[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_16,active_active_active_oh1_hi_lo_16,active_active_active_oh1_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_16 = {1'h0,active_active_active_oh_16[1],2'h0,1'h0,
- active_active_active_oh_16[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_16 = {1'h0,active_active_active_oh_16[3],2'h0,1'h0,
- active_active_active_oh_16[2],2'h0,active_active_active_oh2_lo_lo_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_16 = {1'h0,active_active_active_oh_16[5],2'h0,1'h0,
- active_active_active_oh_16[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_16 = {1'h0,active_active_active_oh_16[7],2'h0,1'h0,active_active_active_oh_16[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_16,active_active_active_oh2_lo_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_16 = {1'h0,active_active_active_oh_16[9],2'h0,1'h0,
- active_active_active_oh_16[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_16 = {1'h0,active_active_active_oh_16[11],2'h0,1'h0,
- active_active_active_oh_16[10],2'h0,active_active_active_oh2_hi_lo_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_16 = {1'h0,active_active_active_oh_16[13],2'h0,1'h0,
- active_active_active_oh_16[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_16 = {1'h0,active_active_active_oh_16[15],2'h0,1'h0,active_active_active_oh_16[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_16,active_active_active_oh2_hi_lo_16,active_active_active_oh2_lo_16}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_16 = {active_active_active_oh_16[3],3'h0,active_active_active_oh_16[2],3'h0
- ,active_active_active_oh_16[1],3'h0,active_active_active_oh_16[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_16 = {active_active_active_oh_16[7],3'h0,active_active_active_oh_16[6],3'h0,
- active_active_active_oh_16[5],3'h0,active_active_active_oh_16[4],3'h0,active_active_active_oh3_lo_lo_16}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_16 = {active_active_active_oh_16[11],3'h0,active_active_active_oh_16[10],3'h0
- ,active_active_active_oh_16[9],3'h0,active_active_active_oh_16[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_16 = {active_active_active_oh_16[15],3'h0,active_active_active_oh_16[14],3'h0,
- active_active_active_oh_16[13],3'h0,active_active_active_oh_16[12],3'h0,active_active_active_oh3_hi_lo_16,
- active_active_active_oh3_lo_16}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_16 = f_io_entry_5_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_485 = ~f_io_entry_5_bits_m & active_active_active_idx_16 == 2'h0 |
- f_io_entry_5_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_486 = _active_active_active_active_T_485 ? active_active_active_oh0_16 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_492 = _active_active_active_active_T_450 & active_active_active_idx_16 == 2'h1 |
- _active_active_active_active_T_454; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_493 = _active_active_active_active_T_492 ? active_active_active_oh1_16 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_494 = _active_active_active_active_T_486 |
- _active_active_active_active_T_493; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_500 = _active_active_active_active_T_450 & active_active_active_idx_16 == 2'h2 |
- _active_active_active_active_T_454; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_501 = _active_active_active_active_T_500 ? active_active_active_oh2_16 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_502 = _active_active_active_active_T_494 |
- _active_active_active_active_T_501; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_508 = _active_active_active_active_T_450 & active_active_active_idx_16 == 2'h3 |
- _active_active_active_active_T_454; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_509 = _active_active_active_active_T_508 ? active_active_active_oh3_16 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_16 = _active_active_active_active_T_502 | _active_active_active_active_T_509; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_449 = f_io_entry_5_bits_tin_vt_valid ? active_active_active_active_16 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_450 = _active_active_active_T_444 | _active_active_active_T_449; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_17 = f_io_entry_5_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_17 = 16'h1 << active_active_active_oh_shiftAmount_17; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_17 = {3'h0,active_active_active_oh_17[3],3'h0,active_active_active_oh_17[2]
- ,3'h0,active_active_active_oh_17[1],3'h0,active_active_active_oh_17[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_17 = {3'h0,active_active_active_oh_17[7],3'h0,active_active_active_oh_17[6],3'h0
- ,active_active_active_oh_17[5],3'h0,active_active_active_oh_17[4],active_active_active_oh0_lo_lo_17}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_17 = {3'h0,active_active_active_oh_17[11],3'h0,active_active_active_oh_17[
- 10],3'h0,active_active_active_oh_17[9],3'h0,active_active_active_oh_17[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_17 = {3'h0,active_active_active_oh_17[15],3'h0,active_active_active_oh_17[14],3'h0
- ,active_active_active_oh_17[13],3'h0,active_active_active_oh_17[12],active_active_active_oh0_hi_lo_17,
- active_active_active_oh0_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_17 = {2'h0,active_active_active_oh_17[1],1'h0,2'h0,
- active_active_active_oh_17[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_17 = {2'h0,active_active_active_oh_17[3],1'h0,2'h0,
- active_active_active_oh_17[2],1'h0,active_active_active_oh1_lo_lo_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_17 = {2'h0,active_active_active_oh_17[5],1'h0,2'h0,
- active_active_active_oh_17[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_17 = {2'h0,active_active_active_oh_17[7],1'h0,2'h0,active_active_active_oh_17[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_17,active_active_active_oh1_lo_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_17 = {2'h0,active_active_active_oh_17[9],1'h0,2'h0,
- active_active_active_oh_17[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_17 = {2'h0,active_active_active_oh_17[11],1'h0,2'h0,
- active_active_active_oh_17[10],1'h0,active_active_active_oh1_hi_lo_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_17 = {2'h0,active_active_active_oh_17[13],1'h0,2'h0,
- active_active_active_oh_17[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_17 = {2'h0,active_active_active_oh_17[15],1'h0,2'h0,active_active_active_oh_17[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_17,active_active_active_oh1_hi_lo_17,active_active_active_oh1_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_17 = {1'h0,active_active_active_oh_17[1],2'h0,1'h0,
- active_active_active_oh_17[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_17 = {1'h0,active_active_active_oh_17[3],2'h0,1'h0,
- active_active_active_oh_17[2],2'h0,active_active_active_oh2_lo_lo_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_17 = {1'h0,active_active_active_oh_17[5],2'h0,1'h0,
- active_active_active_oh_17[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_17 = {1'h0,active_active_active_oh_17[7],2'h0,1'h0,active_active_active_oh_17[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_17,active_active_active_oh2_lo_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_17 = {1'h0,active_active_active_oh_17[9],2'h0,1'h0,
- active_active_active_oh_17[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_17 = {1'h0,active_active_active_oh_17[11],2'h0,1'h0,
- active_active_active_oh_17[10],2'h0,active_active_active_oh2_hi_lo_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_17 = {1'h0,active_active_active_oh_17[13],2'h0,1'h0,
- active_active_active_oh_17[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_17 = {1'h0,active_active_active_oh_17[15],2'h0,1'h0,active_active_active_oh_17[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_17,active_active_active_oh2_hi_lo_17,active_active_active_oh2_lo_17}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_17 = {active_active_active_oh_17[3],3'h0,active_active_active_oh_17[2],3'h0
- ,active_active_active_oh_17[1],3'h0,active_active_active_oh_17[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_17 = {active_active_active_oh_17[7],3'h0,active_active_active_oh_17[6],3'h0,
- active_active_active_oh_17[5],3'h0,active_active_active_oh_17[4],3'h0,active_active_active_oh3_lo_lo_17}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_17 = {active_active_active_oh_17[11],3'h0,active_active_active_oh_17[10],3'h0
- ,active_active_active_oh_17[9],3'h0,active_active_active_oh_17[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_17 = {active_active_active_oh_17[15],3'h0,active_active_active_oh_17[14],3'h0,
- active_active_active_oh_17[13],3'h0,active_active_active_oh_17[12],3'h0,active_active_active_oh3_hi_lo_17,
- active_active_active_oh3_lo_17}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_17 = f_io_entry_5_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_515 = ~f_io_entry_5_bits_m & active_active_active_idx_17 == 2'h0 |
- f_io_entry_5_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_516 = _active_active_active_active_T_515 ? active_active_active_oh0_17 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_522 = _active_active_active_active_T_450 & active_active_active_idx_17 == 2'h1 |
- _active_active_active_active_T_454; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_523 = _active_active_active_active_T_522 ? active_active_active_oh1_17 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_524 = _active_active_active_active_T_516 |
- _active_active_active_active_T_523; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_530 = _active_active_active_active_T_450 & active_active_active_idx_17 == 2'h2 |
- _active_active_active_active_T_454; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_531 = _active_active_active_active_T_530 ? active_active_active_oh2_17 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_532 = _active_active_active_active_T_524 |
- _active_active_active_active_T_531; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_538 = _active_active_active_active_T_450 & active_active_active_idx_17 == 2'h3 |
- _active_active_active_active_T_454; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_539 = _active_active_active_active_T_538 ? active_active_active_oh3_17 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_17 = _active_active_active_active_T_532 | _active_active_active_active_T_539; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_455 = f_io_entry_5_bits_tin_vu_valid ? active_active_active_active_17 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_17 = _active_active_active_T_450 | _active_active_active_T_455; // @[VAlu.scala 250:74]
- wire [63:0] active_active_9 = f_io_entry_5_valid ? active_active_active_17 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_32 = _active_T_31 | active_active_9; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_18 = f_io_entry_6_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_18 = 16'h1 << active_active_active_oh_shiftAmount_18; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_18 = {3'h0,active_active_active_oh_18[3],3'h0,active_active_active_oh_18[2]
- ,3'h0,active_active_active_oh_18[1],3'h0,active_active_active_oh_18[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_18 = {3'h0,active_active_active_oh_18[7],3'h0,active_active_active_oh_18[6],3'h0
- ,active_active_active_oh_18[5],3'h0,active_active_active_oh_18[4],active_active_active_oh0_lo_lo_18}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_18 = {3'h0,active_active_active_oh_18[11],3'h0,active_active_active_oh_18[
- 10],3'h0,active_active_active_oh_18[9],3'h0,active_active_active_oh_18[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_18 = {3'h0,active_active_active_oh_18[15],3'h0,active_active_active_oh_18[14],3'h0
- ,active_active_active_oh_18[13],3'h0,active_active_active_oh_18[12],active_active_active_oh0_hi_lo_18,
- active_active_active_oh0_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_18 = {2'h0,active_active_active_oh_18[1],1'h0,2'h0,
- active_active_active_oh_18[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_18 = {2'h0,active_active_active_oh_18[3],1'h0,2'h0,
- active_active_active_oh_18[2],1'h0,active_active_active_oh1_lo_lo_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_18 = {2'h0,active_active_active_oh_18[5],1'h0,2'h0,
- active_active_active_oh_18[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_18 = {2'h0,active_active_active_oh_18[7],1'h0,2'h0,active_active_active_oh_18[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_18,active_active_active_oh1_lo_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_18 = {2'h0,active_active_active_oh_18[9],1'h0,2'h0,
- active_active_active_oh_18[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_18 = {2'h0,active_active_active_oh_18[11],1'h0,2'h0,
- active_active_active_oh_18[10],1'h0,active_active_active_oh1_hi_lo_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_18 = {2'h0,active_active_active_oh_18[13],1'h0,2'h0,
- active_active_active_oh_18[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_18 = {2'h0,active_active_active_oh_18[15],1'h0,2'h0,active_active_active_oh_18[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_18,active_active_active_oh1_hi_lo_18,active_active_active_oh1_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_18 = {1'h0,active_active_active_oh_18[1],2'h0,1'h0,
- active_active_active_oh_18[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_18 = {1'h0,active_active_active_oh_18[3],2'h0,1'h0,
- active_active_active_oh_18[2],2'h0,active_active_active_oh2_lo_lo_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_18 = {1'h0,active_active_active_oh_18[5],2'h0,1'h0,
- active_active_active_oh_18[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_18 = {1'h0,active_active_active_oh_18[7],2'h0,1'h0,active_active_active_oh_18[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_18,active_active_active_oh2_lo_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_18 = {1'h0,active_active_active_oh_18[9],2'h0,1'h0,
- active_active_active_oh_18[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_18 = {1'h0,active_active_active_oh_18[11],2'h0,1'h0,
- active_active_active_oh_18[10],2'h0,active_active_active_oh2_hi_lo_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_18 = {1'h0,active_active_active_oh_18[13],2'h0,1'h0,
- active_active_active_oh_18[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_18 = {1'h0,active_active_active_oh_18[15],2'h0,1'h0,active_active_active_oh_18[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_18,active_active_active_oh2_hi_lo_18,active_active_active_oh2_lo_18}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_18 = {active_active_active_oh_18[3],3'h0,active_active_active_oh_18[2],3'h0
- ,active_active_active_oh_18[1],3'h0,active_active_active_oh_18[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_18 = {active_active_active_oh_18[7],3'h0,active_active_active_oh_18[6],3'h0,
- active_active_active_oh_18[5],3'h0,active_active_active_oh_18[4],3'h0,active_active_active_oh3_lo_lo_18}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_18 = {active_active_active_oh_18[11],3'h0,active_active_active_oh_18[10],3'h0
- ,active_active_active_oh_18[9],3'h0,active_active_active_oh_18[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_18 = {active_active_active_oh_18[15],3'h0,active_active_active_oh_18[14],3'h0,
- active_active_active_oh_18[13],3'h0,active_active_active_oh_18[12],3'h0,active_active_active_oh3_hi_lo_18,
- active_active_active_oh3_lo_18}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_18 = f_io_entry_6_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_540 = ~f_io_entry_6_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_544 = f_io_entry_6_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_545 = ~f_io_entry_6_bits_m & active_active_active_idx_18 == 2'h0 |
- f_io_entry_6_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_546 = _active_active_active_active_T_545 ? active_active_active_oh0_18 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_552 = _active_active_active_active_T_540 & active_active_active_idx_18 == 2'h1 |
- _active_active_active_active_T_544; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_553 = _active_active_active_active_T_552 ? active_active_active_oh1_18 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_554 = _active_active_active_active_T_546 |
- _active_active_active_active_T_553; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_560 = _active_active_active_active_T_540 & active_active_active_idx_18 == 2'h2 |
- _active_active_active_active_T_544; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_561 = _active_active_active_active_T_560 ? active_active_active_oh2_18 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_562 = _active_active_active_active_T_554 |
- _active_active_active_active_T_561; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_568 = _active_active_active_active_T_540 & active_active_active_idx_18 == 2'h3 |
- _active_active_active_active_T_544; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_569 = _active_active_active_active_T_568 ? active_active_active_oh3_18 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_18 = _active_active_active_active_T_562 | _active_active_active_active_T_569; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_460 = f_io_entry_6_bits_tin_vs_valid ? active_active_active_active_18 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_19 = f_io_entry_6_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_19 = 16'h1 << active_active_active_oh_shiftAmount_19; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_19 = {3'h0,active_active_active_oh_19[3],3'h0,active_active_active_oh_19[2]
- ,3'h0,active_active_active_oh_19[1],3'h0,active_active_active_oh_19[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_19 = {3'h0,active_active_active_oh_19[7],3'h0,active_active_active_oh_19[6],3'h0
- ,active_active_active_oh_19[5],3'h0,active_active_active_oh_19[4],active_active_active_oh0_lo_lo_19}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_19 = {3'h0,active_active_active_oh_19[11],3'h0,active_active_active_oh_19[
- 10],3'h0,active_active_active_oh_19[9],3'h0,active_active_active_oh_19[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_19 = {3'h0,active_active_active_oh_19[15],3'h0,active_active_active_oh_19[14],3'h0
- ,active_active_active_oh_19[13],3'h0,active_active_active_oh_19[12],active_active_active_oh0_hi_lo_19,
- active_active_active_oh0_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_19 = {2'h0,active_active_active_oh_19[1],1'h0,2'h0,
- active_active_active_oh_19[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_19 = {2'h0,active_active_active_oh_19[3],1'h0,2'h0,
- active_active_active_oh_19[2],1'h0,active_active_active_oh1_lo_lo_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_19 = {2'h0,active_active_active_oh_19[5],1'h0,2'h0,
- active_active_active_oh_19[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_19 = {2'h0,active_active_active_oh_19[7],1'h0,2'h0,active_active_active_oh_19[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_19,active_active_active_oh1_lo_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_19 = {2'h0,active_active_active_oh_19[9],1'h0,2'h0,
- active_active_active_oh_19[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_19 = {2'h0,active_active_active_oh_19[11],1'h0,2'h0,
- active_active_active_oh_19[10],1'h0,active_active_active_oh1_hi_lo_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_19 = {2'h0,active_active_active_oh_19[13],1'h0,2'h0,
- active_active_active_oh_19[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_19 = {2'h0,active_active_active_oh_19[15],1'h0,2'h0,active_active_active_oh_19[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_19,active_active_active_oh1_hi_lo_19,active_active_active_oh1_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_19 = {1'h0,active_active_active_oh_19[1],2'h0,1'h0,
- active_active_active_oh_19[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_19 = {1'h0,active_active_active_oh_19[3],2'h0,1'h0,
- active_active_active_oh_19[2],2'h0,active_active_active_oh2_lo_lo_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_19 = {1'h0,active_active_active_oh_19[5],2'h0,1'h0,
- active_active_active_oh_19[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_19 = {1'h0,active_active_active_oh_19[7],2'h0,1'h0,active_active_active_oh_19[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_19,active_active_active_oh2_lo_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_19 = {1'h0,active_active_active_oh_19[9],2'h0,1'h0,
- active_active_active_oh_19[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_19 = {1'h0,active_active_active_oh_19[11],2'h0,1'h0,
- active_active_active_oh_19[10],2'h0,active_active_active_oh2_hi_lo_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_19 = {1'h0,active_active_active_oh_19[13],2'h0,1'h0,
- active_active_active_oh_19[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_19 = {1'h0,active_active_active_oh_19[15],2'h0,1'h0,active_active_active_oh_19[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_19,active_active_active_oh2_hi_lo_19,active_active_active_oh2_lo_19}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_19 = {active_active_active_oh_19[3],3'h0,active_active_active_oh_19[2],3'h0
- ,active_active_active_oh_19[1],3'h0,active_active_active_oh_19[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_19 = {active_active_active_oh_19[7],3'h0,active_active_active_oh_19[6],3'h0,
- active_active_active_oh_19[5],3'h0,active_active_active_oh_19[4],3'h0,active_active_active_oh3_lo_lo_19}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_19 = {active_active_active_oh_19[11],3'h0,active_active_active_oh_19[10],3'h0
- ,active_active_active_oh_19[9],3'h0,active_active_active_oh_19[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_19 = {active_active_active_oh_19[15],3'h0,active_active_active_oh_19[14],3'h0,
- active_active_active_oh_19[13],3'h0,active_active_active_oh_19[12],3'h0,active_active_active_oh3_hi_lo_19,
- active_active_active_oh3_lo_19}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_19 = f_io_entry_6_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_575 = ~f_io_entry_6_bits_m & active_active_active_idx_19 == 2'h0 |
- f_io_entry_6_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_576 = _active_active_active_active_T_575 ? active_active_active_oh0_19 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_582 = _active_active_active_active_T_540 & active_active_active_idx_19 == 2'h1 |
- _active_active_active_active_T_544; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_583 = _active_active_active_active_T_582 ? active_active_active_oh1_19 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_584 = _active_active_active_active_T_576 |
- _active_active_active_active_T_583; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_590 = _active_active_active_active_T_540 & active_active_active_idx_19 == 2'h2 |
- _active_active_active_active_T_544; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_591 = _active_active_active_active_T_590 ? active_active_active_oh2_19 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_592 = _active_active_active_active_T_584 |
- _active_active_active_active_T_591; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_598 = _active_active_active_active_T_540 & active_active_active_idx_19 == 2'h3 |
- _active_active_active_active_T_544; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_599 = _active_active_active_active_T_598 ? active_active_active_oh3_19 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_19 = _active_active_active_active_T_592 | _active_active_active_active_T_599; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_465 = f_io_entry_6_bits_tin_vt_valid ? active_active_active_active_19 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_466 = _active_active_active_T_460 | _active_active_active_T_465; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_20 = f_io_entry_6_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_20 = 16'h1 << active_active_active_oh_shiftAmount_20; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_20 = {3'h0,active_active_active_oh_20[3],3'h0,active_active_active_oh_20[2]
- ,3'h0,active_active_active_oh_20[1],3'h0,active_active_active_oh_20[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_20 = {3'h0,active_active_active_oh_20[7],3'h0,active_active_active_oh_20[6],3'h0
- ,active_active_active_oh_20[5],3'h0,active_active_active_oh_20[4],active_active_active_oh0_lo_lo_20}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_20 = {3'h0,active_active_active_oh_20[11],3'h0,active_active_active_oh_20[
- 10],3'h0,active_active_active_oh_20[9],3'h0,active_active_active_oh_20[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_20 = {3'h0,active_active_active_oh_20[15],3'h0,active_active_active_oh_20[14],3'h0
- ,active_active_active_oh_20[13],3'h0,active_active_active_oh_20[12],active_active_active_oh0_hi_lo_20,
- active_active_active_oh0_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_20 = {2'h0,active_active_active_oh_20[1],1'h0,2'h0,
- active_active_active_oh_20[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_20 = {2'h0,active_active_active_oh_20[3],1'h0,2'h0,
- active_active_active_oh_20[2],1'h0,active_active_active_oh1_lo_lo_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_20 = {2'h0,active_active_active_oh_20[5],1'h0,2'h0,
- active_active_active_oh_20[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_20 = {2'h0,active_active_active_oh_20[7],1'h0,2'h0,active_active_active_oh_20[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_20,active_active_active_oh1_lo_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_20 = {2'h0,active_active_active_oh_20[9],1'h0,2'h0,
- active_active_active_oh_20[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_20 = {2'h0,active_active_active_oh_20[11],1'h0,2'h0,
- active_active_active_oh_20[10],1'h0,active_active_active_oh1_hi_lo_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_20 = {2'h0,active_active_active_oh_20[13],1'h0,2'h0,
- active_active_active_oh_20[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_20 = {2'h0,active_active_active_oh_20[15],1'h0,2'h0,active_active_active_oh_20[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_20,active_active_active_oh1_hi_lo_20,active_active_active_oh1_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_20 = {1'h0,active_active_active_oh_20[1],2'h0,1'h0,
- active_active_active_oh_20[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_20 = {1'h0,active_active_active_oh_20[3],2'h0,1'h0,
- active_active_active_oh_20[2],2'h0,active_active_active_oh2_lo_lo_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_20 = {1'h0,active_active_active_oh_20[5],2'h0,1'h0,
- active_active_active_oh_20[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_20 = {1'h0,active_active_active_oh_20[7],2'h0,1'h0,active_active_active_oh_20[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_20,active_active_active_oh2_lo_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_20 = {1'h0,active_active_active_oh_20[9],2'h0,1'h0,
- active_active_active_oh_20[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_20 = {1'h0,active_active_active_oh_20[11],2'h0,1'h0,
- active_active_active_oh_20[10],2'h0,active_active_active_oh2_hi_lo_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_20 = {1'h0,active_active_active_oh_20[13],2'h0,1'h0,
- active_active_active_oh_20[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_20 = {1'h0,active_active_active_oh_20[15],2'h0,1'h0,active_active_active_oh_20[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_20,active_active_active_oh2_hi_lo_20,active_active_active_oh2_lo_20}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_20 = {active_active_active_oh_20[3],3'h0,active_active_active_oh_20[2],3'h0
- ,active_active_active_oh_20[1],3'h0,active_active_active_oh_20[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_20 = {active_active_active_oh_20[7],3'h0,active_active_active_oh_20[6],3'h0,
- active_active_active_oh_20[5],3'h0,active_active_active_oh_20[4],3'h0,active_active_active_oh3_lo_lo_20}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_20 = {active_active_active_oh_20[11],3'h0,active_active_active_oh_20[10],3'h0
- ,active_active_active_oh_20[9],3'h0,active_active_active_oh_20[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_20 = {active_active_active_oh_20[15],3'h0,active_active_active_oh_20[14],3'h0,
- active_active_active_oh_20[13],3'h0,active_active_active_oh_20[12],3'h0,active_active_active_oh3_hi_lo_20,
- active_active_active_oh3_lo_20}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_20 = f_io_entry_6_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_605 = ~f_io_entry_6_bits_m & active_active_active_idx_20 == 2'h0 |
- f_io_entry_6_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_606 = _active_active_active_active_T_605 ? active_active_active_oh0_20 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_612 = _active_active_active_active_T_540 & active_active_active_idx_20 == 2'h1 |
- _active_active_active_active_T_544; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_613 = _active_active_active_active_T_612 ? active_active_active_oh1_20 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_614 = _active_active_active_active_T_606 |
- _active_active_active_active_T_613; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_620 = _active_active_active_active_T_540 & active_active_active_idx_20 == 2'h2 |
- _active_active_active_active_T_544; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_621 = _active_active_active_active_T_620 ? active_active_active_oh2_20 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_622 = _active_active_active_active_T_614 |
- _active_active_active_active_T_621; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_628 = _active_active_active_active_T_540 & active_active_active_idx_20 == 2'h3 |
- _active_active_active_active_T_544; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_629 = _active_active_active_active_T_628 ? active_active_active_oh3_20 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_20 = _active_active_active_active_T_622 | _active_active_active_active_T_629; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_471 = f_io_entry_6_bits_tin_vu_valid ? active_active_active_active_20 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_18 = _active_active_active_T_466 | _active_active_active_T_471; // @[VAlu.scala 250:74]
- wire [63:0] active_active_10 = f_io_entry_6_valid ? active_active_active_18 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_33 = _active_T_32 | active_active_10; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_21 = f_io_entry_7_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_21 = 16'h1 << active_active_active_oh_shiftAmount_21; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_21 = {3'h0,active_active_active_oh_21[3],3'h0,active_active_active_oh_21[2]
- ,3'h0,active_active_active_oh_21[1],3'h0,active_active_active_oh_21[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_21 = {3'h0,active_active_active_oh_21[7],3'h0,active_active_active_oh_21[6],3'h0
- ,active_active_active_oh_21[5],3'h0,active_active_active_oh_21[4],active_active_active_oh0_lo_lo_21}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_21 = {3'h0,active_active_active_oh_21[11],3'h0,active_active_active_oh_21[
- 10],3'h0,active_active_active_oh_21[9],3'h0,active_active_active_oh_21[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_21 = {3'h0,active_active_active_oh_21[15],3'h0,active_active_active_oh_21[14],3'h0
- ,active_active_active_oh_21[13],3'h0,active_active_active_oh_21[12],active_active_active_oh0_hi_lo_21,
- active_active_active_oh0_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_21 = {2'h0,active_active_active_oh_21[1],1'h0,2'h0,
- active_active_active_oh_21[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_21 = {2'h0,active_active_active_oh_21[3],1'h0,2'h0,
- active_active_active_oh_21[2],1'h0,active_active_active_oh1_lo_lo_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_21 = {2'h0,active_active_active_oh_21[5],1'h0,2'h0,
- active_active_active_oh_21[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_21 = {2'h0,active_active_active_oh_21[7],1'h0,2'h0,active_active_active_oh_21[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_21,active_active_active_oh1_lo_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_21 = {2'h0,active_active_active_oh_21[9],1'h0,2'h0,
- active_active_active_oh_21[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_21 = {2'h0,active_active_active_oh_21[11],1'h0,2'h0,
- active_active_active_oh_21[10],1'h0,active_active_active_oh1_hi_lo_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_21 = {2'h0,active_active_active_oh_21[13],1'h0,2'h0,
- active_active_active_oh_21[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_21 = {2'h0,active_active_active_oh_21[15],1'h0,2'h0,active_active_active_oh_21[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_21,active_active_active_oh1_hi_lo_21,active_active_active_oh1_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_21 = {1'h0,active_active_active_oh_21[1],2'h0,1'h0,
- active_active_active_oh_21[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_21 = {1'h0,active_active_active_oh_21[3],2'h0,1'h0,
- active_active_active_oh_21[2],2'h0,active_active_active_oh2_lo_lo_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_21 = {1'h0,active_active_active_oh_21[5],2'h0,1'h0,
- active_active_active_oh_21[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_21 = {1'h0,active_active_active_oh_21[7],2'h0,1'h0,active_active_active_oh_21[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_21,active_active_active_oh2_lo_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_21 = {1'h0,active_active_active_oh_21[9],2'h0,1'h0,
- active_active_active_oh_21[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_21 = {1'h0,active_active_active_oh_21[11],2'h0,1'h0,
- active_active_active_oh_21[10],2'h0,active_active_active_oh2_hi_lo_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_21 = {1'h0,active_active_active_oh_21[13],2'h0,1'h0,
- active_active_active_oh_21[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_21 = {1'h0,active_active_active_oh_21[15],2'h0,1'h0,active_active_active_oh_21[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_21,active_active_active_oh2_hi_lo_21,active_active_active_oh2_lo_21}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_21 = {active_active_active_oh_21[3],3'h0,active_active_active_oh_21[2],3'h0
- ,active_active_active_oh_21[1],3'h0,active_active_active_oh_21[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_21 = {active_active_active_oh_21[7],3'h0,active_active_active_oh_21[6],3'h0,
- active_active_active_oh_21[5],3'h0,active_active_active_oh_21[4],3'h0,active_active_active_oh3_lo_lo_21}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_21 = {active_active_active_oh_21[11],3'h0,active_active_active_oh_21[10],3'h0
- ,active_active_active_oh_21[9],3'h0,active_active_active_oh_21[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_21 = {active_active_active_oh_21[15],3'h0,active_active_active_oh_21[14],3'h0,
- active_active_active_oh_21[13],3'h0,active_active_active_oh_21[12],3'h0,active_active_active_oh3_hi_lo_21,
- active_active_active_oh3_lo_21}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_21 = f_io_entry_7_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_630 = ~f_io_entry_7_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_634 = f_io_entry_7_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_635 = ~f_io_entry_7_bits_m & active_active_active_idx_21 == 2'h0 |
- f_io_entry_7_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_636 = _active_active_active_active_T_635 ? active_active_active_oh0_21 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_642 = _active_active_active_active_T_630 & active_active_active_idx_21 == 2'h1 |
- _active_active_active_active_T_634; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_643 = _active_active_active_active_T_642 ? active_active_active_oh1_21 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_644 = _active_active_active_active_T_636 |
- _active_active_active_active_T_643; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_650 = _active_active_active_active_T_630 & active_active_active_idx_21 == 2'h2 |
- _active_active_active_active_T_634; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_651 = _active_active_active_active_T_650 ? active_active_active_oh2_21 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_652 = _active_active_active_active_T_644 |
- _active_active_active_active_T_651; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_658 = _active_active_active_active_T_630 & active_active_active_idx_21 == 2'h3 |
- _active_active_active_active_T_634; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_659 = _active_active_active_active_T_658 ? active_active_active_oh3_21 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_21 = _active_active_active_active_T_652 | _active_active_active_active_T_659; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_476 = f_io_entry_7_bits_tin_vs_valid ? active_active_active_active_21 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_22 = f_io_entry_7_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_22 = 16'h1 << active_active_active_oh_shiftAmount_22; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_22 = {3'h0,active_active_active_oh_22[3],3'h0,active_active_active_oh_22[2]
- ,3'h0,active_active_active_oh_22[1],3'h0,active_active_active_oh_22[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_22 = {3'h0,active_active_active_oh_22[7],3'h0,active_active_active_oh_22[6],3'h0
- ,active_active_active_oh_22[5],3'h0,active_active_active_oh_22[4],active_active_active_oh0_lo_lo_22}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_22 = {3'h0,active_active_active_oh_22[11],3'h0,active_active_active_oh_22[
- 10],3'h0,active_active_active_oh_22[9],3'h0,active_active_active_oh_22[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_22 = {3'h0,active_active_active_oh_22[15],3'h0,active_active_active_oh_22[14],3'h0
- ,active_active_active_oh_22[13],3'h0,active_active_active_oh_22[12],active_active_active_oh0_hi_lo_22,
- active_active_active_oh0_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_22 = {2'h0,active_active_active_oh_22[1],1'h0,2'h0,
- active_active_active_oh_22[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_22 = {2'h0,active_active_active_oh_22[3],1'h0,2'h0,
- active_active_active_oh_22[2],1'h0,active_active_active_oh1_lo_lo_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_22 = {2'h0,active_active_active_oh_22[5],1'h0,2'h0,
- active_active_active_oh_22[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_22 = {2'h0,active_active_active_oh_22[7],1'h0,2'h0,active_active_active_oh_22[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_22,active_active_active_oh1_lo_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_22 = {2'h0,active_active_active_oh_22[9],1'h0,2'h0,
- active_active_active_oh_22[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_22 = {2'h0,active_active_active_oh_22[11],1'h0,2'h0,
- active_active_active_oh_22[10],1'h0,active_active_active_oh1_hi_lo_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_22 = {2'h0,active_active_active_oh_22[13],1'h0,2'h0,
- active_active_active_oh_22[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_22 = {2'h0,active_active_active_oh_22[15],1'h0,2'h0,active_active_active_oh_22[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_22,active_active_active_oh1_hi_lo_22,active_active_active_oh1_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_22 = {1'h0,active_active_active_oh_22[1],2'h0,1'h0,
- active_active_active_oh_22[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_22 = {1'h0,active_active_active_oh_22[3],2'h0,1'h0,
- active_active_active_oh_22[2],2'h0,active_active_active_oh2_lo_lo_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_22 = {1'h0,active_active_active_oh_22[5],2'h0,1'h0,
- active_active_active_oh_22[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_22 = {1'h0,active_active_active_oh_22[7],2'h0,1'h0,active_active_active_oh_22[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_22,active_active_active_oh2_lo_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_22 = {1'h0,active_active_active_oh_22[9],2'h0,1'h0,
- active_active_active_oh_22[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_22 = {1'h0,active_active_active_oh_22[11],2'h0,1'h0,
- active_active_active_oh_22[10],2'h0,active_active_active_oh2_hi_lo_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_22 = {1'h0,active_active_active_oh_22[13],2'h0,1'h0,
- active_active_active_oh_22[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_22 = {1'h0,active_active_active_oh_22[15],2'h0,1'h0,active_active_active_oh_22[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_22,active_active_active_oh2_hi_lo_22,active_active_active_oh2_lo_22}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_22 = {active_active_active_oh_22[3],3'h0,active_active_active_oh_22[2],3'h0
- ,active_active_active_oh_22[1],3'h0,active_active_active_oh_22[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_22 = {active_active_active_oh_22[7],3'h0,active_active_active_oh_22[6],3'h0,
- active_active_active_oh_22[5],3'h0,active_active_active_oh_22[4],3'h0,active_active_active_oh3_lo_lo_22}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_22 = {active_active_active_oh_22[11],3'h0,active_active_active_oh_22[10],3'h0
- ,active_active_active_oh_22[9],3'h0,active_active_active_oh_22[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_22 = {active_active_active_oh_22[15],3'h0,active_active_active_oh_22[14],3'h0,
- active_active_active_oh_22[13],3'h0,active_active_active_oh_22[12],3'h0,active_active_active_oh3_hi_lo_22,
- active_active_active_oh3_lo_22}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_22 = f_io_entry_7_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_665 = ~f_io_entry_7_bits_m & active_active_active_idx_22 == 2'h0 |
- f_io_entry_7_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_666 = _active_active_active_active_T_665 ? active_active_active_oh0_22 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_672 = _active_active_active_active_T_630 & active_active_active_idx_22 == 2'h1 |
- _active_active_active_active_T_634; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_673 = _active_active_active_active_T_672 ? active_active_active_oh1_22 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_674 = _active_active_active_active_T_666 |
- _active_active_active_active_T_673; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_680 = _active_active_active_active_T_630 & active_active_active_idx_22 == 2'h2 |
- _active_active_active_active_T_634; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_681 = _active_active_active_active_T_680 ? active_active_active_oh2_22 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_682 = _active_active_active_active_T_674 |
- _active_active_active_active_T_681; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_688 = _active_active_active_active_T_630 & active_active_active_idx_22 == 2'h3 |
- _active_active_active_active_T_634; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_689 = _active_active_active_active_T_688 ? active_active_active_oh3_22 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_22 = _active_active_active_active_T_682 | _active_active_active_active_T_689; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_481 = f_io_entry_7_bits_tin_vt_valid ? active_active_active_active_22 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_482 = _active_active_active_T_476 | _active_active_active_T_481; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_23 = f_io_entry_7_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_23 = 16'h1 << active_active_active_oh_shiftAmount_23; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_23 = {3'h0,active_active_active_oh_23[3],3'h0,active_active_active_oh_23[2]
- ,3'h0,active_active_active_oh_23[1],3'h0,active_active_active_oh_23[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_23 = {3'h0,active_active_active_oh_23[7],3'h0,active_active_active_oh_23[6],3'h0
- ,active_active_active_oh_23[5],3'h0,active_active_active_oh_23[4],active_active_active_oh0_lo_lo_23}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_23 = {3'h0,active_active_active_oh_23[11],3'h0,active_active_active_oh_23[
- 10],3'h0,active_active_active_oh_23[9],3'h0,active_active_active_oh_23[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_23 = {3'h0,active_active_active_oh_23[15],3'h0,active_active_active_oh_23[14],3'h0
- ,active_active_active_oh_23[13],3'h0,active_active_active_oh_23[12],active_active_active_oh0_hi_lo_23,
- active_active_active_oh0_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_23 = {2'h0,active_active_active_oh_23[1],1'h0,2'h0,
- active_active_active_oh_23[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_23 = {2'h0,active_active_active_oh_23[3],1'h0,2'h0,
- active_active_active_oh_23[2],1'h0,active_active_active_oh1_lo_lo_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_23 = {2'h0,active_active_active_oh_23[5],1'h0,2'h0,
- active_active_active_oh_23[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_23 = {2'h0,active_active_active_oh_23[7],1'h0,2'h0,active_active_active_oh_23[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_23,active_active_active_oh1_lo_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_23 = {2'h0,active_active_active_oh_23[9],1'h0,2'h0,
- active_active_active_oh_23[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_23 = {2'h0,active_active_active_oh_23[11],1'h0,2'h0,
- active_active_active_oh_23[10],1'h0,active_active_active_oh1_hi_lo_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_23 = {2'h0,active_active_active_oh_23[13],1'h0,2'h0,
- active_active_active_oh_23[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_23 = {2'h0,active_active_active_oh_23[15],1'h0,2'h0,active_active_active_oh_23[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_23,active_active_active_oh1_hi_lo_23,active_active_active_oh1_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_23 = {1'h0,active_active_active_oh_23[1],2'h0,1'h0,
- active_active_active_oh_23[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_23 = {1'h0,active_active_active_oh_23[3],2'h0,1'h0,
- active_active_active_oh_23[2],2'h0,active_active_active_oh2_lo_lo_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_23 = {1'h0,active_active_active_oh_23[5],2'h0,1'h0,
- active_active_active_oh_23[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_23 = {1'h0,active_active_active_oh_23[7],2'h0,1'h0,active_active_active_oh_23[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_23,active_active_active_oh2_lo_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_23 = {1'h0,active_active_active_oh_23[9],2'h0,1'h0,
- active_active_active_oh_23[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_23 = {1'h0,active_active_active_oh_23[11],2'h0,1'h0,
- active_active_active_oh_23[10],2'h0,active_active_active_oh2_hi_lo_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_23 = {1'h0,active_active_active_oh_23[13],2'h0,1'h0,
- active_active_active_oh_23[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_23 = {1'h0,active_active_active_oh_23[15],2'h0,1'h0,active_active_active_oh_23[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_23,active_active_active_oh2_hi_lo_23,active_active_active_oh2_lo_23}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_23 = {active_active_active_oh_23[3],3'h0,active_active_active_oh_23[2],3'h0
- ,active_active_active_oh_23[1],3'h0,active_active_active_oh_23[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_23 = {active_active_active_oh_23[7],3'h0,active_active_active_oh_23[6],3'h0,
- active_active_active_oh_23[5],3'h0,active_active_active_oh_23[4],3'h0,active_active_active_oh3_lo_lo_23}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_23 = {active_active_active_oh_23[11],3'h0,active_active_active_oh_23[10],3'h0
- ,active_active_active_oh_23[9],3'h0,active_active_active_oh_23[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_23 = {active_active_active_oh_23[15],3'h0,active_active_active_oh_23[14],3'h0,
- active_active_active_oh_23[13],3'h0,active_active_active_oh_23[12],3'h0,active_active_active_oh3_hi_lo_23,
- active_active_active_oh3_lo_23}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_23 = f_io_entry_7_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_695 = ~f_io_entry_7_bits_m & active_active_active_idx_23 == 2'h0 |
- f_io_entry_7_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_696 = _active_active_active_active_T_695 ? active_active_active_oh0_23 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_702 = _active_active_active_active_T_630 & active_active_active_idx_23 == 2'h1 |
- _active_active_active_active_T_634; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_703 = _active_active_active_active_T_702 ? active_active_active_oh1_23 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_704 = _active_active_active_active_T_696 |
- _active_active_active_active_T_703; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_710 = _active_active_active_active_T_630 & active_active_active_idx_23 == 2'h2 |
- _active_active_active_active_T_634; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_711 = _active_active_active_active_T_710 ? active_active_active_oh2_23 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_712 = _active_active_active_active_T_704 |
- _active_active_active_active_T_711; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_718 = _active_active_active_active_T_630 & active_active_active_idx_23 == 2'h3 |
- _active_active_active_active_T_634; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_719 = _active_active_active_active_T_718 ? active_active_active_oh3_23 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_23 = _active_active_active_active_T_712 | _active_active_active_active_T_719; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_487 = f_io_entry_7_bits_tin_vu_valid ? active_active_active_active_23 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_19 = _active_active_active_T_482 | _active_active_active_T_487; // @[VAlu.scala 250:74]
- wire [63:0] active_active_11 = f_io_entry_7_valid ? active_active_active_19 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_34 = _active_T_33 | active_active_11; // @[VCmdq.scala 107:24]
- wire [5:0] _active_active0_T = {{1'd0}, step}; // @[VCmdq.scala 110:48]
- wire [3:0] active_active0_active_oh_shiftAmount = value_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active0_active_oh = 16'h1 << active_active0_active_oh_shiftAmount; // @[OneHot.scala 64:12]
- wire [15:0] active_active0_active_oh0_lo_lo = {3'h0,active_active0_active_oh[3],3'h0,active_active0_active_oh[2],3'h0,
- active_active0_active_oh[1],3'h0,active_active0_active_oh[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh0_lo = {3'h0,active_active0_active_oh[7],3'h0,active_active0_active_oh[6],3'h0,
- active_active0_active_oh[5],3'h0,active_active0_active_oh[4],active_active0_active_oh0_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh0_hi_lo = {3'h0,active_active0_active_oh[11],3'h0,active_active0_active_oh[10],3'h0
- ,active_active0_active_oh[9],3'h0,active_active0_active_oh[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh0 = {3'h0,active_active0_active_oh[15],3'h0,active_active0_active_oh[14],3'h0,
- active_active0_active_oh[13],3'h0,active_active0_active_oh[12],active_active0_active_oh0_hi_lo,
- active_active0_active_oh0_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_lo_lo = {2'h0,active_active0_active_oh[1],1'h0,2'h0,active_active0_active_oh[0
- ],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_lo_lo = {2'h0,active_active0_active_oh[3],1'h0,2'h0,active_active0_active_oh[2],1'h0
- ,active_active0_active_oh1_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_hi_lo = {2'h0,active_active0_active_oh[5],1'h0,2'h0,active_active0_active_oh[4
- ],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh1_lo = {2'h0,active_active0_active_oh[7],1'h0,2'h0,active_active0_active_oh[6],1'h0
- ,active_active0_active_oh1_lo_hi_lo,active_active0_active_oh1_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_lo_lo = {2'h0,active_active0_active_oh[9],1'h0,2'h0,active_active0_active_oh[8
- ],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_hi_lo = {2'h0,active_active0_active_oh[11],1'h0,2'h0,active_active0_active_oh[10
- ],1'h0,active_active0_active_oh1_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_hi_lo = {2'h0,active_active0_active_oh[13],1'h0,2'h0,active_active0_active_oh[
- 12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh1 = {2'h0,active_active0_active_oh[15],1'h0,2'h0,active_active0_active_oh[14],1'h0
- ,active_active0_active_oh1_hi_hi_lo,active_active0_active_oh1_hi_lo,active_active0_active_oh1_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_lo_lo = {1'h0,active_active0_active_oh[1],2'h0,1'h0,active_active0_active_oh[0
- ],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_lo_lo = {1'h0,active_active0_active_oh[3],2'h0,1'h0,active_active0_active_oh[2],2'h0
- ,active_active0_active_oh2_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_hi_lo = {1'h0,active_active0_active_oh[5],2'h0,1'h0,active_active0_active_oh[4
- ],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh2_lo = {1'h0,active_active0_active_oh[7],2'h0,1'h0,active_active0_active_oh[6],2'h0
- ,active_active0_active_oh2_lo_hi_lo,active_active0_active_oh2_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_lo_lo = {1'h0,active_active0_active_oh[9],2'h0,1'h0,active_active0_active_oh[8
- ],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_hi_lo = {1'h0,active_active0_active_oh[11],2'h0,1'h0,active_active0_active_oh[10
- ],2'h0,active_active0_active_oh2_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_hi_lo = {1'h0,active_active0_active_oh[13],2'h0,1'h0,active_active0_active_oh[
- 12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh2 = {1'h0,active_active0_active_oh[15],2'h0,1'h0,active_active0_active_oh[14],2'h0
- ,active_active0_active_oh2_hi_hi_lo,active_active0_active_oh2_hi_lo,active_active0_active_oh2_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_lo_lo = {active_active0_active_oh[3],3'h0,active_active0_active_oh[2],3'h0,
- active_active0_active_oh[1],3'h0,active_active0_active_oh[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh3_lo = {active_active0_active_oh[7],3'h0,active_active0_active_oh[6],3'h0,
- active_active0_active_oh[5],3'h0,active_active0_active_oh[4],3'h0,active_active0_active_oh3_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_hi_lo = {active_active0_active_oh[11],3'h0,active_active0_active_oh[10],3'h0,
- active_active0_active_oh[9],3'h0,active_active0_active_oh[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh3 = {active_active0_active_oh[15],3'h0,active_active0_active_oh[14],3'h0,
- active_active0_active_oh[13],3'h0,active_active0_active_oh[12],3'h0,active_active0_active_oh3_hi_lo,
- active_active0_active_oh3_lo}; // @[Cat.scala 31:58]
- wire [1:0] active_active0_active_idx = value_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active0_active_active_T_5 = _last_T & active_active0_active_idx == 2'h0 | value_m & _active_active0_T[2:
- 0] <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active0_active_active_T_6 = _active_active0_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active0_active_active_T_12 = _last_T & active_active0_active_idx == 2'h1 | value_m & _active_active0_T[2
- :0] <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active0_active_active_T_13 = _active_active0_active_active_T_12 ? active_active0_active_oh1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_14 = _active_active0_active_active_T_6 |
- _active_active0_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active0_active_active_T_20 = _last_T & active_active0_active_idx == 2'h2 | value_m & _active_active0_T[2
- :0] <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active0_active_active_T_21 = _active_active0_active_active_T_20 ? active_active0_active_oh2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_22 = _active_active0_active_active_T_14 |
- _active_active0_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active0_active_active_T_28 = _last_T & active_active0_active_idx == 2'h3 | value_m & _active_active0_T[2
- :0] <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active0_active_active_T_29 = _active_active0_active_active_T_28 ? active_active0_active_oh3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active0_active_active = _active_active0_active_active_T_22 | _active_active0_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] _active_active0_active_T_5 = value_tin_vs_valid ? active_active0_active_active : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active0_active_oh_shiftAmount_1 = value_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active0_active_oh_1 = 16'h1 << active_active0_active_oh_shiftAmount_1; // @[OneHot.scala 64:12]
- wire [15:0] active_active0_active_oh0_lo_lo_1 = {3'h0,active_active0_active_oh_1[3],3'h0,active_active0_active_oh_1[2]
- ,3'h0,active_active0_active_oh_1[1],3'h0,active_active0_active_oh_1[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh0_lo_1 = {3'h0,active_active0_active_oh_1[7],3'h0,active_active0_active_oh_1[6],3'h0
- ,active_active0_active_oh_1[5],3'h0,active_active0_active_oh_1[4],active_active0_active_oh0_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh0_hi_lo_1 = {3'h0,active_active0_active_oh_1[11],3'h0,active_active0_active_oh_1[
- 10],3'h0,active_active0_active_oh_1[9],3'h0,active_active0_active_oh_1[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh0_1 = {3'h0,active_active0_active_oh_1[15],3'h0,active_active0_active_oh_1[14],3'h0
- ,active_active0_active_oh_1[13],3'h0,active_active0_active_oh_1[12],active_active0_active_oh0_hi_lo_1,
- active_active0_active_oh0_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_lo_lo_1 = {2'h0,active_active0_active_oh_1[1],1'h0,2'h0,
- active_active0_active_oh_1[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_lo_lo_1 = {2'h0,active_active0_active_oh_1[3],1'h0,2'h0,
- active_active0_active_oh_1[2],1'h0,active_active0_active_oh1_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_hi_lo_1 = {2'h0,active_active0_active_oh_1[5],1'h0,2'h0,
- active_active0_active_oh_1[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh1_lo_1 = {2'h0,active_active0_active_oh_1[7],1'h0,2'h0,active_active0_active_oh_1[
- 6],1'h0,active_active0_active_oh1_lo_hi_lo_1,active_active0_active_oh1_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_lo_lo_1 = {2'h0,active_active0_active_oh_1[9],1'h0,2'h0,
- active_active0_active_oh_1[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_hi_lo_1 = {2'h0,active_active0_active_oh_1[11],1'h0,2'h0,
- active_active0_active_oh_1[10],1'h0,active_active0_active_oh1_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_hi_lo_1 = {2'h0,active_active0_active_oh_1[13],1'h0,2'h0,
- active_active0_active_oh_1[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh1_1 = {2'h0,active_active0_active_oh_1[15],1'h0,2'h0,active_active0_active_oh_1[14
- ],1'h0,active_active0_active_oh1_hi_hi_lo_1,active_active0_active_oh1_hi_lo_1,active_active0_active_oh1_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_lo_lo_1 = {1'h0,active_active0_active_oh_1[1],2'h0,1'h0,
- active_active0_active_oh_1[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_lo_lo_1 = {1'h0,active_active0_active_oh_1[3],2'h0,1'h0,
- active_active0_active_oh_1[2],2'h0,active_active0_active_oh2_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_hi_lo_1 = {1'h0,active_active0_active_oh_1[5],2'h0,1'h0,
- active_active0_active_oh_1[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh2_lo_1 = {1'h0,active_active0_active_oh_1[7],2'h0,1'h0,active_active0_active_oh_1[
- 6],2'h0,active_active0_active_oh2_lo_hi_lo_1,active_active0_active_oh2_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_lo_lo_1 = {1'h0,active_active0_active_oh_1[9],2'h0,1'h0,
- active_active0_active_oh_1[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_hi_lo_1 = {1'h0,active_active0_active_oh_1[11],2'h0,1'h0,
- active_active0_active_oh_1[10],2'h0,active_active0_active_oh2_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_hi_lo_1 = {1'h0,active_active0_active_oh_1[13],2'h0,1'h0,
- active_active0_active_oh_1[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh2_1 = {1'h0,active_active0_active_oh_1[15],2'h0,1'h0,active_active0_active_oh_1[14
- ],2'h0,active_active0_active_oh2_hi_hi_lo_1,active_active0_active_oh2_hi_lo_1,active_active0_active_oh2_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_lo_lo_1 = {active_active0_active_oh_1[3],3'h0,active_active0_active_oh_1[2],3'h0
- ,active_active0_active_oh_1[1],3'h0,active_active0_active_oh_1[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh3_lo_1 = {active_active0_active_oh_1[7],3'h0,active_active0_active_oh_1[6],3'h0,
- active_active0_active_oh_1[5],3'h0,active_active0_active_oh_1[4],3'h0,active_active0_active_oh3_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_hi_lo_1 = {active_active0_active_oh_1[11],3'h0,active_active0_active_oh_1[10],3'h0
- ,active_active0_active_oh_1[9],3'h0,active_active0_active_oh_1[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh3_1 = {active_active0_active_oh_1[15],3'h0,active_active0_active_oh_1[14],3'h0,
- active_active0_active_oh_1[13],3'h0,active_active0_active_oh_1[12],3'h0,active_active0_active_oh3_hi_lo_1,
- active_active0_active_oh3_lo_1}; // @[Cat.scala 31:58]
- wire [1:0] active_active0_active_idx_1 = value_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active0_active_active_T_35 = _last_T & active_active0_active_idx_1 == 2'h0 | value_m & _active_active0_T
- [2:0] <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active0_active_active_T_36 = _active_active0_active_active_T_35 ? active_active0_active_oh0_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active0_active_active_T_42 = _last_T & active_active0_active_idx_1 == 2'h1 | value_m & _active_active0_T
- [2:0] <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active0_active_active_T_43 = _active_active0_active_active_T_42 ? active_active0_active_oh1_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_44 = _active_active0_active_active_T_36 |
- _active_active0_active_active_T_43; // @[VCommon.scala 107:68]
- wire _active_active0_active_active_T_50 = _last_T & active_active0_active_idx_1 == 2'h2 | value_m & _active_active0_T
- [2:0] <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active0_active_active_T_51 = _active_active0_active_active_T_50 ? active_active0_active_oh2_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_52 = _active_active0_active_active_T_44 |
- _active_active0_active_active_T_51; // @[VCommon.scala 108:68]
- wire _active_active0_active_active_T_58 = _last_T & active_active0_active_idx_1 == 2'h3 | value_m & _active_active0_T
- [2:0] <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active0_active_active_T_59 = _active_active0_active_active_T_58 ? active_active0_active_oh3_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active0_active_active_1 = _active_active0_active_active_T_52 | _active_active0_active_active_T_59; // @[VCommon.scala 109:68]
- wire [63:0] _active_active0_active_T_11 = value_tin_vt_valid ? active_active0_active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active0_active_T_12 = _active_active0_active_T_5 | _active_active0_active_T_11; // @[VAlu.scala 249:74]
- wire [3:0] active_active0_active_oh_shiftAmount_2 = value_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active0_active_oh_2 = 16'h1 << active_active0_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
- wire [15:0] active_active0_active_oh0_lo_lo_2 = {3'h0,active_active0_active_oh_2[3],3'h0,active_active0_active_oh_2[2]
- ,3'h0,active_active0_active_oh_2[1],3'h0,active_active0_active_oh_2[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh0_lo_2 = {3'h0,active_active0_active_oh_2[7],3'h0,active_active0_active_oh_2[6],3'h0
- ,active_active0_active_oh_2[5],3'h0,active_active0_active_oh_2[4],active_active0_active_oh0_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh0_hi_lo_2 = {3'h0,active_active0_active_oh_2[11],3'h0,active_active0_active_oh_2[
- 10],3'h0,active_active0_active_oh_2[9],3'h0,active_active0_active_oh_2[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh0_2 = {3'h0,active_active0_active_oh_2[15],3'h0,active_active0_active_oh_2[14],3'h0
- ,active_active0_active_oh_2[13],3'h0,active_active0_active_oh_2[12],active_active0_active_oh0_hi_lo_2,
- active_active0_active_oh0_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_lo_lo_2 = {2'h0,active_active0_active_oh_2[1],1'h0,2'h0,
- active_active0_active_oh_2[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_lo_lo_2 = {2'h0,active_active0_active_oh_2[3],1'h0,2'h0,
- active_active0_active_oh_2[2],1'h0,active_active0_active_oh1_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_hi_lo_2 = {2'h0,active_active0_active_oh_2[5],1'h0,2'h0,
- active_active0_active_oh_2[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh1_lo_2 = {2'h0,active_active0_active_oh_2[7],1'h0,2'h0,active_active0_active_oh_2[
- 6],1'h0,active_active0_active_oh1_lo_hi_lo_2,active_active0_active_oh1_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_lo_lo_2 = {2'h0,active_active0_active_oh_2[9],1'h0,2'h0,
- active_active0_active_oh_2[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_hi_lo_2 = {2'h0,active_active0_active_oh_2[11],1'h0,2'h0,
- active_active0_active_oh_2[10],1'h0,active_active0_active_oh1_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_hi_lo_2 = {2'h0,active_active0_active_oh_2[13],1'h0,2'h0,
- active_active0_active_oh_2[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh1_2 = {2'h0,active_active0_active_oh_2[15],1'h0,2'h0,active_active0_active_oh_2[14
- ],1'h0,active_active0_active_oh1_hi_hi_lo_2,active_active0_active_oh1_hi_lo_2,active_active0_active_oh1_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_lo_lo_2 = {1'h0,active_active0_active_oh_2[1],2'h0,1'h0,
- active_active0_active_oh_2[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_lo_lo_2 = {1'h0,active_active0_active_oh_2[3],2'h0,1'h0,
- active_active0_active_oh_2[2],2'h0,active_active0_active_oh2_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_hi_lo_2 = {1'h0,active_active0_active_oh_2[5],2'h0,1'h0,
- active_active0_active_oh_2[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh2_lo_2 = {1'h0,active_active0_active_oh_2[7],2'h0,1'h0,active_active0_active_oh_2[
- 6],2'h0,active_active0_active_oh2_lo_hi_lo_2,active_active0_active_oh2_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_lo_lo_2 = {1'h0,active_active0_active_oh_2[9],2'h0,1'h0,
- active_active0_active_oh_2[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_hi_lo_2 = {1'h0,active_active0_active_oh_2[11],2'h0,1'h0,
- active_active0_active_oh_2[10],2'h0,active_active0_active_oh2_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_hi_lo_2 = {1'h0,active_active0_active_oh_2[13],2'h0,1'h0,
- active_active0_active_oh_2[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh2_2 = {1'h0,active_active0_active_oh_2[15],2'h0,1'h0,active_active0_active_oh_2[14
- ],2'h0,active_active0_active_oh2_hi_hi_lo_2,active_active0_active_oh2_hi_lo_2,active_active0_active_oh2_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_lo_lo_2 = {active_active0_active_oh_2[3],3'h0,active_active0_active_oh_2[2],3'h0
- ,active_active0_active_oh_2[1],3'h0,active_active0_active_oh_2[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh3_lo_2 = {active_active0_active_oh_2[7],3'h0,active_active0_active_oh_2[6],3'h0,
- active_active0_active_oh_2[5],3'h0,active_active0_active_oh_2[4],3'h0,active_active0_active_oh3_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_hi_lo_2 = {active_active0_active_oh_2[11],3'h0,active_active0_active_oh_2[10],3'h0
- ,active_active0_active_oh_2[9],3'h0,active_active0_active_oh_2[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh3_2 = {active_active0_active_oh_2[15],3'h0,active_active0_active_oh_2[14],3'h0,
- active_active0_active_oh_2[13],3'h0,active_active0_active_oh_2[12],3'h0,active_active0_active_oh3_hi_lo_2,
- active_active0_active_oh3_lo_2}; // @[Cat.scala 31:58]
- wire [1:0] active_active0_active_idx_2 = value_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active0_active_active_T_65 = _last_T & active_active0_active_idx_2 == 2'h0 | value_m & _active_active0_T
- [2:0] <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active0_active_active_T_66 = _active_active0_active_active_T_65 ? active_active0_active_oh0_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active0_active_active_T_72 = _last_T & active_active0_active_idx_2 == 2'h1 | value_m & _active_active0_T
- [2:0] <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active0_active_active_T_73 = _active_active0_active_active_T_72 ? active_active0_active_oh1_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_74 = _active_active0_active_active_T_66 |
- _active_active0_active_active_T_73; // @[VCommon.scala 107:68]
- wire _active_active0_active_active_T_80 = _last_T & active_active0_active_idx_2 == 2'h2 | value_m & _active_active0_T
- [2:0] <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active0_active_active_T_81 = _active_active0_active_active_T_80 ? active_active0_active_oh2_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_82 = _active_active0_active_active_T_74 |
- _active_active0_active_active_T_81; // @[VCommon.scala 108:68]
- wire _active_active0_active_active_T_88 = _last_T & active_active0_active_idx_2 == 2'h3 | value_m & _active_active0_T
- [2:0] <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active0_active_active_T_89 = _active_active0_active_active_T_88 ? active_active0_active_oh3_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active0_active_active_2 = _active_active0_active_active_T_82 | _active_active0_active_active_T_89; // @[VCommon.scala 109:68]
- wire [63:0] _active_active0_active_T_18 = value_tin_vu_valid ? active_active0_active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active0 = _active_active0_active_T_12 | _active_active0_active_T_18; // @[VAlu.scala 250:74]
- wire _active_active1_active_active_T_5 = _last_T & active_active0_active_idx == 2'h0 | value_m & _step_T_1[2:0] <= 3'h0
- ; // @[VCommon.scala 107:42]
- wire [63:0] _active_active1_active_active_T_6 = _active_active1_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active1_active_active_T_12 = _last_T & active_active0_active_idx == 2'h1 | value_m & _step_T_1[2:0] <= 3'h1
- ; // @[VCommon.scala 108:42]
- wire [63:0] _active_active1_active_active_T_13 = _active_active1_active_active_T_12 ? active_active0_active_oh1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_14 = _active_active1_active_active_T_6 |
- _active_active1_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active1_active_active_T_20 = _last_T & active_active0_active_idx == 2'h2 | value_m & _step_T_1[2:0] <= 3'h2
- ; // @[VCommon.scala 109:42]
- wire [63:0] _active_active1_active_active_T_21 = _active_active1_active_active_T_20 ? active_active0_active_oh2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_22 = _active_active1_active_active_T_14 |
- _active_active1_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active1_active_active_T_28 = _last_T & active_active0_active_idx == 2'h3 | value_m & _step_T_1[2:0] <= 3'h3
- ; // @[VCommon.scala 110:42]
- wire [63:0] _active_active1_active_active_T_29 = _active_active1_active_active_T_28 ? active_active0_active_oh3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active1_active_active = _active_active1_active_active_T_22 | _active_active1_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] _active_active1_active_T_5 = value_tin_vs_valid ? active_active1_active_active : 64'h0; // @[Library.scala 22:8]
- wire _active_active1_active_active_T_35 = _last_T & active_active0_active_idx_1 == 2'h0 | value_m & _step_T_1[2:0]
- <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active1_active_active_T_36 = _active_active1_active_active_T_35 ? active_active0_active_oh0_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active1_active_active_T_42 = _last_T & active_active0_active_idx_1 == 2'h1 | value_m & _step_T_1[2:0]
- <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active1_active_active_T_43 = _active_active1_active_active_T_42 ? active_active0_active_oh1_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_44 = _active_active1_active_active_T_36 |
- _active_active1_active_active_T_43; // @[VCommon.scala 107:68]
- wire _active_active1_active_active_T_50 = _last_T & active_active0_active_idx_1 == 2'h2 | value_m & _step_T_1[2:0]
- <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active1_active_active_T_51 = _active_active1_active_active_T_50 ? active_active0_active_oh2_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_52 = _active_active1_active_active_T_44 |
- _active_active1_active_active_T_51; // @[VCommon.scala 108:68]
- wire _active_active1_active_active_T_58 = _last_T & active_active0_active_idx_1 == 2'h3 | value_m & _step_T_1[2:0]
- <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active1_active_active_T_59 = _active_active1_active_active_T_58 ? active_active0_active_oh3_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active1_active_active_1 = _active_active1_active_active_T_52 | _active_active1_active_active_T_59; // @[VCommon.scala 109:68]
- wire [63:0] _active_active1_active_T_11 = value_tin_vt_valid ? active_active1_active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active1_active_T_12 = _active_active1_active_T_5 | _active_active1_active_T_11; // @[VAlu.scala 249:74]
- wire _active_active1_active_active_T_65 = _last_T & active_active0_active_idx_2 == 2'h0 | value_m & _step_T_1[2:0]
- <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active1_active_active_T_66 = _active_active1_active_active_T_65 ? active_active0_active_oh0_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active1_active_active_T_72 = _last_T & active_active0_active_idx_2 == 2'h1 | value_m & _step_T_1[2:0]
- <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active1_active_active_T_73 = _active_active1_active_active_T_72 ? active_active0_active_oh1_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_74 = _active_active1_active_active_T_66 |
- _active_active1_active_active_T_73; // @[VCommon.scala 107:68]
- wire _active_active1_active_active_T_80 = _last_T & active_active0_active_idx_2 == 2'h2 | value_m & _step_T_1[2:0]
- <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active1_active_active_T_81 = _active_active1_active_active_T_80 ? active_active0_active_oh2_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_82 = _active_active1_active_active_T_74 |
- _active_active1_active_active_T_81; // @[VCommon.scala 108:68]
- wire _active_active1_active_active_T_88 = _last_T & active_active0_active_idx_2 == 2'h3 | value_m & _step_T_1[2:0]
- <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active1_active_active_T_89 = _active_active1_active_active_T_88 ? active_active0_active_oh3_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active1_active_active_2 = _active_active1_active_active_T_82 | _active_active1_active_active_T_89; // @[VCommon.scala 109:68]
- wire [63:0] _active_active1_active_T_18 = value_tin_vu_valid ? active_active1_active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active1 = _active_active1_active_T_12 | _active_active1_active_T_18; // @[VAlu.scala 250:74]
- wire _active_active_T_96 = ~io_out_ready; // @[VCmdq.scala 112:36]
- wire _active_active_T_99 = valid & (~io_out_ready | _T_10); // @[VCmdq.scala 112:32]
- wire [63:0] _active_active_T_101 = _active_active_T_96 ? active_active0 : active_active1; // @[VCmdq.scala 113:29]
- wire [63:0] active_active_12 = _active_active_T_99 ? _active_active_T_101 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_35 = _active_T_34 | active_active_12; // @[VCmdq.scala 114:12]
- wire [63:0] _active_T_36 = _active_T_26 | _active_T_35; // @[VCmdq.scala 127:90]
- wire _GEN_149 = _T_14 & _T_6; // @[VAlu.scala 247:11]
- Fifo4e f ( // @[Fifo4e.scala 24:11]
- .clock(f_clock),
- .reset(f_reset),
- .io_in_ready(f_io_in_ready),
- .io_in_valid(f_io_in_valid),
- .io_in_bits_0_valid(f_io_in_bits_0_valid),
- .io_in_bits_0_bits_tin_op(f_io_in_bits_0_bits_tin_op),
- .io_in_bits_0_bits_tin_f2(f_io_in_bits_0_bits_tin_f2),
- .io_in_bits_0_bits_tin_sz(f_io_in_bits_0_bits_tin_sz),
- .io_in_bits_0_bits_tin_vd_addr(f_io_in_bits_0_bits_tin_vd_addr),
- .io_in_bits_0_bits_tin_ve_addr(f_io_in_bits_0_bits_tin_ve_addr),
- .io_in_bits_0_bits_tin_vs_valid(f_io_in_bits_0_bits_tin_vs_valid),
- .io_in_bits_0_bits_tin_vs_addr(f_io_in_bits_0_bits_tin_vs_addr),
- .io_in_bits_0_bits_tin_vs_tag(f_io_in_bits_0_bits_tin_vs_tag),
- .io_in_bits_0_bits_tin_vt_valid(f_io_in_bits_0_bits_tin_vt_valid),
- .io_in_bits_0_bits_tin_vt_addr(f_io_in_bits_0_bits_tin_vt_addr),
- .io_in_bits_0_bits_tin_vt_tag(f_io_in_bits_0_bits_tin_vt_tag),
- .io_in_bits_0_bits_tin_vu_valid(f_io_in_bits_0_bits_tin_vu_valid),
- .io_in_bits_0_bits_tin_vu_addr(f_io_in_bits_0_bits_tin_vu_addr),
- .io_in_bits_0_bits_tin_vu_tag(f_io_in_bits_0_bits_tin_vu_tag),
- .io_in_bits_0_bits_tin_sv_valid(f_io_in_bits_0_bits_tin_sv_valid),
- .io_in_bits_0_bits_tin_sv_data(f_io_in_bits_0_bits_tin_sv_data),
- .io_in_bits_0_bits_tin_cmdsync(f_io_in_bits_0_bits_tin_cmdsync),
- .io_in_bits_0_bits_m(f_io_in_bits_0_bits_m),
- .io_in_bits_1_valid(f_io_in_bits_1_valid),
- .io_in_bits_1_bits_tin_op(f_io_in_bits_1_bits_tin_op),
- .io_in_bits_1_bits_tin_f2(f_io_in_bits_1_bits_tin_f2),
- .io_in_bits_1_bits_tin_sz(f_io_in_bits_1_bits_tin_sz),
- .io_in_bits_1_bits_tin_vd_addr(f_io_in_bits_1_bits_tin_vd_addr),
- .io_in_bits_1_bits_tin_ve_addr(f_io_in_bits_1_bits_tin_ve_addr),
- .io_in_bits_1_bits_tin_vs_valid(f_io_in_bits_1_bits_tin_vs_valid),
- .io_in_bits_1_bits_tin_vs_addr(f_io_in_bits_1_bits_tin_vs_addr),
- .io_in_bits_1_bits_tin_vs_tag(f_io_in_bits_1_bits_tin_vs_tag),
- .io_in_bits_1_bits_tin_vt_valid(f_io_in_bits_1_bits_tin_vt_valid),
- .io_in_bits_1_bits_tin_vt_addr(f_io_in_bits_1_bits_tin_vt_addr),
- .io_in_bits_1_bits_tin_vt_tag(f_io_in_bits_1_bits_tin_vt_tag),
- .io_in_bits_1_bits_tin_vu_valid(f_io_in_bits_1_bits_tin_vu_valid),
- .io_in_bits_1_bits_tin_vu_addr(f_io_in_bits_1_bits_tin_vu_addr),
- .io_in_bits_1_bits_tin_vu_tag(f_io_in_bits_1_bits_tin_vu_tag),
- .io_in_bits_1_bits_tin_sv_valid(f_io_in_bits_1_bits_tin_sv_valid),
- .io_in_bits_1_bits_tin_sv_data(f_io_in_bits_1_bits_tin_sv_data),
- .io_in_bits_1_bits_tin_cmdsync(f_io_in_bits_1_bits_tin_cmdsync),
- .io_in_bits_1_bits_m(f_io_in_bits_1_bits_m),
- .io_in_bits_2_valid(f_io_in_bits_2_valid),
- .io_in_bits_2_bits_tin_op(f_io_in_bits_2_bits_tin_op),
- .io_in_bits_2_bits_tin_f2(f_io_in_bits_2_bits_tin_f2),
- .io_in_bits_2_bits_tin_sz(f_io_in_bits_2_bits_tin_sz),
- .io_in_bits_2_bits_tin_vd_addr(f_io_in_bits_2_bits_tin_vd_addr),
- .io_in_bits_2_bits_tin_ve_addr(f_io_in_bits_2_bits_tin_ve_addr),
- .io_in_bits_2_bits_tin_vs_valid(f_io_in_bits_2_bits_tin_vs_valid),
- .io_in_bits_2_bits_tin_vs_addr(f_io_in_bits_2_bits_tin_vs_addr),
- .io_in_bits_2_bits_tin_vs_tag(f_io_in_bits_2_bits_tin_vs_tag),
- .io_in_bits_2_bits_tin_vt_valid(f_io_in_bits_2_bits_tin_vt_valid),
- .io_in_bits_2_bits_tin_vt_addr(f_io_in_bits_2_bits_tin_vt_addr),
- .io_in_bits_2_bits_tin_vt_tag(f_io_in_bits_2_bits_tin_vt_tag),
- .io_in_bits_2_bits_tin_vu_valid(f_io_in_bits_2_bits_tin_vu_valid),
- .io_in_bits_2_bits_tin_vu_addr(f_io_in_bits_2_bits_tin_vu_addr),
- .io_in_bits_2_bits_tin_vu_tag(f_io_in_bits_2_bits_tin_vu_tag),
- .io_in_bits_2_bits_tin_sv_valid(f_io_in_bits_2_bits_tin_sv_valid),
- .io_in_bits_2_bits_tin_sv_data(f_io_in_bits_2_bits_tin_sv_data),
- .io_in_bits_2_bits_tin_cmdsync(f_io_in_bits_2_bits_tin_cmdsync),
- .io_in_bits_2_bits_m(f_io_in_bits_2_bits_m),
- .io_in_bits_3_valid(f_io_in_bits_3_valid),
- .io_in_bits_3_bits_tin_op(f_io_in_bits_3_bits_tin_op),
- .io_in_bits_3_bits_tin_f2(f_io_in_bits_3_bits_tin_f2),
- .io_in_bits_3_bits_tin_sz(f_io_in_bits_3_bits_tin_sz),
- .io_in_bits_3_bits_tin_vd_addr(f_io_in_bits_3_bits_tin_vd_addr),
- .io_in_bits_3_bits_tin_ve_addr(f_io_in_bits_3_bits_tin_ve_addr),
- .io_in_bits_3_bits_tin_vs_valid(f_io_in_bits_3_bits_tin_vs_valid),
- .io_in_bits_3_bits_tin_vs_addr(f_io_in_bits_3_bits_tin_vs_addr),
- .io_in_bits_3_bits_tin_vs_tag(f_io_in_bits_3_bits_tin_vs_tag),
- .io_in_bits_3_bits_tin_vt_valid(f_io_in_bits_3_bits_tin_vt_valid),
- .io_in_bits_3_bits_tin_vt_addr(f_io_in_bits_3_bits_tin_vt_addr),
- .io_in_bits_3_bits_tin_vt_tag(f_io_in_bits_3_bits_tin_vt_tag),
- .io_in_bits_3_bits_tin_vu_valid(f_io_in_bits_3_bits_tin_vu_valid),
- .io_in_bits_3_bits_tin_vu_addr(f_io_in_bits_3_bits_tin_vu_addr),
- .io_in_bits_3_bits_tin_vu_tag(f_io_in_bits_3_bits_tin_vu_tag),
- .io_in_bits_3_bits_tin_sv_valid(f_io_in_bits_3_bits_tin_sv_valid),
- .io_in_bits_3_bits_tin_sv_data(f_io_in_bits_3_bits_tin_sv_data),
- .io_in_bits_3_bits_tin_cmdsync(f_io_in_bits_3_bits_tin_cmdsync),
- .io_in_bits_3_bits_m(f_io_in_bits_3_bits_m),
- .io_out_ready(f_io_out_ready),
- .io_out_valid(f_io_out_valid),
- .io_out_bits_tin_op(f_io_out_bits_tin_op),
- .io_out_bits_tin_f2(f_io_out_bits_tin_f2),
- .io_out_bits_tin_sz(f_io_out_bits_tin_sz),
- .io_out_bits_tin_vd_addr(f_io_out_bits_tin_vd_addr),
- .io_out_bits_tin_ve_addr(f_io_out_bits_tin_ve_addr),
- .io_out_bits_tin_vs_valid(f_io_out_bits_tin_vs_valid),
- .io_out_bits_tin_vs_addr(f_io_out_bits_tin_vs_addr),
- .io_out_bits_tin_vs_tag(f_io_out_bits_tin_vs_tag),
- .io_out_bits_tin_vt_valid(f_io_out_bits_tin_vt_valid),
- .io_out_bits_tin_vt_addr(f_io_out_bits_tin_vt_addr),
- .io_out_bits_tin_vt_tag(f_io_out_bits_tin_vt_tag),
- .io_out_bits_tin_vu_valid(f_io_out_bits_tin_vu_valid),
- .io_out_bits_tin_vu_addr(f_io_out_bits_tin_vu_addr),
- .io_out_bits_tin_vu_tag(f_io_out_bits_tin_vu_tag),
- .io_out_bits_tin_sv_valid(f_io_out_bits_tin_sv_valid),
- .io_out_bits_tin_sv_data(f_io_out_bits_tin_sv_data),
- .io_out_bits_tin_cmdsync(f_io_out_bits_tin_cmdsync),
- .io_out_bits_m(f_io_out_bits_m),
- .io_entry_0_valid(f_io_entry_0_valid),
- .io_entry_0_bits_tin_vs_valid(f_io_entry_0_bits_tin_vs_valid),
- .io_entry_0_bits_tin_vs_addr(f_io_entry_0_bits_tin_vs_addr),
- .io_entry_0_bits_tin_vt_valid(f_io_entry_0_bits_tin_vt_valid),
- .io_entry_0_bits_tin_vt_addr(f_io_entry_0_bits_tin_vt_addr),
- .io_entry_0_bits_tin_vu_valid(f_io_entry_0_bits_tin_vu_valid),
- .io_entry_0_bits_tin_vu_addr(f_io_entry_0_bits_tin_vu_addr),
- .io_entry_0_bits_m(f_io_entry_0_bits_m),
- .io_entry_1_valid(f_io_entry_1_valid),
- .io_entry_1_bits_tin_vs_valid(f_io_entry_1_bits_tin_vs_valid),
- .io_entry_1_bits_tin_vs_addr(f_io_entry_1_bits_tin_vs_addr),
- .io_entry_1_bits_tin_vt_valid(f_io_entry_1_bits_tin_vt_valid),
- .io_entry_1_bits_tin_vt_addr(f_io_entry_1_bits_tin_vt_addr),
- .io_entry_1_bits_tin_vu_valid(f_io_entry_1_bits_tin_vu_valid),
- .io_entry_1_bits_tin_vu_addr(f_io_entry_1_bits_tin_vu_addr),
- .io_entry_1_bits_m(f_io_entry_1_bits_m),
- .io_entry_2_valid(f_io_entry_2_valid),
- .io_entry_2_bits_tin_vs_valid(f_io_entry_2_bits_tin_vs_valid),
- .io_entry_2_bits_tin_vs_addr(f_io_entry_2_bits_tin_vs_addr),
- .io_entry_2_bits_tin_vt_valid(f_io_entry_2_bits_tin_vt_valid),
- .io_entry_2_bits_tin_vt_addr(f_io_entry_2_bits_tin_vt_addr),
- .io_entry_2_bits_tin_vu_valid(f_io_entry_2_bits_tin_vu_valid),
- .io_entry_2_bits_tin_vu_addr(f_io_entry_2_bits_tin_vu_addr),
- .io_entry_2_bits_m(f_io_entry_2_bits_m),
- .io_entry_3_valid(f_io_entry_3_valid),
- .io_entry_3_bits_tin_vs_valid(f_io_entry_3_bits_tin_vs_valid),
- .io_entry_3_bits_tin_vs_addr(f_io_entry_3_bits_tin_vs_addr),
- .io_entry_3_bits_tin_vt_valid(f_io_entry_3_bits_tin_vt_valid),
- .io_entry_3_bits_tin_vt_addr(f_io_entry_3_bits_tin_vt_addr),
- .io_entry_3_bits_tin_vu_valid(f_io_entry_3_bits_tin_vu_valid),
- .io_entry_3_bits_tin_vu_addr(f_io_entry_3_bits_tin_vu_addr),
- .io_entry_3_bits_m(f_io_entry_3_bits_m),
- .io_entry_4_valid(f_io_entry_4_valid),
- .io_entry_4_bits_tin_vs_valid(f_io_entry_4_bits_tin_vs_valid),
- .io_entry_4_bits_tin_vs_addr(f_io_entry_4_bits_tin_vs_addr),
- .io_entry_4_bits_tin_vt_valid(f_io_entry_4_bits_tin_vt_valid),
- .io_entry_4_bits_tin_vt_addr(f_io_entry_4_bits_tin_vt_addr),
- .io_entry_4_bits_tin_vu_valid(f_io_entry_4_bits_tin_vu_valid),
- .io_entry_4_bits_tin_vu_addr(f_io_entry_4_bits_tin_vu_addr),
- .io_entry_4_bits_m(f_io_entry_4_bits_m),
- .io_entry_5_valid(f_io_entry_5_valid),
- .io_entry_5_bits_tin_vs_valid(f_io_entry_5_bits_tin_vs_valid),
- .io_entry_5_bits_tin_vs_addr(f_io_entry_5_bits_tin_vs_addr),
- .io_entry_5_bits_tin_vt_valid(f_io_entry_5_bits_tin_vt_valid),
- .io_entry_5_bits_tin_vt_addr(f_io_entry_5_bits_tin_vt_addr),
- .io_entry_5_bits_tin_vu_valid(f_io_entry_5_bits_tin_vu_valid),
- .io_entry_5_bits_tin_vu_addr(f_io_entry_5_bits_tin_vu_addr),
- .io_entry_5_bits_m(f_io_entry_5_bits_m),
- .io_entry_6_valid(f_io_entry_6_valid),
- .io_entry_6_bits_tin_vs_valid(f_io_entry_6_bits_tin_vs_valid),
- .io_entry_6_bits_tin_vs_addr(f_io_entry_6_bits_tin_vs_addr),
- .io_entry_6_bits_tin_vt_valid(f_io_entry_6_bits_tin_vt_valid),
- .io_entry_6_bits_tin_vt_addr(f_io_entry_6_bits_tin_vt_addr),
- .io_entry_6_bits_tin_vu_valid(f_io_entry_6_bits_tin_vu_valid),
- .io_entry_6_bits_tin_vu_addr(f_io_entry_6_bits_tin_vu_addr),
- .io_entry_6_bits_m(f_io_entry_6_bits_m),
- .io_entry_7_valid(f_io_entry_7_valid),
- .io_entry_7_bits_tin_vs_valid(f_io_entry_7_bits_tin_vs_valid),
- .io_entry_7_bits_tin_vs_addr(f_io_entry_7_bits_tin_vs_addr),
- .io_entry_7_bits_tin_vt_valid(f_io_entry_7_bits_tin_vt_valid),
- .io_entry_7_bits_tin_vt_addr(f_io_entry_7_bits_tin_vt_addr),
- .io_entry_7_bits_tin_vu_valid(f_io_entry_7_bits_tin_vu_valid),
- .io_entry_7_bits_tin_vu_addr(f_io_entry_7_bits_tin_vu_addr),
- .io_entry_7_bits_m(f_io_entry_7_bits_m)
- );
- assign io_in_ready = f_io_in_ready; // @[VCmdq.scala 65:15]
- assign io_out_valid = valid; // @[VCmdq.scala 133:16]
- assign io_out_bits_op = value_tin_op; // @[VCmdq.scala 134:15]
- assign io_out_bits_f2 = value_tin_f2; // @[VCmdq.scala 134:15]
- assign io_out_bits_sz = value_tin_sz; // @[VCmdq.scala 134:15]
- assign io_out_bits_vd_addr = value_tin_vd_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_ve_addr = value_tin_ve_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_vs_valid = value_tin_vs_valid; // @[VCmdq.scala 134:15]
- assign io_out_bits_vs_addr = value_tin_vs_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_vs_tag = value_tin_vs_tag; // @[VCmdq.scala 134:15]
- assign io_out_bits_vt_valid = value_tin_vt_valid; // @[VCmdq.scala 134:15]
- assign io_out_bits_vt_addr = value_tin_vt_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_vt_tag = value_tin_vt_tag; // @[VCmdq.scala 134:15]
- assign io_out_bits_vu_valid = value_tin_vu_valid; // @[VCmdq.scala 134:15]
- assign io_out_bits_vu_addr = value_tin_vu_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_vu_tag = value_tin_vu_tag; // @[VCmdq.scala 134:15]
- assign io_out_bits_sv_valid = value_tin_sv_valid; // @[VCmdq.scala 134:15]
- assign io_out_bits_sv_data = value_tin_sv_data; // @[VCmdq.scala 134:15]
- assign io_out_bits_cmdsync = value_tin_cmdsync; // @[VCmdq.scala 134:15]
- assign io_active = active; // @[VCmdq.scala 136:13]
- assign f_clock = clock;
- assign f_reset = reset;
- assign f_io_in_valid = io_in_valid; // @[VCmdq.scala 64:17]
- assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VAlu.scala 186:19 187:12]
- assign f_io_in_bits_0_bits_tin_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 186:19 188:12]
- assign f_io_in_bits_0_bits_tin_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 186:19 189:12]
- assign f_io_in_bits_0_bits_tin_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 191:40 192:14 198:14]
- assign f_io_in_bits_0_bits_tin_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 191:40 193:14 199:14]
- assign f_io_in_bits_0_bits_tin_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_0_bits_tin_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_0_bits_tin_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_0_bits_tin_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_0_bits_tin_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_0_bits_tin_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_0_bits_tin_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_0_bits_tin_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_0_bits_tin_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_0_bits_tin_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_0_bits_tin_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_0_bits_tin_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 186:19 190:17]
- assign f_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VAlu.scala 186:19 187:12]
- assign f_io_in_bits_1_bits_tin_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 186:19 188:12]
- assign f_io_in_bits_1_bits_tin_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 186:19 189:12]
- assign f_io_in_bits_1_bits_tin_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 191:40 192:14 198:14]
- assign f_io_in_bits_1_bits_tin_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 191:40 193:14 199:14]
- assign f_io_in_bits_1_bits_tin_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_1_bits_tin_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_1_bits_tin_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_1_bits_tin_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_1_bits_tin_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_1_bits_tin_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_1_bits_tin_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_1_bits_tin_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_1_bits_tin_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_1_bits_tin_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_1_bits_tin_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_1_bits_tin_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 186:19 190:17]
- assign f_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VAlu.scala 186:19 187:12]
- assign f_io_in_bits_2_bits_tin_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 186:19 188:12]
- assign f_io_in_bits_2_bits_tin_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 186:19 189:12]
- assign f_io_in_bits_2_bits_tin_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 191:40 192:14 198:14]
- assign f_io_in_bits_2_bits_tin_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 191:40 193:14 199:14]
- assign f_io_in_bits_2_bits_tin_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_2_bits_tin_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_2_bits_tin_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_2_bits_tin_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_2_bits_tin_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_2_bits_tin_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_2_bits_tin_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_2_bits_tin_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_2_bits_tin_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_2_bits_tin_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_2_bits_tin_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_2_bits_tin_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 186:19 190:17]
- assign f_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VAlu.scala 186:19 187:12]
- assign f_io_in_bits_3_bits_tin_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 186:19 188:12]
- assign f_io_in_bits_3_bits_tin_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 186:19 189:12]
- assign f_io_in_bits_3_bits_tin_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 191:40 192:14 198:14]
- assign f_io_in_bits_3_bits_tin_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 191:40 193:14 199:14]
- assign f_io_in_bits_3_bits_tin_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_3_bits_tin_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_3_bits_tin_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_3_bits_tin_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_3_bits_tin_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_3_bits_tin_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_3_bits_tin_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_3_bits_tin_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_3_bits_tin_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_3_bits_tin_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_3_bits_tin_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_3_bits_tin_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 186:19 190:17]
- assign f_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_out_ready = ~valid | io_out_ready & last; // @[VCmdq.scala 73:28]
- always @(posedge clock) begin
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_op <= 7'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_op <= f_io_out_bits_tin_op; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_op <= 7'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_f2 <= 3'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_f2 <= f_io_out_bits_tin_f2; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_f2 <= 3'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_sz <= 3'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_sz <= f_io_out_bits_tin_sz; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_sz <= 3'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vd_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vd_addr <= f_io_out_bits_tin_vd_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_vd_addr <= tin_vd_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_vd_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_ve_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_ve_addr <= f_io_out_bits_tin_ve_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_ve_addr <= tin_ve_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_ve_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vs_valid <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vs_valid <= f_io_out_bits_tin_vs_valid; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_vs_valid <= _GEN_71;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vs_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vs_addr <= f_io_out_bits_tin_vs_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_vs_addr <= tin_vs_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_vs_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vs_tag <= 4'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vs_tag <= f_io_out_bits_tin_vs_tag; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_vs_tag <= 4'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vt_valid <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vt_valid <= f_io_out_bits_tin_vt_valid; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_vt_valid <= _GEN_68;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vt_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vt_addr <= f_io_out_bits_tin_vt_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_vt_addr <= tin_vt_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_vt_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vt_tag <= 4'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vt_tag <= f_io_out_bits_tin_vt_tag; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_vt_tag <= 4'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vu_valid <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vu_valid <= f_io_out_bits_tin_vu_valid; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_vu_valid <= _GEN_65;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vu_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vu_addr <= f_io_out_bits_tin_vu_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_vu_addr <= tin_vu_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_vu_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vu_tag <= 4'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vu_tag <= f_io_out_bits_tin_vu_tag; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_vu_tag <= 4'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_sv_valid <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_sv_valid <= f_io_out_bits_tin_sv_valid; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_sv_valid <= _GEN_62;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_sv_data <= 32'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_sv_data <= f_io_out_bits_tin_sv_data; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_sv_data <= 32'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_cmdsync <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_cmdsync <= f_io_out_bits_tin_cmdsync; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_cmdsync <= _GEN_60;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_m <= 1'h0; // @[VCmdq.scala 98:13]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_m <= f_io_out_bits_m; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_m <= _GEN_79;
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (vzip & ~reset & ~(value_tin_ve_addr == _out_vd_addr_T_1)) begin
- $fatal; // @[VAlu.scala 238:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (vzip & ~reset & ~(value_tin_ve_addr == _out_vd_addr_T_1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:238 assert(in.ve.addr === (in.vd.addr + 1.U))\n"); // @[VAlu.scala 238:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_14 & _T_6 & ~(_active_active0_T[4:0] <= 5'h4)) begin
- $fatal; // @[VAlu.scala 247:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_14 & _T_6 & ~(_active_active0_T[4:0] <= 5'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:247 assert(step <= 4.U)\n"); // @[VAlu.scala 247:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_149 & ~(_active_active0_T[2:0] <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_149 & ~(_active_active0_T[2:0] <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_149 & ~(_active_active0_T[2:0] <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_149 & ~(_active_active0_T[2:0] <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_149 & ~(_active_active0_T[2:0] <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_149 & ~(_active_active0_T[2:0] <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_14 & _T_6 & ~(_step_T_1 <= 5'h4)) begin
- $fatal; // @[VAlu.scala 247:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_14 & _T_6 & ~(_step_T_1 <= 5'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:247 assert(step <= 4.U)\n"); // @[VAlu.scala 247:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_149 & ~(_step_T_1[2:0] <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_149 & ~(_step_T_1[2:0] <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_149 & ~(_step_T_1[2:0] <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_149 & ~(_step_T_1[2:0] <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_149 & ~(_step_T_1[2:0] <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_149 & ~(_step_T_1[2:0] <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 118:69]
- active <= 64'h0; // @[VCmdq.scala 123:12]
- end else if (io_in_valid & io_in_ready | _T_9) begin // @[VCmdq.scala 49:23]
- active <= _active_T_36;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 77:43]
- valid <= 1'h0; // @[VCmdq.scala 78:11]
- end else begin
- valid <= f_io_out_valid & f_io_out_ready | _GEN_81;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 77:43]
- step <= 5'h0; // @[VCmdq.scala 80:10]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 81:46]
- step <= 5'h0; // @[VCmdq.scala 82:18 86:12 92:12]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 58:21]
- if (~last) begin
- step <= _step_T_1;
- end else begin
- step <= 5'h0;
- end
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {2{`RANDOM}};
- active = _RAND_0[63:0];
- _RAND_1 = {1{`RANDOM}};
- valid = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- value_tin_op = _RAND_2[6:0];
- _RAND_3 = {1{`RANDOM}};
- value_tin_f2 = _RAND_3[2:0];
- _RAND_4 = {1{`RANDOM}};
- value_tin_sz = _RAND_4[2:0];
- _RAND_5 = {1{`RANDOM}};
- value_tin_vd_addr = _RAND_5[5:0];
- _RAND_6 = {1{`RANDOM}};
- value_tin_ve_addr = _RAND_6[5:0];
- _RAND_7 = {1{`RANDOM}};
- value_tin_vs_valid = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- value_tin_vs_addr = _RAND_8[5:0];
- _RAND_9 = {1{`RANDOM}};
- value_tin_vs_tag = _RAND_9[3:0];
- _RAND_10 = {1{`RANDOM}};
- value_tin_vt_valid = _RAND_10[0:0];
- _RAND_11 = {1{`RANDOM}};
- value_tin_vt_addr = _RAND_11[5:0];
- _RAND_12 = {1{`RANDOM}};
- value_tin_vt_tag = _RAND_12[3:0];
- _RAND_13 = {1{`RANDOM}};
- value_tin_vu_valid = _RAND_13[0:0];
- _RAND_14 = {1{`RANDOM}};
- value_tin_vu_addr = _RAND_14[5:0];
- _RAND_15 = {1{`RANDOM}};
- value_tin_vu_tag = _RAND_15[3:0];
- _RAND_16 = {1{`RANDOM}};
- value_tin_sv_valid = _RAND_16[0:0];
- _RAND_17 = {1{`RANDOM}};
- value_tin_sv_data = _RAND_17[31:0];
- _RAND_18 = {1{`RANDOM}};
- value_tin_cmdsync = _RAND_18[0:0];
- _RAND_19 = {1{`RANDOM}};
- value_m = _RAND_19[0:0];
- _RAND_20 = {1{`RANDOM}};
- step = _RAND_20[4:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- active = 64'h0;
- end
- if (reset) begin
- valid = 1'h0;
- end
- if (reset) begin
- step = 5'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VCmdq_1(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_op,
- input [2:0] io_in_bits_0_bits_f2,
- input [2:0] io_in_bits_0_bits_sz,
- input io_in_bits_0_bits_m,
- input [5:0] io_in_bits_0_bits_vd_addr,
- input [5:0] io_in_bits_0_bits_ve_addr,
- input [5:0] io_in_bits_0_bits_vf_addr,
- input [5:0] io_in_bits_0_bits_vg_addr,
- input io_in_bits_0_bits_vs_valid,
- input [5:0] io_in_bits_0_bits_vs_addr,
- input [3:0] io_in_bits_0_bits_vs_tag,
- input io_in_bits_0_bits_vt_valid,
- input [5:0] io_in_bits_0_bits_vt_addr,
- input [3:0] io_in_bits_0_bits_vt_tag,
- input io_in_bits_0_bits_vu_valid,
- input [5:0] io_in_bits_0_bits_vu_addr,
- input [3:0] io_in_bits_0_bits_vu_tag,
- input io_in_bits_0_bits_vx_valid,
- input [5:0] io_in_bits_0_bits_vx_addr,
- input [3:0] io_in_bits_0_bits_vx_tag,
- input io_in_bits_0_bits_vy_valid,
- input [5:0] io_in_bits_0_bits_vy_addr,
- input [3:0] io_in_bits_0_bits_vy_tag,
- input io_in_bits_0_bits_vz_valid,
- input [5:0] io_in_bits_0_bits_vz_addr,
- input [3:0] io_in_bits_0_bits_vz_tag,
- input io_in_bits_0_bits_sv_valid,
- input [31:0] io_in_bits_0_bits_sv_data,
- input io_in_bits_0_bits_cmdsync,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_op,
- input [2:0] io_in_bits_1_bits_f2,
- input [2:0] io_in_bits_1_bits_sz,
- input io_in_bits_1_bits_m,
- input [5:0] io_in_bits_1_bits_vd_addr,
- input [5:0] io_in_bits_1_bits_ve_addr,
- input [5:0] io_in_bits_1_bits_vf_addr,
- input [5:0] io_in_bits_1_bits_vg_addr,
- input io_in_bits_1_bits_vs_valid,
- input [5:0] io_in_bits_1_bits_vs_addr,
- input [3:0] io_in_bits_1_bits_vs_tag,
- input io_in_bits_1_bits_vt_valid,
- input [5:0] io_in_bits_1_bits_vt_addr,
- input [3:0] io_in_bits_1_bits_vt_tag,
- input io_in_bits_1_bits_vu_valid,
- input [5:0] io_in_bits_1_bits_vu_addr,
- input [3:0] io_in_bits_1_bits_vu_tag,
- input io_in_bits_1_bits_vx_valid,
- input [5:0] io_in_bits_1_bits_vx_addr,
- input [3:0] io_in_bits_1_bits_vx_tag,
- input io_in_bits_1_bits_vy_valid,
- input [5:0] io_in_bits_1_bits_vy_addr,
- input [3:0] io_in_bits_1_bits_vy_tag,
- input io_in_bits_1_bits_vz_valid,
- input [5:0] io_in_bits_1_bits_vz_addr,
- input [3:0] io_in_bits_1_bits_vz_tag,
- input io_in_bits_1_bits_sv_valid,
- input [31:0] io_in_bits_1_bits_sv_data,
- input io_in_bits_1_bits_cmdsync,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_op,
- input [2:0] io_in_bits_2_bits_f2,
- input [2:0] io_in_bits_2_bits_sz,
- input io_in_bits_2_bits_m,
- input [5:0] io_in_bits_2_bits_vd_addr,
- input [5:0] io_in_bits_2_bits_ve_addr,
- input [5:0] io_in_bits_2_bits_vf_addr,
- input [5:0] io_in_bits_2_bits_vg_addr,
- input io_in_bits_2_bits_vs_valid,
- input [5:0] io_in_bits_2_bits_vs_addr,
- input [3:0] io_in_bits_2_bits_vs_tag,
- input io_in_bits_2_bits_vt_valid,
- input [5:0] io_in_bits_2_bits_vt_addr,
- input [3:0] io_in_bits_2_bits_vt_tag,
- input io_in_bits_2_bits_vu_valid,
- input [5:0] io_in_bits_2_bits_vu_addr,
- input [3:0] io_in_bits_2_bits_vu_tag,
- input io_in_bits_2_bits_vx_valid,
- input [5:0] io_in_bits_2_bits_vx_addr,
- input [3:0] io_in_bits_2_bits_vx_tag,
- input io_in_bits_2_bits_vy_valid,
- input [5:0] io_in_bits_2_bits_vy_addr,
- input [3:0] io_in_bits_2_bits_vy_tag,
- input io_in_bits_2_bits_vz_valid,
- input [5:0] io_in_bits_2_bits_vz_addr,
- input [3:0] io_in_bits_2_bits_vz_tag,
- input io_in_bits_2_bits_sv_valid,
- input [31:0] io_in_bits_2_bits_sv_data,
- input io_in_bits_2_bits_cmdsync,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_op,
- input [2:0] io_in_bits_3_bits_f2,
- input [2:0] io_in_bits_3_bits_sz,
- input io_in_bits_3_bits_m,
- input [5:0] io_in_bits_3_bits_vd_addr,
- input [5:0] io_in_bits_3_bits_ve_addr,
- input [5:0] io_in_bits_3_bits_vf_addr,
- input [5:0] io_in_bits_3_bits_vg_addr,
- input io_in_bits_3_bits_vs_valid,
- input [5:0] io_in_bits_3_bits_vs_addr,
- input [3:0] io_in_bits_3_bits_vs_tag,
- input io_in_bits_3_bits_vt_valid,
- input [5:0] io_in_bits_3_bits_vt_addr,
- input [3:0] io_in_bits_3_bits_vt_tag,
- input io_in_bits_3_bits_vu_valid,
- input [5:0] io_in_bits_3_bits_vu_addr,
- input [3:0] io_in_bits_3_bits_vu_tag,
- input io_in_bits_3_bits_vx_valid,
- input [5:0] io_in_bits_3_bits_vx_addr,
- input [3:0] io_in_bits_3_bits_vx_tag,
- input io_in_bits_3_bits_vy_valid,
- input [5:0] io_in_bits_3_bits_vy_addr,
- input [3:0] io_in_bits_3_bits_vy_tag,
- input io_in_bits_3_bits_vz_valid,
- input [5:0] io_in_bits_3_bits_vz_addr,
- input [3:0] io_in_bits_3_bits_vz_tag,
- input io_in_bits_3_bits_sv_valid,
- input [31:0] io_in_bits_3_bits_sv_data,
- input io_in_bits_3_bits_cmdsync,
- input io_out_ready,
- output io_out_valid,
- output [6:0] io_out_bits_op,
- output [2:0] io_out_bits_f2,
- output [2:0] io_out_bits_sz,
- output [5:0] io_out_bits_vd_addr,
- output [5:0] io_out_bits_ve_addr,
- output io_out_bits_vs_valid,
- output [5:0] io_out_bits_vs_addr,
- output [3:0] io_out_bits_vs_tag,
- output io_out_bits_vt_valid,
- output [5:0] io_out_bits_vt_addr,
- output [3:0] io_out_bits_vt_tag,
- output io_out_bits_vu_valid,
- output [5:0] io_out_bits_vu_addr,
- output [3:0] io_out_bits_vu_tag,
- output io_out_bits_sv_valid,
- output [31:0] io_out_bits_sv_data,
- output io_out_bits_cmdsync,
- output [63:0] io_active
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [63:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
-`endif // RANDOMIZE_REG_INIT
- wire f_clock; // @[Fifo4e.scala 24:11]
- wire f_reset; // @[Fifo4e.scala 24:11]
- wire f_io_in_ready; // @[Fifo4e.scala 24:11]
- wire f_io_in_valid; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_0_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_0_bits_tin_f2; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_0_bits_tin_sz; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_ve_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_0_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_0_bits_tin_vt_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_0_bits_tin_vu_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_tin_sv_valid; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_0_bits_tin_sv_data; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_tin_cmdsync; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_1_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_1_bits_tin_f2; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_1_bits_tin_sz; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_ve_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_1_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_1_bits_tin_vt_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_1_bits_tin_vu_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_tin_sv_valid; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_1_bits_tin_sv_data; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_tin_cmdsync; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_2_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_2_bits_tin_f2; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_2_bits_tin_sz; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_ve_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_2_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_2_bits_tin_vt_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_2_bits_tin_vu_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_tin_sv_valid; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_2_bits_tin_sv_data; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_tin_cmdsync; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_3_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_3_bits_tin_f2; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_in_bits_3_bits_tin_sz; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_ve_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_3_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_3_bits_tin_vt_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_3_bits_tin_vu_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_tin_sv_valid; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_3_bits_tin_sv_data; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_tin_cmdsync; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_out_ready; // @[Fifo4e.scala 24:11]
- wire f_io_out_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_out_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_out_bits_tin_f2; // @[Fifo4e.scala 24:11]
- wire [2:0] f_io_out_bits_tin_sz; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_ve_addr; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_out_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_out_bits_tin_vt_tag; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_out_bits_tin_vu_tag; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_tin_sv_valid; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_out_bits_tin_sv_data; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_tin_cmdsync; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_0_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_0_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_0_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_1_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_1_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_1_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_2_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_2_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_2_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_3_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_3_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_3_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_4_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_4_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_4_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_5_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_5_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_5_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_6_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_6_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_6_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_7_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_bits_tin_vt_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_7_bits_tin_vt_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_bits_tin_vu_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_7_bits_tin_vu_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_bits_m; // @[Fifo4e.scala 24:11]
- reg [63:0] active; // @[VCmdq.scala 49:23]
- reg valid; // @[VCmdq.scala 51:22]
- reg [6:0] value_tin_op; // @[VCmdq.scala 53:18]
- reg [2:0] value_tin_f2; // @[VCmdq.scala 53:18]
- reg [2:0] value_tin_sz; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_vd_addr; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_ve_addr; // @[VCmdq.scala 53:18]
- reg value_tin_vs_valid; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_vs_addr; // @[VCmdq.scala 53:18]
- reg [3:0] value_tin_vs_tag; // @[VCmdq.scala 53:18]
- reg value_tin_vt_valid; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_vt_addr; // @[VCmdq.scala 53:18]
- reg [3:0] value_tin_vt_tag; // @[VCmdq.scala 53:18]
- reg value_tin_vu_valid; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_vu_addr; // @[VCmdq.scala 53:18]
- reg [3:0] value_tin_vu_tag; // @[VCmdq.scala 53:18]
- reg value_tin_sv_valid; // @[VCmdq.scala 53:18]
- reg [31:0] value_tin_sv_data; // @[VCmdq.scala 53:18]
- reg value_tin_cmdsync; // @[VCmdq.scala 53:18]
- reg value_m; // @[VCmdq.scala 53:18]
- reg [4:0] step; // @[VCmdq.scala 58:21]
- wire vevnodd = value_tin_op == 7'h41 | value_tin_op == 7'h42 | value_tin_op == 7'h43; // @[VAlu.scala 217:60]
- wire vzip = value_tin_op == 7'h44; // @[VAlu.scala 218:22]
- wire _last_T = ~value_m; // @[VAlu.scala 220:16]
- wire last = ~value_m | step == 5'h3; // @[VAlu.scala 220:19]
- wire [5:0] _out_vd_addr_T_1 = value_tin_vd_addr + 6'h1; // @[VAlu.scala 222:31]
- wire [5:0] _out_ve_addr_T_1 = value_tin_ve_addr + 6'h1; // @[VAlu.scala 223:31]
- wire [5:0] _out_vs_addr_T_1 = value_tin_vs_addr + 6'h1; // @[VAlu.scala 224:31]
- wire [5:0] _out_vt_addr_T_1 = value_tin_vt_addr + 6'h1; // @[VAlu.scala 225:31]
- wire [5:0] _out_vu_addr_T_1 = value_tin_vu_addr + 6'h1; // @[VAlu.scala 226:31]
- wire [6:0] _out_vs_addr_T_2 = {{1'd0}, value_tin_vu_addr}; // @[VAlu.scala 230:35]
- wire [5:0] _out_vs_addr_T_5 = value_tin_vs_addr + 6'h2; // @[VAlu.scala 233:35]
- wire [5:0] _out_vt_addr_T_5 = value_tin_vt_addr + 6'h2; // @[VAlu.scala 234:35]
- wire [5:0] _GEN_0 = step == 5'h1 ? _out_vs_addr_T_2[5:0] : _out_vs_addr_T_5; // @[VAlu.scala 229:27 230:21 233:21]
- wire [5:0] _GEN_1 = step == 5'h1 ? _out_vu_addr_T_1 : _out_vt_addr_T_5; // @[VAlu.scala 229:27 231:21 234:21]
- wire [5:0] tin_vu_addr = value_m & vevnodd ? value_tin_vu_addr : _out_vu_addr_T_1; // @[VAlu.scala 226:17 227:25 228:19]
- wire [5:0] tin_vs_addr = value_m & vevnodd ? _GEN_0 : _out_vs_addr_T_1; // @[VAlu.scala 224:17 227:25]
- wire [5:0] tin_vt_addr = value_m & vevnodd ? _GEN_1 : _out_vt_addr_T_1; // @[VAlu.scala 225:17 227:25]
- wire _T_6 = ~reset; // @[VAlu.scala 238:13]
- wire [5:0] _out_vd_addr_T_3 = value_tin_vd_addr + 6'h2; // @[VAlu.scala 239:33]
- wire [5:0] _out_ve_addr_T_3 = value_tin_ve_addr + 6'h2; // @[VAlu.scala 240:33]
- wire [5:0] tin_vd_addr = vzip ? _out_vd_addr_T_3 : _out_vd_addr_T_1; // @[VAlu.scala 222:17 237:17 239:19]
- wire [5:0] tin_ve_addr = vzip ? _out_ve_addr_T_3 : _out_ve_addr_T_1; // @[VAlu.scala 223:17 237:17 240:19]
- wire _T_9 = io_out_valid & io_out_ready; // @[VCmdq.scala 81:29]
- wire _T_10 = ~last; // @[VCmdq.scala 82:11]
- wire [4:0] _step_T_1 = step + 5'h1; // @[VCmdq.scala 86:20]
- wire _GEN_60 = ~last & value_tin_cmdsync; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_62 = ~last & value_tin_sv_valid; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_65 = ~last & value_tin_vu_valid; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_68 = ~last & value_tin_vt_valid; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_71 = ~last & value_tin_vs_valid; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_79 = ~last & value_m; // @[VCmdq.scala 82:18 85:15 91:15]
- wire _GEN_81 = io_out_valid & io_out_ready ? _T_10 : valid; // @[VCmdq.scala 51:22 81:46]
- wire _T_14 = io_in_valid & io_in_ready | _T_9; // @[VCmdq.scala 118:36]
- wire _fvalid_T = f_io_in_valid & f_io_in_ready; // @[VCmdq.scala 119:38]
- wire [3:0] _fvalid_T_1 = {f_io_in_bits_3_valid,f_io_in_bits_2_valid,f_io_in_bits_1_valid,f_io_in_bits_0_valid}; // @[Cat.scala 31:58]
- wire [3:0] fvalid = _fvalid_T ? _fvalid_T_1 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount = f_io_in_bits_0_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh = 16'h1 << active_active_oh_shiftAmount; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo = {3'h0,active_active_oh[3],3'h0,active_active_oh[2],3'h0,active_active_oh[1],3'h0
- ,active_active_oh[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo = {3'h0,active_active_oh[7],3'h0,active_active_oh[6],3'h0,active_active_oh[5],3'h0,
- active_active_oh[4],active_active_oh0_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo = {3'h0,active_active_oh[11],3'h0,active_active_oh[10],3'h0,active_active_oh[9],3'h0
- ,active_active_oh[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0 = {3'h0,active_active_oh[15],3'h0,active_active_oh[14],3'h0,active_active_oh[13],3'h0,
- active_active_oh[12],active_active_oh0_hi_lo,active_active_oh0_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo = {2'h0,active_active_oh[1],1'h0,2'h0,active_active_oh[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo = {2'h0,active_active_oh[3],1'h0,2'h0,active_active_oh[2],1'h0,
- active_active_oh1_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo = {2'h0,active_active_oh[5],1'h0,2'h0,active_active_oh[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo = {2'h0,active_active_oh[7],1'h0,2'h0,active_active_oh[6],1'h0,
- active_active_oh1_lo_hi_lo,active_active_oh1_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo = {2'h0,active_active_oh[9],1'h0,2'h0,active_active_oh[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo = {2'h0,active_active_oh[11],1'h0,2'h0,active_active_oh[10],1'h0,
- active_active_oh1_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo = {2'h0,active_active_oh[13],1'h0,2'h0,active_active_oh[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1 = {2'h0,active_active_oh[15],1'h0,2'h0,active_active_oh[14],1'h0,
- active_active_oh1_hi_hi_lo,active_active_oh1_hi_lo,active_active_oh1_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo = {1'h0,active_active_oh[1],2'h0,1'h0,active_active_oh[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo = {1'h0,active_active_oh[3],2'h0,1'h0,active_active_oh[2],2'h0,
- active_active_oh2_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo = {1'h0,active_active_oh[5],2'h0,1'h0,active_active_oh[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo = {1'h0,active_active_oh[7],2'h0,1'h0,active_active_oh[6],2'h0,
- active_active_oh2_lo_hi_lo,active_active_oh2_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo = {1'h0,active_active_oh[9],2'h0,1'h0,active_active_oh[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo = {1'h0,active_active_oh[11],2'h0,1'h0,active_active_oh[10],2'h0,
- active_active_oh2_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo = {1'h0,active_active_oh[13],2'h0,1'h0,active_active_oh[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2 = {1'h0,active_active_oh[15],2'h0,1'h0,active_active_oh[14],2'h0,
- active_active_oh2_hi_hi_lo,active_active_oh2_hi_lo,active_active_oh2_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo = {active_active_oh[3],3'h0,active_active_oh[2],3'h0,active_active_oh[1],3'h0,
- active_active_oh[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo = {active_active_oh[7],3'h0,active_active_oh[6],3'h0,active_active_oh[5],3'h0,
- active_active_oh[4],3'h0,active_active_oh3_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo = {active_active_oh[11],3'h0,active_active_oh[10],3'h0,active_active_oh[9],3'h0,
- active_active_oh[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3 = {active_active_oh[15],3'h0,active_active_oh[14],3'h0,active_active_oh[13],3'h0,
- active_active_oh[12],3'h0,active_active_oh3_hi_lo,active_active_oh3_lo}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx = f_io_in_bits_0_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T = ~f_io_in_bits_0_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_4 = f_io_in_bits_0_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_5 = ~f_io_in_bits_0_bits_m & active_active_idx == 2'h0 | f_io_in_bits_0_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_6 = _active_active_active_T_5 ? active_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_12 = _active_active_active_T & active_active_idx == 2'h1 | _active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_13 = _active_active_active_T_12 ? active_active_oh1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_14 = _active_active_active_T_6 | _active_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active_active_T_20 = _active_active_active_T & active_active_idx == 2'h2 | _active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_21 = _active_active_active_T_20 ? active_active_oh2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_22 = _active_active_active_T_14 | _active_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active_active_T_28 = _active_active_active_T & active_active_idx == 2'h3 | _active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_29 = _active_active_active_T_28 ? active_active_oh3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active = _active_active_active_T_22 | _active_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_4 = f_io_in_bits_0_bits_tin_vs_valid ? active_active_active : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount_1 = f_io_in_bits_0_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_1 = 16'h1 << active_active_oh_shiftAmount_1; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_1 = {3'h0,active_active_oh_1[3],3'h0,active_active_oh_1[2],3'h0,active_active_oh_1
- [1],3'h0,active_active_oh_1[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_1 = {3'h0,active_active_oh_1[7],3'h0,active_active_oh_1[6],3'h0,active_active_oh_1[5]
- ,3'h0,active_active_oh_1[4],active_active_oh0_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_1 = {3'h0,active_active_oh_1[11],3'h0,active_active_oh_1[10],3'h0,
- active_active_oh_1[9],3'h0,active_active_oh_1[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_1 = {3'h0,active_active_oh_1[15],3'h0,active_active_oh_1[14],3'h0,active_active_oh_1[13]
- ,3'h0,active_active_oh_1[12],active_active_oh0_hi_lo_1,active_active_oh0_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_1 = {2'h0,active_active_oh_1[1],1'h0,2'h0,active_active_oh_1[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_1 = {2'h0,active_active_oh_1[3],1'h0,2'h0,active_active_oh_1[2],1'h0,
- active_active_oh1_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_1 = {2'h0,active_active_oh_1[5],1'h0,2'h0,active_active_oh_1[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_1 = {2'h0,active_active_oh_1[7],1'h0,2'h0,active_active_oh_1[6],1'h0,
- active_active_oh1_lo_hi_lo_1,active_active_oh1_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_1 = {2'h0,active_active_oh_1[9],1'h0,2'h0,active_active_oh_1[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_1 = {2'h0,active_active_oh_1[11],1'h0,2'h0,active_active_oh_1[10],1'h0,
- active_active_oh1_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_1 = {2'h0,active_active_oh_1[13],1'h0,2'h0,active_active_oh_1[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_1 = {2'h0,active_active_oh_1[15],1'h0,2'h0,active_active_oh_1[14],1'h0,
- active_active_oh1_hi_hi_lo_1,active_active_oh1_hi_lo_1,active_active_oh1_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_1 = {1'h0,active_active_oh_1[1],2'h0,1'h0,active_active_oh_1[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_1 = {1'h0,active_active_oh_1[3],2'h0,1'h0,active_active_oh_1[2],2'h0,
- active_active_oh2_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_1 = {1'h0,active_active_oh_1[5],2'h0,1'h0,active_active_oh_1[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_1 = {1'h0,active_active_oh_1[7],2'h0,1'h0,active_active_oh_1[6],2'h0,
- active_active_oh2_lo_hi_lo_1,active_active_oh2_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_1 = {1'h0,active_active_oh_1[9],2'h0,1'h0,active_active_oh_1[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_1 = {1'h0,active_active_oh_1[11],2'h0,1'h0,active_active_oh_1[10],2'h0,
- active_active_oh2_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_1 = {1'h0,active_active_oh_1[13],2'h0,1'h0,active_active_oh_1[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_1 = {1'h0,active_active_oh_1[15],2'h0,1'h0,active_active_oh_1[14],2'h0,
- active_active_oh2_hi_hi_lo_1,active_active_oh2_hi_lo_1,active_active_oh2_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_1 = {active_active_oh_1[3],3'h0,active_active_oh_1[2],3'h0,active_active_oh_1[1],3'h0
- ,active_active_oh_1[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_1 = {active_active_oh_1[7],3'h0,active_active_oh_1[6],3'h0,active_active_oh_1[5],3'h0
- ,active_active_oh_1[4],3'h0,active_active_oh3_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_1 = {active_active_oh_1[11],3'h0,active_active_oh_1[10],3'h0,active_active_oh_1[9]
- ,3'h0,active_active_oh_1[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_1 = {active_active_oh_1[15],3'h0,active_active_oh_1[14],3'h0,active_active_oh_1[13],3'h0
- ,active_active_oh_1[12],3'h0,active_active_oh3_hi_lo_1,active_active_oh3_lo_1}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_1 = f_io_in_bits_0_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_35 = ~f_io_in_bits_0_bits_m & active_active_idx_1 == 2'h0 | f_io_in_bits_0_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_36 = _active_active_active_T_35 ? active_active_oh0_1 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_42 = _active_active_active_T & active_active_idx_1 == 2'h1 | _active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_43 = _active_active_active_T_42 ? active_active_oh1_1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_44 = _active_active_active_T_36 | _active_active_active_T_43; // @[VCommon.scala 107:68]
- wire _active_active_active_T_50 = _active_active_active_T & active_active_idx_1 == 2'h2 | _active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_51 = _active_active_active_T_50 ? active_active_oh2_1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_52 = _active_active_active_T_44 | _active_active_active_T_51; // @[VCommon.scala 108:68]
- wire _active_active_active_T_58 = _active_active_active_T & active_active_idx_1 == 2'h3 | _active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_59 = _active_active_active_T_58 ? active_active_oh3_1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_1 = _active_active_active_T_52 | _active_active_active_T_59; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_9 = f_io_in_bits_0_bits_tin_vt_valid ? active_active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_T_10 = _active_active_T_4 | _active_active_T_9; // @[VAlu.scala 249:74]
- wire [3:0] active_active_oh_shiftAmount_2 = f_io_in_bits_0_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_2 = 16'h1 << active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_2 = {3'h0,active_active_oh_2[3],3'h0,active_active_oh_2[2],3'h0,active_active_oh_2
- [1],3'h0,active_active_oh_2[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_2 = {3'h0,active_active_oh_2[7],3'h0,active_active_oh_2[6],3'h0,active_active_oh_2[5]
- ,3'h0,active_active_oh_2[4],active_active_oh0_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_2 = {3'h0,active_active_oh_2[11],3'h0,active_active_oh_2[10],3'h0,
- active_active_oh_2[9],3'h0,active_active_oh_2[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_2 = {3'h0,active_active_oh_2[15],3'h0,active_active_oh_2[14],3'h0,active_active_oh_2[13]
- ,3'h0,active_active_oh_2[12],active_active_oh0_hi_lo_2,active_active_oh0_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_2 = {2'h0,active_active_oh_2[1],1'h0,2'h0,active_active_oh_2[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_2 = {2'h0,active_active_oh_2[3],1'h0,2'h0,active_active_oh_2[2],1'h0,
- active_active_oh1_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_2 = {2'h0,active_active_oh_2[5],1'h0,2'h0,active_active_oh_2[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_2 = {2'h0,active_active_oh_2[7],1'h0,2'h0,active_active_oh_2[6],1'h0,
- active_active_oh1_lo_hi_lo_2,active_active_oh1_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_2 = {2'h0,active_active_oh_2[9],1'h0,2'h0,active_active_oh_2[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_2 = {2'h0,active_active_oh_2[11],1'h0,2'h0,active_active_oh_2[10],1'h0,
- active_active_oh1_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_2 = {2'h0,active_active_oh_2[13],1'h0,2'h0,active_active_oh_2[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_2 = {2'h0,active_active_oh_2[15],1'h0,2'h0,active_active_oh_2[14],1'h0,
- active_active_oh1_hi_hi_lo_2,active_active_oh1_hi_lo_2,active_active_oh1_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_2 = {1'h0,active_active_oh_2[1],2'h0,1'h0,active_active_oh_2[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_2 = {1'h0,active_active_oh_2[3],2'h0,1'h0,active_active_oh_2[2],2'h0,
- active_active_oh2_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_2 = {1'h0,active_active_oh_2[5],2'h0,1'h0,active_active_oh_2[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_2 = {1'h0,active_active_oh_2[7],2'h0,1'h0,active_active_oh_2[6],2'h0,
- active_active_oh2_lo_hi_lo_2,active_active_oh2_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_2 = {1'h0,active_active_oh_2[9],2'h0,1'h0,active_active_oh_2[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_2 = {1'h0,active_active_oh_2[11],2'h0,1'h0,active_active_oh_2[10],2'h0,
- active_active_oh2_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_2 = {1'h0,active_active_oh_2[13],2'h0,1'h0,active_active_oh_2[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_2 = {1'h0,active_active_oh_2[15],2'h0,1'h0,active_active_oh_2[14],2'h0,
- active_active_oh2_hi_hi_lo_2,active_active_oh2_hi_lo_2,active_active_oh2_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_2 = {active_active_oh_2[3],3'h0,active_active_oh_2[2],3'h0,active_active_oh_2[1],3'h0
- ,active_active_oh_2[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_2 = {active_active_oh_2[7],3'h0,active_active_oh_2[6],3'h0,active_active_oh_2[5],3'h0
- ,active_active_oh_2[4],3'h0,active_active_oh3_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_2 = {active_active_oh_2[11],3'h0,active_active_oh_2[10],3'h0,active_active_oh_2[9]
- ,3'h0,active_active_oh_2[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_2 = {active_active_oh_2[15],3'h0,active_active_oh_2[14],3'h0,active_active_oh_2[13],3'h0
- ,active_active_oh_2[12],3'h0,active_active_oh3_hi_lo_2,active_active_oh3_lo_2}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_2 = f_io_in_bits_0_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_65 = ~f_io_in_bits_0_bits_m & active_active_idx_2 == 2'h0 | f_io_in_bits_0_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_66 = _active_active_active_T_65 ? active_active_oh0_2 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_72 = _active_active_active_T & active_active_idx_2 == 2'h1 | _active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_73 = _active_active_active_T_72 ? active_active_oh1_2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_74 = _active_active_active_T_66 | _active_active_active_T_73; // @[VCommon.scala 107:68]
- wire _active_active_active_T_80 = _active_active_active_T & active_active_idx_2 == 2'h2 | _active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_81 = _active_active_active_T_80 ? active_active_oh2_2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_82 = _active_active_active_T_74 | _active_active_active_T_81; // @[VCommon.scala 108:68]
- wire _active_active_active_T_88 = _active_active_active_T & active_active_idx_2 == 2'h3 | _active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_89 = _active_active_active_T_88 ? active_active_oh3_2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_2 = _active_active_active_T_82 | _active_active_active_T_89; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_15 = f_io_in_bits_0_bits_tin_vu_valid ? active_active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active = _active_active_T_10 | _active_active_T_15; // @[VAlu.scala 250:74]
- wire [63:0] _active_T_5 = fvalid[0] ? active_active : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount_3 = f_io_in_bits_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_3 = 16'h1 << active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_3 = {3'h0,active_active_oh_3[3],3'h0,active_active_oh_3[2],3'h0,active_active_oh_3
- [1],3'h0,active_active_oh_3[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_3 = {3'h0,active_active_oh_3[7],3'h0,active_active_oh_3[6],3'h0,active_active_oh_3[5]
- ,3'h0,active_active_oh_3[4],active_active_oh0_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_3 = {3'h0,active_active_oh_3[11],3'h0,active_active_oh_3[10],3'h0,
- active_active_oh_3[9],3'h0,active_active_oh_3[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_3 = {3'h0,active_active_oh_3[15],3'h0,active_active_oh_3[14],3'h0,active_active_oh_3[13]
- ,3'h0,active_active_oh_3[12],active_active_oh0_hi_lo_3,active_active_oh0_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_3 = {2'h0,active_active_oh_3[1],1'h0,2'h0,active_active_oh_3[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_3 = {2'h0,active_active_oh_3[3],1'h0,2'h0,active_active_oh_3[2],1'h0,
- active_active_oh1_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_3 = {2'h0,active_active_oh_3[5],1'h0,2'h0,active_active_oh_3[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_3 = {2'h0,active_active_oh_3[7],1'h0,2'h0,active_active_oh_3[6],1'h0,
- active_active_oh1_lo_hi_lo_3,active_active_oh1_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_3 = {2'h0,active_active_oh_3[9],1'h0,2'h0,active_active_oh_3[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_3 = {2'h0,active_active_oh_3[11],1'h0,2'h0,active_active_oh_3[10],1'h0,
- active_active_oh1_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_3 = {2'h0,active_active_oh_3[13],1'h0,2'h0,active_active_oh_3[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_3 = {2'h0,active_active_oh_3[15],1'h0,2'h0,active_active_oh_3[14],1'h0,
- active_active_oh1_hi_hi_lo_3,active_active_oh1_hi_lo_3,active_active_oh1_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_3 = {1'h0,active_active_oh_3[1],2'h0,1'h0,active_active_oh_3[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_3 = {1'h0,active_active_oh_3[3],2'h0,1'h0,active_active_oh_3[2],2'h0,
- active_active_oh2_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_3 = {1'h0,active_active_oh_3[5],2'h0,1'h0,active_active_oh_3[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_3 = {1'h0,active_active_oh_3[7],2'h0,1'h0,active_active_oh_3[6],2'h0,
- active_active_oh2_lo_hi_lo_3,active_active_oh2_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_3 = {1'h0,active_active_oh_3[9],2'h0,1'h0,active_active_oh_3[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_3 = {1'h0,active_active_oh_3[11],2'h0,1'h0,active_active_oh_3[10],2'h0,
- active_active_oh2_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_3 = {1'h0,active_active_oh_3[13],2'h0,1'h0,active_active_oh_3[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_3 = {1'h0,active_active_oh_3[15],2'h0,1'h0,active_active_oh_3[14],2'h0,
- active_active_oh2_hi_hi_lo_3,active_active_oh2_hi_lo_3,active_active_oh2_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_3 = {active_active_oh_3[3],3'h0,active_active_oh_3[2],3'h0,active_active_oh_3[1],3'h0
- ,active_active_oh_3[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_3 = {active_active_oh_3[7],3'h0,active_active_oh_3[6],3'h0,active_active_oh_3[5],3'h0
- ,active_active_oh_3[4],3'h0,active_active_oh3_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_3 = {active_active_oh_3[11],3'h0,active_active_oh_3[10],3'h0,active_active_oh_3[9]
- ,3'h0,active_active_oh_3[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_3 = {active_active_oh_3[15],3'h0,active_active_oh_3[14],3'h0,active_active_oh_3[13],3'h0
- ,active_active_oh_3[12],3'h0,active_active_oh3_hi_lo_3,active_active_oh3_lo_3}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_3 = f_io_in_bits_1_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_90 = ~f_io_in_bits_1_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_94 = f_io_in_bits_1_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_95 = ~f_io_in_bits_1_bits_m & active_active_idx_3 == 2'h0 | f_io_in_bits_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_96 = _active_active_active_T_95 ? active_active_oh0_3 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_102 = _active_active_active_T_90 & active_active_idx_3 == 2'h1 |
- _active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_103 = _active_active_active_T_102 ? active_active_oh1_3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_104 = _active_active_active_T_96 | _active_active_active_T_103; // @[VCommon.scala 107:68]
- wire _active_active_active_T_110 = _active_active_active_T_90 & active_active_idx_3 == 2'h2 |
- _active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_111 = _active_active_active_T_110 ? active_active_oh2_3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_112 = _active_active_active_T_104 | _active_active_active_T_111; // @[VCommon.scala 108:68]
- wire _active_active_active_T_118 = _active_active_active_T_90 & active_active_idx_3 == 2'h3 |
- _active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_119 = _active_active_active_T_118 ? active_active_oh3_3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_3 = _active_active_active_T_112 | _active_active_active_T_119; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_20 = f_io_in_bits_1_bits_tin_vs_valid ? active_active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount_4 = f_io_in_bits_1_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_4 = 16'h1 << active_active_oh_shiftAmount_4; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_4 = {3'h0,active_active_oh_4[3],3'h0,active_active_oh_4[2],3'h0,active_active_oh_4
- [1],3'h0,active_active_oh_4[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_4 = {3'h0,active_active_oh_4[7],3'h0,active_active_oh_4[6],3'h0,active_active_oh_4[5]
- ,3'h0,active_active_oh_4[4],active_active_oh0_lo_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_4 = {3'h0,active_active_oh_4[11],3'h0,active_active_oh_4[10],3'h0,
- active_active_oh_4[9],3'h0,active_active_oh_4[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_4 = {3'h0,active_active_oh_4[15],3'h0,active_active_oh_4[14],3'h0,active_active_oh_4[13]
- ,3'h0,active_active_oh_4[12],active_active_oh0_hi_lo_4,active_active_oh0_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_4 = {2'h0,active_active_oh_4[1],1'h0,2'h0,active_active_oh_4[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_4 = {2'h0,active_active_oh_4[3],1'h0,2'h0,active_active_oh_4[2],1'h0,
- active_active_oh1_lo_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_4 = {2'h0,active_active_oh_4[5],1'h0,2'h0,active_active_oh_4[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_4 = {2'h0,active_active_oh_4[7],1'h0,2'h0,active_active_oh_4[6],1'h0,
- active_active_oh1_lo_hi_lo_4,active_active_oh1_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_4 = {2'h0,active_active_oh_4[9],1'h0,2'h0,active_active_oh_4[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_4 = {2'h0,active_active_oh_4[11],1'h0,2'h0,active_active_oh_4[10],1'h0,
- active_active_oh1_hi_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_4 = {2'h0,active_active_oh_4[13],1'h0,2'h0,active_active_oh_4[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_4 = {2'h0,active_active_oh_4[15],1'h0,2'h0,active_active_oh_4[14],1'h0,
- active_active_oh1_hi_hi_lo_4,active_active_oh1_hi_lo_4,active_active_oh1_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_4 = {1'h0,active_active_oh_4[1],2'h0,1'h0,active_active_oh_4[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_4 = {1'h0,active_active_oh_4[3],2'h0,1'h0,active_active_oh_4[2],2'h0,
- active_active_oh2_lo_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_4 = {1'h0,active_active_oh_4[5],2'h0,1'h0,active_active_oh_4[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_4 = {1'h0,active_active_oh_4[7],2'h0,1'h0,active_active_oh_4[6],2'h0,
- active_active_oh2_lo_hi_lo_4,active_active_oh2_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_4 = {1'h0,active_active_oh_4[9],2'h0,1'h0,active_active_oh_4[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_4 = {1'h0,active_active_oh_4[11],2'h0,1'h0,active_active_oh_4[10],2'h0,
- active_active_oh2_hi_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_4 = {1'h0,active_active_oh_4[13],2'h0,1'h0,active_active_oh_4[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_4 = {1'h0,active_active_oh_4[15],2'h0,1'h0,active_active_oh_4[14],2'h0,
- active_active_oh2_hi_hi_lo_4,active_active_oh2_hi_lo_4,active_active_oh2_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_4 = {active_active_oh_4[3],3'h0,active_active_oh_4[2],3'h0,active_active_oh_4[1],3'h0
- ,active_active_oh_4[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_4 = {active_active_oh_4[7],3'h0,active_active_oh_4[6],3'h0,active_active_oh_4[5],3'h0
- ,active_active_oh_4[4],3'h0,active_active_oh3_lo_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_4 = {active_active_oh_4[11],3'h0,active_active_oh_4[10],3'h0,active_active_oh_4[9]
- ,3'h0,active_active_oh_4[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_4 = {active_active_oh_4[15],3'h0,active_active_oh_4[14],3'h0,active_active_oh_4[13],3'h0
- ,active_active_oh_4[12],3'h0,active_active_oh3_hi_lo_4,active_active_oh3_lo_4}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_4 = f_io_in_bits_1_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_125 = ~f_io_in_bits_1_bits_m & active_active_idx_4 == 2'h0 | f_io_in_bits_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_126 = _active_active_active_T_125 ? active_active_oh0_4 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_132 = _active_active_active_T_90 & active_active_idx_4 == 2'h1 |
- _active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_133 = _active_active_active_T_132 ? active_active_oh1_4 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_134 = _active_active_active_T_126 | _active_active_active_T_133; // @[VCommon.scala 107:68]
- wire _active_active_active_T_140 = _active_active_active_T_90 & active_active_idx_4 == 2'h2 |
- _active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_141 = _active_active_active_T_140 ? active_active_oh2_4 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_142 = _active_active_active_T_134 | _active_active_active_T_141; // @[VCommon.scala 108:68]
- wire _active_active_active_T_148 = _active_active_active_T_90 & active_active_idx_4 == 2'h3 |
- _active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_149 = _active_active_active_T_148 ? active_active_oh3_4 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_4 = _active_active_active_T_142 | _active_active_active_T_149; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_25 = f_io_in_bits_1_bits_tin_vt_valid ? active_active_active_4 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_T_26 = _active_active_T_20 | _active_active_T_25; // @[VAlu.scala 249:74]
- wire [3:0] active_active_oh_shiftAmount_5 = f_io_in_bits_1_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_5 = 16'h1 << active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_5 = {3'h0,active_active_oh_5[3],3'h0,active_active_oh_5[2],3'h0,active_active_oh_5
- [1],3'h0,active_active_oh_5[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_5 = {3'h0,active_active_oh_5[7],3'h0,active_active_oh_5[6],3'h0,active_active_oh_5[5]
- ,3'h0,active_active_oh_5[4],active_active_oh0_lo_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_5 = {3'h0,active_active_oh_5[11],3'h0,active_active_oh_5[10],3'h0,
- active_active_oh_5[9],3'h0,active_active_oh_5[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_5 = {3'h0,active_active_oh_5[15],3'h0,active_active_oh_5[14],3'h0,active_active_oh_5[13]
- ,3'h0,active_active_oh_5[12],active_active_oh0_hi_lo_5,active_active_oh0_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_5 = {2'h0,active_active_oh_5[1],1'h0,2'h0,active_active_oh_5[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_5 = {2'h0,active_active_oh_5[3],1'h0,2'h0,active_active_oh_5[2],1'h0,
- active_active_oh1_lo_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_5 = {2'h0,active_active_oh_5[5],1'h0,2'h0,active_active_oh_5[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_5 = {2'h0,active_active_oh_5[7],1'h0,2'h0,active_active_oh_5[6],1'h0,
- active_active_oh1_lo_hi_lo_5,active_active_oh1_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_5 = {2'h0,active_active_oh_5[9],1'h0,2'h0,active_active_oh_5[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_5 = {2'h0,active_active_oh_5[11],1'h0,2'h0,active_active_oh_5[10],1'h0,
- active_active_oh1_hi_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_5 = {2'h0,active_active_oh_5[13],1'h0,2'h0,active_active_oh_5[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_5 = {2'h0,active_active_oh_5[15],1'h0,2'h0,active_active_oh_5[14],1'h0,
- active_active_oh1_hi_hi_lo_5,active_active_oh1_hi_lo_5,active_active_oh1_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_5 = {1'h0,active_active_oh_5[1],2'h0,1'h0,active_active_oh_5[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_5 = {1'h0,active_active_oh_5[3],2'h0,1'h0,active_active_oh_5[2],2'h0,
- active_active_oh2_lo_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_5 = {1'h0,active_active_oh_5[5],2'h0,1'h0,active_active_oh_5[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_5 = {1'h0,active_active_oh_5[7],2'h0,1'h0,active_active_oh_5[6],2'h0,
- active_active_oh2_lo_hi_lo_5,active_active_oh2_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_5 = {1'h0,active_active_oh_5[9],2'h0,1'h0,active_active_oh_5[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_5 = {1'h0,active_active_oh_5[11],2'h0,1'h0,active_active_oh_5[10],2'h0,
- active_active_oh2_hi_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_5 = {1'h0,active_active_oh_5[13],2'h0,1'h0,active_active_oh_5[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_5 = {1'h0,active_active_oh_5[15],2'h0,1'h0,active_active_oh_5[14],2'h0,
- active_active_oh2_hi_hi_lo_5,active_active_oh2_hi_lo_5,active_active_oh2_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_5 = {active_active_oh_5[3],3'h0,active_active_oh_5[2],3'h0,active_active_oh_5[1],3'h0
- ,active_active_oh_5[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_5 = {active_active_oh_5[7],3'h0,active_active_oh_5[6],3'h0,active_active_oh_5[5],3'h0
- ,active_active_oh_5[4],3'h0,active_active_oh3_lo_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_5 = {active_active_oh_5[11],3'h0,active_active_oh_5[10],3'h0,active_active_oh_5[9]
- ,3'h0,active_active_oh_5[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_5 = {active_active_oh_5[15],3'h0,active_active_oh_5[14],3'h0,active_active_oh_5[13],3'h0
- ,active_active_oh_5[12],3'h0,active_active_oh3_hi_lo_5,active_active_oh3_lo_5}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_5 = f_io_in_bits_1_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_155 = ~f_io_in_bits_1_bits_m & active_active_idx_5 == 2'h0 | f_io_in_bits_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_156 = _active_active_active_T_155 ? active_active_oh0_5 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_162 = _active_active_active_T_90 & active_active_idx_5 == 2'h1 |
- _active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_163 = _active_active_active_T_162 ? active_active_oh1_5 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_164 = _active_active_active_T_156 | _active_active_active_T_163; // @[VCommon.scala 107:68]
- wire _active_active_active_T_170 = _active_active_active_T_90 & active_active_idx_5 == 2'h2 |
- _active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_171 = _active_active_active_T_170 ? active_active_oh2_5 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_172 = _active_active_active_T_164 | _active_active_active_T_171; // @[VCommon.scala 108:68]
- wire _active_active_active_T_178 = _active_active_active_T_90 & active_active_idx_5 == 2'h3 |
- _active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_179 = _active_active_active_T_178 ? active_active_oh3_5 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_5 = _active_active_active_T_172 | _active_active_active_T_179; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_31 = f_io_in_bits_1_bits_tin_vu_valid ? active_active_active_5 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_1 = _active_active_T_26 | _active_active_T_31; // @[VAlu.scala 250:74]
- wire [63:0] _active_T_11 = fvalid[1] ? active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_12 = _active_T_5 | _active_T_11; // @[VCmdq.scala 124:90]
- wire [3:0] active_active_oh_shiftAmount_6 = f_io_in_bits_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_6 = 16'h1 << active_active_oh_shiftAmount_6; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_6 = {3'h0,active_active_oh_6[3],3'h0,active_active_oh_6[2],3'h0,active_active_oh_6
- [1],3'h0,active_active_oh_6[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_6 = {3'h0,active_active_oh_6[7],3'h0,active_active_oh_6[6],3'h0,active_active_oh_6[5]
- ,3'h0,active_active_oh_6[4],active_active_oh0_lo_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_6 = {3'h0,active_active_oh_6[11],3'h0,active_active_oh_6[10],3'h0,
- active_active_oh_6[9],3'h0,active_active_oh_6[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_6 = {3'h0,active_active_oh_6[15],3'h0,active_active_oh_6[14],3'h0,active_active_oh_6[13]
- ,3'h0,active_active_oh_6[12],active_active_oh0_hi_lo_6,active_active_oh0_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_6 = {2'h0,active_active_oh_6[1],1'h0,2'h0,active_active_oh_6[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_6 = {2'h0,active_active_oh_6[3],1'h0,2'h0,active_active_oh_6[2],1'h0,
- active_active_oh1_lo_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_6 = {2'h0,active_active_oh_6[5],1'h0,2'h0,active_active_oh_6[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_6 = {2'h0,active_active_oh_6[7],1'h0,2'h0,active_active_oh_6[6],1'h0,
- active_active_oh1_lo_hi_lo_6,active_active_oh1_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_6 = {2'h0,active_active_oh_6[9],1'h0,2'h0,active_active_oh_6[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_6 = {2'h0,active_active_oh_6[11],1'h0,2'h0,active_active_oh_6[10],1'h0,
- active_active_oh1_hi_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_6 = {2'h0,active_active_oh_6[13],1'h0,2'h0,active_active_oh_6[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_6 = {2'h0,active_active_oh_6[15],1'h0,2'h0,active_active_oh_6[14],1'h0,
- active_active_oh1_hi_hi_lo_6,active_active_oh1_hi_lo_6,active_active_oh1_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_6 = {1'h0,active_active_oh_6[1],2'h0,1'h0,active_active_oh_6[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_6 = {1'h0,active_active_oh_6[3],2'h0,1'h0,active_active_oh_6[2],2'h0,
- active_active_oh2_lo_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_6 = {1'h0,active_active_oh_6[5],2'h0,1'h0,active_active_oh_6[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_6 = {1'h0,active_active_oh_6[7],2'h0,1'h0,active_active_oh_6[6],2'h0,
- active_active_oh2_lo_hi_lo_6,active_active_oh2_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_6 = {1'h0,active_active_oh_6[9],2'h0,1'h0,active_active_oh_6[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_6 = {1'h0,active_active_oh_6[11],2'h0,1'h0,active_active_oh_6[10],2'h0,
- active_active_oh2_hi_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_6 = {1'h0,active_active_oh_6[13],2'h0,1'h0,active_active_oh_6[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_6 = {1'h0,active_active_oh_6[15],2'h0,1'h0,active_active_oh_6[14],2'h0,
- active_active_oh2_hi_hi_lo_6,active_active_oh2_hi_lo_6,active_active_oh2_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_6 = {active_active_oh_6[3],3'h0,active_active_oh_6[2],3'h0,active_active_oh_6[1],3'h0
- ,active_active_oh_6[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_6 = {active_active_oh_6[7],3'h0,active_active_oh_6[6],3'h0,active_active_oh_6[5],3'h0
- ,active_active_oh_6[4],3'h0,active_active_oh3_lo_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_6 = {active_active_oh_6[11],3'h0,active_active_oh_6[10],3'h0,active_active_oh_6[9]
- ,3'h0,active_active_oh_6[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_6 = {active_active_oh_6[15],3'h0,active_active_oh_6[14],3'h0,active_active_oh_6[13],3'h0
- ,active_active_oh_6[12],3'h0,active_active_oh3_hi_lo_6,active_active_oh3_lo_6}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_6 = f_io_in_bits_2_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_180 = ~f_io_in_bits_2_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_184 = f_io_in_bits_2_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_185 = ~f_io_in_bits_2_bits_m & active_active_idx_6 == 2'h0 | f_io_in_bits_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_186 = _active_active_active_T_185 ? active_active_oh0_6 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_192 = _active_active_active_T_180 & active_active_idx_6 == 2'h1 |
- _active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_193 = _active_active_active_T_192 ? active_active_oh1_6 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_194 = _active_active_active_T_186 | _active_active_active_T_193; // @[VCommon.scala 107:68]
- wire _active_active_active_T_200 = _active_active_active_T_180 & active_active_idx_6 == 2'h2 |
- _active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_201 = _active_active_active_T_200 ? active_active_oh2_6 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_202 = _active_active_active_T_194 | _active_active_active_T_201; // @[VCommon.scala 108:68]
- wire _active_active_active_T_208 = _active_active_active_T_180 & active_active_idx_6 == 2'h3 |
- _active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_209 = _active_active_active_T_208 ? active_active_oh3_6 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_6 = _active_active_active_T_202 | _active_active_active_T_209; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_36 = f_io_in_bits_2_bits_tin_vs_valid ? active_active_active_6 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount_7 = f_io_in_bits_2_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_7 = 16'h1 << active_active_oh_shiftAmount_7; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_7 = {3'h0,active_active_oh_7[3],3'h0,active_active_oh_7[2],3'h0,active_active_oh_7
- [1],3'h0,active_active_oh_7[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_7 = {3'h0,active_active_oh_7[7],3'h0,active_active_oh_7[6],3'h0,active_active_oh_7[5]
- ,3'h0,active_active_oh_7[4],active_active_oh0_lo_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_7 = {3'h0,active_active_oh_7[11],3'h0,active_active_oh_7[10],3'h0,
- active_active_oh_7[9],3'h0,active_active_oh_7[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_7 = {3'h0,active_active_oh_7[15],3'h0,active_active_oh_7[14],3'h0,active_active_oh_7[13]
- ,3'h0,active_active_oh_7[12],active_active_oh0_hi_lo_7,active_active_oh0_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_7 = {2'h0,active_active_oh_7[1],1'h0,2'h0,active_active_oh_7[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_7 = {2'h0,active_active_oh_7[3],1'h0,2'h0,active_active_oh_7[2],1'h0,
- active_active_oh1_lo_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_7 = {2'h0,active_active_oh_7[5],1'h0,2'h0,active_active_oh_7[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_7 = {2'h0,active_active_oh_7[7],1'h0,2'h0,active_active_oh_7[6],1'h0,
- active_active_oh1_lo_hi_lo_7,active_active_oh1_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_7 = {2'h0,active_active_oh_7[9],1'h0,2'h0,active_active_oh_7[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_7 = {2'h0,active_active_oh_7[11],1'h0,2'h0,active_active_oh_7[10],1'h0,
- active_active_oh1_hi_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_7 = {2'h0,active_active_oh_7[13],1'h0,2'h0,active_active_oh_7[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_7 = {2'h0,active_active_oh_7[15],1'h0,2'h0,active_active_oh_7[14],1'h0,
- active_active_oh1_hi_hi_lo_7,active_active_oh1_hi_lo_7,active_active_oh1_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_7 = {1'h0,active_active_oh_7[1],2'h0,1'h0,active_active_oh_7[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_7 = {1'h0,active_active_oh_7[3],2'h0,1'h0,active_active_oh_7[2],2'h0,
- active_active_oh2_lo_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_7 = {1'h0,active_active_oh_7[5],2'h0,1'h0,active_active_oh_7[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_7 = {1'h0,active_active_oh_7[7],2'h0,1'h0,active_active_oh_7[6],2'h0,
- active_active_oh2_lo_hi_lo_7,active_active_oh2_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_7 = {1'h0,active_active_oh_7[9],2'h0,1'h0,active_active_oh_7[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_7 = {1'h0,active_active_oh_7[11],2'h0,1'h0,active_active_oh_7[10],2'h0,
- active_active_oh2_hi_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_7 = {1'h0,active_active_oh_7[13],2'h0,1'h0,active_active_oh_7[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_7 = {1'h0,active_active_oh_7[15],2'h0,1'h0,active_active_oh_7[14],2'h0,
- active_active_oh2_hi_hi_lo_7,active_active_oh2_hi_lo_7,active_active_oh2_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_7 = {active_active_oh_7[3],3'h0,active_active_oh_7[2],3'h0,active_active_oh_7[1],3'h0
- ,active_active_oh_7[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_7 = {active_active_oh_7[7],3'h0,active_active_oh_7[6],3'h0,active_active_oh_7[5],3'h0
- ,active_active_oh_7[4],3'h0,active_active_oh3_lo_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_7 = {active_active_oh_7[11],3'h0,active_active_oh_7[10],3'h0,active_active_oh_7[9]
- ,3'h0,active_active_oh_7[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_7 = {active_active_oh_7[15],3'h0,active_active_oh_7[14],3'h0,active_active_oh_7[13],3'h0
- ,active_active_oh_7[12],3'h0,active_active_oh3_hi_lo_7,active_active_oh3_lo_7}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_7 = f_io_in_bits_2_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_215 = ~f_io_in_bits_2_bits_m & active_active_idx_7 == 2'h0 | f_io_in_bits_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_216 = _active_active_active_T_215 ? active_active_oh0_7 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_222 = _active_active_active_T_180 & active_active_idx_7 == 2'h1 |
- _active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_223 = _active_active_active_T_222 ? active_active_oh1_7 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_224 = _active_active_active_T_216 | _active_active_active_T_223; // @[VCommon.scala 107:68]
- wire _active_active_active_T_230 = _active_active_active_T_180 & active_active_idx_7 == 2'h2 |
- _active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_231 = _active_active_active_T_230 ? active_active_oh2_7 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_232 = _active_active_active_T_224 | _active_active_active_T_231; // @[VCommon.scala 108:68]
- wire _active_active_active_T_238 = _active_active_active_T_180 & active_active_idx_7 == 2'h3 |
- _active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_239 = _active_active_active_T_238 ? active_active_oh3_7 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_7 = _active_active_active_T_232 | _active_active_active_T_239; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_41 = f_io_in_bits_2_bits_tin_vt_valid ? active_active_active_7 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_T_42 = _active_active_T_36 | _active_active_T_41; // @[VAlu.scala 249:74]
- wire [3:0] active_active_oh_shiftAmount_8 = f_io_in_bits_2_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_8 = 16'h1 << active_active_oh_shiftAmount_8; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_8 = {3'h0,active_active_oh_8[3],3'h0,active_active_oh_8[2],3'h0,active_active_oh_8
- [1],3'h0,active_active_oh_8[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_8 = {3'h0,active_active_oh_8[7],3'h0,active_active_oh_8[6],3'h0,active_active_oh_8[5]
- ,3'h0,active_active_oh_8[4],active_active_oh0_lo_lo_8}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_8 = {3'h0,active_active_oh_8[11],3'h0,active_active_oh_8[10],3'h0,
- active_active_oh_8[9],3'h0,active_active_oh_8[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_8 = {3'h0,active_active_oh_8[15],3'h0,active_active_oh_8[14],3'h0,active_active_oh_8[13]
- ,3'h0,active_active_oh_8[12],active_active_oh0_hi_lo_8,active_active_oh0_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_8 = {2'h0,active_active_oh_8[1],1'h0,2'h0,active_active_oh_8[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_8 = {2'h0,active_active_oh_8[3],1'h0,2'h0,active_active_oh_8[2],1'h0,
- active_active_oh1_lo_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_8 = {2'h0,active_active_oh_8[5],1'h0,2'h0,active_active_oh_8[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_8 = {2'h0,active_active_oh_8[7],1'h0,2'h0,active_active_oh_8[6],1'h0,
- active_active_oh1_lo_hi_lo_8,active_active_oh1_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_8 = {2'h0,active_active_oh_8[9],1'h0,2'h0,active_active_oh_8[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_8 = {2'h0,active_active_oh_8[11],1'h0,2'h0,active_active_oh_8[10],1'h0,
- active_active_oh1_hi_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_8 = {2'h0,active_active_oh_8[13],1'h0,2'h0,active_active_oh_8[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_8 = {2'h0,active_active_oh_8[15],1'h0,2'h0,active_active_oh_8[14],1'h0,
- active_active_oh1_hi_hi_lo_8,active_active_oh1_hi_lo_8,active_active_oh1_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_8 = {1'h0,active_active_oh_8[1],2'h0,1'h0,active_active_oh_8[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_8 = {1'h0,active_active_oh_8[3],2'h0,1'h0,active_active_oh_8[2],2'h0,
- active_active_oh2_lo_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_8 = {1'h0,active_active_oh_8[5],2'h0,1'h0,active_active_oh_8[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_8 = {1'h0,active_active_oh_8[7],2'h0,1'h0,active_active_oh_8[6],2'h0,
- active_active_oh2_lo_hi_lo_8,active_active_oh2_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_8 = {1'h0,active_active_oh_8[9],2'h0,1'h0,active_active_oh_8[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_8 = {1'h0,active_active_oh_8[11],2'h0,1'h0,active_active_oh_8[10],2'h0,
- active_active_oh2_hi_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_8 = {1'h0,active_active_oh_8[13],2'h0,1'h0,active_active_oh_8[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_8 = {1'h0,active_active_oh_8[15],2'h0,1'h0,active_active_oh_8[14],2'h0,
- active_active_oh2_hi_hi_lo_8,active_active_oh2_hi_lo_8,active_active_oh2_lo_8}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_8 = {active_active_oh_8[3],3'h0,active_active_oh_8[2],3'h0,active_active_oh_8[1],3'h0
- ,active_active_oh_8[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_8 = {active_active_oh_8[7],3'h0,active_active_oh_8[6],3'h0,active_active_oh_8[5],3'h0
- ,active_active_oh_8[4],3'h0,active_active_oh3_lo_lo_8}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_8 = {active_active_oh_8[11],3'h0,active_active_oh_8[10],3'h0,active_active_oh_8[9]
- ,3'h0,active_active_oh_8[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_8 = {active_active_oh_8[15],3'h0,active_active_oh_8[14],3'h0,active_active_oh_8[13],3'h0
- ,active_active_oh_8[12],3'h0,active_active_oh3_hi_lo_8,active_active_oh3_lo_8}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_8 = f_io_in_bits_2_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_245 = ~f_io_in_bits_2_bits_m & active_active_idx_8 == 2'h0 | f_io_in_bits_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_246 = _active_active_active_T_245 ? active_active_oh0_8 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_252 = _active_active_active_T_180 & active_active_idx_8 == 2'h1 |
- _active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_253 = _active_active_active_T_252 ? active_active_oh1_8 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_254 = _active_active_active_T_246 | _active_active_active_T_253; // @[VCommon.scala 107:68]
- wire _active_active_active_T_260 = _active_active_active_T_180 & active_active_idx_8 == 2'h2 |
- _active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_261 = _active_active_active_T_260 ? active_active_oh2_8 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_262 = _active_active_active_T_254 | _active_active_active_T_261; // @[VCommon.scala 108:68]
- wire _active_active_active_T_268 = _active_active_active_T_180 & active_active_idx_8 == 2'h3 |
- _active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_269 = _active_active_active_T_268 ? active_active_oh3_8 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_8 = _active_active_active_T_262 | _active_active_active_T_269; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_47 = f_io_in_bits_2_bits_tin_vu_valid ? active_active_active_8 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_2 = _active_active_T_42 | _active_active_T_47; // @[VAlu.scala 250:74]
- wire [63:0] _active_T_18 = fvalid[2] ? active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_19 = _active_T_12 | _active_T_18; // @[VCmdq.scala 125:90]
- wire [3:0] active_active_oh_shiftAmount_9 = f_io_in_bits_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_9 = 16'h1 << active_active_oh_shiftAmount_9; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_9 = {3'h0,active_active_oh_9[3],3'h0,active_active_oh_9[2],3'h0,active_active_oh_9
- [1],3'h0,active_active_oh_9[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_9 = {3'h0,active_active_oh_9[7],3'h0,active_active_oh_9[6],3'h0,active_active_oh_9[5]
- ,3'h0,active_active_oh_9[4],active_active_oh0_lo_lo_9}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_9 = {3'h0,active_active_oh_9[11],3'h0,active_active_oh_9[10],3'h0,
- active_active_oh_9[9],3'h0,active_active_oh_9[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_9 = {3'h0,active_active_oh_9[15],3'h0,active_active_oh_9[14],3'h0,active_active_oh_9[13]
- ,3'h0,active_active_oh_9[12],active_active_oh0_hi_lo_9,active_active_oh0_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_9 = {2'h0,active_active_oh_9[1],1'h0,2'h0,active_active_oh_9[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_9 = {2'h0,active_active_oh_9[3],1'h0,2'h0,active_active_oh_9[2],1'h0,
- active_active_oh1_lo_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_9 = {2'h0,active_active_oh_9[5],1'h0,2'h0,active_active_oh_9[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_9 = {2'h0,active_active_oh_9[7],1'h0,2'h0,active_active_oh_9[6],1'h0,
- active_active_oh1_lo_hi_lo_9,active_active_oh1_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_9 = {2'h0,active_active_oh_9[9],1'h0,2'h0,active_active_oh_9[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_9 = {2'h0,active_active_oh_9[11],1'h0,2'h0,active_active_oh_9[10],1'h0,
- active_active_oh1_hi_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_9 = {2'h0,active_active_oh_9[13],1'h0,2'h0,active_active_oh_9[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_9 = {2'h0,active_active_oh_9[15],1'h0,2'h0,active_active_oh_9[14],1'h0,
- active_active_oh1_hi_hi_lo_9,active_active_oh1_hi_lo_9,active_active_oh1_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_9 = {1'h0,active_active_oh_9[1],2'h0,1'h0,active_active_oh_9[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_9 = {1'h0,active_active_oh_9[3],2'h0,1'h0,active_active_oh_9[2],2'h0,
- active_active_oh2_lo_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_9 = {1'h0,active_active_oh_9[5],2'h0,1'h0,active_active_oh_9[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_9 = {1'h0,active_active_oh_9[7],2'h0,1'h0,active_active_oh_9[6],2'h0,
- active_active_oh2_lo_hi_lo_9,active_active_oh2_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_9 = {1'h0,active_active_oh_9[9],2'h0,1'h0,active_active_oh_9[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_9 = {1'h0,active_active_oh_9[11],2'h0,1'h0,active_active_oh_9[10],2'h0,
- active_active_oh2_hi_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_9 = {1'h0,active_active_oh_9[13],2'h0,1'h0,active_active_oh_9[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_9 = {1'h0,active_active_oh_9[15],2'h0,1'h0,active_active_oh_9[14],2'h0,
- active_active_oh2_hi_hi_lo_9,active_active_oh2_hi_lo_9,active_active_oh2_lo_9}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_9 = {active_active_oh_9[3],3'h0,active_active_oh_9[2],3'h0,active_active_oh_9[1],3'h0
- ,active_active_oh_9[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_9 = {active_active_oh_9[7],3'h0,active_active_oh_9[6],3'h0,active_active_oh_9[5],3'h0
- ,active_active_oh_9[4],3'h0,active_active_oh3_lo_lo_9}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_9 = {active_active_oh_9[11],3'h0,active_active_oh_9[10],3'h0,active_active_oh_9[9]
- ,3'h0,active_active_oh_9[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_9 = {active_active_oh_9[15],3'h0,active_active_oh_9[14],3'h0,active_active_oh_9[13],3'h0
- ,active_active_oh_9[12],3'h0,active_active_oh3_hi_lo_9,active_active_oh3_lo_9}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_9 = f_io_in_bits_3_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_270 = ~f_io_in_bits_3_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_274 = f_io_in_bits_3_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_275 = ~f_io_in_bits_3_bits_m & active_active_idx_9 == 2'h0 | f_io_in_bits_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_276 = _active_active_active_T_275 ? active_active_oh0_9 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_282 = _active_active_active_T_270 & active_active_idx_9 == 2'h1 |
- _active_active_active_T_274; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_283 = _active_active_active_T_282 ? active_active_oh1_9 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_284 = _active_active_active_T_276 | _active_active_active_T_283; // @[VCommon.scala 107:68]
- wire _active_active_active_T_290 = _active_active_active_T_270 & active_active_idx_9 == 2'h2 |
- _active_active_active_T_274; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_291 = _active_active_active_T_290 ? active_active_oh2_9 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_292 = _active_active_active_T_284 | _active_active_active_T_291; // @[VCommon.scala 108:68]
- wire _active_active_active_T_298 = _active_active_active_T_270 & active_active_idx_9 == 2'h3 |
- _active_active_active_T_274; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_299 = _active_active_active_T_298 ? active_active_oh3_9 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_9 = _active_active_active_T_292 | _active_active_active_T_299; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_52 = f_io_in_bits_3_bits_tin_vs_valid ? active_active_active_9 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount_10 = f_io_in_bits_3_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_10 = 16'h1 << active_active_oh_shiftAmount_10; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_10 = {3'h0,active_active_oh_10[3],3'h0,active_active_oh_10[2],3'h0,
- active_active_oh_10[1],3'h0,active_active_oh_10[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_10 = {3'h0,active_active_oh_10[7],3'h0,active_active_oh_10[6],3'h0,
- active_active_oh_10[5],3'h0,active_active_oh_10[4],active_active_oh0_lo_lo_10}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_10 = {3'h0,active_active_oh_10[11],3'h0,active_active_oh_10[10],3'h0,
- active_active_oh_10[9],3'h0,active_active_oh_10[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_10 = {3'h0,active_active_oh_10[15],3'h0,active_active_oh_10[14],3'h0,active_active_oh_10
- [13],3'h0,active_active_oh_10[12],active_active_oh0_hi_lo_10,active_active_oh0_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_10 = {2'h0,active_active_oh_10[1],1'h0,2'h0,active_active_oh_10[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_10 = {2'h0,active_active_oh_10[3],1'h0,2'h0,active_active_oh_10[2],1'h0,
- active_active_oh1_lo_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_10 = {2'h0,active_active_oh_10[5],1'h0,2'h0,active_active_oh_10[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_10 = {2'h0,active_active_oh_10[7],1'h0,2'h0,active_active_oh_10[6],1'h0,
- active_active_oh1_lo_hi_lo_10,active_active_oh1_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_10 = {2'h0,active_active_oh_10[9],1'h0,2'h0,active_active_oh_10[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_10 = {2'h0,active_active_oh_10[11],1'h0,2'h0,active_active_oh_10[10],1'h0,
- active_active_oh1_hi_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_10 = {2'h0,active_active_oh_10[13],1'h0,2'h0,active_active_oh_10[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_10 = {2'h0,active_active_oh_10[15],1'h0,2'h0,active_active_oh_10[14],1'h0,
- active_active_oh1_hi_hi_lo_10,active_active_oh1_hi_lo_10,active_active_oh1_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_10 = {1'h0,active_active_oh_10[1],2'h0,1'h0,active_active_oh_10[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_10 = {1'h0,active_active_oh_10[3],2'h0,1'h0,active_active_oh_10[2],2'h0,
- active_active_oh2_lo_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_10 = {1'h0,active_active_oh_10[5],2'h0,1'h0,active_active_oh_10[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_10 = {1'h0,active_active_oh_10[7],2'h0,1'h0,active_active_oh_10[6],2'h0,
- active_active_oh2_lo_hi_lo_10,active_active_oh2_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_10 = {1'h0,active_active_oh_10[9],2'h0,1'h0,active_active_oh_10[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_10 = {1'h0,active_active_oh_10[11],2'h0,1'h0,active_active_oh_10[10],2'h0,
- active_active_oh2_hi_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_10 = {1'h0,active_active_oh_10[13],2'h0,1'h0,active_active_oh_10[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_10 = {1'h0,active_active_oh_10[15],2'h0,1'h0,active_active_oh_10[14],2'h0,
- active_active_oh2_hi_hi_lo_10,active_active_oh2_hi_lo_10,active_active_oh2_lo_10}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_10 = {active_active_oh_10[3],3'h0,active_active_oh_10[2],3'h0,active_active_oh_10[
- 1],3'h0,active_active_oh_10[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_10 = {active_active_oh_10[7],3'h0,active_active_oh_10[6],3'h0,active_active_oh_10[5],3'h0
- ,active_active_oh_10[4],3'h0,active_active_oh3_lo_lo_10}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_10 = {active_active_oh_10[11],3'h0,active_active_oh_10[10],3'h0,
- active_active_oh_10[9],3'h0,active_active_oh_10[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_10 = {active_active_oh_10[15],3'h0,active_active_oh_10[14],3'h0,active_active_oh_10[13],3'h0
- ,active_active_oh_10[12],3'h0,active_active_oh3_hi_lo_10,active_active_oh3_lo_10}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_10 = f_io_in_bits_3_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_305 = ~f_io_in_bits_3_bits_m & active_active_idx_10 == 2'h0 | f_io_in_bits_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_306 = _active_active_active_T_305 ? active_active_oh0_10 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_312 = _active_active_active_T_270 & active_active_idx_10 == 2'h1 |
- _active_active_active_T_274; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_313 = _active_active_active_T_312 ? active_active_oh1_10 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_314 = _active_active_active_T_306 | _active_active_active_T_313; // @[VCommon.scala 107:68]
- wire _active_active_active_T_320 = _active_active_active_T_270 & active_active_idx_10 == 2'h2 |
- _active_active_active_T_274; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_321 = _active_active_active_T_320 ? active_active_oh2_10 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_322 = _active_active_active_T_314 | _active_active_active_T_321; // @[VCommon.scala 108:68]
- wire _active_active_active_T_328 = _active_active_active_T_270 & active_active_idx_10 == 2'h3 |
- _active_active_active_T_274; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_329 = _active_active_active_T_328 ? active_active_oh3_10 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_10 = _active_active_active_T_322 | _active_active_active_T_329; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_57 = f_io_in_bits_3_bits_tin_vt_valid ? active_active_active_10 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_T_58 = _active_active_T_52 | _active_active_T_57; // @[VAlu.scala 249:74]
- wire [3:0] active_active_oh_shiftAmount_11 = f_io_in_bits_3_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_11 = 16'h1 << active_active_oh_shiftAmount_11; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_11 = {3'h0,active_active_oh_11[3],3'h0,active_active_oh_11[2],3'h0,
- active_active_oh_11[1],3'h0,active_active_oh_11[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_11 = {3'h0,active_active_oh_11[7],3'h0,active_active_oh_11[6],3'h0,
- active_active_oh_11[5],3'h0,active_active_oh_11[4],active_active_oh0_lo_lo_11}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_11 = {3'h0,active_active_oh_11[11],3'h0,active_active_oh_11[10],3'h0,
- active_active_oh_11[9],3'h0,active_active_oh_11[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_11 = {3'h0,active_active_oh_11[15],3'h0,active_active_oh_11[14],3'h0,active_active_oh_11
- [13],3'h0,active_active_oh_11[12],active_active_oh0_hi_lo_11,active_active_oh0_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_11 = {2'h0,active_active_oh_11[1],1'h0,2'h0,active_active_oh_11[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_11 = {2'h0,active_active_oh_11[3],1'h0,2'h0,active_active_oh_11[2],1'h0,
- active_active_oh1_lo_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_11 = {2'h0,active_active_oh_11[5],1'h0,2'h0,active_active_oh_11[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_11 = {2'h0,active_active_oh_11[7],1'h0,2'h0,active_active_oh_11[6],1'h0,
- active_active_oh1_lo_hi_lo_11,active_active_oh1_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_11 = {2'h0,active_active_oh_11[9],1'h0,2'h0,active_active_oh_11[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_11 = {2'h0,active_active_oh_11[11],1'h0,2'h0,active_active_oh_11[10],1'h0,
- active_active_oh1_hi_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_11 = {2'h0,active_active_oh_11[13],1'h0,2'h0,active_active_oh_11[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_11 = {2'h0,active_active_oh_11[15],1'h0,2'h0,active_active_oh_11[14],1'h0,
- active_active_oh1_hi_hi_lo_11,active_active_oh1_hi_lo_11,active_active_oh1_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_11 = {1'h0,active_active_oh_11[1],2'h0,1'h0,active_active_oh_11[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_11 = {1'h0,active_active_oh_11[3],2'h0,1'h0,active_active_oh_11[2],2'h0,
- active_active_oh2_lo_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_11 = {1'h0,active_active_oh_11[5],2'h0,1'h0,active_active_oh_11[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_11 = {1'h0,active_active_oh_11[7],2'h0,1'h0,active_active_oh_11[6],2'h0,
- active_active_oh2_lo_hi_lo_11,active_active_oh2_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_11 = {1'h0,active_active_oh_11[9],2'h0,1'h0,active_active_oh_11[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_11 = {1'h0,active_active_oh_11[11],2'h0,1'h0,active_active_oh_11[10],2'h0,
- active_active_oh2_hi_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_11 = {1'h0,active_active_oh_11[13],2'h0,1'h0,active_active_oh_11[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_11 = {1'h0,active_active_oh_11[15],2'h0,1'h0,active_active_oh_11[14],2'h0,
- active_active_oh2_hi_hi_lo_11,active_active_oh2_hi_lo_11,active_active_oh2_lo_11}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_11 = {active_active_oh_11[3],3'h0,active_active_oh_11[2],3'h0,active_active_oh_11[
- 1],3'h0,active_active_oh_11[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_11 = {active_active_oh_11[7],3'h0,active_active_oh_11[6],3'h0,active_active_oh_11[5],3'h0
- ,active_active_oh_11[4],3'h0,active_active_oh3_lo_lo_11}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_11 = {active_active_oh_11[11],3'h0,active_active_oh_11[10],3'h0,
- active_active_oh_11[9],3'h0,active_active_oh_11[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_11 = {active_active_oh_11[15],3'h0,active_active_oh_11[14],3'h0,active_active_oh_11[13],3'h0
- ,active_active_oh_11[12],3'h0,active_active_oh3_hi_lo_11,active_active_oh3_lo_11}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_11 = f_io_in_bits_3_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_335 = ~f_io_in_bits_3_bits_m & active_active_idx_11 == 2'h0 | f_io_in_bits_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_336 = _active_active_active_T_335 ? active_active_oh0_11 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_342 = _active_active_active_T_270 & active_active_idx_11 == 2'h1 |
- _active_active_active_T_274; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_343 = _active_active_active_T_342 ? active_active_oh1_11 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_344 = _active_active_active_T_336 | _active_active_active_T_343; // @[VCommon.scala 107:68]
- wire _active_active_active_T_350 = _active_active_active_T_270 & active_active_idx_11 == 2'h2 |
- _active_active_active_T_274; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_351 = _active_active_active_T_350 ? active_active_oh2_11 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_352 = _active_active_active_T_344 | _active_active_active_T_351; // @[VCommon.scala 108:68]
- wire _active_active_active_T_358 = _active_active_active_T_270 & active_active_idx_11 == 2'h3 |
- _active_active_active_T_274; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_359 = _active_active_active_T_358 ? active_active_oh3_11 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_11 = _active_active_active_T_352 | _active_active_active_T_359; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_T_63 = f_io_in_bits_3_bits_tin_vu_valid ? active_active_active_11 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_3 = _active_active_T_58 | _active_active_T_63; // @[VAlu.scala 250:74]
- wire [63:0] _active_T_25 = fvalid[3] ? active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_26 = _active_T_19 | _active_T_25; // @[VCmdq.scala 126:90]
- wire [3:0] active_active_active_oh_shiftAmount = f_io_entry_0_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh = 16'h1 << active_active_active_oh_shiftAmount; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo = {3'h0,active_active_active_oh[3],3'h0,active_active_active_oh[2],3'h0,
- active_active_active_oh[1],3'h0,active_active_active_oh[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo = {3'h0,active_active_active_oh[7],3'h0,active_active_active_oh[6],3'h0,
- active_active_active_oh[5],3'h0,active_active_active_oh[4],active_active_active_oh0_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo = {3'h0,active_active_active_oh[11],3'h0,active_active_active_oh[10],3'h0,
- active_active_active_oh[9],3'h0,active_active_active_oh[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0 = {3'h0,active_active_active_oh[15],3'h0,active_active_active_oh[14],3'h0,
- active_active_active_oh[13],3'h0,active_active_active_oh[12],active_active_active_oh0_hi_lo,
- active_active_active_oh0_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo = {2'h0,active_active_active_oh[1],1'h0,2'h0,active_active_active_oh[0],1'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo = {2'h0,active_active_active_oh[3],1'h0,2'h0,active_active_active_oh[2],1'h0
- ,active_active_active_oh1_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo = {2'h0,active_active_active_oh[5],1'h0,2'h0,active_active_active_oh[4],1'h0
- }; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo = {2'h0,active_active_active_oh[7],1'h0,2'h0,active_active_active_oh[6],1'h0,
- active_active_active_oh1_lo_hi_lo,active_active_active_oh1_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo = {2'h0,active_active_active_oh[9],1'h0,2'h0,active_active_active_oh[8],1'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo = {2'h0,active_active_active_oh[11],1'h0,2'h0,active_active_active_oh[10],1'h0
- ,active_active_active_oh1_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo = {2'h0,active_active_active_oh[13],1'h0,2'h0,active_active_active_oh[12]
- ,1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1 = {2'h0,active_active_active_oh[15],1'h0,2'h0,active_active_active_oh[14],1'h0,
- active_active_active_oh1_hi_hi_lo,active_active_active_oh1_hi_lo,active_active_active_oh1_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo = {1'h0,active_active_active_oh[1],2'h0,1'h0,active_active_active_oh[0],2'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo = {1'h0,active_active_active_oh[3],2'h0,1'h0,active_active_active_oh[2],2'h0
- ,active_active_active_oh2_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo = {1'h0,active_active_active_oh[5],2'h0,1'h0,active_active_active_oh[4],2'h0
- }; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo = {1'h0,active_active_active_oh[7],2'h0,1'h0,active_active_active_oh[6],2'h0,
- active_active_active_oh2_lo_hi_lo,active_active_active_oh2_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo = {1'h0,active_active_active_oh[9],2'h0,1'h0,active_active_active_oh[8],2'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo = {1'h0,active_active_active_oh[11],2'h0,1'h0,active_active_active_oh[10],2'h0
- ,active_active_active_oh2_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo = {1'h0,active_active_active_oh[13],2'h0,1'h0,active_active_active_oh[12]
- ,2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2 = {1'h0,active_active_active_oh[15],2'h0,1'h0,active_active_active_oh[14],2'h0,
- active_active_active_oh2_hi_hi_lo,active_active_active_oh2_hi_lo,active_active_active_oh2_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo = {active_active_active_oh[3],3'h0,active_active_active_oh[2],3'h0,
- active_active_active_oh[1],3'h0,active_active_active_oh[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo = {active_active_active_oh[7],3'h0,active_active_active_oh[6],3'h0,
- active_active_active_oh[5],3'h0,active_active_active_oh[4],3'h0,active_active_active_oh3_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo = {active_active_active_oh[11],3'h0,active_active_active_oh[10],3'h0,
- active_active_active_oh[9],3'h0,active_active_active_oh[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3 = {active_active_active_oh[15],3'h0,active_active_active_oh[14],3'h0,
- active_active_active_oh[13],3'h0,active_active_active_oh[12],3'h0,active_active_active_oh3_hi_lo,
- active_active_active_oh3_lo}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx = f_io_entry_0_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T = ~f_io_entry_0_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_4 = f_io_entry_0_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_5 = ~f_io_entry_0_bits_m & active_active_active_idx == 2'h0 | f_io_entry_0_bits_m
- ; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_6 = _active_active_active_active_T_5 ? active_active_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_active_T_12 = _active_active_active_active_T & active_active_active_idx == 2'h1 |
- _active_active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_13 = _active_active_active_active_T_12 ? active_active_active_oh1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_14 = _active_active_active_active_T_6 | _active_active_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_20 = _active_active_active_active_T & active_active_active_idx == 2'h2 |
- _active_active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_21 = _active_active_active_active_T_20 ? active_active_active_oh2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_22 = _active_active_active_active_T_14 | _active_active_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_28 = _active_active_active_active_T & active_active_active_idx == 2'h3 |
- _active_active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_29 = _active_active_active_active_T_28 ? active_active_active_oh3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active = _active_active_active_active_T_22 | _active_active_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_364 = f_io_entry_0_bits_tin_vs_valid ? active_active_active_active : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_1 = f_io_entry_0_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_1 = 16'h1 << active_active_active_oh_shiftAmount_1; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_1 = {3'h0,active_active_active_oh_1[3],3'h0,active_active_active_oh_1[2],3'h0
- ,active_active_active_oh_1[1],3'h0,active_active_active_oh_1[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_1 = {3'h0,active_active_active_oh_1[7],3'h0,active_active_active_oh_1[6],3'h0,
- active_active_active_oh_1[5],3'h0,active_active_active_oh_1[4],active_active_active_oh0_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_1 = {3'h0,active_active_active_oh_1[11],3'h0,active_active_active_oh_1[10],3'h0
- ,active_active_active_oh_1[9],3'h0,active_active_active_oh_1[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_1 = {3'h0,active_active_active_oh_1[15],3'h0,active_active_active_oh_1[14],3'h0,
- active_active_active_oh_1[13],3'h0,active_active_active_oh_1[12],active_active_active_oh0_hi_lo_1,
- active_active_active_oh0_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_1 = {2'h0,active_active_active_oh_1[1],1'h0,2'h0,
- active_active_active_oh_1[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_1 = {2'h0,active_active_active_oh_1[3],1'h0,2'h0,active_active_active_oh_1[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_1 = {2'h0,active_active_active_oh_1[5],1'h0,2'h0,
- active_active_active_oh_1[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_1 = {2'h0,active_active_active_oh_1[7],1'h0,2'h0,active_active_active_oh_1[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_1,active_active_active_oh1_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_1 = {2'h0,active_active_active_oh_1[9],1'h0,2'h0,
- active_active_active_oh_1[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_1 = {2'h0,active_active_active_oh_1[11],1'h0,2'h0,active_active_active_oh_1
- [10],1'h0,active_active_active_oh1_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_1 = {2'h0,active_active_active_oh_1[13],1'h0,2'h0,
- active_active_active_oh_1[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_1 = {2'h0,active_active_active_oh_1[15],1'h0,2'h0,active_active_active_oh_1[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_1,active_active_active_oh1_hi_lo_1,active_active_active_oh1_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_1 = {1'h0,active_active_active_oh_1[1],2'h0,1'h0,
- active_active_active_oh_1[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_1 = {1'h0,active_active_active_oh_1[3],2'h0,1'h0,active_active_active_oh_1[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_1 = {1'h0,active_active_active_oh_1[5],2'h0,1'h0,
- active_active_active_oh_1[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_1 = {1'h0,active_active_active_oh_1[7],2'h0,1'h0,active_active_active_oh_1[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_1,active_active_active_oh2_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_1 = {1'h0,active_active_active_oh_1[9],2'h0,1'h0,
- active_active_active_oh_1[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_1 = {1'h0,active_active_active_oh_1[11],2'h0,1'h0,active_active_active_oh_1
- [10],2'h0,active_active_active_oh2_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_1 = {1'h0,active_active_active_oh_1[13],2'h0,1'h0,
- active_active_active_oh_1[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_1 = {1'h0,active_active_active_oh_1[15],2'h0,1'h0,active_active_active_oh_1[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_1,active_active_active_oh2_hi_lo_1,active_active_active_oh2_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_1 = {active_active_active_oh_1[3],3'h0,active_active_active_oh_1[2],3'h0,
- active_active_active_oh_1[1],3'h0,active_active_active_oh_1[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_1 = {active_active_active_oh_1[7],3'h0,active_active_active_oh_1[6],3'h0,
- active_active_active_oh_1[5],3'h0,active_active_active_oh_1[4],3'h0,active_active_active_oh3_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_1 = {active_active_active_oh_1[11],3'h0,active_active_active_oh_1[10],3'h0,
- active_active_active_oh_1[9],3'h0,active_active_active_oh_1[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_1 = {active_active_active_oh_1[15],3'h0,active_active_active_oh_1[14],3'h0,
- active_active_active_oh_1[13],3'h0,active_active_active_oh_1[12],3'h0,active_active_active_oh3_hi_lo_1,
- active_active_active_oh3_lo_1}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_1 = f_io_entry_0_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_35 = ~f_io_entry_0_bits_m & active_active_active_idx_1 == 2'h0 |
- f_io_entry_0_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_36 = _active_active_active_active_T_35 ? active_active_active_oh0_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_42 = _active_active_active_active_T & active_active_active_idx_1 == 2'h1 |
- _active_active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_43 = _active_active_active_active_T_42 ? active_active_active_oh1_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_44 = _active_active_active_active_T_36 | _active_active_active_active_T_43; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_50 = _active_active_active_active_T & active_active_active_idx_1 == 2'h2 |
- _active_active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_51 = _active_active_active_active_T_50 ? active_active_active_oh2_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_52 = _active_active_active_active_T_44 | _active_active_active_active_T_51; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_58 = _active_active_active_active_T & active_active_active_idx_1 == 2'h3 |
- _active_active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_59 = _active_active_active_active_T_58 ? active_active_active_oh3_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_1 = _active_active_active_active_T_52 | _active_active_active_active_T_59; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_369 = f_io_entry_0_bits_tin_vt_valid ? active_active_active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_370 = _active_active_active_T_364 | _active_active_active_T_369; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_2 = f_io_entry_0_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_2 = 16'h1 << active_active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_2 = {3'h0,active_active_active_oh_2[3],3'h0,active_active_active_oh_2[2],3'h0
- ,active_active_active_oh_2[1],3'h0,active_active_active_oh_2[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_2 = {3'h0,active_active_active_oh_2[7],3'h0,active_active_active_oh_2[6],3'h0,
- active_active_active_oh_2[5],3'h0,active_active_active_oh_2[4],active_active_active_oh0_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_2 = {3'h0,active_active_active_oh_2[11],3'h0,active_active_active_oh_2[10],3'h0
- ,active_active_active_oh_2[9],3'h0,active_active_active_oh_2[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_2 = {3'h0,active_active_active_oh_2[15],3'h0,active_active_active_oh_2[14],3'h0,
- active_active_active_oh_2[13],3'h0,active_active_active_oh_2[12],active_active_active_oh0_hi_lo_2,
- active_active_active_oh0_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_2 = {2'h0,active_active_active_oh_2[1],1'h0,2'h0,
- active_active_active_oh_2[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_2 = {2'h0,active_active_active_oh_2[3],1'h0,2'h0,active_active_active_oh_2[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_2 = {2'h0,active_active_active_oh_2[5],1'h0,2'h0,
- active_active_active_oh_2[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_2 = {2'h0,active_active_active_oh_2[7],1'h0,2'h0,active_active_active_oh_2[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_2,active_active_active_oh1_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_2 = {2'h0,active_active_active_oh_2[9],1'h0,2'h0,
- active_active_active_oh_2[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_2 = {2'h0,active_active_active_oh_2[11],1'h0,2'h0,active_active_active_oh_2
- [10],1'h0,active_active_active_oh1_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_2 = {2'h0,active_active_active_oh_2[13],1'h0,2'h0,
- active_active_active_oh_2[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_2 = {2'h0,active_active_active_oh_2[15],1'h0,2'h0,active_active_active_oh_2[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_2,active_active_active_oh1_hi_lo_2,active_active_active_oh1_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_2 = {1'h0,active_active_active_oh_2[1],2'h0,1'h0,
- active_active_active_oh_2[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_2 = {1'h0,active_active_active_oh_2[3],2'h0,1'h0,active_active_active_oh_2[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_2 = {1'h0,active_active_active_oh_2[5],2'h0,1'h0,
- active_active_active_oh_2[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_2 = {1'h0,active_active_active_oh_2[7],2'h0,1'h0,active_active_active_oh_2[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_2,active_active_active_oh2_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_2 = {1'h0,active_active_active_oh_2[9],2'h0,1'h0,
- active_active_active_oh_2[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_2 = {1'h0,active_active_active_oh_2[11],2'h0,1'h0,active_active_active_oh_2
- [10],2'h0,active_active_active_oh2_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_2 = {1'h0,active_active_active_oh_2[13],2'h0,1'h0,
- active_active_active_oh_2[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_2 = {1'h0,active_active_active_oh_2[15],2'h0,1'h0,active_active_active_oh_2[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_2,active_active_active_oh2_hi_lo_2,active_active_active_oh2_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_2 = {active_active_active_oh_2[3],3'h0,active_active_active_oh_2[2],3'h0,
- active_active_active_oh_2[1],3'h0,active_active_active_oh_2[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_2 = {active_active_active_oh_2[7],3'h0,active_active_active_oh_2[6],3'h0,
- active_active_active_oh_2[5],3'h0,active_active_active_oh_2[4],3'h0,active_active_active_oh3_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_2 = {active_active_active_oh_2[11],3'h0,active_active_active_oh_2[10],3'h0,
- active_active_active_oh_2[9],3'h0,active_active_active_oh_2[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_2 = {active_active_active_oh_2[15],3'h0,active_active_active_oh_2[14],3'h0,
- active_active_active_oh_2[13],3'h0,active_active_active_oh_2[12],3'h0,active_active_active_oh3_hi_lo_2,
- active_active_active_oh3_lo_2}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_2 = f_io_entry_0_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_65 = ~f_io_entry_0_bits_m & active_active_active_idx_2 == 2'h0 |
- f_io_entry_0_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_66 = _active_active_active_active_T_65 ? active_active_active_oh0_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_72 = _active_active_active_active_T & active_active_active_idx_2 == 2'h1 |
- _active_active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_73 = _active_active_active_active_T_72 ? active_active_active_oh1_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_74 = _active_active_active_active_T_66 | _active_active_active_active_T_73; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_80 = _active_active_active_active_T & active_active_active_idx_2 == 2'h2 |
- _active_active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_81 = _active_active_active_active_T_80 ? active_active_active_oh2_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_82 = _active_active_active_active_T_74 | _active_active_active_active_T_81; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_88 = _active_active_active_active_T & active_active_active_idx_2 == 2'h3 |
- _active_active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_89 = _active_active_active_active_T_88 ? active_active_active_oh3_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_2 = _active_active_active_active_T_82 | _active_active_active_active_T_89; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_375 = f_io_entry_0_bits_tin_vu_valid ? active_active_active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_12 = _active_active_active_T_370 | _active_active_active_T_375; // @[VAlu.scala 250:74]
- wire [63:0] active_active_4 = f_io_entry_0_valid ? active_active_active_12 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_3 = f_io_entry_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_3 = 16'h1 << active_active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_3 = {3'h0,active_active_active_oh_3[3],3'h0,active_active_active_oh_3[2],3'h0
- ,active_active_active_oh_3[1],3'h0,active_active_active_oh_3[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_3 = {3'h0,active_active_active_oh_3[7],3'h0,active_active_active_oh_3[6],3'h0,
- active_active_active_oh_3[5],3'h0,active_active_active_oh_3[4],active_active_active_oh0_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_3 = {3'h0,active_active_active_oh_3[11],3'h0,active_active_active_oh_3[10],3'h0
- ,active_active_active_oh_3[9],3'h0,active_active_active_oh_3[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_3 = {3'h0,active_active_active_oh_3[15],3'h0,active_active_active_oh_3[14],3'h0,
- active_active_active_oh_3[13],3'h0,active_active_active_oh_3[12],active_active_active_oh0_hi_lo_3,
- active_active_active_oh0_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_3 = {2'h0,active_active_active_oh_3[1],1'h0,2'h0,
- active_active_active_oh_3[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_3 = {2'h0,active_active_active_oh_3[3],1'h0,2'h0,active_active_active_oh_3[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_3 = {2'h0,active_active_active_oh_3[5],1'h0,2'h0,
- active_active_active_oh_3[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_3 = {2'h0,active_active_active_oh_3[7],1'h0,2'h0,active_active_active_oh_3[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_3,active_active_active_oh1_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_3 = {2'h0,active_active_active_oh_3[9],1'h0,2'h0,
- active_active_active_oh_3[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_3 = {2'h0,active_active_active_oh_3[11],1'h0,2'h0,active_active_active_oh_3
- [10],1'h0,active_active_active_oh1_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_3 = {2'h0,active_active_active_oh_3[13],1'h0,2'h0,
- active_active_active_oh_3[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_3 = {2'h0,active_active_active_oh_3[15],1'h0,2'h0,active_active_active_oh_3[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_3,active_active_active_oh1_hi_lo_3,active_active_active_oh1_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_3 = {1'h0,active_active_active_oh_3[1],2'h0,1'h0,
- active_active_active_oh_3[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_3 = {1'h0,active_active_active_oh_3[3],2'h0,1'h0,active_active_active_oh_3[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_3 = {1'h0,active_active_active_oh_3[5],2'h0,1'h0,
- active_active_active_oh_3[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_3 = {1'h0,active_active_active_oh_3[7],2'h0,1'h0,active_active_active_oh_3[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_3,active_active_active_oh2_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_3 = {1'h0,active_active_active_oh_3[9],2'h0,1'h0,
- active_active_active_oh_3[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_3 = {1'h0,active_active_active_oh_3[11],2'h0,1'h0,active_active_active_oh_3
- [10],2'h0,active_active_active_oh2_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_3 = {1'h0,active_active_active_oh_3[13],2'h0,1'h0,
- active_active_active_oh_3[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_3 = {1'h0,active_active_active_oh_3[15],2'h0,1'h0,active_active_active_oh_3[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_3,active_active_active_oh2_hi_lo_3,active_active_active_oh2_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_3 = {active_active_active_oh_3[3],3'h0,active_active_active_oh_3[2],3'h0,
- active_active_active_oh_3[1],3'h0,active_active_active_oh_3[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_3 = {active_active_active_oh_3[7],3'h0,active_active_active_oh_3[6],3'h0,
- active_active_active_oh_3[5],3'h0,active_active_active_oh_3[4],3'h0,active_active_active_oh3_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_3 = {active_active_active_oh_3[11],3'h0,active_active_active_oh_3[10],3'h0,
- active_active_active_oh_3[9],3'h0,active_active_active_oh_3[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_3 = {active_active_active_oh_3[15],3'h0,active_active_active_oh_3[14],3'h0,
- active_active_active_oh_3[13],3'h0,active_active_active_oh_3[12],3'h0,active_active_active_oh3_hi_lo_3,
- active_active_active_oh3_lo_3}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_3 = f_io_entry_1_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_90 = ~f_io_entry_1_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_94 = f_io_entry_1_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_95 = ~f_io_entry_1_bits_m & active_active_active_idx_3 == 2'h0 |
- f_io_entry_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_96 = _active_active_active_active_T_95 ? active_active_active_oh0_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_102 = _active_active_active_active_T_90 & active_active_active_idx_3 == 2'h1 |
- _active_active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_103 = _active_active_active_active_T_102 ? active_active_active_oh1_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_104 = _active_active_active_active_T_96 |
- _active_active_active_active_T_103; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_110 = _active_active_active_active_T_90 & active_active_active_idx_3 == 2'h2 |
- _active_active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_111 = _active_active_active_active_T_110 ? active_active_active_oh2_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_112 = _active_active_active_active_T_104 |
- _active_active_active_active_T_111; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_118 = _active_active_active_active_T_90 & active_active_active_idx_3 == 2'h3 |
- _active_active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_119 = _active_active_active_active_T_118 ? active_active_active_oh3_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_3 = _active_active_active_active_T_112 | _active_active_active_active_T_119; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_380 = f_io_entry_1_bits_tin_vs_valid ? active_active_active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_4 = f_io_entry_1_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_4 = 16'h1 << active_active_active_oh_shiftAmount_4; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_4 = {3'h0,active_active_active_oh_4[3],3'h0,active_active_active_oh_4[2],3'h0
- ,active_active_active_oh_4[1],3'h0,active_active_active_oh_4[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_4 = {3'h0,active_active_active_oh_4[7],3'h0,active_active_active_oh_4[6],3'h0,
- active_active_active_oh_4[5],3'h0,active_active_active_oh_4[4],active_active_active_oh0_lo_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_4 = {3'h0,active_active_active_oh_4[11],3'h0,active_active_active_oh_4[10],3'h0
- ,active_active_active_oh_4[9],3'h0,active_active_active_oh_4[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_4 = {3'h0,active_active_active_oh_4[15],3'h0,active_active_active_oh_4[14],3'h0,
- active_active_active_oh_4[13],3'h0,active_active_active_oh_4[12],active_active_active_oh0_hi_lo_4,
- active_active_active_oh0_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_4 = {2'h0,active_active_active_oh_4[1],1'h0,2'h0,
- active_active_active_oh_4[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_4 = {2'h0,active_active_active_oh_4[3],1'h0,2'h0,active_active_active_oh_4[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_4 = {2'h0,active_active_active_oh_4[5],1'h0,2'h0,
- active_active_active_oh_4[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_4 = {2'h0,active_active_active_oh_4[7],1'h0,2'h0,active_active_active_oh_4[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_4,active_active_active_oh1_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_4 = {2'h0,active_active_active_oh_4[9],1'h0,2'h0,
- active_active_active_oh_4[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_4 = {2'h0,active_active_active_oh_4[11],1'h0,2'h0,active_active_active_oh_4
- [10],1'h0,active_active_active_oh1_hi_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_4 = {2'h0,active_active_active_oh_4[13],1'h0,2'h0,
- active_active_active_oh_4[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_4 = {2'h0,active_active_active_oh_4[15],1'h0,2'h0,active_active_active_oh_4[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_4,active_active_active_oh1_hi_lo_4,active_active_active_oh1_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_4 = {1'h0,active_active_active_oh_4[1],2'h0,1'h0,
- active_active_active_oh_4[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_4 = {1'h0,active_active_active_oh_4[3],2'h0,1'h0,active_active_active_oh_4[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_4 = {1'h0,active_active_active_oh_4[5],2'h0,1'h0,
- active_active_active_oh_4[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_4 = {1'h0,active_active_active_oh_4[7],2'h0,1'h0,active_active_active_oh_4[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_4,active_active_active_oh2_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_4 = {1'h0,active_active_active_oh_4[9],2'h0,1'h0,
- active_active_active_oh_4[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_4 = {1'h0,active_active_active_oh_4[11],2'h0,1'h0,active_active_active_oh_4
- [10],2'h0,active_active_active_oh2_hi_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_4 = {1'h0,active_active_active_oh_4[13],2'h0,1'h0,
- active_active_active_oh_4[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_4 = {1'h0,active_active_active_oh_4[15],2'h0,1'h0,active_active_active_oh_4[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_4,active_active_active_oh2_hi_lo_4,active_active_active_oh2_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_4 = {active_active_active_oh_4[3],3'h0,active_active_active_oh_4[2],3'h0,
- active_active_active_oh_4[1],3'h0,active_active_active_oh_4[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_4 = {active_active_active_oh_4[7],3'h0,active_active_active_oh_4[6],3'h0,
- active_active_active_oh_4[5],3'h0,active_active_active_oh_4[4],3'h0,active_active_active_oh3_lo_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_4 = {active_active_active_oh_4[11],3'h0,active_active_active_oh_4[10],3'h0,
- active_active_active_oh_4[9],3'h0,active_active_active_oh_4[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_4 = {active_active_active_oh_4[15],3'h0,active_active_active_oh_4[14],3'h0,
- active_active_active_oh_4[13],3'h0,active_active_active_oh_4[12],3'h0,active_active_active_oh3_hi_lo_4,
- active_active_active_oh3_lo_4}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_4 = f_io_entry_1_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_125 = ~f_io_entry_1_bits_m & active_active_active_idx_4 == 2'h0 |
- f_io_entry_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_126 = _active_active_active_active_T_125 ? active_active_active_oh0_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_132 = _active_active_active_active_T_90 & active_active_active_idx_4 == 2'h1 |
- _active_active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_133 = _active_active_active_active_T_132 ? active_active_active_oh1_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_134 = _active_active_active_active_T_126 |
- _active_active_active_active_T_133; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_140 = _active_active_active_active_T_90 & active_active_active_idx_4 == 2'h2 |
- _active_active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_141 = _active_active_active_active_T_140 ? active_active_active_oh2_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_142 = _active_active_active_active_T_134 |
- _active_active_active_active_T_141; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_148 = _active_active_active_active_T_90 & active_active_active_idx_4 == 2'h3 |
- _active_active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_149 = _active_active_active_active_T_148 ? active_active_active_oh3_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_4 = _active_active_active_active_T_142 | _active_active_active_active_T_149; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_385 = f_io_entry_1_bits_tin_vt_valid ? active_active_active_active_4 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_386 = _active_active_active_T_380 | _active_active_active_T_385; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_5 = f_io_entry_1_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_5 = 16'h1 << active_active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_5 = {3'h0,active_active_active_oh_5[3],3'h0,active_active_active_oh_5[2],3'h0
- ,active_active_active_oh_5[1],3'h0,active_active_active_oh_5[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_5 = {3'h0,active_active_active_oh_5[7],3'h0,active_active_active_oh_5[6],3'h0,
- active_active_active_oh_5[5],3'h0,active_active_active_oh_5[4],active_active_active_oh0_lo_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_5 = {3'h0,active_active_active_oh_5[11],3'h0,active_active_active_oh_5[10],3'h0
- ,active_active_active_oh_5[9],3'h0,active_active_active_oh_5[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_5 = {3'h0,active_active_active_oh_5[15],3'h0,active_active_active_oh_5[14],3'h0,
- active_active_active_oh_5[13],3'h0,active_active_active_oh_5[12],active_active_active_oh0_hi_lo_5,
- active_active_active_oh0_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_5 = {2'h0,active_active_active_oh_5[1],1'h0,2'h0,
- active_active_active_oh_5[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_5 = {2'h0,active_active_active_oh_5[3],1'h0,2'h0,active_active_active_oh_5[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_5 = {2'h0,active_active_active_oh_5[5],1'h0,2'h0,
- active_active_active_oh_5[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_5 = {2'h0,active_active_active_oh_5[7],1'h0,2'h0,active_active_active_oh_5[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_5,active_active_active_oh1_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_5 = {2'h0,active_active_active_oh_5[9],1'h0,2'h0,
- active_active_active_oh_5[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_5 = {2'h0,active_active_active_oh_5[11],1'h0,2'h0,active_active_active_oh_5
- [10],1'h0,active_active_active_oh1_hi_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_5 = {2'h0,active_active_active_oh_5[13],1'h0,2'h0,
- active_active_active_oh_5[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_5 = {2'h0,active_active_active_oh_5[15],1'h0,2'h0,active_active_active_oh_5[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_5,active_active_active_oh1_hi_lo_5,active_active_active_oh1_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_5 = {1'h0,active_active_active_oh_5[1],2'h0,1'h0,
- active_active_active_oh_5[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_5 = {1'h0,active_active_active_oh_5[3],2'h0,1'h0,active_active_active_oh_5[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_5 = {1'h0,active_active_active_oh_5[5],2'h0,1'h0,
- active_active_active_oh_5[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_5 = {1'h0,active_active_active_oh_5[7],2'h0,1'h0,active_active_active_oh_5[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_5,active_active_active_oh2_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_5 = {1'h0,active_active_active_oh_5[9],2'h0,1'h0,
- active_active_active_oh_5[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_5 = {1'h0,active_active_active_oh_5[11],2'h0,1'h0,active_active_active_oh_5
- [10],2'h0,active_active_active_oh2_hi_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_5 = {1'h0,active_active_active_oh_5[13],2'h0,1'h0,
- active_active_active_oh_5[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_5 = {1'h0,active_active_active_oh_5[15],2'h0,1'h0,active_active_active_oh_5[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_5,active_active_active_oh2_hi_lo_5,active_active_active_oh2_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_5 = {active_active_active_oh_5[3],3'h0,active_active_active_oh_5[2],3'h0,
- active_active_active_oh_5[1],3'h0,active_active_active_oh_5[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_5 = {active_active_active_oh_5[7],3'h0,active_active_active_oh_5[6],3'h0,
- active_active_active_oh_5[5],3'h0,active_active_active_oh_5[4],3'h0,active_active_active_oh3_lo_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_5 = {active_active_active_oh_5[11],3'h0,active_active_active_oh_5[10],3'h0,
- active_active_active_oh_5[9],3'h0,active_active_active_oh_5[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_5 = {active_active_active_oh_5[15],3'h0,active_active_active_oh_5[14],3'h0,
- active_active_active_oh_5[13],3'h0,active_active_active_oh_5[12],3'h0,active_active_active_oh3_hi_lo_5,
- active_active_active_oh3_lo_5}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_5 = f_io_entry_1_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_155 = ~f_io_entry_1_bits_m & active_active_active_idx_5 == 2'h0 |
- f_io_entry_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_156 = _active_active_active_active_T_155 ? active_active_active_oh0_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_162 = _active_active_active_active_T_90 & active_active_active_idx_5 == 2'h1 |
- _active_active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_163 = _active_active_active_active_T_162 ? active_active_active_oh1_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_164 = _active_active_active_active_T_156 |
- _active_active_active_active_T_163; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_170 = _active_active_active_active_T_90 & active_active_active_idx_5 == 2'h2 |
- _active_active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_171 = _active_active_active_active_T_170 ? active_active_active_oh2_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_172 = _active_active_active_active_T_164 |
- _active_active_active_active_T_171; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_178 = _active_active_active_active_T_90 & active_active_active_idx_5 == 2'h3 |
- _active_active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_179 = _active_active_active_active_T_178 ? active_active_active_oh3_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_5 = _active_active_active_active_T_172 | _active_active_active_active_T_179; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_391 = f_io_entry_1_bits_tin_vu_valid ? active_active_active_active_5 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_13 = _active_active_active_T_386 | _active_active_active_T_391; // @[VAlu.scala 250:74]
- wire [63:0] active_active_5 = f_io_entry_1_valid ? active_active_active_13 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_28 = active_active_4 | active_active_5; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_6 = f_io_entry_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_6 = 16'h1 << active_active_active_oh_shiftAmount_6; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_6 = {3'h0,active_active_active_oh_6[3],3'h0,active_active_active_oh_6[2],3'h0
- ,active_active_active_oh_6[1],3'h0,active_active_active_oh_6[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_6 = {3'h0,active_active_active_oh_6[7],3'h0,active_active_active_oh_6[6],3'h0,
- active_active_active_oh_6[5],3'h0,active_active_active_oh_6[4],active_active_active_oh0_lo_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_6 = {3'h0,active_active_active_oh_6[11],3'h0,active_active_active_oh_6[10],3'h0
- ,active_active_active_oh_6[9],3'h0,active_active_active_oh_6[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_6 = {3'h0,active_active_active_oh_6[15],3'h0,active_active_active_oh_6[14],3'h0,
- active_active_active_oh_6[13],3'h0,active_active_active_oh_6[12],active_active_active_oh0_hi_lo_6,
- active_active_active_oh0_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_6 = {2'h0,active_active_active_oh_6[1],1'h0,2'h0,
- active_active_active_oh_6[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_6 = {2'h0,active_active_active_oh_6[3],1'h0,2'h0,active_active_active_oh_6[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_6 = {2'h0,active_active_active_oh_6[5],1'h0,2'h0,
- active_active_active_oh_6[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_6 = {2'h0,active_active_active_oh_6[7],1'h0,2'h0,active_active_active_oh_6[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_6,active_active_active_oh1_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_6 = {2'h0,active_active_active_oh_6[9],1'h0,2'h0,
- active_active_active_oh_6[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_6 = {2'h0,active_active_active_oh_6[11],1'h0,2'h0,active_active_active_oh_6
- [10],1'h0,active_active_active_oh1_hi_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_6 = {2'h0,active_active_active_oh_6[13],1'h0,2'h0,
- active_active_active_oh_6[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_6 = {2'h0,active_active_active_oh_6[15],1'h0,2'h0,active_active_active_oh_6[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_6,active_active_active_oh1_hi_lo_6,active_active_active_oh1_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_6 = {1'h0,active_active_active_oh_6[1],2'h0,1'h0,
- active_active_active_oh_6[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_6 = {1'h0,active_active_active_oh_6[3],2'h0,1'h0,active_active_active_oh_6[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_6 = {1'h0,active_active_active_oh_6[5],2'h0,1'h0,
- active_active_active_oh_6[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_6 = {1'h0,active_active_active_oh_6[7],2'h0,1'h0,active_active_active_oh_6[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_6,active_active_active_oh2_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_6 = {1'h0,active_active_active_oh_6[9],2'h0,1'h0,
- active_active_active_oh_6[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_6 = {1'h0,active_active_active_oh_6[11],2'h0,1'h0,active_active_active_oh_6
- [10],2'h0,active_active_active_oh2_hi_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_6 = {1'h0,active_active_active_oh_6[13],2'h0,1'h0,
- active_active_active_oh_6[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_6 = {1'h0,active_active_active_oh_6[15],2'h0,1'h0,active_active_active_oh_6[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_6,active_active_active_oh2_hi_lo_6,active_active_active_oh2_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_6 = {active_active_active_oh_6[3],3'h0,active_active_active_oh_6[2],3'h0,
- active_active_active_oh_6[1],3'h0,active_active_active_oh_6[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_6 = {active_active_active_oh_6[7],3'h0,active_active_active_oh_6[6],3'h0,
- active_active_active_oh_6[5],3'h0,active_active_active_oh_6[4],3'h0,active_active_active_oh3_lo_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_6 = {active_active_active_oh_6[11],3'h0,active_active_active_oh_6[10],3'h0,
- active_active_active_oh_6[9],3'h0,active_active_active_oh_6[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_6 = {active_active_active_oh_6[15],3'h0,active_active_active_oh_6[14],3'h0,
- active_active_active_oh_6[13],3'h0,active_active_active_oh_6[12],3'h0,active_active_active_oh3_hi_lo_6,
- active_active_active_oh3_lo_6}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_6 = f_io_entry_2_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_180 = ~f_io_entry_2_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_184 = f_io_entry_2_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_185 = ~f_io_entry_2_bits_m & active_active_active_idx_6 == 2'h0 |
- f_io_entry_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_186 = _active_active_active_active_T_185 ? active_active_active_oh0_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_192 = _active_active_active_active_T_180 & active_active_active_idx_6 == 2'h1 |
- _active_active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_193 = _active_active_active_active_T_192 ? active_active_active_oh1_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_194 = _active_active_active_active_T_186 |
- _active_active_active_active_T_193; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_200 = _active_active_active_active_T_180 & active_active_active_idx_6 == 2'h2 |
- _active_active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_201 = _active_active_active_active_T_200 ? active_active_active_oh2_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_202 = _active_active_active_active_T_194 |
- _active_active_active_active_T_201; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_208 = _active_active_active_active_T_180 & active_active_active_idx_6 == 2'h3 |
- _active_active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_209 = _active_active_active_active_T_208 ? active_active_active_oh3_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_6 = _active_active_active_active_T_202 | _active_active_active_active_T_209; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_396 = f_io_entry_2_bits_tin_vs_valid ? active_active_active_active_6 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_7 = f_io_entry_2_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_7 = 16'h1 << active_active_active_oh_shiftAmount_7; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_7 = {3'h0,active_active_active_oh_7[3],3'h0,active_active_active_oh_7[2],3'h0
- ,active_active_active_oh_7[1],3'h0,active_active_active_oh_7[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_7 = {3'h0,active_active_active_oh_7[7],3'h0,active_active_active_oh_7[6],3'h0,
- active_active_active_oh_7[5],3'h0,active_active_active_oh_7[4],active_active_active_oh0_lo_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_7 = {3'h0,active_active_active_oh_7[11],3'h0,active_active_active_oh_7[10],3'h0
- ,active_active_active_oh_7[9],3'h0,active_active_active_oh_7[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_7 = {3'h0,active_active_active_oh_7[15],3'h0,active_active_active_oh_7[14],3'h0,
- active_active_active_oh_7[13],3'h0,active_active_active_oh_7[12],active_active_active_oh0_hi_lo_7,
- active_active_active_oh0_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_7 = {2'h0,active_active_active_oh_7[1],1'h0,2'h0,
- active_active_active_oh_7[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_7 = {2'h0,active_active_active_oh_7[3],1'h0,2'h0,active_active_active_oh_7[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_7 = {2'h0,active_active_active_oh_7[5],1'h0,2'h0,
- active_active_active_oh_7[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_7 = {2'h0,active_active_active_oh_7[7],1'h0,2'h0,active_active_active_oh_7[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_7,active_active_active_oh1_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_7 = {2'h0,active_active_active_oh_7[9],1'h0,2'h0,
- active_active_active_oh_7[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_7 = {2'h0,active_active_active_oh_7[11],1'h0,2'h0,active_active_active_oh_7
- [10],1'h0,active_active_active_oh1_hi_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_7 = {2'h0,active_active_active_oh_7[13],1'h0,2'h0,
- active_active_active_oh_7[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_7 = {2'h0,active_active_active_oh_7[15],1'h0,2'h0,active_active_active_oh_7[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_7,active_active_active_oh1_hi_lo_7,active_active_active_oh1_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_7 = {1'h0,active_active_active_oh_7[1],2'h0,1'h0,
- active_active_active_oh_7[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_7 = {1'h0,active_active_active_oh_7[3],2'h0,1'h0,active_active_active_oh_7[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_7 = {1'h0,active_active_active_oh_7[5],2'h0,1'h0,
- active_active_active_oh_7[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_7 = {1'h0,active_active_active_oh_7[7],2'h0,1'h0,active_active_active_oh_7[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_7,active_active_active_oh2_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_7 = {1'h0,active_active_active_oh_7[9],2'h0,1'h0,
- active_active_active_oh_7[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_7 = {1'h0,active_active_active_oh_7[11],2'h0,1'h0,active_active_active_oh_7
- [10],2'h0,active_active_active_oh2_hi_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_7 = {1'h0,active_active_active_oh_7[13],2'h0,1'h0,
- active_active_active_oh_7[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_7 = {1'h0,active_active_active_oh_7[15],2'h0,1'h0,active_active_active_oh_7[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_7,active_active_active_oh2_hi_lo_7,active_active_active_oh2_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_7 = {active_active_active_oh_7[3],3'h0,active_active_active_oh_7[2],3'h0,
- active_active_active_oh_7[1],3'h0,active_active_active_oh_7[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_7 = {active_active_active_oh_7[7],3'h0,active_active_active_oh_7[6],3'h0,
- active_active_active_oh_7[5],3'h0,active_active_active_oh_7[4],3'h0,active_active_active_oh3_lo_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_7 = {active_active_active_oh_7[11],3'h0,active_active_active_oh_7[10],3'h0,
- active_active_active_oh_7[9],3'h0,active_active_active_oh_7[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_7 = {active_active_active_oh_7[15],3'h0,active_active_active_oh_7[14],3'h0,
- active_active_active_oh_7[13],3'h0,active_active_active_oh_7[12],3'h0,active_active_active_oh3_hi_lo_7,
- active_active_active_oh3_lo_7}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_7 = f_io_entry_2_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_215 = ~f_io_entry_2_bits_m & active_active_active_idx_7 == 2'h0 |
- f_io_entry_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_216 = _active_active_active_active_T_215 ? active_active_active_oh0_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_222 = _active_active_active_active_T_180 & active_active_active_idx_7 == 2'h1 |
- _active_active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_223 = _active_active_active_active_T_222 ? active_active_active_oh1_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_224 = _active_active_active_active_T_216 |
- _active_active_active_active_T_223; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_230 = _active_active_active_active_T_180 & active_active_active_idx_7 == 2'h2 |
- _active_active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_231 = _active_active_active_active_T_230 ? active_active_active_oh2_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_232 = _active_active_active_active_T_224 |
- _active_active_active_active_T_231; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_238 = _active_active_active_active_T_180 & active_active_active_idx_7 == 2'h3 |
- _active_active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_239 = _active_active_active_active_T_238 ? active_active_active_oh3_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_7 = _active_active_active_active_T_232 | _active_active_active_active_T_239; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_401 = f_io_entry_2_bits_tin_vt_valid ? active_active_active_active_7 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_402 = _active_active_active_T_396 | _active_active_active_T_401; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_8 = f_io_entry_2_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_8 = 16'h1 << active_active_active_oh_shiftAmount_8; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_8 = {3'h0,active_active_active_oh_8[3],3'h0,active_active_active_oh_8[2],3'h0
- ,active_active_active_oh_8[1],3'h0,active_active_active_oh_8[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_8 = {3'h0,active_active_active_oh_8[7],3'h0,active_active_active_oh_8[6],3'h0,
- active_active_active_oh_8[5],3'h0,active_active_active_oh_8[4],active_active_active_oh0_lo_lo_8}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_8 = {3'h0,active_active_active_oh_8[11],3'h0,active_active_active_oh_8[10],3'h0
- ,active_active_active_oh_8[9],3'h0,active_active_active_oh_8[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_8 = {3'h0,active_active_active_oh_8[15],3'h0,active_active_active_oh_8[14],3'h0,
- active_active_active_oh_8[13],3'h0,active_active_active_oh_8[12],active_active_active_oh0_hi_lo_8,
- active_active_active_oh0_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_8 = {2'h0,active_active_active_oh_8[1],1'h0,2'h0,
- active_active_active_oh_8[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_8 = {2'h0,active_active_active_oh_8[3],1'h0,2'h0,active_active_active_oh_8[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_8 = {2'h0,active_active_active_oh_8[5],1'h0,2'h0,
- active_active_active_oh_8[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_8 = {2'h0,active_active_active_oh_8[7],1'h0,2'h0,active_active_active_oh_8[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_8,active_active_active_oh1_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_8 = {2'h0,active_active_active_oh_8[9],1'h0,2'h0,
- active_active_active_oh_8[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_8 = {2'h0,active_active_active_oh_8[11],1'h0,2'h0,active_active_active_oh_8
- [10],1'h0,active_active_active_oh1_hi_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_8 = {2'h0,active_active_active_oh_8[13],1'h0,2'h0,
- active_active_active_oh_8[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_8 = {2'h0,active_active_active_oh_8[15],1'h0,2'h0,active_active_active_oh_8[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_8,active_active_active_oh1_hi_lo_8,active_active_active_oh1_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_8 = {1'h0,active_active_active_oh_8[1],2'h0,1'h0,
- active_active_active_oh_8[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_8 = {1'h0,active_active_active_oh_8[3],2'h0,1'h0,active_active_active_oh_8[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_8 = {1'h0,active_active_active_oh_8[5],2'h0,1'h0,
- active_active_active_oh_8[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_8 = {1'h0,active_active_active_oh_8[7],2'h0,1'h0,active_active_active_oh_8[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_8,active_active_active_oh2_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_8 = {1'h0,active_active_active_oh_8[9],2'h0,1'h0,
- active_active_active_oh_8[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_8 = {1'h0,active_active_active_oh_8[11],2'h0,1'h0,active_active_active_oh_8
- [10],2'h0,active_active_active_oh2_hi_lo_lo_8}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_8 = {1'h0,active_active_active_oh_8[13],2'h0,1'h0,
- active_active_active_oh_8[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_8 = {1'h0,active_active_active_oh_8[15],2'h0,1'h0,active_active_active_oh_8[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_8,active_active_active_oh2_hi_lo_8,active_active_active_oh2_lo_8}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_8 = {active_active_active_oh_8[3],3'h0,active_active_active_oh_8[2],3'h0,
- active_active_active_oh_8[1],3'h0,active_active_active_oh_8[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_8 = {active_active_active_oh_8[7],3'h0,active_active_active_oh_8[6],3'h0,
- active_active_active_oh_8[5],3'h0,active_active_active_oh_8[4],3'h0,active_active_active_oh3_lo_lo_8}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_8 = {active_active_active_oh_8[11],3'h0,active_active_active_oh_8[10],3'h0,
- active_active_active_oh_8[9],3'h0,active_active_active_oh_8[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_8 = {active_active_active_oh_8[15],3'h0,active_active_active_oh_8[14],3'h0,
- active_active_active_oh_8[13],3'h0,active_active_active_oh_8[12],3'h0,active_active_active_oh3_hi_lo_8,
- active_active_active_oh3_lo_8}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_8 = f_io_entry_2_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_245 = ~f_io_entry_2_bits_m & active_active_active_idx_8 == 2'h0 |
- f_io_entry_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_246 = _active_active_active_active_T_245 ? active_active_active_oh0_8 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_252 = _active_active_active_active_T_180 & active_active_active_idx_8 == 2'h1 |
- _active_active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_253 = _active_active_active_active_T_252 ? active_active_active_oh1_8 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_254 = _active_active_active_active_T_246 |
- _active_active_active_active_T_253; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_260 = _active_active_active_active_T_180 & active_active_active_idx_8 == 2'h2 |
- _active_active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_261 = _active_active_active_active_T_260 ? active_active_active_oh2_8 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_262 = _active_active_active_active_T_254 |
- _active_active_active_active_T_261; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_268 = _active_active_active_active_T_180 & active_active_active_idx_8 == 2'h3 |
- _active_active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_269 = _active_active_active_active_T_268 ? active_active_active_oh3_8 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_8 = _active_active_active_active_T_262 | _active_active_active_active_T_269; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_407 = f_io_entry_2_bits_tin_vu_valid ? active_active_active_active_8 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_14 = _active_active_active_T_402 | _active_active_active_T_407; // @[VAlu.scala 250:74]
- wire [63:0] active_active_6 = f_io_entry_2_valid ? active_active_active_14 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_29 = _active_T_28 | active_active_6; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_9 = f_io_entry_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_9 = 16'h1 << active_active_active_oh_shiftAmount_9; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_9 = {3'h0,active_active_active_oh_9[3],3'h0,active_active_active_oh_9[2],3'h0
- ,active_active_active_oh_9[1],3'h0,active_active_active_oh_9[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_9 = {3'h0,active_active_active_oh_9[7],3'h0,active_active_active_oh_9[6],3'h0,
- active_active_active_oh_9[5],3'h0,active_active_active_oh_9[4],active_active_active_oh0_lo_lo_9}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_9 = {3'h0,active_active_active_oh_9[11],3'h0,active_active_active_oh_9[10],3'h0
- ,active_active_active_oh_9[9],3'h0,active_active_active_oh_9[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_9 = {3'h0,active_active_active_oh_9[15],3'h0,active_active_active_oh_9[14],3'h0,
- active_active_active_oh_9[13],3'h0,active_active_active_oh_9[12],active_active_active_oh0_hi_lo_9,
- active_active_active_oh0_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_9 = {2'h0,active_active_active_oh_9[1],1'h0,2'h0,
- active_active_active_oh_9[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_9 = {2'h0,active_active_active_oh_9[3],1'h0,2'h0,active_active_active_oh_9[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_9 = {2'h0,active_active_active_oh_9[5],1'h0,2'h0,
- active_active_active_oh_9[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_9 = {2'h0,active_active_active_oh_9[7],1'h0,2'h0,active_active_active_oh_9[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_9,active_active_active_oh1_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_9 = {2'h0,active_active_active_oh_9[9],1'h0,2'h0,
- active_active_active_oh_9[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_9 = {2'h0,active_active_active_oh_9[11],1'h0,2'h0,active_active_active_oh_9
- [10],1'h0,active_active_active_oh1_hi_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_9 = {2'h0,active_active_active_oh_9[13],1'h0,2'h0,
- active_active_active_oh_9[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_9 = {2'h0,active_active_active_oh_9[15],1'h0,2'h0,active_active_active_oh_9[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_9,active_active_active_oh1_hi_lo_9,active_active_active_oh1_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_9 = {1'h0,active_active_active_oh_9[1],2'h0,1'h0,
- active_active_active_oh_9[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_9 = {1'h0,active_active_active_oh_9[3],2'h0,1'h0,active_active_active_oh_9[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_9 = {1'h0,active_active_active_oh_9[5],2'h0,1'h0,
- active_active_active_oh_9[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_9 = {1'h0,active_active_active_oh_9[7],2'h0,1'h0,active_active_active_oh_9[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_9,active_active_active_oh2_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_9 = {1'h0,active_active_active_oh_9[9],2'h0,1'h0,
- active_active_active_oh_9[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_9 = {1'h0,active_active_active_oh_9[11],2'h0,1'h0,active_active_active_oh_9
- [10],2'h0,active_active_active_oh2_hi_lo_lo_9}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_9 = {1'h0,active_active_active_oh_9[13],2'h0,1'h0,
- active_active_active_oh_9[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_9 = {1'h0,active_active_active_oh_9[15],2'h0,1'h0,active_active_active_oh_9[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_9,active_active_active_oh2_hi_lo_9,active_active_active_oh2_lo_9}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_9 = {active_active_active_oh_9[3],3'h0,active_active_active_oh_9[2],3'h0,
- active_active_active_oh_9[1],3'h0,active_active_active_oh_9[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_9 = {active_active_active_oh_9[7],3'h0,active_active_active_oh_9[6],3'h0,
- active_active_active_oh_9[5],3'h0,active_active_active_oh_9[4],3'h0,active_active_active_oh3_lo_lo_9}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_9 = {active_active_active_oh_9[11],3'h0,active_active_active_oh_9[10],3'h0,
- active_active_active_oh_9[9],3'h0,active_active_active_oh_9[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_9 = {active_active_active_oh_9[15],3'h0,active_active_active_oh_9[14],3'h0,
- active_active_active_oh_9[13],3'h0,active_active_active_oh_9[12],3'h0,active_active_active_oh3_hi_lo_9,
- active_active_active_oh3_lo_9}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_9 = f_io_entry_3_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_270 = ~f_io_entry_3_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_274 = f_io_entry_3_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_275 = ~f_io_entry_3_bits_m & active_active_active_idx_9 == 2'h0 |
- f_io_entry_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_276 = _active_active_active_active_T_275 ? active_active_active_oh0_9 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_282 = _active_active_active_active_T_270 & active_active_active_idx_9 == 2'h1 |
- _active_active_active_active_T_274; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_283 = _active_active_active_active_T_282 ? active_active_active_oh1_9 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_284 = _active_active_active_active_T_276 |
- _active_active_active_active_T_283; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_290 = _active_active_active_active_T_270 & active_active_active_idx_9 == 2'h2 |
- _active_active_active_active_T_274; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_291 = _active_active_active_active_T_290 ? active_active_active_oh2_9 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_292 = _active_active_active_active_T_284 |
- _active_active_active_active_T_291; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_298 = _active_active_active_active_T_270 & active_active_active_idx_9 == 2'h3 |
- _active_active_active_active_T_274; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_299 = _active_active_active_active_T_298 ? active_active_active_oh3_9 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_9 = _active_active_active_active_T_292 | _active_active_active_active_T_299; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_412 = f_io_entry_3_bits_tin_vs_valid ? active_active_active_active_9 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_10 = f_io_entry_3_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_10 = 16'h1 << active_active_active_oh_shiftAmount_10; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_10 = {3'h0,active_active_active_oh_10[3],3'h0,active_active_active_oh_10[2]
- ,3'h0,active_active_active_oh_10[1],3'h0,active_active_active_oh_10[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_10 = {3'h0,active_active_active_oh_10[7],3'h0,active_active_active_oh_10[6],3'h0
- ,active_active_active_oh_10[5],3'h0,active_active_active_oh_10[4],active_active_active_oh0_lo_lo_10}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_10 = {3'h0,active_active_active_oh_10[11],3'h0,active_active_active_oh_10[
- 10],3'h0,active_active_active_oh_10[9],3'h0,active_active_active_oh_10[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_10 = {3'h0,active_active_active_oh_10[15],3'h0,active_active_active_oh_10[14],3'h0
- ,active_active_active_oh_10[13],3'h0,active_active_active_oh_10[12],active_active_active_oh0_hi_lo_10,
- active_active_active_oh0_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_10 = {2'h0,active_active_active_oh_10[1],1'h0,2'h0,
- active_active_active_oh_10[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_10 = {2'h0,active_active_active_oh_10[3],1'h0,2'h0,
- active_active_active_oh_10[2],1'h0,active_active_active_oh1_lo_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_10 = {2'h0,active_active_active_oh_10[5],1'h0,2'h0,
- active_active_active_oh_10[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_10 = {2'h0,active_active_active_oh_10[7],1'h0,2'h0,active_active_active_oh_10[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_10,active_active_active_oh1_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_10 = {2'h0,active_active_active_oh_10[9],1'h0,2'h0,
- active_active_active_oh_10[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_10 = {2'h0,active_active_active_oh_10[11],1'h0,2'h0,
- active_active_active_oh_10[10],1'h0,active_active_active_oh1_hi_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_10 = {2'h0,active_active_active_oh_10[13],1'h0,2'h0,
- active_active_active_oh_10[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_10 = {2'h0,active_active_active_oh_10[15],1'h0,2'h0,active_active_active_oh_10[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_10,active_active_active_oh1_hi_lo_10,active_active_active_oh1_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_10 = {1'h0,active_active_active_oh_10[1],2'h0,1'h0,
- active_active_active_oh_10[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_10 = {1'h0,active_active_active_oh_10[3],2'h0,1'h0,
- active_active_active_oh_10[2],2'h0,active_active_active_oh2_lo_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_10 = {1'h0,active_active_active_oh_10[5],2'h0,1'h0,
- active_active_active_oh_10[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_10 = {1'h0,active_active_active_oh_10[7],2'h0,1'h0,active_active_active_oh_10[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_10,active_active_active_oh2_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_10 = {1'h0,active_active_active_oh_10[9],2'h0,1'h0,
- active_active_active_oh_10[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_10 = {1'h0,active_active_active_oh_10[11],2'h0,1'h0,
- active_active_active_oh_10[10],2'h0,active_active_active_oh2_hi_lo_lo_10}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_10 = {1'h0,active_active_active_oh_10[13],2'h0,1'h0,
- active_active_active_oh_10[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_10 = {1'h0,active_active_active_oh_10[15],2'h0,1'h0,active_active_active_oh_10[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_10,active_active_active_oh2_hi_lo_10,active_active_active_oh2_lo_10}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_10 = {active_active_active_oh_10[3],3'h0,active_active_active_oh_10[2],3'h0
- ,active_active_active_oh_10[1],3'h0,active_active_active_oh_10[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_10 = {active_active_active_oh_10[7],3'h0,active_active_active_oh_10[6],3'h0,
- active_active_active_oh_10[5],3'h0,active_active_active_oh_10[4],3'h0,active_active_active_oh3_lo_lo_10}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_10 = {active_active_active_oh_10[11],3'h0,active_active_active_oh_10[10],3'h0
- ,active_active_active_oh_10[9],3'h0,active_active_active_oh_10[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_10 = {active_active_active_oh_10[15],3'h0,active_active_active_oh_10[14],3'h0,
- active_active_active_oh_10[13],3'h0,active_active_active_oh_10[12],3'h0,active_active_active_oh3_hi_lo_10,
- active_active_active_oh3_lo_10}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_10 = f_io_entry_3_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_305 = ~f_io_entry_3_bits_m & active_active_active_idx_10 == 2'h0 |
- f_io_entry_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_306 = _active_active_active_active_T_305 ? active_active_active_oh0_10 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_312 = _active_active_active_active_T_270 & active_active_active_idx_10 == 2'h1 |
- _active_active_active_active_T_274; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_313 = _active_active_active_active_T_312 ? active_active_active_oh1_10 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_314 = _active_active_active_active_T_306 |
- _active_active_active_active_T_313; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_320 = _active_active_active_active_T_270 & active_active_active_idx_10 == 2'h2 |
- _active_active_active_active_T_274; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_321 = _active_active_active_active_T_320 ? active_active_active_oh2_10 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_322 = _active_active_active_active_T_314 |
- _active_active_active_active_T_321; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_328 = _active_active_active_active_T_270 & active_active_active_idx_10 == 2'h3 |
- _active_active_active_active_T_274; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_329 = _active_active_active_active_T_328 ? active_active_active_oh3_10 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_10 = _active_active_active_active_T_322 | _active_active_active_active_T_329; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_417 = f_io_entry_3_bits_tin_vt_valid ? active_active_active_active_10 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_418 = _active_active_active_T_412 | _active_active_active_T_417; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_11 = f_io_entry_3_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_11 = 16'h1 << active_active_active_oh_shiftAmount_11; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_11 = {3'h0,active_active_active_oh_11[3],3'h0,active_active_active_oh_11[2]
- ,3'h0,active_active_active_oh_11[1],3'h0,active_active_active_oh_11[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_11 = {3'h0,active_active_active_oh_11[7],3'h0,active_active_active_oh_11[6],3'h0
- ,active_active_active_oh_11[5],3'h0,active_active_active_oh_11[4],active_active_active_oh0_lo_lo_11}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_11 = {3'h0,active_active_active_oh_11[11],3'h0,active_active_active_oh_11[
- 10],3'h0,active_active_active_oh_11[9],3'h0,active_active_active_oh_11[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_11 = {3'h0,active_active_active_oh_11[15],3'h0,active_active_active_oh_11[14],3'h0
- ,active_active_active_oh_11[13],3'h0,active_active_active_oh_11[12],active_active_active_oh0_hi_lo_11,
- active_active_active_oh0_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_11 = {2'h0,active_active_active_oh_11[1],1'h0,2'h0,
- active_active_active_oh_11[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_11 = {2'h0,active_active_active_oh_11[3],1'h0,2'h0,
- active_active_active_oh_11[2],1'h0,active_active_active_oh1_lo_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_11 = {2'h0,active_active_active_oh_11[5],1'h0,2'h0,
- active_active_active_oh_11[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_11 = {2'h0,active_active_active_oh_11[7],1'h0,2'h0,active_active_active_oh_11[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_11,active_active_active_oh1_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_11 = {2'h0,active_active_active_oh_11[9],1'h0,2'h0,
- active_active_active_oh_11[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_11 = {2'h0,active_active_active_oh_11[11],1'h0,2'h0,
- active_active_active_oh_11[10],1'h0,active_active_active_oh1_hi_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_11 = {2'h0,active_active_active_oh_11[13],1'h0,2'h0,
- active_active_active_oh_11[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_11 = {2'h0,active_active_active_oh_11[15],1'h0,2'h0,active_active_active_oh_11[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_11,active_active_active_oh1_hi_lo_11,active_active_active_oh1_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_11 = {1'h0,active_active_active_oh_11[1],2'h0,1'h0,
- active_active_active_oh_11[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_11 = {1'h0,active_active_active_oh_11[3],2'h0,1'h0,
- active_active_active_oh_11[2],2'h0,active_active_active_oh2_lo_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_11 = {1'h0,active_active_active_oh_11[5],2'h0,1'h0,
- active_active_active_oh_11[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_11 = {1'h0,active_active_active_oh_11[7],2'h0,1'h0,active_active_active_oh_11[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_11,active_active_active_oh2_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_11 = {1'h0,active_active_active_oh_11[9],2'h0,1'h0,
- active_active_active_oh_11[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_11 = {1'h0,active_active_active_oh_11[11],2'h0,1'h0,
- active_active_active_oh_11[10],2'h0,active_active_active_oh2_hi_lo_lo_11}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_11 = {1'h0,active_active_active_oh_11[13],2'h0,1'h0,
- active_active_active_oh_11[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_11 = {1'h0,active_active_active_oh_11[15],2'h0,1'h0,active_active_active_oh_11[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_11,active_active_active_oh2_hi_lo_11,active_active_active_oh2_lo_11}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_11 = {active_active_active_oh_11[3],3'h0,active_active_active_oh_11[2],3'h0
- ,active_active_active_oh_11[1],3'h0,active_active_active_oh_11[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_11 = {active_active_active_oh_11[7],3'h0,active_active_active_oh_11[6],3'h0,
- active_active_active_oh_11[5],3'h0,active_active_active_oh_11[4],3'h0,active_active_active_oh3_lo_lo_11}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_11 = {active_active_active_oh_11[11],3'h0,active_active_active_oh_11[10],3'h0
- ,active_active_active_oh_11[9],3'h0,active_active_active_oh_11[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_11 = {active_active_active_oh_11[15],3'h0,active_active_active_oh_11[14],3'h0,
- active_active_active_oh_11[13],3'h0,active_active_active_oh_11[12],3'h0,active_active_active_oh3_hi_lo_11,
- active_active_active_oh3_lo_11}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_11 = f_io_entry_3_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_335 = ~f_io_entry_3_bits_m & active_active_active_idx_11 == 2'h0 |
- f_io_entry_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_336 = _active_active_active_active_T_335 ? active_active_active_oh0_11 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_342 = _active_active_active_active_T_270 & active_active_active_idx_11 == 2'h1 |
- _active_active_active_active_T_274; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_343 = _active_active_active_active_T_342 ? active_active_active_oh1_11 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_344 = _active_active_active_active_T_336 |
- _active_active_active_active_T_343; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_350 = _active_active_active_active_T_270 & active_active_active_idx_11 == 2'h2 |
- _active_active_active_active_T_274; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_351 = _active_active_active_active_T_350 ? active_active_active_oh2_11 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_352 = _active_active_active_active_T_344 |
- _active_active_active_active_T_351; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_358 = _active_active_active_active_T_270 & active_active_active_idx_11 == 2'h3 |
- _active_active_active_active_T_274; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_359 = _active_active_active_active_T_358 ? active_active_active_oh3_11 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_11 = _active_active_active_active_T_352 | _active_active_active_active_T_359; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_423 = f_io_entry_3_bits_tin_vu_valid ? active_active_active_active_11 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_15 = _active_active_active_T_418 | _active_active_active_T_423; // @[VAlu.scala 250:74]
- wire [63:0] active_active_7 = f_io_entry_3_valid ? active_active_active_15 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_30 = _active_T_29 | active_active_7; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_12 = f_io_entry_4_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_12 = 16'h1 << active_active_active_oh_shiftAmount_12; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_12 = {3'h0,active_active_active_oh_12[3],3'h0,active_active_active_oh_12[2]
- ,3'h0,active_active_active_oh_12[1],3'h0,active_active_active_oh_12[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_12 = {3'h0,active_active_active_oh_12[7],3'h0,active_active_active_oh_12[6],3'h0
- ,active_active_active_oh_12[5],3'h0,active_active_active_oh_12[4],active_active_active_oh0_lo_lo_12}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_12 = {3'h0,active_active_active_oh_12[11],3'h0,active_active_active_oh_12[
- 10],3'h0,active_active_active_oh_12[9],3'h0,active_active_active_oh_12[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_12 = {3'h0,active_active_active_oh_12[15],3'h0,active_active_active_oh_12[14],3'h0
- ,active_active_active_oh_12[13],3'h0,active_active_active_oh_12[12],active_active_active_oh0_hi_lo_12,
- active_active_active_oh0_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_12 = {2'h0,active_active_active_oh_12[1],1'h0,2'h0,
- active_active_active_oh_12[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_12 = {2'h0,active_active_active_oh_12[3],1'h0,2'h0,
- active_active_active_oh_12[2],1'h0,active_active_active_oh1_lo_lo_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_12 = {2'h0,active_active_active_oh_12[5],1'h0,2'h0,
- active_active_active_oh_12[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_12 = {2'h0,active_active_active_oh_12[7],1'h0,2'h0,active_active_active_oh_12[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_12,active_active_active_oh1_lo_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_12 = {2'h0,active_active_active_oh_12[9],1'h0,2'h0,
- active_active_active_oh_12[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_12 = {2'h0,active_active_active_oh_12[11],1'h0,2'h0,
- active_active_active_oh_12[10],1'h0,active_active_active_oh1_hi_lo_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_12 = {2'h0,active_active_active_oh_12[13],1'h0,2'h0,
- active_active_active_oh_12[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_12 = {2'h0,active_active_active_oh_12[15],1'h0,2'h0,active_active_active_oh_12[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_12,active_active_active_oh1_hi_lo_12,active_active_active_oh1_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_12 = {1'h0,active_active_active_oh_12[1],2'h0,1'h0,
- active_active_active_oh_12[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_12 = {1'h0,active_active_active_oh_12[3],2'h0,1'h0,
- active_active_active_oh_12[2],2'h0,active_active_active_oh2_lo_lo_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_12 = {1'h0,active_active_active_oh_12[5],2'h0,1'h0,
- active_active_active_oh_12[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_12 = {1'h0,active_active_active_oh_12[7],2'h0,1'h0,active_active_active_oh_12[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_12,active_active_active_oh2_lo_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_12 = {1'h0,active_active_active_oh_12[9],2'h0,1'h0,
- active_active_active_oh_12[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_12 = {1'h0,active_active_active_oh_12[11],2'h0,1'h0,
- active_active_active_oh_12[10],2'h0,active_active_active_oh2_hi_lo_lo_12}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_12 = {1'h0,active_active_active_oh_12[13],2'h0,1'h0,
- active_active_active_oh_12[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_12 = {1'h0,active_active_active_oh_12[15],2'h0,1'h0,active_active_active_oh_12[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_12,active_active_active_oh2_hi_lo_12,active_active_active_oh2_lo_12}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_12 = {active_active_active_oh_12[3],3'h0,active_active_active_oh_12[2],3'h0
- ,active_active_active_oh_12[1],3'h0,active_active_active_oh_12[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_12 = {active_active_active_oh_12[7],3'h0,active_active_active_oh_12[6],3'h0,
- active_active_active_oh_12[5],3'h0,active_active_active_oh_12[4],3'h0,active_active_active_oh3_lo_lo_12}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_12 = {active_active_active_oh_12[11],3'h0,active_active_active_oh_12[10],3'h0
- ,active_active_active_oh_12[9],3'h0,active_active_active_oh_12[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_12 = {active_active_active_oh_12[15],3'h0,active_active_active_oh_12[14],3'h0,
- active_active_active_oh_12[13],3'h0,active_active_active_oh_12[12],3'h0,active_active_active_oh3_hi_lo_12,
- active_active_active_oh3_lo_12}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_12 = f_io_entry_4_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_360 = ~f_io_entry_4_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_364 = f_io_entry_4_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_365 = ~f_io_entry_4_bits_m & active_active_active_idx_12 == 2'h0 |
- f_io_entry_4_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_366 = _active_active_active_active_T_365 ? active_active_active_oh0_12 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_372 = _active_active_active_active_T_360 & active_active_active_idx_12 == 2'h1 |
- _active_active_active_active_T_364; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_373 = _active_active_active_active_T_372 ? active_active_active_oh1_12 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_374 = _active_active_active_active_T_366 |
- _active_active_active_active_T_373; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_380 = _active_active_active_active_T_360 & active_active_active_idx_12 == 2'h2 |
- _active_active_active_active_T_364; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_381 = _active_active_active_active_T_380 ? active_active_active_oh2_12 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_382 = _active_active_active_active_T_374 |
- _active_active_active_active_T_381; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_388 = _active_active_active_active_T_360 & active_active_active_idx_12 == 2'h3 |
- _active_active_active_active_T_364; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_389 = _active_active_active_active_T_388 ? active_active_active_oh3_12 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_12 = _active_active_active_active_T_382 | _active_active_active_active_T_389; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_428 = f_io_entry_4_bits_tin_vs_valid ? active_active_active_active_12 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_13 = f_io_entry_4_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_13 = 16'h1 << active_active_active_oh_shiftAmount_13; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_13 = {3'h0,active_active_active_oh_13[3],3'h0,active_active_active_oh_13[2]
- ,3'h0,active_active_active_oh_13[1],3'h0,active_active_active_oh_13[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_13 = {3'h0,active_active_active_oh_13[7],3'h0,active_active_active_oh_13[6],3'h0
- ,active_active_active_oh_13[5],3'h0,active_active_active_oh_13[4],active_active_active_oh0_lo_lo_13}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_13 = {3'h0,active_active_active_oh_13[11],3'h0,active_active_active_oh_13[
- 10],3'h0,active_active_active_oh_13[9],3'h0,active_active_active_oh_13[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_13 = {3'h0,active_active_active_oh_13[15],3'h0,active_active_active_oh_13[14],3'h0
- ,active_active_active_oh_13[13],3'h0,active_active_active_oh_13[12],active_active_active_oh0_hi_lo_13,
- active_active_active_oh0_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_13 = {2'h0,active_active_active_oh_13[1],1'h0,2'h0,
- active_active_active_oh_13[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_13 = {2'h0,active_active_active_oh_13[3],1'h0,2'h0,
- active_active_active_oh_13[2],1'h0,active_active_active_oh1_lo_lo_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_13 = {2'h0,active_active_active_oh_13[5],1'h0,2'h0,
- active_active_active_oh_13[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_13 = {2'h0,active_active_active_oh_13[7],1'h0,2'h0,active_active_active_oh_13[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_13,active_active_active_oh1_lo_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_13 = {2'h0,active_active_active_oh_13[9],1'h0,2'h0,
- active_active_active_oh_13[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_13 = {2'h0,active_active_active_oh_13[11],1'h0,2'h0,
- active_active_active_oh_13[10],1'h0,active_active_active_oh1_hi_lo_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_13 = {2'h0,active_active_active_oh_13[13],1'h0,2'h0,
- active_active_active_oh_13[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_13 = {2'h0,active_active_active_oh_13[15],1'h0,2'h0,active_active_active_oh_13[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_13,active_active_active_oh1_hi_lo_13,active_active_active_oh1_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_13 = {1'h0,active_active_active_oh_13[1],2'h0,1'h0,
- active_active_active_oh_13[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_13 = {1'h0,active_active_active_oh_13[3],2'h0,1'h0,
- active_active_active_oh_13[2],2'h0,active_active_active_oh2_lo_lo_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_13 = {1'h0,active_active_active_oh_13[5],2'h0,1'h0,
- active_active_active_oh_13[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_13 = {1'h0,active_active_active_oh_13[7],2'h0,1'h0,active_active_active_oh_13[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_13,active_active_active_oh2_lo_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_13 = {1'h0,active_active_active_oh_13[9],2'h0,1'h0,
- active_active_active_oh_13[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_13 = {1'h0,active_active_active_oh_13[11],2'h0,1'h0,
- active_active_active_oh_13[10],2'h0,active_active_active_oh2_hi_lo_lo_13}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_13 = {1'h0,active_active_active_oh_13[13],2'h0,1'h0,
- active_active_active_oh_13[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_13 = {1'h0,active_active_active_oh_13[15],2'h0,1'h0,active_active_active_oh_13[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_13,active_active_active_oh2_hi_lo_13,active_active_active_oh2_lo_13}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_13 = {active_active_active_oh_13[3],3'h0,active_active_active_oh_13[2],3'h0
- ,active_active_active_oh_13[1],3'h0,active_active_active_oh_13[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_13 = {active_active_active_oh_13[7],3'h0,active_active_active_oh_13[6],3'h0,
- active_active_active_oh_13[5],3'h0,active_active_active_oh_13[4],3'h0,active_active_active_oh3_lo_lo_13}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_13 = {active_active_active_oh_13[11],3'h0,active_active_active_oh_13[10],3'h0
- ,active_active_active_oh_13[9],3'h0,active_active_active_oh_13[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_13 = {active_active_active_oh_13[15],3'h0,active_active_active_oh_13[14],3'h0,
- active_active_active_oh_13[13],3'h0,active_active_active_oh_13[12],3'h0,active_active_active_oh3_hi_lo_13,
- active_active_active_oh3_lo_13}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_13 = f_io_entry_4_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_395 = ~f_io_entry_4_bits_m & active_active_active_idx_13 == 2'h0 |
- f_io_entry_4_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_396 = _active_active_active_active_T_395 ? active_active_active_oh0_13 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_402 = _active_active_active_active_T_360 & active_active_active_idx_13 == 2'h1 |
- _active_active_active_active_T_364; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_403 = _active_active_active_active_T_402 ? active_active_active_oh1_13 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_404 = _active_active_active_active_T_396 |
- _active_active_active_active_T_403; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_410 = _active_active_active_active_T_360 & active_active_active_idx_13 == 2'h2 |
- _active_active_active_active_T_364; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_411 = _active_active_active_active_T_410 ? active_active_active_oh2_13 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_412 = _active_active_active_active_T_404 |
- _active_active_active_active_T_411; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_418 = _active_active_active_active_T_360 & active_active_active_idx_13 == 2'h3 |
- _active_active_active_active_T_364; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_419 = _active_active_active_active_T_418 ? active_active_active_oh3_13 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_13 = _active_active_active_active_T_412 | _active_active_active_active_T_419; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_433 = f_io_entry_4_bits_tin_vt_valid ? active_active_active_active_13 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_434 = _active_active_active_T_428 | _active_active_active_T_433; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_14 = f_io_entry_4_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_14 = 16'h1 << active_active_active_oh_shiftAmount_14; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_14 = {3'h0,active_active_active_oh_14[3],3'h0,active_active_active_oh_14[2]
- ,3'h0,active_active_active_oh_14[1],3'h0,active_active_active_oh_14[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_14 = {3'h0,active_active_active_oh_14[7],3'h0,active_active_active_oh_14[6],3'h0
- ,active_active_active_oh_14[5],3'h0,active_active_active_oh_14[4],active_active_active_oh0_lo_lo_14}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_14 = {3'h0,active_active_active_oh_14[11],3'h0,active_active_active_oh_14[
- 10],3'h0,active_active_active_oh_14[9],3'h0,active_active_active_oh_14[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_14 = {3'h0,active_active_active_oh_14[15],3'h0,active_active_active_oh_14[14],3'h0
- ,active_active_active_oh_14[13],3'h0,active_active_active_oh_14[12],active_active_active_oh0_hi_lo_14,
- active_active_active_oh0_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_14 = {2'h0,active_active_active_oh_14[1],1'h0,2'h0,
- active_active_active_oh_14[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_14 = {2'h0,active_active_active_oh_14[3],1'h0,2'h0,
- active_active_active_oh_14[2],1'h0,active_active_active_oh1_lo_lo_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_14 = {2'h0,active_active_active_oh_14[5],1'h0,2'h0,
- active_active_active_oh_14[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_14 = {2'h0,active_active_active_oh_14[7],1'h0,2'h0,active_active_active_oh_14[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_14,active_active_active_oh1_lo_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_14 = {2'h0,active_active_active_oh_14[9],1'h0,2'h0,
- active_active_active_oh_14[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_14 = {2'h0,active_active_active_oh_14[11],1'h0,2'h0,
- active_active_active_oh_14[10],1'h0,active_active_active_oh1_hi_lo_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_14 = {2'h0,active_active_active_oh_14[13],1'h0,2'h0,
- active_active_active_oh_14[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_14 = {2'h0,active_active_active_oh_14[15],1'h0,2'h0,active_active_active_oh_14[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_14,active_active_active_oh1_hi_lo_14,active_active_active_oh1_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_14 = {1'h0,active_active_active_oh_14[1],2'h0,1'h0,
- active_active_active_oh_14[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_14 = {1'h0,active_active_active_oh_14[3],2'h0,1'h0,
- active_active_active_oh_14[2],2'h0,active_active_active_oh2_lo_lo_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_14 = {1'h0,active_active_active_oh_14[5],2'h0,1'h0,
- active_active_active_oh_14[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_14 = {1'h0,active_active_active_oh_14[7],2'h0,1'h0,active_active_active_oh_14[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_14,active_active_active_oh2_lo_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_14 = {1'h0,active_active_active_oh_14[9],2'h0,1'h0,
- active_active_active_oh_14[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_14 = {1'h0,active_active_active_oh_14[11],2'h0,1'h0,
- active_active_active_oh_14[10],2'h0,active_active_active_oh2_hi_lo_lo_14}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_14 = {1'h0,active_active_active_oh_14[13],2'h0,1'h0,
- active_active_active_oh_14[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_14 = {1'h0,active_active_active_oh_14[15],2'h0,1'h0,active_active_active_oh_14[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_14,active_active_active_oh2_hi_lo_14,active_active_active_oh2_lo_14}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_14 = {active_active_active_oh_14[3],3'h0,active_active_active_oh_14[2],3'h0
- ,active_active_active_oh_14[1],3'h0,active_active_active_oh_14[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_14 = {active_active_active_oh_14[7],3'h0,active_active_active_oh_14[6],3'h0,
- active_active_active_oh_14[5],3'h0,active_active_active_oh_14[4],3'h0,active_active_active_oh3_lo_lo_14}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_14 = {active_active_active_oh_14[11],3'h0,active_active_active_oh_14[10],3'h0
- ,active_active_active_oh_14[9],3'h0,active_active_active_oh_14[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_14 = {active_active_active_oh_14[15],3'h0,active_active_active_oh_14[14],3'h0,
- active_active_active_oh_14[13],3'h0,active_active_active_oh_14[12],3'h0,active_active_active_oh3_hi_lo_14,
- active_active_active_oh3_lo_14}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_14 = f_io_entry_4_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_425 = ~f_io_entry_4_bits_m & active_active_active_idx_14 == 2'h0 |
- f_io_entry_4_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_426 = _active_active_active_active_T_425 ? active_active_active_oh0_14 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_432 = _active_active_active_active_T_360 & active_active_active_idx_14 == 2'h1 |
- _active_active_active_active_T_364; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_433 = _active_active_active_active_T_432 ? active_active_active_oh1_14 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_434 = _active_active_active_active_T_426 |
- _active_active_active_active_T_433; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_440 = _active_active_active_active_T_360 & active_active_active_idx_14 == 2'h2 |
- _active_active_active_active_T_364; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_441 = _active_active_active_active_T_440 ? active_active_active_oh2_14 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_442 = _active_active_active_active_T_434 |
- _active_active_active_active_T_441; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_448 = _active_active_active_active_T_360 & active_active_active_idx_14 == 2'h3 |
- _active_active_active_active_T_364; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_449 = _active_active_active_active_T_448 ? active_active_active_oh3_14 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_14 = _active_active_active_active_T_442 | _active_active_active_active_T_449; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_439 = f_io_entry_4_bits_tin_vu_valid ? active_active_active_active_14 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_16 = _active_active_active_T_434 | _active_active_active_T_439; // @[VAlu.scala 250:74]
- wire [63:0] active_active_8 = f_io_entry_4_valid ? active_active_active_16 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_31 = _active_T_30 | active_active_8; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_15 = f_io_entry_5_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_15 = 16'h1 << active_active_active_oh_shiftAmount_15; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_15 = {3'h0,active_active_active_oh_15[3],3'h0,active_active_active_oh_15[2]
- ,3'h0,active_active_active_oh_15[1],3'h0,active_active_active_oh_15[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_15 = {3'h0,active_active_active_oh_15[7],3'h0,active_active_active_oh_15[6],3'h0
- ,active_active_active_oh_15[5],3'h0,active_active_active_oh_15[4],active_active_active_oh0_lo_lo_15}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_15 = {3'h0,active_active_active_oh_15[11],3'h0,active_active_active_oh_15[
- 10],3'h0,active_active_active_oh_15[9],3'h0,active_active_active_oh_15[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_15 = {3'h0,active_active_active_oh_15[15],3'h0,active_active_active_oh_15[14],3'h0
- ,active_active_active_oh_15[13],3'h0,active_active_active_oh_15[12],active_active_active_oh0_hi_lo_15,
- active_active_active_oh0_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_15 = {2'h0,active_active_active_oh_15[1],1'h0,2'h0,
- active_active_active_oh_15[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_15 = {2'h0,active_active_active_oh_15[3],1'h0,2'h0,
- active_active_active_oh_15[2],1'h0,active_active_active_oh1_lo_lo_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_15 = {2'h0,active_active_active_oh_15[5],1'h0,2'h0,
- active_active_active_oh_15[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_15 = {2'h0,active_active_active_oh_15[7],1'h0,2'h0,active_active_active_oh_15[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_15,active_active_active_oh1_lo_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_15 = {2'h0,active_active_active_oh_15[9],1'h0,2'h0,
- active_active_active_oh_15[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_15 = {2'h0,active_active_active_oh_15[11],1'h0,2'h0,
- active_active_active_oh_15[10],1'h0,active_active_active_oh1_hi_lo_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_15 = {2'h0,active_active_active_oh_15[13],1'h0,2'h0,
- active_active_active_oh_15[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_15 = {2'h0,active_active_active_oh_15[15],1'h0,2'h0,active_active_active_oh_15[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_15,active_active_active_oh1_hi_lo_15,active_active_active_oh1_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_15 = {1'h0,active_active_active_oh_15[1],2'h0,1'h0,
- active_active_active_oh_15[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_15 = {1'h0,active_active_active_oh_15[3],2'h0,1'h0,
- active_active_active_oh_15[2],2'h0,active_active_active_oh2_lo_lo_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_15 = {1'h0,active_active_active_oh_15[5],2'h0,1'h0,
- active_active_active_oh_15[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_15 = {1'h0,active_active_active_oh_15[7],2'h0,1'h0,active_active_active_oh_15[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_15,active_active_active_oh2_lo_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_15 = {1'h0,active_active_active_oh_15[9],2'h0,1'h0,
- active_active_active_oh_15[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_15 = {1'h0,active_active_active_oh_15[11],2'h0,1'h0,
- active_active_active_oh_15[10],2'h0,active_active_active_oh2_hi_lo_lo_15}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_15 = {1'h0,active_active_active_oh_15[13],2'h0,1'h0,
- active_active_active_oh_15[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_15 = {1'h0,active_active_active_oh_15[15],2'h0,1'h0,active_active_active_oh_15[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_15,active_active_active_oh2_hi_lo_15,active_active_active_oh2_lo_15}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_15 = {active_active_active_oh_15[3],3'h0,active_active_active_oh_15[2],3'h0
- ,active_active_active_oh_15[1],3'h0,active_active_active_oh_15[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_15 = {active_active_active_oh_15[7],3'h0,active_active_active_oh_15[6],3'h0,
- active_active_active_oh_15[5],3'h0,active_active_active_oh_15[4],3'h0,active_active_active_oh3_lo_lo_15}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_15 = {active_active_active_oh_15[11],3'h0,active_active_active_oh_15[10],3'h0
- ,active_active_active_oh_15[9],3'h0,active_active_active_oh_15[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_15 = {active_active_active_oh_15[15],3'h0,active_active_active_oh_15[14],3'h0,
- active_active_active_oh_15[13],3'h0,active_active_active_oh_15[12],3'h0,active_active_active_oh3_hi_lo_15,
- active_active_active_oh3_lo_15}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_15 = f_io_entry_5_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_450 = ~f_io_entry_5_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_454 = f_io_entry_5_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_455 = ~f_io_entry_5_bits_m & active_active_active_idx_15 == 2'h0 |
- f_io_entry_5_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_456 = _active_active_active_active_T_455 ? active_active_active_oh0_15 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_462 = _active_active_active_active_T_450 & active_active_active_idx_15 == 2'h1 |
- _active_active_active_active_T_454; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_463 = _active_active_active_active_T_462 ? active_active_active_oh1_15 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_464 = _active_active_active_active_T_456 |
- _active_active_active_active_T_463; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_470 = _active_active_active_active_T_450 & active_active_active_idx_15 == 2'h2 |
- _active_active_active_active_T_454; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_471 = _active_active_active_active_T_470 ? active_active_active_oh2_15 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_472 = _active_active_active_active_T_464 |
- _active_active_active_active_T_471; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_478 = _active_active_active_active_T_450 & active_active_active_idx_15 == 2'h3 |
- _active_active_active_active_T_454; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_479 = _active_active_active_active_T_478 ? active_active_active_oh3_15 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_15 = _active_active_active_active_T_472 | _active_active_active_active_T_479; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_444 = f_io_entry_5_bits_tin_vs_valid ? active_active_active_active_15 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_16 = f_io_entry_5_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_16 = 16'h1 << active_active_active_oh_shiftAmount_16; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_16 = {3'h0,active_active_active_oh_16[3],3'h0,active_active_active_oh_16[2]
- ,3'h0,active_active_active_oh_16[1],3'h0,active_active_active_oh_16[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_16 = {3'h0,active_active_active_oh_16[7],3'h0,active_active_active_oh_16[6],3'h0
- ,active_active_active_oh_16[5],3'h0,active_active_active_oh_16[4],active_active_active_oh0_lo_lo_16}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_16 = {3'h0,active_active_active_oh_16[11],3'h0,active_active_active_oh_16[
- 10],3'h0,active_active_active_oh_16[9],3'h0,active_active_active_oh_16[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_16 = {3'h0,active_active_active_oh_16[15],3'h0,active_active_active_oh_16[14],3'h0
- ,active_active_active_oh_16[13],3'h0,active_active_active_oh_16[12],active_active_active_oh0_hi_lo_16,
- active_active_active_oh0_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_16 = {2'h0,active_active_active_oh_16[1],1'h0,2'h0,
- active_active_active_oh_16[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_16 = {2'h0,active_active_active_oh_16[3],1'h0,2'h0,
- active_active_active_oh_16[2],1'h0,active_active_active_oh1_lo_lo_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_16 = {2'h0,active_active_active_oh_16[5],1'h0,2'h0,
- active_active_active_oh_16[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_16 = {2'h0,active_active_active_oh_16[7],1'h0,2'h0,active_active_active_oh_16[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_16,active_active_active_oh1_lo_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_16 = {2'h0,active_active_active_oh_16[9],1'h0,2'h0,
- active_active_active_oh_16[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_16 = {2'h0,active_active_active_oh_16[11],1'h0,2'h0,
- active_active_active_oh_16[10],1'h0,active_active_active_oh1_hi_lo_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_16 = {2'h0,active_active_active_oh_16[13],1'h0,2'h0,
- active_active_active_oh_16[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_16 = {2'h0,active_active_active_oh_16[15],1'h0,2'h0,active_active_active_oh_16[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_16,active_active_active_oh1_hi_lo_16,active_active_active_oh1_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_16 = {1'h0,active_active_active_oh_16[1],2'h0,1'h0,
- active_active_active_oh_16[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_16 = {1'h0,active_active_active_oh_16[3],2'h0,1'h0,
- active_active_active_oh_16[2],2'h0,active_active_active_oh2_lo_lo_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_16 = {1'h0,active_active_active_oh_16[5],2'h0,1'h0,
- active_active_active_oh_16[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_16 = {1'h0,active_active_active_oh_16[7],2'h0,1'h0,active_active_active_oh_16[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_16,active_active_active_oh2_lo_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_16 = {1'h0,active_active_active_oh_16[9],2'h0,1'h0,
- active_active_active_oh_16[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_16 = {1'h0,active_active_active_oh_16[11],2'h0,1'h0,
- active_active_active_oh_16[10],2'h0,active_active_active_oh2_hi_lo_lo_16}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_16 = {1'h0,active_active_active_oh_16[13],2'h0,1'h0,
- active_active_active_oh_16[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_16 = {1'h0,active_active_active_oh_16[15],2'h0,1'h0,active_active_active_oh_16[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_16,active_active_active_oh2_hi_lo_16,active_active_active_oh2_lo_16}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_16 = {active_active_active_oh_16[3],3'h0,active_active_active_oh_16[2],3'h0
- ,active_active_active_oh_16[1],3'h0,active_active_active_oh_16[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_16 = {active_active_active_oh_16[7],3'h0,active_active_active_oh_16[6],3'h0,
- active_active_active_oh_16[5],3'h0,active_active_active_oh_16[4],3'h0,active_active_active_oh3_lo_lo_16}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_16 = {active_active_active_oh_16[11],3'h0,active_active_active_oh_16[10],3'h0
- ,active_active_active_oh_16[9],3'h0,active_active_active_oh_16[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_16 = {active_active_active_oh_16[15],3'h0,active_active_active_oh_16[14],3'h0,
- active_active_active_oh_16[13],3'h0,active_active_active_oh_16[12],3'h0,active_active_active_oh3_hi_lo_16,
- active_active_active_oh3_lo_16}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_16 = f_io_entry_5_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_485 = ~f_io_entry_5_bits_m & active_active_active_idx_16 == 2'h0 |
- f_io_entry_5_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_486 = _active_active_active_active_T_485 ? active_active_active_oh0_16 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_492 = _active_active_active_active_T_450 & active_active_active_idx_16 == 2'h1 |
- _active_active_active_active_T_454; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_493 = _active_active_active_active_T_492 ? active_active_active_oh1_16 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_494 = _active_active_active_active_T_486 |
- _active_active_active_active_T_493; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_500 = _active_active_active_active_T_450 & active_active_active_idx_16 == 2'h2 |
- _active_active_active_active_T_454; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_501 = _active_active_active_active_T_500 ? active_active_active_oh2_16 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_502 = _active_active_active_active_T_494 |
- _active_active_active_active_T_501; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_508 = _active_active_active_active_T_450 & active_active_active_idx_16 == 2'h3 |
- _active_active_active_active_T_454; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_509 = _active_active_active_active_T_508 ? active_active_active_oh3_16 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_16 = _active_active_active_active_T_502 | _active_active_active_active_T_509; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_449 = f_io_entry_5_bits_tin_vt_valid ? active_active_active_active_16 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_450 = _active_active_active_T_444 | _active_active_active_T_449; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_17 = f_io_entry_5_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_17 = 16'h1 << active_active_active_oh_shiftAmount_17; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_17 = {3'h0,active_active_active_oh_17[3],3'h0,active_active_active_oh_17[2]
- ,3'h0,active_active_active_oh_17[1],3'h0,active_active_active_oh_17[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_17 = {3'h0,active_active_active_oh_17[7],3'h0,active_active_active_oh_17[6],3'h0
- ,active_active_active_oh_17[5],3'h0,active_active_active_oh_17[4],active_active_active_oh0_lo_lo_17}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_17 = {3'h0,active_active_active_oh_17[11],3'h0,active_active_active_oh_17[
- 10],3'h0,active_active_active_oh_17[9],3'h0,active_active_active_oh_17[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_17 = {3'h0,active_active_active_oh_17[15],3'h0,active_active_active_oh_17[14],3'h0
- ,active_active_active_oh_17[13],3'h0,active_active_active_oh_17[12],active_active_active_oh0_hi_lo_17,
- active_active_active_oh0_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_17 = {2'h0,active_active_active_oh_17[1],1'h0,2'h0,
- active_active_active_oh_17[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_17 = {2'h0,active_active_active_oh_17[3],1'h0,2'h0,
- active_active_active_oh_17[2],1'h0,active_active_active_oh1_lo_lo_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_17 = {2'h0,active_active_active_oh_17[5],1'h0,2'h0,
- active_active_active_oh_17[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_17 = {2'h0,active_active_active_oh_17[7],1'h0,2'h0,active_active_active_oh_17[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_17,active_active_active_oh1_lo_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_17 = {2'h0,active_active_active_oh_17[9],1'h0,2'h0,
- active_active_active_oh_17[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_17 = {2'h0,active_active_active_oh_17[11],1'h0,2'h0,
- active_active_active_oh_17[10],1'h0,active_active_active_oh1_hi_lo_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_17 = {2'h0,active_active_active_oh_17[13],1'h0,2'h0,
- active_active_active_oh_17[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_17 = {2'h0,active_active_active_oh_17[15],1'h0,2'h0,active_active_active_oh_17[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_17,active_active_active_oh1_hi_lo_17,active_active_active_oh1_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_17 = {1'h0,active_active_active_oh_17[1],2'h0,1'h0,
- active_active_active_oh_17[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_17 = {1'h0,active_active_active_oh_17[3],2'h0,1'h0,
- active_active_active_oh_17[2],2'h0,active_active_active_oh2_lo_lo_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_17 = {1'h0,active_active_active_oh_17[5],2'h0,1'h0,
- active_active_active_oh_17[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_17 = {1'h0,active_active_active_oh_17[7],2'h0,1'h0,active_active_active_oh_17[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_17,active_active_active_oh2_lo_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_17 = {1'h0,active_active_active_oh_17[9],2'h0,1'h0,
- active_active_active_oh_17[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_17 = {1'h0,active_active_active_oh_17[11],2'h0,1'h0,
- active_active_active_oh_17[10],2'h0,active_active_active_oh2_hi_lo_lo_17}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_17 = {1'h0,active_active_active_oh_17[13],2'h0,1'h0,
- active_active_active_oh_17[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_17 = {1'h0,active_active_active_oh_17[15],2'h0,1'h0,active_active_active_oh_17[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_17,active_active_active_oh2_hi_lo_17,active_active_active_oh2_lo_17}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_17 = {active_active_active_oh_17[3],3'h0,active_active_active_oh_17[2],3'h0
- ,active_active_active_oh_17[1],3'h0,active_active_active_oh_17[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_17 = {active_active_active_oh_17[7],3'h0,active_active_active_oh_17[6],3'h0,
- active_active_active_oh_17[5],3'h0,active_active_active_oh_17[4],3'h0,active_active_active_oh3_lo_lo_17}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_17 = {active_active_active_oh_17[11],3'h0,active_active_active_oh_17[10],3'h0
- ,active_active_active_oh_17[9],3'h0,active_active_active_oh_17[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_17 = {active_active_active_oh_17[15],3'h0,active_active_active_oh_17[14],3'h0,
- active_active_active_oh_17[13],3'h0,active_active_active_oh_17[12],3'h0,active_active_active_oh3_hi_lo_17,
- active_active_active_oh3_lo_17}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_17 = f_io_entry_5_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_515 = ~f_io_entry_5_bits_m & active_active_active_idx_17 == 2'h0 |
- f_io_entry_5_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_516 = _active_active_active_active_T_515 ? active_active_active_oh0_17 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_522 = _active_active_active_active_T_450 & active_active_active_idx_17 == 2'h1 |
- _active_active_active_active_T_454; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_523 = _active_active_active_active_T_522 ? active_active_active_oh1_17 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_524 = _active_active_active_active_T_516 |
- _active_active_active_active_T_523; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_530 = _active_active_active_active_T_450 & active_active_active_idx_17 == 2'h2 |
- _active_active_active_active_T_454; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_531 = _active_active_active_active_T_530 ? active_active_active_oh2_17 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_532 = _active_active_active_active_T_524 |
- _active_active_active_active_T_531; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_538 = _active_active_active_active_T_450 & active_active_active_idx_17 == 2'h3 |
- _active_active_active_active_T_454; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_539 = _active_active_active_active_T_538 ? active_active_active_oh3_17 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_17 = _active_active_active_active_T_532 | _active_active_active_active_T_539; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_455 = f_io_entry_5_bits_tin_vu_valid ? active_active_active_active_17 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_17 = _active_active_active_T_450 | _active_active_active_T_455; // @[VAlu.scala 250:74]
- wire [63:0] active_active_9 = f_io_entry_5_valid ? active_active_active_17 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_32 = _active_T_31 | active_active_9; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_18 = f_io_entry_6_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_18 = 16'h1 << active_active_active_oh_shiftAmount_18; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_18 = {3'h0,active_active_active_oh_18[3],3'h0,active_active_active_oh_18[2]
- ,3'h0,active_active_active_oh_18[1],3'h0,active_active_active_oh_18[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_18 = {3'h0,active_active_active_oh_18[7],3'h0,active_active_active_oh_18[6],3'h0
- ,active_active_active_oh_18[5],3'h0,active_active_active_oh_18[4],active_active_active_oh0_lo_lo_18}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_18 = {3'h0,active_active_active_oh_18[11],3'h0,active_active_active_oh_18[
- 10],3'h0,active_active_active_oh_18[9],3'h0,active_active_active_oh_18[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_18 = {3'h0,active_active_active_oh_18[15],3'h0,active_active_active_oh_18[14],3'h0
- ,active_active_active_oh_18[13],3'h0,active_active_active_oh_18[12],active_active_active_oh0_hi_lo_18,
- active_active_active_oh0_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_18 = {2'h0,active_active_active_oh_18[1],1'h0,2'h0,
- active_active_active_oh_18[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_18 = {2'h0,active_active_active_oh_18[3],1'h0,2'h0,
- active_active_active_oh_18[2],1'h0,active_active_active_oh1_lo_lo_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_18 = {2'h0,active_active_active_oh_18[5],1'h0,2'h0,
- active_active_active_oh_18[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_18 = {2'h0,active_active_active_oh_18[7],1'h0,2'h0,active_active_active_oh_18[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_18,active_active_active_oh1_lo_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_18 = {2'h0,active_active_active_oh_18[9],1'h0,2'h0,
- active_active_active_oh_18[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_18 = {2'h0,active_active_active_oh_18[11],1'h0,2'h0,
- active_active_active_oh_18[10],1'h0,active_active_active_oh1_hi_lo_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_18 = {2'h0,active_active_active_oh_18[13],1'h0,2'h0,
- active_active_active_oh_18[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_18 = {2'h0,active_active_active_oh_18[15],1'h0,2'h0,active_active_active_oh_18[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_18,active_active_active_oh1_hi_lo_18,active_active_active_oh1_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_18 = {1'h0,active_active_active_oh_18[1],2'h0,1'h0,
- active_active_active_oh_18[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_18 = {1'h0,active_active_active_oh_18[3],2'h0,1'h0,
- active_active_active_oh_18[2],2'h0,active_active_active_oh2_lo_lo_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_18 = {1'h0,active_active_active_oh_18[5],2'h0,1'h0,
- active_active_active_oh_18[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_18 = {1'h0,active_active_active_oh_18[7],2'h0,1'h0,active_active_active_oh_18[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_18,active_active_active_oh2_lo_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_18 = {1'h0,active_active_active_oh_18[9],2'h0,1'h0,
- active_active_active_oh_18[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_18 = {1'h0,active_active_active_oh_18[11],2'h0,1'h0,
- active_active_active_oh_18[10],2'h0,active_active_active_oh2_hi_lo_lo_18}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_18 = {1'h0,active_active_active_oh_18[13],2'h0,1'h0,
- active_active_active_oh_18[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_18 = {1'h0,active_active_active_oh_18[15],2'h0,1'h0,active_active_active_oh_18[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_18,active_active_active_oh2_hi_lo_18,active_active_active_oh2_lo_18}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_18 = {active_active_active_oh_18[3],3'h0,active_active_active_oh_18[2],3'h0
- ,active_active_active_oh_18[1],3'h0,active_active_active_oh_18[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_18 = {active_active_active_oh_18[7],3'h0,active_active_active_oh_18[6],3'h0,
- active_active_active_oh_18[5],3'h0,active_active_active_oh_18[4],3'h0,active_active_active_oh3_lo_lo_18}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_18 = {active_active_active_oh_18[11],3'h0,active_active_active_oh_18[10],3'h0
- ,active_active_active_oh_18[9],3'h0,active_active_active_oh_18[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_18 = {active_active_active_oh_18[15],3'h0,active_active_active_oh_18[14],3'h0,
- active_active_active_oh_18[13],3'h0,active_active_active_oh_18[12],3'h0,active_active_active_oh3_hi_lo_18,
- active_active_active_oh3_lo_18}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_18 = f_io_entry_6_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_540 = ~f_io_entry_6_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_544 = f_io_entry_6_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_545 = ~f_io_entry_6_bits_m & active_active_active_idx_18 == 2'h0 |
- f_io_entry_6_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_546 = _active_active_active_active_T_545 ? active_active_active_oh0_18 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_552 = _active_active_active_active_T_540 & active_active_active_idx_18 == 2'h1 |
- _active_active_active_active_T_544; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_553 = _active_active_active_active_T_552 ? active_active_active_oh1_18 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_554 = _active_active_active_active_T_546 |
- _active_active_active_active_T_553; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_560 = _active_active_active_active_T_540 & active_active_active_idx_18 == 2'h2 |
- _active_active_active_active_T_544; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_561 = _active_active_active_active_T_560 ? active_active_active_oh2_18 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_562 = _active_active_active_active_T_554 |
- _active_active_active_active_T_561; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_568 = _active_active_active_active_T_540 & active_active_active_idx_18 == 2'h3 |
- _active_active_active_active_T_544; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_569 = _active_active_active_active_T_568 ? active_active_active_oh3_18 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_18 = _active_active_active_active_T_562 | _active_active_active_active_T_569; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_460 = f_io_entry_6_bits_tin_vs_valid ? active_active_active_active_18 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_19 = f_io_entry_6_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_19 = 16'h1 << active_active_active_oh_shiftAmount_19; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_19 = {3'h0,active_active_active_oh_19[3],3'h0,active_active_active_oh_19[2]
- ,3'h0,active_active_active_oh_19[1],3'h0,active_active_active_oh_19[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_19 = {3'h0,active_active_active_oh_19[7],3'h0,active_active_active_oh_19[6],3'h0
- ,active_active_active_oh_19[5],3'h0,active_active_active_oh_19[4],active_active_active_oh0_lo_lo_19}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_19 = {3'h0,active_active_active_oh_19[11],3'h0,active_active_active_oh_19[
- 10],3'h0,active_active_active_oh_19[9],3'h0,active_active_active_oh_19[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_19 = {3'h0,active_active_active_oh_19[15],3'h0,active_active_active_oh_19[14],3'h0
- ,active_active_active_oh_19[13],3'h0,active_active_active_oh_19[12],active_active_active_oh0_hi_lo_19,
- active_active_active_oh0_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_19 = {2'h0,active_active_active_oh_19[1],1'h0,2'h0,
- active_active_active_oh_19[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_19 = {2'h0,active_active_active_oh_19[3],1'h0,2'h0,
- active_active_active_oh_19[2],1'h0,active_active_active_oh1_lo_lo_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_19 = {2'h0,active_active_active_oh_19[5],1'h0,2'h0,
- active_active_active_oh_19[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_19 = {2'h0,active_active_active_oh_19[7],1'h0,2'h0,active_active_active_oh_19[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_19,active_active_active_oh1_lo_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_19 = {2'h0,active_active_active_oh_19[9],1'h0,2'h0,
- active_active_active_oh_19[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_19 = {2'h0,active_active_active_oh_19[11],1'h0,2'h0,
- active_active_active_oh_19[10],1'h0,active_active_active_oh1_hi_lo_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_19 = {2'h0,active_active_active_oh_19[13],1'h0,2'h0,
- active_active_active_oh_19[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_19 = {2'h0,active_active_active_oh_19[15],1'h0,2'h0,active_active_active_oh_19[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_19,active_active_active_oh1_hi_lo_19,active_active_active_oh1_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_19 = {1'h0,active_active_active_oh_19[1],2'h0,1'h0,
- active_active_active_oh_19[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_19 = {1'h0,active_active_active_oh_19[3],2'h0,1'h0,
- active_active_active_oh_19[2],2'h0,active_active_active_oh2_lo_lo_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_19 = {1'h0,active_active_active_oh_19[5],2'h0,1'h0,
- active_active_active_oh_19[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_19 = {1'h0,active_active_active_oh_19[7],2'h0,1'h0,active_active_active_oh_19[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_19,active_active_active_oh2_lo_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_19 = {1'h0,active_active_active_oh_19[9],2'h0,1'h0,
- active_active_active_oh_19[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_19 = {1'h0,active_active_active_oh_19[11],2'h0,1'h0,
- active_active_active_oh_19[10],2'h0,active_active_active_oh2_hi_lo_lo_19}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_19 = {1'h0,active_active_active_oh_19[13],2'h0,1'h0,
- active_active_active_oh_19[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_19 = {1'h0,active_active_active_oh_19[15],2'h0,1'h0,active_active_active_oh_19[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_19,active_active_active_oh2_hi_lo_19,active_active_active_oh2_lo_19}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_19 = {active_active_active_oh_19[3],3'h0,active_active_active_oh_19[2],3'h0
- ,active_active_active_oh_19[1],3'h0,active_active_active_oh_19[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_19 = {active_active_active_oh_19[7],3'h0,active_active_active_oh_19[6],3'h0,
- active_active_active_oh_19[5],3'h0,active_active_active_oh_19[4],3'h0,active_active_active_oh3_lo_lo_19}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_19 = {active_active_active_oh_19[11],3'h0,active_active_active_oh_19[10],3'h0
- ,active_active_active_oh_19[9],3'h0,active_active_active_oh_19[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_19 = {active_active_active_oh_19[15],3'h0,active_active_active_oh_19[14],3'h0,
- active_active_active_oh_19[13],3'h0,active_active_active_oh_19[12],3'h0,active_active_active_oh3_hi_lo_19,
- active_active_active_oh3_lo_19}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_19 = f_io_entry_6_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_575 = ~f_io_entry_6_bits_m & active_active_active_idx_19 == 2'h0 |
- f_io_entry_6_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_576 = _active_active_active_active_T_575 ? active_active_active_oh0_19 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_582 = _active_active_active_active_T_540 & active_active_active_idx_19 == 2'h1 |
- _active_active_active_active_T_544; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_583 = _active_active_active_active_T_582 ? active_active_active_oh1_19 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_584 = _active_active_active_active_T_576 |
- _active_active_active_active_T_583; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_590 = _active_active_active_active_T_540 & active_active_active_idx_19 == 2'h2 |
- _active_active_active_active_T_544; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_591 = _active_active_active_active_T_590 ? active_active_active_oh2_19 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_592 = _active_active_active_active_T_584 |
- _active_active_active_active_T_591; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_598 = _active_active_active_active_T_540 & active_active_active_idx_19 == 2'h3 |
- _active_active_active_active_T_544; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_599 = _active_active_active_active_T_598 ? active_active_active_oh3_19 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_19 = _active_active_active_active_T_592 | _active_active_active_active_T_599; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_465 = f_io_entry_6_bits_tin_vt_valid ? active_active_active_active_19 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_466 = _active_active_active_T_460 | _active_active_active_T_465; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_20 = f_io_entry_6_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_20 = 16'h1 << active_active_active_oh_shiftAmount_20; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_20 = {3'h0,active_active_active_oh_20[3],3'h0,active_active_active_oh_20[2]
- ,3'h0,active_active_active_oh_20[1],3'h0,active_active_active_oh_20[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_20 = {3'h0,active_active_active_oh_20[7],3'h0,active_active_active_oh_20[6],3'h0
- ,active_active_active_oh_20[5],3'h0,active_active_active_oh_20[4],active_active_active_oh0_lo_lo_20}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_20 = {3'h0,active_active_active_oh_20[11],3'h0,active_active_active_oh_20[
- 10],3'h0,active_active_active_oh_20[9],3'h0,active_active_active_oh_20[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_20 = {3'h0,active_active_active_oh_20[15],3'h0,active_active_active_oh_20[14],3'h0
- ,active_active_active_oh_20[13],3'h0,active_active_active_oh_20[12],active_active_active_oh0_hi_lo_20,
- active_active_active_oh0_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_20 = {2'h0,active_active_active_oh_20[1],1'h0,2'h0,
- active_active_active_oh_20[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_20 = {2'h0,active_active_active_oh_20[3],1'h0,2'h0,
- active_active_active_oh_20[2],1'h0,active_active_active_oh1_lo_lo_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_20 = {2'h0,active_active_active_oh_20[5],1'h0,2'h0,
- active_active_active_oh_20[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_20 = {2'h0,active_active_active_oh_20[7],1'h0,2'h0,active_active_active_oh_20[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_20,active_active_active_oh1_lo_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_20 = {2'h0,active_active_active_oh_20[9],1'h0,2'h0,
- active_active_active_oh_20[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_20 = {2'h0,active_active_active_oh_20[11],1'h0,2'h0,
- active_active_active_oh_20[10],1'h0,active_active_active_oh1_hi_lo_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_20 = {2'h0,active_active_active_oh_20[13],1'h0,2'h0,
- active_active_active_oh_20[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_20 = {2'h0,active_active_active_oh_20[15],1'h0,2'h0,active_active_active_oh_20[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_20,active_active_active_oh1_hi_lo_20,active_active_active_oh1_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_20 = {1'h0,active_active_active_oh_20[1],2'h0,1'h0,
- active_active_active_oh_20[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_20 = {1'h0,active_active_active_oh_20[3],2'h0,1'h0,
- active_active_active_oh_20[2],2'h0,active_active_active_oh2_lo_lo_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_20 = {1'h0,active_active_active_oh_20[5],2'h0,1'h0,
- active_active_active_oh_20[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_20 = {1'h0,active_active_active_oh_20[7],2'h0,1'h0,active_active_active_oh_20[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_20,active_active_active_oh2_lo_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_20 = {1'h0,active_active_active_oh_20[9],2'h0,1'h0,
- active_active_active_oh_20[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_20 = {1'h0,active_active_active_oh_20[11],2'h0,1'h0,
- active_active_active_oh_20[10],2'h0,active_active_active_oh2_hi_lo_lo_20}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_20 = {1'h0,active_active_active_oh_20[13],2'h0,1'h0,
- active_active_active_oh_20[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_20 = {1'h0,active_active_active_oh_20[15],2'h0,1'h0,active_active_active_oh_20[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_20,active_active_active_oh2_hi_lo_20,active_active_active_oh2_lo_20}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_20 = {active_active_active_oh_20[3],3'h0,active_active_active_oh_20[2],3'h0
- ,active_active_active_oh_20[1],3'h0,active_active_active_oh_20[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_20 = {active_active_active_oh_20[7],3'h0,active_active_active_oh_20[6],3'h0,
- active_active_active_oh_20[5],3'h0,active_active_active_oh_20[4],3'h0,active_active_active_oh3_lo_lo_20}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_20 = {active_active_active_oh_20[11],3'h0,active_active_active_oh_20[10],3'h0
- ,active_active_active_oh_20[9],3'h0,active_active_active_oh_20[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_20 = {active_active_active_oh_20[15],3'h0,active_active_active_oh_20[14],3'h0,
- active_active_active_oh_20[13],3'h0,active_active_active_oh_20[12],3'h0,active_active_active_oh3_hi_lo_20,
- active_active_active_oh3_lo_20}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_20 = f_io_entry_6_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_605 = ~f_io_entry_6_bits_m & active_active_active_idx_20 == 2'h0 |
- f_io_entry_6_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_606 = _active_active_active_active_T_605 ? active_active_active_oh0_20 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_612 = _active_active_active_active_T_540 & active_active_active_idx_20 == 2'h1 |
- _active_active_active_active_T_544; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_613 = _active_active_active_active_T_612 ? active_active_active_oh1_20 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_614 = _active_active_active_active_T_606 |
- _active_active_active_active_T_613; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_620 = _active_active_active_active_T_540 & active_active_active_idx_20 == 2'h2 |
- _active_active_active_active_T_544; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_621 = _active_active_active_active_T_620 ? active_active_active_oh2_20 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_622 = _active_active_active_active_T_614 |
- _active_active_active_active_T_621; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_628 = _active_active_active_active_T_540 & active_active_active_idx_20 == 2'h3 |
- _active_active_active_active_T_544; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_629 = _active_active_active_active_T_628 ? active_active_active_oh3_20 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_20 = _active_active_active_active_T_622 | _active_active_active_active_T_629; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_471 = f_io_entry_6_bits_tin_vu_valid ? active_active_active_active_20 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_18 = _active_active_active_T_466 | _active_active_active_T_471; // @[VAlu.scala 250:74]
- wire [63:0] active_active_10 = f_io_entry_6_valid ? active_active_active_18 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_33 = _active_T_32 | active_active_10; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_21 = f_io_entry_7_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_21 = 16'h1 << active_active_active_oh_shiftAmount_21; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_21 = {3'h0,active_active_active_oh_21[3],3'h0,active_active_active_oh_21[2]
- ,3'h0,active_active_active_oh_21[1],3'h0,active_active_active_oh_21[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_21 = {3'h0,active_active_active_oh_21[7],3'h0,active_active_active_oh_21[6],3'h0
- ,active_active_active_oh_21[5],3'h0,active_active_active_oh_21[4],active_active_active_oh0_lo_lo_21}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_21 = {3'h0,active_active_active_oh_21[11],3'h0,active_active_active_oh_21[
- 10],3'h0,active_active_active_oh_21[9],3'h0,active_active_active_oh_21[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_21 = {3'h0,active_active_active_oh_21[15],3'h0,active_active_active_oh_21[14],3'h0
- ,active_active_active_oh_21[13],3'h0,active_active_active_oh_21[12],active_active_active_oh0_hi_lo_21,
- active_active_active_oh0_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_21 = {2'h0,active_active_active_oh_21[1],1'h0,2'h0,
- active_active_active_oh_21[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_21 = {2'h0,active_active_active_oh_21[3],1'h0,2'h0,
- active_active_active_oh_21[2],1'h0,active_active_active_oh1_lo_lo_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_21 = {2'h0,active_active_active_oh_21[5],1'h0,2'h0,
- active_active_active_oh_21[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_21 = {2'h0,active_active_active_oh_21[7],1'h0,2'h0,active_active_active_oh_21[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_21,active_active_active_oh1_lo_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_21 = {2'h0,active_active_active_oh_21[9],1'h0,2'h0,
- active_active_active_oh_21[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_21 = {2'h0,active_active_active_oh_21[11],1'h0,2'h0,
- active_active_active_oh_21[10],1'h0,active_active_active_oh1_hi_lo_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_21 = {2'h0,active_active_active_oh_21[13],1'h0,2'h0,
- active_active_active_oh_21[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_21 = {2'h0,active_active_active_oh_21[15],1'h0,2'h0,active_active_active_oh_21[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_21,active_active_active_oh1_hi_lo_21,active_active_active_oh1_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_21 = {1'h0,active_active_active_oh_21[1],2'h0,1'h0,
- active_active_active_oh_21[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_21 = {1'h0,active_active_active_oh_21[3],2'h0,1'h0,
- active_active_active_oh_21[2],2'h0,active_active_active_oh2_lo_lo_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_21 = {1'h0,active_active_active_oh_21[5],2'h0,1'h0,
- active_active_active_oh_21[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_21 = {1'h0,active_active_active_oh_21[7],2'h0,1'h0,active_active_active_oh_21[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_21,active_active_active_oh2_lo_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_21 = {1'h0,active_active_active_oh_21[9],2'h0,1'h0,
- active_active_active_oh_21[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_21 = {1'h0,active_active_active_oh_21[11],2'h0,1'h0,
- active_active_active_oh_21[10],2'h0,active_active_active_oh2_hi_lo_lo_21}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_21 = {1'h0,active_active_active_oh_21[13],2'h0,1'h0,
- active_active_active_oh_21[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_21 = {1'h0,active_active_active_oh_21[15],2'h0,1'h0,active_active_active_oh_21[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_21,active_active_active_oh2_hi_lo_21,active_active_active_oh2_lo_21}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_21 = {active_active_active_oh_21[3],3'h0,active_active_active_oh_21[2],3'h0
- ,active_active_active_oh_21[1],3'h0,active_active_active_oh_21[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_21 = {active_active_active_oh_21[7],3'h0,active_active_active_oh_21[6],3'h0,
- active_active_active_oh_21[5],3'h0,active_active_active_oh_21[4],3'h0,active_active_active_oh3_lo_lo_21}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_21 = {active_active_active_oh_21[11],3'h0,active_active_active_oh_21[10],3'h0
- ,active_active_active_oh_21[9],3'h0,active_active_active_oh_21[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_21 = {active_active_active_oh_21[15],3'h0,active_active_active_oh_21[14],3'h0,
- active_active_active_oh_21[13],3'h0,active_active_active_oh_21[12],3'h0,active_active_active_oh3_hi_lo_21,
- active_active_active_oh3_lo_21}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_21 = f_io_entry_7_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_630 = ~f_io_entry_7_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_634 = f_io_entry_7_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_635 = ~f_io_entry_7_bits_m & active_active_active_idx_21 == 2'h0 |
- f_io_entry_7_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_636 = _active_active_active_active_T_635 ? active_active_active_oh0_21 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_642 = _active_active_active_active_T_630 & active_active_active_idx_21 == 2'h1 |
- _active_active_active_active_T_634; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_643 = _active_active_active_active_T_642 ? active_active_active_oh1_21 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_644 = _active_active_active_active_T_636 |
- _active_active_active_active_T_643; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_650 = _active_active_active_active_T_630 & active_active_active_idx_21 == 2'h2 |
- _active_active_active_active_T_634; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_651 = _active_active_active_active_T_650 ? active_active_active_oh2_21 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_652 = _active_active_active_active_T_644 |
- _active_active_active_active_T_651; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_658 = _active_active_active_active_T_630 & active_active_active_idx_21 == 2'h3 |
- _active_active_active_active_T_634; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_659 = _active_active_active_active_T_658 ? active_active_active_oh3_21 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_21 = _active_active_active_active_T_652 | _active_active_active_active_T_659; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_476 = f_io_entry_7_bits_tin_vs_valid ? active_active_active_active_21 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_22 = f_io_entry_7_bits_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_22 = 16'h1 << active_active_active_oh_shiftAmount_22; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_22 = {3'h0,active_active_active_oh_22[3],3'h0,active_active_active_oh_22[2]
- ,3'h0,active_active_active_oh_22[1],3'h0,active_active_active_oh_22[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_22 = {3'h0,active_active_active_oh_22[7],3'h0,active_active_active_oh_22[6],3'h0
- ,active_active_active_oh_22[5],3'h0,active_active_active_oh_22[4],active_active_active_oh0_lo_lo_22}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_22 = {3'h0,active_active_active_oh_22[11],3'h0,active_active_active_oh_22[
- 10],3'h0,active_active_active_oh_22[9],3'h0,active_active_active_oh_22[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_22 = {3'h0,active_active_active_oh_22[15],3'h0,active_active_active_oh_22[14],3'h0
- ,active_active_active_oh_22[13],3'h0,active_active_active_oh_22[12],active_active_active_oh0_hi_lo_22,
- active_active_active_oh0_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_22 = {2'h0,active_active_active_oh_22[1],1'h0,2'h0,
- active_active_active_oh_22[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_22 = {2'h0,active_active_active_oh_22[3],1'h0,2'h0,
- active_active_active_oh_22[2],1'h0,active_active_active_oh1_lo_lo_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_22 = {2'h0,active_active_active_oh_22[5],1'h0,2'h0,
- active_active_active_oh_22[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_22 = {2'h0,active_active_active_oh_22[7],1'h0,2'h0,active_active_active_oh_22[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_22,active_active_active_oh1_lo_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_22 = {2'h0,active_active_active_oh_22[9],1'h0,2'h0,
- active_active_active_oh_22[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_22 = {2'h0,active_active_active_oh_22[11],1'h0,2'h0,
- active_active_active_oh_22[10],1'h0,active_active_active_oh1_hi_lo_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_22 = {2'h0,active_active_active_oh_22[13],1'h0,2'h0,
- active_active_active_oh_22[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_22 = {2'h0,active_active_active_oh_22[15],1'h0,2'h0,active_active_active_oh_22[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_22,active_active_active_oh1_hi_lo_22,active_active_active_oh1_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_22 = {1'h0,active_active_active_oh_22[1],2'h0,1'h0,
- active_active_active_oh_22[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_22 = {1'h0,active_active_active_oh_22[3],2'h0,1'h0,
- active_active_active_oh_22[2],2'h0,active_active_active_oh2_lo_lo_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_22 = {1'h0,active_active_active_oh_22[5],2'h0,1'h0,
- active_active_active_oh_22[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_22 = {1'h0,active_active_active_oh_22[7],2'h0,1'h0,active_active_active_oh_22[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_22,active_active_active_oh2_lo_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_22 = {1'h0,active_active_active_oh_22[9],2'h0,1'h0,
- active_active_active_oh_22[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_22 = {1'h0,active_active_active_oh_22[11],2'h0,1'h0,
- active_active_active_oh_22[10],2'h0,active_active_active_oh2_hi_lo_lo_22}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_22 = {1'h0,active_active_active_oh_22[13],2'h0,1'h0,
- active_active_active_oh_22[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_22 = {1'h0,active_active_active_oh_22[15],2'h0,1'h0,active_active_active_oh_22[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_22,active_active_active_oh2_hi_lo_22,active_active_active_oh2_lo_22}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_22 = {active_active_active_oh_22[3],3'h0,active_active_active_oh_22[2],3'h0
- ,active_active_active_oh_22[1],3'h0,active_active_active_oh_22[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_22 = {active_active_active_oh_22[7],3'h0,active_active_active_oh_22[6],3'h0,
- active_active_active_oh_22[5],3'h0,active_active_active_oh_22[4],3'h0,active_active_active_oh3_lo_lo_22}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_22 = {active_active_active_oh_22[11],3'h0,active_active_active_oh_22[10],3'h0
- ,active_active_active_oh_22[9],3'h0,active_active_active_oh_22[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_22 = {active_active_active_oh_22[15],3'h0,active_active_active_oh_22[14],3'h0,
- active_active_active_oh_22[13],3'h0,active_active_active_oh_22[12],3'h0,active_active_active_oh3_hi_lo_22,
- active_active_active_oh3_lo_22}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_22 = f_io_entry_7_bits_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_665 = ~f_io_entry_7_bits_m & active_active_active_idx_22 == 2'h0 |
- f_io_entry_7_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_666 = _active_active_active_active_T_665 ? active_active_active_oh0_22 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_672 = _active_active_active_active_T_630 & active_active_active_idx_22 == 2'h1 |
- _active_active_active_active_T_634; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_673 = _active_active_active_active_T_672 ? active_active_active_oh1_22 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_674 = _active_active_active_active_T_666 |
- _active_active_active_active_T_673; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_680 = _active_active_active_active_T_630 & active_active_active_idx_22 == 2'h2 |
- _active_active_active_active_T_634; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_681 = _active_active_active_active_T_680 ? active_active_active_oh2_22 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_682 = _active_active_active_active_T_674 |
- _active_active_active_active_T_681; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_688 = _active_active_active_active_T_630 & active_active_active_idx_22 == 2'h3 |
- _active_active_active_active_T_634; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_689 = _active_active_active_active_T_688 ? active_active_active_oh3_22 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_22 = _active_active_active_active_T_682 | _active_active_active_active_T_689; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_481 = f_io_entry_7_bits_tin_vt_valid ? active_active_active_active_22 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active_active_T_482 = _active_active_active_T_476 | _active_active_active_T_481; // @[VAlu.scala 249:74]
- wire [3:0] active_active_active_oh_shiftAmount_23 = f_io_entry_7_bits_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_23 = 16'h1 << active_active_active_oh_shiftAmount_23; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_23 = {3'h0,active_active_active_oh_23[3],3'h0,active_active_active_oh_23[2]
- ,3'h0,active_active_active_oh_23[1],3'h0,active_active_active_oh_23[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_23 = {3'h0,active_active_active_oh_23[7],3'h0,active_active_active_oh_23[6],3'h0
- ,active_active_active_oh_23[5],3'h0,active_active_active_oh_23[4],active_active_active_oh0_lo_lo_23}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_23 = {3'h0,active_active_active_oh_23[11],3'h0,active_active_active_oh_23[
- 10],3'h0,active_active_active_oh_23[9],3'h0,active_active_active_oh_23[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_23 = {3'h0,active_active_active_oh_23[15],3'h0,active_active_active_oh_23[14],3'h0
- ,active_active_active_oh_23[13],3'h0,active_active_active_oh_23[12],active_active_active_oh0_hi_lo_23,
- active_active_active_oh0_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_23 = {2'h0,active_active_active_oh_23[1],1'h0,2'h0,
- active_active_active_oh_23[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_23 = {2'h0,active_active_active_oh_23[3],1'h0,2'h0,
- active_active_active_oh_23[2],1'h0,active_active_active_oh1_lo_lo_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_23 = {2'h0,active_active_active_oh_23[5],1'h0,2'h0,
- active_active_active_oh_23[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_23 = {2'h0,active_active_active_oh_23[7],1'h0,2'h0,active_active_active_oh_23[
- 6],1'h0,active_active_active_oh1_lo_hi_lo_23,active_active_active_oh1_lo_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_23 = {2'h0,active_active_active_oh_23[9],1'h0,2'h0,
- active_active_active_oh_23[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_23 = {2'h0,active_active_active_oh_23[11],1'h0,2'h0,
- active_active_active_oh_23[10],1'h0,active_active_active_oh1_hi_lo_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_23 = {2'h0,active_active_active_oh_23[13],1'h0,2'h0,
- active_active_active_oh_23[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_23 = {2'h0,active_active_active_oh_23[15],1'h0,2'h0,active_active_active_oh_23[14
- ],1'h0,active_active_active_oh1_hi_hi_lo_23,active_active_active_oh1_hi_lo_23,active_active_active_oh1_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_23 = {1'h0,active_active_active_oh_23[1],2'h0,1'h0,
- active_active_active_oh_23[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_23 = {1'h0,active_active_active_oh_23[3],2'h0,1'h0,
- active_active_active_oh_23[2],2'h0,active_active_active_oh2_lo_lo_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_23 = {1'h0,active_active_active_oh_23[5],2'h0,1'h0,
- active_active_active_oh_23[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_23 = {1'h0,active_active_active_oh_23[7],2'h0,1'h0,active_active_active_oh_23[
- 6],2'h0,active_active_active_oh2_lo_hi_lo_23,active_active_active_oh2_lo_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_23 = {1'h0,active_active_active_oh_23[9],2'h0,1'h0,
- active_active_active_oh_23[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_23 = {1'h0,active_active_active_oh_23[11],2'h0,1'h0,
- active_active_active_oh_23[10],2'h0,active_active_active_oh2_hi_lo_lo_23}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_23 = {1'h0,active_active_active_oh_23[13],2'h0,1'h0,
- active_active_active_oh_23[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_23 = {1'h0,active_active_active_oh_23[15],2'h0,1'h0,active_active_active_oh_23[14
- ],2'h0,active_active_active_oh2_hi_hi_lo_23,active_active_active_oh2_hi_lo_23,active_active_active_oh2_lo_23}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_23 = {active_active_active_oh_23[3],3'h0,active_active_active_oh_23[2],3'h0
- ,active_active_active_oh_23[1],3'h0,active_active_active_oh_23[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_23 = {active_active_active_oh_23[7],3'h0,active_active_active_oh_23[6],3'h0,
- active_active_active_oh_23[5],3'h0,active_active_active_oh_23[4],3'h0,active_active_active_oh3_lo_lo_23}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_23 = {active_active_active_oh_23[11],3'h0,active_active_active_oh_23[10],3'h0
- ,active_active_active_oh_23[9],3'h0,active_active_active_oh_23[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_23 = {active_active_active_oh_23[15],3'h0,active_active_active_oh_23[14],3'h0,
- active_active_active_oh_23[13],3'h0,active_active_active_oh_23[12],3'h0,active_active_active_oh3_hi_lo_23,
- active_active_active_oh3_lo_23}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_23 = f_io_entry_7_bits_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_695 = ~f_io_entry_7_bits_m & active_active_active_idx_23 == 2'h0 |
- f_io_entry_7_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_696 = _active_active_active_active_T_695 ? active_active_active_oh0_23 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_702 = _active_active_active_active_T_630 & active_active_active_idx_23 == 2'h1 |
- _active_active_active_active_T_634; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_703 = _active_active_active_active_T_702 ? active_active_active_oh1_23 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_704 = _active_active_active_active_T_696 |
- _active_active_active_active_T_703; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_710 = _active_active_active_active_T_630 & active_active_active_idx_23 == 2'h2 |
- _active_active_active_active_T_634; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_711 = _active_active_active_active_T_710 ? active_active_active_oh2_23 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_712 = _active_active_active_active_T_704 |
- _active_active_active_active_T_711; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_718 = _active_active_active_active_T_630 & active_active_active_idx_23 == 2'h3 |
- _active_active_active_active_T_634; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_719 = _active_active_active_active_T_718 ? active_active_active_oh3_23 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_23 = _active_active_active_active_T_712 | _active_active_active_active_T_719; // @[VCommon.scala 109:68]
- wire [63:0] _active_active_active_T_487 = f_io_entry_7_bits_tin_vu_valid ? active_active_active_active_23 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_19 = _active_active_active_T_482 | _active_active_active_T_487; // @[VAlu.scala 250:74]
- wire [63:0] active_active_11 = f_io_entry_7_valid ? active_active_active_19 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_34 = _active_T_33 | active_active_11; // @[VCmdq.scala 107:24]
- wire [5:0] _active_active0_T = {{1'd0}, step}; // @[VCmdq.scala 110:48]
- wire [3:0] active_active0_active_oh_shiftAmount = value_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active0_active_oh = 16'h1 << active_active0_active_oh_shiftAmount; // @[OneHot.scala 64:12]
- wire [15:0] active_active0_active_oh0_lo_lo = {3'h0,active_active0_active_oh[3],3'h0,active_active0_active_oh[2],3'h0,
- active_active0_active_oh[1],3'h0,active_active0_active_oh[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh0_lo = {3'h0,active_active0_active_oh[7],3'h0,active_active0_active_oh[6],3'h0,
- active_active0_active_oh[5],3'h0,active_active0_active_oh[4],active_active0_active_oh0_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh0_hi_lo = {3'h0,active_active0_active_oh[11],3'h0,active_active0_active_oh[10],3'h0
- ,active_active0_active_oh[9],3'h0,active_active0_active_oh[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh0 = {3'h0,active_active0_active_oh[15],3'h0,active_active0_active_oh[14],3'h0,
- active_active0_active_oh[13],3'h0,active_active0_active_oh[12],active_active0_active_oh0_hi_lo,
- active_active0_active_oh0_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_lo_lo = {2'h0,active_active0_active_oh[1],1'h0,2'h0,active_active0_active_oh[0
- ],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_lo_lo = {2'h0,active_active0_active_oh[3],1'h0,2'h0,active_active0_active_oh[2],1'h0
- ,active_active0_active_oh1_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_hi_lo = {2'h0,active_active0_active_oh[5],1'h0,2'h0,active_active0_active_oh[4
- ],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh1_lo = {2'h0,active_active0_active_oh[7],1'h0,2'h0,active_active0_active_oh[6],1'h0
- ,active_active0_active_oh1_lo_hi_lo,active_active0_active_oh1_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_lo_lo = {2'h0,active_active0_active_oh[9],1'h0,2'h0,active_active0_active_oh[8
- ],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_hi_lo = {2'h0,active_active0_active_oh[11],1'h0,2'h0,active_active0_active_oh[10
- ],1'h0,active_active0_active_oh1_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_hi_lo = {2'h0,active_active0_active_oh[13],1'h0,2'h0,active_active0_active_oh[
- 12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh1 = {2'h0,active_active0_active_oh[15],1'h0,2'h0,active_active0_active_oh[14],1'h0
- ,active_active0_active_oh1_hi_hi_lo,active_active0_active_oh1_hi_lo,active_active0_active_oh1_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_lo_lo = {1'h0,active_active0_active_oh[1],2'h0,1'h0,active_active0_active_oh[0
- ],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_lo_lo = {1'h0,active_active0_active_oh[3],2'h0,1'h0,active_active0_active_oh[2],2'h0
- ,active_active0_active_oh2_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_hi_lo = {1'h0,active_active0_active_oh[5],2'h0,1'h0,active_active0_active_oh[4
- ],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh2_lo = {1'h0,active_active0_active_oh[7],2'h0,1'h0,active_active0_active_oh[6],2'h0
- ,active_active0_active_oh2_lo_hi_lo,active_active0_active_oh2_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_lo_lo = {1'h0,active_active0_active_oh[9],2'h0,1'h0,active_active0_active_oh[8
- ],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_hi_lo = {1'h0,active_active0_active_oh[11],2'h0,1'h0,active_active0_active_oh[10
- ],2'h0,active_active0_active_oh2_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_hi_lo = {1'h0,active_active0_active_oh[13],2'h0,1'h0,active_active0_active_oh[
- 12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh2 = {1'h0,active_active0_active_oh[15],2'h0,1'h0,active_active0_active_oh[14],2'h0
- ,active_active0_active_oh2_hi_hi_lo,active_active0_active_oh2_hi_lo,active_active0_active_oh2_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_lo_lo = {active_active0_active_oh[3],3'h0,active_active0_active_oh[2],3'h0,
- active_active0_active_oh[1],3'h0,active_active0_active_oh[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh3_lo = {active_active0_active_oh[7],3'h0,active_active0_active_oh[6],3'h0,
- active_active0_active_oh[5],3'h0,active_active0_active_oh[4],3'h0,active_active0_active_oh3_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_hi_lo = {active_active0_active_oh[11],3'h0,active_active0_active_oh[10],3'h0,
- active_active0_active_oh[9],3'h0,active_active0_active_oh[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh3 = {active_active0_active_oh[15],3'h0,active_active0_active_oh[14],3'h0,
- active_active0_active_oh[13],3'h0,active_active0_active_oh[12],3'h0,active_active0_active_oh3_hi_lo,
- active_active0_active_oh3_lo}; // @[Cat.scala 31:58]
- wire [1:0] active_active0_active_idx = value_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active0_active_active_T_5 = _last_T & active_active0_active_idx == 2'h0 | value_m & _active_active0_T[2:
- 0] <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active0_active_active_T_6 = _active_active0_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active0_active_active_T_12 = _last_T & active_active0_active_idx == 2'h1 | value_m & _active_active0_T[2
- :0] <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active0_active_active_T_13 = _active_active0_active_active_T_12 ? active_active0_active_oh1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_14 = _active_active0_active_active_T_6 |
- _active_active0_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active0_active_active_T_20 = _last_T & active_active0_active_idx == 2'h2 | value_m & _active_active0_T[2
- :0] <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active0_active_active_T_21 = _active_active0_active_active_T_20 ? active_active0_active_oh2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_22 = _active_active0_active_active_T_14 |
- _active_active0_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active0_active_active_T_28 = _last_T & active_active0_active_idx == 2'h3 | value_m & _active_active0_T[2
- :0] <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active0_active_active_T_29 = _active_active0_active_active_T_28 ? active_active0_active_oh3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active0_active_active = _active_active0_active_active_T_22 | _active_active0_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] _active_active0_active_T_5 = value_tin_vs_valid ? active_active0_active_active : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active0_active_oh_shiftAmount_1 = value_tin_vt_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active0_active_oh_1 = 16'h1 << active_active0_active_oh_shiftAmount_1; // @[OneHot.scala 64:12]
- wire [15:0] active_active0_active_oh0_lo_lo_1 = {3'h0,active_active0_active_oh_1[3],3'h0,active_active0_active_oh_1[2]
- ,3'h0,active_active0_active_oh_1[1],3'h0,active_active0_active_oh_1[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh0_lo_1 = {3'h0,active_active0_active_oh_1[7],3'h0,active_active0_active_oh_1[6],3'h0
- ,active_active0_active_oh_1[5],3'h0,active_active0_active_oh_1[4],active_active0_active_oh0_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh0_hi_lo_1 = {3'h0,active_active0_active_oh_1[11],3'h0,active_active0_active_oh_1[
- 10],3'h0,active_active0_active_oh_1[9],3'h0,active_active0_active_oh_1[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh0_1 = {3'h0,active_active0_active_oh_1[15],3'h0,active_active0_active_oh_1[14],3'h0
- ,active_active0_active_oh_1[13],3'h0,active_active0_active_oh_1[12],active_active0_active_oh0_hi_lo_1,
- active_active0_active_oh0_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_lo_lo_1 = {2'h0,active_active0_active_oh_1[1],1'h0,2'h0,
- active_active0_active_oh_1[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_lo_lo_1 = {2'h0,active_active0_active_oh_1[3],1'h0,2'h0,
- active_active0_active_oh_1[2],1'h0,active_active0_active_oh1_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_hi_lo_1 = {2'h0,active_active0_active_oh_1[5],1'h0,2'h0,
- active_active0_active_oh_1[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh1_lo_1 = {2'h0,active_active0_active_oh_1[7],1'h0,2'h0,active_active0_active_oh_1[
- 6],1'h0,active_active0_active_oh1_lo_hi_lo_1,active_active0_active_oh1_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_lo_lo_1 = {2'h0,active_active0_active_oh_1[9],1'h0,2'h0,
- active_active0_active_oh_1[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_hi_lo_1 = {2'h0,active_active0_active_oh_1[11],1'h0,2'h0,
- active_active0_active_oh_1[10],1'h0,active_active0_active_oh1_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_hi_lo_1 = {2'h0,active_active0_active_oh_1[13],1'h0,2'h0,
- active_active0_active_oh_1[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh1_1 = {2'h0,active_active0_active_oh_1[15],1'h0,2'h0,active_active0_active_oh_1[14
- ],1'h0,active_active0_active_oh1_hi_hi_lo_1,active_active0_active_oh1_hi_lo_1,active_active0_active_oh1_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_lo_lo_1 = {1'h0,active_active0_active_oh_1[1],2'h0,1'h0,
- active_active0_active_oh_1[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_lo_lo_1 = {1'h0,active_active0_active_oh_1[3],2'h0,1'h0,
- active_active0_active_oh_1[2],2'h0,active_active0_active_oh2_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_hi_lo_1 = {1'h0,active_active0_active_oh_1[5],2'h0,1'h0,
- active_active0_active_oh_1[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh2_lo_1 = {1'h0,active_active0_active_oh_1[7],2'h0,1'h0,active_active0_active_oh_1[
- 6],2'h0,active_active0_active_oh2_lo_hi_lo_1,active_active0_active_oh2_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_lo_lo_1 = {1'h0,active_active0_active_oh_1[9],2'h0,1'h0,
- active_active0_active_oh_1[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_hi_lo_1 = {1'h0,active_active0_active_oh_1[11],2'h0,1'h0,
- active_active0_active_oh_1[10],2'h0,active_active0_active_oh2_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_hi_lo_1 = {1'h0,active_active0_active_oh_1[13],2'h0,1'h0,
- active_active0_active_oh_1[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh2_1 = {1'h0,active_active0_active_oh_1[15],2'h0,1'h0,active_active0_active_oh_1[14
- ],2'h0,active_active0_active_oh2_hi_hi_lo_1,active_active0_active_oh2_hi_lo_1,active_active0_active_oh2_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_lo_lo_1 = {active_active0_active_oh_1[3],3'h0,active_active0_active_oh_1[2],3'h0
- ,active_active0_active_oh_1[1],3'h0,active_active0_active_oh_1[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh3_lo_1 = {active_active0_active_oh_1[7],3'h0,active_active0_active_oh_1[6],3'h0,
- active_active0_active_oh_1[5],3'h0,active_active0_active_oh_1[4],3'h0,active_active0_active_oh3_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_hi_lo_1 = {active_active0_active_oh_1[11],3'h0,active_active0_active_oh_1[10],3'h0
- ,active_active0_active_oh_1[9],3'h0,active_active0_active_oh_1[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh3_1 = {active_active0_active_oh_1[15],3'h0,active_active0_active_oh_1[14],3'h0,
- active_active0_active_oh_1[13],3'h0,active_active0_active_oh_1[12],3'h0,active_active0_active_oh3_hi_lo_1,
- active_active0_active_oh3_lo_1}; // @[Cat.scala 31:58]
- wire [1:0] active_active0_active_idx_1 = value_tin_vt_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active0_active_active_T_35 = _last_T & active_active0_active_idx_1 == 2'h0 | value_m & _active_active0_T
- [2:0] <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active0_active_active_T_36 = _active_active0_active_active_T_35 ? active_active0_active_oh0_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active0_active_active_T_42 = _last_T & active_active0_active_idx_1 == 2'h1 | value_m & _active_active0_T
- [2:0] <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active0_active_active_T_43 = _active_active0_active_active_T_42 ? active_active0_active_oh1_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_44 = _active_active0_active_active_T_36 |
- _active_active0_active_active_T_43; // @[VCommon.scala 107:68]
- wire _active_active0_active_active_T_50 = _last_T & active_active0_active_idx_1 == 2'h2 | value_m & _active_active0_T
- [2:0] <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active0_active_active_T_51 = _active_active0_active_active_T_50 ? active_active0_active_oh2_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_52 = _active_active0_active_active_T_44 |
- _active_active0_active_active_T_51; // @[VCommon.scala 108:68]
- wire _active_active0_active_active_T_58 = _last_T & active_active0_active_idx_1 == 2'h3 | value_m & _active_active0_T
- [2:0] <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active0_active_active_T_59 = _active_active0_active_active_T_58 ? active_active0_active_oh3_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active0_active_active_1 = _active_active0_active_active_T_52 | _active_active0_active_active_T_59; // @[VCommon.scala 109:68]
- wire [63:0] _active_active0_active_T_11 = value_tin_vt_valid ? active_active0_active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active0_active_T_12 = _active_active0_active_T_5 | _active_active0_active_T_11; // @[VAlu.scala 249:74]
- wire [3:0] active_active0_active_oh_shiftAmount_2 = value_tin_vu_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active0_active_oh_2 = 16'h1 << active_active0_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
- wire [15:0] active_active0_active_oh0_lo_lo_2 = {3'h0,active_active0_active_oh_2[3],3'h0,active_active0_active_oh_2[2]
- ,3'h0,active_active0_active_oh_2[1],3'h0,active_active0_active_oh_2[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh0_lo_2 = {3'h0,active_active0_active_oh_2[7],3'h0,active_active0_active_oh_2[6],3'h0
- ,active_active0_active_oh_2[5],3'h0,active_active0_active_oh_2[4],active_active0_active_oh0_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh0_hi_lo_2 = {3'h0,active_active0_active_oh_2[11],3'h0,active_active0_active_oh_2[
- 10],3'h0,active_active0_active_oh_2[9],3'h0,active_active0_active_oh_2[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh0_2 = {3'h0,active_active0_active_oh_2[15],3'h0,active_active0_active_oh_2[14],3'h0
- ,active_active0_active_oh_2[13],3'h0,active_active0_active_oh_2[12],active_active0_active_oh0_hi_lo_2,
- active_active0_active_oh0_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_lo_lo_2 = {2'h0,active_active0_active_oh_2[1],1'h0,2'h0,
- active_active0_active_oh_2[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_lo_lo_2 = {2'h0,active_active0_active_oh_2[3],1'h0,2'h0,
- active_active0_active_oh_2[2],1'h0,active_active0_active_oh1_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_hi_lo_2 = {2'h0,active_active0_active_oh_2[5],1'h0,2'h0,
- active_active0_active_oh_2[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh1_lo_2 = {2'h0,active_active0_active_oh_2[7],1'h0,2'h0,active_active0_active_oh_2[
- 6],1'h0,active_active0_active_oh1_lo_hi_lo_2,active_active0_active_oh1_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_lo_lo_2 = {2'h0,active_active0_active_oh_2[9],1'h0,2'h0,
- active_active0_active_oh_2[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_hi_lo_2 = {2'h0,active_active0_active_oh_2[11],1'h0,2'h0,
- active_active0_active_oh_2[10],1'h0,active_active0_active_oh1_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_hi_lo_2 = {2'h0,active_active0_active_oh_2[13],1'h0,2'h0,
- active_active0_active_oh_2[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh1_2 = {2'h0,active_active0_active_oh_2[15],1'h0,2'h0,active_active0_active_oh_2[14
- ],1'h0,active_active0_active_oh1_hi_hi_lo_2,active_active0_active_oh1_hi_lo_2,active_active0_active_oh1_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_lo_lo_2 = {1'h0,active_active0_active_oh_2[1],2'h0,1'h0,
- active_active0_active_oh_2[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_lo_lo_2 = {1'h0,active_active0_active_oh_2[3],2'h0,1'h0,
- active_active0_active_oh_2[2],2'h0,active_active0_active_oh2_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_hi_lo_2 = {1'h0,active_active0_active_oh_2[5],2'h0,1'h0,
- active_active0_active_oh_2[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh2_lo_2 = {1'h0,active_active0_active_oh_2[7],2'h0,1'h0,active_active0_active_oh_2[
- 6],2'h0,active_active0_active_oh2_lo_hi_lo_2,active_active0_active_oh2_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_lo_lo_2 = {1'h0,active_active0_active_oh_2[9],2'h0,1'h0,
- active_active0_active_oh_2[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_hi_lo_2 = {1'h0,active_active0_active_oh_2[11],2'h0,1'h0,
- active_active0_active_oh_2[10],2'h0,active_active0_active_oh2_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_hi_lo_2 = {1'h0,active_active0_active_oh_2[13],2'h0,1'h0,
- active_active0_active_oh_2[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh2_2 = {1'h0,active_active0_active_oh_2[15],2'h0,1'h0,active_active0_active_oh_2[14
- ],2'h0,active_active0_active_oh2_hi_hi_lo_2,active_active0_active_oh2_hi_lo_2,active_active0_active_oh2_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_lo_lo_2 = {active_active0_active_oh_2[3],3'h0,active_active0_active_oh_2[2],3'h0
- ,active_active0_active_oh_2[1],3'h0,active_active0_active_oh_2[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh3_lo_2 = {active_active0_active_oh_2[7],3'h0,active_active0_active_oh_2[6],3'h0,
- active_active0_active_oh_2[5],3'h0,active_active0_active_oh_2[4],3'h0,active_active0_active_oh3_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_hi_lo_2 = {active_active0_active_oh_2[11],3'h0,active_active0_active_oh_2[10],3'h0
- ,active_active0_active_oh_2[9],3'h0,active_active0_active_oh_2[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh3_2 = {active_active0_active_oh_2[15],3'h0,active_active0_active_oh_2[14],3'h0,
- active_active0_active_oh_2[13],3'h0,active_active0_active_oh_2[12],3'h0,active_active0_active_oh3_hi_lo_2,
- active_active0_active_oh3_lo_2}; // @[Cat.scala 31:58]
- wire [1:0] active_active0_active_idx_2 = value_tin_vu_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active0_active_active_T_65 = _last_T & active_active0_active_idx_2 == 2'h0 | value_m & _active_active0_T
- [2:0] <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active0_active_active_T_66 = _active_active0_active_active_T_65 ? active_active0_active_oh0_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active0_active_active_T_72 = _last_T & active_active0_active_idx_2 == 2'h1 | value_m & _active_active0_T
- [2:0] <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active0_active_active_T_73 = _active_active0_active_active_T_72 ? active_active0_active_oh1_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_74 = _active_active0_active_active_T_66 |
- _active_active0_active_active_T_73; // @[VCommon.scala 107:68]
- wire _active_active0_active_active_T_80 = _last_T & active_active0_active_idx_2 == 2'h2 | value_m & _active_active0_T
- [2:0] <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active0_active_active_T_81 = _active_active0_active_active_T_80 ? active_active0_active_oh2_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_82 = _active_active0_active_active_T_74 |
- _active_active0_active_active_T_81; // @[VCommon.scala 108:68]
- wire _active_active0_active_active_T_88 = _last_T & active_active0_active_idx_2 == 2'h3 | value_m & _active_active0_T
- [2:0] <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active0_active_active_T_89 = _active_active0_active_active_T_88 ? active_active0_active_oh3_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active0_active_active_2 = _active_active0_active_active_T_82 | _active_active0_active_active_T_89; // @[VCommon.scala 109:68]
- wire [63:0] _active_active0_active_T_18 = value_tin_vu_valid ? active_active0_active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active0 = _active_active0_active_T_12 | _active_active0_active_T_18; // @[VAlu.scala 250:74]
- wire _active_active1_active_active_T_5 = _last_T & active_active0_active_idx == 2'h0 | value_m & _step_T_1[2:0] <= 3'h0
- ; // @[VCommon.scala 107:42]
- wire [63:0] _active_active1_active_active_T_6 = _active_active1_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active1_active_active_T_12 = _last_T & active_active0_active_idx == 2'h1 | value_m & _step_T_1[2:0] <= 3'h1
- ; // @[VCommon.scala 108:42]
- wire [63:0] _active_active1_active_active_T_13 = _active_active1_active_active_T_12 ? active_active0_active_oh1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_14 = _active_active1_active_active_T_6 |
- _active_active1_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active1_active_active_T_20 = _last_T & active_active0_active_idx == 2'h2 | value_m & _step_T_1[2:0] <= 3'h2
- ; // @[VCommon.scala 109:42]
- wire [63:0] _active_active1_active_active_T_21 = _active_active1_active_active_T_20 ? active_active0_active_oh2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_22 = _active_active1_active_active_T_14 |
- _active_active1_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active1_active_active_T_28 = _last_T & active_active0_active_idx == 2'h3 | value_m & _step_T_1[2:0] <= 3'h3
- ; // @[VCommon.scala 110:42]
- wire [63:0] _active_active1_active_active_T_29 = _active_active1_active_active_T_28 ? active_active0_active_oh3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active1_active_active = _active_active1_active_active_T_22 | _active_active1_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] _active_active1_active_T_5 = value_tin_vs_valid ? active_active1_active_active : 64'h0; // @[Library.scala 22:8]
- wire _active_active1_active_active_T_35 = _last_T & active_active0_active_idx_1 == 2'h0 | value_m & _step_T_1[2:0]
- <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active1_active_active_T_36 = _active_active1_active_active_T_35 ? active_active0_active_oh0_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active1_active_active_T_42 = _last_T & active_active0_active_idx_1 == 2'h1 | value_m & _step_T_1[2:0]
- <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active1_active_active_T_43 = _active_active1_active_active_T_42 ? active_active0_active_oh1_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_44 = _active_active1_active_active_T_36 |
- _active_active1_active_active_T_43; // @[VCommon.scala 107:68]
- wire _active_active1_active_active_T_50 = _last_T & active_active0_active_idx_1 == 2'h2 | value_m & _step_T_1[2:0]
- <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active1_active_active_T_51 = _active_active1_active_active_T_50 ? active_active0_active_oh2_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_52 = _active_active1_active_active_T_44 |
- _active_active1_active_active_T_51; // @[VCommon.scala 108:68]
- wire _active_active1_active_active_T_58 = _last_T & active_active0_active_idx_1 == 2'h3 | value_m & _step_T_1[2:0]
- <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active1_active_active_T_59 = _active_active1_active_active_T_58 ? active_active0_active_oh3_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active1_active_active_1 = _active_active1_active_active_T_52 | _active_active1_active_active_T_59; // @[VCommon.scala 109:68]
- wire [63:0] _active_active1_active_T_11 = value_tin_vt_valid ? active_active1_active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_active1_active_T_12 = _active_active1_active_T_5 | _active_active1_active_T_11; // @[VAlu.scala 249:74]
- wire _active_active1_active_active_T_65 = _last_T & active_active0_active_idx_2 == 2'h0 | value_m & _step_T_1[2:0]
- <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active1_active_active_T_66 = _active_active1_active_active_T_65 ? active_active0_active_oh0_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active1_active_active_T_72 = _last_T & active_active0_active_idx_2 == 2'h1 | value_m & _step_T_1[2:0]
- <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active1_active_active_T_73 = _active_active1_active_active_T_72 ? active_active0_active_oh1_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_74 = _active_active1_active_active_T_66 |
- _active_active1_active_active_T_73; // @[VCommon.scala 107:68]
- wire _active_active1_active_active_T_80 = _last_T & active_active0_active_idx_2 == 2'h2 | value_m & _step_T_1[2:0]
- <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active1_active_active_T_81 = _active_active1_active_active_T_80 ? active_active0_active_oh2_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_82 = _active_active1_active_active_T_74 |
- _active_active1_active_active_T_81; // @[VCommon.scala 108:68]
- wire _active_active1_active_active_T_88 = _last_T & active_active0_active_idx_2 == 2'h3 | value_m & _step_T_1[2:0]
- <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active1_active_active_T_89 = _active_active1_active_active_T_88 ? active_active0_active_oh3_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active1_active_active_2 = _active_active1_active_active_T_82 | _active_active1_active_active_T_89; // @[VCommon.scala 109:68]
- wire [63:0] _active_active1_active_T_18 = value_tin_vu_valid ? active_active1_active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active1 = _active_active1_active_T_12 | _active_active1_active_T_18; // @[VAlu.scala 250:74]
- wire _active_active_T_96 = ~io_out_ready; // @[VCmdq.scala 112:36]
- wire _active_active_T_99 = valid & (~io_out_ready | _T_10); // @[VCmdq.scala 112:32]
- wire [63:0] _active_active_T_101 = _active_active_T_96 ? active_active0 : active_active1; // @[VCmdq.scala 113:29]
- wire [63:0] active_active_12 = _active_active_T_99 ? _active_active_T_101 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_35 = _active_T_34 | active_active_12; // @[VCmdq.scala 114:12]
- wire [63:0] _active_T_36 = _active_T_26 | _active_T_35; // @[VCmdq.scala 127:90]
- wire _GEN_149 = _T_14 & _T_6; // @[VAlu.scala 247:11]
- Fifo4e f ( // @[Fifo4e.scala 24:11]
- .clock(f_clock),
- .reset(f_reset),
- .io_in_ready(f_io_in_ready),
- .io_in_valid(f_io_in_valid),
- .io_in_bits_0_valid(f_io_in_bits_0_valid),
- .io_in_bits_0_bits_tin_op(f_io_in_bits_0_bits_tin_op),
- .io_in_bits_0_bits_tin_f2(f_io_in_bits_0_bits_tin_f2),
- .io_in_bits_0_bits_tin_sz(f_io_in_bits_0_bits_tin_sz),
- .io_in_bits_0_bits_tin_vd_addr(f_io_in_bits_0_bits_tin_vd_addr),
- .io_in_bits_0_bits_tin_ve_addr(f_io_in_bits_0_bits_tin_ve_addr),
- .io_in_bits_0_bits_tin_vs_valid(f_io_in_bits_0_bits_tin_vs_valid),
- .io_in_bits_0_bits_tin_vs_addr(f_io_in_bits_0_bits_tin_vs_addr),
- .io_in_bits_0_bits_tin_vs_tag(f_io_in_bits_0_bits_tin_vs_tag),
- .io_in_bits_0_bits_tin_vt_valid(f_io_in_bits_0_bits_tin_vt_valid),
- .io_in_bits_0_bits_tin_vt_addr(f_io_in_bits_0_bits_tin_vt_addr),
- .io_in_bits_0_bits_tin_vt_tag(f_io_in_bits_0_bits_tin_vt_tag),
- .io_in_bits_0_bits_tin_vu_valid(f_io_in_bits_0_bits_tin_vu_valid),
- .io_in_bits_0_bits_tin_vu_addr(f_io_in_bits_0_bits_tin_vu_addr),
- .io_in_bits_0_bits_tin_vu_tag(f_io_in_bits_0_bits_tin_vu_tag),
- .io_in_bits_0_bits_tin_sv_valid(f_io_in_bits_0_bits_tin_sv_valid),
- .io_in_bits_0_bits_tin_sv_data(f_io_in_bits_0_bits_tin_sv_data),
- .io_in_bits_0_bits_tin_cmdsync(f_io_in_bits_0_bits_tin_cmdsync),
- .io_in_bits_0_bits_m(f_io_in_bits_0_bits_m),
- .io_in_bits_1_valid(f_io_in_bits_1_valid),
- .io_in_bits_1_bits_tin_op(f_io_in_bits_1_bits_tin_op),
- .io_in_bits_1_bits_tin_f2(f_io_in_bits_1_bits_tin_f2),
- .io_in_bits_1_bits_tin_sz(f_io_in_bits_1_bits_tin_sz),
- .io_in_bits_1_bits_tin_vd_addr(f_io_in_bits_1_bits_tin_vd_addr),
- .io_in_bits_1_bits_tin_ve_addr(f_io_in_bits_1_bits_tin_ve_addr),
- .io_in_bits_1_bits_tin_vs_valid(f_io_in_bits_1_bits_tin_vs_valid),
- .io_in_bits_1_bits_tin_vs_addr(f_io_in_bits_1_bits_tin_vs_addr),
- .io_in_bits_1_bits_tin_vs_tag(f_io_in_bits_1_bits_tin_vs_tag),
- .io_in_bits_1_bits_tin_vt_valid(f_io_in_bits_1_bits_tin_vt_valid),
- .io_in_bits_1_bits_tin_vt_addr(f_io_in_bits_1_bits_tin_vt_addr),
- .io_in_bits_1_bits_tin_vt_tag(f_io_in_bits_1_bits_tin_vt_tag),
- .io_in_bits_1_bits_tin_vu_valid(f_io_in_bits_1_bits_tin_vu_valid),
- .io_in_bits_1_bits_tin_vu_addr(f_io_in_bits_1_bits_tin_vu_addr),
- .io_in_bits_1_bits_tin_vu_tag(f_io_in_bits_1_bits_tin_vu_tag),
- .io_in_bits_1_bits_tin_sv_valid(f_io_in_bits_1_bits_tin_sv_valid),
- .io_in_bits_1_bits_tin_sv_data(f_io_in_bits_1_bits_tin_sv_data),
- .io_in_bits_1_bits_tin_cmdsync(f_io_in_bits_1_bits_tin_cmdsync),
- .io_in_bits_1_bits_m(f_io_in_bits_1_bits_m),
- .io_in_bits_2_valid(f_io_in_bits_2_valid),
- .io_in_bits_2_bits_tin_op(f_io_in_bits_2_bits_tin_op),
- .io_in_bits_2_bits_tin_f2(f_io_in_bits_2_bits_tin_f2),
- .io_in_bits_2_bits_tin_sz(f_io_in_bits_2_bits_tin_sz),
- .io_in_bits_2_bits_tin_vd_addr(f_io_in_bits_2_bits_tin_vd_addr),
- .io_in_bits_2_bits_tin_ve_addr(f_io_in_bits_2_bits_tin_ve_addr),
- .io_in_bits_2_bits_tin_vs_valid(f_io_in_bits_2_bits_tin_vs_valid),
- .io_in_bits_2_bits_tin_vs_addr(f_io_in_bits_2_bits_tin_vs_addr),
- .io_in_bits_2_bits_tin_vs_tag(f_io_in_bits_2_bits_tin_vs_tag),
- .io_in_bits_2_bits_tin_vt_valid(f_io_in_bits_2_bits_tin_vt_valid),
- .io_in_bits_2_bits_tin_vt_addr(f_io_in_bits_2_bits_tin_vt_addr),
- .io_in_bits_2_bits_tin_vt_tag(f_io_in_bits_2_bits_tin_vt_tag),
- .io_in_bits_2_bits_tin_vu_valid(f_io_in_bits_2_bits_tin_vu_valid),
- .io_in_bits_2_bits_tin_vu_addr(f_io_in_bits_2_bits_tin_vu_addr),
- .io_in_bits_2_bits_tin_vu_tag(f_io_in_bits_2_bits_tin_vu_tag),
- .io_in_bits_2_bits_tin_sv_valid(f_io_in_bits_2_bits_tin_sv_valid),
- .io_in_bits_2_bits_tin_sv_data(f_io_in_bits_2_bits_tin_sv_data),
- .io_in_bits_2_bits_tin_cmdsync(f_io_in_bits_2_bits_tin_cmdsync),
- .io_in_bits_2_bits_m(f_io_in_bits_2_bits_m),
- .io_in_bits_3_valid(f_io_in_bits_3_valid),
- .io_in_bits_3_bits_tin_op(f_io_in_bits_3_bits_tin_op),
- .io_in_bits_3_bits_tin_f2(f_io_in_bits_3_bits_tin_f2),
- .io_in_bits_3_bits_tin_sz(f_io_in_bits_3_bits_tin_sz),
- .io_in_bits_3_bits_tin_vd_addr(f_io_in_bits_3_bits_tin_vd_addr),
- .io_in_bits_3_bits_tin_ve_addr(f_io_in_bits_3_bits_tin_ve_addr),
- .io_in_bits_3_bits_tin_vs_valid(f_io_in_bits_3_bits_tin_vs_valid),
- .io_in_bits_3_bits_tin_vs_addr(f_io_in_bits_3_bits_tin_vs_addr),
- .io_in_bits_3_bits_tin_vs_tag(f_io_in_bits_3_bits_tin_vs_tag),
- .io_in_bits_3_bits_tin_vt_valid(f_io_in_bits_3_bits_tin_vt_valid),
- .io_in_bits_3_bits_tin_vt_addr(f_io_in_bits_3_bits_tin_vt_addr),
- .io_in_bits_3_bits_tin_vt_tag(f_io_in_bits_3_bits_tin_vt_tag),
- .io_in_bits_3_bits_tin_vu_valid(f_io_in_bits_3_bits_tin_vu_valid),
- .io_in_bits_3_bits_tin_vu_addr(f_io_in_bits_3_bits_tin_vu_addr),
- .io_in_bits_3_bits_tin_vu_tag(f_io_in_bits_3_bits_tin_vu_tag),
- .io_in_bits_3_bits_tin_sv_valid(f_io_in_bits_3_bits_tin_sv_valid),
- .io_in_bits_3_bits_tin_sv_data(f_io_in_bits_3_bits_tin_sv_data),
- .io_in_bits_3_bits_tin_cmdsync(f_io_in_bits_3_bits_tin_cmdsync),
- .io_in_bits_3_bits_m(f_io_in_bits_3_bits_m),
- .io_out_ready(f_io_out_ready),
- .io_out_valid(f_io_out_valid),
- .io_out_bits_tin_op(f_io_out_bits_tin_op),
- .io_out_bits_tin_f2(f_io_out_bits_tin_f2),
- .io_out_bits_tin_sz(f_io_out_bits_tin_sz),
- .io_out_bits_tin_vd_addr(f_io_out_bits_tin_vd_addr),
- .io_out_bits_tin_ve_addr(f_io_out_bits_tin_ve_addr),
- .io_out_bits_tin_vs_valid(f_io_out_bits_tin_vs_valid),
- .io_out_bits_tin_vs_addr(f_io_out_bits_tin_vs_addr),
- .io_out_bits_tin_vs_tag(f_io_out_bits_tin_vs_tag),
- .io_out_bits_tin_vt_valid(f_io_out_bits_tin_vt_valid),
- .io_out_bits_tin_vt_addr(f_io_out_bits_tin_vt_addr),
- .io_out_bits_tin_vt_tag(f_io_out_bits_tin_vt_tag),
- .io_out_bits_tin_vu_valid(f_io_out_bits_tin_vu_valid),
- .io_out_bits_tin_vu_addr(f_io_out_bits_tin_vu_addr),
- .io_out_bits_tin_vu_tag(f_io_out_bits_tin_vu_tag),
- .io_out_bits_tin_sv_valid(f_io_out_bits_tin_sv_valid),
- .io_out_bits_tin_sv_data(f_io_out_bits_tin_sv_data),
- .io_out_bits_tin_cmdsync(f_io_out_bits_tin_cmdsync),
- .io_out_bits_m(f_io_out_bits_m),
- .io_entry_0_valid(f_io_entry_0_valid),
- .io_entry_0_bits_tin_vs_valid(f_io_entry_0_bits_tin_vs_valid),
- .io_entry_0_bits_tin_vs_addr(f_io_entry_0_bits_tin_vs_addr),
- .io_entry_0_bits_tin_vt_valid(f_io_entry_0_bits_tin_vt_valid),
- .io_entry_0_bits_tin_vt_addr(f_io_entry_0_bits_tin_vt_addr),
- .io_entry_0_bits_tin_vu_valid(f_io_entry_0_bits_tin_vu_valid),
- .io_entry_0_bits_tin_vu_addr(f_io_entry_0_bits_tin_vu_addr),
- .io_entry_0_bits_m(f_io_entry_0_bits_m),
- .io_entry_1_valid(f_io_entry_1_valid),
- .io_entry_1_bits_tin_vs_valid(f_io_entry_1_bits_tin_vs_valid),
- .io_entry_1_bits_tin_vs_addr(f_io_entry_1_bits_tin_vs_addr),
- .io_entry_1_bits_tin_vt_valid(f_io_entry_1_bits_tin_vt_valid),
- .io_entry_1_bits_tin_vt_addr(f_io_entry_1_bits_tin_vt_addr),
- .io_entry_1_bits_tin_vu_valid(f_io_entry_1_bits_tin_vu_valid),
- .io_entry_1_bits_tin_vu_addr(f_io_entry_1_bits_tin_vu_addr),
- .io_entry_1_bits_m(f_io_entry_1_bits_m),
- .io_entry_2_valid(f_io_entry_2_valid),
- .io_entry_2_bits_tin_vs_valid(f_io_entry_2_bits_tin_vs_valid),
- .io_entry_2_bits_tin_vs_addr(f_io_entry_2_bits_tin_vs_addr),
- .io_entry_2_bits_tin_vt_valid(f_io_entry_2_bits_tin_vt_valid),
- .io_entry_2_bits_tin_vt_addr(f_io_entry_2_bits_tin_vt_addr),
- .io_entry_2_bits_tin_vu_valid(f_io_entry_2_bits_tin_vu_valid),
- .io_entry_2_bits_tin_vu_addr(f_io_entry_2_bits_tin_vu_addr),
- .io_entry_2_bits_m(f_io_entry_2_bits_m),
- .io_entry_3_valid(f_io_entry_3_valid),
- .io_entry_3_bits_tin_vs_valid(f_io_entry_3_bits_tin_vs_valid),
- .io_entry_3_bits_tin_vs_addr(f_io_entry_3_bits_tin_vs_addr),
- .io_entry_3_bits_tin_vt_valid(f_io_entry_3_bits_tin_vt_valid),
- .io_entry_3_bits_tin_vt_addr(f_io_entry_3_bits_tin_vt_addr),
- .io_entry_3_bits_tin_vu_valid(f_io_entry_3_bits_tin_vu_valid),
- .io_entry_3_bits_tin_vu_addr(f_io_entry_3_bits_tin_vu_addr),
- .io_entry_3_bits_m(f_io_entry_3_bits_m),
- .io_entry_4_valid(f_io_entry_4_valid),
- .io_entry_4_bits_tin_vs_valid(f_io_entry_4_bits_tin_vs_valid),
- .io_entry_4_bits_tin_vs_addr(f_io_entry_4_bits_tin_vs_addr),
- .io_entry_4_bits_tin_vt_valid(f_io_entry_4_bits_tin_vt_valid),
- .io_entry_4_bits_tin_vt_addr(f_io_entry_4_bits_tin_vt_addr),
- .io_entry_4_bits_tin_vu_valid(f_io_entry_4_bits_tin_vu_valid),
- .io_entry_4_bits_tin_vu_addr(f_io_entry_4_bits_tin_vu_addr),
- .io_entry_4_bits_m(f_io_entry_4_bits_m),
- .io_entry_5_valid(f_io_entry_5_valid),
- .io_entry_5_bits_tin_vs_valid(f_io_entry_5_bits_tin_vs_valid),
- .io_entry_5_bits_tin_vs_addr(f_io_entry_5_bits_tin_vs_addr),
- .io_entry_5_bits_tin_vt_valid(f_io_entry_5_bits_tin_vt_valid),
- .io_entry_5_bits_tin_vt_addr(f_io_entry_5_bits_tin_vt_addr),
- .io_entry_5_bits_tin_vu_valid(f_io_entry_5_bits_tin_vu_valid),
- .io_entry_5_bits_tin_vu_addr(f_io_entry_5_bits_tin_vu_addr),
- .io_entry_5_bits_m(f_io_entry_5_bits_m),
- .io_entry_6_valid(f_io_entry_6_valid),
- .io_entry_6_bits_tin_vs_valid(f_io_entry_6_bits_tin_vs_valid),
- .io_entry_6_bits_tin_vs_addr(f_io_entry_6_bits_tin_vs_addr),
- .io_entry_6_bits_tin_vt_valid(f_io_entry_6_bits_tin_vt_valid),
- .io_entry_6_bits_tin_vt_addr(f_io_entry_6_bits_tin_vt_addr),
- .io_entry_6_bits_tin_vu_valid(f_io_entry_6_bits_tin_vu_valid),
- .io_entry_6_bits_tin_vu_addr(f_io_entry_6_bits_tin_vu_addr),
- .io_entry_6_bits_m(f_io_entry_6_bits_m),
- .io_entry_7_valid(f_io_entry_7_valid),
- .io_entry_7_bits_tin_vs_valid(f_io_entry_7_bits_tin_vs_valid),
- .io_entry_7_bits_tin_vs_addr(f_io_entry_7_bits_tin_vs_addr),
- .io_entry_7_bits_tin_vt_valid(f_io_entry_7_bits_tin_vt_valid),
- .io_entry_7_bits_tin_vt_addr(f_io_entry_7_bits_tin_vt_addr),
- .io_entry_7_bits_tin_vu_valid(f_io_entry_7_bits_tin_vu_valid),
- .io_entry_7_bits_tin_vu_addr(f_io_entry_7_bits_tin_vu_addr),
- .io_entry_7_bits_m(f_io_entry_7_bits_m)
- );
- assign io_in_ready = f_io_in_ready; // @[VCmdq.scala 65:15]
- assign io_out_valid = valid; // @[VCmdq.scala 133:16]
- assign io_out_bits_op = value_tin_op; // @[VCmdq.scala 134:15]
- assign io_out_bits_f2 = value_tin_f2; // @[VCmdq.scala 134:15]
- assign io_out_bits_sz = value_tin_sz; // @[VCmdq.scala 134:15]
- assign io_out_bits_vd_addr = value_tin_vd_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_ve_addr = value_tin_ve_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_vs_valid = value_tin_vs_valid; // @[VCmdq.scala 134:15]
- assign io_out_bits_vs_addr = value_tin_vs_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_vs_tag = value_tin_vs_tag; // @[VCmdq.scala 134:15]
- assign io_out_bits_vt_valid = value_tin_vt_valid; // @[VCmdq.scala 134:15]
- assign io_out_bits_vt_addr = value_tin_vt_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_vt_tag = value_tin_vt_tag; // @[VCmdq.scala 134:15]
- assign io_out_bits_vu_valid = value_tin_vu_valid; // @[VCmdq.scala 134:15]
- assign io_out_bits_vu_addr = value_tin_vu_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_vu_tag = value_tin_vu_tag; // @[VCmdq.scala 134:15]
- assign io_out_bits_sv_valid = value_tin_sv_valid; // @[VCmdq.scala 134:15]
- assign io_out_bits_sv_data = value_tin_sv_data; // @[VCmdq.scala 134:15]
- assign io_out_bits_cmdsync = value_tin_cmdsync; // @[VCmdq.scala 134:15]
- assign io_active = active; // @[VCmdq.scala 136:13]
- assign f_clock = clock;
- assign f_reset = reset;
- assign f_io_in_valid = io_in_valid; // @[VCmdq.scala 64:17]
- assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VAlu.scala 186:19 187:12]
- assign f_io_in_bits_0_bits_tin_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 186:19 188:12]
- assign f_io_in_bits_0_bits_tin_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 186:19 189:12]
- assign f_io_in_bits_0_bits_tin_vd_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vd_addr :
- io_in_bits_0_bits_vf_addr; // @[VAlu.scala 191:40 192:14 198:14]
- assign f_io_in_bits_0_bits_tin_ve_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_ve_addr :
- io_in_bits_0_bits_vg_addr; // @[VAlu.scala 191:40 193:14 199:14]
- assign f_io_in_bits_0_bits_tin_vs_valid = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vs_valid :
- io_in_bits_0_bits_vx_valid; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_0_bits_tin_vs_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vs_addr :
- io_in_bits_0_bits_vx_addr; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_0_bits_tin_vs_tag = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vs_tag :
- io_in_bits_0_bits_vx_tag; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_0_bits_tin_vt_valid = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vt_valid :
- io_in_bits_0_bits_vy_valid; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_0_bits_tin_vt_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vt_addr :
- io_in_bits_0_bits_vy_addr; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_0_bits_tin_vt_tag = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vt_tag :
- io_in_bits_0_bits_vy_tag; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_0_bits_tin_vu_valid = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vu_valid :
- io_in_bits_0_bits_vz_valid; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_0_bits_tin_vu_addr = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vu_addr :
- io_in_bits_0_bits_vz_addr; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_0_bits_tin_vu_tag = ~io_in_bits_0_bits_cmdsync ? io_in_bits_0_bits_vu_tag :
- io_in_bits_0_bits_vz_tag; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_0_bits_tin_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_0_bits_tin_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_0_bits_tin_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 186:19 190:17]
- assign f_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VAlu.scala 186:19 187:12]
- assign f_io_in_bits_1_bits_tin_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 186:19 188:12]
- assign f_io_in_bits_1_bits_tin_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 186:19 189:12]
- assign f_io_in_bits_1_bits_tin_vd_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vd_addr :
- io_in_bits_1_bits_vf_addr; // @[VAlu.scala 191:40 192:14 198:14]
- assign f_io_in_bits_1_bits_tin_ve_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_ve_addr :
- io_in_bits_1_bits_vg_addr; // @[VAlu.scala 191:40 193:14 199:14]
- assign f_io_in_bits_1_bits_tin_vs_valid = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vs_valid :
- io_in_bits_1_bits_vx_valid; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_1_bits_tin_vs_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vs_addr :
- io_in_bits_1_bits_vx_addr; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_1_bits_tin_vs_tag = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vs_tag :
- io_in_bits_1_bits_vx_tag; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_1_bits_tin_vt_valid = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vt_valid :
- io_in_bits_1_bits_vy_valid; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_1_bits_tin_vt_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vt_addr :
- io_in_bits_1_bits_vy_addr; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_1_bits_tin_vt_tag = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vt_tag :
- io_in_bits_1_bits_vy_tag; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_1_bits_tin_vu_valid = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vu_valid :
- io_in_bits_1_bits_vz_valid; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_1_bits_tin_vu_addr = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vu_addr :
- io_in_bits_1_bits_vz_addr; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_1_bits_tin_vu_tag = ~io_in_bits_1_bits_cmdsync ? io_in_bits_1_bits_vu_tag :
- io_in_bits_1_bits_vz_tag; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_1_bits_tin_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_1_bits_tin_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_1_bits_tin_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 186:19 190:17]
- assign f_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VAlu.scala 186:19 187:12]
- assign f_io_in_bits_2_bits_tin_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 186:19 188:12]
- assign f_io_in_bits_2_bits_tin_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 186:19 189:12]
- assign f_io_in_bits_2_bits_tin_vd_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vd_addr :
- io_in_bits_2_bits_vf_addr; // @[VAlu.scala 191:40 192:14 198:14]
- assign f_io_in_bits_2_bits_tin_ve_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_ve_addr :
- io_in_bits_2_bits_vg_addr; // @[VAlu.scala 191:40 193:14 199:14]
- assign f_io_in_bits_2_bits_tin_vs_valid = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vs_valid :
- io_in_bits_2_bits_vx_valid; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_2_bits_tin_vs_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vs_addr :
- io_in_bits_2_bits_vx_addr; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_2_bits_tin_vs_tag = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vs_tag :
- io_in_bits_2_bits_vx_tag; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_2_bits_tin_vt_valid = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vt_valid :
- io_in_bits_2_bits_vy_valid; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_2_bits_tin_vt_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vt_addr :
- io_in_bits_2_bits_vy_addr; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_2_bits_tin_vt_tag = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vt_tag :
- io_in_bits_2_bits_vy_tag; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_2_bits_tin_vu_valid = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vu_valid :
- io_in_bits_2_bits_vz_valid; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_2_bits_tin_vu_addr = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vu_addr :
- io_in_bits_2_bits_vz_addr; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_2_bits_tin_vu_tag = ~io_in_bits_2_bits_cmdsync ? io_in_bits_2_bits_vu_tag :
- io_in_bits_2_bits_vz_tag; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_2_bits_tin_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_2_bits_tin_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_2_bits_tin_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 186:19 190:17]
- assign f_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VAlu.scala 186:19 187:12]
- assign f_io_in_bits_3_bits_tin_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 186:19 188:12]
- assign f_io_in_bits_3_bits_tin_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 186:19 189:12]
- assign f_io_in_bits_3_bits_tin_vd_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vd_addr :
- io_in_bits_3_bits_vf_addr; // @[VAlu.scala 191:40 192:14 198:14]
- assign f_io_in_bits_3_bits_tin_ve_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_ve_addr :
- io_in_bits_3_bits_vg_addr; // @[VAlu.scala 191:40 193:14 199:14]
- assign f_io_in_bits_3_bits_tin_vs_valid = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vs_valid :
- io_in_bits_3_bits_vx_valid; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_3_bits_tin_vs_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vs_addr :
- io_in_bits_3_bits_vx_addr; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_3_bits_tin_vs_tag = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vs_tag :
- io_in_bits_3_bits_vx_tag; // @[VAlu.scala 191:40 194:14 200:14]
- assign f_io_in_bits_3_bits_tin_vt_valid = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vt_valid :
- io_in_bits_3_bits_vy_valid; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_3_bits_tin_vt_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vt_addr :
- io_in_bits_3_bits_vy_addr; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_3_bits_tin_vt_tag = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vt_tag :
- io_in_bits_3_bits_vy_tag; // @[VAlu.scala 191:40 195:14 201:14]
- assign f_io_in_bits_3_bits_tin_vu_valid = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vu_valid :
- io_in_bits_3_bits_vz_valid; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_3_bits_tin_vu_addr = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vu_addr :
- io_in_bits_3_bits_vz_addr; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_3_bits_tin_vu_tag = ~io_in_bits_3_bits_cmdsync ? io_in_bits_3_bits_vu_tag :
- io_in_bits_3_bits_vz_tag; // @[VAlu.scala 191:40 196:14 202:14]
- assign f_io_in_bits_3_bits_tin_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_3_bits_tin_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 186:19 204:12]
- assign f_io_in_bits_3_bits_tin_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 186:19 190:17]
- assign f_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_out_ready = ~valid | io_out_ready & last; // @[VCmdq.scala 73:28]
- always @(posedge clock) begin
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_op <= 7'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_op <= f_io_out_bits_tin_op; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_op <= 7'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_f2 <= 3'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_f2 <= f_io_out_bits_tin_f2; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_f2 <= 3'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_sz <= 3'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_sz <= f_io_out_bits_tin_sz; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_sz <= 3'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vd_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vd_addr <= f_io_out_bits_tin_vd_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_vd_addr <= tin_vd_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_vd_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_ve_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_ve_addr <= f_io_out_bits_tin_ve_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_ve_addr <= tin_ve_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_ve_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vs_valid <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vs_valid <= f_io_out_bits_tin_vs_valid; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_vs_valid <= _GEN_71;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vs_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vs_addr <= f_io_out_bits_tin_vs_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_vs_addr <= tin_vs_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_vs_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vs_tag <= 4'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vs_tag <= f_io_out_bits_tin_vs_tag; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_vs_tag <= 4'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vt_valid <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vt_valid <= f_io_out_bits_tin_vt_valid; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_vt_valid <= _GEN_68;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vt_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vt_addr <= f_io_out_bits_tin_vt_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_vt_addr <= tin_vt_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_vt_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vt_tag <= 4'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vt_tag <= f_io_out_bits_tin_vt_tag; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_vt_tag <= 4'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vu_valid <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vu_valid <= f_io_out_bits_tin_vu_valid; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_vu_valid <= _GEN_65;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vu_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vu_addr <= f_io_out_bits_tin_vu_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_vu_addr <= tin_vu_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_vu_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vu_tag <= 4'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vu_tag <= f_io_out_bits_tin_vu_tag; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_vu_tag <= 4'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_sv_valid <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_sv_valid <= f_io_out_bits_tin_sv_valid; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_sv_valid <= _GEN_62;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_sv_data <= 32'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_sv_data <= f_io_out_bits_tin_sv_data; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_sv_data <= 32'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_cmdsync <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_cmdsync <= f_io_out_bits_tin_cmdsync; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_cmdsync <= _GEN_60;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_m <= 1'h0; // @[VCmdq.scala 98:13]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_m <= f_io_out_bits_m; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_m <= _GEN_79;
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (vzip & ~reset & ~(value_tin_ve_addr == _out_vd_addr_T_1)) begin
- $fatal; // @[VAlu.scala 238:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (vzip & ~reset & ~(value_tin_ve_addr == _out_vd_addr_T_1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:238 assert(in.ve.addr === (in.vd.addr + 1.U))\n"); // @[VAlu.scala 238:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_14 & _T_6 & ~(_active_active0_T[4:0] <= 5'h4)) begin
- $fatal; // @[VAlu.scala 247:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_14 & _T_6 & ~(_active_active0_T[4:0] <= 5'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:247 assert(step <= 4.U)\n"); // @[VAlu.scala 247:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_149 & ~(_active_active0_T[2:0] <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_149 & ~(_active_active0_T[2:0] <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_149 & ~(_active_active0_T[2:0] <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_149 & ~(_active_active0_T[2:0] <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_149 & ~(_active_active0_T[2:0] <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_149 & ~(_active_active0_T[2:0] <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_14 & _T_6 & ~(_step_T_1 <= 5'h4)) begin
- $fatal; // @[VAlu.scala 247:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_14 & _T_6 & ~(_step_T_1 <= 5'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:247 assert(step <= 4.U)\n"); // @[VAlu.scala 247:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_149 & ~(_step_T_1[2:0] <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_149 & ~(_step_T_1[2:0] <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_149 & ~(_step_T_1[2:0] <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_149 & ~(_step_T_1[2:0] <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_149 & ~(_step_T_1[2:0] <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_149 & ~(_step_T_1[2:0] <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 118:69]
- active <= 64'h0; // @[VCmdq.scala 123:12]
- end else if (io_in_valid & io_in_ready | _T_9) begin // @[VCmdq.scala 49:23]
- active <= _active_T_36;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 77:43]
- valid <= 1'h0; // @[VCmdq.scala 78:11]
- end else begin
- valid <= f_io_out_valid & f_io_out_ready | _GEN_81;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 77:43]
- step <= 5'h0; // @[VCmdq.scala 80:10]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 81:46]
- step <= 5'h0; // @[VCmdq.scala 82:18 86:12 92:12]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 58:21]
- if (~last) begin
- step <= _step_T_1;
- end else begin
- step <= 5'h0;
- end
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {2{`RANDOM}};
- active = _RAND_0[63:0];
- _RAND_1 = {1{`RANDOM}};
- valid = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- value_tin_op = _RAND_2[6:0];
- _RAND_3 = {1{`RANDOM}};
- value_tin_f2 = _RAND_3[2:0];
- _RAND_4 = {1{`RANDOM}};
- value_tin_sz = _RAND_4[2:0];
- _RAND_5 = {1{`RANDOM}};
- value_tin_vd_addr = _RAND_5[5:0];
- _RAND_6 = {1{`RANDOM}};
- value_tin_ve_addr = _RAND_6[5:0];
- _RAND_7 = {1{`RANDOM}};
- value_tin_vs_valid = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- value_tin_vs_addr = _RAND_8[5:0];
- _RAND_9 = {1{`RANDOM}};
- value_tin_vs_tag = _RAND_9[3:0];
- _RAND_10 = {1{`RANDOM}};
- value_tin_vt_valid = _RAND_10[0:0];
- _RAND_11 = {1{`RANDOM}};
- value_tin_vt_addr = _RAND_11[5:0];
- _RAND_12 = {1{`RANDOM}};
- value_tin_vt_tag = _RAND_12[3:0];
- _RAND_13 = {1{`RANDOM}};
- value_tin_vu_valid = _RAND_13[0:0];
- _RAND_14 = {1{`RANDOM}};
- value_tin_vu_addr = _RAND_14[5:0];
- _RAND_15 = {1{`RANDOM}};
- value_tin_vu_tag = _RAND_15[3:0];
- _RAND_16 = {1{`RANDOM}};
- value_tin_sv_valid = _RAND_16[0:0];
- _RAND_17 = {1{`RANDOM}};
- value_tin_sv_data = _RAND_17[31:0];
- _RAND_18 = {1{`RANDOM}};
- value_tin_cmdsync = _RAND_18[0:0];
- _RAND_19 = {1{`RANDOM}};
- value_m = _RAND_19[0:0];
- _RAND_20 = {1{`RANDOM}};
- step = _RAND_20[4:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- active = 64'h0;
- end
- if (reset) begin
- valid = 1'h0;
- end
- if (reset) begin
- step = 5'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VAluIntLane(
- input clock,
- input reset,
- input io_in_vdvalid,
- input io_in_vevalid,
- input [2:0] io_in_sz,
- input io_in_negative,
- input io_in_round,
- input io_in_signed,
- input io_op_absd,
- input io_op_acc,
- input io_op_dup,
- input io_op_max,
- input io_op_min,
- input io_op_mv,
- input io_op_mv2,
- input io_op_mvp,
- input io_op_srans,
- input io_op_sraqs,
- input io_op_dwinit,
- input io_op_dwconv,
- input io_op_dwconvData,
- input io_op_add_en,
- input io_op_add_add,
- input io_op_add_adds,
- input io_op_add_addw,
- input io_op_add_add3,
- input io_op_add_hadd,
- input io_op_cmp_en,
- input io_op_cmp_eq,
- input io_op_cmp_ne,
- input io_op_cmp_lt,
- input io_op_cmp_le,
- input io_op_cmp_gt,
- input io_op_cmp_ge,
- input io_op_log_en,
- input io_op_log_and,
- input io_op_log_or,
- input io_op_log_xor,
- input io_op_log_not,
- input io_op_log_rev,
- input io_op_log_ror,
- input io_op_log_clb,
- input io_op_log_clz,
- input io_op_log_cpop,
- input io_op_mul0_en,
- input io_op_mul0_dmulh,
- input io_op_mul0_mul,
- input io_op_mul0_mulh,
- input io_op_mul0_muls,
- input io_op_mul0_mulw,
- input io_op_mul0_madd,
- input io_op_mul1_en,
- input io_op_mul1_dmulh,
- input io_op_mul1_mul,
- input io_op_mul1_mulh,
- input io_op_mul1_muls,
- input io_op_padd_en,
- input io_op_padd_add,
- input io_op_padd_sub,
- input io_op_rsub_en,
- input io_op_rsub_rsub,
- input io_op_shf_en_l,
- input io_op_shf_en_r,
- input io_op_shf_shl,
- input io_op_shf_shr,
- input io_op_shf_shf,
- input io_op_sub_en,
- input io_op_sub_sub,
- input io_op_sub_subs,
- input io_op_sub_subw,
- input io_op_sub_hsub,
- input [31:0] io_read_0_data,
- input [31:0] io_read_1_data,
- input [31:0] io_read_2_data,
- input [31:0] io_read_3_data,
- input [31:0] io_read_5_data,
- output [31:0] io_write_0_data,
- output [31:0] io_write_1_data,
- input [31:0] io_load_0,
- input [31:0] io_load_1
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
-`endif // RANDOMIZE_REG_INIT
- wire [31:0] ina_b = io_in_sz[0] ? io_read_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] inb_b = io_in_sz[0] ? io_read_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] inc_b = io_in_sz[0] ? io_read_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] ind_b = io_in_sz[0] ? io_read_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] inf_b = io_in_sz[0] ? io_read_5_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] ina_h = io_in_sz[1] ? io_read_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] inb_h = io_in_sz[1] ? io_read_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] inc_h = io_in_sz[1] ? io_read_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] ina_w = io_in_sz[2] ? io_read_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] inb_w = io_in_sz[2] ? io_read_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] inc_w = io_in_sz[2] ? io_read_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] acc_a = io_op_acc ? ina_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] acc_b = io_op_acc ? inb_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] acc_c = io_op_acc ? inc_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] add_a = io_op_add_en ? ina_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] add_b = io_op_add_en ? inb_b : 32'h0; // @[Library.scala 32:8]
- wire add_r = io_op_add_hadd & io_in_round; // @[VAluInt.scala 923:32]
- wire [31:0] cmp_a = io_op_cmp_en ? ina_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] cmp_b = io_op_cmp_en ? inb_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] log_a = io_op_log_en ? ina_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] log_b = io_op_log_en ? inb_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul0_a = io_op_mul0_en ? ina_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul0_b = io_op_mul0_en ? inb_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul1_a = io_op_mul1_en ? inc_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul1_b = io_op_mul1_en ? inb_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] rsub_a = io_op_rsub_en ? ina_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] rsub_b = io_op_rsub_en ? inb_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shl_a = io_op_shf_en_l ? ina_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shl_b = io_op_shf_en_l ? inb_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shr_a = io_op_shf_en_r ? ina_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shr_b = io_op_shf_en_r ? inb_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] srans_a = io_op_srans ? ina_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] srans_b = io_op_srans ? inb_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] srans_c = io_op_srans ? inc_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sraqs_a = io_op_sraqs ? ina_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sraqs_b = io_op_sraqs ? inb_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sraqs_c = io_op_sraqs ? inc_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sraqs_d = io_op_sraqs ? ind_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sraqs_f = io_op_sraqs ? inf_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sub_a = io_op_sub_en ? ina_b : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sub_b = io_op_sub_en ? inb_b : 32'h0; // @[Library.scala 32:8]
- wire sub_r = io_op_sub_hsub & io_in_round; // @[VAluInt.scala 958:32]
- wire add_sa = add_a[7] & io_in_signed; // @[VAluInt.scala 973:29]
- wire add_sb = add_b[7] & io_in_signed; // @[VAluInt.scala 974:29]
- wire [8:0] _adder_T_2 = {add_sa,add_a[7:0]}; // @[VAluInt.scala 975:44]
- wire [8:0] _adder_T_5 = {add_sb,add_b[7:0]}; // @[VAluInt.scala 975:78]
- wire [9:0] _adder_T_7 = $signed(_adder_T_2) + $signed(_adder_T_5); // @[VAluInt.scala 975:86]
- wire [9:0] _GEN_6 = {{9'd0}, add_r}; // @[VAluInt.scala 975:93]
- wire [9:0] adder = _adder_T_7 + _GEN_6; // @[VAluInt.scala 975:93]
- wire [1:0] sataddmsb = adder[8:7]; // @[VAluInt.scala 976:28]
- wire _sataddsel_T_1 = io_in_signed & sataddmsb == 2'h2; // @[VAluInt.scala 978:21]
- wire _sataddsel_T_3 = io_in_signed & sataddmsb == 2'h1; // @[VAluInt.scala 979:21]
- wire _sataddsel_T_4 = ~io_in_signed; // @[VAluInt.scala 980:13]
- wire _sataddsel_T_6 = ~io_in_signed & sataddmsb[1]; // @[VAluInt.scala 980:21]
- wire [2:0] sataddsel = {_sataddsel_T_1,_sataddsel_T_3,_sataddsel_T_6}; // @[Cat.scala 31:58]
- wire [1:0] _T_3 = sataddsel[1] + sataddsel[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_7 = {{1'd0}, sataddsel[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_5 = _GEN_7 + _T_3; // @[Bitwise.scala 48:55]
- wire _T_9 = ~reset; // @[VAluInt.scala 981:13]
- wire sub_sa = sub_a[7] & io_in_signed; // @[VAluInt.scala 983:29]
- wire sub_sb = sub_b[7] & io_in_signed; // @[VAluInt.scala 984:29]
- wire [8:0] _subtr_T_2 = {sub_sa,sub_a[7:0]}; // @[VAluInt.scala 985:44]
- wire [8:0] _subtr_T_5 = {sub_sb,sub_b[7:0]}; // @[VAluInt.scala 985:78]
- wire [9:0] _subtr_T_7 = $signed(_subtr_T_2) - $signed(_subtr_T_5); // @[VAluInt.scala 985:86]
- wire [9:0] _GEN_8 = {{9'd0}, sub_r}; // @[VAluInt.scala 985:93]
- wire [9:0] subtr = _subtr_T_7 + _GEN_8; // @[VAluInt.scala 985:93]
- wire [1:0] satsubmsb = subtr[8:7]; // @[VAluInt.scala 986:28]
- wire _satsubsel_T_1 = io_in_signed & satsubmsb == 2'h2; // @[VAluInt.scala 988:21]
- wire _satsubsel_T_3 = io_in_signed & satsubmsb == 2'h1; // @[VAluInt.scala 989:21]
- wire _satsubsel_T_6 = _sataddsel_T_4 & satsubmsb[1]; // @[VAluInt.scala 990:21]
- wire [2:0] satsubsel = {_satsubsel_T_1,_satsubsel_T_3,_satsubsel_T_6}; // @[Cat.scala 31:58]
- wire [1:0] _T_14 = satsubsel[1] + satsubsel[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_9 = {{1'd0}, satsubsel[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_16 = _GEN_9 + _T_14; // @[Bitwise.scala 48:55]
- wire [7:0] rsubtr = rsub_b[7:0] - rsub_a[7:0]; // @[VAluInt.scala 993:32]
- wire xeq = cmp_a[7:0] == cmp_b[7:0]; // @[VAluInt.scala 995:28]
- wire xne = cmp_a[7:0] != cmp_b[7:0]; // @[VAluInt.scala 996:28]
- wire [7:0] _slt_T_1 = cmp_a[7:0]; // @[VAluInt.scala 997:34]
- wire [7:0] _slt_T_3 = cmp_b[7:0]; // @[VAluInt.scala 997:56]
- wire slt = $signed(_slt_T_1) < $signed(_slt_T_3); // @[VAluInt.scala 997:37]
- wire ult = cmp_a[7:0] < cmp_b[7:0]; // @[VAluInt.scala 998:28]
- wire sle = slt | xeq; // @[VAluInt.scala 999:21]
- wire ule = ult | xeq; // @[VAluInt.scala 1000:21]
- wire sult = io_in_signed ? slt : ult; // @[VAluInt.scala 1002:21]
- wire [14:0] _GEN_0 = {{7'd0}, shl_a[7:0]}; // @[VAluInt.scala 1062:29]
- wire [14:0] _shl_T_2 = _GEN_0 << shl_b[2:0]; // @[VAluInt.scala 1062:29]
- wire [7:0] shl = _shl_T_2[7:0]; // @[VAluInt.scala 1062:49]
- wire [3:0] _GEN_10 = {{1'd0}, shl_b[2:0]}; // @[VAluInt.scala 1063:40]
- wire [3:0] _sln_T_3 = 4'h8 - _GEN_10; // @[VAluInt.scala 1063:40]
- wire [22:0] _GEN_2 = {{15'd0}, shl_a[7:0]}; // @[VAluInt.scala 1063:29]
- wire [22:0] _sln_T_4 = _GEN_2 << _sln_T_3; // @[VAluInt.scala 1063:29]
- wire [14:0] sln = _sln_T_4[14:0]; // @[VAluInt.scala 1063:60]
- wire [7:0] srl = shr_a[7:0] >> shr_b[2:0]; // @[VAluInt.scala 1064:28]
- wire [2:0] _srs_T_4 = 3'h7 - shr_b[2:0]; // @[VAluInt.scala 1065:66]
- wire [14:0] _srs_T_5 = 15'hff << _srs_T_4; // @[VAluInt.scala 1065:49]
- wire [7:0] srs = shr_a[7] ? _srs_T_5[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] sra = srs | srl; // @[VAluInt.scala 1066:21]
- wire [7:0] shf_slnsz = sln[7:0]; // @[VAluInt.scala 1010:24]
- wire shf_input_neg = shl_a[7]; // @[VAluInt.scala 1011:26]
- wire shf_input_zero = shl_a[7:0] == 8'h0; // @[VAluInt.scala 1012:28]
- wire shf_shamt_neg = shl_b[7]; // @[VAluInt.scala 1013:26]
- wire [7:0] _shf_shamt_negsat_T = shl_b[7:0]; // @[VAluInt.scala 1017:32]
- wire shf_shamt_negsat = $signed(_shf_shamt_negsat_T) <= -8'sh7; // @[VAluInt.scala 1017:39]
- wire shf_shamt_possat = $signed(_shf_shamt_negsat_T) >= 8'sh7; // @[VAluInt.scala 1018:39]
- wire [2:0] _shf_signb_T_3 = shl_b[2:0] - 3'h1; // @[VAluInt.scala 1019:65]
- wire [7:0] shf_signb = 8'hff >> _shf_signb_T_3; // @[VAluInt.scala 1019:36]
- wire _shf_possat_T_6 = ~shf_input_zero; // @[VAluInt.scala 1020:112]
- wire shf_possat = shf_shamt_neg & ~shf_input_neg & (shf_shamt_negsat | sln[14:7] != 8'h0) & ~shf_input_zero; // @[VAluInt.scala 1020:109]
- wire shf_negsat = shf_shamt_neg & shf_input_neg & (shf_shamt_negsat | sln[14:7] != shf_signb); // @[VAluInt.scala 1021:48]
- wire _shf_rs_T = ~shf_shamt_neg; // @[VAluInt.scala 1028:23]
- wire _shf_rs_T_2 = ~shf_shamt_neg & ~shf_shamt_possat; // @[VAluInt.scala 1028:34]
- wire [7:0] _shf_rs_T_3 = _shf_rs_T_2 ? sra : 8'h0; // @[Library.scala 32:8]
- wire _shf_rs_T_6 = _shf_rs_T & shf_shamt_possat & shf_input_neg; // @[VAluInt.scala 1029:51]
- wire [7:0] _shf_rs_T_8 = _shf_rs_T_6 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_rs_T_9 = _shf_rs_T_3 | _shf_rs_T_8; // @[VAluInt.scala 1028:57]
- wire _shf_rs_T_13 = shf_shamt_neg & ~shf_possat & ~shf_negsat; // @[VAluInt.scala 1030:45]
- wire [7:0] _shf_rs_T_14 = _shf_rs_T_13 ? shf_slnsz : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_rs_T_15 = _shf_rs_T_9 | _shf_rs_T_14; // @[VAluInt.scala 1029:79]
- wire _shf_rs_T_16 = shf_shamt_neg & shf_possat; // @[VAluInt.scala 1031:34]
- wire [7:0] _shf_rs_T_17 = _shf_rs_T_16 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_rs_T_18 = _shf_rs_T_15 | _shf_rs_T_17; // @[VAluInt.scala 1030:64]
- wire _shf_rs_T_19 = shf_shamt_neg & shf_negsat; // @[VAluInt.scala 1032:34]
- wire [7:0] _shf_rs_T_20 = _shf_rs_T_19 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] shf_rs = _shf_rs_T_18 | _shf_rs_T_20; // @[VAluInt.scala 1031:53]
- wire [4:0] _shf_shamt_negsat_T_4 = 5'sh0 - 5'sh8; // @[VAluInt.scala 1035:42]
- wire [7:0] _GEN_11 = {{3{_shf_shamt_negsat_T_4[4]}},_shf_shamt_negsat_T_4}; // @[VAluInt.scala 1035:39]
- wire shf_shamt_negsat_1 = $signed(_shf_shamt_negsat_T) <= $signed(_GEN_11); // @[VAluInt.scala 1035:39]
- wire shf_shamt_possat_1 = $signed(_shf_shamt_negsat_T) >= 8'sh8; // @[VAluInt.scala 1036:39]
- wire shf_possat_1 = shf_shamt_neg & (shf_shamt_negsat_1 | sln[14:8] != 7'h0) & _shf_possat_T_6; // @[VAluInt.scala 1037:89]
- wire _shf_ru_T_2 = _shf_rs_T & ~shf_shamt_possat_1; // @[VAluInt.scala 1041:34]
- wire [7:0] _shf_ru_T_3 = _shf_ru_T_2 ? srl : 8'h0; // @[Library.scala 32:8]
- wire _shf_ru_T_5 = shf_shamt_neg & ~shf_possat_1; // @[VAluInt.scala 1042:34]
- wire [7:0] _shf_ru_T_6 = _shf_ru_T_5 ? shf_slnsz : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_ru_T_7 = _shf_ru_T_3 | _shf_ru_T_6; // @[VAluInt.scala 1041:57]
- wire _shf_ru_T_8 = shf_shamt_neg & shf_possat_1; // @[VAluInt.scala 1043:34]
- wire [7:0] _shf_ru_T_9 = _shf_ru_T_8 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] shf_ru = _shf_ru_T_7 | _shf_ru_T_9; // @[VAluInt.scala 1042:53]
- wire [7:0] shf = io_in_signed ? shf_rs : shf_ru; // @[VAluInt.scala 1045:12]
- wire [7:0] shr = io_in_signed ? sra : srl; // @[VAluInt.scala 1068:20]
- wire shf_rnd_shamt_zero = shl_b[7:0] == 8'h0; // @[VAluInt.scala 1053:28]
- wire [7:0] _shf_rnd_rbit_T_2 = {shl_a[6:0],shf_input_neg}; // @[Cat.scala 31:58]
- wire [7:0] _shf_rnd_rbit_T_4 = _shf_rnd_rbit_T_2 >> shl_b[2:0]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_rbit = _shf_rnd_rbit_T_4[0]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_shamt_possat = io_in_signed ? shf_shamt_possat_1 : $signed(_shf_shamt_negsat_T) > 8'sh8; // @[VAluInt.scala 1055:31]
- wire _shf_rnd_r_T_5 = io_in_round & ~shf_rnd_shamt_possat & _shf_rs_T & ~shf_rnd_shamt_zero; // @[VAluInt.scala 1056:60]
- wire _shf_rnd_r_T_6 = _shf_rnd_r_T_5 & shf_rnd_rbit; // @[Library.scala 36:8]
- wire _shf_rnd_r_T_9 = io_in_round & shf_rnd_shamt_possat & shf_input_neg & io_in_signed; // @[VAluInt.scala 1057:59]
- wire shf_rnd = _shf_rnd_r_T_6 | _shf_rnd_r_T_9; // @[VAluInt.scala 1056:82]
- wire _mul0_as_T_1 = io_in_signed & mul0_a[7]; // @[VAluInt.scala 1199:32]
- wire _mul0_bs_T_1 = io_in_signed & mul0_b[7]; // @[VAluInt.scala 1200:32]
- wire mul0_sign = mul0_a[7] != mul0_b[7] & mul0_a[7:0] != 8'h0 & mul0_b[7:0] != 8'h0; // @[VAluInt.scala 1201:70]
- wire [8:0] _prod0_T = {_mul0_as_T_1,mul0_a[7:0]}; // @[VAluInt.scala 1202:28]
- wire [8:0] _prod0_T_1 = {_mul0_bs_T_1,mul0_b[7:0]}; // @[VAluInt.scala 1202:45]
- wire [17:0] prod0 = $signed(_prod0_T) * $signed(_prod0_T_1); // @[VAluInt.scala 1202:53]
- wire [7:0] prodh0 = prod0[15:8]; // @[VAluInt.scala 1203:25]
- wire [7:0] proddh0 = prod0[14:7]; // @[VAluInt.scala 1204:26]
- wire _mul1_as_T_1 = io_in_signed & mul1_a[7]; // @[VAluInt.scala 1206:32]
- wire _mul1_bs_T_1 = io_in_signed & mul1_b[7]; // @[VAluInt.scala 1207:32]
- wire mul1_sign = mul1_a[7] != mul1_b[7] & mul1_a[7:0] != 8'h0 & mul1_b[7:0] != 8'h0; // @[VAluInt.scala 1208:70]
- wire [8:0] _prod1_T = {_mul1_as_T_1,mul1_a[7:0]}; // @[VAluInt.scala 1209:28]
- wire [8:0] _prod1_T_1 = {_mul1_bs_T_1,mul1_b[7:0]}; // @[VAluInt.scala 1209:45]
- wire [17:0] prod1 = $signed(_prod1_T) * $signed(_prod1_T_1); // @[VAluInt.scala 1209:53]
- wire [7:0] prodh1 = prod1[15:8]; // @[VAluInt.scala 1210:25]
- wire [7:0] proddh1 = prod1[14:7]; // @[VAluInt.scala 1211:26]
- wire _muls0_umax_T_1 = prodh0 != 8'h0; // @[VAluInt.scala 1213:42]
- wire muls0_umax = _sataddsel_T_4 & prodh0 != 8'h0; // @[VAluInt.scala 1213:32]
- wire muls0_smax = io_in_signed & ~mul0_sign & (prod0[7] | _muls0_umax_T_1); // @[VAluInt.scala 1214:46]
- wire muls0_smin = io_in_signed & mul0_sign & (~prod0[7] | prodh0 != 8'hff); // @[VAluInt.scala 1215:46]
- wire muls0_base = ~(muls0_umax | muls0_smax | muls0_smin); // @[VAluInt.scala 1216:24]
- wire [3:0] _T_22 = {muls0_umax,muls0_smax,muls0_smin,muls0_base}; // @[Cat.scala 31:58]
- wire [1:0] _T_27 = _T_22[0] + _T_22[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_29 = _T_22[2] + _T_22[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_31 = _T_27 + _T_29; // @[Bitwise.scala 48:55]
- wire _muls1_umax_T_1 = prodh1 != 8'h0; // @[VAluInt.scala 1219:42]
- wire muls1_umax = _sataddsel_T_4 & prodh1 != 8'h0; // @[VAluInt.scala 1219:32]
- wire muls1_smax = io_in_signed & ~mul1_sign & (prod1[7] | _muls1_umax_T_1); // @[VAluInt.scala 1220:46]
- wire muls1_smin = io_in_signed & mul1_sign & (~prod1[7] | prodh1 != 8'hff); // @[VAluInt.scala 1221:46]
- wire muls1_base = ~(muls1_umax | muls1_smax | muls1_smin); // @[VAluInt.scala 1222:24]
- wire [3:0] _T_37 = {muls1_umax,muls1_smax,muls1_smin,muls1_base}; // @[Cat.scala 31:58]
- wire [1:0] _T_42 = _T_37[0] + _T_37[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_44 = _T_37[2] + _T_37[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_46 = _T_42 + _T_44; // @[Bitwise.scala 48:55]
- wire dmulh0_possat = mul0_a[7:0] == 8'h80 & mul0_b[7:0] == 8'h80; // @[VAluInt.scala 1227:50]
- wire dmulh1_possat = mul1_a[7:0] == 8'h80 & mul1_b[7:0] == 8'h80; // @[VAluInt.scala 1229:50]
- wire _dmulh0_T = ~dmulh0_possat; // @[VAluInt.scala 1231:26]
- wire [7:0] _dmulh0_T_1 = _dmulh0_T ? proddh0 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh0_T_4 = dmulh0_possat ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] dmulh0 = _dmulh0_T_1 | _dmulh0_T_4; // @[VAluInt.scala 1231:51]
- wire _dmulh1_T = ~dmulh1_possat; // @[VAluInt.scala 1234:26]
- wire [7:0] _dmulh1_T_1 = _dmulh1_T ? proddh1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh1_T_4 = dmulh1_possat ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] dmulh1 = _dmulh1_T_1 | _dmulh1_T_4; // @[VAluInt.scala 1234:51]
- wire [7:0] _muls0_T_1 = muls0_umax ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [6:0] _muls0_T_3 = muls0_smax ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_12 = {{1'd0}, _muls0_T_3}; // @[VAluInt.scala 1240:51]
- wire [7:0] _muls0_T_4 = _muls0_T_1 | _GEN_12; // @[VAluInt.scala 1240:51]
- wire [7:0] _muls0_T_6 = muls0_smin ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _muls0_T_7 = _muls0_T_4 | _muls0_T_6; // @[VAluInt.scala 1241:57]
- wire [7:0] _muls0_T_9 = muls0_base ? prod0[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] muls0 = _muls0_T_7 | _muls0_T_9; // @[VAluInt.scala 1242:71]
- wire [7:0] _muls1_T_1 = muls1_umax ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [6:0] _muls1_T_3 = muls1_smax ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_13 = {{1'd0}, _muls1_T_3}; // @[VAluInt.scala 1245:51]
- wire [7:0] _muls1_T_4 = _muls1_T_1 | _GEN_13; // @[VAluInt.scala 1245:51]
- wire [7:0] _muls1_T_6 = muls1_smin ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _muls1_T_7 = _muls1_T_4 | _muls1_T_6; // @[VAluInt.scala 1246:57]
- wire [7:0] _muls1_T_9 = muls1_base ? prod1[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] muls1 = _muls1_T_7 | _muls1_T_9; // @[VAluInt.scala 1247:71]
- wire _dmulh0_rnd_T_4 = io_in_round & io_op_mul0_dmulh & io_in_sz[0] & _dmulh0_T; // @[VAluInt.scala 1250:72]
- wire _dmulh0_rnd_T_7 = ~prod0[6]; // @[VAluInt.scala 1252:40]
- wire [7:0] _dmulh0_rnd_T_9 = _dmulh0_rnd_T_7 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh0_rnd_T_11 = prod0[6] ? 8'h1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh0_rnd_T_12 = io_in_negative & mul0_sign ? _dmulh0_rnd_T_9 : _dmulh0_rnd_T_11; // @[VAluInt.scala 1251:33]
- wire [7:0] dmulh0_rnd = _dmulh0_rnd_T_4 ? _dmulh0_rnd_T_12 : 8'h0; // @[Library.scala 32:8]
- wire _dmulh1_rnd_T_4 = io_in_round & io_op_mul1_dmulh & io_in_sz[0] & _dmulh1_T; // @[VAluInt.scala 1255:72]
- wire _dmulh1_rnd_T_7 = ~prod1[6]; // @[VAluInt.scala 1257:40]
- wire [7:0] _dmulh1_rnd_T_9 = _dmulh1_rnd_T_7 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh1_rnd_T_11 = prod1[6] ? 8'h1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh1_rnd_T_12 = io_in_negative & mul1_sign ? _dmulh1_rnd_T_9 : _dmulh1_rnd_T_11; // @[VAluInt.scala 1256:33]
- wire [7:0] dmulh1_rnd = _dmulh1_rnd_T_4 ? _dmulh1_rnd_T_12 : 8'h0; // @[Library.scala 32:8]
- wire mulh0_rnd = io_in_round & io_op_mul0_mulh & prod0[7]; // @[VAluInt.scala 1260:48]
- wire mulh1_rnd = io_in_round & io_op_mul1_mulh & prod1[7]; // @[VAluInt.scala 1261:48]
- wire [7:0] _absd_T_1 = sult ? rsubtr : subtr[7:0]; // @[VAluInt.scala 1265:39]
- wire [7:0] absd = io_op_absd ? _absd_T_1 : 8'h0; // @[Library.scala 32:8]
- wire _acc_T_2 = io_in_signed & acc_b[7]; // @[VAluInt.scala 1270:55]
- wire [8:0] _acc_T_4 = {_acc_T_2,acc_b[7:0]}; // @[Cat.scala 31:58]
- wire acc_r_r__2 = _acc_T_4[8]; // @[Library.scala 64:25]
- wire [15:0] acc_r = {acc_r_r__2,acc_r_r__2,acc_r_r__2,acc_r_r__2,acc_r_r__2,acc_r_r__2,acc_r_r__2,_acc_T_2,acc_b[7:0]}
- ; // @[Cat.scala 31:58]
- wire [15:0] acc = acc_a[15:0] + acc_r; // @[VAluInt.scala 1270:34]
- wire _add_T_1 = sataddsel[2] & io_op_add_adds; // @[VAluInt.scala 1279:36]
- wire [7:0] _add_T_3 = _add_T_1 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire _add_T_5 = sataddsel[1] & io_op_add_adds; // @[VAluInt.scala 1280:36]
- wire [6:0] _add_T_7 = _add_T_5 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_14 = {{1'd0}, _add_T_7}; // @[VAluInt.scala 1279:89]
- wire [7:0] _add_T_8 = _add_T_3 | _GEN_14; // @[VAluInt.scala 1279:89]
- wire _add_T_10 = sataddsel[0] & io_op_add_adds; // @[VAluInt.scala 1281:36]
- wire [7:0] _add_T_12 = _add_T_10 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _add_T_13 = _add_T_8 | _add_T_12; // @[VAluInt.scala 1280:75]
- wire _add_T_17 = sataddsel == 3'h0 & io_op_add_adds | io_op_add_add | io_op_add_add3; // @[VAluInt.scala 1282:76]
- wire [7:0] _add_T_19 = _add_T_17 ? adder[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _add_T_20 = _add_T_13 | _add_T_19; // @[VAluInt.scala 1281:69]
- wire [7:0] _add_T_22 = io_op_add_hadd ? adder[8:1] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] add = _add_T_20 | _add_T_22; // @[VAluInt.scala 1282:115]
- wire addw_r_r__2 = adder[9]; // @[Library.scala 64:25]
- wire [15:0] addw_r = {addw_r_r__2,addw_r_r__2,addw_r_r__2,addw_r_r__2,addw_r_r__2,addw_r_r__2,adder}; // @[Cat.scala 31:58]
- wire [15:0] addw = io_op_add_addw ? addw_r : 16'h0; // @[Library.scala 32:8]
- wire [7:0] dup = io_op_dup ? io_read_1_data[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _max_T_2 = sult ? cmp_b[7:0] : cmp_a[7:0]; // @[VAluInt.scala 1290:37]
- wire [7:0] max = io_op_max ? _max_T_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _min_T_2 = sult ? cmp_a[7:0] : cmp_b[7:0]; // @[VAluInt.scala 1291:37]
- wire [7:0] min = io_op_min ? _min_T_2 : 8'h0; // @[Library.scala 32:8]
- wire _mul0_T = io_op_mul0_mul | io_op_mul0_madd; // @[VAluInt.scala 1293:39]
- wire [7:0] _mul0_T_2 = _mul0_T ? prod0[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_3 = io_op_mul0_dmulh ? dmulh0 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_4 = _mul0_T_2 | _mul0_T_3; // @[VAluInt.scala 1293:79]
- wire [7:0] _mul0_T_5 = io_op_mul0_mulh ? prodh0 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_6 = _mul0_T_4 | _mul0_T_5; // @[VAluInt.scala 1294:50]
- wire [7:0] _mul0_T_7 = io_op_mul0_muls ? muls0 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] mul0 = _mul0_T_6 | _mul0_T_7; // @[VAluInt.scala 1295:48]
- wire [7:0] _mul1_T_1 = io_op_mul1_mul ? prod1[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul1_T_2 = io_op_mul1_dmulh ? dmulh1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul1_T_3 = _mul1_T_1 | _mul1_T_2; // @[VAluInt.scala 1298:60]
- wire [7:0] _mul1_T_4 = io_op_mul1_mulh ? prodh1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul1_T_5 = _mul1_T_3 | _mul1_T_4; // @[VAluInt.scala 1299:50]
- wire [7:0] _mul1_T_6 = io_op_mul1_muls ? muls1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] mul1 = _mul1_T_5 | _mul1_T_6; // @[VAluInt.scala 1300:48]
- wire [15:0] mulw = io_op_mul0_mulw ? prod0[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [7:0] rsub = io_op_rsub_rsub ? rsubtr : 8'h0; // @[Library.scala 32:8]
- wire [3:0] srans_shamt = srans_b[3:0]; // @[VAluInt.scala 1084:22]
- wire [15:0] srans_srl = srans_a[15:0] >> srans_shamt; // @[VAluInt.scala 1085:21]
- wire _srans_srs_T_1 = srans_a[15] & io_in_signed; // @[VAluInt.scala 1088:41]
- wire [3:0] _srans_srs_T_4 = 4'hf - srans_shamt; // @[VAluInt.scala 1089:68]
- wire [30:0] _srans_srs_T_5 = 31'hffff << _srans_srs_T_4; // @[VAluInt.scala 1089:47]
- wire [15:0] srans_srs = _srans_srs_T_1 ? _srans_srs_T_5[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] srans_sra = srans_srs | srans_srl; // @[VAluInt.scala 1090:23]
- wire [15:0] _srans_rbit_T_1 = {srans_a[14:0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] _srans_rbit_T_2 = _srans_rbit_T_1 >> srans_shamt; // @[VAluInt.scala 1093:53]
- wire srans_rbit = _srans_rbit_T_2[0]; // @[VAluInt.scala 1093:53]
- wire [15:0] srans_smin = 16'sh0 - 16'sh80; // @[VAluInt.scala 1098:20]
- wire [15:0] _srans_rshf_T_2 = srans_sra + 16'h1; // @[VAluInt.scala 1099:43]
- wire [15:0] srans_rshf = io_in_round & srans_rbit ? _srans_rshf_T_2 : srans_sra; // @[VAluInt.scala 1099:23]
- wire srans_is_umax = _sataddsel_T_4 & srans_rshf > 16'hff; // @[VAluInt.scala 1101:31]
- wire [15:0] _srans_is_smax_T = io_in_round & srans_rbit ? _srans_rshf_T_2 : srans_sra; // @[VAluInt.scala 1103:40]
- wire srans_is_smax = io_in_signed & $signed(_srans_is_smax_T) > 16'sh7f; // @[VAluInt.scala 1103:31]
- wire srans_is_smin = io_in_signed & $signed(_srans_is_smax_T) < $signed(srans_smin); // @[VAluInt.scala 1104:31]
- wire srans_is_norm = ~(srans_is_umax | srans_is_smax | srans_is_smin); // @[VAluInt.scala 1105:23]
- wire [3:0] _srans_T_2 = {srans_is_umax,srans_is_smax,srans_is_smin,srans_is_norm}; // @[Cat.scala 31:58]
- wire [1:0] _srans_T_7 = _srans_T_2[0] + _srans_T_2[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _srans_T_9 = _srans_T_2[2] + _srans_T_2[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _srans_T_11 = _srans_T_7 + _srans_T_9; // @[Bitwise.scala 48:55]
- wire [7:0] _srans_r_T = srans_is_umax ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _srans_r_T_3 = srans_is_smax ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _srans_r_T_4 = _srans_r_T | _srans_r_T_3; // @[VAluInt.scala 1108:58]
- wire [15:0] _srans_r_T_5 = 16'sh0 - 16'sh80; // @[VAluInt.scala 1110:37]
- wire [7:0] _srans_r_T_7 = srans_is_smin ? _srans_r_T_5[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _srans_r_T_8 = _srans_r_T_4 | _srans_r_T_7; // @[VAluInt.scala 1109:58]
- wire [7:0] _srans_r_T_10 = srans_is_norm ? srans_rshf[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] srans = _srans_r_T_8 | _srans_r_T_10; // @[VAluInt.scala 1110:58]
- wire [4:0] sraqs_shamt = sraqs_b[4:0]; // @[VAluInt.scala 1084:22]
- wire [31:0] sraqs_srl = sraqs_a >> sraqs_shamt; // @[VAluInt.scala 1085:21]
- wire _sraqs_srs_T_1 = sraqs_a[31] & io_in_signed; // @[VAluInt.scala 1088:41]
- wire [4:0] _sraqs_srs_T_4 = 5'h1f - sraqs_shamt; // @[VAluInt.scala 1089:68]
- wire [62:0] _sraqs_srs_T_5 = 63'hffffffff << _sraqs_srs_T_4; // @[VAluInt.scala 1089:47]
- wire [31:0] sraqs_srs = _sraqs_srs_T_1 ? _sraqs_srs_T_5[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sraqs_sra = sraqs_srs | sraqs_srl; // @[VAluInt.scala 1090:23]
- wire [31:0] _sraqs_rbit_T_1 = {sraqs_a[30:0],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] _sraqs_rbit_T_2 = _sraqs_rbit_T_1 >> sraqs_shamt; // @[VAluInt.scala 1093:53]
- wire sraqs_rbit = _sraqs_rbit_T_2[0]; // @[VAluInt.scala 1093:53]
- wire [31:0] sraqs_smin = 32'sh0 - 32'sh80; // @[VAluInt.scala 1098:20]
- wire [31:0] _sraqs_rshf_T_2 = sraqs_sra + 32'h1; // @[VAluInt.scala 1099:43]
- wire [31:0] sraqs_rshf = io_in_round & sraqs_rbit ? _sraqs_rshf_T_2 : sraqs_sra; // @[VAluInt.scala 1099:23]
- wire sraqs_is_umax = _sataddsel_T_4 & sraqs_rshf > 32'hff; // @[VAluInt.scala 1101:31]
- wire [31:0] _sraqs_is_smax_T = io_in_round & sraqs_rbit ? _sraqs_rshf_T_2 : sraqs_sra; // @[VAluInt.scala 1103:40]
- wire sraqs_is_smax = io_in_signed & $signed(_sraqs_is_smax_T) > 32'sh7f; // @[VAluInt.scala 1103:31]
- wire sraqs_is_smin = io_in_signed & $signed(_sraqs_is_smax_T) < $signed(sraqs_smin); // @[VAluInt.scala 1104:31]
- wire sraqs_is_norm = ~(sraqs_is_umax | sraqs_is_smax | sraqs_is_smin); // @[VAluInt.scala 1105:23]
- wire [3:0] _sraqs_T_2 = {sraqs_is_umax,sraqs_is_smax,sraqs_is_smin,sraqs_is_norm}; // @[Cat.scala 31:58]
- wire [1:0] _sraqs_T_7 = _sraqs_T_2[0] + _sraqs_T_2[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _sraqs_T_9 = _sraqs_T_2[2] + _sraqs_T_2[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _sraqs_T_11 = _sraqs_T_7 + _sraqs_T_9; // @[Bitwise.scala 48:55]
- wire [7:0] _sraqs_r_T = sraqs_is_umax ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sraqs_r_T_3 = sraqs_is_smax ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sraqs_r_T_4 = _sraqs_r_T | _sraqs_r_T_3; // @[VAluInt.scala 1108:58]
- wire [31:0] _sraqs_r_T_5 = 32'sh0 - 32'sh80; // @[VAluInt.scala 1110:37]
- wire [7:0] _sraqs_r_T_7 = sraqs_is_smin ? _sraqs_r_T_5[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sraqs_r_T_8 = _sraqs_r_T_4 | _sraqs_r_T_7; // @[VAluInt.scala 1109:58]
- wire [7:0] _sraqs_r_T_10 = sraqs_is_norm ? sraqs_rshf[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] sraqs = _sraqs_r_T_8 | _sraqs_r_T_10; // @[VAluInt.scala 1110:58]
- wire _sub_T_1 = satsubsel[2] & io_op_sub_subs; // @[VAluInt.scala 1348:36]
- wire [7:0] _sub_T_3 = _sub_T_1 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire _sub_T_5 = satsubsel[1] & io_op_sub_subs; // @[VAluInt.scala 1349:36]
- wire [6:0] _sub_T_7 = _sub_T_5 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_15 = {{1'd0}, _sub_T_7}; // @[VAluInt.scala 1348:89]
- wire [7:0] _sub_T_8 = _sub_T_3 | _GEN_15; // @[VAluInt.scala 1348:89]
- wire _sub_T_15 = satsubsel == 3'h0 & io_op_sub_subs | io_op_sub_sub; // @[VAluInt.scala 1351:59]
- wire [7:0] _sub_T_17 = _sub_T_15 ? subtr[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sub_T_18 = _sub_T_8 | _sub_T_17; // @[VAluInt.scala 1350:68]
- wire [7:0] _sub_T_20 = io_op_sub_hsub ? subtr[8:1] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] sub = _sub_T_18 | _sub_T_20; // @[VAluInt.scala 1351:97]
- wire subw_r_r__2 = subtr[9]; // @[Library.scala 64:25]
- wire [15:0] subw_r = {subw_r_r__2,subw_r_r__2,subw_r_r__2,subw_r_r__2,subw_r_r__2,subw_r_r__2,subtr}; // @[Cat.scala 31:58]
- wire [15:0] subw = io_op_sub_subw ? subw_r : 16'h0; // @[Library.scala 32:8]
- wire _cmp_T_1 = io_op_cmp_eq & xeq; // @[Library.scala 36:8]
- wire _cmp_T_2 = io_op_cmp_ne & xne; // @[Library.scala 36:8]
- wire _cmp_T_3 = _cmp_T_1 | _cmp_T_2; // @[VAluInt.scala 1358:45]
- wire _cmp_T_4 = io_op_cmp_lt & io_in_signed; // @[VAluInt.scala 1360:39]
- wire _cmp_T_5 = _cmp_T_4 & slt; // @[Library.scala 36:8]
- wire _cmp_T_6 = _cmp_T_3 | _cmp_T_5; // @[VAluInt.scala 1359:45]
- wire _cmp_T_8 = io_op_cmp_lt & _sataddsel_T_4; // @[VAluInt.scala 1361:39]
- wire _cmp_T_9 = _cmp_T_8 & ult; // @[Library.scala 36:8]
- wire _cmp_T_10 = _cmp_T_6 | _cmp_T_9; // @[VAluInt.scala 1360:56]
- wire _cmp_T_11 = io_op_cmp_le & io_in_signed; // @[VAluInt.scala 1362:39]
- wire _cmp_T_12 = _cmp_T_11 & sle; // @[Library.scala 36:8]
- wire _cmp_T_13 = _cmp_T_10 | _cmp_T_12; // @[VAluInt.scala 1361:56]
- wire _cmp_T_15 = io_op_cmp_le & _sataddsel_T_4; // @[VAluInt.scala 1363:39]
- wire _cmp_T_16 = _cmp_T_15 & ule; // @[Library.scala 36:8]
- wire _cmp_T_17 = _cmp_T_13 | _cmp_T_16; // @[VAluInt.scala 1362:56]
- wire _cmp_T_18 = io_op_cmp_gt & io_in_signed; // @[VAluInt.scala 1364:39]
- wire _cmp_T_19 = ~sle; // @[VAluInt.scala 1364:51]
- wire _cmp_T_20 = _cmp_T_18 & _cmp_T_19; // @[Library.scala 36:8]
- wire _cmp_T_21 = _cmp_T_17 | _cmp_T_20; // @[VAluInt.scala 1363:56]
- wire _cmp_T_23 = io_op_cmp_gt & _sataddsel_T_4; // @[VAluInt.scala 1365:39]
- wire _cmp_T_24 = ~ule; // @[VAluInt.scala 1365:51]
- wire _cmp_T_25 = _cmp_T_23 & _cmp_T_24; // @[Library.scala 36:8]
- wire _cmp_T_26 = _cmp_T_21 | _cmp_T_25; // @[VAluInt.scala 1364:57]
- wire _cmp_T_27 = io_op_cmp_ge & io_in_signed; // @[VAluInt.scala 1366:39]
- wire _cmp_T_28 = ~slt; // @[VAluInt.scala 1366:51]
- wire _cmp_T_29 = _cmp_T_27 & _cmp_T_28; // @[Library.scala 36:8]
- wire _cmp_T_30 = _cmp_T_26 | _cmp_T_29; // @[VAluInt.scala 1365:57]
- wire _cmp_T_32 = io_op_cmp_ge & _sataddsel_T_4; // @[VAluInt.scala 1367:39]
- wire _cmp_T_33 = ~ult; // @[VAluInt.scala 1367:51]
- wire _cmp_T_34 = _cmp_T_32 & _cmp_T_33; // @[Library.scala 36:8]
- wire _cmp_T_35 = _cmp_T_30 | _cmp_T_34; // @[VAluInt.scala 1366:57]
- wire cmp = io_in_sz[0] & _cmp_T_35; // @[VAluInt.scala 1357:30]
- wire [7:0] _log_T_2 = log_a[7:0] & log_b[7:0]; // @[VAluInt.scala 1371:42]
- wire [7:0] _log_T_3 = io_op_log_and ? _log_T_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_6 = log_a[7:0] | log_b[7:0]; // @[VAluInt.scala 1372:42]
- wire [7:0] _log_T_7 = io_op_log_or ? _log_T_6 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_8 = _log_T_3 | _log_T_7; // @[VAluInt.scala 1371:56]
- wire [7:0] _log_T_11 = log_a[7:0] ^ log_b[7:0]; // @[VAluInt.scala 1373:42]
- wire [7:0] _log_T_12 = io_op_log_xor ? _log_T_11 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_13 = _log_T_8 | _log_T_12; // @[VAluInt.scala 1372:56]
- wire [7:0] _log_T_16 = ~log_a[7:0]; // @[VAluInt.scala 1374:51]
- wire [7:0] _log_T_17 = io_in_sz[0] ? _log_T_16 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_18 = io_op_log_not ? _log_T_17 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_19 = _log_T_13 | _log_T_18; // @[VAluInt.scala 1373:56]
- wire _log_b_T_1 = ~log_b[0]; // @[VAluInt.scala 1151:23]
- wire [7:0] _log_b_T_10 = {log_a[6],log_a[7],log_a[4],log_a[5],log_a[2],log_a[3],log_a[0],log_a[1]}; // @[Cat.scala 31:58]
- wire [7:0] log_b_1 = ~log_b[0] ? log_a[7:0] : _log_b_T_10; // @[VAluInt.scala 1151:22]
- wire _log_c_T_1 = ~log_b[1]; // @[VAluInt.scala 1152:23]
- wire [7:0] _log_c_T_6 = {log_b_1[5:4],log_b_1[7:6],log_b_1[1:0],log_b_1[3:2]}; // @[Cat.scala 31:58]
- wire [7:0] log_c = ~log_b[1] ? log_b_1 : _log_c_T_6; // @[VAluInt.scala 1152:22]
- wire _log_d_T_1 = ~log_b[2]; // @[VAluInt.scala 1153:23]
- wire [7:0] _log_d_T_4 = {log_c[3:0],log_c[7:4]}; // @[Cat.scala 31:58]
- wire [7:0] log_d = ~log_b[2] ? log_c : _log_d_T_4; // @[VAluInt.scala 1153:22]
- wire [7:0] _log_T_22 = io_op_log_rev ? log_d : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_23 = _log_T_19 | _log_T_22; // @[VAluInt.scala 1374:65]
- wire [7:0] _log_b_T_15 = {log_a[0],log_a[7:1]}; // @[Cat.scala 31:58]
- wire [7:0] log_b_2 = _log_b_T_1 ? log_a[7:0] : _log_b_T_15; // @[VAluInt.scala 1188:22]
- wire [7:0] _log_c_T_11 = {log_b_2[1:0],log_b_2[7:2]}; // @[Cat.scala 31:58]
- wire [7:0] log_c_1 = _log_c_T_1 ? log_b_2 : _log_c_T_11; // @[VAluInt.scala 1189:22]
- wire [7:0] _log_d_T_9 = {log_c_1[3:0],log_c_1[7:4]}; // @[Cat.scala 31:58]
- wire [7:0] log_d_1 = _log_d_T_1 ? log_c_1 : _log_d_T_9; // @[VAluInt.scala 1190:22]
- wire [7:0] _log_T_27 = io_in_sz[0] ? log_d_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_28 = io_op_log_ror ? _log_T_27 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_29 = _log_T_23 | _log_T_28; // @[VAluInt.scala 1375:60]
- wire [7:0] _GEN_16 = {{4'd0}, _log_T_16[7:4]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_4 = _GEN_16 & 8'hf; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_6 = {_log_T_16[3:0], 4'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clo_T_8 = _log_clo_T_6 & 8'hf0; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clo_T_9 = _log_clo_T_4 | _log_clo_T_8; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_17 = {{2'd0}, _log_clo_T_9[7:2]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_14 = _GEN_17 & 8'h33; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_16 = {_log_clo_T_9[5:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clo_T_18 = _log_clo_T_16 & 8'hcc; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clo_T_19 = _log_clo_T_14 | _log_clo_T_18; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_18 = {{1'd0}, _log_clo_T_19[7:1]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_24 = _GEN_18 & 8'h55; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_26 = {_log_clo_T_19[6:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clo_T_28 = _log_clo_T_26 & 8'haa; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clo_T_29 = _log_clo_T_24 | _log_clo_T_28; // @[Bitwise.scala 105:39]
- wire [8:0] _log_clo_T_30 = {1'h1,_log_clo_T_29}; // @[Cat.scala 31:58]
- wire [3:0] _log_clo_T_40 = _log_clo_T_30[7] ? 4'h7 : 4'h8; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_41 = _log_clo_T_30[6] ? 4'h6 : _log_clo_T_40; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_42 = _log_clo_T_30[5] ? 4'h5 : _log_clo_T_41; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_43 = _log_clo_T_30[4] ? 4'h4 : _log_clo_T_42; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_44 = _log_clo_T_30[3] ? 4'h3 : _log_clo_T_43; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_45 = _log_clo_T_30[2] ? 4'h2 : _log_clo_T_44; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_46 = _log_clo_T_30[1] ? 4'h1 : _log_clo_T_45; // @[Mux.scala 47:70]
- wire [3:0] log_clo = _log_clo_T_30[0] ? 4'h0 : _log_clo_T_46; // @[Mux.scala 47:70]
- wire [7:0] _GEN_19 = {{4'd0}, log_a[7:4]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_3 = _GEN_19 & 8'hf; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_5 = {log_a[3:0], 4'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clz_T_7 = _log_clz_T_5 & 8'hf0; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clz_T_8 = _log_clz_T_3 | _log_clz_T_7; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_20 = {{2'd0}, _log_clz_T_8[7:2]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_13 = _GEN_20 & 8'h33; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_15 = {_log_clz_T_8[5:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clz_T_17 = _log_clz_T_15 & 8'hcc; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clz_T_18 = _log_clz_T_13 | _log_clz_T_17; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_21 = {{1'd0}, _log_clz_T_18[7:1]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_23 = _GEN_21 & 8'h55; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_25 = {_log_clz_T_18[6:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clz_T_27 = _log_clz_T_25 & 8'haa; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clz_T_28 = _log_clz_T_23 | _log_clz_T_27; // @[Bitwise.scala 105:39]
- wire [8:0] _log_clz_T_29 = {1'h1,_log_clz_T_28}; // @[Cat.scala 31:58]
- wire [3:0] _log_clz_T_39 = _log_clz_T_29[7] ? 4'h7 : 4'h8; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_40 = _log_clz_T_29[6] ? 4'h6 : _log_clz_T_39; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_41 = _log_clz_T_29[5] ? 4'h5 : _log_clz_T_40; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_42 = _log_clz_T_29[4] ? 4'h4 : _log_clz_T_41; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_43 = _log_clz_T_29[3] ? 4'h3 : _log_clz_T_42; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_44 = _log_clz_T_29[2] ? 4'h2 : _log_clz_T_43; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_45 = _log_clz_T_29[1] ? 4'h1 : _log_clz_T_44; // @[Mux.scala 47:70]
- wire [3:0] log_clz = _log_clz_T_29[0] ? 4'h0 : _log_clz_T_45; // @[Mux.scala 47:70]
- wire [3:0] _log_T_33 = log_a[7] ? log_clo : log_clz; // @[Library.scala 289:8]
- wire [3:0] _log_T_34 = io_in_sz[0] ? _log_T_33 : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _log_T_35 = io_op_log_clb ? _log_T_34 : 4'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_22 = {{4'd0}, _log_T_35}; // @[VAluInt.scala 1376:81]
- wire [7:0] _log_T_36 = _log_T_29 | _GEN_22; // @[VAluInt.scala 1376:81]
- wire [3:0] _log_T_86 = io_in_sz[0] ? log_clz : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _log_T_87 = io_op_log_clz ? _log_T_86 : 4'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_26 = {{4'd0}, _log_T_87}; // @[VAluInt.scala 1377:69]
- wire [7:0] _log_T_88 = _log_T_36 | _GEN_26; // @[VAluInt.scala 1377:69]
- wire [1:0] _log_T_98 = log_a[0] + log_a[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_100 = log_a[2] + log_a[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_102 = _log_T_98 + _log_T_100; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_104 = log_a[4] + log_a[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_106 = log_a[6] + log_a[7]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_108 = _log_T_104 + _log_T_106; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_110 = _log_T_102 + _log_T_108; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_112 = io_op_log_cpop ? _log_T_110 : 4'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_27 = {{4'd0}, _log_T_112}; // @[VAluInt.scala 1378:69]
- wire [7:0] log = _log_T_88 | _GEN_27; // @[VAluInt.scala 1378:69]
- wire [7:0] _shift_T = io_op_shf_shl ? shl : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shift_T_1 = io_op_shf_shr ? shr : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shift_T_2 = _shift_T | _shift_T_1; // @[VAluInt.scala 1383:35]
- wire [7:0] _shift_T_3 = io_op_shf_shf ? shf : 8'h0; // @[Library.scala 32:8]
- wire [7:0] shift = _shift_T_2 | _shift_T_3; // @[VAluInt.scala 1384:35]
- wire _alu_oh_T = absd != 8'h0; // @[VAluInt.scala 1388:30]
- wire _alu_oh_T_1 = add != 8'h0; // @[VAluInt.scala 1389:30]
- wire _alu_oh_T_3 = dup != 8'h0; // @[VAluInt.scala 1391:30]
- wire _alu_oh_T_4 = log != 8'h0; // @[VAluInt.scala 1392:30]
- wire _alu_oh_T_5 = max != 8'h0; // @[VAluInt.scala 1393:30]
- wire _alu_oh_T_6 = min != 8'h0; // @[VAluInt.scala 1394:30]
- wire _alu_oh_T_7 = mul0 != 8'h0; // @[VAluInt.scala 1395:30]
- wire _alu_oh_T_9 = rsub != 8'h0; // @[VAluInt.scala 1397:30]
- wire _alu_oh_T_10 = shift != 8'h0; // @[VAluInt.scala 1398:30]
- wire _alu_oh_T_11 = srans != 8'h0; // @[VAluInt.scala 1399:30]
- wire _alu_oh_T_12 = sraqs != 8'h0; // @[VAluInt.scala 1400:30]
- wire _alu_oh_T_13 = sub != 8'h0; // @[VAluInt.scala 1401:30]
- wire [6:0] alu_oh_lo = {_alu_oh_T_7,1'h0,_alu_oh_T_9,_alu_oh_T_10,_alu_oh_T_11,_alu_oh_T_12,_alu_oh_T_13}; // @[Cat.scala 31:58]
- wire [13:0] alu_oh = {_alu_oh_T,_alu_oh_T_1,cmp,_alu_oh_T_3,_alu_oh_T_4,_alu_oh_T_5,_alu_oh_T_6,alu_oh_lo}; // @[Cat.scala 31:58]
- wire [1:0] _T_66 = alu_oh[1] + alu_oh[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_28 = {{1'd0}, alu_oh[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_68 = _GEN_28 + _T_66; // @[Bitwise.scala 48:55]
- wire [1:0] _T_70 = alu_oh[3] + alu_oh[4]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_72 = alu_oh[5] + alu_oh[6]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_74 = _T_70 + _T_72; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_29 = {{1'd0}, _T_68[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_76 = _GEN_29 + _T_74; // @[Bitwise.scala 48:55]
- wire [1:0] _T_78 = alu_oh[8] + alu_oh[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_30 = {{1'd0}, alu_oh[7]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_80 = _GEN_30 + _T_78; // @[Bitwise.scala 48:55]
- wire [1:0] _T_82 = alu_oh[10] + alu_oh[11]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_84 = alu_oh[12] + alu_oh[13]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_86 = _T_82 + _T_84; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_31 = {{1'd0}, _T_80[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_88 = _GEN_31 + _T_86; // @[Bitwise.scala 48:55]
- wire [3:0] _T_90 = _T_76[2:0] + _T_88[2:0]; // @[Bitwise.scala 48:55]
- wire [7:0] _alu0_0_T = mul0 | absd; // @[VAluInt.scala 1405:23]
- wire [7:0] _alu0_0_T_1 = _alu0_0_T | add; // @[VAluInt.scala 1405:30]
- wire [7:0] _GEN_32 = {{7'd0}, cmp}; // @[VAluInt.scala 1405:36]
- wire [7:0] _alu0_0_T_2 = _alu0_0_T_1 | _GEN_32; // @[VAluInt.scala 1405:36]
- wire [7:0] _alu0_0_T_3 = _alu0_0_T_2 | dup; // @[VAluInt.scala 1405:42]
- wire [7:0] _alu0_0_T_4 = _alu0_0_T_3 | log; // @[VAluInt.scala 1405:48]
- wire [7:0] _alu0_0_T_5 = _alu0_0_T_4 | max; // @[VAluInt.scala 1405:54]
- wire [7:0] _alu0_0_T_6 = _alu0_0_T_5 | min; // @[VAluInt.scala 1405:60]
- wire [7:0] _alu0_0_T_8 = _alu0_0_T_6 | rsub; // @[VAluInt.scala 1405:73]
- wire [7:0] _alu0_0_T_9 = _alu0_0_T_8 | shift; // @[VAluInt.scala 1405:80]
- wire [7:0] _alu0_0_T_10 = _alu0_0_T_9 | srans; // @[VAluInt.scala 1405:88]
- wire [7:0] _alu0_0_T_11 = _alu0_0_T_10 | sraqs; // @[VAluInt.scala 1405:96]
- wire [7:0] _alu0_0_T_12 = _alu0_0_T_11 | sub; // @[VAluInt.scala 1405:104]
- wire [7:0] _alu0_0_T_14 = io_op_mv ? ina_b[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] alu0__0 = _alu0_0_T_12 | _alu0_0_T_14; // @[VAluInt.scala 1405:110]
- wire [7:0] _alu1_0_T_1 = io_op_mvp ? inb_b[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _alu1_0_T_2 = mul1 | _alu1_0_T_1; // @[VAluInt.scala 1408:23]
- wire [7:0] _alu1_0_T_4 = io_op_mv2 ? inc_b[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] alu1__0 = _alu1_0_T_2 | _alu1_0_T_4; // @[VAluInt.scala 1409:44]
- wire [7:0] _GEN_33 = {{7'd0}, mulh0_rnd}; // @[VAluInt.scala 1412:29]
- wire [7:0] _rnd0_0_T = dmulh0_rnd | _GEN_33; // @[VAluInt.scala 1412:29]
- wire [7:0] _GEN_34 = {{7'd0}, shf_rnd}; // @[VAluInt.scala 1412:41]
- wire [7:0] rnd0__0 = _rnd0_0_T | _GEN_34; // @[VAluInt.scala 1412:41]
- wire [7:0] _GEN_35 = {{7'd0}, mulh1_rnd}; // @[VAluInt.scala 1413:29]
- wire [7:0] rnd1__0 = dmulh1_rnd | _GEN_35; // @[VAluInt.scala 1413:29]
- wire [15:0] _aluw0_0_T = acc | addw; // @[VAluInt.scala 1417:31]
- wire [15:0] _aluw0_0_T_1 = _aluw0_0_T | mulw; // @[VAluInt.scala 1417:38]
- wire [15:0] aluw0__0 = _aluw0_0_T_1 | subw; // @[VAluInt.scala 1417:45]
- wire add_sa_1 = add_a[15] & io_in_signed; // @[VAluInt.scala 973:29]
- wire add_sb_1 = add_b[15] & io_in_signed; // @[VAluInt.scala 974:29]
- wire [8:0] _adder_T_11 = {add_sa_1,add_a[15:8]}; // @[VAluInt.scala 975:44]
- wire [8:0] _adder_T_14 = {add_sb_1,add_b[15:8]}; // @[VAluInt.scala 975:78]
- wire [9:0] _adder_T_16 = $signed(_adder_T_11) + $signed(_adder_T_14); // @[VAluInt.scala 975:86]
- wire [9:0] adder_1 = _adder_T_16 + _GEN_6; // @[VAluInt.scala 975:93]
- wire [1:0] sataddmsb_1 = adder_1[8:7]; // @[VAluInt.scala 976:28]
- wire _sataddsel_T_8 = io_in_signed & sataddmsb_1 == 2'h2; // @[VAluInt.scala 978:21]
- wire _sataddsel_T_10 = io_in_signed & sataddmsb_1 == 2'h1; // @[VAluInt.scala 979:21]
- wire _sataddsel_T_13 = ~io_in_signed & sataddmsb_1[1]; // @[VAluInt.scala 980:21]
- wire [2:0] sataddsel_1 = {_sataddsel_T_8,_sataddsel_T_10,_sataddsel_T_13}; // @[Cat.scala 31:58]
- wire [1:0] _T_99 = sataddsel_1[1] + sataddsel_1[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_37 = {{1'd0}, sataddsel_1[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_101 = _GEN_37 + _T_99; // @[Bitwise.scala 48:55]
- wire sub_sa_1 = sub_a[15] & io_in_signed; // @[VAluInt.scala 983:29]
- wire sub_sb_1 = sub_b[15] & io_in_signed; // @[VAluInt.scala 984:29]
- wire [8:0] _subtr_T_11 = {sub_sa_1,sub_a[15:8]}; // @[VAluInt.scala 985:44]
- wire [8:0] _subtr_T_14 = {sub_sb_1,sub_b[15:8]}; // @[VAluInt.scala 985:78]
- wire [9:0] _subtr_T_16 = $signed(_subtr_T_11) - $signed(_subtr_T_14); // @[VAluInt.scala 985:86]
- wire [9:0] subtr_1 = _subtr_T_16 + _GEN_8; // @[VAluInt.scala 985:93]
- wire [1:0] satsubmsb_1 = subtr_1[8:7]; // @[VAluInt.scala 986:28]
- wire _satsubsel_T_8 = io_in_signed & satsubmsb_1 == 2'h2; // @[VAluInt.scala 988:21]
- wire _satsubsel_T_10 = io_in_signed & satsubmsb_1 == 2'h1; // @[VAluInt.scala 989:21]
- wire _satsubsel_T_13 = _sataddsel_T_4 & satsubmsb_1[1]; // @[VAluInt.scala 990:21]
- wire [2:0] satsubsel_1 = {_satsubsel_T_8,_satsubsel_T_10,_satsubsel_T_13}; // @[Cat.scala 31:58]
- wire [1:0] _T_110 = satsubsel_1[1] + satsubsel_1[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_39 = {{1'd0}, satsubsel_1[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_112 = _GEN_39 + _T_110; // @[Bitwise.scala 48:55]
- wire [7:0] rsubtr_1 = rsub_b[15:8] - rsub_a[15:8]; // @[VAluInt.scala 993:32]
- wire xeq_1 = cmp_a[15:8] == cmp_b[15:8]; // @[VAluInt.scala 995:28]
- wire xne_1 = cmp_a[15:8] != cmp_b[15:8]; // @[VAluInt.scala 996:28]
- wire [7:0] _slt_T_5 = cmp_a[15:8]; // @[VAluInt.scala 997:34]
- wire [7:0] _slt_T_7 = cmp_b[15:8]; // @[VAluInt.scala 997:56]
- wire slt_1 = $signed(_slt_T_5) < $signed(_slt_T_7); // @[VAluInt.scala 997:37]
- wire ult_1 = cmp_a[15:8] < cmp_b[15:8]; // @[VAluInt.scala 998:28]
- wire sle_1 = slt_1 | xeq_1; // @[VAluInt.scala 999:21]
- wire ule_1 = ult_1 | xeq_1; // @[VAluInt.scala 1000:21]
- wire sult_1 = io_in_signed ? slt_1 : ult_1; // @[VAluInt.scala 1002:21]
- wire [14:0] _GEN_3 = {{7'd0}, shl_a[15:8]}; // @[VAluInt.scala 1062:29]
- wire [14:0] _shl_T_5 = _GEN_3 << shl_b[10:8]; // @[VAluInt.scala 1062:29]
- wire [7:0] shl_1 = _shl_T_5[7:0]; // @[VAluInt.scala 1062:49]
- wire [3:0] _GEN_40 = {{1'd0}, shl_b[10:8]}; // @[VAluInt.scala 1063:40]
- wire [3:0] _sln_T_8 = 4'h8 - _GEN_40; // @[VAluInt.scala 1063:40]
- wire [22:0] _GEN_5 = {{15'd0}, shl_a[15:8]}; // @[VAluInt.scala 1063:29]
- wire [22:0] _sln_T_9 = _GEN_5 << _sln_T_8; // @[VAluInt.scala 1063:29]
- wire [14:0] sln_1 = _sln_T_9[14:0]; // @[VAluInt.scala 1063:60]
- wire [7:0] srl_1 = shr_a[15:8] >> shr_b[10:8]; // @[VAluInt.scala 1064:28]
- wire [2:0] _srs_T_11 = 3'h7 - shr_b[10:8]; // @[VAluInt.scala 1065:66]
- wire [14:0] _srs_T_12 = 15'hff << _srs_T_11; // @[VAluInt.scala 1065:49]
- wire [7:0] srs_1 = shr_a[15] ? _srs_T_12[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] sra_1 = srs_1 | srl_1; // @[VAluInt.scala 1066:21]
- wire [7:0] shf_slnsz_1 = sln_1[7:0]; // @[VAluInt.scala 1010:24]
- wire shf_input_neg_1 = shl_a[15]; // @[VAluInt.scala 1011:26]
- wire shf_input_zero_1 = shl_a[15:8] == 8'h0; // @[VAluInt.scala 1012:28]
- wire shf_shamt_neg_1 = shl_b[15]; // @[VAluInt.scala 1013:26]
- wire [7:0] _shf_shamt_negsat_T_5 = shl_b[15:8]; // @[VAluInt.scala 1017:32]
- wire shf_shamt_negsat_2 = $signed(_shf_shamt_negsat_T_5) <= -8'sh7; // @[VAluInt.scala 1017:39]
- wire shf_shamt_possat_2 = $signed(_shf_shamt_negsat_T_5) >= 8'sh7; // @[VAluInt.scala 1018:39]
- wire [2:0] _shf_signb_T_7 = shl_b[10:8] - 3'h1; // @[VAluInt.scala 1019:65]
- wire [7:0] shf_signb_1 = 8'hff >> _shf_signb_T_7; // @[VAluInt.scala 1019:36]
- wire _shf_possat_T_18 = ~shf_input_zero_1; // @[VAluInt.scala 1020:112]
- wire shf_possat_2 = shf_shamt_neg_1 & ~shf_input_neg_1 & (shf_shamt_negsat_2 | sln_1[14:7] != 8'h0) & ~
- shf_input_zero_1; // @[VAluInt.scala 1020:109]
- wire shf_negsat_1 = shf_shamt_neg_1 & shf_input_neg_1 & (shf_shamt_negsat_2 | sln_1[14:7] != shf_signb_1); // @[VAluInt.scala 1021:48]
- wire _shf_rs_T_22 = ~shf_shamt_neg_1; // @[VAluInt.scala 1028:23]
- wire _shf_rs_T_24 = ~shf_shamt_neg_1 & ~shf_shamt_possat_2; // @[VAluInt.scala 1028:34]
- wire [7:0] _shf_rs_T_25 = _shf_rs_T_24 ? sra_1 : 8'h0; // @[Library.scala 32:8]
- wire _shf_rs_T_28 = _shf_rs_T_22 & shf_shamt_possat_2 & shf_input_neg_1; // @[VAluInt.scala 1029:51]
- wire [7:0] _shf_rs_T_30 = _shf_rs_T_28 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_rs_T_31 = _shf_rs_T_25 | _shf_rs_T_30; // @[VAluInt.scala 1028:57]
- wire _shf_rs_T_35 = shf_shamt_neg_1 & ~shf_possat_2 & ~shf_negsat_1; // @[VAluInt.scala 1030:45]
- wire [7:0] _shf_rs_T_36 = _shf_rs_T_35 ? shf_slnsz_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_rs_T_37 = _shf_rs_T_31 | _shf_rs_T_36; // @[VAluInt.scala 1029:79]
- wire _shf_rs_T_38 = shf_shamt_neg_1 & shf_possat_2; // @[VAluInt.scala 1031:34]
- wire [7:0] _shf_rs_T_39 = _shf_rs_T_38 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_rs_T_40 = _shf_rs_T_37 | _shf_rs_T_39; // @[VAluInt.scala 1030:64]
- wire _shf_rs_T_41 = shf_shamt_neg_1 & shf_negsat_1; // @[VAluInt.scala 1032:34]
- wire [7:0] _shf_rs_T_42 = _shf_rs_T_41 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] shf_rs_1 = _shf_rs_T_40 | _shf_rs_T_42; // @[VAluInt.scala 1031:53]
- wire shf_shamt_negsat_3 = $signed(_shf_shamt_negsat_T_5) <= $signed(_GEN_11); // @[VAluInt.scala 1035:39]
- wire shf_shamt_possat_3 = $signed(_shf_shamt_negsat_T_5) >= 8'sh8; // @[VAluInt.scala 1036:39]
- wire shf_possat_3 = shf_shamt_neg_1 & (shf_shamt_negsat_3 | sln_1[14:8] != 7'h0) & _shf_possat_T_18; // @[VAluInt.scala 1037:89]
- wire _shf_ru_T_13 = _shf_rs_T_22 & ~shf_shamt_possat_3; // @[VAluInt.scala 1041:34]
- wire [7:0] _shf_ru_T_14 = _shf_ru_T_13 ? srl_1 : 8'h0; // @[Library.scala 32:8]
- wire _shf_ru_T_16 = shf_shamt_neg_1 & ~shf_possat_3; // @[VAluInt.scala 1042:34]
- wire [7:0] _shf_ru_T_17 = _shf_ru_T_16 ? shf_slnsz_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_ru_T_18 = _shf_ru_T_14 | _shf_ru_T_17; // @[VAluInt.scala 1041:57]
- wire _shf_ru_T_19 = shf_shamt_neg_1 & shf_possat_3; // @[VAluInt.scala 1043:34]
- wire [7:0] _shf_ru_T_20 = _shf_ru_T_19 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] shf_ru_1 = _shf_ru_T_18 | _shf_ru_T_20; // @[VAluInt.scala 1042:53]
- wire [7:0] shf_1 = io_in_signed ? shf_rs_1 : shf_ru_1; // @[VAluInt.scala 1045:12]
- wire [7:0] shr_1 = io_in_signed ? sra_1 : srl_1; // @[VAluInt.scala 1068:20]
- wire shf_rnd_shamt_zero_1 = shl_b[15:8] == 8'h0; // @[VAluInt.scala 1053:28]
- wire [7:0] _shf_rnd_rbit_T_7 = {shl_a[14:8],shf_input_neg_1}; // @[Cat.scala 31:58]
- wire [7:0] _shf_rnd_rbit_T_9 = _shf_rnd_rbit_T_7 >> shl_b[10:8]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_rbit_1 = _shf_rnd_rbit_T_9[0]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_shamt_possat_1 = io_in_signed ? shf_shamt_possat_3 : $signed(_shf_shamt_negsat_T_5) > 8'sh8; // @[VAluInt.scala 1055:31]
- wire _shf_rnd_r_T_16 = io_in_round & ~shf_rnd_shamt_possat_1 & _shf_rs_T_22 & ~shf_rnd_shamt_zero_1; // @[VAluInt.scala 1056:60]
- wire _shf_rnd_r_T_17 = _shf_rnd_r_T_16 & shf_rnd_rbit_1; // @[Library.scala 36:8]
- wire _shf_rnd_r_T_20 = io_in_round & shf_rnd_shamt_possat_1 & shf_input_neg_1 & io_in_signed; // @[VAluInt.scala 1057:59]
- wire shf_rnd_1 = _shf_rnd_r_T_17 | _shf_rnd_r_T_20; // @[VAluInt.scala 1056:82]
- wire _mul0_as_T_4 = io_in_signed & mul0_a[15]; // @[VAluInt.scala 1199:32]
- wire _mul0_bs_T_4 = io_in_signed & mul0_b[15]; // @[VAluInt.scala 1200:32]
- wire mul0_sign_1 = mul0_a[15] != mul0_b[15] & mul0_a[15:8] != 8'h0 & mul0_b[15:8] != 8'h0; // @[VAluInt.scala 1201:70]
- wire [8:0] _prod0_T_3 = {_mul0_as_T_4,mul0_a[15:8]}; // @[VAluInt.scala 1202:28]
- wire [8:0] _prod0_T_4 = {_mul0_bs_T_4,mul0_b[15:8]}; // @[VAluInt.scala 1202:45]
- wire [17:0] prod0_1 = $signed(_prod0_T_3) * $signed(_prod0_T_4); // @[VAluInt.scala 1202:53]
- wire [7:0] prodh0_1 = prod0_1[15:8]; // @[VAluInt.scala 1203:25]
- wire [7:0] proddh0_1 = prod0_1[14:7]; // @[VAluInt.scala 1204:26]
- wire _mul1_as_T_4 = io_in_signed & mul1_a[15]; // @[VAluInt.scala 1206:32]
- wire _mul1_bs_T_4 = io_in_signed & mul1_b[15]; // @[VAluInt.scala 1207:32]
- wire mul1_sign_1 = mul1_a[15] != mul1_b[15] & mul1_a[15:8] != 8'h0 & mul1_b[15:8] != 8'h0; // @[VAluInt.scala 1208:70]
- wire [8:0] _prod1_T_3 = {_mul1_as_T_4,mul1_a[15:8]}; // @[VAluInt.scala 1209:28]
- wire [8:0] _prod1_T_4 = {_mul1_bs_T_4,mul1_b[15:8]}; // @[VAluInt.scala 1209:45]
- wire [17:0] prod1_1 = $signed(_prod1_T_3) * $signed(_prod1_T_4); // @[VAluInt.scala 1209:53]
- wire [7:0] prodh1_1 = prod1_1[15:8]; // @[VAluInt.scala 1210:25]
- wire [7:0] proddh1_1 = prod1_1[14:7]; // @[VAluInt.scala 1211:26]
- wire _muls0_umax_T_3 = prodh0_1 != 8'h0; // @[VAluInt.scala 1213:42]
- wire muls0_umax_1 = _sataddsel_T_4 & prodh0_1 != 8'h0; // @[VAluInt.scala 1213:32]
- wire muls0_smax_1 = io_in_signed & ~mul0_sign_1 & (prod0_1[7] | _muls0_umax_T_3); // @[VAluInt.scala 1214:46]
- wire muls0_smin_1 = io_in_signed & mul0_sign_1 & (~prod0_1[7] | prodh0_1 != 8'hff); // @[VAluInt.scala 1215:46]
- wire muls0_base_1 = ~(muls0_umax_1 | muls0_smax_1 | muls0_smin_1); // @[VAluInt.scala 1216:24]
- wire [3:0] _T_118 = {muls0_umax_1,muls0_smax_1,muls0_smin_1,muls0_base_1}; // @[Cat.scala 31:58]
- wire [1:0] _T_123 = _T_118[0] + _T_118[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_125 = _T_118[2] + _T_118[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_127 = _T_123 + _T_125; // @[Bitwise.scala 48:55]
- wire _muls1_umax_T_3 = prodh1_1 != 8'h0; // @[VAluInt.scala 1219:42]
- wire muls1_umax_1 = _sataddsel_T_4 & prodh1_1 != 8'h0; // @[VAluInt.scala 1219:32]
- wire muls1_smax_1 = io_in_signed & ~mul1_sign_1 & (prod1_1[7] | _muls1_umax_T_3); // @[VAluInt.scala 1220:46]
- wire muls1_smin_1 = io_in_signed & mul1_sign_1 & (~prod1_1[7] | prodh1_1 != 8'hff); // @[VAluInt.scala 1221:46]
- wire muls1_base_1 = ~(muls1_umax_1 | muls1_smax_1 | muls1_smin_1); // @[VAluInt.scala 1222:24]
- wire [3:0] _T_133 = {muls1_umax_1,muls1_smax_1,muls1_smin_1,muls1_base_1}; // @[Cat.scala 31:58]
- wire [1:0] _T_138 = _T_133[0] + _T_133[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_140 = _T_133[2] + _T_133[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_142 = _T_138 + _T_140; // @[Bitwise.scala 48:55]
- wire dmulh0_possat_1 = mul0_a[15:8] == 8'h80 & mul0_b[15:8] == 8'h80; // @[VAluInt.scala 1227:50]
- wire dmulh1_possat_1 = mul1_a[15:8] == 8'h80 & mul1_b[15:8] == 8'h80; // @[VAluInt.scala 1229:50]
- wire _dmulh0_T_5 = ~dmulh0_possat_1; // @[VAluInt.scala 1231:26]
- wire [7:0] _dmulh0_T_6 = _dmulh0_T_5 ? proddh0_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh0_T_9 = dmulh0_possat_1 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] dmulh0_1 = _dmulh0_T_6 | _dmulh0_T_9; // @[VAluInt.scala 1231:51]
- wire _dmulh1_T_5 = ~dmulh1_possat_1; // @[VAluInt.scala 1234:26]
- wire [7:0] _dmulh1_T_6 = _dmulh1_T_5 ? proddh1_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh1_T_9 = dmulh1_possat_1 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] dmulh1_1 = _dmulh1_T_6 | _dmulh1_T_9; // @[VAluInt.scala 1234:51]
- wire [7:0] _muls0_T_11 = muls0_umax_1 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [6:0] _muls0_T_13 = muls0_smax_1 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_42 = {{1'd0}, _muls0_T_13}; // @[VAluInt.scala 1240:51]
- wire [7:0] _muls0_T_14 = _muls0_T_11 | _GEN_42; // @[VAluInt.scala 1240:51]
- wire [7:0] _muls0_T_16 = muls0_smin_1 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _muls0_T_17 = _muls0_T_14 | _muls0_T_16; // @[VAluInt.scala 1241:57]
- wire [7:0] _muls0_T_19 = muls0_base_1 ? prod0_1[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] muls0_1 = _muls0_T_17 | _muls0_T_19; // @[VAluInt.scala 1242:71]
- wire [7:0] _muls1_T_11 = muls1_umax_1 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [6:0] _muls1_T_13 = muls1_smax_1 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_43 = {{1'd0}, _muls1_T_13}; // @[VAluInt.scala 1245:51]
- wire [7:0] _muls1_T_14 = _muls1_T_11 | _GEN_43; // @[VAluInt.scala 1245:51]
- wire [7:0] _muls1_T_16 = muls1_smin_1 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _muls1_T_17 = _muls1_T_14 | _muls1_T_16; // @[VAluInt.scala 1246:57]
- wire [7:0] _muls1_T_19 = muls1_base_1 ? prod1_1[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] muls1_1 = _muls1_T_17 | _muls1_T_19; // @[VAluInt.scala 1247:71]
- wire _dmulh0_rnd_T_17 = io_in_round & io_op_mul0_dmulh & io_in_sz[0] & _dmulh0_T_5; // @[VAluInt.scala 1250:72]
- wire _dmulh0_rnd_T_20 = ~prod0_1[6]; // @[VAluInt.scala 1252:40]
- wire [7:0] _dmulh0_rnd_T_22 = _dmulh0_rnd_T_20 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh0_rnd_T_24 = prod0_1[6] ? 8'h1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh0_rnd_T_25 = io_in_negative & mul0_sign_1 ? _dmulh0_rnd_T_22 : _dmulh0_rnd_T_24; // @[VAluInt.scala 1251:33]
- wire [7:0] dmulh0_rnd_1 = _dmulh0_rnd_T_17 ? _dmulh0_rnd_T_25 : 8'h0; // @[Library.scala 32:8]
- wire _dmulh1_rnd_T_17 = io_in_round & io_op_mul1_dmulh & io_in_sz[0] & _dmulh1_T_5; // @[VAluInt.scala 1255:72]
- wire _dmulh1_rnd_T_20 = ~prod1_1[6]; // @[VAluInt.scala 1257:40]
- wire [7:0] _dmulh1_rnd_T_22 = _dmulh1_rnd_T_20 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh1_rnd_T_24 = prod1_1[6] ? 8'h1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh1_rnd_T_25 = io_in_negative & mul1_sign_1 ? _dmulh1_rnd_T_22 : _dmulh1_rnd_T_24; // @[VAluInt.scala 1256:33]
- wire [7:0] dmulh1_rnd_1 = _dmulh1_rnd_T_17 ? _dmulh1_rnd_T_25 : 8'h0; // @[Library.scala 32:8]
- wire mulh0_rnd_1 = io_in_round & io_op_mul0_mulh & prod0_1[7]; // @[VAluInt.scala 1260:48]
- wire mulh1_rnd_1 = io_in_round & io_op_mul1_mulh & prod1_1[7]; // @[VAluInt.scala 1261:48]
- wire [7:0] _absd_T_3 = sult_1 ? rsubtr_1 : subtr_1[7:0]; // @[VAluInt.scala 1265:39]
- wire [7:0] absd_1 = io_op_absd ? _absd_T_3 : 8'h0; // @[Library.scala 32:8]
- wire _acc_T_8 = io_in_signed & acc_b[15]; // @[VAluInt.scala 1272:55]
- wire [8:0] _acc_T_10 = {_acc_T_8,acc_b[15:8]}; // @[Cat.scala 31:58]
- wire acc_r_r_1_2 = _acc_T_10[8]; // @[Library.scala 64:25]
- wire [15:0] acc_r_1 = {acc_r_r_1_2,acc_r_r_1_2,acc_r_r_1_2,acc_r_r_1_2,acc_r_r_1_2,acc_r_r_1_2,acc_r_r_1_2,_acc_T_8,
- acc_b[15:8]}; // @[Cat.scala 31:58]
- wire [15:0] acc_1 = acc_c[15:0] + acc_r_1; // @[VAluInt.scala 1272:34]
- wire _add_T_24 = sataddsel_1[2] & io_op_add_adds; // @[VAluInt.scala 1279:36]
- wire [7:0] _add_T_26 = _add_T_24 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire _add_T_28 = sataddsel_1[1] & io_op_add_adds; // @[VAluInt.scala 1280:36]
- wire [6:0] _add_T_30 = _add_T_28 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_44 = {{1'd0}, _add_T_30}; // @[VAluInt.scala 1279:89]
- wire [7:0] _add_T_31 = _add_T_26 | _GEN_44; // @[VAluInt.scala 1279:89]
- wire _add_T_33 = sataddsel_1[0] & io_op_add_adds; // @[VAluInt.scala 1281:36]
- wire [7:0] _add_T_35 = _add_T_33 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _add_T_36 = _add_T_31 | _add_T_35; // @[VAluInt.scala 1280:75]
- wire _add_T_40 = sataddsel_1 == 3'h0 & io_op_add_adds | io_op_add_add | io_op_add_add3; // @[VAluInt.scala 1282:76]
- wire [7:0] _add_T_42 = _add_T_40 ? adder_1[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _add_T_43 = _add_T_36 | _add_T_42; // @[VAluInt.scala 1281:69]
- wire [7:0] _add_T_45 = io_op_add_hadd ? adder_1[8:1] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] add_1 = _add_T_43 | _add_T_45; // @[VAluInt.scala 1282:115]
- wire addw_r_r_1_2 = adder_1[9]; // @[Library.scala 64:25]
- wire [15:0] addw_r_1 = {addw_r_r_1_2,addw_r_r_1_2,addw_r_r_1_2,addw_r_r_1_2,addw_r_r_1_2,addw_r_r_1_2,adder_1}; // @[Cat.scala 31:58]
- wire [15:0] addw_1 = io_op_add_addw ? addw_r_1 : 16'h0; // @[Library.scala 32:8]
- wire [7:0] dup_1 = io_op_dup ? io_read_1_data[15:8] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _max_T_5 = sult_1 ? cmp_b[15:8] : cmp_a[15:8]; // @[VAluInt.scala 1290:37]
- wire [7:0] max_1 = io_op_max ? _max_T_5 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _min_T_5 = sult_1 ? cmp_a[15:8] : cmp_b[15:8]; // @[VAluInt.scala 1291:37]
- wire [7:0] min_1 = io_op_min ? _min_T_5 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_10 = _mul0_T ? prod0_1[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_11 = io_op_mul0_dmulh ? dmulh0_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_12 = _mul0_T_10 | _mul0_T_11; // @[VAluInt.scala 1293:79]
- wire [7:0] _mul0_T_13 = io_op_mul0_mulh ? prodh0_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_14 = _mul0_T_12 | _mul0_T_13; // @[VAluInt.scala 1294:50]
- wire [7:0] _mul0_T_15 = io_op_mul0_muls ? muls0_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] mul0_1 = _mul0_T_14 | _mul0_T_15; // @[VAluInt.scala 1295:48]
- wire [7:0] _mul1_T_8 = io_op_mul1_mul ? prod1_1[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul1_T_9 = io_op_mul1_dmulh ? dmulh1_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul1_T_10 = _mul1_T_8 | _mul1_T_9; // @[VAluInt.scala 1298:60]
- wire [7:0] _mul1_T_11 = io_op_mul1_mulh ? prodh1_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul1_T_12 = _mul1_T_10 | _mul1_T_11; // @[VAluInt.scala 1299:50]
- wire [7:0] _mul1_T_13 = io_op_mul1_muls ? muls1_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] mul1_1 = _mul1_T_12 | _mul1_T_13; // @[VAluInt.scala 1300:48]
- wire [15:0] mulw_1 = io_op_mul0_mulw ? prod0_1[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [7:0] rsub_1 = io_op_rsub_rsub ? rsubtr_1 : 8'h0; // @[Library.scala 32:8]
- wire [3:0] srans_shamt_1 = srans_b[11:8]; // @[VAluInt.scala 1084:22]
- wire [15:0] srans_srl_1 = srans_c[15:0] >> srans_shamt_1; // @[VAluInt.scala 1085:21]
- wire _srans_srs_T_8 = srans_c[15] & io_in_signed; // @[VAluInt.scala 1088:41]
- wire [3:0] _srans_srs_T_11 = 4'hf - srans_shamt_1; // @[VAluInt.scala 1089:68]
- wire [30:0] _srans_srs_T_12 = 31'hffff << _srans_srs_T_11; // @[VAluInt.scala 1089:47]
- wire [15:0] srans_srs_1 = _srans_srs_T_8 ? _srans_srs_T_12[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] srans_sra_1 = srans_srs_1 | srans_srl_1; // @[VAluInt.scala 1090:23]
- wire [15:0] _srans_rbit_T_4 = {srans_c[14:0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] _srans_rbit_T_5 = _srans_rbit_T_4 >> srans_shamt_1; // @[VAluInt.scala 1093:53]
- wire srans_rbit_1 = _srans_rbit_T_5[0]; // @[VAluInt.scala 1093:53]
- wire [15:0] _srans_rshf_T_5 = srans_sra_1 + 16'h1; // @[VAluInt.scala 1099:43]
- wire [15:0] srans_rshf_1 = io_in_round & srans_rbit_1 ? _srans_rshf_T_5 : srans_sra_1; // @[VAluInt.scala 1099:23]
- wire srans_is_umax_1 = _sataddsel_T_4 & srans_rshf_1 > 16'hff; // @[VAluInt.scala 1101:31]
- wire [15:0] _srans_is_smax_T_2 = io_in_round & srans_rbit_1 ? _srans_rshf_T_5 : srans_sra_1; // @[VAluInt.scala 1103:40]
- wire srans_is_smax_1 = io_in_signed & $signed(_srans_is_smax_T_2) > 16'sh7f; // @[VAluInt.scala 1103:31]
- wire srans_is_smin_1 = io_in_signed & $signed(_srans_is_smax_T_2) < $signed(srans_smin); // @[VAluInt.scala 1104:31]
- wire srans_is_norm_1 = ~(srans_is_umax_1 | srans_is_smax_1 | srans_is_smin_1); // @[VAluInt.scala 1105:23]
- wire [3:0] _srans_T_19 = {srans_is_umax_1,srans_is_smax_1,srans_is_smin_1,srans_is_norm_1}; // @[Cat.scala 31:58]
- wire [1:0] _srans_T_24 = _srans_T_19[0] + _srans_T_19[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _srans_T_26 = _srans_T_19[2] + _srans_T_19[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _srans_T_28 = _srans_T_24 + _srans_T_26; // @[Bitwise.scala 48:55]
- wire [7:0] _srans_r_T_11 = srans_is_umax_1 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _srans_r_T_14 = srans_is_smax_1 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _srans_r_T_15 = _srans_r_T_11 | _srans_r_T_14; // @[VAluInt.scala 1108:58]
- wire [7:0] _srans_r_T_18 = srans_is_smin_1 ? _srans_r_T_5[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _srans_r_T_19 = _srans_r_T_15 | _srans_r_T_18; // @[VAluInt.scala 1109:58]
- wire [7:0] _srans_r_T_21 = srans_is_norm_1 ? srans_rshf_1[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] srans_1 = _srans_r_T_19 | _srans_r_T_21; // @[VAluInt.scala 1110:58]
- wire [4:0] sraqs_shamt_1 = sraqs_b[12:8]; // @[VAluInt.scala 1084:22]
- wire [31:0] sraqs_srl_1 = sraqs_d >> sraqs_shamt_1; // @[VAluInt.scala 1085:21]
- wire _sraqs_srs_T_8 = sraqs_d[31] & io_in_signed; // @[VAluInt.scala 1088:41]
- wire [4:0] _sraqs_srs_T_11 = 5'h1f - sraqs_shamt_1; // @[VAluInt.scala 1089:68]
- wire [62:0] _sraqs_srs_T_12 = 63'hffffffff << _sraqs_srs_T_11; // @[VAluInt.scala 1089:47]
- wire [31:0] sraqs_srs_1 = _sraqs_srs_T_8 ? _sraqs_srs_T_12[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sraqs_sra_1 = sraqs_srs_1 | sraqs_srl_1; // @[VAluInt.scala 1090:23]
- wire [31:0] _sraqs_rbit_T_4 = {sraqs_d[30:0],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] _sraqs_rbit_T_5 = _sraqs_rbit_T_4 >> sraqs_shamt_1; // @[VAluInt.scala 1093:53]
- wire sraqs_rbit_1 = _sraqs_rbit_T_5[0]; // @[VAluInt.scala 1093:53]
- wire [31:0] _sraqs_rshf_T_5 = sraqs_sra_1 + 32'h1; // @[VAluInt.scala 1099:43]
- wire [31:0] sraqs_rshf_1 = io_in_round & sraqs_rbit_1 ? _sraqs_rshf_T_5 : sraqs_sra_1; // @[VAluInt.scala 1099:23]
- wire sraqs_is_umax_1 = _sataddsel_T_4 & sraqs_rshf_1 > 32'hff; // @[VAluInt.scala 1101:31]
- wire [31:0] _sraqs_is_smax_T_2 = io_in_round & sraqs_rbit_1 ? _sraqs_rshf_T_5 : sraqs_sra_1; // @[VAluInt.scala 1103:40]
- wire sraqs_is_smax_1 = io_in_signed & $signed(_sraqs_is_smax_T_2) > 32'sh7f; // @[VAluInt.scala 1103:31]
- wire sraqs_is_smin_1 = io_in_signed & $signed(_sraqs_is_smax_T_2) < $signed(sraqs_smin); // @[VAluInt.scala 1104:31]
- wire sraqs_is_norm_1 = ~(sraqs_is_umax_1 | sraqs_is_smax_1 | sraqs_is_smin_1); // @[VAluInt.scala 1105:23]
- wire [3:0] _sraqs_T_19 = {sraqs_is_umax_1,sraqs_is_smax_1,sraqs_is_smin_1,sraqs_is_norm_1}; // @[Cat.scala 31:58]
- wire [1:0] _sraqs_T_24 = _sraqs_T_19[0] + _sraqs_T_19[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _sraqs_T_26 = _sraqs_T_19[2] + _sraqs_T_19[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _sraqs_T_28 = _sraqs_T_24 + _sraqs_T_26; // @[Bitwise.scala 48:55]
- wire [7:0] _sraqs_r_T_11 = sraqs_is_umax_1 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sraqs_r_T_14 = sraqs_is_smax_1 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sraqs_r_T_15 = _sraqs_r_T_11 | _sraqs_r_T_14; // @[VAluInt.scala 1108:58]
- wire [7:0] _sraqs_r_T_18 = sraqs_is_smin_1 ? _sraqs_r_T_5[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sraqs_r_T_19 = _sraqs_r_T_15 | _sraqs_r_T_18; // @[VAluInt.scala 1109:58]
- wire [7:0] _sraqs_r_T_21 = sraqs_is_norm_1 ? sraqs_rshf_1[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] sraqs_1 = _sraqs_r_T_19 | _sraqs_r_T_21; // @[VAluInt.scala 1110:58]
- wire _sub_T_22 = satsubsel_1[2] & io_op_sub_subs; // @[VAluInt.scala 1348:36]
- wire [7:0] _sub_T_24 = _sub_T_22 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire _sub_T_26 = satsubsel_1[1] & io_op_sub_subs; // @[VAluInt.scala 1349:36]
- wire [6:0] _sub_T_28 = _sub_T_26 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_45 = {{1'd0}, _sub_T_28}; // @[VAluInt.scala 1348:89]
- wire [7:0] _sub_T_29 = _sub_T_24 | _GEN_45; // @[VAluInt.scala 1348:89]
- wire _sub_T_36 = satsubsel_1 == 3'h0 & io_op_sub_subs | io_op_sub_sub; // @[VAluInt.scala 1351:59]
- wire [7:0] _sub_T_38 = _sub_T_36 ? subtr_1[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sub_T_39 = _sub_T_29 | _sub_T_38; // @[VAluInt.scala 1350:68]
- wire [7:0] _sub_T_41 = io_op_sub_hsub ? subtr_1[8:1] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] sub_1 = _sub_T_39 | _sub_T_41; // @[VAluInt.scala 1351:97]
- wire subw_r_r_1_2 = subtr_1[9]; // @[Library.scala 64:25]
- wire [15:0] subw_r_1 = {subw_r_r_1_2,subw_r_r_1_2,subw_r_r_1_2,subw_r_r_1_2,subw_r_r_1_2,subw_r_r_1_2,subtr_1}; // @[Cat.scala 31:58]
- wire [15:0] subw_1 = io_op_sub_subw ? subw_r_1 : 16'h0; // @[Library.scala 32:8]
- wire _cmp_T_37 = io_op_cmp_eq & xeq_1; // @[Library.scala 36:8]
- wire _cmp_T_38 = io_op_cmp_ne & xne_1; // @[Library.scala 36:8]
- wire _cmp_T_39 = _cmp_T_37 | _cmp_T_38; // @[VAluInt.scala 1358:45]
- wire _cmp_T_41 = _cmp_T_4 & slt_1; // @[Library.scala 36:8]
- wire _cmp_T_42 = _cmp_T_39 | _cmp_T_41; // @[VAluInt.scala 1359:45]
- wire _cmp_T_45 = _cmp_T_8 & ult_1; // @[Library.scala 36:8]
- wire _cmp_T_46 = _cmp_T_42 | _cmp_T_45; // @[VAluInt.scala 1360:56]
- wire _cmp_T_48 = _cmp_T_11 & sle_1; // @[Library.scala 36:8]
- wire _cmp_T_49 = _cmp_T_46 | _cmp_T_48; // @[VAluInt.scala 1361:56]
- wire _cmp_T_52 = _cmp_T_15 & ule_1; // @[Library.scala 36:8]
- wire _cmp_T_53 = _cmp_T_49 | _cmp_T_52; // @[VAluInt.scala 1362:56]
- wire _cmp_T_55 = ~sle_1; // @[VAluInt.scala 1364:51]
- wire _cmp_T_56 = _cmp_T_18 & _cmp_T_55; // @[Library.scala 36:8]
- wire _cmp_T_57 = _cmp_T_53 | _cmp_T_56; // @[VAluInt.scala 1363:56]
- wire _cmp_T_60 = ~ule_1; // @[VAluInt.scala 1365:51]
- wire _cmp_T_61 = _cmp_T_23 & _cmp_T_60; // @[Library.scala 36:8]
- wire _cmp_T_62 = _cmp_T_57 | _cmp_T_61; // @[VAluInt.scala 1364:57]
- wire _cmp_T_64 = ~slt_1; // @[VAluInt.scala 1366:51]
- wire _cmp_T_65 = _cmp_T_27 & _cmp_T_64; // @[Library.scala 36:8]
- wire _cmp_T_66 = _cmp_T_62 | _cmp_T_65; // @[VAluInt.scala 1365:57]
- wire _cmp_T_69 = ~ult_1; // @[VAluInt.scala 1367:51]
- wire _cmp_T_70 = _cmp_T_32 & _cmp_T_69; // @[Library.scala 36:8]
- wire _cmp_T_71 = _cmp_T_66 | _cmp_T_70; // @[VAluInt.scala 1366:57]
- wire cmp_1 = io_in_sz[0] & _cmp_T_71; // @[VAluInt.scala 1357:30]
- wire [7:0] _log_T_115 = log_a[15:8] & log_b[15:8]; // @[VAluInt.scala 1371:42]
- wire [7:0] _log_T_116 = io_op_log_and ? _log_T_115 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_119 = log_a[15:8] | log_b[15:8]; // @[VAluInt.scala 1372:42]
- wire [7:0] _log_T_120 = io_op_log_or ? _log_T_119 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_121 = _log_T_116 | _log_T_120; // @[VAluInt.scala 1371:56]
- wire [7:0] _log_T_124 = log_a[15:8] ^ log_b[15:8]; // @[VAluInt.scala 1373:42]
- wire [7:0] _log_T_125 = io_op_log_xor ? _log_T_124 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_126 = _log_T_121 | _log_T_125; // @[VAluInt.scala 1372:56]
- wire [7:0] _log_T_129 = ~log_a[15:8]; // @[VAluInt.scala 1374:51]
- wire [7:0] _log_T_130 = io_in_sz[0] ? _log_T_129 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_131 = io_op_log_not ? _log_T_130 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_132 = _log_T_126 | _log_T_131; // @[VAluInt.scala 1373:56]
- wire _log_b_T_17 = ~log_b[8]; // @[VAluInt.scala 1151:23]
- wire [7:0] _log_b_T_26 = {log_a[14],log_a[15],log_a[12],log_a[13],log_a[10],log_a[11],log_a[8],log_a[9]}; // @[Cat.scala 31:58]
- wire [7:0] log_b_3 = ~log_b[8] ? log_a[15:8] : _log_b_T_26; // @[VAluInt.scala 1151:22]
- wire _log_c_T_13 = ~log_b[9]; // @[VAluInt.scala 1152:23]
- wire [7:0] _log_c_T_18 = {log_b_3[5:4],log_b_3[7:6],log_b_3[1:0],log_b_3[3:2]}; // @[Cat.scala 31:58]
- wire [7:0] log_c_2 = ~log_b[9] ? log_b_3 : _log_c_T_18; // @[VAluInt.scala 1152:22]
- wire _log_d_T_11 = ~log_b[10]; // @[VAluInt.scala 1153:23]
- wire [7:0] _log_d_T_14 = {log_c_2[3:0],log_c_2[7:4]}; // @[Cat.scala 31:58]
- wire [7:0] log_d_2 = ~log_b[10] ? log_c_2 : _log_d_T_14; // @[VAluInt.scala 1153:22]
- wire [7:0] _log_T_135 = io_op_log_rev ? log_d_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_136 = _log_T_132 | _log_T_135; // @[VAluInt.scala 1374:65]
- wire [7:0] _log_b_T_31 = {log_a[8],log_a[15:9]}; // @[Cat.scala 31:58]
- wire [7:0] log_b_4 = _log_b_T_17 ? log_a[15:8] : _log_b_T_31; // @[VAluInt.scala 1188:22]
- wire [7:0] _log_c_T_23 = {log_b_4[1:0],log_b_4[7:2]}; // @[Cat.scala 31:58]
- wire [7:0] log_c_3 = _log_c_T_13 ? log_b_4 : _log_c_T_23; // @[VAluInt.scala 1189:22]
- wire [7:0] _log_d_T_19 = {log_c_3[3:0],log_c_3[7:4]}; // @[Cat.scala 31:58]
- wire [7:0] log_d_3 = _log_d_T_11 ? log_c_3 : _log_d_T_19; // @[VAluInt.scala 1190:22]
- wire [7:0] _log_T_140 = io_in_sz[0] ? log_d_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_141 = io_op_log_ror ? _log_T_140 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_142 = _log_T_136 | _log_T_141; // @[VAluInt.scala 1375:60]
- wire [7:0] _GEN_46 = {{4'd0}, _log_T_129[7:4]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_51 = _GEN_46 & 8'hf; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_53 = {_log_T_129[3:0], 4'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clo_T_55 = _log_clo_T_53 & 8'hf0; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clo_T_56 = _log_clo_T_51 | _log_clo_T_55; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_47 = {{2'd0}, _log_clo_T_56[7:2]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_61 = _GEN_47 & 8'h33; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_63 = {_log_clo_T_56[5:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clo_T_65 = _log_clo_T_63 & 8'hcc; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clo_T_66 = _log_clo_T_61 | _log_clo_T_65; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_48 = {{1'd0}, _log_clo_T_66[7:1]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_71 = _GEN_48 & 8'h55; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_73 = {_log_clo_T_66[6:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clo_T_75 = _log_clo_T_73 & 8'haa; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clo_T_76 = _log_clo_T_71 | _log_clo_T_75; // @[Bitwise.scala 105:39]
- wire [8:0] _log_clo_T_77 = {1'h1,_log_clo_T_76}; // @[Cat.scala 31:58]
- wire [3:0] _log_clo_T_87 = _log_clo_T_77[7] ? 4'h7 : 4'h8; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_88 = _log_clo_T_77[6] ? 4'h6 : _log_clo_T_87; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_89 = _log_clo_T_77[5] ? 4'h5 : _log_clo_T_88; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_90 = _log_clo_T_77[4] ? 4'h4 : _log_clo_T_89; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_91 = _log_clo_T_77[3] ? 4'h3 : _log_clo_T_90; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_92 = _log_clo_T_77[2] ? 4'h2 : _log_clo_T_91; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_93 = _log_clo_T_77[1] ? 4'h1 : _log_clo_T_92; // @[Mux.scala 47:70]
- wire [3:0] log_clo_1 = _log_clo_T_77[0] ? 4'h0 : _log_clo_T_93; // @[Mux.scala 47:70]
- wire [7:0] _GEN_49 = {{4'd0}, log_a[15:12]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_49 = _GEN_49 & 8'hf; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_51 = {log_a[11:8], 4'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clz_T_53 = _log_clz_T_51 & 8'hf0; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clz_T_54 = _log_clz_T_49 | _log_clz_T_53; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_50 = {{2'd0}, _log_clz_T_54[7:2]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_59 = _GEN_50 & 8'h33; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_61 = {_log_clz_T_54[5:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clz_T_63 = _log_clz_T_61 & 8'hcc; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clz_T_64 = _log_clz_T_59 | _log_clz_T_63; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_51 = {{1'd0}, _log_clz_T_64[7:1]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_69 = _GEN_51 & 8'h55; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_71 = {_log_clz_T_64[6:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clz_T_73 = _log_clz_T_71 & 8'haa; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clz_T_74 = _log_clz_T_69 | _log_clz_T_73; // @[Bitwise.scala 105:39]
- wire [8:0] _log_clz_T_75 = {1'h1,_log_clz_T_74}; // @[Cat.scala 31:58]
- wire [3:0] _log_clz_T_85 = _log_clz_T_75[7] ? 4'h7 : 4'h8; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_86 = _log_clz_T_75[6] ? 4'h6 : _log_clz_T_85; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_87 = _log_clz_T_75[5] ? 4'h5 : _log_clz_T_86; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_88 = _log_clz_T_75[4] ? 4'h4 : _log_clz_T_87; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_89 = _log_clz_T_75[3] ? 4'h3 : _log_clz_T_88; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_90 = _log_clz_T_75[2] ? 4'h2 : _log_clz_T_89; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_91 = _log_clz_T_75[1] ? 4'h1 : _log_clz_T_90; // @[Mux.scala 47:70]
- wire [3:0] log_clz_1 = _log_clz_T_75[0] ? 4'h0 : _log_clz_T_91; // @[Mux.scala 47:70]
- wire [3:0] _log_T_146 = log_a[15] ? log_clo_1 : log_clz_1; // @[Library.scala 289:8]
- wire [3:0] _log_T_147 = io_in_sz[0] ? _log_T_146 : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _log_T_148 = io_op_log_clb ? _log_T_147 : 4'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_52 = {{4'd0}, _log_T_148}; // @[VAluInt.scala 1376:81]
- wire [7:0] _log_T_149 = _log_T_142 | _GEN_52; // @[VAluInt.scala 1376:81]
- wire [3:0] _log_T_199 = io_in_sz[0] ? log_clz_1 : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _log_T_200 = io_op_log_clz ? _log_T_199 : 4'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_56 = {{4'd0}, _log_T_200}; // @[VAluInt.scala 1377:69]
- wire [7:0] _log_T_201 = _log_T_149 | _GEN_56; // @[VAluInt.scala 1377:69]
- wire [1:0] _log_T_211 = log_a[8] + log_a[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_213 = log_a[10] + log_a[11]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_215 = _log_T_211 + _log_T_213; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_217 = log_a[12] + log_a[13]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_219 = log_a[14] + log_a[15]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_221 = _log_T_217 + _log_T_219; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_223 = _log_T_215 + _log_T_221; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_225 = io_op_log_cpop ? _log_T_223 : 4'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_57 = {{4'd0}, _log_T_225}; // @[VAluInt.scala 1378:69]
- wire [7:0] log_1 = _log_T_201 | _GEN_57; // @[VAluInt.scala 1378:69]
- wire [7:0] _shift_T_4 = io_op_shf_shl ? shl_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shift_T_5 = io_op_shf_shr ? shr_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shift_T_6 = _shift_T_4 | _shift_T_5; // @[VAluInt.scala 1383:35]
- wire [7:0] _shift_T_7 = io_op_shf_shf ? shf_1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] shift_1 = _shift_T_6 | _shift_T_7; // @[VAluInt.scala 1384:35]
- wire _alu_oh_T_14 = absd_1 != 8'h0; // @[VAluInt.scala 1388:30]
- wire _alu_oh_T_15 = add_1 != 8'h0; // @[VAluInt.scala 1389:30]
- wire _alu_oh_T_17 = dup_1 != 8'h0; // @[VAluInt.scala 1391:30]
- wire _alu_oh_T_18 = log_1 != 8'h0; // @[VAluInt.scala 1392:30]
- wire _alu_oh_T_19 = max_1 != 8'h0; // @[VAluInt.scala 1393:30]
- wire _alu_oh_T_20 = min_1 != 8'h0; // @[VAluInt.scala 1394:30]
- wire _alu_oh_T_21 = mul0_1 != 8'h0; // @[VAluInt.scala 1395:30]
- wire _alu_oh_T_23 = rsub_1 != 8'h0; // @[VAluInt.scala 1397:30]
- wire _alu_oh_T_24 = shift_1 != 8'h0; // @[VAluInt.scala 1398:30]
- wire _alu_oh_T_25 = srans_1 != 8'h0; // @[VAluInt.scala 1399:30]
- wire _alu_oh_T_26 = sraqs_1 != 8'h0; // @[VAluInt.scala 1400:30]
- wire _alu_oh_T_27 = sub_1 != 8'h0; // @[VAluInt.scala 1401:30]
- wire [6:0] alu_oh_lo_1 = {_alu_oh_T_21,1'h0,_alu_oh_T_23,_alu_oh_T_24,_alu_oh_T_25,_alu_oh_T_26,_alu_oh_T_27}; // @[Cat.scala 31:58]
- wire [13:0] alu_oh_1 = {_alu_oh_T_14,_alu_oh_T_15,cmp_1,_alu_oh_T_17,_alu_oh_T_18,_alu_oh_T_19,_alu_oh_T_20,
- alu_oh_lo_1}; // @[Cat.scala 31:58]
- wire [1:0] _T_162 = alu_oh_1[1] + alu_oh_1[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_58 = {{1'd0}, alu_oh_1[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_164 = _GEN_58 + _T_162; // @[Bitwise.scala 48:55]
- wire [1:0] _T_166 = alu_oh_1[3] + alu_oh_1[4]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_168 = alu_oh_1[5] + alu_oh_1[6]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_170 = _T_166 + _T_168; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_59 = {{1'd0}, _T_164[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_172 = _GEN_59 + _T_170; // @[Bitwise.scala 48:55]
- wire [1:0] _T_174 = alu_oh_1[8] + alu_oh_1[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_60 = {{1'd0}, alu_oh_1[7]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_176 = _GEN_60 + _T_174; // @[Bitwise.scala 48:55]
- wire [1:0] _T_178 = alu_oh_1[10] + alu_oh_1[11]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_180 = alu_oh_1[12] + alu_oh_1[13]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_182 = _T_178 + _T_180; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_61 = {{1'd0}, _T_176[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_184 = _GEN_61 + _T_182; // @[Bitwise.scala 48:55]
- wire [3:0] _T_186 = _T_172[2:0] + _T_184[2:0]; // @[Bitwise.scala 48:55]
- wire [7:0] _alu0_1_T = mul0_1 | absd_1; // @[VAluInt.scala 1405:23]
- wire [7:0] _alu0_1_T_1 = _alu0_1_T | add_1; // @[VAluInt.scala 1405:30]
- wire [7:0] _GEN_62 = {{7'd0}, cmp_1}; // @[VAluInt.scala 1405:36]
- wire [7:0] _alu0_1_T_2 = _alu0_1_T_1 | _GEN_62; // @[VAluInt.scala 1405:36]
- wire [7:0] _alu0_1_T_3 = _alu0_1_T_2 | dup_1; // @[VAluInt.scala 1405:42]
- wire [7:0] _alu0_1_T_4 = _alu0_1_T_3 | log_1; // @[VAluInt.scala 1405:48]
- wire [7:0] _alu0_1_T_5 = _alu0_1_T_4 | max_1; // @[VAluInt.scala 1405:54]
- wire [7:0] _alu0_1_T_6 = _alu0_1_T_5 | min_1; // @[VAluInt.scala 1405:60]
- wire [7:0] _alu0_1_T_8 = _alu0_1_T_6 | rsub_1; // @[VAluInt.scala 1405:73]
- wire [7:0] _alu0_1_T_9 = _alu0_1_T_8 | shift_1; // @[VAluInt.scala 1405:80]
- wire [7:0] _alu0_1_T_10 = _alu0_1_T_9 | srans_1; // @[VAluInt.scala 1405:88]
- wire [7:0] _alu0_1_T_11 = _alu0_1_T_10 | sraqs_1; // @[VAluInt.scala 1405:96]
- wire [7:0] _alu0_1_T_12 = _alu0_1_T_11 | sub_1; // @[VAluInt.scala 1405:104]
- wire [7:0] _alu0_1_T_14 = io_op_mv ? ina_b[15:8] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] alu0__1 = _alu0_1_T_12 | _alu0_1_T_14; // @[VAluInt.scala 1405:110]
- wire [7:0] _alu1_1_T_1 = io_op_mvp ? inb_b[15:8] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _alu1_1_T_2 = mul1_1 | _alu1_1_T_1; // @[VAluInt.scala 1408:23]
- wire [7:0] _alu1_1_T_4 = io_op_mv2 ? inc_b[15:8] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] alu1__1 = _alu1_1_T_2 | _alu1_1_T_4; // @[VAluInt.scala 1409:44]
- wire [7:0] _GEN_63 = {{7'd0}, mulh0_rnd_1}; // @[VAluInt.scala 1412:29]
- wire [7:0] _rnd0_1_T = dmulh0_rnd_1 | _GEN_63; // @[VAluInt.scala 1412:29]
- wire [7:0] _GEN_64 = {{7'd0}, shf_rnd_1}; // @[VAluInt.scala 1412:41]
- wire [7:0] rnd0__1 = _rnd0_1_T | _GEN_64; // @[VAluInt.scala 1412:41]
- wire [7:0] _GEN_65 = {{7'd0}, mulh1_rnd_1}; // @[VAluInt.scala 1413:29]
- wire [7:0] rnd1__1 = dmulh1_rnd_1 | _GEN_65; // @[VAluInt.scala 1413:29]
- wire [15:0] _aluw1_0_T = acc_1 | addw_1; // @[VAluInt.scala 1419:31]
- wire [15:0] _aluw1_0_T_1 = _aluw1_0_T | mulw_1; // @[VAluInt.scala 1419:38]
- wire [15:0] aluw1__0 = _aluw1_0_T_1 | subw_1; // @[VAluInt.scala 1419:45]
- wire add_sa_2 = add_a[23] & io_in_signed; // @[VAluInt.scala 973:29]
- wire add_sb_2 = add_b[23] & io_in_signed; // @[VAluInt.scala 974:29]
- wire [8:0] _adder_T_20 = {add_sa_2,add_a[23:16]}; // @[VAluInt.scala 975:44]
- wire [8:0] _adder_T_23 = {add_sb_2,add_b[23:16]}; // @[VAluInt.scala 975:78]
- wire [9:0] _adder_T_25 = $signed(_adder_T_20) + $signed(_adder_T_23); // @[VAluInt.scala 975:86]
- wire [9:0] adder_2 = _adder_T_25 + _GEN_6; // @[VAluInt.scala 975:93]
- wire [1:0] sataddmsb_2 = adder_2[8:7]; // @[VAluInt.scala 976:28]
- wire _sataddsel_T_15 = io_in_signed & sataddmsb_2 == 2'h2; // @[VAluInt.scala 978:21]
- wire _sataddsel_T_17 = io_in_signed & sataddmsb_2 == 2'h1; // @[VAluInt.scala 979:21]
- wire _sataddsel_T_20 = ~io_in_signed & sataddmsb_2[1]; // @[VAluInt.scala 980:21]
- wire [2:0] sataddsel_2 = {_sataddsel_T_15,_sataddsel_T_17,_sataddsel_T_20}; // @[Cat.scala 31:58]
- wire [1:0] _T_195 = sataddsel_2[1] + sataddsel_2[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_67 = {{1'd0}, sataddsel_2[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_197 = _GEN_67 + _T_195; // @[Bitwise.scala 48:55]
- wire sub_sa_2 = sub_a[23] & io_in_signed; // @[VAluInt.scala 983:29]
- wire sub_sb_2 = sub_b[23] & io_in_signed; // @[VAluInt.scala 984:29]
- wire [8:0] _subtr_T_20 = {sub_sa_2,sub_a[23:16]}; // @[VAluInt.scala 985:44]
- wire [8:0] _subtr_T_23 = {sub_sb_2,sub_b[23:16]}; // @[VAluInt.scala 985:78]
- wire [9:0] _subtr_T_25 = $signed(_subtr_T_20) - $signed(_subtr_T_23); // @[VAluInt.scala 985:86]
- wire [9:0] subtr_2 = _subtr_T_25 + _GEN_8; // @[VAluInt.scala 985:93]
- wire [1:0] satsubmsb_2 = subtr_2[8:7]; // @[VAluInt.scala 986:28]
- wire _satsubsel_T_15 = io_in_signed & satsubmsb_2 == 2'h2; // @[VAluInt.scala 988:21]
- wire _satsubsel_T_17 = io_in_signed & satsubmsb_2 == 2'h1; // @[VAluInt.scala 989:21]
- wire _satsubsel_T_20 = _sataddsel_T_4 & satsubmsb_2[1]; // @[VAluInt.scala 990:21]
- wire [2:0] satsubsel_2 = {_satsubsel_T_15,_satsubsel_T_17,_satsubsel_T_20}; // @[Cat.scala 31:58]
- wire [1:0] _T_206 = satsubsel_2[1] + satsubsel_2[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_69 = {{1'd0}, satsubsel_2[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_208 = _GEN_69 + _T_206; // @[Bitwise.scala 48:55]
- wire [7:0] rsubtr_2 = rsub_b[23:16] - rsub_a[23:16]; // @[VAluInt.scala 993:32]
- wire xeq_2 = cmp_a[23:16] == cmp_b[23:16]; // @[VAluInt.scala 995:28]
- wire xne_2 = cmp_a[23:16] != cmp_b[23:16]; // @[VAluInt.scala 996:28]
- wire [7:0] _slt_T_9 = cmp_a[23:16]; // @[VAluInt.scala 997:34]
- wire [7:0] _slt_T_11 = cmp_b[23:16]; // @[VAluInt.scala 997:56]
- wire slt_2 = $signed(_slt_T_9) < $signed(_slt_T_11); // @[VAluInt.scala 997:37]
- wire ult_2 = cmp_a[23:16] < cmp_b[23:16]; // @[VAluInt.scala 998:28]
- wire sle_2 = slt_2 | xeq_2; // @[VAluInt.scala 999:21]
- wire ule_2 = ult_2 | xeq_2; // @[VAluInt.scala 1000:21]
- wire sult_2 = io_in_signed ? slt_2 : ult_2; // @[VAluInt.scala 1002:21]
- wire [14:0] _GEN_23 = {{7'd0}, shl_a[23:16]}; // @[VAluInt.scala 1062:29]
- wire [14:0] _shl_T_8 = _GEN_23 << shl_b[18:16]; // @[VAluInt.scala 1062:29]
- wire [7:0] shl_2 = _shl_T_8[7:0]; // @[VAluInt.scala 1062:49]
- wire [3:0] _GEN_70 = {{1'd0}, shl_b[18:16]}; // @[VAluInt.scala 1063:40]
- wire [3:0] _sln_T_13 = 4'h8 - _GEN_70; // @[VAluInt.scala 1063:40]
- wire [22:0] _GEN_24 = {{15'd0}, shl_a[23:16]}; // @[VAluInt.scala 1063:29]
- wire [22:0] _sln_T_14 = _GEN_24 << _sln_T_13; // @[VAluInt.scala 1063:29]
- wire [14:0] sln_2 = _sln_T_14[14:0]; // @[VAluInt.scala 1063:60]
- wire [7:0] srl_2 = shr_a[23:16] >> shr_b[18:16]; // @[VAluInt.scala 1064:28]
- wire [2:0] _srs_T_18 = 3'h7 - shr_b[18:16]; // @[VAluInt.scala 1065:66]
- wire [14:0] _srs_T_19 = 15'hff << _srs_T_18; // @[VAluInt.scala 1065:49]
- wire [7:0] srs_2 = shr_a[23] ? _srs_T_19[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] sra_2 = srs_2 | srl_2; // @[VAluInt.scala 1066:21]
- wire [7:0] shf_slnsz_2 = sln_2[7:0]; // @[VAluInt.scala 1010:24]
- wire shf_input_neg_2 = shl_a[23]; // @[VAluInt.scala 1011:26]
- wire shf_input_zero_2 = shl_a[23:16] == 8'h0; // @[VAluInt.scala 1012:28]
- wire shf_shamt_neg_2 = shl_b[23]; // @[VAluInt.scala 1013:26]
- wire [7:0] _shf_shamt_negsat_T_10 = shl_b[23:16]; // @[VAluInt.scala 1017:32]
- wire shf_shamt_negsat_4 = $signed(_shf_shamt_negsat_T_10) <= -8'sh7; // @[VAluInt.scala 1017:39]
- wire shf_shamt_possat_4 = $signed(_shf_shamt_negsat_T_10) >= 8'sh7; // @[VAluInt.scala 1018:39]
- wire [2:0] _shf_signb_T_11 = shl_b[18:16] - 3'h1; // @[VAluInt.scala 1019:65]
- wire [7:0] shf_signb_2 = 8'hff >> _shf_signb_T_11; // @[VAluInt.scala 1019:36]
- wire _shf_possat_T_30 = ~shf_input_zero_2; // @[VAluInt.scala 1020:112]
- wire shf_possat_4 = shf_shamt_neg_2 & ~shf_input_neg_2 & (shf_shamt_negsat_4 | sln_2[14:7] != 8'h0) & ~
- shf_input_zero_2; // @[VAluInt.scala 1020:109]
- wire shf_negsat_2 = shf_shamt_neg_2 & shf_input_neg_2 & (shf_shamt_negsat_4 | sln_2[14:7] != shf_signb_2); // @[VAluInt.scala 1021:48]
- wire _shf_rs_T_44 = ~shf_shamt_neg_2; // @[VAluInt.scala 1028:23]
- wire _shf_rs_T_46 = ~shf_shamt_neg_2 & ~shf_shamt_possat_4; // @[VAluInt.scala 1028:34]
- wire [7:0] _shf_rs_T_47 = _shf_rs_T_46 ? sra_2 : 8'h0; // @[Library.scala 32:8]
- wire _shf_rs_T_50 = _shf_rs_T_44 & shf_shamt_possat_4 & shf_input_neg_2; // @[VAluInt.scala 1029:51]
- wire [7:0] _shf_rs_T_52 = _shf_rs_T_50 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_rs_T_53 = _shf_rs_T_47 | _shf_rs_T_52; // @[VAluInt.scala 1028:57]
- wire _shf_rs_T_57 = shf_shamt_neg_2 & ~shf_possat_4 & ~shf_negsat_2; // @[VAluInt.scala 1030:45]
- wire [7:0] _shf_rs_T_58 = _shf_rs_T_57 ? shf_slnsz_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_rs_T_59 = _shf_rs_T_53 | _shf_rs_T_58; // @[VAluInt.scala 1029:79]
- wire _shf_rs_T_60 = shf_shamt_neg_2 & shf_possat_4; // @[VAluInt.scala 1031:34]
- wire [7:0] _shf_rs_T_61 = _shf_rs_T_60 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_rs_T_62 = _shf_rs_T_59 | _shf_rs_T_61; // @[VAluInt.scala 1030:64]
- wire _shf_rs_T_63 = shf_shamt_neg_2 & shf_negsat_2; // @[VAluInt.scala 1032:34]
- wire [7:0] _shf_rs_T_64 = _shf_rs_T_63 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] shf_rs_2 = _shf_rs_T_62 | _shf_rs_T_64; // @[VAluInt.scala 1031:53]
- wire shf_shamt_negsat_5 = $signed(_shf_shamt_negsat_T_10) <= $signed(_GEN_11); // @[VAluInt.scala 1035:39]
- wire shf_shamt_possat_5 = $signed(_shf_shamt_negsat_T_10) >= 8'sh8; // @[VAluInt.scala 1036:39]
- wire shf_possat_5 = shf_shamt_neg_2 & (shf_shamt_negsat_5 | sln_2[14:8] != 7'h0) & _shf_possat_T_30; // @[VAluInt.scala 1037:89]
- wire _shf_ru_T_24 = _shf_rs_T_44 & ~shf_shamt_possat_5; // @[VAluInt.scala 1041:34]
- wire [7:0] _shf_ru_T_25 = _shf_ru_T_24 ? srl_2 : 8'h0; // @[Library.scala 32:8]
- wire _shf_ru_T_27 = shf_shamt_neg_2 & ~shf_possat_5; // @[VAluInt.scala 1042:34]
- wire [7:0] _shf_ru_T_28 = _shf_ru_T_27 ? shf_slnsz_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_ru_T_29 = _shf_ru_T_25 | _shf_ru_T_28; // @[VAluInt.scala 1041:57]
- wire _shf_ru_T_30 = shf_shamt_neg_2 & shf_possat_5; // @[VAluInt.scala 1043:34]
- wire [7:0] _shf_ru_T_31 = _shf_ru_T_30 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] shf_ru_2 = _shf_ru_T_29 | _shf_ru_T_31; // @[VAluInt.scala 1042:53]
- wire [7:0] shf_2 = io_in_signed ? shf_rs_2 : shf_ru_2; // @[VAluInt.scala 1045:12]
- wire [7:0] shr_2 = io_in_signed ? sra_2 : srl_2; // @[VAluInt.scala 1068:20]
- wire shf_rnd_shamt_zero_2 = shl_b[23:16] == 8'h0; // @[VAluInt.scala 1053:28]
- wire [7:0] _shf_rnd_rbit_T_12 = {shl_a[22:16],shf_input_neg_2}; // @[Cat.scala 31:58]
- wire [7:0] _shf_rnd_rbit_T_14 = _shf_rnd_rbit_T_12 >> shl_b[18:16]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_rbit_2 = _shf_rnd_rbit_T_14[0]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_shamt_possat_2 = io_in_signed ? shf_shamt_possat_5 : $signed(_shf_shamt_negsat_T_10) > 8'sh8; // @[VAluInt.scala 1055:31]
- wire _shf_rnd_r_T_27 = io_in_round & ~shf_rnd_shamt_possat_2 & _shf_rs_T_44 & ~shf_rnd_shamt_zero_2; // @[VAluInt.scala 1056:60]
- wire _shf_rnd_r_T_28 = _shf_rnd_r_T_27 & shf_rnd_rbit_2; // @[Library.scala 36:8]
- wire _shf_rnd_r_T_31 = io_in_round & shf_rnd_shamt_possat_2 & shf_input_neg_2 & io_in_signed; // @[VAluInt.scala 1057:59]
- wire shf_rnd_2 = _shf_rnd_r_T_28 | _shf_rnd_r_T_31; // @[VAluInt.scala 1056:82]
- wire _mul0_as_T_7 = io_in_signed & mul0_a[23]; // @[VAluInt.scala 1199:32]
- wire _mul0_bs_T_7 = io_in_signed & mul0_b[23]; // @[VAluInt.scala 1200:32]
- wire mul0_sign_2 = mul0_a[23] != mul0_b[23] & mul0_a[23:16] != 8'h0 & mul0_b[23:16] != 8'h0; // @[VAluInt.scala 1201:70]
- wire [8:0] _prod0_T_6 = {_mul0_as_T_7,mul0_a[23:16]}; // @[VAluInt.scala 1202:28]
- wire [8:0] _prod0_T_7 = {_mul0_bs_T_7,mul0_b[23:16]}; // @[VAluInt.scala 1202:45]
- wire [17:0] prod0_2 = $signed(_prod0_T_6) * $signed(_prod0_T_7); // @[VAluInt.scala 1202:53]
- wire [7:0] prodh0_2 = prod0_2[15:8]; // @[VAluInt.scala 1203:25]
- wire [7:0] proddh0_2 = prod0_2[14:7]; // @[VAluInt.scala 1204:26]
- wire _mul1_as_T_7 = io_in_signed & mul1_a[23]; // @[VAluInt.scala 1206:32]
- wire _mul1_bs_T_7 = io_in_signed & mul1_b[23]; // @[VAluInt.scala 1207:32]
- wire mul1_sign_2 = mul1_a[23] != mul1_b[23] & mul1_a[23:16] != 8'h0 & mul1_b[23:16] != 8'h0; // @[VAluInt.scala 1208:70]
- wire [8:0] _prod1_T_6 = {_mul1_as_T_7,mul1_a[23:16]}; // @[VAluInt.scala 1209:28]
- wire [8:0] _prod1_T_7 = {_mul1_bs_T_7,mul1_b[23:16]}; // @[VAluInt.scala 1209:45]
- wire [17:0] prod1_2 = $signed(_prod1_T_6) * $signed(_prod1_T_7); // @[VAluInt.scala 1209:53]
- wire [7:0] prodh1_2 = prod1_2[15:8]; // @[VAluInt.scala 1210:25]
- wire [7:0] proddh1_2 = prod1_2[14:7]; // @[VAluInt.scala 1211:26]
- wire _muls0_umax_T_5 = prodh0_2 != 8'h0; // @[VAluInt.scala 1213:42]
- wire muls0_umax_2 = _sataddsel_T_4 & prodh0_2 != 8'h0; // @[VAluInt.scala 1213:32]
- wire muls0_smax_2 = io_in_signed & ~mul0_sign_2 & (prod0_2[7] | _muls0_umax_T_5); // @[VAluInt.scala 1214:46]
- wire muls0_smin_2 = io_in_signed & mul0_sign_2 & (~prod0_2[7] | prodh0_2 != 8'hff); // @[VAluInt.scala 1215:46]
- wire muls0_base_2 = ~(muls0_umax_2 | muls0_smax_2 | muls0_smin_2); // @[VAluInt.scala 1216:24]
- wire [3:0] _T_214 = {muls0_umax_2,muls0_smax_2,muls0_smin_2,muls0_base_2}; // @[Cat.scala 31:58]
- wire [1:0] _T_219 = _T_214[0] + _T_214[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_221 = _T_214[2] + _T_214[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_223 = _T_219 + _T_221; // @[Bitwise.scala 48:55]
- wire _muls1_umax_T_5 = prodh1_2 != 8'h0; // @[VAluInt.scala 1219:42]
- wire muls1_umax_2 = _sataddsel_T_4 & prodh1_2 != 8'h0; // @[VAluInt.scala 1219:32]
- wire muls1_smax_2 = io_in_signed & ~mul1_sign_2 & (prod1_2[7] | _muls1_umax_T_5); // @[VAluInt.scala 1220:46]
- wire muls1_smin_2 = io_in_signed & mul1_sign_2 & (~prod1_2[7] | prodh1_2 != 8'hff); // @[VAluInt.scala 1221:46]
- wire muls1_base_2 = ~(muls1_umax_2 | muls1_smax_2 | muls1_smin_2); // @[VAluInt.scala 1222:24]
- wire [3:0] _T_229 = {muls1_umax_2,muls1_smax_2,muls1_smin_2,muls1_base_2}; // @[Cat.scala 31:58]
- wire [1:0] _T_234 = _T_229[0] + _T_229[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_236 = _T_229[2] + _T_229[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_238 = _T_234 + _T_236; // @[Bitwise.scala 48:55]
- wire dmulh0_possat_2 = mul0_a[23:16] == 8'h80 & mul0_b[23:16] == 8'h80; // @[VAluInt.scala 1227:50]
- wire dmulh1_possat_2 = mul1_a[23:16] == 8'h80 & mul1_b[23:16] == 8'h80; // @[VAluInt.scala 1229:50]
- wire _dmulh0_T_10 = ~dmulh0_possat_2; // @[VAluInt.scala 1231:26]
- wire [7:0] _dmulh0_T_11 = _dmulh0_T_10 ? proddh0_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh0_T_14 = dmulh0_possat_2 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] dmulh0_2 = _dmulh0_T_11 | _dmulh0_T_14; // @[VAluInt.scala 1231:51]
- wire _dmulh1_T_10 = ~dmulh1_possat_2; // @[VAluInt.scala 1234:26]
- wire [7:0] _dmulh1_T_11 = _dmulh1_T_10 ? proddh1_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh1_T_14 = dmulh1_possat_2 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] dmulh1_2 = _dmulh1_T_11 | _dmulh1_T_14; // @[VAluInt.scala 1234:51]
- wire [7:0] _muls0_T_21 = muls0_umax_2 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [6:0] _muls0_T_23 = muls0_smax_2 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_72 = {{1'd0}, _muls0_T_23}; // @[VAluInt.scala 1240:51]
- wire [7:0] _muls0_T_24 = _muls0_T_21 | _GEN_72; // @[VAluInt.scala 1240:51]
- wire [7:0] _muls0_T_26 = muls0_smin_2 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _muls0_T_27 = _muls0_T_24 | _muls0_T_26; // @[VAluInt.scala 1241:57]
- wire [7:0] _muls0_T_29 = muls0_base_2 ? prod0_2[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] muls0_2 = _muls0_T_27 | _muls0_T_29; // @[VAluInt.scala 1242:71]
- wire [7:0] _muls1_T_21 = muls1_umax_2 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [6:0] _muls1_T_23 = muls1_smax_2 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_73 = {{1'd0}, _muls1_T_23}; // @[VAluInt.scala 1245:51]
- wire [7:0] _muls1_T_24 = _muls1_T_21 | _GEN_73; // @[VAluInt.scala 1245:51]
- wire [7:0] _muls1_T_26 = muls1_smin_2 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _muls1_T_27 = _muls1_T_24 | _muls1_T_26; // @[VAluInt.scala 1246:57]
- wire [7:0] _muls1_T_29 = muls1_base_2 ? prod1_2[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] muls1_2 = _muls1_T_27 | _muls1_T_29; // @[VAluInt.scala 1247:71]
- wire _dmulh0_rnd_T_30 = io_in_round & io_op_mul0_dmulh & io_in_sz[0] & _dmulh0_T_10; // @[VAluInt.scala 1250:72]
- wire _dmulh0_rnd_T_33 = ~prod0_2[6]; // @[VAluInt.scala 1252:40]
- wire [7:0] _dmulh0_rnd_T_35 = _dmulh0_rnd_T_33 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh0_rnd_T_37 = prod0_2[6] ? 8'h1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh0_rnd_T_38 = io_in_negative & mul0_sign_2 ? _dmulh0_rnd_T_35 : _dmulh0_rnd_T_37; // @[VAluInt.scala 1251:33]
- wire [7:0] dmulh0_rnd_2 = _dmulh0_rnd_T_30 ? _dmulh0_rnd_T_38 : 8'h0; // @[Library.scala 32:8]
- wire _dmulh1_rnd_T_30 = io_in_round & io_op_mul1_dmulh & io_in_sz[0] & _dmulh1_T_10; // @[VAluInt.scala 1255:72]
- wire _dmulh1_rnd_T_33 = ~prod1_2[6]; // @[VAluInt.scala 1257:40]
- wire [7:0] _dmulh1_rnd_T_35 = _dmulh1_rnd_T_33 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh1_rnd_T_37 = prod1_2[6] ? 8'h1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh1_rnd_T_38 = io_in_negative & mul1_sign_2 ? _dmulh1_rnd_T_35 : _dmulh1_rnd_T_37; // @[VAluInt.scala 1256:33]
- wire [7:0] dmulh1_rnd_2 = _dmulh1_rnd_T_30 ? _dmulh1_rnd_T_38 : 8'h0; // @[Library.scala 32:8]
- wire mulh0_rnd_2 = io_in_round & io_op_mul0_mulh & prod0_2[7]; // @[VAluInt.scala 1260:48]
- wire mulh1_rnd_2 = io_in_round & io_op_mul1_mulh & prod1_2[7]; // @[VAluInt.scala 1261:48]
- wire [7:0] _absd_T_5 = sult_2 ? rsubtr_2 : subtr_2[7:0]; // @[VAluInt.scala 1265:39]
- wire [7:0] absd_2 = io_op_absd ? _absd_T_5 : 8'h0; // @[Library.scala 32:8]
- wire _acc_T_14 = io_in_signed & acc_b[23]; // @[VAluInt.scala 1270:55]
- wire [8:0] _acc_T_16 = {_acc_T_14,acc_b[23:16]}; // @[Cat.scala 31:58]
- wire acc_r_r_2_2 = _acc_T_16[8]; // @[Library.scala 64:25]
- wire [15:0] acc_r_2 = {acc_r_r_2_2,acc_r_r_2_2,acc_r_r_2_2,acc_r_r_2_2,acc_r_r_2_2,acc_r_r_2_2,acc_r_r_2_2,_acc_T_14,
- acc_b[23:16]}; // @[Cat.scala 31:58]
- wire [15:0] acc_2 = acc_a[31:16] + acc_r_2; // @[VAluInt.scala 1270:34]
- wire _add_T_47 = sataddsel_2[2] & io_op_add_adds; // @[VAluInt.scala 1279:36]
- wire [7:0] _add_T_49 = _add_T_47 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire _add_T_51 = sataddsel_2[1] & io_op_add_adds; // @[VAluInt.scala 1280:36]
- wire [6:0] _add_T_53 = _add_T_51 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_74 = {{1'd0}, _add_T_53}; // @[VAluInt.scala 1279:89]
- wire [7:0] _add_T_54 = _add_T_49 | _GEN_74; // @[VAluInt.scala 1279:89]
- wire _add_T_56 = sataddsel_2[0] & io_op_add_adds; // @[VAluInt.scala 1281:36]
- wire [7:0] _add_T_58 = _add_T_56 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _add_T_59 = _add_T_54 | _add_T_58; // @[VAluInt.scala 1280:75]
- wire _add_T_63 = sataddsel_2 == 3'h0 & io_op_add_adds | io_op_add_add | io_op_add_add3; // @[VAluInt.scala 1282:76]
- wire [7:0] _add_T_65 = _add_T_63 ? adder_2[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _add_T_66 = _add_T_59 | _add_T_65; // @[VAluInt.scala 1281:69]
- wire [7:0] _add_T_68 = io_op_add_hadd ? adder_2[8:1] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] add_2 = _add_T_66 | _add_T_68; // @[VAluInt.scala 1282:115]
- wire addw_r_r_2_2 = adder_2[9]; // @[Library.scala 64:25]
- wire [15:0] addw_r_2 = {addw_r_r_2_2,addw_r_r_2_2,addw_r_r_2_2,addw_r_r_2_2,addw_r_r_2_2,addw_r_r_2_2,adder_2}; // @[Cat.scala 31:58]
- wire [15:0] addw_2 = io_op_add_addw ? addw_r_2 : 16'h0; // @[Library.scala 32:8]
- wire [7:0] dup_2 = io_op_dup ? io_read_1_data[23:16] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _max_T_8 = sult_2 ? cmp_b[23:16] : cmp_a[23:16]; // @[VAluInt.scala 1290:37]
- wire [7:0] max_2 = io_op_max ? _max_T_8 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _min_T_8 = sult_2 ? cmp_a[23:16] : cmp_b[23:16]; // @[VAluInt.scala 1291:37]
- wire [7:0] min_2 = io_op_min ? _min_T_8 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_18 = _mul0_T ? prod0_2[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_19 = io_op_mul0_dmulh ? dmulh0_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_20 = _mul0_T_18 | _mul0_T_19; // @[VAluInt.scala 1293:79]
- wire [7:0] _mul0_T_21 = io_op_mul0_mulh ? prodh0_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_22 = _mul0_T_20 | _mul0_T_21; // @[VAluInt.scala 1294:50]
- wire [7:0] _mul0_T_23 = io_op_mul0_muls ? muls0_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] mul0_2 = _mul0_T_22 | _mul0_T_23; // @[VAluInt.scala 1295:48]
- wire [7:0] _mul1_T_15 = io_op_mul1_mul ? prod1_2[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul1_T_16 = io_op_mul1_dmulh ? dmulh1_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul1_T_17 = _mul1_T_15 | _mul1_T_16; // @[VAluInt.scala 1298:60]
- wire [7:0] _mul1_T_18 = io_op_mul1_mulh ? prodh1_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul1_T_19 = _mul1_T_17 | _mul1_T_18; // @[VAluInt.scala 1299:50]
- wire [7:0] _mul1_T_20 = io_op_mul1_muls ? muls1_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] mul1_2 = _mul1_T_19 | _mul1_T_20; // @[VAluInt.scala 1300:48]
- wire [15:0] mulw_2 = io_op_mul0_mulw ? prod0_2[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [7:0] rsub_2 = io_op_rsub_rsub ? rsubtr_2 : 8'h0; // @[Library.scala 32:8]
- wire [3:0] srans_shamt_2 = srans_b[19:16]; // @[VAluInt.scala 1084:22]
- wire [15:0] srans_srl_2 = srans_a[31:16] >> srans_shamt_2; // @[VAluInt.scala 1085:21]
- wire _srans_srs_T_15 = srans_a[31] & io_in_signed; // @[VAluInt.scala 1088:41]
- wire [3:0] _srans_srs_T_18 = 4'hf - srans_shamt_2; // @[VAluInt.scala 1089:68]
- wire [30:0] _srans_srs_T_19 = 31'hffff << _srans_srs_T_18; // @[VAluInt.scala 1089:47]
- wire [15:0] srans_srs_2 = _srans_srs_T_15 ? _srans_srs_T_19[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] srans_sra_2 = srans_srs_2 | srans_srl_2; // @[VAluInt.scala 1090:23]
- wire [15:0] _srans_rbit_T_7 = {srans_a[30:16],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] _srans_rbit_T_8 = _srans_rbit_T_7 >> srans_shamt_2; // @[VAluInt.scala 1093:53]
- wire srans_rbit_2 = _srans_rbit_T_8[0]; // @[VAluInt.scala 1093:53]
- wire [15:0] _srans_rshf_T_8 = srans_sra_2 + 16'h1; // @[VAluInt.scala 1099:43]
- wire [15:0] srans_rshf_2 = io_in_round & srans_rbit_2 ? _srans_rshf_T_8 : srans_sra_2; // @[VAluInt.scala 1099:23]
- wire srans_is_umax_2 = _sataddsel_T_4 & srans_rshf_2 > 16'hff; // @[VAluInt.scala 1101:31]
- wire [15:0] _srans_is_smax_T_4 = io_in_round & srans_rbit_2 ? _srans_rshf_T_8 : srans_sra_2; // @[VAluInt.scala 1103:40]
- wire srans_is_smax_2 = io_in_signed & $signed(_srans_is_smax_T_4) > 16'sh7f; // @[VAluInt.scala 1103:31]
- wire srans_is_smin_2 = io_in_signed & $signed(_srans_is_smax_T_4) < $signed(srans_smin); // @[VAluInt.scala 1104:31]
- wire srans_is_norm_2 = ~(srans_is_umax_2 | srans_is_smax_2 | srans_is_smin_2); // @[VAluInt.scala 1105:23]
- wire [3:0] _srans_T_36 = {srans_is_umax_2,srans_is_smax_2,srans_is_smin_2,srans_is_norm_2}; // @[Cat.scala 31:58]
- wire [1:0] _srans_T_41 = _srans_T_36[0] + _srans_T_36[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _srans_T_43 = _srans_T_36[2] + _srans_T_36[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _srans_T_45 = _srans_T_41 + _srans_T_43; // @[Bitwise.scala 48:55]
- wire [7:0] _srans_r_T_22 = srans_is_umax_2 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _srans_r_T_25 = srans_is_smax_2 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _srans_r_T_26 = _srans_r_T_22 | _srans_r_T_25; // @[VAluInt.scala 1108:58]
- wire [7:0] _srans_r_T_29 = srans_is_smin_2 ? _srans_r_T_5[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _srans_r_T_30 = _srans_r_T_26 | _srans_r_T_29; // @[VAluInt.scala 1109:58]
- wire [7:0] _srans_r_T_32 = srans_is_norm_2 ? srans_rshf_2[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] srans_2 = _srans_r_T_30 | _srans_r_T_32; // @[VAluInt.scala 1110:58]
- wire [4:0] sraqs_shamt_2 = sraqs_b[20:16]; // @[VAluInt.scala 1084:22]
- wire [31:0] sraqs_srl_2 = sraqs_c >> sraqs_shamt_2; // @[VAluInt.scala 1085:21]
- wire _sraqs_srs_T_15 = sraqs_c[31] & io_in_signed; // @[VAluInt.scala 1088:41]
- wire [4:0] _sraqs_srs_T_18 = 5'h1f - sraqs_shamt_2; // @[VAluInt.scala 1089:68]
- wire [62:0] _sraqs_srs_T_19 = 63'hffffffff << _sraqs_srs_T_18; // @[VAluInt.scala 1089:47]
- wire [31:0] sraqs_srs_2 = _sraqs_srs_T_15 ? _sraqs_srs_T_19[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sraqs_sra_2 = sraqs_srs_2 | sraqs_srl_2; // @[VAluInt.scala 1090:23]
- wire [31:0] _sraqs_rbit_T_7 = {sraqs_c[30:0],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] _sraqs_rbit_T_8 = _sraqs_rbit_T_7 >> sraqs_shamt_2; // @[VAluInt.scala 1093:53]
- wire sraqs_rbit_2 = _sraqs_rbit_T_8[0]; // @[VAluInt.scala 1093:53]
- wire [31:0] _sraqs_rshf_T_8 = sraqs_sra_2 + 32'h1; // @[VAluInt.scala 1099:43]
- wire [31:0] sraqs_rshf_2 = io_in_round & sraqs_rbit_2 ? _sraqs_rshf_T_8 : sraqs_sra_2; // @[VAluInt.scala 1099:23]
- wire sraqs_is_umax_2 = _sataddsel_T_4 & sraqs_rshf_2 > 32'hff; // @[VAluInt.scala 1101:31]
- wire [31:0] _sraqs_is_smax_T_4 = io_in_round & sraqs_rbit_2 ? _sraqs_rshf_T_8 : sraqs_sra_2; // @[VAluInt.scala 1103:40]
- wire sraqs_is_smax_2 = io_in_signed & $signed(_sraqs_is_smax_T_4) > 32'sh7f; // @[VAluInt.scala 1103:31]
- wire sraqs_is_smin_2 = io_in_signed & $signed(_sraqs_is_smax_T_4) < $signed(sraqs_smin); // @[VAluInt.scala 1104:31]
- wire sraqs_is_norm_2 = ~(sraqs_is_umax_2 | sraqs_is_smax_2 | sraqs_is_smin_2); // @[VAluInt.scala 1105:23]
- wire [3:0] _sraqs_T_36 = {sraqs_is_umax_2,sraqs_is_smax_2,sraqs_is_smin_2,sraqs_is_norm_2}; // @[Cat.scala 31:58]
- wire [1:0] _sraqs_T_41 = _sraqs_T_36[0] + _sraqs_T_36[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _sraqs_T_43 = _sraqs_T_36[2] + _sraqs_T_36[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _sraqs_T_45 = _sraqs_T_41 + _sraqs_T_43; // @[Bitwise.scala 48:55]
- wire [7:0] _sraqs_r_T_22 = sraqs_is_umax_2 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sraqs_r_T_25 = sraqs_is_smax_2 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sraqs_r_T_26 = _sraqs_r_T_22 | _sraqs_r_T_25; // @[VAluInt.scala 1108:58]
- wire [7:0] _sraqs_r_T_29 = sraqs_is_smin_2 ? _sraqs_r_T_5[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sraqs_r_T_30 = _sraqs_r_T_26 | _sraqs_r_T_29; // @[VAluInt.scala 1109:58]
- wire [7:0] _sraqs_r_T_32 = sraqs_is_norm_2 ? sraqs_rshf_2[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] sraqs_2 = _sraqs_r_T_30 | _sraqs_r_T_32; // @[VAluInt.scala 1110:58]
- wire _sub_T_43 = satsubsel_2[2] & io_op_sub_subs; // @[VAluInt.scala 1348:36]
- wire [7:0] _sub_T_45 = _sub_T_43 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire _sub_T_47 = satsubsel_2[1] & io_op_sub_subs; // @[VAluInt.scala 1349:36]
- wire [6:0] _sub_T_49 = _sub_T_47 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_75 = {{1'd0}, _sub_T_49}; // @[VAluInt.scala 1348:89]
- wire [7:0] _sub_T_50 = _sub_T_45 | _GEN_75; // @[VAluInt.scala 1348:89]
- wire _sub_T_57 = satsubsel_2 == 3'h0 & io_op_sub_subs | io_op_sub_sub; // @[VAluInt.scala 1351:59]
- wire [7:0] _sub_T_59 = _sub_T_57 ? subtr_2[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sub_T_60 = _sub_T_50 | _sub_T_59; // @[VAluInt.scala 1350:68]
- wire [7:0] _sub_T_62 = io_op_sub_hsub ? subtr_2[8:1] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] sub_2 = _sub_T_60 | _sub_T_62; // @[VAluInt.scala 1351:97]
- wire subw_r_r_2_2 = subtr_2[9]; // @[Library.scala 64:25]
- wire [15:0] subw_r_2 = {subw_r_r_2_2,subw_r_r_2_2,subw_r_r_2_2,subw_r_r_2_2,subw_r_r_2_2,subw_r_r_2_2,subtr_2}; // @[Cat.scala 31:58]
- wire [15:0] subw_2 = io_op_sub_subw ? subw_r_2 : 16'h0; // @[Library.scala 32:8]
- wire _cmp_T_73 = io_op_cmp_eq & xeq_2; // @[Library.scala 36:8]
- wire _cmp_T_74 = io_op_cmp_ne & xne_2; // @[Library.scala 36:8]
- wire _cmp_T_75 = _cmp_T_73 | _cmp_T_74; // @[VAluInt.scala 1358:45]
- wire _cmp_T_77 = _cmp_T_4 & slt_2; // @[Library.scala 36:8]
- wire _cmp_T_78 = _cmp_T_75 | _cmp_T_77; // @[VAluInt.scala 1359:45]
- wire _cmp_T_81 = _cmp_T_8 & ult_2; // @[Library.scala 36:8]
- wire _cmp_T_82 = _cmp_T_78 | _cmp_T_81; // @[VAluInt.scala 1360:56]
- wire _cmp_T_84 = _cmp_T_11 & sle_2; // @[Library.scala 36:8]
- wire _cmp_T_85 = _cmp_T_82 | _cmp_T_84; // @[VAluInt.scala 1361:56]
- wire _cmp_T_88 = _cmp_T_15 & ule_2; // @[Library.scala 36:8]
- wire _cmp_T_89 = _cmp_T_85 | _cmp_T_88; // @[VAluInt.scala 1362:56]
- wire _cmp_T_91 = ~sle_2; // @[VAluInt.scala 1364:51]
- wire _cmp_T_92 = _cmp_T_18 & _cmp_T_91; // @[Library.scala 36:8]
- wire _cmp_T_93 = _cmp_T_89 | _cmp_T_92; // @[VAluInt.scala 1363:56]
- wire _cmp_T_96 = ~ule_2; // @[VAluInt.scala 1365:51]
- wire _cmp_T_97 = _cmp_T_23 & _cmp_T_96; // @[Library.scala 36:8]
- wire _cmp_T_98 = _cmp_T_93 | _cmp_T_97; // @[VAluInt.scala 1364:57]
- wire _cmp_T_100 = ~slt_2; // @[VAluInt.scala 1366:51]
- wire _cmp_T_101 = _cmp_T_27 & _cmp_T_100; // @[Library.scala 36:8]
- wire _cmp_T_102 = _cmp_T_98 | _cmp_T_101; // @[VAluInt.scala 1365:57]
- wire _cmp_T_105 = ~ult_2; // @[VAluInt.scala 1367:51]
- wire _cmp_T_106 = _cmp_T_32 & _cmp_T_105; // @[Library.scala 36:8]
- wire _cmp_T_107 = _cmp_T_102 | _cmp_T_106; // @[VAluInt.scala 1366:57]
- wire cmp_2 = io_in_sz[0] & _cmp_T_107; // @[VAluInt.scala 1357:30]
- wire [7:0] _log_T_228 = log_a[23:16] & log_b[23:16]; // @[VAluInt.scala 1371:42]
- wire [7:0] _log_T_229 = io_op_log_and ? _log_T_228 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_232 = log_a[23:16] | log_b[23:16]; // @[VAluInt.scala 1372:42]
- wire [7:0] _log_T_233 = io_op_log_or ? _log_T_232 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_234 = _log_T_229 | _log_T_233; // @[VAluInt.scala 1371:56]
- wire [7:0] _log_T_237 = log_a[23:16] ^ log_b[23:16]; // @[VAluInt.scala 1373:42]
- wire [7:0] _log_T_238 = io_op_log_xor ? _log_T_237 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_239 = _log_T_234 | _log_T_238; // @[VAluInt.scala 1372:56]
- wire [7:0] _log_T_242 = ~log_a[23:16]; // @[VAluInt.scala 1374:51]
- wire [7:0] _log_T_243 = io_in_sz[0] ? _log_T_242 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_244 = io_op_log_not ? _log_T_243 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_245 = _log_T_239 | _log_T_244; // @[VAluInt.scala 1373:56]
- wire _log_b_T_33 = ~log_b[16]; // @[VAluInt.scala 1151:23]
- wire [7:0] _log_b_T_42 = {log_a[22],log_a[23],log_a[20],log_a[21],log_a[18],log_a[19],log_a[16],log_a[17]}; // @[Cat.scala 31:58]
- wire [7:0] log_b_5 = ~log_b[16] ? log_a[23:16] : _log_b_T_42; // @[VAluInt.scala 1151:22]
- wire _log_c_T_25 = ~log_b[17]; // @[VAluInt.scala 1152:23]
- wire [7:0] _log_c_T_30 = {log_b_5[5:4],log_b_5[7:6],log_b_5[1:0],log_b_5[3:2]}; // @[Cat.scala 31:58]
- wire [7:0] log_c_4 = ~log_b[17] ? log_b_5 : _log_c_T_30; // @[VAluInt.scala 1152:22]
- wire _log_d_T_21 = ~log_b[18]; // @[VAluInt.scala 1153:23]
- wire [7:0] _log_d_T_24 = {log_c_4[3:0],log_c_4[7:4]}; // @[Cat.scala 31:58]
- wire [7:0] log_d_4 = ~log_b[18] ? log_c_4 : _log_d_T_24; // @[VAluInt.scala 1153:22]
- wire [7:0] _log_T_248 = io_op_log_rev ? log_d_4 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_249 = _log_T_245 | _log_T_248; // @[VAluInt.scala 1374:65]
- wire [7:0] _log_b_T_47 = {log_a[16],log_a[23:17]}; // @[Cat.scala 31:58]
- wire [7:0] log_b_6 = _log_b_T_33 ? log_a[23:16] : _log_b_T_47; // @[VAluInt.scala 1188:22]
- wire [7:0] _log_c_T_35 = {log_b_6[1:0],log_b_6[7:2]}; // @[Cat.scala 31:58]
- wire [7:0] log_c_5 = _log_c_T_25 ? log_b_6 : _log_c_T_35; // @[VAluInt.scala 1189:22]
- wire [7:0] _log_d_T_29 = {log_c_5[3:0],log_c_5[7:4]}; // @[Cat.scala 31:58]
- wire [7:0] log_d_5 = _log_d_T_21 ? log_c_5 : _log_d_T_29; // @[VAluInt.scala 1190:22]
- wire [7:0] _log_T_253 = io_in_sz[0] ? log_d_5 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_254 = io_op_log_ror ? _log_T_253 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_255 = _log_T_249 | _log_T_254; // @[VAluInt.scala 1375:60]
- wire [7:0] _GEN_76 = {{4'd0}, _log_T_242[7:4]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_98 = _GEN_76 & 8'hf; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_100 = {_log_T_242[3:0], 4'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clo_T_102 = _log_clo_T_100 & 8'hf0; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clo_T_103 = _log_clo_T_98 | _log_clo_T_102; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_77 = {{2'd0}, _log_clo_T_103[7:2]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_108 = _GEN_77 & 8'h33; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_110 = {_log_clo_T_103[5:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clo_T_112 = _log_clo_T_110 & 8'hcc; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clo_T_113 = _log_clo_T_108 | _log_clo_T_112; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_78 = {{1'd0}, _log_clo_T_113[7:1]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_118 = _GEN_78 & 8'h55; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_120 = {_log_clo_T_113[6:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clo_T_122 = _log_clo_T_120 & 8'haa; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clo_T_123 = _log_clo_T_118 | _log_clo_T_122; // @[Bitwise.scala 105:39]
- wire [8:0] _log_clo_T_124 = {1'h1,_log_clo_T_123}; // @[Cat.scala 31:58]
- wire [3:0] _log_clo_T_134 = _log_clo_T_124[7] ? 4'h7 : 4'h8; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_135 = _log_clo_T_124[6] ? 4'h6 : _log_clo_T_134; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_136 = _log_clo_T_124[5] ? 4'h5 : _log_clo_T_135; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_137 = _log_clo_T_124[4] ? 4'h4 : _log_clo_T_136; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_138 = _log_clo_T_124[3] ? 4'h3 : _log_clo_T_137; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_139 = _log_clo_T_124[2] ? 4'h2 : _log_clo_T_138; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_140 = _log_clo_T_124[1] ? 4'h1 : _log_clo_T_139; // @[Mux.scala 47:70]
- wire [3:0] log_clo_2 = _log_clo_T_124[0] ? 4'h0 : _log_clo_T_140; // @[Mux.scala 47:70]
- wire [7:0] _GEN_79 = {{4'd0}, log_a[23:20]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_95 = _GEN_79 & 8'hf; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_97 = {log_a[19:16], 4'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clz_T_99 = _log_clz_T_97 & 8'hf0; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clz_T_100 = _log_clz_T_95 | _log_clz_T_99; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_80 = {{2'd0}, _log_clz_T_100[7:2]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_105 = _GEN_80 & 8'h33; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_107 = {_log_clz_T_100[5:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clz_T_109 = _log_clz_T_107 & 8'hcc; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clz_T_110 = _log_clz_T_105 | _log_clz_T_109; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_81 = {{1'd0}, _log_clz_T_110[7:1]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_115 = _GEN_81 & 8'h55; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_117 = {_log_clz_T_110[6:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clz_T_119 = _log_clz_T_117 & 8'haa; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clz_T_120 = _log_clz_T_115 | _log_clz_T_119; // @[Bitwise.scala 105:39]
- wire [8:0] _log_clz_T_121 = {1'h1,_log_clz_T_120}; // @[Cat.scala 31:58]
- wire [3:0] _log_clz_T_131 = _log_clz_T_121[7] ? 4'h7 : 4'h8; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_132 = _log_clz_T_121[6] ? 4'h6 : _log_clz_T_131; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_133 = _log_clz_T_121[5] ? 4'h5 : _log_clz_T_132; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_134 = _log_clz_T_121[4] ? 4'h4 : _log_clz_T_133; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_135 = _log_clz_T_121[3] ? 4'h3 : _log_clz_T_134; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_136 = _log_clz_T_121[2] ? 4'h2 : _log_clz_T_135; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_137 = _log_clz_T_121[1] ? 4'h1 : _log_clz_T_136; // @[Mux.scala 47:70]
- wire [3:0] log_clz_2 = _log_clz_T_121[0] ? 4'h0 : _log_clz_T_137; // @[Mux.scala 47:70]
- wire [3:0] _log_T_259 = log_a[23] ? log_clo_2 : log_clz_2; // @[Library.scala 289:8]
- wire [3:0] _log_T_260 = io_in_sz[0] ? _log_T_259 : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _log_T_261 = io_op_log_clb ? _log_T_260 : 4'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_82 = {{4'd0}, _log_T_261}; // @[VAluInt.scala 1376:81]
- wire [7:0] _log_T_262 = _log_T_255 | _GEN_82; // @[VAluInt.scala 1376:81]
- wire [3:0] _log_T_312 = io_in_sz[0] ? log_clz_2 : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _log_T_313 = io_op_log_clz ? _log_T_312 : 4'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_86 = {{4'd0}, _log_T_313}; // @[VAluInt.scala 1377:69]
- wire [7:0] _log_T_314 = _log_T_262 | _GEN_86; // @[VAluInt.scala 1377:69]
- wire [1:0] _log_T_324 = log_a[16] + log_a[17]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_326 = log_a[18] + log_a[19]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_328 = _log_T_324 + _log_T_326; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_330 = log_a[20] + log_a[21]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_332 = log_a[22] + log_a[23]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_334 = _log_T_330 + _log_T_332; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_336 = _log_T_328 + _log_T_334; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_338 = io_op_log_cpop ? _log_T_336 : 4'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_87 = {{4'd0}, _log_T_338}; // @[VAluInt.scala 1378:69]
- wire [7:0] log_2 = _log_T_314 | _GEN_87; // @[VAluInt.scala 1378:69]
- wire [7:0] _shift_T_8 = io_op_shf_shl ? shl_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shift_T_9 = io_op_shf_shr ? shr_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shift_T_10 = _shift_T_8 | _shift_T_9; // @[VAluInt.scala 1383:35]
- wire [7:0] _shift_T_11 = io_op_shf_shf ? shf_2 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] shift_2 = _shift_T_10 | _shift_T_11; // @[VAluInt.scala 1384:35]
- wire _alu_oh_T_28 = absd_2 != 8'h0; // @[VAluInt.scala 1388:30]
- wire _alu_oh_T_29 = add_2 != 8'h0; // @[VAluInt.scala 1389:30]
- wire _alu_oh_T_31 = dup_2 != 8'h0; // @[VAluInt.scala 1391:30]
- wire _alu_oh_T_32 = log_2 != 8'h0; // @[VAluInt.scala 1392:30]
- wire _alu_oh_T_33 = max_2 != 8'h0; // @[VAluInt.scala 1393:30]
- wire _alu_oh_T_34 = min_2 != 8'h0; // @[VAluInt.scala 1394:30]
- wire _alu_oh_T_35 = mul0_2 != 8'h0; // @[VAluInt.scala 1395:30]
- wire _alu_oh_T_37 = rsub_2 != 8'h0; // @[VAluInt.scala 1397:30]
- wire _alu_oh_T_38 = shift_2 != 8'h0; // @[VAluInt.scala 1398:30]
- wire _alu_oh_T_39 = srans_2 != 8'h0; // @[VAluInt.scala 1399:30]
- wire _alu_oh_T_40 = sraqs_2 != 8'h0; // @[VAluInt.scala 1400:30]
- wire _alu_oh_T_41 = sub_2 != 8'h0; // @[VAluInt.scala 1401:30]
- wire [6:0] alu_oh_lo_2 = {_alu_oh_T_35,1'h0,_alu_oh_T_37,_alu_oh_T_38,_alu_oh_T_39,_alu_oh_T_40,_alu_oh_T_41}; // @[Cat.scala 31:58]
- wire [13:0] alu_oh_2 = {_alu_oh_T_28,_alu_oh_T_29,cmp_2,_alu_oh_T_31,_alu_oh_T_32,_alu_oh_T_33,_alu_oh_T_34,
- alu_oh_lo_2}; // @[Cat.scala 31:58]
- wire [1:0] _T_258 = alu_oh_2[1] + alu_oh_2[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_88 = {{1'd0}, alu_oh_2[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_260 = _GEN_88 + _T_258; // @[Bitwise.scala 48:55]
- wire [1:0] _T_262 = alu_oh_2[3] + alu_oh_2[4]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_264 = alu_oh_2[5] + alu_oh_2[6]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_266 = _T_262 + _T_264; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_89 = {{1'd0}, _T_260[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_268 = _GEN_89 + _T_266; // @[Bitwise.scala 48:55]
- wire [1:0] _T_270 = alu_oh_2[8] + alu_oh_2[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_90 = {{1'd0}, alu_oh_2[7]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_272 = _GEN_90 + _T_270; // @[Bitwise.scala 48:55]
- wire [1:0] _T_274 = alu_oh_2[10] + alu_oh_2[11]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_276 = alu_oh_2[12] + alu_oh_2[13]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_278 = _T_274 + _T_276; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_91 = {{1'd0}, _T_272[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_280 = _GEN_91 + _T_278; // @[Bitwise.scala 48:55]
- wire [3:0] _T_282 = _T_268[2:0] + _T_280[2:0]; // @[Bitwise.scala 48:55]
- wire [7:0] _alu0_2_T = mul0_2 | absd_2; // @[VAluInt.scala 1405:23]
- wire [7:0] _alu0_2_T_1 = _alu0_2_T | add_2; // @[VAluInt.scala 1405:30]
- wire [7:0] _GEN_92 = {{7'd0}, cmp_2}; // @[VAluInt.scala 1405:36]
- wire [7:0] _alu0_2_T_2 = _alu0_2_T_1 | _GEN_92; // @[VAluInt.scala 1405:36]
- wire [7:0] _alu0_2_T_3 = _alu0_2_T_2 | dup_2; // @[VAluInt.scala 1405:42]
- wire [7:0] _alu0_2_T_4 = _alu0_2_T_3 | log_2; // @[VAluInt.scala 1405:48]
- wire [7:0] _alu0_2_T_5 = _alu0_2_T_4 | max_2; // @[VAluInt.scala 1405:54]
- wire [7:0] _alu0_2_T_6 = _alu0_2_T_5 | min_2; // @[VAluInt.scala 1405:60]
- wire [7:0] _alu0_2_T_8 = _alu0_2_T_6 | rsub_2; // @[VAluInt.scala 1405:73]
- wire [7:0] _alu0_2_T_9 = _alu0_2_T_8 | shift_2; // @[VAluInt.scala 1405:80]
- wire [7:0] _alu0_2_T_10 = _alu0_2_T_9 | srans_2; // @[VAluInt.scala 1405:88]
- wire [7:0] _alu0_2_T_11 = _alu0_2_T_10 | sraqs_2; // @[VAluInt.scala 1405:96]
- wire [7:0] _alu0_2_T_12 = _alu0_2_T_11 | sub_2; // @[VAluInt.scala 1405:104]
- wire [7:0] _alu0_2_T_14 = io_op_mv ? ina_b[23:16] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] alu0__2 = _alu0_2_T_12 | _alu0_2_T_14; // @[VAluInt.scala 1405:110]
- wire [7:0] _alu1_2_T_1 = io_op_mvp ? inb_b[23:16] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _alu1_2_T_2 = mul1_2 | _alu1_2_T_1; // @[VAluInt.scala 1408:23]
- wire [7:0] _alu1_2_T_4 = io_op_mv2 ? inc_b[23:16] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] alu1__2 = _alu1_2_T_2 | _alu1_2_T_4; // @[VAluInt.scala 1409:44]
- wire [7:0] _GEN_93 = {{7'd0}, mulh0_rnd_2}; // @[VAluInt.scala 1412:29]
- wire [7:0] _rnd0_2_T = dmulh0_rnd_2 | _GEN_93; // @[VAluInt.scala 1412:29]
- wire [7:0] _GEN_94 = {{7'd0}, shf_rnd_2}; // @[VAluInt.scala 1412:41]
- wire [7:0] rnd0__2 = _rnd0_2_T | _GEN_94; // @[VAluInt.scala 1412:41]
- wire [7:0] _GEN_95 = {{7'd0}, mulh1_rnd_2}; // @[VAluInt.scala 1413:29]
- wire [7:0] rnd1__2 = dmulh1_rnd_2 | _GEN_95; // @[VAluInt.scala 1413:29]
- wire [15:0] _aluw0_1_T = acc_2 | addw_2; // @[VAluInt.scala 1417:31]
- wire [15:0] _aluw0_1_T_1 = _aluw0_1_T | mulw_2; // @[VAluInt.scala 1417:38]
- wire [15:0] aluw0__1 = _aluw0_1_T_1 | subw_2; // @[VAluInt.scala 1417:45]
- wire add_sa_3 = add_a[31] & io_in_signed; // @[VAluInt.scala 973:29]
- wire add_sb_3 = add_b[31] & io_in_signed; // @[VAluInt.scala 974:29]
- wire [8:0] _adder_T_29 = {add_sa_3,add_a[31:24]}; // @[VAluInt.scala 975:44]
- wire [8:0] _adder_T_32 = {add_sb_3,add_b[31:24]}; // @[VAluInt.scala 975:78]
- wire [9:0] _adder_T_34 = $signed(_adder_T_29) + $signed(_adder_T_32); // @[VAluInt.scala 975:86]
- wire [9:0] adder_3 = _adder_T_34 + _GEN_6; // @[VAluInt.scala 975:93]
- wire [1:0] sataddmsb_3 = adder_3[8:7]; // @[VAluInt.scala 976:28]
- wire _sataddsel_T_22 = io_in_signed & sataddmsb_3 == 2'h2; // @[VAluInt.scala 978:21]
- wire _sataddsel_T_24 = io_in_signed & sataddmsb_3 == 2'h1; // @[VAluInt.scala 979:21]
- wire _sataddsel_T_27 = ~io_in_signed & sataddmsb_3[1]; // @[VAluInt.scala 980:21]
- wire [2:0] sataddsel_3 = {_sataddsel_T_22,_sataddsel_T_24,_sataddsel_T_27}; // @[Cat.scala 31:58]
- wire [1:0] _T_291 = sataddsel_3[1] + sataddsel_3[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_97 = {{1'd0}, sataddsel_3[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_293 = _GEN_97 + _T_291; // @[Bitwise.scala 48:55]
- wire sub_sa_3 = sub_a[31] & io_in_signed; // @[VAluInt.scala 983:29]
- wire sub_sb_3 = sub_b[31] & io_in_signed; // @[VAluInt.scala 984:29]
- wire [8:0] _subtr_T_29 = {sub_sa_3,sub_a[31:24]}; // @[VAluInt.scala 985:44]
- wire [8:0] _subtr_T_32 = {sub_sb_3,sub_b[31:24]}; // @[VAluInt.scala 985:78]
- wire [9:0] _subtr_T_34 = $signed(_subtr_T_29) - $signed(_subtr_T_32); // @[VAluInt.scala 985:86]
- wire [9:0] subtr_3 = _subtr_T_34 + _GEN_8; // @[VAluInt.scala 985:93]
- wire [1:0] satsubmsb_3 = subtr_3[8:7]; // @[VAluInt.scala 986:28]
- wire _satsubsel_T_22 = io_in_signed & satsubmsb_3 == 2'h2; // @[VAluInt.scala 988:21]
- wire _satsubsel_T_24 = io_in_signed & satsubmsb_3 == 2'h1; // @[VAluInt.scala 989:21]
- wire _satsubsel_T_27 = _sataddsel_T_4 & satsubmsb_3[1]; // @[VAluInt.scala 990:21]
- wire [2:0] satsubsel_3 = {_satsubsel_T_22,_satsubsel_T_24,_satsubsel_T_27}; // @[Cat.scala 31:58]
- wire [1:0] _T_302 = satsubsel_3[1] + satsubsel_3[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_99 = {{1'd0}, satsubsel_3[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_304 = _GEN_99 + _T_302; // @[Bitwise.scala 48:55]
- wire [7:0] rsubtr_3 = rsub_b[31:24] - rsub_a[31:24]; // @[VAluInt.scala 993:32]
- wire xeq_3 = cmp_a[31:24] == cmp_b[31:24]; // @[VAluInt.scala 995:28]
- wire xne_3 = cmp_a[31:24] != cmp_b[31:24]; // @[VAluInt.scala 996:28]
- wire [7:0] _slt_T_13 = cmp_a[31:24]; // @[VAluInt.scala 997:34]
- wire [7:0] _slt_T_15 = cmp_b[31:24]; // @[VAluInt.scala 997:56]
- wire slt_3 = $signed(_slt_T_13) < $signed(_slt_T_15); // @[VAluInt.scala 997:37]
- wire ult_3 = cmp_a[31:24] < cmp_b[31:24]; // @[VAluInt.scala 998:28]
- wire sle_3 = slt_3 | xeq_3; // @[VAluInt.scala 999:21]
- wire ule_3 = ult_3 | xeq_3; // @[VAluInt.scala 1000:21]
- wire sult_3 = io_in_signed ? slt_3 : ult_3; // @[VAluInt.scala 1002:21]
- wire [14:0] _GEN_25 = {{7'd0}, shl_a[31:24]}; // @[VAluInt.scala 1062:29]
- wire [14:0] _shl_T_11 = _GEN_25 << shl_b[26:24]; // @[VAluInt.scala 1062:29]
- wire [7:0] shl_3 = _shl_T_11[7:0]; // @[VAluInt.scala 1062:49]
- wire [3:0] _GEN_100 = {{1'd0}, shl_b[26:24]}; // @[VAluInt.scala 1063:40]
- wire [3:0] _sln_T_18 = 4'h8 - _GEN_100; // @[VAluInt.scala 1063:40]
- wire [22:0] _GEN_36 = {{15'd0}, shl_a[31:24]}; // @[VAluInt.scala 1063:29]
- wire [22:0] _sln_T_19 = _GEN_36 << _sln_T_18; // @[VAluInt.scala 1063:29]
- wire [14:0] sln_3 = _sln_T_19[14:0]; // @[VAluInt.scala 1063:60]
- wire [7:0] srl_3 = shr_a[31:24] >> shr_b[26:24]; // @[VAluInt.scala 1064:28]
- wire [2:0] _srs_T_25 = 3'h7 - shr_b[26:24]; // @[VAluInt.scala 1065:66]
- wire [14:0] _srs_T_26 = 15'hff << _srs_T_25; // @[VAluInt.scala 1065:49]
- wire [7:0] srs_3 = shr_a[31] ? _srs_T_26[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] sra_3 = srs_3 | srl_3; // @[VAluInt.scala 1066:21]
- wire [7:0] shf_slnsz_3 = sln_3[7:0]; // @[VAluInt.scala 1010:24]
- wire shf_input_neg_3 = shl_a[31]; // @[VAluInt.scala 1011:26]
- wire shf_input_zero_3 = shl_a[31:24] == 8'h0; // @[VAluInt.scala 1012:28]
- wire shf_shamt_neg_3 = shl_b[31]; // @[VAluInt.scala 1013:26]
- wire [7:0] _shf_shamt_negsat_T_15 = shl_b[31:24]; // @[VAluInt.scala 1017:32]
- wire shf_shamt_negsat_6 = $signed(_shf_shamt_negsat_T_15) <= -8'sh7; // @[VAluInt.scala 1017:39]
- wire shf_shamt_possat_6 = $signed(_shf_shamt_negsat_T_15) >= 8'sh7; // @[VAluInt.scala 1018:39]
- wire [2:0] _shf_signb_T_15 = shl_b[26:24] - 3'h1; // @[VAluInt.scala 1019:65]
- wire [7:0] shf_signb_3 = 8'hff >> _shf_signb_T_15; // @[VAluInt.scala 1019:36]
- wire _shf_possat_T_42 = ~shf_input_zero_3; // @[VAluInt.scala 1020:112]
- wire shf_possat_6 = shf_shamt_neg_3 & ~shf_input_neg_3 & (shf_shamt_negsat_6 | sln_3[14:7] != 8'h0) & ~
- shf_input_zero_3; // @[VAluInt.scala 1020:109]
- wire shf_negsat_3 = shf_shamt_neg_3 & shf_input_neg_3 & (shf_shamt_negsat_6 | sln_3[14:7] != shf_signb_3); // @[VAluInt.scala 1021:48]
- wire _shf_rs_T_66 = ~shf_shamt_neg_3; // @[VAluInt.scala 1028:23]
- wire _shf_rs_T_68 = ~shf_shamt_neg_3 & ~shf_shamt_possat_6; // @[VAluInt.scala 1028:34]
- wire [7:0] _shf_rs_T_69 = _shf_rs_T_68 ? sra_3 : 8'h0; // @[Library.scala 32:8]
- wire _shf_rs_T_72 = _shf_rs_T_66 & shf_shamt_possat_6 & shf_input_neg_3; // @[VAluInt.scala 1029:51]
- wire [7:0] _shf_rs_T_74 = _shf_rs_T_72 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_rs_T_75 = _shf_rs_T_69 | _shf_rs_T_74; // @[VAluInt.scala 1028:57]
- wire _shf_rs_T_79 = shf_shamt_neg_3 & ~shf_possat_6 & ~shf_negsat_3; // @[VAluInt.scala 1030:45]
- wire [7:0] _shf_rs_T_80 = _shf_rs_T_79 ? shf_slnsz_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_rs_T_81 = _shf_rs_T_75 | _shf_rs_T_80; // @[VAluInt.scala 1029:79]
- wire _shf_rs_T_82 = shf_shamt_neg_3 & shf_possat_6; // @[VAluInt.scala 1031:34]
- wire [7:0] _shf_rs_T_83 = _shf_rs_T_82 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_rs_T_84 = _shf_rs_T_81 | _shf_rs_T_83; // @[VAluInt.scala 1030:64]
- wire _shf_rs_T_85 = shf_shamt_neg_3 & shf_negsat_3; // @[VAluInt.scala 1032:34]
- wire [7:0] _shf_rs_T_86 = _shf_rs_T_85 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] shf_rs_3 = _shf_rs_T_84 | _shf_rs_T_86; // @[VAluInt.scala 1031:53]
- wire shf_shamt_negsat_7 = $signed(_shf_shamt_negsat_T_15) <= $signed(_GEN_11); // @[VAluInt.scala 1035:39]
- wire shf_shamt_possat_7 = $signed(_shf_shamt_negsat_T_15) >= 8'sh8; // @[VAluInt.scala 1036:39]
- wire shf_possat_7 = shf_shamt_neg_3 & (shf_shamt_negsat_7 | sln_3[14:8] != 7'h0) & _shf_possat_T_42; // @[VAluInt.scala 1037:89]
- wire _shf_ru_T_35 = _shf_rs_T_66 & ~shf_shamt_possat_7; // @[VAluInt.scala 1041:34]
- wire [7:0] _shf_ru_T_36 = _shf_ru_T_35 ? srl_3 : 8'h0; // @[Library.scala 32:8]
- wire _shf_ru_T_38 = shf_shamt_neg_3 & ~shf_possat_7; // @[VAluInt.scala 1042:34]
- wire [7:0] _shf_ru_T_39 = _shf_ru_T_38 ? shf_slnsz_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shf_ru_T_40 = _shf_ru_T_36 | _shf_ru_T_39; // @[VAluInt.scala 1041:57]
- wire _shf_ru_T_41 = shf_shamt_neg_3 & shf_possat_7; // @[VAluInt.scala 1043:34]
- wire [7:0] _shf_ru_T_42 = _shf_ru_T_41 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] shf_ru_3 = _shf_ru_T_40 | _shf_ru_T_42; // @[VAluInt.scala 1042:53]
- wire [7:0] shf_3 = io_in_signed ? shf_rs_3 : shf_ru_3; // @[VAluInt.scala 1045:12]
- wire [7:0] shr_3 = io_in_signed ? sra_3 : srl_3; // @[VAluInt.scala 1068:20]
- wire shf_rnd_shamt_zero_3 = shl_b[31:24] == 8'h0; // @[VAluInt.scala 1053:28]
- wire [7:0] _shf_rnd_rbit_T_17 = {shl_a[30:24],shf_input_neg_3}; // @[Cat.scala 31:58]
- wire [7:0] _shf_rnd_rbit_T_19 = _shf_rnd_rbit_T_17 >> shl_b[26:24]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_rbit_3 = _shf_rnd_rbit_T_19[0]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_shamt_possat_3 = io_in_signed ? shf_shamt_possat_7 : $signed(_shf_shamt_negsat_T_15) > 8'sh8; // @[VAluInt.scala 1055:31]
- wire _shf_rnd_r_T_38 = io_in_round & ~shf_rnd_shamt_possat_3 & _shf_rs_T_66 & ~shf_rnd_shamt_zero_3; // @[VAluInt.scala 1056:60]
- wire _shf_rnd_r_T_39 = _shf_rnd_r_T_38 & shf_rnd_rbit_3; // @[Library.scala 36:8]
- wire _shf_rnd_r_T_42 = io_in_round & shf_rnd_shamt_possat_3 & shf_input_neg_3 & io_in_signed; // @[VAluInt.scala 1057:59]
- wire shf_rnd_3 = _shf_rnd_r_T_39 | _shf_rnd_r_T_42; // @[VAluInt.scala 1056:82]
- wire _mul0_as_T_10 = io_in_signed & mul0_a[31]; // @[VAluInt.scala 1199:32]
- wire _mul0_bs_T_10 = io_in_signed & mul0_b[31]; // @[VAluInt.scala 1200:32]
- wire mul0_sign_3 = mul0_a[31] != mul0_b[31] & mul0_a[31:24] != 8'h0 & mul0_b[31:24] != 8'h0; // @[VAluInt.scala 1201:70]
- wire [8:0] _prod0_T_9 = {_mul0_as_T_10,mul0_a[31:24]}; // @[VAluInt.scala 1202:28]
- wire [8:0] _prod0_T_10 = {_mul0_bs_T_10,mul0_b[31:24]}; // @[VAluInt.scala 1202:45]
- wire [17:0] prod0_3 = $signed(_prod0_T_9) * $signed(_prod0_T_10); // @[VAluInt.scala 1202:53]
- wire [7:0] prodh0_3 = prod0_3[15:8]; // @[VAluInt.scala 1203:25]
- wire [7:0] proddh0_3 = prod0_3[14:7]; // @[VAluInt.scala 1204:26]
- wire _mul1_as_T_10 = io_in_signed & mul1_a[31]; // @[VAluInt.scala 1206:32]
- wire _mul1_bs_T_10 = io_in_signed & mul1_b[31]; // @[VAluInt.scala 1207:32]
- wire mul1_sign_3 = mul1_a[31] != mul1_b[31] & mul1_a[31:24] != 8'h0 & mul1_b[31:24] != 8'h0; // @[VAluInt.scala 1208:70]
- wire [8:0] _prod1_T_9 = {_mul1_as_T_10,mul1_a[31:24]}; // @[VAluInt.scala 1209:28]
- wire [8:0] _prod1_T_10 = {_mul1_bs_T_10,mul1_b[31:24]}; // @[VAluInt.scala 1209:45]
- wire [17:0] prod1_3 = $signed(_prod1_T_9) * $signed(_prod1_T_10); // @[VAluInt.scala 1209:53]
- wire [7:0] prodh1_3 = prod1_3[15:8]; // @[VAluInt.scala 1210:25]
- wire [7:0] proddh1_3 = prod1_3[14:7]; // @[VAluInt.scala 1211:26]
- wire _muls0_umax_T_7 = prodh0_3 != 8'h0; // @[VAluInt.scala 1213:42]
- wire muls0_umax_3 = _sataddsel_T_4 & prodh0_3 != 8'h0; // @[VAluInt.scala 1213:32]
- wire muls0_smax_3 = io_in_signed & ~mul0_sign_3 & (prod0_3[7] | _muls0_umax_T_7); // @[VAluInt.scala 1214:46]
- wire muls0_smin_3 = io_in_signed & mul0_sign_3 & (~prod0_3[7] | prodh0_3 != 8'hff); // @[VAluInt.scala 1215:46]
- wire muls0_base_3 = ~(muls0_umax_3 | muls0_smax_3 | muls0_smin_3); // @[VAluInt.scala 1216:24]
- wire [3:0] _T_310 = {muls0_umax_3,muls0_smax_3,muls0_smin_3,muls0_base_3}; // @[Cat.scala 31:58]
- wire [1:0] _T_315 = _T_310[0] + _T_310[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_317 = _T_310[2] + _T_310[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_319 = _T_315 + _T_317; // @[Bitwise.scala 48:55]
- wire _muls1_umax_T_7 = prodh1_3 != 8'h0; // @[VAluInt.scala 1219:42]
- wire muls1_umax_3 = _sataddsel_T_4 & prodh1_3 != 8'h0; // @[VAluInt.scala 1219:32]
- wire muls1_smax_3 = io_in_signed & ~mul1_sign_3 & (prod1_3[7] | _muls1_umax_T_7); // @[VAluInt.scala 1220:46]
- wire muls1_smin_3 = io_in_signed & mul1_sign_3 & (~prod1_3[7] | prodh1_3 != 8'hff); // @[VAluInt.scala 1221:46]
- wire muls1_base_3 = ~(muls1_umax_3 | muls1_smax_3 | muls1_smin_3); // @[VAluInt.scala 1222:24]
- wire [3:0] _T_325 = {muls1_umax_3,muls1_smax_3,muls1_smin_3,muls1_base_3}; // @[Cat.scala 31:58]
- wire [1:0] _T_330 = _T_325[0] + _T_325[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_332 = _T_325[2] + _T_325[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_334 = _T_330 + _T_332; // @[Bitwise.scala 48:55]
- wire dmulh0_possat_3 = mul0_a[31:24] == 8'h80 & mul0_b[31:24] == 8'h80; // @[VAluInt.scala 1227:50]
- wire dmulh1_possat_3 = mul1_a[31:24] == 8'h80 & mul1_b[31:24] == 8'h80; // @[VAluInt.scala 1229:50]
- wire _dmulh0_T_15 = ~dmulh0_possat_3; // @[VAluInt.scala 1231:26]
- wire [7:0] _dmulh0_T_16 = _dmulh0_T_15 ? proddh0_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh0_T_19 = dmulh0_possat_3 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] dmulh0_3 = _dmulh0_T_16 | _dmulh0_T_19; // @[VAluInt.scala 1231:51]
- wire _dmulh1_T_15 = ~dmulh1_possat_3; // @[VAluInt.scala 1234:26]
- wire [7:0] _dmulh1_T_16 = _dmulh1_T_15 ? proddh1_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh1_T_19 = dmulh1_possat_3 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] dmulh1_3 = _dmulh1_T_16 | _dmulh1_T_19; // @[VAluInt.scala 1234:51]
- wire [7:0] _muls0_T_31 = muls0_umax_3 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [6:0] _muls0_T_33 = muls0_smax_3 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_102 = {{1'd0}, _muls0_T_33}; // @[VAluInt.scala 1240:51]
- wire [7:0] _muls0_T_34 = _muls0_T_31 | _GEN_102; // @[VAluInt.scala 1240:51]
- wire [7:0] _muls0_T_36 = muls0_smin_3 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _muls0_T_37 = _muls0_T_34 | _muls0_T_36; // @[VAluInt.scala 1241:57]
- wire [7:0] _muls0_T_39 = muls0_base_3 ? prod0_3[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] muls0_3 = _muls0_T_37 | _muls0_T_39; // @[VAluInt.scala 1242:71]
- wire [7:0] _muls1_T_31 = muls1_umax_3 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [6:0] _muls1_T_33 = muls1_smax_3 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_103 = {{1'd0}, _muls1_T_33}; // @[VAluInt.scala 1245:51]
- wire [7:0] _muls1_T_34 = _muls1_T_31 | _GEN_103; // @[VAluInt.scala 1245:51]
- wire [7:0] _muls1_T_36 = muls1_smin_3 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _muls1_T_37 = _muls1_T_34 | _muls1_T_36; // @[VAluInt.scala 1246:57]
- wire [7:0] _muls1_T_39 = muls1_base_3 ? prod1_3[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] muls1_3 = _muls1_T_37 | _muls1_T_39; // @[VAluInt.scala 1247:71]
- wire _dmulh0_rnd_T_43 = io_in_round & io_op_mul0_dmulh & io_in_sz[0] & _dmulh0_T_15; // @[VAluInt.scala 1250:72]
- wire _dmulh0_rnd_T_46 = ~prod0_3[6]; // @[VAluInt.scala 1252:40]
- wire [7:0] _dmulh0_rnd_T_48 = _dmulh0_rnd_T_46 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh0_rnd_T_50 = prod0_3[6] ? 8'h1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh0_rnd_T_51 = io_in_negative & mul0_sign_3 ? _dmulh0_rnd_T_48 : _dmulh0_rnd_T_50; // @[VAluInt.scala 1251:33]
- wire [7:0] dmulh0_rnd_3 = _dmulh0_rnd_T_43 ? _dmulh0_rnd_T_51 : 8'h0; // @[Library.scala 32:8]
- wire _dmulh1_rnd_T_43 = io_in_round & io_op_mul1_dmulh & io_in_sz[0] & _dmulh1_T_15; // @[VAluInt.scala 1255:72]
- wire _dmulh1_rnd_T_46 = ~prod1_3[6]; // @[VAluInt.scala 1257:40]
- wire [7:0] _dmulh1_rnd_T_48 = _dmulh1_rnd_T_46 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh1_rnd_T_50 = prod1_3[6] ? 8'h1 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _dmulh1_rnd_T_51 = io_in_negative & mul1_sign_3 ? _dmulh1_rnd_T_48 : _dmulh1_rnd_T_50; // @[VAluInt.scala 1256:33]
- wire [7:0] dmulh1_rnd_3 = _dmulh1_rnd_T_43 ? _dmulh1_rnd_T_51 : 8'h0; // @[Library.scala 32:8]
- wire mulh0_rnd_3 = io_in_round & io_op_mul0_mulh & prod0_3[7]; // @[VAluInt.scala 1260:48]
- wire mulh1_rnd_3 = io_in_round & io_op_mul1_mulh & prod1_3[7]; // @[VAluInt.scala 1261:48]
- wire [7:0] _absd_T_7 = sult_3 ? rsubtr_3 : subtr_3[7:0]; // @[VAluInt.scala 1265:39]
- wire [7:0] absd_3 = io_op_absd ? _absd_T_7 : 8'h0; // @[Library.scala 32:8]
- wire _acc_T_20 = io_in_signed & acc_b[31]; // @[VAluInt.scala 1272:55]
- wire [8:0] _acc_T_22 = {_acc_T_20,acc_b[31:24]}; // @[Cat.scala 31:58]
- wire acc_r_r_3_2 = _acc_T_22[8]; // @[Library.scala 64:25]
- wire [15:0] acc_r_3 = {acc_r_r_3_2,acc_r_r_3_2,acc_r_r_3_2,acc_r_r_3_2,acc_r_r_3_2,acc_r_r_3_2,acc_r_r_3_2,_acc_T_20,
- acc_b[31:24]}; // @[Cat.scala 31:58]
- wire [15:0] acc_3 = acc_c[31:16] + acc_r_3; // @[VAluInt.scala 1272:34]
- wire _add_T_70 = sataddsel_3[2] & io_op_add_adds; // @[VAluInt.scala 1279:36]
- wire [7:0] _add_T_72 = _add_T_70 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire _add_T_74 = sataddsel_3[1] & io_op_add_adds; // @[VAluInt.scala 1280:36]
- wire [6:0] _add_T_76 = _add_T_74 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_104 = {{1'd0}, _add_T_76}; // @[VAluInt.scala 1279:89]
- wire [7:0] _add_T_77 = _add_T_72 | _GEN_104; // @[VAluInt.scala 1279:89]
- wire _add_T_79 = sataddsel_3[0] & io_op_add_adds; // @[VAluInt.scala 1281:36]
- wire [7:0] _add_T_81 = _add_T_79 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _add_T_82 = _add_T_77 | _add_T_81; // @[VAluInt.scala 1280:75]
- wire _add_T_86 = sataddsel_3 == 3'h0 & io_op_add_adds | io_op_add_add | io_op_add_add3; // @[VAluInt.scala 1282:76]
- wire [7:0] _add_T_88 = _add_T_86 ? adder_3[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _add_T_89 = _add_T_82 | _add_T_88; // @[VAluInt.scala 1281:69]
- wire [7:0] _add_T_91 = io_op_add_hadd ? adder_3[8:1] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] add_3 = _add_T_89 | _add_T_91; // @[VAluInt.scala 1282:115]
- wire addw_r_r_3_2 = adder_3[9]; // @[Library.scala 64:25]
- wire [15:0] addw_r_3 = {addw_r_r_3_2,addw_r_r_3_2,addw_r_r_3_2,addw_r_r_3_2,addw_r_r_3_2,addw_r_r_3_2,adder_3}; // @[Cat.scala 31:58]
- wire [15:0] addw_3 = io_op_add_addw ? addw_r_3 : 16'h0; // @[Library.scala 32:8]
- wire [7:0] dup_3 = io_op_dup ? io_read_1_data[31:24] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _max_T_11 = sult_3 ? cmp_b[31:24] : cmp_a[31:24]; // @[VAluInt.scala 1290:37]
- wire [7:0] max_3 = io_op_max ? _max_T_11 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _min_T_11 = sult_3 ? cmp_a[31:24] : cmp_b[31:24]; // @[VAluInt.scala 1291:37]
- wire [7:0] min_3 = io_op_min ? _min_T_11 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_26 = _mul0_T ? prod0_3[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_27 = io_op_mul0_dmulh ? dmulh0_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_28 = _mul0_T_26 | _mul0_T_27; // @[VAluInt.scala 1293:79]
- wire [7:0] _mul0_T_29 = io_op_mul0_mulh ? prodh0_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul0_T_30 = _mul0_T_28 | _mul0_T_29; // @[VAluInt.scala 1294:50]
- wire [7:0] _mul0_T_31 = io_op_mul0_muls ? muls0_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] mul0_3 = _mul0_T_30 | _mul0_T_31; // @[VAluInt.scala 1295:48]
- wire [7:0] _mul1_T_22 = io_op_mul1_mul ? prod1_3[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul1_T_23 = io_op_mul1_dmulh ? dmulh1_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul1_T_24 = _mul1_T_22 | _mul1_T_23; // @[VAluInt.scala 1298:60]
- wire [7:0] _mul1_T_25 = io_op_mul1_mulh ? prodh1_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _mul1_T_26 = _mul1_T_24 | _mul1_T_25; // @[VAluInt.scala 1299:50]
- wire [7:0] _mul1_T_27 = io_op_mul1_muls ? muls1_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] mul1_3 = _mul1_T_26 | _mul1_T_27; // @[VAluInt.scala 1300:48]
- wire [15:0] mulw_3 = io_op_mul0_mulw ? prod0_3[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [7:0] rsub_3 = io_op_rsub_rsub ? rsubtr_3 : 8'h0; // @[Library.scala 32:8]
- wire [3:0] srans_shamt_3 = srans_b[27:24]; // @[VAluInt.scala 1084:22]
- wire [15:0] srans_srl_3 = srans_c[31:16] >> srans_shamt_3; // @[VAluInt.scala 1085:21]
- wire _srans_srs_T_22 = srans_c[31] & io_in_signed; // @[VAluInt.scala 1088:41]
- wire [3:0] _srans_srs_T_25 = 4'hf - srans_shamt_3; // @[VAluInt.scala 1089:68]
- wire [30:0] _srans_srs_T_26 = 31'hffff << _srans_srs_T_25; // @[VAluInt.scala 1089:47]
- wire [15:0] srans_srs_3 = _srans_srs_T_22 ? _srans_srs_T_26[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] srans_sra_3 = srans_srs_3 | srans_srl_3; // @[VAluInt.scala 1090:23]
- wire [15:0] _srans_rbit_T_10 = {srans_c[30:16],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] _srans_rbit_T_11 = _srans_rbit_T_10 >> srans_shamt_3; // @[VAluInt.scala 1093:53]
- wire srans_rbit_3 = _srans_rbit_T_11[0]; // @[VAluInt.scala 1093:53]
- wire [15:0] _srans_rshf_T_11 = srans_sra_3 + 16'h1; // @[VAluInt.scala 1099:43]
- wire [15:0] srans_rshf_3 = io_in_round & srans_rbit_3 ? _srans_rshf_T_11 : srans_sra_3; // @[VAluInt.scala 1099:23]
- wire srans_is_umax_3 = _sataddsel_T_4 & srans_rshf_3 > 16'hff; // @[VAluInt.scala 1101:31]
- wire [15:0] _srans_is_smax_T_6 = io_in_round & srans_rbit_3 ? _srans_rshf_T_11 : srans_sra_3; // @[VAluInt.scala 1103:40]
- wire srans_is_smax_3 = io_in_signed & $signed(_srans_is_smax_T_6) > 16'sh7f; // @[VAluInt.scala 1103:31]
- wire srans_is_smin_3 = io_in_signed & $signed(_srans_is_smax_T_6) < $signed(srans_smin); // @[VAluInt.scala 1104:31]
- wire srans_is_norm_3 = ~(srans_is_umax_3 | srans_is_smax_3 | srans_is_smin_3); // @[VAluInt.scala 1105:23]
- wire [3:0] _srans_T_53 = {srans_is_umax_3,srans_is_smax_3,srans_is_smin_3,srans_is_norm_3}; // @[Cat.scala 31:58]
- wire [1:0] _srans_T_58 = _srans_T_53[0] + _srans_T_53[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _srans_T_60 = _srans_T_53[2] + _srans_T_53[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _srans_T_62 = _srans_T_58 + _srans_T_60; // @[Bitwise.scala 48:55]
- wire [7:0] _srans_r_T_33 = srans_is_umax_3 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _srans_r_T_36 = srans_is_smax_3 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _srans_r_T_37 = _srans_r_T_33 | _srans_r_T_36; // @[VAluInt.scala 1108:58]
- wire [7:0] _srans_r_T_40 = srans_is_smin_3 ? _srans_r_T_5[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _srans_r_T_41 = _srans_r_T_37 | _srans_r_T_40; // @[VAluInt.scala 1109:58]
- wire [7:0] _srans_r_T_43 = srans_is_norm_3 ? srans_rshf_3[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] srans_3 = _srans_r_T_41 | _srans_r_T_43; // @[VAluInt.scala 1110:58]
- wire [4:0] sraqs_shamt_3 = sraqs_b[28:24]; // @[VAluInt.scala 1084:22]
- wire [31:0] sraqs_srl_3 = sraqs_f >> sraqs_shamt_3; // @[VAluInt.scala 1085:21]
- wire _sraqs_srs_T_22 = sraqs_f[31] & io_in_signed; // @[VAluInt.scala 1088:41]
- wire [4:0] _sraqs_srs_T_25 = 5'h1f - sraqs_shamt_3; // @[VAluInt.scala 1089:68]
- wire [62:0] _sraqs_srs_T_26 = 63'hffffffff << _sraqs_srs_T_25; // @[VAluInt.scala 1089:47]
- wire [31:0] sraqs_srs_3 = _sraqs_srs_T_22 ? _sraqs_srs_T_26[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sraqs_sra_3 = sraqs_srs_3 | sraqs_srl_3; // @[VAluInt.scala 1090:23]
- wire [31:0] _sraqs_rbit_T_10 = {sraqs_f[30:0],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] _sraqs_rbit_T_11 = _sraqs_rbit_T_10 >> sraqs_shamt_3; // @[VAluInt.scala 1093:53]
- wire sraqs_rbit_3 = _sraqs_rbit_T_11[0]; // @[VAluInt.scala 1093:53]
- wire [31:0] _sraqs_rshf_T_11 = sraqs_sra_3 + 32'h1; // @[VAluInt.scala 1099:43]
- wire [31:0] sraqs_rshf_3 = io_in_round & sraqs_rbit_3 ? _sraqs_rshf_T_11 : sraqs_sra_3; // @[VAluInt.scala 1099:23]
- wire sraqs_is_umax_3 = _sataddsel_T_4 & sraqs_rshf_3 > 32'hff; // @[VAluInt.scala 1101:31]
- wire [31:0] _sraqs_is_smax_T_6 = io_in_round & sraqs_rbit_3 ? _sraqs_rshf_T_11 : sraqs_sra_3; // @[VAluInt.scala 1103:40]
- wire sraqs_is_smax_3 = io_in_signed & $signed(_sraqs_is_smax_T_6) > 32'sh7f; // @[VAluInt.scala 1103:31]
- wire sraqs_is_smin_3 = io_in_signed & $signed(_sraqs_is_smax_T_6) < $signed(sraqs_smin); // @[VAluInt.scala 1104:31]
- wire sraqs_is_norm_3 = ~(sraqs_is_umax_3 | sraqs_is_smax_3 | sraqs_is_smin_3); // @[VAluInt.scala 1105:23]
- wire [3:0] _sraqs_T_53 = {sraqs_is_umax_3,sraqs_is_smax_3,sraqs_is_smin_3,sraqs_is_norm_3}; // @[Cat.scala 31:58]
- wire [1:0] _sraqs_T_58 = _sraqs_T_53[0] + _sraqs_T_53[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _sraqs_T_60 = _sraqs_T_53[2] + _sraqs_T_53[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _sraqs_T_62 = _sraqs_T_58 + _sraqs_T_60; // @[Bitwise.scala 48:55]
- wire [7:0] _sraqs_r_T_33 = sraqs_is_umax_3 ? 8'hff : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sraqs_r_T_36 = sraqs_is_smax_3 ? 8'h7f : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sraqs_r_T_37 = _sraqs_r_T_33 | _sraqs_r_T_36; // @[VAluInt.scala 1108:58]
- wire [7:0] _sraqs_r_T_40 = sraqs_is_smin_3 ? _sraqs_r_T_5[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sraqs_r_T_41 = _sraqs_r_T_37 | _sraqs_r_T_40; // @[VAluInt.scala 1109:58]
- wire [7:0] _sraqs_r_T_43 = sraqs_is_norm_3 ? sraqs_rshf_3[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] sraqs_3 = _sraqs_r_T_41 | _sraqs_r_T_43; // @[VAluInt.scala 1110:58]
- wire _sub_T_64 = satsubsel_3[2] & io_op_sub_subs; // @[VAluInt.scala 1348:36]
- wire [7:0] _sub_T_66 = _sub_T_64 ? 8'h80 : 8'h0; // @[Library.scala 32:8]
- wire _sub_T_68 = satsubsel_3[1] & io_op_sub_subs; // @[VAluInt.scala 1349:36]
- wire [6:0] _sub_T_70 = _sub_T_68 ? 7'h7f : 7'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_105 = {{1'd0}, _sub_T_70}; // @[VAluInt.scala 1348:89]
- wire [7:0] _sub_T_71 = _sub_T_66 | _GEN_105; // @[VAluInt.scala 1348:89]
- wire _sub_T_78 = satsubsel_3 == 3'h0 & io_op_sub_subs | io_op_sub_sub; // @[VAluInt.scala 1351:59]
- wire [7:0] _sub_T_80 = _sub_T_78 ? subtr_3[7:0] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _sub_T_81 = _sub_T_71 | _sub_T_80; // @[VAluInt.scala 1350:68]
- wire [7:0] _sub_T_83 = io_op_sub_hsub ? subtr_3[8:1] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] sub_3 = _sub_T_81 | _sub_T_83; // @[VAluInt.scala 1351:97]
- wire subw_r_r_3_2 = subtr_3[9]; // @[Library.scala 64:25]
- wire [15:0] subw_r_3 = {subw_r_r_3_2,subw_r_r_3_2,subw_r_r_3_2,subw_r_r_3_2,subw_r_r_3_2,subw_r_r_3_2,subtr_3}; // @[Cat.scala 31:58]
- wire [15:0] subw_3 = io_op_sub_subw ? subw_r_3 : 16'h0; // @[Library.scala 32:8]
- wire _cmp_T_109 = io_op_cmp_eq & xeq_3; // @[Library.scala 36:8]
- wire _cmp_T_110 = io_op_cmp_ne & xne_3; // @[Library.scala 36:8]
- wire _cmp_T_111 = _cmp_T_109 | _cmp_T_110; // @[VAluInt.scala 1358:45]
- wire _cmp_T_113 = _cmp_T_4 & slt_3; // @[Library.scala 36:8]
- wire _cmp_T_114 = _cmp_T_111 | _cmp_T_113; // @[VAluInt.scala 1359:45]
- wire _cmp_T_117 = _cmp_T_8 & ult_3; // @[Library.scala 36:8]
- wire _cmp_T_118 = _cmp_T_114 | _cmp_T_117; // @[VAluInt.scala 1360:56]
- wire _cmp_T_120 = _cmp_T_11 & sle_3; // @[Library.scala 36:8]
- wire _cmp_T_121 = _cmp_T_118 | _cmp_T_120; // @[VAluInt.scala 1361:56]
- wire _cmp_T_124 = _cmp_T_15 & ule_3; // @[Library.scala 36:8]
- wire _cmp_T_125 = _cmp_T_121 | _cmp_T_124; // @[VAluInt.scala 1362:56]
- wire _cmp_T_127 = ~sle_3; // @[VAluInt.scala 1364:51]
- wire _cmp_T_128 = _cmp_T_18 & _cmp_T_127; // @[Library.scala 36:8]
- wire _cmp_T_129 = _cmp_T_125 | _cmp_T_128; // @[VAluInt.scala 1363:56]
- wire _cmp_T_132 = ~ule_3; // @[VAluInt.scala 1365:51]
- wire _cmp_T_133 = _cmp_T_23 & _cmp_T_132; // @[Library.scala 36:8]
- wire _cmp_T_134 = _cmp_T_129 | _cmp_T_133; // @[VAluInt.scala 1364:57]
- wire _cmp_T_136 = ~slt_3; // @[VAluInt.scala 1366:51]
- wire _cmp_T_137 = _cmp_T_27 & _cmp_T_136; // @[Library.scala 36:8]
- wire _cmp_T_138 = _cmp_T_134 | _cmp_T_137; // @[VAluInt.scala 1365:57]
- wire _cmp_T_141 = ~ult_3; // @[VAluInt.scala 1367:51]
- wire _cmp_T_142 = _cmp_T_32 & _cmp_T_141; // @[Library.scala 36:8]
- wire _cmp_T_143 = _cmp_T_138 | _cmp_T_142; // @[VAluInt.scala 1366:57]
- wire cmp_3 = io_in_sz[0] & _cmp_T_143; // @[VAluInt.scala 1357:30]
- wire [7:0] _log_T_341 = log_a[31:24] & log_b[31:24]; // @[VAluInt.scala 1371:42]
- wire [7:0] _log_T_342 = io_op_log_and ? _log_T_341 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_345 = log_a[31:24] | log_b[31:24]; // @[VAluInt.scala 1372:42]
- wire [7:0] _log_T_346 = io_op_log_or ? _log_T_345 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_347 = _log_T_342 | _log_T_346; // @[VAluInt.scala 1371:56]
- wire [7:0] _log_T_350 = log_a[31:24] ^ log_b[31:24]; // @[VAluInt.scala 1373:42]
- wire [7:0] _log_T_351 = io_op_log_xor ? _log_T_350 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_352 = _log_T_347 | _log_T_351; // @[VAluInt.scala 1372:56]
- wire [7:0] _log_T_355 = ~log_a[31:24]; // @[VAluInt.scala 1374:51]
- wire [7:0] _log_T_356 = io_in_sz[0] ? _log_T_355 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_357 = io_op_log_not ? _log_T_356 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_358 = _log_T_352 | _log_T_357; // @[VAluInt.scala 1373:56]
- wire _log_b_T_49 = ~log_b[24]; // @[VAluInt.scala 1151:23]
- wire [7:0] _log_b_T_58 = {log_a[30],log_a[31],log_a[28],log_a[29],log_a[26],log_a[27],log_a[24],log_a[25]}; // @[Cat.scala 31:58]
- wire [7:0] log_b_7 = ~log_b[24] ? log_a[31:24] : _log_b_T_58; // @[VAluInt.scala 1151:22]
- wire _log_c_T_37 = ~log_b[25]; // @[VAluInt.scala 1152:23]
- wire [7:0] _log_c_T_42 = {log_b_7[5:4],log_b_7[7:6],log_b_7[1:0],log_b_7[3:2]}; // @[Cat.scala 31:58]
- wire [7:0] log_c_6 = ~log_b[25] ? log_b_7 : _log_c_T_42; // @[VAluInt.scala 1152:22]
- wire _log_d_T_31 = ~log_b[26]; // @[VAluInt.scala 1153:23]
- wire [7:0] _log_d_T_34 = {log_c_6[3:0],log_c_6[7:4]}; // @[Cat.scala 31:58]
- wire [7:0] log_d_6 = ~log_b[26] ? log_c_6 : _log_d_T_34; // @[VAluInt.scala 1153:22]
- wire [7:0] _log_T_361 = io_op_log_rev ? log_d_6 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_362 = _log_T_358 | _log_T_361; // @[VAluInt.scala 1374:65]
- wire [7:0] _log_b_T_63 = {log_a[24],log_a[31:25]}; // @[Cat.scala 31:58]
- wire [7:0] log_b_8 = _log_b_T_49 ? log_a[31:24] : _log_b_T_63; // @[VAluInt.scala 1188:22]
- wire [7:0] _log_c_T_47 = {log_b_8[1:0],log_b_8[7:2]}; // @[Cat.scala 31:58]
- wire [7:0] log_c_7 = _log_c_T_37 ? log_b_8 : _log_c_T_47; // @[VAluInt.scala 1189:22]
- wire [7:0] _log_d_T_39 = {log_c_7[3:0],log_c_7[7:4]}; // @[Cat.scala 31:58]
- wire [7:0] log_d_7 = _log_d_T_31 ? log_c_7 : _log_d_T_39; // @[VAluInt.scala 1190:22]
- wire [7:0] _log_T_366 = io_in_sz[0] ? log_d_7 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_367 = io_op_log_ror ? _log_T_366 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _log_T_368 = _log_T_362 | _log_T_367; // @[VAluInt.scala 1375:60]
- wire [7:0] _GEN_106 = {{4'd0}, _log_T_355[7:4]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_145 = _GEN_106 & 8'hf; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_147 = {_log_T_355[3:0], 4'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clo_T_149 = _log_clo_T_147 & 8'hf0; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clo_T_150 = _log_clo_T_145 | _log_clo_T_149; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_107 = {{2'd0}, _log_clo_T_150[7:2]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_155 = _GEN_107 & 8'h33; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_157 = {_log_clo_T_150[5:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clo_T_159 = _log_clo_T_157 & 8'hcc; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clo_T_160 = _log_clo_T_155 | _log_clo_T_159; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_108 = {{1'd0}, _log_clo_T_160[7:1]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_165 = _GEN_108 & 8'h55; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clo_T_167 = {_log_clo_T_160[6:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clo_T_169 = _log_clo_T_167 & 8'haa; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clo_T_170 = _log_clo_T_165 | _log_clo_T_169; // @[Bitwise.scala 105:39]
- wire [8:0] _log_clo_T_171 = {1'h1,_log_clo_T_170}; // @[Cat.scala 31:58]
- wire [3:0] _log_clo_T_181 = _log_clo_T_171[7] ? 4'h7 : 4'h8; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_182 = _log_clo_T_171[6] ? 4'h6 : _log_clo_T_181; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_183 = _log_clo_T_171[5] ? 4'h5 : _log_clo_T_182; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_184 = _log_clo_T_171[4] ? 4'h4 : _log_clo_T_183; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_185 = _log_clo_T_171[3] ? 4'h3 : _log_clo_T_184; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_186 = _log_clo_T_171[2] ? 4'h2 : _log_clo_T_185; // @[Mux.scala 47:70]
- wire [3:0] _log_clo_T_187 = _log_clo_T_171[1] ? 4'h1 : _log_clo_T_186; // @[Mux.scala 47:70]
- wire [3:0] log_clo_3 = _log_clo_T_171[0] ? 4'h0 : _log_clo_T_187; // @[Mux.scala 47:70]
- wire [7:0] _GEN_109 = {{4'd0}, log_a[31:28]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_141 = _GEN_109 & 8'hf; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_143 = {log_a[27:24], 4'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clz_T_145 = _log_clz_T_143 & 8'hf0; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clz_T_146 = _log_clz_T_141 | _log_clz_T_145; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_110 = {{2'd0}, _log_clz_T_146[7:2]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_151 = _GEN_110 & 8'h33; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_153 = {_log_clz_T_146[5:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clz_T_155 = _log_clz_T_153 & 8'hcc; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clz_T_156 = _log_clz_T_151 | _log_clz_T_155; // @[Bitwise.scala 105:39]
- wire [7:0] _GEN_111 = {{1'd0}, _log_clz_T_156[7:1]}; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_161 = _GEN_111 & 8'h55; // @[Bitwise.scala 105:31]
- wire [7:0] _log_clz_T_163 = {_log_clz_T_156[6:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [7:0] _log_clz_T_165 = _log_clz_T_163 & 8'haa; // @[Bitwise.scala 105:80]
- wire [7:0] _log_clz_T_166 = _log_clz_T_161 | _log_clz_T_165; // @[Bitwise.scala 105:39]
- wire [8:0] _log_clz_T_167 = {1'h1,_log_clz_T_166}; // @[Cat.scala 31:58]
- wire [3:0] _log_clz_T_177 = _log_clz_T_167[7] ? 4'h7 : 4'h8; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_178 = _log_clz_T_167[6] ? 4'h6 : _log_clz_T_177; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_179 = _log_clz_T_167[5] ? 4'h5 : _log_clz_T_178; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_180 = _log_clz_T_167[4] ? 4'h4 : _log_clz_T_179; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_181 = _log_clz_T_167[3] ? 4'h3 : _log_clz_T_180; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_182 = _log_clz_T_167[2] ? 4'h2 : _log_clz_T_181; // @[Mux.scala 47:70]
- wire [3:0] _log_clz_T_183 = _log_clz_T_167[1] ? 4'h1 : _log_clz_T_182; // @[Mux.scala 47:70]
- wire [3:0] log_clz_3 = _log_clz_T_167[0] ? 4'h0 : _log_clz_T_183; // @[Mux.scala 47:70]
- wire [3:0] _log_T_372 = log_a[31] ? log_clo_3 : log_clz_3; // @[Library.scala 289:8]
- wire [3:0] _log_T_373 = io_in_sz[0] ? _log_T_372 : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _log_T_374 = io_op_log_clb ? _log_T_373 : 4'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_112 = {{4'd0}, _log_T_374}; // @[VAluInt.scala 1376:81]
- wire [7:0] _log_T_375 = _log_T_368 | _GEN_112; // @[VAluInt.scala 1376:81]
- wire [3:0] _log_T_425 = io_in_sz[0] ? log_clz_3 : 4'h0; // @[Library.scala 32:8]
- wire [3:0] _log_T_426 = io_op_log_clz ? _log_T_425 : 4'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_116 = {{4'd0}, _log_T_426}; // @[VAluInt.scala 1377:69]
- wire [7:0] _log_T_427 = _log_T_375 | _GEN_116; // @[VAluInt.scala 1377:69]
- wire [1:0] _log_T_437 = log_a[24] + log_a[25]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_439 = log_a[26] + log_a[27]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_441 = _log_T_437 + _log_T_439; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_443 = log_a[28] + log_a[29]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_445 = log_a[30] + log_a[31]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_447 = _log_T_443 + _log_T_445; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_449 = _log_T_441 + _log_T_447; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_451 = io_op_log_cpop ? _log_T_449 : 4'h0; // @[Library.scala 32:8]
- wire [7:0] _GEN_117 = {{4'd0}, _log_T_451}; // @[VAluInt.scala 1378:69]
- wire [7:0] log_3 = _log_T_427 | _GEN_117; // @[VAluInt.scala 1378:69]
- wire [7:0] _shift_T_12 = io_op_shf_shl ? shl_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shift_T_13 = io_op_shf_shr ? shr_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _shift_T_14 = _shift_T_12 | _shift_T_13; // @[VAluInt.scala 1383:35]
- wire [7:0] _shift_T_15 = io_op_shf_shf ? shf_3 : 8'h0; // @[Library.scala 32:8]
- wire [7:0] shift_3 = _shift_T_14 | _shift_T_15; // @[VAluInt.scala 1384:35]
- wire _alu_oh_T_42 = absd_3 != 8'h0; // @[VAluInt.scala 1388:30]
- wire _alu_oh_T_43 = add_3 != 8'h0; // @[VAluInt.scala 1389:30]
- wire _alu_oh_T_45 = dup_3 != 8'h0; // @[VAluInt.scala 1391:30]
- wire _alu_oh_T_46 = log_3 != 8'h0; // @[VAluInt.scala 1392:30]
- wire _alu_oh_T_47 = max_3 != 8'h0; // @[VAluInt.scala 1393:30]
- wire _alu_oh_T_48 = min_3 != 8'h0; // @[VAluInt.scala 1394:30]
- wire _alu_oh_T_49 = mul0_3 != 8'h0; // @[VAluInt.scala 1395:30]
- wire _alu_oh_T_51 = rsub_3 != 8'h0; // @[VAluInt.scala 1397:30]
- wire _alu_oh_T_52 = shift_3 != 8'h0; // @[VAluInt.scala 1398:30]
- wire _alu_oh_T_53 = srans_3 != 8'h0; // @[VAluInt.scala 1399:30]
- wire _alu_oh_T_54 = sraqs_3 != 8'h0; // @[VAluInt.scala 1400:30]
- wire _alu_oh_T_55 = sub_3 != 8'h0; // @[VAluInt.scala 1401:30]
- wire [6:0] alu_oh_lo_3 = {_alu_oh_T_49,1'h0,_alu_oh_T_51,_alu_oh_T_52,_alu_oh_T_53,_alu_oh_T_54,_alu_oh_T_55}; // @[Cat.scala 31:58]
- wire [13:0] alu_oh_3 = {_alu_oh_T_42,_alu_oh_T_43,cmp_3,_alu_oh_T_45,_alu_oh_T_46,_alu_oh_T_47,_alu_oh_T_48,
- alu_oh_lo_3}; // @[Cat.scala 31:58]
- wire [1:0] _T_354 = alu_oh_3[1] + alu_oh_3[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_118 = {{1'd0}, alu_oh_3[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_356 = _GEN_118 + _T_354; // @[Bitwise.scala 48:55]
- wire [1:0] _T_358 = alu_oh_3[3] + alu_oh_3[4]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_360 = alu_oh_3[5] + alu_oh_3[6]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_362 = _T_358 + _T_360; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_119 = {{1'd0}, _T_356[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_364 = _GEN_119 + _T_362; // @[Bitwise.scala 48:55]
- wire [1:0] _T_366 = alu_oh_3[8] + alu_oh_3[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_120 = {{1'd0}, alu_oh_3[7]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_368 = _GEN_120 + _T_366; // @[Bitwise.scala 48:55]
- wire [1:0] _T_370 = alu_oh_3[10] + alu_oh_3[11]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_372 = alu_oh_3[12] + alu_oh_3[13]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_374 = _T_370 + _T_372; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_121 = {{1'd0}, _T_368[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_376 = _GEN_121 + _T_374; // @[Bitwise.scala 48:55]
- wire [3:0] _T_378 = _T_364[2:0] + _T_376[2:0]; // @[Bitwise.scala 48:55]
- wire [7:0] _alu0_3_T = mul0_3 | absd_3; // @[VAluInt.scala 1405:23]
- wire [7:0] _alu0_3_T_1 = _alu0_3_T | add_3; // @[VAluInt.scala 1405:30]
- wire [7:0] _GEN_122 = {{7'd0}, cmp_3}; // @[VAluInt.scala 1405:36]
- wire [7:0] _alu0_3_T_2 = _alu0_3_T_1 | _GEN_122; // @[VAluInt.scala 1405:36]
- wire [7:0] _alu0_3_T_3 = _alu0_3_T_2 | dup_3; // @[VAluInt.scala 1405:42]
- wire [7:0] _alu0_3_T_4 = _alu0_3_T_3 | log_3; // @[VAluInt.scala 1405:48]
- wire [7:0] _alu0_3_T_5 = _alu0_3_T_4 | max_3; // @[VAluInt.scala 1405:54]
- wire [7:0] _alu0_3_T_6 = _alu0_3_T_5 | min_3; // @[VAluInt.scala 1405:60]
- wire [7:0] _alu0_3_T_8 = _alu0_3_T_6 | rsub_3; // @[VAluInt.scala 1405:73]
- wire [7:0] _alu0_3_T_9 = _alu0_3_T_8 | shift_3; // @[VAluInt.scala 1405:80]
- wire [7:0] _alu0_3_T_10 = _alu0_3_T_9 | srans_3; // @[VAluInt.scala 1405:88]
- wire [7:0] _alu0_3_T_11 = _alu0_3_T_10 | sraqs_3; // @[VAluInt.scala 1405:96]
- wire [7:0] _alu0_3_T_12 = _alu0_3_T_11 | sub_3; // @[VAluInt.scala 1405:104]
- wire [7:0] _alu0_3_T_14 = io_op_mv ? ina_b[31:24] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] alu0__3 = _alu0_3_T_12 | _alu0_3_T_14; // @[VAluInt.scala 1405:110]
- wire [7:0] _alu1_3_T_1 = io_op_mvp ? inb_b[31:24] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] _alu1_3_T_2 = mul1_3 | _alu1_3_T_1; // @[VAluInt.scala 1408:23]
- wire [7:0] _alu1_3_T_4 = io_op_mv2 ? inc_b[31:24] : 8'h0; // @[Library.scala 32:8]
- wire [7:0] alu1__3 = _alu1_3_T_2 | _alu1_3_T_4; // @[VAluInt.scala 1409:44]
- wire [7:0] _GEN_123 = {{7'd0}, mulh0_rnd_3}; // @[VAluInt.scala 1412:29]
- wire [7:0] _rnd0_3_T = dmulh0_rnd_3 | _GEN_123; // @[VAluInt.scala 1412:29]
- wire [7:0] _GEN_124 = {{7'd0}, shf_rnd_3}; // @[VAluInt.scala 1412:41]
- wire [7:0] rnd0__3 = _rnd0_3_T | _GEN_124; // @[VAluInt.scala 1412:41]
- wire [7:0] _GEN_125 = {{7'd0}, mulh1_rnd_3}; // @[VAluInt.scala 1413:29]
- wire [7:0] rnd1__3 = dmulh1_rnd_3 | _GEN_125; // @[VAluInt.scala 1413:29]
- wire [15:0] _aluw1_1_T = acc_3 | addw_3; // @[VAluInt.scala 1419:31]
- wire [15:0] _aluw1_1_T_1 = _aluw1_1_T | mulw_3; // @[VAluInt.scala 1419:38]
- wire [15:0] aluw1__1 = _aluw1_1_T_1 | subw_3; // @[VAluInt.scala 1419:45]
- wire [31:0] outb0 = {alu0__3,alu0__2,alu0__1,alu0__0}; // @[VAluInt.scala 1424:25]
- wire [31:0] outb1 = {alu1__3,alu1__2,alu1__1,alu1__0}; // @[VAluInt.scala 1425:25]
- wire [31:0] rndb0 = {rnd0__3,rnd0__2,rnd0__1,rnd0__0}; // @[VAluInt.scala 1426:25]
- wire [31:0] rndb1 = {rnd1__3,rnd1__2,rnd1__1,rnd1__0}; // @[VAluInt.scala 1427:25]
- wire [31:0] outwb0 = {aluw0__1,aluw0__0}; // @[VAluInt.scala 1428:27]
- wire [31:0] outwb1 = {aluw1__1,aluw1__0}; // @[VAluInt.scala 1429:27]
- wire [31:0] acc_a_1 = io_op_acc ? ina_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] acc_b_1 = io_op_acc ? inb_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] acc_c_1 = io_op_acc ? inc_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] add_a_1 = io_op_add_en ? ina_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] add_b_1 = io_op_add_en ? inb_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] cmp_a_1 = io_op_cmp_en ? ina_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] cmp_b_1 = io_op_cmp_en ? inb_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] log_a_1 = io_op_log_en ? ina_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] log_b_9 = io_op_log_en ? inb_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul0_a_1 = io_op_mul0_en ? ina_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul0_b_1 = io_op_mul0_en ? inb_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul1_a_1 = io_op_mul1_en ? inc_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul1_b_1 = io_op_mul1_en ? inb_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] padd_a_1 = io_op_padd_en ? ina_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] rsub_a_1 = io_op_rsub_en ? ina_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] rsub_b_1 = io_op_rsub_en ? inb_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shl_a_1 = io_op_shf_en_l ? ina_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shl_b_1 = io_op_shf_en_l ? inb_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shr_a_1 = io_op_shf_en_r ? ina_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shr_b_1 = io_op_shf_en_r ? inb_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] srans_a_1 = io_op_srans ? ina_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] srans_b_1 = io_op_srans ? inb_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] srans_c_1 = io_op_srans ? inc_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sub_a_1 = io_op_sub_en ? ina_h : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sub_b_1 = io_op_sub_en ? inb_h : 32'h0; // @[Library.scala 32:8]
- wire add_sa_4 = add_a_1[15] & io_in_signed; // @[VAluInt.scala 973:29]
- wire add_sb_4 = add_b_1[15] & io_in_signed; // @[VAluInt.scala 974:29]
- wire [16:0] _adder_T_38 = {add_sa_4,add_a_1[15:0]}; // @[VAluInt.scala 975:44]
- wire [16:0] _adder_T_41 = {add_sb_4,add_b_1[15:0]}; // @[VAluInt.scala 975:78]
- wire [17:0] _adder_T_43 = $signed(_adder_T_38) + $signed(_adder_T_41); // @[VAluInt.scala 975:86]
- wire [17:0] _GEN_126 = {{17'd0}, add_r}; // @[VAluInt.scala 975:93]
- wire [17:0] adder_4 = _adder_T_43 + _GEN_126; // @[VAluInt.scala 975:93]
- wire [1:0] sataddmsb_4 = adder_4[16:15]; // @[VAluInt.scala 976:28]
- wire _sataddsel_T_29 = io_in_signed & sataddmsb_4 == 2'h2; // @[VAluInt.scala 978:21]
- wire _sataddsel_T_31 = io_in_signed & sataddmsb_4 == 2'h1; // @[VAluInt.scala 979:21]
- wire _sataddsel_T_34 = ~io_in_signed & sataddmsb_4[1]; // @[VAluInt.scala 980:21]
- wire [2:0] sataddsel_4 = {_sataddsel_T_29,_sataddsel_T_31,_sataddsel_T_34}; // @[Cat.scala 31:58]
- wire [1:0] _T_387 = sataddsel_4[1] + sataddsel_4[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_127 = {{1'd0}, sataddsel_4[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_389 = _GEN_127 + _T_387; // @[Bitwise.scala 48:55]
- wire sub_sa_4 = sub_a_1[15] & io_in_signed; // @[VAluInt.scala 983:29]
- wire sub_sb_4 = sub_b_1[15] & io_in_signed; // @[VAluInt.scala 984:29]
- wire [16:0] _subtr_T_38 = {sub_sa_4,sub_a_1[15:0]}; // @[VAluInt.scala 985:44]
- wire [16:0] _subtr_T_41 = {sub_sb_4,sub_b_1[15:0]}; // @[VAluInt.scala 985:78]
- wire [17:0] _subtr_T_43 = $signed(_subtr_T_38) - $signed(_subtr_T_41); // @[VAluInt.scala 985:86]
- wire [17:0] _GEN_128 = {{17'd0}, sub_r}; // @[VAluInt.scala 985:93]
- wire [17:0] subtr_4 = _subtr_T_43 + _GEN_128; // @[VAluInt.scala 985:93]
- wire [1:0] satsubmsb_4 = subtr_4[16:15]; // @[VAluInt.scala 986:28]
- wire _satsubsel_T_29 = io_in_signed & satsubmsb_4 == 2'h2; // @[VAluInt.scala 988:21]
- wire _satsubsel_T_31 = io_in_signed & satsubmsb_4 == 2'h1; // @[VAluInt.scala 989:21]
- wire _satsubsel_T_34 = _sataddsel_T_4 & satsubmsb_4[1]; // @[VAluInt.scala 990:21]
- wire [2:0] satsubsel_4 = {_satsubsel_T_29,_satsubsel_T_31,_satsubsel_T_34}; // @[Cat.scala 31:58]
- wire [1:0] _T_398 = satsubsel_4[1] + satsubsel_4[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_129 = {{1'd0}, satsubsel_4[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_400 = _GEN_129 + _T_398; // @[Bitwise.scala 48:55]
- wire [15:0] rsubtr_4 = rsub_b_1[15:0] - rsub_a_1[15:0]; // @[VAluInt.scala 993:32]
- wire xeq_4 = cmp_a_1[15:0] == cmp_b_1[15:0]; // @[VAluInt.scala 995:28]
- wire xne_4 = cmp_a_1[15:0] != cmp_b_1[15:0]; // @[VAluInt.scala 996:28]
- wire [15:0] _slt_T_17 = cmp_a_1[15:0]; // @[VAluInt.scala 997:34]
- wire [15:0] _slt_T_19 = cmp_b_1[15:0]; // @[VAluInt.scala 997:56]
- wire slt_4 = $signed(_slt_T_17) < $signed(_slt_T_19); // @[VAluInt.scala 997:37]
- wire ult_4 = cmp_a_1[15:0] < cmp_b_1[15:0]; // @[VAluInt.scala 998:28]
- wire sle_4 = slt_4 | xeq_4; // @[VAluInt.scala 999:21]
- wire ule_4 = ult_4 | xeq_4; // @[VAluInt.scala 1000:21]
- wire sult_4 = io_in_signed ? slt_4 : ult_4; // @[VAluInt.scala 1002:21]
- wire [30:0] _GEN_38 = {{15'd0}, shl_a_1[15:0]}; // @[VAluInt.scala 1062:29]
- wire [30:0] _shl_T_14 = _GEN_38 << shl_b_1[3:0]; // @[VAluInt.scala 1062:29]
- wire [15:0] shl_4 = _shl_T_14[15:0]; // @[VAluInt.scala 1062:49]
- wire [4:0] _GEN_130 = {{1'd0}, shl_b_1[3:0]}; // @[VAluInt.scala 1063:40]
- wire [4:0] _sln_T_23 = 5'h10 - _GEN_130; // @[VAluInt.scala 1063:40]
- wire [46:0] _GEN_41 = {{31'd0}, shl_a_1[15:0]}; // @[VAluInt.scala 1063:29]
- wire [46:0] _sln_T_24 = _GEN_41 << _sln_T_23; // @[VAluInt.scala 1063:29]
- wire [30:0] sln_4 = _sln_T_24[30:0]; // @[VAluInt.scala 1063:60]
- wire [15:0] srl_4 = shr_a_1[15:0] >> shr_b_1[3:0]; // @[VAluInt.scala 1064:28]
- wire [3:0] _srs_T_32 = 4'hf - shr_b_1[3:0]; // @[VAluInt.scala 1065:66]
- wire [30:0] _srs_T_33 = 31'hffff << _srs_T_32; // @[VAluInt.scala 1065:49]
- wire [15:0] srs_4 = shr_a_1[15] ? _srs_T_33[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] sra_4 = srs_4 | srl_4; // @[VAluInt.scala 1066:21]
- wire [15:0] shf_slnsz_4 = sln_4[15:0]; // @[VAluInt.scala 1010:24]
- wire shf_input_neg_4 = shl_a_1[15]; // @[VAluInt.scala 1011:26]
- wire shf_input_zero_4 = shl_a_1[15:0] == 16'h0; // @[VAluInt.scala 1012:28]
- wire shf_shamt_neg_4 = shl_b_1[15]; // @[VAluInt.scala 1013:26]
- wire [15:0] _shf_shamt_negsat_T_20 = shl_b_1[15:0]; // @[VAluInt.scala 1017:32]
- wire shf_shamt_negsat_8 = $signed(_shf_shamt_negsat_T_20) <= -16'shf; // @[VAluInt.scala 1017:39]
- wire shf_shamt_possat_8 = $signed(_shf_shamt_negsat_T_20) >= 16'shf; // @[VAluInt.scala 1018:39]
- wire [3:0] _shf_signb_T_19 = shl_b_1[3:0] - 4'h1; // @[VAluInt.scala 1019:65]
- wire [15:0] shf_signb_4 = 16'hffff >> _shf_signb_T_19; // @[VAluInt.scala 1019:36]
- wire _shf_possat_T_54 = ~shf_input_zero_4; // @[VAluInt.scala 1020:112]
- wire shf_possat_8 = shf_shamt_neg_4 & ~shf_input_neg_4 & (shf_shamt_negsat_8 | sln_4[30:15] != 16'h0) & ~
- shf_input_zero_4; // @[VAluInt.scala 1020:109]
- wire shf_negsat_4 = shf_shamt_neg_4 & shf_input_neg_4 & (shf_shamt_negsat_8 | sln_4[30:15] != shf_signb_4); // @[VAluInt.scala 1021:48]
- wire _shf_rs_T_88 = ~shf_shamt_neg_4; // @[VAluInt.scala 1028:23]
- wire _shf_rs_T_90 = ~shf_shamt_neg_4 & ~shf_shamt_possat_8; // @[VAluInt.scala 1028:34]
- wire [15:0] _shf_rs_T_91 = _shf_rs_T_90 ? sra_4 : 16'h0; // @[Library.scala 32:8]
- wire _shf_rs_T_94 = _shf_rs_T_88 & shf_shamt_possat_8 & shf_input_neg_4; // @[VAluInt.scala 1029:51]
- wire [15:0] _shf_rs_T_96 = _shf_rs_T_94 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _shf_rs_T_97 = _shf_rs_T_91 | _shf_rs_T_96; // @[VAluInt.scala 1028:57]
- wire _shf_rs_T_101 = shf_shamt_neg_4 & ~shf_possat_8 & ~shf_negsat_4; // @[VAluInt.scala 1030:45]
- wire [15:0] _shf_rs_T_102 = _shf_rs_T_101 ? shf_slnsz_4 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _shf_rs_T_103 = _shf_rs_T_97 | _shf_rs_T_102; // @[VAluInt.scala 1029:79]
- wire _shf_rs_T_104 = shf_shamt_neg_4 & shf_possat_8; // @[VAluInt.scala 1031:34]
- wire [15:0] _shf_rs_T_105 = _shf_rs_T_104 ? 16'h7fff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _shf_rs_T_106 = _shf_rs_T_103 | _shf_rs_T_105; // @[VAluInt.scala 1030:64]
- wire _shf_rs_T_107 = shf_shamt_neg_4 & shf_negsat_4; // @[VAluInt.scala 1032:34]
- wire [15:0] _shf_rs_T_108 = _shf_rs_T_107 ? 16'h8000 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] shf_rs_4 = _shf_rs_T_106 | _shf_rs_T_108; // @[VAluInt.scala 1031:53]
- wire [5:0] _shf_shamt_negsat_T_24 = 6'sh0 - 6'sh10; // @[VAluInt.scala 1035:42]
- wire [15:0] _GEN_131 = {{10{_shf_shamt_negsat_T_24[5]}},_shf_shamt_negsat_T_24}; // @[VAluInt.scala 1035:39]
- wire shf_shamt_negsat_9 = $signed(_shf_shamt_negsat_T_20) <= $signed(_GEN_131); // @[VAluInt.scala 1035:39]
- wire shf_shamt_possat_9 = $signed(_shf_shamt_negsat_T_20) >= 16'sh10; // @[VAluInt.scala 1036:39]
- wire shf_possat_9 = shf_shamt_neg_4 & (shf_shamt_negsat_9 | sln_4[30:16] != 15'h0) & _shf_possat_T_54; // @[VAluInt.scala 1037:89]
- wire _shf_ru_T_46 = _shf_rs_T_88 & ~shf_shamt_possat_9; // @[VAluInt.scala 1041:34]
- wire [15:0] _shf_ru_T_47 = _shf_ru_T_46 ? srl_4 : 16'h0; // @[Library.scala 32:8]
- wire _shf_ru_T_49 = shf_shamt_neg_4 & ~shf_possat_9; // @[VAluInt.scala 1042:34]
- wire [15:0] _shf_ru_T_50 = _shf_ru_T_49 ? shf_slnsz_4 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _shf_ru_T_51 = _shf_ru_T_47 | _shf_ru_T_50; // @[VAluInt.scala 1041:57]
- wire _shf_ru_T_52 = shf_shamt_neg_4 & shf_possat_9; // @[VAluInt.scala 1043:34]
- wire [15:0] _shf_ru_T_53 = _shf_ru_T_52 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] shf_ru_4 = _shf_ru_T_51 | _shf_ru_T_53; // @[VAluInt.scala 1042:53]
- wire [15:0] shf_4 = io_in_signed ? shf_rs_4 : shf_ru_4; // @[VAluInt.scala 1045:12]
- wire [15:0] shr_4 = io_in_signed ? sra_4 : srl_4; // @[VAluInt.scala 1068:20]
- wire shf_rnd_shamt_zero_4 = shl_b_1[15:0] == 16'h0; // @[VAluInt.scala 1053:28]
- wire [15:0] _shf_rnd_rbit_T_22 = {shl_a_1[14:0],shf_input_neg_4}; // @[Cat.scala 31:58]
- wire [15:0] _shf_rnd_rbit_T_24 = _shf_rnd_rbit_T_22 >> shl_b_1[3:0]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_rbit_4 = _shf_rnd_rbit_T_24[0]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_shamt_possat_4 = io_in_signed ? shf_shamt_possat_9 : $signed(_shf_shamt_negsat_T_20) > 16'sh10; // @[VAluInt.scala 1055:31]
- wire _shf_rnd_r_T_49 = io_in_round & ~shf_rnd_shamt_possat_4 & _shf_rs_T_88 & ~shf_rnd_shamt_zero_4; // @[VAluInt.scala 1056:60]
- wire _shf_rnd_r_T_50 = _shf_rnd_r_T_49 & shf_rnd_rbit_4; // @[Library.scala 36:8]
- wire _shf_rnd_r_T_53 = io_in_round & shf_rnd_shamt_possat_4 & shf_input_neg_4 & io_in_signed; // @[VAluInt.scala 1057:59]
- wire shf_rnd_4 = _shf_rnd_r_T_50 | _shf_rnd_r_T_53; // @[VAluInt.scala 1056:82]
- wire _mul0_as_T_13 = io_in_signed & mul0_a_1[15]; // @[VAluInt.scala 1199:32]
- wire _mul0_bs_T_13 = io_in_signed & mul0_b_1[15]; // @[VAluInt.scala 1200:32]
- wire mul0_sign_4 = mul0_a_1[15] != mul0_b_1[15] & mul0_a_1[15:0] != 16'h0 & mul0_b_1[15:0] != 16'h0; // @[VAluInt.scala 1201:70]
- wire [16:0] _prod0_T_12 = {_mul0_as_T_13,mul0_a_1[15:0]}; // @[VAluInt.scala 1202:28]
- wire [16:0] _prod0_T_13 = {_mul0_bs_T_13,mul0_b_1[15:0]}; // @[VAluInt.scala 1202:45]
- wire [33:0] prod0_4 = $signed(_prod0_T_12) * $signed(_prod0_T_13); // @[VAluInt.scala 1202:53]
- wire [15:0] prodh0_4 = prod0_4[31:16]; // @[VAluInt.scala 1203:25]
- wire [15:0] proddh0_4 = prod0_4[30:15]; // @[VAluInt.scala 1204:26]
- wire _mul1_as_T_13 = io_in_signed & mul1_a_1[15]; // @[VAluInt.scala 1206:32]
- wire _mul1_bs_T_13 = io_in_signed & mul1_b_1[15]; // @[VAluInt.scala 1207:32]
- wire mul1_sign_4 = mul1_a_1[15] != mul1_b_1[15] & mul1_a_1[15:0] != 16'h0 & mul1_b_1[15:0] != 16'h0; // @[VAluInt.scala 1208:70]
- wire [16:0] _prod1_T_12 = {_mul1_as_T_13,mul1_a_1[15:0]}; // @[VAluInt.scala 1209:28]
- wire [16:0] _prod1_T_13 = {_mul1_bs_T_13,mul1_b_1[15:0]}; // @[VAluInt.scala 1209:45]
- wire [33:0] prod1_4 = $signed(_prod1_T_12) * $signed(_prod1_T_13); // @[VAluInt.scala 1209:53]
- wire [15:0] prodh1_4 = prod1_4[31:16]; // @[VAluInt.scala 1210:25]
- wire [15:0] proddh1_4 = prod1_4[30:15]; // @[VAluInt.scala 1211:26]
- wire _muls0_umax_T_9 = prodh0_4 != 16'h0; // @[VAluInt.scala 1213:42]
- wire muls0_umax_4 = _sataddsel_T_4 & prodh0_4 != 16'h0; // @[VAluInt.scala 1213:32]
- wire muls0_smax_4 = io_in_signed & ~mul0_sign_4 & (prod0_4[15] | _muls0_umax_T_9); // @[VAluInt.scala 1214:46]
- wire muls0_smin_4 = io_in_signed & mul0_sign_4 & (~prod0_4[15] | prodh0_4 != 16'hffff); // @[VAluInt.scala 1215:46]
- wire muls0_base_4 = ~(muls0_umax_4 | muls0_smax_4 | muls0_smin_4); // @[VAluInt.scala 1216:24]
- wire [3:0] _T_406 = {muls0_umax_4,muls0_smax_4,muls0_smin_4,muls0_base_4}; // @[Cat.scala 31:58]
- wire [1:0] _T_411 = _T_406[0] + _T_406[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_413 = _T_406[2] + _T_406[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_415 = _T_411 + _T_413; // @[Bitwise.scala 48:55]
- wire _muls1_umax_T_9 = prodh1_4 != 16'h0; // @[VAluInt.scala 1219:42]
- wire muls1_umax_4 = _sataddsel_T_4 & prodh1_4 != 16'h0; // @[VAluInt.scala 1219:32]
- wire muls1_smax_4 = io_in_signed & ~mul1_sign_4 & (prod1_4[15] | _muls1_umax_T_9); // @[VAluInt.scala 1220:46]
- wire muls1_smin_4 = io_in_signed & mul1_sign_4 & (~prod1_4[15] | prodh1_4 != 16'hffff); // @[VAluInt.scala 1221:46]
- wire muls1_base_4 = ~(muls1_umax_4 | muls1_smax_4 | muls1_smin_4); // @[VAluInt.scala 1222:24]
- wire [3:0] _T_421 = {muls1_umax_4,muls1_smax_4,muls1_smin_4,muls1_base_4}; // @[Cat.scala 31:58]
- wire [1:0] _T_426 = _T_421[0] + _T_421[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_428 = _T_421[2] + _T_421[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_430 = _T_426 + _T_428; // @[Bitwise.scala 48:55]
- wire dmulh0_possat_4 = mul0_a_1[15:0] == 16'h8000 & mul0_b_1[15:0] == 16'h8000; // @[VAluInt.scala 1227:50]
- wire dmulh1_possat_4 = mul1_a_1[15:0] == 16'h8000 & mul1_b_1[15:0] == 16'h8000; // @[VAluInt.scala 1229:50]
- wire _dmulh0_T_20 = ~dmulh0_possat_4; // @[VAluInt.scala 1231:26]
- wire [15:0] _dmulh0_T_21 = _dmulh0_T_20 ? proddh0_4 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _dmulh0_T_24 = dmulh0_possat_4 ? 16'h7fff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] dmulh0_4 = _dmulh0_T_21 | _dmulh0_T_24; // @[VAluInt.scala 1231:51]
- wire _dmulh1_T_20 = ~dmulh1_possat_4; // @[VAluInt.scala 1234:26]
- wire [15:0] _dmulh1_T_21 = _dmulh1_T_20 ? proddh1_4 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _dmulh1_T_24 = dmulh1_possat_4 ? 16'h7fff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] dmulh1_4 = _dmulh1_T_21 | _dmulh1_T_24; // @[VAluInt.scala 1234:51]
- wire [15:0] _muls0_T_41 = muls0_umax_4 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [14:0] _muls0_T_43 = muls0_smax_4 ? 15'h7fff : 15'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_132 = {{1'd0}, _muls0_T_43}; // @[VAluInt.scala 1240:51]
- wire [15:0] _muls0_T_44 = _muls0_T_41 | _GEN_132; // @[VAluInt.scala 1240:51]
- wire [15:0] _muls0_T_46 = muls0_smin_4 ? 16'h8000 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _muls0_T_47 = _muls0_T_44 | _muls0_T_46; // @[VAluInt.scala 1241:57]
- wire [15:0] _muls0_T_49 = muls0_base_4 ? prod0_4[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] muls0_4 = _muls0_T_47 | _muls0_T_49; // @[VAluInt.scala 1242:71]
- wire [15:0] _muls1_T_41 = muls1_umax_4 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [14:0] _muls1_T_43 = muls1_smax_4 ? 15'h7fff : 15'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_133 = {{1'd0}, _muls1_T_43}; // @[VAluInt.scala 1245:51]
- wire [15:0] _muls1_T_44 = _muls1_T_41 | _GEN_133; // @[VAluInt.scala 1245:51]
- wire [15:0] _muls1_T_46 = muls1_smin_4 ? 16'h8000 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _muls1_T_47 = _muls1_T_44 | _muls1_T_46; // @[VAluInt.scala 1246:57]
- wire [15:0] _muls1_T_49 = muls1_base_4 ? prod1_4[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] muls1_4 = _muls1_T_47 | _muls1_T_49; // @[VAluInt.scala 1247:71]
- wire _dmulh0_rnd_T_56 = io_in_round & io_op_mul0_dmulh & io_in_sz[1] & _dmulh0_T_20; // @[VAluInt.scala 1250:72]
- wire _dmulh0_rnd_T_59 = ~prod0_4[14]; // @[VAluInt.scala 1252:40]
- wire [15:0] _dmulh0_rnd_T_61 = _dmulh0_rnd_T_59 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _dmulh0_rnd_T_63 = prod0_4[14] ? 16'h1 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _dmulh0_rnd_T_64 = io_in_negative & mul0_sign_4 ? _dmulh0_rnd_T_61 : _dmulh0_rnd_T_63; // @[VAluInt.scala 1251:33]
- wire [15:0] dmulh0_rnd_4 = _dmulh0_rnd_T_56 ? _dmulh0_rnd_T_64 : 16'h0; // @[Library.scala 32:8]
- wire _dmulh1_rnd_T_56 = io_in_round & io_op_mul1_dmulh & io_in_sz[1] & _dmulh1_T_20; // @[VAluInt.scala 1255:72]
- wire _dmulh1_rnd_T_59 = ~prod1_4[14]; // @[VAluInt.scala 1257:40]
- wire [15:0] _dmulh1_rnd_T_61 = _dmulh1_rnd_T_59 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _dmulh1_rnd_T_63 = prod1_4[14] ? 16'h1 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _dmulh1_rnd_T_64 = io_in_negative & mul1_sign_4 ? _dmulh1_rnd_T_61 : _dmulh1_rnd_T_63; // @[VAluInt.scala 1256:33]
- wire [15:0] dmulh1_rnd_4 = _dmulh1_rnd_T_56 ? _dmulh1_rnd_T_64 : 16'h0; // @[Library.scala 32:8]
- wire mulh0_rnd_4 = io_in_round & io_op_mul0_mulh & prod0_4[15]; // @[VAluInt.scala 1260:48]
- wire mulh1_rnd_4 = io_in_round & io_op_mul1_mulh & prod1_4[15]; // @[VAluInt.scala 1261:48]
- wire [15:0] _absd_T_9 = sult_4 ? rsubtr_4 : subtr_4[15:0]; // @[VAluInt.scala 1265:39]
- wire [15:0] absd_4 = io_op_absd ? _absd_T_9 : 16'h0; // @[Library.scala 32:8]
- wire _acc_T_26 = io_in_signed & acc_b_1[15]; // @[VAluInt.scala 1270:55]
- wire [16:0] _acc_T_28 = {_acc_T_26,acc_b_1[15:0]}; // @[Cat.scala 31:58]
- wire acc_r_r_4_2 = _acc_T_28[16]; // @[Library.scala 64:25]
- wire [6:0] acc_r_lo_4 = {acc_r_r_4_2,acc_r_r_4_2,acc_r_r_4_2,acc_r_r_4_2,acc_r_r_4_2,acc_r_r_4_2,acc_r_r_4_2}; // @[Library.scala 57:7]
- wire [31:0] acc_r_4 = {acc_r_r_4_2,acc_r_r_4_2,acc_r_r_4_2,acc_r_r_4_2,acc_r_r_4_2,acc_r_r_4_2,acc_r_r_4_2,acc_r_r_4_2
- ,acc_r_lo_4,_acc_T_28}; // @[Cat.scala 31:58]
- wire [31:0] acc_4 = acc_a_1 + acc_r_4; // @[VAluInt.scala 1270:34]
- wire _add_T_93 = sataddsel_4[2] & io_op_add_adds; // @[VAluInt.scala 1279:36]
- wire [15:0] _add_T_95 = _add_T_93 ? 16'h8000 : 16'h0; // @[Library.scala 32:8]
- wire _add_T_97 = sataddsel_4[1] & io_op_add_adds; // @[VAluInt.scala 1280:36]
- wire [14:0] _add_T_99 = _add_T_97 ? 15'h7fff : 15'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_134 = {{1'd0}, _add_T_99}; // @[VAluInt.scala 1279:89]
- wire [15:0] _add_T_100 = _add_T_95 | _GEN_134; // @[VAluInt.scala 1279:89]
- wire _add_T_102 = sataddsel_4[0] & io_op_add_adds; // @[VAluInt.scala 1281:36]
- wire [15:0] _add_T_104 = _add_T_102 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _add_T_105 = _add_T_100 | _add_T_104; // @[VAluInt.scala 1280:75]
- wire _add_T_109 = sataddsel_4 == 3'h0 & io_op_add_adds | io_op_add_add | io_op_add_add3; // @[VAluInt.scala 1282:76]
- wire [15:0] _add_T_111 = _add_T_109 ? adder_4[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _add_T_112 = _add_T_105 | _add_T_111; // @[VAluInt.scala 1281:69]
- wire [15:0] _add_T_114 = io_op_add_hadd ? adder_4[16:1] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] add_4 = _add_T_112 | _add_T_114; // @[VAluInt.scala 1282:115]
- wire addw_r_r_4_2 = adder_4[17]; // @[Library.scala 64:25]
- wire [6:0] addw_r_lo_4 = {addw_r_r_4_2,addw_r_r_4_2,addw_r_r_4_2,addw_r_r_4_2,addw_r_r_4_2,addw_r_r_4_2,addw_r_r_4_2}; // @[Library.scala 57:7]
- wire [31:0] addw_r_4 = {addw_r_r_4_2,addw_r_r_4_2,addw_r_r_4_2,addw_r_r_4_2,addw_r_r_4_2,addw_r_r_4_2,addw_r_r_4_2,
- addw_r_lo_4,adder_4}; // @[Cat.scala 31:58]
- wire [31:0] addw_4 = io_op_add_addw ? addw_r_4 : 32'h0; // @[Library.scala 32:8]
- wire [15:0] dup_4 = io_op_dup ? io_read_1_data[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _max_T_14 = sult_4 ? cmp_b_1[15:0] : cmp_a_1[15:0]; // @[VAluInt.scala 1290:37]
- wire [15:0] max_4 = io_op_max ? _max_T_14 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _min_T_14 = sult_4 ? cmp_a_1[15:0] : cmp_b_1[15:0]; // @[VAluInt.scala 1291:37]
- wire [15:0] min_4 = io_op_min ? _min_T_14 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul0_T_34 = _mul0_T ? prod0_4[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul0_T_35 = io_op_mul0_dmulh ? dmulh0_4 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul0_T_36 = _mul0_T_34 | _mul0_T_35; // @[VAluInt.scala 1293:79]
- wire [15:0] _mul0_T_37 = io_op_mul0_mulh ? prodh0_4 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul0_T_38 = _mul0_T_36 | _mul0_T_37; // @[VAluInt.scala 1294:50]
- wire [15:0] _mul0_T_39 = io_op_mul0_muls ? muls0_4 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] mul0_4 = _mul0_T_38 | _mul0_T_39; // @[VAluInt.scala 1295:48]
- wire [15:0] _mul1_T_29 = io_op_mul1_mul ? prod1_4[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul1_T_30 = io_op_mul1_dmulh ? dmulh1_4 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul1_T_31 = _mul1_T_29 | _mul1_T_30; // @[VAluInt.scala 1298:60]
- wire [15:0] _mul1_T_32 = io_op_mul1_mulh ? prodh1_4 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul1_T_33 = _mul1_T_31 | _mul1_T_32; // @[VAluInt.scala 1299:50]
- wire [15:0] _mul1_T_34 = io_op_mul1_muls ? muls1_4 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] mul1_4 = _mul1_T_33 | _mul1_T_34; // @[VAluInt.scala 1300:48]
- wire [31:0] mulw_4 = io_op_mul0_mulw ? prod0_4[31:0] : 32'h0; // @[Library.scala 32:8]
- wire _padd_a_T_1 = io_in_signed & padd_a_1[7]; // @[VAluInt.scala 1311:30]
- wire _padd_b_T_1 = io_in_signed & padd_a_1[15]; // @[VAluInt.scala 1312:30]
- wire [8:0] _padd_add_T = {_padd_a_T_1,padd_a_1[7:0]}; // @[VAluInt.scala 1313:54]
- wire [8:0] _padd_add_T_1 = {_padd_b_T_1,padd_a_1[15:8]}; // @[VAluInt.scala 1313:66]
- wire [9:0] _padd_add_T_3 = $signed(_padd_add_T) + $signed(_padd_add_T_1); // @[VAluInt.scala 1313:74]
- wire padd_add_r_r__2 = _padd_add_T_3[9]; // @[Library.scala 64:25]
- wire [15:0] padd_add_r = {padd_add_r_r__2,padd_add_r_r__2,padd_add_r_r__2,padd_add_r_r__2,padd_add_r_r__2,
- padd_add_r_r__2,_padd_add_T_3}; // @[Cat.scala 31:58]
- wire [15:0] padd_add = io_op_padd_add ? padd_add_r : 16'h0; // @[Library.scala 32:8]
- wire [9:0] _padd_sub_T_3 = $signed(_padd_add_T) - $signed(_padd_add_T_1); // @[VAluInt.scala 1314:74]
- wire padd_sub_r_r__2 = _padd_sub_T_3[9]; // @[Library.scala 64:25]
- wire [15:0] padd_sub_r = {padd_sub_r_r__2,padd_sub_r_r__2,padd_sub_r_r__2,padd_sub_r_r__2,padd_sub_r_r__2,
- padd_sub_r_r__2,_padd_sub_T_3}; // @[Cat.scala 31:58]
- wire [15:0] padd_sub = io_op_padd_sub ? padd_sub_r : 16'h0; // @[Library.scala 32:8]
- wire [15:0] padd = padd_add | padd_sub; // @[VAluInt.scala 1317:15]
- wire [15:0] rsub_4 = io_op_rsub_rsub ? rsubtr_4 : 16'h0; // @[Library.scala 32:8]
- wire [4:0] srans_shamt_4 = srans_b_1[4:0]; // @[VAluInt.scala 1084:22]
- wire [31:0] srans_srl_4 = srans_a_1 >> srans_shamt_4; // @[VAluInt.scala 1085:21]
- wire _srans_srs_T_29 = srans_a_1[31] & io_in_signed; // @[VAluInt.scala 1088:41]
- wire [4:0] _srans_srs_T_32 = 5'h1f - srans_shamt_4; // @[VAluInt.scala 1089:68]
- wire [62:0] _srans_srs_T_33 = 63'hffffffff << _srans_srs_T_32; // @[VAluInt.scala 1089:47]
- wire [31:0] srans_srs_4 = _srans_srs_T_29 ? _srans_srs_T_33[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] srans_sra_4 = srans_srs_4 | srans_srl_4; // @[VAluInt.scala 1090:23]
- wire [31:0] _srans_rbit_T_13 = {srans_a_1[30:0],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] _srans_rbit_T_14 = _srans_rbit_T_13 >> srans_shamt_4; // @[VAluInt.scala 1093:53]
- wire srans_rbit_4 = _srans_rbit_T_14[0]; // @[VAluInt.scala 1093:53]
- wire [31:0] srans_smin_4 = 32'sh0 - 32'sh8000; // @[VAluInt.scala 1098:20]
- wire [31:0] _srans_rshf_T_14 = srans_sra_4 + 32'h1; // @[VAluInt.scala 1099:43]
- wire [31:0] srans_rshf_4 = io_in_round & srans_rbit_4 ? _srans_rshf_T_14 : srans_sra_4; // @[VAluInt.scala 1099:23]
- wire srans_is_umax_4 = _sataddsel_T_4 & srans_rshf_4 > 32'hffff; // @[VAluInt.scala 1101:31]
- wire [31:0] _srans_is_smax_T_8 = io_in_round & srans_rbit_4 ? _srans_rshf_T_14 : srans_sra_4; // @[VAluInt.scala 1103:40]
- wire srans_is_smax_4 = io_in_signed & $signed(_srans_is_smax_T_8) > 32'sh7fff; // @[VAluInt.scala 1103:31]
- wire srans_is_smin_4 = io_in_signed & $signed(_srans_is_smax_T_8) < $signed(srans_smin_4); // @[VAluInt.scala 1104:31]
- wire srans_is_norm_4 = ~(srans_is_umax_4 | srans_is_smax_4 | srans_is_smin_4); // @[VAluInt.scala 1105:23]
- wire [3:0] _srans_T_70 = {srans_is_umax_4,srans_is_smax_4,srans_is_smin_4,srans_is_norm_4}; // @[Cat.scala 31:58]
- wire [1:0] _srans_T_75 = _srans_T_70[0] + _srans_T_70[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _srans_T_77 = _srans_T_70[2] + _srans_T_70[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _srans_T_79 = _srans_T_75 + _srans_T_77; // @[Bitwise.scala 48:55]
- wire [15:0] _srans_r_T_44 = srans_is_umax_4 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _srans_r_T_47 = srans_is_smax_4 ? 16'h7fff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _srans_r_T_48 = _srans_r_T_44 | _srans_r_T_47; // @[VAluInt.scala 1108:58]
- wire [31:0] _srans_r_T_49 = 32'sh0 - 32'sh8000; // @[VAluInt.scala 1110:37]
- wire [15:0] _srans_r_T_51 = srans_is_smin_4 ? _srans_r_T_49[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _srans_r_T_52 = _srans_r_T_48 | _srans_r_T_51; // @[VAluInt.scala 1109:58]
- wire [15:0] _srans_r_T_54 = srans_is_norm_4 ? srans_rshf_4[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] srans_4 = _srans_r_T_52 | _srans_r_T_54; // @[VAluInt.scala 1110:58]
- wire _sub_T_85 = satsubsel_4[2] & io_op_sub_subs; // @[VAluInt.scala 1348:36]
- wire [15:0] _sub_T_87 = _sub_T_85 ? 16'h8000 : 16'h0; // @[Library.scala 32:8]
- wire _sub_T_89 = satsubsel_4[1] & io_op_sub_subs; // @[VAluInt.scala 1349:36]
- wire [14:0] _sub_T_91 = _sub_T_89 ? 15'h7fff : 15'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_135 = {{1'd0}, _sub_T_91}; // @[VAluInt.scala 1348:89]
- wire [15:0] _sub_T_92 = _sub_T_87 | _GEN_135; // @[VAluInt.scala 1348:89]
- wire _sub_T_99 = satsubsel_4 == 3'h0 & io_op_sub_subs | io_op_sub_sub; // @[VAluInt.scala 1351:59]
- wire [15:0] _sub_T_101 = _sub_T_99 ? subtr_4[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _sub_T_102 = _sub_T_92 | _sub_T_101; // @[VAluInt.scala 1350:68]
- wire [15:0] _sub_T_104 = io_op_sub_hsub ? subtr_4[16:1] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] sub_4 = _sub_T_102 | _sub_T_104; // @[VAluInt.scala 1351:97]
- wire subw_r_r_4_2 = subtr_4[17]; // @[Library.scala 64:25]
- wire [6:0] subw_r_lo_4 = {subw_r_r_4_2,subw_r_r_4_2,subw_r_r_4_2,subw_r_r_4_2,subw_r_r_4_2,subw_r_r_4_2,subw_r_r_4_2}; // @[Library.scala 57:7]
- wire [31:0] subw_r_4 = {subw_r_r_4_2,subw_r_r_4_2,subw_r_r_4_2,subw_r_r_4_2,subw_r_r_4_2,subw_r_r_4_2,subw_r_r_4_2,
- subw_r_lo_4,subtr_4}; // @[Cat.scala 31:58]
- wire [31:0] subw_4 = io_op_sub_subw ? subw_r_4 : 32'h0; // @[Library.scala 32:8]
- wire _cmp_T_145 = io_op_cmp_eq & xeq_4; // @[Library.scala 36:8]
- wire _cmp_T_146 = io_op_cmp_ne & xne_4; // @[Library.scala 36:8]
- wire _cmp_T_147 = _cmp_T_145 | _cmp_T_146; // @[VAluInt.scala 1358:45]
- wire _cmp_T_149 = _cmp_T_4 & slt_4; // @[Library.scala 36:8]
- wire _cmp_T_150 = _cmp_T_147 | _cmp_T_149; // @[VAluInt.scala 1359:45]
- wire _cmp_T_153 = _cmp_T_8 & ult_4; // @[Library.scala 36:8]
- wire _cmp_T_154 = _cmp_T_150 | _cmp_T_153; // @[VAluInt.scala 1360:56]
- wire _cmp_T_156 = _cmp_T_11 & sle_4; // @[Library.scala 36:8]
- wire _cmp_T_157 = _cmp_T_154 | _cmp_T_156; // @[VAluInt.scala 1361:56]
- wire _cmp_T_160 = _cmp_T_15 & ule_4; // @[Library.scala 36:8]
- wire _cmp_T_161 = _cmp_T_157 | _cmp_T_160; // @[VAluInt.scala 1362:56]
- wire _cmp_T_163 = ~sle_4; // @[VAluInt.scala 1364:51]
- wire _cmp_T_164 = _cmp_T_18 & _cmp_T_163; // @[Library.scala 36:8]
- wire _cmp_T_165 = _cmp_T_161 | _cmp_T_164; // @[VAluInt.scala 1363:56]
- wire _cmp_T_168 = ~ule_4; // @[VAluInt.scala 1365:51]
- wire _cmp_T_169 = _cmp_T_23 & _cmp_T_168; // @[Library.scala 36:8]
- wire _cmp_T_170 = _cmp_T_165 | _cmp_T_169; // @[VAluInt.scala 1364:57]
- wire _cmp_T_172 = ~slt_4; // @[VAluInt.scala 1366:51]
- wire _cmp_T_173 = _cmp_T_27 & _cmp_T_172; // @[Library.scala 36:8]
- wire _cmp_T_174 = _cmp_T_170 | _cmp_T_173; // @[VAluInt.scala 1365:57]
- wire _cmp_T_177 = ~ult_4; // @[VAluInt.scala 1367:51]
- wire _cmp_T_178 = _cmp_T_32 & _cmp_T_177; // @[Library.scala 36:8]
- wire _cmp_T_179 = _cmp_T_174 | _cmp_T_178; // @[VAluInt.scala 1366:57]
- wire cmp_4 = io_in_sz[1] & _cmp_T_179; // @[VAluInt.scala 1357:30]
- wire [15:0] _log_T_454 = log_a_1[15:0] & log_b_9[15:0]; // @[VAluInt.scala 1371:42]
- wire [15:0] _log_T_455 = io_op_log_and ? _log_T_454 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_458 = log_a_1[15:0] | log_b_9[15:0]; // @[VAluInt.scala 1372:42]
- wire [15:0] _log_T_459 = io_op_log_or ? _log_T_458 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_460 = _log_T_455 | _log_T_459; // @[VAluInt.scala 1371:56]
- wire [15:0] _log_T_463 = log_a_1[15:0] ^ log_b_9[15:0]; // @[VAluInt.scala 1373:42]
- wire [15:0] _log_T_464 = io_op_log_xor ? _log_T_463 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_465 = _log_T_460 | _log_T_464; // @[VAluInt.scala 1372:56]
- wire [15:0] _log_T_468 = ~log_a_1[15:0]; // @[VAluInt.scala 1374:51]
- wire [15:0] _log_T_469 = io_in_sz[1] ? _log_T_468 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_470 = io_op_log_not ? _log_T_469 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_471 = _log_T_465 | _log_T_470; // @[VAluInt.scala 1373:56]
- wire _log_b_T_65 = ~log_b_9[0]; // @[VAluInt.scala 1138:23]
- wire [7:0] log_b_lo_4 = {log_a_1[6],log_a_1[7],log_a_1[4],log_a_1[5],log_a_1[2],log_a_1[3],log_a_1[0],log_a_1[1]}; // @[Cat.scala 31:58]
- wire [15:0] _log_b_T_82 = {log_a_1[14],log_a_1[15],log_a_1[12],log_a_1[13],log_a_1[10],log_a_1[11],log_a_1[8],log_a_1[
- 9],log_b_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] log_b_10 = ~log_b_9[0] ? log_a_1[15:0] : _log_b_T_82; // @[VAluInt.scala 1138:22]
- wire _log_c_T_49 = ~log_b_9[1]; // @[VAluInt.scala 1140:23]
- wire [15:0] _log_c_T_58 = {log_b_10[13:12],log_b_10[15:14],log_b_10[9:8],log_b_10[11:10],log_b_10[5:4],log_b_10[7:6],
- log_b_10[1:0],log_b_10[3:2]}; // @[Cat.scala 31:58]
- wire [15:0] log_c_8 = ~log_b_9[1] ? log_b_10 : _log_c_T_58; // @[VAluInt.scala 1140:22]
- wire _log_d_T_41 = ~log_b_9[2]; // @[VAluInt.scala 1142:23]
- wire [15:0] _log_d_T_46 = {log_c_8[11:8],log_c_8[15:12],log_c_8[3:0],log_c_8[7:4]}; // @[Cat.scala 31:58]
- wire [15:0] log_d_8 = ~log_b_9[2] ? log_c_8 : _log_d_T_46; // @[VAluInt.scala 1142:22]
- wire _log_e_T_1 = ~log_b_9[3]; // @[VAluInt.scala 1143:23]
- wire [15:0] _log_e_T_4 = {log_d_8[7:0],log_d_8[15:8]}; // @[Cat.scala 31:58]
- wire [15:0] log_e = ~log_b_9[3] ? log_d_8 : _log_e_T_4; // @[VAluInt.scala 1143:22]
- wire [15:0] _log_T_474 = io_op_log_rev ? log_e : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_475 = _log_T_471 | _log_T_474; // @[VAluInt.scala 1374:65]
- wire [15:0] _log_b_T_87 = {log_a_1[0],log_a_1[15:1]}; // @[Cat.scala 31:58]
- wire [15:0] log_b_11 = _log_b_T_65 ? log_a_1[15:0] : _log_b_T_87; // @[VAluInt.scala 1177:22]
- wire [15:0] _log_c_T_63 = {log_b_11[1:0],log_b_11[15:2]}; // @[Cat.scala 31:58]
- wire [15:0] log_c_9 = _log_c_T_49 ? log_b_11 : _log_c_T_63; // @[VAluInt.scala 1178:22]
- wire [15:0] _log_d_T_51 = {log_c_9[3:0],log_c_9[15:4]}; // @[Cat.scala 31:58]
- wire [15:0] log_d_9 = _log_d_T_41 ? log_c_9 : _log_d_T_51; // @[VAluInt.scala 1179:22]
- wire [15:0] _log_e_T_9 = {log_d_9[7:0],log_d_9[15:8]}; // @[Cat.scala 31:58]
- wire [15:0] log_e_1 = _log_e_T_1 ? log_d_9 : _log_e_T_9; // @[VAluInt.scala 1180:22]
- wire [15:0] _log_T_479 = io_in_sz[1] ? log_e_1 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_480 = io_op_log_ror ? _log_T_479 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_481 = _log_T_475 | _log_T_480; // @[VAluInt.scala 1375:60]
- wire [15:0] _GEN_136 = {{8'd0}, _log_T_468[15:8]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_192 = _GEN_136 & 16'hff; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_194 = {_log_T_468[7:0], 8'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clo_T_196 = _log_clo_T_194 & 16'hff00; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clo_T_197 = _log_clo_T_192 | _log_clo_T_196; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_137 = {{4'd0}, _log_clo_T_197[15:4]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_202 = _GEN_137 & 16'hf0f; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_204 = {_log_clo_T_197[11:0], 4'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clo_T_206 = _log_clo_T_204 & 16'hf0f0; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clo_T_207 = _log_clo_T_202 | _log_clo_T_206; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_138 = {{2'd0}, _log_clo_T_207[15:2]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_212 = _GEN_138 & 16'h3333; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_214 = {_log_clo_T_207[13:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clo_T_216 = _log_clo_T_214 & 16'hcccc; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clo_T_217 = _log_clo_T_212 | _log_clo_T_216; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_139 = {{1'd0}, _log_clo_T_217[15:1]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_222 = _GEN_139 & 16'h5555; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_224 = {_log_clo_T_217[14:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clo_T_226 = _log_clo_T_224 & 16'haaaa; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clo_T_227 = _log_clo_T_222 | _log_clo_T_226; // @[Bitwise.scala 105:39]
- wire [16:0] _log_clo_T_228 = {1'h1,_log_clo_T_227}; // @[Cat.scala 31:58]
- wire [4:0] _log_clo_T_246 = _log_clo_T_228[15] ? 5'hf : 5'h10; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_247 = _log_clo_T_228[14] ? 5'he : _log_clo_T_246; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_248 = _log_clo_T_228[13] ? 5'hd : _log_clo_T_247; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_249 = _log_clo_T_228[12] ? 5'hc : _log_clo_T_248; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_250 = _log_clo_T_228[11] ? 5'hb : _log_clo_T_249; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_251 = _log_clo_T_228[10] ? 5'ha : _log_clo_T_250; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_252 = _log_clo_T_228[9] ? 5'h9 : _log_clo_T_251; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_253 = _log_clo_T_228[8] ? 5'h8 : _log_clo_T_252; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_254 = _log_clo_T_228[7] ? 5'h7 : _log_clo_T_253; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_255 = _log_clo_T_228[6] ? 5'h6 : _log_clo_T_254; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_256 = _log_clo_T_228[5] ? 5'h5 : _log_clo_T_255; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_257 = _log_clo_T_228[4] ? 5'h4 : _log_clo_T_256; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_258 = _log_clo_T_228[3] ? 5'h3 : _log_clo_T_257; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_259 = _log_clo_T_228[2] ? 5'h2 : _log_clo_T_258; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_260 = _log_clo_T_228[1] ? 5'h1 : _log_clo_T_259; // @[Mux.scala 47:70]
- wire [4:0] log_clo_4 = _log_clo_T_228[0] ? 5'h0 : _log_clo_T_260; // @[Mux.scala 47:70]
- wire [15:0] _GEN_140 = {{8'd0}, log_a_1[15:8]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_187 = _GEN_140 & 16'hff; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_189 = {log_a_1[7:0], 8'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clz_T_191 = _log_clz_T_189 & 16'hff00; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clz_T_192 = _log_clz_T_187 | _log_clz_T_191; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_141 = {{4'd0}, _log_clz_T_192[15:4]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_197 = _GEN_141 & 16'hf0f; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_199 = {_log_clz_T_192[11:0], 4'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clz_T_201 = _log_clz_T_199 & 16'hf0f0; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clz_T_202 = _log_clz_T_197 | _log_clz_T_201; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_142 = {{2'd0}, _log_clz_T_202[15:2]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_207 = _GEN_142 & 16'h3333; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_209 = {_log_clz_T_202[13:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clz_T_211 = _log_clz_T_209 & 16'hcccc; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clz_T_212 = _log_clz_T_207 | _log_clz_T_211; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_143 = {{1'd0}, _log_clz_T_212[15:1]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_217 = _GEN_143 & 16'h5555; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_219 = {_log_clz_T_212[14:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clz_T_221 = _log_clz_T_219 & 16'haaaa; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clz_T_222 = _log_clz_T_217 | _log_clz_T_221; // @[Bitwise.scala 105:39]
- wire [16:0] _log_clz_T_223 = {1'h1,_log_clz_T_222}; // @[Cat.scala 31:58]
- wire [4:0] _log_clz_T_241 = _log_clz_T_223[15] ? 5'hf : 5'h10; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_242 = _log_clz_T_223[14] ? 5'he : _log_clz_T_241; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_243 = _log_clz_T_223[13] ? 5'hd : _log_clz_T_242; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_244 = _log_clz_T_223[12] ? 5'hc : _log_clz_T_243; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_245 = _log_clz_T_223[11] ? 5'hb : _log_clz_T_244; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_246 = _log_clz_T_223[10] ? 5'ha : _log_clz_T_245; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_247 = _log_clz_T_223[9] ? 5'h9 : _log_clz_T_246; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_248 = _log_clz_T_223[8] ? 5'h8 : _log_clz_T_247; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_249 = _log_clz_T_223[7] ? 5'h7 : _log_clz_T_248; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_250 = _log_clz_T_223[6] ? 5'h6 : _log_clz_T_249; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_251 = _log_clz_T_223[5] ? 5'h5 : _log_clz_T_250; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_252 = _log_clz_T_223[4] ? 5'h4 : _log_clz_T_251; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_253 = _log_clz_T_223[3] ? 5'h3 : _log_clz_T_252; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_254 = _log_clz_T_223[2] ? 5'h2 : _log_clz_T_253; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_255 = _log_clz_T_223[1] ? 5'h1 : _log_clz_T_254; // @[Mux.scala 47:70]
- wire [4:0] log_clz_4 = _log_clz_T_223[0] ? 5'h0 : _log_clz_T_255; // @[Mux.scala 47:70]
- wire [4:0] _log_T_485 = log_a_1[15] ? log_clo_4 : log_clz_4; // @[Library.scala 289:8]
- wire [4:0] _log_T_486 = io_in_sz[1] ? _log_T_485 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _log_T_487 = io_op_log_clb ? _log_T_486 : 5'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_144 = {{11'd0}, _log_T_487}; // @[VAluInt.scala 1376:81]
- wire [15:0] _log_T_488 = _log_T_481 | _GEN_144; // @[VAluInt.scala 1376:81]
- wire [4:0] _log_T_564 = io_in_sz[1] ? log_clz_4 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _log_T_565 = io_op_log_clz ? _log_T_564 : 5'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_149 = {{11'd0}, _log_T_565}; // @[VAluInt.scala 1377:69]
- wire [15:0] _log_T_566 = _log_T_488 | _GEN_149; // @[VAluInt.scala 1377:69]
- wire [1:0] _log_T_584 = log_a_1[0] + log_a_1[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_586 = log_a_1[2] + log_a_1[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_588 = _log_T_584 + _log_T_586; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_590 = log_a_1[4] + log_a_1[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_592 = log_a_1[6] + log_a_1[7]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_594 = _log_T_590 + _log_T_592; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_596 = _log_T_588 + _log_T_594; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_598 = log_a_1[8] + log_a_1[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_600 = log_a_1[10] + log_a_1[11]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_602 = _log_T_598 + _log_T_600; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_604 = log_a_1[12] + log_a_1[13]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_606 = log_a_1[14] + log_a_1[15]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_608 = _log_T_604 + _log_T_606; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_610 = _log_T_602 + _log_T_608; // @[Bitwise.scala 48:55]
- wire [4:0] _log_T_612 = _log_T_596 + _log_T_610; // @[Bitwise.scala 48:55]
- wire [4:0] _log_T_614 = io_op_log_cpop ? _log_T_612 : 5'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_150 = {{11'd0}, _log_T_614}; // @[VAluInt.scala 1378:69]
- wire [15:0] log_4 = _log_T_566 | _GEN_150; // @[VAluInt.scala 1378:69]
- wire [15:0] _shift_T_16 = io_op_shf_shl ? shl_4 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _shift_T_17 = io_op_shf_shr ? shr_4 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _shift_T_18 = _shift_T_16 | _shift_T_17; // @[VAluInt.scala 1383:35]
- wire [15:0] _shift_T_19 = io_op_shf_shf ? shf_4 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] shift_4 = _shift_T_18 | _shift_T_19; // @[VAluInt.scala 1384:35]
- wire _alu_oh_T_56 = absd_4 != 16'h0; // @[VAluInt.scala 1388:30]
- wire _alu_oh_T_57 = add_4 != 16'h0; // @[VAluInt.scala 1389:30]
- wire _alu_oh_T_59 = dup_4 != 16'h0; // @[VAluInt.scala 1391:30]
- wire _alu_oh_T_60 = log_4 != 16'h0; // @[VAluInt.scala 1392:30]
- wire _alu_oh_T_61 = max_4 != 16'h0; // @[VAluInt.scala 1393:30]
- wire _alu_oh_T_62 = min_4 != 16'h0; // @[VAluInt.scala 1394:30]
- wire _alu_oh_T_63 = mul0_4 != 16'h0; // @[VAluInt.scala 1395:30]
- wire _alu_oh_T_64 = padd != 16'h0; // @[VAluInt.scala 1396:30]
- wire _alu_oh_T_65 = rsub_4 != 16'h0; // @[VAluInt.scala 1397:30]
- wire _alu_oh_T_66 = shift_4 != 16'h0; // @[VAluInt.scala 1398:30]
- wire _alu_oh_T_67 = srans_4 != 16'h0; // @[VAluInt.scala 1399:30]
- wire _alu_oh_T_69 = sub_4 != 16'h0; // @[VAluInt.scala 1401:30]
- wire [6:0] alu_oh_lo_4 = {_alu_oh_T_63,_alu_oh_T_64,_alu_oh_T_65,_alu_oh_T_66,_alu_oh_T_67,1'h0,_alu_oh_T_69}; // @[Cat.scala 31:58]
- wire [13:0] alu_oh_4 = {_alu_oh_T_56,_alu_oh_T_57,cmp_4,_alu_oh_T_59,_alu_oh_T_60,_alu_oh_T_61,_alu_oh_T_62,
- alu_oh_lo_4}; // @[Cat.scala 31:58]
- wire [1:0] _T_450 = alu_oh_4[1] + alu_oh_4[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_151 = {{1'd0}, alu_oh_4[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_452 = _GEN_151 + _T_450; // @[Bitwise.scala 48:55]
- wire [1:0] _T_454 = alu_oh_4[3] + alu_oh_4[4]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_456 = alu_oh_4[5] + alu_oh_4[6]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_458 = _T_454 + _T_456; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_152 = {{1'd0}, _T_452[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_460 = _GEN_152 + _T_458; // @[Bitwise.scala 48:55]
- wire [1:0] _T_462 = alu_oh_4[8] + alu_oh_4[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_153 = {{1'd0}, alu_oh_4[7]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_464 = _GEN_153 + _T_462; // @[Bitwise.scala 48:55]
- wire [1:0] _T_466 = alu_oh_4[10] + alu_oh_4[11]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_468 = alu_oh_4[12] + alu_oh_4[13]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_470 = _T_466 + _T_468; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_154 = {{1'd0}, _T_464[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_472 = _GEN_154 + _T_470; // @[Bitwise.scala 48:55]
- wire [3:0] _T_474 = _T_460[2:0] + _T_472[2:0]; // @[Bitwise.scala 48:55]
- wire [15:0] _alu0_0_T_16 = mul0_4 | absd_4; // @[VAluInt.scala 1405:23]
- wire [15:0] _alu0_0_T_17 = _alu0_0_T_16 | add_4; // @[VAluInt.scala 1405:30]
- wire [15:0] _GEN_155 = {{15'd0}, cmp_4}; // @[VAluInt.scala 1405:36]
- wire [15:0] _alu0_0_T_18 = _alu0_0_T_17 | _GEN_155; // @[VAluInt.scala 1405:36]
- wire [15:0] _alu0_0_T_19 = _alu0_0_T_18 | dup_4; // @[VAluInt.scala 1405:42]
- wire [15:0] _alu0_0_T_20 = _alu0_0_T_19 | log_4; // @[VAluInt.scala 1405:48]
- wire [15:0] _alu0_0_T_21 = _alu0_0_T_20 | max_4; // @[VAluInt.scala 1405:54]
- wire [15:0] _alu0_0_T_22 = _alu0_0_T_21 | min_4; // @[VAluInt.scala 1405:60]
- wire [15:0] _alu0_0_T_23 = _alu0_0_T_22 | padd; // @[VAluInt.scala 1405:66]
- wire [15:0] _alu0_0_T_24 = _alu0_0_T_23 | rsub_4; // @[VAluInt.scala 1405:73]
- wire [15:0] _alu0_0_T_25 = _alu0_0_T_24 | shift_4; // @[VAluInt.scala 1405:80]
- wire [15:0] _alu0_0_T_26 = _alu0_0_T_25 | srans_4; // @[VAluInt.scala 1405:88]
- wire [15:0] _alu0_0_T_28 = _alu0_0_T_26 | sub_4; // @[VAluInt.scala 1405:104]
- wire [15:0] _alu0_0_T_30 = io_op_mv ? ina_h[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] alu0_1_0 = _alu0_0_T_28 | _alu0_0_T_30; // @[VAluInt.scala 1405:110]
- wire [15:0] _alu1_0_T_7 = io_op_mvp ? inb_h[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _alu1_0_T_8 = mul1_4 | _alu1_0_T_7; // @[VAluInt.scala 1408:23]
- wire [15:0] _alu1_0_T_10 = io_op_mv2 ? inc_h[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] alu1_1_0 = _alu1_0_T_8 | _alu1_0_T_10; // @[VAluInt.scala 1409:44]
- wire [15:0] _GEN_156 = {{15'd0}, mulh0_rnd_4}; // @[VAluInt.scala 1412:29]
- wire [15:0] _rnd0_0_T_2 = dmulh0_rnd_4 | _GEN_156; // @[VAluInt.scala 1412:29]
- wire [15:0] _GEN_157 = {{15'd0}, shf_rnd_4}; // @[VAluInt.scala 1412:41]
- wire [15:0] rnd0_1_0 = _rnd0_0_T_2 | _GEN_157; // @[VAluInt.scala 1412:41]
- wire [15:0] _GEN_158 = {{15'd0}, mulh1_rnd_4}; // @[VAluInt.scala 1413:29]
- wire [15:0] rnd1_1_0 = dmulh1_rnd_4 | _GEN_158; // @[VAluInt.scala 1413:29]
- wire [31:0] _aluw0_0_T_3 = acc_4 | addw_4; // @[VAluInt.scala 1417:31]
- wire [31:0] _aluw0_0_T_4 = _aluw0_0_T_3 | mulw_4; // @[VAluInt.scala 1417:38]
- wire [31:0] aluw0_1_0 = _aluw0_0_T_4 | subw_4; // @[VAluInt.scala 1417:45]
- wire add_sa_5 = add_a_1[31] & io_in_signed; // @[VAluInt.scala 973:29]
- wire add_sb_5 = add_b_1[31] & io_in_signed; // @[VAluInt.scala 974:29]
- wire [16:0] _adder_T_47 = {add_sa_5,add_a_1[31:16]}; // @[VAluInt.scala 975:44]
- wire [16:0] _adder_T_50 = {add_sb_5,add_b_1[31:16]}; // @[VAluInt.scala 975:78]
- wire [17:0] _adder_T_52 = $signed(_adder_T_47) + $signed(_adder_T_50); // @[VAluInt.scala 975:86]
- wire [17:0] adder_5 = _adder_T_52 + _GEN_126; // @[VAluInt.scala 975:93]
- wire [1:0] sataddmsb_5 = adder_5[16:15]; // @[VAluInt.scala 976:28]
- wire _sataddsel_T_36 = io_in_signed & sataddmsb_5 == 2'h2; // @[VAluInt.scala 978:21]
- wire _sataddsel_T_38 = io_in_signed & sataddmsb_5 == 2'h1; // @[VAluInt.scala 979:21]
- wire _sataddsel_T_41 = ~io_in_signed & sataddmsb_5[1]; // @[VAluInt.scala 980:21]
- wire [2:0] sataddsel_5 = {_sataddsel_T_36,_sataddsel_T_38,_sataddsel_T_41}; // @[Cat.scala 31:58]
- wire [1:0] _T_483 = sataddsel_5[1] + sataddsel_5[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_160 = {{1'd0}, sataddsel_5[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_485 = _GEN_160 + _T_483; // @[Bitwise.scala 48:55]
- wire sub_sa_5 = sub_a_1[31] & io_in_signed; // @[VAluInt.scala 983:29]
- wire sub_sb_5 = sub_b_1[31] & io_in_signed; // @[VAluInt.scala 984:29]
- wire [16:0] _subtr_T_47 = {sub_sa_5,sub_a_1[31:16]}; // @[VAluInt.scala 985:44]
- wire [16:0] _subtr_T_50 = {sub_sb_5,sub_b_1[31:16]}; // @[VAluInt.scala 985:78]
- wire [17:0] _subtr_T_52 = $signed(_subtr_T_47) - $signed(_subtr_T_50); // @[VAluInt.scala 985:86]
- wire [17:0] subtr_5 = _subtr_T_52 + _GEN_128; // @[VAluInt.scala 985:93]
- wire [1:0] satsubmsb_5 = subtr_5[16:15]; // @[VAluInt.scala 986:28]
- wire _satsubsel_T_36 = io_in_signed & satsubmsb_5 == 2'h2; // @[VAluInt.scala 988:21]
- wire _satsubsel_T_38 = io_in_signed & satsubmsb_5 == 2'h1; // @[VAluInt.scala 989:21]
- wire _satsubsel_T_41 = _sataddsel_T_4 & satsubmsb_5[1]; // @[VAluInt.scala 990:21]
- wire [2:0] satsubsel_5 = {_satsubsel_T_36,_satsubsel_T_38,_satsubsel_T_41}; // @[Cat.scala 31:58]
- wire [1:0] _T_494 = satsubsel_5[1] + satsubsel_5[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_162 = {{1'd0}, satsubsel_5[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_496 = _GEN_162 + _T_494; // @[Bitwise.scala 48:55]
- wire [15:0] rsubtr_5 = rsub_b_1[31:16] - rsub_a_1[31:16]; // @[VAluInt.scala 993:32]
- wire xeq_5 = cmp_a_1[31:16] == cmp_b_1[31:16]; // @[VAluInt.scala 995:28]
- wire xne_5 = cmp_a_1[31:16] != cmp_b_1[31:16]; // @[VAluInt.scala 996:28]
- wire [15:0] _slt_T_21 = cmp_a_1[31:16]; // @[VAluInt.scala 997:34]
- wire [15:0] _slt_T_23 = cmp_b_1[31:16]; // @[VAluInt.scala 997:56]
- wire slt_5 = $signed(_slt_T_21) < $signed(_slt_T_23); // @[VAluInt.scala 997:37]
- wire ult_5 = cmp_a_1[31:16] < cmp_b_1[31:16]; // @[VAluInt.scala 998:28]
- wire sle_5 = slt_5 | xeq_5; // @[VAluInt.scala 999:21]
- wire ule_5 = ult_5 | xeq_5; // @[VAluInt.scala 1000:21]
- wire sult_5 = io_in_signed ? slt_5 : ult_5; // @[VAluInt.scala 1002:21]
- wire [30:0] _GEN_53 = {{15'd0}, shl_a_1[31:16]}; // @[VAluInt.scala 1062:29]
- wire [30:0] _shl_T_17 = _GEN_53 << shl_b_1[19:16]; // @[VAluInt.scala 1062:29]
- wire [15:0] shl_5 = _shl_T_17[15:0]; // @[VAluInt.scala 1062:49]
- wire [4:0] _GEN_163 = {{1'd0}, shl_b_1[19:16]}; // @[VAluInt.scala 1063:40]
- wire [4:0] _sln_T_28 = 5'h10 - _GEN_163; // @[VAluInt.scala 1063:40]
- wire [46:0] _GEN_54 = {{31'd0}, shl_a_1[31:16]}; // @[VAluInt.scala 1063:29]
- wire [46:0] _sln_T_29 = _GEN_54 << _sln_T_28; // @[VAluInt.scala 1063:29]
- wire [30:0] sln_5 = _sln_T_29[30:0]; // @[VAluInt.scala 1063:60]
- wire [15:0] srl_5 = shr_a_1[31:16] >> shr_b_1[19:16]; // @[VAluInt.scala 1064:28]
- wire [3:0] _srs_T_39 = 4'hf - shr_b_1[19:16]; // @[VAluInt.scala 1065:66]
- wire [30:0] _srs_T_40 = 31'hffff << _srs_T_39; // @[VAluInt.scala 1065:49]
- wire [15:0] srs_5 = shr_a_1[31] ? _srs_T_40[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] sra_5 = srs_5 | srl_5; // @[VAluInt.scala 1066:21]
- wire [15:0] shf_slnsz_5 = sln_5[15:0]; // @[VAluInt.scala 1010:24]
- wire shf_input_neg_5 = shl_a_1[31]; // @[VAluInt.scala 1011:26]
- wire shf_input_zero_5 = shl_a_1[31:16] == 16'h0; // @[VAluInt.scala 1012:28]
- wire shf_shamt_neg_5 = shl_b_1[31]; // @[VAluInt.scala 1013:26]
- wire [15:0] _shf_shamt_negsat_T_25 = shl_b_1[31:16]; // @[VAluInt.scala 1017:32]
- wire shf_shamt_negsat_10 = $signed(_shf_shamt_negsat_T_25) <= -16'shf; // @[VAluInt.scala 1017:39]
- wire shf_shamt_possat_10 = $signed(_shf_shamt_negsat_T_25) >= 16'shf; // @[VAluInt.scala 1018:39]
- wire [3:0] _shf_signb_T_23 = shl_b_1[19:16] - 4'h1; // @[VAluInt.scala 1019:65]
- wire [15:0] shf_signb_5 = 16'hffff >> _shf_signb_T_23; // @[VAluInt.scala 1019:36]
- wire _shf_possat_T_66 = ~shf_input_zero_5; // @[VAluInt.scala 1020:112]
- wire shf_possat_10 = shf_shamt_neg_5 & ~shf_input_neg_5 & (shf_shamt_negsat_10 | sln_5[30:15] != 16'h0) & ~
- shf_input_zero_5; // @[VAluInt.scala 1020:109]
- wire shf_negsat_5 = shf_shamt_neg_5 & shf_input_neg_5 & (shf_shamt_negsat_10 | sln_5[30:15] != shf_signb_5); // @[VAluInt.scala 1021:48]
- wire _shf_rs_T_110 = ~shf_shamt_neg_5; // @[VAluInt.scala 1028:23]
- wire _shf_rs_T_112 = ~shf_shamt_neg_5 & ~shf_shamt_possat_10; // @[VAluInt.scala 1028:34]
- wire [15:0] _shf_rs_T_113 = _shf_rs_T_112 ? sra_5 : 16'h0; // @[Library.scala 32:8]
- wire _shf_rs_T_116 = _shf_rs_T_110 & shf_shamt_possat_10 & shf_input_neg_5; // @[VAluInt.scala 1029:51]
- wire [15:0] _shf_rs_T_118 = _shf_rs_T_116 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _shf_rs_T_119 = _shf_rs_T_113 | _shf_rs_T_118; // @[VAluInt.scala 1028:57]
- wire _shf_rs_T_123 = shf_shamt_neg_5 & ~shf_possat_10 & ~shf_negsat_5; // @[VAluInt.scala 1030:45]
- wire [15:0] _shf_rs_T_124 = _shf_rs_T_123 ? shf_slnsz_5 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _shf_rs_T_125 = _shf_rs_T_119 | _shf_rs_T_124; // @[VAluInt.scala 1029:79]
- wire _shf_rs_T_126 = shf_shamt_neg_5 & shf_possat_10; // @[VAluInt.scala 1031:34]
- wire [15:0] _shf_rs_T_127 = _shf_rs_T_126 ? 16'h7fff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _shf_rs_T_128 = _shf_rs_T_125 | _shf_rs_T_127; // @[VAluInt.scala 1030:64]
- wire _shf_rs_T_129 = shf_shamt_neg_5 & shf_negsat_5; // @[VAluInt.scala 1032:34]
- wire [15:0] _shf_rs_T_130 = _shf_rs_T_129 ? 16'h8000 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] shf_rs_5 = _shf_rs_T_128 | _shf_rs_T_130; // @[VAluInt.scala 1031:53]
- wire shf_shamt_negsat_11 = $signed(_shf_shamt_negsat_T_25) <= $signed(_GEN_131); // @[VAluInt.scala 1035:39]
- wire shf_shamt_possat_11 = $signed(_shf_shamt_negsat_T_25) >= 16'sh10; // @[VAluInt.scala 1036:39]
- wire shf_possat_11 = shf_shamt_neg_5 & (shf_shamt_negsat_11 | sln_5[30:16] != 15'h0) & _shf_possat_T_66; // @[VAluInt.scala 1037:89]
- wire _shf_ru_T_57 = _shf_rs_T_110 & ~shf_shamt_possat_11; // @[VAluInt.scala 1041:34]
- wire [15:0] _shf_ru_T_58 = _shf_ru_T_57 ? srl_5 : 16'h0; // @[Library.scala 32:8]
- wire _shf_ru_T_60 = shf_shamt_neg_5 & ~shf_possat_11; // @[VAluInt.scala 1042:34]
- wire [15:0] _shf_ru_T_61 = _shf_ru_T_60 ? shf_slnsz_5 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _shf_ru_T_62 = _shf_ru_T_58 | _shf_ru_T_61; // @[VAluInt.scala 1041:57]
- wire _shf_ru_T_63 = shf_shamt_neg_5 & shf_possat_11; // @[VAluInt.scala 1043:34]
- wire [15:0] _shf_ru_T_64 = _shf_ru_T_63 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] shf_ru_5 = _shf_ru_T_62 | _shf_ru_T_64; // @[VAluInt.scala 1042:53]
- wire [15:0] shf_5 = io_in_signed ? shf_rs_5 : shf_ru_5; // @[VAluInt.scala 1045:12]
- wire [15:0] shr_5 = io_in_signed ? sra_5 : srl_5; // @[VAluInt.scala 1068:20]
- wire shf_rnd_shamt_zero_5 = shl_b_1[31:16] == 16'h0; // @[VAluInt.scala 1053:28]
- wire [15:0] _shf_rnd_rbit_T_27 = {shl_a_1[30:16],shf_input_neg_5}; // @[Cat.scala 31:58]
- wire [15:0] _shf_rnd_rbit_T_29 = _shf_rnd_rbit_T_27 >> shl_b_1[19:16]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_rbit_5 = _shf_rnd_rbit_T_29[0]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_shamt_possat_5 = io_in_signed ? shf_shamt_possat_11 : $signed(_shf_shamt_negsat_T_25) > 16'sh10; // @[VAluInt.scala 1055:31]
- wire _shf_rnd_r_T_60 = io_in_round & ~shf_rnd_shamt_possat_5 & _shf_rs_T_110 & ~shf_rnd_shamt_zero_5; // @[VAluInt.scala 1056:60]
- wire _shf_rnd_r_T_61 = _shf_rnd_r_T_60 & shf_rnd_rbit_5; // @[Library.scala 36:8]
- wire _shf_rnd_r_T_64 = io_in_round & shf_rnd_shamt_possat_5 & shf_input_neg_5 & io_in_signed; // @[VAluInt.scala 1057:59]
- wire shf_rnd_5 = _shf_rnd_r_T_61 | _shf_rnd_r_T_64; // @[VAluInt.scala 1056:82]
- wire _mul0_as_T_16 = io_in_signed & mul0_a_1[31]; // @[VAluInt.scala 1199:32]
- wire _mul0_bs_T_16 = io_in_signed & mul0_b_1[31]; // @[VAluInt.scala 1200:32]
- wire mul0_sign_5 = mul0_a_1[31] != mul0_b_1[31] & mul0_a_1[31:16] != 16'h0 & mul0_b_1[31:16] != 16'h0; // @[VAluInt.scala 1201:70]
- wire [16:0] _prod0_T_15 = {_mul0_as_T_16,mul0_a_1[31:16]}; // @[VAluInt.scala 1202:28]
- wire [16:0] _prod0_T_16 = {_mul0_bs_T_16,mul0_b_1[31:16]}; // @[VAluInt.scala 1202:45]
- wire [33:0] prod0_5 = $signed(_prod0_T_15) * $signed(_prod0_T_16); // @[VAluInt.scala 1202:53]
- wire [15:0] prodh0_5 = prod0_5[31:16]; // @[VAluInt.scala 1203:25]
- wire [15:0] proddh0_5 = prod0_5[30:15]; // @[VAluInt.scala 1204:26]
- wire _mul1_as_T_16 = io_in_signed & mul1_a_1[31]; // @[VAluInt.scala 1206:32]
- wire _mul1_bs_T_16 = io_in_signed & mul1_b_1[31]; // @[VAluInt.scala 1207:32]
- wire mul1_sign_5 = mul1_a_1[31] != mul1_b_1[31] & mul1_a_1[31:16] != 16'h0 & mul1_b_1[31:16] != 16'h0; // @[VAluInt.scala 1208:70]
- wire [16:0] _prod1_T_15 = {_mul1_as_T_16,mul1_a_1[31:16]}; // @[VAluInt.scala 1209:28]
- wire [16:0] _prod1_T_16 = {_mul1_bs_T_16,mul1_b_1[31:16]}; // @[VAluInt.scala 1209:45]
- wire [33:0] prod1_5 = $signed(_prod1_T_15) * $signed(_prod1_T_16); // @[VAluInt.scala 1209:53]
- wire [15:0] prodh1_5 = prod1_5[31:16]; // @[VAluInt.scala 1210:25]
- wire [15:0] proddh1_5 = prod1_5[30:15]; // @[VAluInt.scala 1211:26]
- wire _muls0_umax_T_11 = prodh0_5 != 16'h0; // @[VAluInt.scala 1213:42]
- wire muls0_umax_5 = _sataddsel_T_4 & prodh0_5 != 16'h0; // @[VAluInt.scala 1213:32]
- wire muls0_smax_5 = io_in_signed & ~mul0_sign_5 & (prod0_5[15] | _muls0_umax_T_11); // @[VAluInt.scala 1214:46]
- wire muls0_smin_5 = io_in_signed & mul0_sign_5 & (~prod0_5[15] | prodh0_5 != 16'hffff); // @[VAluInt.scala 1215:46]
- wire muls0_base_5 = ~(muls0_umax_5 | muls0_smax_5 | muls0_smin_5); // @[VAluInt.scala 1216:24]
- wire [3:0] _T_502 = {muls0_umax_5,muls0_smax_5,muls0_smin_5,muls0_base_5}; // @[Cat.scala 31:58]
- wire [1:0] _T_507 = _T_502[0] + _T_502[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_509 = _T_502[2] + _T_502[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_511 = _T_507 + _T_509; // @[Bitwise.scala 48:55]
- wire _muls1_umax_T_11 = prodh1_5 != 16'h0; // @[VAluInt.scala 1219:42]
- wire muls1_umax_5 = _sataddsel_T_4 & prodh1_5 != 16'h0; // @[VAluInt.scala 1219:32]
- wire muls1_smax_5 = io_in_signed & ~mul1_sign_5 & (prod1_5[15] | _muls1_umax_T_11); // @[VAluInt.scala 1220:46]
- wire muls1_smin_5 = io_in_signed & mul1_sign_5 & (~prod1_5[15] | prodh1_5 != 16'hffff); // @[VAluInt.scala 1221:46]
- wire muls1_base_5 = ~(muls1_umax_5 | muls1_smax_5 | muls1_smin_5); // @[VAluInt.scala 1222:24]
- wire [3:0] _T_517 = {muls1_umax_5,muls1_smax_5,muls1_smin_5,muls1_base_5}; // @[Cat.scala 31:58]
- wire [1:0] _T_522 = _T_517[0] + _T_517[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_524 = _T_517[2] + _T_517[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_526 = _T_522 + _T_524; // @[Bitwise.scala 48:55]
- wire dmulh0_possat_5 = mul0_a_1[31:16] == 16'h8000 & mul0_b_1[31:16] == 16'h8000; // @[VAluInt.scala 1227:50]
- wire dmulh1_possat_5 = mul1_a_1[31:16] == 16'h8000 & mul1_b_1[31:16] == 16'h8000; // @[VAluInt.scala 1229:50]
- wire _dmulh0_T_25 = ~dmulh0_possat_5; // @[VAluInt.scala 1231:26]
- wire [15:0] _dmulh0_T_26 = _dmulh0_T_25 ? proddh0_5 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _dmulh0_T_29 = dmulh0_possat_5 ? 16'h7fff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] dmulh0_5 = _dmulh0_T_26 | _dmulh0_T_29; // @[VAluInt.scala 1231:51]
- wire _dmulh1_T_25 = ~dmulh1_possat_5; // @[VAluInt.scala 1234:26]
- wire [15:0] _dmulh1_T_26 = _dmulh1_T_25 ? proddh1_5 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _dmulh1_T_29 = dmulh1_possat_5 ? 16'h7fff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] dmulh1_5 = _dmulh1_T_26 | _dmulh1_T_29; // @[VAluInt.scala 1234:51]
- wire [15:0] _muls0_T_51 = muls0_umax_5 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [14:0] _muls0_T_53 = muls0_smax_5 ? 15'h7fff : 15'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_165 = {{1'd0}, _muls0_T_53}; // @[VAluInt.scala 1240:51]
- wire [15:0] _muls0_T_54 = _muls0_T_51 | _GEN_165; // @[VAluInt.scala 1240:51]
- wire [15:0] _muls0_T_56 = muls0_smin_5 ? 16'h8000 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _muls0_T_57 = _muls0_T_54 | _muls0_T_56; // @[VAluInt.scala 1241:57]
- wire [15:0] _muls0_T_59 = muls0_base_5 ? prod0_5[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] muls0_5 = _muls0_T_57 | _muls0_T_59; // @[VAluInt.scala 1242:71]
- wire [15:0] _muls1_T_51 = muls1_umax_5 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [14:0] _muls1_T_53 = muls1_smax_5 ? 15'h7fff : 15'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_166 = {{1'd0}, _muls1_T_53}; // @[VAluInt.scala 1245:51]
- wire [15:0] _muls1_T_54 = _muls1_T_51 | _GEN_166; // @[VAluInt.scala 1245:51]
- wire [15:0] _muls1_T_56 = muls1_smin_5 ? 16'h8000 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _muls1_T_57 = _muls1_T_54 | _muls1_T_56; // @[VAluInt.scala 1246:57]
- wire [15:0] _muls1_T_59 = muls1_base_5 ? prod1_5[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] muls1_5 = _muls1_T_57 | _muls1_T_59; // @[VAluInt.scala 1247:71]
- wire _dmulh0_rnd_T_69 = io_in_round & io_op_mul0_dmulh & io_in_sz[1] & _dmulh0_T_25; // @[VAluInt.scala 1250:72]
- wire _dmulh0_rnd_T_72 = ~prod0_5[14]; // @[VAluInt.scala 1252:40]
- wire [15:0] _dmulh0_rnd_T_74 = _dmulh0_rnd_T_72 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _dmulh0_rnd_T_76 = prod0_5[14] ? 16'h1 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _dmulh0_rnd_T_77 = io_in_negative & mul0_sign_5 ? _dmulh0_rnd_T_74 : _dmulh0_rnd_T_76; // @[VAluInt.scala 1251:33]
- wire [15:0] dmulh0_rnd_5 = _dmulh0_rnd_T_69 ? _dmulh0_rnd_T_77 : 16'h0; // @[Library.scala 32:8]
- wire _dmulh1_rnd_T_69 = io_in_round & io_op_mul1_dmulh & io_in_sz[1] & _dmulh1_T_25; // @[VAluInt.scala 1255:72]
- wire _dmulh1_rnd_T_72 = ~prod1_5[14]; // @[VAluInt.scala 1257:40]
- wire [15:0] _dmulh1_rnd_T_74 = _dmulh1_rnd_T_72 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _dmulh1_rnd_T_76 = prod1_5[14] ? 16'h1 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _dmulh1_rnd_T_77 = io_in_negative & mul1_sign_5 ? _dmulh1_rnd_T_74 : _dmulh1_rnd_T_76; // @[VAluInt.scala 1256:33]
- wire [15:0] dmulh1_rnd_5 = _dmulh1_rnd_T_69 ? _dmulh1_rnd_T_77 : 16'h0; // @[Library.scala 32:8]
- wire mulh0_rnd_5 = io_in_round & io_op_mul0_mulh & prod0_5[15]; // @[VAluInt.scala 1260:48]
- wire mulh1_rnd_5 = io_in_round & io_op_mul1_mulh & prod1_5[15]; // @[VAluInt.scala 1261:48]
- wire [15:0] _absd_T_11 = sult_5 ? rsubtr_5 : subtr_5[15:0]; // @[VAluInt.scala 1265:39]
- wire [15:0] absd_5 = io_op_absd ? _absd_T_11 : 16'h0; // @[Library.scala 32:8]
- wire _acc_T_32 = io_in_signed & acc_b_1[31]; // @[VAluInt.scala 1272:55]
- wire [16:0] _acc_T_34 = {_acc_T_32,acc_b_1[31:16]}; // @[Cat.scala 31:58]
- wire acc_r_r_5_2 = _acc_T_34[16]; // @[Library.scala 64:25]
- wire [6:0] acc_r_lo_5 = {acc_r_r_5_2,acc_r_r_5_2,acc_r_r_5_2,acc_r_r_5_2,acc_r_r_5_2,acc_r_r_5_2,acc_r_r_5_2}; // @[Library.scala 57:7]
- wire [31:0] acc_r_5 = {acc_r_r_5_2,acc_r_r_5_2,acc_r_r_5_2,acc_r_r_5_2,acc_r_r_5_2,acc_r_r_5_2,acc_r_r_5_2,acc_r_r_5_2
- ,acc_r_lo_5,_acc_T_34}; // @[Cat.scala 31:58]
- wire [31:0] acc_5 = acc_c_1 + acc_r_5; // @[VAluInt.scala 1272:34]
- wire _add_T_116 = sataddsel_5[2] & io_op_add_adds; // @[VAluInt.scala 1279:36]
- wire [15:0] _add_T_118 = _add_T_116 ? 16'h8000 : 16'h0; // @[Library.scala 32:8]
- wire _add_T_120 = sataddsel_5[1] & io_op_add_adds; // @[VAluInt.scala 1280:36]
- wire [14:0] _add_T_122 = _add_T_120 ? 15'h7fff : 15'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_167 = {{1'd0}, _add_T_122}; // @[VAluInt.scala 1279:89]
- wire [15:0] _add_T_123 = _add_T_118 | _GEN_167; // @[VAluInt.scala 1279:89]
- wire _add_T_125 = sataddsel_5[0] & io_op_add_adds; // @[VAluInt.scala 1281:36]
- wire [15:0] _add_T_127 = _add_T_125 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _add_T_128 = _add_T_123 | _add_T_127; // @[VAluInt.scala 1280:75]
- wire _add_T_132 = sataddsel_5 == 3'h0 & io_op_add_adds | io_op_add_add | io_op_add_add3; // @[VAluInt.scala 1282:76]
- wire [15:0] _add_T_134 = _add_T_132 ? adder_5[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _add_T_135 = _add_T_128 | _add_T_134; // @[VAluInt.scala 1281:69]
- wire [15:0] _add_T_137 = io_op_add_hadd ? adder_5[16:1] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] add_5 = _add_T_135 | _add_T_137; // @[VAluInt.scala 1282:115]
- wire addw_r_r_5_2 = adder_5[17]; // @[Library.scala 64:25]
- wire [6:0] addw_r_lo_5 = {addw_r_r_5_2,addw_r_r_5_2,addw_r_r_5_2,addw_r_r_5_2,addw_r_r_5_2,addw_r_r_5_2,addw_r_r_5_2}; // @[Library.scala 57:7]
- wire [31:0] addw_r_5 = {addw_r_r_5_2,addw_r_r_5_2,addw_r_r_5_2,addw_r_r_5_2,addw_r_r_5_2,addw_r_r_5_2,addw_r_r_5_2,
- addw_r_lo_5,adder_5}; // @[Cat.scala 31:58]
- wire [31:0] addw_5 = io_op_add_addw ? addw_r_5 : 32'h0; // @[Library.scala 32:8]
- wire [15:0] dup_5 = io_op_dup ? io_read_1_data[31:16] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _max_T_17 = sult_5 ? cmp_b_1[31:16] : cmp_a_1[31:16]; // @[VAluInt.scala 1290:37]
- wire [15:0] max_5 = io_op_max ? _max_T_17 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _min_T_17 = sult_5 ? cmp_a_1[31:16] : cmp_b_1[31:16]; // @[VAluInt.scala 1291:37]
- wire [15:0] min_5 = io_op_min ? _min_T_17 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul0_T_42 = _mul0_T ? prod0_5[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul0_T_43 = io_op_mul0_dmulh ? dmulh0_5 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul0_T_44 = _mul0_T_42 | _mul0_T_43; // @[VAluInt.scala 1293:79]
- wire [15:0] _mul0_T_45 = io_op_mul0_mulh ? prodh0_5 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul0_T_46 = _mul0_T_44 | _mul0_T_45; // @[VAluInt.scala 1294:50]
- wire [15:0] _mul0_T_47 = io_op_mul0_muls ? muls0_5 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] mul0_5 = _mul0_T_46 | _mul0_T_47; // @[VAluInt.scala 1295:48]
- wire [15:0] _mul1_T_36 = io_op_mul1_mul ? prod1_5[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul1_T_37 = io_op_mul1_dmulh ? dmulh1_5 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul1_T_38 = _mul1_T_36 | _mul1_T_37; // @[VAluInt.scala 1298:60]
- wire [15:0] _mul1_T_39 = io_op_mul1_mulh ? prodh1_5 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _mul1_T_40 = _mul1_T_38 | _mul1_T_39; // @[VAluInt.scala 1299:50]
- wire [15:0] _mul1_T_41 = io_op_mul1_muls ? muls1_5 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] mul1_5 = _mul1_T_40 | _mul1_T_41; // @[VAluInt.scala 1300:48]
- wire [31:0] mulw_5 = io_op_mul0_mulw ? prod0_5[31:0] : 32'h0; // @[Library.scala 32:8]
- wire _padd_a_T_4 = io_in_signed & padd_a_1[23]; // @[VAluInt.scala 1311:30]
- wire _padd_b_T_4 = io_in_signed & padd_a_1[31]; // @[VAluInt.scala 1312:30]
- wire [8:0] _padd_add_T_4 = {_padd_a_T_4,padd_a_1[23:16]}; // @[VAluInt.scala 1313:54]
- wire [8:0] _padd_add_T_5 = {_padd_b_T_4,padd_a_1[31:24]}; // @[VAluInt.scala 1313:66]
- wire [9:0] _padd_add_T_7 = $signed(_padd_add_T_4) + $signed(_padd_add_T_5); // @[VAluInt.scala 1313:74]
- wire padd_add_r_r_1_2 = _padd_add_T_7[9]; // @[Library.scala 64:25]
- wire [15:0] padd_add_r_1 = {padd_add_r_r_1_2,padd_add_r_r_1_2,padd_add_r_r_1_2,padd_add_r_r_1_2,padd_add_r_r_1_2,
- padd_add_r_r_1_2,_padd_add_T_7}; // @[Cat.scala 31:58]
- wire [15:0] padd_add_1 = io_op_padd_add ? padd_add_r_1 : 16'h0; // @[Library.scala 32:8]
- wire [9:0] _padd_sub_T_7 = $signed(_padd_add_T_4) - $signed(_padd_add_T_5); // @[VAluInt.scala 1314:74]
- wire padd_sub_r_r_1_2 = _padd_sub_T_7[9]; // @[Library.scala 64:25]
- wire [15:0] padd_sub_r_1 = {padd_sub_r_r_1_2,padd_sub_r_r_1_2,padd_sub_r_r_1_2,padd_sub_r_r_1_2,padd_sub_r_r_1_2,
- padd_sub_r_r_1_2,_padd_sub_T_7}; // @[Cat.scala 31:58]
- wire [15:0] padd_sub_1 = io_op_padd_sub ? padd_sub_r_1 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] padd_1 = padd_add_1 | padd_sub_1; // @[VAluInt.scala 1317:15]
- wire [15:0] rsub_5 = io_op_rsub_rsub ? rsubtr_5 : 16'h0; // @[Library.scala 32:8]
- wire [4:0] srans_shamt_5 = srans_b_1[20:16]; // @[VAluInt.scala 1084:22]
- wire [31:0] srans_srl_5 = srans_c_1 >> srans_shamt_5; // @[VAluInt.scala 1085:21]
- wire _srans_srs_T_36 = srans_c_1[31] & io_in_signed; // @[VAluInt.scala 1088:41]
- wire [4:0] _srans_srs_T_39 = 5'h1f - srans_shamt_5; // @[VAluInt.scala 1089:68]
- wire [62:0] _srans_srs_T_40 = 63'hffffffff << _srans_srs_T_39; // @[VAluInt.scala 1089:47]
- wire [31:0] srans_srs_5 = _srans_srs_T_36 ? _srans_srs_T_40[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] srans_sra_5 = srans_srs_5 | srans_srl_5; // @[VAluInt.scala 1090:23]
- wire [31:0] _srans_rbit_T_16 = {srans_c_1[30:0],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] _srans_rbit_T_17 = _srans_rbit_T_16 >> srans_shamt_5; // @[VAluInt.scala 1093:53]
- wire srans_rbit_5 = _srans_rbit_T_17[0]; // @[VAluInt.scala 1093:53]
- wire [31:0] _srans_rshf_T_17 = srans_sra_5 + 32'h1; // @[VAluInt.scala 1099:43]
- wire [31:0] srans_rshf_5 = io_in_round & srans_rbit_5 ? _srans_rshf_T_17 : srans_sra_5; // @[VAluInt.scala 1099:23]
- wire srans_is_umax_5 = _sataddsel_T_4 & srans_rshf_5 > 32'hffff; // @[VAluInt.scala 1101:31]
- wire [31:0] _srans_is_smax_T_10 = io_in_round & srans_rbit_5 ? _srans_rshf_T_17 : srans_sra_5; // @[VAluInt.scala 1103:40]
- wire srans_is_smax_5 = io_in_signed & $signed(_srans_is_smax_T_10) > 32'sh7fff; // @[VAluInt.scala 1103:31]
- wire srans_is_smin_5 = io_in_signed & $signed(_srans_is_smax_T_10) < $signed(srans_smin_4); // @[VAluInt.scala 1104:31]
- wire srans_is_norm_5 = ~(srans_is_umax_5 | srans_is_smax_5 | srans_is_smin_5); // @[VAluInt.scala 1105:23]
- wire [3:0] _srans_T_87 = {srans_is_umax_5,srans_is_smax_5,srans_is_smin_5,srans_is_norm_5}; // @[Cat.scala 31:58]
- wire [1:0] _srans_T_92 = _srans_T_87[0] + _srans_T_87[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _srans_T_94 = _srans_T_87[2] + _srans_T_87[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _srans_T_96 = _srans_T_92 + _srans_T_94; // @[Bitwise.scala 48:55]
- wire [15:0] _srans_r_T_55 = srans_is_umax_5 ? 16'hffff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _srans_r_T_58 = srans_is_smax_5 ? 16'h7fff : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _srans_r_T_59 = _srans_r_T_55 | _srans_r_T_58; // @[VAluInt.scala 1108:58]
- wire [15:0] _srans_r_T_62 = srans_is_smin_5 ? _srans_r_T_49[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _srans_r_T_63 = _srans_r_T_59 | _srans_r_T_62; // @[VAluInt.scala 1109:58]
- wire [15:0] _srans_r_T_65 = srans_is_norm_5 ? srans_rshf_5[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] srans_5 = _srans_r_T_63 | _srans_r_T_65; // @[VAluInt.scala 1110:58]
- wire _sub_T_106 = satsubsel_5[2] & io_op_sub_subs; // @[VAluInt.scala 1348:36]
- wire [15:0] _sub_T_108 = _sub_T_106 ? 16'h8000 : 16'h0; // @[Library.scala 32:8]
- wire _sub_T_110 = satsubsel_5[1] & io_op_sub_subs; // @[VAluInt.scala 1349:36]
- wire [14:0] _sub_T_112 = _sub_T_110 ? 15'h7fff : 15'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_168 = {{1'd0}, _sub_T_112}; // @[VAluInt.scala 1348:89]
- wire [15:0] _sub_T_113 = _sub_T_108 | _GEN_168; // @[VAluInt.scala 1348:89]
- wire _sub_T_120 = satsubsel_5 == 3'h0 & io_op_sub_subs | io_op_sub_sub; // @[VAluInt.scala 1351:59]
- wire [15:0] _sub_T_122 = _sub_T_120 ? subtr_5[15:0] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _sub_T_123 = _sub_T_113 | _sub_T_122; // @[VAluInt.scala 1350:68]
- wire [15:0] _sub_T_125 = io_op_sub_hsub ? subtr_5[16:1] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] sub_5 = _sub_T_123 | _sub_T_125; // @[VAluInt.scala 1351:97]
- wire subw_r_r_5_2 = subtr_5[17]; // @[Library.scala 64:25]
- wire [6:0] subw_r_lo_5 = {subw_r_r_5_2,subw_r_r_5_2,subw_r_r_5_2,subw_r_r_5_2,subw_r_r_5_2,subw_r_r_5_2,subw_r_r_5_2}; // @[Library.scala 57:7]
- wire [31:0] subw_r_5 = {subw_r_r_5_2,subw_r_r_5_2,subw_r_r_5_2,subw_r_r_5_2,subw_r_r_5_2,subw_r_r_5_2,subw_r_r_5_2,
- subw_r_lo_5,subtr_5}; // @[Cat.scala 31:58]
- wire [31:0] subw_5 = io_op_sub_subw ? subw_r_5 : 32'h0; // @[Library.scala 32:8]
- wire _cmp_T_181 = io_op_cmp_eq & xeq_5; // @[Library.scala 36:8]
- wire _cmp_T_182 = io_op_cmp_ne & xne_5; // @[Library.scala 36:8]
- wire _cmp_T_183 = _cmp_T_181 | _cmp_T_182; // @[VAluInt.scala 1358:45]
- wire _cmp_T_185 = _cmp_T_4 & slt_5; // @[Library.scala 36:8]
- wire _cmp_T_186 = _cmp_T_183 | _cmp_T_185; // @[VAluInt.scala 1359:45]
- wire _cmp_T_189 = _cmp_T_8 & ult_5; // @[Library.scala 36:8]
- wire _cmp_T_190 = _cmp_T_186 | _cmp_T_189; // @[VAluInt.scala 1360:56]
- wire _cmp_T_192 = _cmp_T_11 & sle_5; // @[Library.scala 36:8]
- wire _cmp_T_193 = _cmp_T_190 | _cmp_T_192; // @[VAluInt.scala 1361:56]
- wire _cmp_T_196 = _cmp_T_15 & ule_5; // @[Library.scala 36:8]
- wire _cmp_T_197 = _cmp_T_193 | _cmp_T_196; // @[VAluInt.scala 1362:56]
- wire _cmp_T_199 = ~sle_5; // @[VAluInt.scala 1364:51]
- wire _cmp_T_200 = _cmp_T_18 & _cmp_T_199; // @[Library.scala 36:8]
- wire _cmp_T_201 = _cmp_T_197 | _cmp_T_200; // @[VAluInt.scala 1363:56]
- wire _cmp_T_204 = ~ule_5; // @[VAluInt.scala 1365:51]
- wire _cmp_T_205 = _cmp_T_23 & _cmp_T_204; // @[Library.scala 36:8]
- wire _cmp_T_206 = _cmp_T_201 | _cmp_T_205; // @[VAluInt.scala 1364:57]
- wire _cmp_T_208 = ~slt_5; // @[VAluInt.scala 1366:51]
- wire _cmp_T_209 = _cmp_T_27 & _cmp_T_208; // @[Library.scala 36:8]
- wire _cmp_T_210 = _cmp_T_206 | _cmp_T_209; // @[VAluInt.scala 1365:57]
- wire _cmp_T_213 = ~ult_5; // @[VAluInt.scala 1367:51]
- wire _cmp_T_214 = _cmp_T_32 & _cmp_T_213; // @[Library.scala 36:8]
- wire _cmp_T_215 = _cmp_T_210 | _cmp_T_214; // @[VAluInt.scala 1366:57]
- wire cmp_5 = io_in_sz[1] & _cmp_T_215; // @[VAluInt.scala 1357:30]
- wire [15:0] _log_T_617 = log_a_1[31:16] & log_b_9[31:16]; // @[VAluInt.scala 1371:42]
- wire [15:0] _log_T_618 = io_op_log_and ? _log_T_617 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_621 = log_a_1[31:16] | log_b_9[31:16]; // @[VAluInt.scala 1372:42]
- wire [15:0] _log_T_622 = io_op_log_or ? _log_T_621 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_623 = _log_T_618 | _log_T_622; // @[VAluInt.scala 1371:56]
- wire [15:0] _log_T_626 = log_a_1[31:16] ^ log_b_9[31:16]; // @[VAluInt.scala 1373:42]
- wire [15:0] _log_T_627 = io_op_log_xor ? _log_T_626 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_628 = _log_T_623 | _log_T_627; // @[VAluInt.scala 1372:56]
- wire [15:0] _log_T_631 = ~log_a_1[31:16]; // @[VAluInt.scala 1374:51]
- wire [15:0] _log_T_632 = io_in_sz[1] ? _log_T_631 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_633 = io_op_log_not ? _log_T_632 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_634 = _log_T_628 | _log_T_633; // @[VAluInt.scala 1373:56]
- wire _log_b_T_89 = ~log_b_9[16]; // @[VAluInt.scala 1138:23]
- wire [7:0] log_b_lo_5 = {log_a_1[22],log_a_1[23],log_a_1[20],log_a_1[21],log_a_1[18],log_a_1[19],log_a_1[16],log_a_1[
- 17]}; // @[Cat.scala 31:58]
- wire [15:0] _log_b_T_106 = {log_a_1[30],log_a_1[31],log_a_1[28],log_a_1[29],log_a_1[26],log_a_1[27],log_a_1[24],
- log_a_1[25],log_b_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] log_b_12 = ~log_b_9[16] ? log_a_1[31:16] : _log_b_T_106; // @[VAluInt.scala 1138:22]
- wire _log_c_T_65 = ~log_b_9[17]; // @[VAluInt.scala 1140:23]
- wire [15:0] _log_c_T_74 = {log_b_12[13:12],log_b_12[15:14],log_b_12[9:8],log_b_12[11:10],log_b_12[5:4],log_b_12[7:6],
- log_b_12[1:0],log_b_12[3:2]}; // @[Cat.scala 31:58]
- wire [15:0] log_c_10 = ~log_b_9[17] ? log_b_12 : _log_c_T_74; // @[VAluInt.scala 1140:22]
- wire _log_d_T_53 = ~log_b_9[18]; // @[VAluInt.scala 1142:23]
- wire [15:0] _log_d_T_58 = {log_c_10[11:8],log_c_10[15:12],log_c_10[3:0],log_c_10[7:4]}; // @[Cat.scala 31:58]
- wire [15:0] log_d_10 = ~log_b_9[18] ? log_c_10 : _log_d_T_58; // @[VAluInt.scala 1142:22]
- wire _log_e_T_11 = ~log_b_9[19]; // @[VAluInt.scala 1143:23]
- wire [15:0] _log_e_T_14 = {log_d_10[7:0],log_d_10[15:8]}; // @[Cat.scala 31:58]
- wire [15:0] log_e_2 = ~log_b_9[19] ? log_d_10 : _log_e_T_14; // @[VAluInt.scala 1143:22]
- wire [15:0] _log_T_637 = io_op_log_rev ? log_e_2 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_638 = _log_T_634 | _log_T_637; // @[VAluInt.scala 1374:65]
- wire [15:0] _log_b_T_111 = {log_a_1[16],log_a_1[31:17]}; // @[Cat.scala 31:58]
- wire [15:0] log_b_13 = _log_b_T_89 ? log_a_1[31:16] : _log_b_T_111; // @[VAluInt.scala 1177:22]
- wire [15:0] _log_c_T_79 = {log_b_13[1:0],log_b_13[15:2]}; // @[Cat.scala 31:58]
- wire [15:0] log_c_11 = _log_c_T_65 ? log_b_13 : _log_c_T_79; // @[VAluInt.scala 1178:22]
- wire [15:0] _log_d_T_63 = {log_c_11[3:0],log_c_11[15:4]}; // @[Cat.scala 31:58]
- wire [15:0] log_d_11 = _log_d_T_53 ? log_c_11 : _log_d_T_63; // @[VAluInt.scala 1179:22]
- wire [15:0] _log_e_T_19 = {log_d_11[7:0],log_d_11[15:8]}; // @[Cat.scala 31:58]
- wire [15:0] log_e_3 = _log_e_T_11 ? log_d_11 : _log_e_T_19; // @[VAluInt.scala 1180:22]
- wire [15:0] _log_T_642 = io_in_sz[1] ? log_e_3 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_643 = io_op_log_ror ? _log_T_642 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _log_T_644 = _log_T_638 | _log_T_643; // @[VAluInt.scala 1375:60]
- wire [15:0] _GEN_169 = {{8'd0}, _log_T_631[15:8]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_265 = _GEN_169 & 16'hff; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_267 = {_log_T_631[7:0], 8'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clo_T_269 = _log_clo_T_267 & 16'hff00; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clo_T_270 = _log_clo_T_265 | _log_clo_T_269; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_170 = {{4'd0}, _log_clo_T_270[15:4]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_275 = _GEN_170 & 16'hf0f; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_277 = {_log_clo_T_270[11:0], 4'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clo_T_279 = _log_clo_T_277 & 16'hf0f0; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clo_T_280 = _log_clo_T_275 | _log_clo_T_279; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_171 = {{2'd0}, _log_clo_T_280[15:2]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_285 = _GEN_171 & 16'h3333; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_287 = {_log_clo_T_280[13:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clo_T_289 = _log_clo_T_287 & 16'hcccc; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clo_T_290 = _log_clo_T_285 | _log_clo_T_289; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_172 = {{1'd0}, _log_clo_T_290[15:1]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_295 = _GEN_172 & 16'h5555; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clo_T_297 = {_log_clo_T_290[14:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clo_T_299 = _log_clo_T_297 & 16'haaaa; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clo_T_300 = _log_clo_T_295 | _log_clo_T_299; // @[Bitwise.scala 105:39]
- wire [16:0] _log_clo_T_301 = {1'h1,_log_clo_T_300}; // @[Cat.scala 31:58]
- wire [4:0] _log_clo_T_319 = _log_clo_T_301[15] ? 5'hf : 5'h10; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_320 = _log_clo_T_301[14] ? 5'he : _log_clo_T_319; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_321 = _log_clo_T_301[13] ? 5'hd : _log_clo_T_320; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_322 = _log_clo_T_301[12] ? 5'hc : _log_clo_T_321; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_323 = _log_clo_T_301[11] ? 5'hb : _log_clo_T_322; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_324 = _log_clo_T_301[10] ? 5'ha : _log_clo_T_323; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_325 = _log_clo_T_301[9] ? 5'h9 : _log_clo_T_324; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_326 = _log_clo_T_301[8] ? 5'h8 : _log_clo_T_325; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_327 = _log_clo_T_301[7] ? 5'h7 : _log_clo_T_326; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_328 = _log_clo_T_301[6] ? 5'h6 : _log_clo_T_327; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_329 = _log_clo_T_301[5] ? 5'h5 : _log_clo_T_328; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_330 = _log_clo_T_301[4] ? 5'h4 : _log_clo_T_329; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_331 = _log_clo_T_301[3] ? 5'h3 : _log_clo_T_330; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_332 = _log_clo_T_301[2] ? 5'h2 : _log_clo_T_331; // @[Mux.scala 47:70]
- wire [4:0] _log_clo_T_333 = _log_clo_T_301[1] ? 5'h1 : _log_clo_T_332; // @[Mux.scala 47:70]
- wire [4:0] log_clo_5 = _log_clo_T_301[0] ? 5'h0 : _log_clo_T_333; // @[Mux.scala 47:70]
- wire [15:0] _GEN_173 = {{8'd0}, log_a_1[31:24]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_259 = _GEN_173 & 16'hff; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_261 = {log_a_1[23:16], 8'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clz_T_263 = _log_clz_T_261 & 16'hff00; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clz_T_264 = _log_clz_T_259 | _log_clz_T_263; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_174 = {{4'd0}, _log_clz_T_264[15:4]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_269 = _GEN_174 & 16'hf0f; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_271 = {_log_clz_T_264[11:0], 4'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clz_T_273 = _log_clz_T_271 & 16'hf0f0; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clz_T_274 = _log_clz_T_269 | _log_clz_T_273; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_175 = {{2'd0}, _log_clz_T_274[15:2]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_279 = _GEN_175 & 16'h3333; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_281 = {_log_clz_T_274[13:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clz_T_283 = _log_clz_T_281 & 16'hcccc; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clz_T_284 = _log_clz_T_279 | _log_clz_T_283; // @[Bitwise.scala 105:39]
- wire [15:0] _GEN_176 = {{1'd0}, _log_clz_T_284[15:1]}; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_289 = _GEN_176 & 16'h5555; // @[Bitwise.scala 105:31]
- wire [15:0] _log_clz_T_291 = {_log_clz_T_284[14:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [15:0] _log_clz_T_293 = _log_clz_T_291 & 16'haaaa; // @[Bitwise.scala 105:80]
- wire [15:0] _log_clz_T_294 = _log_clz_T_289 | _log_clz_T_293; // @[Bitwise.scala 105:39]
- wire [16:0] _log_clz_T_295 = {1'h1,_log_clz_T_294}; // @[Cat.scala 31:58]
- wire [4:0] _log_clz_T_313 = _log_clz_T_295[15] ? 5'hf : 5'h10; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_314 = _log_clz_T_295[14] ? 5'he : _log_clz_T_313; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_315 = _log_clz_T_295[13] ? 5'hd : _log_clz_T_314; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_316 = _log_clz_T_295[12] ? 5'hc : _log_clz_T_315; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_317 = _log_clz_T_295[11] ? 5'hb : _log_clz_T_316; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_318 = _log_clz_T_295[10] ? 5'ha : _log_clz_T_317; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_319 = _log_clz_T_295[9] ? 5'h9 : _log_clz_T_318; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_320 = _log_clz_T_295[8] ? 5'h8 : _log_clz_T_319; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_321 = _log_clz_T_295[7] ? 5'h7 : _log_clz_T_320; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_322 = _log_clz_T_295[6] ? 5'h6 : _log_clz_T_321; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_323 = _log_clz_T_295[5] ? 5'h5 : _log_clz_T_322; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_324 = _log_clz_T_295[4] ? 5'h4 : _log_clz_T_323; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_325 = _log_clz_T_295[3] ? 5'h3 : _log_clz_T_324; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_326 = _log_clz_T_295[2] ? 5'h2 : _log_clz_T_325; // @[Mux.scala 47:70]
- wire [4:0] _log_clz_T_327 = _log_clz_T_295[1] ? 5'h1 : _log_clz_T_326; // @[Mux.scala 47:70]
- wire [4:0] log_clz_5 = _log_clz_T_295[0] ? 5'h0 : _log_clz_T_327; // @[Mux.scala 47:70]
- wire [4:0] _log_T_648 = log_a_1[31] ? log_clo_5 : log_clz_5; // @[Library.scala 289:8]
- wire [4:0] _log_T_649 = io_in_sz[1] ? _log_T_648 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _log_T_650 = io_op_log_clb ? _log_T_649 : 5'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_177 = {{11'd0}, _log_T_650}; // @[VAluInt.scala 1376:81]
- wire [15:0] _log_T_651 = _log_T_644 | _GEN_177; // @[VAluInt.scala 1376:81]
- wire [4:0] _log_T_727 = io_in_sz[1] ? log_clz_5 : 5'h0; // @[Library.scala 32:8]
- wire [4:0] _log_T_728 = io_op_log_clz ? _log_T_727 : 5'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_182 = {{11'd0}, _log_T_728}; // @[VAluInt.scala 1377:69]
- wire [15:0] _log_T_729 = _log_T_651 | _GEN_182; // @[VAluInt.scala 1377:69]
- wire [1:0] _log_T_747 = log_a_1[16] + log_a_1[17]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_749 = log_a_1[18] + log_a_1[19]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_751 = _log_T_747 + _log_T_749; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_753 = log_a_1[20] + log_a_1[21]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_755 = log_a_1[22] + log_a_1[23]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_757 = _log_T_753 + _log_T_755; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_759 = _log_T_751 + _log_T_757; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_761 = log_a_1[24] + log_a_1[25]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_763 = log_a_1[26] + log_a_1[27]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_765 = _log_T_761 + _log_T_763; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_767 = log_a_1[28] + log_a_1[29]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_769 = log_a_1[30] + log_a_1[31]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_771 = _log_T_767 + _log_T_769; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_773 = _log_T_765 + _log_T_771; // @[Bitwise.scala 48:55]
- wire [4:0] _log_T_775 = _log_T_759 + _log_T_773; // @[Bitwise.scala 48:55]
- wire [4:0] _log_T_777 = io_op_log_cpop ? _log_T_775 : 5'h0; // @[Library.scala 32:8]
- wire [15:0] _GEN_183 = {{11'd0}, _log_T_777}; // @[VAluInt.scala 1378:69]
- wire [15:0] log_5 = _log_T_729 | _GEN_183; // @[VAluInt.scala 1378:69]
- wire [15:0] _shift_T_20 = io_op_shf_shl ? shl_5 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _shift_T_21 = io_op_shf_shr ? shr_5 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _shift_T_22 = _shift_T_20 | _shift_T_21; // @[VAluInt.scala 1383:35]
- wire [15:0] _shift_T_23 = io_op_shf_shf ? shf_5 : 16'h0; // @[Library.scala 32:8]
- wire [15:0] shift_5 = _shift_T_22 | _shift_T_23; // @[VAluInt.scala 1384:35]
- wire _alu_oh_T_70 = absd_5 != 16'h0; // @[VAluInt.scala 1388:30]
- wire _alu_oh_T_71 = add_5 != 16'h0; // @[VAluInt.scala 1389:30]
- wire _alu_oh_T_73 = dup_5 != 16'h0; // @[VAluInt.scala 1391:30]
- wire _alu_oh_T_74 = log_5 != 16'h0; // @[VAluInt.scala 1392:30]
- wire _alu_oh_T_75 = max_5 != 16'h0; // @[VAluInt.scala 1393:30]
- wire _alu_oh_T_76 = min_5 != 16'h0; // @[VAluInt.scala 1394:30]
- wire _alu_oh_T_77 = mul0_5 != 16'h0; // @[VAluInt.scala 1395:30]
- wire _alu_oh_T_78 = padd_1 != 16'h0; // @[VAluInt.scala 1396:30]
- wire _alu_oh_T_79 = rsub_5 != 16'h0; // @[VAluInt.scala 1397:30]
- wire _alu_oh_T_80 = shift_5 != 16'h0; // @[VAluInt.scala 1398:30]
- wire _alu_oh_T_81 = srans_5 != 16'h0; // @[VAluInt.scala 1399:30]
- wire _alu_oh_T_83 = sub_5 != 16'h0; // @[VAluInt.scala 1401:30]
- wire [6:0] alu_oh_lo_5 = {_alu_oh_T_77,_alu_oh_T_78,_alu_oh_T_79,_alu_oh_T_80,_alu_oh_T_81,1'h0,_alu_oh_T_83}; // @[Cat.scala 31:58]
- wire [13:0] alu_oh_5 = {_alu_oh_T_70,_alu_oh_T_71,cmp_5,_alu_oh_T_73,_alu_oh_T_74,_alu_oh_T_75,_alu_oh_T_76,
- alu_oh_lo_5}; // @[Cat.scala 31:58]
- wire [1:0] _T_546 = alu_oh_5[1] + alu_oh_5[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_184 = {{1'd0}, alu_oh_5[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_548 = _GEN_184 + _T_546; // @[Bitwise.scala 48:55]
- wire [1:0] _T_550 = alu_oh_5[3] + alu_oh_5[4]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_552 = alu_oh_5[5] + alu_oh_5[6]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_554 = _T_550 + _T_552; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_185 = {{1'd0}, _T_548[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_556 = _GEN_185 + _T_554; // @[Bitwise.scala 48:55]
- wire [1:0] _T_558 = alu_oh_5[8] + alu_oh_5[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_186 = {{1'd0}, alu_oh_5[7]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_560 = _GEN_186 + _T_558; // @[Bitwise.scala 48:55]
- wire [1:0] _T_562 = alu_oh_5[10] + alu_oh_5[11]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_564 = alu_oh_5[12] + alu_oh_5[13]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_566 = _T_562 + _T_564; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_187 = {{1'd0}, _T_560[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_568 = _GEN_187 + _T_566; // @[Bitwise.scala 48:55]
- wire [3:0] _T_570 = _T_556[2:0] + _T_568[2:0]; // @[Bitwise.scala 48:55]
- wire [15:0] _alu0_1_T_16 = mul0_5 | absd_5; // @[VAluInt.scala 1405:23]
- wire [15:0] _alu0_1_T_17 = _alu0_1_T_16 | add_5; // @[VAluInt.scala 1405:30]
- wire [15:0] _GEN_188 = {{15'd0}, cmp_5}; // @[VAluInt.scala 1405:36]
- wire [15:0] _alu0_1_T_18 = _alu0_1_T_17 | _GEN_188; // @[VAluInt.scala 1405:36]
- wire [15:0] _alu0_1_T_19 = _alu0_1_T_18 | dup_5; // @[VAluInt.scala 1405:42]
- wire [15:0] _alu0_1_T_20 = _alu0_1_T_19 | log_5; // @[VAluInt.scala 1405:48]
- wire [15:0] _alu0_1_T_21 = _alu0_1_T_20 | max_5; // @[VAluInt.scala 1405:54]
- wire [15:0] _alu0_1_T_22 = _alu0_1_T_21 | min_5; // @[VAluInt.scala 1405:60]
- wire [15:0] _alu0_1_T_23 = _alu0_1_T_22 | padd_1; // @[VAluInt.scala 1405:66]
- wire [15:0] _alu0_1_T_24 = _alu0_1_T_23 | rsub_5; // @[VAluInt.scala 1405:73]
- wire [15:0] _alu0_1_T_25 = _alu0_1_T_24 | shift_5; // @[VAluInt.scala 1405:80]
- wire [15:0] _alu0_1_T_26 = _alu0_1_T_25 | srans_5; // @[VAluInt.scala 1405:88]
- wire [15:0] _alu0_1_T_28 = _alu0_1_T_26 | sub_5; // @[VAluInt.scala 1405:104]
- wire [15:0] _alu0_1_T_30 = io_op_mv ? ina_h[31:16] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] alu0_1_1 = _alu0_1_T_28 | _alu0_1_T_30; // @[VAluInt.scala 1405:110]
- wire [15:0] _alu1_1_T_7 = io_op_mvp ? inb_h[31:16] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] _alu1_1_T_8 = mul1_5 | _alu1_1_T_7; // @[VAluInt.scala 1408:23]
- wire [15:0] _alu1_1_T_10 = io_op_mv2 ? inc_h[31:16] : 16'h0; // @[Library.scala 32:8]
- wire [15:0] alu1_1_1 = _alu1_1_T_8 | _alu1_1_T_10; // @[VAluInt.scala 1409:44]
- wire [15:0] _GEN_189 = {{15'd0}, mulh0_rnd_5}; // @[VAluInt.scala 1412:29]
- wire [15:0] _rnd0_1_T_2 = dmulh0_rnd_5 | _GEN_189; // @[VAluInt.scala 1412:29]
- wire [15:0] _GEN_190 = {{15'd0}, shf_rnd_5}; // @[VAluInt.scala 1412:41]
- wire [15:0] rnd0_1_1 = _rnd0_1_T_2 | _GEN_190; // @[VAluInt.scala 1412:41]
- wire [15:0] _GEN_191 = {{15'd0}, mulh1_rnd_5}; // @[VAluInt.scala 1413:29]
- wire [15:0] rnd1_1_1 = dmulh1_rnd_5 | _GEN_191; // @[VAluInt.scala 1413:29]
- wire [31:0] _aluw1_0_T_3 = acc_5 | addw_5; // @[VAluInt.scala 1419:31]
- wire [31:0] _aluw1_0_T_4 = _aluw1_0_T_3 | mulw_5; // @[VAluInt.scala 1419:38]
- wire [31:0] aluw1_1_0 = _aluw1_0_T_4 | subw_5; // @[VAluInt.scala 1419:45]
- wire [31:0] outh0 = {alu0_1_1,alu0_1_0}; // @[VAluInt.scala 1424:25]
- wire [31:0] outh1 = {alu1_1_1,alu1_1_0}; // @[VAluInt.scala 1425:25]
- wire [31:0] rndh0 = {rnd0_1_1,rnd0_1_0}; // @[VAluInt.scala 1426:25]
- wire [31:0] rndh1 = {rnd1_1_1,rnd1_1_0}; // @[VAluInt.scala 1427:25]
- wire [31:0] add_a_2 = io_op_add_en ? ina_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] add_b_2 = io_op_add_en ? inb_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] cmp_a_2 = io_op_cmp_en ? ina_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] cmp_b_2 = io_op_cmp_en ? inb_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] log_a_2 = io_op_log_en ? ina_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] log_b_14 = io_op_log_en ? inb_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul0_a_2 = io_op_mul0_en ? ina_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul0_b_2 = io_op_mul0_en ? inb_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul1_a_2 = io_op_mul1_en ? inc_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul1_b_2 = io_op_mul1_en ? inb_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] padd_a_4 = io_op_padd_en ? ina_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] rsub_a_2 = io_op_rsub_en ? ina_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] rsub_b_2 = io_op_rsub_en ? inb_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shl_a_2 = io_op_shf_en_l ? ina_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shl_b_2 = io_op_shf_en_l ? inb_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shr_a_2 = io_op_shf_en_r ? ina_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shr_b_2 = io_op_shf_en_r ? inb_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sub_a_2 = io_op_sub_en ? ina_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sub_b_2 = io_op_sub_en ? inb_w : 32'h0; // @[Library.scala 32:8]
- wire add_sa_6 = add_a_2[31] & io_in_signed; // @[VAluInt.scala 973:29]
- wire add_sb_6 = add_b_2[31] & io_in_signed; // @[VAluInt.scala 974:29]
- wire [32:0] _adder_T_56 = {add_sa_6,add_a_2}; // @[VAluInt.scala 975:44]
- wire [32:0] _adder_T_59 = {add_sb_6,add_b_2}; // @[VAluInt.scala 975:78]
- wire [33:0] _adder_T_61 = $signed(_adder_T_56) + $signed(_adder_T_59); // @[VAluInt.scala 975:86]
- wire [33:0] _GEN_192 = {{33'd0}, add_r}; // @[VAluInt.scala 975:93]
- wire [33:0] adder_6 = _adder_T_61 + _GEN_192; // @[VAluInt.scala 975:93]
- wire [1:0] sataddmsb_6 = adder_6[32:31]; // @[VAluInt.scala 976:28]
- wire _sataddsel_T_43 = io_in_signed & sataddmsb_6 == 2'h2; // @[VAluInt.scala 978:21]
- wire _sataddsel_T_45 = io_in_signed & sataddmsb_6 == 2'h1; // @[VAluInt.scala 979:21]
- wire _sataddsel_T_48 = ~io_in_signed & sataddmsb_6[1]; // @[VAluInt.scala 980:21]
- wire [2:0] sataddsel_6 = {_sataddsel_T_43,_sataddsel_T_45,_sataddsel_T_48}; // @[Cat.scala 31:58]
- wire [1:0] _T_579 = sataddsel_6[1] + sataddsel_6[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_193 = {{1'd0}, sataddsel_6[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_581 = _GEN_193 + _T_579; // @[Bitwise.scala 48:55]
- wire sub_sa_6 = sub_a_2[31] & io_in_signed; // @[VAluInt.scala 983:29]
- wire sub_sb_6 = sub_b_2[31] & io_in_signed; // @[VAluInt.scala 984:29]
- wire [32:0] _subtr_T_56 = {sub_sa_6,sub_a_2}; // @[VAluInt.scala 985:44]
- wire [32:0] _subtr_T_59 = {sub_sb_6,sub_b_2}; // @[VAluInt.scala 985:78]
- wire [33:0] _subtr_T_61 = $signed(_subtr_T_56) - $signed(_subtr_T_59); // @[VAluInt.scala 985:86]
- wire [33:0] _GEN_194 = {{33'd0}, sub_r}; // @[VAluInt.scala 985:93]
- wire [33:0] subtr_6 = _subtr_T_61 + _GEN_194; // @[VAluInt.scala 985:93]
- wire [1:0] satsubmsb_6 = subtr_6[32:31]; // @[VAluInt.scala 986:28]
- wire _satsubsel_T_43 = io_in_signed & satsubmsb_6 == 2'h2; // @[VAluInt.scala 988:21]
- wire _satsubsel_T_45 = io_in_signed & satsubmsb_6 == 2'h1; // @[VAluInt.scala 989:21]
- wire _satsubsel_T_48 = _sataddsel_T_4 & satsubmsb_6[1]; // @[VAluInt.scala 990:21]
- wire [2:0] satsubsel_6 = {_satsubsel_T_43,_satsubsel_T_45,_satsubsel_T_48}; // @[Cat.scala 31:58]
- wire [1:0] _T_590 = satsubsel_6[1] + satsubsel_6[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_195 = {{1'd0}, satsubsel_6[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_592 = _GEN_195 + _T_590; // @[Bitwise.scala 48:55]
- wire [31:0] rsubtr_6 = rsub_b_2 - rsub_a_2; // @[VAluInt.scala 993:32]
- wire xeq_6 = cmp_a_2 == cmp_b_2; // @[VAluInt.scala 995:28]
- wire xne_6 = cmp_a_2 != cmp_b_2; // @[VAluInt.scala 996:28]
- wire [31:0] _slt_T_25 = io_op_cmp_en ? ina_w : 32'h0; // @[VAluInt.scala 997:34]
- wire [31:0] _slt_T_27 = io_op_cmp_en ? inb_w : 32'h0; // @[VAluInt.scala 997:56]
- wire slt_6 = $signed(_slt_T_25) < $signed(_slt_T_27); // @[VAluInt.scala 997:37]
- wire ult_6 = cmp_a_2 < cmp_b_2; // @[VAluInt.scala 998:28]
- wire sle_6 = slt_6 | xeq_6; // @[VAluInt.scala 999:21]
- wire ule_6 = ult_6 | xeq_6; // @[VAluInt.scala 1000:21]
- wire sult_6 = io_in_signed ? slt_6 : ult_6; // @[VAluInt.scala 1002:21]
- wire [62:0] _GEN_55 = {{31'd0}, shl_a_2}; // @[VAluInt.scala 1062:29]
- wire [62:0] _shl_T_20 = _GEN_55 << shl_b_2[4:0]; // @[VAluInt.scala 1062:29]
- wire [31:0] shl_6 = _shl_T_20[31:0]; // @[VAluInt.scala 1062:49]
- wire [5:0] _GEN_196 = {{1'd0}, shl_b_2[4:0]}; // @[VAluInt.scala 1063:40]
- wire [5:0] _sln_T_33 = 6'h20 - _GEN_196; // @[VAluInt.scala 1063:40]
- wire [94:0] _GEN_66 = {{63'd0}, shl_a_2}; // @[VAluInt.scala 1063:29]
- wire [94:0] _sln_T_34 = _GEN_66 << _sln_T_33; // @[VAluInt.scala 1063:29]
- wire [62:0] sln_6 = _sln_T_34[62:0]; // @[VAluInt.scala 1063:60]
- wire [31:0] srl_6 = shr_a_2 >> shr_b_2[4:0]; // @[VAluInt.scala 1064:28]
- wire [4:0] _srs_T_46 = 5'h1f - shr_b_2[4:0]; // @[VAluInt.scala 1065:66]
- wire [62:0] _srs_T_47 = 63'hffffffff << _srs_T_46; // @[VAluInt.scala 1065:49]
- wire [31:0] srs_6 = shr_a_2[31] ? _srs_T_47[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sra_6 = srs_6 | srl_6; // @[VAluInt.scala 1066:21]
- wire [31:0] shf_slnsz_6 = sln_6[31:0]; // @[VAluInt.scala 1010:24]
- wire shf_input_neg_6 = shl_a_2[31]; // @[VAluInt.scala 1011:26]
- wire shf_input_zero_6 = shl_a_2 == 32'h0; // @[VAluInt.scala 1012:28]
- wire shf_shamt_neg_6 = shl_b_2[31]; // @[VAluInt.scala 1013:26]
- wire [31:0] _shf_shamt_negsat_T_30 = io_op_shf_en_l ? inb_w : 32'h0; // @[VAluInt.scala 1017:32]
- wire shf_shamt_negsat_12 = $signed(_shf_shamt_negsat_T_30) <= -32'sh1f; // @[VAluInt.scala 1017:39]
- wire shf_shamt_possat_12 = $signed(_shf_shamt_negsat_T_30) >= 32'sh1f; // @[VAluInt.scala 1018:39]
- wire [4:0] _shf_signb_T_27 = shl_b_2[4:0] - 5'h1; // @[VAluInt.scala 1019:65]
- wire [31:0] shf_signb_6 = 32'hffffffff >> _shf_signb_T_27; // @[VAluInt.scala 1019:36]
- wire _shf_possat_T_78 = ~shf_input_zero_6; // @[VAluInt.scala 1020:112]
- wire shf_possat_12 = shf_shamt_neg_6 & ~shf_input_neg_6 & (shf_shamt_negsat_12 | sln_6[62:31] != 32'h0) & ~
- shf_input_zero_6; // @[VAluInt.scala 1020:109]
- wire shf_negsat_6 = shf_shamt_neg_6 & shf_input_neg_6 & (shf_shamt_negsat_12 | sln_6[62:31] != shf_signb_6); // @[VAluInt.scala 1021:48]
- wire _shf_rs_T_132 = ~shf_shamt_neg_6; // @[VAluInt.scala 1028:23]
- wire _shf_rs_T_134 = ~shf_shamt_neg_6 & ~shf_shamt_possat_12; // @[VAluInt.scala 1028:34]
- wire [31:0] _shf_rs_T_135 = _shf_rs_T_134 ? sra_6 : 32'h0; // @[Library.scala 32:8]
- wire _shf_rs_T_138 = _shf_rs_T_132 & shf_shamt_possat_12 & shf_input_neg_6; // @[VAluInt.scala 1029:51]
- wire [31:0] _shf_rs_T_140 = _shf_rs_T_138 ? 32'hffffffff : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _shf_rs_T_141 = _shf_rs_T_135 | _shf_rs_T_140; // @[VAluInt.scala 1028:57]
- wire _shf_rs_T_145 = shf_shamt_neg_6 & ~shf_possat_12 & ~shf_negsat_6; // @[VAluInt.scala 1030:45]
- wire [31:0] _shf_rs_T_146 = _shf_rs_T_145 ? shf_slnsz_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _shf_rs_T_147 = _shf_rs_T_141 | _shf_rs_T_146; // @[VAluInt.scala 1029:79]
- wire _shf_rs_T_148 = shf_shamt_neg_6 & shf_possat_12; // @[VAluInt.scala 1031:34]
- wire [31:0] _shf_rs_T_149 = _shf_rs_T_148 ? 32'h7fffffff : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _shf_rs_T_150 = _shf_rs_T_147 | _shf_rs_T_149; // @[VAluInt.scala 1030:64]
- wire _shf_rs_T_151 = shf_shamt_neg_6 & shf_negsat_6; // @[VAluInt.scala 1032:34]
- wire [31:0] _shf_rs_T_152 = _shf_rs_T_151 ? 32'h80000000 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shf_rs_6 = _shf_rs_T_150 | _shf_rs_T_152; // @[VAluInt.scala 1031:53]
- wire [6:0] _shf_shamt_negsat_T_34 = 7'sh0 - 7'sh20; // @[VAluInt.scala 1035:42]
- wire [31:0] _GEN_197 = {{25{_shf_shamt_negsat_T_34[6]}},_shf_shamt_negsat_T_34}; // @[VAluInt.scala 1035:39]
- wire shf_shamt_negsat_13 = $signed(_shf_shamt_negsat_T_30) <= $signed(_GEN_197); // @[VAluInt.scala 1035:39]
- wire shf_shamt_possat_13 = $signed(_shf_shamt_negsat_T_30) >= 32'sh20; // @[VAluInt.scala 1036:39]
- wire shf_possat_13 = shf_shamt_neg_6 & (shf_shamt_negsat_13 | sln_6[62:32] != 31'h0) & _shf_possat_T_78; // @[VAluInt.scala 1037:89]
- wire _shf_ru_T_68 = _shf_rs_T_132 & ~shf_shamt_possat_13; // @[VAluInt.scala 1041:34]
- wire [31:0] _shf_ru_T_69 = _shf_ru_T_68 ? srl_6 : 32'h0; // @[Library.scala 32:8]
- wire _shf_ru_T_71 = shf_shamt_neg_6 & ~shf_possat_13; // @[VAluInt.scala 1042:34]
- wire [31:0] _shf_ru_T_72 = _shf_ru_T_71 ? shf_slnsz_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _shf_ru_T_73 = _shf_ru_T_69 | _shf_ru_T_72; // @[VAluInt.scala 1041:57]
- wire _shf_ru_T_74 = shf_shamt_neg_6 & shf_possat_13; // @[VAluInt.scala 1043:34]
- wire [31:0] _shf_ru_T_75 = _shf_ru_T_74 ? 32'hffffffff : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shf_ru_6 = _shf_ru_T_73 | _shf_ru_T_75; // @[VAluInt.scala 1042:53]
- wire [31:0] shf_6 = io_in_signed ? shf_rs_6 : shf_ru_6; // @[VAluInt.scala 1045:12]
- wire [31:0] shr_6 = io_in_signed ? sra_6 : srl_6; // @[VAluInt.scala 1068:20]
- wire shf_rnd_shamt_zero_6 = shl_b_2 == 32'h0; // @[VAluInt.scala 1053:28]
- wire [31:0] _shf_rnd_rbit_T_32 = {shl_a_2[30:0],shf_input_neg_6}; // @[Cat.scala 31:58]
- wire [31:0] _shf_rnd_rbit_T_34 = _shf_rnd_rbit_T_32 >> shl_b_2[4:0]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_rbit_6 = _shf_rnd_rbit_T_34[0]; // @[VAluInt.scala 1054:52]
- wire shf_rnd_shamt_possat_6 = io_in_signed ? shf_shamt_possat_13 : $signed(_shf_shamt_negsat_T_30) > 32'sh20; // @[VAluInt.scala 1055:31]
- wire _shf_rnd_r_T_71 = io_in_round & ~shf_rnd_shamt_possat_6 & _shf_rs_T_132 & ~shf_rnd_shamt_zero_6; // @[VAluInt.scala 1056:60]
- wire _shf_rnd_r_T_72 = _shf_rnd_r_T_71 & shf_rnd_rbit_6; // @[Library.scala 36:8]
- wire _shf_rnd_r_T_75 = io_in_round & shf_rnd_shamt_possat_6 & shf_input_neg_6 & io_in_signed; // @[VAluInt.scala 1057:59]
- wire shf_rnd_6 = _shf_rnd_r_T_72 | _shf_rnd_r_T_75; // @[VAluInt.scala 1056:82]
- wire _mul0_as_T_19 = io_in_signed & mul0_a_2[31]; // @[VAluInt.scala 1199:32]
- wire _mul0_bs_T_19 = io_in_signed & mul0_b_2[31]; // @[VAluInt.scala 1200:32]
- wire mul0_sign_6 = mul0_a_2[31] != mul0_b_2[31] & mul0_a_2 != 32'h0 & mul0_b_2 != 32'h0; // @[VAluInt.scala 1201:70]
- wire [32:0] _prod0_T_18 = {_mul0_as_T_19,mul0_a_2}; // @[VAluInt.scala 1202:28]
- wire [32:0] _prod0_T_19 = {_mul0_bs_T_19,mul0_b_2}; // @[VAluInt.scala 1202:45]
- wire [65:0] prod0_6 = $signed(_prod0_T_18) * $signed(_prod0_T_19); // @[VAluInt.scala 1202:53]
- wire [31:0] prodh0_6 = prod0_6[63:32]; // @[VAluInt.scala 1203:25]
- wire [31:0] proddh0_6 = prod0_6[62:31]; // @[VAluInt.scala 1204:26]
- wire _mul1_as_T_19 = io_in_signed & mul1_a_2[31]; // @[VAluInt.scala 1206:32]
- wire _mul1_bs_T_19 = io_in_signed & mul1_b_2[31]; // @[VAluInt.scala 1207:32]
- wire mul1_sign_6 = mul1_a_2[31] != mul1_b_2[31] & mul1_a_2 != 32'h0 & mul1_b_2 != 32'h0; // @[VAluInt.scala 1208:70]
- wire [32:0] _prod1_T_18 = {_mul1_as_T_19,mul1_a_2}; // @[VAluInt.scala 1209:28]
- wire [32:0] _prod1_T_19 = {_mul1_bs_T_19,mul1_b_2}; // @[VAluInt.scala 1209:45]
- wire [65:0] prod1_6 = $signed(_prod1_T_18) * $signed(_prod1_T_19); // @[VAluInt.scala 1209:53]
- wire [31:0] prodh1_6 = prod1_6[63:32]; // @[VAluInt.scala 1210:25]
- wire [31:0] proddh1_6 = prod1_6[62:31]; // @[VAluInt.scala 1211:26]
- wire _muls0_umax_T_13 = prodh0_6 != 32'h0; // @[VAluInt.scala 1213:42]
- wire muls0_umax_6 = _sataddsel_T_4 & prodh0_6 != 32'h0; // @[VAluInt.scala 1213:32]
- wire muls0_smax_6 = io_in_signed & ~mul0_sign_6 & (prod0_6[31] | _muls0_umax_T_13); // @[VAluInt.scala 1214:46]
- wire muls0_smin_6 = io_in_signed & mul0_sign_6 & (~prod0_6[31] | prodh0_6 != 32'hffffffff); // @[VAluInt.scala 1215:46]
- wire muls0_base_6 = ~(muls0_umax_6 | muls0_smax_6 | muls0_smin_6); // @[VAluInt.scala 1216:24]
- wire [3:0] _T_598 = {muls0_umax_6,muls0_smax_6,muls0_smin_6,muls0_base_6}; // @[Cat.scala 31:58]
- wire [1:0] _T_603 = _T_598[0] + _T_598[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_605 = _T_598[2] + _T_598[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_607 = _T_603 + _T_605; // @[Bitwise.scala 48:55]
- wire _muls1_umax_T_13 = prodh1_6 != 32'h0; // @[VAluInt.scala 1219:42]
- wire muls1_umax_6 = _sataddsel_T_4 & prodh1_6 != 32'h0; // @[VAluInt.scala 1219:32]
- wire muls1_smax_6 = io_in_signed & ~mul1_sign_6 & (prod1_6[31] | _muls1_umax_T_13); // @[VAluInt.scala 1220:46]
- wire muls1_smin_6 = io_in_signed & mul1_sign_6 & (~prod1_6[31] | prodh1_6 != 32'hffffffff); // @[VAluInt.scala 1221:46]
- wire muls1_base_6 = ~(muls1_umax_6 | muls1_smax_6 | muls1_smin_6); // @[VAluInt.scala 1222:24]
- wire [3:0] _T_613 = {muls1_umax_6,muls1_smax_6,muls1_smin_6,muls1_base_6}; // @[Cat.scala 31:58]
- wire [1:0] _T_618 = _T_613[0] + _T_613[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_620 = _T_613[2] + _T_613[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_622 = _T_618 + _T_620; // @[Bitwise.scala 48:55]
- wire dmulh0_possat_6 = mul0_a_2 == 32'h80000000 & mul0_b_2 == 32'h80000000; // @[VAluInt.scala 1227:50]
- wire dmulh1_possat_6 = mul1_a_2 == 32'h80000000 & mul1_b_2 == 32'h80000000; // @[VAluInt.scala 1229:50]
- wire _dmulh0_T_30 = ~dmulh0_possat_6; // @[VAluInt.scala 1231:26]
- wire [31:0] _dmulh0_T_31 = _dmulh0_T_30 ? proddh0_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _dmulh0_T_34 = dmulh0_possat_6 ? 32'h7fffffff : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dmulh0_6 = _dmulh0_T_31 | _dmulh0_T_34; // @[VAluInt.scala 1231:51]
- wire _dmulh1_T_30 = ~dmulh1_possat_6; // @[VAluInt.scala 1234:26]
- wire [31:0] _dmulh1_T_31 = _dmulh1_T_30 ? proddh1_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _dmulh1_T_34 = dmulh1_possat_6 ? 32'h7fffffff : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dmulh1_6 = _dmulh1_T_31 | _dmulh1_T_34; // @[VAluInt.scala 1234:51]
- wire [31:0] _muls0_T_61 = muls0_umax_6 ? 32'hffffffff : 32'h0; // @[Library.scala 32:8]
- wire [30:0] _muls0_T_63 = muls0_smax_6 ? 31'h7fffffff : 31'h0; // @[Library.scala 32:8]
- wire [31:0] _GEN_198 = {{1'd0}, _muls0_T_63}; // @[VAluInt.scala 1240:51]
- wire [31:0] _muls0_T_64 = _muls0_T_61 | _GEN_198; // @[VAluInt.scala 1240:51]
- wire [31:0] _muls0_T_66 = muls0_smin_6 ? 32'h80000000 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _muls0_T_67 = _muls0_T_64 | _muls0_T_66; // @[VAluInt.scala 1241:57]
- wire [31:0] _muls0_T_69 = muls0_base_6 ? prod0_6[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] muls0_6 = _muls0_T_67 | _muls0_T_69; // @[VAluInt.scala 1242:71]
- wire [31:0] _muls1_T_61 = muls1_umax_6 ? 32'hffffffff : 32'h0; // @[Library.scala 32:8]
- wire [30:0] _muls1_T_63 = muls1_smax_6 ? 31'h7fffffff : 31'h0; // @[Library.scala 32:8]
- wire [31:0] _GEN_199 = {{1'd0}, _muls1_T_63}; // @[VAluInt.scala 1245:51]
- wire [31:0] _muls1_T_64 = _muls1_T_61 | _GEN_199; // @[VAluInt.scala 1245:51]
- wire [31:0] _muls1_T_66 = muls1_smin_6 ? 32'h80000000 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _muls1_T_67 = _muls1_T_64 | _muls1_T_66; // @[VAluInt.scala 1246:57]
- wire [31:0] _muls1_T_69 = muls1_base_6 ? prod1_6[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] muls1_6 = _muls1_T_67 | _muls1_T_69; // @[VAluInt.scala 1247:71]
- wire _dmulh0_rnd_T_82 = io_in_round & io_op_mul0_dmulh & io_in_sz[2] & _dmulh0_T_30; // @[VAluInt.scala 1250:72]
- wire _dmulh0_rnd_T_85 = ~prod0_6[30]; // @[VAluInt.scala 1252:40]
- wire [31:0] _dmulh0_rnd_T_87 = _dmulh0_rnd_T_85 ? 32'hffffffff : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _dmulh0_rnd_T_89 = prod0_6[30] ? 32'h1 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _dmulh0_rnd_T_90 = io_in_negative & mul0_sign_6 ? _dmulh0_rnd_T_87 : _dmulh0_rnd_T_89; // @[VAluInt.scala 1251:33]
- wire [31:0] dmulh0_rnd_6 = _dmulh0_rnd_T_82 ? _dmulh0_rnd_T_90 : 32'h0; // @[Library.scala 32:8]
- wire _dmulh1_rnd_T_82 = io_in_round & io_op_mul1_dmulh & io_in_sz[2] & _dmulh1_T_30; // @[VAluInt.scala 1255:72]
- wire _dmulh1_rnd_T_85 = ~prod1_6[30]; // @[VAluInt.scala 1257:40]
- wire [31:0] _dmulh1_rnd_T_87 = _dmulh1_rnd_T_85 ? 32'hffffffff : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _dmulh1_rnd_T_89 = prod1_6[30] ? 32'h1 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _dmulh1_rnd_T_90 = io_in_negative & mul1_sign_6 ? _dmulh1_rnd_T_87 : _dmulh1_rnd_T_89; // @[VAluInt.scala 1256:33]
- wire [31:0] dmulh1_rnd_6 = _dmulh1_rnd_T_82 ? _dmulh1_rnd_T_90 : 32'h0; // @[Library.scala 32:8]
- wire mulh0_rnd_6 = io_in_round & io_op_mul0_mulh & prod0_6[31]; // @[VAluInt.scala 1260:48]
- wire mulh1_rnd_6 = io_in_round & io_op_mul1_mulh & prod1_6[31]; // @[VAluInt.scala 1261:48]
- wire [31:0] _absd_T_13 = sult_6 ? rsubtr_6 : subtr_6[31:0]; // @[VAluInt.scala 1265:39]
- wire [31:0] absd_6 = io_op_absd ? _absd_T_13 : 32'h0; // @[Library.scala 32:8]
- wire _add_T_139 = sataddsel_6[2] & io_op_add_adds; // @[VAluInt.scala 1279:36]
- wire [31:0] _add_T_141 = _add_T_139 ? 32'h80000000 : 32'h0; // @[Library.scala 32:8]
- wire _add_T_143 = sataddsel_6[1] & io_op_add_adds; // @[VAluInt.scala 1280:36]
- wire [30:0] _add_T_145 = _add_T_143 ? 31'h7fffffff : 31'h0; // @[Library.scala 32:8]
- wire [31:0] _GEN_200 = {{1'd0}, _add_T_145}; // @[VAluInt.scala 1279:89]
- wire [31:0] _add_T_146 = _add_T_141 | _GEN_200; // @[VAluInt.scala 1279:89]
- wire _add_T_148 = sataddsel_6[0] & io_op_add_adds; // @[VAluInt.scala 1281:36]
- wire [31:0] _add_T_150 = _add_T_148 ? 32'hffffffff : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _add_T_151 = _add_T_146 | _add_T_150; // @[VAluInt.scala 1280:75]
- wire _add_T_155 = sataddsel_6 == 3'h0 & io_op_add_adds | io_op_add_add | io_op_add_add3; // @[VAluInt.scala 1282:76]
- wire [31:0] _add_T_157 = _add_T_155 ? adder_6[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _add_T_158 = _add_T_151 | _add_T_157; // @[VAluInt.scala 1281:69]
- wire [31:0] _add_T_160 = io_op_add_hadd ? adder_6[32:1] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] add_6 = _add_T_158 | _add_T_160; // @[VAluInt.scala 1282:115]
- wire [31:0] dup_6 = io_op_dup ? io_read_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _max_T_20 = sult_6 ? cmp_b_2 : cmp_a_2; // @[VAluInt.scala 1290:37]
- wire [31:0] max_6 = io_op_max ? _max_T_20 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _min_T_20 = sult_6 ? cmp_a_2 : cmp_b_2; // @[VAluInt.scala 1291:37]
- wire [31:0] min_6 = io_op_min ? _min_T_20 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _mul0_T_50 = _mul0_T ? prod0_6[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _mul0_T_51 = io_op_mul0_dmulh ? dmulh0_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _mul0_T_52 = _mul0_T_50 | _mul0_T_51; // @[VAluInt.scala 1293:79]
- wire [31:0] _mul0_T_53 = io_op_mul0_mulh ? prodh0_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _mul0_T_54 = _mul0_T_52 | _mul0_T_53; // @[VAluInt.scala 1294:50]
- wire [31:0] _mul0_T_55 = io_op_mul0_muls ? muls0_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul0_6 = _mul0_T_54 | _mul0_T_55; // @[VAluInt.scala 1295:48]
- wire [31:0] _mul1_T_43 = io_op_mul1_mul ? prod1_6[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _mul1_T_44 = io_op_mul1_dmulh ? dmulh1_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _mul1_T_45 = _mul1_T_43 | _mul1_T_44; // @[VAluInt.scala 1298:60]
- wire [31:0] _mul1_T_46 = io_op_mul1_mulh ? prodh1_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _mul1_T_47 = _mul1_T_45 | _mul1_T_46; // @[VAluInt.scala 1299:50]
- wire [31:0] _mul1_T_48 = io_op_mul1_muls ? muls1_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] mul1_6 = _mul1_T_47 | _mul1_T_48; // @[VAluInt.scala 1300:48]
- wire _padd_a_T_7 = io_in_signed & padd_a_4[15]; // @[VAluInt.scala 1311:30]
- wire _padd_b_T_7 = io_in_signed & padd_a_4[31]; // @[VAluInt.scala 1312:30]
- wire [16:0] _padd_add_T_8 = {_padd_a_T_7,padd_a_4[15:0]}; // @[VAluInt.scala 1313:54]
- wire [16:0] _padd_add_T_9 = {_padd_b_T_7,padd_a_4[31:16]}; // @[VAluInt.scala 1313:66]
- wire [17:0] _padd_add_T_11 = $signed(_padd_add_T_8) + $signed(_padd_add_T_9); // @[VAluInt.scala 1313:74]
- wire padd_add_r_r_2_2 = _padd_add_T_11[17]; // @[Library.scala 64:25]
- wire [6:0] padd_add_r_lo_2 = {padd_add_r_r_2_2,padd_add_r_r_2_2,padd_add_r_r_2_2,padd_add_r_r_2_2,padd_add_r_r_2_2,
- padd_add_r_r_2_2,padd_add_r_r_2_2}; // @[Library.scala 57:7]
- wire [31:0] padd_add_r_2 = {padd_add_r_r_2_2,padd_add_r_r_2_2,padd_add_r_r_2_2,padd_add_r_r_2_2,padd_add_r_r_2_2,
- padd_add_r_r_2_2,padd_add_r_r_2_2,padd_add_r_lo_2,_padd_add_T_11}; // @[Cat.scala 31:58]
- wire [31:0] padd_add_2 = io_op_padd_add ? padd_add_r_2 : 32'h0; // @[Library.scala 32:8]
- wire [17:0] _padd_sub_T_11 = $signed(_padd_add_T_8) - $signed(_padd_add_T_9); // @[VAluInt.scala 1314:74]
- wire padd_sub_r_r_2_2 = _padd_sub_T_11[17]; // @[Library.scala 64:25]
- wire [6:0] padd_sub_r_lo_2 = {padd_sub_r_r_2_2,padd_sub_r_r_2_2,padd_sub_r_r_2_2,padd_sub_r_r_2_2,padd_sub_r_r_2_2,
- padd_sub_r_r_2_2,padd_sub_r_r_2_2}; // @[Library.scala 57:7]
- wire [31:0] padd_sub_r_2 = {padd_sub_r_r_2_2,padd_sub_r_r_2_2,padd_sub_r_r_2_2,padd_sub_r_r_2_2,padd_sub_r_r_2_2,
- padd_sub_r_r_2_2,padd_sub_r_r_2_2,padd_sub_r_lo_2,_padd_sub_T_11}; // @[Cat.scala 31:58]
- wire [31:0] padd_sub_2 = io_op_padd_sub ? padd_sub_r_2 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] padd_2 = padd_add_2 | padd_sub_2; // @[VAluInt.scala 1317:15]
- wire [31:0] rsub_6 = io_op_rsub_rsub ? rsubtr_6 : 32'h0; // @[Library.scala 32:8]
- wire _sub_T_127 = satsubsel_6[2] & io_op_sub_subs; // @[VAluInt.scala 1348:36]
- wire [31:0] _sub_T_129 = _sub_T_127 ? 32'h80000000 : 32'h0; // @[Library.scala 32:8]
- wire _sub_T_131 = satsubsel_6[1] & io_op_sub_subs; // @[VAluInt.scala 1349:36]
- wire [30:0] _sub_T_133 = _sub_T_131 ? 31'h7fffffff : 31'h0; // @[Library.scala 32:8]
- wire [31:0] _GEN_201 = {{1'd0}, _sub_T_133}; // @[VAluInt.scala 1348:89]
- wire [31:0] _sub_T_134 = _sub_T_129 | _GEN_201; // @[VAluInt.scala 1348:89]
- wire _sub_T_141 = satsubsel_6 == 3'h0 & io_op_sub_subs | io_op_sub_sub; // @[VAluInt.scala 1351:59]
- wire [31:0] _sub_T_143 = _sub_T_141 ? subtr_6[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _sub_T_144 = _sub_T_134 | _sub_T_143; // @[VAluInt.scala 1350:68]
- wire [31:0] _sub_T_146 = io_op_sub_hsub ? subtr_6[32:1] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] sub_6 = _sub_T_144 | _sub_T_146; // @[VAluInt.scala 1351:97]
- wire _cmp_T_217 = io_op_cmp_eq & xeq_6; // @[Library.scala 36:8]
- wire _cmp_T_218 = io_op_cmp_ne & xne_6; // @[Library.scala 36:8]
- wire _cmp_T_219 = _cmp_T_217 | _cmp_T_218; // @[VAluInt.scala 1358:45]
- wire _cmp_T_221 = _cmp_T_4 & slt_6; // @[Library.scala 36:8]
- wire _cmp_T_222 = _cmp_T_219 | _cmp_T_221; // @[VAluInt.scala 1359:45]
- wire _cmp_T_225 = _cmp_T_8 & ult_6; // @[Library.scala 36:8]
- wire _cmp_T_226 = _cmp_T_222 | _cmp_T_225; // @[VAluInt.scala 1360:56]
- wire _cmp_T_228 = _cmp_T_11 & sle_6; // @[Library.scala 36:8]
- wire _cmp_T_229 = _cmp_T_226 | _cmp_T_228; // @[VAluInt.scala 1361:56]
- wire _cmp_T_232 = _cmp_T_15 & ule_6; // @[Library.scala 36:8]
- wire _cmp_T_233 = _cmp_T_229 | _cmp_T_232; // @[VAluInt.scala 1362:56]
- wire _cmp_T_235 = ~sle_6; // @[VAluInt.scala 1364:51]
- wire _cmp_T_236 = _cmp_T_18 & _cmp_T_235; // @[Library.scala 36:8]
- wire _cmp_T_237 = _cmp_T_233 | _cmp_T_236; // @[VAluInt.scala 1363:56]
- wire _cmp_T_240 = ~ule_6; // @[VAluInt.scala 1365:51]
- wire _cmp_T_241 = _cmp_T_23 & _cmp_T_240; // @[Library.scala 36:8]
- wire _cmp_T_242 = _cmp_T_237 | _cmp_T_241; // @[VAluInt.scala 1364:57]
- wire _cmp_T_244 = ~slt_6; // @[VAluInt.scala 1366:51]
- wire _cmp_T_245 = _cmp_T_27 & _cmp_T_244; // @[Library.scala 36:8]
- wire _cmp_T_246 = _cmp_T_242 | _cmp_T_245; // @[VAluInt.scala 1365:57]
- wire _cmp_T_249 = ~ult_6; // @[VAluInt.scala 1367:51]
- wire _cmp_T_250 = _cmp_T_32 & _cmp_T_249; // @[Library.scala 36:8]
- wire _cmp_T_251 = _cmp_T_246 | _cmp_T_250; // @[VAluInt.scala 1366:57]
- wire cmp_6 = io_in_sz[2] & _cmp_T_251; // @[VAluInt.scala 1357:30]
- wire [31:0] _log_T_780 = log_a_2 & log_b_14; // @[VAluInt.scala 1371:42]
- wire [31:0] _log_T_781 = io_op_log_and ? _log_T_780 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _log_T_784 = log_a_2 | log_b_14; // @[VAluInt.scala 1372:42]
- wire [31:0] _log_T_785 = io_op_log_or ? _log_T_784 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _log_T_786 = _log_T_781 | _log_T_785; // @[VAluInt.scala 1371:56]
- wire [31:0] _log_T_789 = log_a_2 ^ log_b_14; // @[VAluInt.scala 1373:42]
- wire [31:0] _log_T_790 = io_op_log_xor ? _log_T_789 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _log_T_791 = _log_T_786 | _log_T_790; // @[VAluInt.scala 1372:56]
- wire [31:0] _log_T_794 = ~log_a_2; // @[VAluInt.scala 1374:51]
- wire [31:0] _log_T_795 = io_in_sz[2] ? _log_T_794 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _log_T_796 = io_op_log_not ? _log_T_795 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _log_T_797 = _log_T_791 | _log_T_796; // @[VAluInt.scala 1373:56]
- wire _log_b_T_113 = ~log_b_14[0]; // @[VAluInt.scala 1118:23]
- wire [7:0] log_b_lo_lo_6 = {log_a_2[6],log_a_2[7],log_a_2[4],log_a_2[5],log_a_2[2],log_a_2[3],log_a_2[0],log_a_2[1]}; // @[Cat.scala 31:58]
- wire [15:0] log_b_lo_6 = {log_a_2[14],log_a_2[15],log_a_2[12],log_a_2[13],log_a_2[10],log_a_2[11],log_a_2[8],log_a_2[9
- ],log_b_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] log_b_hi_lo_6 = {log_a_2[22],log_a_2[23],log_a_2[20],log_a_2[21],log_a_2[18],log_a_2[19],log_a_2[16],
- log_a_2[17]}; // @[Cat.scala 31:58]
- wire [31:0] _log_b_T_146 = {log_a_2[30],log_a_2[31],log_a_2[28],log_a_2[29],log_a_2[26],log_a_2[27],log_a_2[24],
- log_a_2[25],log_b_hi_lo_6,log_b_lo_6}; // @[Cat.scala 31:58]
- wire [31:0] log_b_15 = ~log_b_14[0] ? log_a_2 : _log_b_T_146; // @[VAluInt.scala 1118:22]
- wire _log_c_T_81 = ~log_b_14[1]; // @[VAluInt.scala 1122:23]
- wire [15:0] log_c_lo_6 = {log_b_15[13:12],log_b_15[15:14],log_b_15[9:8],log_b_15[11:10],log_b_15[5:4],log_b_15[7:6],
- log_b_15[1:0],log_b_15[3:2]}; // @[Cat.scala 31:58]
- wire [31:0] _log_c_T_98 = {log_b_15[29:28],log_b_15[31:30],log_b_15[25:24],log_b_15[27:26],log_b_15[21:20],log_b_15[23
- :22],log_b_15[17:16],log_b_15[19:18],log_c_lo_6}; // @[Cat.scala 31:58]
- wire [31:0] log_c_12 = ~log_b_14[1] ? log_b_15 : _log_c_T_98; // @[VAluInt.scala 1122:22]
- wire _log_d_T_65 = ~log_b_14[2]; // @[VAluInt.scala 1126:23]
- wire [31:0] _log_d_T_74 = {log_c_12[27:24],log_c_12[31:28],log_c_12[19:16],log_c_12[23:20],log_c_12[11:8],log_c_12[15:
- 12],log_c_12[3:0],log_c_12[7:4]}; // @[Cat.scala 31:58]
- wire [31:0] log_d_12 = ~log_b_14[2] ? log_c_12 : _log_d_T_74; // @[VAluInt.scala 1126:22]
- wire _log_e_T_21 = ~log_b_14[3]; // @[VAluInt.scala 1128:23]
- wire [31:0] _log_e_T_26 = {log_d_12[23:16],log_d_12[31:24],log_d_12[7:0],log_d_12[15:8]}; // @[Cat.scala 31:58]
- wire [31:0] log_e_4 = ~log_b_14[3] ? log_d_12 : _log_e_T_26; // @[VAluInt.scala 1128:22]
- wire _log_f_T_1 = ~log_b_14[4]; // @[VAluInt.scala 1129:23]
- wire [31:0] _log_f_T_4 = {log_e_4[15:0],log_e_4[31:16]}; // @[Cat.scala 31:58]
- wire [31:0] log_f = ~log_b_14[4] ? log_e_4 : _log_f_T_4; // @[VAluInt.scala 1129:22]
- wire [31:0] _log_T_800 = io_op_log_rev ? log_f : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _log_T_801 = _log_T_797 | _log_T_800; // @[VAluInt.scala 1374:65]
- wire [31:0] _log_b_T_151 = {log_a_2[0],log_a_2[31:1]}; // @[Cat.scala 31:58]
- wire [31:0] log_b_16 = _log_b_T_113 ? log_a_2 : _log_b_T_151; // @[VAluInt.scala 1164:22]
- wire [31:0] _log_c_T_103 = {log_b_16[1:0],log_b_16[31:2]}; // @[Cat.scala 31:58]
- wire [31:0] log_c_13 = _log_c_T_81 ? log_b_16 : _log_c_T_103; // @[VAluInt.scala 1165:22]
- wire [31:0] _log_d_T_79 = {log_c_13[3:0],log_c_13[31:4]}; // @[Cat.scala 31:58]
- wire [31:0] log_d_13 = _log_d_T_65 ? log_c_13 : _log_d_T_79; // @[VAluInt.scala 1166:22]
- wire [31:0] _log_e_T_31 = {log_d_13[7:0],log_d_13[31:8]}; // @[Cat.scala 31:58]
- wire [31:0] log_e_5 = _log_e_T_21 ? log_d_13 : _log_e_T_31; // @[VAluInt.scala 1167:22]
- wire [31:0] _log_f_T_9 = {log_e_5[15:0],log_e_5[31:16]}; // @[Cat.scala 31:58]
- wire [31:0] log_f_1 = _log_f_T_1 ? log_e_5 : _log_f_T_9; // @[VAluInt.scala 1168:22]
- wire [31:0] _log_T_805 = io_in_sz[2] ? log_f_1 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _log_T_806 = io_op_log_ror ? _log_T_805 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _log_T_807 = _log_T_801 | _log_T_806; // @[VAluInt.scala 1375:60]
- wire [31:0] _GEN_202 = {{16'd0}, _log_T_794[31:16]}; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clo_T_338 = _GEN_202 & 32'hffff; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clo_T_340 = {_log_T_794[15:0], 16'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _log_clo_T_342 = _log_clo_T_340 & 32'hffff0000; // @[Bitwise.scala 105:80]
- wire [31:0] _log_clo_T_343 = _log_clo_T_338 | _log_clo_T_342; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_203 = {{8'd0}, _log_clo_T_343[31:8]}; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clo_T_348 = _GEN_203 & 32'hff00ff; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clo_T_350 = {_log_clo_T_343[23:0], 8'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _log_clo_T_352 = _log_clo_T_350 & 32'hff00ff00; // @[Bitwise.scala 105:80]
- wire [31:0] _log_clo_T_353 = _log_clo_T_348 | _log_clo_T_352; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_204 = {{4'd0}, _log_clo_T_353[31:4]}; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clo_T_358 = _GEN_204 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clo_T_360 = {_log_clo_T_353[27:0], 4'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _log_clo_T_362 = _log_clo_T_360 & 32'hf0f0f0f0; // @[Bitwise.scala 105:80]
- wire [31:0] _log_clo_T_363 = _log_clo_T_358 | _log_clo_T_362; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_205 = {{2'd0}, _log_clo_T_363[31:2]}; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clo_T_368 = _GEN_205 & 32'h33333333; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clo_T_370 = {_log_clo_T_363[29:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _log_clo_T_372 = _log_clo_T_370 & 32'hcccccccc; // @[Bitwise.scala 105:80]
- wire [31:0] _log_clo_T_373 = _log_clo_T_368 | _log_clo_T_372; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_206 = {{1'd0}, _log_clo_T_373[31:1]}; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clo_T_378 = _GEN_206 & 32'h55555555; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clo_T_380 = {_log_clo_T_373[30:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _log_clo_T_382 = _log_clo_T_380 & 32'haaaaaaaa; // @[Bitwise.scala 105:80]
- wire [31:0] _log_clo_T_383 = _log_clo_T_378 | _log_clo_T_382; // @[Bitwise.scala 105:39]
- wire [32:0] _log_clo_T_384 = {1'h1,_log_clo_T_383}; // @[Cat.scala 31:58]
- wire [5:0] _log_clo_T_418 = _log_clo_T_384[31] ? 6'h1f : 6'h20; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_419 = _log_clo_T_384[30] ? 6'h1e : _log_clo_T_418; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_420 = _log_clo_T_384[29] ? 6'h1d : _log_clo_T_419; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_421 = _log_clo_T_384[28] ? 6'h1c : _log_clo_T_420; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_422 = _log_clo_T_384[27] ? 6'h1b : _log_clo_T_421; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_423 = _log_clo_T_384[26] ? 6'h1a : _log_clo_T_422; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_424 = _log_clo_T_384[25] ? 6'h19 : _log_clo_T_423; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_425 = _log_clo_T_384[24] ? 6'h18 : _log_clo_T_424; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_426 = _log_clo_T_384[23] ? 6'h17 : _log_clo_T_425; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_427 = _log_clo_T_384[22] ? 6'h16 : _log_clo_T_426; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_428 = _log_clo_T_384[21] ? 6'h15 : _log_clo_T_427; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_429 = _log_clo_T_384[20] ? 6'h14 : _log_clo_T_428; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_430 = _log_clo_T_384[19] ? 6'h13 : _log_clo_T_429; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_431 = _log_clo_T_384[18] ? 6'h12 : _log_clo_T_430; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_432 = _log_clo_T_384[17] ? 6'h11 : _log_clo_T_431; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_433 = _log_clo_T_384[16] ? 6'h10 : _log_clo_T_432; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_434 = _log_clo_T_384[15] ? 6'hf : _log_clo_T_433; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_435 = _log_clo_T_384[14] ? 6'he : _log_clo_T_434; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_436 = _log_clo_T_384[13] ? 6'hd : _log_clo_T_435; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_437 = _log_clo_T_384[12] ? 6'hc : _log_clo_T_436; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_438 = _log_clo_T_384[11] ? 6'hb : _log_clo_T_437; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_439 = _log_clo_T_384[10] ? 6'ha : _log_clo_T_438; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_440 = _log_clo_T_384[9] ? 6'h9 : _log_clo_T_439; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_441 = _log_clo_T_384[8] ? 6'h8 : _log_clo_T_440; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_442 = _log_clo_T_384[7] ? 6'h7 : _log_clo_T_441; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_443 = _log_clo_T_384[6] ? 6'h6 : _log_clo_T_442; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_444 = _log_clo_T_384[5] ? 6'h5 : _log_clo_T_443; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_445 = _log_clo_T_384[4] ? 6'h4 : _log_clo_T_444; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_446 = _log_clo_T_384[3] ? 6'h3 : _log_clo_T_445; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_447 = _log_clo_T_384[2] ? 6'h2 : _log_clo_T_446; // @[Mux.scala 47:70]
- wire [5:0] _log_clo_T_448 = _log_clo_T_384[1] ? 6'h1 : _log_clo_T_447; // @[Mux.scala 47:70]
- wire [5:0] log_clo_6 = _log_clo_T_384[0] ? 6'h0 : _log_clo_T_448; // @[Mux.scala 47:70]
- wire [31:0] _GEN_207 = {{16'd0}, log_a_2[31:16]}; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clz_T_331 = _GEN_207 & 32'hffff; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clz_T_333 = {log_a_2[15:0], 16'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _log_clz_T_335 = _log_clz_T_333 & 32'hffff0000; // @[Bitwise.scala 105:80]
- wire [31:0] _log_clz_T_336 = _log_clz_T_331 | _log_clz_T_335; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_208 = {{8'd0}, _log_clz_T_336[31:8]}; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clz_T_341 = _GEN_208 & 32'hff00ff; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clz_T_343 = {_log_clz_T_336[23:0], 8'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _log_clz_T_345 = _log_clz_T_343 & 32'hff00ff00; // @[Bitwise.scala 105:80]
- wire [31:0] _log_clz_T_346 = _log_clz_T_341 | _log_clz_T_345; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_209 = {{4'd0}, _log_clz_T_346[31:4]}; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clz_T_351 = _GEN_209 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clz_T_353 = {_log_clz_T_346[27:0], 4'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _log_clz_T_355 = _log_clz_T_353 & 32'hf0f0f0f0; // @[Bitwise.scala 105:80]
- wire [31:0] _log_clz_T_356 = _log_clz_T_351 | _log_clz_T_355; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_210 = {{2'd0}, _log_clz_T_356[31:2]}; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clz_T_361 = _GEN_210 & 32'h33333333; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clz_T_363 = {_log_clz_T_356[29:0], 2'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _log_clz_T_365 = _log_clz_T_363 & 32'hcccccccc; // @[Bitwise.scala 105:80]
- wire [31:0] _log_clz_T_366 = _log_clz_T_361 | _log_clz_T_365; // @[Bitwise.scala 105:39]
- wire [31:0] _GEN_211 = {{1'd0}, _log_clz_T_366[31:1]}; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clz_T_371 = _GEN_211 & 32'h55555555; // @[Bitwise.scala 105:31]
- wire [31:0] _log_clz_T_373 = {_log_clz_T_366[30:0], 1'h0}; // @[Bitwise.scala 105:70]
- wire [31:0] _log_clz_T_375 = _log_clz_T_373 & 32'haaaaaaaa; // @[Bitwise.scala 105:80]
- wire [31:0] _log_clz_T_376 = _log_clz_T_371 | _log_clz_T_375; // @[Bitwise.scala 105:39]
- wire [32:0] _log_clz_T_377 = {1'h1,_log_clz_T_376}; // @[Cat.scala 31:58]
- wire [5:0] _log_clz_T_411 = _log_clz_T_377[31] ? 6'h1f : 6'h20; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_412 = _log_clz_T_377[30] ? 6'h1e : _log_clz_T_411; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_413 = _log_clz_T_377[29] ? 6'h1d : _log_clz_T_412; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_414 = _log_clz_T_377[28] ? 6'h1c : _log_clz_T_413; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_415 = _log_clz_T_377[27] ? 6'h1b : _log_clz_T_414; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_416 = _log_clz_T_377[26] ? 6'h1a : _log_clz_T_415; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_417 = _log_clz_T_377[25] ? 6'h19 : _log_clz_T_416; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_418 = _log_clz_T_377[24] ? 6'h18 : _log_clz_T_417; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_419 = _log_clz_T_377[23] ? 6'h17 : _log_clz_T_418; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_420 = _log_clz_T_377[22] ? 6'h16 : _log_clz_T_419; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_421 = _log_clz_T_377[21] ? 6'h15 : _log_clz_T_420; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_422 = _log_clz_T_377[20] ? 6'h14 : _log_clz_T_421; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_423 = _log_clz_T_377[19] ? 6'h13 : _log_clz_T_422; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_424 = _log_clz_T_377[18] ? 6'h12 : _log_clz_T_423; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_425 = _log_clz_T_377[17] ? 6'h11 : _log_clz_T_424; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_426 = _log_clz_T_377[16] ? 6'h10 : _log_clz_T_425; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_427 = _log_clz_T_377[15] ? 6'hf : _log_clz_T_426; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_428 = _log_clz_T_377[14] ? 6'he : _log_clz_T_427; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_429 = _log_clz_T_377[13] ? 6'hd : _log_clz_T_428; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_430 = _log_clz_T_377[12] ? 6'hc : _log_clz_T_429; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_431 = _log_clz_T_377[11] ? 6'hb : _log_clz_T_430; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_432 = _log_clz_T_377[10] ? 6'ha : _log_clz_T_431; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_433 = _log_clz_T_377[9] ? 6'h9 : _log_clz_T_432; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_434 = _log_clz_T_377[8] ? 6'h8 : _log_clz_T_433; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_435 = _log_clz_T_377[7] ? 6'h7 : _log_clz_T_434; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_436 = _log_clz_T_377[6] ? 6'h6 : _log_clz_T_435; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_437 = _log_clz_T_377[5] ? 6'h5 : _log_clz_T_436; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_438 = _log_clz_T_377[4] ? 6'h4 : _log_clz_T_437; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_439 = _log_clz_T_377[3] ? 6'h3 : _log_clz_T_438; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_440 = _log_clz_T_377[2] ? 6'h2 : _log_clz_T_439; // @[Mux.scala 47:70]
- wire [5:0] _log_clz_T_441 = _log_clz_T_377[1] ? 6'h1 : _log_clz_T_440; // @[Mux.scala 47:70]
- wire [5:0] log_clz_6 = _log_clz_T_377[0] ? 6'h0 : _log_clz_T_441; // @[Mux.scala 47:70]
- wire [5:0] _log_T_811 = log_a_2[31] ? log_clo_6 : log_clz_6; // @[Library.scala 289:8]
- wire [5:0] _log_T_812 = io_in_sz[2] ? _log_T_811 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _log_T_813 = io_op_log_clb ? _log_T_812 : 6'h0; // @[Library.scala 32:8]
- wire [31:0] _GEN_212 = {{26'd0}, _log_T_813}; // @[VAluInt.scala 1376:81]
- wire [31:0] _log_T_814 = _log_T_807 | _GEN_212; // @[VAluInt.scala 1376:81]
- wire [5:0] _log_T_932 = io_in_sz[2] ? log_clz_6 : 6'h0; // @[Library.scala 32:8]
- wire [5:0] _log_T_933 = io_op_log_clz ? _log_T_932 : 6'h0; // @[Library.scala 32:8]
- wire [31:0] _GEN_218 = {{26'd0}, _log_T_933}; // @[VAluInt.scala 1377:69]
- wire [31:0] _log_T_934 = _log_T_814 | _GEN_218; // @[VAluInt.scala 1377:69]
- wire [1:0] _log_T_968 = log_a_2[0] + log_a_2[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_970 = log_a_2[2] + log_a_2[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_972 = _log_T_968 + _log_T_970; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_974 = log_a_2[4] + log_a_2[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_976 = log_a_2[6] + log_a_2[7]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_978 = _log_T_974 + _log_T_976; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_980 = _log_T_972 + _log_T_978; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_982 = log_a_2[8] + log_a_2[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_984 = log_a_2[10] + log_a_2[11]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_986 = _log_T_982 + _log_T_984; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_988 = log_a_2[12] + log_a_2[13]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_990 = log_a_2[14] + log_a_2[15]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_992 = _log_T_988 + _log_T_990; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_994 = _log_T_986 + _log_T_992; // @[Bitwise.scala 48:55]
- wire [4:0] _log_T_996 = _log_T_980 + _log_T_994; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_998 = log_a_2[16] + log_a_2[17]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_1000 = log_a_2[18] + log_a_2[19]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_1002 = _log_T_998 + _log_T_1000; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_1004 = log_a_2[20] + log_a_2[21]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_1006 = log_a_2[22] + log_a_2[23]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_1008 = _log_T_1004 + _log_T_1006; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_1010 = _log_T_1002 + _log_T_1008; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_1012 = log_a_2[24] + log_a_2[25]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_1014 = log_a_2[26] + log_a_2[27]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_1016 = _log_T_1012 + _log_T_1014; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_1018 = log_a_2[28] + log_a_2[29]; // @[Bitwise.scala 48:55]
- wire [1:0] _log_T_1020 = log_a_2[30] + log_a_2[31]; // @[Bitwise.scala 48:55]
- wire [2:0] _log_T_1022 = _log_T_1018 + _log_T_1020; // @[Bitwise.scala 48:55]
- wire [3:0] _log_T_1024 = _log_T_1016 + _log_T_1022; // @[Bitwise.scala 48:55]
- wire [4:0] _log_T_1026 = _log_T_1010 + _log_T_1024; // @[Bitwise.scala 48:55]
- wire [5:0] _log_T_1028 = _log_T_996 + _log_T_1026; // @[Bitwise.scala 48:55]
- wire [5:0] _log_T_1030 = io_op_log_cpop ? _log_T_1028 : 6'h0; // @[Library.scala 32:8]
- wire [31:0] _GEN_219 = {{26'd0}, _log_T_1030}; // @[VAluInt.scala 1378:69]
- wire [31:0] log_6 = _log_T_934 | _GEN_219; // @[VAluInt.scala 1378:69]
- wire [31:0] _shift_T_24 = io_op_shf_shl ? shl_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _shift_T_25 = io_op_shf_shr ? shr_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _shift_T_26 = _shift_T_24 | _shift_T_25; // @[VAluInt.scala 1383:35]
- wire [31:0] _shift_T_27 = io_op_shf_shf ? shf_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] shift_6 = _shift_T_26 | _shift_T_27; // @[VAluInt.scala 1384:35]
- wire _alu_oh_T_84 = absd_6 != 32'h0; // @[VAluInt.scala 1388:30]
- wire _alu_oh_T_85 = add_6 != 32'h0; // @[VAluInt.scala 1389:30]
- wire _alu_oh_T_87 = dup_6 != 32'h0; // @[VAluInt.scala 1391:30]
- wire _alu_oh_T_88 = log_6 != 32'h0; // @[VAluInt.scala 1392:30]
- wire _alu_oh_T_89 = max_6 != 32'h0; // @[VAluInt.scala 1393:30]
- wire _alu_oh_T_90 = min_6 != 32'h0; // @[VAluInt.scala 1394:30]
- wire _alu_oh_T_91 = mul0_6 != 32'h0; // @[VAluInt.scala 1395:30]
- wire _alu_oh_T_92 = padd_2 != 32'h0; // @[VAluInt.scala 1396:30]
- wire _alu_oh_T_93 = rsub_6 != 32'h0; // @[VAluInt.scala 1397:30]
- wire _alu_oh_T_94 = shift_6 != 32'h0; // @[VAluInt.scala 1398:30]
- wire _alu_oh_T_97 = sub_6 != 32'h0; // @[VAluInt.scala 1401:30]
- wire [6:0] alu_oh_lo_6 = {_alu_oh_T_91,_alu_oh_T_92,_alu_oh_T_93,_alu_oh_T_94,2'h0,_alu_oh_T_97}; // @[Cat.scala 31:58]
- wire [13:0] alu_oh_6 = {_alu_oh_T_84,_alu_oh_T_85,cmp_6,_alu_oh_T_87,_alu_oh_T_88,_alu_oh_T_89,_alu_oh_T_90,
- alu_oh_lo_6}; // @[Cat.scala 31:58]
- wire [1:0] _T_642 = alu_oh_6[1] + alu_oh_6[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_220 = {{1'd0}, alu_oh_6[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_644 = _GEN_220 + _T_642; // @[Bitwise.scala 48:55]
- wire [1:0] _T_646 = alu_oh_6[3] + alu_oh_6[4]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_648 = alu_oh_6[5] + alu_oh_6[6]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_650 = _T_646 + _T_648; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_221 = {{1'd0}, _T_644[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_652 = _GEN_221 + _T_650; // @[Bitwise.scala 48:55]
- wire [1:0] _T_654 = alu_oh_6[8] + alu_oh_6[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_222 = {{1'd0}, alu_oh_6[7]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_656 = _GEN_222 + _T_654; // @[Bitwise.scala 48:55]
- wire [1:0] _T_658 = alu_oh_6[10] + alu_oh_6[11]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_660 = alu_oh_6[12] + alu_oh_6[13]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_662 = _T_658 + _T_660; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_223 = {{1'd0}, _T_656[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_664 = _GEN_223 + _T_662; // @[Bitwise.scala 48:55]
- wire [3:0] _T_666 = _T_652[2:0] + _T_664[2:0]; // @[Bitwise.scala 48:55]
- wire [31:0] _alu0_0_T_32 = mul0_6 | absd_6; // @[VAluInt.scala 1405:23]
- wire [31:0] _alu0_0_T_33 = _alu0_0_T_32 | add_6; // @[VAluInt.scala 1405:30]
- wire [31:0] _GEN_224 = {{31'd0}, cmp_6}; // @[VAluInt.scala 1405:36]
- wire [31:0] _alu0_0_T_34 = _alu0_0_T_33 | _GEN_224; // @[VAluInt.scala 1405:36]
- wire [31:0] _alu0_0_T_35 = _alu0_0_T_34 | dup_6; // @[VAluInt.scala 1405:42]
- wire [31:0] _alu0_0_T_36 = _alu0_0_T_35 | log_6; // @[VAluInt.scala 1405:48]
- wire [31:0] _alu0_0_T_37 = _alu0_0_T_36 | max_6; // @[VAluInt.scala 1405:54]
- wire [31:0] _alu0_0_T_38 = _alu0_0_T_37 | min_6; // @[VAluInt.scala 1405:60]
- wire [31:0] _alu0_0_T_39 = _alu0_0_T_38 | padd_2; // @[VAluInt.scala 1405:66]
- wire [31:0] _alu0_0_T_40 = _alu0_0_T_39 | rsub_6; // @[VAluInt.scala 1405:73]
- wire [31:0] _alu0_0_T_41 = _alu0_0_T_40 | shift_6; // @[VAluInt.scala 1405:80]
- wire [31:0] _alu0_0_T_44 = _alu0_0_T_41 | sub_6; // @[VAluInt.scala 1405:104]
- wire [31:0] _alu0_0_T_46 = io_op_mv ? ina_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] alu0_2_0 = _alu0_0_T_44 | _alu0_0_T_46; // @[VAluInt.scala 1405:110]
- wire [31:0] _alu1_0_T_13 = io_op_mvp ? inb_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _alu1_0_T_14 = mul1_6 | _alu1_0_T_13; // @[VAluInt.scala 1408:23]
- wire [31:0] _alu1_0_T_16 = io_op_mv2 ? inc_w : 32'h0; // @[Library.scala 32:8]
- wire [31:0] alu1_2_0 = _alu1_0_T_14 | _alu1_0_T_16; // @[VAluInt.scala 1409:44]
- wire [31:0] _GEN_225 = {{31'd0}, mulh0_rnd_6}; // @[VAluInt.scala 1412:29]
- wire [31:0] _rnd0_0_T_4 = dmulh0_rnd_6 | _GEN_225; // @[VAluInt.scala 1412:29]
- wire [31:0] _GEN_226 = {{31'd0}, shf_rnd_6}; // @[VAluInt.scala 1412:41]
- wire [31:0] rnd0_2_0 = _rnd0_0_T_4 | _GEN_226; // @[VAluInt.scala 1412:41]
- wire [31:0] _GEN_227 = {{31'd0}, mulh1_rnd_6}; // @[VAluInt.scala 1413:29]
- wire [31:0] rnd1_2_0 = dmulh1_rnd_6 | _GEN_227; // @[VAluInt.scala 1413:29]
- wire [31:0] _out0_T = outb0 | outh0; // @[VAluInt.scala 1468:20]
- wire [31:0] _out0_T_1 = _out0_T | alu0_2_0; // @[VAluInt.scala 1468:28]
- wire [31:0] _out0_T_2 = _out0_T_1 | outwb0; // @[VAluInt.scala 1468:36]
- wire [31:0] out0 = _out0_T_2 | aluw0_1_0; // @[VAluInt.scala 1468:45]
- wire [31:0] _out1_T = outb1 | outh1; // @[VAluInt.scala 1469:20]
- wire [31:0] _out1_T_1 = _out1_T | alu1_2_0; // @[VAluInt.scala 1469:28]
- wire [31:0] _out1_T_2 = _out1_T_1 | outwb1; // @[VAluInt.scala 1469:36]
- wire [31:0] out1 = _out1_T_2 | aluw1_1_0; // @[VAluInt.scala 1469:45]
- wire [31:0] _rnd0_T = rndb0 | rndh0; // @[VAluInt.scala 1470:20]
- wire [31:0] rnd0_3 = _rnd0_T | rnd0_2_0; // @[VAluInt.scala 1470:28]
- wire [31:0] _rnd1_T = rndb1 | rndh1; // @[VAluInt.scala 1471:20]
- wire [31:0] rnd1_3 = _rnd1_T | rnd1_2_0; // @[VAluInt.scala 1471:28]
- wire accvalid0 = io_op_dwinit | io_op_mul0_dmulh | io_op_mul0_mulh | io_op_add_add3 | io_op_mul0_madd | io_op_shf_shf
- ; // @[VAluInt.scala 1475:108]
- wire accvalid1 = io_op_dwinit | io_op_mul1_dmulh | io_op_mul1_mulh; // @[VAluInt.scala 1476:52]
- wire _accum0_T = io_op_add_add3 | io_op_mul0_madd; // @[VAluInt.scala 1478:37]
- wire [31:0] _accum0_T_1 = _accum0_T ? io_read_2_data : 32'h0; // @[Library.scala 32:8]
- wire _accum0_T_2 = io_op_mul0_dmulh | io_op_mul0_mulh; // @[VAluInt.scala 1480:39]
- wire _accum0_T_3 = _accum0_T_2 | io_op_shf_shf; // @[VAluInt.scala 1481:38]
- wire [31:0] _accum0_T_4 = _accum0_T_3 ? rnd0_3 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _accum0_T_5 = _accum0_T_1 | _accum0_T_4; // @[VAluInt.scala 1479:56]
- wire [31:0] _accum0_T_6 = io_op_dwinit ? io_read_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] accum0 = _accum0_T_5 | _accum0_T_6; // @[VAluInt.scala 1482:43]
- wire _accum1_T = io_op_mul1_dmulh | io_op_mul1_mulh; // @[VAluInt.scala 1485:39]
- wire [31:0] _accum1_T_1 = _accum1_T ? rnd1_3 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _accum1_T_2 = io_op_dwinit ? io_read_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] accum1 = _accum1_T_1 | _accum1_T_2; // @[VAluInt.scala 1486:45]
- reg [2:0] wsz; // @[VAluInt.scala 1491:20]
- reg waccvalid0; // @[VAluInt.scala 1492:27]
- reg waccvalid1; // @[VAluInt.scala 1493:27]
- reg [31:0] wdata0; // @[VAluInt.scala 1494:19]
- reg [31:0] waccm0; // @[VAluInt.scala 1495:19]
- reg [31:0] wdata1; // @[VAluInt.scala 1496:19]
- reg [31:0] waccm1; // @[VAluInt.scala 1497:19]
- wire _wsz_T = io_in_vdvalid | io_in_vevalid; // @[VAluInt.scala 1499:30]
- wire [31:0] _wdata0_T = out0 | io_load_0; // @[VAluInt.scala 1504:20]
- wire [31:0] _wdata1_T = out1 | io_load_1; // @[VAluInt.scala 1514:20]
- wire [31:0] io_write_0_data_dm = waccvalid0 ? wdata0 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] io_write_0_data_am = waccvalid0 ? waccm0 : 32'h0; // @[Library.scala 32:8]
- wire _io_write_0_data_rm_T_1 = waccvalid0 & wsz[0]; // @[VAluInt.scala 1526:23]
- wire [7:0] _io_write_0_data_rm_T_5 = io_write_0_data_dm[31:24] + io_write_0_data_am[31:24]; // @[VAluInt.scala 1526:48]
- wire [7:0] _io_write_0_data_rm_T_9 = io_write_0_data_dm[23:16] + io_write_0_data_am[23:16]; // @[VAluInt.scala 1527:48]
- wire [7:0] _io_write_0_data_rm_T_13 = io_write_0_data_dm[15:8] + io_write_0_data_am[15:8]; // @[VAluInt.scala 1528:48]
- wire [7:0] _io_write_0_data_rm_T_17 = io_write_0_data_dm[7:0] + io_write_0_data_am[7:0]; // @[VAluInt.scala 1529:48]
- wire [31:0] _io_write_0_data_rm_T_18 = {_io_write_0_data_rm_T_5,_io_write_0_data_rm_T_9,_io_write_0_data_rm_T_13,
- _io_write_0_data_rm_T_17}; // @[Cat.scala 31:58]
- wire [31:0] _io_write_0_data_rm_T_19 = _io_write_0_data_rm_T_1 ? _io_write_0_data_rm_T_18 : 32'h0; // @[Library.scala 32:8]
- wire _io_write_0_data_rm_T_21 = waccvalid0 & wsz[1]; // @[VAluInt.scala 1530:23]
- wire [15:0] _io_write_0_data_rm_T_25 = io_write_0_data_dm[31:16] + io_write_0_data_am[31:16]; // @[VAluInt.scala 1530:48]
- wire [15:0] _io_write_0_data_rm_T_29 = io_write_0_data_dm[15:0] + io_write_0_data_am[15:0]; // @[VAluInt.scala 1531:48]
- wire [31:0] _io_write_0_data_rm_T_30 = {_io_write_0_data_rm_T_25,_io_write_0_data_rm_T_29}; // @[Cat.scala 31:58]
- wire [31:0] _io_write_0_data_rm_T_31 = _io_write_0_data_rm_T_21 ? _io_write_0_data_rm_T_30 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _io_write_0_data_rm_T_32 = _io_write_0_data_rm_T_19 | _io_write_0_data_rm_T_31; // @[VAluInt.scala 1529:62]
- wire _io_write_0_data_rm_T_34 = waccvalid0 & wsz[2]; // @[VAluInt.scala 1532:23]
- wire [31:0] _io_write_0_data_rm_T_38 = io_write_0_data_dm + io_write_0_data_am; // @[VAluInt.scala 1532:44]
- wire [31:0] _io_write_0_data_rm_T_39 = _io_write_0_data_rm_T_34 ? _io_write_0_data_rm_T_38 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] io_write_0_data_rm = _io_write_0_data_rm_T_32 | _io_write_0_data_rm_T_39; // @[VAluInt.scala 1531:62]
- wire _io_write_0_data_rn_T = ~waccvalid0; // @[VAluInt.scala 1533:20]
- wire [31:0] io_write_0_data_rn = _io_write_0_data_rn_T ? wdata0 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] io_write_1_data_dm = waccvalid1 ? wdata1 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] io_write_1_data_am = waccvalid1 ? waccm1 : 32'h0; // @[Library.scala 32:8]
- wire _io_write_1_data_rm_T_1 = waccvalid1 & wsz[0]; // @[VAluInt.scala 1526:23]
- wire [7:0] _io_write_1_data_rm_T_5 = io_write_1_data_dm[31:24] + io_write_1_data_am[31:24]; // @[VAluInt.scala 1526:48]
- wire [7:0] _io_write_1_data_rm_T_9 = io_write_1_data_dm[23:16] + io_write_1_data_am[23:16]; // @[VAluInt.scala 1527:48]
- wire [7:0] _io_write_1_data_rm_T_13 = io_write_1_data_dm[15:8] + io_write_1_data_am[15:8]; // @[VAluInt.scala 1528:48]
- wire [7:0] _io_write_1_data_rm_T_17 = io_write_1_data_dm[7:0] + io_write_1_data_am[7:0]; // @[VAluInt.scala 1529:48]
- wire [31:0] _io_write_1_data_rm_T_18 = {_io_write_1_data_rm_T_5,_io_write_1_data_rm_T_9,_io_write_1_data_rm_T_13,
- _io_write_1_data_rm_T_17}; // @[Cat.scala 31:58]
- wire [31:0] _io_write_1_data_rm_T_19 = _io_write_1_data_rm_T_1 ? _io_write_1_data_rm_T_18 : 32'h0; // @[Library.scala 32:8]
- wire _io_write_1_data_rm_T_21 = waccvalid1 & wsz[1]; // @[VAluInt.scala 1530:23]
- wire [15:0] _io_write_1_data_rm_T_25 = io_write_1_data_dm[31:16] + io_write_1_data_am[31:16]; // @[VAluInt.scala 1530:48]
- wire [15:0] _io_write_1_data_rm_T_29 = io_write_1_data_dm[15:0] + io_write_1_data_am[15:0]; // @[VAluInt.scala 1531:48]
- wire [31:0] _io_write_1_data_rm_T_30 = {_io_write_1_data_rm_T_25,_io_write_1_data_rm_T_29}; // @[Cat.scala 31:58]
- wire [31:0] _io_write_1_data_rm_T_31 = _io_write_1_data_rm_T_21 ? _io_write_1_data_rm_T_30 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _io_write_1_data_rm_T_32 = _io_write_1_data_rm_T_19 | _io_write_1_data_rm_T_31; // @[VAluInt.scala 1529:62]
- wire _io_write_1_data_rm_T_34 = waccvalid1 & wsz[2]; // @[VAluInt.scala 1532:23]
- wire [31:0] _io_write_1_data_rm_T_38 = io_write_1_data_dm + io_write_1_data_am; // @[VAluInt.scala 1532:44]
- wire [31:0] _io_write_1_data_rm_T_39 = _io_write_1_data_rm_T_34 ? _io_write_1_data_rm_T_38 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] io_write_1_data_rm = _io_write_1_data_rm_T_32 | _io_write_1_data_rm_T_39; // @[VAluInt.scala 1531:62]
- wire _io_write_1_data_rn_T = ~waccvalid1; // @[VAluInt.scala 1533:20]
- wire [31:0] io_write_1_data_rn = _io_write_1_data_rn_T ? wdata1 : 32'h0; // @[Library.scala 32:8]
- assign io_write_0_data = io_write_0_data_rm | io_write_0_data_rn; // @[VAluInt.scala 1536:8]
- assign io_write_1_data = io_write_1_data_rm | io_write_1_data_rn; // @[VAluInt.scala 1536:8]
- always @(posedge clock) begin
- if (io_in_vdvalid) begin // @[VAluInt.scala 1503:24]
- wdata0 <= _wdata0_T; // @[VAluInt.scala 1504:12]
- end
- if (accvalid0) begin // @[VAluInt.scala 1507:20]
- waccm0 <= accum0; // @[VAluInt.scala 1508:12]
- end else if (io_op_dwconvData) begin // @[VAluInt.scala 1509:34]
- waccm0 <= io_write_0_data; // @[VAluInt.scala 1510:12]
- end
- if (io_in_vevalid) begin // @[VAluInt.scala 1513:24]
- wdata1 <= _wdata1_T; // @[VAluInt.scala 1514:12]
- end
- if (accvalid1) begin // @[VAluInt.scala 1517:20]
- waccm1 <= accum1; // @[VAluInt.scala 1518:12]
- end else if (io_op_dwconvData) begin // @[VAluInt.scala 1519:34]
- waccm1 <= io_write_1_data; // @[VAluInt.scala 1520:12]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 981:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:981 assert(PopCount(sataddsel) <= 1.U)\n"); // @[VAluInt.scala 981:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_16[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 991:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_16[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:991 assert(PopCount(satsubsel) <= 1.U)\n"); // @[VAluInt.scala 991:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat & shf_negsat))) begin
- $fatal; // @[VAluInt.scala 1022:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat & shf_negsat))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1022 assert(!(possat && negsat))\n"); // @[VAluInt.scala 1022:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_31 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1217:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_31 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1217 assert(PopCount(Cat(muls0_umax, muls0_smax, muls0_smin, muls0_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1217:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_46 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1223:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_46 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1223 assert(PopCount(Cat(muls1_umax, muls1_smax, muls1_smin, muls1_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1223:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_srans_T_11 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1106:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_srans_T_11 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1106 assert(PopCount(Cat(is_umax, is_smax, is_smin, is_norm)) <= 1.U)\n"
- ); // @[VAluInt.scala 1106:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_sraqs_T_11 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1106:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_sraqs_T_11 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1106 assert(PopCount(Cat(is_umax, is_smax, is_smin, is_norm)) <= 1.U)\n"
- ); // @[VAluInt.scala 1106:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_90 <= 4'h1)) begin
- $fatal; // @[VAluInt.scala 1403:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_90 <= 4'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1403 assert(PopCount(alu_oh) <= 1.U)\n"); // @[VAluInt.scala 1403:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_101[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 981:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_101[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:981 assert(PopCount(sataddsel) <= 1.U)\n"); // @[VAluInt.scala 981:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_112[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 991:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_112[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:991 assert(PopCount(satsubsel) <= 1.U)\n"); // @[VAluInt.scala 991:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat_2 & shf_negsat_1))) begin
- $fatal; // @[VAluInt.scala 1022:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat_2 & shf_negsat_1))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1022 assert(!(possat && negsat))\n"); // @[VAluInt.scala 1022:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_127 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1217:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_127 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1217 assert(PopCount(Cat(muls0_umax, muls0_smax, muls0_smin, muls0_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1217:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_142 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1223:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_142 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1223 assert(PopCount(Cat(muls1_umax, muls1_smax, muls1_smin, muls1_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1223:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_srans_T_28 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1106:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_srans_T_28 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1106 assert(PopCount(Cat(is_umax, is_smax, is_smin, is_norm)) <= 1.U)\n"
- ); // @[VAluInt.scala 1106:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_sraqs_T_28 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1106:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_sraqs_T_28 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1106 assert(PopCount(Cat(is_umax, is_smax, is_smin, is_norm)) <= 1.U)\n"
- ); // @[VAluInt.scala 1106:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_186 <= 4'h1)) begin
- $fatal; // @[VAluInt.scala 1403:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_186 <= 4'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1403 assert(PopCount(alu_oh) <= 1.U)\n"); // @[VAluInt.scala 1403:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_197[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 981:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_197[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:981 assert(PopCount(sataddsel) <= 1.U)\n"); // @[VAluInt.scala 981:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_208[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 991:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_208[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:991 assert(PopCount(satsubsel) <= 1.U)\n"); // @[VAluInt.scala 991:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat_4 & shf_negsat_2))) begin
- $fatal; // @[VAluInt.scala 1022:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat_4 & shf_negsat_2))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1022 assert(!(possat && negsat))\n"); // @[VAluInt.scala 1022:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_223 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1217:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_223 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1217 assert(PopCount(Cat(muls0_umax, muls0_smax, muls0_smin, muls0_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1217:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_238 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1223:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_238 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1223 assert(PopCount(Cat(muls1_umax, muls1_smax, muls1_smin, muls1_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1223:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_srans_T_45 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1106:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_srans_T_45 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1106 assert(PopCount(Cat(is_umax, is_smax, is_smin, is_norm)) <= 1.U)\n"
- ); // @[VAluInt.scala 1106:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_sraqs_T_45 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1106:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_sraqs_T_45 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1106 assert(PopCount(Cat(is_umax, is_smax, is_smin, is_norm)) <= 1.U)\n"
- ); // @[VAluInt.scala 1106:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_282 <= 4'h1)) begin
- $fatal; // @[VAluInt.scala 1403:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_282 <= 4'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1403 assert(PopCount(alu_oh) <= 1.U)\n"); // @[VAluInt.scala 1403:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_293[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 981:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_293[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:981 assert(PopCount(sataddsel) <= 1.U)\n"); // @[VAluInt.scala 981:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_304[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 991:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_304[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:991 assert(PopCount(satsubsel) <= 1.U)\n"); // @[VAluInt.scala 991:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat_6 & shf_negsat_3))) begin
- $fatal; // @[VAluInt.scala 1022:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat_6 & shf_negsat_3))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1022 assert(!(possat && negsat))\n"); // @[VAluInt.scala 1022:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_319 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1217:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_319 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1217 assert(PopCount(Cat(muls0_umax, muls0_smax, muls0_smin, muls0_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1217:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_334 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1223:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_334 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1223 assert(PopCount(Cat(muls1_umax, muls1_smax, muls1_smin, muls1_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1223:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_srans_T_62 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1106:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_srans_T_62 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1106 assert(PopCount(Cat(is_umax, is_smax, is_smin, is_norm)) <= 1.U)\n"
- ); // @[VAluInt.scala 1106:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_sraqs_T_62 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1106:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_sraqs_T_62 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1106 assert(PopCount(Cat(is_umax, is_smax, is_smin, is_norm)) <= 1.U)\n"
- ); // @[VAluInt.scala 1106:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_378 <= 4'h1)) begin
- $fatal; // @[VAluInt.scala 1403:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_378 <= 4'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1403 assert(PopCount(alu_oh) <= 1.U)\n"); // @[VAluInt.scala 1403:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_389[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 981:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_389[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:981 assert(PopCount(sataddsel) <= 1.U)\n"); // @[VAluInt.scala 981:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_400[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 991:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_400[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:991 assert(PopCount(satsubsel) <= 1.U)\n"); // @[VAluInt.scala 991:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat_8 & shf_negsat_4))) begin
- $fatal; // @[VAluInt.scala 1022:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat_8 & shf_negsat_4))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1022 assert(!(possat && negsat))\n"); // @[VAluInt.scala 1022:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_415 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1217:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_415 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1217 assert(PopCount(Cat(muls0_umax, muls0_smax, muls0_smin, muls0_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1217:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_430 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1223:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_430 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1223 assert(PopCount(Cat(muls1_umax, muls1_smax, muls1_smin, muls1_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1223:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_srans_T_79 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1106:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_srans_T_79 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1106 assert(PopCount(Cat(is_umax, is_smax, is_smin, is_norm)) <= 1.U)\n"
- ); // @[VAluInt.scala 1106:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_474 <= 4'h1)) begin
- $fatal; // @[VAluInt.scala 1403:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_474 <= 4'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1403 assert(PopCount(alu_oh) <= 1.U)\n"); // @[VAluInt.scala 1403:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_485[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 981:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_485[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:981 assert(PopCount(sataddsel) <= 1.U)\n"); // @[VAluInt.scala 981:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_496[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 991:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_496[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:991 assert(PopCount(satsubsel) <= 1.U)\n"); // @[VAluInt.scala 991:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat_10 & shf_negsat_5))) begin
- $fatal; // @[VAluInt.scala 1022:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat_10 & shf_negsat_5))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1022 assert(!(possat && negsat))\n"); // @[VAluInt.scala 1022:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_511 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1217:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_511 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1217 assert(PopCount(Cat(muls0_umax, muls0_smax, muls0_smin, muls0_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1217:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_526 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1223:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_526 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1223 assert(PopCount(Cat(muls1_umax, muls1_smax, muls1_smin, muls1_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1223:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_srans_T_96 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1106:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_srans_T_96 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1106 assert(PopCount(Cat(is_umax, is_smax, is_smin, is_norm)) <= 1.U)\n"
- ); // @[VAluInt.scala 1106:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_570 <= 4'h1)) begin
- $fatal; // @[VAluInt.scala 1403:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_570 <= 4'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1403 assert(PopCount(alu_oh) <= 1.U)\n"); // @[VAluInt.scala 1403:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_581[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 981:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_581[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:981 assert(PopCount(sataddsel) <= 1.U)\n"); // @[VAluInt.scala 981:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_592[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 991:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_592[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:991 assert(PopCount(satsubsel) <= 1.U)\n"); // @[VAluInt.scala 991:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat_12 & shf_negsat_6))) begin
- $fatal; // @[VAluInt.scala 1022:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(~(shf_possat_12 & shf_negsat_6))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1022 assert(!(possat && negsat))\n"); // @[VAluInt.scala 1022:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_607 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1217:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_607 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1217 assert(PopCount(Cat(muls0_umax, muls0_smax, muls0_smin, muls0_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1217:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_622 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 1223:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_622 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:1223 assert(PopCount(Cat(muls1_umax, muls1_smax, muls1_smin, muls1_base)) <= 1.U)\n"
- ); // @[VAluInt.scala 1223:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(_T_666 <= 4'h1)) begin
- $fatal; // @[VAluInt.scala 1403:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(_T_666 <= 4'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:1403 assert(PopCount(alu_oh) <= 1.U)\n"); // @[VAluInt.scala 1403:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Library.scala 32:8]
- wsz <= 3'h0;
- end else if (_wsz_T) begin
- wsz <= io_in_sz;
- end else begin
- wsz <= 3'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 1500:27]
- waccvalid0 <= 1'h0;
- end else begin
- waccvalid0 <= accvalid0 | io_op_dwconv;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 1501:27]
- waccvalid1 <= 1'h0;
- end else begin
- waccvalid1 <= accvalid1 | io_op_dwconv;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- wsz = _RAND_0[2:0];
- _RAND_1 = {1{`RANDOM}};
- waccvalid0 = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- waccvalid1 = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- wdata0 = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- waccm0 = _RAND_4[31:0];
- _RAND_5 = {1{`RANDOM}};
- wdata1 = _RAND_5[31:0];
- _RAND_6 = {1{`RANDOM}};
- waccm1 = _RAND_6[31:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- wsz = 3'h0;
- end
- if (reset) begin
- waccvalid0 = 1'h0;
- end
- if (reset) begin
- waccvalid1 = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VAluInt(
- input clock,
- input reset,
- input io_in_valid,
- input [6:0] io_in_op,
- input [2:0] io_in_f2,
- input [2:0] io_in_sz,
- input [5:0] io_in_vd_addr,
- input [5:0] io_in_ve_addr,
- input [31:0] io_in_sv_data,
- input [255:0] io_read_0_data,
- input [255:0] io_read_1_data,
- input [255:0] io_read_2_data,
- input [255:0] io_read_3_data,
- input [255:0] io_read_4_data,
- input [255:0] io_read_5_data,
- output io_write_0_valid,
- output [5:0] io_write_0_addr,
- output [255:0] io_write_0_data,
- output io_write_1_valid,
- output [5:0] io_write_1_addr,
- output [255:0] io_write_1_data,
- output io_whint_0_valid,
- output [5:0] io_whint_0_addr,
- output io_whint_1_valid,
- output [5:0] io_whint_1_addr
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
- reg [31:0] _RAND_34;
- reg [31:0] _RAND_35;
- reg [31:0] _RAND_36;
- reg [31:0] _RAND_37;
- reg [31:0] _RAND_38;
- reg [31:0] _RAND_39;
- reg [31:0] _RAND_40;
- reg [31:0] _RAND_41;
- reg [31:0] _RAND_42;
- reg [31:0] _RAND_43;
- reg [31:0] _RAND_44;
- reg [31:0] _RAND_45;
- reg [31:0] _RAND_46;
- reg [31:0] _RAND_47;
- reg [31:0] _RAND_48;
- reg [31:0] _RAND_49;
- reg [31:0] _RAND_50;
- reg [31:0] _RAND_51;
- reg [31:0] _RAND_52;
- reg [31:0] _RAND_53;
- reg [31:0] _RAND_54;
- reg [31:0] _RAND_55;
- reg [31:0] _RAND_56;
- reg [31:0] _RAND_57;
- reg [31:0] _RAND_58;
- reg [31:0] _RAND_59;
- reg [31:0] _RAND_60;
- reg [31:0] _RAND_61;
- reg [31:0] _RAND_62;
- reg [31:0] _RAND_63;
- reg [31:0] _RAND_64;
- reg [31:0] _RAND_65;
- reg [31:0] _RAND_66;
- reg [31:0] _RAND_67;
- reg [31:0] _RAND_68;
- reg [31:0] _RAND_69;
- reg [31:0] _RAND_70;
- reg [31:0] _RAND_71;
- reg [31:0] _RAND_72;
- reg [31:0] _RAND_73;
- reg [31:0] _RAND_74;
- reg [31:0] _RAND_75;
- reg [31:0] _RAND_76;
- reg [31:0] _RAND_77;
- reg [31:0] _RAND_78;
- reg [31:0] _RAND_79;
- reg [31:0] _RAND_80;
- reg [31:0] _RAND_81;
- reg [31:0] _RAND_82;
- reg [31:0] _RAND_83;
- reg [31:0] _RAND_84;
- reg [31:0] _RAND_85;
- reg [31:0] _RAND_86;
-`endif // RANDOMIZE_REG_INIT
- wire valu_0_clock; // @[VAluInt.scala 418:11]
- wire valu_0_reset; // @[VAluInt.scala 418:11]
- wire valu_0_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_0_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_0_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_0_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_0_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_0_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_1_clock; // @[VAluInt.scala 418:11]
- wire valu_1_reset; // @[VAluInt.scala 418:11]
- wire valu_1_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_1_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_1_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_1_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_1_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_1_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_2_clock; // @[VAluInt.scala 418:11]
- wire valu_2_reset; // @[VAluInt.scala 418:11]
- wire valu_2_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_2_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_2_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_2_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_2_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_2_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_3_clock; // @[VAluInt.scala 418:11]
- wire valu_3_reset; // @[VAluInt.scala 418:11]
- wire valu_3_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_3_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_3_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_3_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_3_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_3_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_4_clock; // @[VAluInt.scala 418:11]
- wire valu_4_reset; // @[VAluInt.scala 418:11]
- wire valu_4_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_4_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_4_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_4_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_4_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_4_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_5_clock; // @[VAluInt.scala 418:11]
- wire valu_5_reset; // @[VAluInt.scala 418:11]
- wire valu_5_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_5_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_5_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_5_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_5_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_5_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_6_clock; // @[VAluInt.scala 418:11]
- wire valu_6_reset; // @[VAluInt.scala 418:11]
- wire valu_6_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_6_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_6_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_6_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_6_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_6_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_7_clock; // @[VAluInt.scala 418:11]
- wire valu_7_reset; // @[VAluInt.scala 418:11]
- wire valu_7_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_7_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_7_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_7_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_7_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_7_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_load_1; // @[VAluInt.scala 418:11]
- wire [1:0] _T_4 = io_in_sz[1] + io_in_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_89 = {{1'd0}, io_in_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_6 = _GEN_89 + _T_4; // @[Bitwise.scala 48:55]
- wire _T_11 = ~reset; // @[VAluInt.scala 63:9]
- wire e_absd = io_in_op == 7'hf; // @[VAluInt.scala 79:26]
- wire e_acc = io_in_op == 7'h35; // @[VAluInt.scala 80:26]
- wire e_dup = io_in_op == 7'h1; // @[VAluInt.scala 81:26]
- wire e_max = io_in_op == 7'h10; // @[VAluInt.scala 82:26]
- wire e_min = io_in_op == 7'h11; // @[VAluInt.scala 83:26]
- wire e_rsub = io_in_op == 7'h8; // @[VAluInt.scala 84:26]
- wire e_srans = io_in_op == 7'h25; // @[VAluInt.scala 85:26]
- wire e_sraqs = io_in_op == 7'h26; // @[VAluInt.scala 86:42]
- wire _e_slidevn_T_3 = io_in_op == 7'h3c; // @[VAluInt.scala 88:86]
- wire e_slidevn = io_in_op == 7'h3a | io_in_op == 7'h3b | io_in_op == 7'h3c; // @[VAluInt.scala 88:74]
- wire _e_slidevp_T_3 = io_in_op == 7'h3f; // @[VAluInt.scala 89:86]
- wire e_slidevp = io_in_op == 7'h3d | io_in_op == 7'h3e | io_in_op == 7'h3f; // @[VAluInt.scala 89:74]
- wire e_sel = io_in_op == 7'h40; // @[VAluInt.scala 92:24]
- wire _e_evn_T_1 = io_in_op == 7'h43; // @[VAluInt.scala 93:49]
- wire e_evn = io_in_op == 7'h41 | io_in_op == 7'h43; // @[VAluInt.scala 93:37]
- wire e_odd = io_in_op == 7'h42 | _e_evn_T_1; // @[VAluInt.scala 94:37]
- wire e_zip = io_in_op == 7'h44; // @[VAluInt.scala 95:24]
- wire e_dwinit = io_in_op == 7'h21; // @[VAluInt.scala 97:27]
- wire _e_dwconv_T_1 = io_in_op == 7'h47; // @[VAluInt.scala 98:55]
- wire e_dwconv = io_in_op == 7'h46 | io_in_op == 7'h47; // @[VAluInt.scala 98:43]
- wire e_add_add = io_in_op == 7'h6; // @[VAluInt.scala 101:29]
- wire e_add_adds = io_in_op == 7'h31; // @[VAluInt.scala 102:29]
- wire e_add_addw = io_in_op == 7'h33; // @[VAluInt.scala 103:29]
- wire e_add_add3 = io_in_op == 7'h12; // @[VAluInt.scala 104:29]
- wire e_add_hadd = io_in_op == 7'h38; // @[VAluInt.scala 105:29]
- wire e_add = e_add_add | e_add_adds | e_add_addw | e_add_add3 | e_add_hadd; // @[VAluInt.scala 106:67]
- wire e_cmp_eq = io_in_op == 7'h9; // @[VAluInt.scala 108:27]
- wire e_cmp_ne = io_in_op == 7'ha; // @[VAluInt.scala 109:27]
- wire e_cmp_lt = io_in_op == 7'hb; // @[VAluInt.scala 110:27]
- wire e_cmp_le = io_in_op == 7'hc; // @[VAluInt.scala 111:27]
- wire e_cmp_gt = io_in_op == 7'hd; // @[VAluInt.scala 112:27]
- wire e_cmp_ge = io_in_op == 7'he; // @[VAluInt.scala 113:27]
- wire e_cmp = e_cmp_eq | e_cmp_ne | e_cmp_lt | e_cmp_le | e_cmp_gt | e_cmp_ge; // @[VAluInt.scala 114:75]
- wire [5:0] _T_13 = {e_cmp_eq,e_cmp_ne,e_cmp_lt,e_cmp_le,e_cmp_gt,e_cmp_ge}; // @[Cat.scala 31:58]
- wire [1:0] _T_20 = _T_13[1] + _T_13[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_90 = {{1'd0}, _T_13[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_22 = _GEN_90 + _T_20; // @[Bitwise.scala 48:55]
- wire [1:0] _T_24 = _T_13[4] + _T_13[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_91 = {{1'd0}, _T_13[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_26 = _GEN_91 + _T_24; // @[Bitwise.scala 48:55]
- wire [2:0] _T_28 = _T_22[1:0] + _T_26[1:0]; // @[Bitwise.scala 48:55]
- wire e_log_and = io_in_op == 7'h13; // @[VAluInt.scala 117:29]
- wire e_log_or = io_in_op == 7'h14; // @[VAluInt.scala 118:29]
- wire e_log_xor = io_in_op == 7'h15; // @[VAluInt.scala 119:29]
- wire e_log_not = io_in_op == 7'h16; // @[VAluInt.scala 120:29]
- wire e_log_rev = io_in_op == 7'h17; // @[VAluInt.scala 121:29]
- wire e_log_ror = io_in_op == 7'h18; // @[VAluInt.scala 122:29]
- wire e_log_clb = io_in_op == 7'h19; // @[VAluInt.scala 123:29]
- wire e_log_clz = io_in_op == 7'h1a; // @[VAluInt.scala 124:29]
- wire e_log_cpop = io_in_op == 7'h1b; // @[VAluInt.scala 125:29]
- wire e_log = e_log_and | e_log_or | e_log_xor | e_log_not | e_log_rev | e_log_ror | e_log_clb | e_log_clz |
- e_log_cpop; // @[VAluInt.scala 126:115]
- wire [8:0] _T_34 = {e_log_and,e_log_or,e_log_xor,e_log_not,e_log_rev,e_log_ror,e_log_clb,e_log_clz,e_log_cpop}; // @[Cat.scala 31:58]
- wire [1:0] _T_44 = _T_34[0] + _T_34[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_46 = _T_34[2] + _T_34[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_48 = _T_44 + _T_46; // @[Bitwise.scala 48:55]
- wire [1:0] _T_50 = _T_34[4] + _T_34[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_52 = _T_34[7] + _T_34[8]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_92 = {{1'd0}, _T_34[6]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_54 = _GEN_92 + _T_52; // @[Bitwise.scala 48:55]
- wire [2:0] _T_56 = _T_50 + _T_54[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _T_58 = _T_48 + _T_56; // @[Bitwise.scala 48:55]
- wire _e_mul0_dmulh_T_1 = io_in_op == 7'h2e; // @[VAluInt.scala 129:58]
- wire e_mul0_dmulh = io_in_op == 7'h2d | io_in_op == 7'h2e; // @[VAluInt.scala 129:46]
- wire _e_mul0_mul_T_1 = io_in_op == 7'h28; // @[VAluInt.scala 130:56]
- wire e_mul0_mul = io_in_op == 7'h27 | io_in_op == 7'h28; // @[VAluInt.scala 130:44]
- wire _e_mul0_mulh_T_1 = io_in_op == 7'h2c; // @[VAluInt.scala 131:57]
- wire e_mul0_mulh = io_in_op == 7'h2b | io_in_op == 7'h2c; // @[VAluInt.scala 131:45]
- wire _e_mul0_muls_T_1 = io_in_op == 7'h2a; // @[VAluInt.scala 132:57]
- wire e_mul0_muls = io_in_op == 7'h29 | io_in_op == 7'h2a; // @[VAluInt.scala 132:45]
- wire e_mul0_mulw = io_in_op == 7'h2f; // @[VAluInt.scala 133:31]
- wire e_mul0_madd = io_in_op == 7'h30; // @[VAluInt.scala 134:31]
- wire e_mul0 = e_mul0_dmulh | e_mul0_mul | e_mul0_mulh | e_mul0_muls | e_mul0_mulw | e_mul0_madd; // @[VAluInt.scala 135:88]
- wire e_mul1 = _e_mul0_dmulh_T_1 | _e_mul0_mul_T_1 | _e_mul0_mulh_T_1 | _e_mul0_muls_T_1; // @[VAluInt.scala 141:58]
- wire e_mv2 = io_in_op == 7'h1d; // @[VAluInt.scala 143:24]
- wire e_mvp = io_in_op == 7'h1e; // @[VAluInt.scala 144:24]
- wire e_mv = io_in_op == 7'h1c | e_mv2 | e_mvp; // @[VAluInt.scala 145:45]
- wire e_padd_add = io_in_op == 7'h36; // @[VAluInt.scala 147:29]
- wire e_padd_sub = io_in_op == 7'h37; // @[VAluInt.scala 148:29]
- wire e_padd = e_padd_add | e_padd_sub; // @[VAluInt.scala 149:27]
- wire e_shf_shl = io_in_op == 7'h22; // @[VAluInt.scala 151:28]
- wire e_shf_shr = io_in_op == 7'h23; // @[VAluInt.scala 152:28]
- wire e_shf_shf = io_in_op == 7'h24; // @[VAluInt.scala 153:28]
- wire e_shf_l = e_shf_shl | e_shf_shf; // @[VAluInt.scala 154:27]
- wire e_shf_r = e_shf_shr | e_shf_shf; // @[VAluInt.scala 155:27]
- wire e_sub_sub = io_in_op == 7'h7; // @[VAluInt.scala 157:29]
- wire e_sub_subs = io_in_op == 7'h32; // @[VAluInt.scala 158:29]
- wire e_sub_subw = io_in_op == 7'h34; // @[VAluInt.scala 159:29]
- wire e_sub_hsub = io_in_op == 7'h39; // @[VAluInt.scala 160:29]
- wire e_sub = e_sub_sub | e_sub_subs | e_sub_subw | e_sub_hsub; // @[VAluInt.scala 161:53]
- wire e_negative = io_in_f2[0] & e_mul0_dmulh; // @[VAluInt.scala 163:32]
- wire e_round = io_in_f2[1] & (e_add_hadd | e_sub_hsub | e_mul0_dmulh | e_mul0_mulh | e_shf_shf | e_srans | e_sraqs); // @[VAluInt.scala 164:32]
- wire e_signed = ~io_in_f2[0] | e_mul0_dmulh; // @[VAluInt.scala 165:33]
- reg vdvalid0; // @[VAluInt.scala 174:25]
- reg vdvalid1; // @[VAluInt.scala 175:25]
- reg vevalid0; // @[VAluInt.scala 176:25]
- reg vevalid1; // @[VAluInt.scala 177:25]
- reg wmask; // @[VAluInt.scala 178:22]
- reg [5:0] vdaddr0_addr; // @[VAluInt.scala 179:20]
- reg [5:0] vdaddr1_addr; // @[VAluInt.scala 180:20]
- reg [5:0] veaddr0_addr; // @[VAluInt.scala 181:20]
- reg [5:0] veaddr1_addr; // @[VAluInt.scala 182:20]
- reg [2:0] sz; // @[VAluInt.scala 183:19]
- reg [2:0] f2; // @[VAluInt.scala 184:19]
- reg [31:0] sv; // @[VAluInt.scala 185:19]
- wire nxt_vdvalid = e_dwconv | e_mul0 | e_absd | e_acc | e_add | e_cmp | e_dup | e_log | e_evn | e_max | e_min | e_mv
- | e_padd | e_rsub | e_sel | e_shf_l | e_shf_r | e_slidevn | e_slidevp | e_srans | e_sraqs | e_sub | e_zip; // @[VAluInt.scala 189:240]
- wire nxt_vevalid = e_dwconv | e_mul1 | e_mul0_mulw | e_acc | e_add_addw | e_mv2 | e_mvp | e_odd | _e_slidevn_T_3 |
- _e_slidevp_T_3 | e_sub_subw | e_zip; // @[VAluInt.scala 190:149]
- wire nxt_widen = e_acc | e_add_addw | e_mul0_mulw | e_sub_subw; // @[VAluInt.scala 191:56]
- wire _sz_T = nxt_vdvalid | nxt_vevalid; // @[VAluInt.scala 195:29]
- wire [2:0] _sz_T_1 = {{1'd0}, io_in_sz[2:1]}; // @[VAluInt.scala 195:69]
- wire _vdvalid1_T = ~wmask; // @[VAluInt.scala 208:27]
- reg negative; // @[VAluInt.scala 226:21]
- reg round; // @[VAluInt.scala 227:21]
- reg signed_; // @[VAluInt.scala 228:21]
- reg absd; // @[VAluInt.scala 238:18]
- reg acc; // @[VAluInt.scala 239:18]
- reg dup; // @[VAluInt.scala 240:18]
- reg max; // @[VAluInt.scala 241:18]
- reg min; // @[VAluInt.scala 242:18]
- reg srans; // @[VAluInt.scala 243:18]
- reg sraqs; // @[VAluInt.scala 244:18]
- reg slidevn; // @[VAluInt.scala 246:21]
- reg slidevp; // @[VAluInt.scala 247:21]
- reg slidehn2; // @[VAluInt.scala 248:21]
- reg slidehp2; // @[VAluInt.scala 249:21]
- reg sel; // @[VAluInt.scala 250:21]
- reg evn; // @[VAluInt.scala 251:21]
- reg odd; // @[VAluInt.scala 252:21]
- reg zip; // @[VAluInt.scala 253:21]
- reg dwinit; // @[VAluInt.scala 255:23]
- reg dwconv; // @[VAluInt.scala 256:23]
- reg dwconvData; // @[VAluInt.scala 257:23]
- reg add; // @[VAluInt.scala 259:21]
- reg add_add; // @[VAluInt.scala 260:21]
- reg add_adds; // @[VAluInt.scala 261:21]
- reg add_addw; // @[VAluInt.scala 262:21]
- reg add_add3; // @[VAluInt.scala 263:21]
- reg add_hadd; // @[VAluInt.scala 264:21]
- reg padd; // @[VAluInt.scala 266:17]
- reg padd_add; // @[VAluInt.scala 267:21]
- reg padd_sub; // @[VAluInt.scala 268:21]
- reg rsub; // @[VAluInt.scala 270:22]
- reg rsub_rsub; // @[VAluInt.scala 271:22]
- reg sub; // @[VAluInt.scala 273:21]
- reg sub_sub; // @[VAluInt.scala 274:21]
- reg sub_subs; // @[VAluInt.scala 275:21]
- reg sub_subw; // @[VAluInt.scala 276:21]
- reg sub_hsub; // @[VAluInt.scala 277:21]
- reg cmp; // @[VAluInt.scala 279:19]
- reg cmp_eq; // @[VAluInt.scala 280:19]
- reg cmp_ne; // @[VAluInt.scala 281:19]
- reg cmp_lt; // @[VAluInt.scala 282:19]
- reg cmp_le; // @[VAluInt.scala 283:19]
- reg cmp_gt; // @[VAluInt.scala 284:19]
- reg cmp_ge; // @[VAluInt.scala 285:19]
- reg log; // @[VAluInt.scala 287:21]
- reg log_and; // @[VAluInt.scala 288:21]
- reg log_or; // @[VAluInt.scala 289:21]
- reg log_xor; // @[VAluInt.scala 290:21]
- reg log_not; // @[VAluInt.scala 291:21]
- reg log_rev; // @[VAluInt.scala 292:21]
- reg log_ror; // @[VAluInt.scala 293:21]
- reg log_clb; // @[VAluInt.scala 294:21]
- reg log_clz; // @[VAluInt.scala 295:21]
- reg log_cpop; // @[VAluInt.scala 296:21]
- reg mul0; // @[VAluInt.scala 298:23]
- reg mul0_dmulh; // @[VAluInt.scala 299:23]
- reg mul0_mul; // @[VAluInt.scala 300:23]
- reg mul0_mulh; // @[VAluInt.scala 301:23]
- reg mul0_muls; // @[VAluInt.scala 302:23]
- reg mul0_mulw; // @[VAluInt.scala 303:23]
- reg mul0_madd; // @[VAluInt.scala 304:23]
- reg mul1; // @[VAluInt.scala 306:23]
- reg mul1_dmulh; // @[VAluInt.scala 307:23]
- reg mul1_mul; // @[VAluInt.scala 308:23]
- reg mul1_mulh; // @[VAluInt.scala 309:23]
- reg mul1_muls; // @[VAluInt.scala 310:23]
- reg mv; // @[VAluInt.scala 312:16]
- reg mv2; // @[VAluInt.scala 313:16]
- reg mvp; // @[VAluInt.scala 314:16]
- reg shf_l; // @[VAluInt.scala 316:20]
- reg shf_r; // @[VAluInt.scala 317:20]
- reg shf_shl; // @[VAluInt.scala 318:20]
- reg shf_shr; // @[VAluInt.scala 319:20]
- reg shf_shf; // @[VAluInt.scala 320:20]
- reg validClr; // @[VAluInt.scala 322:25]
- wire _evnb_T_4 = evn & sz[0]; // @[VAluInt.scala 677:76]
- wire [255:0] _evnb_T_5 = _evnb_T_4 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] evnb_evnodd_31 = _evnb_T_5[247:240]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_30 = _evnb_T_5[231:224]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_29 = _evnb_T_5[215:208]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_28 = _evnb_T_5[199:192]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_27 = _evnb_T_5[183:176]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_26 = _evnb_T_5[167:160]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_25 = _evnb_T_5[151:144]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_24 = _evnb_T_5[135:128]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_23 = _evnb_T_5[119:112]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_22 = _evnb_T_5[103:96]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_21 = _evnb_T_5[87:80]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_20 = _evnb_T_5[71:64]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_19 = _evnb_T_5[55:48]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_18 = _evnb_T_5[39:32]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_17 = _evnb_T_5[23:16]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_16 = _evnb_T_5[7:0]; // @[VAluInt.scala 668:21]
- wire [63:0] evnb_out_hi_lo = {evnb_evnodd_23,evnb_evnodd_22,evnb_evnodd_21,evnb_evnodd_20,evnb_evnodd_19,
- evnb_evnodd_18,evnb_evnodd_17,evnb_evnodd_16}; // @[VAluInt.scala 671:22]
- wire [255:0] _evnb_T_2 = _evnb_T_4 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] evnb_evnodd_15 = _evnb_T_2[247:240]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_14 = _evnb_T_2[231:224]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_13 = _evnb_T_2[215:208]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_12 = _evnb_T_2[199:192]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_11 = _evnb_T_2[183:176]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_10 = _evnb_T_2[167:160]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_9 = _evnb_T_2[151:144]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_8 = _evnb_T_2[135:128]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_7 = _evnb_T_2[119:112]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_6 = _evnb_T_2[103:96]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_5 = _evnb_T_2[87:80]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_4 = _evnb_T_2[71:64]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_3 = _evnb_T_2[55:48]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_2 = _evnb_T_2[39:32]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_1 = _evnb_T_2[23:16]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_0 = _evnb_T_2[7:0]; // @[VAluInt.scala 661:21]
- wire [63:0] evnb_out_lo_lo = {evnb_evnodd_7,evnb_evnodd_6,evnb_evnodd_5,evnb_evnodd_4,evnb_evnodd_3,evnb_evnodd_2,
- evnb_evnodd_1,evnb_evnodd_0}; // @[VAluInt.scala 671:22]
- wire [127:0] evnb_out_lo = {evnb_evnodd_15,evnb_evnodd_14,evnb_evnodd_13,evnb_evnodd_12,evnb_evnodd_11,evnb_evnodd_10,
- evnb_evnodd_9,evnb_evnodd_8,evnb_out_lo_lo}; // @[VAluInt.scala 671:22]
- wire [255:0] evnb = {evnb_evnodd_31,evnb_evnodd_30,evnb_evnodd_29,evnb_evnodd_28,evnb_evnodd_27,evnb_evnodd_26,
- evnb_evnodd_25,evnb_evnodd_24,evnb_out_hi_lo,evnb_out_lo}; // @[VAluInt.scala 671:22]
- wire _evnh_T_4 = evn & sz[1]; // @[VAluInt.scala 678:76]
- wire [255:0] _evnh_T_5 = _evnh_T_4 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] evnh_evnodd_15 = _evnh_T_5[239:224]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_14 = _evnh_T_5[207:192]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_13 = _evnh_T_5[175:160]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_12 = _evnh_T_5[143:128]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_11 = _evnh_T_5[111:96]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_10 = _evnh_T_5[79:64]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_9 = _evnh_T_5[47:32]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_8 = _evnh_T_5[15:0]; // @[VAluInt.scala 668:21]
- wire [255:0] _evnh_T_2 = _evnh_T_4 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] evnh_evnodd_7 = _evnh_T_2[239:224]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_6 = _evnh_T_2[207:192]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_5 = _evnh_T_2[175:160]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_4 = _evnh_T_2[143:128]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_3 = _evnh_T_2[111:96]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_2 = _evnh_T_2[79:64]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_1 = _evnh_T_2[47:32]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_0 = _evnh_T_2[15:0]; // @[VAluInt.scala 661:21]
- wire [127:0] evnh_out_lo = {evnh_evnodd_7,evnh_evnodd_6,evnh_evnodd_5,evnh_evnodd_4,evnh_evnodd_3,evnh_evnodd_2,
- evnh_evnodd_1,evnh_evnodd_0}; // @[VAluInt.scala 671:22]
- wire [255:0] evnh = {evnh_evnodd_15,evnh_evnodd_14,evnh_evnodd_13,evnh_evnodd_12,evnh_evnodd_11,evnh_evnodd_10,
- evnh_evnodd_9,evnh_evnodd_8,evnh_out_lo}; // @[VAluInt.scala 671:22]
- wire [255:0] _evn0_T = evnb | evnh; // @[VAluInt.scala 684:19]
- wire _evnw_T_4 = evn & sz[2]; // @[VAluInt.scala 679:76]
- wire [255:0] _evnw_T_5 = _evnw_T_4 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] evnw_evnodd_7 = _evnw_T_5[223:192]; // @[VAluInt.scala 668:21]
- wire [31:0] evnw_evnodd_6 = _evnw_T_5[159:128]; // @[VAluInt.scala 668:21]
- wire [31:0] evnw_evnodd_5 = _evnw_T_5[95:64]; // @[VAluInt.scala 668:21]
- wire [31:0] evnw_evnodd_4 = _evnw_T_5[31:0]; // @[VAluInt.scala 668:21]
- wire [255:0] _evnw_T_2 = _evnw_T_4 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] evnw_evnodd_3 = _evnw_T_2[223:192]; // @[VAluInt.scala 661:21]
- wire [31:0] evnw_evnodd_2 = _evnw_T_2[159:128]; // @[VAluInt.scala 661:21]
- wire [31:0] evnw_evnodd_1 = _evnw_T_2[95:64]; // @[VAluInt.scala 661:21]
- wire [31:0] evnw_evnodd_0 = _evnw_T_2[31:0]; // @[VAluInt.scala 661:21]
- wire [255:0] evnw = {evnw_evnodd_7,evnw_evnodd_6,evnw_evnodd_5,evnw_evnodd_4,evnw_evnodd_3,evnw_evnodd_2,evnw_evnodd_1
- ,evnw_evnodd_0}; // @[VAluInt.scala 671:22]
- wire [255:0] evn0 = _evn0_T | evnw; // @[VAluInt.scala 684:26]
- wire _T_94 = zip & sz[0]; // @[VAluInt.scala 720:80]
- wire [255:0] _T_95 = _T_94 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] zip0__31 = _T_95[127:120]; // @[VAluInt.scala 707:21]
- wire [255:0] _T_92 = _T_94 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] zip0__30 = _T_92[127:120]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__29 = _T_95[119:112]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__28 = _T_92[119:112]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__27 = _T_95[111:104]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__26 = _T_92[111:104]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__25 = _T_95[103:96]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__24 = _T_92[103:96]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__23 = _T_95[95:88]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__22 = _T_92[95:88]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__21 = _T_95[87:80]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__20 = _T_92[87:80]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__19 = _T_95[79:72]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__18 = _T_92[79:72]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__17 = _T_95[71:64]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__16 = _T_92[71:64]; // @[VAluInt.scala 704:21]
- wire [63:0] out0_hi_lo = {zip0__23,zip0__22,zip0__21,zip0__20,zip0__19,zip0__18,zip0__17,zip0__16}; // @[VAluInt.scala 712:21]
- wire [7:0] zip0__15 = _T_95[63:56]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__14 = _T_92[63:56]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__13 = _T_95[55:48]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__12 = _T_92[55:48]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__11 = _T_95[47:40]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__10 = _T_92[47:40]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__9 = _T_95[39:32]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__8 = _T_92[39:32]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__7 = _T_95[31:24]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__6 = _T_92[31:24]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__5 = _T_95[23:16]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__4 = _T_92[23:16]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__3 = _T_95[15:8]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__2 = _T_92[15:8]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__1 = _T_95[7:0]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__0 = _T_92[7:0]; // @[VAluInt.scala 704:21]
- wire [63:0] out0_lo_lo = {zip0__7,zip0__6,zip0__5,zip0__4,zip0__3,zip0__2,zip0__1,zip0__0}; // @[VAluInt.scala 712:21]
- wire [127:0] out0_lo = {zip0__15,zip0__14,zip0__13,zip0__12,zip0__11,zip0__10,zip0__9,zip0__8,out0_lo_lo}; // @[VAluInt.scala 712:21]
- wire [255:0] zipb0 = {zip0__31,zip0__30,zip0__29,zip0__28,zip0__27,zip0__26,zip0__25,zip0__24,out0_hi_lo,out0_lo}; // @[VAluInt.scala 712:21]
- wire _T_100 = zip & sz[1]; // @[VAluInt.scala 721:80]
- wire [255:0] _T_101 = _T_100 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] zip0_1_15 = _T_101[127:112]; // @[VAluInt.scala 707:21]
- wire [255:0] _T_98 = _T_100 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] zip0_1_14 = _T_98[127:112]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_13 = _T_101[111:96]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_12 = _T_98[111:96]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_11 = _T_101[95:80]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_10 = _T_98[95:80]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_9 = _T_101[79:64]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_8 = _T_98[79:64]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_7 = _T_101[63:48]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_6 = _T_98[63:48]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_5 = _T_101[47:32]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_4 = _T_98[47:32]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_3 = _T_101[31:16]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_2 = _T_98[31:16]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_1 = _T_101[15:0]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_0 = _T_98[15:0]; // @[VAluInt.scala 704:21]
- wire [127:0] out0_lo_1 = {zip0_1_7,zip0_1_6,zip0_1_5,zip0_1_4,zip0_1_3,zip0_1_2,zip0_1_1,zip0_1_0}; // @[VAluInt.scala 712:21]
- wire [255:0] ziph0 = {zip0_1_15,zip0_1_14,zip0_1_13,zip0_1_12,zip0_1_11,zip0_1_10,zip0_1_9,zip0_1_8,out0_lo_1}; // @[VAluInt.scala 712:21]
- wire [255:0] _zip0_T = zipb0 | ziph0; // @[VAluInt.scala 724:20]
- wire _T_106 = zip & sz[2]; // @[VAluInt.scala 722:80]
- wire [255:0] _T_107 = _T_106 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] zip0_2_7 = _T_107[127:96]; // @[VAluInt.scala 707:21]
- wire [255:0] _T_104 = _T_106 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] zip0_2_6 = _T_104[127:96]; // @[VAluInt.scala 704:21]
- wire [31:0] zip0_2_5 = _T_107[95:64]; // @[VAluInt.scala 707:21]
- wire [31:0] zip0_2_4 = _T_104[95:64]; // @[VAluInt.scala 704:21]
- wire [31:0] zip0_2_3 = _T_107[63:32]; // @[VAluInt.scala 707:21]
- wire [31:0] zip0_2_2 = _T_104[63:32]; // @[VAluInt.scala 704:21]
- wire [31:0] zip0_2_1 = _T_107[31:0]; // @[VAluInt.scala 707:21]
- wire [31:0] zip0_2_0 = _T_104[31:0]; // @[VAluInt.scala 704:21]
- wire [255:0] zipw0 = {zip0_2_7,zip0_2_6,zip0_2_5,zip0_2_4,zip0_2_3,zip0_2_2,zip0_2_1,zip0_2_0}; // @[VAluInt.scala 712:21]
- wire [255:0] zip0_3 = _zip0_T | zipw0; // @[VAluInt.scala 724:28]
- wire [255:0] _load_0_T = evn0 | zip0_3; // @[VAluInt.scala 742:19]
- wire _slidenb0_out_T = f2[1:0] == 2'h0; // @[VAluInt.scala 549:25]
- wire _slidenb0_T_5 = slidevn & sz[0]; // @[VAluInt.scala 595:94]
- wire [255:0] _slidenb0_T_6 = _slidenb0_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidenb0_in_32 = _slidenb0_T_6[7:0]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenb0_T_3 = _slidenb0_T_5 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidenb0_in_31 = _slidenb0_T_3[255:248]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_30 = _slidenb0_T_3[247:240]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_29 = _slidenb0_T_3[239:232]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_28 = _slidenb0_T_3[231:224]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_27 = _slidenb0_T_3[223:216]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_26 = _slidenb0_T_3[215:208]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_25 = _slidenb0_T_3[207:200]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_24 = _slidenb0_T_3[199:192]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_23 = _slidenb0_T_3[191:184]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_22 = _slidenb0_T_3[183:176]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_21 = _slidenb0_T_3[175:168]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_20 = _slidenb0_T_3[167:160]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_19 = _slidenb0_T_3[159:152]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_18 = _slidenb0_T_3[151:144]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_17 = _slidenb0_T_3[143:136]; // @[VAluInt.scala 538:23]
- wire [63:0] slidenb0_out_hi_lo = {slidenb0_in_24,slidenb0_in_23,slidenb0_in_22,slidenb0_in_21,slidenb0_in_20,
- slidenb0_in_19,slidenb0_in_18,slidenb0_in_17}; // @[VAluInt.scala 549:40]
- wire [7:0] slidenb0_in_16 = _slidenb0_T_3[135:128]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_15 = _slidenb0_T_3[127:120]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_14 = _slidenb0_T_3[119:112]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_13 = _slidenb0_T_3[111:104]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_12 = _slidenb0_T_3[103:96]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_11 = _slidenb0_T_3[95:88]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_10 = _slidenb0_T_3[87:80]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_9 = _slidenb0_T_3[79:72]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_8 = _slidenb0_T_3[71:64]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_7 = _slidenb0_T_3[63:56]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_6 = _slidenb0_T_3[55:48]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_5 = _slidenb0_T_3[47:40]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_4 = _slidenb0_T_3[39:32]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_3 = _slidenb0_T_3[31:24]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_2 = _slidenb0_T_3[23:16]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_1 = _slidenb0_T_3[15:8]; // @[VAluInt.scala 538:23]
- wire [63:0] slidenb0_out_lo_lo = {slidenb0_in_8,slidenb0_in_7,slidenb0_in_6,slidenb0_in_5,slidenb0_in_4,slidenb0_in_3,
- slidenb0_in_2,slidenb0_in_1}; // @[VAluInt.scala 549:40]
- wire [127:0] slidenb0_out_lo = {slidenb0_in_16,slidenb0_in_15,slidenb0_in_14,slidenb0_in_13,slidenb0_in_12,
- slidenb0_in_11,slidenb0_in_10,slidenb0_in_9,slidenb0_out_lo_lo}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenb0_out_T_1 = {slidenb0_in_32,slidenb0_in_31,slidenb0_in_30,slidenb0_in_29,slidenb0_in_28,
- slidenb0_in_27,slidenb0_in_26,slidenb0_in_25,slidenb0_out_hi_lo,slidenb0_out_lo}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenb0_out_T_2 = _slidenb0_out_T ? _slidenb0_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire _slidenb0_out_T_3 = f2[1:0] == 2'h1; // @[VAluInt.scala 550:25]
- wire [7:0] slidenb0_in_33 = _slidenb0_T_6[15:8]; // @[VAluInt.scala 539:23]
- wire [63:0] slidenb0_out_hi_lo_1 = {slidenb0_in_25,slidenb0_in_24,slidenb0_in_23,slidenb0_in_22,slidenb0_in_21,
- slidenb0_in_20,slidenb0_in_19,slidenb0_in_18}; // @[VAluInt.scala 550:40]
- wire [63:0] slidenb0_out_lo_lo_1 = {slidenb0_in_9,slidenb0_in_8,slidenb0_in_7,slidenb0_in_6,slidenb0_in_5,
- slidenb0_in_4,slidenb0_in_3,slidenb0_in_2}; // @[VAluInt.scala 550:40]
- wire [127:0] slidenb0_out_lo_1 = {slidenb0_in_17,slidenb0_in_16,slidenb0_in_15,slidenb0_in_14,slidenb0_in_13,
- slidenb0_in_12,slidenb0_in_11,slidenb0_in_10,slidenb0_out_lo_lo_1}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenb0_out_T_4 = {slidenb0_in_33,slidenb0_in_32,slidenb0_in_31,slidenb0_in_30,slidenb0_in_29,
- slidenb0_in_28,slidenb0_in_27,slidenb0_in_26,slidenb0_out_hi_lo_1,slidenb0_out_lo_1}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenb0_out_T_5 = _slidenb0_out_T_3 ? _slidenb0_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenb0_out_T_6 = _slidenb0_out_T_2 | _slidenb0_out_T_5; // @[VAluInt.scala 549:48]
- wire _slidenb0_out_T_7 = f2[1:0] == 2'h2; // @[VAluInt.scala 551:25]
- wire [7:0] slidenb0_in_34 = _slidenb0_T_6[23:16]; // @[VAluInt.scala 539:23]
- wire [63:0] slidenb0_out_hi_lo_2 = {slidenb0_in_26,slidenb0_in_25,slidenb0_in_24,slidenb0_in_23,slidenb0_in_22,
- slidenb0_in_21,slidenb0_in_20,slidenb0_in_19}; // @[VAluInt.scala 551:40]
- wire [63:0] slidenb0_out_lo_lo_2 = {slidenb0_in_10,slidenb0_in_9,slidenb0_in_8,slidenb0_in_7,slidenb0_in_6,
- slidenb0_in_5,slidenb0_in_4,slidenb0_in_3}; // @[VAluInt.scala 551:40]
- wire [127:0] slidenb0_out_lo_2 = {slidenb0_in_18,slidenb0_in_17,slidenb0_in_16,slidenb0_in_15,slidenb0_in_14,
- slidenb0_in_13,slidenb0_in_12,slidenb0_in_11,slidenb0_out_lo_lo_2}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenb0_out_T_8 = {slidenb0_in_34,slidenb0_in_33,slidenb0_in_32,slidenb0_in_31,slidenb0_in_30,
- slidenb0_in_29,slidenb0_in_28,slidenb0_in_27,slidenb0_out_hi_lo_2,slidenb0_out_lo_2}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenb0_out_T_9 = _slidenb0_out_T_7 ? _slidenb0_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenb0_out_T_10 = _slidenb0_out_T_6 | _slidenb0_out_T_9; // @[VAluInt.scala 550:48]
- wire _slidenb0_out_T_11 = f2[1:0] == 2'h3; // @[VAluInt.scala 552:25]
- wire [7:0] slidenb0_in_35 = _slidenb0_T_6[31:24]; // @[VAluInt.scala 539:23]
- wire [63:0] slidenb0_out_hi_lo_3 = {slidenb0_in_27,slidenb0_in_26,slidenb0_in_25,slidenb0_in_24,slidenb0_in_23,
- slidenb0_in_22,slidenb0_in_21,slidenb0_in_20}; // @[VAluInt.scala 552:40]
- wire [63:0] slidenb0_out_lo_lo_3 = {slidenb0_in_11,slidenb0_in_10,slidenb0_in_9,slidenb0_in_8,slidenb0_in_7,
- slidenb0_in_6,slidenb0_in_5,slidenb0_in_4}; // @[VAluInt.scala 552:40]
- wire [127:0] slidenb0_out_lo_3 = {slidenb0_in_19,slidenb0_in_18,slidenb0_in_17,slidenb0_in_16,slidenb0_in_15,
- slidenb0_in_14,slidenb0_in_13,slidenb0_in_12,slidenb0_out_lo_lo_3}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenb0_out_T_12 = {slidenb0_in_35,slidenb0_in_34,slidenb0_in_33,slidenb0_in_32,slidenb0_in_31,
- slidenb0_in_30,slidenb0_in_29,slidenb0_in_28,slidenb0_out_hi_lo_3,slidenb0_out_lo_3}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenb0_out_T_13 = _slidenb0_out_T_11 ? _slidenb0_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidenb0 = _slidenb0_out_T_10 | _slidenb0_out_T_13; // @[VAluInt.scala 551:48]
- wire _slidenh0_T_5 = slidevn & sz[1]; // @[VAluInt.scala 596:94]
- wire [255:0] _slidenh0_T_6 = _slidenh0_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slidenh0_in_16 = _slidenh0_T_6[15:0]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenh0_T_3 = _slidenh0_T_5 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slidenh0_in_15 = _slidenh0_T_3[255:240]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_14 = _slidenh0_T_3[239:224]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_13 = _slidenh0_T_3[223:208]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_12 = _slidenh0_T_3[207:192]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_11 = _slidenh0_T_3[191:176]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_10 = _slidenh0_T_3[175:160]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_9 = _slidenh0_T_3[159:144]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_8 = _slidenh0_T_3[143:128]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_7 = _slidenh0_T_3[127:112]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_6 = _slidenh0_T_3[111:96]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_5 = _slidenh0_T_3[95:80]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_4 = _slidenh0_T_3[79:64]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_3 = _slidenh0_T_3[63:48]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_2 = _slidenh0_T_3[47:32]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_1 = _slidenh0_T_3[31:16]; // @[VAluInt.scala 538:23]
- wire [127:0] slidenh0_out_lo = {slidenh0_in_8,slidenh0_in_7,slidenh0_in_6,slidenh0_in_5,slidenh0_in_4,slidenh0_in_3,
- slidenh0_in_2,slidenh0_in_1}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenh0_out_T_1 = {slidenh0_in_16,slidenh0_in_15,slidenh0_in_14,slidenh0_in_13,slidenh0_in_12,
- slidenh0_in_11,slidenh0_in_10,slidenh0_in_9,slidenh0_out_lo}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenh0_out_T_2 = _slidenb0_out_T ? _slidenh0_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slidenh0_in_17 = _slidenh0_T_6[31:16]; // @[VAluInt.scala 539:23]
- wire [127:0] slidenh0_out_lo_1 = {slidenh0_in_9,slidenh0_in_8,slidenh0_in_7,slidenh0_in_6,slidenh0_in_5,slidenh0_in_4,
- slidenh0_in_3,slidenh0_in_2}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenh0_out_T_4 = {slidenh0_in_17,slidenh0_in_16,slidenh0_in_15,slidenh0_in_14,slidenh0_in_13,
- slidenh0_in_12,slidenh0_in_11,slidenh0_in_10,slidenh0_out_lo_1}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenh0_out_T_5 = _slidenb0_out_T_3 ? _slidenh0_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenh0_out_T_6 = _slidenh0_out_T_2 | _slidenh0_out_T_5; // @[VAluInt.scala 549:48]
- wire [15:0] slidenh0_in_18 = _slidenh0_T_6[47:32]; // @[VAluInt.scala 539:23]
- wire [127:0] slidenh0_out_lo_2 = {slidenh0_in_10,slidenh0_in_9,slidenh0_in_8,slidenh0_in_7,slidenh0_in_6,slidenh0_in_5
- ,slidenh0_in_4,slidenh0_in_3}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenh0_out_T_8 = {slidenh0_in_18,slidenh0_in_17,slidenh0_in_16,slidenh0_in_15,slidenh0_in_14,
- slidenh0_in_13,slidenh0_in_12,slidenh0_in_11,slidenh0_out_lo_2}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenh0_out_T_9 = _slidenb0_out_T_7 ? _slidenh0_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenh0_out_T_10 = _slidenh0_out_T_6 | _slidenh0_out_T_9; // @[VAluInt.scala 550:48]
- wire [15:0] slidenh0_in_19 = _slidenh0_T_6[63:48]; // @[VAluInt.scala 539:23]
- wire [127:0] slidenh0_out_lo_3 = {slidenh0_in_11,slidenh0_in_10,slidenh0_in_9,slidenh0_in_8,slidenh0_in_7,
- slidenh0_in_6,slidenh0_in_5,slidenh0_in_4}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenh0_out_T_12 = {slidenh0_in_19,slidenh0_in_18,slidenh0_in_17,slidenh0_in_16,slidenh0_in_15,
- slidenh0_in_14,slidenh0_in_13,slidenh0_in_12,slidenh0_out_lo_3}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenh0_out_T_13 = _slidenb0_out_T_11 ? _slidenh0_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidenh0 = _slidenh0_out_T_10 | _slidenh0_out_T_13; // @[VAluInt.scala 551:48]
- wire [255:0] _slide0_T = slidenb0 | slidenh0; // @[VAluInt.scala 611:25]
- wire _slidenw0_T_5 = slidevn & sz[2]; // @[VAluInt.scala 597:94]
- wire [255:0] _slidenw0_T_6 = _slidenw0_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidenw0_in_8 = _slidenw0_T_6[31:0]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw0_T_3 = _slidenw0_T_5 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidenw0_in_7 = _slidenw0_T_3[255:224]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw0_in_6 = _slidenw0_T_3[223:192]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw0_in_5 = _slidenw0_T_3[191:160]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw0_in_4 = _slidenw0_T_3[159:128]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw0_in_3 = _slidenw0_T_3[127:96]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw0_in_2 = _slidenw0_T_3[95:64]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw0_in_1 = _slidenw0_T_3[63:32]; // @[VAluInt.scala 538:23]
- wire [255:0] _slidenw0_out_T_1 = {slidenw0_in_8,slidenw0_in_7,slidenw0_in_6,slidenw0_in_5,slidenw0_in_4,slidenw0_in_3,
- slidenw0_in_2,slidenw0_in_1}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenw0_out_T_2 = _slidenb0_out_T ? _slidenw0_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidenw0_in_9 = _slidenw0_T_6[63:32]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw0_out_T_4 = {slidenw0_in_9,slidenw0_in_8,slidenw0_in_7,slidenw0_in_6,slidenw0_in_5,slidenw0_in_4,
- slidenw0_in_3,slidenw0_in_2}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenw0_out_T_5 = _slidenb0_out_T_3 ? _slidenw0_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenw0_out_T_6 = _slidenw0_out_T_2 | _slidenw0_out_T_5; // @[VAluInt.scala 549:48]
- wire [31:0] slidenw0_in_10 = _slidenw0_T_6[95:64]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw0_out_T_8 = {slidenw0_in_10,slidenw0_in_9,slidenw0_in_8,slidenw0_in_7,slidenw0_in_6,slidenw0_in_5
- ,slidenw0_in_4,slidenw0_in_3}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenw0_out_T_9 = _slidenb0_out_T_7 ? _slidenw0_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenw0_out_T_10 = _slidenw0_out_T_6 | _slidenw0_out_T_9; // @[VAluInt.scala 550:48]
- wire [31:0] slidenw0_in_11 = _slidenw0_T_6[127:96]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw0_out_T_12 = {slidenw0_in_11,slidenw0_in_10,slidenw0_in_9,slidenw0_in_8,slidenw0_in_7,
- slidenw0_in_6,slidenw0_in_5,slidenw0_in_4}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenw0_out_T_13 = _slidenb0_out_T_11 ? _slidenw0_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidenw0 = _slidenw0_out_T_10 | _slidenw0_out_T_13; // @[VAluInt.scala 551:48]
- wire [255:0] _slide0_T_1 = _slide0_T | slidenw0; // @[VAluInt.scala 611:36]
- wire _slidepb0_T_5 = slidevp & sz[0]; // @[VAluInt.scala 603:94]
- wire [255:0] _slidepb0_T_6 = _slidepb0_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidepb0_in_62 = _slidepb0_T_6[247:240]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_61 = _slidepb0_T_6[239:232]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_60 = _slidepb0_T_6[231:224]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_59 = _slidepb0_T_6[223:216]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_58 = _slidepb0_T_6[215:208]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_57 = _slidepb0_T_6[207:200]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_56 = _slidepb0_T_6[199:192]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_55 = _slidepb0_T_6[191:184]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_54 = _slidepb0_T_6[183:176]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_53 = _slidepb0_T_6[175:168]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_52 = _slidepb0_T_6[167:160]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_51 = _slidepb0_T_6[159:152]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_50 = _slidepb0_T_6[151:144]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_49 = _slidepb0_T_6[143:136]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_48 = _slidepb0_T_6[135:128]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_47 = _slidepb0_T_6[127:120]; // @[VAluInt.scala 576:23]
- wire [63:0] slidepb0_out_hi_lo = {slidepb0_in_54,slidepb0_in_53,slidepb0_in_52,slidepb0_in_51,slidepb0_in_50,
- slidepb0_in_49,slidepb0_in_48,slidepb0_in_47}; // @[VAluInt.scala 586:40]
- wire [7:0] slidepb0_in_46 = _slidepb0_T_6[119:112]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_45 = _slidepb0_T_6[111:104]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_44 = _slidepb0_T_6[103:96]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_43 = _slidepb0_T_6[95:88]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_42 = _slidepb0_T_6[87:80]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_41 = _slidepb0_T_6[79:72]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_40 = _slidepb0_T_6[71:64]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_39 = _slidepb0_T_6[63:56]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_38 = _slidepb0_T_6[55:48]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_37 = _slidepb0_T_6[47:40]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_36 = _slidepb0_T_6[39:32]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_35 = _slidepb0_T_6[31:24]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_34 = _slidepb0_T_6[23:16]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_33 = _slidepb0_T_6[15:8]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_32 = _slidepb0_T_6[7:0]; // @[VAluInt.scala 576:23]
- wire [255:0] _slidepb0_T_3 = _slidepb0_T_5 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidepb0_in_31 = _slidepb0_T_3[255:248]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb0_out_lo_lo = {slidepb0_in_38,slidepb0_in_37,slidepb0_in_36,slidepb0_in_35,slidepb0_in_34,
- slidepb0_in_33,slidepb0_in_32,slidepb0_in_31}; // @[VAluInt.scala 586:40]
- wire [127:0] slidepb0_out_lo = {slidepb0_in_46,slidepb0_in_45,slidepb0_in_44,slidepb0_in_43,slidepb0_in_42,
- slidepb0_in_41,slidepb0_in_40,slidepb0_in_39,slidepb0_out_lo_lo}; // @[VAluInt.scala 586:40]
- wire [255:0] _slidepb0_out_T_1 = {slidepb0_in_62,slidepb0_in_61,slidepb0_in_60,slidepb0_in_59,slidepb0_in_58,
- slidepb0_in_57,slidepb0_in_56,slidepb0_in_55,slidepb0_out_hi_lo,slidepb0_out_lo}; // @[VAluInt.scala 586:40]
- wire [255:0] _slidepb0_out_T_2 = _slidenb0_out_T ? _slidepb0_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [63:0] slidepb0_out_hi_lo_1 = {slidepb0_in_53,slidepb0_in_52,slidepb0_in_51,slidepb0_in_50,slidepb0_in_49,
- slidepb0_in_48,slidepb0_in_47,slidepb0_in_46}; // @[VAluInt.scala 587:40]
- wire [7:0] slidepb0_in_30 = _slidepb0_T_3[247:240]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb0_out_lo_lo_1 = {slidepb0_in_37,slidepb0_in_36,slidepb0_in_35,slidepb0_in_34,slidepb0_in_33,
- slidepb0_in_32,slidepb0_in_31,slidepb0_in_30}; // @[VAluInt.scala 587:40]
- wire [127:0] slidepb0_out_lo_1 = {slidepb0_in_45,slidepb0_in_44,slidepb0_in_43,slidepb0_in_42,slidepb0_in_41,
- slidepb0_in_40,slidepb0_in_39,slidepb0_in_38,slidepb0_out_lo_lo_1}; // @[VAluInt.scala 587:40]
- wire [255:0] _slidepb0_out_T_4 = {slidepb0_in_61,slidepb0_in_60,slidepb0_in_59,slidepb0_in_58,slidepb0_in_57,
- slidepb0_in_56,slidepb0_in_55,slidepb0_in_54,slidepb0_out_hi_lo_1,slidepb0_out_lo_1}; // @[VAluInt.scala 587:40]
- wire [255:0] _slidepb0_out_T_5 = _slidenb0_out_T_3 ? _slidepb0_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepb0_out_T_6 = _slidepb0_out_T_2 | _slidepb0_out_T_5; // @[VAluInt.scala 586:48]
- wire [63:0] slidepb0_out_hi_lo_2 = {slidepb0_in_52,slidepb0_in_51,slidepb0_in_50,slidepb0_in_49,slidepb0_in_48,
- slidepb0_in_47,slidepb0_in_46,slidepb0_in_45}; // @[VAluInt.scala 588:40]
- wire [7:0] slidepb0_in_29 = _slidepb0_T_3[239:232]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb0_out_lo_lo_2 = {slidepb0_in_36,slidepb0_in_35,slidepb0_in_34,slidepb0_in_33,slidepb0_in_32,
- slidepb0_in_31,slidepb0_in_30,slidepb0_in_29}; // @[VAluInt.scala 588:40]
- wire [127:0] slidepb0_out_lo_2 = {slidepb0_in_44,slidepb0_in_43,slidepb0_in_42,slidepb0_in_41,slidepb0_in_40,
- slidepb0_in_39,slidepb0_in_38,slidepb0_in_37,slidepb0_out_lo_lo_2}; // @[VAluInt.scala 588:40]
- wire [255:0] _slidepb0_out_T_8 = {slidepb0_in_60,slidepb0_in_59,slidepb0_in_58,slidepb0_in_57,slidepb0_in_56,
- slidepb0_in_55,slidepb0_in_54,slidepb0_in_53,slidepb0_out_hi_lo_2,slidepb0_out_lo_2}; // @[VAluInt.scala 588:40]
- wire [255:0] _slidepb0_out_T_9 = _slidenb0_out_T_7 ? _slidepb0_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepb0_out_T_10 = _slidepb0_out_T_6 | _slidepb0_out_T_9; // @[VAluInt.scala 587:48]
- wire [63:0] slidepb0_out_hi_lo_3 = {slidepb0_in_51,slidepb0_in_50,slidepb0_in_49,slidepb0_in_48,slidepb0_in_47,
- slidepb0_in_46,slidepb0_in_45,slidepb0_in_44}; // @[VAluInt.scala 589:40]
- wire [7:0] slidepb0_in_28 = _slidepb0_T_3[231:224]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb0_out_lo_lo_3 = {slidepb0_in_35,slidepb0_in_34,slidepb0_in_33,slidepb0_in_32,slidepb0_in_31,
- slidepb0_in_30,slidepb0_in_29,slidepb0_in_28}; // @[VAluInt.scala 589:40]
- wire [127:0] slidepb0_out_lo_3 = {slidepb0_in_43,slidepb0_in_42,slidepb0_in_41,slidepb0_in_40,slidepb0_in_39,
- slidepb0_in_38,slidepb0_in_37,slidepb0_in_36,slidepb0_out_lo_lo_3}; // @[VAluInt.scala 589:40]
- wire [255:0] _slidepb0_out_T_12 = {slidepb0_in_59,slidepb0_in_58,slidepb0_in_57,slidepb0_in_56,slidepb0_in_55,
- slidepb0_in_54,slidepb0_in_53,slidepb0_in_52,slidepb0_out_hi_lo_3,slidepb0_out_lo_3}; // @[VAluInt.scala 589:40]
- wire [255:0] _slidepb0_out_T_13 = _slidenb0_out_T_11 ? _slidepb0_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidepb0 = _slidepb0_out_T_10 | _slidepb0_out_T_13; // @[VAluInt.scala 588:48]
- wire [255:0] _slide0_T_2 = _slide0_T_1 | slidepb0; // @[VAluInt.scala 611:47]
- wire _slideph0_T_5 = slidevp & sz[1]; // @[VAluInt.scala 604:94]
- wire [255:0] _slideph0_T_6 = _slideph0_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slideph0_in_30 = _slideph0_T_6[239:224]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_29 = _slideph0_T_6[223:208]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_28 = _slideph0_T_6[207:192]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_27 = _slideph0_T_6[191:176]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_26 = _slideph0_T_6[175:160]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_25 = _slideph0_T_6[159:144]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_24 = _slideph0_T_6[143:128]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_23 = _slideph0_T_6[127:112]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_22 = _slideph0_T_6[111:96]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_21 = _slideph0_T_6[95:80]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_20 = _slideph0_T_6[79:64]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_19 = _slideph0_T_6[63:48]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_18 = _slideph0_T_6[47:32]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_17 = _slideph0_T_6[31:16]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_16 = _slideph0_T_6[15:0]; // @[VAluInt.scala 576:23]
- wire [255:0] _slideph0_T_3 = _slideph0_T_5 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slideph0_in_15 = _slideph0_T_3[255:240]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph0_out_lo = {slideph0_in_22,slideph0_in_21,slideph0_in_20,slideph0_in_19,slideph0_in_18,
- slideph0_in_17,slideph0_in_16,slideph0_in_15}; // @[VAluInt.scala 586:40]
- wire [255:0] _slideph0_out_T_1 = {slideph0_in_30,slideph0_in_29,slideph0_in_28,slideph0_in_27,slideph0_in_26,
- slideph0_in_25,slideph0_in_24,slideph0_in_23,slideph0_out_lo}; // @[VAluInt.scala 586:40]
- wire [255:0] _slideph0_out_T_2 = _slidenb0_out_T ? _slideph0_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slideph0_in_14 = _slideph0_T_3[239:224]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph0_out_lo_1 = {slideph0_in_21,slideph0_in_20,slideph0_in_19,slideph0_in_18,slideph0_in_17,
- slideph0_in_16,slideph0_in_15,slideph0_in_14}; // @[VAluInt.scala 587:40]
- wire [255:0] _slideph0_out_T_4 = {slideph0_in_29,slideph0_in_28,slideph0_in_27,slideph0_in_26,slideph0_in_25,
- slideph0_in_24,slideph0_in_23,slideph0_in_22,slideph0_out_lo_1}; // @[VAluInt.scala 587:40]
- wire [255:0] _slideph0_out_T_5 = _slidenb0_out_T_3 ? _slideph0_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slideph0_out_T_6 = _slideph0_out_T_2 | _slideph0_out_T_5; // @[VAluInt.scala 586:48]
- wire [15:0] slideph0_in_13 = _slideph0_T_3[223:208]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph0_out_lo_2 = {slideph0_in_20,slideph0_in_19,slideph0_in_18,slideph0_in_17,slideph0_in_16,
- slideph0_in_15,slideph0_in_14,slideph0_in_13}; // @[VAluInt.scala 588:40]
- wire [255:0] _slideph0_out_T_8 = {slideph0_in_28,slideph0_in_27,slideph0_in_26,slideph0_in_25,slideph0_in_24,
- slideph0_in_23,slideph0_in_22,slideph0_in_21,slideph0_out_lo_2}; // @[VAluInt.scala 588:40]
- wire [255:0] _slideph0_out_T_9 = _slidenb0_out_T_7 ? _slideph0_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slideph0_out_T_10 = _slideph0_out_T_6 | _slideph0_out_T_9; // @[VAluInt.scala 587:48]
- wire [15:0] slideph0_in_12 = _slideph0_T_3[207:192]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph0_out_lo_3 = {slideph0_in_19,slideph0_in_18,slideph0_in_17,slideph0_in_16,slideph0_in_15,
- slideph0_in_14,slideph0_in_13,slideph0_in_12}; // @[VAluInt.scala 589:40]
- wire [255:0] _slideph0_out_T_12 = {slideph0_in_27,slideph0_in_26,slideph0_in_25,slideph0_in_24,slideph0_in_23,
- slideph0_in_22,slideph0_in_21,slideph0_in_20,slideph0_out_lo_3}; // @[VAluInt.scala 589:40]
- wire [255:0] _slideph0_out_T_13 = _slidenb0_out_T_11 ? _slideph0_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slideph0 = _slideph0_out_T_10 | _slideph0_out_T_13; // @[VAluInt.scala 588:48]
- wire [255:0] _slide0_T_3 = _slide0_T_2 | slideph0; // @[VAluInt.scala 612:25]
- wire _slidepw0_T_5 = slidevp & sz[2]; // @[VAluInt.scala 605:94]
- wire [255:0] _slidepw0_T_6 = _slidepw0_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidepw0_in_14 = _slidepw0_T_6[223:192]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw0_in_13 = _slidepw0_T_6[191:160]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw0_in_12 = _slidepw0_T_6[159:128]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw0_in_11 = _slidepw0_T_6[127:96]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw0_in_10 = _slidepw0_T_6[95:64]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw0_in_9 = _slidepw0_T_6[63:32]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw0_in_8 = _slidepw0_T_6[31:0]; // @[VAluInt.scala 576:23]
- wire [255:0] _slidepw0_T_3 = _slidepw0_T_5 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidepw0_in_7 = _slidepw0_T_3[255:224]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw0_out_T_1 = {slidepw0_in_14,slidepw0_in_13,slidepw0_in_12,slidepw0_in_11,slidepw0_in_10,
- slidepw0_in_9,slidepw0_in_8,slidepw0_in_7}; // @[VAluInt.scala 586:40]
- wire [255:0] _slidepw0_out_T_2 = _slidenb0_out_T ? _slidepw0_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidepw0_in_6 = _slidepw0_T_3[223:192]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw0_out_T_4 = {slidepw0_in_13,slidepw0_in_12,slidepw0_in_11,slidepw0_in_10,slidepw0_in_9,
- slidepw0_in_8,slidepw0_in_7,slidepw0_in_6}; // @[VAluInt.scala 587:40]
- wire [255:0] _slidepw0_out_T_5 = _slidenb0_out_T_3 ? _slidepw0_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepw0_out_T_6 = _slidepw0_out_T_2 | _slidepw0_out_T_5; // @[VAluInt.scala 586:48]
- wire [31:0] slidepw0_in_5 = _slidepw0_T_3[191:160]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw0_out_T_8 = {slidepw0_in_12,slidepw0_in_11,slidepw0_in_10,slidepw0_in_9,slidepw0_in_8,
- slidepw0_in_7,slidepw0_in_6,slidepw0_in_5}; // @[VAluInt.scala 588:40]
- wire [255:0] _slidepw0_out_T_9 = _slidenb0_out_T_7 ? _slidepw0_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepw0_out_T_10 = _slidepw0_out_T_6 | _slidepw0_out_T_9; // @[VAluInt.scala 587:48]
- wire [31:0] slidepw0_in_4 = _slidepw0_T_3[159:128]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw0_out_T_12 = {slidepw0_in_11,slidepw0_in_10,slidepw0_in_9,slidepw0_in_8,slidepw0_in_7,
- slidepw0_in_6,slidepw0_in_5,slidepw0_in_4}; // @[VAluInt.scala 589:40]
- wire [255:0] _slidepw0_out_T_13 = _slidenb0_out_T_11 ? _slidepw0_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidepw0 = _slidepw0_out_T_10 | _slidepw0_out_T_13; // @[VAluInt.scala 588:48]
- wire [255:0] slide0 = _slide0_T_3 | slidepw0; // @[VAluInt.scala 612:36]
- wire [255:0] _load_0_T_1 = _load_0_T | slide0; // @[VAluInt.scala 742:26]
- wire [1:0] sparse = sv[3:2]; // @[VDot.scala 67:24]
- wire sparse0 = sparse == 2'h0; // @[VDot.scala 73:26]
- wire _adata0_T_14 = dwconv & sparse0; // @[VDot.scala 127:31]
- wire [31:0] adata0_7 = _adata0_T_14 ? io_read_0_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire sparse1 = sparse == 2'h1; // @[VDot.scala 74:26]
- wire _adata1_7_T = dwconv & sparse1; // @[VDot.scala 99:33]
- wire [31:0] adata1_7 = _adata1_7_T ? io_read_1_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_7_T = adata0_7 | adata1_7; // @[VDot.scala 129:32]
- wire sparse2 = sparse == 2'h2; // @[VDot.scala 75:26]
- wire _adata2_7_T = dwconv & sparse2; // @[VDot.scala 112:29]
- wire [31:0] adata2_7 = _adata2_7_T ? io_read_0_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_7 = _adatac_0_7_T | adata2_7; // @[VDot.scala 129:44]
- wire asign = sv[21]; // @[VDot.scala 69:23]
- wire as_42 = adatac_0_7[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_170 = {as_42,adatac_0_7[7:0]}; // @[VDot.scala 170:56]
- wire [8:0] abias = sv[20:12]; // @[VDot.scala 68:23]
- wire [8:0] _aval_T_171 = dwconv ? abias : 9'h0; // @[VDot.scala 170:72]
- wire [9:0] aval_42 = $signed(_aval_T_170) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_7 = dwconv ? io_read_3_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire bsign = sv[31]; // @[VDot.scala 71:23]
- wire bs_42 = bdatac_0_7[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_170 = {bs_42,bdatac_0_7[7:0]}; // @[VDot.scala 171:56]
- wire [8:0] bbias = sv[30:22]; // @[VDot.scala 70:23]
- wire [8:0] _bval_T_171 = dwconv ? bbias : 9'h0; // @[VDot.scala 171:72]
- wire [9:0] bval_42 = $signed(_bval_T_170) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_42 = $signed(aval_42) * $signed(bval_42); // @[VDot.scala 172:25]
- wire [31:0] adata0_15 = _adata0_T_14 ? io_read_1_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_8 = _adata1_7_T ? io_read_1_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_7_T = adata0_15 | adata1_8; // @[VDot.scala 129:32]
- wire [31:0] adata2_8 = _adata2_7_T ? io_read_1_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_1_7 = _adatac_1_7_T | adata2_8; // @[VDot.scala 129:44]
- wire as_43 = adatac_1_7[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_174 = {as_43,adatac_1_7[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_43 = $signed(_aval_T_174) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_7 = dwconv ? io_read_4_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire bs_43 = bdatac_1_7[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_174 = {bs_43,bdatac_1_7[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_43 = $signed(_bval_T_174) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_43 = $signed(aval_43) * $signed(bval_43); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_14 = $signed(mval_42) + $signed(mval_43); // @[VDot.scala 180:26]
- wire [31:0] adata0_23 = _adata0_T_14 ? io_read_2_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_9 = _adata1_7_T ? io_read_2_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_7_T = adata0_23 | adata1_9; // @[VDot.scala 129:32]
- wire [31:0] adata2_9 = _adata2_7_T ? io_read_1_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_2_7 = _adatac_2_7_T | adata2_9; // @[VDot.scala 129:44]
- wire as_44 = adatac_2_7[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_178 = {as_44,adatac_2_7[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_44 = $signed(_aval_T_178) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_7 = dwconv ? io_read_5_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire bs_44 = bdatac_2_7[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_178 = {bs_44,bdatac_2_7[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_44 = $signed(_bval_T_178) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_44 = $signed(aval_44) * $signed(bval_44); // @[VDot.scala 172:25]
- wire [20:0] _GEN_94 = {{1{mval_44[19]}},mval_44}; // @[VDot.scala 180:37]
- wire [21:0] dotp_14 = $signed(_dotp_T_14) + $signed(_GEN_94); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_44 = dotp_14[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_14 = $signed(_dotp_T_14) + $signed(_GEN_94); // @[Cat.scala 31:58]
- wire [31:0] adata0_6 = _adata0_T_14 ? io_read_0_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_6 = _adata1_7_T ? io_read_1_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_6_T = adata0_6 | adata1_6; // @[VDot.scala 129:32]
- wire [31:0] adata2_6 = _adata2_7_T ? io_read_0_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_6 = _adatac_0_6_T | adata2_6; // @[VDot.scala 129:44]
- wire as_36 = adatac_0_6[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_146 = {as_36,adatac_0_6[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_36 = $signed(_aval_T_146) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_6 = dwconv ? io_read_3_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire bs_36 = bdatac_0_6[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_146 = {bs_36,bdatac_0_6[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_36 = $signed(_bval_T_146) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_36 = $signed(aval_36) * $signed(bval_36); // @[VDot.scala 172:25]
- wire [31:0] adata0_14 = _adata0_T_14 ? io_read_1_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_6_T = adata0_14 | adata1_7; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_6 = _adatac_1_6_T | adata2_7; // @[VDot.scala 129:44]
- wire as_37 = adatac_1_6[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_150 = {as_37,adatac_1_6[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_37 = $signed(_aval_T_150) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_6 = dwconv ? io_read_4_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire bs_37 = bdatac_1_6[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_150 = {bs_37,bdatac_1_6[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_37 = $signed(_bval_T_150) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_37 = $signed(aval_37) * $signed(bval_37); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_12 = $signed(mval_36) + $signed(mval_37); // @[VDot.scala 180:26]
- wire [31:0] adata0_22 = _adata0_T_14 ? io_read_2_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_6_T = adata0_22 | adata1_8; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_6 = _adatac_2_6_T | adata2_8; // @[VDot.scala 129:44]
- wire as_38 = adatac_2_6[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_154 = {as_38,adatac_2_6[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_38 = $signed(_aval_T_154) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_6 = dwconv ? io_read_5_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire bs_38 = bdatac_2_6[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_154 = {bs_38,bdatac_2_6[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_38 = $signed(_bval_T_154) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_38 = $signed(aval_38) * $signed(bval_38); // @[VDot.scala 172:25]
- wire [20:0] _GEN_95 = {{1{mval_38[19]}},mval_38}; // @[VDot.scala 180:37]
- wire [21:0] dotp_12 = $signed(_dotp_T_12) + $signed(_GEN_95); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_38 = dotp_12[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_12 = $signed(_dotp_T_12) + $signed(_GEN_95); // @[Cat.scala 31:58]
- wire [31:0] adata0_5 = _adata0_T_14 ? io_read_0_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_5 = _adata1_7_T ? io_read_1_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_5_T = adata0_5 | adata1_5; // @[VDot.scala 129:32]
- wire [31:0] adata2_5 = _adata2_7_T ? io_read_0_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_5 = _adatac_0_5_T | adata2_5; // @[VDot.scala 129:44]
- wire as_30 = adatac_0_5[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_122 = {as_30,adatac_0_5[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_30 = $signed(_aval_T_122) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_5 = dwconv ? io_read_3_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire bs_30 = bdatac_0_5[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_122 = {bs_30,bdatac_0_5[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_30 = $signed(_bval_T_122) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_30 = $signed(aval_30) * $signed(bval_30); // @[VDot.scala 172:25]
- wire [31:0] adata0_13 = _adata0_T_14 ? io_read_1_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_5_T = adata0_13 | adata1_6; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_5 = _adatac_1_5_T | adata2_6; // @[VDot.scala 129:44]
- wire as_31 = adatac_1_5[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_126 = {as_31,adatac_1_5[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_31 = $signed(_aval_T_126) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_5 = dwconv ? io_read_4_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire bs_31 = bdatac_1_5[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_126 = {bs_31,bdatac_1_5[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_31 = $signed(_bval_T_126) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_31 = $signed(aval_31) * $signed(bval_31); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_10 = $signed(mval_30) + $signed(mval_31); // @[VDot.scala 180:26]
- wire [31:0] adata0_21 = _adata0_T_14 ? io_read_2_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_5_T = adata0_21 | adata1_7; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_5 = _adatac_2_5_T | adata2_7; // @[VDot.scala 129:44]
- wire as_32 = adatac_2_5[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_130 = {as_32,adatac_2_5[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_32 = $signed(_aval_T_130) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_5 = dwconv ? io_read_5_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire bs_32 = bdatac_2_5[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_130 = {bs_32,bdatac_2_5[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_32 = $signed(_bval_T_130) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_32 = $signed(aval_32) * $signed(bval_32); // @[VDot.scala 172:25]
- wire [20:0] _GEN_96 = {{1{mval_32[19]}},mval_32}; // @[VDot.scala 180:37]
- wire [21:0] dotp_10 = $signed(_dotp_T_10) + $signed(_GEN_96); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_32 = dotp_10[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_10 = $signed(_dotp_T_10) + $signed(_GEN_96); // @[Cat.scala 31:58]
- wire [31:0] adata0_4 = _adata0_T_14 ? io_read_0_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_4 = _adata1_7_T ? io_read_1_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_4_T = adata0_4 | adata1_4; // @[VDot.scala 129:32]
- wire [31:0] adata2_4 = _adata2_7_T ? io_read_0_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_4 = _adatac_0_4_T | adata2_4; // @[VDot.scala 129:44]
- wire as_24 = adatac_0_4[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_98 = {as_24,adatac_0_4[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_24 = $signed(_aval_T_98) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_4 = dwconv ? io_read_3_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire bs_24 = bdatac_0_4[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_98 = {bs_24,bdatac_0_4[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_24 = $signed(_bval_T_98) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_24 = $signed(aval_24) * $signed(bval_24); // @[VDot.scala 172:25]
- wire [31:0] adata0_12 = _adata0_T_14 ? io_read_1_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_4_T = adata0_12 | adata1_5; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_4 = _adatac_1_4_T | adata2_5; // @[VDot.scala 129:44]
- wire as_25 = adatac_1_4[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_102 = {as_25,adatac_1_4[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_25 = $signed(_aval_T_102) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_4 = dwconv ? io_read_4_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire bs_25 = bdatac_1_4[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_102 = {bs_25,bdatac_1_4[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_25 = $signed(_bval_T_102) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_25 = $signed(aval_25) * $signed(bval_25); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_8 = $signed(mval_24) + $signed(mval_25); // @[VDot.scala 180:26]
- wire [31:0] adata0_20 = _adata0_T_14 ? io_read_2_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_4_T = adata0_20 | adata1_6; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_4 = _adatac_2_4_T | adata2_6; // @[VDot.scala 129:44]
- wire as_26 = adatac_2_4[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_106 = {as_26,adatac_2_4[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_26 = $signed(_aval_T_106) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_4 = dwconv ? io_read_5_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire bs_26 = bdatac_2_4[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_106 = {bs_26,bdatac_2_4[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_26 = $signed(_bval_T_106) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_26 = $signed(aval_26) * $signed(bval_26); // @[VDot.scala 172:25]
- wire [20:0] _GEN_97 = {{1{mval_26[19]}},mval_26}; // @[VDot.scala 180:37]
- wire [21:0] dotp_8 = $signed(_dotp_T_8) + $signed(_GEN_97); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_26 = dotp_8[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_8 = $signed(_dotp_T_8) + $signed(_GEN_97); // @[Cat.scala 31:58]
- wire [31:0] adata0_3 = _adata0_T_14 ? io_read_0_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_3 = _adata1_7_T ? io_read_1_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_3_T = adata0_3 | adata1_3; // @[VDot.scala 129:32]
- wire [31:0] adata2_3 = _adata2_7_T ? io_read_0_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_3 = _adatac_0_3_T | adata2_3; // @[VDot.scala 129:44]
- wire as_18 = adatac_0_3[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_74 = {as_18,adatac_0_3[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_18 = $signed(_aval_T_74) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_3 = dwconv ? io_read_3_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire bs_18 = bdatac_0_3[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_74 = {bs_18,bdatac_0_3[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_18 = $signed(_bval_T_74) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_18 = $signed(aval_18) * $signed(bval_18); // @[VDot.scala 172:25]
- wire [31:0] adata0_11 = _adata0_T_14 ? io_read_1_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_3_T = adata0_11 | adata1_4; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_3 = _adatac_1_3_T | adata2_4; // @[VDot.scala 129:44]
- wire as_19 = adatac_1_3[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_78 = {as_19,adatac_1_3[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_19 = $signed(_aval_T_78) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_3 = dwconv ? io_read_4_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire bs_19 = bdatac_1_3[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_78 = {bs_19,bdatac_1_3[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_19 = $signed(_bval_T_78) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_19 = $signed(aval_19) * $signed(bval_19); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_6 = $signed(mval_18) + $signed(mval_19); // @[VDot.scala 180:26]
- wire [31:0] adata0_19 = _adata0_T_14 ? io_read_2_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_3_T = adata0_19 | adata1_5; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_3 = _adatac_2_3_T | adata2_5; // @[VDot.scala 129:44]
- wire as_20 = adatac_2_3[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_82 = {as_20,adatac_2_3[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_20 = $signed(_aval_T_82) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_3 = dwconv ? io_read_5_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire bs_20 = bdatac_2_3[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_82 = {bs_20,bdatac_2_3[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_20 = $signed(_bval_T_82) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_20 = $signed(aval_20) * $signed(bval_20); // @[VDot.scala 172:25]
- wire [20:0] _GEN_98 = {{1{mval_20[19]}},mval_20}; // @[VDot.scala 180:37]
- wire [21:0] dotp_6 = $signed(_dotp_T_6) + $signed(_GEN_98); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_20 = dotp_6[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_6 = $signed(_dotp_T_6) + $signed(_GEN_98); // @[Cat.scala 31:58]
- wire [31:0] adata0_2 = _adata0_T_14 ? io_read_0_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_2 = _adata1_7_T ? io_read_1_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_2_T = adata0_2 | adata1_2; // @[VDot.scala 129:32]
- wire [31:0] adata2_2 = _adata2_7_T ? io_read_0_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_2 = _adatac_0_2_T | adata2_2; // @[VDot.scala 129:44]
- wire as_12 = adatac_0_2[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_50 = {as_12,adatac_0_2[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_12 = $signed(_aval_T_50) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_2 = dwconv ? io_read_3_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire bs_12 = bdatac_0_2[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_50 = {bs_12,bdatac_0_2[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_12 = $signed(_bval_T_50) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_12 = $signed(aval_12) * $signed(bval_12); // @[VDot.scala 172:25]
- wire [31:0] adata0_10 = _adata0_T_14 ? io_read_1_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_2_T = adata0_10 | adata1_3; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_2 = _adatac_1_2_T | adata2_3; // @[VDot.scala 129:44]
- wire as_13 = adatac_1_2[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_54 = {as_13,adatac_1_2[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_13 = $signed(_aval_T_54) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_2 = dwconv ? io_read_4_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire bs_13 = bdatac_1_2[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_54 = {bs_13,bdatac_1_2[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_13 = $signed(_bval_T_54) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_13 = $signed(aval_13) * $signed(bval_13); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_4 = $signed(mval_12) + $signed(mval_13); // @[VDot.scala 180:26]
- wire [31:0] adata0_18 = _adata0_T_14 ? io_read_2_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_2_T = adata0_18 | adata1_4; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_2 = _adatac_2_2_T | adata2_4; // @[VDot.scala 129:44]
- wire as_14 = adatac_2_2[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_58 = {as_14,adatac_2_2[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_14 = $signed(_aval_T_58) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_2 = dwconv ? io_read_5_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire bs_14 = bdatac_2_2[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_58 = {bs_14,bdatac_2_2[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_14 = $signed(_bval_T_58) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_14 = $signed(aval_14) * $signed(bval_14); // @[VDot.scala 172:25]
- wire [20:0] _GEN_99 = {{1{mval_14[19]}},mval_14}; // @[VDot.scala 180:37]
- wire [21:0] dotp_4 = $signed(_dotp_T_4) + $signed(_GEN_99); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_14 = dotp_4[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_4 = $signed(_dotp_T_4) + $signed(_GEN_99); // @[Cat.scala 31:58]
- wire [31:0] adata0_1 = _adata0_T_14 ? io_read_0_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_1 = _adata1_7_T ? io_read_1_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_1_T = adata0_1 | adata1_1; // @[VDot.scala 129:32]
- wire [31:0] adata2_1 = _adata2_7_T ? io_read_0_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_1 = _adatac_0_1_T | adata2_1; // @[VDot.scala 129:44]
- wire as_6 = adatac_0_1[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_26 = {as_6,adatac_0_1[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_6 = $signed(_aval_T_26) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_1 = dwconv ? io_read_3_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire bs_6 = bdatac_0_1[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_26 = {bs_6,bdatac_0_1[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_6 = $signed(_bval_T_26) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_6 = $signed(aval_6) * $signed(bval_6); // @[VDot.scala 172:25]
- wire [31:0] adata0_9 = _adata0_T_14 ? io_read_1_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_1_T = adata0_9 | adata1_2; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_1 = _adatac_1_1_T | adata2_2; // @[VDot.scala 129:44]
- wire as_7 = adatac_1_1[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_30 = {as_7,adatac_1_1[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_7 = $signed(_aval_T_30) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_1 = dwconv ? io_read_4_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire bs_7 = bdatac_1_1[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_30 = {bs_7,bdatac_1_1[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_7 = $signed(_bval_T_30) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_7 = $signed(aval_7) * $signed(bval_7); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_2 = $signed(mval_6) + $signed(mval_7); // @[VDot.scala 180:26]
- wire [31:0] adata0_17 = _adata0_T_14 ? io_read_2_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_1_T = adata0_17 | adata1_3; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_1 = _adatac_2_1_T | adata2_3; // @[VDot.scala 129:44]
- wire as_8 = adatac_2_1[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_34 = {as_8,adatac_2_1[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_8 = $signed(_aval_T_34) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_1 = dwconv ? io_read_5_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire bs_8 = bdatac_2_1[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_34 = {bs_8,bdatac_2_1[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_8 = $signed(_bval_T_34) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_8 = $signed(aval_8) * $signed(bval_8); // @[VDot.scala 172:25]
- wire [20:0] _GEN_100 = {{1{mval_8[19]}},mval_8}; // @[VDot.scala 180:37]
- wire [21:0] dotp_2 = $signed(_dotp_T_2) + $signed(_GEN_100); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_8 = dotp_2[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_2 = $signed(_dotp_T_2) + $signed(_GEN_100); // @[Cat.scala 31:58]
- wire [31:0] adata0 = _adata0_T_14 ? io_read_0_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_0 = _adata1_7_T ? io_read_0_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_0_T = adata0 | adata1_0; // @[VDot.scala 129:32]
- wire [31:0] adata2_0 = _adata2_7_T ? io_read_0_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_0 = _adatac_0_0_T | adata2_0; // @[VDot.scala 129:44]
- wire as = adatac_0_0[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_2 = {as,adatac_0_0[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval = $signed(_aval_T_2) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_0 = dwconv ? io_read_3_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire bs = bdatac_0_0[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_2 = {bs,bdatac_0_0[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval = $signed(_bval_T_2) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval = $signed(aval) * $signed(bval); // @[VDot.scala 172:25]
- wire [31:0] adata0_8 = _adata0_T_14 ? io_read_1_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_0_T = adata0_8 | adata1_1; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_0 = _adatac_1_0_T | adata2_1; // @[VDot.scala 129:44]
- wire as_1 = adatac_1_0[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_6 = {as_1,adatac_1_0[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_1 = $signed(_aval_T_6) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_0 = dwconv ? io_read_4_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire bs_1 = bdatac_1_0[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_6 = {bs_1,bdatac_1_0[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_1 = $signed(_bval_T_6) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_1 = $signed(aval_1) * $signed(bval_1); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T = $signed(mval) + $signed(mval_1); // @[VDot.scala 180:26]
- wire [31:0] adata0_16 = _adata0_T_14 ? io_read_2_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_0_T = adata0_16 | adata1_2; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_0 = _adatac_2_0_T | adata2_2; // @[VDot.scala 129:44]
- wire as_2 = adatac_2_0[7] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_10 = {as_2,adatac_2_0[7:0]}; // @[VDot.scala 170:56]
- wire [9:0] aval_2 = $signed(_aval_T_10) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_0 = dwconv ? io_read_5_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire bs_2 = bdatac_2_0[7] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_10 = {bs_2,bdatac_2_0[7:0]}; // @[VDot.scala 171:56]
- wire [9:0] bval_2 = $signed(_bval_T_10) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_2 = $signed(aval_2) * $signed(bval_2); // @[VDot.scala 172:25]
- wire [20:0] _GEN_101 = {{1{mval_2[19]}},mval_2}; // @[VDot.scala 180:37]
- wire [21:0] dotp = $signed(_dotp_T) + $signed(_GEN_101); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_2 = dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo = $signed(_dotp_T) + $signed(_GEN_101); // @[Cat.scala 31:58]
- wire [127:0] out0_lo_3 = {_sdotp_T_20,sdotp_lo_6,_sdotp_T_14,sdotp_lo_4,_sdotp_T_8,sdotp_lo_2,_sdotp_T_2,sdotp_lo}; // @[VDot.scala 142:22]
- wire [255:0] dwconv0 = {_sdotp_T_44,sdotp_lo_14,_sdotp_T_38,sdotp_lo_12,_sdotp_T_32,sdotp_lo_10,_sdotp_T_26,sdotp_lo_8
- ,out0_lo_3}; // @[VDot.scala 142:22]
- wire [255:0] _load_0_T_2 = _load_0_T_1 | dwconv0; // @[VAluInt.scala 742:35]
- wire _selb0_T_1 = sel & sz[0]; // @[VAluInt.scala 639:33]
- wire [255:0] _selb0_T_2 = _selb0_T_1 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _selb0_T_8 = _selb0_T_1 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _selb0_T_5 = _selb0_T_1 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] selb0_sout_31 = _selb0_T_2[248] ? _selb0_T_8[255:248] : _selb0_T_5[255:248]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_30 = _selb0_T_2[240] ? _selb0_T_8[247:240] : _selb0_T_5[247:240]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_29 = _selb0_T_2[232] ? _selb0_T_8[239:232] : _selb0_T_5[239:232]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_28 = _selb0_T_2[224] ? _selb0_T_8[231:224] : _selb0_T_5[231:224]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_27 = _selb0_T_2[216] ? _selb0_T_8[223:216] : _selb0_T_5[223:216]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_26 = _selb0_T_2[208] ? _selb0_T_8[215:208] : _selb0_T_5[215:208]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_25 = _selb0_T_2[200] ? _selb0_T_8[207:200] : _selb0_T_5[207:200]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_24 = _selb0_T_2[192] ? _selb0_T_8[199:192] : _selb0_T_5[199:192]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_23 = _selb0_T_2[184] ? _selb0_T_8[191:184] : _selb0_T_5[191:184]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_22 = _selb0_T_2[176] ? _selb0_T_8[183:176] : _selb0_T_5[183:176]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_21 = _selb0_T_2[168] ? _selb0_T_8[175:168] : _selb0_T_5[175:168]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_20 = _selb0_T_2[160] ? _selb0_T_8[167:160] : _selb0_T_5[167:160]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_19 = _selb0_T_2[152] ? _selb0_T_8[159:152] : _selb0_T_5[159:152]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_18 = _selb0_T_2[144] ? _selb0_T_8[151:144] : _selb0_T_5[151:144]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_17 = _selb0_T_2[136] ? _selb0_T_8[143:136] : _selb0_T_5[143:136]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_16 = _selb0_T_2[128] ? _selb0_T_8[135:128] : _selb0_T_5[135:128]; // @[VAluInt.scala 630:21]
- wire [63:0] selb0_out_hi_lo = {selb0_sout_23,selb0_sout_22,selb0_sout_21,selb0_sout_20,selb0_sout_19,selb0_sout_18,
- selb0_sout_17,selb0_sout_16}; // @[VAluInt.scala 633:20]
- wire [7:0] selb0_sout_15 = _selb0_T_2[120] ? _selb0_T_8[127:120] : _selb0_T_5[127:120]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_14 = _selb0_T_2[112] ? _selb0_T_8[119:112] : _selb0_T_5[119:112]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_13 = _selb0_T_2[104] ? _selb0_T_8[111:104] : _selb0_T_5[111:104]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_12 = _selb0_T_2[96] ? _selb0_T_8[103:96] : _selb0_T_5[103:96]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_11 = _selb0_T_2[88] ? _selb0_T_8[95:88] : _selb0_T_5[95:88]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_10 = _selb0_T_2[80] ? _selb0_T_8[87:80] : _selb0_T_5[87:80]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_9 = _selb0_T_2[72] ? _selb0_T_8[79:72] : _selb0_T_5[79:72]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_8 = _selb0_T_2[64] ? _selb0_T_8[71:64] : _selb0_T_5[71:64]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_7 = _selb0_T_2[56] ? _selb0_T_8[63:56] : _selb0_T_5[63:56]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_6 = _selb0_T_2[48] ? _selb0_T_8[55:48] : _selb0_T_5[55:48]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_5 = _selb0_T_2[40] ? _selb0_T_8[47:40] : _selb0_T_5[47:40]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_4 = _selb0_T_2[32] ? _selb0_T_8[39:32] : _selb0_T_5[39:32]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_3 = _selb0_T_2[24] ? _selb0_T_8[31:24] : _selb0_T_5[31:24]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_2 = _selb0_T_2[16] ? _selb0_T_8[23:16] : _selb0_T_5[23:16]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_1 = _selb0_T_2[8] ? _selb0_T_8[15:8] : _selb0_T_5[15:8]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_0 = _selb0_T_2[0] ? _selb0_T_8[7:0] : _selb0_T_5[7:0]; // @[VAluInt.scala 630:21]
- wire [63:0] selb0_out_lo_lo = {selb0_sout_7,selb0_sout_6,selb0_sout_5,selb0_sout_4,selb0_sout_3,selb0_sout_2,
- selb0_sout_1,selb0_sout_0}; // @[VAluInt.scala 633:20]
- wire [127:0] selb0_out_lo = {selb0_sout_15,selb0_sout_14,selb0_sout_13,selb0_sout_12,selb0_sout_11,selb0_sout_10,
- selb0_sout_9,selb0_sout_8,selb0_out_lo_lo}; // @[VAluInt.scala 633:20]
- wire [255:0] selb0 = {selb0_sout_31,selb0_sout_30,selb0_sout_29,selb0_sout_28,selb0_sout_27,selb0_sout_26,
- selb0_sout_25,selb0_sout_24,selb0_out_hi_lo,selb0_out_lo}; // @[VAluInt.scala 633:20]
- wire _selh0_T_1 = sel & sz[1]; // @[VAluInt.scala 640:33]
- wire [255:0] _selh0_T_2 = _selh0_T_1 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _selh0_T_8 = _selh0_T_1 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _selh0_T_5 = _selh0_T_1 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] selh0_sout_15 = _selh0_T_2[240] ? _selh0_T_8[255:240] : _selh0_T_5[255:240]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_14 = _selh0_T_2[224] ? _selh0_T_8[239:224] : _selh0_T_5[239:224]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_13 = _selh0_T_2[208] ? _selh0_T_8[223:208] : _selh0_T_5[223:208]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_12 = _selh0_T_2[192] ? _selh0_T_8[207:192] : _selh0_T_5[207:192]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_11 = _selh0_T_2[176] ? _selh0_T_8[191:176] : _selh0_T_5[191:176]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_10 = _selh0_T_2[160] ? _selh0_T_8[175:160] : _selh0_T_5[175:160]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_9 = _selh0_T_2[144] ? _selh0_T_8[159:144] : _selh0_T_5[159:144]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_8 = _selh0_T_2[128] ? _selh0_T_8[143:128] : _selh0_T_5[143:128]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_7 = _selh0_T_2[112] ? _selh0_T_8[127:112] : _selh0_T_5[127:112]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_6 = _selh0_T_2[96] ? _selh0_T_8[111:96] : _selh0_T_5[111:96]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_5 = _selh0_T_2[80] ? _selh0_T_8[95:80] : _selh0_T_5[95:80]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_4 = _selh0_T_2[64] ? _selh0_T_8[79:64] : _selh0_T_5[79:64]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_3 = _selh0_T_2[48] ? _selh0_T_8[63:48] : _selh0_T_5[63:48]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_2 = _selh0_T_2[32] ? _selh0_T_8[47:32] : _selh0_T_5[47:32]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_1 = _selh0_T_2[16] ? _selh0_T_8[31:16] : _selh0_T_5[31:16]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_0 = _selh0_T_2[0] ? _selh0_T_8[15:0] : _selh0_T_5[15:0]; // @[VAluInt.scala 630:21]
- wire [127:0] selh0_out_lo = {selh0_sout_7,selh0_sout_6,selh0_sout_5,selh0_sout_4,selh0_sout_3,selh0_sout_2,
- selh0_sout_1,selh0_sout_0}; // @[VAluInt.scala 633:20]
- wire [255:0] selh0 = {selh0_sout_15,selh0_sout_14,selh0_sout_13,selh0_sout_12,selh0_sout_11,selh0_sout_10,selh0_sout_9
- ,selh0_sout_8,selh0_out_lo}; // @[VAluInt.scala 633:20]
- wire [255:0] _sel0_T = selb0 | selh0; // @[VAluInt.scala 643:20]
- wire _selw0_T_1 = sel & sz[2]; // @[VAluInt.scala 641:33]
- wire [255:0] _selw0_T_2 = _selw0_T_1 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _selw0_T_8 = _selw0_T_1 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _selw0_T_5 = _selw0_T_1 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] selw0_sout_7 = _selw0_T_2[224] ? _selw0_T_8[255:224] : _selw0_T_5[255:224]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_6 = _selw0_T_2[192] ? _selw0_T_8[223:192] : _selw0_T_5[223:192]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_5 = _selw0_T_2[160] ? _selw0_T_8[191:160] : _selw0_T_5[191:160]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_4 = _selw0_T_2[128] ? _selw0_T_8[159:128] : _selw0_T_5[159:128]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_3 = _selw0_T_2[96] ? _selw0_T_8[127:96] : _selw0_T_5[127:96]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_2 = _selw0_T_2[64] ? _selw0_T_8[95:64] : _selw0_T_5[95:64]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_1 = _selw0_T_2[32] ? _selw0_T_8[63:32] : _selw0_T_5[63:32]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_0 = _selw0_T_2[0] ? _selw0_T_8[31:0] : _selw0_T_5[31:0]; // @[VAluInt.scala 630:21]
- wire [255:0] selw0 = {selw0_sout_7,selw0_sout_6,selw0_sout_5,selw0_sout_4,selw0_sout_3,selw0_sout_2,selw0_sout_1,
- selw0_sout_0}; // @[VAluInt.scala 633:20]
- wire [255:0] sel0 = _sel0_T | selw0; // @[VAluInt.scala 643:28]
- wire [255:0] load_0 = _load_0_T_2 | sel0; // @[VAluInt.scala 742:45]
- wire _oddb_T_4 = odd & sz[0]; // @[VAluInt.scala 680:76]
- wire [255:0] _oddb_T_5 = _oddb_T_4 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] oddb_evnodd_31 = _oddb_T_5[255:248]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_30 = _oddb_T_5[239:232]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_29 = _oddb_T_5[223:216]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_28 = _oddb_T_5[207:200]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_27 = _oddb_T_5[191:184]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_26 = _oddb_T_5[175:168]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_25 = _oddb_T_5[159:152]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_24 = _oddb_T_5[143:136]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_23 = _oddb_T_5[127:120]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_22 = _oddb_T_5[111:104]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_21 = _oddb_T_5[95:88]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_20 = _oddb_T_5[79:72]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_19 = _oddb_T_5[63:56]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_18 = _oddb_T_5[47:40]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_17 = _oddb_T_5[31:24]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_16 = _oddb_T_5[15:8]; // @[VAluInt.scala 668:21]
- wire [63:0] oddb_out_hi_lo = {oddb_evnodd_23,oddb_evnodd_22,oddb_evnodd_21,oddb_evnodd_20,oddb_evnodd_19,
- oddb_evnodd_18,oddb_evnodd_17,oddb_evnodd_16}; // @[VAluInt.scala 671:22]
- wire [255:0] _oddb_T_2 = _oddb_T_4 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] oddb_evnodd_15 = _oddb_T_2[255:248]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_14 = _oddb_T_2[239:232]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_13 = _oddb_T_2[223:216]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_12 = _oddb_T_2[207:200]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_11 = _oddb_T_2[191:184]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_10 = _oddb_T_2[175:168]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_9 = _oddb_T_2[159:152]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_8 = _oddb_T_2[143:136]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_7 = _oddb_T_2[127:120]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_6 = _oddb_T_2[111:104]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_5 = _oddb_T_2[95:88]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_4 = _oddb_T_2[79:72]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_3 = _oddb_T_2[63:56]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_2 = _oddb_T_2[47:40]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_1 = _oddb_T_2[31:24]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_0 = _oddb_T_2[15:8]; // @[VAluInt.scala 661:21]
- wire [63:0] oddb_out_lo_lo = {oddb_evnodd_7,oddb_evnodd_6,oddb_evnodd_5,oddb_evnodd_4,oddb_evnodd_3,oddb_evnodd_2,
- oddb_evnodd_1,oddb_evnodd_0}; // @[VAluInt.scala 671:22]
- wire [127:0] oddb_out_lo = {oddb_evnodd_15,oddb_evnodd_14,oddb_evnodd_13,oddb_evnodd_12,oddb_evnodd_11,oddb_evnodd_10,
- oddb_evnodd_9,oddb_evnodd_8,oddb_out_lo_lo}; // @[VAluInt.scala 671:22]
- wire [255:0] oddb = {oddb_evnodd_31,oddb_evnodd_30,oddb_evnodd_29,oddb_evnodd_28,oddb_evnodd_27,oddb_evnodd_26,
- oddb_evnodd_25,oddb_evnodd_24,oddb_out_hi_lo,oddb_out_lo}; // @[VAluInt.scala 671:22]
- wire _oddh_T_4 = odd & sz[1]; // @[VAluInt.scala 681:76]
- wire [255:0] _oddh_T_5 = _oddh_T_4 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] oddh_evnodd_15 = _oddh_T_5[255:240]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_14 = _oddh_T_5[223:208]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_13 = _oddh_T_5[191:176]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_12 = _oddh_T_5[159:144]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_11 = _oddh_T_5[127:112]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_10 = _oddh_T_5[95:80]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_9 = _oddh_T_5[63:48]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_8 = _oddh_T_5[31:16]; // @[VAluInt.scala 668:21]
- wire [255:0] _oddh_T_2 = _oddh_T_4 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] oddh_evnodd_7 = _oddh_T_2[255:240]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_6 = _oddh_T_2[223:208]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_5 = _oddh_T_2[191:176]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_4 = _oddh_T_2[159:144]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_3 = _oddh_T_2[127:112]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_2 = _oddh_T_2[95:80]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_1 = _oddh_T_2[63:48]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_0 = _oddh_T_2[31:16]; // @[VAluInt.scala 661:21]
- wire [127:0] oddh_out_lo = {oddh_evnodd_7,oddh_evnodd_6,oddh_evnodd_5,oddh_evnodd_4,oddh_evnodd_3,oddh_evnodd_2,
- oddh_evnodd_1,oddh_evnodd_0}; // @[VAluInt.scala 671:22]
- wire [255:0] oddh = {oddh_evnodd_15,oddh_evnodd_14,oddh_evnodd_13,oddh_evnodd_12,oddh_evnodd_11,oddh_evnodd_10,
- oddh_evnodd_9,oddh_evnodd_8,oddh_out_lo}; // @[VAluInt.scala 671:22]
- wire [255:0] _odd1_T = oddb | oddh; // @[VAluInt.scala 685:19]
- wire _oddw_T_4 = odd & sz[2]; // @[VAluInt.scala 682:76]
- wire [255:0] _oddw_T_5 = _oddw_T_4 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] oddw_evnodd_7 = _oddw_T_5[255:224]; // @[VAluInt.scala 668:21]
- wire [31:0] oddw_evnodd_6 = _oddw_T_5[191:160]; // @[VAluInt.scala 668:21]
- wire [31:0] oddw_evnodd_5 = _oddw_T_5[127:96]; // @[VAluInt.scala 668:21]
- wire [31:0] oddw_evnodd_4 = _oddw_T_5[63:32]; // @[VAluInt.scala 668:21]
- wire [255:0] _oddw_T_2 = _oddw_T_4 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] oddw_evnodd_3 = _oddw_T_2[255:224]; // @[VAluInt.scala 661:21]
- wire [31:0] oddw_evnodd_2 = _oddw_T_2[191:160]; // @[VAluInt.scala 661:21]
- wire [31:0] oddw_evnodd_1 = _oddw_T_2[127:96]; // @[VAluInt.scala 661:21]
- wire [31:0] oddw_evnodd_0 = _oddw_T_2[63:32]; // @[VAluInt.scala 661:21]
- wire [255:0] oddw = {oddw_evnodd_7,oddw_evnodd_6,oddw_evnodd_5,oddw_evnodd_4,oddw_evnodd_3,oddw_evnodd_2,oddw_evnodd_1
- ,oddw_evnodd_0}; // @[VAluInt.scala 671:22]
- wire [255:0] odd1 = _odd1_T | oddw; // @[VAluInt.scala 685:26]
- wire [7:0] zip1__31 = _T_95[255:248]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__30 = _T_92[255:248]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__29 = _T_95[247:240]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__28 = _T_92[247:240]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__27 = _T_95[239:232]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__26 = _T_92[239:232]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__25 = _T_95[231:224]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__24 = _T_92[231:224]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__23 = _T_95[223:216]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__22 = _T_92[223:216]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__21 = _T_95[215:208]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__20 = _T_92[215:208]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__19 = _T_95[207:200]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__18 = _T_92[207:200]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__17 = _T_95[199:192]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__16 = _T_92[199:192]; // @[VAluInt.scala 705:21]
- wire [63:0] out1_hi_lo = {zip1__23,zip1__22,zip1__21,zip1__20,zip1__19,zip1__18,zip1__17,zip1__16}; // @[VAluInt.scala 713:21]
- wire [7:0] zip1__15 = _T_95[191:184]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__14 = _T_92[191:184]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__13 = _T_95[183:176]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__12 = _T_92[183:176]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__11 = _T_95[175:168]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__10 = _T_92[175:168]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__9 = _T_95[167:160]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__8 = _T_92[167:160]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__7 = _T_95[159:152]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__6 = _T_92[159:152]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__5 = _T_95[151:144]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__4 = _T_92[151:144]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__3 = _T_95[143:136]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__2 = _T_92[143:136]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__1 = _T_95[135:128]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__0 = _T_92[135:128]; // @[VAluInt.scala 705:21]
- wire [63:0] out1_lo_lo = {zip1__7,zip1__6,zip1__5,zip1__4,zip1__3,zip1__2,zip1__1,zip1__0}; // @[VAluInt.scala 713:21]
- wire [127:0] out1_lo = {zip1__15,zip1__14,zip1__13,zip1__12,zip1__11,zip1__10,zip1__9,zip1__8,out1_lo_lo}; // @[VAluInt.scala 713:21]
- wire [255:0] zipb1 = {zip1__31,zip1__30,zip1__29,zip1__28,zip1__27,zip1__26,zip1__25,zip1__24,out1_hi_lo,out1_lo}; // @[VAluInt.scala 713:21]
- wire [15:0] zip1_1_15 = _T_101[255:240]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_14 = _T_98[255:240]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_13 = _T_101[239:224]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_12 = _T_98[239:224]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_11 = _T_101[223:208]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_10 = _T_98[223:208]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_9 = _T_101[207:192]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_8 = _T_98[207:192]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_7 = _T_101[191:176]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_6 = _T_98[191:176]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_5 = _T_101[175:160]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_4 = _T_98[175:160]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_3 = _T_101[159:144]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_2 = _T_98[159:144]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_1 = _T_101[143:128]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_0 = _T_98[143:128]; // @[VAluInt.scala 705:21]
- wire [127:0] out1_lo_1 = {zip1_1_7,zip1_1_6,zip1_1_5,zip1_1_4,zip1_1_3,zip1_1_2,zip1_1_1,zip1_1_0}; // @[VAluInt.scala 713:21]
- wire [255:0] ziph1 = {zip1_1_15,zip1_1_14,zip1_1_13,zip1_1_12,zip1_1_11,zip1_1_10,zip1_1_9,zip1_1_8,out1_lo_1}; // @[VAluInt.scala 713:21]
- wire [255:0] _zip1_T = zipb1 | ziph1; // @[VAluInt.scala 725:20]
- wire [31:0] zip1_2_7 = _T_107[255:224]; // @[VAluInt.scala 708:21]
- wire [31:0] zip1_2_6 = _T_104[255:224]; // @[VAluInt.scala 705:21]
- wire [31:0] zip1_2_5 = _T_107[223:192]; // @[VAluInt.scala 708:21]
- wire [31:0] zip1_2_4 = _T_104[223:192]; // @[VAluInt.scala 705:21]
- wire [31:0] zip1_2_3 = _T_107[191:160]; // @[VAluInt.scala 708:21]
- wire [31:0] zip1_2_2 = _T_104[191:160]; // @[VAluInt.scala 705:21]
- wire [31:0] zip1_2_1 = _T_107[159:128]; // @[VAluInt.scala 708:21]
- wire [31:0] zip1_2_0 = _T_104[159:128]; // @[VAluInt.scala 705:21]
- wire [255:0] zipw1 = {zip1_2_7,zip1_2_6,zip1_2_5,zip1_2_4,zip1_2_3,zip1_2_2,zip1_2_1,zip1_2_0}; // @[VAluInt.scala 713:21]
- wire [255:0] zip1_3 = _zip1_T | zipw1; // @[VAluInt.scala 725:28]
- wire [255:0] _load_1_T = odd1 | zip1_3; // @[VAluInt.scala 743:19]
- wire _slidenb1_T_5 = slidehn2 & sz[0]; // @[VAluInt.scala 599:96]
- wire [255:0] _slidenb1_T_6 = _slidenb1_T_5 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidenb1_in_32 = _slidenb1_T_6[7:0]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenb1_T_3 = _slidenb1_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidenb1_in_31 = _slidenb1_T_3[255:248]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_30 = _slidenb1_T_3[247:240]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_29 = _slidenb1_T_3[239:232]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_28 = _slidenb1_T_3[231:224]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_27 = _slidenb1_T_3[223:216]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_26 = _slidenb1_T_3[215:208]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_25 = _slidenb1_T_3[207:200]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_24 = _slidenb1_T_3[199:192]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_23 = _slidenb1_T_3[191:184]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_22 = _slidenb1_T_3[183:176]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_21 = _slidenb1_T_3[175:168]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_20 = _slidenb1_T_3[167:160]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_19 = _slidenb1_T_3[159:152]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_18 = _slidenb1_T_3[151:144]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_17 = _slidenb1_T_3[143:136]; // @[VAluInt.scala 538:23]
- wire [63:0] slidenb1_out_hi_lo = {slidenb1_in_24,slidenb1_in_23,slidenb1_in_22,slidenb1_in_21,slidenb1_in_20,
- slidenb1_in_19,slidenb1_in_18,slidenb1_in_17}; // @[VAluInt.scala 549:40]
- wire [7:0] slidenb1_in_16 = _slidenb1_T_3[135:128]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_15 = _slidenb1_T_3[127:120]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_14 = _slidenb1_T_3[119:112]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_13 = _slidenb1_T_3[111:104]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_12 = _slidenb1_T_3[103:96]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_11 = _slidenb1_T_3[95:88]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_10 = _slidenb1_T_3[87:80]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_9 = _slidenb1_T_3[79:72]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_8 = _slidenb1_T_3[71:64]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_7 = _slidenb1_T_3[63:56]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_6 = _slidenb1_T_3[55:48]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_5 = _slidenb1_T_3[47:40]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_4 = _slidenb1_T_3[39:32]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_3 = _slidenb1_T_3[31:24]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_2 = _slidenb1_T_3[23:16]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_1 = _slidenb1_T_3[15:8]; // @[VAluInt.scala 538:23]
- wire [63:0] slidenb1_out_lo_lo = {slidenb1_in_8,slidenb1_in_7,slidenb1_in_6,slidenb1_in_5,slidenb1_in_4,slidenb1_in_3,
- slidenb1_in_2,slidenb1_in_1}; // @[VAluInt.scala 549:40]
- wire [127:0] slidenb1_out_lo = {slidenb1_in_16,slidenb1_in_15,slidenb1_in_14,slidenb1_in_13,slidenb1_in_12,
- slidenb1_in_11,slidenb1_in_10,slidenb1_in_9,slidenb1_out_lo_lo}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenb1_out_T_1 = {slidenb1_in_32,slidenb1_in_31,slidenb1_in_30,slidenb1_in_29,slidenb1_in_28,
- slidenb1_in_27,slidenb1_in_26,slidenb1_in_25,slidenb1_out_hi_lo,slidenb1_out_lo}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenb1_out_T_2 = _slidenb0_out_T ? _slidenb1_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidenb1_in_33 = _slidenb1_T_6[15:8]; // @[VAluInt.scala 539:23]
- wire [63:0] slidenb1_out_hi_lo_1 = {slidenb1_in_25,slidenb1_in_24,slidenb1_in_23,slidenb1_in_22,slidenb1_in_21,
- slidenb1_in_20,slidenb1_in_19,slidenb1_in_18}; // @[VAluInt.scala 550:40]
- wire [63:0] slidenb1_out_lo_lo_1 = {slidenb1_in_9,slidenb1_in_8,slidenb1_in_7,slidenb1_in_6,slidenb1_in_5,
- slidenb1_in_4,slidenb1_in_3,slidenb1_in_2}; // @[VAluInt.scala 550:40]
- wire [127:0] slidenb1_out_lo_1 = {slidenb1_in_17,slidenb1_in_16,slidenb1_in_15,slidenb1_in_14,slidenb1_in_13,
- slidenb1_in_12,slidenb1_in_11,slidenb1_in_10,slidenb1_out_lo_lo_1}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenb1_out_T_4 = {slidenb1_in_33,slidenb1_in_32,slidenb1_in_31,slidenb1_in_30,slidenb1_in_29,
- slidenb1_in_28,slidenb1_in_27,slidenb1_in_26,slidenb1_out_hi_lo_1,slidenb1_out_lo_1}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenb1_out_T_5 = _slidenb0_out_T_3 ? _slidenb1_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenb1_out_T_6 = _slidenb1_out_T_2 | _slidenb1_out_T_5; // @[VAluInt.scala 549:48]
- wire [7:0] slidenb1_in_34 = _slidenb1_T_6[23:16]; // @[VAluInt.scala 539:23]
- wire [63:0] slidenb1_out_hi_lo_2 = {slidenb1_in_26,slidenb1_in_25,slidenb1_in_24,slidenb1_in_23,slidenb1_in_22,
- slidenb1_in_21,slidenb1_in_20,slidenb1_in_19}; // @[VAluInt.scala 551:40]
- wire [63:0] slidenb1_out_lo_lo_2 = {slidenb1_in_10,slidenb1_in_9,slidenb1_in_8,slidenb1_in_7,slidenb1_in_6,
- slidenb1_in_5,slidenb1_in_4,slidenb1_in_3}; // @[VAluInt.scala 551:40]
- wire [127:0] slidenb1_out_lo_2 = {slidenb1_in_18,slidenb1_in_17,slidenb1_in_16,slidenb1_in_15,slidenb1_in_14,
- slidenb1_in_13,slidenb1_in_12,slidenb1_in_11,slidenb1_out_lo_lo_2}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenb1_out_T_8 = {slidenb1_in_34,slidenb1_in_33,slidenb1_in_32,slidenb1_in_31,slidenb1_in_30,
- slidenb1_in_29,slidenb1_in_28,slidenb1_in_27,slidenb1_out_hi_lo_2,slidenb1_out_lo_2}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenb1_out_T_9 = _slidenb0_out_T_7 ? _slidenb1_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenb1_out_T_10 = _slidenb1_out_T_6 | _slidenb1_out_T_9; // @[VAluInt.scala 550:48]
- wire [7:0] slidenb1_in_35 = _slidenb1_T_6[31:24]; // @[VAluInt.scala 539:23]
- wire [63:0] slidenb1_out_hi_lo_3 = {slidenb1_in_27,slidenb1_in_26,slidenb1_in_25,slidenb1_in_24,slidenb1_in_23,
- slidenb1_in_22,slidenb1_in_21,slidenb1_in_20}; // @[VAluInt.scala 552:40]
- wire [63:0] slidenb1_out_lo_lo_3 = {slidenb1_in_11,slidenb1_in_10,slidenb1_in_9,slidenb1_in_8,slidenb1_in_7,
- slidenb1_in_6,slidenb1_in_5,slidenb1_in_4}; // @[VAluInt.scala 552:40]
- wire [127:0] slidenb1_out_lo_3 = {slidenb1_in_19,slidenb1_in_18,slidenb1_in_17,slidenb1_in_16,slidenb1_in_15,
- slidenb1_in_14,slidenb1_in_13,slidenb1_in_12,slidenb1_out_lo_lo_3}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenb1_out_T_12 = {slidenb1_in_35,slidenb1_in_34,slidenb1_in_33,slidenb1_in_32,slidenb1_in_31,
- slidenb1_in_30,slidenb1_in_29,slidenb1_in_28,slidenb1_out_hi_lo_3,slidenb1_out_lo_3}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenb1_out_T_13 = _slidenb0_out_T_11 ? _slidenb1_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidenb1 = _slidenb1_out_T_10 | _slidenb1_out_T_13; // @[VAluInt.scala 551:48]
- wire _slidenh1_T_5 = slidehn2 & sz[1]; // @[VAluInt.scala 600:96]
- wire [255:0] _slidenh1_T_6 = _slidenh1_T_5 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slidenh1_in_16 = _slidenh1_T_6[15:0]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenh1_T_3 = _slidenh1_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slidenh1_in_15 = _slidenh1_T_3[255:240]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_14 = _slidenh1_T_3[239:224]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_13 = _slidenh1_T_3[223:208]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_12 = _slidenh1_T_3[207:192]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_11 = _slidenh1_T_3[191:176]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_10 = _slidenh1_T_3[175:160]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_9 = _slidenh1_T_3[159:144]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_8 = _slidenh1_T_3[143:128]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_7 = _slidenh1_T_3[127:112]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_6 = _slidenh1_T_3[111:96]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_5 = _slidenh1_T_3[95:80]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_4 = _slidenh1_T_3[79:64]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_3 = _slidenh1_T_3[63:48]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_2 = _slidenh1_T_3[47:32]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_1 = _slidenh1_T_3[31:16]; // @[VAluInt.scala 538:23]
- wire [127:0] slidenh1_out_lo = {slidenh1_in_8,slidenh1_in_7,slidenh1_in_6,slidenh1_in_5,slidenh1_in_4,slidenh1_in_3,
- slidenh1_in_2,slidenh1_in_1}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenh1_out_T_1 = {slidenh1_in_16,slidenh1_in_15,slidenh1_in_14,slidenh1_in_13,slidenh1_in_12,
- slidenh1_in_11,slidenh1_in_10,slidenh1_in_9,slidenh1_out_lo}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenh1_out_T_2 = _slidenb0_out_T ? _slidenh1_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slidenh1_in_17 = _slidenh1_T_6[31:16]; // @[VAluInt.scala 539:23]
- wire [127:0] slidenh1_out_lo_1 = {slidenh1_in_9,slidenh1_in_8,slidenh1_in_7,slidenh1_in_6,slidenh1_in_5,slidenh1_in_4,
- slidenh1_in_3,slidenh1_in_2}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenh1_out_T_4 = {slidenh1_in_17,slidenh1_in_16,slidenh1_in_15,slidenh1_in_14,slidenh1_in_13,
- slidenh1_in_12,slidenh1_in_11,slidenh1_in_10,slidenh1_out_lo_1}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenh1_out_T_5 = _slidenb0_out_T_3 ? _slidenh1_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenh1_out_T_6 = _slidenh1_out_T_2 | _slidenh1_out_T_5; // @[VAluInt.scala 549:48]
- wire [15:0] slidenh1_in_18 = _slidenh1_T_6[47:32]; // @[VAluInt.scala 539:23]
- wire [127:0] slidenh1_out_lo_2 = {slidenh1_in_10,slidenh1_in_9,slidenh1_in_8,slidenh1_in_7,slidenh1_in_6,slidenh1_in_5
- ,slidenh1_in_4,slidenh1_in_3}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenh1_out_T_8 = {slidenh1_in_18,slidenh1_in_17,slidenh1_in_16,slidenh1_in_15,slidenh1_in_14,
- slidenh1_in_13,slidenh1_in_12,slidenh1_in_11,slidenh1_out_lo_2}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenh1_out_T_9 = _slidenb0_out_T_7 ? _slidenh1_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenh1_out_T_10 = _slidenh1_out_T_6 | _slidenh1_out_T_9; // @[VAluInt.scala 550:48]
- wire [15:0] slidenh1_in_19 = _slidenh1_T_6[63:48]; // @[VAluInt.scala 539:23]
- wire [127:0] slidenh1_out_lo_3 = {slidenh1_in_11,slidenh1_in_10,slidenh1_in_9,slidenh1_in_8,slidenh1_in_7,
- slidenh1_in_6,slidenh1_in_5,slidenh1_in_4}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenh1_out_T_12 = {slidenh1_in_19,slidenh1_in_18,slidenh1_in_17,slidenh1_in_16,slidenh1_in_15,
- slidenh1_in_14,slidenh1_in_13,slidenh1_in_12,slidenh1_out_lo_3}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenh1_out_T_13 = _slidenb0_out_T_11 ? _slidenh1_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidenh1 = _slidenh1_out_T_10 | _slidenh1_out_T_13; // @[VAluInt.scala 551:48]
- wire [255:0] _slide1_T = slidenb1 | slidenh1; // @[VAluInt.scala 614:25]
- wire _slidenw1_T_5 = slidehn2 & sz[2]; // @[VAluInt.scala 601:96]
- wire [255:0] _slidenw1_T_6 = _slidenw1_T_5 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidenw1_in_8 = _slidenw1_T_6[31:0]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw1_T_3 = _slidenw1_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidenw1_in_7 = _slidenw1_T_3[255:224]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw1_in_6 = _slidenw1_T_3[223:192]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw1_in_5 = _slidenw1_T_3[191:160]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw1_in_4 = _slidenw1_T_3[159:128]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw1_in_3 = _slidenw1_T_3[127:96]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw1_in_2 = _slidenw1_T_3[95:64]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw1_in_1 = _slidenw1_T_3[63:32]; // @[VAluInt.scala 538:23]
- wire [255:0] _slidenw1_out_T_1 = {slidenw1_in_8,slidenw1_in_7,slidenw1_in_6,slidenw1_in_5,slidenw1_in_4,slidenw1_in_3,
- slidenw1_in_2,slidenw1_in_1}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenw1_out_T_2 = _slidenb0_out_T ? _slidenw1_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidenw1_in_9 = _slidenw1_T_6[63:32]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw1_out_T_4 = {slidenw1_in_9,slidenw1_in_8,slidenw1_in_7,slidenw1_in_6,slidenw1_in_5,slidenw1_in_4,
- slidenw1_in_3,slidenw1_in_2}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenw1_out_T_5 = _slidenb0_out_T_3 ? _slidenw1_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenw1_out_T_6 = _slidenw1_out_T_2 | _slidenw1_out_T_5; // @[VAluInt.scala 549:48]
- wire [31:0] slidenw1_in_10 = _slidenw1_T_6[95:64]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw1_out_T_8 = {slidenw1_in_10,slidenw1_in_9,slidenw1_in_8,slidenw1_in_7,slidenw1_in_6,slidenw1_in_5
- ,slidenw1_in_4,slidenw1_in_3}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenw1_out_T_9 = _slidenb0_out_T_7 ? _slidenw1_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenw1_out_T_10 = _slidenw1_out_T_6 | _slidenw1_out_T_9; // @[VAluInt.scala 550:48]
- wire [31:0] slidenw1_in_11 = _slidenw1_T_6[127:96]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw1_out_T_12 = {slidenw1_in_11,slidenw1_in_10,slidenw1_in_9,slidenw1_in_8,slidenw1_in_7,
- slidenw1_in_6,slidenw1_in_5,slidenw1_in_4}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenw1_out_T_13 = _slidenb0_out_T_11 ? _slidenw1_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidenw1 = _slidenw1_out_T_10 | _slidenw1_out_T_13; // @[VAluInt.scala 551:48]
- wire [255:0] _slide1_T_1 = _slide1_T | slidenw1; // @[VAluInt.scala 614:36]
- wire _slidepb1_T_5 = slidehp2 & sz[0]; // @[VAluInt.scala 607:96]
- wire [255:0] _slidepb1_T_6 = _slidepb1_T_5 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidepb1_in_62 = _slidepb1_T_6[247:240]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_61 = _slidepb1_T_6[239:232]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_60 = _slidepb1_T_6[231:224]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_59 = _slidepb1_T_6[223:216]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_58 = _slidepb1_T_6[215:208]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_57 = _slidepb1_T_6[207:200]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_56 = _slidepb1_T_6[199:192]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_55 = _slidepb1_T_6[191:184]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_54 = _slidepb1_T_6[183:176]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_53 = _slidepb1_T_6[175:168]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_52 = _slidepb1_T_6[167:160]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_51 = _slidepb1_T_6[159:152]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_50 = _slidepb1_T_6[151:144]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_49 = _slidepb1_T_6[143:136]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_48 = _slidepb1_T_6[135:128]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_47 = _slidepb1_T_6[127:120]; // @[VAluInt.scala 576:23]
- wire [63:0] slidepb1_out_hi_lo = {slidepb1_in_54,slidepb1_in_53,slidepb1_in_52,slidepb1_in_51,slidepb1_in_50,
- slidepb1_in_49,slidepb1_in_48,slidepb1_in_47}; // @[VAluInt.scala 586:40]
- wire [7:0] slidepb1_in_46 = _slidepb1_T_6[119:112]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_45 = _slidepb1_T_6[111:104]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_44 = _slidepb1_T_6[103:96]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_43 = _slidepb1_T_6[95:88]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_42 = _slidepb1_T_6[87:80]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_41 = _slidepb1_T_6[79:72]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_40 = _slidepb1_T_6[71:64]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_39 = _slidepb1_T_6[63:56]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_38 = _slidepb1_T_6[55:48]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_37 = _slidepb1_T_6[47:40]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_36 = _slidepb1_T_6[39:32]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_35 = _slidepb1_T_6[31:24]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_34 = _slidepb1_T_6[23:16]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_33 = _slidepb1_T_6[15:8]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_32 = _slidepb1_T_6[7:0]; // @[VAluInt.scala 576:23]
- wire [255:0] _slidepb1_T_3 = _slidepb1_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidepb1_in_31 = _slidepb1_T_3[255:248]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb1_out_lo_lo = {slidepb1_in_38,slidepb1_in_37,slidepb1_in_36,slidepb1_in_35,slidepb1_in_34,
- slidepb1_in_33,slidepb1_in_32,slidepb1_in_31}; // @[VAluInt.scala 586:40]
- wire [127:0] slidepb1_out_lo = {slidepb1_in_46,slidepb1_in_45,slidepb1_in_44,slidepb1_in_43,slidepb1_in_42,
- slidepb1_in_41,slidepb1_in_40,slidepb1_in_39,slidepb1_out_lo_lo}; // @[VAluInt.scala 586:40]
- wire [255:0] _slidepb1_out_T_1 = {slidepb1_in_62,slidepb1_in_61,slidepb1_in_60,slidepb1_in_59,slidepb1_in_58,
- slidepb1_in_57,slidepb1_in_56,slidepb1_in_55,slidepb1_out_hi_lo,slidepb1_out_lo}; // @[VAluInt.scala 586:40]
- wire [255:0] _slidepb1_out_T_2 = _slidenb0_out_T ? _slidepb1_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [63:0] slidepb1_out_hi_lo_1 = {slidepb1_in_53,slidepb1_in_52,slidepb1_in_51,slidepb1_in_50,slidepb1_in_49,
- slidepb1_in_48,slidepb1_in_47,slidepb1_in_46}; // @[VAluInt.scala 587:40]
- wire [7:0] slidepb1_in_30 = _slidepb1_T_3[247:240]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb1_out_lo_lo_1 = {slidepb1_in_37,slidepb1_in_36,slidepb1_in_35,slidepb1_in_34,slidepb1_in_33,
- slidepb1_in_32,slidepb1_in_31,slidepb1_in_30}; // @[VAluInt.scala 587:40]
- wire [127:0] slidepb1_out_lo_1 = {slidepb1_in_45,slidepb1_in_44,slidepb1_in_43,slidepb1_in_42,slidepb1_in_41,
- slidepb1_in_40,slidepb1_in_39,slidepb1_in_38,slidepb1_out_lo_lo_1}; // @[VAluInt.scala 587:40]
- wire [255:0] _slidepb1_out_T_4 = {slidepb1_in_61,slidepb1_in_60,slidepb1_in_59,slidepb1_in_58,slidepb1_in_57,
- slidepb1_in_56,slidepb1_in_55,slidepb1_in_54,slidepb1_out_hi_lo_1,slidepb1_out_lo_1}; // @[VAluInt.scala 587:40]
- wire [255:0] _slidepb1_out_T_5 = _slidenb0_out_T_3 ? _slidepb1_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepb1_out_T_6 = _slidepb1_out_T_2 | _slidepb1_out_T_5; // @[VAluInt.scala 586:48]
- wire [63:0] slidepb1_out_hi_lo_2 = {slidepb1_in_52,slidepb1_in_51,slidepb1_in_50,slidepb1_in_49,slidepb1_in_48,
- slidepb1_in_47,slidepb1_in_46,slidepb1_in_45}; // @[VAluInt.scala 588:40]
- wire [7:0] slidepb1_in_29 = _slidepb1_T_3[239:232]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb1_out_lo_lo_2 = {slidepb1_in_36,slidepb1_in_35,slidepb1_in_34,slidepb1_in_33,slidepb1_in_32,
- slidepb1_in_31,slidepb1_in_30,slidepb1_in_29}; // @[VAluInt.scala 588:40]
- wire [127:0] slidepb1_out_lo_2 = {slidepb1_in_44,slidepb1_in_43,slidepb1_in_42,slidepb1_in_41,slidepb1_in_40,
- slidepb1_in_39,slidepb1_in_38,slidepb1_in_37,slidepb1_out_lo_lo_2}; // @[VAluInt.scala 588:40]
- wire [255:0] _slidepb1_out_T_8 = {slidepb1_in_60,slidepb1_in_59,slidepb1_in_58,slidepb1_in_57,slidepb1_in_56,
- slidepb1_in_55,slidepb1_in_54,slidepb1_in_53,slidepb1_out_hi_lo_2,slidepb1_out_lo_2}; // @[VAluInt.scala 588:40]
- wire [255:0] _slidepb1_out_T_9 = _slidenb0_out_T_7 ? _slidepb1_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepb1_out_T_10 = _slidepb1_out_T_6 | _slidepb1_out_T_9; // @[VAluInt.scala 587:48]
- wire [63:0] slidepb1_out_hi_lo_3 = {slidepb1_in_51,slidepb1_in_50,slidepb1_in_49,slidepb1_in_48,slidepb1_in_47,
- slidepb1_in_46,slidepb1_in_45,slidepb1_in_44}; // @[VAluInt.scala 589:40]
- wire [7:0] slidepb1_in_28 = _slidepb1_T_3[231:224]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb1_out_lo_lo_3 = {slidepb1_in_35,slidepb1_in_34,slidepb1_in_33,slidepb1_in_32,slidepb1_in_31,
- slidepb1_in_30,slidepb1_in_29,slidepb1_in_28}; // @[VAluInt.scala 589:40]
- wire [127:0] slidepb1_out_lo_3 = {slidepb1_in_43,slidepb1_in_42,slidepb1_in_41,slidepb1_in_40,slidepb1_in_39,
- slidepb1_in_38,slidepb1_in_37,slidepb1_in_36,slidepb1_out_lo_lo_3}; // @[VAluInt.scala 589:40]
- wire [255:0] _slidepb1_out_T_12 = {slidepb1_in_59,slidepb1_in_58,slidepb1_in_57,slidepb1_in_56,slidepb1_in_55,
- slidepb1_in_54,slidepb1_in_53,slidepb1_in_52,slidepb1_out_hi_lo_3,slidepb1_out_lo_3}; // @[VAluInt.scala 589:40]
- wire [255:0] _slidepb1_out_T_13 = _slidenb0_out_T_11 ? _slidepb1_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidepb1 = _slidepb1_out_T_10 | _slidepb1_out_T_13; // @[VAluInt.scala 588:48]
- wire [255:0] _slide1_T_2 = _slide1_T_1 | slidepb1; // @[VAluInt.scala 614:47]
- wire _slideph1_T_5 = slidehp2 & sz[1]; // @[VAluInt.scala 608:96]
- wire [255:0] _slideph1_T_6 = _slideph1_T_5 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slideph1_in_30 = _slideph1_T_6[239:224]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_29 = _slideph1_T_6[223:208]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_28 = _slideph1_T_6[207:192]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_27 = _slideph1_T_6[191:176]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_26 = _slideph1_T_6[175:160]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_25 = _slideph1_T_6[159:144]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_24 = _slideph1_T_6[143:128]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_23 = _slideph1_T_6[127:112]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_22 = _slideph1_T_6[111:96]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_21 = _slideph1_T_6[95:80]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_20 = _slideph1_T_6[79:64]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_19 = _slideph1_T_6[63:48]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_18 = _slideph1_T_6[47:32]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_17 = _slideph1_T_6[31:16]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_16 = _slideph1_T_6[15:0]; // @[VAluInt.scala 576:23]
- wire [255:0] _slideph1_T_3 = _slideph1_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slideph1_in_15 = _slideph1_T_3[255:240]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph1_out_lo = {slideph1_in_22,slideph1_in_21,slideph1_in_20,slideph1_in_19,slideph1_in_18,
- slideph1_in_17,slideph1_in_16,slideph1_in_15}; // @[VAluInt.scala 586:40]
- wire [255:0] _slideph1_out_T_1 = {slideph1_in_30,slideph1_in_29,slideph1_in_28,slideph1_in_27,slideph1_in_26,
- slideph1_in_25,slideph1_in_24,slideph1_in_23,slideph1_out_lo}; // @[VAluInt.scala 586:40]
- wire [255:0] _slideph1_out_T_2 = _slidenb0_out_T ? _slideph1_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slideph1_in_14 = _slideph1_T_3[239:224]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph1_out_lo_1 = {slideph1_in_21,slideph1_in_20,slideph1_in_19,slideph1_in_18,slideph1_in_17,
- slideph1_in_16,slideph1_in_15,slideph1_in_14}; // @[VAluInt.scala 587:40]
- wire [255:0] _slideph1_out_T_4 = {slideph1_in_29,slideph1_in_28,slideph1_in_27,slideph1_in_26,slideph1_in_25,
- slideph1_in_24,slideph1_in_23,slideph1_in_22,slideph1_out_lo_1}; // @[VAluInt.scala 587:40]
- wire [255:0] _slideph1_out_T_5 = _slidenb0_out_T_3 ? _slideph1_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slideph1_out_T_6 = _slideph1_out_T_2 | _slideph1_out_T_5; // @[VAluInt.scala 586:48]
- wire [15:0] slideph1_in_13 = _slideph1_T_3[223:208]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph1_out_lo_2 = {slideph1_in_20,slideph1_in_19,slideph1_in_18,slideph1_in_17,slideph1_in_16,
- slideph1_in_15,slideph1_in_14,slideph1_in_13}; // @[VAluInt.scala 588:40]
- wire [255:0] _slideph1_out_T_8 = {slideph1_in_28,slideph1_in_27,slideph1_in_26,slideph1_in_25,slideph1_in_24,
- slideph1_in_23,slideph1_in_22,slideph1_in_21,slideph1_out_lo_2}; // @[VAluInt.scala 588:40]
- wire [255:0] _slideph1_out_T_9 = _slidenb0_out_T_7 ? _slideph1_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slideph1_out_T_10 = _slideph1_out_T_6 | _slideph1_out_T_9; // @[VAluInt.scala 587:48]
- wire [15:0] slideph1_in_12 = _slideph1_T_3[207:192]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph1_out_lo_3 = {slideph1_in_19,slideph1_in_18,slideph1_in_17,slideph1_in_16,slideph1_in_15,
- slideph1_in_14,slideph1_in_13,slideph1_in_12}; // @[VAluInt.scala 589:40]
- wire [255:0] _slideph1_out_T_12 = {slideph1_in_27,slideph1_in_26,slideph1_in_25,slideph1_in_24,slideph1_in_23,
- slideph1_in_22,slideph1_in_21,slideph1_in_20,slideph1_out_lo_3}; // @[VAluInt.scala 589:40]
- wire [255:0] _slideph1_out_T_13 = _slidenb0_out_T_11 ? _slideph1_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slideph1 = _slideph1_out_T_10 | _slideph1_out_T_13; // @[VAluInt.scala 588:48]
- wire [255:0] _slide1_T_3 = _slide1_T_2 | slideph1; // @[VAluInt.scala 615:25]
- wire _slidepw1_T_5 = slidehp2 & sz[2]; // @[VAluInt.scala 609:96]
- wire [255:0] _slidepw1_T_6 = _slidepw1_T_5 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidepw1_in_14 = _slidepw1_T_6[223:192]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw1_in_13 = _slidepw1_T_6[191:160]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw1_in_12 = _slidepw1_T_6[159:128]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw1_in_11 = _slidepw1_T_6[127:96]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw1_in_10 = _slidepw1_T_6[95:64]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw1_in_9 = _slidepw1_T_6[63:32]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw1_in_8 = _slidepw1_T_6[31:0]; // @[VAluInt.scala 576:23]
- wire [255:0] _slidepw1_T_3 = _slidepw1_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidepw1_in_7 = _slidepw1_T_3[255:224]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw1_out_T_1 = {slidepw1_in_14,slidepw1_in_13,slidepw1_in_12,slidepw1_in_11,slidepw1_in_10,
- slidepw1_in_9,slidepw1_in_8,slidepw1_in_7}; // @[VAluInt.scala 586:40]
- wire [255:0] _slidepw1_out_T_2 = _slidenb0_out_T ? _slidepw1_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidepw1_in_6 = _slidepw1_T_3[223:192]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw1_out_T_4 = {slidepw1_in_13,slidepw1_in_12,slidepw1_in_11,slidepw1_in_10,slidepw1_in_9,
- slidepw1_in_8,slidepw1_in_7,slidepw1_in_6}; // @[VAluInt.scala 587:40]
- wire [255:0] _slidepw1_out_T_5 = _slidenb0_out_T_3 ? _slidepw1_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepw1_out_T_6 = _slidepw1_out_T_2 | _slidepw1_out_T_5; // @[VAluInt.scala 586:48]
- wire [31:0] slidepw1_in_5 = _slidepw1_T_3[191:160]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw1_out_T_8 = {slidepw1_in_12,slidepw1_in_11,slidepw1_in_10,slidepw1_in_9,slidepw1_in_8,
- slidepw1_in_7,slidepw1_in_6,slidepw1_in_5}; // @[VAluInt.scala 588:40]
- wire [255:0] _slidepw1_out_T_9 = _slidenb0_out_T_7 ? _slidepw1_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepw1_out_T_10 = _slidepw1_out_T_6 | _slidepw1_out_T_9; // @[VAluInt.scala 587:48]
- wire [31:0] slidepw1_in_4 = _slidepw1_T_3[159:128]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw1_out_T_12 = {slidepw1_in_11,slidepw1_in_10,slidepw1_in_9,slidepw1_in_8,slidepw1_in_7,
- slidepw1_in_6,slidepw1_in_5,slidepw1_in_4}; // @[VAluInt.scala 589:40]
- wire [255:0] _slidepw1_out_T_13 = _slidenb0_out_T_11 ? _slidepw1_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidepw1 = _slidepw1_out_T_10 | _slidepw1_out_T_13; // @[VAluInt.scala 588:48]
- wire [255:0] slide1 = _slide1_T_3 | slidepw1; // @[VAluInt.scala 615:36]
- wire [255:0] _load_1_T_1 = _load_1_T | slide1; // @[VAluInt.scala 743:26]
- wire as_45 = adatac_0_7[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_182 = {as_45,adatac_0_7[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_45 = $signed(_aval_T_182) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_45 = bdatac_0_7[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_182 = {bs_45,bdatac_0_7[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_45 = $signed(_bval_T_182) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_45 = $signed(aval_45) * $signed(bval_45); // @[VDot.scala 172:25]
- wire as_46 = adatac_1_7[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_186 = {as_46,adatac_1_7[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_46 = $signed(_aval_T_186) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_46 = bdatac_1_7[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_186 = {bs_46,bdatac_1_7[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_46 = $signed(_bval_T_186) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_46 = $signed(aval_46) * $signed(bval_46); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_15 = $signed(mval_45) + $signed(mval_46); // @[VDot.scala 180:26]
- wire as_47 = adatac_2_7[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_190 = {as_47,adatac_2_7[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_47 = $signed(_aval_T_190) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_47 = bdatac_2_7[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_190 = {bs_47,bdatac_2_7[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_47 = $signed(_bval_T_190) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_47 = $signed(aval_47) * $signed(bval_47); // @[VDot.scala 172:25]
- wire [20:0] _GEN_102 = {{1{mval_47[19]}},mval_47}; // @[VDot.scala 180:37]
- wire [21:0] dotp_15 = $signed(_dotp_T_15) + $signed(_GEN_102); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_47 = dotp_15[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_15 = $signed(_dotp_T_15) + $signed(_GEN_102); // @[Cat.scala 31:58]
- wire as_39 = adatac_0_6[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_158 = {as_39,adatac_0_6[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_39 = $signed(_aval_T_158) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_39 = bdatac_0_6[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_158 = {bs_39,bdatac_0_6[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_39 = $signed(_bval_T_158) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_39 = $signed(aval_39) * $signed(bval_39); // @[VDot.scala 172:25]
- wire as_40 = adatac_1_6[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_162 = {as_40,adatac_1_6[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_40 = $signed(_aval_T_162) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_40 = bdatac_1_6[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_162 = {bs_40,bdatac_1_6[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_40 = $signed(_bval_T_162) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_40 = $signed(aval_40) * $signed(bval_40); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_13 = $signed(mval_39) + $signed(mval_40); // @[VDot.scala 180:26]
- wire as_41 = adatac_2_6[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_166 = {as_41,adatac_2_6[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_41 = $signed(_aval_T_166) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_41 = bdatac_2_6[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_166 = {bs_41,bdatac_2_6[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_41 = $signed(_bval_T_166) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_41 = $signed(aval_41) * $signed(bval_41); // @[VDot.scala 172:25]
- wire [20:0] _GEN_103 = {{1{mval_41[19]}},mval_41}; // @[VDot.scala 180:37]
- wire [21:0] dotp_13 = $signed(_dotp_T_13) + $signed(_GEN_103); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_41 = dotp_13[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_13 = $signed(_dotp_T_13) + $signed(_GEN_103); // @[Cat.scala 31:58]
- wire as_33 = adatac_0_5[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_134 = {as_33,adatac_0_5[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_33 = $signed(_aval_T_134) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_33 = bdatac_0_5[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_134 = {bs_33,bdatac_0_5[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_33 = $signed(_bval_T_134) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_33 = $signed(aval_33) * $signed(bval_33); // @[VDot.scala 172:25]
- wire as_34 = adatac_1_5[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_138 = {as_34,adatac_1_5[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_34 = $signed(_aval_T_138) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_34 = bdatac_1_5[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_138 = {bs_34,bdatac_1_5[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_34 = $signed(_bval_T_138) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_34 = $signed(aval_34) * $signed(bval_34); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_11 = $signed(mval_33) + $signed(mval_34); // @[VDot.scala 180:26]
- wire as_35 = adatac_2_5[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_142 = {as_35,adatac_2_5[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_35 = $signed(_aval_T_142) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_35 = bdatac_2_5[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_142 = {bs_35,bdatac_2_5[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_35 = $signed(_bval_T_142) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_35 = $signed(aval_35) * $signed(bval_35); // @[VDot.scala 172:25]
- wire [20:0] _GEN_104 = {{1{mval_35[19]}},mval_35}; // @[VDot.scala 180:37]
- wire [21:0] dotp_11 = $signed(_dotp_T_11) + $signed(_GEN_104); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_35 = dotp_11[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_11 = $signed(_dotp_T_11) + $signed(_GEN_104); // @[Cat.scala 31:58]
- wire as_27 = adatac_0_4[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_110 = {as_27,adatac_0_4[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_27 = $signed(_aval_T_110) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_27 = bdatac_0_4[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_110 = {bs_27,bdatac_0_4[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_27 = $signed(_bval_T_110) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_27 = $signed(aval_27) * $signed(bval_27); // @[VDot.scala 172:25]
- wire as_28 = adatac_1_4[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_114 = {as_28,adatac_1_4[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_28 = $signed(_aval_T_114) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_28 = bdatac_1_4[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_114 = {bs_28,bdatac_1_4[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_28 = $signed(_bval_T_114) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_28 = $signed(aval_28) * $signed(bval_28); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_9 = $signed(mval_27) + $signed(mval_28); // @[VDot.scala 180:26]
- wire as_29 = adatac_2_4[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_118 = {as_29,adatac_2_4[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_29 = $signed(_aval_T_118) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_29 = bdatac_2_4[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_118 = {bs_29,bdatac_2_4[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_29 = $signed(_bval_T_118) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_29 = $signed(aval_29) * $signed(bval_29); // @[VDot.scala 172:25]
- wire [20:0] _GEN_105 = {{1{mval_29[19]}},mval_29}; // @[VDot.scala 180:37]
- wire [21:0] dotp_9 = $signed(_dotp_T_9) + $signed(_GEN_105); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_29 = dotp_9[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_9 = $signed(_dotp_T_9) + $signed(_GEN_105); // @[Cat.scala 31:58]
- wire as_21 = adatac_0_3[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_86 = {as_21,adatac_0_3[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_21 = $signed(_aval_T_86) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_21 = bdatac_0_3[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_86 = {bs_21,bdatac_0_3[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_21 = $signed(_bval_T_86) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_21 = $signed(aval_21) * $signed(bval_21); // @[VDot.scala 172:25]
- wire as_22 = adatac_1_3[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_90 = {as_22,adatac_1_3[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_22 = $signed(_aval_T_90) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_22 = bdatac_1_3[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_90 = {bs_22,bdatac_1_3[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_22 = $signed(_bval_T_90) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_22 = $signed(aval_22) * $signed(bval_22); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_7 = $signed(mval_21) + $signed(mval_22); // @[VDot.scala 180:26]
- wire as_23 = adatac_2_3[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_94 = {as_23,adatac_2_3[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_23 = $signed(_aval_T_94) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_23 = bdatac_2_3[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_94 = {bs_23,bdatac_2_3[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_23 = $signed(_bval_T_94) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_23 = $signed(aval_23) * $signed(bval_23); // @[VDot.scala 172:25]
- wire [20:0] _GEN_106 = {{1{mval_23[19]}},mval_23}; // @[VDot.scala 180:37]
- wire [21:0] dotp_7 = $signed(_dotp_T_7) + $signed(_GEN_106); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_23 = dotp_7[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_7 = $signed(_dotp_T_7) + $signed(_GEN_106); // @[Cat.scala 31:58]
- wire as_15 = adatac_0_2[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_62 = {as_15,adatac_0_2[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_15 = $signed(_aval_T_62) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_15 = bdatac_0_2[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_62 = {bs_15,bdatac_0_2[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_15 = $signed(_bval_T_62) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_15 = $signed(aval_15) * $signed(bval_15); // @[VDot.scala 172:25]
- wire as_16 = adatac_1_2[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_66 = {as_16,adatac_1_2[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_16 = $signed(_aval_T_66) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_16 = bdatac_1_2[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_66 = {bs_16,bdatac_1_2[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_16 = $signed(_bval_T_66) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_16 = $signed(aval_16) * $signed(bval_16); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_5 = $signed(mval_15) + $signed(mval_16); // @[VDot.scala 180:26]
- wire as_17 = adatac_2_2[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_70 = {as_17,adatac_2_2[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_17 = $signed(_aval_T_70) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_17 = bdatac_2_2[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_70 = {bs_17,bdatac_2_2[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_17 = $signed(_bval_T_70) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_17 = $signed(aval_17) * $signed(bval_17); // @[VDot.scala 172:25]
- wire [20:0] _GEN_107 = {{1{mval_17[19]}},mval_17}; // @[VDot.scala 180:37]
- wire [21:0] dotp_5 = $signed(_dotp_T_5) + $signed(_GEN_107); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_17 = dotp_5[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_5 = $signed(_dotp_T_5) + $signed(_GEN_107); // @[Cat.scala 31:58]
- wire as_9 = adatac_0_1[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_38 = {as_9,adatac_0_1[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_9 = $signed(_aval_T_38) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_9 = bdatac_0_1[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_38 = {bs_9,bdatac_0_1[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_9 = $signed(_bval_T_38) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_9 = $signed(aval_9) * $signed(bval_9); // @[VDot.scala 172:25]
- wire as_10 = adatac_1_1[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_42 = {as_10,adatac_1_1[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_10 = $signed(_aval_T_42) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_10 = bdatac_1_1[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_42 = {bs_10,bdatac_1_1[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_10 = $signed(_bval_T_42) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_10 = $signed(aval_10) * $signed(bval_10); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_3 = $signed(mval_9) + $signed(mval_10); // @[VDot.scala 180:26]
- wire as_11 = adatac_2_1[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_46 = {as_11,adatac_2_1[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_11 = $signed(_aval_T_46) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_11 = bdatac_2_1[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_46 = {bs_11,bdatac_2_1[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_11 = $signed(_bval_T_46) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_11 = $signed(aval_11) * $signed(bval_11); // @[VDot.scala 172:25]
- wire [20:0] _GEN_108 = {{1{mval_11[19]}},mval_11}; // @[VDot.scala 180:37]
- wire [21:0] dotp_3 = $signed(_dotp_T_3) + $signed(_GEN_108); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_11 = dotp_3[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_3 = $signed(_dotp_T_3) + $signed(_GEN_108); // @[Cat.scala 31:58]
- wire as_3 = adatac_0_0[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_14 = {as_3,adatac_0_0[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_3 = $signed(_aval_T_14) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_3 = bdatac_0_0[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_14 = {bs_3,bdatac_0_0[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_3 = $signed(_bval_T_14) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_3 = $signed(aval_3) * $signed(bval_3); // @[VDot.scala 172:25]
- wire as_4 = adatac_1_0[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_18 = {as_4,adatac_1_0[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_4 = $signed(_aval_T_18) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_4 = bdatac_1_0[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_18 = {bs_4,bdatac_1_0[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_4 = $signed(_bval_T_18) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_4 = $signed(aval_4) * $signed(bval_4); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_1 = $signed(mval_3) + $signed(mval_4); // @[VDot.scala 180:26]
- wire as_5 = adatac_2_0[23] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_22 = {as_5,adatac_2_0[23:16]}; // @[VDot.scala 170:56]
- wire [9:0] aval_5 = $signed(_aval_T_22) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_5 = bdatac_2_0[23] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_22 = {bs_5,bdatac_2_0[23:16]}; // @[VDot.scala 171:56]
- wire [9:0] bval_5 = $signed(_bval_T_22) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_5 = $signed(aval_5) * $signed(bval_5); // @[VDot.scala 172:25]
- wire [20:0] _GEN_109 = {{1{mval_5[19]}},mval_5}; // @[VDot.scala 180:37]
- wire [21:0] dotp_1 = $signed(_dotp_T_1) + $signed(_GEN_109); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_5 = dotp_1[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_1 = $signed(_dotp_T_1) + $signed(_GEN_109); // @[Cat.scala 31:58]
- wire [127:0] out1_lo_3 = {_sdotp_T_23,sdotp_lo_7,_sdotp_T_17,sdotp_lo_5,_sdotp_T_11,sdotp_lo_3,_sdotp_T_5,sdotp_lo_1}; // @[VDot.scala 143:22]
- wire [255:0] dwconv1 = {_sdotp_T_47,sdotp_lo_15,_sdotp_T_41,sdotp_lo_13,_sdotp_T_35,sdotp_lo_11,_sdotp_T_29,sdotp_lo_9
- ,out1_lo_3}; // @[VDot.scala 143:22]
- wire [255:0] load_1 = _load_1_T_1 | dwconv1; // @[VAluInt.scala 743:35]
- wire [31:0] vddata_1 = valu_1_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [31:0] vddata_0 = valu_0_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [31:0] vddata_3 = valu_3_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [31:0] vddata_2 = valu_2_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [127:0] io_write_0_data_lo = {vddata_3,vddata_2,vddata_1,vddata_0}; // @[VAluInt.scala 757:30]
- wire [31:0] vddata_5 = valu_5_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [31:0] vddata_4 = valu_4_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [31:0] vddata_7 = valu_7_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [31:0] vddata_6 = valu_6_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [127:0] io_write_0_data_hi = {vddata_7,vddata_6,vddata_5,vddata_4}; // @[VAluInt.scala 757:30]
- wire [31:0] vedata_1 = valu_1_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [31:0] vedata_0 = valu_0_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [31:0] vedata_3 = valu_3_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [31:0] vedata_2 = valu_2_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [127:0] io_write_1_data_lo = {vedata_3,vedata_2,vedata_1,vedata_0}; // @[VAluInt.scala 761:30]
- wire [31:0] vedata_5 = valu_5_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [31:0] vedata_4 = valu_4_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [31:0] vedata_7 = valu_7_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [31:0] vedata_6 = valu_6_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [127:0] io_write_1_data_hi = {vedata_7,vedata_6,vedata_5,vedata_4}; // @[VAluInt.scala 761:30]
- VAluIntLane valu_0 ( // @[VAluInt.scala 418:11]
- .clock(valu_0_clock),
- .reset(valu_0_reset),
- .io_in_vdvalid(valu_0_io_in_vdvalid),
- .io_in_vevalid(valu_0_io_in_vevalid),
- .io_in_sz(valu_0_io_in_sz),
- .io_in_negative(valu_0_io_in_negative),
- .io_in_round(valu_0_io_in_round),
- .io_in_signed(valu_0_io_in_signed),
- .io_op_absd(valu_0_io_op_absd),
- .io_op_acc(valu_0_io_op_acc),
- .io_op_dup(valu_0_io_op_dup),
- .io_op_max(valu_0_io_op_max),
- .io_op_min(valu_0_io_op_min),
- .io_op_mv(valu_0_io_op_mv),
- .io_op_mv2(valu_0_io_op_mv2),
- .io_op_mvp(valu_0_io_op_mvp),
- .io_op_srans(valu_0_io_op_srans),
- .io_op_sraqs(valu_0_io_op_sraqs),
- .io_op_dwinit(valu_0_io_op_dwinit),
- .io_op_dwconv(valu_0_io_op_dwconv),
- .io_op_dwconvData(valu_0_io_op_dwconvData),
- .io_op_add_en(valu_0_io_op_add_en),
- .io_op_add_add(valu_0_io_op_add_add),
- .io_op_add_adds(valu_0_io_op_add_adds),
- .io_op_add_addw(valu_0_io_op_add_addw),
- .io_op_add_add3(valu_0_io_op_add_add3),
- .io_op_add_hadd(valu_0_io_op_add_hadd),
- .io_op_cmp_en(valu_0_io_op_cmp_en),
- .io_op_cmp_eq(valu_0_io_op_cmp_eq),
- .io_op_cmp_ne(valu_0_io_op_cmp_ne),
- .io_op_cmp_lt(valu_0_io_op_cmp_lt),
- .io_op_cmp_le(valu_0_io_op_cmp_le),
- .io_op_cmp_gt(valu_0_io_op_cmp_gt),
- .io_op_cmp_ge(valu_0_io_op_cmp_ge),
- .io_op_log_en(valu_0_io_op_log_en),
- .io_op_log_and(valu_0_io_op_log_and),
- .io_op_log_or(valu_0_io_op_log_or),
- .io_op_log_xor(valu_0_io_op_log_xor),
- .io_op_log_not(valu_0_io_op_log_not),
- .io_op_log_rev(valu_0_io_op_log_rev),
- .io_op_log_ror(valu_0_io_op_log_ror),
- .io_op_log_clb(valu_0_io_op_log_clb),
- .io_op_log_clz(valu_0_io_op_log_clz),
- .io_op_log_cpop(valu_0_io_op_log_cpop),
- .io_op_mul0_en(valu_0_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_0_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_0_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_0_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_0_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_0_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_0_io_op_mul0_madd),
- .io_op_mul1_en(valu_0_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_0_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_0_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_0_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_0_io_op_mul1_muls),
- .io_op_padd_en(valu_0_io_op_padd_en),
- .io_op_padd_add(valu_0_io_op_padd_add),
- .io_op_padd_sub(valu_0_io_op_padd_sub),
- .io_op_rsub_en(valu_0_io_op_rsub_en),
- .io_op_rsub_rsub(valu_0_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_0_io_op_shf_en_l),
- .io_op_shf_en_r(valu_0_io_op_shf_en_r),
- .io_op_shf_shl(valu_0_io_op_shf_shl),
- .io_op_shf_shr(valu_0_io_op_shf_shr),
- .io_op_shf_shf(valu_0_io_op_shf_shf),
- .io_op_sub_en(valu_0_io_op_sub_en),
- .io_op_sub_sub(valu_0_io_op_sub_sub),
- .io_op_sub_subs(valu_0_io_op_sub_subs),
- .io_op_sub_subw(valu_0_io_op_sub_subw),
- .io_op_sub_hsub(valu_0_io_op_sub_hsub),
- .io_read_0_data(valu_0_io_read_0_data),
- .io_read_1_data(valu_0_io_read_1_data),
- .io_read_2_data(valu_0_io_read_2_data),
- .io_read_3_data(valu_0_io_read_3_data),
- .io_read_5_data(valu_0_io_read_5_data),
- .io_write_0_data(valu_0_io_write_0_data),
- .io_write_1_data(valu_0_io_write_1_data),
- .io_load_0(valu_0_io_load_0),
- .io_load_1(valu_0_io_load_1)
- );
- VAluIntLane valu_1 ( // @[VAluInt.scala 418:11]
- .clock(valu_1_clock),
- .reset(valu_1_reset),
- .io_in_vdvalid(valu_1_io_in_vdvalid),
- .io_in_vevalid(valu_1_io_in_vevalid),
- .io_in_sz(valu_1_io_in_sz),
- .io_in_negative(valu_1_io_in_negative),
- .io_in_round(valu_1_io_in_round),
- .io_in_signed(valu_1_io_in_signed),
- .io_op_absd(valu_1_io_op_absd),
- .io_op_acc(valu_1_io_op_acc),
- .io_op_dup(valu_1_io_op_dup),
- .io_op_max(valu_1_io_op_max),
- .io_op_min(valu_1_io_op_min),
- .io_op_mv(valu_1_io_op_mv),
- .io_op_mv2(valu_1_io_op_mv2),
- .io_op_mvp(valu_1_io_op_mvp),
- .io_op_srans(valu_1_io_op_srans),
- .io_op_sraqs(valu_1_io_op_sraqs),
- .io_op_dwinit(valu_1_io_op_dwinit),
- .io_op_dwconv(valu_1_io_op_dwconv),
- .io_op_dwconvData(valu_1_io_op_dwconvData),
- .io_op_add_en(valu_1_io_op_add_en),
- .io_op_add_add(valu_1_io_op_add_add),
- .io_op_add_adds(valu_1_io_op_add_adds),
- .io_op_add_addw(valu_1_io_op_add_addw),
- .io_op_add_add3(valu_1_io_op_add_add3),
- .io_op_add_hadd(valu_1_io_op_add_hadd),
- .io_op_cmp_en(valu_1_io_op_cmp_en),
- .io_op_cmp_eq(valu_1_io_op_cmp_eq),
- .io_op_cmp_ne(valu_1_io_op_cmp_ne),
- .io_op_cmp_lt(valu_1_io_op_cmp_lt),
- .io_op_cmp_le(valu_1_io_op_cmp_le),
- .io_op_cmp_gt(valu_1_io_op_cmp_gt),
- .io_op_cmp_ge(valu_1_io_op_cmp_ge),
- .io_op_log_en(valu_1_io_op_log_en),
- .io_op_log_and(valu_1_io_op_log_and),
- .io_op_log_or(valu_1_io_op_log_or),
- .io_op_log_xor(valu_1_io_op_log_xor),
- .io_op_log_not(valu_1_io_op_log_not),
- .io_op_log_rev(valu_1_io_op_log_rev),
- .io_op_log_ror(valu_1_io_op_log_ror),
- .io_op_log_clb(valu_1_io_op_log_clb),
- .io_op_log_clz(valu_1_io_op_log_clz),
- .io_op_log_cpop(valu_1_io_op_log_cpop),
- .io_op_mul0_en(valu_1_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_1_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_1_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_1_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_1_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_1_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_1_io_op_mul0_madd),
- .io_op_mul1_en(valu_1_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_1_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_1_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_1_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_1_io_op_mul1_muls),
- .io_op_padd_en(valu_1_io_op_padd_en),
- .io_op_padd_add(valu_1_io_op_padd_add),
- .io_op_padd_sub(valu_1_io_op_padd_sub),
- .io_op_rsub_en(valu_1_io_op_rsub_en),
- .io_op_rsub_rsub(valu_1_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_1_io_op_shf_en_l),
- .io_op_shf_en_r(valu_1_io_op_shf_en_r),
- .io_op_shf_shl(valu_1_io_op_shf_shl),
- .io_op_shf_shr(valu_1_io_op_shf_shr),
- .io_op_shf_shf(valu_1_io_op_shf_shf),
- .io_op_sub_en(valu_1_io_op_sub_en),
- .io_op_sub_sub(valu_1_io_op_sub_sub),
- .io_op_sub_subs(valu_1_io_op_sub_subs),
- .io_op_sub_subw(valu_1_io_op_sub_subw),
- .io_op_sub_hsub(valu_1_io_op_sub_hsub),
- .io_read_0_data(valu_1_io_read_0_data),
- .io_read_1_data(valu_1_io_read_1_data),
- .io_read_2_data(valu_1_io_read_2_data),
- .io_read_3_data(valu_1_io_read_3_data),
- .io_read_5_data(valu_1_io_read_5_data),
- .io_write_0_data(valu_1_io_write_0_data),
- .io_write_1_data(valu_1_io_write_1_data),
- .io_load_0(valu_1_io_load_0),
- .io_load_1(valu_1_io_load_1)
- );
- VAluIntLane valu_2 ( // @[VAluInt.scala 418:11]
- .clock(valu_2_clock),
- .reset(valu_2_reset),
- .io_in_vdvalid(valu_2_io_in_vdvalid),
- .io_in_vevalid(valu_2_io_in_vevalid),
- .io_in_sz(valu_2_io_in_sz),
- .io_in_negative(valu_2_io_in_negative),
- .io_in_round(valu_2_io_in_round),
- .io_in_signed(valu_2_io_in_signed),
- .io_op_absd(valu_2_io_op_absd),
- .io_op_acc(valu_2_io_op_acc),
- .io_op_dup(valu_2_io_op_dup),
- .io_op_max(valu_2_io_op_max),
- .io_op_min(valu_2_io_op_min),
- .io_op_mv(valu_2_io_op_mv),
- .io_op_mv2(valu_2_io_op_mv2),
- .io_op_mvp(valu_2_io_op_mvp),
- .io_op_srans(valu_2_io_op_srans),
- .io_op_sraqs(valu_2_io_op_sraqs),
- .io_op_dwinit(valu_2_io_op_dwinit),
- .io_op_dwconv(valu_2_io_op_dwconv),
- .io_op_dwconvData(valu_2_io_op_dwconvData),
- .io_op_add_en(valu_2_io_op_add_en),
- .io_op_add_add(valu_2_io_op_add_add),
- .io_op_add_adds(valu_2_io_op_add_adds),
- .io_op_add_addw(valu_2_io_op_add_addw),
- .io_op_add_add3(valu_2_io_op_add_add3),
- .io_op_add_hadd(valu_2_io_op_add_hadd),
- .io_op_cmp_en(valu_2_io_op_cmp_en),
- .io_op_cmp_eq(valu_2_io_op_cmp_eq),
- .io_op_cmp_ne(valu_2_io_op_cmp_ne),
- .io_op_cmp_lt(valu_2_io_op_cmp_lt),
- .io_op_cmp_le(valu_2_io_op_cmp_le),
- .io_op_cmp_gt(valu_2_io_op_cmp_gt),
- .io_op_cmp_ge(valu_2_io_op_cmp_ge),
- .io_op_log_en(valu_2_io_op_log_en),
- .io_op_log_and(valu_2_io_op_log_and),
- .io_op_log_or(valu_2_io_op_log_or),
- .io_op_log_xor(valu_2_io_op_log_xor),
- .io_op_log_not(valu_2_io_op_log_not),
- .io_op_log_rev(valu_2_io_op_log_rev),
- .io_op_log_ror(valu_2_io_op_log_ror),
- .io_op_log_clb(valu_2_io_op_log_clb),
- .io_op_log_clz(valu_2_io_op_log_clz),
- .io_op_log_cpop(valu_2_io_op_log_cpop),
- .io_op_mul0_en(valu_2_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_2_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_2_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_2_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_2_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_2_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_2_io_op_mul0_madd),
- .io_op_mul1_en(valu_2_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_2_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_2_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_2_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_2_io_op_mul1_muls),
- .io_op_padd_en(valu_2_io_op_padd_en),
- .io_op_padd_add(valu_2_io_op_padd_add),
- .io_op_padd_sub(valu_2_io_op_padd_sub),
- .io_op_rsub_en(valu_2_io_op_rsub_en),
- .io_op_rsub_rsub(valu_2_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_2_io_op_shf_en_l),
- .io_op_shf_en_r(valu_2_io_op_shf_en_r),
- .io_op_shf_shl(valu_2_io_op_shf_shl),
- .io_op_shf_shr(valu_2_io_op_shf_shr),
- .io_op_shf_shf(valu_2_io_op_shf_shf),
- .io_op_sub_en(valu_2_io_op_sub_en),
- .io_op_sub_sub(valu_2_io_op_sub_sub),
- .io_op_sub_subs(valu_2_io_op_sub_subs),
- .io_op_sub_subw(valu_2_io_op_sub_subw),
- .io_op_sub_hsub(valu_2_io_op_sub_hsub),
- .io_read_0_data(valu_2_io_read_0_data),
- .io_read_1_data(valu_2_io_read_1_data),
- .io_read_2_data(valu_2_io_read_2_data),
- .io_read_3_data(valu_2_io_read_3_data),
- .io_read_5_data(valu_2_io_read_5_data),
- .io_write_0_data(valu_2_io_write_0_data),
- .io_write_1_data(valu_2_io_write_1_data),
- .io_load_0(valu_2_io_load_0),
- .io_load_1(valu_2_io_load_1)
- );
- VAluIntLane valu_3 ( // @[VAluInt.scala 418:11]
- .clock(valu_3_clock),
- .reset(valu_3_reset),
- .io_in_vdvalid(valu_3_io_in_vdvalid),
- .io_in_vevalid(valu_3_io_in_vevalid),
- .io_in_sz(valu_3_io_in_sz),
- .io_in_negative(valu_3_io_in_negative),
- .io_in_round(valu_3_io_in_round),
- .io_in_signed(valu_3_io_in_signed),
- .io_op_absd(valu_3_io_op_absd),
- .io_op_acc(valu_3_io_op_acc),
- .io_op_dup(valu_3_io_op_dup),
- .io_op_max(valu_3_io_op_max),
- .io_op_min(valu_3_io_op_min),
- .io_op_mv(valu_3_io_op_mv),
- .io_op_mv2(valu_3_io_op_mv2),
- .io_op_mvp(valu_3_io_op_mvp),
- .io_op_srans(valu_3_io_op_srans),
- .io_op_sraqs(valu_3_io_op_sraqs),
- .io_op_dwinit(valu_3_io_op_dwinit),
- .io_op_dwconv(valu_3_io_op_dwconv),
- .io_op_dwconvData(valu_3_io_op_dwconvData),
- .io_op_add_en(valu_3_io_op_add_en),
- .io_op_add_add(valu_3_io_op_add_add),
- .io_op_add_adds(valu_3_io_op_add_adds),
- .io_op_add_addw(valu_3_io_op_add_addw),
- .io_op_add_add3(valu_3_io_op_add_add3),
- .io_op_add_hadd(valu_3_io_op_add_hadd),
- .io_op_cmp_en(valu_3_io_op_cmp_en),
- .io_op_cmp_eq(valu_3_io_op_cmp_eq),
- .io_op_cmp_ne(valu_3_io_op_cmp_ne),
- .io_op_cmp_lt(valu_3_io_op_cmp_lt),
- .io_op_cmp_le(valu_3_io_op_cmp_le),
- .io_op_cmp_gt(valu_3_io_op_cmp_gt),
- .io_op_cmp_ge(valu_3_io_op_cmp_ge),
- .io_op_log_en(valu_3_io_op_log_en),
- .io_op_log_and(valu_3_io_op_log_and),
- .io_op_log_or(valu_3_io_op_log_or),
- .io_op_log_xor(valu_3_io_op_log_xor),
- .io_op_log_not(valu_3_io_op_log_not),
- .io_op_log_rev(valu_3_io_op_log_rev),
- .io_op_log_ror(valu_3_io_op_log_ror),
- .io_op_log_clb(valu_3_io_op_log_clb),
- .io_op_log_clz(valu_3_io_op_log_clz),
- .io_op_log_cpop(valu_3_io_op_log_cpop),
- .io_op_mul0_en(valu_3_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_3_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_3_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_3_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_3_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_3_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_3_io_op_mul0_madd),
- .io_op_mul1_en(valu_3_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_3_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_3_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_3_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_3_io_op_mul1_muls),
- .io_op_padd_en(valu_3_io_op_padd_en),
- .io_op_padd_add(valu_3_io_op_padd_add),
- .io_op_padd_sub(valu_3_io_op_padd_sub),
- .io_op_rsub_en(valu_3_io_op_rsub_en),
- .io_op_rsub_rsub(valu_3_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_3_io_op_shf_en_l),
- .io_op_shf_en_r(valu_3_io_op_shf_en_r),
- .io_op_shf_shl(valu_3_io_op_shf_shl),
- .io_op_shf_shr(valu_3_io_op_shf_shr),
- .io_op_shf_shf(valu_3_io_op_shf_shf),
- .io_op_sub_en(valu_3_io_op_sub_en),
- .io_op_sub_sub(valu_3_io_op_sub_sub),
- .io_op_sub_subs(valu_3_io_op_sub_subs),
- .io_op_sub_subw(valu_3_io_op_sub_subw),
- .io_op_sub_hsub(valu_3_io_op_sub_hsub),
- .io_read_0_data(valu_3_io_read_0_data),
- .io_read_1_data(valu_3_io_read_1_data),
- .io_read_2_data(valu_3_io_read_2_data),
- .io_read_3_data(valu_3_io_read_3_data),
- .io_read_5_data(valu_3_io_read_5_data),
- .io_write_0_data(valu_3_io_write_0_data),
- .io_write_1_data(valu_3_io_write_1_data),
- .io_load_0(valu_3_io_load_0),
- .io_load_1(valu_3_io_load_1)
- );
- VAluIntLane valu_4 ( // @[VAluInt.scala 418:11]
- .clock(valu_4_clock),
- .reset(valu_4_reset),
- .io_in_vdvalid(valu_4_io_in_vdvalid),
- .io_in_vevalid(valu_4_io_in_vevalid),
- .io_in_sz(valu_4_io_in_sz),
- .io_in_negative(valu_4_io_in_negative),
- .io_in_round(valu_4_io_in_round),
- .io_in_signed(valu_4_io_in_signed),
- .io_op_absd(valu_4_io_op_absd),
- .io_op_acc(valu_4_io_op_acc),
- .io_op_dup(valu_4_io_op_dup),
- .io_op_max(valu_4_io_op_max),
- .io_op_min(valu_4_io_op_min),
- .io_op_mv(valu_4_io_op_mv),
- .io_op_mv2(valu_4_io_op_mv2),
- .io_op_mvp(valu_4_io_op_mvp),
- .io_op_srans(valu_4_io_op_srans),
- .io_op_sraqs(valu_4_io_op_sraqs),
- .io_op_dwinit(valu_4_io_op_dwinit),
- .io_op_dwconv(valu_4_io_op_dwconv),
- .io_op_dwconvData(valu_4_io_op_dwconvData),
- .io_op_add_en(valu_4_io_op_add_en),
- .io_op_add_add(valu_4_io_op_add_add),
- .io_op_add_adds(valu_4_io_op_add_adds),
- .io_op_add_addw(valu_4_io_op_add_addw),
- .io_op_add_add3(valu_4_io_op_add_add3),
- .io_op_add_hadd(valu_4_io_op_add_hadd),
- .io_op_cmp_en(valu_4_io_op_cmp_en),
- .io_op_cmp_eq(valu_4_io_op_cmp_eq),
- .io_op_cmp_ne(valu_4_io_op_cmp_ne),
- .io_op_cmp_lt(valu_4_io_op_cmp_lt),
- .io_op_cmp_le(valu_4_io_op_cmp_le),
- .io_op_cmp_gt(valu_4_io_op_cmp_gt),
- .io_op_cmp_ge(valu_4_io_op_cmp_ge),
- .io_op_log_en(valu_4_io_op_log_en),
- .io_op_log_and(valu_4_io_op_log_and),
- .io_op_log_or(valu_4_io_op_log_or),
- .io_op_log_xor(valu_4_io_op_log_xor),
- .io_op_log_not(valu_4_io_op_log_not),
- .io_op_log_rev(valu_4_io_op_log_rev),
- .io_op_log_ror(valu_4_io_op_log_ror),
- .io_op_log_clb(valu_4_io_op_log_clb),
- .io_op_log_clz(valu_4_io_op_log_clz),
- .io_op_log_cpop(valu_4_io_op_log_cpop),
- .io_op_mul0_en(valu_4_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_4_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_4_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_4_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_4_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_4_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_4_io_op_mul0_madd),
- .io_op_mul1_en(valu_4_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_4_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_4_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_4_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_4_io_op_mul1_muls),
- .io_op_padd_en(valu_4_io_op_padd_en),
- .io_op_padd_add(valu_4_io_op_padd_add),
- .io_op_padd_sub(valu_4_io_op_padd_sub),
- .io_op_rsub_en(valu_4_io_op_rsub_en),
- .io_op_rsub_rsub(valu_4_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_4_io_op_shf_en_l),
- .io_op_shf_en_r(valu_4_io_op_shf_en_r),
- .io_op_shf_shl(valu_4_io_op_shf_shl),
- .io_op_shf_shr(valu_4_io_op_shf_shr),
- .io_op_shf_shf(valu_4_io_op_shf_shf),
- .io_op_sub_en(valu_4_io_op_sub_en),
- .io_op_sub_sub(valu_4_io_op_sub_sub),
- .io_op_sub_subs(valu_4_io_op_sub_subs),
- .io_op_sub_subw(valu_4_io_op_sub_subw),
- .io_op_sub_hsub(valu_4_io_op_sub_hsub),
- .io_read_0_data(valu_4_io_read_0_data),
- .io_read_1_data(valu_4_io_read_1_data),
- .io_read_2_data(valu_4_io_read_2_data),
- .io_read_3_data(valu_4_io_read_3_data),
- .io_read_5_data(valu_4_io_read_5_data),
- .io_write_0_data(valu_4_io_write_0_data),
- .io_write_1_data(valu_4_io_write_1_data),
- .io_load_0(valu_4_io_load_0),
- .io_load_1(valu_4_io_load_1)
- );
- VAluIntLane valu_5 ( // @[VAluInt.scala 418:11]
- .clock(valu_5_clock),
- .reset(valu_5_reset),
- .io_in_vdvalid(valu_5_io_in_vdvalid),
- .io_in_vevalid(valu_5_io_in_vevalid),
- .io_in_sz(valu_5_io_in_sz),
- .io_in_negative(valu_5_io_in_negative),
- .io_in_round(valu_5_io_in_round),
- .io_in_signed(valu_5_io_in_signed),
- .io_op_absd(valu_5_io_op_absd),
- .io_op_acc(valu_5_io_op_acc),
- .io_op_dup(valu_5_io_op_dup),
- .io_op_max(valu_5_io_op_max),
- .io_op_min(valu_5_io_op_min),
- .io_op_mv(valu_5_io_op_mv),
- .io_op_mv2(valu_5_io_op_mv2),
- .io_op_mvp(valu_5_io_op_mvp),
- .io_op_srans(valu_5_io_op_srans),
- .io_op_sraqs(valu_5_io_op_sraqs),
- .io_op_dwinit(valu_5_io_op_dwinit),
- .io_op_dwconv(valu_5_io_op_dwconv),
- .io_op_dwconvData(valu_5_io_op_dwconvData),
- .io_op_add_en(valu_5_io_op_add_en),
- .io_op_add_add(valu_5_io_op_add_add),
- .io_op_add_adds(valu_5_io_op_add_adds),
- .io_op_add_addw(valu_5_io_op_add_addw),
- .io_op_add_add3(valu_5_io_op_add_add3),
- .io_op_add_hadd(valu_5_io_op_add_hadd),
- .io_op_cmp_en(valu_5_io_op_cmp_en),
- .io_op_cmp_eq(valu_5_io_op_cmp_eq),
- .io_op_cmp_ne(valu_5_io_op_cmp_ne),
- .io_op_cmp_lt(valu_5_io_op_cmp_lt),
- .io_op_cmp_le(valu_5_io_op_cmp_le),
- .io_op_cmp_gt(valu_5_io_op_cmp_gt),
- .io_op_cmp_ge(valu_5_io_op_cmp_ge),
- .io_op_log_en(valu_5_io_op_log_en),
- .io_op_log_and(valu_5_io_op_log_and),
- .io_op_log_or(valu_5_io_op_log_or),
- .io_op_log_xor(valu_5_io_op_log_xor),
- .io_op_log_not(valu_5_io_op_log_not),
- .io_op_log_rev(valu_5_io_op_log_rev),
- .io_op_log_ror(valu_5_io_op_log_ror),
- .io_op_log_clb(valu_5_io_op_log_clb),
- .io_op_log_clz(valu_5_io_op_log_clz),
- .io_op_log_cpop(valu_5_io_op_log_cpop),
- .io_op_mul0_en(valu_5_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_5_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_5_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_5_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_5_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_5_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_5_io_op_mul0_madd),
- .io_op_mul1_en(valu_5_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_5_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_5_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_5_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_5_io_op_mul1_muls),
- .io_op_padd_en(valu_5_io_op_padd_en),
- .io_op_padd_add(valu_5_io_op_padd_add),
- .io_op_padd_sub(valu_5_io_op_padd_sub),
- .io_op_rsub_en(valu_5_io_op_rsub_en),
- .io_op_rsub_rsub(valu_5_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_5_io_op_shf_en_l),
- .io_op_shf_en_r(valu_5_io_op_shf_en_r),
- .io_op_shf_shl(valu_5_io_op_shf_shl),
- .io_op_shf_shr(valu_5_io_op_shf_shr),
- .io_op_shf_shf(valu_5_io_op_shf_shf),
- .io_op_sub_en(valu_5_io_op_sub_en),
- .io_op_sub_sub(valu_5_io_op_sub_sub),
- .io_op_sub_subs(valu_5_io_op_sub_subs),
- .io_op_sub_subw(valu_5_io_op_sub_subw),
- .io_op_sub_hsub(valu_5_io_op_sub_hsub),
- .io_read_0_data(valu_5_io_read_0_data),
- .io_read_1_data(valu_5_io_read_1_data),
- .io_read_2_data(valu_5_io_read_2_data),
- .io_read_3_data(valu_5_io_read_3_data),
- .io_read_5_data(valu_5_io_read_5_data),
- .io_write_0_data(valu_5_io_write_0_data),
- .io_write_1_data(valu_5_io_write_1_data),
- .io_load_0(valu_5_io_load_0),
- .io_load_1(valu_5_io_load_1)
- );
- VAluIntLane valu_6 ( // @[VAluInt.scala 418:11]
- .clock(valu_6_clock),
- .reset(valu_6_reset),
- .io_in_vdvalid(valu_6_io_in_vdvalid),
- .io_in_vevalid(valu_6_io_in_vevalid),
- .io_in_sz(valu_6_io_in_sz),
- .io_in_negative(valu_6_io_in_negative),
- .io_in_round(valu_6_io_in_round),
- .io_in_signed(valu_6_io_in_signed),
- .io_op_absd(valu_6_io_op_absd),
- .io_op_acc(valu_6_io_op_acc),
- .io_op_dup(valu_6_io_op_dup),
- .io_op_max(valu_6_io_op_max),
- .io_op_min(valu_6_io_op_min),
- .io_op_mv(valu_6_io_op_mv),
- .io_op_mv2(valu_6_io_op_mv2),
- .io_op_mvp(valu_6_io_op_mvp),
- .io_op_srans(valu_6_io_op_srans),
- .io_op_sraqs(valu_6_io_op_sraqs),
- .io_op_dwinit(valu_6_io_op_dwinit),
- .io_op_dwconv(valu_6_io_op_dwconv),
- .io_op_dwconvData(valu_6_io_op_dwconvData),
- .io_op_add_en(valu_6_io_op_add_en),
- .io_op_add_add(valu_6_io_op_add_add),
- .io_op_add_adds(valu_6_io_op_add_adds),
- .io_op_add_addw(valu_6_io_op_add_addw),
- .io_op_add_add3(valu_6_io_op_add_add3),
- .io_op_add_hadd(valu_6_io_op_add_hadd),
- .io_op_cmp_en(valu_6_io_op_cmp_en),
- .io_op_cmp_eq(valu_6_io_op_cmp_eq),
- .io_op_cmp_ne(valu_6_io_op_cmp_ne),
- .io_op_cmp_lt(valu_6_io_op_cmp_lt),
- .io_op_cmp_le(valu_6_io_op_cmp_le),
- .io_op_cmp_gt(valu_6_io_op_cmp_gt),
- .io_op_cmp_ge(valu_6_io_op_cmp_ge),
- .io_op_log_en(valu_6_io_op_log_en),
- .io_op_log_and(valu_6_io_op_log_and),
- .io_op_log_or(valu_6_io_op_log_or),
- .io_op_log_xor(valu_6_io_op_log_xor),
- .io_op_log_not(valu_6_io_op_log_not),
- .io_op_log_rev(valu_6_io_op_log_rev),
- .io_op_log_ror(valu_6_io_op_log_ror),
- .io_op_log_clb(valu_6_io_op_log_clb),
- .io_op_log_clz(valu_6_io_op_log_clz),
- .io_op_log_cpop(valu_6_io_op_log_cpop),
- .io_op_mul0_en(valu_6_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_6_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_6_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_6_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_6_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_6_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_6_io_op_mul0_madd),
- .io_op_mul1_en(valu_6_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_6_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_6_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_6_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_6_io_op_mul1_muls),
- .io_op_padd_en(valu_6_io_op_padd_en),
- .io_op_padd_add(valu_6_io_op_padd_add),
- .io_op_padd_sub(valu_6_io_op_padd_sub),
- .io_op_rsub_en(valu_6_io_op_rsub_en),
- .io_op_rsub_rsub(valu_6_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_6_io_op_shf_en_l),
- .io_op_shf_en_r(valu_6_io_op_shf_en_r),
- .io_op_shf_shl(valu_6_io_op_shf_shl),
- .io_op_shf_shr(valu_6_io_op_shf_shr),
- .io_op_shf_shf(valu_6_io_op_shf_shf),
- .io_op_sub_en(valu_6_io_op_sub_en),
- .io_op_sub_sub(valu_6_io_op_sub_sub),
- .io_op_sub_subs(valu_6_io_op_sub_subs),
- .io_op_sub_subw(valu_6_io_op_sub_subw),
- .io_op_sub_hsub(valu_6_io_op_sub_hsub),
- .io_read_0_data(valu_6_io_read_0_data),
- .io_read_1_data(valu_6_io_read_1_data),
- .io_read_2_data(valu_6_io_read_2_data),
- .io_read_3_data(valu_6_io_read_3_data),
- .io_read_5_data(valu_6_io_read_5_data),
- .io_write_0_data(valu_6_io_write_0_data),
- .io_write_1_data(valu_6_io_write_1_data),
- .io_load_0(valu_6_io_load_0),
- .io_load_1(valu_6_io_load_1)
- );
- VAluIntLane valu_7 ( // @[VAluInt.scala 418:11]
- .clock(valu_7_clock),
- .reset(valu_7_reset),
- .io_in_vdvalid(valu_7_io_in_vdvalid),
- .io_in_vevalid(valu_7_io_in_vevalid),
- .io_in_sz(valu_7_io_in_sz),
- .io_in_negative(valu_7_io_in_negative),
- .io_in_round(valu_7_io_in_round),
- .io_in_signed(valu_7_io_in_signed),
- .io_op_absd(valu_7_io_op_absd),
- .io_op_acc(valu_7_io_op_acc),
- .io_op_dup(valu_7_io_op_dup),
- .io_op_max(valu_7_io_op_max),
- .io_op_min(valu_7_io_op_min),
- .io_op_mv(valu_7_io_op_mv),
- .io_op_mv2(valu_7_io_op_mv2),
- .io_op_mvp(valu_7_io_op_mvp),
- .io_op_srans(valu_7_io_op_srans),
- .io_op_sraqs(valu_7_io_op_sraqs),
- .io_op_dwinit(valu_7_io_op_dwinit),
- .io_op_dwconv(valu_7_io_op_dwconv),
- .io_op_dwconvData(valu_7_io_op_dwconvData),
- .io_op_add_en(valu_7_io_op_add_en),
- .io_op_add_add(valu_7_io_op_add_add),
- .io_op_add_adds(valu_7_io_op_add_adds),
- .io_op_add_addw(valu_7_io_op_add_addw),
- .io_op_add_add3(valu_7_io_op_add_add3),
- .io_op_add_hadd(valu_7_io_op_add_hadd),
- .io_op_cmp_en(valu_7_io_op_cmp_en),
- .io_op_cmp_eq(valu_7_io_op_cmp_eq),
- .io_op_cmp_ne(valu_7_io_op_cmp_ne),
- .io_op_cmp_lt(valu_7_io_op_cmp_lt),
- .io_op_cmp_le(valu_7_io_op_cmp_le),
- .io_op_cmp_gt(valu_7_io_op_cmp_gt),
- .io_op_cmp_ge(valu_7_io_op_cmp_ge),
- .io_op_log_en(valu_7_io_op_log_en),
- .io_op_log_and(valu_7_io_op_log_and),
- .io_op_log_or(valu_7_io_op_log_or),
- .io_op_log_xor(valu_7_io_op_log_xor),
- .io_op_log_not(valu_7_io_op_log_not),
- .io_op_log_rev(valu_7_io_op_log_rev),
- .io_op_log_ror(valu_7_io_op_log_ror),
- .io_op_log_clb(valu_7_io_op_log_clb),
- .io_op_log_clz(valu_7_io_op_log_clz),
- .io_op_log_cpop(valu_7_io_op_log_cpop),
- .io_op_mul0_en(valu_7_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_7_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_7_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_7_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_7_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_7_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_7_io_op_mul0_madd),
- .io_op_mul1_en(valu_7_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_7_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_7_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_7_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_7_io_op_mul1_muls),
- .io_op_padd_en(valu_7_io_op_padd_en),
- .io_op_padd_add(valu_7_io_op_padd_add),
- .io_op_padd_sub(valu_7_io_op_padd_sub),
- .io_op_rsub_en(valu_7_io_op_rsub_en),
- .io_op_rsub_rsub(valu_7_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_7_io_op_shf_en_l),
- .io_op_shf_en_r(valu_7_io_op_shf_en_r),
- .io_op_shf_shl(valu_7_io_op_shf_shl),
- .io_op_shf_shr(valu_7_io_op_shf_shr),
- .io_op_shf_shf(valu_7_io_op_shf_shf),
- .io_op_sub_en(valu_7_io_op_sub_en),
- .io_op_sub_sub(valu_7_io_op_sub_sub),
- .io_op_sub_subs(valu_7_io_op_sub_subs),
- .io_op_sub_subw(valu_7_io_op_sub_subw),
- .io_op_sub_hsub(valu_7_io_op_sub_hsub),
- .io_read_0_data(valu_7_io_read_0_data),
- .io_read_1_data(valu_7_io_read_1_data),
- .io_read_2_data(valu_7_io_read_2_data),
- .io_read_3_data(valu_7_io_read_3_data),
- .io_read_5_data(valu_7_io_read_5_data),
- .io_write_0_data(valu_7_io_write_0_data),
- .io_write_1_data(valu_7_io_write_1_data),
- .io_load_0(valu_7_io_load_0),
- .io_load_1(valu_7_io_load_1)
- );
- assign io_write_0_valid = vdvalid1; // @[VAluInt.scala 755:21]
- assign io_write_0_addr = vdaddr1_addr; // @[VAluInt.scala 756:20]
- assign io_write_0_data = {io_write_0_data_hi,io_write_0_data_lo}; // @[VAluInt.scala 757:30]
- assign io_write_1_valid = vevalid1; // @[VAluInt.scala 759:21]
- assign io_write_1_addr = veaddr1_addr; // @[VAluInt.scala 760:20]
- assign io_write_1_data = {io_write_1_data_hi,io_write_1_data_lo}; // @[VAluInt.scala 761:30]
- assign io_whint_0_valid = vdvalid0 & _vdvalid1_T; // @[VAluInt.scala 763:33]
- assign io_whint_0_addr = vdaddr0_addr; // @[VAluInt.scala 764:20]
- assign io_whint_1_valid = vevalid0 & _vdvalid1_T; // @[VAluInt.scala 766:33]
- assign io_whint_1_addr = veaddr0_addr; // @[VAluInt.scala 767:20]
- assign valu_0_clock = clock;
- assign valu_0_reset = reset;
- assign valu_0_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_0_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_0_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_0_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_0_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_0_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_0_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_0_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_0_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_0_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_0_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_0_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_0_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_0_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_0_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_0_io_op_sraqs = sraqs; // @[VAluInt.scala 453:25]
- assign valu_0_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_0_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_0_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_0_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_0_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_0_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_0_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_0_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_0_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_0_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_0_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_0_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_0_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_0_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_0_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_0_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_0_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_0_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_0_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_0_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_0_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_0_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_0_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_0_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_0_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_0_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_0_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_0_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_0_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_0_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_0_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_0_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_0_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_0_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_0_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_0_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_0_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_0_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_0_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_0_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_0_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_0_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_0_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_0_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_0_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_0_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_0_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_0_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_0_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_0_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_0_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_0_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_0_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_0_io_read_0_data = io_read_0_data[31:0]; // @[VAluInt.scala 430:49]
- assign valu_0_io_read_1_data = io_read_1_data[31:0]; // @[VAluInt.scala 430:49]
- assign valu_0_io_read_2_data = io_read_2_data[31:0]; // @[VAluInt.scala 430:49]
- assign valu_0_io_read_3_data = io_read_3_data[31:0]; // @[VAluInt.scala 430:49]
- assign valu_0_io_read_5_data = io_read_5_data[31:0]; // @[VAluInt.scala 430:49]
- assign valu_0_io_load_0 = load_0[31:0]; // @[VAluInt.scala 433:36]
- assign valu_0_io_load_1 = load_1[31:0]; // @[VAluInt.scala 433:36]
- assign valu_1_clock = clock;
- assign valu_1_reset = reset;
- assign valu_1_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_1_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_1_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_1_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_1_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_1_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_1_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_1_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_1_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_1_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_1_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_1_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_1_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_1_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_1_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_1_io_op_sraqs = sraqs; // @[VAluInt.scala 453:25]
- assign valu_1_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_1_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_1_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_1_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_1_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_1_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_1_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_1_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_1_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_1_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_1_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_1_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_1_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_1_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_1_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_1_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_1_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_1_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_1_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_1_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_1_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_1_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_1_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_1_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_1_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_1_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_1_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_1_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_1_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_1_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_1_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_1_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_1_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_1_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_1_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_1_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_1_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_1_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_1_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_1_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_1_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_1_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_1_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_1_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_1_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_1_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_1_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_1_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_1_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_1_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_1_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_1_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_1_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_1_io_read_0_data = io_read_0_data[63:32]; // @[VAluInt.scala 430:49]
- assign valu_1_io_read_1_data = io_read_1_data[63:32]; // @[VAluInt.scala 430:49]
- assign valu_1_io_read_2_data = io_read_2_data[63:32]; // @[VAluInt.scala 430:49]
- assign valu_1_io_read_3_data = io_read_3_data[63:32]; // @[VAluInt.scala 430:49]
- assign valu_1_io_read_5_data = io_read_5_data[63:32]; // @[VAluInt.scala 430:49]
- assign valu_1_io_load_0 = load_0[63:32]; // @[VAluInt.scala 433:36]
- assign valu_1_io_load_1 = load_1[63:32]; // @[VAluInt.scala 433:36]
- assign valu_2_clock = clock;
- assign valu_2_reset = reset;
- assign valu_2_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_2_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_2_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_2_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_2_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_2_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_2_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_2_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_2_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_2_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_2_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_2_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_2_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_2_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_2_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_2_io_op_sraqs = sraqs; // @[VAluInt.scala 453:25]
- assign valu_2_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_2_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_2_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_2_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_2_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_2_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_2_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_2_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_2_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_2_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_2_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_2_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_2_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_2_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_2_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_2_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_2_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_2_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_2_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_2_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_2_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_2_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_2_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_2_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_2_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_2_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_2_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_2_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_2_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_2_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_2_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_2_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_2_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_2_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_2_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_2_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_2_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_2_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_2_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_2_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_2_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_2_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_2_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_2_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_2_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_2_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_2_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_2_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_2_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_2_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_2_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_2_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_2_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_2_io_read_0_data = io_read_0_data[95:64]; // @[VAluInt.scala 430:49]
- assign valu_2_io_read_1_data = io_read_1_data[95:64]; // @[VAluInt.scala 430:49]
- assign valu_2_io_read_2_data = io_read_2_data[95:64]; // @[VAluInt.scala 430:49]
- assign valu_2_io_read_3_data = io_read_3_data[95:64]; // @[VAluInt.scala 430:49]
- assign valu_2_io_read_5_data = io_read_5_data[95:64]; // @[VAluInt.scala 430:49]
- assign valu_2_io_load_0 = load_0[95:64]; // @[VAluInt.scala 433:36]
- assign valu_2_io_load_1 = load_1[95:64]; // @[VAluInt.scala 433:36]
- assign valu_3_clock = clock;
- assign valu_3_reset = reset;
- assign valu_3_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_3_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_3_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_3_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_3_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_3_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_3_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_3_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_3_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_3_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_3_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_3_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_3_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_3_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_3_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_3_io_op_sraqs = sraqs; // @[VAluInt.scala 453:25]
- assign valu_3_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_3_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_3_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_3_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_3_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_3_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_3_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_3_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_3_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_3_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_3_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_3_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_3_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_3_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_3_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_3_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_3_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_3_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_3_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_3_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_3_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_3_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_3_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_3_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_3_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_3_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_3_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_3_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_3_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_3_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_3_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_3_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_3_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_3_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_3_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_3_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_3_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_3_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_3_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_3_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_3_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_3_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_3_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_3_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_3_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_3_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_3_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_3_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_3_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_3_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_3_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_3_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_3_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_3_io_read_0_data = io_read_0_data[127:96]; // @[VAluInt.scala 430:49]
- assign valu_3_io_read_1_data = io_read_1_data[127:96]; // @[VAluInt.scala 430:49]
- assign valu_3_io_read_2_data = io_read_2_data[127:96]; // @[VAluInt.scala 430:49]
- assign valu_3_io_read_3_data = io_read_3_data[127:96]; // @[VAluInt.scala 430:49]
- assign valu_3_io_read_5_data = io_read_5_data[127:96]; // @[VAluInt.scala 430:49]
- assign valu_3_io_load_0 = load_0[127:96]; // @[VAluInt.scala 433:36]
- assign valu_3_io_load_1 = load_1[127:96]; // @[VAluInt.scala 433:36]
- assign valu_4_clock = clock;
- assign valu_4_reset = reset;
- assign valu_4_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_4_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_4_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_4_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_4_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_4_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_4_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_4_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_4_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_4_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_4_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_4_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_4_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_4_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_4_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_4_io_op_sraqs = sraqs; // @[VAluInt.scala 453:25]
- assign valu_4_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_4_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_4_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_4_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_4_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_4_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_4_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_4_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_4_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_4_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_4_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_4_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_4_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_4_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_4_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_4_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_4_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_4_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_4_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_4_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_4_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_4_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_4_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_4_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_4_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_4_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_4_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_4_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_4_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_4_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_4_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_4_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_4_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_4_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_4_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_4_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_4_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_4_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_4_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_4_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_4_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_4_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_4_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_4_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_4_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_4_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_4_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_4_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_4_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_4_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_4_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_4_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_4_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_4_io_read_0_data = io_read_0_data[159:128]; // @[VAluInt.scala 430:49]
- assign valu_4_io_read_1_data = io_read_1_data[159:128]; // @[VAluInt.scala 430:49]
- assign valu_4_io_read_2_data = io_read_2_data[159:128]; // @[VAluInt.scala 430:49]
- assign valu_4_io_read_3_data = io_read_3_data[159:128]; // @[VAluInt.scala 430:49]
- assign valu_4_io_read_5_data = io_read_5_data[159:128]; // @[VAluInt.scala 430:49]
- assign valu_4_io_load_0 = load_0[159:128]; // @[VAluInt.scala 433:36]
- assign valu_4_io_load_1 = load_1[159:128]; // @[VAluInt.scala 433:36]
- assign valu_5_clock = clock;
- assign valu_5_reset = reset;
- assign valu_5_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_5_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_5_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_5_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_5_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_5_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_5_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_5_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_5_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_5_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_5_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_5_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_5_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_5_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_5_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_5_io_op_sraqs = sraqs; // @[VAluInt.scala 453:25]
- assign valu_5_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_5_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_5_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_5_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_5_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_5_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_5_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_5_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_5_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_5_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_5_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_5_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_5_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_5_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_5_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_5_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_5_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_5_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_5_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_5_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_5_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_5_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_5_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_5_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_5_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_5_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_5_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_5_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_5_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_5_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_5_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_5_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_5_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_5_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_5_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_5_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_5_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_5_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_5_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_5_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_5_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_5_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_5_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_5_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_5_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_5_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_5_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_5_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_5_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_5_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_5_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_5_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_5_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_5_io_read_0_data = io_read_0_data[191:160]; // @[VAluInt.scala 430:49]
- assign valu_5_io_read_1_data = io_read_1_data[191:160]; // @[VAluInt.scala 430:49]
- assign valu_5_io_read_2_data = io_read_2_data[191:160]; // @[VAluInt.scala 430:49]
- assign valu_5_io_read_3_data = io_read_3_data[191:160]; // @[VAluInt.scala 430:49]
- assign valu_5_io_read_5_data = io_read_5_data[191:160]; // @[VAluInt.scala 430:49]
- assign valu_5_io_load_0 = load_0[191:160]; // @[VAluInt.scala 433:36]
- assign valu_5_io_load_1 = load_1[191:160]; // @[VAluInt.scala 433:36]
- assign valu_6_clock = clock;
- assign valu_6_reset = reset;
- assign valu_6_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_6_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_6_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_6_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_6_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_6_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_6_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_6_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_6_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_6_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_6_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_6_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_6_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_6_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_6_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_6_io_op_sraqs = sraqs; // @[VAluInt.scala 453:25]
- assign valu_6_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_6_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_6_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_6_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_6_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_6_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_6_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_6_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_6_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_6_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_6_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_6_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_6_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_6_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_6_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_6_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_6_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_6_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_6_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_6_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_6_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_6_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_6_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_6_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_6_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_6_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_6_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_6_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_6_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_6_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_6_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_6_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_6_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_6_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_6_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_6_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_6_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_6_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_6_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_6_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_6_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_6_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_6_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_6_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_6_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_6_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_6_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_6_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_6_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_6_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_6_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_6_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_6_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_6_io_read_0_data = io_read_0_data[223:192]; // @[VAluInt.scala 430:49]
- assign valu_6_io_read_1_data = io_read_1_data[223:192]; // @[VAluInt.scala 430:49]
- assign valu_6_io_read_2_data = io_read_2_data[223:192]; // @[VAluInt.scala 430:49]
- assign valu_6_io_read_3_data = io_read_3_data[223:192]; // @[VAluInt.scala 430:49]
- assign valu_6_io_read_5_data = io_read_5_data[223:192]; // @[VAluInt.scala 430:49]
- assign valu_6_io_load_0 = load_0[223:192]; // @[VAluInt.scala 433:36]
- assign valu_6_io_load_1 = load_1[223:192]; // @[VAluInt.scala 433:36]
- assign valu_7_clock = clock;
- assign valu_7_reset = reset;
- assign valu_7_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_7_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_7_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_7_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_7_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_7_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_7_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_7_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_7_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_7_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_7_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_7_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_7_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_7_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_7_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_7_io_op_sraqs = sraqs; // @[VAluInt.scala 453:25]
- assign valu_7_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_7_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_7_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_7_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_7_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_7_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_7_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_7_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_7_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_7_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_7_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_7_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_7_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_7_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_7_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_7_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_7_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_7_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_7_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_7_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_7_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_7_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_7_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_7_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_7_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_7_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_7_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_7_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_7_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_7_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_7_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_7_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_7_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_7_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_7_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_7_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_7_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_7_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_7_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_7_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_7_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_7_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_7_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_7_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_7_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_7_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_7_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_7_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_7_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_7_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_7_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_7_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_7_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_7_io_read_0_data = io_read_0_data[255:224]; // @[VAluInt.scala 430:49]
- assign valu_7_io_read_1_data = io_read_1_data[255:224]; // @[VAluInt.scala 430:49]
- assign valu_7_io_read_2_data = io_read_2_data[255:224]; // @[VAluInt.scala 430:49]
- assign valu_7_io_read_3_data = io_read_3_data[255:224]; // @[VAluInt.scala 430:49]
- assign valu_7_io_read_5_data = io_read_5_data[255:224]; // @[VAluInt.scala 430:49]
- assign valu_7_io_load_0 = load_0[255:224]; // @[VAluInt.scala 433:36]
- assign valu_7_io_load_1 = load_1[255:224]; // @[VAluInt.scala 433:36]
- always @(posedge clock) begin
- if (io_in_valid) begin // @[VAluInt.scala 211:22]
- vdaddr0_addr <= io_in_vd_addr; // @[VAluInt.scala 212:13]
- end
- if (vdvalid0) begin // @[VAluInt.scala 216:19]
- vdaddr1_addr <= vdaddr0_addr; // @[VAluInt.scala 217:13]
- end
- if (io_in_valid) begin // @[VAluInt.scala 211:22]
- veaddr0_addr <= io_in_ve_addr; // @[VAluInt.scala 213:13]
- end
- if (vevalid0) begin // @[VAluInt.scala 220:19]
- veaddr1_addr <= veaddr0_addr; // @[VAluInt.scala 221:13]
- end
- if (io_in_valid) begin // @[VAluInt.scala 230:22]
- negative <= e_negative; // @[VAluInt.scala 231:14]
- end
- if (io_in_valid) begin // @[VAluInt.scala 230:22]
- round <= e_round; // @[VAluInt.scala 232:14]
- end
- if (io_in_valid) begin // @[VAluInt.scala 230:22]
- signed_ <= e_signed; // @[VAluInt.scala 233:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- absd <= io_in_valid & e_absd; // @[VAluInt.scala 328:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- acc <= io_in_valid & e_acc; // @[VAluInt.scala 329:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- dup <= io_in_valid & e_dup; // @[VAluInt.scala 330:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- max <= io_in_valid & e_max; // @[VAluInt.scala 331:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- min <= io_in_valid & e_min; // @[VAluInt.scala 332:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- srans <= io_in_valid & e_srans; // @[VAluInt.scala 333:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- sraqs <= io_in_valid & e_sraqs; // @[VAluInt.scala 334:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- slidevn <= io_in_valid & e_slidevn; // @[VAluInt.scala 336:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- slidevp <= io_in_valid & e_slidevp; // @[VAluInt.scala 337:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- slidehn2 <= io_in_valid & _e_slidevn_T_3; // @[VAluInt.scala 338:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- slidehp2 <= io_in_valid & _e_slidevp_T_3; // @[VAluInt.scala 339:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- sel <= io_in_valid & e_sel; // @[VAluInt.scala 340:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- evn <= io_in_valid & e_evn; // @[VAluInt.scala 341:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- odd <= io_in_valid & e_odd; // @[VAluInt.scala 342:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- zip <= io_in_valid & e_zip; // @[VAluInt.scala 343:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- dwinit <= io_in_valid & e_dwinit; // @[VAluInt.scala 345:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- dwconv <= io_in_valid & e_dwconv; // @[VAluInt.scala 346:14]
- end
- dwconvData <= dwconv; // @[VAluInt.scala 413:14]
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- add <= io_in_valid & e_add; // @[VAluInt.scala 348:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- add_add <= io_in_valid & e_add_add; // @[VAluInt.scala 349:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- add_adds <= io_in_valid & e_add_adds; // @[VAluInt.scala 350:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- add_addw <= io_in_valid & e_add_addw; // @[VAluInt.scala 351:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- add_add3 <= io_in_valid & e_add_add3; // @[VAluInt.scala 352:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- add_hadd <= io_in_valid & e_add_hadd; // @[VAluInt.scala 353:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- padd <= io_in_valid & e_padd; // @[VAluInt.scala 355:10]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- padd_add <= io_in_valid & e_padd_add; // @[VAluInt.scala 356:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- padd_sub <= io_in_valid & e_padd_sub; // @[VAluInt.scala 357:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- rsub <= io_in_valid & (e_rsub | e_absd); // @[VAluInt.scala 396:10]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- rsub_rsub <= io_in_valid & e_rsub; // @[VAluInt.scala 397:15]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- sub <= io_in_valid & (e_sub | e_absd); // @[VAluInt.scala 405:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- sub_sub <= io_in_valid & e_sub_sub; // @[VAluInt.scala 406:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- sub_subs <= io_in_valid & e_sub_subs; // @[VAluInt.scala 407:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- sub_subw <= io_in_valid & e_sub_subw; // @[VAluInt.scala 408:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- sub_hsub <= io_in_valid & e_sub_hsub; // @[VAluInt.scala 409:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp <= io_in_valid & (e_cmp | e_absd | e_max | e_min); // @[VAluInt.scala 359:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp_eq <= io_in_valid & e_cmp_eq; // @[VAluInt.scala 360:12]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp_ne <= io_in_valid & e_cmp_ne; // @[VAluInt.scala 361:12]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp_lt <= io_in_valid & e_cmp_lt; // @[VAluInt.scala 362:12]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp_le <= io_in_valid & e_cmp_le; // @[VAluInt.scala 363:12]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp_gt <= io_in_valid & e_cmp_gt; // @[VAluInt.scala 364:12]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp_ge <= io_in_valid & e_cmp_ge; // @[VAluInt.scala 365:12]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log <= io_in_valid & e_log; // @[VAluInt.scala 367:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_and <= io_in_valid & e_log_and; // @[VAluInt.scala 368:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_or <= io_in_valid & e_log_or; // @[VAluInt.scala 369:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_xor <= io_in_valid & e_log_xor; // @[VAluInt.scala 370:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_not <= io_in_valid & e_log_not; // @[VAluInt.scala 371:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_rev <= io_in_valid & e_log_rev; // @[VAluInt.scala 372:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_ror <= io_in_valid & e_log_ror; // @[VAluInt.scala 373:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_clb <= io_in_valid & e_log_clb; // @[VAluInt.scala 374:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_clz <= io_in_valid & e_log_clz; // @[VAluInt.scala 375:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_cpop <= io_in_valid & e_log_cpop; // @[VAluInt.scala 376:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0 <= io_in_valid & e_mul0; // @[VAluInt.scala 378:10]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0_dmulh <= io_in_valid & e_mul0_dmulh; // @[VAluInt.scala 379:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0_mul <= io_in_valid & e_mul0_mul; // @[VAluInt.scala 380:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0_mulh <= io_in_valid & e_mul0_mulh; // @[VAluInt.scala 381:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0_muls <= io_in_valid & e_mul0_muls; // @[VAluInt.scala 382:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0_mulw <= io_in_valid & e_mul0_mulw; // @[VAluInt.scala 383:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0_madd <= io_in_valid & e_mul0_madd; // @[VAluInt.scala 384:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul1 <= io_in_valid & e_mul1; // @[VAluInt.scala 386:10]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul1_dmulh <= io_in_valid & _e_mul0_dmulh_T_1; // @[VAluInt.scala 387:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul1_mul <= io_in_valid & _e_mul0_mul_T_1; // @[VAluInt.scala 388:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul1_mulh <= io_in_valid & _e_mul0_mulh_T_1; // @[VAluInt.scala 389:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul1_muls <= io_in_valid & _e_mul0_muls_T_1; // @[VAluInt.scala 390:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mv <= io_in_valid & e_mv; // @[VAluInt.scala 392:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mv2 <= io_in_valid & e_mv2; // @[VAluInt.scala 393:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mvp <= io_in_valid & e_mvp; // @[VAluInt.scala 394:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- shf_l <= io_in_valid & e_shf_l; // @[VAluInt.scala 399:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- shf_r <= io_in_valid & e_shf_r; // @[VAluInt.scala 400:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- shf_shl <= io_in_valid & e_shf_shl; // @[VAluInt.scala 401:13]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- shf_shr <= io_in_valid & e_shf_shr; // @[VAluInt.scala 402:13]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- shf_shf <= io_in_valid & e_shf_shf; // @[VAluInt.scala 403:13]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~io_in_valid | _T_6[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 63:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~io_in_valid | _T_6[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:63 assert(!io.in.valid || PopCount(io.in.sz) <= 1.U)\n"); // @[VAluInt.scala 63:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_11 & ~(_T_28 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 115:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_11 & ~(_T_28 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:115 assert(PopCount(Cat(e_cmp_eq, e_cmp_ne, e_cmp_lt, e_cmp_le, e_cmp_gt, e_cmp_ge)) <= 1.U)\n"
- ); // @[VAluInt.scala 115:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_11 & ~(_T_58 <= 4'h1)) begin
- $fatal; // @[VAluInt.scala 127:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_11 & ~(_T_58 <= 4'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:127 assert(PopCount(Cat(e_log_and, e_log_or, e_log_xor, e_log_not, e_log_rev, e_log_ror, e_log_clb, e_log_clz, e_log_cpop)) <= 1.U)\n"
- ); // @[VAluInt.scala 127:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_dmulh_T_1 & ~e_mul0_dmulh))) begin
- $fatal; // @[VAluInt.scala 167:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_dmulh_T_1 & ~e_mul0_dmulh))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:167 assert(!(e_mul1_dmulh && !e_mul0_dmulh))\n"); // @[VAluInt.scala 167:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_mul_T_1 & ~e_mul0_mul))) begin
- $fatal; // @[VAluInt.scala 168:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_mul_T_1 & ~e_mul0_mul))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:168 assert(!(e_mul1_mul && !e_mul0_mul))\n"); // @[VAluInt.scala 168:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_mulh_T_1 & ~e_mul0_mulh))) begin
- $fatal; // @[VAluInt.scala 169:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_mulh_T_1 & ~e_mul0_mulh))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:169 assert(!(e_mul1_mulh && !e_mul0_mulh))\n"); // @[VAluInt.scala 169:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_muls_T_1 & ~e_mul0_muls))) begin
- $fatal; // @[VAluInt.scala 170:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_muls_T_1 & ~e_mul0_muls))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:170 assert(!(e_mul1_muls && !e_mul0_muls))\n"); // @[VAluInt.scala 170:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 187:22]
- vdvalid0 <= 1'h0; // @[VAluInt.scala 192:14]
- end else if (io_in_valid) begin // @[VAluInt.scala 198:38]
- vdvalid0 <= nxt_vdvalid; // @[VAluInt.scala 199:14]
- end else if (vdvalid0 | vevalid0) begin // @[VAluInt.scala 174:25]
- vdvalid0 <= 1'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 208:24]
- vdvalid1 <= 1'h0;
- end else begin
- vdvalid1 <= vdvalid0 & ~wmask;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 187:22]
- vevalid0 <= 1'h0; // @[VAluInt.scala 193:14]
- end else if (io_in_valid) begin // @[VAluInt.scala 198:38]
- vevalid0 <= nxt_vevalid; // @[VAluInt.scala 200:14]
- end else if (vdvalid0 | vevalid0) begin // @[VAluInt.scala 176:25]
- vevalid0 <= 1'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 209:24]
- vevalid1 <= 1'h0;
- end else begin
- vevalid1 <= vevalid0 & _vdvalid1_T;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 187:22]
- wmask <= 1'h0; // @[VAluInt.scala 194:11]
- end else if (io_in_valid) begin // @[VAluInt.scala 198:38]
- wmask <= _e_dwconv_T_1; // @[VAluInt.scala 201:11]
- end else if (vdvalid0 | vevalid0) begin // @[VAluInt.scala 178:22]
- wmask <= 1'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 187:22]
- sz <= 3'h0; // @[Library.scala 32:8 VAluInt.scala 195:48]
- end else if (io_in_valid) begin // @[VAluInt.scala 198:38]
- if (_sz_T) begin // @[VAluInt.scala 202:8]
- if (nxt_widen) begin
- sz <= _sz_T_1;
- end else begin
- sz <= io_in_sz;
- end
- end else begin
- sz <= 3'h0;
- end
- end else if (vdvalid0 | vevalid0) begin // @[VAluInt.scala 183:19]
- sz <= 3'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 187:22]
- f2 <= 3'h0; // @[VAluInt.scala 196:8]
- end else if (io_in_valid) begin // @[VAluInt.scala 198:38]
- f2 <= io_in_f2; // @[VAluInt.scala 203:8]
- end else if (vdvalid0 | vevalid0) begin // @[VAluInt.scala 184:19]
- f2 <= 3'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 187:22]
- sv <= 32'h0; // @[VAluInt.scala 197:8]
- end else if (io_in_valid) begin // @[VAluInt.scala 198:38]
- sv <= io_in_sv_data; // @[VAluInt.scala 204:8]
- end else if (vdvalid0 | vevalid0) begin // @[VAluInt.scala 185:19]
- sv <= 32'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 322:25]
- validClr <= 1'h0; // @[VAluInt.scala 322:25]
- end else begin
- validClr <= io_in_valid; // @[VAluInt.scala 323:12]
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- vdvalid0 = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- vdvalid1 = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- vevalid0 = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- vevalid1 = _RAND_3[0:0];
- _RAND_4 = {1{`RANDOM}};
- wmask = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- vdaddr0_addr = _RAND_5[5:0];
- _RAND_6 = {1{`RANDOM}};
- vdaddr1_addr = _RAND_6[5:0];
- _RAND_7 = {1{`RANDOM}};
- veaddr0_addr = _RAND_7[5:0];
- _RAND_8 = {1{`RANDOM}};
- veaddr1_addr = _RAND_8[5:0];
- _RAND_9 = {1{`RANDOM}};
- sz = _RAND_9[2:0];
- _RAND_10 = {1{`RANDOM}};
- f2 = _RAND_10[2:0];
- _RAND_11 = {1{`RANDOM}};
- sv = _RAND_11[31:0];
- _RAND_12 = {1{`RANDOM}};
- negative = _RAND_12[0:0];
- _RAND_13 = {1{`RANDOM}};
- round = _RAND_13[0:0];
- _RAND_14 = {1{`RANDOM}};
- signed_ = _RAND_14[0:0];
- _RAND_15 = {1{`RANDOM}};
- absd = _RAND_15[0:0];
- _RAND_16 = {1{`RANDOM}};
- acc = _RAND_16[0:0];
- _RAND_17 = {1{`RANDOM}};
- dup = _RAND_17[0:0];
- _RAND_18 = {1{`RANDOM}};
- max = _RAND_18[0:0];
- _RAND_19 = {1{`RANDOM}};
- min = _RAND_19[0:0];
- _RAND_20 = {1{`RANDOM}};
- srans = _RAND_20[0:0];
- _RAND_21 = {1{`RANDOM}};
- sraqs = _RAND_21[0:0];
- _RAND_22 = {1{`RANDOM}};
- slidevn = _RAND_22[0:0];
- _RAND_23 = {1{`RANDOM}};
- slidevp = _RAND_23[0:0];
- _RAND_24 = {1{`RANDOM}};
- slidehn2 = _RAND_24[0:0];
- _RAND_25 = {1{`RANDOM}};
- slidehp2 = _RAND_25[0:0];
- _RAND_26 = {1{`RANDOM}};
- sel = _RAND_26[0:0];
- _RAND_27 = {1{`RANDOM}};
- evn = _RAND_27[0:0];
- _RAND_28 = {1{`RANDOM}};
- odd = _RAND_28[0:0];
- _RAND_29 = {1{`RANDOM}};
- zip = _RAND_29[0:0];
- _RAND_30 = {1{`RANDOM}};
- dwinit = _RAND_30[0:0];
- _RAND_31 = {1{`RANDOM}};
- dwconv = _RAND_31[0:0];
- _RAND_32 = {1{`RANDOM}};
- dwconvData = _RAND_32[0:0];
- _RAND_33 = {1{`RANDOM}};
- add = _RAND_33[0:0];
- _RAND_34 = {1{`RANDOM}};
- add_add = _RAND_34[0:0];
- _RAND_35 = {1{`RANDOM}};
- add_adds = _RAND_35[0:0];
- _RAND_36 = {1{`RANDOM}};
- add_addw = _RAND_36[0:0];
- _RAND_37 = {1{`RANDOM}};
- add_add3 = _RAND_37[0:0];
- _RAND_38 = {1{`RANDOM}};
- add_hadd = _RAND_38[0:0];
- _RAND_39 = {1{`RANDOM}};
- padd = _RAND_39[0:0];
- _RAND_40 = {1{`RANDOM}};
- padd_add = _RAND_40[0:0];
- _RAND_41 = {1{`RANDOM}};
- padd_sub = _RAND_41[0:0];
- _RAND_42 = {1{`RANDOM}};
- rsub = _RAND_42[0:0];
- _RAND_43 = {1{`RANDOM}};
- rsub_rsub = _RAND_43[0:0];
- _RAND_44 = {1{`RANDOM}};
- sub = _RAND_44[0:0];
- _RAND_45 = {1{`RANDOM}};
- sub_sub = _RAND_45[0:0];
- _RAND_46 = {1{`RANDOM}};
- sub_subs = _RAND_46[0:0];
- _RAND_47 = {1{`RANDOM}};
- sub_subw = _RAND_47[0:0];
- _RAND_48 = {1{`RANDOM}};
- sub_hsub = _RAND_48[0:0];
- _RAND_49 = {1{`RANDOM}};
- cmp = _RAND_49[0:0];
- _RAND_50 = {1{`RANDOM}};
- cmp_eq = _RAND_50[0:0];
- _RAND_51 = {1{`RANDOM}};
- cmp_ne = _RAND_51[0:0];
- _RAND_52 = {1{`RANDOM}};
- cmp_lt = _RAND_52[0:0];
- _RAND_53 = {1{`RANDOM}};
- cmp_le = _RAND_53[0:0];
- _RAND_54 = {1{`RANDOM}};
- cmp_gt = _RAND_54[0:0];
- _RAND_55 = {1{`RANDOM}};
- cmp_ge = _RAND_55[0:0];
- _RAND_56 = {1{`RANDOM}};
- log = _RAND_56[0:0];
- _RAND_57 = {1{`RANDOM}};
- log_and = _RAND_57[0:0];
- _RAND_58 = {1{`RANDOM}};
- log_or = _RAND_58[0:0];
- _RAND_59 = {1{`RANDOM}};
- log_xor = _RAND_59[0:0];
- _RAND_60 = {1{`RANDOM}};
- log_not = _RAND_60[0:0];
- _RAND_61 = {1{`RANDOM}};
- log_rev = _RAND_61[0:0];
- _RAND_62 = {1{`RANDOM}};
- log_ror = _RAND_62[0:0];
- _RAND_63 = {1{`RANDOM}};
- log_clb = _RAND_63[0:0];
- _RAND_64 = {1{`RANDOM}};
- log_clz = _RAND_64[0:0];
- _RAND_65 = {1{`RANDOM}};
- log_cpop = _RAND_65[0:0];
- _RAND_66 = {1{`RANDOM}};
- mul0 = _RAND_66[0:0];
- _RAND_67 = {1{`RANDOM}};
- mul0_dmulh = _RAND_67[0:0];
- _RAND_68 = {1{`RANDOM}};
- mul0_mul = _RAND_68[0:0];
- _RAND_69 = {1{`RANDOM}};
- mul0_mulh = _RAND_69[0:0];
- _RAND_70 = {1{`RANDOM}};
- mul0_muls = _RAND_70[0:0];
- _RAND_71 = {1{`RANDOM}};
- mul0_mulw = _RAND_71[0:0];
- _RAND_72 = {1{`RANDOM}};
- mul0_madd = _RAND_72[0:0];
- _RAND_73 = {1{`RANDOM}};
- mul1 = _RAND_73[0:0];
- _RAND_74 = {1{`RANDOM}};
- mul1_dmulh = _RAND_74[0:0];
- _RAND_75 = {1{`RANDOM}};
- mul1_mul = _RAND_75[0:0];
- _RAND_76 = {1{`RANDOM}};
- mul1_mulh = _RAND_76[0:0];
- _RAND_77 = {1{`RANDOM}};
- mul1_muls = _RAND_77[0:0];
- _RAND_78 = {1{`RANDOM}};
- mv = _RAND_78[0:0];
- _RAND_79 = {1{`RANDOM}};
- mv2 = _RAND_79[0:0];
- _RAND_80 = {1{`RANDOM}};
- mvp = _RAND_80[0:0];
- _RAND_81 = {1{`RANDOM}};
- shf_l = _RAND_81[0:0];
- _RAND_82 = {1{`RANDOM}};
- shf_r = _RAND_82[0:0];
- _RAND_83 = {1{`RANDOM}};
- shf_shl = _RAND_83[0:0];
- _RAND_84 = {1{`RANDOM}};
- shf_shr = _RAND_84[0:0];
- _RAND_85 = {1{`RANDOM}};
- shf_shf = _RAND_85[0:0];
- _RAND_86 = {1{`RANDOM}};
- validClr = _RAND_86[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- vdvalid0 = 1'h0;
- end
- if (reset) begin
- vdvalid1 = 1'h0;
- end
- if (reset) begin
- vevalid0 = 1'h0;
- end
- if (reset) begin
- vevalid1 = 1'h0;
- end
- if (reset) begin
- wmask = 1'h0;
- end
- if (reset) begin
- sz = 3'h0;
- end
- if (reset) begin
- f2 = 3'h0;
- end
- if (reset) begin
- sv = 32'h0;
- end
- if (reset) begin
- validClr = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VAluInt_1(
- input clock,
- input reset,
- input io_in_valid,
- input [6:0] io_in_op,
- input [2:0] io_in_f2,
- input [2:0] io_in_sz,
- input [5:0] io_in_vd_addr,
- input [5:0] io_in_ve_addr,
- input [31:0] io_in_sv_data,
- input [255:0] io_read_0_data,
- input [255:0] io_read_1_data,
- input [255:0] io_read_2_data,
- input [255:0] io_read_3_data,
- input [255:0] io_read_4_data,
- input [255:0] io_read_5_data,
- output io_write_0_valid,
- output [5:0] io_write_0_addr,
- output [255:0] io_write_0_data,
- output io_write_1_valid,
- output [5:0] io_write_1_addr,
- output [255:0] io_write_1_data,
- output io_whint_0_valid,
- output [5:0] io_whint_0_addr,
- output io_whint_1_valid,
- output [5:0] io_whint_1_addr
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
- reg [31:0] _RAND_34;
- reg [31:0] _RAND_35;
- reg [31:0] _RAND_36;
- reg [31:0] _RAND_37;
- reg [31:0] _RAND_38;
- reg [31:0] _RAND_39;
- reg [31:0] _RAND_40;
- reg [31:0] _RAND_41;
- reg [31:0] _RAND_42;
- reg [31:0] _RAND_43;
- reg [31:0] _RAND_44;
- reg [31:0] _RAND_45;
- reg [31:0] _RAND_46;
- reg [31:0] _RAND_47;
- reg [31:0] _RAND_48;
- reg [31:0] _RAND_49;
- reg [31:0] _RAND_50;
- reg [31:0] _RAND_51;
- reg [31:0] _RAND_52;
- reg [31:0] _RAND_53;
- reg [31:0] _RAND_54;
- reg [31:0] _RAND_55;
- reg [31:0] _RAND_56;
- reg [31:0] _RAND_57;
- reg [31:0] _RAND_58;
- reg [31:0] _RAND_59;
- reg [31:0] _RAND_60;
- reg [31:0] _RAND_61;
- reg [31:0] _RAND_62;
- reg [31:0] _RAND_63;
- reg [31:0] _RAND_64;
- reg [31:0] _RAND_65;
- reg [31:0] _RAND_66;
- reg [31:0] _RAND_67;
- reg [31:0] _RAND_68;
- reg [31:0] _RAND_69;
- reg [31:0] _RAND_70;
- reg [31:0] _RAND_71;
- reg [31:0] _RAND_72;
- reg [31:0] _RAND_73;
- reg [31:0] _RAND_74;
- reg [31:0] _RAND_75;
- reg [31:0] _RAND_76;
- reg [31:0] _RAND_77;
- reg [31:0] _RAND_78;
- reg [31:0] _RAND_79;
- reg [31:0] _RAND_80;
- reg [31:0] _RAND_81;
- reg [31:0] _RAND_82;
- reg [31:0] _RAND_83;
- reg [31:0] _RAND_84;
- reg [31:0] _RAND_85;
-`endif // RANDOMIZE_REG_INIT
- wire valu_0_clock; // @[VAluInt.scala 418:11]
- wire valu_0_reset; // @[VAluInt.scala 418:11]
- wire valu_0_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_0_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_0_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_0_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_0_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_0_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_0_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_0_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_1_clock; // @[VAluInt.scala 418:11]
- wire valu_1_reset; // @[VAluInt.scala 418:11]
- wire valu_1_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_1_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_1_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_1_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_1_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_1_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_1_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_1_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_2_clock; // @[VAluInt.scala 418:11]
- wire valu_2_reset; // @[VAluInt.scala 418:11]
- wire valu_2_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_2_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_2_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_2_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_2_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_2_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_2_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_2_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_3_clock; // @[VAluInt.scala 418:11]
- wire valu_3_reset; // @[VAluInt.scala 418:11]
- wire valu_3_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_3_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_3_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_3_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_3_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_3_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_3_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_3_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_4_clock; // @[VAluInt.scala 418:11]
- wire valu_4_reset; // @[VAluInt.scala 418:11]
- wire valu_4_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_4_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_4_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_4_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_4_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_4_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_4_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_4_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_5_clock; // @[VAluInt.scala 418:11]
- wire valu_5_reset; // @[VAluInt.scala 418:11]
- wire valu_5_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_5_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_5_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_5_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_5_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_5_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_5_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_5_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_6_clock; // @[VAluInt.scala 418:11]
- wire valu_6_reset; // @[VAluInt.scala 418:11]
- wire valu_6_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_6_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_6_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_6_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_6_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_6_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_6_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_6_io_load_1; // @[VAluInt.scala 418:11]
- wire valu_7_clock; // @[VAluInt.scala 418:11]
- wire valu_7_reset; // @[VAluInt.scala 418:11]
- wire valu_7_io_in_vdvalid; // @[VAluInt.scala 418:11]
- wire valu_7_io_in_vevalid; // @[VAluInt.scala 418:11]
- wire [2:0] valu_7_io_in_sz; // @[VAluInt.scala 418:11]
- wire valu_7_io_in_negative; // @[VAluInt.scala 418:11]
- wire valu_7_io_in_round; // @[VAluInt.scala 418:11]
- wire valu_7_io_in_signed; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_absd; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_acc; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_dup; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_max; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_min; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mv; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mv2; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mvp; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_srans; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_sraqs; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_dwinit; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_dwconv; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_dwconvData; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_add_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_add_add; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_add_adds; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_add_addw; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_add_add3; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_add_hadd; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_eq; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_ne; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_lt; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_le; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_gt; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_cmp_ge; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_and; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_or; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_xor; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_not; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_rev; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_ror; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_clb; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_clz; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_log_cpop; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_dmulh; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_mul; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_mulh; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_muls; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_mulw; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul0_madd; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul1_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul1_dmulh; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul1_mul; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul1_mulh; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_mul1_muls; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_padd_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_padd_add; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_padd_sub; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_rsub_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_rsub_rsub; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_shf_en_l; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_shf_en_r; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_shf_shl; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_shf_shr; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_shf_shf; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_sub_en; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_sub_sub; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_sub_subs; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_sub_subw; // @[VAluInt.scala 418:11]
- wire valu_7_io_op_sub_hsub; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_read_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_read_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_read_2_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_read_3_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_read_5_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_write_0_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_write_1_data; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_load_0; // @[VAluInt.scala 418:11]
- wire [31:0] valu_7_io_load_1; // @[VAluInt.scala 418:11]
- wire [1:0] _T_4 = io_in_sz[1] + io_in_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_89 = {{1'd0}, io_in_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_6 = _GEN_89 + _T_4; // @[Bitwise.scala 48:55]
- wire _T_11 = ~reset; // @[VAluInt.scala 63:9]
- wire e_absd = io_in_op == 7'hf; // @[VAluInt.scala 79:26]
- wire e_acc = io_in_op == 7'h35; // @[VAluInt.scala 80:26]
- wire e_dup = io_in_op == 7'h1; // @[VAluInt.scala 81:26]
- wire e_max = io_in_op == 7'h10; // @[VAluInt.scala 82:26]
- wire e_min = io_in_op == 7'h11; // @[VAluInt.scala 83:26]
- wire e_rsub = io_in_op == 7'h8; // @[VAluInt.scala 84:26]
- wire e_srans = io_in_op == 7'h25; // @[VAluInt.scala 85:26]
- wire _e_slidevn_T_3 = io_in_op == 7'h3c; // @[VAluInt.scala 88:86]
- wire e_slidevn = io_in_op == 7'h3a | io_in_op == 7'h3b | io_in_op == 7'h3c; // @[VAluInt.scala 88:74]
- wire _e_slidevp_T_3 = io_in_op == 7'h3f; // @[VAluInt.scala 89:86]
- wire e_slidevp = io_in_op == 7'h3d | io_in_op == 7'h3e | io_in_op == 7'h3f; // @[VAluInt.scala 89:74]
- wire e_sel = io_in_op == 7'h40; // @[VAluInt.scala 92:24]
- wire _e_evn_T_1 = io_in_op == 7'h43; // @[VAluInt.scala 93:49]
- wire e_evn = io_in_op == 7'h41 | io_in_op == 7'h43; // @[VAluInt.scala 93:37]
- wire e_odd = io_in_op == 7'h42 | _e_evn_T_1; // @[VAluInt.scala 94:37]
- wire e_zip = io_in_op == 7'h44; // @[VAluInt.scala 95:24]
- wire e_dwinit = io_in_op == 7'h21; // @[VAluInt.scala 97:27]
- wire _e_dwconv_T_1 = io_in_op == 7'h47; // @[VAluInt.scala 98:55]
- wire e_dwconv = io_in_op == 7'h46 | io_in_op == 7'h47; // @[VAluInt.scala 98:43]
- wire e_add_add = io_in_op == 7'h6; // @[VAluInt.scala 101:29]
- wire e_add_adds = io_in_op == 7'h31; // @[VAluInt.scala 102:29]
- wire e_add_addw = io_in_op == 7'h33; // @[VAluInt.scala 103:29]
- wire e_add_add3 = io_in_op == 7'h12; // @[VAluInt.scala 104:29]
- wire e_add_hadd = io_in_op == 7'h38; // @[VAluInt.scala 105:29]
- wire e_add = e_add_add | e_add_adds | e_add_addw | e_add_add3 | e_add_hadd; // @[VAluInt.scala 106:67]
- wire e_cmp_eq = io_in_op == 7'h9; // @[VAluInt.scala 108:27]
- wire e_cmp_ne = io_in_op == 7'ha; // @[VAluInt.scala 109:27]
- wire e_cmp_lt = io_in_op == 7'hb; // @[VAluInt.scala 110:27]
- wire e_cmp_le = io_in_op == 7'hc; // @[VAluInt.scala 111:27]
- wire e_cmp_gt = io_in_op == 7'hd; // @[VAluInt.scala 112:27]
- wire e_cmp_ge = io_in_op == 7'he; // @[VAluInt.scala 113:27]
- wire e_cmp = e_cmp_eq | e_cmp_ne | e_cmp_lt | e_cmp_le | e_cmp_gt | e_cmp_ge; // @[VAluInt.scala 114:75]
- wire [5:0] _T_13 = {e_cmp_eq,e_cmp_ne,e_cmp_lt,e_cmp_le,e_cmp_gt,e_cmp_ge}; // @[Cat.scala 31:58]
- wire [1:0] _T_20 = _T_13[1] + _T_13[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_90 = {{1'd0}, _T_13[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_22 = _GEN_90 + _T_20; // @[Bitwise.scala 48:55]
- wire [1:0] _T_24 = _T_13[4] + _T_13[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_91 = {{1'd0}, _T_13[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_26 = _GEN_91 + _T_24; // @[Bitwise.scala 48:55]
- wire [2:0] _T_28 = _T_22[1:0] + _T_26[1:0]; // @[Bitwise.scala 48:55]
- wire e_log_and = io_in_op == 7'h13; // @[VAluInt.scala 117:29]
- wire e_log_or = io_in_op == 7'h14; // @[VAluInt.scala 118:29]
- wire e_log_xor = io_in_op == 7'h15; // @[VAluInt.scala 119:29]
- wire e_log_not = io_in_op == 7'h16; // @[VAluInt.scala 120:29]
- wire e_log_rev = io_in_op == 7'h17; // @[VAluInt.scala 121:29]
- wire e_log_ror = io_in_op == 7'h18; // @[VAluInt.scala 122:29]
- wire e_log_clb = io_in_op == 7'h19; // @[VAluInt.scala 123:29]
- wire e_log_clz = io_in_op == 7'h1a; // @[VAluInt.scala 124:29]
- wire e_log_cpop = io_in_op == 7'h1b; // @[VAluInt.scala 125:29]
- wire e_log = e_log_and | e_log_or | e_log_xor | e_log_not | e_log_rev | e_log_ror | e_log_clb | e_log_clz |
- e_log_cpop; // @[VAluInt.scala 126:115]
- wire [8:0] _T_34 = {e_log_and,e_log_or,e_log_xor,e_log_not,e_log_rev,e_log_ror,e_log_clb,e_log_clz,e_log_cpop}; // @[Cat.scala 31:58]
- wire [1:0] _T_44 = _T_34[0] + _T_34[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_46 = _T_34[2] + _T_34[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_48 = _T_44 + _T_46; // @[Bitwise.scala 48:55]
- wire [1:0] _T_50 = _T_34[4] + _T_34[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_52 = _T_34[7] + _T_34[8]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_92 = {{1'd0}, _T_34[6]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_54 = _GEN_92 + _T_52; // @[Bitwise.scala 48:55]
- wire [2:0] _T_56 = _T_50 + _T_54[1:0]; // @[Bitwise.scala 48:55]
- wire [3:0] _T_58 = _T_48 + _T_56; // @[Bitwise.scala 48:55]
- wire _e_mul0_dmulh_T_1 = io_in_op == 7'h2e; // @[VAluInt.scala 129:58]
- wire e_mul0_dmulh = io_in_op == 7'h2d | io_in_op == 7'h2e; // @[VAluInt.scala 129:46]
- wire _e_mul0_mul_T_1 = io_in_op == 7'h28; // @[VAluInt.scala 130:56]
- wire e_mul0_mul = io_in_op == 7'h27 | io_in_op == 7'h28; // @[VAluInt.scala 130:44]
- wire _e_mul0_mulh_T_1 = io_in_op == 7'h2c; // @[VAluInt.scala 131:57]
- wire e_mul0_mulh = io_in_op == 7'h2b | io_in_op == 7'h2c; // @[VAluInt.scala 131:45]
- wire _e_mul0_muls_T_1 = io_in_op == 7'h2a; // @[VAluInt.scala 132:57]
- wire e_mul0_muls = io_in_op == 7'h29 | io_in_op == 7'h2a; // @[VAluInt.scala 132:45]
- wire e_mul0_mulw = io_in_op == 7'h2f; // @[VAluInt.scala 133:31]
- wire e_mul0_madd = io_in_op == 7'h30; // @[VAluInt.scala 134:31]
- wire e_mul0 = e_mul0_dmulh | e_mul0_mul | e_mul0_mulh | e_mul0_muls | e_mul0_mulw | e_mul0_madd; // @[VAluInt.scala 135:88]
- wire e_mul1 = _e_mul0_dmulh_T_1 | _e_mul0_mul_T_1 | _e_mul0_mulh_T_1 | _e_mul0_muls_T_1; // @[VAluInt.scala 141:58]
- wire e_mv2 = io_in_op == 7'h1d; // @[VAluInt.scala 143:24]
- wire e_mvp = io_in_op == 7'h1e; // @[VAluInt.scala 144:24]
- wire e_mv = io_in_op == 7'h1c | e_mv2 | e_mvp; // @[VAluInt.scala 145:45]
- wire e_padd_add = io_in_op == 7'h36; // @[VAluInt.scala 147:29]
- wire e_padd_sub = io_in_op == 7'h37; // @[VAluInt.scala 148:29]
- wire e_padd = e_padd_add | e_padd_sub; // @[VAluInt.scala 149:27]
- wire e_shf_shl = io_in_op == 7'h22; // @[VAluInt.scala 151:28]
- wire e_shf_shr = io_in_op == 7'h23; // @[VAluInt.scala 152:28]
- wire e_shf_shf = io_in_op == 7'h24; // @[VAluInt.scala 153:28]
- wire e_shf_l = e_shf_shl | e_shf_shf; // @[VAluInt.scala 154:27]
- wire e_shf_r = e_shf_shr | e_shf_shf; // @[VAluInt.scala 155:27]
- wire e_sub_sub = io_in_op == 7'h7; // @[VAluInt.scala 157:29]
- wire e_sub_subs = io_in_op == 7'h32; // @[VAluInt.scala 158:29]
- wire e_sub_subw = io_in_op == 7'h34; // @[VAluInt.scala 159:29]
- wire e_sub_hsub = io_in_op == 7'h39; // @[VAluInt.scala 160:29]
- wire e_sub = e_sub_sub | e_sub_subs | e_sub_subw | e_sub_hsub; // @[VAluInt.scala 161:53]
- wire e_negative = io_in_f2[0] & e_mul0_dmulh; // @[VAluInt.scala 163:32]
- wire e_round = io_in_f2[1] & (e_add_hadd | e_sub_hsub | e_mul0_dmulh | e_mul0_mulh | e_shf_shf | e_srans); // @[VAluInt.scala 164:32]
- wire e_signed = ~io_in_f2[0] | e_mul0_dmulh; // @[VAluInt.scala 165:33]
- reg vdvalid0; // @[VAluInt.scala 174:25]
- reg vdvalid1; // @[VAluInt.scala 175:25]
- reg vevalid0; // @[VAluInt.scala 176:25]
- reg vevalid1; // @[VAluInt.scala 177:25]
- reg wmask; // @[VAluInt.scala 178:22]
- reg [5:0] vdaddr0_addr; // @[VAluInt.scala 179:20]
- reg [5:0] vdaddr1_addr; // @[VAluInt.scala 180:20]
- reg [5:0] veaddr0_addr; // @[VAluInt.scala 181:20]
- reg [5:0] veaddr1_addr; // @[VAluInt.scala 182:20]
- reg [2:0] sz; // @[VAluInt.scala 183:19]
- reg [2:0] f2; // @[VAluInt.scala 184:19]
- reg [31:0] sv; // @[VAluInt.scala 185:19]
- wire nxt_vdvalid = e_dwconv | e_mul0 | e_absd | e_acc | e_add | e_cmp | e_dup | e_log | e_evn | e_max | e_min | e_mv
- | e_padd | e_rsub | e_sel | e_shf_l | e_shf_r | e_slidevn | e_slidevp | e_srans | e_sub | e_zip; // @[VAluInt.scala 189:240]
- wire nxt_vevalid = e_dwconv | e_mul1 | e_mul0_mulw | e_acc | e_add_addw | e_mv2 | e_mvp | e_odd | _e_slidevn_T_3 |
- _e_slidevp_T_3 | e_sub_subw | e_zip; // @[VAluInt.scala 190:149]
- wire nxt_widen = e_acc | e_add_addw | e_mul0_mulw | e_sub_subw; // @[VAluInt.scala 191:56]
- wire _sz_T = nxt_vdvalid | nxt_vevalid; // @[VAluInt.scala 195:29]
- wire [2:0] _sz_T_1 = {{1'd0}, io_in_sz[2:1]}; // @[VAluInt.scala 195:69]
- wire _vdvalid1_T = ~wmask; // @[VAluInt.scala 208:27]
- reg negative; // @[VAluInt.scala 226:21]
- reg round; // @[VAluInt.scala 227:21]
- reg signed_; // @[VAluInt.scala 228:21]
- reg absd; // @[VAluInt.scala 238:18]
- reg acc; // @[VAluInt.scala 239:18]
- reg dup; // @[VAluInt.scala 240:18]
- reg max; // @[VAluInt.scala 241:18]
- reg min; // @[VAluInt.scala 242:18]
- reg srans; // @[VAluInt.scala 243:18]
- reg slidevn; // @[VAluInt.scala 246:21]
- reg slidevp; // @[VAluInt.scala 247:21]
- reg slidehn2; // @[VAluInt.scala 248:21]
- reg slidehp2; // @[VAluInt.scala 249:21]
- reg sel; // @[VAluInt.scala 250:21]
- reg evn; // @[VAluInt.scala 251:21]
- reg odd; // @[VAluInt.scala 252:21]
- reg zip; // @[VAluInt.scala 253:21]
- reg dwinit; // @[VAluInt.scala 255:23]
- reg dwconv; // @[VAluInt.scala 256:23]
- reg dwconvData; // @[VAluInt.scala 257:23]
- reg add; // @[VAluInt.scala 259:21]
- reg add_add; // @[VAluInt.scala 260:21]
- reg add_adds; // @[VAluInt.scala 261:21]
- reg add_addw; // @[VAluInt.scala 262:21]
- reg add_add3; // @[VAluInt.scala 263:21]
- reg add_hadd; // @[VAluInt.scala 264:21]
- reg padd; // @[VAluInt.scala 266:17]
- reg padd_add; // @[VAluInt.scala 267:21]
- reg padd_sub; // @[VAluInt.scala 268:21]
- reg rsub; // @[VAluInt.scala 270:22]
- reg rsub_rsub; // @[VAluInt.scala 271:22]
- reg sub; // @[VAluInt.scala 273:21]
- reg sub_sub; // @[VAluInt.scala 274:21]
- reg sub_subs; // @[VAluInt.scala 275:21]
- reg sub_subw; // @[VAluInt.scala 276:21]
- reg sub_hsub; // @[VAluInt.scala 277:21]
- reg cmp; // @[VAluInt.scala 279:19]
- reg cmp_eq; // @[VAluInt.scala 280:19]
- reg cmp_ne; // @[VAluInt.scala 281:19]
- reg cmp_lt; // @[VAluInt.scala 282:19]
- reg cmp_le; // @[VAluInt.scala 283:19]
- reg cmp_gt; // @[VAluInt.scala 284:19]
- reg cmp_ge; // @[VAluInt.scala 285:19]
- reg log; // @[VAluInt.scala 287:21]
- reg log_and; // @[VAluInt.scala 288:21]
- reg log_or; // @[VAluInt.scala 289:21]
- reg log_xor; // @[VAluInt.scala 290:21]
- reg log_not; // @[VAluInt.scala 291:21]
- reg log_rev; // @[VAluInt.scala 292:21]
- reg log_ror; // @[VAluInt.scala 293:21]
- reg log_clb; // @[VAluInt.scala 294:21]
- reg log_clz; // @[VAluInt.scala 295:21]
- reg log_cpop; // @[VAluInt.scala 296:21]
- reg mul0; // @[VAluInt.scala 298:23]
- reg mul0_dmulh; // @[VAluInt.scala 299:23]
- reg mul0_mul; // @[VAluInt.scala 300:23]
- reg mul0_mulh; // @[VAluInt.scala 301:23]
- reg mul0_muls; // @[VAluInt.scala 302:23]
- reg mul0_mulw; // @[VAluInt.scala 303:23]
- reg mul0_madd; // @[VAluInt.scala 304:23]
- reg mul1; // @[VAluInt.scala 306:23]
- reg mul1_dmulh; // @[VAluInt.scala 307:23]
- reg mul1_mul; // @[VAluInt.scala 308:23]
- reg mul1_mulh; // @[VAluInt.scala 309:23]
- reg mul1_muls; // @[VAluInt.scala 310:23]
- reg mv; // @[VAluInt.scala 312:16]
- reg mv2; // @[VAluInt.scala 313:16]
- reg mvp; // @[VAluInt.scala 314:16]
- reg shf_l; // @[VAluInt.scala 316:20]
- reg shf_r; // @[VAluInt.scala 317:20]
- reg shf_shl; // @[VAluInt.scala 318:20]
- reg shf_shr; // @[VAluInt.scala 319:20]
- reg shf_shf; // @[VAluInt.scala 320:20]
- reg validClr; // @[VAluInt.scala 322:25]
- wire _evnb_T_4 = evn & sz[0]; // @[VAluInt.scala 677:76]
- wire [255:0] _evnb_T_5 = _evnb_T_4 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] evnb_evnodd_31 = _evnb_T_5[247:240]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_30 = _evnb_T_5[231:224]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_29 = _evnb_T_5[215:208]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_28 = _evnb_T_5[199:192]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_27 = _evnb_T_5[183:176]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_26 = _evnb_T_5[167:160]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_25 = _evnb_T_5[151:144]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_24 = _evnb_T_5[135:128]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_23 = _evnb_T_5[119:112]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_22 = _evnb_T_5[103:96]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_21 = _evnb_T_5[87:80]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_20 = _evnb_T_5[71:64]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_19 = _evnb_T_5[55:48]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_18 = _evnb_T_5[39:32]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_17 = _evnb_T_5[23:16]; // @[VAluInt.scala 668:21]
- wire [7:0] evnb_evnodd_16 = _evnb_T_5[7:0]; // @[VAluInt.scala 668:21]
- wire [63:0] evnb_out_hi_lo = {evnb_evnodd_23,evnb_evnodd_22,evnb_evnodd_21,evnb_evnodd_20,evnb_evnodd_19,
- evnb_evnodd_18,evnb_evnodd_17,evnb_evnodd_16}; // @[VAluInt.scala 671:22]
- wire [255:0] _evnb_T_2 = _evnb_T_4 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] evnb_evnodd_15 = _evnb_T_2[247:240]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_14 = _evnb_T_2[231:224]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_13 = _evnb_T_2[215:208]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_12 = _evnb_T_2[199:192]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_11 = _evnb_T_2[183:176]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_10 = _evnb_T_2[167:160]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_9 = _evnb_T_2[151:144]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_8 = _evnb_T_2[135:128]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_7 = _evnb_T_2[119:112]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_6 = _evnb_T_2[103:96]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_5 = _evnb_T_2[87:80]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_4 = _evnb_T_2[71:64]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_3 = _evnb_T_2[55:48]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_2 = _evnb_T_2[39:32]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_1 = _evnb_T_2[23:16]; // @[VAluInt.scala 661:21]
- wire [7:0] evnb_evnodd_0 = _evnb_T_2[7:0]; // @[VAluInt.scala 661:21]
- wire [63:0] evnb_out_lo_lo = {evnb_evnodd_7,evnb_evnodd_6,evnb_evnodd_5,evnb_evnodd_4,evnb_evnodd_3,evnb_evnodd_2,
- evnb_evnodd_1,evnb_evnodd_0}; // @[VAluInt.scala 671:22]
- wire [127:0] evnb_out_lo = {evnb_evnodd_15,evnb_evnodd_14,evnb_evnodd_13,evnb_evnodd_12,evnb_evnodd_11,evnb_evnodd_10,
- evnb_evnodd_9,evnb_evnodd_8,evnb_out_lo_lo}; // @[VAluInt.scala 671:22]
- wire [255:0] evnb = {evnb_evnodd_31,evnb_evnodd_30,evnb_evnodd_29,evnb_evnodd_28,evnb_evnodd_27,evnb_evnodd_26,
- evnb_evnodd_25,evnb_evnodd_24,evnb_out_hi_lo,evnb_out_lo}; // @[VAluInt.scala 671:22]
- wire _evnh_T_4 = evn & sz[1]; // @[VAluInt.scala 678:76]
- wire [255:0] _evnh_T_5 = _evnh_T_4 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] evnh_evnodd_15 = _evnh_T_5[239:224]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_14 = _evnh_T_5[207:192]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_13 = _evnh_T_5[175:160]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_12 = _evnh_T_5[143:128]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_11 = _evnh_T_5[111:96]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_10 = _evnh_T_5[79:64]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_9 = _evnh_T_5[47:32]; // @[VAluInt.scala 668:21]
- wire [15:0] evnh_evnodd_8 = _evnh_T_5[15:0]; // @[VAluInt.scala 668:21]
- wire [255:0] _evnh_T_2 = _evnh_T_4 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] evnh_evnodd_7 = _evnh_T_2[239:224]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_6 = _evnh_T_2[207:192]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_5 = _evnh_T_2[175:160]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_4 = _evnh_T_2[143:128]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_3 = _evnh_T_2[111:96]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_2 = _evnh_T_2[79:64]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_1 = _evnh_T_2[47:32]; // @[VAluInt.scala 661:21]
- wire [15:0] evnh_evnodd_0 = _evnh_T_2[15:0]; // @[VAluInt.scala 661:21]
- wire [127:0] evnh_out_lo = {evnh_evnodd_7,evnh_evnodd_6,evnh_evnodd_5,evnh_evnodd_4,evnh_evnodd_3,evnh_evnodd_2,
- evnh_evnodd_1,evnh_evnodd_0}; // @[VAluInt.scala 671:22]
- wire [255:0] evnh = {evnh_evnodd_15,evnh_evnodd_14,evnh_evnodd_13,evnh_evnodd_12,evnh_evnodd_11,evnh_evnodd_10,
- evnh_evnodd_9,evnh_evnodd_8,evnh_out_lo}; // @[VAluInt.scala 671:22]
- wire [255:0] _evn0_T = evnb | evnh; // @[VAluInt.scala 684:19]
- wire _evnw_T_4 = evn & sz[2]; // @[VAluInt.scala 679:76]
- wire [255:0] _evnw_T_5 = _evnw_T_4 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] evnw_evnodd_7 = _evnw_T_5[223:192]; // @[VAluInt.scala 668:21]
- wire [31:0] evnw_evnodd_6 = _evnw_T_5[159:128]; // @[VAluInt.scala 668:21]
- wire [31:0] evnw_evnodd_5 = _evnw_T_5[95:64]; // @[VAluInt.scala 668:21]
- wire [31:0] evnw_evnodd_4 = _evnw_T_5[31:0]; // @[VAluInt.scala 668:21]
- wire [255:0] _evnw_T_2 = _evnw_T_4 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] evnw_evnodd_3 = _evnw_T_2[223:192]; // @[VAluInt.scala 661:21]
- wire [31:0] evnw_evnodd_2 = _evnw_T_2[159:128]; // @[VAluInt.scala 661:21]
- wire [31:0] evnw_evnodd_1 = _evnw_T_2[95:64]; // @[VAluInt.scala 661:21]
- wire [31:0] evnw_evnodd_0 = _evnw_T_2[31:0]; // @[VAluInt.scala 661:21]
- wire [255:0] evnw = {evnw_evnodd_7,evnw_evnodd_6,evnw_evnodd_5,evnw_evnodd_4,evnw_evnodd_3,evnw_evnodd_2,evnw_evnodd_1
- ,evnw_evnodd_0}; // @[VAluInt.scala 671:22]
- wire [255:0] evn0 = _evn0_T | evnw; // @[VAluInt.scala 684:26]
- wire _T_94 = zip & sz[0]; // @[VAluInt.scala 720:80]
- wire [255:0] _T_95 = _T_94 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] zip0__31 = _T_95[127:120]; // @[VAluInt.scala 707:21]
- wire [255:0] _T_92 = _T_94 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] zip0__30 = _T_92[127:120]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__29 = _T_95[119:112]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__28 = _T_92[119:112]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__27 = _T_95[111:104]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__26 = _T_92[111:104]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__25 = _T_95[103:96]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__24 = _T_92[103:96]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__23 = _T_95[95:88]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__22 = _T_92[95:88]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__21 = _T_95[87:80]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__20 = _T_92[87:80]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__19 = _T_95[79:72]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__18 = _T_92[79:72]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__17 = _T_95[71:64]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__16 = _T_92[71:64]; // @[VAluInt.scala 704:21]
- wire [63:0] out0_hi_lo = {zip0__23,zip0__22,zip0__21,zip0__20,zip0__19,zip0__18,zip0__17,zip0__16}; // @[VAluInt.scala 712:21]
- wire [7:0] zip0__15 = _T_95[63:56]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__14 = _T_92[63:56]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__13 = _T_95[55:48]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__12 = _T_92[55:48]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__11 = _T_95[47:40]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__10 = _T_92[47:40]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__9 = _T_95[39:32]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__8 = _T_92[39:32]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__7 = _T_95[31:24]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__6 = _T_92[31:24]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__5 = _T_95[23:16]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__4 = _T_92[23:16]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__3 = _T_95[15:8]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__2 = _T_92[15:8]; // @[VAluInt.scala 704:21]
- wire [7:0] zip0__1 = _T_95[7:0]; // @[VAluInt.scala 707:21]
- wire [7:0] zip0__0 = _T_92[7:0]; // @[VAluInt.scala 704:21]
- wire [63:0] out0_lo_lo = {zip0__7,zip0__6,zip0__5,zip0__4,zip0__3,zip0__2,zip0__1,zip0__0}; // @[VAluInt.scala 712:21]
- wire [127:0] out0_lo = {zip0__15,zip0__14,zip0__13,zip0__12,zip0__11,zip0__10,zip0__9,zip0__8,out0_lo_lo}; // @[VAluInt.scala 712:21]
- wire [255:0] zipb0 = {zip0__31,zip0__30,zip0__29,zip0__28,zip0__27,zip0__26,zip0__25,zip0__24,out0_hi_lo,out0_lo}; // @[VAluInt.scala 712:21]
- wire _T_100 = zip & sz[1]; // @[VAluInt.scala 721:80]
- wire [255:0] _T_101 = _T_100 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] zip0_1_15 = _T_101[127:112]; // @[VAluInt.scala 707:21]
- wire [255:0] _T_98 = _T_100 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] zip0_1_14 = _T_98[127:112]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_13 = _T_101[111:96]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_12 = _T_98[111:96]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_11 = _T_101[95:80]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_10 = _T_98[95:80]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_9 = _T_101[79:64]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_8 = _T_98[79:64]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_7 = _T_101[63:48]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_6 = _T_98[63:48]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_5 = _T_101[47:32]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_4 = _T_98[47:32]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_3 = _T_101[31:16]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_2 = _T_98[31:16]; // @[VAluInt.scala 704:21]
- wire [15:0] zip0_1_1 = _T_101[15:0]; // @[VAluInt.scala 707:21]
- wire [15:0] zip0_1_0 = _T_98[15:0]; // @[VAluInt.scala 704:21]
- wire [127:0] out0_lo_1 = {zip0_1_7,zip0_1_6,zip0_1_5,zip0_1_4,zip0_1_3,zip0_1_2,zip0_1_1,zip0_1_0}; // @[VAluInt.scala 712:21]
- wire [255:0] ziph0 = {zip0_1_15,zip0_1_14,zip0_1_13,zip0_1_12,zip0_1_11,zip0_1_10,zip0_1_9,zip0_1_8,out0_lo_1}; // @[VAluInt.scala 712:21]
- wire [255:0] _zip0_T = zipb0 | ziph0; // @[VAluInt.scala 724:20]
- wire _T_106 = zip & sz[2]; // @[VAluInt.scala 722:80]
- wire [255:0] _T_107 = _T_106 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] zip0_2_7 = _T_107[127:96]; // @[VAluInt.scala 707:21]
- wire [255:0] _T_104 = _T_106 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] zip0_2_6 = _T_104[127:96]; // @[VAluInt.scala 704:21]
- wire [31:0] zip0_2_5 = _T_107[95:64]; // @[VAluInt.scala 707:21]
- wire [31:0] zip0_2_4 = _T_104[95:64]; // @[VAluInt.scala 704:21]
- wire [31:0] zip0_2_3 = _T_107[63:32]; // @[VAluInt.scala 707:21]
- wire [31:0] zip0_2_2 = _T_104[63:32]; // @[VAluInt.scala 704:21]
- wire [31:0] zip0_2_1 = _T_107[31:0]; // @[VAluInt.scala 707:21]
- wire [31:0] zip0_2_0 = _T_104[31:0]; // @[VAluInt.scala 704:21]
- wire [255:0] zipw0 = {zip0_2_7,zip0_2_6,zip0_2_5,zip0_2_4,zip0_2_3,zip0_2_2,zip0_2_1,zip0_2_0}; // @[VAluInt.scala 712:21]
- wire [255:0] zip0_3 = _zip0_T | zipw0; // @[VAluInt.scala 724:28]
- wire [255:0] _load_0_T = evn0 | zip0_3; // @[VAluInt.scala 742:19]
- wire _slidenb0_out_T = f2[1:0] == 2'h0; // @[VAluInt.scala 549:25]
- wire _slidenb0_T_5 = slidevn & sz[0]; // @[VAluInt.scala 595:94]
- wire [255:0] _slidenb0_T_6 = _slidenb0_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidenb0_in_32 = _slidenb0_T_6[7:0]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenb0_T_3 = _slidenb0_T_5 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidenb0_in_31 = _slidenb0_T_3[255:248]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_30 = _slidenb0_T_3[247:240]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_29 = _slidenb0_T_3[239:232]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_28 = _slidenb0_T_3[231:224]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_27 = _slidenb0_T_3[223:216]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_26 = _slidenb0_T_3[215:208]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_25 = _slidenb0_T_3[207:200]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_24 = _slidenb0_T_3[199:192]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_23 = _slidenb0_T_3[191:184]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_22 = _slidenb0_T_3[183:176]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_21 = _slidenb0_T_3[175:168]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_20 = _slidenb0_T_3[167:160]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_19 = _slidenb0_T_3[159:152]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_18 = _slidenb0_T_3[151:144]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_17 = _slidenb0_T_3[143:136]; // @[VAluInt.scala 538:23]
- wire [63:0] slidenb0_out_hi_lo = {slidenb0_in_24,slidenb0_in_23,slidenb0_in_22,slidenb0_in_21,slidenb0_in_20,
- slidenb0_in_19,slidenb0_in_18,slidenb0_in_17}; // @[VAluInt.scala 549:40]
- wire [7:0] slidenb0_in_16 = _slidenb0_T_3[135:128]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_15 = _slidenb0_T_3[127:120]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_14 = _slidenb0_T_3[119:112]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_13 = _slidenb0_T_3[111:104]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_12 = _slidenb0_T_3[103:96]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_11 = _slidenb0_T_3[95:88]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_10 = _slidenb0_T_3[87:80]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_9 = _slidenb0_T_3[79:72]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_8 = _slidenb0_T_3[71:64]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_7 = _slidenb0_T_3[63:56]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_6 = _slidenb0_T_3[55:48]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_5 = _slidenb0_T_3[47:40]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_4 = _slidenb0_T_3[39:32]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_3 = _slidenb0_T_3[31:24]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_2 = _slidenb0_T_3[23:16]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb0_in_1 = _slidenb0_T_3[15:8]; // @[VAluInt.scala 538:23]
- wire [63:0] slidenb0_out_lo_lo = {slidenb0_in_8,slidenb0_in_7,slidenb0_in_6,slidenb0_in_5,slidenb0_in_4,slidenb0_in_3,
- slidenb0_in_2,slidenb0_in_1}; // @[VAluInt.scala 549:40]
- wire [127:0] slidenb0_out_lo = {slidenb0_in_16,slidenb0_in_15,slidenb0_in_14,slidenb0_in_13,slidenb0_in_12,
- slidenb0_in_11,slidenb0_in_10,slidenb0_in_9,slidenb0_out_lo_lo}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenb0_out_T_1 = {slidenb0_in_32,slidenb0_in_31,slidenb0_in_30,slidenb0_in_29,slidenb0_in_28,
- slidenb0_in_27,slidenb0_in_26,slidenb0_in_25,slidenb0_out_hi_lo,slidenb0_out_lo}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenb0_out_T_2 = _slidenb0_out_T ? _slidenb0_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire _slidenb0_out_T_3 = f2[1:0] == 2'h1; // @[VAluInt.scala 550:25]
- wire [7:0] slidenb0_in_33 = _slidenb0_T_6[15:8]; // @[VAluInt.scala 539:23]
- wire [63:0] slidenb0_out_hi_lo_1 = {slidenb0_in_25,slidenb0_in_24,slidenb0_in_23,slidenb0_in_22,slidenb0_in_21,
- slidenb0_in_20,slidenb0_in_19,slidenb0_in_18}; // @[VAluInt.scala 550:40]
- wire [63:0] slidenb0_out_lo_lo_1 = {slidenb0_in_9,slidenb0_in_8,slidenb0_in_7,slidenb0_in_6,slidenb0_in_5,
- slidenb0_in_4,slidenb0_in_3,slidenb0_in_2}; // @[VAluInt.scala 550:40]
- wire [127:0] slidenb0_out_lo_1 = {slidenb0_in_17,slidenb0_in_16,slidenb0_in_15,slidenb0_in_14,slidenb0_in_13,
- slidenb0_in_12,slidenb0_in_11,slidenb0_in_10,slidenb0_out_lo_lo_1}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenb0_out_T_4 = {slidenb0_in_33,slidenb0_in_32,slidenb0_in_31,slidenb0_in_30,slidenb0_in_29,
- slidenb0_in_28,slidenb0_in_27,slidenb0_in_26,slidenb0_out_hi_lo_1,slidenb0_out_lo_1}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenb0_out_T_5 = _slidenb0_out_T_3 ? _slidenb0_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenb0_out_T_6 = _slidenb0_out_T_2 | _slidenb0_out_T_5; // @[VAluInt.scala 549:48]
- wire _slidenb0_out_T_7 = f2[1:0] == 2'h2; // @[VAluInt.scala 551:25]
- wire [7:0] slidenb0_in_34 = _slidenb0_T_6[23:16]; // @[VAluInt.scala 539:23]
- wire [63:0] slidenb0_out_hi_lo_2 = {slidenb0_in_26,slidenb0_in_25,slidenb0_in_24,slidenb0_in_23,slidenb0_in_22,
- slidenb0_in_21,slidenb0_in_20,slidenb0_in_19}; // @[VAluInt.scala 551:40]
- wire [63:0] slidenb0_out_lo_lo_2 = {slidenb0_in_10,slidenb0_in_9,slidenb0_in_8,slidenb0_in_7,slidenb0_in_6,
- slidenb0_in_5,slidenb0_in_4,slidenb0_in_3}; // @[VAluInt.scala 551:40]
- wire [127:0] slidenb0_out_lo_2 = {slidenb0_in_18,slidenb0_in_17,slidenb0_in_16,slidenb0_in_15,slidenb0_in_14,
- slidenb0_in_13,slidenb0_in_12,slidenb0_in_11,slidenb0_out_lo_lo_2}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenb0_out_T_8 = {slidenb0_in_34,slidenb0_in_33,slidenb0_in_32,slidenb0_in_31,slidenb0_in_30,
- slidenb0_in_29,slidenb0_in_28,slidenb0_in_27,slidenb0_out_hi_lo_2,slidenb0_out_lo_2}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenb0_out_T_9 = _slidenb0_out_T_7 ? _slidenb0_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenb0_out_T_10 = _slidenb0_out_T_6 | _slidenb0_out_T_9; // @[VAluInt.scala 550:48]
- wire _slidenb0_out_T_11 = f2[1:0] == 2'h3; // @[VAluInt.scala 552:25]
- wire [7:0] slidenb0_in_35 = _slidenb0_T_6[31:24]; // @[VAluInt.scala 539:23]
- wire [63:0] slidenb0_out_hi_lo_3 = {slidenb0_in_27,slidenb0_in_26,slidenb0_in_25,slidenb0_in_24,slidenb0_in_23,
- slidenb0_in_22,slidenb0_in_21,slidenb0_in_20}; // @[VAluInt.scala 552:40]
- wire [63:0] slidenb0_out_lo_lo_3 = {slidenb0_in_11,slidenb0_in_10,slidenb0_in_9,slidenb0_in_8,slidenb0_in_7,
- slidenb0_in_6,slidenb0_in_5,slidenb0_in_4}; // @[VAluInt.scala 552:40]
- wire [127:0] slidenb0_out_lo_3 = {slidenb0_in_19,slidenb0_in_18,slidenb0_in_17,slidenb0_in_16,slidenb0_in_15,
- slidenb0_in_14,slidenb0_in_13,slidenb0_in_12,slidenb0_out_lo_lo_3}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenb0_out_T_12 = {slidenb0_in_35,slidenb0_in_34,slidenb0_in_33,slidenb0_in_32,slidenb0_in_31,
- slidenb0_in_30,slidenb0_in_29,slidenb0_in_28,slidenb0_out_hi_lo_3,slidenb0_out_lo_3}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenb0_out_T_13 = _slidenb0_out_T_11 ? _slidenb0_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidenb0 = _slidenb0_out_T_10 | _slidenb0_out_T_13; // @[VAluInt.scala 551:48]
- wire _slidenh0_T_5 = slidevn & sz[1]; // @[VAluInt.scala 596:94]
- wire [255:0] _slidenh0_T_6 = _slidenh0_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slidenh0_in_16 = _slidenh0_T_6[15:0]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenh0_T_3 = _slidenh0_T_5 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slidenh0_in_15 = _slidenh0_T_3[255:240]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_14 = _slidenh0_T_3[239:224]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_13 = _slidenh0_T_3[223:208]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_12 = _slidenh0_T_3[207:192]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_11 = _slidenh0_T_3[191:176]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_10 = _slidenh0_T_3[175:160]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_9 = _slidenh0_T_3[159:144]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_8 = _slidenh0_T_3[143:128]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_7 = _slidenh0_T_3[127:112]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_6 = _slidenh0_T_3[111:96]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_5 = _slidenh0_T_3[95:80]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_4 = _slidenh0_T_3[79:64]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_3 = _slidenh0_T_3[63:48]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_2 = _slidenh0_T_3[47:32]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh0_in_1 = _slidenh0_T_3[31:16]; // @[VAluInt.scala 538:23]
- wire [127:0] slidenh0_out_lo = {slidenh0_in_8,slidenh0_in_7,slidenh0_in_6,slidenh0_in_5,slidenh0_in_4,slidenh0_in_3,
- slidenh0_in_2,slidenh0_in_1}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenh0_out_T_1 = {slidenh0_in_16,slidenh0_in_15,slidenh0_in_14,slidenh0_in_13,slidenh0_in_12,
- slidenh0_in_11,slidenh0_in_10,slidenh0_in_9,slidenh0_out_lo}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenh0_out_T_2 = _slidenb0_out_T ? _slidenh0_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slidenh0_in_17 = _slidenh0_T_6[31:16]; // @[VAluInt.scala 539:23]
- wire [127:0] slidenh0_out_lo_1 = {slidenh0_in_9,slidenh0_in_8,slidenh0_in_7,slidenh0_in_6,slidenh0_in_5,slidenh0_in_4,
- slidenh0_in_3,slidenh0_in_2}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenh0_out_T_4 = {slidenh0_in_17,slidenh0_in_16,slidenh0_in_15,slidenh0_in_14,slidenh0_in_13,
- slidenh0_in_12,slidenh0_in_11,slidenh0_in_10,slidenh0_out_lo_1}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenh0_out_T_5 = _slidenb0_out_T_3 ? _slidenh0_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenh0_out_T_6 = _slidenh0_out_T_2 | _slidenh0_out_T_5; // @[VAluInt.scala 549:48]
- wire [15:0] slidenh0_in_18 = _slidenh0_T_6[47:32]; // @[VAluInt.scala 539:23]
- wire [127:0] slidenh0_out_lo_2 = {slidenh0_in_10,slidenh0_in_9,slidenh0_in_8,slidenh0_in_7,slidenh0_in_6,slidenh0_in_5
- ,slidenh0_in_4,slidenh0_in_3}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenh0_out_T_8 = {slidenh0_in_18,slidenh0_in_17,slidenh0_in_16,slidenh0_in_15,slidenh0_in_14,
- slidenh0_in_13,slidenh0_in_12,slidenh0_in_11,slidenh0_out_lo_2}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenh0_out_T_9 = _slidenb0_out_T_7 ? _slidenh0_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenh0_out_T_10 = _slidenh0_out_T_6 | _slidenh0_out_T_9; // @[VAluInt.scala 550:48]
- wire [15:0] slidenh0_in_19 = _slidenh0_T_6[63:48]; // @[VAluInt.scala 539:23]
- wire [127:0] slidenh0_out_lo_3 = {slidenh0_in_11,slidenh0_in_10,slidenh0_in_9,slidenh0_in_8,slidenh0_in_7,
- slidenh0_in_6,slidenh0_in_5,slidenh0_in_4}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenh0_out_T_12 = {slidenh0_in_19,slidenh0_in_18,slidenh0_in_17,slidenh0_in_16,slidenh0_in_15,
- slidenh0_in_14,slidenh0_in_13,slidenh0_in_12,slidenh0_out_lo_3}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenh0_out_T_13 = _slidenb0_out_T_11 ? _slidenh0_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidenh0 = _slidenh0_out_T_10 | _slidenh0_out_T_13; // @[VAluInt.scala 551:48]
- wire [255:0] _slide0_T = slidenb0 | slidenh0; // @[VAluInt.scala 611:25]
- wire _slidenw0_T_5 = slidevn & sz[2]; // @[VAluInt.scala 597:94]
- wire [255:0] _slidenw0_T_6 = _slidenw0_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidenw0_in_8 = _slidenw0_T_6[31:0]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw0_T_3 = _slidenw0_T_5 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidenw0_in_7 = _slidenw0_T_3[255:224]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw0_in_6 = _slidenw0_T_3[223:192]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw0_in_5 = _slidenw0_T_3[191:160]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw0_in_4 = _slidenw0_T_3[159:128]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw0_in_3 = _slidenw0_T_3[127:96]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw0_in_2 = _slidenw0_T_3[95:64]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw0_in_1 = _slidenw0_T_3[63:32]; // @[VAluInt.scala 538:23]
- wire [255:0] _slidenw0_out_T_1 = {slidenw0_in_8,slidenw0_in_7,slidenw0_in_6,slidenw0_in_5,slidenw0_in_4,slidenw0_in_3,
- slidenw0_in_2,slidenw0_in_1}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenw0_out_T_2 = _slidenb0_out_T ? _slidenw0_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidenw0_in_9 = _slidenw0_T_6[63:32]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw0_out_T_4 = {slidenw0_in_9,slidenw0_in_8,slidenw0_in_7,slidenw0_in_6,slidenw0_in_5,slidenw0_in_4,
- slidenw0_in_3,slidenw0_in_2}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenw0_out_T_5 = _slidenb0_out_T_3 ? _slidenw0_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenw0_out_T_6 = _slidenw0_out_T_2 | _slidenw0_out_T_5; // @[VAluInt.scala 549:48]
- wire [31:0] slidenw0_in_10 = _slidenw0_T_6[95:64]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw0_out_T_8 = {slidenw0_in_10,slidenw0_in_9,slidenw0_in_8,slidenw0_in_7,slidenw0_in_6,slidenw0_in_5
- ,slidenw0_in_4,slidenw0_in_3}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenw0_out_T_9 = _slidenb0_out_T_7 ? _slidenw0_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenw0_out_T_10 = _slidenw0_out_T_6 | _slidenw0_out_T_9; // @[VAluInt.scala 550:48]
- wire [31:0] slidenw0_in_11 = _slidenw0_T_6[127:96]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw0_out_T_12 = {slidenw0_in_11,slidenw0_in_10,slidenw0_in_9,slidenw0_in_8,slidenw0_in_7,
- slidenw0_in_6,slidenw0_in_5,slidenw0_in_4}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenw0_out_T_13 = _slidenb0_out_T_11 ? _slidenw0_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidenw0 = _slidenw0_out_T_10 | _slidenw0_out_T_13; // @[VAluInt.scala 551:48]
- wire [255:0] _slide0_T_1 = _slide0_T | slidenw0; // @[VAluInt.scala 611:36]
- wire _slidepb0_T_5 = slidevp & sz[0]; // @[VAluInt.scala 603:94]
- wire [255:0] _slidepb0_T_6 = _slidepb0_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidepb0_in_62 = _slidepb0_T_6[247:240]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_61 = _slidepb0_T_6[239:232]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_60 = _slidepb0_T_6[231:224]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_59 = _slidepb0_T_6[223:216]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_58 = _slidepb0_T_6[215:208]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_57 = _slidepb0_T_6[207:200]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_56 = _slidepb0_T_6[199:192]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_55 = _slidepb0_T_6[191:184]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_54 = _slidepb0_T_6[183:176]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_53 = _slidepb0_T_6[175:168]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_52 = _slidepb0_T_6[167:160]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_51 = _slidepb0_T_6[159:152]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_50 = _slidepb0_T_6[151:144]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_49 = _slidepb0_T_6[143:136]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_48 = _slidepb0_T_6[135:128]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_47 = _slidepb0_T_6[127:120]; // @[VAluInt.scala 576:23]
- wire [63:0] slidepb0_out_hi_lo = {slidepb0_in_54,slidepb0_in_53,slidepb0_in_52,slidepb0_in_51,slidepb0_in_50,
- slidepb0_in_49,slidepb0_in_48,slidepb0_in_47}; // @[VAluInt.scala 586:40]
- wire [7:0] slidepb0_in_46 = _slidepb0_T_6[119:112]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_45 = _slidepb0_T_6[111:104]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_44 = _slidepb0_T_6[103:96]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_43 = _slidepb0_T_6[95:88]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_42 = _slidepb0_T_6[87:80]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_41 = _slidepb0_T_6[79:72]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_40 = _slidepb0_T_6[71:64]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_39 = _slidepb0_T_6[63:56]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_38 = _slidepb0_T_6[55:48]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_37 = _slidepb0_T_6[47:40]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_36 = _slidepb0_T_6[39:32]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_35 = _slidepb0_T_6[31:24]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_34 = _slidepb0_T_6[23:16]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_33 = _slidepb0_T_6[15:8]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb0_in_32 = _slidepb0_T_6[7:0]; // @[VAluInt.scala 576:23]
- wire [255:0] _slidepb0_T_3 = _slidepb0_T_5 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidepb0_in_31 = _slidepb0_T_3[255:248]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb0_out_lo_lo = {slidepb0_in_38,slidepb0_in_37,slidepb0_in_36,slidepb0_in_35,slidepb0_in_34,
- slidepb0_in_33,slidepb0_in_32,slidepb0_in_31}; // @[VAluInt.scala 586:40]
- wire [127:0] slidepb0_out_lo = {slidepb0_in_46,slidepb0_in_45,slidepb0_in_44,slidepb0_in_43,slidepb0_in_42,
- slidepb0_in_41,slidepb0_in_40,slidepb0_in_39,slidepb0_out_lo_lo}; // @[VAluInt.scala 586:40]
- wire [255:0] _slidepb0_out_T_1 = {slidepb0_in_62,slidepb0_in_61,slidepb0_in_60,slidepb0_in_59,slidepb0_in_58,
- slidepb0_in_57,slidepb0_in_56,slidepb0_in_55,slidepb0_out_hi_lo,slidepb0_out_lo}; // @[VAluInt.scala 586:40]
- wire [255:0] _slidepb0_out_T_2 = _slidenb0_out_T ? _slidepb0_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [63:0] slidepb0_out_hi_lo_1 = {slidepb0_in_53,slidepb0_in_52,slidepb0_in_51,slidepb0_in_50,slidepb0_in_49,
- slidepb0_in_48,slidepb0_in_47,slidepb0_in_46}; // @[VAluInt.scala 587:40]
- wire [7:0] slidepb0_in_30 = _slidepb0_T_3[247:240]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb0_out_lo_lo_1 = {slidepb0_in_37,slidepb0_in_36,slidepb0_in_35,slidepb0_in_34,slidepb0_in_33,
- slidepb0_in_32,slidepb0_in_31,slidepb0_in_30}; // @[VAluInt.scala 587:40]
- wire [127:0] slidepb0_out_lo_1 = {slidepb0_in_45,slidepb0_in_44,slidepb0_in_43,slidepb0_in_42,slidepb0_in_41,
- slidepb0_in_40,slidepb0_in_39,slidepb0_in_38,slidepb0_out_lo_lo_1}; // @[VAluInt.scala 587:40]
- wire [255:0] _slidepb0_out_T_4 = {slidepb0_in_61,slidepb0_in_60,slidepb0_in_59,slidepb0_in_58,slidepb0_in_57,
- slidepb0_in_56,slidepb0_in_55,slidepb0_in_54,slidepb0_out_hi_lo_1,slidepb0_out_lo_1}; // @[VAluInt.scala 587:40]
- wire [255:0] _slidepb0_out_T_5 = _slidenb0_out_T_3 ? _slidepb0_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepb0_out_T_6 = _slidepb0_out_T_2 | _slidepb0_out_T_5; // @[VAluInt.scala 586:48]
- wire [63:0] slidepb0_out_hi_lo_2 = {slidepb0_in_52,slidepb0_in_51,slidepb0_in_50,slidepb0_in_49,slidepb0_in_48,
- slidepb0_in_47,slidepb0_in_46,slidepb0_in_45}; // @[VAluInt.scala 588:40]
- wire [7:0] slidepb0_in_29 = _slidepb0_T_3[239:232]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb0_out_lo_lo_2 = {slidepb0_in_36,slidepb0_in_35,slidepb0_in_34,slidepb0_in_33,slidepb0_in_32,
- slidepb0_in_31,slidepb0_in_30,slidepb0_in_29}; // @[VAluInt.scala 588:40]
- wire [127:0] slidepb0_out_lo_2 = {slidepb0_in_44,slidepb0_in_43,slidepb0_in_42,slidepb0_in_41,slidepb0_in_40,
- slidepb0_in_39,slidepb0_in_38,slidepb0_in_37,slidepb0_out_lo_lo_2}; // @[VAluInt.scala 588:40]
- wire [255:0] _slidepb0_out_T_8 = {slidepb0_in_60,slidepb0_in_59,slidepb0_in_58,slidepb0_in_57,slidepb0_in_56,
- slidepb0_in_55,slidepb0_in_54,slidepb0_in_53,slidepb0_out_hi_lo_2,slidepb0_out_lo_2}; // @[VAluInt.scala 588:40]
- wire [255:0] _slidepb0_out_T_9 = _slidenb0_out_T_7 ? _slidepb0_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepb0_out_T_10 = _slidepb0_out_T_6 | _slidepb0_out_T_9; // @[VAluInt.scala 587:48]
- wire [63:0] slidepb0_out_hi_lo_3 = {slidepb0_in_51,slidepb0_in_50,slidepb0_in_49,slidepb0_in_48,slidepb0_in_47,
- slidepb0_in_46,slidepb0_in_45,slidepb0_in_44}; // @[VAluInt.scala 589:40]
- wire [7:0] slidepb0_in_28 = _slidepb0_T_3[231:224]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb0_out_lo_lo_3 = {slidepb0_in_35,slidepb0_in_34,slidepb0_in_33,slidepb0_in_32,slidepb0_in_31,
- slidepb0_in_30,slidepb0_in_29,slidepb0_in_28}; // @[VAluInt.scala 589:40]
- wire [127:0] slidepb0_out_lo_3 = {slidepb0_in_43,slidepb0_in_42,slidepb0_in_41,slidepb0_in_40,slidepb0_in_39,
- slidepb0_in_38,slidepb0_in_37,slidepb0_in_36,slidepb0_out_lo_lo_3}; // @[VAluInt.scala 589:40]
- wire [255:0] _slidepb0_out_T_12 = {slidepb0_in_59,slidepb0_in_58,slidepb0_in_57,slidepb0_in_56,slidepb0_in_55,
- slidepb0_in_54,slidepb0_in_53,slidepb0_in_52,slidepb0_out_hi_lo_3,slidepb0_out_lo_3}; // @[VAluInt.scala 589:40]
- wire [255:0] _slidepb0_out_T_13 = _slidenb0_out_T_11 ? _slidepb0_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidepb0 = _slidepb0_out_T_10 | _slidepb0_out_T_13; // @[VAluInt.scala 588:48]
- wire [255:0] _slide0_T_2 = _slide0_T_1 | slidepb0; // @[VAluInt.scala 611:47]
- wire _slideph0_T_5 = slidevp & sz[1]; // @[VAluInt.scala 604:94]
- wire [255:0] _slideph0_T_6 = _slideph0_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slideph0_in_30 = _slideph0_T_6[239:224]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_29 = _slideph0_T_6[223:208]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_28 = _slideph0_T_6[207:192]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_27 = _slideph0_T_6[191:176]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_26 = _slideph0_T_6[175:160]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_25 = _slideph0_T_6[159:144]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_24 = _slideph0_T_6[143:128]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_23 = _slideph0_T_6[127:112]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_22 = _slideph0_T_6[111:96]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_21 = _slideph0_T_6[95:80]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_20 = _slideph0_T_6[79:64]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_19 = _slideph0_T_6[63:48]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_18 = _slideph0_T_6[47:32]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_17 = _slideph0_T_6[31:16]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph0_in_16 = _slideph0_T_6[15:0]; // @[VAluInt.scala 576:23]
- wire [255:0] _slideph0_T_3 = _slideph0_T_5 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slideph0_in_15 = _slideph0_T_3[255:240]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph0_out_lo = {slideph0_in_22,slideph0_in_21,slideph0_in_20,slideph0_in_19,slideph0_in_18,
- slideph0_in_17,slideph0_in_16,slideph0_in_15}; // @[VAluInt.scala 586:40]
- wire [255:0] _slideph0_out_T_1 = {slideph0_in_30,slideph0_in_29,slideph0_in_28,slideph0_in_27,slideph0_in_26,
- slideph0_in_25,slideph0_in_24,slideph0_in_23,slideph0_out_lo}; // @[VAluInt.scala 586:40]
- wire [255:0] _slideph0_out_T_2 = _slidenb0_out_T ? _slideph0_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slideph0_in_14 = _slideph0_T_3[239:224]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph0_out_lo_1 = {slideph0_in_21,slideph0_in_20,slideph0_in_19,slideph0_in_18,slideph0_in_17,
- slideph0_in_16,slideph0_in_15,slideph0_in_14}; // @[VAluInt.scala 587:40]
- wire [255:0] _slideph0_out_T_4 = {slideph0_in_29,slideph0_in_28,slideph0_in_27,slideph0_in_26,slideph0_in_25,
- slideph0_in_24,slideph0_in_23,slideph0_in_22,slideph0_out_lo_1}; // @[VAluInt.scala 587:40]
- wire [255:0] _slideph0_out_T_5 = _slidenb0_out_T_3 ? _slideph0_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slideph0_out_T_6 = _slideph0_out_T_2 | _slideph0_out_T_5; // @[VAluInt.scala 586:48]
- wire [15:0] slideph0_in_13 = _slideph0_T_3[223:208]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph0_out_lo_2 = {slideph0_in_20,slideph0_in_19,slideph0_in_18,slideph0_in_17,slideph0_in_16,
- slideph0_in_15,slideph0_in_14,slideph0_in_13}; // @[VAluInt.scala 588:40]
- wire [255:0] _slideph0_out_T_8 = {slideph0_in_28,slideph0_in_27,slideph0_in_26,slideph0_in_25,slideph0_in_24,
- slideph0_in_23,slideph0_in_22,slideph0_in_21,slideph0_out_lo_2}; // @[VAluInt.scala 588:40]
- wire [255:0] _slideph0_out_T_9 = _slidenb0_out_T_7 ? _slideph0_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slideph0_out_T_10 = _slideph0_out_T_6 | _slideph0_out_T_9; // @[VAluInt.scala 587:48]
- wire [15:0] slideph0_in_12 = _slideph0_T_3[207:192]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph0_out_lo_3 = {slideph0_in_19,slideph0_in_18,slideph0_in_17,slideph0_in_16,slideph0_in_15,
- slideph0_in_14,slideph0_in_13,slideph0_in_12}; // @[VAluInt.scala 589:40]
- wire [255:0] _slideph0_out_T_12 = {slideph0_in_27,slideph0_in_26,slideph0_in_25,slideph0_in_24,slideph0_in_23,
- slideph0_in_22,slideph0_in_21,slideph0_in_20,slideph0_out_lo_3}; // @[VAluInt.scala 589:40]
- wire [255:0] _slideph0_out_T_13 = _slidenb0_out_T_11 ? _slideph0_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slideph0 = _slideph0_out_T_10 | _slideph0_out_T_13; // @[VAluInt.scala 588:48]
- wire [255:0] _slide0_T_3 = _slide0_T_2 | slideph0; // @[VAluInt.scala 612:25]
- wire _slidepw0_T_5 = slidevp & sz[2]; // @[VAluInt.scala 605:94]
- wire [255:0] _slidepw0_T_6 = _slidepw0_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidepw0_in_14 = _slidepw0_T_6[223:192]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw0_in_13 = _slidepw0_T_6[191:160]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw0_in_12 = _slidepw0_T_6[159:128]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw0_in_11 = _slidepw0_T_6[127:96]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw0_in_10 = _slidepw0_T_6[95:64]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw0_in_9 = _slidepw0_T_6[63:32]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw0_in_8 = _slidepw0_T_6[31:0]; // @[VAluInt.scala 576:23]
- wire [255:0] _slidepw0_T_3 = _slidepw0_T_5 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidepw0_in_7 = _slidepw0_T_3[255:224]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw0_out_T_1 = {slidepw0_in_14,slidepw0_in_13,slidepw0_in_12,slidepw0_in_11,slidepw0_in_10,
- slidepw0_in_9,slidepw0_in_8,slidepw0_in_7}; // @[VAluInt.scala 586:40]
- wire [255:0] _slidepw0_out_T_2 = _slidenb0_out_T ? _slidepw0_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidepw0_in_6 = _slidepw0_T_3[223:192]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw0_out_T_4 = {slidepw0_in_13,slidepw0_in_12,slidepw0_in_11,slidepw0_in_10,slidepw0_in_9,
- slidepw0_in_8,slidepw0_in_7,slidepw0_in_6}; // @[VAluInt.scala 587:40]
- wire [255:0] _slidepw0_out_T_5 = _slidenb0_out_T_3 ? _slidepw0_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepw0_out_T_6 = _slidepw0_out_T_2 | _slidepw0_out_T_5; // @[VAluInt.scala 586:48]
- wire [31:0] slidepw0_in_5 = _slidepw0_T_3[191:160]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw0_out_T_8 = {slidepw0_in_12,slidepw0_in_11,slidepw0_in_10,slidepw0_in_9,slidepw0_in_8,
- slidepw0_in_7,slidepw0_in_6,slidepw0_in_5}; // @[VAluInt.scala 588:40]
- wire [255:0] _slidepw0_out_T_9 = _slidenb0_out_T_7 ? _slidepw0_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepw0_out_T_10 = _slidepw0_out_T_6 | _slidepw0_out_T_9; // @[VAluInt.scala 587:48]
- wire [31:0] slidepw0_in_4 = _slidepw0_T_3[159:128]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw0_out_T_12 = {slidepw0_in_11,slidepw0_in_10,slidepw0_in_9,slidepw0_in_8,slidepw0_in_7,
- slidepw0_in_6,slidepw0_in_5,slidepw0_in_4}; // @[VAluInt.scala 589:40]
- wire [255:0] _slidepw0_out_T_13 = _slidenb0_out_T_11 ? _slidepw0_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidepw0 = _slidepw0_out_T_10 | _slidepw0_out_T_13; // @[VAluInt.scala 588:48]
- wire [255:0] slide0 = _slide0_T_3 | slidepw0; // @[VAluInt.scala 612:36]
- wire [255:0] _load_0_T_1 = _load_0_T | slide0; // @[VAluInt.scala 742:26]
- wire [1:0] sparse = sv[3:2]; // @[VDot.scala 67:24]
- wire sparse0 = sparse == 2'h0; // @[VDot.scala 73:26]
- wire _adata0_T_14 = dwconv & sparse0; // @[VDot.scala 127:31]
- wire [31:0] adata0_7 = _adata0_T_14 ? io_read_3_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire sparse1 = sparse == 2'h1; // @[VDot.scala 74:26]
- wire _adata1_7_T = dwconv & sparse1; // @[VDot.scala 99:33]
- wire [31:0] adata1_7 = _adata1_7_T ? io_read_4_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_7_T = adata0_7 | adata1_7; // @[VDot.scala 129:32]
- wire sparse2 = sparse == 2'h2; // @[VDot.scala 75:26]
- wire _adata2_7_T = dwconv & sparse2; // @[VDot.scala 112:29]
- wire [31:0] adata2_7 = _adata2_7_T ? io_read_3_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_7 = _adatac_0_7_T | adata2_7; // @[VDot.scala 129:44]
- wire asign = sv[21]; // @[VDot.scala 69:23]
- wire as_42 = adatac_0_7[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_170 = {as_42,adatac_0_7[15:8]}; // @[VDot.scala 170:56]
- wire [8:0] abias = sv[20:12]; // @[VDot.scala 68:23]
- wire [8:0] _aval_T_171 = dwconv ? abias : 9'h0; // @[VDot.scala 170:72]
- wire [9:0] aval_42 = $signed(_aval_T_170) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_7 = dwconv ? io_read_0_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire bsign = sv[31]; // @[VDot.scala 71:23]
- wire bs_42 = bdatac_0_7[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_170 = {bs_42,bdatac_0_7[15:8]}; // @[VDot.scala 171:56]
- wire [8:0] bbias = sv[30:22]; // @[VDot.scala 70:23]
- wire [8:0] _bval_T_171 = dwconv ? bbias : 9'h0; // @[VDot.scala 171:72]
- wire [9:0] bval_42 = $signed(_bval_T_170) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_42 = $signed(aval_42) * $signed(bval_42); // @[VDot.scala 172:25]
- wire [31:0] adata0_15 = _adata0_T_14 ? io_read_4_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_8 = _adata1_7_T ? io_read_4_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_7_T = adata0_15 | adata1_8; // @[VDot.scala 129:32]
- wire [31:0] adata2_8 = _adata2_7_T ? io_read_4_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_1_7 = _adatac_1_7_T | adata2_8; // @[VDot.scala 129:44]
- wire as_43 = adatac_1_7[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_174 = {as_43,adatac_1_7[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_43 = $signed(_aval_T_174) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_7 = dwconv ? io_read_1_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire bs_43 = bdatac_1_7[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_174 = {bs_43,bdatac_1_7[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_43 = $signed(_bval_T_174) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_43 = $signed(aval_43) * $signed(bval_43); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_14 = $signed(mval_42) + $signed(mval_43); // @[VDot.scala 180:26]
- wire [31:0] adata0_23 = _adata0_T_14 ? io_read_5_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_9 = _adata1_7_T ? io_read_5_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_7_T = adata0_23 | adata1_9; // @[VDot.scala 129:32]
- wire [31:0] adata2_9 = _adata2_7_T ? io_read_4_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_2_7 = _adatac_2_7_T | adata2_9; // @[VDot.scala 129:44]
- wire as_44 = adatac_2_7[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_178 = {as_44,adatac_2_7[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_44 = $signed(_aval_T_178) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_7 = dwconv ? io_read_2_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire bs_44 = bdatac_2_7[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_178 = {bs_44,bdatac_2_7[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_44 = $signed(_bval_T_178) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_44 = $signed(aval_44) * $signed(bval_44); // @[VDot.scala 172:25]
- wire [20:0] _GEN_94 = {{1{mval_44[19]}},mval_44}; // @[VDot.scala 180:37]
- wire [21:0] dotp_14 = $signed(_dotp_T_14) + $signed(_GEN_94); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_44 = dotp_14[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_14 = $signed(_dotp_T_14) + $signed(_GEN_94); // @[Cat.scala 31:58]
- wire [31:0] adata0_6 = _adata0_T_14 ? io_read_3_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_6 = _adata1_7_T ? io_read_4_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_6_T = adata0_6 | adata1_6; // @[VDot.scala 129:32]
- wire [31:0] adata2_6 = _adata2_7_T ? io_read_3_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_6 = _adatac_0_6_T | adata2_6; // @[VDot.scala 129:44]
- wire as_36 = adatac_0_6[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_146 = {as_36,adatac_0_6[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_36 = $signed(_aval_T_146) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_6 = dwconv ? io_read_0_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire bs_36 = bdatac_0_6[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_146 = {bs_36,bdatac_0_6[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_36 = $signed(_bval_T_146) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_36 = $signed(aval_36) * $signed(bval_36); // @[VDot.scala 172:25]
- wire [31:0] adata0_14 = _adata0_T_14 ? io_read_4_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_6_T = adata0_14 | adata1_7; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_6 = _adatac_1_6_T | adata2_7; // @[VDot.scala 129:44]
- wire as_37 = adatac_1_6[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_150 = {as_37,adatac_1_6[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_37 = $signed(_aval_T_150) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_6 = dwconv ? io_read_1_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire bs_37 = bdatac_1_6[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_150 = {bs_37,bdatac_1_6[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_37 = $signed(_bval_T_150) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_37 = $signed(aval_37) * $signed(bval_37); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_12 = $signed(mval_36) + $signed(mval_37); // @[VDot.scala 180:26]
- wire [31:0] adata0_22 = _adata0_T_14 ? io_read_5_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_6_T = adata0_22 | adata1_8; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_6 = _adatac_2_6_T | adata2_8; // @[VDot.scala 129:44]
- wire as_38 = adatac_2_6[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_154 = {as_38,adatac_2_6[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_38 = $signed(_aval_T_154) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_6 = dwconv ? io_read_2_data[223:192] : 32'h0; // @[Library.scala 32:8]
- wire bs_38 = bdatac_2_6[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_154 = {bs_38,bdatac_2_6[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_38 = $signed(_bval_T_154) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_38 = $signed(aval_38) * $signed(bval_38); // @[VDot.scala 172:25]
- wire [20:0] _GEN_95 = {{1{mval_38[19]}},mval_38}; // @[VDot.scala 180:37]
- wire [21:0] dotp_12 = $signed(_dotp_T_12) + $signed(_GEN_95); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_38 = dotp_12[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_12 = $signed(_dotp_T_12) + $signed(_GEN_95); // @[Cat.scala 31:58]
- wire [31:0] adata0_5 = _adata0_T_14 ? io_read_3_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_5 = _adata1_7_T ? io_read_4_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_5_T = adata0_5 | adata1_5; // @[VDot.scala 129:32]
- wire [31:0] adata2_5 = _adata2_7_T ? io_read_3_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_5 = _adatac_0_5_T | adata2_5; // @[VDot.scala 129:44]
- wire as_30 = adatac_0_5[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_122 = {as_30,adatac_0_5[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_30 = $signed(_aval_T_122) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_5 = dwconv ? io_read_0_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire bs_30 = bdatac_0_5[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_122 = {bs_30,bdatac_0_5[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_30 = $signed(_bval_T_122) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_30 = $signed(aval_30) * $signed(bval_30); // @[VDot.scala 172:25]
- wire [31:0] adata0_13 = _adata0_T_14 ? io_read_4_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_5_T = adata0_13 | adata1_6; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_5 = _adatac_1_5_T | adata2_6; // @[VDot.scala 129:44]
- wire as_31 = adatac_1_5[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_126 = {as_31,adatac_1_5[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_31 = $signed(_aval_T_126) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_5 = dwconv ? io_read_1_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire bs_31 = bdatac_1_5[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_126 = {bs_31,bdatac_1_5[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_31 = $signed(_bval_T_126) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_31 = $signed(aval_31) * $signed(bval_31); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_10 = $signed(mval_30) + $signed(mval_31); // @[VDot.scala 180:26]
- wire [31:0] adata0_21 = _adata0_T_14 ? io_read_5_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_5_T = adata0_21 | adata1_7; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_5 = _adatac_2_5_T | adata2_7; // @[VDot.scala 129:44]
- wire as_32 = adatac_2_5[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_130 = {as_32,adatac_2_5[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_32 = $signed(_aval_T_130) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_5 = dwconv ? io_read_2_data[191:160] : 32'h0; // @[Library.scala 32:8]
- wire bs_32 = bdatac_2_5[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_130 = {bs_32,bdatac_2_5[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_32 = $signed(_bval_T_130) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_32 = $signed(aval_32) * $signed(bval_32); // @[VDot.scala 172:25]
- wire [20:0] _GEN_96 = {{1{mval_32[19]}},mval_32}; // @[VDot.scala 180:37]
- wire [21:0] dotp_10 = $signed(_dotp_T_10) + $signed(_GEN_96); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_32 = dotp_10[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_10 = $signed(_dotp_T_10) + $signed(_GEN_96); // @[Cat.scala 31:58]
- wire [31:0] adata0_4 = _adata0_T_14 ? io_read_3_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_4 = _adata1_7_T ? io_read_4_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_4_T = adata0_4 | adata1_4; // @[VDot.scala 129:32]
- wire [31:0] adata2_4 = _adata2_7_T ? io_read_3_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_4 = _adatac_0_4_T | adata2_4; // @[VDot.scala 129:44]
- wire as_24 = adatac_0_4[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_98 = {as_24,adatac_0_4[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_24 = $signed(_aval_T_98) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_4 = dwconv ? io_read_0_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire bs_24 = bdatac_0_4[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_98 = {bs_24,bdatac_0_4[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_24 = $signed(_bval_T_98) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_24 = $signed(aval_24) * $signed(bval_24); // @[VDot.scala 172:25]
- wire [31:0] adata0_12 = _adata0_T_14 ? io_read_4_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_4_T = adata0_12 | adata1_5; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_4 = _adatac_1_4_T | adata2_5; // @[VDot.scala 129:44]
- wire as_25 = adatac_1_4[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_102 = {as_25,adatac_1_4[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_25 = $signed(_aval_T_102) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_4 = dwconv ? io_read_1_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire bs_25 = bdatac_1_4[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_102 = {bs_25,bdatac_1_4[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_25 = $signed(_bval_T_102) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_25 = $signed(aval_25) * $signed(bval_25); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_8 = $signed(mval_24) + $signed(mval_25); // @[VDot.scala 180:26]
- wire [31:0] adata0_20 = _adata0_T_14 ? io_read_5_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_4_T = adata0_20 | adata1_6; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_4 = _adatac_2_4_T | adata2_6; // @[VDot.scala 129:44]
- wire as_26 = adatac_2_4[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_106 = {as_26,adatac_2_4[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_26 = $signed(_aval_T_106) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_4 = dwconv ? io_read_2_data[159:128] : 32'h0; // @[Library.scala 32:8]
- wire bs_26 = bdatac_2_4[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_106 = {bs_26,bdatac_2_4[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_26 = $signed(_bval_T_106) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_26 = $signed(aval_26) * $signed(bval_26); // @[VDot.scala 172:25]
- wire [20:0] _GEN_97 = {{1{mval_26[19]}},mval_26}; // @[VDot.scala 180:37]
- wire [21:0] dotp_8 = $signed(_dotp_T_8) + $signed(_GEN_97); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_26 = dotp_8[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_8 = $signed(_dotp_T_8) + $signed(_GEN_97); // @[Cat.scala 31:58]
- wire [31:0] adata0_3 = _adata0_T_14 ? io_read_3_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_3 = _adata1_7_T ? io_read_4_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_3_T = adata0_3 | adata1_3; // @[VDot.scala 129:32]
- wire [31:0] adata2_3 = _adata2_7_T ? io_read_3_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_3 = _adatac_0_3_T | adata2_3; // @[VDot.scala 129:44]
- wire as_18 = adatac_0_3[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_74 = {as_18,adatac_0_3[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_18 = $signed(_aval_T_74) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_3 = dwconv ? io_read_0_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire bs_18 = bdatac_0_3[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_74 = {bs_18,bdatac_0_3[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_18 = $signed(_bval_T_74) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_18 = $signed(aval_18) * $signed(bval_18); // @[VDot.scala 172:25]
- wire [31:0] adata0_11 = _adata0_T_14 ? io_read_4_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_3_T = adata0_11 | adata1_4; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_3 = _adatac_1_3_T | adata2_4; // @[VDot.scala 129:44]
- wire as_19 = adatac_1_3[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_78 = {as_19,adatac_1_3[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_19 = $signed(_aval_T_78) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_3 = dwconv ? io_read_1_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire bs_19 = bdatac_1_3[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_78 = {bs_19,bdatac_1_3[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_19 = $signed(_bval_T_78) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_19 = $signed(aval_19) * $signed(bval_19); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_6 = $signed(mval_18) + $signed(mval_19); // @[VDot.scala 180:26]
- wire [31:0] adata0_19 = _adata0_T_14 ? io_read_5_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_3_T = adata0_19 | adata1_5; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_3 = _adatac_2_3_T | adata2_5; // @[VDot.scala 129:44]
- wire as_20 = adatac_2_3[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_82 = {as_20,adatac_2_3[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_20 = $signed(_aval_T_82) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_3 = dwconv ? io_read_2_data[127:96] : 32'h0; // @[Library.scala 32:8]
- wire bs_20 = bdatac_2_3[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_82 = {bs_20,bdatac_2_3[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_20 = $signed(_bval_T_82) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_20 = $signed(aval_20) * $signed(bval_20); // @[VDot.scala 172:25]
- wire [20:0] _GEN_98 = {{1{mval_20[19]}},mval_20}; // @[VDot.scala 180:37]
- wire [21:0] dotp_6 = $signed(_dotp_T_6) + $signed(_GEN_98); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_20 = dotp_6[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_6 = $signed(_dotp_T_6) + $signed(_GEN_98); // @[Cat.scala 31:58]
- wire [31:0] adata0_2 = _adata0_T_14 ? io_read_3_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_2 = _adata1_7_T ? io_read_4_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_2_T = adata0_2 | adata1_2; // @[VDot.scala 129:32]
- wire [31:0] adata2_2 = _adata2_7_T ? io_read_3_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_2 = _adatac_0_2_T | adata2_2; // @[VDot.scala 129:44]
- wire as_12 = adatac_0_2[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_50 = {as_12,adatac_0_2[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_12 = $signed(_aval_T_50) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_2 = dwconv ? io_read_0_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire bs_12 = bdatac_0_2[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_50 = {bs_12,bdatac_0_2[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_12 = $signed(_bval_T_50) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_12 = $signed(aval_12) * $signed(bval_12); // @[VDot.scala 172:25]
- wire [31:0] adata0_10 = _adata0_T_14 ? io_read_4_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_2_T = adata0_10 | adata1_3; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_2 = _adatac_1_2_T | adata2_3; // @[VDot.scala 129:44]
- wire as_13 = adatac_1_2[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_54 = {as_13,adatac_1_2[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_13 = $signed(_aval_T_54) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_2 = dwconv ? io_read_1_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire bs_13 = bdatac_1_2[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_54 = {bs_13,bdatac_1_2[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_13 = $signed(_bval_T_54) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_13 = $signed(aval_13) * $signed(bval_13); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_4 = $signed(mval_12) + $signed(mval_13); // @[VDot.scala 180:26]
- wire [31:0] adata0_18 = _adata0_T_14 ? io_read_5_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_2_T = adata0_18 | adata1_4; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_2 = _adatac_2_2_T | adata2_4; // @[VDot.scala 129:44]
- wire as_14 = adatac_2_2[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_58 = {as_14,adatac_2_2[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_14 = $signed(_aval_T_58) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_2 = dwconv ? io_read_2_data[95:64] : 32'h0; // @[Library.scala 32:8]
- wire bs_14 = bdatac_2_2[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_58 = {bs_14,bdatac_2_2[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_14 = $signed(_bval_T_58) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_14 = $signed(aval_14) * $signed(bval_14); // @[VDot.scala 172:25]
- wire [20:0] _GEN_99 = {{1{mval_14[19]}},mval_14}; // @[VDot.scala 180:37]
- wire [21:0] dotp_4 = $signed(_dotp_T_4) + $signed(_GEN_99); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_14 = dotp_4[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_4 = $signed(_dotp_T_4) + $signed(_GEN_99); // @[Cat.scala 31:58]
- wire [31:0] adata0_1 = _adata0_T_14 ? io_read_3_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_1 = _adata1_7_T ? io_read_4_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_1_T = adata0_1 | adata1_1; // @[VDot.scala 129:32]
- wire [31:0] adata2_1 = _adata2_7_T ? io_read_3_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_1 = _adatac_0_1_T | adata2_1; // @[VDot.scala 129:44]
- wire as_6 = adatac_0_1[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_26 = {as_6,adatac_0_1[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_6 = $signed(_aval_T_26) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_1 = dwconv ? io_read_0_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire bs_6 = bdatac_0_1[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_26 = {bs_6,bdatac_0_1[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_6 = $signed(_bval_T_26) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_6 = $signed(aval_6) * $signed(bval_6); // @[VDot.scala 172:25]
- wire [31:0] adata0_9 = _adata0_T_14 ? io_read_4_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_1_T = adata0_9 | adata1_2; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_1 = _adatac_1_1_T | adata2_2; // @[VDot.scala 129:44]
- wire as_7 = adatac_1_1[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_30 = {as_7,adatac_1_1[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_7 = $signed(_aval_T_30) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_1 = dwconv ? io_read_1_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire bs_7 = bdatac_1_1[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_30 = {bs_7,bdatac_1_1[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_7 = $signed(_bval_T_30) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_7 = $signed(aval_7) * $signed(bval_7); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_2 = $signed(mval_6) + $signed(mval_7); // @[VDot.scala 180:26]
- wire [31:0] adata0_17 = _adata0_T_14 ? io_read_5_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_1_T = adata0_17 | adata1_3; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_1 = _adatac_2_1_T | adata2_3; // @[VDot.scala 129:44]
- wire as_8 = adatac_2_1[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_34 = {as_8,adatac_2_1[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_8 = $signed(_aval_T_34) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_1 = dwconv ? io_read_2_data[63:32] : 32'h0; // @[Library.scala 32:8]
- wire bs_8 = bdatac_2_1[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_34 = {bs_8,bdatac_2_1[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_8 = $signed(_bval_T_34) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_8 = $signed(aval_8) * $signed(bval_8); // @[VDot.scala 172:25]
- wire [20:0] _GEN_100 = {{1{mval_8[19]}},mval_8}; // @[VDot.scala 180:37]
- wire [21:0] dotp_2 = $signed(_dotp_T_2) + $signed(_GEN_100); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_8 = dotp_2[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_2 = $signed(_dotp_T_2) + $signed(_GEN_100); // @[Cat.scala 31:58]
- wire [31:0] adata0 = _adata0_T_14 ? io_read_3_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adata1_0 = _adata1_7_T ? io_read_3_data[255:224] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_0_0_T = adata0 | adata1_0; // @[VDot.scala 129:32]
- wire [31:0] adata2_0 = _adata2_7_T ? io_read_3_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] adatac_0_0 = _adatac_0_0_T | adata2_0; // @[VDot.scala 129:44]
- wire as = adatac_0_0[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_2 = {as,adatac_0_0[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval = $signed(_aval_T_2) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_0_0 = dwconv ? io_read_0_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire bs = bdatac_0_0[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_2 = {bs,bdatac_0_0[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval = $signed(_bval_T_2) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval = $signed(aval) * $signed(bval); // @[VDot.scala 172:25]
- wire [31:0] adata0_8 = _adata0_T_14 ? io_read_4_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_1_0_T = adata0_8 | adata1_1; // @[VDot.scala 129:32]
- wire [31:0] adatac_1_0 = _adatac_1_0_T | adata2_1; // @[VDot.scala 129:44]
- wire as_1 = adatac_1_0[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_6 = {as_1,adatac_1_0[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_1 = $signed(_aval_T_6) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_1_0 = dwconv ? io_read_1_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire bs_1 = bdatac_1_0[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_6 = {bs_1,bdatac_1_0[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_1 = $signed(_bval_T_6) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_1 = $signed(aval_1) * $signed(bval_1); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T = $signed(mval) + $signed(mval_1); // @[VDot.scala 180:26]
- wire [31:0] adata0_16 = _adata0_T_14 ? io_read_5_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] _adatac_2_0_T = adata0_16 | adata1_2; // @[VDot.scala 129:32]
- wire [31:0] adatac_2_0 = _adatac_2_0_T | adata2_2; // @[VDot.scala 129:44]
- wire as_2 = adatac_2_0[15] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_10 = {as_2,adatac_2_0[15:8]}; // @[VDot.scala 170:56]
- wire [9:0] aval_2 = $signed(_aval_T_10) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire [31:0] bdatac_2_0 = dwconv ? io_read_2_data[31:0] : 32'h0; // @[Library.scala 32:8]
- wire bs_2 = bdatac_2_0[15] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_10 = {bs_2,bdatac_2_0[15:8]}; // @[VDot.scala 171:56]
- wire [9:0] bval_2 = $signed(_bval_T_10) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_2 = $signed(aval_2) * $signed(bval_2); // @[VDot.scala 172:25]
- wire [20:0] _GEN_101 = {{1{mval_2[19]}},mval_2}; // @[VDot.scala 180:37]
- wire [21:0] dotp = $signed(_dotp_T) + $signed(_GEN_101); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_2 = dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo = $signed(_dotp_T) + $signed(_GEN_101); // @[Cat.scala 31:58]
- wire [127:0] out0_lo_3 = {_sdotp_T_20,sdotp_lo_6,_sdotp_T_14,sdotp_lo_4,_sdotp_T_8,sdotp_lo_2,_sdotp_T_2,sdotp_lo}; // @[VDot.scala 142:22]
- wire [255:0] dwconv0 = {_sdotp_T_44,sdotp_lo_14,_sdotp_T_38,sdotp_lo_12,_sdotp_T_32,sdotp_lo_10,_sdotp_T_26,sdotp_lo_8
- ,out0_lo_3}; // @[VDot.scala 142:22]
- wire [255:0] _load_0_T_2 = _load_0_T_1 | dwconv0; // @[VAluInt.scala 742:35]
- wire _selb0_T_1 = sel & sz[0]; // @[VAluInt.scala 639:33]
- wire [255:0] _selb0_T_2 = _selb0_T_1 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _selb0_T_8 = _selb0_T_1 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _selb0_T_5 = _selb0_T_1 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] selb0_sout_31 = _selb0_T_2[248] ? _selb0_T_8[255:248] : _selb0_T_5[255:248]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_30 = _selb0_T_2[240] ? _selb0_T_8[247:240] : _selb0_T_5[247:240]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_29 = _selb0_T_2[232] ? _selb0_T_8[239:232] : _selb0_T_5[239:232]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_28 = _selb0_T_2[224] ? _selb0_T_8[231:224] : _selb0_T_5[231:224]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_27 = _selb0_T_2[216] ? _selb0_T_8[223:216] : _selb0_T_5[223:216]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_26 = _selb0_T_2[208] ? _selb0_T_8[215:208] : _selb0_T_5[215:208]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_25 = _selb0_T_2[200] ? _selb0_T_8[207:200] : _selb0_T_5[207:200]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_24 = _selb0_T_2[192] ? _selb0_T_8[199:192] : _selb0_T_5[199:192]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_23 = _selb0_T_2[184] ? _selb0_T_8[191:184] : _selb0_T_5[191:184]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_22 = _selb0_T_2[176] ? _selb0_T_8[183:176] : _selb0_T_5[183:176]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_21 = _selb0_T_2[168] ? _selb0_T_8[175:168] : _selb0_T_5[175:168]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_20 = _selb0_T_2[160] ? _selb0_T_8[167:160] : _selb0_T_5[167:160]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_19 = _selb0_T_2[152] ? _selb0_T_8[159:152] : _selb0_T_5[159:152]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_18 = _selb0_T_2[144] ? _selb0_T_8[151:144] : _selb0_T_5[151:144]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_17 = _selb0_T_2[136] ? _selb0_T_8[143:136] : _selb0_T_5[143:136]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_16 = _selb0_T_2[128] ? _selb0_T_8[135:128] : _selb0_T_5[135:128]; // @[VAluInt.scala 630:21]
- wire [63:0] selb0_out_hi_lo = {selb0_sout_23,selb0_sout_22,selb0_sout_21,selb0_sout_20,selb0_sout_19,selb0_sout_18,
- selb0_sout_17,selb0_sout_16}; // @[VAluInt.scala 633:20]
- wire [7:0] selb0_sout_15 = _selb0_T_2[120] ? _selb0_T_8[127:120] : _selb0_T_5[127:120]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_14 = _selb0_T_2[112] ? _selb0_T_8[119:112] : _selb0_T_5[119:112]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_13 = _selb0_T_2[104] ? _selb0_T_8[111:104] : _selb0_T_5[111:104]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_12 = _selb0_T_2[96] ? _selb0_T_8[103:96] : _selb0_T_5[103:96]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_11 = _selb0_T_2[88] ? _selb0_T_8[95:88] : _selb0_T_5[95:88]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_10 = _selb0_T_2[80] ? _selb0_T_8[87:80] : _selb0_T_5[87:80]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_9 = _selb0_T_2[72] ? _selb0_T_8[79:72] : _selb0_T_5[79:72]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_8 = _selb0_T_2[64] ? _selb0_T_8[71:64] : _selb0_T_5[71:64]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_7 = _selb0_T_2[56] ? _selb0_T_8[63:56] : _selb0_T_5[63:56]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_6 = _selb0_T_2[48] ? _selb0_T_8[55:48] : _selb0_T_5[55:48]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_5 = _selb0_T_2[40] ? _selb0_T_8[47:40] : _selb0_T_5[47:40]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_4 = _selb0_T_2[32] ? _selb0_T_8[39:32] : _selb0_T_5[39:32]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_3 = _selb0_T_2[24] ? _selb0_T_8[31:24] : _selb0_T_5[31:24]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_2 = _selb0_T_2[16] ? _selb0_T_8[23:16] : _selb0_T_5[23:16]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_1 = _selb0_T_2[8] ? _selb0_T_8[15:8] : _selb0_T_5[15:8]; // @[VAluInt.scala 630:21]
- wire [7:0] selb0_sout_0 = _selb0_T_2[0] ? _selb0_T_8[7:0] : _selb0_T_5[7:0]; // @[VAluInt.scala 630:21]
- wire [63:0] selb0_out_lo_lo = {selb0_sout_7,selb0_sout_6,selb0_sout_5,selb0_sout_4,selb0_sout_3,selb0_sout_2,
- selb0_sout_1,selb0_sout_0}; // @[VAluInt.scala 633:20]
- wire [127:0] selb0_out_lo = {selb0_sout_15,selb0_sout_14,selb0_sout_13,selb0_sout_12,selb0_sout_11,selb0_sout_10,
- selb0_sout_9,selb0_sout_8,selb0_out_lo_lo}; // @[VAluInt.scala 633:20]
- wire [255:0] selb0 = {selb0_sout_31,selb0_sout_30,selb0_sout_29,selb0_sout_28,selb0_sout_27,selb0_sout_26,
- selb0_sout_25,selb0_sout_24,selb0_out_hi_lo,selb0_out_lo}; // @[VAluInt.scala 633:20]
- wire _selh0_T_1 = sel & sz[1]; // @[VAluInt.scala 640:33]
- wire [255:0] _selh0_T_2 = _selh0_T_1 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _selh0_T_8 = _selh0_T_1 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _selh0_T_5 = _selh0_T_1 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] selh0_sout_15 = _selh0_T_2[240] ? _selh0_T_8[255:240] : _selh0_T_5[255:240]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_14 = _selh0_T_2[224] ? _selh0_T_8[239:224] : _selh0_T_5[239:224]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_13 = _selh0_T_2[208] ? _selh0_T_8[223:208] : _selh0_T_5[223:208]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_12 = _selh0_T_2[192] ? _selh0_T_8[207:192] : _selh0_T_5[207:192]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_11 = _selh0_T_2[176] ? _selh0_T_8[191:176] : _selh0_T_5[191:176]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_10 = _selh0_T_2[160] ? _selh0_T_8[175:160] : _selh0_T_5[175:160]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_9 = _selh0_T_2[144] ? _selh0_T_8[159:144] : _selh0_T_5[159:144]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_8 = _selh0_T_2[128] ? _selh0_T_8[143:128] : _selh0_T_5[143:128]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_7 = _selh0_T_2[112] ? _selh0_T_8[127:112] : _selh0_T_5[127:112]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_6 = _selh0_T_2[96] ? _selh0_T_8[111:96] : _selh0_T_5[111:96]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_5 = _selh0_T_2[80] ? _selh0_T_8[95:80] : _selh0_T_5[95:80]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_4 = _selh0_T_2[64] ? _selh0_T_8[79:64] : _selh0_T_5[79:64]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_3 = _selh0_T_2[48] ? _selh0_T_8[63:48] : _selh0_T_5[63:48]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_2 = _selh0_T_2[32] ? _selh0_T_8[47:32] : _selh0_T_5[47:32]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_1 = _selh0_T_2[16] ? _selh0_T_8[31:16] : _selh0_T_5[31:16]; // @[VAluInt.scala 630:21]
- wire [15:0] selh0_sout_0 = _selh0_T_2[0] ? _selh0_T_8[15:0] : _selh0_T_5[15:0]; // @[VAluInt.scala 630:21]
- wire [127:0] selh0_out_lo = {selh0_sout_7,selh0_sout_6,selh0_sout_5,selh0_sout_4,selh0_sout_3,selh0_sout_2,
- selh0_sout_1,selh0_sout_0}; // @[VAluInt.scala 633:20]
- wire [255:0] selh0 = {selh0_sout_15,selh0_sout_14,selh0_sout_13,selh0_sout_12,selh0_sout_11,selh0_sout_10,selh0_sout_9
- ,selh0_sout_8,selh0_out_lo}; // @[VAluInt.scala 633:20]
- wire [255:0] _sel0_T = selb0 | selh0; // @[VAluInt.scala 643:20]
- wire _selw0_T_1 = sel & sz[2]; // @[VAluInt.scala 641:33]
- wire [255:0] _selw0_T_2 = _selw0_T_1 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _selw0_T_8 = _selw0_T_1 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _selw0_T_5 = _selw0_T_1 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] selw0_sout_7 = _selw0_T_2[224] ? _selw0_T_8[255:224] : _selw0_T_5[255:224]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_6 = _selw0_T_2[192] ? _selw0_T_8[223:192] : _selw0_T_5[223:192]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_5 = _selw0_T_2[160] ? _selw0_T_8[191:160] : _selw0_T_5[191:160]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_4 = _selw0_T_2[128] ? _selw0_T_8[159:128] : _selw0_T_5[159:128]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_3 = _selw0_T_2[96] ? _selw0_T_8[127:96] : _selw0_T_5[127:96]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_2 = _selw0_T_2[64] ? _selw0_T_8[95:64] : _selw0_T_5[95:64]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_1 = _selw0_T_2[32] ? _selw0_T_8[63:32] : _selw0_T_5[63:32]; // @[VAluInt.scala 630:21]
- wire [31:0] selw0_sout_0 = _selw0_T_2[0] ? _selw0_T_8[31:0] : _selw0_T_5[31:0]; // @[VAluInt.scala 630:21]
- wire [255:0] selw0 = {selw0_sout_7,selw0_sout_6,selw0_sout_5,selw0_sout_4,selw0_sout_3,selw0_sout_2,selw0_sout_1,
- selw0_sout_0}; // @[VAluInt.scala 633:20]
- wire [255:0] sel0 = _sel0_T | selw0; // @[VAluInt.scala 643:28]
- wire [255:0] load_0 = _load_0_T_2 | sel0; // @[VAluInt.scala 742:45]
- wire _oddb_T_4 = odd & sz[0]; // @[VAluInt.scala 680:76]
- wire [255:0] _oddb_T_5 = _oddb_T_4 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] oddb_evnodd_31 = _oddb_T_5[255:248]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_30 = _oddb_T_5[239:232]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_29 = _oddb_T_5[223:216]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_28 = _oddb_T_5[207:200]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_27 = _oddb_T_5[191:184]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_26 = _oddb_T_5[175:168]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_25 = _oddb_T_5[159:152]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_24 = _oddb_T_5[143:136]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_23 = _oddb_T_5[127:120]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_22 = _oddb_T_5[111:104]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_21 = _oddb_T_5[95:88]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_20 = _oddb_T_5[79:72]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_19 = _oddb_T_5[63:56]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_18 = _oddb_T_5[47:40]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_17 = _oddb_T_5[31:24]; // @[VAluInt.scala 668:21]
- wire [7:0] oddb_evnodd_16 = _oddb_T_5[15:8]; // @[VAluInt.scala 668:21]
- wire [63:0] oddb_out_hi_lo = {oddb_evnodd_23,oddb_evnodd_22,oddb_evnodd_21,oddb_evnodd_20,oddb_evnodd_19,
- oddb_evnodd_18,oddb_evnodd_17,oddb_evnodd_16}; // @[VAluInt.scala 671:22]
- wire [255:0] _oddb_T_2 = _oddb_T_4 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] oddb_evnodd_15 = _oddb_T_2[255:248]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_14 = _oddb_T_2[239:232]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_13 = _oddb_T_2[223:216]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_12 = _oddb_T_2[207:200]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_11 = _oddb_T_2[191:184]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_10 = _oddb_T_2[175:168]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_9 = _oddb_T_2[159:152]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_8 = _oddb_T_2[143:136]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_7 = _oddb_T_2[127:120]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_6 = _oddb_T_2[111:104]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_5 = _oddb_T_2[95:88]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_4 = _oddb_T_2[79:72]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_3 = _oddb_T_2[63:56]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_2 = _oddb_T_2[47:40]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_1 = _oddb_T_2[31:24]; // @[VAluInt.scala 661:21]
- wire [7:0] oddb_evnodd_0 = _oddb_T_2[15:8]; // @[VAluInt.scala 661:21]
- wire [63:0] oddb_out_lo_lo = {oddb_evnodd_7,oddb_evnodd_6,oddb_evnodd_5,oddb_evnodd_4,oddb_evnodd_3,oddb_evnodd_2,
- oddb_evnodd_1,oddb_evnodd_0}; // @[VAluInt.scala 671:22]
- wire [127:0] oddb_out_lo = {oddb_evnodd_15,oddb_evnodd_14,oddb_evnodd_13,oddb_evnodd_12,oddb_evnodd_11,oddb_evnodd_10,
- oddb_evnodd_9,oddb_evnodd_8,oddb_out_lo_lo}; // @[VAluInt.scala 671:22]
- wire [255:0] oddb = {oddb_evnodd_31,oddb_evnodd_30,oddb_evnodd_29,oddb_evnodd_28,oddb_evnodd_27,oddb_evnodd_26,
- oddb_evnodd_25,oddb_evnodd_24,oddb_out_hi_lo,oddb_out_lo}; // @[VAluInt.scala 671:22]
- wire _oddh_T_4 = odd & sz[1]; // @[VAluInt.scala 681:76]
- wire [255:0] _oddh_T_5 = _oddh_T_4 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] oddh_evnodd_15 = _oddh_T_5[255:240]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_14 = _oddh_T_5[223:208]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_13 = _oddh_T_5[191:176]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_12 = _oddh_T_5[159:144]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_11 = _oddh_T_5[127:112]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_10 = _oddh_T_5[95:80]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_9 = _oddh_T_5[63:48]; // @[VAluInt.scala 668:21]
- wire [15:0] oddh_evnodd_8 = _oddh_T_5[31:16]; // @[VAluInt.scala 668:21]
- wire [255:0] _oddh_T_2 = _oddh_T_4 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] oddh_evnodd_7 = _oddh_T_2[255:240]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_6 = _oddh_T_2[223:208]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_5 = _oddh_T_2[191:176]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_4 = _oddh_T_2[159:144]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_3 = _oddh_T_2[127:112]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_2 = _oddh_T_2[95:80]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_1 = _oddh_T_2[63:48]; // @[VAluInt.scala 661:21]
- wire [15:0] oddh_evnodd_0 = _oddh_T_2[31:16]; // @[VAluInt.scala 661:21]
- wire [127:0] oddh_out_lo = {oddh_evnodd_7,oddh_evnodd_6,oddh_evnodd_5,oddh_evnodd_4,oddh_evnodd_3,oddh_evnodd_2,
- oddh_evnodd_1,oddh_evnodd_0}; // @[VAluInt.scala 671:22]
- wire [255:0] oddh = {oddh_evnodd_15,oddh_evnodd_14,oddh_evnodd_13,oddh_evnodd_12,oddh_evnodd_11,oddh_evnodd_10,
- oddh_evnodd_9,oddh_evnodd_8,oddh_out_lo}; // @[VAluInt.scala 671:22]
- wire [255:0] _odd1_T = oddb | oddh; // @[VAluInt.scala 685:19]
- wire _oddw_T_4 = odd & sz[2]; // @[VAluInt.scala 682:76]
- wire [255:0] _oddw_T_5 = _oddw_T_4 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] oddw_evnodd_7 = _oddw_T_5[255:224]; // @[VAluInt.scala 668:21]
- wire [31:0] oddw_evnodd_6 = _oddw_T_5[191:160]; // @[VAluInt.scala 668:21]
- wire [31:0] oddw_evnodd_5 = _oddw_T_5[127:96]; // @[VAluInt.scala 668:21]
- wire [31:0] oddw_evnodd_4 = _oddw_T_5[63:32]; // @[VAluInt.scala 668:21]
- wire [255:0] _oddw_T_2 = _oddw_T_4 ? io_read_0_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] oddw_evnodd_3 = _oddw_T_2[255:224]; // @[VAluInt.scala 661:21]
- wire [31:0] oddw_evnodd_2 = _oddw_T_2[191:160]; // @[VAluInt.scala 661:21]
- wire [31:0] oddw_evnodd_1 = _oddw_T_2[127:96]; // @[VAluInt.scala 661:21]
- wire [31:0] oddw_evnodd_0 = _oddw_T_2[63:32]; // @[VAluInt.scala 661:21]
- wire [255:0] oddw = {oddw_evnodd_7,oddw_evnodd_6,oddw_evnodd_5,oddw_evnodd_4,oddw_evnodd_3,oddw_evnodd_2,oddw_evnodd_1
- ,oddw_evnodd_0}; // @[VAluInt.scala 671:22]
- wire [255:0] odd1 = _odd1_T | oddw; // @[VAluInt.scala 685:26]
- wire [7:0] zip1__31 = _T_95[255:248]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__30 = _T_92[255:248]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__29 = _T_95[247:240]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__28 = _T_92[247:240]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__27 = _T_95[239:232]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__26 = _T_92[239:232]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__25 = _T_95[231:224]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__24 = _T_92[231:224]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__23 = _T_95[223:216]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__22 = _T_92[223:216]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__21 = _T_95[215:208]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__20 = _T_92[215:208]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__19 = _T_95[207:200]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__18 = _T_92[207:200]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__17 = _T_95[199:192]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__16 = _T_92[199:192]; // @[VAluInt.scala 705:21]
- wire [63:0] out1_hi_lo = {zip1__23,zip1__22,zip1__21,zip1__20,zip1__19,zip1__18,zip1__17,zip1__16}; // @[VAluInt.scala 713:21]
- wire [7:0] zip1__15 = _T_95[191:184]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__14 = _T_92[191:184]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__13 = _T_95[183:176]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__12 = _T_92[183:176]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__11 = _T_95[175:168]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__10 = _T_92[175:168]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__9 = _T_95[167:160]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__8 = _T_92[167:160]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__7 = _T_95[159:152]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__6 = _T_92[159:152]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__5 = _T_95[151:144]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__4 = _T_92[151:144]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__3 = _T_95[143:136]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__2 = _T_92[143:136]; // @[VAluInt.scala 705:21]
- wire [7:0] zip1__1 = _T_95[135:128]; // @[VAluInt.scala 708:21]
- wire [7:0] zip1__0 = _T_92[135:128]; // @[VAluInt.scala 705:21]
- wire [63:0] out1_lo_lo = {zip1__7,zip1__6,zip1__5,zip1__4,zip1__3,zip1__2,zip1__1,zip1__0}; // @[VAluInt.scala 713:21]
- wire [127:0] out1_lo = {zip1__15,zip1__14,zip1__13,zip1__12,zip1__11,zip1__10,zip1__9,zip1__8,out1_lo_lo}; // @[VAluInt.scala 713:21]
- wire [255:0] zipb1 = {zip1__31,zip1__30,zip1__29,zip1__28,zip1__27,zip1__26,zip1__25,zip1__24,out1_hi_lo,out1_lo}; // @[VAluInt.scala 713:21]
- wire [15:0] zip1_1_15 = _T_101[255:240]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_14 = _T_98[255:240]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_13 = _T_101[239:224]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_12 = _T_98[239:224]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_11 = _T_101[223:208]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_10 = _T_98[223:208]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_9 = _T_101[207:192]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_8 = _T_98[207:192]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_7 = _T_101[191:176]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_6 = _T_98[191:176]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_5 = _T_101[175:160]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_4 = _T_98[175:160]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_3 = _T_101[159:144]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_2 = _T_98[159:144]; // @[VAluInt.scala 705:21]
- wire [15:0] zip1_1_1 = _T_101[143:128]; // @[VAluInt.scala 708:21]
- wire [15:0] zip1_1_0 = _T_98[143:128]; // @[VAluInt.scala 705:21]
- wire [127:0] out1_lo_1 = {zip1_1_7,zip1_1_6,zip1_1_5,zip1_1_4,zip1_1_3,zip1_1_2,zip1_1_1,zip1_1_0}; // @[VAluInt.scala 713:21]
- wire [255:0] ziph1 = {zip1_1_15,zip1_1_14,zip1_1_13,zip1_1_12,zip1_1_11,zip1_1_10,zip1_1_9,zip1_1_8,out1_lo_1}; // @[VAluInt.scala 713:21]
- wire [255:0] _zip1_T = zipb1 | ziph1; // @[VAluInt.scala 725:20]
- wire [31:0] zip1_2_7 = _T_107[255:224]; // @[VAluInt.scala 708:21]
- wire [31:0] zip1_2_6 = _T_104[255:224]; // @[VAluInt.scala 705:21]
- wire [31:0] zip1_2_5 = _T_107[223:192]; // @[VAluInt.scala 708:21]
- wire [31:0] zip1_2_4 = _T_104[223:192]; // @[VAluInt.scala 705:21]
- wire [31:0] zip1_2_3 = _T_107[191:160]; // @[VAluInt.scala 708:21]
- wire [31:0] zip1_2_2 = _T_104[191:160]; // @[VAluInt.scala 705:21]
- wire [31:0] zip1_2_1 = _T_107[159:128]; // @[VAluInt.scala 708:21]
- wire [31:0] zip1_2_0 = _T_104[159:128]; // @[VAluInt.scala 705:21]
- wire [255:0] zipw1 = {zip1_2_7,zip1_2_6,zip1_2_5,zip1_2_4,zip1_2_3,zip1_2_2,zip1_2_1,zip1_2_0}; // @[VAluInt.scala 713:21]
- wire [255:0] zip1_3 = _zip1_T | zipw1; // @[VAluInt.scala 725:28]
- wire [255:0] _load_1_T = odd1 | zip1_3; // @[VAluInt.scala 743:19]
- wire _slidenb1_T_5 = slidehn2 & sz[0]; // @[VAluInt.scala 599:96]
- wire [255:0] _slidenb1_T_6 = _slidenb1_T_5 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidenb1_in_32 = _slidenb1_T_6[7:0]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenb1_T_3 = _slidenb1_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidenb1_in_31 = _slidenb1_T_3[255:248]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_30 = _slidenb1_T_3[247:240]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_29 = _slidenb1_T_3[239:232]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_28 = _slidenb1_T_3[231:224]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_27 = _slidenb1_T_3[223:216]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_26 = _slidenb1_T_3[215:208]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_25 = _slidenb1_T_3[207:200]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_24 = _slidenb1_T_3[199:192]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_23 = _slidenb1_T_3[191:184]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_22 = _slidenb1_T_3[183:176]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_21 = _slidenb1_T_3[175:168]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_20 = _slidenb1_T_3[167:160]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_19 = _slidenb1_T_3[159:152]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_18 = _slidenb1_T_3[151:144]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_17 = _slidenb1_T_3[143:136]; // @[VAluInt.scala 538:23]
- wire [63:0] slidenb1_out_hi_lo = {slidenb1_in_24,slidenb1_in_23,slidenb1_in_22,slidenb1_in_21,slidenb1_in_20,
- slidenb1_in_19,slidenb1_in_18,slidenb1_in_17}; // @[VAluInt.scala 549:40]
- wire [7:0] slidenb1_in_16 = _slidenb1_T_3[135:128]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_15 = _slidenb1_T_3[127:120]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_14 = _slidenb1_T_3[119:112]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_13 = _slidenb1_T_3[111:104]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_12 = _slidenb1_T_3[103:96]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_11 = _slidenb1_T_3[95:88]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_10 = _slidenb1_T_3[87:80]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_9 = _slidenb1_T_3[79:72]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_8 = _slidenb1_T_3[71:64]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_7 = _slidenb1_T_3[63:56]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_6 = _slidenb1_T_3[55:48]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_5 = _slidenb1_T_3[47:40]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_4 = _slidenb1_T_3[39:32]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_3 = _slidenb1_T_3[31:24]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_2 = _slidenb1_T_3[23:16]; // @[VAluInt.scala 538:23]
- wire [7:0] slidenb1_in_1 = _slidenb1_T_3[15:8]; // @[VAluInt.scala 538:23]
- wire [63:0] slidenb1_out_lo_lo = {slidenb1_in_8,slidenb1_in_7,slidenb1_in_6,slidenb1_in_5,slidenb1_in_4,slidenb1_in_3,
- slidenb1_in_2,slidenb1_in_1}; // @[VAluInt.scala 549:40]
- wire [127:0] slidenb1_out_lo = {slidenb1_in_16,slidenb1_in_15,slidenb1_in_14,slidenb1_in_13,slidenb1_in_12,
- slidenb1_in_11,slidenb1_in_10,slidenb1_in_9,slidenb1_out_lo_lo}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenb1_out_T_1 = {slidenb1_in_32,slidenb1_in_31,slidenb1_in_30,slidenb1_in_29,slidenb1_in_28,
- slidenb1_in_27,slidenb1_in_26,slidenb1_in_25,slidenb1_out_hi_lo,slidenb1_out_lo}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenb1_out_T_2 = _slidenb0_out_T ? _slidenb1_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidenb1_in_33 = _slidenb1_T_6[15:8]; // @[VAluInt.scala 539:23]
- wire [63:0] slidenb1_out_hi_lo_1 = {slidenb1_in_25,slidenb1_in_24,slidenb1_in_23,slidenb1_in_22,slidenb1_in_21,
- slidenb1_in_20,slidenb1_in_19,slidenb1_in_18}; // @[VAluInt.scala 550:40]
- wire [63:0] slidenb1_out_lo_lo_1 = {slidenb1_in_9,slidenb1_in_8,slidenb1_in_7,slidenb1_in_6,slidenb1_in_5,
- slidenb1_in_4,slidenb1_in_3,slidenb1_in_2}; // @[VAluInt.scala 550:40]
- wire [127:0] slidenb1_out_lo_1 = {slidenb1_in_17,slidenb1_in_16,slidenb1_in_15,slidenb1_in_14,slidenb1_in_13,
- slidenb1_in_12,slidenb1_in_11,slidenb1_in_10,slidenb1_out_lo_lo_1}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenb1_out_T_4 = {slidenb1_in_33,slidenb1_in_32,slidenb1_in_31,slidenb1_in_30,slidenb1_in_29,
- slidenb1_in_28,slidenb1_in_27,slidenb1_in_26,slidenb1_out_hi_lo_1,slidenb1_out_lo_1}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenb1_out_T_5 = _slidenb0_out_T_3 ? _slidenb1_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenb1_out_T_6 = _slidenb1_out_T_2 | _slidenb1_out_T_5; // @[VAluInt.scala 549:48]
- wire [7:0] slidenb1_in_34 = _slidenb1_T_6[23:16]; // @[VAluInt.scala 539:23]
- wire [63:0] slidenb1_out_hi_lo_2 = {slidenb1_in_26,slidenb1_in_25,slidenb1_in_24,slidenb1_in_23,slidenb1_in_22,
- slidenb1_in_21,slidenb1_in_20,slidenb1_in_19}; // @[VAluInt.scala 551:40]
- wire [63:0] slidenb1_out_lo_lo_2 = {slidenb1_in_10,slidenb1_in_9,slidenb1_in_8,slidenb1_in_7,slidenb1_in_6,
- slidenb1_in_5,slidenb1_in_4,slidenb1_in_3}; // @[VAluInt.scala 551:40]
- wire [127:0] slidenb1_out_lo_2 = {slidenb1_in_18,slidenb1_in_17,slidenb1_in_16,slidenb1_in_15,slidenb1_in_14,
- slidenb1_in_13,slidenb1_in_12,slidenb1_in_11,slidenb1_out_lo_lo_2}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenb1_out_T_8 = {slidenb1_in_34,slidenb1_in_33,slidenb1_in_32,slidenb1_in_31,slidenb1_in_30,
- slidenb1_in_29,slidenb1_in_28,slidenb1_in_27,slidenb1_out_hi_lo_2,slidenb1_out_lo_2}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenb1_out_T_9 = _slidenb0_out_T_7 ? _slidenb1_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenb1_out_T_10 = _slidenb1_out_T_6 | _slidenb1_out_T_9; // @[VAluInt.scala 550:48]
- wire [7:0] slidenb1_in_35 = _slidenb1_T_6[31:24]; // @[VAluInt.scala 539:23]
- wire [63:0] slidenb1_out_hi_lo_3 = {slidenb1_in_27,slidenb1_in_26,slidenb1_in_25,slidenb1_in_24,slidenb1_in_23,
- slidenb1_in_22,slidenb1_in_21,slidenb1_in_20}; // @[VAluInt.scala 552:40]
- wire [63:0] slidenb1_out_lo_lo_3 = {slidenb1_in_11,slidenb1_in_10,slidenb1_in_9,slidenb1_in_8,slidenb1_in_7,
- slidenb1_in_6,slidenb1_in_5,slidenb1_in_4}; // @[VAluInt.scala 552:40]
- wire [127:0] slidenb1_out_lo_3 = {slidenb1_in_19,slidenb1_in_18,slidenb1_in_17,slidenb1_in_16,slidenb1_in_15,
- slidenb1_in_14,slidenb1_in_13,slidenb1_in_12,slidenb1_out_lo_lo_3}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenb1_out_T_12 = {slidenb1_in_35,slidenb1_in_34,slidenb1_in_33,slidenb1_in_32,slidenb1_in_31,
- slidenb1_in_30,slidenb1_in_29,slidenb1_in_28,slidenb1_out_hi_lo_3,slidenb1_out_lo_3}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenb1_out_T_13 = _slidenb0_out_T_11 ? _slidenb1_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidenb1 = _slidenb1_out_T_10 | _slidenb1_out_T_13; // @[VAluInt.scala 551:48]
- wire _slidenh1_T_5 = slidehn2 & sz[1]; // @[VAluInt.scala 600:96]
- wire [255:0] _slidenh1_T_6 = _slidenh1_T_5 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slidenh1_in_16 = _slidenh1_T_6[15:0]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenh1_T_3 = _slidenh1_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slidenh1_in_15 = _slidenh1_T_3[255:240]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_14 = _slidenh1_T_3[239:224]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_13 = _slidenh1_T_3[223:208]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_12 = _slidenh1_T_3[207:192]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_11 = _slidenh1_T_3[191:176]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_10 = _slidenh1_T_3[175:160]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_9 = _slidenh1_T_3[159:144]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_8 = _slidenh1_T_3[143:128]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_7 = _slidenh1_T_3[127:112]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_6 = _slidenh1_T_3[111:96]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_5 = _slidenh1_T_3[95:80]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_4 = _slidenh1_T_3[79:64]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_3 = _slidenh1_T_3[63:48]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_2 = _slidenh1_T_3[47:32]; // @[VAluInt.scala 538:23]
- wire [15:0] slidenh1_in_1 = _slidenh1_T_3[31:16]; // @[VAluInt.scala 538:23]
- wire [127:0] slidenh1_out_lo = {slidenh1_in_8,slidenh1_in_7,slidenh1_in_6,slidenh1_in_5,slidenh1_in_4,slidenh1_in_3,
- slidenh1_in_2,slidenh1_in_1}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenh1_out_T_1 = {slidenh1_in_16,slidenh1_in_15,slidenh1_in_14,slidenh1_in_13,slidenh1_in_12,
- slidenh1_in_11,slidenh1_in_10,slidenh1_in_9,slidenh1_out_lo}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenh1_out_T_2 = _slidenb0_out_T ? _slidenh1_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slidenh1_in_17 = _slidenh1_T_6[31:16]; // @[VAluInt.scala 539:23]
- wire [127:0] slidenh1_out_lo_1 = {slidenh1_in_9,slidenh1_in_8,slidenh1_in_7,slidenh1_in_6,slidenh1_in_5,slidenh1_in_4,
- slidenh1_in_3,slidenh1_in_2}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenh1_out_T_4 = {slidenh1_in_17,slidenh1_in_16,slidenh1_in_15,slidenh1_in_14,slidenh1_in_13,
- slidenh1_in_12,slidenh1_in_11,slidenh1_in_10,slidenh1_out_lo_1}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenh1_out_T_5 = _slidenb0_out_T_3 ? _slidenh1_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenh1_out_T_6 = _slidenh1_out_T_2 | _slidenh1_out_T_5; // @[VAluInt.scala 549:48]
- wire [15:0] slidenh1_in_18 = _slidenh1_T_6[47:32]; // @[VAluInt.scala 539:23]
- wire [127:0] slidenh1_out_lo_2 = {slidenh1_in_10,slidenh1_in_9,slidenh1_in_8,slidenh1_in_7,slidenh1_in_6,slidenh1_in_5
- ,slidenh1_in_4,slidenh1_in_3}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenh1_out_T_8 = {slidenh1_in_18,slidenh1_in_17,slidenh1_in_16,slidenh1_in_15,slidenh1_in_14,
- slidenh1_in_13,slidenh1_in_12,slidenh1_in_11,slidenh1_out_lo_2}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenh1_out_T_9 = _slidenb0_out_T_7 ? _slidenh1_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenh1_out_T_10 = _slidenh1_out_T_6 | _slidenh1_out_T_9; // @[VAluInt.scala 550:48]
- wire [15:0] slidenh1_in_19 = _slidenh1_T_6[63:48]; // @[VAluInt.scala 539:23]
- wire [127:0] slidenh1_out_lo_3 = {slidenh1_in_11,slidenh1_in_10,slidenh1_in_9,slidenh1_in_8,slidenh1_in_7,
- slidenh1_in_6,slidenh1_in_5,slidenh1_in_4}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenh1_out_T_12 = {slidenh1_in_19,slidenh1_in_18,slidenh1_in_17,slidenh1_in_16,slidenh1_in_15,
- slidenh1_in_14,slidenh1_in_13,slidenh1_in_12,slidenh1_out_lo_3}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenh1_out_T_13 = _slidenb0_out_T_11 ? _slidenh1_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidenh1 = _slidenh1_out_T_10 | _slidenh1_out_T_13; // @[VAluInt.scala 551:48]
- wire [255:0] _slide1_T = slidenb1 | slidenh1; // @[VAluInt.scala 614:25]
- wire _slidenw1_T_5 = slidehn2 & sz[2]; // @[VAluInt.scala 601:96]
- wire [255:0] _slidenw1_T_6 = _slidenw1_T_5 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidenw1_in_8 = _slidenw1_T_6[31:0]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw1_T_3 = _slidenw1_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidenw1_in_7 = _slidenw1_T_3[255:224]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw1_in_6 = _slidenw1_T_3[223:192]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw1_in_5 = _slidenw1_T_3[191:160]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw1_in_4 = _slidenw1_T_3[159:128]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw1_in_3 = _slidenw1_T_3[127:96]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw1_in_2 = _slidenw1_T_3[95:64]; // @[VAluInt.scala 538:23]
- wire [31:0] slidenw1_in_1 = _slidenw1_T_3[63:32]; // @[VAluInt.scala 538:23]
- wire [255:0] _slidenw1_out_T_1 = {slidenw1_in_8,slidenw1_in_7,slidenw1_in_6,slidenw1_in_5,slidenw1_in_4,slidenw1_in_3,
- slidenw1_in_2,slidenw1_in_1}; // @[VAluInt.scala 549:40]
- wire [255:0] _slidenw1_out_T_2 = _slidenb0_out_T ? _slidenw1_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidenw1_in_9 = _slidenw1_T_6[63:32]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw1_out_T_4 = {slidenw1_in_9,slidenw1_in_8,slidenw1_in_7,slidenw1_in_6,slidenw1_in_5,slidenw1_in_4,
- slidenw1_in_3,slidenw1_in_2}; // @[VAluInt.scala 550:40]
- wire [255:0] _slidenw1_out_T_5 = _slidenb0_out_T_3 ? _slidenw1_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenw1_out_T_6 = _slidenw1_out_T_2 | _slidenw1_out_T_5; // @[VAluInt.scala 549:48]
- wire [31:0] slidenw1_in_10 = _slidenw1_T_6[95:64]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw1_out_T_8 = {slidenw1_in_10,slidenw1_in_9,slidenw1_in_8,slidenw1_in_7,slidenw1_in_6,slidenw1_in_5
- ,slidenw1_in_4,slidenw1_in_3}; // @[VAluInt.scala 551:40]
- wire [255:0] _slidenw1_out_T_9 = _slidenb0_out_T_7 ? _slidenw1_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidenw1_out_T_10 = _slidenw1_out_T_6 | _slidenw1_out_T_9; // @[VAluInt.scala 550:48]
- wire [31:0] slidenw1_in_11 = _slidenw1_T_6[127:96]; // @[VAluInt.scala 539:23]
- wire [255:0] _slidenw1_out_T_12 = {slidenw1_in_11,slidenw1_in_10,slidenw1_in_9,slidenw1_in_8,slidenw1_in_7,
- slidenw1_in_6,slidenw1_in_5,slidenw1_in_4}; // @[VAluInt.scala 552:40]
- wire [255:0] _slidenw1_out_T_13 = _slidenb0_out_T_11 ? _slidenw1_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidenw1 = _slidenw1_out_T_10 | _slidenw1_out_T_13; // @[VAluInt.scala 551:48]
- wire [255:0] _slide1_T_1 = _slide1_T | slidenw1; // @[VAluInt.scala 614:36]
- wire _slidepb1_T_5 = slidehp2 & sz[0]; // @[VAluInt.scala 607:96]
- wire [255:0] _slidepb1_T_6 = _slidepb1_T_5 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidepb1_in_62 = _slidepb1_T_6[247:240]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_61 = _slidepb1_T_6[239:232]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_60 = _slidepb1_T_6[231:224]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_59 = _slidepb1_T_6[223:216]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_58 = _slidepb1_T_6[215:208]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_57 = _slidepb1_T_6[207:200]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_56 = _slidepb1_T_6[199:192]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_55 = _slidepb1_T_6[191:184]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_54 = _slidepb1_T_6[183:176]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_53 = _slidepb1_T_6[175:168]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_52 = _slidepb1_T_6[167:160]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_51 = _slidepb1_T_6[159:152]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_50 = _slidepb1_T_6[151:144]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_49 = _slidepb1_T_6[143:136]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_48 = _slidepb1_T_6[135:128]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_47 = _slidepb1_T_6[127:120]; // @[VAluInt.scala 576:23]
- wire [63:0] slidepb1_out_hi_lo = {slidepb1_in_54,slidepb1_in_53,slidepb1_in_52,slidepb1_in_51,slidepb1_in_50,
- slidepb1_in_49,slidepb1_in_48,slidepb1_in_47}; // @[VAluInt.scala 586:40]
- wire [7:0] slidepb1_in_46 = _slidepb1_T_6[119:112]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_45 = _slidepb1_T_6[111:104]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_44 = _slidepb1_T_6[103:96]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_43 = _slidepb1_T_6[95:88]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_42 = _slidepb1_T_6[87:80]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_41 = _slidepb1_T_6[79:72]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_40 = _slidepb1_T_6[71:64]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_39 = _slidepb1_T_6[63:56]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_38 = _slidepb1_T_6[55:48]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_37 = _slidepb1_T_6[47:40]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_36 = _slidepb1_T_6[39:32]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_35 = _slidepb1_T_6[31:24]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_34 = _slidepb1_T_6[23:16]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_33 = _slidepb1_T_6[15:8]; // @[VAluInt.scala 576:23]
- wire [7:0] slidepb1_in_32 = _slidepb1_T_6[7:0]; // @[VAluInt.scala 576:23]
- wire [255:0] _slidepb1_T_3 = _slidepb1_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [7:0] slidepb1_in_31 = _slidepb1_T_3[255:248]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb1_out_lo_lo = {slidepb1_in_38,slidepb1_in_37,slidepb1_in_36,slidepb1_in_35,slidepb1_in_34,
- slidepb1_in_33,slidepb1_in_32,slidepb1_in_31}; // @[VAluInt.scala 586:40]
- wire [127:0] slidepb1_out_lo = {slidepb1_in_46,slidepb1_in_45,slidepb1_in_44,slidepb1_in_43,slidepb1_in_42,
- slidepb1_in_41,slidepb1_in_40,slidepb1_in_39,slidepb1_out_lo_lo}; // @[VAluInt.scala 586:40]
- wire [255:0] _slidepb1_out_T_1 = {slidepb1_in_62,slidepb1_in_61,slidepb1_in_60,slidepb1_in_59,slidepb1_in_58,
- slidepb1_in_57,slidepb1_in_56,slidepb1_in_55,slidepb1_out_hi_lo,slidepb1_out_lo}; // @[VAluInt.scala 586:40]
- wire [255:0] _slidepb1_out_T_2 = _slidenb0_out_T ? _slidepb1_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [63:0] slidepb1_out_hi_lo_1 = {slidepb1_in_53,slidepb1_in_52,slidepb1_in_51,slidepb1_in_50,slidepb1_in_49,
- slidepb1_in_48,slidepb1_in_47,slidepb1_in_46}; // @[VAluInt.scala 587:40]
- wire [7:0] slidepb1_in_30 = _slidepb1_T_3[247:240]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb1_out_lo_lo_1 = {slidepb1_in_37,slidepb1_in_36,slidepb1_in_35,slidepb1_in_34,slidepb1_in_33,
- slidepb1_in_32,slidepb1_in_31,slidepb1_in_30}; // @[VAluInt.scala 587:40]
- wire [127:0] slidepb1_out_lo_1 = {slidepb1_in_45,slidepb1_in_44,slidepb1_in_43,slidepb1_in_42,slidepb1_in_41,
- slidepb1_in_40,slidepb1_in_39,slidepb1_in_38,slidepb1_out_lo_lo_1}; // @[VAluInt.scala 587:40]
- wire [255:0] _slidepb1_out_T_4 = {slidepb1_in_61,slidepb1_in_60,slidepb1_in_59,slidepb1_in_58,slidepb1_in_57,
- slidepb1_in_56,slidepb1_in_55,slidepb1_in_54,slidepb1_out_hi_lo_1,slidepb1_out_lo_1}; // @[VAluInt.scala 587:40]
- wire [255:0] _slidepb1_out_T_5 = _slidenb0_out_T_3 ? _slidepb1_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepb1_out_T_6 = _slidepb1_out_T_2 | _slidepb1_out_T_5; // @[VAluInt.scala 586:48]
- wire [63:0] slidepb1_out_hi_lo_2 = {slidepb1_in_52,slidepb1_in_51,slidepb1_in_50,slidepb1_in_49,slidepb1_in_48,
- slidepb1_in_47,slidepb1_in_46,slidepb1_in_45}; // @[VAluInt.scala 588:40]
- wire [7:0] slidepb1_in_29 = _slidepb1_T_3[239:232]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb1_out_lo_lo_2 = {slidepb1_in_36,slidepb1_in_35,slidepb1_in_34,slidepb1_in_33,slidepb1_in_32,
- slidepb1_in_31,slidepb1_in_30,slidepb1_in_29}; // @[VAluInt.scala 588:40]
- wire [127:0] slidepb1_out_lo_2 = {slidepb1_in_44,slidepb1_in_43,slidepb1_in_42,slidepb1_in_41,slidepb1_in_40,
- slidepb1_in_39,slidepb1_in_38,slidepb1_in_37,slidepb1_out_lo_lo_2}; // @[VAluInt.scala 588:40]
- wire [255:0] _slidepb1_out_T_8 = {slidepb1_in_60,slidepb1_in_59,slidepb1_in_58,slidepb1_in_57,slidepb1_in_56,
- slidepb1_in_55,slidepb1_in_54,slidepb1_in_53,slidepb1_out_hi_lo_2,slidepb1_out_lo_2}; // @[VAluInt.scala 588:40]
- wire [255:0] _slidepb1_out_T_9 = _slidenb0_out_T_7 ? _slidepb1_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepb1_out_T_10 = _slidepb1_out_T_6 | _slidepb1_out_T_9; // @[VAluInt.scala 587:48]
- wire [63:0] slidepb1_out_hi_lo_3 = {slidepb1_in_51,slidepb1_in_50,slidepb1_in_49,slidepb1_in_48,slidepb1_in_47,
- slidepb1_in_46,slidepb1_in_45,slidepb1_in_44}; // @[VAluInt.scala 589:40]
- wire [7:0] slidepb1_in_28 = _slidepb1_T_3[231:224]; // @[VAluInt.scala 575:23]
- wire [63:0] slidepb1_out_lo_lo_3 = {slidepb1_in_35,slidepb1_in_34,slidepb1_in_33,slidepb1_in_32,slidepb1_in_31,
- slidepb1_in_30,slidepb1_in_29,slidepb1_in_28}; // @[VAluInt.scala 589:40]
- wire [127:0] slidepb1_out_lo_3 = {slidepb1_in_43,slidepb1_in_42,slidepb1_in_41,slidepb1_in_40,slidepb1_in_39,
- slidepb1_in_38,slidepb1_in_37,slidepb1_in_36,slidepb1_out_lo_lo_3}; // @[VAluInt.scala 589:40]
- wire [255:0] _slidepb1_out_T_12 = {slidepb1_in_59,slidepb1_in_58,slidepb1_in_57,slidepb1_in_56,slidepb1_in_55,
- slidepb1_in_54,slidepb1_in_53,slidepb1_in_52,slidepb1_out_hi_lo_3,slidepb1_out_lo_3}; // @[VAluInt.scala 589:40]
- wire [255:0] _slidepb1_out_T_13 = _slidenb0_out_T_11 ? _slidepb1_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidepb1 = _slidepb1_out_T_10 | _slidepb1_out_T_13; // @[VAluInt.scala 588:48]
- wire [255:0] _slide1_T_2 = _slide1_T_1 | slidepb1; // @[VAluInt.scala 614:47]
- wire _slideph1_T_5 = slidehp2 & sz[1]; // @[VAluInt.scala 608:96]
- wire [255:0] _slideph1_T_6 = _slideph1_T_5 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slideph1_in_30 = _slideph1_T_6[239:224]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_29 = _slideph1_T_6[223:208]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_28 = _slideph1_T_6[207:192]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_27 = _slideph1_T_6[191:176]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_26 = _slideph1_T_6[175:160]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_25 = _slideph1_T_6[159:144]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_24 = _slideph1_T_6[143:128]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_23 = _slideph1_T_6[127:112]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_22 = _slideph1_T_6[111:96]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_21 = _slideph1_T_6[95:80]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_20 = _slideph1_T_6[79:64]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_19 = _slideph1_T_6[63:48]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_18 = _slideph1_T_6[47:32]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_17 = _slideph1_T_6[31:16]; // @[VAluInt.scala 576:23]
- wire [15:0] slideph1_in_16 = _slideph1_T_6[15:0]; // @[VAluInt.scala 576:23]
- wire [255:0] _slideph1_T_3 = _slideph1_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slideph1_in_15 = _slideph1_T_3[255:240]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph1_out_lo = {slideph1_in_22,slideph1_in_21,slideph1_in_20,slideph1_in_19,slideph1_in_18,
- slideph1_in_17,slideph1_in_16,slideph1_in_15}; // @[VAluInt.scala 586:40]
- wire [255:0] _slideph1_out_T_1 = {slideph1_in_30,slideph1_in_29,slideph1_in_28,slideph1_in_27,slideph1_in_26,
- slideph1_in_25,slideph1_in_24,slideph1_in_23,slideph1_out_lo}; // @[VAluInt.scala 586:40]
- wire [255:0] _slideph1_out_T_2 = _slidenb0_out_T ? _slideph1_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [15:0] slideph1_in_14 = _slideph1_T_3[239:224]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph1_out_lo_1 = {slideph1_in_21,slideph1_in_20,slideph1_in_19,slideph1_in_18,slideph1_in_17,
- slideph1_in_16,slideph1_in_15,slideph1_in_14}; // @[VAluInt.scala 587:40]
- wire [255:0] _slideph1_out_T_4 = {slideph1_in_29,slideph1_in_28,slideph1_in_27,slideph1_in_26,slideph1_in_25,
- slideph1_in_24,slideph1_in_23,slideph1_in_22,slideph1_out_lo_1}; // @[VAluInt.scala 587:40]
- wire [255:0] _slideph1_out_T_5 = _slidenb0_out_T_3 ? _slideph1_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slideph1_out_T_6 = _slideph1_out_T_2 | _slideph1_out_T_5; // @[VAluInt.scala 586:48]
- wire [15:0] slideph1_in_13 = _slideph1_T_3[223:208]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph1_out_lo_2 = {slideph1_in_20,slideph1_in_19,slideph1_in_18,slideph1_in_17,slideph1_in_16,
- slideph1_in_15,slideph1_in_14,slideph1_in_13}; // @[VAluInt.scala 588:40]
- wire [255:0] _slideph1_out_T_8 = {slideph1_in_28,slideph1_in_27,slideph1_in_26,slideph1_in_25,slideph1_in_24,
- slideph1_in_23,slideph1_in_22,slideph1_in_21,slideph1_out_lo_2}; // @[VAluInt.scala 588:40]
- wire [255:0] _slideph1_out_T_9 = _slidenb0_out_T_7 ? _slideph1_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slideph1_out_T_10 = _slideph1_out_T_6 | _slideph1_out_T_9; // @[VAluInt.scala 587:48]
- wire [15:0] slideph1_in_12 = _slideph1_T_3[207:192]; // @[VAluInt.scala 575:23]
- wire [127:0] slideph1_out_lo_3 = {slideph1_in_19,slideph1_in_18,slideph1_in_17,slideph1_in_16,slideph1_in_15,
- slideph1_in_14,slideph1_in_13,slideph1_in_12}; // @[VAluInt.scala 589:40]
- wire [255:0] _slideph1_out_T_12 = {slideph1_in_27,slideph1_in_26,slideph1_in_25,slideph1_in_24,slideph1_in_23,
- slideph1_in_22,slideph1_in_21,slideph1_in_20,slideph1_out_lo_3}; // @[VAluInt.scala 589:40]
- wire [255:0] _slideph1_out_T_13 = _slidenb0_out_T_11 ? _slideph1_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slideph1 = _slideph1_out_T_10 | _slideph1_out_T_13; // @[VAluInt.scala 588:48]
- wire [255:0] _slide1_T_3 = _slide1_T_2 | slideph1; // @[VAluInt.scala 615:25]
- wire _slidepw1_T_5 = slidehp2 & sz[2]; // @[VAluInt.scala 609:96]
- wire [255:0] _slidepw1_T_6 = _slidepw1_T_5 ? io_read_2_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidepw1_in_14 = _slidepw1_T_6[223:192]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw1_in_13 = _slidepw1_T_6[191:160]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw1_in_12 = _slidepw1_T_6[159:128]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw1_in_11 = _slidepw1_T_6[127:96]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw1_in_10 = _slidepw1_T_6[95:64]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw1_in_9 = _slidepw1_T_6[63:32]; // @[VAluInt.scala 576:23]
- wire [31:0] slidepw1_in_8 = _slidepw1_T_6[31:0]; // @[VAluInt.scala 576:23]
- wire [255:0] _slidepw1_T_3 = _slidepw1_T_5 ? io_read_1_data : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidepw1_in_7 = _slidepw1_T_3[255:224]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw1_out_T_1 = {slidepw1_in_14,slidepw1_in_13,slidepw1_in_12,slidepw1_in_11,slidepw1_in_10,
- slidepw1_in_9,slidepw1_in_8,slidepw1_in_7}; // @[VAluInt.scala 586:40]
- wire [255:0] _slidepw1_out_T_2 = _slidenb0_out_T ? _slidepw1_out_T_1 : 256'h0; // @[Library.scala 32:8]
- wire [31:0] slidepw1_in_6 = _slidepw1_T_3[223:192]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw1_out_T_4 = {slidepw1_in_13,slidepw1_in_12,slidepw1_in_11,slidepw1_in_10,slidepw1_in_9,
- slidepw1_in_8,slidepw1_in_7,slidepw1_in_6}; // @[VAluInt.scala 587:40]
- wire [255:0] _slidepw1_out_T_5 = _slidenb0_out_T_3 ? _slidepw1_out_T_4 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepw1_out_T_6 = _slidepw1_out_T_2 | _slidepw1_out_T_5; // @[VAluInt.scala 586:48]
- wire [31:0] slidepw1_in_5 = _slidepw1_T_3[191:160]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw1_out_T_8 = {slidepw1_in_12,slidepw1_in_11,slidepw1_in_10,slidepw1_in_9,slidepw1_in_8,
- slidepw1_in_7,slidepw1_in_6,slidepw1_in_5}; // @[VAluInt.scala 588:40]
- wire [255:0] _slidepw1_out_T_9 = _slidenb0_out_T_7 ? _slidepw1_out_T_8 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _slidepw1_out_T_10 = _slidepw1_out_T_6 | _slidepw1_out_T_9; // @[VAluInt.scala 587:48]
- wire [31:0] slidepw1_in_4 = _slidepw1_T_3[159:128]; // @[VAluInt.scala 575:23]
- wire [255:0] _slidepw1_out_T_12 = {slidepw1_in_11,slidepw1_in_10,slidepw1_in_9,slidepw1_in_8,slidepw1_in_7,
- slidepw1_in_6,slidepw1_in_5,slidepw1_in_4}; // @[VAluInt.scala 589:40]
- wire [255:0] _slidepw1_out_T_13 = _slidenb0_out_T_11 ? _slidepw1_out_T_12 : 256'h0; // @[Library.scala 32:8]
- wire [255:0] slidepw1 = _slidepw1_out_T_10 | _slidepw1_out_T_13; // @[VAluInt.scala 588:48]
- wire [255:0] slide1 = _slide1_T_3 | slidepw1; // @[VAluInt.scala 615:36]
- wire [255:0] _load_1_T_1 = _load_1_T | slide1; // @[VAluInt.scala 743:26]
- wire as_45 = adatac_0_7[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_182 = {as_45,adatac_0_7[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_45 = $signed(_aval_T_182) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_45 = bdatac_0_7[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_182 = {bs_45,bdatac_0_7[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_45 = $signed(_bval_T_182) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_45 = $signed(aval_45) * $signed(bval_45); // @[VDot.scala 172:25]
- wire as_46 = adatac_1_7[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_186 = {as_46,adatac_1_7[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_46 = $signed(_aval_T_186) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_46 = bdatac_1_7[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_186 = {bs_46,bdatac_1_7[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_46 = $signed(_bval_T_186) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_46 = $signed(aval_46) * $signed(bval_46); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_15 = $signed(mval_45) + $signed(mval_46); // @[VDot.scala 180:26]
- wire as_47 = adatac_2_7[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_190 = {as_47,adatac_2_7[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_47 = $signed(_aval_T_190) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_47 = bdatac_2_7[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_190 = {bs_47,bdatac_2_7[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_47 = $signed(_bval_T_190) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_47 = $signed(aval_47) * $signed(bval_47); // @[VDot.scala 172:25]
- wire [20:0] _GEN_102 = {{1{mval_47[19]}},mval_47}; // @[VDot.scala 180:37]
- wire [21:0] dotp_15 = $signed(_dotp_T_15) + $signed(_GEN_102); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_47 = dotp_15[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_15 = $signed(_dotp_T_15) + $signed(_GEN_102); // @[Cat.scala 31:58]
- wire as_39 = adatac_0_6[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_158 = {as_39,adatac_0_6[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_39 = $signed(_aval_T_158) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_39 = bdatac_0_6[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_158 = {bs_39,bdatac_0_6[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_39 = $signed(_bval_T_158) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_39 = $signed(aval_39) * $signed(bval_39); // @[VDot.scala 172:25]
- wire as_40 = adatac_1_6[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_162 = {as_40,adatac_1_6[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_40 = $signed(_aval_T_162) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_40 = bdatac_1_6[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_162 = {bs_40,bdatac_1_6[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_40 = $signed(_bval_T_162) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_40 = $signed(aval_40) * $signed(bval_40); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_13 = $signed(mval_39) + $signed(mval_40); // @[VDot.scala 180:26]
- wire as_41 = adatac_2_6[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_166 = {as_41,adatac_2_6[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_41 = $signed(_aval_T_166) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_41 = bdatac_2_6[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_166 = {bs_41,bdatac_2_6[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_41 = $signed(_bval_T_166) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_41 = $signed(aval_41) * $signed(bval_41); // @[VDot.scala 172:25]
- wire [20:0] _GEN_103 = {{1{mval_41[19]}},mval_41}; // @[VDot.scala 180:37]
- wire [21:0] dotp_13 = $signed(_dotp_T_13) + $signed(_GEN_103); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_41 = dotp_13[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_13 = $signed(_dotp_T_13) + $signed(_GEN_103); // @[Cat.scala 31:58]
- wire as_33 = adatac_0_5[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_134 = {as_33,adatac_0_5[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_33 = $signed(_aval_T_134) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_33 = bdatac_0_5[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_134 = {bs_33,bdatac_0_5[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_33 = $signed(_bval_T_134) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_33 = $signed(aval_33) * $signed(bval_33); // @[VDot.scala 172:25]
- wire as_34 = adatac_1_5[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_138 = {as_34,adatac_1_5[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_34 = $signed(_aval_T_138) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_34 = bdatac_1_5[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_138 = {bs_34,bdatac_1_5[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_34 = $signed(_bval_T_138) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_34 = $signed(aval_34) * $signed(bval_34); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_11 = $signed(mval_33) + $signed(mval_34); // @[VDot.scala 180:26]
- wire as_35 = adatac_2_5[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_142 = {as_35,adatac_2_5[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_35 = $signed(_aval_T_142) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_35 = bdatac_2_5[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_142 = {bs_35,bdatac_2_5[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_35 = $signed(_bval_T_142) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_35 = $signed(aval_35) * $signed(bval_35); // @[VDot.scala 172:25]
- wire [20:0] _GEN_104 = {{1{mval_35[19]}},mval_35}; // @[VDot.scala 180:37]
- wire [21:0] dotp_11 = $signed(_dotp_T_11) + $signed(_GEN_104); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_35 = dotp_11[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_11 = $signed(_dotp_T_11) + $signed(_GEN_104); // @[Cat.scala 31:58]
- wire as_27 = adatac_0_4[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_110 = {as_27,adatac_0_4[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_27 = $signed(_aval_T_110) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_27 = bdatac_0_4[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_110 = {bs_27,bdatac_0_4[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_27 = $signed(_bval_T_110) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_27 = $signed(aval_27) * $signed(bval_27); // @[VDot.scala 172:25]
- wire as_28 = adatac_1_4[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_114 = {as_28,adatac_1_4[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_28 = $signed(_aval_T_114) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_28 = bdatac_1_4[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_114 = {bs_28,bdatac_1_4[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_28 = $signed(_bval_T_114) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_28 = $signed(aval_28) * $signed(bval_28); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_9 = $signed(mval_27) + $signed(mval_28); // @[VDot.scala 180:26]
- wire as_29 = adatac_2_4[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_118 = {as_29,adatac_2_4[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_29 = $signed(_aval_T_118) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_29 = bdatac_2_4[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_118 = {bs_29,bdatac_2_4[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_29 = $signed(_bval_T_118) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_29 = $signed(aval_29) * $signed(bval_29); // @[VDot.scala 172:25]
- wire [20:0] _GEN_105 = {{1{mval_29[19]}},mval_29}; // @[VDot.scala 180:37]
- wire [21:0] dotp_9 = $signed(_dotp_T_9) + $signed(_GEN_105); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_29 = dotp_9[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_9 = $signed(_dotp_T_9) + $signed(_GEN_105); // @[Cat.scala 31:58]
- wire as_21 = adatac_0_3[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_86 = {as_21,adatac_0_3[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_21 = $signed(_aval_T_86) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_21 = bdatac_0_3[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_86 = {bs_21,bdatac_0_3[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_21 = $signed(_bval_T_86) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_21 = $signed(aval_21) * $signed(bval_21); // @[VDot.scala 172:25]
- wire as_22 = adatac_1_3[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_90 = {as_22,adatac_1_3[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_22 = $signed(_aval_T_90) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_22 = bdatac_1_3[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_90 = {bs_22,bdatac_1_3[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_22 = $signed(_bval_T_90) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_22 = $signed(aval_22) * $signed(bval_22); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_7 = $signed(mval_21) + $signed(mval_22); // @[VDot.scala 180:26]
- wire as_23 = adatac_2_3[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_94 = {as_23,adatac_2_3[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_23 = $signed(_aval_T_94) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_23 = bdatac_2_3[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_94 = {bs_23,bdatac_2_3[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_23 = $signed(_bval_T_94) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_23 = $signed(aval_23) * $signed(bval_23); // @[VDot.scala 172:25]
- wire [20:0] _GEN_106 = {{1{mval_23[19]}},mval_23}; // @[VDot.scala 180:37]
- wire [21:0] dotp_7 = $signed(_dotp_T_7) + $signed(_GEN_106); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_23 = dotp_7[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_7 = $signed(_dotp_T_7) + $signed(_GEN_106); // @[Cat.scala 31:58]
- wire as_15 = adatac_0_2[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_62 = {as_15,adatac_0_2[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_15 = $signed(_aval_T_62) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_15 = bdatac_0_2[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_62 = {bs_15,bdatac_0_2[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_15 = $signed(_bval_T_62) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_15 = $signed(aval_15) * $signed(bval_15); // @[VDot.scala 172:25]
- wire as_16 = adatac_1_2[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_66 = {as_16,adatac_1_2[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_16 = $signed(_aval_T_66) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_16 = bdatac_1_2[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_66 = {bs_16,bdatac_1_2[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_16 = $signed(_bval_T_66) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_16 = $signed(aval_16) * $signed(bval_16); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_5 = $signed(mval_15) + $signed(mval_16); // @[VDot.scala 180:26]
- wire as_17 = adatac_2_2[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_70 = {as_17,adatac_2_2[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_17 = $signed(_aval_T_70) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_17 = bdatac_2_2[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_70 = {bs_17,bdatac_2_2[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_17 = $signed(_bval_T_70) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_17 = $signed(aval_17) * $signed(bval_17); // @[VDot.scala 172:25]
- wire [20:0] _GEN_107 = {{1{mval_17[19]}},mval_17}; // @[VDot.scala 180:37]
- wire [21:0] dotp_5 = $signed(_dotp_T_5) + $signed(_GEN_107); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_17 = dotp_5[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_5 = $signed(_dotp_T_5) + $signed(_GEN_107); // @[Cat.scala 31:58]
- wire as_9 = adatac_0_1[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_38 = {as_9,adatac_0_1[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_9 = $signed(_aval_T_38) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_9 = bdatac_0_1[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_38 = {bs_9,bdatac_0_1[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_9 = $signed(_bval_T_38) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_9 = $signed(aval_9) * $signed(bval_9); // @[VDot.scala 172:25]
- wire as_10 = adatac_1_1[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_42 = {as_10,adatac_1_1[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_10 = $signed(_aval_T_42) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_10 = bdatac_1_1[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_42 = {bs_10,bdatac_1_1[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_10 = $signed(_bval_T_42) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_10 = $signed(aval_10) * $signed(bval_10); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_3 = $signed(mval_9) + $signed(mval_10); // @[VDot.scala 180:26]
- wire as_11 = adatac_2_1[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_46 = {as_11,adatac_2_1[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_11 = $signed(_aval_T_46) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_11 = bdatac_2_1[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_46 = {bs_11,bdatac_2_1[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_11 = $signed(_bval_T_46) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_11 = $signed(aval_11) * $signed(bval_11); // @[VDot.scala 172:25]
- wire [20:0] _GEN_108 = {{1{mval_11[19]}},mval_11}; // @[VDot.scala 180:37]
- wire [21:0] dotp_3 = $signed(_dotp_T_3) + $signed(_GEN_108); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_11 = dotp_3[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_3 = $signed(_dotp_T_3) + $signed(_GEN_108); // @[Cat.scala 31:58]
- wire as_3 = adatac_0_0[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_14 = {as_3,adatac_0_0[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_3 = $signed(_aval_T_14) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_3 = bdatac_0_0[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_14 = {bs_3,bdatac_0_0[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_3 = $signed(_bval_T_14) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_3 = $signed(aval_3) * $signed(bval_3); // @[VDot.scala 172:25]
- wire as_4 = adatac_1_0[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_18 = {as_4,adatac_1_0[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_4 = $signed(_aval_T_18) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_4 = bdatac_1_0[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_18 = {bs_4,bdatac_1_0[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_4 = $signed(_bval_T_18) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_4 = $signed(aval_4) * $signed(bval_4); // @[VDot.scala 172:25]
- wire [20:0] _dotp_T_1 = $signed(mval_3) + $signed(mval_4); // @[VDot.scala 180:26]
- wire as_5 = adatac_2_0[31] & asign; // @[VDot.scala 168:38]
- wire [8:0] _aval_T_22 = {as_5,adatac_2_0[31:24]}; // @[VDot.scala 170:56]
- wire [9:0] aval_5 = $signed(_aval_T_22) + $signed(_aval_T_171); // @[VDot.scala 170:63]
- wire bs_5 = bdatac_2_0[31] & bsign; // @[VDot.scala 169:38]
- wire [8:0] _bval_T_22 = {bs_5,bdatac_2_0[31:24]}; // @[VDot.scala 171:56]
- wire [9:0] bval_5 = $signed(_bval_T_22) + $signed(_bval_T_171); // @[VDot.scala 171:63]
- wire [19:0] mval_5 = $signed(aval_5) * $signed(bval_5); // @[VDot.scala 172:25]
- wire [20:0] _GEN_109 = {{1{mval_5[19]}},mval_5}; // @[VDot.scala 180:37]
- wire [21:0] dotp_1 = $signed(_dotp_T_1) + $signed(_GEN_109); // @[VDot.scala 180:37]
- wire [9:0] _sdotp_T_5 = dotp_1[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] sdotp_lo_1 = $signed(_dotp_T_1) + $signed(_GEN_109); // @[Cat.scala 31:58]
- wire [127:0] out1_lo_3 = {_sdotp_T_23,sdotp_lo_7,_sdotp_T_17,sdotp_lo_5,_sdotp_T_11,sdotp_lo_3,_sdotp_T_5,sdotp_lo_1}; // @[VDot.scala 143:22]
- wire [255:0] dwconv1 = {_sdotp_T_47,sdotp_lo_15,_sdotp_T_41,sdotp_lo_13,_sdotp_T_35,sdotp_lo_11,_sdotp_T_29,sdotp_lo_9
- ,out1_lo_3}; // @[VDot.scala 143:22]
- wire [255:0] load_1 = _load_1_T_1 | dwconv1; // @[VAluInt.scala 743:35]
- wire [31:0] vddata_1 = valu_1_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [31:0] vddata_0 = valu_0_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [31:0] vddata_3 = valu_3_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [31:0] vddata_2 = valu_2_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [127:0] io_write_0_data_lo = {vddata_3,vddata_2,vddata_1,vddata_0}; // @[VAluInt.scala 757:30]
- wire [31:0] vddata_5 = valu_5_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [31:0] vddata_4 = valu_4_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [31:0] vddata_7 = valu_7_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [31:0] vddata_6 = valu_6_io_write_0_data; // @[VAluInt.scala 747:20 751:15]
- wire [127:0] io_write_0_data_hi = {vddata_7,vddata_6,vddata_5,vddata_4}; // @[VAluInt.scala 757:30]
- wire [31:0] vedata_1 = valu_1_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [31:0] vedata_0 = valu_0_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [31:0] vedata_3 = valu_3_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [31:0] vedata_2 = valu_2_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [127:0] io_write_1_data_lo = {vedata_3,vedata_2,vedata_1,vedata_0}; // @[VAluInt.scala 761:30]
- wire [31:0] vedata_5 = valu_5_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [31:0] vedata_4 = valu_4_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [31:0] vedata_7 = valu_7_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [31:0] vedata_6 = valu_6_io_write_1_data; // @[VAluInt.scala 748:20 752:15]
- wire [127:0] io_write_1_data_hi = {vedata_7,vedata_6,vedata_5,vedata_4}; // @[VAluInt.scala 761:30]
- VAluIntLane valu_0 ( // @[VAluInt.scala 418:11]
- .clock(valu_0_clock),
- .reset(valu_0_reset),
- .io_in_vdvalid(valu_0_io_in_vdvalid),
- .io_in_vevalid(valu_0_io_in_vevalid),
- .io_in_sz(valu_0_io_in_sz),
- .io_in_negative(valu_0_io_in_negative),
- .io_in_round(valu_0_io_in_round),
- .io_in_signed(valu_0_io_in_signed),
- .io_op_absd(valu_0_io_op_absd),
- .io_op_acc(valu_0_io_op_acc),
- .io_op_dup(valu_0_io_op_dup),
- .io_op_max(valu_0_io_op_max),
- .io_op_min(valu_0_io_op_min),
- .io_op_mv(valu_0_io_op_mv),
- .io_op_mv2(valu_0_io_op_mv2),
- .io_op_mvp(valu_0_io_op_mvp),
- .io_op_srans(valu_0_io_op_srans),
- .io_op_sraqs(valu_0_io_op_sraqs),
- .io_op_dwinit(valu_0_io_op_dwinit),
- .io_op_dwconv(valu_0_io_op_dwconv),
- .io_op_dwconvData(valu_0_io_op_dwconvData),
- .io_op_add_en(valu_0_io_op_add_en),
- .io_op_add_add(valu_0_io_op_add_add),
- .io_op_add_adds(valu_0_io_op_add_adds),
- .io_op_add_addw(valu_0_io_op_add_addw),
- .io_op_add_add3(valu_0_io_op_add_add3),
- .io_op_add_hadd(valu_0_io_op_add_hadd),
- .io_op_cmp_en(valu_0_io_op_cmp_en),
- .io_op_cmp_eq(valu_0_io_op_cmp_eq),
- .io_op_cmp_ne(valu_0_io_op_cmp_ne),
- .io_op_cmp_lt(valu_0_io_op_cmp_lt),
- .io_op_cmp_le(valu_0_io_op_cmp_le),
- .io_op_cmp_gt(valu_0_io_op_cmp_gt),
- .io_op_cmp_ge(valu_0_io_op_cmp_ge),
- .io_op_log_en(valu_0_io_op_log_en),
- .io_op_log_and(valu_0_io_op_log_and),
- .io_op_log_or(valu_0_io_op_log_or),
- .io_op_log_xor(valu_0_io_op_log_xor),
- .io_op_log_not(valu_0_io_op_log_not),
- .io_op_log_rev(valu_0_io_op_log_rev),
- .io_op_log_ror(valu_0_io_op_log_ror),
- .io_op_log_clb(valu_0_io_op_log_clb),
- .io_op_log_clz(valu_0_io_op_log_clz),
- .io_op_log_cpop(valu_0_io_op_log_cpop),
- .io_op_mul0_en(valu_0_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_0_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_0_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_0_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_0_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_0_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_0_io_op_mul0_madd),
- .io_op_mul1_en(valu_0_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_0_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_0_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_0_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_0_io_op_mul1_muls),
- .io_op_padd_en(valu_0_io_op_padd_en),
- .io_op_padd_add(valu_0_io_op_padd_add),
- .io_op_padd_sub(valu_0_io_op_padd_sub),
- .io_op_rsub_en(valu_0_io_op_rsub_en),
- .io_op_rsub_rsub(valu_0_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_0_io_op_shf_en_l),
- .io_op_shf_en_r(valu_0_io_op_shf_en_r),
- .io_op_shf_shl(valu_0_io_op_shf_shl),
- .io_op_shf_shr(valu_0_io_op_shf_shr),
- .io_op_shf_shf(valu_0_io_op_shf_shf),
- .io_op_sub_en(valu_0_io_op_sub_en),
- .io_op_sub_sub(valu_0_io_op_sub_sub),
- .io_op_sub_subs(valu_0_io_op_sub_subs),
- .io_op_sub_subw(valu_0_io_op_sub_subw),
- .io_op_sub_hsub(valu_0_io_op_sub_hsub),
- .io_read_0_data(valu_0_io_read_0_data),
- .io_read_1_data(valu_0_io_read_1_data),
- .io_read_2_data(valu_0_io_read_2_data),
- .io_read_3_data(valu_0_io_read_3_data),
- .io_read_5_data(valu_0_io_read_5_data),
- .io_write_0_data(valu_0_io_write_0_data),
- .io_write_1_data(valu_0_io_write_1_data),
- .io_load_0(valu_0_io_load_0),
- .io_load_1(valu_0_io_load_1)
- );
- VAluIntLane valu_1 ( // @[VAluInt.scala 418:11]
- .clock(valu_1_clock),
- .reset(valu_1_reset),
- .io_in_vdvalid(valu_1_io_in_vdvalid),
- .io_in_vevalid(valu_1_io_in_vevalid),
- .io_in_sz(valu_1_io_in_sz),
- .io_in_negative(valu_1_io_in_negative),
- .io_in_round(valu_1_io_in_round),
- .io_in_signed(valu_1_io_in_signed),
- .io_op_absd(valu_1_io_op_absd),
- .io_op_acc(valu_1_io_op_acc),
- .io_op_dup(valu_1_io_op_dup),
- .io_op_max(valu_1_io_op_max),
- .io_op_min(valu_1_io_op_min),
- .io_op_mv(valu_1_io_op_mv),
- .io_op_mv2(valu_1_io_op_mv2),
- .io_op_mvp(valu_1_io_op_mvp),
- .io_op_srans(valu_1_io_op_srans),
- .io_op_sraqs(valu_1_io_op_sraqs),
- .io_op_dwinit(valu_1_io_op_dwinit),
- .io_op_dwconv(valu_1_io_op_dwconv),
- .io_op_dwconvData(valu_1_io_op_dwconvData),
- .io_op_add_en(valu_1_io_op_add_en),
- .io_op_add_add(valu_1_io_op_add_add),
- .io_op_add_adds(valu_1_io_op_add_adds),
- .io_op_add_addw(valu_1_io_op_add_addw),
- .io_op_add_add3(valu_1_io_op_add_add3),
- .io_op_add_hadd(valu_1_io_op_add_hadd),
- .io_op_cmp_en(valu_1_io_op_cmp_en),
- .io_op_cmp_eq(valu_1_io_op_cmp_eq),
- .io_op_cmp_ne(valu_1_io_op_cmp_ne),
- .io_op_cmp_lt(valu_1_io_op_cmp_lt),
- .io_op_cmp_le(valu_1_io_op_cmp_le),
- .io_op_cmp_gt(valu_1_io_op_cmp_gt),
- .io_op_cmp_ge(valu_1_io_op_cmp_ge),
- .io_op_log_en(valu_1_io_op_log_en),
- .io_op_log_and(valu_1_io_op_log_and),
- .io_op_log_or(valu_1_io_op_log_or),
- .io_op_log_xor(valu_1_io_op_log_xor),
- .io_op_log_not(valu_1_io_op_log_not),
- .io_op_log_rev(valu_1_io_op_log_rev),
- .io_op_log_ror(valu_1_io_op_log_ror),
- .io_op_log_clb(valu_1_io_op_log_clb),
- .io_op_log_clz(valu_1_io_op_log_clz),
- .io_op_log_cpop(valu_1_io_op_log_cpop),
- .io_op_mul0_en(valu_1_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_1_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_1_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_1_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_1_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_1_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_1_io_op_mul0_madd),
- .io_op_mul1_en(valu_1_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_1_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_1_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_1_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_1_io_op_mul1_muls),
- .io_op_padd_en(valu_1_io_op_padd_en),
- .io_op_padd_add(valu_1_io_op_padd_add),
- .io_op_padd_sub(valu_1_io_op_padd_sub),
- .io_op_rsub_en(valu_1_io_op_rsub_en),
- .io_op_rsub_rsub(valu_1_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_1_io_op_shf_en_l),
- .io_op_shf_en_r(valu_1_io_op_shf_en_r),
- .io_op_shf_shl(valu_1_io_op_shf_shl),
- .io_op_shf_shr(valu_1_io_op_shf_shr),
- .io_op_shf_shf(valu_1_io_op_shf_shf),
- .io_op_sub_en(valu_1_io_op_sub_en),
- .io_op_sub_sub(valu_1_io_op_sub_sub),
- .io_op_sub_subs(valu_1_io_op_sub_subs),
- .io_op_sub_subw(valu_1_io_op_sub_subw),
- .io_op_sub_hsub(valu_1_io_op_sub_hsub),
- .io_read_0_data(valu_1_io_read_0_data),
- .io_read_1_data(valu_1_io_read_1_data),
- .io_read_2_data(valu_1_io_read_2_data),
- .io_read_3_data(valu_1_io_read_3_data),
- .io_read_5_data(valu_1_io_read_5_data),
- .io_write_0_data(valu_1_io_write_0_data),
- .io_write_1_data(valu_1_io_write_1_data),
- .io_load_0(valu_1_io_load_0),
- .io_load_1(valu_1_io_load_1)
- );
- VAluIntLane valu_2 ( // @[VAluInt.scala 418:11]
- .clock(valu_2_clock),
- .reset(valu_2_reset),
- .io_in_vdvalid(valu_2_io_in_vdvalid),
- .io_in_vevalid(valu_2_io_in_vevalid),
- .io_in_sz(valu_2_io_in_sz),
- .io_in_negative(valu_2_io_in_negative),
- .io_in_round(valu_2_io_in_round),
- .io_in_signed(valu_2_io_in_signed),
- .io_op_absd(valu_2_io_op_absd),
- .io_op_acc(valu_2_io_op_acc),
- .io_op_dup(valu_2_io_op_dup),
- .io_op_max(valu_2_io_op_max),
- .io_op_min(valu_2_io_op_min),
- .io_op_mv(valu_2_io_op_mv),
- .io_op_mv2(valu_2_io_op_mv2),
- .io_op_mvp(valu_2_io_op_mvp),
- .io_op_srans(valu_2_io_op_srans),
- .io_op_sraqs(valu_2_io_op_sraqs),
- .io_op_dwinit(valu_2_io_op_dwinit),
- .io_op_dwconv(valu_2_io_op_dwconv),
- .io_op_dwconvData(valu_2_io_op_dwconvData),
- .io_op_add_en(valu_2_io_op_add_en),
- .io_op_add_add(valu_2_io_op_add_add),
- .io_op_add_adds(valu_2_io_op_add_adds),
- .io_op_add_addw(valu_2_io_op_add_addw),
- .io_op_add_add3(valu_2_io_op_add_add3),
- .io_op_add_hadd(valu_2_io_op_add_hadd),
- .io_op_cmp_en(valu_2_io_op_cmp_en),
- .io_op_cmp_eq(valu_2_io_op_cmp_eq),
- .io_op_cmp_ne(valu_2_io_op_cmp_ne),
- .io_op_cmp_lt(valu_2_io_op_cmp_lt),
- .io_op_cmp_le(valu_2_io_op_cmp_le),
- .io_op_cmp_gt(valu_2_io_op_cmp_gt),
- .io_op_cmp_ge(valu_2_io_op_cmp_ge),
- .io_op_log_en(valu_2_io_op_log_en),
- .io_op_log_and(valu_2_io_op_log_and),
- .io_op_log_or(valu_2_io_op_log_or),
- .io_op_log_xor(valu_2_io_op_log_xor),
- .io_op_log_not(valu_2_io_op_log_not),
- .io_op_log_rev(valu_2_io_op_log_rev),
- .io_op_log_ror(valu_2_io_op_log_ror),
- .io_op_log_clb(valu_2_io_op_log_clb),
- .io_op_log_clz(valu_2_io_op_log_clz),
- .io_op_log_cpop(valu_2_io_op_log_cpop),
- .io_op_mul0_en(valu_2_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_2_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_2_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_2_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_2_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_2_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_2_io_op_mul0_madd),
- .io_op_mul1_en(valu_2_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_2_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_2_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_2_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_2_io_op_mul1_muls),
- .io_op_padd_en(valu_2_io_op_padd_en),
- .io_op_padd_add(valu_2_io_op_padd_add),
- .io_op_padd_sub(valu_2_io_op_padd_sub),
- .io_op_rsub_en(valu_2_io_op_rsub_en),
- .io_op_rsub_rsub(valu_2_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_2_io_op_shf_en_l),
- .io_op_shf_en_r(valu_2_io_op_shf_en_r),
- .io_op_shf_shl(valu_2_io_op_shf_shl),
- .io_op_shf_shr(valu_2_io_op_shf_shr),
- .io_op_shf_shf(valu_2_io_op_shf_shf),
- .io_op_sub_en(valu_2_io_op_sub_en),
- .io_op_sub_sub(valu_2_io_op_sub_sub),
- .io_op_sub_subs(valu_2_io_op_sub_subs),
- .io_op_sub_subw(valu_2_io_op_sub_subw),
- .io_op_sub_hsub(valu_2_io_op_sub_hsub),
- .io_read_0_data(valu_2_io_read_0_data),
- .io_read_1_data(valu_2_io_read_1_data),
- .io_read_2_data(valu_2_io_read_2_data),
- .io_read_3_data(valu_2_io_read_3_data),
- .io_read_5_data(valu_2_io_read_5_data),
- .io_write_0_data(valu_2_io_write_0_data),
- .io_write_1_data(valu_2_io_write_1_data),
- .io_load_0(valu_2_io_load_0),
- .io_load_1(valu_2_io_load_1)
- );
- VAluIntLane valu_3 ( // @[VAluInt.scala 418:11]
- .clock(valu_3_clock),
- .reset(valu_3_reset),
- .io_in_vdvalid(valu_3_io_in_vdvalid),
- .io_in_vevalid(valu_3_io_in_vevalid),
- .io_in_sz(valu_3_io_in_sz),
- .io_in_negative(valu_3_io_in_negative),
- .io_in_round(valu_3_io_in_round),
- .io_in_signed(valu_3_io_in_signed),
- .io_op_absd(valu_3_io_op_absd),
- .io_op_acc(valu_3_io_op_acc),
- .io_op_dup(valu_3_io_op_dup),
- .io_op_max(valu_3_io_op_max),
- .io_op_min(valu_3_io_op_min),
- .io_op_mv(valu_3_io_op_mv),
- .io_op_mv2(valu_3_io_op_mv2),
- .io_op_mvp(valu_3_io_op_mvp),
- .io_op_srans(valu_3_io_op_srans),
- .io_op_sraqs(valu_3_io_op_sraqs),
- .io_op_dwinit(valu_3_io_op_dwinit),
- .io_op_dwconv(valu_3_io_op_dwconv),
- .io_op_dwconvData(valu_3_io_op_dwconvData),
- .io_op_add_en(valu_3_io_op_add_en),
- .io_op_add_add(valu_3_io_op_add_add),
- .io_op_add_adds(valu_3_io_op_add_adds),
- .io_op_add_addw(valu_3_io_op_add_addw),
- .io_op_add_add3(valu_3_io_op_add_add3),
- .io_op_add_hadd(valu_3_io_op_add_hadd),
- .io_op_cmp_en(valu_3_io_op_cmp_en),
- .io_op_cmp_eq(valu_3_io_op_cmp_eq),
- .io_op_cmp_ne(valu_3_io_op_cmp_ne),
- .io_op_cmp_lt(valu_3_io_op_cmp_lt),
- .io_op_cmp_le(valu_3_io_op_cmp_le),
- .io_op_cmp_gt(valu_3_io_op_cmp_gt),
- .io_op_cmp_ge(valu_3_io_op_cmp_ge),
- .io_op_log_en(valu_3_io_op_log_en),
- .io_op_log_and(valu_3_io_op_log_and),
- .io_op_log_or(valu_3_io_op_log_or),
- .io_op_log_xor(valu_3_io_op_log_xor),
- .io_op_log_not(valu_3_io_op_log_not),
- .io_op_log_rev(valu_3_io_op_log_rev),
- .io_op_log_ror(valu_3_io_op_log_ror),
- .io_op_log_clb(valu_3_io_op_log_clb),
- .io_op_log_clz(valu_3_io_op_log_clz),
- .io_op_log_cpop(valu_3_io_op_log_cpop),
- .io_op_mul0_en(valu_3_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_3_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_3_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_3_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_3_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_3_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_3_io_op_mul0_madd),
- .io_op_mul1_en(valu_3_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_3_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_3_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_3_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_3_io_op_mul1_muls),
- .io_op_padd_en(valu_3_io_op_padd_en),
- .io_op_padd_add(valu_3_io_op_padd_add),
- .io_op_padd_sub(valu_3_io_op_padd_sub),
- .io_op_rsub_en(valu_3_io_op_rsub_en),
- .io_op_rsub_rsub(valu_3_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_3_io_op_shf_en_l),
- .io_op_shf_en_r(valu_3_io_op_shf_en_r),
- .io_op_shf_shl(valu_3_io_op_shf_shl),
- .io_op_shf_shr(valu_3_io_op_shf_shr),
- .io_op_shf_shf(valu_3_io_op_shf_shf),
- .io_op_sub_en(valu_3_io_op_sub_en),
- .io_op_sub_sub(valu_3_io_op_sub_sub),
- .io_op_sub_subs(valu_3_io_op_sub_subs),
- .io_op_sub_subw(valu_3_io_op_sub_subw),
- .io_op_sub_hsub(valu_3_io_op_sub_hsub),
- .io_read_0_data(valu_3_io_read_0_data),
- .io_read_1_data(valu_3_io_read_1_data),
- .io_read_2_data(valu_3_io_read_2_data),
- .io_read_3_data(valu_3_io_read_3_data),
- .io_read_5_data(valu_3_io_read_5_data),
- .io_write_0_data(valu_3_io_write_0_data),
- .io_write_1_data(valu_3_io_write_1_data),
- .io_load_0(valu_3_io_load_0),
- .io_load_1(valu_3_io_load_1)
- );
- VAluIntLane valu_4 ( // @[VAluInt.scala 418:11]
- .clock(valu_4_clock),
- .reset(valu_4_reset),
- .io_in_vdvalid(valu_4_io_in_vdvalid),
- .io_in_vevalid(valu_4_io_in_vevalid),
- .io_in_sz(valu_4_io_in_sz),
- .io_in_negative(valu_4_io_in_negative),
- .io_in_round(valu_4_io_in_round),
- .io_in_signed(valu_4_io_in_signed),
- .io_op_absd(valu_4_io_op_absd),
- .io_op_acc(valu_4_io_op_acc),
- .io_op_dup(valu_4_io_op_dup),
- .io_op_max(valu_4_io_op_max),
- .io_op_min(valu_4_io_op_min),
- .io_op_mv(valu_4_io_op_mv),
- .io_op_mv2(valu_4_io_op_mv2),
- .io_op_mvp(valu_4_io_op_mvp),
- .io_op_srans(valu_4_io_op_srans),
- .io_op_sraqs(valu_4_io_op_sraqs),
- .io_op_dwinit(valu_4_io_op_dwinit),
- .io_op_dwconv(valu_4_io_op_dwconv),
- .io_op_dwconvData(valu_4_io_op_dwconvData),
- .io_op_add_en(valu_4_io_op_add_en),
- .io_op_add_add(valu_4_io_op_add_add),
- .io_op_add_adds(valu_4_io_op_add_adds),
- .io_op_add_addw(valu_4_io_op_add_addw),
- .io_op_add_add3(valu_4_io_op_add_add3),
- .io_op_add_hadd(valu_4_io_op_add_hadd),
- .io_op_cmp_en(valu_4_io_op_cmp_en),
- .io_op_cmp_eq(valu_4_io_op_cmp_eq),
- .io_op_cmp_ne(valu_4_io_op_cmp_ne),
- .io_op_cmp_lt(valu_4_io_op_cmp_lt),
- .io_op_cmp_le(valu_4_io_op_cmp_le),
- .io_op_cmp_gt(valu_4_io_op_cmp_gt),
- .io_op_cmp_ge(valu_4_io_op_cmp_ge),
- .io_op_log_en(valu_4_io_op_log_en),
- .io_op_log_and(valu_4_io_op_log_and),
- .io_op_log_or(valu_4_io_op_log_or),
- .io_op_log_xor(valu_4_io_op_log_xor),
- .io_op_log_not(valu_4_io_op_log_not),
- .io_op_log_rev(valu_4_io_op_log_rev),
- .io_op_log_ror(valu_4_io_op_log_ror),
- .io_op_log_clb(valu_4_io_op_log_clb),
- .io_op_log_clz(valu_4_io_op_log_clz),
- .io_op_log_cpop(valu_4_io_op_log_cpop),
- .io_op_mul0_en(valu_4_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_4_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_4_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_4_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_4_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_4_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_4_io_op_mul0_madd),
- .io_op_mul1_en(valu_4_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_4_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_4_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_4_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_4_io_op_mul1_muls),
- .io_op_padd_en(valu_4_io_op_padd_en),
- .io_op_padd_add(valu_4_io_op_padd_add),
- .io_op_padd_sub(valu_4_io_op_padd_sub),
- .io_op_rsub_en(valu_4_io_op_rsub_en),
- .io_op_rsub_rsub(valu_4_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_4_io_op_shf_en_l),
- .io_op_shf_en_r(valu_4_io_op_shf_en_r),
- .io_op_shf_shl(valu_4_io_op_shf_shl),
- .io_op_shf_shr(valu_4_io_op_shf_shr),
- .io_op_shf_shf(valu_4_io_op_shf_shf),
- .io_op_sub_en(valu_4_io_op_sub_en),
- .io_op_sub_sub(valu_4_io_op_sub_sub),
- .io_op_sub_subs(valu_4_io_op_sub_subs),
- .io_op_sub_subw(valu_4_io_op_sub_subw),
- .io_op_sub_hsub(valu_4_io_op_sub_hsub),
- .io_read_0_data(valu_4_io_read_0_data),
- .io_read_1_data(valu_4_io_read_1_data),
- .io_read_2_data(valu_4_io_read_2_data),
- .io_read_3_data(valu_4_io_read_3_data),
- .io_read_5_data(valu_4_io_read_5_data),
- .io_write_0_data(valu_4_io_write_0_data),
- .io_write_1_data(valu_4_io_write_1_data),
- .io_load_0(valu_4_io_load_0),
- .io_load_1(valu_4_io_load_1)
- );
- VAluIntLane valu_5 ( // @[VAluInt.scala 418:11]
- .clock(valu_5_clock),
- .reset(valu_5_reset),
- .io_in_vdvalid(valu_5_io_in_vdvalid),
- .io_in_vevalid(valu_5_io_in_vevalid),
- .io_in_sz(valu_5_io_in_sz),
- .io_in_negative(valu_5_io_in_negative),
- .io_in_round(valu_5_io_in_round),
- .io_in_signed(valu_5_io_in_signed),
- .io_op_absd(valu_5_io_op_absd),
- .io_op_acc(valu_5_io_op_acc),
- .io_op_dup(valu_5_io_op_dup),
- .io_op_max(valu_5_io_op_max),
- .io_op_min(valu_5_io_op_min),
- .io_op_mv(valu_5_io_op_mv),
- .io_op_mv2(valu_5_io_op_mv2),
- .io_op_mvp(valu_5_io_op_mvp),
- .io_op_srans(valu_5_io_op_srans),
- .io_op_sraqs(valu_5_io_op_sraqs),
- .io_op_dwinit(valu_5_io_op_dwinit),
- .io_op_dwconv(valu_5_io_op_dwconv),
- .io_op_dwconvData(valu_5_io_op_dwconvData),
- .io_op_add_en(valu_5_io_op_add_en),
- .io_op_add_add(valu_5_io_op_add_add),
- .io_op_add_adds(valu_5_io_op_add_adds),
- .io_op_add_addw(valu_5_io_op_add_addw),
- .io_op_add_add3(valu_5_io_op_add_add3),
- .io_op_add_hadd(valu_5_io_op_add_hadd),
- .io_op_cmp_en(valu_5_io_op_cmp_en),
- .io_op_cmp_eq(valu_5_io_op_cmp_eq),
- .io_op_cmp_ne(valu_5_io_op_cmp_ne),
- .io_op_cmp_lt(valu_5_io_op_cmp_lt),
- .io_op_cmp_le(valu_5_io_op_cmp_le),
- .io_op_cmp_gt(valu_5_io_op_cmp_gt),
- .io_op_cmp_ge(valu_5_io_op_cmp_ge),
- .io_op_log_en(valu_5_io_op_log_en),
- .io_op_log_and(valu_5_io_op_log_and),
- .io_op_log_or(valu_5_io_op_log_or),
- .io_op_log_xor(valu_5_io_op_log_xor),
- .io_op_log_not(valu_5_io_op_log_not),
- .io_op_log_rev(valu_5_io_op_log_rev),
- .io_op_log_ror(valu_5_io_op_log_ror),
- .io_op_log_clb(valu_5_io_op_log_clb),
- .io_op_log_clz(valu_5_io_op_log_clz),
- .io_op_log_cpop(valu_5_io_op_log_cpop),
- .io_op_mul0_en(valu_5_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_5_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_5_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_5_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_5_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_5_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_5_io_op_mul0_madd),
- .io_op_mul1_en(valu_5_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_5_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_5_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_5_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_5_io_op_mul1_muls),
- .io_op_padd_en(valu_5_io_op_padd_en),
- .io_op_padd_add(valu_5_io_op_padd_add),
- .io_op_padd_sub(valu_5_io_op_padd_sub),
- .io_op_rsub_en(valu_5_io_op_rsub_en),
- .io_op_rsub_rsub(valu_5_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_5_io_op_shf_en_l),
- .io_op_shf_en_r(valu_5_io_op_shf_en_r),
- .io_op_shf_shl(valu_5_io_op_shf_shl),
- .io_op_shf_shr(valu_5_io_op_shf_shr),
- .io_op_shf_shf(valu_5_io_op_shf_shf),
- .io_op_sub_en(valu_5_io_op_sub_en),
- .io_op_sub_sub(valu_5_io_op_sub_sub),
- .io_op_sub_subs(valu_5_io_op_sub_subs),
- .io_op_sub_subw(valu_5_io_op_sub_subw),
- .io_op_sub_hsub(valu_5_io_op_sub_hsub),
- .io_read_0_data(valu_5_io_read_0_data),
- .io_read_1_data(valu_5_io_read_1_data),
- .io_read_2_data(valu_5_io_read_2_data),
- .io_read_3_data(valu_5_io_read_3_data),
- .io_read_5_data(valu_5_io_read_5_data),
- .io_write_0_data(valu_5_io_write_0_data),
- .io_write_1_data(valu_5_io_write_1_data),
- .io_load_0(valu_5_io_load_0),
- .io_load_1(valu_5_io_load_1)
- );
- VAluIntLane valu_6 ( // @[VAluInt.scala 418:11]
- .clock(valu_6_clock),
- .reset(valu_6_reset),
- .io_in_vdvalid(valu_6_io_in_vdvalid),
- .io_in_vevalid(valu_6_io_in_vevalid),
- .io_in_sz(valu_6_io_in_sz),
- .io_in_negative(valu_6_io_in_negative),
- .io_in_round(valu_6_io_in_round),
- .io_in_signed(valu_6_io_in_signed),
- .io_op_absd(valu_6_io_op_absd),
- .io_op_acc(valu_6_io_op_acc),
- .io_op_dup(valu_6_io_op_dup),
- .io_op_max(valu_6_io_op_max),
- .io_op_min(valu_6_io_op_min),
- .io_op_mv(valu_6_io_op_mv),
- .io_op_mv2(valu_6_io_op_mv2),
- .io_op_mvp(valu_6_io_op_mvp),
- .io_op_srans(valu_6_io_op_srans),
- .io_op_sraqs(valu_6_io_op_sraqs),
- .io_op_dwinit(valu_6_io_op_dwinit),
- .io_op_dwconv(valu_6_io_op_dwconv),
- .io_op_dwconvData(valu_6_io_op_dwconvData),
- .io_op_add_en(valu_6_io_op_add_en),
- .io_op_add_add(valu_6_io_op_add_add),
- .io_op_add_adds(valu_6_io_op_add_adds),
- .io_op_add_addw(valu_6_io_op_add_addw),
- .io_op_add_add3(valu_6_io_op_add_add3),
- .io_op_add_hadd(valu_6_io_op_add_hadd),
- .io_op_cmp_en(valu_6_io_op_cmp_en),
- .io_op_cmp_eq(valu_6_io_op_cmp_eq),
- .io_op_cmp_ne(valu_6_io_op_cmp_ne),
- .io_op_cmp_lt(valu_6_io_op_cmp_lt),
- .io_op_cmp_le(valu_6_io_op_cmp_le),
- .io_op_cmp_gt(valu_6_io_op_cmp_gt),
- .io_op_cmp_ge(valu_6_io_op_cmp_ge),
- .io_op_log_en(valu_6_io_op_log_en),
- .io_op_log_and(valu_6_io_op_log_and),
- .io_op_log_or(valu_6_io_op_log_or),
- .io_op_log_xor(valu_6_io_op_log_xor),
- .io_op_log_not(valu_6_io_op_log_not),
- .io_op_log_rev(valu_6_io_op_log_rev),
- .io_op_log_ror(valu_6_io_op_log_ror),
- .io_op_log_clb(valu_6_io_op_log_clb),
- .io_op_log_clz(valu_6_io_op_log_clz),
- .io_op_log_cpop(valu_6_io_op_log_cpop),
- .io_op_mul0_en(valu_6_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_6_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_6_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_6_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_6_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_6_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_6_io_op_mul0_madd),
- .io_op_mul1_en(valu_6_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_6_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_6_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_6_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_6_io_op_mul1_muls),
- .io_op_padd_en(valu_6_io_op_padd_en),
- .io_op_padd_add(valu_6_io_op_padd_add),
- .io_op_padd_sub(valu_6_io_op_padd_sub),
- .io_op_rsub_en(valu_6_io_op_rsub_en),
- .io_op_rsub_rsub(valu_6_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_6_io_op_shf_en_l),
- .io_op_shf_en_r(valu_6_io_op_shf_en_r),
- .io_op_shf_shl(valu_6_io_op_shf_shl),
- .io_op_shf_shr(valu_6_io_op_shf_shr),
- .io_op_shf_shf(valu_6_io_op_shf_shf),
- .io_op_sub_en(valu_6_io_op_sub_en),
- .io_op_sub_sub(valu_6_io_op_sub_sub),
- .io_op_sub_subs(valu_6_io_op_sub_subs),
- .io_op_sub_subw(valu_6_io_op_sub_subw),
- .io_op_sub_hsub(valu_6_io_op_sub_hsub),
- .io_read_0_data(valu_6_io_read_0_data),
- .io_read_1_data(valu_6_io_read_1_data),
- .io_read_2_data(valu_6_io_read_2_data),
- .io_read_3_data(valu_6_io_read_3_data),
- .io_read_5_data(valu_6_io_read_5_data),
- .io_write_0_data(valu_6_io_write_0_data),
- .io_write_1_data(valu_6_io_write_1_data),
- .io_load_0(valu_6_io_load_0),
- .io_load_1(valu_6_io_load_1)
- );
- VAluIntLane valu_7 ( // @[VAluInt.scala 418:11]
- .clock(valu_7_clock),
- .reset(valu_7_reset),
- .io_in_vdvalid(valu_7_io_in_vdvalid),
- .io_in_vevalid(valu_7_io_in_vevalid),
- .io_in_sz(valu_7_io_in_sz),
- .io_in_negative(valu_7_io_in_negative),
- .io_in_round(valu_7_io_in_round),
- .io_in_signed(valu_7_io_in_signed),
- .io_op_absd(valu_7_io_op_absd),
- .io_op_acc(valu_7_io_op_acc),
- .io_op_dup(valu_7_io_op_dup),
- .io_op_max(valu_7_io_op_max),
- .io_op_min(valu_7_io_op_min),
- .io_op_mv(valu_7_io_op_mv),
- .io_op_mv2(valu_7_io_op_mv2),
- .io_op_mvp(valu_7_io_op_mvp),
- .io_op_srans(valu_7_io_op_srans),
- .io_op_sraqs(valu_7_io_op_sraqs),
- .io_op_dwinit(valu_7_io_op_dwinit),
- .io_op_dwconv(valu_7_io_op_dwconv),
- .io_op_dwconvData(valu_7_io_op_dwconvData),
- .io_op_add_en(valu_7_io_op_add_en),
- .io_op_add_add(valu_7_io_op_add_add),
- .io_op_add_adds(valu_7_io_op_add_adds),
- .io_op_add_addw(valu_7_io_op_add_addw),
- .io_op_add_add3(valu_7_io_op_add_add3),
- .io_op_add_hadd(valu_7_io_op_add_hadd),
- .io_op_cmp_en(valu_7_io_op_cmp_en),
- .io_op_cmp_eq(valu_7_io_op_cmp_eq),
- .io_op_cmp_ne(valu_7_io_op_cmp_ne),
- .io_op_cmp_lt(valu_7_io_op_cmp_lt),
- .io_op_cmp_le(valu_7_io_op_cmp_le),
- .io_op_cmp_gt(valu_7_io_op_cmp_gt),
- .io_op_cmp_ge(valu_7_io_op_cmp_ge),
- .io_op_log_en(valu_7_io_op_log_en),
- .io_op_log_and(valu_7_io_op_log_and),
- .io_op_log_or(valu_7_io_op_log_or),
- .io_op_log_xor(valu_7_io_op_log_xor),
- .io_op_log_not(valu_7_io_op_log_not),
- .io_op_log_rev(valu_7_io_op_log_rev),
- .io_op_log_ror(valu_7_io_op_log_ror),
- .io_op_log_clb(valu_7_io_op_log_clb),
- .io_op_log_clz(valu_7_io_op_log_clz),
- .io_op_log_cpop(valu_7_io_op_log_cpop),
- .io_op_mul0_en(valu_7_io_op_mul0_en),
- .io_op_mul0_dmulh(valu_7_io_op_mul0_dmulh),
- .io_op_mul0_mul(valu_7_io_op_mul0_mul),
- .io_op_mul0_mulh(valu_7_io_op_mul0_mulh),
- .io_op_mul0_muls(valu_7_io_op_mul0_muls),
- .io_op_mul0_mulw(valu_7_io_op_mul0_mulw),
- .io_op_mul0_madd(valu_7_io_op_mul0_madd),
- .io_op_mul1_en(valu_7_io_op_mul1_en),
- .io_op_mul1_dmulh(valu_7_io_op_mul1_dmulh),
- .io_op_mul1_mul(valu_7_io_op_mul1_mul),
- .io_op_mul1_mulh(valu_7_io_op_mul1_mulh),
- .io_op_mul1_muls(valu_7_io_op_mul1_muls),
- .io_op_padd_en(valu_7_io_op_padd_en),
- .io_op_padd_add(valu_7_io_op_padd_add),
- .io_op_padd_sub(valu_7_io_op_padd_sub),
- .io_op_rsub_en(valu_7_io_op_rsub_en),
- .io_op_rsub_rsub(valu_7_io_op_rsub_rsub),
- .io_op_shf_en_l(valu_7_io_op_shf_en_l),
- .io_op_shf_en_r(valu_7_io_op_shf_en_r),
- .io_op_shf_shl(valu_7_io_op_shf_shl),
- .io_op_shf_shr(valu_7_io_op_shf_shr),
- .io_op_shf_shf(valu_7_io_op_shf_shf),
- .io_op_sub_en(valu_7_io_op_sub_en),
- .io_op_sub_sub(valu_7_io_op_sub_sub),
- .io_op_sub_subs(valu_7_io_op_sub_subs),
- .io_op_sub_subw(valu_7_io_op_sub_subw),
- .io_op_sub_hsub(valu_7_io_op_sub_hsub),
- .io_read_0_data(valu_7_io_read_0_data),
- .io_read_1_data(valu_7_io_read_1_data),
- .io_read_2_data(valu_7_io_read_2_data),
- .io_read_3_data(valu_7_io_read_3_data),
- .io_read_5_data(valu_7_io_read_5_data),
- .io_write_0_data(valu_7_io_write_0_data),
- .io_write_1_data(valu_7_io_write_1_data),
- .io_load_0(valu_7_io_load_0),
- .io_load_1(valu_7_io_load_1)
- );
- assign io_write_0_valid = vdvalid1; // @[VAluInt.scala 755:21]
- assign io_write_0_addr = vdaddr1_addr; // @[VAluInt.scala 756:20]
- assign io_write_0_data = {io_write_0_data_hi,io_write_0_data_lo}; // @[VAluInt.scala 757:30]
- assign io_write_1_valid = vevalid1; // @[VAluInt.scala 759:21]
- assign io_write_1_addr = veaddr1_addr; // @[VAluInt.scala 760:20]
- assign io_write_1_data = {io_write_1_data_hi,io_write_1_data_lo}; // @[VAluInt.scala 761:30]
- assign io_whint_0_valid = vdvalid0 & _vdvalid1_T; // @[VAluInt.scala 763:33]
- assign io_whint_0_addr = vdaddr0_addr; // @[VAluInt.scala 764:20]
- assign io_whint_1_valid = vevalid0 & _vdvalid1_T; // @[VAluInt.scala 766:33]
- assign io_whint_1_addr = veaddr0_addr; // @[VAluInt.scala 767:20]
- assign valu_0_clock = clock;
- assign valu_0_reset = reset;
- assign valu_0_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_0_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_0_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_0_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_0_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_0_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_0_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_0_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_0_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_0_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_0_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_0_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_0_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_0_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_0_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_0_io_op_sraqs = 1'h0; // @[VAluInt.scala 453:25]
- assign valu_0_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_0_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_0_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_0_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_0_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_0_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_0_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_0_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_0_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_0_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_0_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_0_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_0_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_0_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_0_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_0_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_0_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_0_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_0_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_0_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_0_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_0_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_0_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_0_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_0_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_0_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_0_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_0_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_0_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_0_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_0_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_0_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_0_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_0_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_0_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_0_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_0_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_0_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_0_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_0_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_0_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_0_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_0_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_0_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_0_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_0_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_0_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_0_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_0_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_0_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_0_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_0_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_0_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_0_io_read_0_data = io_read_0_data[31:0]; // @[VAluInt.scala 430:49]
- assign valu_0_io_read_1_data = io_read_1_data[31:0]; // @[VAluInt.scala 430:49]
- assign valu_0_io_read_2_data = io_read_2_data[31:0]; // @[VAluInt.scala 430:49]
- assign valu_0_io_read_3_data = io_read_3_data[31:0]; // @[VAluInt.scala 430:49]
- assign valu_0_io_read_5_data = io_read_5_data[31:0]; // @[VAluInt.scala 430:49]
- assign valu_0_io_load_0 = load_0[31:0]; // @[VAluInt.scala 433:36]
- assign valu_0_io_load_1 = load_1[31:0]; // @[VAluInt.scala 433:36]
- assign valu_1_clock = clock;
- assign valu_1_reset = reset;
- assign valu_1_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_1_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_1_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_1_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_1_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_1_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_1_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_1_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_1_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_1_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_1_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_1_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_1_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_1_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_1_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_1_io_op_sraqs = 1'h0; // @[VAluInt.scala 453:25]
- assign valu_1_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_1_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_1_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_1_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_1_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_1_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_1_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_1_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_1_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_1_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_1_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_1_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_1_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_1_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_1_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_1_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_1_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_1_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_1_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_1_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_1_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_1_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_1_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_1_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_1_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_1_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_1_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_1_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_1_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_1_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_1_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_1_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_1_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_1_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_1_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_1_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_1_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_1_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_1_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_1_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_1_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_1_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_1_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_1_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_1_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_1_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_1_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_1_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_1_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_1_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_1_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_1_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_1_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_1_io_read_0_data = io_read_0_data[63:32]; // @[VAluInt.scala 430:49]
- assign valu_1_io_read_1_data = io_read_1_data[63:32]; // @[VAluInt.scala 430:49]
- assign valu_1_io_read_2_data = io_read_2_data[63:32]; // @[VAluInt.scala 430:49]
- assign valu_1_io_read_3_data = io_read_3_data[63:32]; // @[VAluInt.scala 430:49]
- assign valu_1_io_read_5_data = io_read_5_data[63:32]; // @[VAluInt.scala 430:49]
- assign valu_1_io_load_0 = load_0[63:32]; // @[VAluInt.scala 433:36]
- assign valu_1_io_load_1 = load_1[63:32]; // @[VAluInt.scala 433:36]
- assign valu_2_clock = clock;
- assign valu_2_reset = reset;
- assign valu_2_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_2_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_2_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_2_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_2_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_2_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_2_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_2_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_2_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_2_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_2_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_2_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_2_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_2_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_2_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_2_io_op_sraqs = 1'h0; // @[VAluInt.scala 453:25]
- assign valu_2_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_2_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_2_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_2_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_2_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_2_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_2_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_2_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_2_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_2_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_2_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_2_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_2_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_2_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_2_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_2_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_2_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_2_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_2_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_2_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_2_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_2_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_2_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_2_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_2_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_2_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_2_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_2_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_2_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_2_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_2_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_2_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_2_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_2_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_2_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_2_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_2_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_2_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_2_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_2_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_2_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_2_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_2_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_2_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_2_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_2_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_2_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_2_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_2_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_2_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_2_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_2_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_2_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_2_io_read_0_data = io_read_0_data[95:64]; // @[VAluInt.scala 430:49]
- assign valu_2_io_read_1_data = io_read_1_data[95:64]; // @[VAluInt.scala 430:49]
- assign valu_2_io_read_2_data = io_read_2_data[95:64]; // @[VAluInt.scala 430:49]
- assign valu_2_io_read_3_data = io_read_3_data[95:64]; // @[VAluInt.scala 430:49]
- assign valu_2_io_read_5_data = io_read_5_data[95:64]; // @[VAluInt.scala 430:49]
- assign valu_2_io_load_0 = load_0[95:64]; // @[VAluInt.scala 433:36]
- assign valu_2_io_load_1 = load_1[95:64]; // @[VAluInt.scala 433:36]
- assign valu_3_clock = clock;
- assign valu_3_reset = reset;
- assign valu_3_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_3_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_3_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_3_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_3_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_3_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_3_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_3_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_3_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_3_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_3_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_3_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_3_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_3_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_3_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_3_io_op_sraqs = 1'h0; // @[VAluInt.scala 453:25]
- assign valu_3_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_3_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_3_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_3_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_3_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_3_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_3_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_3_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_3_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_3_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_3_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_3_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_3_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_3_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_3_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_3_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_3_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_3_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_3_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_3_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_3_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_3_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_3_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_3_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_3_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_3_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_3_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_3_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_3_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_3_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_3_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_3_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_3_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_3_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_3_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_3_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_3_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_3_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_3_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_3_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_3_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_3_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_3_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_3_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_3_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_3_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_3_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_3_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_3_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_3_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_3_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_3_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_3_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_3_io_read_0_data = io_read_0_data[127:96]; // @[VAluInt.scala 430:49]
- assign valu_3_io_read_1_data = io_read_1_data[127:96]; // @[VAluInt.scala 430:49]
- assign valu_3_io_read_2_data = io_read_2_data[127:96]; // @[VAluInt.scala 430:49]
- assign valu_3_io_read_3_data = io_read_3_data[127:96]; // @[VAluInt.scala 430:49]
- assign valu_3_io_read_5_data = io_read_5_data[127:96]; // @[VAluInt.scala 430:49]
- assign valu_3_io_load_0 = load_0[127:96]; // @[VAluInt.scala 433:36]
- assign valu_3_io_load_1 = load_1[127:96]; // @[VAluInt.scala 433:36]
- assign valu_4_clock = clock;
- assign valu_4_reset = reset;
- assign valu_4_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_4_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_4_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_4_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_4_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_4_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_4_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_4_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_4_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_4_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_4_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_4_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_4_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_4_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_4_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_4_io_op_sraqs = 1'h0; // @[VAluInt.scala 453:25]
- assign valu_4_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_4_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_4_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_4_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_4_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_4_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_4_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_4_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_4_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_4_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_4_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_4_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_4_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_4_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_4_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_4_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_4_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_4_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_4_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_4_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_4_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_4_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_4_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_4_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_4_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_4_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_4_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_4_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_4_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_4_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_4_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_4_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_4_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_4_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_4_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_4_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_4_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_4_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_4_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_4_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_4_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_4_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_4_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_4_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_4_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_4_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_4_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_4_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_4_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_4_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_4_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_4_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_4_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_4_io_read_0_data = io_read_0_data[159:128]; // @[VAluInt.scala 430:49]
- assign valu_4_io_read_1_data = io_read_1_data[159:128]; // @[VAluInt.scala 430:49]
- assign valu_4_io_read_2_data = io_read_2_data[159:128]; // @[VAluInt.scala 430:49]
- assign valu_4_io_read_3_data = io_read_3_data[159:128]; // @[VAluInt.scala 430:49]
- assign valu_4_io_read_5_data = io_read_5_data[159:128]; // @[VAluInt.scala 430:49]
- assign valu_4_io_load_0 = load_0[159:128]; // @[VAluInt.scala 433:36]
- assign valu_4_io_load_1 = load_1[159:128]; // @[VAluInt.scala 433:36]
- assign valu_5_clock = clock;
- assign valu_5_reset = reset;
- assign valu_5_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_5_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_5_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_5_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_5_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_5_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_5_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_5_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_5_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_5_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_5_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_5_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_5_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_5_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_5_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_5_io_op_sraqs = 1'h0; // @[VAluInt.scala 453:25]
- assign valu_5_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_5_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_5_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_5_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_5_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_5_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_5_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_5_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_5_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_5_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_5_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_5_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_5_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_5_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_5_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_5_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_5_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_5_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_5_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_5_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_5_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_5_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_5_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_5_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_5_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_5_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_5_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_5_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_5_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_5_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_5_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_5_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_5_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_5_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_5_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_5_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_5_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_5_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_5_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_5_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_5_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_5_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_5_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_5_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_5_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_5_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_5_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_5_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_5_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_5_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_5_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_5_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_5_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_5_io_read_0_data = io_read_0_data[191:160]; // @[VAluInt.scala 430:49]
- assign valu_5_io_read_1_data = io_read_1_data[191:160]; // @[VAluInt.scala 430:49]
- assign valu_5_io_read_2_data = io_read_2_data[191:160]; // @[VAluInt.scala 430:49]
- assign valu_5_io_read_3_data = io_read_3_data[191:160]; // @[VAluInt.scala 430:49]
- assign valu_5_io_read_5_data = io_read_5_data[191:160]; // @[VAluInt.scala 430:49]
- assign valu_5_io_load_0 = load_0[191:160]; // @[VAluInt.scala 433:36]
- assign valu_5_io_load_1 = load_1[191:160]; // @[VAluInt.scala 433:36]
- assign valu_6_clock = clock;
- assign valu_6_reset = reset;
- assign valu_6_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_6_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_6_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_6_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_6_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_6_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_6_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_6_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_6_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_6_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_6_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_6_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_6_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_6_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_6_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_6_io_op_sraqs = 1'h0; // @[VAluInt.scala 453:25]
- assign valu_6_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_6_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_6_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_6_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_6_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_6_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_6_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_6_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_6_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_6_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_6_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_6_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_6_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_6_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_6_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_6_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_6_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_6_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_6_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_6_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_6_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_6_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_6_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_6_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_6_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_6_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_6_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_6_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_6_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_6_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_6_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_6_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_6_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_6_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_6_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_6_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_6_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_6_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_6_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_6_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_6_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_6_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_6_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_6_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_6_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_6_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_6_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_6_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_6_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_6_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_6_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_6_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_6_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_6_io_read_0_data = io_read_0_data[223:192]; // @[VAluInt.scala 430:49]
- assign valu_6_io_read_1_data = io_read_1_data[223:192]; // @[VAluInt.scala 430:49]
- assign valu_6_io_read_2_data = io_read_2_data[223:192]; // @[VAluInt.scala 430:49]
- assign valu_6_io_read_3_data = io_read_3_data[223:192]; // @[VAluInt.scala 430:49]
- assign valu_6_io_read_5_data = io_read_5_data[223:192]; // @[VAluInt.scala 430:49]
- assign valu_6_io_load_0 = load_0[223:192]; // @[VAluInt.scala 433:36]
- assign valu_6_io_load_1 = load_1[223:192]; // @[VAluInt.scala 433:36]
- assign valu_7_clock = clock;
- assign valu_7_reset = reset;
- assign valu_7_io_in_vdvalid = vdvalid0; // @[VAluInt.scala 426:27]
- assign valu_7_io_in_vevalid = vevalid0; // @[VAluInt.scala 427:27]
- assign valu_7_io_in_sz = sz; // @[VAluInt.scala 428:22]
- assign valu_7_io_in_negative = negative; // @[VAluInt.scala 438:28]
- assign valu_7_io_in_round = round; // @[VAluInt.scala 439:28]
- assign valu_7_io_in_signed = signed_; // @[VAluInt.scala 440:28]
- assign valu_7_io_op_absd = absd; // @[VAluInt.scala 444:24]
- assign valu_7_io_op_acc = acc; // @[VAluInt.scala 445:24]
- assign valu_7_io_op_dup = dup; // @[VAluInt.scala 446:24]
- assign valu_7_io_op_max = max; // @[VAluInt.scala 447:24]
- assign valu_7_io_op_min = min; // @[VAluInt.scala 448:24]
- assign valu_7_io_op_mv = mv; // @[VAluInt.scala 449:24]
- assign valu_7_io_op_mv2 = mv2; // @[VAluInt.scala 450:24]
- assign valu_7_io_op_mvp = mvp; // @[VAluInt.scala 451:24]
- assign valu_7_io_op_srans = srans; // @[VAluInt.scala 452:25]
- assign valu_7_io_op_sraqs = 1'h0; // @[VAluInt.scala 453:25]
- assign valu_7_io_op_dwinit = dwinit; // @[VAluInt.scala 455:26]
- assign valu_7_io_op_dwconv = dwconv; // @[VAluInt.scala 456:26]
- assign valu_7_io_op_dwconvData = dwconvData; // @[VAluInt.scala 457:30]
- assign valu_7_io_op_add_en = add; // @[VAluInt.scala 459:26]
- assign valu_7_io_op_add_add = add_add; // @[VAluInt.scala 460:28]
- assign valu_7_io_op_add_adds = add_adds; // @[VAluInt.scala 461:28]
- assign valu_7_io_op_add_addw = add_addw; // @[VAluInt.scala 462:28]
- assign valu_7_io_op_add_add3 = add_add3; // @[VAluInt.scala 463:28]
- assign valu_7_io_op_add_hadd = add_hadd; // @[VAluInt.scala 464:28]
- assign valu_7_io_op_cmp_en = cmp; // @[VAluInt.scala 466:26]
- assign valu_7_io_op_cmp_eq = cmp_eq; // @[VAluInt.scala 467:26]
- assign valu_7_io_op_cmp_ne = cmp_ne; // @[VAluInt.scala 468:26]
- assign valu_7_io_op_cmp_lt = cmp_lt; // @[VAluInt.scala 469:26]
- assign valu_7_io_op_cmp_le = cmp_le; // @[VAluInt.scala 470:26]
- assign valu_7_io_op_cmp_gt = cmp_gt; // @[VAluInt.scala 471:26]
- assign valu_7_io_op_cmp_ge = cmp_ge; // @[VAluInt.scala 472:26]
- assign valu_7_io_op_log_en = log; // @[VAluInt.scala 474:26]
- assign valu_7_io_op_log_and = log_and; // @[VAluInt.scala 475:28]
- assign valu_7_io_op_log_or = log_or; // @[VAluInt.scala 476:28]
- assign valu_7_io_op_log_xor = log_xor; // @[VAluInt.scala 477:28]
- assign valu_7_io_op_log_not = log_not; // @[VAluInt.scala 478:28]
- assign valu_7_io_op_log_rev = log_rev; // @[VAluInt.scala 479:28]
- assign valu_7_io_op_log_ror = log_ror; // @[VAluInt.scala 480:28]
- assign valu_7_io_op_log_clb = log_clb; // @[VAluInt.scala 481:28]
- assign valu_7_io_op_log_clz = log_clz; // @[VAluInt.scala 482:28]
- assign valu_7_io_op_log_cpop = log_cpop; // @[VAluInt.scala 483:28]
- assign valu_7_io_op_mul0_en = mul0; // @[VAluInt.scala 485:27]
- assign valu_7_io_op_mul0_dmulh = mul0_dmulh; // @[VAluInt.scala 486:30]
- assign valu_7_io_op_mul0_mul = mul0_mul; // @[VAluInt.scala 487:30]
- assign valu_7_io_op_mul0_mulh = mul0_mulh; // @[VAluInt.scala 488:30]
- assign valu_7_io_op_mul0_muls = mul0_muls; // @[VAluInt.scala 489:30]
- assign valu_7_io_op_mul0_mulw = mul0_mulw; // @[VAluInt.scala 490:30]
- assign valu_7_io_op_mul0_madd = mul0_madd; // @[VAluInt.scala 491:30]
- assign valu_7_io_op_mul1_en = mul1; // @[VAluInt.scala 493:27]
- assign valu_7_io_op_mul1_dmulh = mul1_dmulh; // @[VAluInt.scala 494:30]
- assign valu_7_io_op_mul1_mul = mul1_mul; // @[VAluInt.scala 495:30]
- assign valu_7_io_op_mul1_mulh = mul1_mulh; // @[VAluInt.scala 496:30]
- assign valu_7_io_op_mul1_muls = mul1_muls; // @[VAluInt.scala 497:30]
- assign valu_7_io_op_padd_en = padd; // @[VAluInt.scala 499:27]
- assign valu_7_io_op_padd_add = padd_add; // @[VAluInt.scala 500:28]
- assign valu_7_io_op_padd_sub = padd_sub; // @[VAluInt.scala 501:28]
- assign valu_7_io_op_rsub_en = rsub; // @[VAluInt.scala 503:27]
- assign valu_7_io_op_rsub_rsub = rsub_rsub; // @[VAluInt.scala 504:29]
- assign valu_7_io_op_shf_en_l = shf_l; // @[VAluInt.scala 506:28]
- assign valu_7_io_op_shf_en_r = shf_r; // @[VAluInt.scala 507:28]
- assign valu_7_io_op_shf_shl = shf_shl; // @[VAluInt.scala 508:27]
- assign valu_7_io_op_shf_shr = shf_shr; // @[VAluInt.scala 509:27]
- assign valu_7_io_op_shf_shf = shf_shf; // @[VAluInt.scala 510:27]
- assign valu_7_io_op_sub_en = sub; // @[VAluInt.scala 512:26]
- assign valu_7_io_op_sub_sub = sub_sub; // @[VAluInt.scala 513:28]
- assign valu_7_io_op_sub_subs = sub_subs; // @[VAluInt.scala 514:28]
- assign valu_7_io_op_sub_subw = sub_subw; // @[VAluInt.scala 515:28]
- assign valu_7_io_op_sub_hsub = sub_hsub; // @[VAluInt.scala 516:28]
- assign valu_7_io_read_0_data = io_read_0_data[255:224]; // @[VAluInt.scala 430:49]
- assign valu_7_io_read_1_data = io_read_1_data[255:224]; // @[VAluInt.scala 430:49]
- assign valu_7_io_read_2_data = io_read_2_data[255:224]; // @[VAluInt.scala 430:49]
- assign valu_7_io_read_3_data = io_read_3_data[255:224]; // @[VAluInt.scala 430:49]
- assign valu_7_io_read_5_data = io_read_5_data[255:224]; // @[VAluInt.scala 430:49]
- assign valu_7_io_load_0 = load_0[255:224]; // @[VAluInt.scala 433:36]
- assign valu_7_io_load_1 = load_1[255:224]; // @[VAluInt.scala 433:36]
- always @(posedge clock) begin
- if (io_in_valid) begin // @[VAluInt.scala 211:22]
- vdaddr0_addr <= io_in_vd_addr; // @[VAluInt.scala 212:13]
- end
- if (vdvalid0) begin // @[VAluInt.scala 216:19]
- vdaddr1_addr <= vdaddr0_addr; // @[VAluInt.scala 217:13]
- end
- if (io_in_valid) begin // @[VAluInt.scala 211:22]
- veaddr0_addr <= io_in_ve_addr; // @[VAluInt.scala 213:13]
- end
- if (vevalid0) begin // @[VAluInt.scala 220:19]
- veaddr1_addr <= veaddr0_addr; // @[VAluInt.scala 221:13]
- end
- if (io_in_valid) begin // @[VAluInt.scala 230:22]
- negative <= e_negative; // @[VAluInt.scala 231:14]
- end
- if (io_in_valid) begin // @[VAluInt.scala 230:22]
- round <= e_round; // @[VAluInt.scala 232:14]
- end
- if (io_in_valid) begin // @[VAluInt.scala 230:22]
- signed_ <= e_signed; // @[VAluInt.scala 233:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- absd <= io_in_valid & e_absd; // @[VAluInt.scala 328:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- acc <= io_in_valid & e_acc; // @[VAluInt.scala 329:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- dup <= io_in_valid & e_dup; // @[VAluInt.scala 330:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- max <= io_in_valid & e_max; // @[VAluInt.scala 331:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- min <= io_in_valid & e_min; // @[VAluInt.scala 332:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- srans <= io_in_valid & e_srans; // @[VAluInt.scala 333:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- slidevn <= io_in_valid & e_slidevn; // @[VAluInt.scala 336:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- slidevp <= io_in_valid & e_slidevp; // @[VAluInt.scala 337:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- slidehn2 <= io_in_valid & _e_slidevn_T_3; // @[VAluInt.scala 338:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- slidehp2 <= io_in_valid & _e_slidevp_T_3; // @[VAluInt.scala 339:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- sel <= io_in_valid & e_sel; // @[VAluInt.scala 340:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- evn <= io_in_valid & e_evn; // @[VAluInt.scala 341:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- odd <= io_in_valid & e_odd; // @[VAluInt.scala 342:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- zip <= io_in_valid & e_zip; // @[VAluInt.scala 343:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- dwinit <= io_in_valid & e_dwinit; // @[VAluInt.scala 345:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- dwconv <= io_in_valid & e_dwconv; // @[VAluInt.scala 346:14]
- end
- dwconvData <= dwconv; // @[VAluInt.scala 413:14]
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- add <= io_in_valid & e_add; // @[VAluInt.scala 348:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- add_add <= io_in_valid & e_add_add; // @[VAluInt.scala 349:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- add_adds <= io_in_valid & e_add_adds; // @[VAluInt.scala 350:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- add_addw <= io_in_valid & e_add_addw; // @[VAluInt.scala 351:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- add_add3 <= io_in_valid & e_add_add3; // @[VAluInt.scala 352:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- add_hadd <= io_in_valid & e_add_hadd; // @[VAluInt.scala 353:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- padd <= io_in_valid & e_padd; // @[VAluInt.scala 355:10]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- padd_add <= io_in_valid & e_padd_add; // @[VAluInt.scala 356:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- padd_sub <= io_in_valid & e_padd_sub; // @[VAluInt.scala 357:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- rsub <= io_in_valid & (e_rsub | e_absd); // @[VAluInt.scala 396:10]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- rsub_rsub <= io_in_valid & e_rsub; // @[VAluInt.scala 397:15]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- sub <= io_in_valid & (e_sub | e_absd); // @[VAluInt.scala 405:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- sub_sub <= io_in_valid & e_sub_sub; // @[VAluInt.scala 406:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- sub_subs <= io_in_valid & e_sub_subs; // @[VAluInt.scala 407:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- sub_subw <= io_in_valid & e_sub_subw; // @[VAluInt.scala 408:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- sub_hsub <= io_in_valid & e_sub_hsub; // @[VAluInt.scala 409:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp <= io_in_valid & (e_cmp | e_absd | e_max | e_min); // @[VAluInt.scala 359:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp_eq <= io_in_valid & e_cmp_eq; // @[VAluInt.scala 360:12]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp_ne <= io_in_valid & e_cmp_ne; // @[VAluInt.scala 361:12]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp_lt <= io_in_valid & e_cmp_lt; // @[VAluInt.scala 362:12]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp_le <= io_in_valid & e_cmp_le; // @[VAluInt.scala 363:12]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp_gt <= io_in_valid & e_cmp_gt; // @[VAluInt.scala 364:12]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- cmp_ge <= io_in_valid & e_cmp_ge; // @[VAluInt.scala 365:12]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log <= io_in_valid & e_log; // @[VAluInt.scala 367:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_and <= io_in_valid & e_log_and; // @[VAluInt.scala 368:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_or <= io_in_valid & e_log_or; // @[VAluInt.scala 369:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_xor <= io_in_valid & e_log_xor; // @[VAluInt.scala 370:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_not <= io_in_valid & e_log_not; // @[VAluInt.scala 371:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_rev <= io_in_valid & e_log_rev; // @[VAluInt.scala 372:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_ror <= io_in_valid & e_log_ror; // @[VAluInt.scala 373:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_clb <= io_in_valid & e_log_clb; // @[VAluInt.scala 374:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_clz <= io_in_valid & e_log_clz; // @[VAluInt.scala 375:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- log_cpop <= io_in_valid & e_log_cpop; // @[VAluInt.scala 376:14]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0 <= io_in_valid & e_mul0; // @[VAluInt.scala 378:10]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0_dmulh <= io_in_valid & e_mul0_dmulh; // @[VAluInt.scala 379:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0_mul <= io_in_valid & e_mul0_mul; // @[VAluInt.scala 380:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0_mulh <= io_in_valid & e_mul0_mulh; // @[VAluInt.scala 381:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0_muls <= io_in_valid & e_mul0_muls; // @[VAluInt.scala 382:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0_mulw <= io_in_valid & e_mul0_mulw; // @[VAluInt.scala 383:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul0_madd <= io_in_valid & e_mul0_madd; // @[VAluInt.scala 384:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul1 <= io_in_valid & e_mul1; // @[VAluInt.scala 386:10]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul1_dmulh <= io_in_valid & _e_mul0_dmulh_T_1; // @[VAluInt.scala 387:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul1_mul <= io_in_valid & _e_mul0_mul_T_1; // @[VAluInt.scala 388:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul1_mulh <= io_in_valid & _e_mul0_mulh_T_1; // @[VAluInt.scala 389:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mul1_muls <= io_in_valid & _e_mul0_muls_T_1; // @[VAluInt.scala 390:16]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mv <= io_in_valid & e_mv; // @[VAluInt.scala 392:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mv2 <= io_in_valid & e_mv2; // @[VAluInt.scala 393:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- mvp <= io_in_valid & e_mvp; // @[VAluInt.scala 394:9]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- shf_l <= io_in_valid & e_shf_l; // @[VAluInt.scala 399:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- shf_r <= io_in_valid & e_shf_r; // @[VAluInt.scala 400:11]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- shf_shl <= io_in_valid & e_shf_shl; // @[VAluInt.scala 401:13]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- shf_shr <= io_in_valid & e_shf_shr; // @[VAluInt.scala 402:13]
- end
- if (io_in_valid | validClr) begin // @[VAluInt.scala 325:34]
- shf_shf <= io_in_valid & e_shf_shf; // @[VAluInt.scala 403:13]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~io_in_valid | _T_6[1:0] <= 2'h1)) begin
- $fatal; // @[VAluInt.scala 63:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~io_in_valid | _T_6[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:63 assert(!io.in.valid || PopCount(io.in.sz) <= 1.U)\n"); // @[VAluInt.scala 63:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_11 & ~(_T_28 <= 3'h1)) begin
- $fatal; // @[VAluInt.scala 115:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_11 & ~(_T_28 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:115 assert(PopCount(Cat(e_cmp_eq, e_cmp_ne, e_cmp_lt, e_cmp_le, e_cmp_gt, e_cmp_ge)) <= 1.U)\n"
- ); // @[VAluInt.scala 115:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_11 & ~(_T_58 <= 4'h1)) begin
- $fatal; // @[VAluInt.scala 127:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_11 & ~(_T_58 <= 4'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAluInt.scala:127 assert(PopCount(Cat(e_log_and, e_log_or, e_log_xor, e_log_not, e_log_rev, e_log_ror, e_log_clb, e_log_clz, e_log_cpop)) <= 1.U)\n"
- ); // @[VAluInt.scala 127:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_dmulh_T_1 & ~e_mul0_dmulh))) begin
- $fatal; // @[VAluInt.scala 167:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_dmulh_T_1 & ~e_mul0_dmulh))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:167 assert(!(e_mul1_dmulh && !e_mul0_dmulh))\n"); // @[VAluInt.scala 167:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_mul_T_1 & ~e_mul0_mul))) begin
- $fatal; // @[VAluInt.scala 168:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_mul_T_1 & ~e_mul0_mul))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:168 assert(!(e_mul1_mul && !e_mul0_mul))\n"); // @[VAluInt.scala 168:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_mulh_T_1 & ~e_mul0_mulh))) begin
- $fatal; // @[VAluInt.scala 169:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_mulh_T_1 & ~e_mul0_mulh))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:169 assert(!(e_mul1_mulh && !e_mul0_mulh))\n"); // @[VAluInt.scala 169:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_muls_T_1 & ~e_mul0_muls))) begin
- $fatal; // @[VAluInt.scala 170:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_11 & ~(~(_e_mul0_muls_T_1 & ~e_mul0_muls))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAluInt.scala:170 assert(!(e_mul1_muls && !e_mul0_muls))\n"); // @[VAluInt.scala 170:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 187:22]
- vdvalid0 <= 1'h0; // @[VAluInt.scala 192:14]
- end else if (io_in_valid) begin // @[VAluInt.scala 198:38]
- vdvalid0 <= nxt_vdvalid; // @[VAluInt.scala 199:14]
- end else if (vdvalid0 | vevalid0) begin // @[VAluInt.scala 174:25]
- vdvalid0 <= 1'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 208:24]
- vdvalid1 <= 1'h0;
- end else begin
- vdvalid1 <= vdvalid0 & ~wmask;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 187:22]
- vevalid0 <= 1'h0; // @[VAluInt.scala 193:14]
- end else if (io_in_valid) begin // @[VAluInt.scala 198:38]
- vevalid0 <= nxt_vevalid; // @[VAluInt.scala 200:14]
- end else if (vdvalid0 | vevalid0) begin // @[VAluInt.scala 176:25]
- vevalid0 <= 1'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 209:24]
- vevalid1 <= 1'h0;
- end else begin
- vevalid1 <= vevalid0 & _vdvalid1_T;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 187:22]
- wmask <= 1'h0; // @[VAluInt.scala 194:11]
- end else if (io_in_valid) begin // @[VAluInt.scala 198:38]
- wmask <= _e_dwconv_T_1; // @[VAluInt.scala 201:11]
- end else if (vdvalid0 | vevalid0) begin // @[VAluInt.scala 178:22]
- wmask <= 1'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 187:22]
- sz <= 3'h0; // @[Library.scala 32:8 VAluInt.scala 195:48]
- end else if (io_in_valid) begin // @[VAluInt.scala 198:38]
- if (_sz_T) begin // @[VAluInt.scala 202:8]
- if (nxt_widen) begin
- sz <= _sz_T_1;
- end else begin
- sz <= io_in_sz;
- end
- end else begin
- sz <= 3'h0;
- end
- end else if (vdvalid0 | vevalid0) begin // @[VAluInt.scala 183:19]
- sz <= 3'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 187:22]
- f2 <= 3'h0; // @[VAluInt.scala 196:8]
- end else if (io_in_valid) begin // @[VAluInt.scala 198:38]
- f2 <= io_in_f2; // @[VAluInt.scala 203:8]
- end else if (vdvalid0 | vevalid0) begin // @[VAluInt.scala 184:19]
- f2 <= 3'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 187:22]
- sv <= 32'h0; // @[VAluInt.scala 197:8]
- end else if (io_in_valid) begin // @[VAluInt.scala 198:38]
- sv <= io_in_sv_data; // @[VAluInt.scala 204:8]
- end else if (vdvalid0 | vevalid0) begin // @[VAluInt.scala 185:19]
- sv <= 32'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAluInt.scala 322:25]
- validClr <= 1'h0; // @[VAluInt.scala 322:25]
- end else begin
- validClr <= io_in_valid; // @[VAluInt.scala 323:12]
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- vdvalid0 = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- vdvalid1 = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- vevalid0 = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- vevalid1 = _RAND_3[0:0];
- _RAND_4 = {1{`RANDOM}};
- wmask = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- vdaddr0_addr = _RAND_5[5:0];
- _RAND_6 = {1{`RANDOM}};
- vdaddr1_addr = _RAND_6[5:0];
- _RAND_7 = {1{`RANDOM}};
- veaddr0_addr = _RAND_7[5:0];
- _RAND_8 = {1{`RANDOM}};
- veaddr1_addr = _RAND_8[5:0];
- _RAND_9 = {1{`RANDOM}};
- sz = _RAND_9[2:0];
- _RAND_10 = {1{`RANDOM}};
- f2 = _RAND_10[2:0];
- _RAND_11 = {1{`RANDOM}};
- sv = _RAND_11[31:0];
- _RAND_12 = {1{`RANDOM}};
- negative = _RAND_12[0:0];
- _RAND_13 = {1{`RANDOM}};
- round = _RAND_13[0:0];
- _RAND_14 = {1{`RANDOM}};
- signed_ = _RAND_14[0:0];
- _RAND_15 = {1{`RANDOM}};
- absd = _RAND_15[0:0];
- _RAND_16 = {1{`RANDOM}};
- acc = _RAND_16[0:0];
- _RAND_17 = {1{`RANDOM}};
- dup = _RAND_17[0:0];
- _RAND_18 = {1{`RANDOM}};
- max = _RAND_18[0:0];
- _RAND_19 = {1{`RANDOM}};
- min = _RAND_19[0:0];
- _RAND_20 = {1{`RANDOM}};
- srans = _RAND_20[0:0];
- _RAND_21 = {1{`RANDOM}};
- slidevn = _RAND_21[0:0];
- _RAND_22 = {1{`RANDOM}};
- slidevp = _RAND_22[0:0];
- _RAND_23 = {1{`RANDOM}};
- slidehn2 = _RAND_23[0:0];
- _RAND_24 = {1{`RANDOM}};
- slidehp2 = _RAND_24[0:0];
- _RAND_25 = {1{`RANDOM}};
- sel = _RAND_25[0:0];
- _RAND_26 = {1{`RANDOM}};
- evn = _RAND_26[0:0];
- _RAND_27 = {1{`RANDOM}};
- odd = _RAND_27[0:0];
- _RAND_28 = {1{`RANDOM}};
- zip = _RAND_28[0:0];
- _RAND_29 = {1{`RANDOM}};
- dwinit = _RAND_29[0:0];
- _RAND_30 = {1{`RANDOM}};
- dwconv = _RAND_30[0:0];
- _RAND_31 = {1{`RANDOM}};
- dwconvData = _RAND_31[0:0];
- _RAND_32 = {1{`RANDOM}};
- add = _RAND_32[0:0];
- _RAND_33 = {1{`RANDOM}};
- add_add = _RAND_33[0:0];
- _RAND_34 = {1{`RANDOM}};
- add_adds = _RAND_34[0:0];
- _RAND_35 = {1{`RANDOM}};
- add_addw = _RAND_35[0:0];
- _RAND_36 = {1{`RANDOM}};
- add_add3 = _RAND_36[0:0];
- _RAND_37 = {1{`RANDOM}};
- add_hadd = _RAND_37[0:0];
- _RAND_38 = {1{`RANDOM}};
- padd = _RAND_38[0:0];
- _RAND_39 = {1{`RANDOM}};
- padd_add = _RAND_39[0:0];
- _RAND_40 = {1{`RANDOM}};
- padd_sub = _RAND_40[0:0];
- _RAND_41 = {1{`RANDOM}};
- rsub = _RAND_41[0:0];
- _RAND_42 = {1{`RANDOM}};
- rsub_rsub = _RAND_42[0:0];
- _RAND_43 = {1{`RANDOM}};
- sub = _RAND_43[0:0];
- _RAND_44 = {1{`RANDOM}};
- sub_sub = _RAND_44[0:0];
- _RAND_45 = {1{`RANDOM}};
- sub_subs = _RAND_45[0:0];
- _RAND_46 = {1{`RANDOM}};
- sub_subw = _RAND_46[0:0];
- _RAND_47 = {1{`RANDOM}};
- sub_hsub = _RAND_47[0:0];
- _RAND_48 = {1{`RANDOM}};
- cmp = _RAND_48[0:0];
- _RAND_49 = {1{`RANDOM}};
- cmp_eq = _RAND_49[0:0];
- _RAND_50 = {1{`RANDOM}};
- cmp_ne = _RAND_50[0:0];
- _RAND_51 = {1{`RANDOM}};
- cmp_lt = _RAND_51[0:0];
- _RAND_52 = {1{`RANDOM}};
- cmp_le = _RAND_52[0:0];
- _RAND_53 = {1{`RANDOM}};
- cmp_gt = _RAND_53[0:0];
- _RAND_54 = {1{`RANDOM}};
- cmp_ge = _RAND_54[0:0];
- _RAND_55 = {1{`RANDOM}};
- log = _RAND_55[0:0];
- _RAND_56 = {1{`RANDOM}};
- log_and = _RAND_56[0:0];
- _RAND_57 = {1{`RANDOM}};
- log_or = _RAND_57[0:0];
- _RAND_58 = {1{`RANDOM}};
- log_xor = _RAND_58[0:0];
- _RAND_59 = {1{`RANDOM}};
- log_not = _RAND_59[0:0];
- _RAND_60 = {1{`RANDOM}};
- log_rev = _RAND_60[0:0];
- _RAND_61 = {1{`RANDOM}};
- log_ror = _RAND_61[0:0];
- _RAND_62 = {1{`RANDOM}};
- log_clb = _RAND_62[0:0];
- _RAND_63 = {1{`RANDOM}};
- log_clz = _RAND_63[0:0];
- _RAND_64 = {1{`RANDOM}};
- log_cpop = _RAND_64[0:0];
- _RAND_65 = {1{`RANDOM}};
- mul0 = _RAND_65[0:0];
- _RAND_66 = {1{`RANDOM}};
- mul0_dmulh = _RAND_66[0:0];
- _RAND_67 = {1{`RANDOM}};
- mul0_mul = _RAND_67[0:0];
- _RAND_68 = {1{`RANDOM}};
- mul0_mulh = _RAND_68[0:0];
- _RAND_69 = {1{`RANDOM}};
- mul0_muls = _RAND_69[0:0];
- _RAND_70 = {1{`RANDOM}};
- mul0_mulw = _RAND_70[0:0];
- _RAND_71 = {1{`RANDOM}};
- mul0_madd = _RAND_71[0:0];
- _RAND_72 = {1{`RANDOM}};
- mul1 = _RAND_72[0:0];
- _RAND_73 = {1{`RANDOM}};
- mul1_dmulh = _RAND_73[0:0];
- _RAND_74 = {1{`RANDOM}};
- mul1_mul = _RAND_74[0:0];
- _RAND_75 = {1{`RANDOM}};
- mul1_mulh = _RAND_75[0:0];
- _RAND_76 = {1{`RANDOM}};
- mul1_muls = _RAND_76[0:0];
- _RAND_77 = {1{`RANDOM}};
- mv = _RAND_77[0:0];
- _RAND_78 = {1{`RANDOM}};
- mv2 = _RAND_78[0:0];
- _RAND_79 = {1{`RANDOM}};
- mvp = _RAND_79[0:0];
- _RAND_80 = {1{`RANDOM}};
- shf_l = _RAND_80[0:0];
- _RAND_81 = {1{`RANDOM}};
- shf_r = _RAND_81[0:0];
- _RAND_82 = {1{`RANDOM}};
- shf_shl = _RAND_82[0:0];
- _RAND_83 = {1{`RANDOM}};
- shf_shr = _RAND_83[0:0];
- _RAND_84 = {1{`RANDOM}};
- shf_shf = _RAND_84[0:0];
- _RAND_85 = {1{`RANDOM}};
- validClr = _RAND_85[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- vdvalid0 = 1'h0;
- end
- if (reset) begin
- vdvalid1 = 1'h0;
- end
- if (reset) begin
- vevalid0 = 1'h0;
- end
- if (reset) begin
- vevalid1 = 1'h0;
- end
- if (reset) begin
- wmask = 1'h0;
- end
- if (reset) begin
- sz = 3'h0;
- end
- if (reset) begin
- f2 = 3'h0;
- end
- if (reset) begin
- sv = 32'h0;
- end
- if (reset) begin
- validClr = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VAlu(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_op,
- input [2:0] io_in_bits_0_bits_f2,
- input [2:0] io_in_bits_0_bits_sz,
- input io_in_bits_0_bits_m,
- input [5:0] io_in_bits_0_bits_vd_addr,
- input [5:0] io_in_bits_0_bits_ve_addr,
- input [5:0] io_in_bits_0_bits_vf_addr,
- input [5:0] io_in_bits_0_bits_vg_addr,
- input io_in_bits_0_bits_vs_valid,
- input [5:0] io_in_bits_0_bits_vs_addr,
- input [3:0] io_in_bits_0_bits_vs_tag,
- input io_in_bits_0_bits_vt_valid,
- input [5:0] io_in_bits_0_bits_vt_addr,
- input [3:0] io_in_bits_0_bits_vt_tag,
- input io_in_bits_0_bits_vu_valid,
- input [5:0] io_in_bits_0_bits_vu_addr,
- input [3:0] io_in_bits_0_bits_vu_tag,
- input io_in_bits_0_bits_vx_valid,
- input [5:0] io_in_bits_0_bits_vx_addr,
- input [3:0] io_in_bits_0_bits_vx_tag,
- input io_in_bits_0_bits_vy_valid,
- input [5:0] io_in_bits_0_bits_vy_addr,
- input [3:0] io_in_bits_0_bits_vy_tag,
- input io_in_bits_0_bits_vz_valid,
- input [5:0] io_in_bits_0_bits_vz_addr,
- input [3:0] io_in_bits_0_bits_vz_tag,
- input io_in_bits_0_bits_sv_valid,
- input [31:0] io_in_bits_0_bits_sv_data,
- input io_in_bits_0_bits_cmdsync,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_op,
- input [2:0] io_in_bits_1_bits_f2,
- input [2:0] io_in_bits_1_bits_sz,
- input io_in_bits_1_bits_m,
- input [5:0] io_in_bits_1_bits_vd_addr,
- input [5:0] io_in_bits_1_bits_ve_addr,
- input [5:0] io_in_bits_1_bits_vf_addr,
- input [5:0] io_in_bits_1_bits_vg_addr,
- input io_in_bits_1_bits_vs_valid,
- input [5:0] io_in_bits_1_bits_vs_addr,
- input [3:0] io_in_bits_1_bits_vs_tag,
- input io_in_bits_1_bits_vt_valid,
- input [5:0] io_in_bits_1_bits_vt_addr,
- input [3:0] io_in_bits_1_bits_vt_tag,
- input io_in_bits_1_bits_vu_valid,
- input [5:0] io_in_bits_1_bits_vu_addr,
- input [3:0] io_in_bits_1_bits_vu_tag,
- input io_in_bits_1_bits_vx_valid,
- input [5:0] io_in_bits_1_bits_vx_addr,
- input [3:0] io_in_bits_1_bits_vx_tag,
- input io_in_bits_1_bits_vy_valid,
- input [5:0] io_in_bits_1_bits_vy_addr,
- input [3:0] io_in_bits_1_bits_vy_tag,
- input io_in_bits_1_bits_vz_valid,
- input [5:0] io_in_bits_1_bits_vz_addr,
- input [3:0] io_in_bits_1_bits_vz_tag,
- input io_in_bits_1_bits_sv_valid,
- input [31:0] io_in_bits_1_bits_sv_data,
- input io_in_bits_1_bits_cmdsync,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_op,
- input [2:0] io_in_bits_2_bits_f2,
- input [2:0] io_in_bits_2_bits_sz,
- input io_in_bits_2_bits_m,
- input [5:0] io_in_bits_2_bits_vd_addr,
- input [5:0] io_in_bits_2_bits_ve_addr,
- input [5:0] io_in_bits_2_bits_vf_addr,
- input [5:0] io_in_bits_2_bits_vg_addr,
- input io_in_bits_2_bits_vs_valid,
- input [5:0] io_in_bits_2_bits_vs_addr,
- input [3:0] io_in_bits_2_bits_vs_tag,
- input io_in_bits_2_bits_vt_valid,
- input [5:0] io_in_bits_2_bits_vt_addr,
- input [3:0] io_in_bits_2_bits_vt_tag,
- input io_in_bits_2_bits_vu_valid,
- input [5:0] io_in_bits_2_bits_vu_addr,
- input [3:0] io_in_bits_2_bits_vu_tag,
- input io_in_bits_2_bits_vx_valid,
- input [5:0] io_in_bits_2_bits_vx_addr,
- input [3:0] io_in_bits_2_bits_vx_tag,
- input io_in_bits_2_bits_vy_valid,
- input [5:0] io_in_bits_2_bits_vy_addr,
- input [3:0] io_in_bits_2_bits_vy_tag,
- input io_in_bits_2_bits_vz_valid,
- input [5:0] io_in_bits_2_bits_vz_addr,
- input [3:0] io_in_bits_2_bits_vz_tag,
- input io_in_bits_2_bits_sv_valid,
- input [31:0] io_in_bits_2_bits_sv_data,
- input io_in_bits_2_bits_cmdsync,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_op,
- input [2:0] io_in_bits_3_bits_f2,
- input [2:0] io_in_bits_3_bits_sz,
- input io_in_bits_3_bits_m,
- input [5:0] io_in_bits_3_bits_vd_addr,
- input [5:0] io_in_bits_3_bits_ve_addr,
- input [5:0] io_in_bits_3_bits_vf_addr,
- input [5:0] io_in_bits_3_bits_vg_addr,
- input io_in_bits_3_bits_vs_valid,
- input [5:0] io_in_bits_3_bits_vs_addr,
- input [3:0] io_in_bits_3_bits_vs_tag,
- input io_in_bits_3_bits_vt_valid,
- input [5:0] io_in_bits_3_bits_vt_addr,
- input [3:0] io_in_bits_3_bits_vt_tag,
- input io_in_bits_3_bits_vu_valid,
- input [5:0] io_in_bits_3_bits_vu_addr,
- input [3:0] io_in_bits_3_bits_vu_tag,
- input io_in_bits_3_bits_vx_valid,
- input [5:0] io_in_bits_3_bits_vx_addr,
- input [3:0] io_in_bits_3_bits_vx_tag,
- input io_in_bits_3_bits_vy_valid,
- input [5:0] io_in_bits_3_bits_vy_addr,
- input [3:0] io_in_bits_3_bits_vy_tag,
- input io_in_bits_3_bits_vz_valid,
- input [5:0] io_in_bits_3_bits_vz_addr,
- input [3:0] io_in_bits_3_bits_vz_tag,
- input io_in_bits_3_bits_sv_valid,
- input [31:0] io_in_bits_3_bits_sv_data,
- input io_in_bits_3_bits_cmdsync,
- output [63:0] io_active,
- input [127:0] io_vrfsb,
- output io_read_0_valid,
- output [5:0] io_read_0_addr,
- input [255:0] io_read_0_data,
- output io_read_1_valid,
- output [5:0] io_read_1_addr,
- input [255:0] io_read_1_data,
- output io_read_2_valid,
- output [5:0] io_read_2_addr,
- input [255:0] io_read_2_data,
- output io_read_3_valid,
- output [5:0] io_read_3_addr,
- input [255:0] io_read_3_data,
- output io_read_4_valid,
- output [5:0] io_read_4_addr,
- input [255:0] io_read_4_data,
- output io_read_5_valid,
- output [5:0] io_read_5_addr,
- input [255:0] io_read_5_data,
- output io_write_0_valid,
- output [5:0] io_write_0_addr,
- output [255:0] io_write_0_data,
- output io_write_1_valid,
- output [5:0] io_write_1_addr,
- output [255:0] io_write_1_data,
- output io_write_2_valid,
- output [5:0] io_write_2_addr,
- output [255:0] io_write_2_data,
- output io_write_3_valid,
- output [5:0] io_write_3_addr,
- output [255:0] io_write_3_data,
- output io_whint_0_valid,
- output [5:0] io_whint_0_addr,
- output io_whint_1_valid,
- output [5:0] io_whint_1_addr,
- output io_whint_2_valid,
- output [5:0] io_whint_2_addr,
- output io_whint_3_valid,
- output [5:0] io_whint_3_addr,
- output io_scalar_0_valid,
- output [31:0] io_scalar_0_data,
- output io_scalar_1_valid,
- output [31:0] io_scalar_1_data
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
-`endif // RANDOMIZE_REG_INIT
- wire q0_clock; // @[VCmdq.scala 30:11]
- wire q0_reset; // @[VCmdq.scala 30:11]
- wire q0_io_in_ready; // @[VCmdq.scala 30:11]
- wire q0_io_in_valid; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_0_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q0_io_in_bits_0_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q0_io_in_bits_0_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q0_io_in_bits_0_bits_sz; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_0_bits_m; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_0_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_0_bits_ve_addr; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_0_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_0_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_in_bits_0_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_0_bits_vt_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_0_bits_vt_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_in_bits_0_bits_vt_tag; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_0_bits_vu_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_0_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_in_bits_0_bits_vu_tag; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_0_bits_sv_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q0_io_in_bits_0_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_0_bits_cmdsync; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_1_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q0_io_in_bits_1_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q0_io_in_bits_1_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q0_io_in_bits_1_bits_sz; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_1_bits_m; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_1_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_1_bits_ve_addr; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_1_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_1_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_in_bits_1_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_1_bits_vt_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_1_bits_vt_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_in_bits_1_bits_vt_tag; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_1_bits_vu_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_1_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_in_bits_1_bits_vu_tag; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_1_bits_sv_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q0_io_in_bits_1_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_1_bits_cmdsync; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_2_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q0_io_in_bits_2_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q0_io_in_bits_2_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q0_io_in_bits_2_bits_sz; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_2_bits_m; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_2_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_2_bits_ve_addr; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_2_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_2_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_in_bits_2_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_2_bits_vt_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_2_bits_vt_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_in_bits_2_bits_vt_tag; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_2_bits_vu_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_2_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_in_bits_2_bits_vu_tag; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_2_bits_sv_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q0_io_in_bits_2_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_2_bits_cmdsync; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_3_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q0_io_in_bits_3_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q0_io_in_bits_3_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q0_io_in_bits_3_bits_sz; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_3_bits_m; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_3_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_3_bits_ve_addr; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_3_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_3_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_in_bits_3_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_3_bits_vt_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_3_bits_vt_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_in_bits_3_bits_vt_tag; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_3_bits_vu_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_in_bits_3_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_in_bits_3_bits_vu_tag; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_3_bits_sv_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q0_io_in_bits_3_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q0_io_in_bits_3_bits_cmdsync; // @[VCmdq.scala 30:11]
- wire q0_io_out_ready; // @[VCmdq.scala 30:11]
- wire q0_io_out_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q0_io_out_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q0_io_out_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q0_io_out_bits_sz; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_out_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_out_bits_ve_addr; // @[VCmdq.scala 30:11]
- wire q0_io_out_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_out_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_out_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire q0_io_out_bits_vt_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_out_bits_vt_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_out_bits_vt_tag; // @[VCmdq.scala 30:11]
- wire q0_io_out_bits_vu_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q0_io_out_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q0_io_out_bits_vu_tag; // @[VCmdq.scala 30:11]
- wire q0_io_out_bits_sv_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q0_io_out_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q0_io_out_bits_cmdsync; // @[VCmdq.scala 30:11]
- wire [63:0] q0_io_active; // @[VCmdq.scala 30:11]
- wire q1_clock; // @[VCmdq.scala 30:11]
- wire q1_reset; // @[VCmdq.scala 30:11]
- wire q1_io_in_ready; // @[VCmdq.scala 30:11]
- wire q1_io_in_valid; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_0_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q1_io_in_bits_0_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q1_io_in_bits_0_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q1_io_in_bits_0_bits_sz; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_0_bits_m; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_0_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_0_bits_ve_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_0_bits_vf_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_0_bits_vg_addr; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_0_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_0_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_0_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_0_bits_vt_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_0_bits_vt_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_0_bits_vt_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_0_bits_vu_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_0_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_0_bits_vu_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_0_bits_vx_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_0_bits_vx_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_0_bits_vx_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_0_bits_vy_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_0_bits_vy_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_0_bits_vy_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_0_bits_vz_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_0_bits_vz_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_0_bits_vz_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_0_bits_sv_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q1_io_in_bits_0_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_0_bits_cmdsync; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_1_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q1_io_in_bits_1_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q1_io_in_bits_1_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q1_io_in_bits_1_bits_sz; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_1_bits_m; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_1_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_1_bits_ve_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_1_bits_vf_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_1_bits_vg_addr; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_1_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_1_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_1_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_1_bits_vt_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_1_bits_vt_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_1_bits_vt_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_1_bits_vu_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_1_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_1_bits_vu_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_1_bits_vx_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_1_bits_vx_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_1_bits_vx_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_1_bits_vy_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_1_bits_vy_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_1_bits_vy_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_1_bits_vz_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_1_bits_vz_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_1_bits_vz_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_1_bits_sv_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q1_io_in_bits_1_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_1_bits_cmdsync; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_2_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q1_io_in_bits_2_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q1_io_in_bits_2_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q1_io_in_bits_2_bits_sz; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_2_bits_m; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_2_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_2_bits_ve_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_2_bits_vf_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_2_bits_vg_addr; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_2_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_2_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_2_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_2_bits_vt_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_2_bits_vt_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_2_bits_vt_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_2_bits_vu_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_2_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_2_bits_vu_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_2_bits_vx_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_2_bits_vx_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_2_bits_vx_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_2_bits_vy_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_2_bits_vy_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_2_bits_vy_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_2_bits_vz_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_2_bits_vz_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_2_bits_vz_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_2_bits_sv_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q1_io_in_bits_2_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_2_bits_cmdsync; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_3_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q1_io_in_bits_3_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q1_io_in_bits_3_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q1_io_in_bits_3_bits_sz; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_3_bits_m; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_3_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_3_bits_ve_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_3_bits_vf_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_3_bits_vg_addr; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_3_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_3_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_3_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_3_bits_vt_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_3_bits_vt_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_3_bits_vt_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_3_bits_vu_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_3_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_3_bits_vu_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_3_bits_vx_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_3_bits_vx_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_3_bits_vx_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_3_bits_vy_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_3_bits_vy_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_3_bits_vy_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_3_bits_vz_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_in_bits_3_bits_vz_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_in_bits_3_bits_vz_tag; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_3_bits_sv_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q1_io_in_bits_3_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q1_io_in_bits_3_bits_cmdsync; // @[VCmdq.scala 30:11]
- wire q1_io_out_ready; // @[VCmdq.scala 30:11]
- wire q1_io_out_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q1_io_out_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q1_io_out_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q1_io_out_bits_sz; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_out_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_out_bits_ve_addr; // @[VCmdq.scala 30:11]
- wire q1_io_out_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_out_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_out_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire q1_io_out_bits_vt_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_out_bits_vt_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_out_bits_vt_tag; // @[VCmdq.scala 30:11]
- wire q1_io_out_bits_vu_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q1_io_out_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q1_io_out_bits_vu_tag; // @[VCmdq.scala 30:11]
- wire q1_io_out_bits_sv_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q1_io_out_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q1_io_out_bits_cmdsync; // @[VCmdq.scala 30:11]
- wire [63:0] q1_io_active; // @[VCmdq.scala 30:11]
- wire alu0_clock; // @[VAlu.scala 337:20]
- wire alu0_reset; // @[VAlu.scala 337:20]
- wire alu0_io_in_valid; // @[VAlu.scala 337:20]
- wire [6:0] alu0_io_in_op; // @[VAlu.scala 337:20]
- wire [2:0] alu0_io_in_f2; // @[VAlu.scala 337:20]
- wire [2:0] alu0_io_in_sz; // @[VAlu.scala 337:20]
- wire [5:0] alu0_io_in_vd_addr; // @[VAlu.scala 337:20]
- wire [5:0] alu0_io_in_ve_addr; // @[VAlu.scala 337:20]
- wire [31:0] alu0_io_in_sv_data; // @[VAlu.scala 337:20]
- wire [255:0] alu0_io_read_0_data; // @[VAlu.scala 337:20]
- wire [255:0] alu0_io_read_1_data; // @[VAlu.scala 337:20]
- wire [255:0] alu0_io_read_2_data; // @[VAlu.scala 337:20]
- wire [255:0] alu0_io_read_3_data; // @[VAlu.scala 337:20]
- wire [255:0] alu0_io_read_4_data; // @[VAlu.scala 337:20]
- wire [255:0] alu0_io_read_5_data; // @[VAlu.scala 337:20]
- wire alu0_io_write_0_valid; // @[VAlu.scala 337:20]
- wire [5:0] alu0_io_write_0_addr; // @[VAlu.scala 337:20]
- wire [255:0] alu0_io_write_0_data; // @[VAlu.scala 337:20]
- wire alu0_io_write_1_valid; // @[VAlu.scala 337:20]
- wire [5:0] alu0_io_write_1_addr; // @[VAlu.scala 337:20]
- wire [255:0] alu0_io_write_1_data; // @[VAlu.scala 337:20]
- wire alu0_io_whint_0_valid; // @[VAlu.scala 337:20]
- wire [5:0] alu0_io_whint_0_addr; // @[VAlu.scala 337:20]
- wire alu0_io_whint_1_valid; // @[VAlu.scala 337:20]
- wire [5:0] alu0_io_whint_1_addr; // @[VAlu.scala 337:20]
- wire alu1_clock; // @[VAlu.scala 371:20]
- wire alu1_reset; // @[VAlu.scala 371:20]
- wire alu1_io_in_valid; // @[VAlu.scala 371:20]
- wire [6:0] alu1_io_in_op; // @[VAlu.scala 371:20]
- wire [2:0] alu1_io_in_f2; // @[VAlu.scala 371:20]
- wire [2:0] alu1_io_in_sz; // @[VAlu.scala 371:20]
- wire [5:0] alu1_io_in_vd_addr; // @[VAlu.scala 371:20]
- wire [5:0] alu1_io_in_ve_addr; // @[VAlu.scala 371:20]
- wire [31:0] alu1_io_in_sv_data; // @[VAlu.scala 371:20]
- wire [255:0] alu1_io_read_0_data; // @[VAlu.scala 371:20]
- wire [255:0] alu1_io_read_1_data; // @[VAlu.scala 371:20]
- wire [255:0] alu1_io_read_2_data; // @[VAlu.scala 371:20]
- wire [255:0] alu1_io_read_3_data; // @[VAlu.scala 371:20]
- wire [255:0] alu1_io_read_4_data; // @[VAlu.scala 371:20]
- wire [255:0] alu1_io_read_5_data; // @[VAlu.scala 371:20]
- wire alu1_io_write_0_valid; // @[VAlu.scala 371:20]
- wire [5:0] alu1_io_write_0_addr; // @[VAlu.scala 371:20]
- wire [255:0] alu1_io_write_0_data; // @[VAlu.scala 371:20]
- wire alu1_io_write_1_valid; // @[VAlu.scala 371:20]
- wire [5:0] alu1_io_write_1_addr; // @[VAlu.scala 371:20]
- wire [255:0] alu1_io_write_1_data; // @[VAlu.scala 371:20]
- wire alu1_io_whint_0_valid; // @[VAlu.scala 371:20]
- wire [5:0] alu1_io_whint_0_addr; // @[VAlu.scala 371:20]
- wire alu1_io_whint_1_valid; // @[VAlu.scala 371:20]
- wire [5:0] alu1_io_whint_1_addr; // @[VAlu.scala 371:20]
- wire _T = io_in_valid & io_in_ready; // @[VAlu.scala 78:23]
- wire _supported_T_1 = io_in_bits_0_bits_op == 7'h35; // @[VAlu.scala 84:16]
- wire _supported_T_2 = io_in_bits_0_bits_op == 7'hf | _supported_T_1; // @[VAlu.scala 83:30]
- wire _supported_T_3 = io_in_bits_0_bits_op == 7'h6; // @[VAlu.scala 85:16]
- wire _supported_T_4 = _supported_T_2 | _supported_T_3; // @[VAlu.scala 84:29]
- wire _supported_T_5 = io_in_bits_0_bits_op == 7'h31; // @[VAlu.scala 86:16]
- wire _supported_T_6 = _supported_T_4 | _supported_T_5; // @[VAlu.scala 85:29]
- wire _supported_T_7 = io_in_bits_0_bits_op == 7'h33; // @[VAlu.scala 87:16]
- wire _supported_T_8 = _supported_T_6 | _supported_T_7; // @[VAlu.scala 86:30]
- wire _supported_T_9 = io_in_bits_0_bits_op == 7'h12; // @[VAlu.scala 88:16]
- wire _supported_T_10 = _supported_T_8 | _supported_T_9; // @[VAlu.scala 87:30]
- wire _supported_T_11 = io_in_bits_0_bits_op == 7'h1; // @[VAlu.scala 89:16]
- wire _supported_T_12 = _supported_T_10 | _supported_T_11; // @[VAlu.scala 88:30]
- wire _supported_T_13 = io_in_bits_0_bits_op == 7'h38; // @[VAlu.scala 90:16]
- wire _supported_T_14 = _supported_T_12 | _supported_T_13; // @[VAlu.scala 89:29]
- wire _supported_T_15 = io_in_bits_0_bits_op == 7'h39; // @[VAlu.scala 91:16]
- wire _supported_T_16 = _supported_T_14 | _supported_T_15; // @[VAlu.scala 90:30]
- wire _supported_T_17 = io_in_bits_0_bits_op == 7'h10; // @[VAlu.scala 92:16]
- wire _supported_T_18 = _supported_T_16 | _supported_T_17; // @[VAlu.scala 91:30]
- wire _supported_T_19 = io_in_bits_0_bits_op == 7'h11; // @[VAlu.scala 93:16]
- wire _supported_T_20 = _supported_T_18 | _supported_T_19; // @[VAlu.scala 92:29]
- wire _supported_T_21 = io_in_bits_0_bits_op == 7'h36; // @[VAlu.scala 94:16]
- wire _supported_T_22 = _supported_T_20 | _supported_T_21; // @[VAlu.scala 93:29]
- wire _supported_T_23 = io_in_bits_0_bits_op == 7'h37; // @[VAlu.scala 95:16]
- wire _supported_T_24 = _supported_T_22 | _supported_T_23; // @[VAlu.scala 94:30]
- wire _supported_T_25 = io_in_bits_0_bits_op == 7'h8; // @[VAlu.scala 96:16]
- wire _supported_T_26 = _supported_T_24 | _supported_T_25; // @[VAlu.scala 95:30]
- wire _supported_T_27 = io_in_bits_0_bits_op == 7'h7; // @[VAlu.scala 97:16]
- wire _supported_T_28 = _supported_T_26 | _supported_T_27; // @[VAlu.scala 96:30]
- wire _supported_T_29 = io_in_bits_0_bits_op == 7'h32; // @[VAlu.scala 98:16]
- wire _supported_T_30 = _supported_T_28 | _supported_T_29; // @[VAlu.scala 97:29]
- wire _supported_T_31 = io_in_bits_0_bits_op == 7'h34; // @[VAlu.scala 99:16]
- wire _supported_T_32 = _supported_T_30 | _supported_T_31; // @[VAlu.scala 98:30]
- wire _supported_T_33 = io_in_bits_0_bits_op == 7'h9; // @[VAlu.scala 101:16]
- wire _supported_T_34 = _supported_T_32 | _supported_T_33; // @[VAlu.scala 99:30]
- wire _supported_T_35 = io_in_bits_0_bits_op == 7'ha; // @[VAlu.scala 102:16]
- wire _supported_T_36 = _supported_T_34 | _supported_T_35; // @[VAlu.scala 101:28]
- wire _supported_T_37 = io_in_bits_0_bits_op == 7'hb; // @[VAlu.scala 103:16]
- wire _supported_T_38 = _supported_T_36 | _supported_T_37; // @[VAlu.scala 102:28]
- wire _supported_T_39 = io_in_bits_0_bits_op == 7'hc; // @[VAlu.scala 104:16]
- wire _supported_T_40 = _supported_T_38 | _supported_T_39; // @[VAlu.scala 103:28]
- wire _supported_T_41 = io_in_bits_0_bits_op == 7'hd; // @[VAlu.scala 105:16]
- wire _supported_T_42 = _supported_T_40 | _supported_T_41; // @[VAlu.scala 104:28]
- wire _supported_T_43 = io_in_bits_0_bits_op == 7'he; // @[VAlu.scala 106:16]
- wire _supported_T_44 = _supported_T_42 | _supported_T_43; // @[VAlu.scala 105:28]
- wire _supported_T_45 = io_in_bits_0_bits_op == 7'h13; // @[VAlu.scala 108:16]
- wire _supported_T_46 = _supported_T_44 | _supported_T_45; // @[VAlu.scala 106:28]
- wire _supported_T_47 = io_in_bits_0_bits_op == 7'h19; // @[VAlu.scala 109:16]
- wire _supported_T_48 = _supported_T_46 | _supported_T_47; // @[VAlu.scala 108:29]
- wire _supported_T_49 = io_in_bits_0_bits_op == 7'h1a; // @[VAlu.scala 110:16]
- wire _supported_T_50 = _supported_T_48 | _supported_T_49; // @[VAlu.scala 109:29]
- wire _supported_T_51 = io_in_bits_0_bits_op == 7'h1b; // @[VAlu.scala 111:16]
- wire _supported_T_52 = _supported_T_50 | _supported_T_51; // @[VAlu.scala 110:29]
- wire _supported_T_53 = io_in_bits_0_bits_op == 7'h1c; // @[VAlu.scala 112:16]
- wire _supported_T_54 = _supported_T_52 | _supported_T_53; // @[VAlu.scala 111:30]
- wire _supported_T_55 = io_in_bits_0_bits_op == 7'h1d; // @[VAlu.scala 113:16]
- wire _supported_T_56 = _supported_T_54 | _supported_T_55; // @[VAlu.scala 112:28]
- wire _supported_T_57 = io_in_bits_0_bits_op == 7'h1e; // @[VAlu.scala 114:16]
- wire _supported_T_58 = _supported_T_56 | _supported_T_57; // @[VAlu.scala 113:29]
- wire _supported_T_59 = io_in_bits_0_bits_op == 7'h21; // @[VAlu.scala 115:16]
- wire _supported_T_60 = _supported_T_58 | _supported_T_59; // @[VAlu.scala 114:29]
- wire _supported_T_61 = io_in_bits_0_bits_op == 7'h16; // @[VAlu.scala 116:16]
- wire _supported_T_62 = _supported_T_60 | _supported_T_61; // @[VAlu.scala 115:32]
- wire _supported_T_63 = io_in_bits_0_bits_op == 7'h14; // @[VAlu.scala 117:16]
- wire _supported_T_64 = _supported_T_62 | _supported_T_63; // @[VAlu.scala 116:29]
- wire _supported_T_65 = io_in_bits_0_bits_op == 7'h17; // @[VAlu.scala 118:16]
- wire _supported_T_66 = _supported_T_64 | _supported_T_65; // @[VAlu.scala 117:28]
- wire _supported_T_67 = io_in_bits_0_bits_op == 7'h18; // @[VAlu.scala 119:16]
- wire _supported_T_68 = _supported_T_66 | _supported_T_67; // @[VAlu.scala 118:29]
- wire _supported_T_69 = io_in_bits_0_bits_op == 7'h15; // @[VAlu.scala 120:16]
- wire _supported_T_70 = _supported_T_68 | _supported_T_69; // @[VAlu.scala 119:29]
- wire _supported_T_71 = io_in_bits_0_bits_op == 7'h22; // @[VAlu.scala 122:16]
- wire _supported_T_72 = _supported_T_70 | _supported_T_71; // @[VAlu.scala 120:29]
- wire _supported_T_73 = io_in_bits_0_bits_op == 7'h23; // @[VAlu.scala 123:16]
- wire _supported_T_74 = _supported_T_72 | _supported_T_73; // @[VAlu.scala 122:29]
- wire _supported_T_75 = io_in_bits_0_bits_op == 7'h24; // @[VAlu.scala 124:16]
- wire _supported_T_76 = _supported_T_74 | _supported_T_75; // @[VAlu.scala 123:29]
- wire _supported_T_77 = io_in_bits_0_bits_op == 7'h25; // @[VAlu.scala 125:16]
- wire _supported_T_78 = _supported_T_76 | _supported_T_77; // @[VAlu.scala 124:29]
- wire _supported_T_79 = io_in_bits_0_bits_op == 7'h26; // @[VAlu.scala 126:16]
- wire _supported_T_80 = _supported_T_78 | _supported_T_79; // @[VAlu.scala 125:31]
- wire _supported_T_81 = io_in_bits_0_bits_op == 7'h2d; // @[VAlu.scala 128:16]
- wire _supported_T_82 = _supported_T_80 | _supported_T_81; // @[VAlu.scala 126:31]
- wire _supported_T_83 = io_in_bits_0_bits_op == 7'h2e; // @[VAlu.scala 129:16]
- wire _supported_T_84 = _supported_T_82 | _supported_T_83; // @[VAlu.scala 128:31]
- wire _supported_T_85 = io_in_bits_0_bits_op == 7'h30; // @[VAlu.scala 130:16]
- wire _supported_T_86 = _supported_T_84 | _supported_T_85; // @[VAlu.scala 129:32]
- wire _supported_T_87 = io_in_bits_0_bits_op == 7'h27; // @[VAlu.scala 131:16]
- wire _supported_T_88 = _supported_T_86 | _supported_T_87; // @[VAlu.scala 130:30]
- wire _supported_T_89 = io_in_bits_0_bits_op == 7'h28; // @[VAlu.scala 132:16]
- wire _supported_T_90 = _supported_T_88 | _supported_T_89; // @[VAlu.scala 131:29]
- wire _supported_T_91 = io_in_bits_0_bits_op == 7'h2b; // @[VAlu.scala 133:16]
- wire _supported_T_92 = _supported_T_90 | _supported_T_91; // @[VAlu.scala 132:30]
- wire _supported_T_93 = io_in_bits_0_bits_op == 7'h2c; // @[VAlu.scala 134:16]
- wire _supported_T_94 = _supported_T_92 | _supported_T_93; // @[VAlu.scala 133:30]
- wire _supported_T_95 = io_in_bits_0_bits_op == 7'h29; // @[VAlu.scala 135:16]
- wire _supported_T_96 = _supported_T_94 | _supported_T_95; // @[VAlu.scala 134:31]
- wire _supported_T_97 = io_in_bits_0_bits_op == 7'h2a; // @[VAlu.scala 136:16]
- wire _supported_T_98 = _supported_T_96 | _supported_T_97; // @[VAlu.scala 135:30]
- wire _supported_T_99 = io_in_bits_0_bits_op == 7'h2f; // @[VAlu.scala 137:16]
- wire _supported_T_100 = _supported_T_98 | _supported_T_99; // @[VAlu.scala 136:31]
- wire _supported_T_101 = io_in_bits_0_bits_op == 7'h3a; // @[VAlu.scala 139:16]
- wire _supported_T_102 = _supported_T_100 | _supported_T_101; // @[VAlu.scala 137:30]
- wire _supported_T_103 = io_in_bits_0_bits_op == 7'h3d; // @[VAlu.scala 140:16]
- wire _supported_T_104 = _supported_T_102 | _supported_T_103; // @[VAlu.scala 139:33]
- wire _supported_T_105 = io_in_bits_0_bits_op == 7'h3c; // @[VAlu.scala 141:16]
- wire _supported_T_106 = _supported_T_104 | _supported_T_105; // @[VAlu.scala 140:33]
- wire _supported_T_107 = io_in_bits_0_bits_op == 7'h3f; // @[VAlu.scala 142:16]
- wire _supported_T_108 = _supported_T_106 | _supported_T_107; // @[VAlu.scala 141:34]
- wire _supported_T_109 = io_in_bits_0_bits_op == 7'h40; // @[VAlu.scala 143:16]
- wire _supported_T_110 = _supported_T_108 | _supported_T_109; // @[VAlu.scala 142:34]
- wire _supported_T_111 = io_in_bits_0_bits_op == 7'h41; // @[VAlu.scala 144:16]
- wire _supported_T_112 = _supported_T_110 | _supported_T_111; // @[VAlu.scala 143:29]
- wire _supported_T_113 = io_in_bits_0_bits_op == 7'h42; // @[VAlu.scala 145:16]
- wire _supported_T_114 = _supported_T_112 | _supported_T_113; // @[VAlu.scala 144:29]
- wire _supported_T_115 = io_in_bits_0_bits_op == 7'h43; // @[VAlu.scala 146:16]
- wire _supported_T_116 = _supported_T_114 | _supported_T_115; // @[VAlu.scala 145:29]
- wire _supported_T_117 = io_in_bits_0_bits_op == 7'h44; // @[VAlu.scala 147:16]
- wire _supported_T_118 = _supported_T_116 | _supported_T_117; // @[VAlu.scala 146:32]
- wire _supported_T_119 = io_in_bits_0_bits_op == 7'h46; // @[VAlu.scala 149:16]
- wire _supported_T_120 = _supported_T_118 | _supported_T_119; // @[VAlu.scala 147:29]
- wire _supported_T_121 = io_in_bits_0_bits_op == 7'h47; // @[VAlu.scala 150:16]
- wire supported = _supported_T_120 | _supported_T_121; // @[VAlu.scala 149:32]
- wire _T_1 = ~supported; // @[VAlu.scala 152:15]
- wire _T_3 = ~reset; // @[VAlu.scala 153:17]
- wire _T_14 = _supported_T_119 | _supported_T_121; // @[VAlu.scala 159:34]
- wire [1:0] sparse = io_in_bits_0_bits_sv_data[3:2]; // @[VAlu.scala 160:50]
- wire _supported_T_123 = io_in_bits_1_bits_op == 7'h35; // @[VAlu.scala 84:16]
- wire _supported_T_124 = io_in_bits_1_bits_op == 7'hf | _supported_T_123; // @[VAlu.scala 83:30]
- wire _supported_T_125 = io_in_bits_1_bits_op == 7'h6; // @[VAlu.scala 85:16]
- wire _supported_T_126 = _supported_T_124 | _supported_T_125; // @[VAlu.scala 84:29]
- wire _supported_T_127 = io_in_bits_1_bits_op == 7'h31; // @[VAlu.scala 86:16]
- wire _supported_T_128 = _supported_T_126 | _supported_T_127; // @[VAlu.scala 85:29]
- wire _supported_T_129 = io_in_bits_1_bits_op == 7'h33; // @[VAlu.scala 87:16]
- wire _supported_T_130 = _supported_T_128 | _supported_T_129; // @[VAlu.scala 86:30]
- wire _supported_T_131 = io_in_bits_1_bits_op == 7'h12; // @[VAlu.scala 88:16]
- wire _supported_T_132 = _supported_T_130 | _supported_T_131; // @[VAlu.scala 87:30]
- wire _supported_T_133 = io_in_bits_1_bits_op == 7'h1; // @[VAlu.scala 89:16]
- wire _supported_T_134 = _supported_T_132 | _supported_T_133; // @[VAlu.scala 88:30]
- wire _supported_T_135 = io_in_bits_1_bits_op == 7'h38; // @[VAlu.scala 90:16]
- wire _supported_T_136 = _supported_T_134 | _supported_T_135; // @[VAlu.scala 89:29]
- wire _supported_T_137 = io_in_bits_1_bits_op == 7'h39; // @[VAlu.scala 91:16]
- wire _supported_T_138 = _supported_T_136 | _supported_T_137; // @[VAlu.scala 90:30]
- wire _supported_T_139 = io_in_bits_1_bits_op == 7'h10; // @[VAlu.scala 92:16]
- wire _supported_T_140 = _supported_T_138 | _supported_T_139; // @[VAlu.scala 91:30]
- wire _supported_T_141 = io_in_bits_1_bits_op == 7'h11; // @[VAlu.scala 93:16]
- wire _supported_T_142 = _supported_T_140 | _supported_T_141; // @[VAlu.scala 92:29]
- wire _supported_T_143 = io_in_bits_1_bits_op == 7'h36; // @[VAlu.scala 94:16]
- wire _supported_T_144 = _supported_T_142 | _supported_T_143; // @[VAlu.scala 93:29]
- wire _supported_T_145 = io_in_bits_1_bits_op == 7'h37; // @[VAlu.scala 95:16]
- wire _supported_T_146 = _supported_T_144 | _supported_T_145; // @[VAlu.scala 94:30]
- wire _supported_T_147 = io_in_bits_1_bits_op == 7'h8; // @[VAlu.scala 96:16]
- wire _supported_T_148 = _supported_T_146 | _supported_T_147; // @[VAlu.scala 95:30]
- wire _supported_T_149 = io_in_bits_1_bits_op == 7'h7; // @[VAlu.scala 97:16]
- wire _supported_T_150 = _supported_T_148 | _supported_T_149; // @[VAlu.scala 96:30]
- wire _supported_T_151 = io_in_bits_1_bits_op == 7'h32; // @[VAlu.scala 98:16]
- wire _supported_T_152 = _supported_T_150 | _supported_T_151; // @[VAlu.scala 97:29]
- wire _supported_T_153 = io_in_bits_1_bits_op == 7'h34; // @[VAlu.scala 99:16]
- wire _supported_T_154 = _supported_T_152 | _supported_T_153; // @[VAlu.scala 98:30]
- wire _supported_T_155 = io_in_bits_1_bits_op == 7'h9; // @[VAlu.scala 101:16]
- wire _supported_T_156 = _supported_T_154 | _supported_T_155; // @[VAlu.scala 99:30]
- wire _supported_T_157 = io_in_bits_1_bits_op == 7'ha; // @[VAlu.scala 102:16]
- wire _supported_T_158 = _supported_T_156 | _supported_T_157; // @[VAlu.scala 101:28]
- wire _supported_T_159 = io_in_bits_1_bits_op == 7'hb; // @[VAlu.scala 103:16]
- wire _supported_T_160 = _supported_T_158 | _supported_T_159; // @[VAlu.scala 102:28]
- wire _supported_T_161 = io_in_bits_1_bits_op == 7'hc; // @[VAlu.scala 104:16]
- wire _supported_T_162 = _supported_T_160 | _supported_T_161; // @[VAlu.scala 103:28]
- wire _supported_T_163 = io_in_bits_1_bits_op == 7'hd; // @[VAlu.scala 105:16]
- wire _supported_T_164 = _supported_T_162 | _supported_T_163; // @[VAlu.scala 104:28]
- wire _supported_T_165 = io_in_bits_1_bits_op == 7'he; // @[VAlu.scala 106:16]
- wire _supported_T_166 = _supported_T_164 | _supported_T_165; // @[VAlu.scala 105:28]
- wire _supported_T_167 = io_in_bits_1_bits_op == 7'h13; // @[VAlu.scala 108:16]
- wire _supported_T_168 = _supported_T_166 | _supported_T_167; // @[VAlu.scala 106:28]
- wire _supported_T_169 = io_in_bits_1_bits_op == 7'h19; // @[VAlu.scala 109:16]
- wire _supported_T_170 = _supported_T_168 | _supported_T_169; // @[VAlu.scala 108:29]
- wire _supported_T_171 = io_in_bits_1_bits_op == 7'h1a; // @[VAlu.scala 110:16]
- wire _supported_T_172 = _supported_T_170 | _supported_T_171; // @[VAlu.scala 109:29]
- wire _supported_T_173 = io_in_bits_1_bits_op == 7'h1b; // @[VAlu.scala 111:16]
- wire _supported_T_174 = _supported_T_172 | _supported_T_173; // @[VAlu.scala 110:29]
- wire _supported_T_175 = io_in_bits_1_bits_op == 7'h1c; // @[VAlu.scala 112:16]
- wire _supported_T_176 = _supported_T_174 | _supported_T_175; // @[VAlu.scala 111:30]
- wire _supported_T_177 = io_in_bits_1_bits_op == 7'h1d; // @[VAlu.scala 113:16]
- wire _supported_T_178 = _supported_T_176 | _supported_T_177; // @[VAlu.scala 112:28]
- wire _supported_T_179 = io_in_bits_1_bits_op == 7'h1e; // @[VAlu.scala 114:16]
- wire _supported_T_180 = _supported_T_178 | _supported_T_179; // @[VAlu.scala 113:29]
- wire _supported_T_181 = io_in_bits_1_bits_op == 7'h21; // @[VAlu.scala 115:16]
- wire _supported_T_182 = _supported_T_180 | _supported_T_181; // @[VAlu.scala 114:29]
- wire _supported_T_183 = io_in_bits_1_bits_op == 7'h16; // @[VAlu.scala 116:16]
- wire _supported_T_184 = _supported_T_182 | _supported_T_183; // @[VAlu.scala 115:32]
- wire _supported_T_185 = io_in_bits_1_bits_op == 7'h14; // @[VAlu.scala 117:16]
- wire _supported_T_186 = _supported_T_184 | _supported_T_185; // @[VAlu.scala 116:29]
- wire _supported_T_187 = io_in_bits_1_bits_op == 7'h17; // @[VAlu.scala 118:16]
- wire _supported_T_188 = _supported_T_186 | _supported_T_187; // @[VAlu.scala 117:28]
- wire _supported_T_189 = io_in_bits_1_bits_op == 7'h18; // @[VAlu.scala 119:16]
- wire _supported_T_190 = _supported_T_188 | _supported_T_189; // @[VAlu.scala 118:29]
- wire _supported_T_191 = io_in_bits_1_bits_op == 7'h15; // @[VAlu.scala 120:16]
- wire _supported_T_192 = _supported_T_190 | _supported_T_191; // @[VAlu.scala 119:29]
- wire _supported_T_193 = io_in_bits_1_bits_op == 7'h22; // @[VAlu.scala 122:16]
- wire _supported_T_194 = _supported_T_192 | _supported_T_193; // @[VAlu.scala 120:29]
- wire _supported_T_195 = io_in_bits_1_bits_op == 7'h23; // @[VAlu.scala 123:16]
- wire _supported_T_196 = _supported_T_194 | _supported_T_195; // @[VAlu.scala 122:29]
- wire _supported_T_197 = io_in_bits_1_bits_op == 7'h24; // @[VAlu.scala 124:16]
- wire _supported_T_198 = _supported_T_196 | _supported_T_197; // @[VAlu.scala 123:29]
- wire _supported_T_199 = io_in_bits_1_bits_op == 7'h25; // @[VAlu.scala 125:16]
- wire _supported_T_200 = _supported_T_198 | _supported_T_199; // @[VAlu.scala 124:29]
- wire _supported_T_201 = io_in_bits_1_bits_op == 7'h26; // @[VAlu.scala 126:16]
- wire _supported_T_202 = _supported_T_200 | _supported_T_201; // @[VAlu.scala 125:31]
- wire _supported_T_203 = io_in_bits_1_bits_op == 7'h2d; // @[VAlu.scala 128:16]
- wire _supported_T_204 = _supported_T_202 | _supported_T_203; // @[VAlu.scala 126:31]
- wire _supported_T_205 = io_in_bits_1_bits_op == 7'h2e; // @[VAlu.scala 129:16]
- wire _supported_T_206 = _supported_T_204 | _supported_T_205; // @[VAlu.scala 128:31]
- wire _supported_T_207 = io_in_bits_1_bits_op == 7'h30; // @[VAlu.scala 130:16]
- wire _supported_T_208 = _supported_T_206 | _supported_T_207; // @[VAlu.scala 129:32]
- wire _supported_T_209 = io_in_bits_1_bits_op == 7'h27; // @[VAlu.scala 131:16]
- wire _supported_T_210 = _supported_T_208 | _supported_T_209; // @[VAlu.scala 130:30]
- wire _supported_T_211 = io_in_bits_1_bits_op == 7'h28; // @[VAlu.scala 132:16]
- wire _supported_T_212 = _supported_T_210 | _supported_T_211; // @[VAlu.scala 131:29]
- wire _supported_T_213 = io_in_bits_1_bits_op == 7'h2b; // @[VAlu.scala 133:16]
- wire _supported_T_214 = _supported_T_212 | _supported_T_213; // @[VAlu.scala 132:30]
- wire _supported_T_215 = io_in_bits_1_bits_op == 7'h2c; // @[VAlu.scala 134:16]
- wire _supported_T_216 = _supported_T_214 | _supported_T_215; // @[VAlu.scala 133:30]
- wire _supported_T_217 = io_in_bits_1_bits_op == 7'h29; // @[VAlu.scala 135:16]
- wire _supported_T_218 = _supported_T_216 | _supported_T_217; // @[VAlu.scala 134:31]
- wire _supported_T_219 = io_in_bits_1_bits_op == 7'h2a; // @[VAlu.scala 136:16]
- wire _supported_T_220 = _supported_T_218 | _supported_T_219; // @[VAlu.scala 135:30]
- wire _supported_T_221 = io_in_bits_1_bits_op == 7'h2f; // @[VAlu.scala 137:16]
- wire _supported_T_222 = _supported_T_220 | _supported_T_221; // @[VAlu.scala 136:31]
- wire _supported_T_223 = io_in_bits_1_bits_op == 7'h3a; // @[VAlu.scala 139:16]
- wire _supported_T_224 = _supported_T_222 | _supported_T_223; // @[VAlu.scala 137:30]
- wire _supported_T_225 = io_in_bits_1_bits_op == 7'h3d; // @[VAlu.scala 140:16]
- wire _supported_T_226 = _supported_T_224 | _supported_T_225; // @[VAlu.scala 139:33]
- wire _supported_T_227 = io_in_bits_1_bits_op == 7'h3c; // @[VAlu.scala 141:16]
- wire _supported_T_228 = _supported_T_226 | _supported_T_227; // @[VAlu.scala 140:33]
- wire _supported_T_229 = io_in_bits_1_bits_op == 7'h3f; // @[VAlu.scala 142:16]
- wire _supported_T_230 = _supported_T_228 | _supported_T_229; // @[VAlu.scala 141:34]
- wire _supported_T_231 = io_in_bits_1_bits_op == 7'h40; // @[VAlu.scala 143:16]
- wire _supported_T_232 = _supported_T_230 | _supported_T_231; // @[VAlu.scala 142:34]
- wire _supported_T_233 = io_in_bits_1_bits_op == 7'h41; // @[VAlu.scala 144:16]
- wire _supported_T_234 = _supported_T_232 | _supported_T_233; // @[VAlu.scala 143:29]
- wire _supported_T_235 = io_in_bits_1_bits_op == 7'h42; // @[VAlu.scala 145:16]
- wire _supported_T_236 = _supported_T_234 | _supported_T_235; // @[VAlu.scala 144:29]
- wire _supported_T_237 = io_in_bits_1_bits_op == 7'h43; // @[VAlu.scala 146:16]
- wire _supported_T_238 = _supported_T_236 | _supported_T_237; // @[VAlu.scala 145:29]
- wire _supported_T_239 = io_in_bits_1_bits_op == 7'h44; // @[VAlu.scala 147:16]
- wire _supported_T_240 = _supported_T_238 | _supported_T_239; // @[VAlu.scala 146:32]
- wire _supported_T_241 = io_in_bits_1_bits_op == 7'h46; // @[VAlu.scala 149:16]
- wire _supported_T_242 = _supported_T_240 | _supported_T_241; // @[VAlu.scala 147:29]
- wire _supported_T_243 = io_in_bits_1_bits_op == 7'h47; // @[VAlu.scala 150:16]
- wire supported_1 = _supported_T_242 | _supported_T_243; // @[VAlu.scala 149:32]
- wire _T_32 = ~supported_1; // @[VAlu.scala 152:15]
- wire _T_45 = _supported_T_241 | _supported_T_243; // @[VAlu.scala 159:34]
- wire [1:0] sparse_1 = io_in_bits_1_bits_sv_data[3:2]; // @[VAlu.scala 160:50]
- wire _supported_T_245 = io_in_bits_2_bits_op == 7'h35; // @[VAlu.scala 84:16]
- wire _supported_T_246 = io_in_bits_2_bits_op == 7'hf | _supported_T_245; // @[VAlu.scala 83:30]
- wire _supported_T_247 = io_in_bits_2_bits_op == 7'h6; // @[VAlu.scala 85:16]
- wire _supported_T_248 = _supported_T_246 | _supported_T_247; // @[VAlu.scala 84:29]
- wire _supported_T_249 = io_in_bits_2_bits_op == 7'h31; // @[VAlu.scala 86:16]
- wire _supported_T_250 = _supported_T_248 | _supported_T_249; // @[VAlu.scala 85:29]
- wire _supported_T_251 = io_in_bits_2_bits_op == 7'h33; // @[VAlu.scala 87:16]
- wire _supported_T_252 = _supported_T_250 | _supported_T_251; // @[VAlu.scala 86:30]
- wire _supported_T_253 = io_in_bits_2_bits_op == 7'h12; // @[VAlu.scala 88:16]
- wire _supported_T_254 = _supported_T_252 | _supported_T_253; // @[VAlu.scala 87:30]
- wire _supported_T_255 = io_in_bits_2_bits_op == 7'h1; // @[VAlu.scala 89:16]
- wire _supported_T_256 = _supported_T_254 | _supported_T_255; // @[VAlu.scala 88:30]
- wire _supported_T_257 = io_in_bits_2_bits_op == 7'h38; // @[VAlu.scala 90:16]
- wire _supported_T_258 = _supported_T_256 | _supported_T_257; // @[VAlu.scala 89:29]
- wire _supported_T_259 = io_in_bits_2_bits_op == 7'h39; // @[VAlu.scala 91:16]
- wire _supported_T_260 = _supported_T_258 | _supported_T_259; // @[VAlu.scala 90:30]
- wire _supported_T_261 = io_in_bits_2_bits_op == 7'h10; // @[VAlu.scala 92:16]
- wire _supported_T_262 = _supported_T_260 | _supported_T_261; // @[VAlu.scala 91:30]
- wire _supported_T_263 = io_in_bits_2_bits_op == 7'h11; // @[VAlu.scala 93:16]
- wire _supported_T_264 = _supported_T_262 | _supported_T_263; // @[VAlu.scala 92:29]
- wire _supported_T_265 = io_in_bits_2_bits_op == 7'h36; // @[VAlu.scala 94:16]
- wire _supported_T_266 = _supported_T_264 | _supported_T_265; // @[VAlu.scala 93:29]
- wire _supported_T_267 = io_in_bits_2_bits_op == 7'h37; // @[VAlu.scala 95:16]
- wire _supported_T_268 = _supported_T_266 | _supported_T_267; // @[VAlu.scala 94:30]
- wire _supported_T_269 = io_in_bits_2_bits_op == 7'h8; // @[VAlu.scala 96:16]
- wire _supported_T_270 = _supported_T_268 | _supported_T_269; // @[VAlu.scala 95:30]
- wire _supported_T_271 = io_in_bits_2_bits_op == 7'h7; // @[VAlu.scala 97:16]
- wire _supported_T_272 = _supported_T_270 | _supported_T_271; // @[VAlu.scala 96:30]
- wire _supported_T_273 = io_in_bits_2_bits_op == 7'h32; // @[VAlu.scala 98:16]
- wire _supported_T_274 = _supported_T_272 | _supported_T_273; // @[VAlu.scala 97:29]
- wire _supported_T_275 = io_in_bits_2_bits_op == 7'h34; // @[VAlu.scala 99:16]
- wire _supported_T_276 = _supported_T_274 | _supported_T_275; // @[VAlu.scala 98:30]
- wire _supported_T_277 = io_in_bits_2_bits_op == 7'h9; // @[VAlu.scala 101:16]
- wire _supported_T_278 = _supported_T_276 | _supported_T_277; // @[VAlu.scala 99:30]
- wire _supported_T_279 = io_in_bits_2_bits_op == 7'ha; // @[VAlu.scala 102:16]
- wire _supported_T_280 = _supported_T_278 | _supported_T_279; // @[VAlu.scala 101:28]
- wire _supported_T_281 = io_in_bits_2_bits_op == 7'hb; // @[VAlu.scala 103:16]
- wire _supported_T_282 = _supported_T_280 | _supported_T_281; // @[VAlu.scala 102:28]
- wire _supported_T_283 = io_in_bits_2_bits_op == 7'hc; // @[VAlu.scala 104:16]
- wire _supported_T_284 = _supported_T_282 | _supported_T_283; // @[VAlu.scala 103:28]
- wire _supported_T_285 = io_in_bits_2_bits_op == 7'hd; // @[VAlu.scala 105:16]
- wire _supported_T_286 = _supported_T_284 | _supported_T_285; // @[VAlu.scala 104:28]
- wire _supported_T_287 = io_in_bits_2_bits_op == 7'he; // @[VAlu.scala 106:16]
- wire _supported_T_288 = _supported_T_286 | _supported_T_287; // @[VAlu.scala 105:28]
- wire _supported_T_289 = io_in_bits_2_bits_op == 7'h13; // @[VAlu.scala 108:16]
- wire _supported_T_290 = _supported_T_288 | _supported_T_289; // @[VAlu.scala 106:28]
- wire _supported_T_291 = io_in_bits_2_bits_op == 7'h19; // @[VAlu.scala 109:16]
- wire _supported_T_292 = _supported_T_290 | _supported_T_291; // @[VAlu.scala 108:29]
- wire _supported_T_293 = io_in_bits_2_bits_op == 7'h1a; // @[VAlu.scala 110:16]
- wire _supported_T_294 = _supported_T_292 | _supported_T_293; // @[VAlu.scala 109:29]
- wire _supported_T_295 = io_in_bits_2_bits_op == 7'h1b; // @[VAlu.scala 111:16]
- wire _supported_T_296 = _supported_T_294 | _supported_T_295; // @[VAlu.scala 110:29]
- wire _supported_T_297 = io_in_bits_2_bits_op == 7'h1c; // @[VAlu.scala 112:16]
- wire _supported_T_298 = _supported_T_296 | _supported_T_297; // @[VAlu.scala 111:30]
- wire _supported_T_299 = io_in_bits_2_bits_op == 7'h1d; // @[VAlu.scala 113:16]
- wire _supported_T_300 = _supported_T_298 | _supported_T_299; // @[VAlu.scala 112:28]
- wire _supported_T_301 = io_in_bits_2_bits_op == 7'h1e; // @[VAlu.scala 114:16]
- wire _supported_T_302 = _supported_T_300 | _supported_T_301; // @[VAlu.scala 113:29]
- wire _supported_T_303 = io_in_bits_2_bits_op == 7'h21; // @[VAlu.scala 115:16]
- wire _supported_T_304 = _supported_T_302 | _supported_T_303; // @[VAlu.scala 114:29]
- wire _supported_T_305 = io_in_bits_2_bits_op == 7'h16; // @[VAlu.scala 116:16]
- wire _supported_T_306 = _supported_T_304 | _supported_T_305; // @[VAlu.scala 115:32]
- wire _supported_T_307 = io_in_bits_2_bits_op == 7'h14; // @[VAlu.scala 117:16]
- wire _supported_T_308 = _supported_T_306 | _supported_T_307; // @[VAlu.scala 116:29]
- wire _supported_T_309 = io_in_bits_2_bits_op == 7'h17; // @[VAlu.scala 118:16]
- wire _supported_T_310 = _supported_T_308 | _supported_T_309; // @[VAlu.scala 117:28]
- wire _supported_T_311 = io_in_bits_2_bits_op == 7'h18; // @[VAlu.scala 119:16]
- wire _supported_T_312 = _supported_T_310 | _supported_T_311; // @[VAlu.scala 118:29]
- wire _supported_T_313 = io_in_bits_2_bits_op == 7'h15; // @[VAlu.scala 120:16]
- wire _supported_T_314 = _supported_T_312 | _supported_T_313; // @[VAlu.scala 119:29]
- wire _supported_T_315 = io_in_bits_2_bits_op == 7'h22; // @[VAlu.scala 122:16]
- wire _supported_T_316 = _supported_T_314 | _supported_T_315; // @[VAlu.scala 120:29]
- wire _supported_T_317 = io_in_bits_2_bits_op == 7'h23; // @[VAlu.scala 123:16]
- wire _supported_T_318 = _supported_T_316 | _supported_T_317; // @[VAlu.scala 122:29]
- wire _supported_T_319 = io_in_bits_2_bits_op == 7'h24; // @[VAlu.scala 124:16]
- wire _supported_T_320 = _supported_T_318 | _supported_T_319; // @[VAlu.scala 123:29]
- wire _supported_T_321 = io_in_bits_2_bits_op == 7'h25; // @[VAlu.scala 125:16]
- wire _supported_T_322 = _supported_T_320 | _supported_T_321; // @[VAlu.scala 124:29]
- wire _supported_T_323 = io_in_bits_2_bits_op == 7'h26; // @[VAlu.scala 126:16]
- wire _supported_T_324 = _supported_T_322 | _supported_T_323; // @[VAlu.scala 125:31]
- wire _supported_T_325 = io_in_bits_2_bits_op == 7'h2d; // @[VAlu.scala 128:16]
- wire _supported_T_326 = _supported_T_324 | _supported_T_325; // @[VAlu.scala 126:31]
- wire _supported_T_327 = io_in_bits_2_bits_op == 7'h2e; // @[VAlu.scala 129:16]
- wire _supported_T_328 = _supported_T_326 | _supported_T_327; // @[VAlu.scala 128:31]
- wire _supported_T_329 = io_in_bits_2_bits_op == 7'h30; // @[VAlu.scala 130:16]
- wire _supported_T_330 = _supported_T_328 | _supported_T_329; // @[VAlu.scala 129:32]
- wire _supported_T_331 = io_in_bits_2_bits_op == 7'h27; // @[VAlu.scala 131:16]
- wire _supported_T_332 = _supported_T_330 | _supported_T_331; // @[VAlu.scala 130:30]
- wire _supported_T_333 = io_in_bits_2_bits_op == 7'h28; // @[VAlu.scala 132:16]
- wire _supported_T_334 = _supported_T_332 | _supported_T_333; // @[VAlu.scala 131:29]
- wire _supported_T_335 = io_in_bits_2_bits_op == 7'h2b; // @[VAlu.scala 133:16]
- wire _supported_T_336 = _supported_T_334 | _supported_T_335; // @[VAlu.scala 132:30]
- wire _supported_T_337 = io_in_bits_2_bits_op == 7'h2c; // @[VAlu.scala 134:16]
- wire _supported_T_338 = _supported_T_336 | _supported_T_337; // @[VAlu.scala 133:30]
- wire _supported_T_339 = io_in_bits_2_bits_op == 7'h29; // @[VAlu.scala 135:16]
- wire _supported_T_340 = _supported_T_338 | _supported_T_339; // @[VAlu.scala 134:31]
- wire _supported_T_341 = io_in_bits_2_bits_op == 7'h2a; // @[VAlu.scala 136:16]
- wire _supported_T_342 = _supported_T_340 | _supported_T_341; // @[VAlu.scala 135:30]
- wire _supported_T_343 = io_in_bits_2_bits_op == 7'h2f; // @[VAlu.scala 137:16]
- wire _supported_T_344 = _supported_T_342 | _supported_T_343; // @[VAlu.scala 136:31]
- wire _supported_T_345 = io_in_bits_2_bits_op == 7'h3a; // @[VAlu.scala 139:16]
- wire _supported_T_346 = _supported_T_344 | _supported_T_345; // @[VAlu.scala 137:30]
- wire _supported_T_347 = io_in_bits_2_bits_op == 7'h3d; // @[VAlu.scala 140:16]
- wire _supported_T_348 = _supported_T_346 | _supported_T_347; // @[VAlu.scala 139:33]
- wire _supported_T_349 = io_in_bits_2_bits_op == 7'h3c; // @[VAlu.scala 141:16]
- wire _supported_T_350 = _supported_T_348 | _supported_T_349; // @[VAlu.scala 140:33]
- wire _supported_T_351 = io_in_bits_2_bits_op == 7'h3f; // @[VAlu.scala 142:16]
- wire _supported_T_352 = _supported_T_350 | _supported_T_351; // @[VAlu.scala 141:34]
- wire _supported_T_353 = io_in_bits_2_bits_op == 7'h40; // @[VAlu.scala 143:16]
- wire _supported_T_354 = _supported_T_352 | _supported_T_353; // @[VAlu.scala 142:34]
- wire _supported_T_355 = io_in_bits_2_bits_op == 7'h41; // @[VAlu.scala 144:16]
- wire _supported_T_356 = _supported_T_354 | _supported_T_355; // @[VAlu.scala 143:29]
- wire _supported_T_357 = io_in_bits_2_bits_op == 7'h42; // @[VAlu.scala 145:16]
- wire _supported_T_358 = _supported_T_356 | _supported_T_357; // @[VAlu.scala 144:29]
- wire _supported_T_359 = io_in_bits_2_bits_op == 7'h43; // @[VAlu.scala 146:16]
- wire _supported_T_360 = _supported_T_358 | _supported_T_359; // @[VAlu.scala 145:29]
- wire _supported_T_361 = io_in_bits_2_bits_op == 7'h44; // @[VAlu.scala 147:16]
- wire _supported_T_362 = _supported_T_360 | _supported_T_361; // @[VAlu.scala 146:32]
- wire _supported_T_363 = io_in_bits_2_bits_op == 7'h46; // @[VAlu.scala 149:16]
- wire _supported_T_364 = _supported_T_362 | _supported_T_363; // @[VAlu.scala 147:29]
- wire _supported_T_365 = io_in_bits_2_bits_op == 7'h47; // @[VAlu.scala 150:16]
- wire supported_2 = _supported_T_364 | _supported_T_365; // @[VAlu.scala 149:32]
- wire _T_63 = ~supported_2; // @[VAlu.scala 152:15]
- wire _T_76 = _supported_T_363 | _supported_T_365; // @[VAlu.scala 159:34]
- wire [1:0] sparse_2 = io_in_bits_2_bits_sv_data[3:2]; // @[VAlu.scala 160:50]
- wire _supported_T_367 = io_in_bits_3_bits_op == 7'h35; // @[VAlu.scala 84:16]
- wire _supported_T_368 = io_in_bits_3_bits_op == 7'hf | _supported_T_367; // @[VAlu.scala 83:30]
- wire _supported_T_369 = io_in_bits_3_bits_op == 7'h6; // @[VAlu.scala 85:16]
- wire _supported_T_370 = _supported_T_368 | _supported_T_369; // @[VAlu.scala 84:29]
- wire _supported_T_371 = io_in_bits_3_bits_op == 7'h31; // @[VAlu.scala 86:16]
- wire _supported_T_372 = _supported_T_370 | _supported_T_371; // @[VAlu.scala 85:29]
- wire _supported_T_373 = io_in_bits_3_bits_op == 7'h33; // @[VAlu.scala 87:16]
- wire _supported_T_374 = _supported_T_372 | _supported_T_373; // @[VAlu.scala 86:30]
- wire _supported_T_375 = io_in_bits_3_bits_op == 7'h12; // @[VAlu.scala 88:16]
- wire _supported_T_376 = _supported_T_374 | _supported_T_375; // @[VAlu.scala 87:30]
- wire _supported_T_377 = io_in_bits_3_bits_op == 7'h1; // @[VAlu.scala 89:16]
- wire _supported_T_378 = _supported_T_376 | _supported_T_377; // @[VAlu.scala 88:30]
- wire _supported_T_379 = io_in_bits_3_bits_op == 7'h38; // @[VAlu.scala 90:16]
- wire _supported_T_380 = _supported_T_378 | _supported_T_379; // @[VAlu.scala 89:29]
- wire _supported_T_381 = io_in_bits_3_bits_op == 7'h39; // @[VAlu.scala 91:16]
- wire _supported_T_382 = _supported_T_380 | _supported_T_381; // @[VAlu.scala 90:30]
- wire _supported_T_383 = io_in_bits_3_bits_op == 7'h10; // @[VAlu.scala 92:16]
- wire _supported_T_384 = _supported_T_382 | _supported_T_383; // @[VAlu.scala 91:30]
- wire _supported_T_385 = io_in_bits_3_bits_op == 7'h11; // @[VAlu.scala 93:16]
- wire _supported_T_386 = _supported_T_384 | _supported_T_385; // @[VAlu.scala 92:29]
- wire _supported_T_387 = io_in_bits_3_bits_op == 7'h36; // @[VAlu.scala 94:16]
- wire _supported_T_388 = _supported_T_386 | _supported_T_387; // @[VAlu.scala 93:29]
- wire _supported_T_389 = io_in_bits_3_bits_op == 7'h37; // @[VAlu.scala 95:16]
- wire _supported_T_390 = _supported_T_388 | _supported_T_389; // @[VAlu.scala 94:30]
- wire _supported_T_391 = io_in_bits_3_bits_op == 7'h8; // @[VAlu.scala 96:16]
- wire _supported_T_392 = _supported_T_390 | _supported_T_391; // @[VAlu.scala 95:30]
- wire _supported_T_393 = io_in_bits_3_bits_op == 7'h7; // @[VAlu.scala 97:16]
- wire _supported_T_394 = _supported_T_392 | _supported_T_393; // @[VAlu.scala 96:30]
- wire _supported_T_395 = io_in_bits_3_bits_op == 7'h32; // @[VAlu.scala 98:16]
- wire _supported_T_396 = _supported_T_394 | _supported_T_395; // @[VAlu.scala 97:29]
- wire _supported_T_397 = io_in_bits_3_bits_op == 7'h34; // @[VAlu.scala 99:16]
- wire _supported_T_398 = _supported_T_396 | _supported_T_397; // @[VAlu.scala 98:30]
- wire _supported_T_399 = io_in_bits_3_bits_op == 7'h9; // @[VAlu.scala 101:16]
- wire _supported_T_400 = _supported_T_398 | _supported_T_399; // @[VAlu.scala 99:30]
- wire _supported_T_401 = io_in_bits_3_bits_op == 7'ha; // @[VAlu.scala 102:16]
- wire _supported_T_402 = _supported_T_400 | _supported_T_401; // @[VAlu.scala 101:28]
- wire _supported_T_403 = io_in_bits_3_bits_op == 7'hb; // @[VAlu.scala 103:16]
- wire _supported_T_404 = _supported_T_402 | _supported_T_403; // @[VAlu.scala 102:28]
- wire _supported_T_405 = io_in_bits_3_bits_op == 7'hc; // @[VAlu.scala 104:16]
- wire _supported_T_406 = _supported_T_404 | _supported_T_405; // @[VAlu.scala 103:28]
- wire _supported_T_407 = io_in_bits_3_bits_op == 7'hd; // @[VAlu.scala 105:16]
- wire _supported_T_408 = _supported_T_406 | _supported_T_407; // @[VAlu.scala 104:28]
- wire _supported_T_409 = io_in_bits_3_bits_op == 7'he; // @[VAlu.scala 106:16]
- wire _supported_T_410 = _supported_T_408 | _supported_T_409; // @[VAlu.scala 105:28]
- wire _supported_T_411 = io_in_bits_3_bits_op == 7'h13; // @[VAlu.scala 108:16]
- wire _supported_T_412 = _supported_T_410 | _supported_T_411; // @[VAlu.scala 106:28]
- wire _supported_T_413 = io_in_bits_3_bits_op == 7'h19; // @[VAlu.scala 109:16]
- wire _supported_T_414 = _supported_T_412 | _supported_T_413; // @[VAlu.scala 108:29]
- wire _supported_T_415 = io_in_bits_3_bits_op == 7'h1a; // @[VAlu.scala 110:16]
- wire _supported_T_416 = _supported_T_414 | _supported_T_415; // @[VAlu.scala 109:29]
- wire _supported_T_417 = io_in_bits_3_bits_op == 7'h1b; // @[VAlu.scala 111:16]
- wire _supported_T_418 = _supported_T_416 | _supported_T_417; // @[VAlu.scala 110:29]
- wire _supported_T_419 = io_in_bits_3_bits_op == 7'h1c; // @[VAlu.scala 112:16]
- wire _supported_T_420 = _supported_T_418 | _supported_T_419; // @[VAlu.scala 111:30]
- wire _supported_T_421 = io_in_bits_3_bits_op == 7'h1d; // @[VAlu.scala 113:16]
- wire _supported_T_422 = _supported_T_420 | _supported_T_421; // @[VAlu.scala 112:28]
- wire _supported_T_423 = io_in_bits_3_bits_op == 7'h1e; // @[VAlu.scala 114:16]
- wire _supported_T_424 = _supported_T_422 | _supported_T_423; // @[VAlu.scala 113:29]
- wire _supported_T_425 = io_in_bits_3_bits_op == 7'h21; // @[VAlu.scala 115:16]
- wire _supported_T_426 = _supported_T_424 | _supported_T_425; // @[VAlu.scala 114:29]
- wire _supported_T_427 = io_in_bits_3_bits_op == 7'h16; // @[VAlu.scala 116:16]
- wire _supported_T_428 = _supported_T_426 | _supported_T_427; // @[VAlu.scala 115:32]
- wire _supported_T_429 = io_in_bits_3_bits_op == 7'h14; // @[VAlu.scala 117:16]
- wire _supported_T_430 = _supported_T_428 | _supported_T_429; // @[VAlu.scala 116:29]
- wire _supported_T_431 = io_in_bits_3_bits_op == 7'h17; // @[VAlu.scala 118:16]
- wire _supported_T_432 = _supported_T_430 | _supported_T_431; // @[VAlu.scala 117:28]
- wire _supported_T_433 = io_in_bits_3_bits_op == 7'h18; // @[VAlu.scala 119:16]
- wire _supported_T_434 = _supported_T_432 | _supported_T_433; // @[VAlu.scala 118:29]
- wire _supported_T_435 = io_in_bits_3_bits_op == 7'h15; // @[VAlu.scala 120:16]
- wire _supported_T_436 = _supported_T_434 | _supported_T_435; // @[VAlu.scala 119:29]
- wire _supported_T_437 = io_in_bits_3_bits_op == 7'h22; // @[VAlu.scala 122:16]
- wire _supported_T_438 = _supported_T_436 | _supported_T_437; // @[VAlu.scala 120:29]
- wire _supported_T_439 = io_in_bits_3_bits_op == 7'h23; // @[VAlu.scala 123:16]
- wire _supported_T_440 = _supported_T_438 | _supported_T_439; // @[VAlu.scala 122:29]
- wire _supported_T_441 = io_in_bits_3_bits_op == 7'h24; // @[VAlu.scala 124:16]
- wire _supported_T_442 = _supported_T_440 | _supported_T_441; // @[VAlu.scala 123:29]
- wire _supported_T_443 = io_in_bits_3_bits_op == 7'h25; // @[VAlu.scala 125:16]
- wire _supported_T_444 = _supported_T_442 | _supported_T_443; // @[VAlu.scala 124:29]
- wire _supported_T_445 = io_in_bits_3_bits_op == 7'h26; // @[VAlu.scala 126:16]
- wire _supported_T_446 = _supported_T_444 | _supported_T_445; // @[VAlu.scala 125:31]
- wire _supported_T_447 = io_in_bits_3_bits_op == 7'h2d; // @[VAlu.scala 128:16]
- wire _supported_T_448 = _supported_T_446 | _supported_T_447; // @[VAlu.scala 126:31]
- wire _supported_T_449 = io_in_bits_3_bits_op == 7'h2e; // @[VAlu.scala 129:16]
- wire _supported_T_450 = _supported_T_448 | _supported_T_449; // @[VAlu.scala 128:31]
- wire _supported_T_451 = io_in_bits_3_bits_op == 7'h30; // @[VAlu.scala 130:16]
- wire _supported_T_452 = _supported_T_450 | _supported_T_451; // @[VAlu.scala 129:32]
- wire _supported_T_453 = io_in_bits_3_bits_op == 7'h27; // @[VAlu.scala 131:16]
- wire _supported_T_454 = _supported_T_452 | _supported_T_453; // @[VAlu.scala 130:30]
- wire _supported_T_455 = io_in_bits_3_bits_op == 7'h28; // @[VAlu.scala 132:16]
- wire _supported_T_456 = _supported_T_454 | _supported_T_455; // @[VAlu.scala 131:29]
- wire _supported_T_457 = io_in_bits_3_bits_op == 7'h2b; // @[VAlu.scala 133:16]
- wire _supported_T_458 = _supported_T_456 | _supported_T_457; // @[VAlu.scala 132:30]
- wire _supported_T_459 = io_in_bits_3_bits_op == 7'h2c; // @[VAlu.scala 134:16]
- wire _supported_T_460 = _supported_T_458 | _supported_T_459; // @[VAlu.scala 133:30]
- wire _supported_T_461 = io_in_bits_3_bits_op == 7'h29; // @[VAlu.scala 135:16]
- wire _supported_T_462 = _supported_T_460 | _supported_T_461; // @[VAlu.scala 134:31]
- wire _supported_T_463 = io_in_bits_3_bits_op == 7'h2a; // @[VAlu.scala 136:16]
- wire _supported_T_464 = _supported_T_462 | _supported_T_463; // @[VAlu.scala 135:30]
- wire _supported_T_465 = io_in_bits_3_bits_op == 7'h2f; // @[VAlu.scala 137:16]
- wire _supported_T_466 = _supported_T_464 | _supported_T_465; // @[VAlu.scala 136:31]
- wire _supported_T_467 = io_in_bits_3_bits_op == 7'h3a; // @[VAlu.scala 139:16]
- wire _supported_T_468 = _supported_T_466 | _supported_T_467; // @[VAlu.scala 137:30]
- wire _supported_T_469 = io_in_bits_3_bits_op == 7'h3d; // @[VAlu.scala 140:16]
- wire _supported_T_470 = _supported_T_468 | _supported_T_469; // @[VAlu.scala 139:33]
- wire _supported_T_471 = io_in_bits_3_bits_op == 7'h3c; // @[VAlu.scala 141:16]
- wire _supported_T_472 = _supported_T_470 | _supported_T_471; // @[VAlu.scala 140:33]
- wire _supported_T_473 = io_in_bits_3_bits_op == 7'h3f; // @[VAlu.scala 142:16]
- wire _supported_T_474 = _supported_T_472 | _supported_T_473; // @[VAlu.scala 141:34]
- wire _supported_T_475 = io_in_bits_3_bits_op == 7'h40; // @[VAlu.scala 143:16]
- wire _supported_T_476 = _supported_T_474 | _supported_T_475; // @[VAlu.scala 142:34]
- wire _supported_T_477 = io_in_bits_3_bits_op == 7'h41; // @[VAlu.scala 144:16]
- wire _supported_T_478 = _supported_T_476 | _supported_T_477; // @[VAlu.scala 143:29]
- wire _supported_T_479 = io_in_bits_3_bits_op == 7'h42; // @[VAlu.scala 145:16]
- wire _supported_T_480 = _supported_T_478 | _supported_T_479; // @[VAlu.scala 144:29]
- wire _supported_T_481 = io_in_bits_3_bits_op == 7'h43; // @[VAlu.scala 146:16]
- wire _supported_T_482 = _supported_T_480 | _supported_T_481; // @[VAlu.scala 145:29]
- wire _supported_T_483 = io_in_bits_3_bits_op == 7'h44; // @[VAlu.scala 147:16]
- wire _supported_T_484 = _supported_T_482 | _supported_T_483; // @[VAlu.scala 146:32]
- wire _supported_T_485 = io_in_bits_3_bits_op == 7'h46; // @[VAlu.scala 149:16]
- wire _supported_T_486 = _supported_T_484 | _supported_T_485; // @[VAlu.scala 147:29]
- wire _supported_T_487 = io_in_bits_3_bits_op == 7'h47; // @[VAlu.scala 150:16]
- wire supported_3 = _supported_T_486 | _supported_T_487; // @[VAlu.scala 149:32]
- wire _T_94 = ~supported_3; // @[VAlu.scala 152:15]
- wire _T_107 = _supported_T_485 | _supported_T_487; // @[VAlu.scala 159:34]
- wire [1:0] sparse_3 = io_in_bits_3_bits_sv_data[3:2]; // @[VAlu.scala 160:50]
- wire [3:0] _q0ready_tag_T_1 = q0_io_out_bits_vs_tag >> q0_io_out_bits_vs_addr[1:0]; // @[VCommon.scala 135:20]
- wire q0ready_tag = _q0ready_tag_T_1[0]; // @[VCommon.scala 135:20]
- wire [6:0] q0ready_idx = {q0ready_tag,q0_io_out_bits_vs_addr}; // @[Cat.scala 31:58]
- wire [127:0] _q0ready_T_1 = io_vrfsb >> q0ready_idx; // @[VCommon.scala 138:21]
- wire _q0ready_T_4 = ~q0_io_out_bits_vs_valid | ~_q0ready_T_1[0]; // @[VCommon.scala 138:15]
- wire [3:0] _q0ready_tag_T_3 = q0_io_out_bits_vt_tag >> q0_io_out_bits_vt_addr[1:0]; // @[VCommon.scala 135:20]
- wire q0ready_tag_1 = _q0ready_tag_T_3[0]; // @[VCommon.scala 135:20]
- wire [6:0] q0ready_idx_1 = {q0ready_tag_1,q0_io_out_bits_vt_addr}; // @[Cat.scala 31:58]
- wire [127:0] _q0ready_T_6 = io_vrfsb >> q0ready_idx_1; // @[VCommon.scala 138:21]
- wire _q0ready_T_9 = ~q0_io_out_bits_vt_valid | ~_q0ready_T_6[0]; // @[VCommon.scala 138:15]
- wire _q0ready_T_10 = _q0ready_T_4 & _q0ready_T_9; // @[VAlu.scala 266:62]
- wire [3:0] _q0ready_tag_T_5 = q0_io_out_bits_vu_tag >> q0_io_out_bits_vu_addr[1:0]; // @[VCommon.scala 135:20]
- wire q0ready_tag_2 = _q0ready_tag_T_5[0]; // @[VCommon.scala 135:20]
- wire [6:0] q0ready_idx_2 = {q0ready_tag_2,q0_io_out_bits_vu_addr}; // @[Cat.scala 31:58]
- wire [127:0] _q0ready_T_12 = io_vrfsb >> q0ready_idx_2; // @[VCommon.scala 138:21]
- wire _q0ready_T_15 = ~q0_io_out_bits_vu_valid | ~_q0ready_T_12[0]; // @[VCommon.scala 138:15]
- wire q0ready = _q0ready_T_10 & _q0ready_T_15; // @[VAlu.scala 267:62]
- wire [3:0] _q1ready_tag_T_1 = q1_io_out_bits_vs_tag >> q1_io_out_bits_vs_addr[1:0]; // @[VCommon.scala 135:20]
- wire q1ready_tag = _q1ready_tag_T_1[0]; // @[VCommon.scala 135:20]
- wire [6:0] q1ready_idx = {q1ready_tag,q1_io_out_bits_vs_addr}; // @[Cat.scala 31:58]
- wire [127:0] _q1ready_T_1 = io_vrfsb >> q1ready_idx; // @[VCommon.scala 138:21]
- wire _q1ready_T_4 = ~q1_io_out_bits_vs_valid | ~_q1ready_T_1[0]; // @[VCommon.scala 138:15]
- wire [3:0] _q1ready_tag_T_3 = q1_io_out_bits_vt_tag >> q1_io_out_bits_vt_addr[1:0]; // @[VCommon.scala 135:20]
- wire q1ready_tag_1 = _q1ready_tag_T_3[0]; // @[VCommon.scala 135:20]
- wire [6:0] q1ready_idx_1 = {q1ready_tag_1,q1_io_out_bits_vt_addr}; // @[Cat.scala 31:58]
- wire [127:0] _q1ready_T_6 = io_vrfsb >> q1ready_idx_1; // @[VCommon.scala 138:21]
- wire _q1ready_T_9 = ~q1_io_out_bits_vt_valid | ~_q1ready_T_6[0]; // @[VCommon.scala 138:15]
- wire _q1ready_T_10 = _q1ready_T_4 & _q1ready_T_9; // @[VAlu.scala 270:62]
- wire [3:0] _q1ready_tag_T_5 = q1_io_out_bits_vu_tag >> q1_io_out_bits_vu_addr[1:0]; // @[VCommon.scala 135:20]
- wire q1ready_tag_2 = _q1ready_tag_T_5[0]; // @[VCommon.scala 135:20]
- wire [6:0] q1ready_idx_2 = {q1ready_tag_2,q1_io_out_bits_vu_addr}; // @[Cat.scala 31:58]
- wire [127:0] _q1ready_T_12 = io_vrfsb >> q1ready_idx_2; // @[VCommon.scala 138:21]
- wire _q1ready_T_15 = ~q1_io_out_bits_vu_valid | ~_q1ready_T_12[0]; // @[VCommon.scala 138:15]
- wire q1ready = _q1ready_T_10 & _q1ready_T_15; // @[VAlu.scala 271:62]
- reg alureg; // @[VAlu.scala 279:23]
- wire _alusel_1_T_2 = ~alureg; // @[VAlu.scala 284:72]
- wire alusel_1 = io_in_bits_0_valid & ~io_in_bits_0_bits_cmdsync ? ~alureg : alureg; // @[VAlu.scala 284:19]
- wire _alusel_2_T_2 = ~alusel_1; // @[VAlu.scala 285:72]
- wire alusel_2 = io_in_bits_1_valid & ~io_in_bits_1_bits_cmdsync ? ~alusel_1 : alusel_1; // @[VAlu.scala 285:19]
- wire _alusel_3_T_2 = ~alusel_2; // @[VAlu.scala 286:72]
- wire alusel_3 = io_in_bits_2_valid & ~io_in_bits_2_bits_cmdsync ? ~alusel_2 : alusel_2; // @[VAlu.scala 286:19]
- wire _alusel_4_T_2 = ~alusel_3; // @[VAlu.scala 287:72]
- wire _GEN_1 = _T & io_in_bits_0_valid; // @[VAlu.scala 153:17]
- wire _GEN_4 = _GEN_1 & _T_3; // @[VAlu.scala 155:15]
- wire _GEN_15 = _GEN_1 & _T_14 & _T_3; // @[VAlu.scala 161:17]
- wire _GEN_41 = _T & io_in_bits_1_valid; // @[VAlu.scala 153:17]
- wire _GEN_44 = _GEN_41 & _T_3; // @[VAlu.scala 155:15]
- wire _GEN_55 = _GEN_41 & _T_45 & _T_3; // @[VAlu.scala 161:17]
- wire _GEN_81 = _T & io_in_bits_2_valid; // @[VAlu.scala 153:17]
- wire _GEN_84 = _GEN_81 & _T_3; // @[VAlu.scala 155:15]
- wire _GEN_95 = _GEN_81 & _T_76 & _T_3; // @[VAlu.scala 161:17]
- wire _GEN_121 = _T & io_in_bits_3_valid; // @[VAlu.scala 153:17]
- wire _GEN_124 = _GEN_121 & _T_3; // @[VAlu.scala 155:15]
- wire _GEN_135 = _GEN_121 & _T_107 & _T_3; // @[VAlu.scala 161:17]
- VCmdq q0 ( // @[VCmdq.scala 30:11]
- .clock(q0_clock),
- .reset(q0_reset),
- .io_in_ready(q0_io_in_ready),
- .io_in_valid(q0_io_in_valid),
- .io_in_bits_0_valid(q0_io_in_bits_0_valid),
- .io_in_bits_0_bits_op(q0_io_in_bits_0_bits_op),
- .io_in_bits_0_bits_f2(q0_io_in_bits_0_bits_f2),
- .io_in_bits_0_bits_sz(q0_io_in_bits_0_bits_sz),
- .io_in_bits_0_bits_m(q0_io_in_bits_0_bits_m),
- .io_in_bits_0_bits_vd_addr(q0_io_in_bits_0_bits_vd_addr),
- .io_in_bits_0_bits_ve_addr(q0_io_in_bits_0_bits_ve_addr),
- .io_in_bits_0_bits_vs_valid(q0_io_in_bits_0_bits_vs_valid),
- .io_in_bits_0_bits_vs_addr(q0_io_in_bits_0_bits_vs_addr),
- .io_in_bits_0_bits_vs_tag(q0_io_in_bits_0_bits_vs_tag),
- .io_in_bits_0_bits_vt_valid(q0_io_in_bits_0_bits_vt_valid),
- .io_in_bits_0_bits_vt_addr(q0_io_in_bits_0_bits_vt_addr),
- .io_in_bits_0_bits_vt_tag(q0_io_in_bits_0_bits_vt_tag),
- .io_in_bits_0_bits_vu_valid(q0_io_in_bits_0_bits_vu_valid),
- .io_in_bits_0_bits_vu_addr(q0_io_in_bits_0_bits_vu_addr),
- .io_in_bits_0_bits_vu_tag(q0_io_in_bits_0_bits_vu_tag),
- .io_in_bits_0_bits_sv_valid(q0_io_in_bits_0_bits_sv_valid),
- .io_in_bits_0_bits_sv_data(q0_io_in_bits_0_bits_sv_data),
- .io_in_bits_0_bits_cmdsync(q0_io_in_bits_0_bits_cmdsync),
- .io_in_bits_1_valid(q0_io_in_bits_1_valid),
- .io_in_bits_1_bits_op(q0_io_in_bits_1_bits_op),
- .io_in_bits_1_bits_f2(q0_io_in_bits_1_bits_f2),
- .io_in_bits_1_bits_sz(q0_io_in_bits_1_bits_sz),
- .io_in_bits_1_bits_m(q0_io_in_bits_1_bits_m),
- .io_in_bits_1_bits_vd_addr(q0_io_in_bits_1_bits_vd_addr),
- .io_in_bits_1_bits_ve_addr(q0_io_in_bits_1_bits_ve_addr),
- .io_in_bits_1_bits_vs_valid(q0_io_in_bits_1_bits_vs_valid),
- .io_in_bits_1_bits_vs_addr(q0_io_in_bits_1_bits_vs_addr),
- .io_in_bits_1_bits_vs_tag(q0_io_in_bits_1_bits_vs_tag),
- .io_in_bits_1_bits_vt_valid(q0_io_in_bits_1_bits_vt_valid),
- .io_in_bits_1_bits_vt_addr(q0_io_in_bits_1_bits_vt_addr),
- .io_in_bits_1_bits_vt_tag(q0_io_in_bits_1_bits_vt_tag),
- .io_in_bits_1_bits_vu_valid(q0_io_in_bits_1_bits_vu_valid),
- .io_in_bits_1_bits_vu_addr(q0_io_in_bits_1_bits_vu_addr),
- .io_in_bits_1_bits_vu_tag(q0_io_in_bits_1_bits_vu_tag),
- .io_in_bits_1_bits_sv_valid(q0_io_in_bits_1_bits_sv_valid),
- .io_in_bits_1_bits_sv_data(q0_io_in_bits_1_bits_sv_data),
- .io_in_bits_1_bits_cmdsync(q0_io_in_bits_1_bits_cmdsync),
- .io_in_bits_2_valid(q0_io_in_bits_2_valid),
- .io_in_bits_2_bits_op(q0_io_in_bits_2_bits_op),
- .io_in_bits_2_bits_f2(q0_io_in_bits_2_bits_f2),
- .io_in_bits_2_bits_sz(q0_io_in_bits_2_bits_sz),
- .io_in_bits_2_bits_m(q0_io_in_bits_2_bits_m),
- .io_in_bits_2_bits_vd_addr(q0_io_in_bits_2_bits_vd_addr),
- .io_in_bits_2_bits_ve_addr(q0_io_in_bits_2_bits_ve_addr),
- .io_in_bits_2_bits_vs_valid(q0_io_in_bits_2_bits_vs_valid),
- .io_in_bits_2_bits_vs_addr(q0_io_in_bits_2_bits_vs_addr),
- .io_in_bits_2_bits_vs_tag(q0_io_in_bits_2_bits_vs_tag),
- .io_in_bits_2_bits_vt_valid(q0_io_in_bits_2_bits_vt_valid),
- .io_in_bits_2_bits_vt_addr(q0_io_in_bits_2_bits_vt_addr),
- .io_in_bits_2_bits_vt_tag(q0_io_in_bits_2_bits_vt_tag),
- .io_in_bits_2_bits_vu_valid(q0_io_in_bits_2_bits_vu_valid),
- .io_in_bits_2_bits_vu_addr(q0_io_in_bits_2_bits_vu_addr),
- .io_in_bits_2_bits_vu_tag(q0_io_in_bits_2_bits_vu_tag),
- .io_in_bits_2_bits_sv_valid(q0_io_in_bits_2_bits_sv_valid),
- .io_in_bits_2_bits_sv_data(q0_io_in_bits_2_bits_sv_data),
- .io_in_bits_2_bits_cmdsync(q0_io_in_bits_2_bits_cmdsync),
- .io_in_bits_3_valid(q0_io_in_bits_3_valid),
- .io_in_bits_3_bits_op(q0_io_in_bits_3_bits_op),
- .io_in_bits_3_bits_f2(q0_io_in_bits_3_bits_f2),
- .io_in_bits_3_bits_sz(q0_io_in_bits_3_bits_sz),
- .io_in_bits_3_bits_m(q0_io_in_bits_3_bits_m),
- .io_in_bits_3_bits_vd_addr(q0_io_in_bits_3_bits_vd_addr),
- .io_in_bits_3_bits_ve_addr(q0_io_in_bits_3_bits_ve_addr),
- .io_in_bits_3_bits_vs_valid(q0_io_in_bits_3_bits_vs_valid),
- .io_in_bits_3_bits_vs_addr(q0_io_in_bits_3_bits_vs_addr),
- .io_in_bits_3_bits_vs_tag(q0_io_in_bits_3_bits_vs_tag),
- .io_in_bits_3_bits_vt_valid(q0_io_in_bits_3_bits_vt_valid),
- .io_in_bits_3_bits_vt_addr(q0_io_in_bits_3_bits_vt_addr),
- .io_in_bits_3_bits_vt_tag(q0_io_in_bits_3_bits_vt_tag),
- .io_in_bits_3_bits_vu_valid(q0_io_in_bits_3_bits_vu_valid),
- .io_in_bits_3_bits_vu_addr(q0_io_in_bits_3_bits_vu_addr),
- .io_in_bits_3_bits_vu_tag(q0_io_in_bits_3_bits_vu_tag),
- .io_in_bits_3_bits_sv_valid(q0_io_in_bits_3_bits_sv_valid),
- .io_in_bits_3_bits_sv_data(q0_io_in_bits_3_bits_sv_data),
- .io_in_bits_3_bits_cmdsync(q0_io_in_bits_3_bits_cmdsync),
- .io_out_ready(q0_io_out_ready),
- .io_out_valid(q0_io_out_valid),
- .io_out_bits_op(q0_io_out_bits_op),
- .io_out_bits_f2(q0_io_out_bits_f2),
- .io_out_bits_sz(q0_io_out_bits_sz),
- .io_out_bits_vd_addr(q0_io_out_bits_vd_addr),
- .io_out_bits_ve_addr(q0_io_out_bits_ve_addr),
- .io_out_bits_vs_valid(q0_io_out_bits_vs_valid),
- .io_out_bits_vs_addr(q0_io_out_bits_vs_addr),
- .io_out_bits_vs_tag(q0_io_out_bits_vs_tag),
- .io_out_bits_vt_valid(q0_io_out_bits_vt_valid),
- .io_out_bits_vt_addr(q0_io_out_bits_vt_addr),
- .io_out_bits_vt_tag(q0_io_out_bits_vt_tag),
- .io_out_bits_vu_valid(q0_io_out_bits_vu_valid),
- .io_out_bits_vu_addr(q0_io_out_bits_vu_addr),
- .io_out_bits_vu_tag(q0_io_out_bits_vu_tag),
- .io_out_bits_sv_valid(q0_io_out_bits_sv_valid),
- .io_out_bits_sv_data(q0_io_out_bits_sv_data),
- .io_out_bits_cmdsync(q0_io_out_bits_cmdsync),
- .io_active(q0_io_active)
- );
- VCmdq_1 q1 ( // @[VCmdq.scala 30:11]
- .clock(q1_clock),
- .reset(q1_reset),
- .io_in_ready(q1_io_in_ready),
- .io_in_valid(q1_io_in_valid),
- .io_in_bits_0_valid(q1_io_in_bits_0_valid),
- .io_in_bits_0_bits_op(q1_io_in_bits_0_bits_op),
- .io_in_bits_0_bits_f2(q1_io_in_bits_0_bits_f2),
- .io_in_bits_0_bits_sz(q1_io_in_bits_0_bits_sz),
- .io_in_bits_0_bits_m(q1_io_in_bits_0_bits_m),
- .io_in_bits_0_bits_vd_addr(q1_io_in_bits_0_bits_vd_addr),
- .io_in_bits_0_bits_ve_addr(q1_io_in_bits_0_bits_ve_addr),
- .io_in_bits_0_bits_vf_addr(q1_io_in_bits_0_bits_vf_addr),
- .io_in_bits_0_bits_vg_addr(q1_io_in_bits_0_bits_vg_addr),
- .io_in_bits_0_bits_vs_valid(q1_io_in_bits_0_bits_vs_valid),
- .io_in_bits_0_bits_vs_addr(q1_io_in_bits_0_bits_vs_addr),
- .io_in_bits_0_bits_vs_tag(q1_io_in_bits_0_bits_vs_tag),
- .io_in_bits_0_bits_vt_valid(q1_io_in_bits_0_bits_vt_valid),
- .io_in_bits_0_bits_vt_addr(q1_io_in_bits_0_bits_vt_addr),
- .io_in_bits_0_bits_vt_tag(q1_io_in_bits_0_bits_vt_tag),
- .io_in_bits_0_bits_vu_valid(q1_io_in_bits_0_bits_vu_valid),
- .io_in_bits_0_bits_vu_addr(q1_io_in_bits_0_bits_vu_addr),
- .io_in_bits_0_bits_vu_tag(q1_io_in_bits_0_bits_vu_tag),
- .io_in_bits_0_bits_vx_valid(q1_io_in_bits_0_bits_vx_valid),
- .io_in_bits_0_bits_vx_addr(q1_io_in_bits_0_bits_vx_addr),
- .io_in_bits_0_bits_vx_tag(q1_io_in_bits_0_bits_vx_tag),
- .io_in_bits_0_bits_vy_valid(q1_io_in_bits_0_bits_vy_valid),
- .io_in_bits_0_bits_vy_addr(q1_io_in_bits_0_bits_vy_addr),
- .io_in_bits_0_bits_vy_tag(q1_io_in_bits_0_bits_vy_tag),
- .io_in_bits_0_bits_vz_valid(q1_io_in_bits_0_bits_vz_valid),
- .io_in_bits_0_bits_vz_addr(q1_io_in_bits_0_bits_vz_addr),
- .io_in_bits_0_bits_vz_tag(q1_io_in_bits_0_bits_vz_tag),
- .io_in_bits_0_bits_sv_valid(q1_io_in_bits_0_bits_sv_valid),
- .io_in_bits_0_bits_sv_data(q1_io_in_bits_0_bits_sv_data),
- .io_in_bits_0_bits_cmdsync(q1_io_in_bits_0_bits_cmdsync),
- .io_in_bits_1_valid(q1_io_in_bits_1_valid),
- .io_in_bits_1_bits_op(q1_io_in_bits_1_bits_op),
- .io_in_bits_1_bits_f2(q1_io_in_bits_1_bits_f2),
- .io_in_bits_1_bits_sz(q1_io_in_bits_1_bits_sz),
- .io_in_bits_1_bits_m(q1_io_in_bits_1_bits_m),
- .io_in_bits_1_bits_vd_addr(q1_io_in_bits_1_bits_vd_addr),
- .io_in_bits_1_bits_ve_addr(q1_io_in_bits_1_bits_ve_addr),
- .io_in_bits_1_bits_vf_addr(q1_io_in_bits_1_bits_vf_addr),
- .io_in_bits_1_bits_vg_addr(q1_io_in_bits_1_bits_vg_addr),
- .io_in_bits_1_bits_vs_valid(q1_io_in_bits_1_bits_vs_valid),
- .io_in_bits_1_bits_vs_addr(q1_io_in_bits_1_bits_vs_addr),
- .io_in_bits_1_bits_vs_tag(q1_io_in_bits_1_bits_vs_tag),
- .io_in_bits_1_bits_vt_valid(q1_io_in_bits_1_bits_vt_valid),
- .io_in_bits_1_bits_vt_addr(q1_io_in_bits_1_bits_vt_addr),
- .io_in_bits_1_bits_vt_tag(q1_io_in_bits_1_bits_vt_tag),
- .io_in_bits_1_bits_vu_valid(q1_io_in_bits_1_bits_vu_valid),
- .io_in_bits_1_bits_vu_addr(q1_io_in_bits_1_bits_vu_addr),
- .io_in_bits_1_bits_vu_tag(q1_io_in_bits_1_bits_vu_tag),
- .io_in_bits_1_bits_vx_valid(q1_io_in_bits_1_bits_vx_valid),
- .io_in_bits_1_bits_vx_addr(q1_io_in_bits_1_bits_vx_addr),
- .io_in_bits_1_bits_vx_tag(q1_io_in_bits_1_bits_vx_tag),
- .io_in_bits_1_bits_vy_valid(q1_io_in_bits_1_bits_vy_valid),
- .io_in_bits_1_bits_vy_addr(q1_io_in_bits_1_bits_vy_addr),
- .io_in_bits_1_bits_vy_tag(q1_io_in_bits_1_bits_vy_tag),
- .io_in_bits_1_bits_vz_valid(q1_io_in_bits_1_bits_vz_valid),
- .io_in_bits_1_bits_vz_addr(q1_io_in_bits_1_bits_vz_addr),
- .io_in_bits_1_bits_vz_tag(q1_io_in_bits_1_bits_vz_tag),
- .io_in_bits_1_bits_sv_valid(q1_io_in_bits_1_bits_sv_valid),
- .io_in_bits_1_bits_sv_data(q1_io_in_bits_1_bits_sv_data),
- .io_in_bits_1_bits_cmdsync(q1_io_in_bits_1_bits_cmdsync),
- .io_in_bits_2_valid(q1_io_in_bits_2_valid),
- .io_in_bits_2_bits_op(q1_io_in_bits_2_bits_op),
- .io_in_bits_2_bits_f2(q1_io_in_bits_2_bits_f2),
- .io_in_bits_2_bits_sz(q1_io_in_bits_2_bits_sz),
- .io_in_bits_2_bits_m(q1_io_in_bits_2_bits_m),
- .io_in_bits_2_bits_vd_addr(q1_io_in_bits_2_bits_vd_addr),
- .io_in_bits_2_bits_ve_addr(q1_io_in_bits_2_bits_ve_addr),
- .io_in_bits_2_bits_vf_addr(q1_io_in_bits_2_bits_vf_addr),
- .io_in_bits_2_bits_vg_addr(q1_io_in_bits_2_bits_vg_addr),
- .io_in_bits_2_bits_vs_valid(q1_io_in_bits_2_bits_vs_valid),
- .io_in_bits_2_bits_vs_addr(q1_io_in_bits_2_bits_vs_addr),
- .io_in_bits_2_bits_vs_tag(q1_io_in_bits_2_bits_vs_tag),
- .io_in_bits_2_bits_vt_valid(q1_io_in_bits_2_bits_vt_valid),
- .io_in_bits_2_bits_vt_addr(q1_io_in_bits_2_bits_vt_addr),
- .io_in_bits_2_bits_vt_tag(q1_io_in_bits_2_bits_vt_tag),
- .io_in_bits_2_bits_vu_valid(q1_io_in_bits_2_bits_vu_valid),
- .io_in_bits_2_bits_vu_addr(q1_io_in_bits_2_bits_vu_addr),
- .io_in_bits_2_bits_vu_tag(q1_io_in_bits_2_bits_vu_tag),
- .io_in_bits_2_bits_vx_valid(q1_io_in_bits_2_bits_vx_valid),
- .io_in_bits_2_bits_vx_addr(q1_io_in_bits_2_bits_vx_addr),
- .io_in_bits_2_bits_vx_tag(q1_io_in_bits_2_bits_vx_tag),
- .io_in_bits_2_bits_vy_valid(q1_io_in_bits_2_bits_vy_valid),
- .io_in_bits_2_bits_vy_addr(q1_io_in_bits_2_bits_vy_addr),
- .io_in_bits_2_bits_vy_tag(q1_io_in_bits_2_bits_vy_tag),
- .io_in_bits_2_bits_vz_valid(q1_io_in_bits_2_bits_vz_valid),
- .io_in_bits_2_bits_vz_addr(q1_io_in_bits_2_bits_vz_addr),
- .io_in_bits_2_bits_vz_tag(q1_io_in_bits_2_bits_vz_tag),
- .io_in_bits_2_bits_sv_valid(q1_io_in_bits_2_bits_sv_valid),
- .io_in_bits_2_bits_sv_data(q1_io_in_bits_2_bits_sv_data),
- .io_in_bits_2_bits_cmdsync(q1_io_in_bits_2_bits_cmdsync),
- .io_in_bits_3_valid(q1_io_in_bits_3_valid),
- .io_in_bits_3_bits_op(q1_io_in_bits_3_bits_op),
- .io_in_bits_3_bits_f2(q1_io_in_bits_3_bits_f2),
- .io_in_bits_3_bits_sz(q1_io_in_bits_3_bits_sz),
- .io_in_bits_3_bits_m(q1_io_in_bits_3_bits_m),
- .io_in_bits_3_bits_vd_addr(q1_io_in_bits_3_bits_vd_addr),
- .io_in_bits_3_bits_ve_addr(q1_io_in_bits_3_bits_ve_addr),
- .io_in_bits_3_bits_vf_addr(q1_io_in_bits_3_bits_vf_addr),
- .io_in_bits_3_bits_vg_addr(q1_io_in_bits_3_bits_vg_addr),
- .io_in_bits_3_bits_vs_valid(q1_io_in_bits_3_bits_vs_valid),
- .io_in_bits_3_bits_vs_addr(q1_io_in_bits_3_bits_vs_addr),
- .io_in_bits_3_bits_vs_tag(q1_io_in_bits_3_bits_vs_tag),
- .io_in_bits_3_bits_vt_valid(q1_io_in_bits_3_bits_vt_valid),
- .io_in_bits_3_bits_vt_addr(q1_io_in_bits_3_bits_vt_addr),
- .io_in_bits_3_bits_vt_tag(q1_io_in_bits_3_bits_vt_tag),
- .io_in_bits_3_bits_vu_valid(q1_io_in_bits_3_bits_vu_valid),
- .io_in_bits_3_bits_vu_addr(q1_io_in_bits_3_bits_vu_addr),
- .io_in_bits_3_bits_vu_tag(q1_io_in_bits_3_bits_vu_tag),
- .io_in_bits_3_bits_vx_valid(q1_io_in_bits_3_bits_vx_valid),
- .io_in_bits_3_bits_vx_addr(q1_io_in_bits_3_bits_vx_addr),
- .io_in_bits_3_bits_vx_tag(q1_io_in_bits_3_bits_vx_tag),
- .io_in_bits_3_bits_vy_valid(q1_io_in_bits_3_bits_vy_valid),
- .io_in_bits_3_bits_vy_addr(q1_io_in_bits_3_bits_vy_addr),
- .io_in_bits_3_bits_vy_tag(q1_io_in_bits_3_bits_vy_tag),
- .io_in_bits_3_bits_vz_valid(q1_io_in_bits_3_bits_vz_valid),
- .io_in_bits_3_bits_vz_addr(q1_io_in_bits_3_bits_vz_addr),
- .io_in_bits_3_bits_vz_tag(q1_io_in_bits_3_bits_vz_tag),
- .io_in_bits_3_bits_sv_valid(q1_io_in_bits_3_bits_sv_valid),
- .io_in_bits_3_bits_sv_data(q1_io_in_bits_3_bits_sv_data),
- .io_in_bits_3_bits_cmdsync(q1_io_in_bits_3_bits_cmdsync),
- .io_out_ready(q1_io_out_ready),
- .io_out_valid(q1_io_out_valid),
- .io_out_bits_op(q1_io_out_bits_op),
- .io_out_bits_f2(q1_io_out_bits_f2),
- .io_out_bits_sz(q1_io_out_bits_sz),
- .io_out_bits_vd_addr(q1_io_out_bits_vd_addr),
- .io_out_bits_ve_addr(q1_io_out_bits_ve_addr),
- .io_out_bits_vs_valid(q1_io_out_bits_vs_valid),
- .io_out_bits_vs_addr(q1_io_out_bits_vs_addr),
- .io_out_bits_vs_tag(q1_io_out_bits_vs_tag),
- .io_out_bits_vt_valid(q1_io_out_bits_vt_valid),
- .io_out_bits_vt_addr(q1_io_out_bits_vt_addr),
- .io_out_bits_vt_tag(q1_io_out_bits_vt_tag),
- .io_out_bits_vu_valid(q1_io_out_bits_vu_valid),
- .io_out_bits_vu_addr(q1_io_out_bits_vu_addr),
- .io_out_bits_vu_tag(q1_io_out_bits_vu_tag),
- .io_out_bits_sv_valid(q1_io_out_bits_sv_valid),
- .io_out_bits_sv_data(q1_io_out_bits_sv_data),
- .io_out_bits_cmdsync(q1_io_out_bits_cmdsync),
- .io_active(q1_io_active)
- );
- VAluInt alu0 ( // @[VAlu.scala 337:20]
- .clock(alu0_clock),
- .reset(alu0_reset),
- .io_in_valid(alu0_io_in_valid),
- .io_in_op(alu0_io_in_op),
- .io_in_f2(alu0_io_in_f2),
- .io_in_sz(alu0_io_in_sz),
- .io_in_vd_addr(alu0_io_in_vd_addr),
- .io_in_ve_addr(alu0_io_in_ve_addr),
- .io_in_sv_data(alu0_io_in_sv_data),
- .io_read_0_data(alu0_io_read_0_data),
- .io_read_1_data(alu0_io_read_1_data),
- .io_read_2_data(alu0_io_read_2_data),
- .io_read_3_data(alu0_io_read_3_data),
- .io_read_4_data(alu0_io_read_4_data),
- .io_read_5_data(alu0_io_read_5_data),
- .io_write_0_valid(alu0_io_write_0_valid),
- .io_write_0_addr(alu0_io_write_0_addr),
- .io_write_0_data(alu0_io_write_0_data),
- .io_write_1_valid(alu0_io_write_1_valid),
- .io_write_1_addr(alu0_io_write_1_addr),
- .io_write_1_data(alu0_io_write_1_data),
- .io_whint_0_valid(alu0_io_whint_0_valid),
- .io_whint_0_addr(alu0_io_whint_0_addr),
- .io_whint_1_valid(alu0_io_whint_1_valid),
- .io_whint_1_addr(alu0_io_whint_1_addr)
- );
- VAluInt_1 alu1 ( // @[VAlu.scala 371:20]
- .clock(alu1_clock),
- .reset(alu1_reset),
- .io_in_valid(alu1_io_in_valid),
- .io_in_op(alu1_io_in_op),
- .io_in_f2(alu1_io_in_f2),
- .io_in_sz(alu1_io_in_sz),
- .io_in_vd_addr(alu1_io_in_vd_addr),
- .io_in_ve_addr(alu1_io_in_ve_addr),
- .io_in_sv_data(alu1_io_in_sv_data),
- .io_read_0_data(alu1_io_read_0_data),
- .io_read_1_data(alu1_io_read_1_data),
- .io_read_2_data(alu1_io_read_2_data),
- .io_read_3_data(alu1_io_read_3_data),
- .io_read_4_data(alu1_io_read_4_data),
- .io_read_5_data(alu1_io_read_5_data),
- .io_write_0_valid(alu1_io_write_0_valid),
- .io_write_0_addr(alu1_io_write_0_addr),
- .io_write_0_data(alu1_io_write_0_data),
- .io_write_1_valid(alu1_io_write_1_valid),
- .io_write_1_addr(alu1_io_write_1_addr),
- .io_write_1_data(alu1_io_write_1_data),
- .io_whint_0_valid(alu1_io_whint_0_valid),
- .io_whint_0_addr(alu1_io_whint_0_addr),
- .io_whint_1_valid(alu1_io_whint_1_valid),
- .io_whint_1_addr(alu1_io_whint_1_addr)
- );
- assign io_in_ready = q0_io_in_ready & q1_io_in_ready; // @[VAlu.scala 261:33]
- assign io_active = q0_io_active | q1_io_active; // @[VAlu.scala 405:29]
- assign io_read_0_valid = q0_io_out_bits_vs_valid; // @[VAlu.scala 300:20]
- assign io_read_0_addr = q0_io_out_bits_vs_addr; // @[VAlu.scala 307:19]
- assign io_read_1_valid = q0_io_out_bits_vt_valid; // @[VAlu.scala 301:20]
- assign io_read_1_addr = q0_io_out_bits_vt_addr; // @[VAlu.scala 308:19]
- assign io_read_2_valid = q0_io_out_bits_vu_valid; // @[VAlu.scala 302:20]
- assign io_read_2_addr = q0_io_out_bits_vu_addr; // @[VAlu.scala 309:19]
- assign io_read_3_valid = q1_io_out_bits_vs_valid; // @[VAlu.scala 303:20]
- assign io_read_3_addr = q1_io_out_bits_vs_addr; // @[VAlu.scala 310:19]
- assign io_read_4_valid = q1_io_out_bits_vt_valid; // @[VAlu.scala 304:20]
- assign io_read_4_addr = q1_io_out_bits_vt_addr; // @[VAlu.scala 311:19]
- assign io_read_5_valid = q1_io_out_bits_vu_valid; // @[VAlu.scala 305:20]
- assign io_read_5_addr = q1_io_out_bits_vu_addr; // @[VAlu.scala 312:19]
- assign io_write_0_valid = alu0_io_write_0_valid; // @[VAlu.scala 355:21]
- assign io_write_0_addr = alu0_io_write_0_addr; // @[VAlu.scala 356:20]
- assign io_write_0_data = alu0_io_write_0_data; // @[VAlu.scala 357:20]
- assign io_write_1_valid = alu0_io_write_1_valid; // @[VAlu.scala 359:21]
- assign io_write_1_addr = alu0_io_write_1_addr; // @[VAlu.scala 360:20]
- assign io_write_1_data = alu0_io_write_1_data; // @[VAlu.scala 361:20]
- assign io_write_2_valid = alu1_io_write_0_valid; // @[VAlu.scala 389:21]
- assign io_write_2_addr = alu1_io_write_0_addr; // @[VAlu.scala 390:20]
- assign io_write_2_data = alu1_io_write_0_data; // @[VAlu.scala 391:20]
- assign io_write_3_valid = alu1_io_write_1_valid; // @[VAlu.scala 393:21]
- assign io_write_3_addr = alu1_io_write_1_addr; // @[VAlu.scala 394:20]
- assign io_write_3_data = alu1_io_write_1_data; // @[VAlu.scala 395:20]
- assign io_whint_0_valid = alu0_io_whint_0_valid; // @[VAlu.scala 363:21]
- assign io_whint_0_addr = alu0_io_whint_0_addr; // @[VAlu.scala 364:20]
- assign io_whint_1_valid = alu0_io_whint_1_valid; // @[VAlu.scala 366:21]
- assign io_whint_1_addr = alu0_io_whint_1_addr; // @[VAlu.scala 367:20]
- assign io_whint_2_valid = alu1_io_whint_0_valid; // @[VAlu.scala 397:21]
- assign io_whint_2_addr = alu1_io_whint_0_addr; // @[VAlu.scala 398:20]
- assign io_whint_3_valid = alu1_io_whint_1_valid; // @[VAlu.scala 400:21]
- assign io_whint_3_addr = alu1_io_whint_1_addr; // @[VAlu.scala 401:20]
- assign io_scalar_0_valid = q0_io_out_bits_sv_valid; // @[VAlu.scala 321:22]
- assign io_scalar_0_data = q0_io_out_bits_sv_data; // @[VAlu.scala 324:21]
- assign io_scalar_1_valid = q1_io_out_bits_sv_valid; // @[VAlu.scala 322:22]
- assign io_scalar_1_data = q1_io_out_bits_sv_data; // @[VAlu.scala 325:21]
- assign q0_clock = clock;
- assign q0_reset = reset;
- assign q0_io_in_valid = io_in_valid & q1_io_in_ready; // @[VAlu.scala 259:33]
- assign q0_io_in_bits_0_valid = io_in_bits_0_valid & (_alusel_1_T_2 | io_in_bits_0_bits_cmdsync); // @[VAlu.scala 294:51]
- assign q0_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_0_bits_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_valid = io_in_bits_1_valid & (_alusel_2_T_2 | io_in_bits_1_bits_cmdsync); // @[VAlu.scala 294:51]
- assign q0_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_1_bits_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_valid = io_in_bits_2_valid & (_alusel_3_T_2 | io_in_bits_2_bits_cmdsync); // @[VAlu.scala 294:51]
- assign q0_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_2_bits_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_valid = io_in_bits_3_valid & (_alusel_4_T_2 | io_in_bits_3_bits_cmdsync); // @[VAlu.scala 294:51]
- assign q0_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 263:17]
- assign q0_io_in_bits_3_bits_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 263:17]
- assign q0_io_out_ready = q0ready & (~q0_io_out_bits_cmdsync | q1_io_out_valid & q1ready & q1_io_out_bits_cmdsync); // @[VAlu.scala 274:30]
- assign q1_clock = clock;
- assign q1_reset = reset;
- assign q1_io_in_valid = io_in_valid & q0_io_in_ready; // @[VAlu.scala 260:33]
- assign q1_io_in_bits_0_valid = io_in_bits_0_valid & (alureg | io_in_bits_0_bits_cmdsync); // @[VAlu.scala 295:51]
- assign q1_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_ve_addr = io_in_bits_0_bits_ve_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vf_addr = io_in_bits_0_bits_vf_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vg_addr = io_in_bits_0_bits_vg_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vt_valid = io_in_bits_0_bits_vt_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vt_addr = io_in_bits_0_bits_vt_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vt_tag = io_in_bits_0_bits_vt_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vu_valid = io_in_bits_0_bits_vu_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vu_addr = io_in_bits_0_bits_vu_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vu_tag = io_in_bits_0_bits_vu_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vx_valid = io_in_bits_0_bits_vx_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vx_addr = io_in_bits_0_bits_vx_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vx_tag = io_in_bits_0_bits_vx_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vy_valid = io_in_bits_0_bits_vy_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vy_addr = io_in_bits_0_bits_vy_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vy_tag = io_in_bits_0_bits_vy_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vz_valid = io_in_bits_0_bits_vz_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vz_addr = io_in_bits_0_bits_vz_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_vz_tag = io_in_bits_0_bits_vz_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_sv_valid = io_in_bits_0_bits_sv_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_0_bits_cmdsync = io_in_bits_0_bits_cmdsync; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_valid = io_in_bits_1_valid & (alusel_1 | io_in_bits_1_bits_cmdsync); // @[VAlu.scala 295:51]
- assign q1_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_ve_addr = io_in_bits_1_bits_ve_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vf_addr = io_in_bits_1_bits_vf_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vg_addr = io_in_bits_1_bits_vg_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vt_valid = io_in_bits_1_bits_vt_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vt_addr = io_in_bits_1_bits_vt_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vt_tag = io_in_bits_1_bits_vt_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vu_valid = io_in_bits_1_bits_vu_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vu_addr = io_in_bits_1_bits_vu_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vu_tag = io_in_bits_1_bits_vu_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vx_valid = io_in_bits_1_bits_vx_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vx_addr = io_in_bits_1_bits_vx_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vx_tag = io_in_bits_1_bits_vx_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vy_valid = io_in_bits_1_bits_vy_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vy_addr = io_in_bits_1_bits_vy_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vy_tag = io_in_bits_1_bits_vy_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vz_valid = io_in_bits_1_bits_vz_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vz_addr = io_in_bits_1_bits_vz_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_vz_tag = io_in_bits_1_bits_vz_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_sv_valid = io_in_bits_1_bits_sv_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_1_bits_cmdsync = io_in_bits_1_bits_cmdsync; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_valid = io_in_bits_2_valid & (alusel_2 | io_in_bits_2_bits_cmdsync); // @[VAlu.scala 295:51]
- assign q1_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_ve_addr = io_in_bits_2_bits_ve_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vf_addr = io_in_bits_2_bits_vf_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vg_addr = io_in_bits_2_bits_vg_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vt_valid = io_in_bits_2_bits_vt_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vt_addr = io_in_bits_2_bits_vt_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vt_tag = io_in_bits_2_bits_vt_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vu_valid = io_in_bits_2_bits_vu_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vu_addr = io_in_bits_2_bits_vu_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vu_tag = io_in_bits_2_bits_vu_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vx_valid = io_in_bits_2_bits_vx_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vx_addr = io_in_bits_2_bits_vx_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vx_tag = io_in_bits_2_bits_vx_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vy_valid = io_in_bits_2_bits_vy_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vy_addr = io_in_bits_2_bits_vy_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vy_tag = io_in_bits_2_bits_vy_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vz_valid = io_in_bits_2_bits_vz_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vz_addr = io_in_bits_2_bits_vz_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_vz_tag = io_in_bits_2_bits_vz_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_sv_valid = io_in_bits_2_bits_sv_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_2_bits_cmdsync = io_in_bits_2_bits_cmdsync; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_valid = io_in_bits_3_valid & (alusel_3 | io_in_bits_3_bits_cmdsync); // @[VAlu.scala 295:51]
- assign q1_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_ve_addr = io_in_bits_3_bits_ve_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vf_addr = io_in_bits_3_bits_vf_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vg_addr = io_in_bits_3_bits_vg_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vt_valid = io_in_bits_3_bits_vt_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vt_addr = io_in_bits_3_bits_vt_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vt_tag = io_in_bits_3_bits_vt_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vu_valid = io_in_bits_3_bits_vu_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vu_addr = io_in_bits_3_bits_vu_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vu_tag = io_in_bits_3_bits_vu_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vx_valid = io_in_bits_3_bits_vx_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vx_addr = io_in_bits_3_bits_vx_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vx_tag = io_in_bits_3_bits_vx_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vy_valid = io_in_bits_3_bits_vy_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vy_addr = io_in_bits_3_bits_vy_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vy_tag = io_in_bits_3_bits_vy_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vz_valid = io_in_bits_3_bits_vz_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vz_addr = io_in_bits_3_bits_vz_addr; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_vz_tag = io_in_bits_3_bits_vz_tag; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_sv_valid = io_in_bits_3_bits_sv_valid; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VAlu.scala 264:17]
- assign q1_io_in_bits_3_bits_cmdsync = io_in_bits_3_bits_cmdsync; // @[VAlu.scala 264:17]
- assign q1_io_out_ready = q1ready & (~q1_io_out_bits_cmdsync | q0_io_out_valid & q0ready & q0_io_out_bits_cmdsync); // @[VAlu.scala 275:30]
- assign alu0_clock = clock;
- assign alu0_reset = reset;
- assign alu0_io_in_valid = q0_io_out_valid & q0_io_out_ready; // @[VAlu.scala 339:39]
- assign alu0_io_in_op = q0_io_out_bits_op; // @[VAlu.scala 340:17]
- assign alu0_io_in_f2 = q0_io_out_bits_f2; // @[VAlu.scala 341:17]
- assign alu0_io_in_sz = q0_io_out_bits_sz; // @[VAlu.scala 342:17]
- assign alu0_io_in_vd_addr = q0_io_out_bits_vd_addr; // @[VAlu.scala 343:22]
- assign alu0_io_in_ve_addr = q0_io_out_bits_ve_addr; // @[VAlu.scala 344:22]
- assign alu0_io_in_sv_data = q0_io_out_bits_sv_data; // @[VAlu.scala 345:22]
- assign alu0_io_read_0_data = io_read_0_data; // @[VAlu.scala 347:24]
- assign alu0_io_read_1_data = io_read_1_data; // @[VAlu.scala 348:24]
- assign alu0_io_read_2_data = io_read_2_data; // @[VAlu.scala 349:24]
- assign alu0_io_read_3_data = io_read_3_data; // @[VAlu.scala 350:24]
- assign alu0_io_read_4_data = io_read_4_data; // @[VAlu.scala 351:24]
- assign alu0_io_read_5_data = io_read_5_data; // @[VAlu.scala 352:24]
- assign alu1_clock = clock;
- assign alu1_reset = reset;
- assign alu1_io_in_valid = q1_io_out_valid & q1_io_out_ready; // @[VAlu.scala 373:39]
- assign alu1_io_in_op = q1_io_out_bits_op; // @[VAlu.scala 374:17]
- assign alu1_io_in_f2 = q1_io_out_bits_f2; // @[VAlu.scala 375:17]
- assign alu1_io_in_sz = q1_io_out_bits_sz; // @[VAlu.scala 376:17]
- assign alu1_io_in_vd_addr = q1_io_out_bits_vd_addr; // @[VAlu.scala 377:22]
- assign alu1_io_in_ve_addr = q1_io_out_bits_ve_addr; // @[VAlu.scala 378:22]
- assign alu1_io_in_sv_data = q1_io_out_bits_sv_data; // @[VAlu.scala 379:22]
- assign alu1_io_read_0_data = io_read_3_data; // @[VAlu.scala 381:24]
- assign alu1_io_read_1_data = io_read_4_data; // @[VAlu.scala 382:24]
- assign alu1_io_read_2_data = io_read_5_data; // @[VAlu.scala 383:24]
- assign alu1_io_read_3_data = io_read_0_data; // @[VAlu.scala 384:24]
- assign alu1_io_read_4_data = io_read_1_data; // @[VAlu.scala 385:24]
- assign alu1_io_read_5_data = io_read_2_data; // @[VAlu.scala 386:24]
- always @(posedge clock) begin
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T & io_in_bits_0_valid & _T_1 & ~reset) begin
- $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_0_bits_op); // @[VAlu.scala 153:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_1 & _T_3 & _T_1) begin
- $fatal; // @[VAlu.scala 155:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_1 & _T_3 & _T_1) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:155 assert(supported)\n"); // @[VAlu.scala 155:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_4 & ~(~(io_in_bits_0_bits_vt_valid & io_in_bits_0_bits_sv_valid))) begin
- $fatal; // @[VAlu.scala 157:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_4 & ~(~(io_in_bits_0_bits_vt_valid & io_in_bits_0_bits_sv_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:157 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
- ); // @[VAlu.scala 157:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_1 & _T_14 & _T_3 & ~(~io_in_bits_0_bits_m)) begin
- $fatal; // @[VAlu.scala 161:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_1 & _T_14 & _T_3 & ~(~io_in_bits_0_bits_m)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:161 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 161:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_15 & ~(io_in_bits_0_bits_sz == 3'h4)) begin
- $fatal; // @[VAlu.scala 162:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_15 & ~(io_in_bits_0_bits_sz == 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:162 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 162:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_15 & ~(~io_in_bits_0_bits_sv_valid)) begin
- $fatal; // @[VAlu.scala 163:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_15 & ~(~io_in_bits_0_bits_sv_valid)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:163 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 163:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_15 & ~(sparse < 2'h3)) begin
- $fatal; // @[VAlu.scala 164:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_15 & ~(sparse < 2'h3)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:164 assert(sparse < 3.U)\n"); // @[VAlu.scala 164:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T & io_in_bits_1_valid & _T_32 & ~reset) begin
- $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_1_bits_op); // @[VAlu.scala 153:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_41 & _T_3 & _T_32) begin
- $fatal; // @[VAlu.scala 155:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_41 & _T_3 & _T_32) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:155 assert(supported)\n"); // @[VAlu.scala 155:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_44 & ~(~(io_in_bits_1_bits_vt_valid & io_in_bits_1_bits_sv_valid))) begin
- $fatal; // @[VAlu.scala 157:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_44 & ~(~(io_in_bits_1_bits_vt_valid & io_in_bits_1_bits_sv_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:157 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
- ); // @[VAlu.scala 157:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_41 & _T_45 & _T_3 & ~(~io_in_bits_1_bits_m)) begin
- $fatal; // @[VAlu.scala 161:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_41 & _T_45 & _T_3 & ~(~io_in_bits_1_bits_m)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:161 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 161:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_55 & ~(io_in_bits_1_bits_sz == 3'h4)) begin
- $fatal; // @[VAlu.scala 162:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_55 & ~(io_in_bits_1_bits_sz == 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:162 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 162:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_55 & ~(~io_in_bits_1_bits_sv_valid)) begin
- $fatal; // @[VAlu.scala 163:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_55 & ~(~io_in_bits_1_bits_sv_valid)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:163 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 163:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_55 & ~(sparse_1 < 2'h3)) begin
- $fatal; // @[VAlu.scala 164:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_55 & ~(sparse_1 < 2'h3)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:164 assert(sparse < 3.U)\n"); // @[VAlu.scala 164:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T & io_in_bits_2_valid & _T_63 & ~reset) begin
- $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_2_bits_op); // @[VAlu.scala 153:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_81 & _T_3 & _T_63) begin
- $fatal; // @[VAlu.scala 155:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_81 & _T_3 & _T_63) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:155 assert(supported)\n"); // @[VAlu.scala 155:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_84 & ~(~(io_in_bits_2_bits_vt_valid & io_in_bits_2_bits_sv_valid))) begin
- $fatal; // @[VAlu.scala 157:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_84 & ~(~(io_in_bits_2_bits_vt_valid & io_in_bits_2_bits_sv_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:157 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
- ); // @[VAlu.scala 157:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_81 & _T_76 & _T_3 & ~(~io_in_bits_2_bits_m)) begin
- $fatal; // @[VAlu.scala 161:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_81 & _T_76 & _T_3 & ~(~io_in_bits_2_bits_m)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:161 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 161:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_95 & ~(io_in_bits_2_bits_sz == 3'h4)) begin
- $fatal; // @[VAlu.scala 162:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_95 & ~(io_in_bits_2_bits_sz == 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:162 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 162:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_95 & ~(~io_in_bits_2_bits_sv_valid)) begin
- $fatal; // @[VAlu.scala 163:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_95 & ~(~io_in_bits_2_bits_sv_valid)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:163 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 163:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_95 & ~(sparse_2 < 2'h3)) begin
- $fatal; // @[VAlu.scala 164:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_95 & ~(sparse_2 < 2'h3)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:164 assert(sparse < 3.U)\n"); // @[VAlu.scala 164:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T & io_in_bits_3_valid & _T_94 & ~reset) begin
- $fwrite(32'h80000002,"**Op=%d unsupported\n",io_in_bits_3_bits_op); // @[VAlu.scala 153:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_121 & _T_3 & _T_94) begin
- $fatal; // @[VAlu.scala 155:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_121 & _T_3 & _T_94) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:155 assert(supported)\n"); // @[VAlu.scala 155:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_124 & ~(~(io_in_bits_3_bits_vt_valid & io_in_bits_3_bits_sv_valid))) begin
- $fatal; // @[VAlu.scala 157:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_124 & ~(~(io_in_bits_3_bits_vt_valid & io_in_bits_3_bits_sv_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:157 assert(!(io.in.bits(i).bits.vt.valid && io.in.bits(i).bits.sv.valid))\n"
- ); // @[VAlu.scala 157:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_121 & _T_107 & _T_3 & ~(~io_in_bits_3_bits_m)) begin
- $fatal; // @[VAlu.scala 161:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_121 & _T_107 & _T_3 & ~(~io_in_bits_3_bits_m)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:161 assert(io.in.bits(i).bits.m === false.B)\n"); // @[VAlu.scala 161:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_135 & ~(io_in_bits_3_bits_sz == 3'h4)) begin
- $fatal; // @[VAlu.scala 162:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_135 & ~(io_in_bits_3_bits_sz == 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:162 assert(io.in.bits(i).bits.sz === 4.U)\n"); // @[VAlu.scala 162:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_135 & ~(~io_in_bits_3_bits_sv_valid)) begin
- $fatal; // @[VAlu.scala 163:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_135 & ~(~io_in_bits_3_bits_sv_valid)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VAlu.scala:163 assert(io.in.bits(i).bits.sv.valid === false.B)\n"); // @[VAlu.scala 163:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_135 & ~(sparse_3 < 2'h3)) begin
- $fatal; // @[VAlu.scala 164:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_135 & ~(sparse_3 < 2'h3)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VAlu.scala:164 assert(sparse < 3.U)\n"); // @[VAlu.scala 164:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VAlu.scala 289:37]
- alureg <= 1'h0; // @[VAlu.scala 285:19 286:19 287:19]
- end else if (_T) begin // @[VAlu.scala 279:23]
- if (io_in_bits_3_valid & ~io_in_bits_3_bits_cmdsync) begin
- alureg <= ~alusel_3;
- end else if (io_in_bits_2_valid & ~io_in_bits_2_bits_cmdsync) begin
- alureg <= ~alusel_2;
- end else if (io_in_bits_1_valid & ~io_in_bits_1_bits_cmdsync) begin
- alureg <= ~alusel_1;
- end else begin
- alureg <= alusel_1;
- end
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- alureg = _RAND_0[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- alureg = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Fifo4e_2(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input io_in_bits_0_bits_tin_conv,
- input io_in_bits_0_bits_tin_init,
- input io_in_bits_0_bits_tin_tran,
- input io_in_bits_0_bits_tin_wclr,
- input [5:0] io_in_bits_0_bits_tin_addr1,
- input [5:0] io_in_bits_0_bits_tin_addr2,
- input [5:0] io_in_bits_0_bits_tin_base2,
- input [1:0] io_in_bits_0_bits_tin_mode,
- input [7:0] io_in_bits_0_bits_tin_mark2,
- input [2:0] io_in_bits_0_bits_tin_index,
- input [2:0] io_in_bits_0_bits_tin_end,
- input [8:0] io_in_bits_0_bits_tin_abias,
- input [8:0] io_in_bits_0_bits_tin_bbias,
- input io_in_bits_0_bits_tin_asign,
- input io_in_bits_0_bits_tin_bsign,
- input io_in_bits_0_bits_m,
- input io_in_bits_1_valid,
- input io_in_bits_1_bits_tin_conv,
- input io_in_bits_1_bits_tin_init,
- input io_in_bits_1_bits_tin_tran,
- input io_in_bits_1_bits_tin_wclr,
- input [5:0] io_in_bits_1_bits_tin_addr1,
- input [5:0] io_in_bits_1_bits_tin_addr2,
- input [5:0] io_in_bits_1_bits_tin_base2,
- input [1:0] io_in_bits_1_bits_tin_mode,
- input [7:0] io_in_bits_1_bits_tin_mark2,
- input [2:0] io_in_bits_1_bits_tin_index,
- input [2:0] io_in_bits_1_bits_tin_end,
- input [8:0] io_in_bits_1_bits_tin_abias,
- input [8:0] io_in_bits_1_bits_tin_bbias,
- input io_in_bits_1_bits_tin_asign,
- input io_in_bits_1_bits_tin_bsign,
- input io_in_bits_1_bits_m,
- input io_in_bits_2_valid,
- input io_in_bits_2_bits_tin_conv,
- input io_in_bits_2_bits_tin_init,
- input io_in_bits_2_bits_tin_tran,
- input io_in_bits_2_bits_tin_wclr,
- input [5:0] io_in_bits_2_bits_tin_addr1,
- input [5:0] io_in_bits_2_bits_tin_addr2,
- input [5:0] io_in_bits_2_bits_tin_base2,
- input [1:0] io_in_bits_2_bits_tin_mode,
- input [7:0] io_in_bits_2_bits_tin_mark2,
- input [2:0] io_in_bits_2_bits_tin_index,
- input [2:0] io_in_bits_2_bits_tin_end,
- input [8:0] io_in_bits_2_bits_tin_abias,
- input [8:0] io_in_bits_2_bits_tin_bbias,
- input io_in_bits_2_bits_tin_asign,
- input io_in_bits_2_bits_tin_bsign,
- input io_in_bits_2_bits_m,
- input io_in_bits_3_valid,
- input io_in_bits_3_bits_tin_conv,
- input io_in_bits_3_bits_tin_init,
- input io_in_bits_3_bits_tin_tran,
- input io_in_bits_3_bits_tin_wclr,
- input [5:0] io_in_bits_3_bits_tin_addr1,
- input [5:0] io_in_bits_3_bits_tin_addr2,
- input [5:0] io_in_bits_3_bits_tin_base2,
- input [1:0] io_in_bits_3_bits_tin_mode,
- input [7:0] io_in_bits_3_bits_tin_mark2,
- input [2:0] io_in_bits_3_bits_tin_index,
- input [2:0] io_in_bits_3_bits_tin_end,
- input [8:0] io_in_bits_3_bits_tin_abias,
- input [8:0] io_in_bits_3_bits_tin_bbias,
- input io_in_bits_3_bits_tin_asign,
- input io_in_bits_3_bits_tin_bsign,
- input io_in_bits_3_bits_m,
- input io_out_ready,
- output io_out_valid,
- output io_out_bits_tin_conv,
- output io_out_bits_tin_init,
- output io_out_bits_tin_tran,
- output io_out_bits_tin_wclr,
- output [5:0] io_out_bits_tin_addr1,
- output [5:0] io_out_bits_tin_addr2,
- output [5:0] io_out_bits_tin_base2,
- output [1:0] io_out_bits_tin_mode,
- output [7:0] io_out_bits_tin_mark2,
- output [2:0] io_out_bits_tin_index,
- output [2:0] io_out_bits_tin_end,
- output [8:0] io_out_bits_tin_abias,
- output [8:0] io_out_bits_tin_bbias,
- output io_out_bits_tin_asign,
- output io_out_bits_tin_bsign,
- output io_out_bits_m,
- output io_entry_0_valid,
- output io_entry_0_bits_tin_conv,
- output io_entry_0_bits_tin_init,
- output io_entry_0_bits_tin_tran,
- output [5:0] io_entry_0_bits_tin_addr1,
- output [5:0] io_entry_0_bits_tin_base2,
- output [7:0] io_entry_0_bits_tin_mark2,
- output io_entry_1_valid,
- output io_entry_1_bits_tin_conv,
- output io_entry_1_bits_tin_init,
- output io_entry_1_bits_tin_tran,
- output [5:0] io_entry_1_bits_tin_addr1,
- output [5:0] io_entry_1_bits_tin_base2,
- output [7:0] io_entry_1_bits_tin_mark2,
- output io_entry_2_valid,
- output io_entry_2_bits_tin_conv,
- output io_entry_2_bits_tin_init,
- output io_entry_2_bits_tin_tran,
- output [5:0] io_entry_2_bits_tin_addr1,
- output [5:0] io_entry_2_bits_tin_base2,
- output [7:0] io_entry_2_bits_tin_mark2,
- output io_entry_3_valid,
- output io_entry_3_bits_tin_conv,
- output io_entry_3_bits_tin_init,
- output io_entry_3_bits_tin_tran,
- output [5:0] io_entry_3_bits_tin_addr1,
- output [5:0] io_entry_3_bits_tin_base2,
- output [7:0] io_entry_3_bits_tin_mark2
-);
-`ifdef RANDOMIZE_MEM_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
-`endif // RANDOMIZE_REG_INIT
- reg mem_tin_conv [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_conv_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_conv_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg mem_tin_init [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_init_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_init_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg mem_tin_tran [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_tran_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_tran_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg mem_tin_wclr [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_wclr_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_wclr_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg [5:0] mem_tin_addr1 [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr1_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr1_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr1_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg [5:0] mem_tin_addr2 [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_addr2_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_addr2_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr2_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg [5:0] mem_tin_base2 [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_base2_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_base2_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_base2_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg [1:0] mem_tin_mode [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mode_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mode_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg [7:0] mem_tin_mark2 [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_mark2_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_mark2_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_mark2_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg [2:0] mem_tin_index [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_index_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_index_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_index_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg [2:0] mem_tin_end [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_end_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_end_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_end_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg [8:0] mem_tin_abias [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_abias_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_abias_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_abias_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg [8:0] mem_tin_bbias [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [8:0] mem_tin_bbias_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bbias_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bbias_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg mem_tin_asign [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_asign_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_asign_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg mem_tin_bsign [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_bsign_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_bsign_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg mem_m [0:3]; // @[Fifo4e.scala 43:16]
- wire mem_m_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_m_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_en; // @[Fifo4e.scala 43:16]
- reg [1:0] in0pos; // @[Fifo4e.scala 45:23]
- reg [1:0] in1pos; // @[Fifo4e.scala 46:23]
- reg [1:0] in2pos; // @[Fifo4e.scala 47:23]
- reg [1:0] in3pos; // @[Fifo4e.scala 48:23]
- reg [1:0] outpos; // @[Fifo4e.scala 49:23]
- reg [2:0] mcount; // @[Fifo4e.scala 50:23]
- wire ivalid = io_in_valid & io_in_ready; // @[Fifo4e.scala 56:28]
- wire dec = io_out_valid & io_out_ready; // @[Fifo4e.scala 57:29]
- wire [3:0] iactive = {io_in_bits_3_valid,io_in_bits_2_valid,io_in_bits_1_valid,io_in_bits_0_valid}; // @[Cat.scala 31:58]
- wire [1:0] _icount_T = io_in_bits_0_valid + io_in_bits_1_valid; // @[Fifo4e.scala 62:36]
- wire [1:0] _GEN_1114 = {{1'd0}, io_in_bits_2_valid}; // @[Fifo4e.scala 62:59]
- wire [1:0] _icount_T_2 = _icount_T + _GEN_1114; // @[Fifo4e.scala 62:59]
- wire [1:0] _GEN_1115 = {{1'd0}, io_in_bits_3_valid}; // @[Fifo4e.scala 63:36]
- wire [2:0] icount = _icount_T_2 + _GEN_1115; // @[Fifo4e.scala 63:36]
- wire [2:0] _GEN_1116 = {{1'd0}, in0pos}; // @[Fifo4e.scala 38:15]
- wire [3:0] in0pos_c = _GEN_1116 + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in0pos_d_T_2 = in0pos_c - 4'h4; // @[Fifo4e.scala 39:31]
- wire [3:0] _in0pos_d_T_3 = in0pos_c < 4'h4 ? in0pos_c : _in0pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [1:0] in0pos_d = _in0pos_d_T_3[1:0]; // @[Fifo4e.scala 39:37]
- wire [2:0] _GEN_1117 = {{1'd0}, in1pos}; // @[Fifo4e.scala 38:15]
- wire [3:0] in1pos_c = _GEN_1117 + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in1pos_d_T_2 = in1pos_c - 4'h4; // @[Fifo4e.scala 39:31]
- wire [3:0] _in1pos_d_T_3 = in1pos_c < 4'h4 ? in1pos_c : _in1pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [1:0] in1pos_d = _in1pos_d_T_3[1:0]; // @[Fifo4e.scala 39:37]
- wire [2:0] _GEN_1118 = {{1'd0}, in2pos}; // @[Fifo4e.scala 38:15]
- wire [3:0] in2pos_c = _GEN_1118 + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in2pos_d_T_2 = in2pos_c - 4'h4; // @[Fifo4e.scala 39:31]
- wire [3:0] _in2pos_d_T_3 = in2pos_c < 4'h4 ? in2pos_c : _in2pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [1:0] in2pos_d = _in2pos_d_T_3[1:0]; // @[Fifo4e.scala 39:37]
- wire [2:0] _GEN_1119 = {{1'd0}, in3pos}; // @[Fifo4e.scala 38:15]
- wire [3:0] in3pos_c = _GEN_1119 + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in3pos_d_T_2 = in3pos_c - 4'h4; // @[Fifo4e.scala 39:31]
- wire [3:0] _in3pos_d_T_3 = in3pos_c < 4'h4 ? in3pos_c : _in3pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [1:0] in3pos_d = _in3pos_d_T_3[1:0]; // @[Fifo4e.scala 39:37]
- wire [2:0] outpos_c = outpos + 2'h1; // @[Fifo4e.scala 38:15]
- wire [2:0] _outpos_d_T_2 = outpos_c - 3'h4; // @[Fifo4e.scala 39:31]
- wire [2:0] _outpos_d_T_3 = outpos_c < 3'h4 ? outpos_c : _outpos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [1:0] outpos_d = _outpos_d_T_3[1:0]; // @[Fifo4e.scala 39:37]
- wire [2:0] inc = ivalid ? icount : 3'h0; // @[Library.scala 22:8]
- wire _T = ivalid | dec; // @[Fifo4e.scala 81:16]
- wire [2:0] _nxtcount_T_1 = mcount + inc; // @[Fifo4e.scala 82:27]
- wire [2:0] _GEN_1120 = {{2'd0}, dec}; // @[Fifo4e.scala 82:33]
- wire [2:0] nxtcount = _nxtcount_T_1 - _GEN_1120; // @[Fifo4e.scala 82:33]
- wire _in0_T_1 = iactive == 4'h8; // @[Fifo4.scala 31:27]
- wire _in0_T_3 = iactive[2:0] == 3'h4; // @[Fifo4.scala 32:27]
- wire _in0_T_5 = iactive[1:0] == 2'h2; // @[Fifo4.scala 33:27]
- wire [3:0] in0valid = {_in0_T_1,_in0_T_3,_in0_T_5,iactive[0]}; // @[Cat.scala 31:58]
- wire _in1_T_3 = iactive == 4'ha; // @[Fifo4.scala 37:27]
- wire _in1_T_4 = iactive == 4'hc | _in1_T_3; // @[Fifo4.scala 36:36]
- wire _in1_T_6 = iactive == 4'h9; // @[Fifo4.scala 38:27]
- wire _in1_T_7 = _in1_T_4 | _in1_T_6; // @[Fifo4.scala 37:36]
- wire _in1_T_11 = iactive[2:0] == 3'h5; // @[Fifo4.scala 40:27]
- wire _in1_T_12 = iactive[2:0] == 3'h6 | _in1_T_11; // @[Fifo4.scala 39:35]
- wire _in1_T_14 = iactive[1:0] == 2'h3; // @[Fifo4.scala 41:27]
- wire [3:0] in1valid = {_in1_T_7,_in1_T_12,_in1_T_14,1'h0}; // @[Cat.scala 31:58]
- wire _in2_T_3 = iactive == 4'hd; // @[Fifo4.scala 45:27]
- wire _in2_T_4 = iactive == 4'he | _in2_T_3; // @[Fifo4.scala 44:36]
- wire _in2_T_6 = iactive == 4'hb; // @[Fifo4.scala 46:27]
- wire _in2_T_7 = _in2_T_4 | _in2_T_6; // @[Fifo4.scala 45:36]
- wire [3:0] _GEN_1121 = {{1'd0}, iactive[2:0]}; // @[Fifo4.scala 47:27]
- wire _in2_T_11 = iactive[2:0] == 3'h7; // @[Fifo4.scala 48:27]
- wire _in2_T_12 = _GEN_1121 == 4'hf | _in2_T_11; // @[Fifo4.scala 47:36]
- wire [3:0] in2valid = {_in2_T_7,_in2_T_12,2'h0}; // @[Cat.scala 31:58]
- wire _in3_T_1 = iactive == 4'hf; // @[Fifo4.scala 51:27]
- wire [3:0] in3valid = {_in3_T_1,1'h0,2'h0}; // @[Cat.scala 31:58]
- wire _valid_T = in0pos == 2'h0; // @[Fifo4e.scala 92:28]
- wire _valid_T_3 = in1pos == 2'h0; // @[Fifo4e.scala 93:28]
- wire _valid_T_5 = in1pos == 2'h0 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_6 = in0pos == 2'h0 & in0valid[3] | _valid_T_5; // @[Fifo4e.scala 92:51]
- wire _valid_T_7 = in2pos == 2'h0; // @[Fifo4e.scala 94:28]
- wire _valid_T_9 = in2pos == 2'h0 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_10 = _valid_T_6 | _valid_T_9; // @[Fifo4e.scala 93:51]
- wire _valid_T_13 = in3pos == 2'h0 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_14 = _valid_T_10 | _valid_T_13; // @[Fifo4e.scala 94:51]
- wire _valid_T_20 = _valid_T_3 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_21 = _valid_T & in0valid[2] | _valid_T_20; // @[Fifo4e.scala 96:51]
- wire _valid_T_24 = _valid_T_7 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_25 = _valid_T_21 | _valid_T_24; // @[Fifo4e.scala 97:51]
- wire _valid_T_31 = _valid_T_3 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_32 = _valid_T & in0valid[1] | _valid_T_31; // @[Fifo4e.scala 99:51]
- wire _valid_T_35 = _valid_T & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid = {_valid_T_14,_valid_T_25,_valid_T_32,_valid_T_35}; // @[Cat.scala 31:58]
- wire _GEN_49 = valid[2] ? 1'h0 : valid[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_89 = valid[1] ? 1'h0 : valid[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_109 = valid[1] ? 1'h0 : _GEN_49; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_149 = valid[0] ? 1'h0 : valid[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_169 = valid[0] ? 1'h0 : _GEN_89; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_189 = valid[0] ? 1'h0 : _GEN_109; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_36 = in0pos == 2'h1; // @[Fifo4e.scala 92:28]
- wire _valid_T_39 = in1pos == 2'h1; // @[Fifo4e.scala 93:28]
- wire _valid_T_41 = in1pos == 2'h1 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_42 = in0pos == 2'h1 & in0valid[3] | _valid_T_41; // @[Fifo4e.scala 92:51]
- wire _valid_T_43 = in2pos == 2'h1; // @[Fifo4e.scala 94:28]
- wire _valid_T_45 = in2pos == 2'h1 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_46 = _valid_T_42 | _valid_T_45; // @[Fifo4e.scala 93:51]
- wire _valid_T_49 = in3pos == 2'h1 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_50 = _valid_T_46 | _valid_T_49; // @[Fifo4e.scala 94:51]
- wire _valid_T_56 = _valid_T_39 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_57 = _valid_T_36 & in0valid[2] | _valid_T_56; // @[Fifo4e.scala 96:51]
- wire _valid_T_60 = _valid_T_43 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_61 = _valid_T_57 | _valid_T_60; // @[Fifo4e.scala 97:51]
- wire _valid_T_67 = _valid_T_39 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_68 = _valid_T_36 & in0valid[1] | _valid_T_67; // @[Fifo4e.scala 99:51]
- wire _valid_T_71 = _valid_T_36 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_1 = {_valid_T_50,_valid_T_61,_valid_T_68,_valid_T_71}; // @[Cat.scala 31:58]
- wire _GEN_327 = valid_1[2] ? 1'h0 : valid_1[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_365 = valid_1[1] ? 1'h0 : valid_1[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_384 = valid_1[1] ? 1'h0 : _GEN_327; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_422 = valid_1[0] ? 1'h0 : valid_1[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_441 = valid_1[0] ? 1'h0 : _GEN_365; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_460 = valid_1[0] ? 1'h0 : _GEN_384; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_72 = in0pos == 2'h2; // @[Fifo4e.scala 92:28]
- wire _valid_T_75 = in1pos == 2'h2; // @[Fifo4e.scala 93:28]
- wire _valid_T_77 = in1pos == 2'h2 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_78 = in0pos == 2'h2 & in0valid[3] | _valid_T_77; // @[Fifo4e.scala 92:51]
- wire _valid_T_79 = in2pos == 2'h2; // @[Fifo4e.scala 94:28]
- wire _valid_T_81 = in2pos == 2'h2 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_82 = _valid_T_78 | _valid_T_81; // @[Fifo4e.scala 93:51]
- wire _valid_T_85 = in3pos == 2'h2 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_86 = _valid_T_82 | _valid_T_85; // @[Fifo4e.scala 94:51]
- wire _valid_T_92 = _valid_T_75 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_93 = _valid_T_72 & in0valid[2] | _valid_T_92; // @[Fifo4e.scala 96:51]
- wire _valid_T_96 = _valid_T_79 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_97 = _valid_T_93 | _valid_T_96; // @[Fifo4e.scala 97:51]
- wire _valid_T_103 = _valid_T_75 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_104 = _valid_T_72 & in0valid[1] | _valid_T_103; // @[Fifo4e.scala 99:51]
- wire _valid_T_107 = _valid_T_72 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_2 = {_valid_T_86,_valid_T_97,_valid_T_104,_valid_T_107}; // @[Cat.scala 31:58]
- wire _GEN_595 = valid_2[2] ? 1'h0 : valid_2[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_635 = valid_2[1] ? 1'h0 : valid_2[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_655 = valid_2[1] ? 1'h0 : _GEN_595; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_695 = valid_2[0] ? 1'h0 : valid_2[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_715 = valid_2[0] ? 1'h0 : _GEN_635; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_735 = valid_2[0] ? 1'h0 : _GEN_655; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_108 = in0pos == 2'h3; // @[Fifo4e.scala 92:28]
- wire _valid_T_111 = in1pos == 2'h3; // @[Fifo4e.scala 93:28]
- wire _valid_T_113 = in1pos == 2'h3 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_114 = in0pos == 2'h3 & in0valid[3] | _valid_T_113; // @[Fifo4e.scala 92:51]
- wire _valid_T_115 = in2pos == 2'h3; // @[Fifo4e.scala 94:28]
- wire _valid_T_117 = in2pos == 2'h3 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_118 = _valid_T_114 | _valid_T_117; // @[Fifo4e.scala 93:51]
- wire _valid_T_121 = in3pos == 2'h3 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_122 = _valid_T_118 | _valid_T_121; // @[Fifo4e.scala 94:51]
- wire _valid_T_128 = _valid_T_111 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_129 = _valid_T_108 & in0valid[2] | _valid_T_128; // @[Fifo4e.scala 96:51]
- wire _valid_T_132 = _valid_T_115 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_133 = _valid_T_129 | _valid_T_132; // @[Fifo4e.scala 97:51]
- wire _valid_T_139 = _valid_T_111 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_140 = _valid_T_108 & in0valid[1] | _valid_T_139; // @[Fifo4e.scala 99:51]
- wire _valid_T_143 = _valid_T_108 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_3 = {_valid_T_122,_valid_T_133,_valid_T_140,_valid_T_143}; // @[Cat.scala 31:58]
- wire _GEN_875 = valid_3[2] ? 1'h0 : valid_3[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_915 = valid_3[1] ? 1'h0 : valid_3[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_935 = valid_3[1] ? 1'h0 : _GEN_875; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_975 = valid_3[0] ? 1'h0 : valid_3[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_995 = valid_3[0] ? 1'h0 : _GEN_915; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1015 = valid_3[0] ? 1'h0 : _GEN_935; // @[Fifo4e.scala 104:23 43:16]
- reg [3:0] active; // @[Fifo4e.scala 118:23]
- wire [3:0] _GEN_0 = {{3'd0}, icount >= 3'h1}; // @[Fifo4e.scala 121:24]
- wire [3:0] _activeSet_T_1 = _GEN_0 << in0pos; // @[Fifo4e.scala 121:24]
- wire [3:0] _GEN_1 = {{3'd0}, icount >= 3'h2}; // @[Fifo4e.scala 121:54]
- wire [3:0] _activeSet_T_3 = _GEN_1 << in1pos; // @[Fifo4e.scala 121:54]
- wire [3:0] _activeSet_T_4 = _activeSet_T_1 | _activeSet_T_3; // @[Fifo4e.scala 121:35]
- wire [3:0] _GEN_2 = {{3'd0}, icount >= 3'h3}; // @[Fifo4e.scala 122:24]
- wire [3:0] _activeSet_T_6 = _GEN_2 << in2pos; // @[Fifo4e.scala 122:24]
- wire [3:0] _activeSet_T_7 = _activeSet_T_4 | _activeSet_T_6; // @[Fifo4e.scala 121:65]
- wire [3:0] _GEN_3 = {{3'd0}, icount >= 3'h4}; // @[Fifo4e.scala 122:54]
- wire [3:0] _activeSet_T_9 = _GEN_3 << in3pos; // @[Fifo4e.scala 122:54]
- wire [3:0] _activeSet_T_10 = _activeSet_T_7 | _activeSet_T_9; // @[Fifo4e.scala 122:35]
- wire [3:0] activeSet = ivalid ? _activeSet_T_10 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _activeClr_T_1 = 4'h1 << outpos; // @[Fifo4e.scala 124:59]
- wire [3:0] activeClr = dec ? _activeClr_T_1 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _active_T = active | activeSet; // @[Fifo4e.scala 127:23]
- wire [3:0] _active_T_1 = ~activeClr; // @[Fifo4e.scala 127:38]
- wire [3:0] _active_T_2 = _active_T & _active_T_1; // @[Fifo4e.scala 127:36]
- wire [2:0] _io_in_ready_T_1 = 3'h4 - icount; // @[Fifo4e.scala 132:33]
- assign mem_tin_conv_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_conv_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_conv_io_out_bits_MPORT_data = mem_tin_conv[mem_tin_conv_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_conv_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_conv_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_conv_io_entry_0_bits_MPORT_data = mem_tin_conv[mem_tin_conv_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_conv_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_conv_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_conv_io_entry_1_bits_MPORT_data = mem_tin_conv[mem_tin_conv_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_conv_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_conv_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_conv_io_entry_2_bits_MPORT_data = mem_tin_conv[mem_tin_conv_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_conv_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_conv_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_conv_io_entry_3_bits_MPORT_data = mem_tin_conv[mem_tin_conv_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_conv_MPORT_data = io_in_bits_0_bits_tin_conv;
- assign mem_tin_conv_MPORT_addr = 2'h0;
- assign mem_tin_conv_MPORT_mask = 1'h1;
- assign mem_tin_conv_MPORT_en = ivalid & valid[0];
- assign mem_tin_conv_MPORT_1_data = io_in_bits_1_bits_tin_conv;
- assign mem_tin_conv_MPORT_1_addr = 2'h0;
- assign mem_tin_conv_MPORT_1_mask = 1'h1;
- assign mem_tin_conv_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_conv_MPORT_2_data = io_in_bits_2_bits_tin_conv;
- assign mem_tin_conv_MPORT_2_addr = 2'h0;
- assign mem_tin_conv_MPORT_2_mask = 1'h1;
- assign mem_tin_conv_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_conv_MPORT_3_data = io_in_bits_3_bits_tin_conv;
- assign mem_tin_conv_MPORT_3_addr = 2'h0;
- assign mem_tin_conv_MPORT_3_mask = 1'h1;
- assign mem_tin_conv_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_conv_MPORT_4_data = io_in_bits_0_bits_tin_conv;
- assign mem_tin_conv_MPORT_4_addr = 2'h1;
- assign mem_tin_conv_MPORT_4_mask = 1'h1;
- assign mem_tin_conv_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_conv_MPORT_5_data = io_in_bits_1_bits_tin_conv;
- assign mem_tin_conv_MPORT_5_addr = 2'h1;
- assign mem_tin_conv_MPORT_5_mask = 1'h1;
- assign mem_tin_conv_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_conv_MPORT_6_data = io_in_bits_2_bits_tin_conv;
- assign mem_tin_conv_MPORT_6_addr = 2'h1;
- assign mem_tin_conv_MPORT_6_mask = 1'h1;
- assign mem_tin_conv_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_conv_MPORT_7_data = io_in_bits_3_bits_tin_conv;
- assign mem_tin_conv_MPORT_7_addr = 2'h1;
- assign mem_tin_conv_MPORT_7_mask = 1'h1;
- assign mem_tin_conv_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_conv_MPORT_8_data = io_in_bits_0_bits_tin_conv;
- assign mem_tin_conv_MPORT_8_addr = 2'h2;
- assign mem_tin_conv_MPORT_8_mask = 1'h1;
- assign mem_tin_conv_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_conv_MPORT_9_data = io_in_bits_1_bits_tin_conv;
- assign mem_tin_conv_MPORT_9_addr = 2'h2;
- assign mem_tin_conv_MPORT_9_mask = 1'h1;
- assign mem_tin_conv_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_conv_MPORT_10_data = io_in_bits_2_bits_tin_conv;
- assign mem_tin_conv_MPORT_10_addr = 2'h2;
- assign mem_tin_conv_MPORT_10_mask = 1'h1;
- assign mem_tin_conv_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_conv_MPORT_11_data = io_in_bits_3_bits_tin_conv;
- assign mem_tin_conv_MPORT_11_addr = 2'h2;
- assign mem_tin_conv_MPORT_11_mask = 1'h1;
- assign mem_tin_conv_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_conv_MPORT_12_data = io_in_bits_0_bits_tin_conv;
- assign mem_tin_conv_MPORT_12_addr = 2'h3;
- assign mem_tin_conv_MPORT_12_mask = 1'h1;
- assign mem_tin_conv_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_conv_MPORT_13_data = io_in_bits_1_bits_tin_conv;
- assign mem_tin_conv_MPORT_13_addr = 2'h3;
- assign mem_tin_conv_MPORT_13_mask = 1'h1;
- assign mem_tin_conv_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_conv_MPORT_14_data = io_in_bits_2_bits_tin_conv;
- assign mem_tin_conv_MPORT_14_addr = 2'h3;
- assign mem_tin_conv_MPORT_14_mask = 1'h1;
- assign mem_tin_conv_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_conv_MPORT_15_data = io_in_bits_3_bits_tin_conv;
- assign mem_tin_conv_MPORT_15_addr = 2'h3;
- assign mem_tin_conv_MPORT_15_mask = 1'h1;
- assign mem_tin_conv_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_init_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_init_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_init_io_out_bits_MPORT_data = mem_tin_init[mem_tin_init_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_init_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_init_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_init_io_entry_0_bits_MPORT_data = mem_tin_init[mem_tin_init_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_init_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_init_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_init_io_entry_1_bits_MPORT_data = mem_tin_init[mem_tin_init_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_init_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_init_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_init_io_entry_2_bits_MPORT_data = mem_tin_init[mem_tin_init_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_init_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_init_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_init_io_entry_3_bits_MPORT_data = mem_tin_init[mem_tin_init_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_init_MPORT_data = io_in_bits_0_bits_tin_init;
- assign mem_tin_init_MPORT_addr = 2'h0;
- assign mem_tin_init_MPORT_mask = 1'h1;
- assign mem_tin_init_MPORT_en = ivalid & valid[0];
- assign mem_tin_init_MPORT_1_data = io_in_bits_1_bits_tin_init;
- assign mem_tin_init_MPORT_1_addr = 2'h0;
- assign mem_tin_init_MPORT_1_mask = 1'h1;
- assign mem_tin_init_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_init_MPORT_2_data = io_in_bits_2_bits_tin_init;
- assign mem_tin_init_MPORT_2_addr = 2'h0;
- assign mem_tin_init_MPORT_2_mask = 1'h1;
- assign mem_tin_init_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_init_MPORT_3_data = io_in_bits_3_bits_tin_init;
- assign mem_tin_init_MPORT_3_addr = 2'h0;
- assign mem_tin_init_MPORT_3_mask = 1'h1;
- assign mem_tin_init_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_init_MPORT_4_data = io_in_bits_0_bits_tin_init;
- assign mem_tin_init_MPORT_4_addr = 2'h1;
- assign mem_tin_init_MPORT_4_mask = 1'h1;
- assign mem_tin_init_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_init_MPORT_5_data = io_in_bits_1_bits_tin_init;
- assign mem_tin_init_MPORT_5_addr = 2'h1;
- assign mem_tin_init_MPORT_5_mask = 1'h1;
- assign mem_tin_init_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_init_MPORT_6_data = io_in_bits_2_bits_tin_init;
- assign mem_tin_init_MPORT_6_addr = 2'h1;
- assign mem_tin_init_MPORT_6_mask = 1'h1;
- assign mem_tin_init_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_init_MPORT_7_data = io_in_bits_3_bits_tin_init;
- assign mem_tin_init_MPORT_7_addr = 2'h1;
- assign mem_tin_init_MPORT_7_mask = 1'h1;
- assign mem_tin_init_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_init_MPORT_8_data = io_in_bits_0_bits_tin_init;
- assign mem_tin_init_MPORT_8_addr = 2'h2;
- assign mem_tin_init_MPORT_8_mask = 1'h1;
- assign mem_tin_init_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_init_MPORT_9_data = io_in_bits_1_bits_tin_init;
- assign mem_tin_init_MPORT_9_addr = 2'h2;
- assign mem_tin_init_MPORT_9_mask = 1'h1;
- assign mem_tin_init_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_init_MPORT_10_data = io_in_bits_2_bits_tin_init;
- assign mem_tin_init_MPORT_10_addr = 2'h2;
- assign mem_tin_init_MPORT_10_mask = 1'h1;
- assign mem_tin_init_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_init_MPORT_11_data = io_in_bits_3_bits_tin_init;
- assign mem_tin_init_MPORT_11_addr = 2'h2;
- assign mem_tin_init_MPORT_11_mask = 1'h1;
- assign mem_tin_init_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_init_MPORT_12_data = io_in_bits_0_bits_tin_init;
- assign mem_tin_init_MPORT_12_addr = 2'h3;
- assign mem_tin_init_MPORT_12_mask = 1'h1;
- assign mem_tin_init_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_init_MPORT_13_data = io_in_bits_1_bits_tin_init;
- assign mem_tin_init_MPORT_13_addr = 2'h3;
- assign mem_tin_init_MPORT_13_mask = 1'h1;
- assign mem_tin_init_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_init_MPORT_14_data = io_in_bits_2_bits_tin_init;
- assign mem_tin_init_MPORT_14_addr = 2'h3;
- assign mem_tin_init_MPORT_14_mask = 1'h1;
- assign mem_tin_init_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_init_MPORT_15_data = io_in_bits_3_bits_tin_init;
- assign mem_tin_init_MPORT_15_addr = 2'h3;
- assign mem_tin_init_MPORT_15_mask = 1'h1;
- assign mem_tin_init_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_tran_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_tran_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_tran_io_out_bits_MPORT_data = mem_tin_tran[mem_tin_tran_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_tran_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_tran_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_tran_io_entry_0_bits_MPORT_data = mem_tin_tran[mem_tin_tran_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_tran_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_tran_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_tran_io_entry_1_bits_MPORT_data = mem_tin_tran[mem_tin_tran_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_tran_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_tran_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_tran_io_entry_2_bits_MPORT_data = mem_tin_tran[mem_tin_tran_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_tran_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_tran_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_tran_io_entry_3_bits_MPORT_data = mem_tin_tran[mem_tin_tran_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_tran_MPORT_data = io_in_bits_0_bits_tin_tran;
- assign mem_tin_tran_MPORT_addr = 2'h0;
- assign mem_tin_tran_MPORT_mask = 1'h1;
- assign mem_tin_tran_MPORT_en = ivalid & valid[0];
- assign mem_tin_tran_MPORT_1_data = io_in_bits_1_bits_tin_tran;
- assign mem_tin_tran_MPORT_1_addr = 2'h0;
- assign mem_tin_tran_MPORT_1_mask = 1'h1;
- assign mem_tin_tran_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_tran_MPORT_2_data = io_in_bits_2_bits_tin_tran;
- assign mem_tin_tran_MPORT_2_addr = 2'h0;
- assign mem_tin_tran_MPORT_2_mask = 1'h1;
- assign mem_tin_tran_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_tran_MPORT_3_data = io_in_bits_3_bits_tin_tran;
- assign mem_tin_tran_MPORT_3_addr = 2'h0;
- assign mem_tin_tran_MPORT_3_mask = 1'h1;
- assign mem_tin_tran_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_tran_MPORT_4_data = io_in_bits_0_bits_tin_tran;
- assign mem_tin_tran_MPORT_4_addr = 2'h1;
- assign mem_tin_tran_MPORT_4_mask = 1'h1;
- assign mem_tin_tran_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_tran_MPORT_5_data = io_in_bits_1_bits_tin_tran;
- assign mem_tin_tran_MPORT_5_addr = 2'h1;
- assign mem_tin_tran_MPORT_5_mask = 1'h1;
- assign mem_tin_tran_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_tran_MPORT_6_data = io_in_bits_2_bits_tin_tran;
- assign mem_tin_tran_MPORT_6_addr = 2'h1;
- assign mem_tin_tran_MPORT_6_mask = 1'h1;
- assign mem_tin_tran_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_tran_MPORT_7_data = io_in_bits_3_bits_tin_tran;
- assign mem_tin_tran_MPORT_7_addr = 2'h1;
- assign mem_tin_tran_MPORT_7_mask = 1'h1;
- assign mem_tin_tran_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_tran_MPORT_8_data = io_in_bits_0_bits_tin_tran;
- assign mem_tin_tran_MPORT_8_addr = 2'h2;
- assign mem_tin_tran_MPORT_8_mask = 1'h1;
- assign mem_tin_tran_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_tran_MPORT_9_data = io_in_bits_1_bits_tin_tran;
- assign mem_tin_tran_MPORT_9_addr = 2'h2;
- assign mem_tin_tran_MPORT_9_mask = 1'h1;
- assign mem_tin_tran_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_tran_MPORT_10_data = io_in_bits_2_bits_tin_tran;
- assign mem_tin_tran_MPORT_10_addr = 2'h2;
- assign mem_tin_tran_MPORT_10_mask = 1'h1;
- assign mem_tin_tran_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_tran_MPORT_11_data = io_in_bits_3_bits_tin_tran;
- assign mem_tin_tran_MPORT_11_addr = 2'h2;
- assign mem_tin_tran_MPORT_11_mask = 1'h1;
- assign mem_tin_tran_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_tran_MPORT_12_data = io_in_bits_0_bits_tin_tran;
- assign mem_tin_tran_MPORT_12_addr = 2'h3;
- assign mem_tin_tran_MPORT_12_mask = 1'h1;
- assign mem_tin_tran_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_tran_MPORT_13_data = io_in_bits_1_bits_tin_tran;
- assign mem_tin_tran_MPORT_13_addr = 2'h3;
- assign mem_tin_tran_MPORT_13_mask = 1'h1;
- assign mem_tin_tran_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_tran_MPORT_14_data = io_in_bits_2_bits_tin_tran;
- assign mem_tin_tran_MPORT_14_addr = 2'h3;
- assign mem_tin_tran_MPORT_14_mask = 1'h1;
- assign mem_tin_tran_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_tran_MPORT_15_data = io_in_bits_3_bits_tin_tran;
- assign mem_tin_tran_MPORT_15_addr = 2'h3;
- assign mem_tin_tran_MPORT_15_mask = 1'h1;
- assign mem_tin_tran_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_wclr_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_wclr_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_wclr_io_out_bits_MPORT_data = mem_tin_wclr[mem_tin_wclr_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_wclr_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_wclr_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_wclr_io_entry_0_bits_MPORT_data = mem_tin_wclr[mem_tin_wclr_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_wclr_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_wclr_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_wclr_io_entry_1_bits_MPORT_data = mem_tin_wclr[mem_tin_wclr_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_wclr_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_wclr_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_wclr_io_entry_2_bits_MPORT_data = mem_tin_wclr[mem_tin_wclr_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_wclr_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_wclr_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_wclr_io_entry_3_bits_MPORT_data = mem_tin_wclr[mem_tin_wclr_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_wclr_MPORT_data = io_in_bits_0_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_addr = 2'h0;
- assign mem_tin_wclr_MPORT_mask = 1'h1;
- assign mem_tin_wclr_MPORT_en = ivalid & valid[0];
- assign mem_tin_wclr_MPORT_1_data = io_in_bits_1_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_1_addr = 2'h0;
- assign mem_tin_wclr_MPORT_1_mask = 1'h1;
- assign mem_tin_wclr_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_wclr_MPORT_2_data = io_in_bits_2_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_2_addr = 2'h0;
- assign mem_tin_wclr_MPORT_2_mask = 1'h1;
- assign mem_tin_wclr_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_wclr_MPORT_3_data = io_in_bits_3_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_3_addr = 2'h0;
- assign mem_tin_wclr_MPORT_3_mask = 1'h1;
- assign mem_tin_wclr_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_wclr_MPORT_4_data = io_in_bits_0_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_4_addr = 2'h1;
- assign mem_tin_wclr_MPORT_4_mask = 1'h1;
- assign mem_tin_wclr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_wclr_MPORT_5_data = io_in_bits_1_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_5_addr = 2'h1;
- assign mem_tin_wclr_MPORT_5_mask = 1'h1;
- assign mem_tin_wclr_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_wclr_MPORT_6_data = io_in_bits_2_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_6_addr = 2'h1;
- assign mem_tin_wclr_MPORT_6_mask = 1'h1;
- assign mem_tin_wclr_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_wclr_MPORT_7_data = io_in_bits_3_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_7_addr = 2'h1;
- assign mem_tin_wclr_MPORT_7_mask = 1'h1;
- assign mem_tin_wclr_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_wclr_MPORT_8_data = io_in_bits_0_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_8_addr = 2'h2;
- assign mem_tin_wclr_MPORT_8_mask = 1'h1;
- assign mem_tin_wclr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_wclr_MPORT_9_data = io_in_bits_1_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_9_addr = 2'h2;
- assign mem_tin_wclr_MPORT_9_mask = 1'h1;
- assign mem_tin_wclr_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_wclr_MPORT_10_data = io_in_bits_2_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_10_addr = 2'h2;
- assign mem_tin_wclr_MPORT_10_mask = 1'h1;
- assign mem_tin_wclr_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_wclr_MPORT_11_data = io_in_bits_3_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_11_addr = 2'h2;
- assign mem_tin_wclr_MPORT_11_mask = 1'h1;
- assign mem_tin_wclr_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_wclr_MPORT_12_data = io_in_bits_0_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_12_addr = 2'h3;
- assign mem_tin_wclr_MPORT_12_mask = 1'h1;
- assign mem_tin_wclr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_wclr_MPORT_13_data = io_in_bits_1_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_13_addr = 2'h3;
- assign mem_tin_wclr_MPORT_13_mask = 1'h1;
- assign mem_tin_wclr_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_wclr_MPORT_14_data = io_in_bits_2_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_14_addr = 2'h3;
- assign mem_tin_wclr_MPORT_14_mask = 1'h1;
- assign mem_tin_wclr_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_wclr_MPORT_15_data = io_in_bits_3_bits_tin_wclr;
- assign mem_tin_wclr_MPORT_15_addr = 2'h3;
- assign mem_tin_wclr_MPORT_15_mask = 1'h1;
- assign mem_tin_wclr_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_addr1_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_addr1_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_addr1_io_out_bits_MPORT_data = mem_tin_addr1[mem_tin_addr1_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr1_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_addr1_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_addr1_io_entry_0_bits_MPORT_data = mem_tin_addr1[mem_tin_addr1_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr1_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_addr1_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_addr1_io_entry_1_bits_MPORT_data = mem_tin_addr1[mem_tin_addr1_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr1_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_addr1_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_addr1_io_entry_2_bits_MPORT_data = mem_tin_addr1[mem_tin_addr1_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr1_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_addr1_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_addr1_io_entry_3_bits_MPORT_data = mem_tin_addr1[mem_tin_addr1_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr1_MPORT_data = io_in_bits_0_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_addr = 2'h0;
- assign mem_tin_addr1_MPORT_mask = 1'h1;
- assign mem_tin_addr1_MPORT_en = ivalid & valid[0];
- assign mem_tin_addr1_MPORT_1_data = io_in_bits_1_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_1_addr = 2'h0;
- assign mem_tin_addr1_MPORT_1_mask = 1'h1;
- assign mem_tin_addr1_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_addr1_MPORT_2_data = io_in_bits_2_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_2_addr = 2'h0;
- assign mem_tin_addr1_MPORT_2_mask = 1'h1;
- assign mem_tin_addr1_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_addr1_MPORT_3_data = io_in_bits_3_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_3_addr = 2'h0;
- assign mem_tin_addr1_MPORT_3_mask = 1'h1;
- assign mem_tin_addr1_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_addr1_MPORT_4_data = io_in_bits_0_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_4_addr = 2'h1;
- assign mem_tin_addr1_MPORT_4_mask = 1'h1;
- assign mem_tin_addr1_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_addr1_MPORT_5_data = io_in_bits_1_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_5_addr = 2'h1;
- assign mem_tin_addr1_MPORT_5_mask = 1'h1;
- assign mem_tin_addr1_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_addr1_MPORT_6_data = io_in_bits_2_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_6_addr = 2'h1;
- assign mem_tin_addr1_MPORT_6_mask = 1'h1;
- assign mem_tin_addr1_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_addr1_MPORT_7_data = io_in_bits_3_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_7_addr = 2'h1;
- assign mem_tin_addr1_MPORT_7_mask = 1'h1;
- assign mem_tin_addr1_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_addr1_MPORT_8_data = io_in_bits_0_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_8_addr = 2'h2;
- assign mem_tin_addr1_MPORT_8_mask = 1'h1;
- assign mem_tin_addr1_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_addr1_MPORT_9_data = io_in_bits_1_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_9_addr = 2'h2;
- assign mem_tin_addr1_MPORT_9_mask = 1'h1;
- assign mem_tin_addr1_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_addr1_MPORT_10_data = io_in_bits_2_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_10_addr = 2'h2;
- assign mem_tin_addr1_MPORT_10_mask = 1'h1;
- assign mem_tin_addr1_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_addr1_MPORT_11_data = io_in_bits_3_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_11_addr = 2'h2;
- assign mem_tin_addr1_MPORT_11_mask = 1'h1;
- assign mem_tin_addr1_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_addr1_MPORT_12_data = io_in_bits_0_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_12_addr = 2'h3;
- assign mem_tin_addr1_MPORT_12_mask = 1'h1;
- assign mem_tin_addr1_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_addr1_MPORT_13_data = io_in_bits_1_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_13_addr = 2'h3;
- assign mem_tin_addr1_MPORT_13_mask = 1'h1;
- assign mem_tin_addr1_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_addr1_MPORT_14_data = io_in_bits_2_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_14_addr = 2'h3;
- assign mem_tin_addr1_MPORT_14_mask = 1'h1;
- assign mem_tin_addr1_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_addr1_MPORT_15_data = io_in_bits_3_bits_tin_addr1;
- assign mem_tin_addr1_MPORT_15_addr = 2'h3;
- assign mem_tin_addr1_MPORT_15_mask = 1'h1;
- assign mem_tin_addr1_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_addr2_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_addr2_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_addr2_io_out_bits_MPORT_data = mem_tin_addr2[mem_tin_addr2_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr2_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_addr2_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_addr2_io_entry_0_bits_MPORT_data = mem_tin_addr2[mem_tin_addr2_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr2_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_addr2_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_addr2_io_entry_1_bits_MPORT_data = mem_tin_addr2[mem_tin_addr2_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr2_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_addr2_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_addr2_io_entry_2_bits_MPORT_data = mem_tin_addr2[mem_tin_addr2_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr2_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_addr2_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_addr2_io_entry_3_bits_MPORT_data = mem_tin_addr2[mem_tin_addr2_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr2_MPORT_data = io_in_bits_0_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_addr = 2'h0;
- assign mem_tin_addr2_MPORT_mask = 1'h1;
- assign mem_tin_addr2_MPORT_en = ivalid & valid[0];
- assign mem_tin_addr2_MPORT_1_data = io_in_bits_1_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_1_addr = 2'h0;
- assign mem_tin_addr2_MPORT_1_mask = 1'h1;
- assign mem_tin_addr2_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_addr2_MPORT_2_data = io_in_bits_2_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_2_addr = 2'h0;
- assign mem_tin_addr2_MPORT_2_mask = 1'h1;
- assign mem_tin_addr2_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_addr2_MPORT_3_data = io_in_bits_3_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_3_addr = 2'h0;
- assign mem_tin_addr2_MPORT_3_mask = 1'h1;
- assign mem_tin_addr2_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_addr2_MPORT_4_data = io_in_bits_0_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_4_addr = 2'h1;
- assign mem_tin_addr2_MPORT_4_mask = 1'h1;
- assign mem_tin_addr2_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_addr2_MPORT_5_data = io_in_bits_1_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_5_addr = 2'h1;
- assign mem_tin_addr2_MPORT_5_mask = 1'h1;
- assign mem_tin_addr2_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_addr2_MPORT_6_data = io_in_bits_2_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_6_addr = 2'h1;
- assign mem_tin_addr2_MPORT_6_mask = 1'h1;
- assign mem_tin_addr2_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_addr2_MPORT_7_data = io_in_bits_3_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_7_addr = 2'h1;
- assign mem_tin_addr2_MPORT_7_mask = 1'h1;
- assign mem_tin_addr2_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_addr2_MPORT_8_data = io_in_bits_0_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_8_addr = 2'h2;
- assign mem_tin_addr2_MPORT_8_mask = 1'h1;
- assign mem_tin_addr2_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_addr2_MPORT_9_data = io_in_bits_1_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_9_addr = 2'h2;
- assign mem_tin_addr2_MPORT_9_mask = 1'h1;
- assign mem_tin_addr2_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_addr2_MPORT_10_data = io_in_bits_2_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_10_addr = 2'h2;
- assign mem_tin_addr2_MPORT_10_mask = 1'h1;
- assign mem_tin_addr2_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_addr2_MPORT_11_data = io_in_bits_3_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_11_addr = 2'h2;
- assign mem_tin_addr2_MPORT_11_mask = 1'h1;
- assign mem_tin_addr2_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_addr2_MPORT_12_data = io_in_bits_0_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_12_addr = 2'h3;
- assign mem_tin_addr2_MPORT_12_mask = 1'h1;
- assign mem_tin_addr2_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_addr2_MPORT_13_data = io_in_bits_1_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_13_addr = 2'h3;
- assign mem_tin_addr2_MPORT_13_mask = 1'h1;
- assign mem_tin_addr2_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_addr2_MPORT_14_data = io_in_bits_2_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_14_addr = 2'h3;
- assign mem_tin_addr2_MPORT_14_mask = 1'h1;
- assign mem_tin_addr2_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_addr2_MPORT_15_data = io_in_bits_3_bits_tin_addr2;
- assign mem_tin_addr2_MPORT_15_addr = 2'h3;
- assign mem_tin_addr2_MPORT_15_mask = 1'h1;
- assign mem_tin_addr2_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_base2_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_base2_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_base2_io_out_bits_MPORT_data = mem_tin_base2[mem_tin_base2_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_base2_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_base2_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_base2_io_entry_0_bits_MPORT_data = mem_tin_base2[mem_tin_base2_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_base2_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_base2_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_base2_io_entry_1_bits_MPORT_data = mem_tin_base2[mem_tin_base2_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_base2_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_base2_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_base2_io_entry_2_bits_MPORT_data = mem_tin_base2[mem_tin_base2_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_base2_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_base2_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_base2_io_entry_3_bits_MPORT_data = mem_tin_base2[mem_tin_base2_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_base2_MPORT_data = io_in_bits_0_bits_tin_base2;
- assign mem_tin_base2_MPORT_addr = 2'h0;
- assign mem_tin_base2_MPORT_mask = 1'h1;
- assign mem_tin_base2_MPORT_en = ivalid & valid[0];
- assign mem_tin_base2_MPORT_1_data = io_in_bits_1_bits_tin_base2;
- assign mem_tin_base2_MPORT_1_addr = 2'h0;
- assign mem_tin_base2_MPORT_1_mask = 1'h1;
- assign mem_tin_base2_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_base2_MPORT_2_data = io_in_bits_2_bits_tin_base2;
- assign mem_tin_base2_MPORT_2_addr = 2'h0;
- assign mem_tin_base2_MPORT_2_mask = 1'h1;
- assign mem_tin_base2_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_base2_MPORT_3_data = io_in_bits_3_bits_tin_base2;
- assign mem_tin_base2_MPORT_3_addr = 2'h0;
- assign mem_tin_base2_MPORT_3_mask = 1'h1;
- assign mem_tin_base2_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_base2_MPORT_4_data = io_in_bits_0_bits_tin_base2;
- assign mem_tin_base2_MPORT_4_addr = 2'h1;
- assign mem_tin_base2_MPORT_4_mask = 1'h1;
- assign mem_tin_base2_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_base2_MPORT_5_data = io_in_bits_1_bits_tin_base2;
- assign mem_tin_base2_MPORT_5_addr = 2'h1;
- assign mem_tin_base2_MPORT_5_mask = 1'h1;
- assign mem_tin_base2_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_base2_MPORT_6_data = io_in_bits_2_bits_tin_base2;
- assign mem_tin_base2_MPORT_6_addr = 2'h1;
- assign mem_tin_base2_MPORT_6_mask = 1'h1;
- assign mem_tin_base2_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_base2_MPORT_7_data = io_in_bits_3_bits_tin_base2;
- assign mem_tin_base2_MPORT_7_addr = 2'h1;
- assign mem_tin_base2_MPORT_7_mask = 1'h1;
- assign mem_tin_base2_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_base2_MPORT_8_data = io_in_bits_0_bits_tin_base2;
- assign mem_tin_base2_MPORT_8_addr = 2'h2;
- assign mem_tin_base2_MPORT_8_mask = 1'h1;
- assign mem_tin_base2_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_base2_MPORT_9_data = io_in_bits_1_bits_tin_base2;
- assign mem_tin_base2_MPORT_9_addr = 2'h2;
- assign mem_tin_base2_MPORT_9_mask = 1'h1;
- assign mem_tin_base2_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_base2_MPORT_10_data = io_in_bits_2_bits_tin_base2;
- assign mem_tin_base2_MPORT_10_addr = 2'h2;
- assign mem_tin_base2_MPORT_10_mask = 1'h1;
- assign mem_tin_base2_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_base2_MPORT_11_data = io_in_bits_3_bits_tin_base2;
- assign mem_tin_base2_MPORT_11_addr = 2'h2;
- assign mem_tin_base2_MPORT_11_mask = 1'h1;
- assign mem_tin_base2_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_base2_MPORT_12_data = io_in_bits_0_bits_tin_base2;
- assign mem_tin_base2_MPORT_12_addr = 2'h3;
- assign mem_tin_base2_MPORT_12_mask = 1'h1;
- assign mem_tin_base2_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_base2_MPORT_13_data = io_in_bits_1_bits_tin_base2;
- assign mem_tin_base2_MPORT_13_addr = 2'h3;
- assign mem_tin_base2_MPORT_13_mask = 1'h1;
- assign mem_tin_base2_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_base2_MPORT_14_data = io_in_bits_2_bits_tin_base2;
- assign mem_tin_base2_MPORT_14_addr = 2'h3;
- assign mem_tin_base2_MPORT_14_mask = 1'h1;
- assign mem_tin_base2_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_base2_MPORT_15_data = io_in_bits_3_bits_tin_base2;
- assign mem_tin_base2_MPORT_15_addr = 2'h3;
- assign mem_tin_base2_MPORT_15_mask = 1'h1;
- assign mem_tin_base2_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_mode_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_mode_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_mode_io_out_bits_MPORT_data = mem_tin_mode[mem_tin_mode_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_mode_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_mode_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_mode_io_entry_0_bits_MPORT_data = mem_tin_mode[mem_tin_mode_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_mode_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_mode_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_mode_io_entry_1_bits_MPORT_data = mem_tin_mode[mem_tin_mode_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_mode_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_mode_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_mode_io_entry_2_bits_MPORT_data = mem_tin_mode[mem_tin_mode_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_mode_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_mode_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_mode_io_entry_3_bits_MPORT_data = mem_tin_mode[mem_tin_mode_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_mode_MPORT_data = io_in_bits_0_bits_tin_mode;
- assign mem_tin_mode_MPORT_addr = 2'h0;
- assign mem_tin_mode_MPORT_mask = 1'h1;
- assign mem_tin_mode_MPORT_en = ivalid & valid[0];
- assign mem_tin_mode_MPORT_1_data = io_in_bits_1_bits_tin_mode;
- assign mem_tin_mode_MPORT_1_addr = 2'h0;
- assign mem_tin_mode_MPORT_1_mask = 1'h1;
- assign mem_tin_mode_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_mode_MPORT_2_data = io_in_bits_2_bits_tin_mode;
- assign mem_tin_mode_MPORT_2_addr = 2'h0;
- assign mem_tin_mode_MPORT_2_mask = 1'h1;
- assign mem_tin_mode_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_mode_MPORT_3_data = io_in_bits_3_bits_tin_mode;
- assign mem_tin_mode_MPORT_3_addr = 2'h0;
- assign mem_tin_mode_MPORT_3_mask = 1'h1;
- assign mem_tin_mode_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_mode_MPORT_4_data = io_in_bits_0_bits_tin_mode;
- assign mem_tin_mode_MPORT_4_addr = 2'h1;
- assign mem_tin_mode_MPORT_4_mask = 1'h1;
- assign mem_tin_mode_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_mode_MPORT_5_data = io_in_bits_1_bits_tin_mode;
- assign mem_tin_mode_MPORT_5_addr = 2'h1;
- assign mem_tin_mode_MPORT_5_mask = 1'h1;
- assign mem_tin_mode_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_mode_MPORT_6_data = io_in_bits_2_bits_tin_mode;
- assign mem_tin_mode_MPORT_6_addr = 2'h1;
- assign mem_tin_mode_MPORT_6_mask = 1'h1;
- assign mem_tin_mode_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_mode_MPORT_7_data = io_in_bits_3_bits_tin_mode;
- assign mem_tin_mode_MPORT_7_addr = 2'h1;
- assign mem_tin_mode_MPORT_7_mask = 1'h1;
- assign mem_tin_mode_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_mode_MPORT_8_data = io_in_bits_0_bits_tin_mode;
- assign mem_tin_mode_MPORT_8_addr = 2'h2;
- assign mem_tin_mode_MPORT_8_mask = 1'h1;
- assign mem_tin_mode_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_mode_MPORT_9_data = io_in_bits_1_bits_tin_mode;
- assign mem_tin_mode_MPORT_9_addr = 2'h2;
- assign mem_tin_mode_MPORT_9_mask = 1'h1;
- assign mem_tin_mode_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_mode_MPORT_10_data = io_in_bits_2_bits_tin_mode;
- assign mem_tin_mode_MPORT_10_addr = 2'h2;
- assign mem_tin_mode_MPORT_10_mask = 1'h1;
- assign mem_tin_mode_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_mode_MPORT_11_data = io_in_bits_3_bits_tin_mode;
- assign mem_tin_mode_MPORT_11_addr = 2'h2;
- assign mem_tin_mode_MPORT_11_mask = 1'h1;
- assign mem_tin_mode_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_mode_MPORT_12_data = io_in_bits_0_bits_tin_mode;
- assign mem_tin_mode_MPORT_12_addr = 2'h3;
- assign mem_tin_mode_MPORT_12_mask = 1'h1;
- assign mem_tin_mode_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_mode_MPORT_13_data = io_in_bits_1_bits_tin_mode;
- assign mem_tin_mode_MPORT_13_addr = 2'h3;
- assign mem_tin_mode_MPORT_13_mask = 1'h1;
- assign mem_tin_mode_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_mode_MPORT_14_data = io_in_bits_2_bits_tin_mode;
- assign mem_tin_mode_MPORT_14_addr = 2'h3;
- assign mem_tin_mode_MPORT_14_mask = 1'h1;
- assign mem_tin_mode_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_mode_MPORT_15_data = io_in_bits_3_bits_tin_mode;
- assign mem_tin_mode_MPORT_15_addr = 2'h3;
- assign mem_tin_mode_MPORT_15_mask = 1'h1;
- assign mem_tin_mode_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_mark2_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_mark2_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_mark2_io_out_bits_MPORT_data = mem_tin_mark2[mem_tin_mark2_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_mark2_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_mark2_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_mark2_io_entry_0_bits_MPORT_data = mem_tin_mark2[mem_tin_mark2_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_mark2_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_mark2_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_mark2_io_entry_1_bits_MPORT_data = mem_tin_mark2[mem_tin_mark2_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_mark2_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_mark2_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_mark2_io_entry_2_bits_MPORT_data = mem_tin_mark2[mem_tin_mark2_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_mark2_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_mark2_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_mark2_io_entry_3_bits_MPORT_data = mem_tin_mark2[mem_tin_mark2_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_mark2_MPORT_data = io_in_bits_0_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_addr = 2'h0;
- assign mem_tin_mark2_MPORT_mask = 1'h1;
- assign mem_tin_mark2_MPORT_en = ivalid & valid[0];
- assign mem_tin_mark2_MPORT_1_data = io_in_bits_1_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_1_addr = 2'h0;
- assign mem_tin_mark2_MPORT_1_mask = 1'h1;
- assign mem_tin_mark2_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_mark2_MPORT_2_data = io_in_bits_2_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_2_addr = 2'h0;
- assign mem_tin_mark2_MPORT_2_mask = 1'h1;
- assign mem_tin_mark2_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_mark2_MPORT_3_data = io_in_bits_3_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_3_addr = 2'h0;
- assign mem_tin_mark2_MPORT_3_mask = 1'h1;
- assign mem_tin_mark2_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_mark2_MPORT_4_data = io_in_bits_0_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_4_addr = 2'h1;
- assign mem_tin_mark2_MPORT_4_mask = 1'h1;
- assign mem_tin_mark2_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_mark2_MPORT_5_data = io_in_bits_1_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_5_addr = 2'h1;
- assign mem_tin_mark2_MPORT_5_mask = 1'h1;
- assign mem_tin_mark2_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_mark2_MPORT_6_data = io_in_bits_2_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_6_addr = 2'h1;
- assign mem_tin_mark2_MPORT_6_mask = 1'h1;
- assign mem_tin_mark2_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_mark2_MPORT_7_data = io_in_bits_3_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_7_addr = 2'h1;
- assign mem_tin_mark2_MPORT_7_mask = 1'h1;
- assign mem_tin_mark2_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_mark2_MPORT_8_data = io_in_bits_0_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_8_addr = 2'h2;
- assign mem_tin_mark2_MPORT_8_mask = 1'h1;
- assign mem_tin_mark2_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_mark2_MPORT_9_data = io_in_bits_1_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_9_addr = 2'h2;
- assign mem_tin_mark2_MPORT_9_mask = 1'h1;
- assign mem_tin_mark2_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_mark2_MPORT_10_data = io_in_bits_2_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_10_addr = 2'h2;
- assign mem_tin_mark2_MPORT_10_mask = 1'h1;
- assign mem_tin_mark2_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_mark2_MPORT_11_data = io_in_bits_3_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_11_addr = 2'h2;
- assign mem_tin_mark2_MPORT_11_mask = 1'h1;
- assign mem_tin_mark2_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_mark2_MPORT_12_data = io_in_bits_0_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_12_addr = 2'h3;
- assign mem_tin_mark2_MPORT_12_mask = 1'h1;
- assign mem_tin_mark2_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_mark2_MPORT_13_data = io_in_bits_1_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_13_addr = 2'h3;
- assign mem_tin_mark2_MPORT_13_mask = 1'h1;
- assign mem_tin_mark2_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_mark2_MPORT_14_data = io_in_bits_2_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_14_addr = 2'h3;
- assign mem_tin_mark2_MPORT_14_mask = 1'h1;
- assign mem_tin_mark2_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_mark2_MPORT_15_data = io_in_bits_3_bits_tin_mark2;
- assign mem_tin_mark2_MPORT_15_addr = 2'h3;
- assign mem_tin_mark2_MPORT_15_mask = 1'h1;
- assign mem_tin_mark2_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_index_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_index_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_index_io_out_bits_MPORT_data = mem_tin_index[mem_tin_index_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_index_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_index_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_index_io_entry_0_bits_MPORT_data = mem_tin_index[mem_tin_index_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_index_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_index_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_index_io_entry_1_bits_MPORT_data = mem_tin_index[mem_tin_index_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_index_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_index_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_index_io_entry_2_bits_MPORT_data = mem_tin_index[mem_tin_index_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_index_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_index_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_index_io_entry_3_bits_MPORT_data = mem_tin_index[mem_tin_index_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_index_MPORT_data = io_in_bits_0_bits_tin_index;
- assign mem_tin_index_MPORT_addr = 2'h0;
- assign mem_tin_index_MPORT_mask = 1'h1;
- assign mem_tin_index_MPORT_en = ivalid & valid[0];
- assign mem_tin_index_MPORT_1_data = io_in_bits_1_bits_tin_index;
- assign mem_tin_index_MPORT_1_addr = 2'h0;
- assign mem_tin_index_MPORT_1_mask = 1'h1;
- assign mem_tin_index_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_index_MPORT_2_data = io_in_bits_2_bits_tin_index;
- assign mem_tin_index_MPORT_2_addr = 2'h0;
- assign mem_tin_index_MPORT_2_mask = 1'h1;
- assign mem_tin_index_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_index_MPORT_3_data = io_in_bits_3_bits_tin_index;
- assign mem_tin_index_MPORT_3_addr = 2'h0;
- assign mem_tin_index_MPORT_3_mask = 1'h1;
- assign mem_tin_index_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_index_MPORT_4_data = io_in_bits_0_bits_tin_index;
- assign mem_tin_index_MPORT_4_addr = 2'h1;
- assign mem_tin_index_MPORT_4_mask = 1'h1;
- assign mem_tin_index_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_index_MPORT_5_data = io_in_bits_1_bits_tin_index;
- assign mem_tin_index_MPORT_5_addr = 2'h1;
- assign mem_tin_index_MPORT_5_mask = 1'h1;
- assign mem_tin_index_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_index_MPORT_6_data = io_in_bits_2_bits_tin_index;
- assign mem_tin_index_MPORT_6_addr = 2'h1;
- assign mem_tin_index_MPORT_6_mask = 1'h1;
- assign mem_tin_index_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_index_MPORT_7_data = io_in_bits_3_bits_tin_index;
- assign mem_tin_index_MPORT_7_addr = 2'h1;
- assign mem_tin_index_MPORT_7_mask = 1'h1;
- assign mem_tin_index_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_index_MPORT_8_data = io_in_bits_0_bits_tin_index;
- assign mem_tin_index_MPORT_8_addr = 2'h2;
- assign mem_tin_index_MPORT_8_mask = 1'h1;
- assign mem_tin_index_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_index_MPORT_9_data = io_in_bits_1_bits_tin_index;
- assign mem_tin_index_MPORT_9_addr = 2'h2;
- assign mem_tin_index_MPORT_9_mask = 1'h1;
- assign mem_tin_index_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_index_MPORT_10_data = io_in_bits_2_bits_tin_index;
- assign mem_tin_index_MPORT_10_addr = 2'h2;
- assign mem_tin_index_MPORT_10_mask = 1'h1;
- assign mem_tin_index_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_index_MPORT_11_data = io_in_bits_3_bits_tin_index;
- assign mem_tin_index_MPORT_11_addr = 2'h2;
- assign mem_tin_index_MPORT_11_mask = 1'h1;
- assign mem_tin_index_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_index_MPORT_12_data = io_in_bits_0_bits_tin_index;
- assign mem_tin_index_MPORT_12_addr = 2'h3;
- assign mem_tin_index_MPORT_12_mask = 1'h1;
- assign mem_tin_index_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_index_MPORT_13_data = io_in_bits_1_bits_tin_index;
- assign mem_tin_index_MPORT_13_addr = 2'h3;
- assign mem_tin_index_MPORT_13_mask = 1'h1;
- assign mem_tin_index_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_index_MPORT_14_data = io_in_bits_2_bits_tin_index;
- assign mem_tin_index_MPORT_14_addr = 2'h3;
- assign mem_tin_index_MPORT_14_mask = 1'h1;
- assign mem_tin_index_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_index_MPORT_15_data = io_in_bits_3_bits_tin_index;
- assign mem_tin_index_MPORT_15_addr = 2'h3;
- assign mem_tin_index_MPORT_15_mask = 1'h1;
- assign mem_tin_index_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_end_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_end_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_end_io_out_bits_MPORT_data = mem_tin_end[mem_tin_end_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_end_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_end_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_end_io_entry_0_bits_MPORT_data = mem_tin_end[mem_tin_end_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_end_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_end_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_end_io_entry_1_bits_MPORT_data = mem_tin_end[mem_tin_end_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_end_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_end_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_end_io_entry_2_bits_MPORT_data = mem_tin_end[mem_tin_end_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_end_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_end_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_end_io_entry_3_bits_MPORT_data = mem_tin_end[mem_tin_end_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_end_MPORT_data = io_in_bits_0_bits_tin_end;
- assign mem_tin_end_MPORT_addr = 2'h0;
- assign mem_tin_end_MPORT_mask = 1'h1;
- assign mem_tin_end_MPORT_en = ivalid & valid[0];
- assign mem_tin_end_MPORT_1_data = io_in_bits_1_bits_tin_end;
- assign mem_tin_end_MPORT_1_addr = 2'h0;
- assign mem_tin_end_MPORT_1_mask = 1'h1;
- assign mem_tin_end_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_end_MPORT_2_data = io_in_bits_2_bits_tin_end;
- assign mem_tin_end_MPORT_2_addr = 2'h0;
- assign mem_tin_end_MPORT_2_mask = 1'h1;
- assign mem_tin_end_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_end_MPORT_3_data = io_in_bits_3_bits_tin_end;
- assign mem_tin_end_MPORT_3_addr = 2'h0;
- assign mem_tin_end_MPORT_3_mask = 1'h1;
- assign mem_tin_end_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_end_MPORT_4_data = io_in_bits_0_bits_tin_end;
- assign mem_tin_end_MPORT_4_addr = 2'h1;
- assign mem_tin_end_MPORT_4_mask = 1'h1;
- assign mem_tin_end_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_end_MPORT_5_data = io_in_bits_1_bits_tin_end;
- assign mem_tin_end_MPORT_5_addr = 2'h1;
- assign mem_tin_end_MPORT_5_mask = 1'h1;
- assign mem_tin_end_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_end_MPORT_6_data = io_in_bits_2_bits_tin_end;
- assign mem_tin_end_MPORT_6_addr = 2'h1;
- assign mem_tin_end_MPORT_6_mask = 1'h1;
- assign mem_tin_end_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_end_MPORT_7_data = io_in_bits_3_bits_tin_end;
- assign mem_tin_end_MPORT_7_addr = 2'h1;
- assign mem_tin_end_MPORT_7_mask = 1'h1;
- assign mem_tin_end_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_end_MPORT_8_data = io_in_bits_0_bits_tin_end;
- assign mem_tin_end_MPORT_8_addr = 2'h2;
- assign mem_tin_end_MPORT_8_mask = 1'h1;
- assign mem_tin_end_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_end_MPORT_9_data = io_in_bits_1_bits_tin_end;
- assign mem_tin_end_MPORT_9_addr = 2'h2;
- assign mem_tin_end_MPORT_9_mask = 1'h1;
- assign mem_tin_end_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_end_MPORT_10_data = io_in_bits_2_bits_tin_end;
- assign mem_tin_end_MPORT_10_addr = 2'h2;
- assign mem_tin_end_MPORT_10_mask = 1'h1;
- assign mem_tin_end_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_end_MPORT_11_data = io_in_bits_3_bits_tin_end;
- assign mem_tin_end_MPORT_11_addr = 2'h2;
- assign mem_tin_end_MPORT_11_mask = 1'h1;
- assign mem_tin_end_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_end_MPORT_12_data = io_in_bits_0_bits_tin_end;
- assign mem_tin_end_MPORT_12_addr = 2'h3;
- assign mem_tin_end_MPORT_12_mask = 1'h1;
- assign mem_tin_end_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_end_MPORT_13_data = io_in_bits_1_bits_tin_end;
- assign mem_tin_end_MPORT_13_addr = 2'h3;
- assign mem_tin_end_MPORT_13_mask = 1'h1;
- assign mem_tin_end_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_end_MPORT_14_data = io_in_bits_2_bits_tin_end;
- assign mem_tin_end_MPORT_14_addr = 2'h3;
- assign mem_tin_end_MPORT_14_mask = 1'h1;
- assign mem_tin_end_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_end_MPORT_15_data = io_in_bits_3_bits_tin_end;
- assign mem_tin_end_MPORT_15_addr = 2'h3;
- assign mem_tin_end_MPORT_15_mask = 1'h1;
- assign mem_tin_end_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_abias_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_abias_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_abias_io_out_bits_MPORT_data = mem_tin_abias[mem_tin_abias_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_abias_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_abias_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_abias_io_entry_0_bits_MPORT_data = mem_tin_abias[mem_tin_abias_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_abias_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_abias_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_abias_io_entry_1_bits_MPORT_data = mem_tin_abias[mem_tin_abias_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_abias_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_abias_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_abias_io_entry_2_bits_MPORT_data = mem_tin_abias[mem_tin_abias_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_abias_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_abias_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_abias_io_entry_3_bits_MPORT_data = mem_tin_abias[mem_tin_abias_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_abias_MPORT_data = io_in_bits_0_bits_tin_abias;
- assign mem_tin_abias_MPORT_addr = 2'h0;
- assign mem_tin_abias_MPORT_mask = 1'h1;
- assign mem_tin_abias_MPORT_en = ivalid & valid[0];
- assign mem_tin_abias_MPORT_1_data = io_in_bits_1_bits_tin_abias;
- assign mem_tin_abias_MPORT_1_addr = 2'h0;
- assign mem_tin_abias_MPORT_1_mask = 1'h1;
- assign mem_tin_abias_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_abias_MPORT_2_data = io_in_bits_2_bits_tin_abias;
- assign mem_tin_abias_MPORT_2_addr = 2'h0;
- assign mem_tin_abias_MPORT_2_mask = 1'h1;
- assign mem_tin_abias_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_abias_MPORT_3_data = io_in_bits_3_bits_tin_abias;
- assign mem_tin_abias_MPORT_3_addr = 2'h0;
- assign mem_tin_abias_MPORT_3_mask = 1'h1;
- assign mem_tin_abias_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_abias_MPORT_4_data = io_in_bits_0_bits_tin_abias;
- assign mem_tin_abias_MPORT_4_addr = 2'h1;
- assign mem_tin_abias_MPORT_4_mask = 1'h1;
- assign mem_tin_abias_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_abias_MPORT_5_data = io_in_bits_1_bits_tin_abias;
- assign mem_tin_abias_MPORT_5_addr = 2'h1;
- assign mem_tin_abias_MPORT_5_mask = 1'h1;
- assign mem_tin_abias_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_abias_MPORT_6_data = io_in_bits_2_bits_tin_abias;
- assign mem_tin_abias_MPORT_6_addr = 2'h1;
- assign mem_tin_abias_MPORT_6_mask = 1'h1;
- assign mem_tin_abias_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_abias_MPORT_7_data = io_in_bits_3_bits_tin_abias;
- assign mem_tin_abias_MPORT_7_addr = 2'h1;
- assign mem_tin_abias_MPORT_7_mask = 1'h1;
- assign mem_tin_abias_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_abias_MPORT_8_data = io_in_bits_0_bits_tin_abias;
- assign mem_tin_abias_MPORT_8_addr = 2'h2;
- assign mem_tin_abias_MPORT_8_mask = 1'h1;
- assign mem_tin_abias_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_abias_MPORT_9_data = io_in_bits_1_bits_tin_abias;
- assign mem_tin_abias_MPORT_9_addr = 2'h2;
- assign mem_tin_abias_MPORT_9_mask = 1'h1;
- assign mem_tin_abias_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_abias_MPORT_10_data = io_in_bits_2_bits_tin_abias;
- assign mem_tin_abias_MPORT_10_addr = 2'h2;
- assign mem_tin_abias_MPORT_10_mask = 1'h1;
- assign mem_tin_abias_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_abias_MPORT_11_data = io_in_bits_3_bits_tin_abias;
- assign mem_tin_abias_MPORT_11_addr = 2'h2;
- assign mem_tin_abias_MPORT_11_mask = 1'h1;
- assign mem_tin_abias_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_abias_MPORT_12_data = io_in_bits_0_bits_tin_abias;
- assign mem_tin_abias_MPORT_12_addr = 2'h3;
- assign mem_tin_abias_MPORT_12_mask = 1'h1;
- assign mem_tin_abias_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_abias_MPORT_13_data = io_in_bits_1_bits_tin_abias;
- assign mem_tin_abias_MPORT_13_addr = 2'h3;
- assign mem_tin_abias_MPORT_13_mask = 1'h1;
- assign mem_tin_abias_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_abias_MPORT_14_data = io_in_bits_2_bits_tin_abias;
- assign mem_tin_abias_MPORT_14_addr = 2'h3;
- assign mem_tin_abias_MPORT_14_mask = 1'h1;
- assign mem_tin_abias_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_abias_MPORT_15_data = io_in_bits_3_bits_tin_abias;
- assign mem_tin_abias_MPORT_15_addr = 2'h3;
- assign mem_tin_abias_MPORT_15_mask = 1'h1;
- assign mem_tin_abias_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_bbias_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_bbias_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_bbias_io_out_bits_MPORT_data = mem_tin_bbias[mem_tin_bbias_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_bbias_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_bbias_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_bbias_io_entry_0_bits_MPORT_data = mem_tin_bbias[mem_tin_bbias_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_bbias_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_bbias_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_bbias_io_entry_1_bits_MPORT_data = mem_tin_bbias[mem_tin_bbias_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_bbias_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_bbias_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_bbias_io_entry_2_bits_MPORT_data = mem_tin_bbias[mem_tin_bbias_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_bbias_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_bbias_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_bbias_io_entry_3_bits_MPORT_data = mem_tin_bbias[mem_tin_bbias_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_bbias_MPORT_data = io_in_bits_0_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_addr = 2'h0;
- assign mem_tin_bbias_MPORT_mask = 1'h1;
- assign mem_tin_bbias_MPORT_en = ivalid & valid[0];
- assign mem_tin_bbias_MPORT_1_data = io_in_bits_1_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_1_addr = 2'h0;
- assign mem_tin_bbias_MPORT_1_mask = 1'h1;
- assign mem_tin_bbias_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_bbias_MPORT_2_data = io_in_bits_2_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_2_addr = 2'h0;
- assign mem_tin_bbias_MPORT_2_mask = 1'h1;
- assign mem_tin_bbias_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_bbias_MPORT_3_data = io_in_bits_3_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_3_addr = 2'h0;
- assign mem_tin_bbias_MPORT_3_mask = 1'h1;
- assign mem_tin_bbias_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_bbias_MPORT_4_data = io_in_bits_0_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_4_addr = 2'h1;
- assign mem_tin_bbias_MPORT_4_mask = 1'h1;
- assign mem_tin_bbias_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_bbias_MPORT_5_data = io_in_bits_1_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_5_addr = 2'h1;
- assign mem_tin_bbias_MPORT_5_mask = 1'h1;
- assign mem_tin_bbias_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_bbias_MPORT_6_data = io_in_bits_2_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_6_addr = 2'h1;
- assign mem_tin_bbias_MPORT_6_mask = 1'h1;
- assign mem_tin_bbias_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_bbias_MPORT_7_data = io_in_bits_3_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_7_addr = 2'h1;
- assign mem_tin_bbias_MPORT_7_mask = 1'h1;
- assign mem_tin_bbias_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_bbias_MPORT_8_data = io_in_bits_0_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_8_addr = 2'h2;
- assign mem_tin_bbias_MPORT_8_mask = 1'h1;
- assign mem_tin_bbias_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_bbias_MPORT_9_data = io_in_bits_1_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_9_addr = 2'h2;
- assign mem_tin_bbias_MPORT_9_mask = 1'h1;
- assign mem_tin_bbias_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_bbias_MPORT_10_data = io_in_bits_2_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_10_addr = 2'h2;
- assign mem_tin_bbias_MPORT_10_mask = 1'h1;
- assign mem_tin_bbias_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_bbias_MPORT_11_data = io_in_bits_3_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_11_addr = 2'h2;
- assign mem_tin_bbias_MPORT_11_mask = 1'h1;
- assign mem_tin_bbias_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_bbias_MPORT_12_data = io_in_bits_0_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_12_addr = 2'h3;
- assign mem_tin_bbias_MPORT_12_mask = 1'h1;
- assign mem_tin_bbias_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_bbias_MPORT_13_data = io_in_bits_1_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_13_addr = 2'h3;
- assign mem_tin_bbias_MPORT_13_mask = 1'h1;
- assign mem_tin_bbias_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_bbias_MPORT_14_data = io_in_bits_2_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_14_addr = 2'h3;
- assign mem_tin_bbias_MPORT_14_mask = 1'h1;
- assign mem_tin_bbias_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_bbias_MPORT_15_data = io_in_bits_3_bits_tin_bbias;
- assign mem_tin_bbias_MPORT_15_addr = 2'h3;
- assign mem_tin_bbias_MPORT_15_mask = 1'h1;
- assign mem_tin_bbias_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_asign_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_asign_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_asign_io_out_bits_MPORT_data = mem_tin_asign[mem_tin_asign_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_asign_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_asign_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_asign_io_entry_0_bits_MPORT_data = mem_tin_asign[mem_tin_asign_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_asign_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_asign_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_asign_io_entry_1_bits_MPORT_data = mem_tin_asign[mem_tin_asign_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_asign_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_asign_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_asign_io_entry_2_bits_MPORT_data = mem_tin_asign[mem_tin_asign_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_asign_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_asign_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_asign_io_entry_3_bits_MPORT_data = mem_tin_asign[mem_tin_asign_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_asign_MPORT_data = io_in_bits_0_bits_tin_asign;
- assign mem_tin_asign_MPORT_addr = 2'h0;
- assign mem_tin_asign_MPORT_mask = 1'h1;
- assign mem_tin_asign_MPORT_en = ivalid & valid[0];
- assign mem_tin_asign_MPORT_1_data = io_in_bits_1_bits_tin_asign;
- assign mem_tin_asign_MPORT_1_addr = 2'h0;
- assign mem_tin_asign_MPORT_1_mask = 1'h1;
- assign mem_tin_asign_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_asign_MPORT_2_data = io_in_bits_2_bits_tin_asign;
- assign mem_tin_asign_MPORT_2_addr = 2'h0;
- assign mem_tin_asign_MPORT_2_mask = 1'h1;
- assign mem_tin_asign_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_asign_MPORT_3_data = io_in_bits_3_bits_tin_asign;
- assign mem_tin_asign_MPORT_3_addr = 2'h0;
- assign mem_tin_asign_MPORT_3_mask = 1'h1;
- assign mem_tin_asign_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_asign_MPORT_4_data = io_in_bits_0_bits_tin_asign;
- assign mem_tin_asign_MPORT_4_addr = 2'h1;
- assign mem_tin_asign_MPORT_4_mask = 1'h1;
- assign mem_tin_asign_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_asign_MPORT_5_data = io_in_bits_1_bits_tin_asign;
- assign mem_tin_asign_MPORT_5_addr = 2'h1;
- assign mem_tin_asign_MPORT_5_mask = 1'h1;
- assign mem_tin_asign_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_asign_MPORT_6_data = io_in_bits_2_bits_tin_asign;
- assign mem_tin_asign_MPORT_6_addr = 2'h1;
- assign mem_tin_asign_MPORT_6_mask = 1'h1;
- assign mem_tin_asign_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_asign_MPORT_7_data = io_in_bits_3_bits_tin_asign;
- assign mem_tin_asign_MPORT_7_addr = 2'h1;
- assign mem_tin_asign_MPORT_7_mask = 1'h1;
- assign mem_tin_asign_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_asign_MPORT_8_data = io_in_bits_0_bits_tin_asign;
- assign mem_tin_asign_MPORT_8_addr = 2'h2;
- assign mem_tin_asign_MPORT_8_mask = 1'h1;
- assign mem_tin_asign_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_asign_MPORT_9_data = io_in_bits_1_bits_tin_asign;
- assign mem_tin_asign_MPORT_9_addr = 2'h2;
- assign mem_tin_asign_MPORT_9_mask = 1'h1;
- assign mem_tin_asign_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_asign_MPORT_10_data = io_in_bits_2_bits_tin_asign;
- assign mem_tin_asign_MPORT_10_addr = 2'h2;
- assign mem_tin_asign_MPORT_10_mask = 1'h1;
- assign mem_tin_asign_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_asign_MPORT_11_data = io_in_bits_3_bits_tin_asign;
- assign mem_tin_asign_MPORT_11_addr = 2'h2;
- assign mem_tin_asign_MPORT_11_mask = 1'h1;
- assign mem_tin_asign_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_asign_MPORT_12_data = io_in_bits_0_bits_tin_asign;
- assign mem_tin_asign_MPORT_12_addr = 2'h3;
- assign mem_tin_asign_MPORT_12_mask = 1'h1;
- assign mem_tin_asign_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_asign_MPORT_13_data = io_in_bits_1_bits_tin_asign;
- assign mem_tin_asign_MPORT_13_addr = 2'h3;
- assign mem_tin_asign_MPORT_13_mask = 1'h1;
- assign mem_tin_asign_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_asign_MPORT_14_data = io_in_bits_2_bits_tin_asign;
- assign mem_tin_asign_MPORT_14_addr = 2'h3;
- assign mem_tin_asign_MPORT_14_mask = 1'h1;
- assign mem_tin_asign_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_asign_MPORT_15_data = io_in_bits_3_bits_tin_asign;
- assign mem_tin_asign_MPORT_15_addr = 2'h3;
- assign mem_tin_asign_MPORT_15_mask = 1'h1;
- assign mem_tin_asign_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_tin_bsign_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_bsign_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_bsign_io_out_bits_MPORT_data = mem_tin_bsign[mem_tin_bsign_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_bsign_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_bsign_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_tin_bsign_io_entry_0_bits_MPORT_data = mem_tin_bsign[mem_tin_bsign_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_bsign_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_bsign_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_tin_bsign_io_entry_1_bits_MPORT_data = mem_tin_bsign[mem_tin_bsign_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_bsign_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_bsign_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_tin_bsign_io_entry_2_bits_MPORT_data = mem_tin_bsign[mem_tin_bsign_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_bsign_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_bsign_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_tin_bsign_io_entry_3_bits_MPORT_data = mem_tin_bsign[mem_tin_bsign_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_bsign_MPORT_data = io_in_bits_0_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_addr = 2'h0;
- assign mem_tin_bsign_MPORT_mask = 1'h1;
- assign mem_tin_bsign_MPORT_en = ivalid & valid[0];
- assign mem_tin_bsign_MPORT_1_data = io_in_bits_1_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_1_addr = 2'h0;
- assign mem_tin_bsign_MPORT_1_mask = 1'h1;
- assign mem_tin_bsign_MPORT_1_en = ivalid & _GEN_149;
- assign mem_tin_bsign_MPORT_2_data = io_in_bits_2_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_2_addr = 2'h0;
- assign mem_tin_bsign_MPORT_2_mask = 1'h1;
- assign mem_tin_bsign_MPORT_2_en = ivalid & _GEN_169;
- assign mem_tin_bsign_MPORT_3_data = io_in_bits_3_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_3_addr = 2'h0;
- assign mem_tin_bsign_MPORT_3_mask = 1'h1;
- assign mem_tin_bsign_MPORT_3_en = ivalid & _GEN_189;
- assign mem_tin_bsign_MPORT_4_data = io_in_bits_0_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_4_addr = 2'h1;
- assign mem_tin_bsign_MPORT_4_mask = 1'h1;
- assign mem_tin_bsign_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_bsign_MPORT_5_data = io_in_bits_1_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_5_addr = 2'h1;
- assign mem_tin_bsign_MPORT_5_mask = 1'h1;
- assign mem_tin_bsign_MPORT_5_en = ivalid & _GEN_422;
- assign mem_tin_bsign_MPORT_6_data = io_in_bits_2_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_6_addr = 2'h1;
- assign mem_tin_bsign_MPORT_6_mask = 1'h1;
- assign mem_tin_bsign_MPORT_6_en = ivalid & _GEN_441;
- assign mem_tin_bsign_MPORT_7_data = io_in_bits_3_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_7_addr = 2'h1;
- assign mem_tin_bsign_MPORT_7_mask = 1'h1;
- assign mem_tin_bsign_MPORT_7_en = ivalid & _GEN_460;
- assign mem_tin_bsign_MPORT_8_data = io_in_bits_0_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_8_addr = 2'h2;
- assign mem_tin_bsign_MPORT_8_mask = 1'h1;
- assign mem_tin_bsign_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_bsign_MPORT_9_data = io_in_bits_1_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_9_addr = 2'h2;
- assign mem_tin_bsign_MPORT_9_mask = 1'h1;
- assign mem_tin_bsign_MPORT_9_en = ivalid & _GEN_695;
- assign mem_tin_bsign_MPORT_10_data = io_in_bits_2_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_10_addr = 2'h2;
- assign mem_tin_bsign_MPORT_10_mask = 1'h1;
- assign mem_tin_bsign_MPORT_10_en = ivalid & _GEN_715;
- assign mem_tin_bsign_MPORT_11_data = io_in_bits_3_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_11_addr = 2'h2;
- assign mem_tin_bsign_MPORT_11_mask = 1'h1;
- assign mem_tin_bsign_MPORT_11_en = ivalid & _GEN_735;
- assign mem_tin_bsign_MPORT_12_data = io_in_bits_0_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_12_addr = 2'h3;
- assign mem_tin_bsign_MPORT_12_mask = 1'h1;
- assign mem_tin_bsign_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_bsign_MPORT_13_data = io_in_bits_1_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_13_addr = 2'h3;
- assign mem_tin_bsign_MPORT_13_mask = 1'h1;
- assign mem_tin_bsign_MPORT_13_en = ivalid & _GEN_975;
- assign mem_tin_bsign_MPORT_14_data = io_in_bits_2_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_14_addr = 2'h3;
- assign mem_tin_bsign_MPORT_14_mask = 1'h1;
- assign mem_tin_bsign_MPORT_14_en = ivalid & _GEN_995;
- assign mem_tin_bsign_MPORT_15_data = io_in_bits_3_bits_tin_bsign;
- assign mem_tin_bsign_MPORT_15_addr = 2'h3;
- assign mem_tin_bsign_MPORT_15_mask = 1'h1;
- assign mem_tin_bsign_MPORT_15_en = ivalid & _GEN_1015;
- assign mem_m_io_out_bits_MPORT_en = 1'h1;
- assign mem_m_io_out_bits_MPORT_addr = outpos;
- assign mem_m_io_out_bits_MPORT_data = mem_m[mem_m_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_0_bits_MPORT_addr = 2'h0;
- assign mem_m_io_entry_0_bits_MPORT_data = mem_m[mem_m_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_1_bits_MPORT_addr = 2'h1;
- assign mem_m_io_entry_1_bits_MPORT_data = mem_m[mem_m_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_2_bits_MPORT_addr = 2'h2;
- assign mem_m_io_entry_2_bits_MPORT_data = mem_m[mem_m_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_3_bits_MPORT_addr = 2'h3;
- assign mem_m_io_entry_3_bits_MPORT_data = mem_m[mem_m_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_MPORT_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_addr = 2'h0;
- assign mem_m_MPORT_mask = 1'h1;
- assign mem_m_MPORT_en = ivalid & valid[0];
- assign mem_m_MPORT_1_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_1_addr = 2'h0;
- assign mem_m_MPORT_1_mask = 1'h1;
- assign mem_m_MPORT_1_en = ivalid & _GEN_149;
- assign mem_m_MPORT_2_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_2_addr = 2'h0;
- assign mem_m_MPORT_2_mask = 1'h1;
- assign mem_m_MPORT_2_en = ivalid & _GEN_169;
- assign mem_m_MPORT_3_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_3_addr = 2'h0;
- assign mem_m_MPORT_3_mask = 1'h1;
- assign mem_m_MPORT_3_en = ivalid & _GEN_189;
- assign mem_m_MPORT_4_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_4_addr = 2'h1;
- assign mem_m_MPORT_4_mask = 1'h1;
- assign mem_m_MPORT_4_en = ivalid & valid_1[0];
- assign mem_m_MPORT_5_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_5_addr = 2'h1;
- assign mem_m_MPORT_5_mask = 1'h1;
- assign mem_m_MPORT_5_en = ivalid & _GEN_422;
- assign mem_m_MPORT_6_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_6_addr = 2'h1;
- assign mem_m_MPORT_6_mask = 1'h1;
- assign mem_m_MPORT_6_en = ivalid & _GEN_441;
- assign mem_m_MPORT_7_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_7_addr = 2'h1;
- assign mem_m_MPORT_7_mask = 1'h1;
- assign mem_m_MPORT_7_en = ivalid & _GEN_460;
- assign mem_m_MPORT_8_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_8_addr = 2'h2;
- assign mem_m_MPORT_8_mask = 1'h1;
- assign mem_m_MPORT_8_en = ivalid & valid_2[0];
- assign mem_m_MPORT_9_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_9_addr = 2'h2;
- assign mem_m_MPORT_9_mask = 1'h1;
- assign mem_m_MPORT_9_en = ivalid & _GEN_695;
- assign mem_m_MPORT_10_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_10_addr = 2'h2;
- assign mem_m_MPORT_10_mask = 1'h1;
- assign mem_m_MPORT_10_en = ivalid & _GEN_715;
- assign mem_m_MPORT_11_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_11_addr = 2'h2;
- assign mem_m_MPORT_11_mask = 1'h1;
- assign mem_m_MPORT_11_en = ivalid & _GEN_735;
- assign mem_m_MPORT_12_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_12_addr = 2'h3;
- assign mem_m_MPORT_12_mask = 1'h1;
- assign mem_m_MPORT_12_en = ivalid & valid_3[0];
- assign mem_m_MPORT_13_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_13_addr = 2'h3;
- assign mem_m_MPORT_13_mask = 1'h1;
- assign mem_m_MPORT_13_en = ivalid & _GEN_975;
- assign mem_m_MPORT_14_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_14_addr = 2'h3;
- assign mem_m_MPORT_14_mask = 1'h1;
- assign mem_m_MPORT_14_en = ivalid & _GEN_995;
- assign mem_m_MPORT_15_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_15_addr = 2'h3;
- assign mem_m_MPORT_15_mask = 1'h1;
- assign mem_m_MPORT_15_en = ivalid & _GEN_1015;
- assign io_in_ready = mcount <= _io_in_ready_T_1; // @[Fifo4e.scala 132:25]
- assign io_out_valid = mcount != 3'h0; // @[Fifo4e.scala 134:26]
- assign io_out_bits_tin_conv = mem_tin_conv_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_init = mem_tin_init_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_tran = mem_tin_tran_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_wclr = mem_tin_wclr_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_addr1 = mem_tin_addr1_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_addr2 = mem_tin_addr2_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_base2 = mem_tin_base2_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_mode = mem_tin_mode_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_mark2 = mem_tin_mark2_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_index = mem_tin_index_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_end = mem_tin_end_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_abias = mem_tin_abias_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_bbias = mem_tin_bbias_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_asign = mem_tin_asign_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_bsign = mem_tin_bsign_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_m = mem_m_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_entry_0_valid = active[0]; // @[Fifo4e.scala 140:32]
- assign io_entry_0_bits_tin_conv = mem_tin_conv_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_tin_init = mem_tin_init_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_tin_tran = mem_tin_tran_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_tin_addr1 = mem_tin_addr1_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_tin_base2 = mem_tin_base2_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_tin_mark2 = mem_tin_mark2_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_valid = active[1]; // @[Fifo4e.scala 140:32]
- assign io_entry_1_bits_tin_conv = mem_tin_conv_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_tin_init = mem_tin_init_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_tin_tran = mem_tin_tran_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_tin_addr1 = mem_tin_addr1_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_tin_base2 = mem_tin_base2_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_tin_mark2 = mem_tin_mark2_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_valid = active[2]; // @[Fifo4e.scala 140:32]
- assign io_entry_2_bits_tin_conv = mem_tin_conv_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_tin_init = mem_tin_init_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_tin_tran = mem_tin_tran_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_tin_addr1 = mem_tin_addr1_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_tin_base2 = mem_tin_base2_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_tin_mark2 = mem_tin_mark2_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_valid = active[3]; // @[Fifo4e.scala 140:32]
- assign io_entry_3_bits_tin_conv = mem_tin_conv_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_tin_init = mem_tin_init_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_tin_tran = mem_tin_tran_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_tin_addr1 = mem_tin_addr1_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_tin_base2 = mem_tin_base2_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_tin_mark2 = mem_tin_mark2_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- always @(posedge clock) begin
- if (mem_tin_conv_MPORT_en & mem_tin_conv_MPORT_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_addr] <= mem_tin_conv_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_1_en & mem_tin_conv_MPORT_1_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_1_addr] <= mem_tin_conv_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_2_en & mem_tin_conv_MPORT_2_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_2_addr] <= mem_tin_conv_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_3_en & mem_tin_conv_MPORT_3_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_3_addr] <= mem_tin_conv_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_4_en & mem_tin_conv_MPORT_4_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_4_addr] <= mem_tin_conv_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_5_en & mem_tin_conv_MPORT_5_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_5_addr] <= mem_tin_conv_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_6_en & mem_tin_conv_MPORT_6_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_6_addr] <= mem_tin_conv_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_7_en & mem_tin_conv_MPORT_7_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_7_addr] <= mem_tin_conv_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_8_en & mem_tin_conv_MPORT_8_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_8_addr] <= mem_tin_conv_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_9_en & mem_tin_conv_MPORT_9_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_9_addr] <= mem_tin_conv_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_10_en & mem_tin_conv_MPORT_10_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_10_addr] <= mem_tin_conv_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_11_en & mem_tin_conv_MPORT_11_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_11_addr] <= mem_tin_conv_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_12_en & mem_tin_conv_MPORT_12_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_12_addr] <= mem_tin_conv_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_13_en & mem_tin_conv_MPORT_13_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_13_addr] <= mem_tin_conv_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_14_en & mem_tin_conv_MPORT_14_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_14_addr] <= mem_tin_conv_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_conv_MPORT_15_en & mem_tin_conv_MPORT_15_mask) begin
- mem_tin_conv[mem_tin_conv_MPORT_15_addr] <= mem_tin_conv_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_en & mem_tin_init_MPORT_mask) begin
- mem_tin_init[mem_tin_init_MPORT_addr] <= mem_tin_init_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_1_en & mem_tin_init_MPORT_1_mask) begin
- mem_tin_init[mem_tin_init_MPORT_1_addr] <= mem_tin_init_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_2_en & mem_tin_init_MPORT_2_mask) begin
- mem_tin_init[mem_tin_init_MPORT_2_addr] <= mem_tin_init_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_3_en & mem_tin_init_MPORT_3_mask) begin
- mem_tin_init[mem_tin_init_MPORT_3_addr] <= mem_tin_init_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_4_en & mem_tin_init_MPORT_4_mask) begin
- mem_tin_init[mem_tin_init_MPORT_4_addr] <= mem_tin_init_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_5_en & mem_tin_init_MPORT_5_mask) begin
- mem_tin_init[mem_tin_init_MPORT_5_addr] <= mem_tin_init_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_6_en & mem_tin_init_MPORT_6_mask) begin
- mem_tin_init[mem_tin_init_MPORT_6_addr] <= mem_tin_init_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_7_en & mem_tin_init_MPORT_7_mask) begin
- mem_tin_init[mem_tin_init_MPORT_7_addr] <= mem_tin_init_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_8_en & mem_tin_init_MPORT_8_mask) begin
- mem_tin_init[mem_tin_init_MPORT_8_addr] <= mem_tin_init_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_9_en & mem_tin_init_MPORT_9_mask) begin
- mem_tin_init[mem_tin_init_MPORT_9_addr] <= mem_tin_init_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_10_en & mem_tin_init_MPORT_10_mask) begin
- mem_tin_init[mem_tin_init_MPORT_10_addr] <= mem_tin_init_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_11_en & mem_tin_init_MPORT_11_mask) begin
- mem_tin_init[mem_tin_init_MPORT_11_addr] <= mem_tin_init_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_12_en & mem_tin_init_MPORT_12_mask) begin
- mem_tin_init[mem_tin_init_MPORT_12_addr] <= mem_tin_init_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_13_en & mem_tin_init_MPORT_13_mask) begin
- mem_tin_init[mem_tin_init_MPORT_13_addr] <= mem_tin_init_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_14_en & mem_tin_init_MPORT_14_mask) begin
- mem_tin_init[mem_tin_init_MPORT_14_addr] <= mem_tin_init_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_init_MPORT_15_en & mem_tin_init_MPORT_15_mask) begin
- mem_tin_init[mem_tin_init_MPORT_15_addr] <= mem_tin_init_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_en & mem_tin_tran_MPORT_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_addr] <= mem_tin_tran_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_1_en & mem_tin_tran_MPORT_1_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_1_addr] <= mem_tin_tran_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_2_en & mem_tin_tran_MPORT_2_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_2_addr] <= mem_tin_tran_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_3_en & mem_tin_tran_MPORT_3_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_3_addr] <= mem_tin_tran_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_4_en & mem_tin_tran_MPORT_4_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_4_addr] <= mem_tin_tran_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_5_en & mem_tin_tran_MPORT_5_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_5_addr] <= mem_tin_tran_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_6_en & mem_tin_tran_MPORT_6_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_6_addr] <= mem_tin_tran_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_7_en & mem_tin_tran_MPORT_7_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_7_addr] <= mem_tin_tran_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_8_en & mem_tin_tran_MPORT_8_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_8_addr] <= mem_tin_tran_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_9_en & mem_tin_tran_MPORT_9_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_9_addr] <= mem_tin_tran_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_10_en & mem_tin_tran_MPORT_10_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_10_addr] <= mem_tin_tran_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_11_en & mem_tin_tran_MPORT_11_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_11_addr] <= mem_tin_tran_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_12_en & mem_tin_tran_MPORT_12_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_12_addr] <= mem_tin_tran_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_13_en & mem_tin_tran_MPORT_13_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_13_addr] <= mem_tin_tran_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_14_en & mem_tin_tran_MPORT_14_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_14_addr] <= mem_tin_tran_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_tran_MPORT_15_en & mem_tin_tran_MPORT_15_mask) begin
- mem_tin_tran[mem_tin_tran_MPORT_15_addr] <= mem_tin_tran_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_en & mem_tin_wclr_MPORT_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_addr] <= mem_tin_wclr_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_1_en & mem_tin_wclr_MPORT_1_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_1_addr] <= mem_tin_wclr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_2_en & mem_tin_wclr_MPORT_2_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_2_addr] <= mem_tin_wclr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_3_en & mem_tin_wclr_MPORT_3_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_3_addr] <= mem_tin_wclr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_4_en & mem_tin_wclr_MPORT_4_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_4_addr] <= mem_tin_wclr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_5_en & mem_tin_wclr_MPORT_5_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_5_addr] <= mem_tin_wclr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_6_en & mem_tin_wclr_MPORT_6_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_6_addr] <= mem_tin_wclr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_7_en & mem_tin_wclr_MPORT_7_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_7_addr] <= mem_tin_wclr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_8_en & mem_tin_wclr_MPORT_8_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_8_addr] <= mem_tin_wclr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_9_en & mem_tin_wclr_MPORT_9_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_9_addr] <= mem_tin_wclr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_10_en & mem_tin_wclr_MPORT_10_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_10_addr] <= mem_tin_wclr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_11_en & mem_tin_wclr_MPORT_11_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_11_addr] <= mem_tin_wclr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_12_en & mem_tin_wclr_MPORT_12_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_12_addr] <= mem_tin_wclr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_13_en & mem_tin_wclr_MPORT_13_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_13_addr] <= mem_tin_wclr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_14_en & mem_tin_wclr_MPORT_14_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_14_addr] <= mem_tin_wclr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_wclr_MPORT_15_en & mem_tin_wclr_MPORT_15_mask) begin
- mem_tin_wclr[mem_tin_wclr_MPORT_15_addr] <= mem_tin_wclr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_en & mem_tin_addr1_MPORT_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_addr] <= mem_tin_addr1_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_1_en & mem_tin_addr1_MPORT_1_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_1_addr] <= mem_tin_addr1_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_2_en & mem_tin_addr1_MPORT_2_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_2_addr] <= mem_tin_addr1_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_3_en & mem_tin_addr1_MPORT_3_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_3_addr] <= mem_tin_addr1_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_4_en & mem_tin_addr1_MPORT_4_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_4_addr] <= mem_tin_addr1_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_5_en & mem_tin_addr1_MPORT_5_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_5_addr] <= mem_tin_addr1_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_6_en & mem_tin_addr1_MPORT_6_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_6_addr] <= mem_tin_addr1_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_7_en & mem_tin_addr1_MPORT_7_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_7_addr] <= mem_tin_addr1_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_8_en & mem_tin_addr1_MPORT_8_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_8_addr] <= mem_tin_addr1_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_9_en & mem_tin_addr1_MPORT_9_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_9_addr] <= mem_tin_addr1_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_10_en & mem_tin_addr1_MPORT_10_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_10_addr] <= mem_tin_addr1_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_11_en & mem_tin_addr1_MPORT_11_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_11_addr] <= mem_tin_addr1_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_12_en & mem_tin_addr1_MPORT_12_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_12_addr] <= mem_tin_addr1_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_13_en & mem_tin_addr1_MPORT_13_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_13_addr] <= mem_tin_addr1_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_14_en & mem_tin_addr1_MPORT_14_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_14_addr] <= mem_tin_addr1_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr1_MPORT_15_en & mem_tin_addr1_MPORT_15_mask) begin
- mem_tin_addr1[mem_tin_addr1_MPORT_15_addr] <= mem_tin_addr1_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_en & mem_tin_addr2_MPORT_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_addr] <= mem_tin_addr2_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_1_en & mem_tin_addr2_MPORT_1_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_1_addr] <= mem_tin_addr2_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_2_en & mem_tin_addr2_MPORT_2_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_2_addr] <= mem_tin_addr2_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_3_en & mem_tin_addr2_MPORT_3_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_3_addr] <= mem_tin_addr2_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_4_en & mem_tin_addr2_MPORT_4_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_4_addr] <= mem_tin_addr2_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_5_en & mem_tin_addr2_MPORT_5_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_5_addr] <= mem_tin_addr2_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_6_en & mem_tin_addr2_MPORT_6_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_6_addr] <= mem_tin_addr2_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_7_en & mem_tin_addr2_MPORT_7_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_7_addr] <= mem_tin_addr2_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_8_en & mem_tin_addr2_MPORT_8_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_8_addr] <= mem_tin_addr2_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_9_en & mem_tin_addr2_MPORT_9_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_9_addr] <= mem_tin_addr2_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_10_en & mem_tin_addr2_MPORT_10_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_10_addr] <= mem_tin_addr2_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_11_en & mem_tin_addr2_MPORT_11_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_11_addr] <= mem_tin_addr2_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_12_en & mem_tin_addr2_MPORT_12_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_12_addr] <= mem_tin_addr2_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_13_en & mem_tin_addr2_MPORT_13_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_13_addr] <= mem_tin_addr2_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_14_en & mem_tin_addr2_MPORT_14_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_14_addr] <= mem_tin_addr2_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr2_MPORT_15_en & mem_tin_addr2_MPORT_15_mask) begin
- mem_tin_addr2[mem_tin_addr2_MPORT_15_addr] <= mem_tin_addr2_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_en & mem_tin_base2_MPORT_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_addr] <= mem_tin_base2_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_1_en & mem_tin_base2_MPORT_1_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_1_addr] <= mem_tin_base2_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_2_en & mem_tin_base2_MPORT_2_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_2_addr] <= mem_tin_base2_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_3_en & mem_tin_base2_MPORT_3_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_3_addr] <= mem_tin_base2_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_4_en & mem_tin_base2_MPORT_4_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_4_addr] <= mem_tin_base2_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_5_en & mem_tin_base2_MPORT_5_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_5_addr] <= mem_tin_base2_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_6_en & mem_tin_base2_MPORT_6_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_6_addr] <= mem_tin_base2_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_7_en & mem_tin_base2_MPORT_7_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_7_addr] <= mem_tin_base2_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_8_en & mem_tin_base2_MPORT_8_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_8_addr] <= mem_tin_base2_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_9_en & mem_tin_base2_MPORT_9_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_9_addr] <= mem_tin_base2_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_10_en & mem_tin_base2_MPORT_10_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_10_addr] <= mem_tin_base2_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_11_en & mem_tin_base2_MPORT_11_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_11_addr] <= mem_tin_base2_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_12_en & mem_tin_base2_MPORT_12_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_12_addr] <= mem_tin_base2_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_13_en & mem_tin_base2_MPORT_13_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_13_addr] <= mem_tin_base2_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_14_en & mem_tin_base2_MPORT_14_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_14_addr] <= mem_tin_base2_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_base2_MPORT_15_en & mem_tin_base2_MPORT_15_mask) begin
- mem_tin_base2[mem_tin_base2_MPORT_15_addr] <= mem_tin_base2_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_en & mem_tin_mode_MPORT_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_addr] <= mem_tin_mode_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_1_en & mem_tin_mode_MPORT_1_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_1_addr] <= mem_tin_mode_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_2_en & mem_tin_mode_MPORT_2_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_2_addr] <= mem_tin_mode_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_3_en & mem_tin_mode_MPORT_3_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_3_addr] <= mem_tin_mode_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_4_en & mem_tin_mode_MPORT_4_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_4_addr] <= mem_tin_mode_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_5_en & mem_tin_mode_MPORT_5_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_5_addr] <= mem_tin_mode_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_6_en & mem_tin_mode_MPORT_6_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_6_addr] <= mem_tin_mode_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_7_en & mem_tin_mode_MPORT_7_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_7_addr] <= mem_tin_mode_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_8_en & mem_tin_mode_MPORT_8_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_8_addr] <= mem_tin_mode_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_9_en & mem_tin_mode_MPORT_9_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_9_addr] <= mem_tin_mode_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_10_en & mem_tin_mode_MPORT_10_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_10_addr] <= mem_tin_mode_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_11_en & mem_tin_mode_MPORT_11_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_11_addr] <= mem_tin_mode_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_12_en & mem_tin_mode_MPORT_12_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_12_addr] <= mem_tin_mode_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_13_en & mem_tin_mode_MPORT_13_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_13_addr] <= mem_tin_mode_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_14_en & mem_tin_mode_MPORT_14_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_14_addr] <= mem_tin_mode_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mode_MPORT_15_en & mem_tin_mode_MPORT_15_mask) begin
- mem_tin_mode[mem_tin_mode_MPORT_15_addr] <= mem_tin_mode_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_en & mem_tin_mark2_MPORT_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_addr] <= mem_tin_mark2_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_1_en & mem_tin_mark2_MPORT_1_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_1_addr] <= mem_tin_mark2_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_2_en & mem_tin_mark2_MPORT_2_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_2_addr] <= mem_tin_mark2_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_3_en & mem_tin_mark2_MPORT_3_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_3_addr] <= mem_tin_mark2_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_4_en & mem_tin_mark2_MPORT_4_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_4_addr] <= mem_tin_mark2_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_5_en & mem_tin_mark2_MPORT_5_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_5_addr] <= mem_tin_mark2_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_6_en & mem_tin_mark2_MPORT_6_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_6_addr] <= mem_tin_mark2_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_7_en & mem_tin_mark2_MPORT_7_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_7_addr] <= mem_tin_mark2_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_8_en & mem_tin_mark2_MPORT_8_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_8_addr] <= mem_tin_mark2_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_9_en & mem_tin_mark2_MPORT_9_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_9_addr] <= mem_tin_mark2_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_10_en & mem_tin_mark2_MPORT_10_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_10_addr] <= mem_tin_mark2_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_11_en & mem_tin_mark2_MPORT_11_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_11_addr] <= mem_tin_mark2_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_12_en & mem_tin_mark2_MPORT_12_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_12_addr] <= mem_tin_mark2_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_13_en & mem_tin_mark2_MPORT_13_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_13_addr] <= mem_tin_mark2_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_14_en & mem_tin_mark2_MPORT_14_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_14_addr] <= mem_tin_mark2_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_mark2_MPORT_15_en & mem_tin_mark2_MPORT_15_mask) begin
- mem_tin_mark2[mem_tin_mark2_MPORT_15_addr] <= mem_tin_mark2_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_en & mem_tin_index_MPORT_mask) begin
- mem_tin_index[mem_tin_index_MPORT_addr] <= mem_tin_index_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_1_en & mem_tin_index_MPORT_1_mask) begin
- mem_tin_index[mem_tin_index_MPORT_1_addr] <= mem_tin_index_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_2_en & mem_tin_index_MPORT_2_mask) begin
- mem_tin_index[mem_tin_index_MPORT_2_addr] <= mem_tin_index_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_3_en & mem_tin_index_MPORT_3_mask) begin
- mem_tin_index[mem_tin_index_MPORT_3_addr] <= mem_tin_index_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_4_en & mem_tin_index_MPORT_4_mask) begin
- mem_tin_index[mem_tin_index_MPORT_4_addr] <= mem_tin_index_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_5_en & mem_tin_index_MPORT_5_mask) begin
- mem_tin_index[mem_tin_index_MPORT_5_addr] <= mem_tin_index_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_6_en & mem_tin_index_MPORT_6_mask) begin
- mem_tin_index[mem_tin_index_MPORT_6_addr] <= mem_tin_index_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_7_en & mem_tin_index_MPORT_7_mask) begin
- mem_tin_index[mem_tin_index_MPORT_7_addr] <= mem_tin_index_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_8_en & mem_tin_index_MPORT_8_mask) begin
- mem_tin_index[mem_tin_index_MPORT_8_addr] <= mem_tin_index_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_9_en & mem_tin_index_MPORT_9_mask) begin
- mem_tin_index[mem_tin_index_MPORT_9_addr] <= mem_tin_index_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_10_en & mem_tin_index_MPORT_10_mask) begin
- mem_tin_index[mem_tin_index_MPORT_10_addr] <= mem_tin_index_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_11_en & mem_tin_index_MPORT_11_mask) begin
- mem_tin_index[mem_tin_index_MPORT_11_addr] <= mem_tin_index_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_12_en & mem_tin_index_MPORT_12_mask) begin
- mem_tin_index[mem_tin_index_MPORT_12_addr] <= mem_tin_index_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_13_en & mem_tin_index_MPORT_13_mask) begin
- mem_tin_index[mem_tin_index_MPORT_13_addr] <= mem_tin_index_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_14_en & mem_tin_index_MPORT_14_mask) begin
- mem_tin_index[mem_tin_index_MPORT_14_addr] <= mem_tin_index_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_index_MPORT_15_en & mem_tin_index_MPORT_15_mask) begin
- mem_tin_index[mem_tin_index_MPORT_15_addr] <= mem_tin_index_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_en & mem_tin_end_MPORT_mask) begin
- mem_tin_end[mem_tin_end_MPORT_addr] <= mem_tin_end_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_1_en & mem_tin_end_MPORT_1_mask) begin
- mem_tin_end[mem_tin_end_MPORT_1_addr] <= mem_tin_end_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_2_en & mem_tin_end_MPORT_2_mask) begin
- mem_tin_end[mem_tin_end_MPORT_2_addr] <= mem_tin_end_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_3_en & mem_tin_end_MPORT_3_mask) begin
- mem_tin_end[mem_tin_end_MPORT_3_addr] <= mem_tin_end_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_4_en & mem_tin_end_MPORT_4_mask) begin
- mem_tin_end[mem_tin_end_MPORT_4_addr] <= mem_tin_end_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_5_en & mem_tin_end_MPORT_5_mask) begin
- mem_tin_end[mem_tin_end_MPORT_5_addr] <= mem_tin_end_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_6_en & mem_tin_end_MPORT_6_mask) begin
- mem_tin_end[mem_tin_end_MPORT_6_addr] <= mem_tin_end_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_7_en & mem_tin_end_MPORT_7_mask) begin
- mem_tin_end[mem_tin_end_MPORT_7_addr] <= mem_tin_end_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_8_en & mem_tin_end_MPORT_8_mask) begin
- mem_tin_end[mem_tin_end_MPORT_8_addr] <= mem_tin_end_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_9_en & mem_tin_end_MPORT_9_mask) begin
- mem_tin_end[mem_tin_end_MPORT_9_addr] <= mem_tin_end_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_10_en & mem_tin_end_MPORT_10_mask) begin
- mem_tin_end[mem_tin_end_MPORT_10_addr] <= mem_tin_end_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_11_en & mem_tin_end_MPORT_11_mask) begin
- mem_tin_end[mem_tin_end_MPORT_11_addr] <= mem_tin_end_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_12_en & mem_tin_end_MPORT_12_mask) begin
- mem_tin_end[mem_tin_end_MPORT_12_addr] <= mem_tin_end_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_13_en & mem_tin_end_MPORT_13_mask) begin
- mem_tin_end[mem_tin_end_MPORT_13_addr] <= mem_tin_end_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_14_en & mem_tin_end_MPORT_14_mask) begin
- mem_tin_end[mem_tin_end_MPORT_14_addr] <= mem_tin_end_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_end_MPORT_15_en & mem_tin_end_MPORT_15_mask) begin
- mem_tin_end[mem_tin_end_MPORT_15_addr] <= mem_tin_end_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_en & mem_tin_abias_MPORT_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_addr] <= mem_tin_abias_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_1_en & mem_tin_abias_MPORT_1_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_1_addr] <= mem_tin_abias_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_2_en & mem_tin_abias_MPORT_2_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_2_addr] <= mem_tin_abias_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_3_en & mem_tin_abias_MPORT_3_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_3_addr] <= mem_tin_abias_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_4_en & mem_tin_abias_MPORT_4_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_4_addr] <= mem_tin_abias_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_5_en & mem_tin_abias_MPORT_5_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_5_addr] <= mem_tin_abias_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_6_en & mem_tin_abias_MPORT_6_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_6_addr] <= mem_tin_abias_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_7_en & mem_tin_abias_MPORT_7_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_7_addr] <= mem_tin_abias_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_8_en & mem_tin_abias_MPORT_8_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_8_addr] <= mem_tin_abias_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_9_en & mem_tin_abias_MPORT_9_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_9_addr] <= mem_tin_abias_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_10_en & mem_tin_abias_MPORT_10_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_10_addr] <= mem_tin_abias_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_11_en & mem_tin_abias_MPORT_11_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_11_addr] <= mem_tin_abias_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_12_en & mem_tin_abias_MPORT_12_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_12_addr] <= mem_tin_abias_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_13_en & mem_tin_abias_MPORT_13_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_13_addr] <= mem_tin_abias_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_14_en & mem_tin_abias_MPORT_14_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_14_addr] <= mem_tin_abias_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_abias_MPORT_15_en & mem_tin_abias_MPORT_15_mask) begin
- mem_tin_abias[mem_tin_abias_MPORT_15_addr] <= mem_tin_abias_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_en & mem_tin_bbias_MPORT_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_addr] <= mem_tin_bbias_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_1_en & mem_tin_bbias_MPORT_1_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_1_addr] <= mem_tin_bbias_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_2_en & mem_tin_bbias_MPORT_2_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_2_addr] <= mem_tin_bbias_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_3_en & mem_tin_bbias_MPORT_3_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_3_addr] <= mem_tin_bbias_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_4_en & mem_tin_bbias_MPORT_4_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_4_addr] <= mem_tin_bbias_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_5_en & mem_tin_bbias_MPORT_5_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_5_addr] <= mem_tin_bbias_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_6_en & mem_tin_bbias_MPORT_6_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_6_addr] <= mem_tin_bbias_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_7_en & mem_tin_bbias_MPORT_7_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_7_addr] <= mem_tin_bbias_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_8_en & mem_tin_bbias_MPORT_8_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_8_addr] <= mem_tin_bbias_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_9_en & mem_tin_bbias_MPORT_9_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_9_addr] <= mem_tin_bbias_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_10_en & mem_tin_bbias_MPORT_10_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_10_addr] <= mem_tin_bbias_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_11_en & mem_tin_bbias_MPORT_11_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_11_addr] <= mem_tin_bbias_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_12_en & mem_tin_bbias_MPORT_12_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_12_addr] <= mem_tin_bbias_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_13_en & mem_tin_bbias_MPORT_13_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_13_addr] <= mem_tin_bbias_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_14_en & mem_tin_bbias_MPORT_14_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_14_addr] <= mem_tin_bbias_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bbias_MPORT_15_en & mem_tin_bbias_MPORT_15_mask) begin
- mem_tin_bbias[mem_tin_bbias_MPORT_15_addr] <= mem_tin_bbias_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_en & mem_tin_asign_MPORT_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_addr] <= mem_tin_asign_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_1_en & mem_tin_asign_MPORT_1_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_1_addr] <= mem_tin_asign_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_2_en & mem_tin_asign_MPORT_2_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_2_addr] <= mem_tin_asign_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_3_en & mem_tin_asign_MPORT_3_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_3_addr] <= mem_tin_asign_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_4_en & mem_tin_asign_MPORT_4_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_4_addr] <= mem_tin_asign_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_5_en & mem_tin_asign_MPORT_5_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_5_addr] <= mem_tin_asign_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_6_en & mem_tin_asign_MPORT_6_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_6_addr] <= mem_tin_asign_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_7_en & mem_tin_asign_MPORT_7_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_7_addr] <= mem_tin_asign_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_8_en & mem_tin_asign_MPORT_8_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_8_addr] <= mem_tin_asign_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_9_en & mem_tin_asign_MPORT_9_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_9_addr] <= mem_tin_asign_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_10_en & mem_tin_asign_MPORT_10_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_10_addr] <= mem_tin_asign_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_11_en & mem_tin_asign_MPORT_11_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_11_addr] <= mem_tin_asign_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_12_en & mem_tin_asign_MPORT_12_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_12_addr] <= mem_tin_asign_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_13_en & mem_tin_asign_MPORT_13_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_13_addr] <= mem_tin_asign_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_14_en & mem_tin_asign_MPORT_14_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_14_addr] <= mem_tin_asign_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_asign_MPORT_15_en & mem_tin_asign_MPORT_15_mask) begin
- mem_tin_asign[mem_tin_asign_MPORT_15_addr] <= mem_tin_asign_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_en & mem_tin_bsign_MPORT_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_addr] <= mem_tin_bsign_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_1_en & mem_tin_bsign_MPORT_1_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_1_addr] <= mem_tin_bsign_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_2_en & mem_tin_bsign_MPORT_2_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_2_addr] <= mem_tin_bsign_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_3_en & mem_tin_bsign_MPORT_3_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_3_addr] <= mem_tin_bsign_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_4_en & mem_tin_bsign_MPORT_4_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_4_addr] <= mem_tin_bsign_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_5_en & mem_tin_bsign_MPORT_5_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_5_addr] <= mem_tin_bsign_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_6_en & mem_tin_bsign_MPORT_6_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_6_addr] <= mem_tin_bsign_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_7_en & mem_tin_bsign_MPORT_7_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_7_addr] <= mem_tin_bsign_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_8_en & mem_tin_bsign_MPORT_8_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_8_addr] <= mem_tin_bsign_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_9_en & mem_tin_bsign_MPORT_9_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_9_addr] <= mem_tin_bsign_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_10_en & mem_tin_bsign_MPORT_10_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_10_addr] <= mem_tin_bsign_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_11_en & mem_tin_bsign_MPORT_11_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_11_addr] <= mem_tin_bsign_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_12_en & mem_tin_bsign_MPORT_12_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_12_addr] <= mem_tin_bsign_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_13_en & mem_tin_bsign_MPORT_13_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_13_addr] <= mem_tin_bsign_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_14_en & mem_tin_bsign_MPORT_14_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_14_addr] <= mem_tin_bsign_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_bsign_MPORT_15_en & mem_tin_bsign_MPORT_15_mask) begin
- mem_tin_bsign[mem_tin_bsign_MPORT_15_addr] <= mem_tin_bsign_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_en & mem_m_MPORT_mask) begin
- mem_m[mem_m_MPORT_addr] <= mem_m_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_1_en & mem_m_MPORT_1_mask) begin
- mem_m[mem_m_MPORT_1_addr] <= mem_m_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_2_en & mem_m_MPORT_2_mask) begin
- mem_m[mem_m_MPORT_2_addr] <= mem_m_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_3_en & mem_m_MPORT_3_mask) begin
- mem_m[mem_m_MPORT_3_addr] <= mem_m_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_4_en & mem_m_MPORT_4_mask) begin
- mem_m[mem_m_MPORT_4_addr] <= mem_m_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_5_en & mem_m_MPORT_5_mask) begin
- mem_m[mem_m_MPORT_5_addr] <= mem_m_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_6_en & mem_m_MPORT_6_mask) begin
- mem_m[mem_m_MPORT_6_addr] <= mem_m_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_7_en & mem_m_MPORT_7_mask) begin
- mem_m[mem_m_MPORT_7_addr] <= mem_m_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_8_en & mem_m_MPORT_8_mask) begin
- mem_m[mem_m_MPORT_8_addr] <= mem_m_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_9_en & mem_m_MPORT_9_mask) begin
- mem_m[mem_m_MPORT_9_addr] <= mem_m_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_10_en & mem_m_MPORT_10_mask) begin
- mem_m[mem_m_MPORT_10_addr] <= mem_m_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_11_en & mem_m_MPORT_11_mask) begin
- mem_m[mem_m_MPORT_11_addr] <= mem_m_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_12_en & mem_m_MPORT_12_mask) begin
- mem_m[mem_m_MPORT_12_addr] <= mem_m_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_13_en & mem_m_MPORT_13_mask) begin
- mem_m[mem_m_MPORT_13_addr] <= mem_m_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_14_en & mem_m_MPORT_14_mask) begin
- mem_m[mem_m_MPORT_14_addr] <= mem_m_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_15_en & mem_m_MPORT_15_mask) begin
- mem_m[mem_m_MPORT_15_addr] <= mem_m_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(mcount <= 3'h4)) begin
- $fatal; // @[Fifo4e.scala 137:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(mcount <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Fifo4e.scala:137 assert(mcount <= n.U)\n"); // @[Fifo4e.scala 137:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in0pos <= 2'h0; // @[Fifo4e.scala 68:12]
- end else if (ivalid) begin // @[Fifo4e.scala 45:23]
- in0pos <= in0pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in1pos <= 2'h1; // @[Fifo4e.scala 69:12]
- end else if (ivalid) begin // @[Fifo4e.scala 46:23]
- in1pos <= in1pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in2pos <= 2'h2; // @[Fifo4e.scala 70:12]
- end else if (ivalid) begin // @[Fifo4e.scala 47:23]
- in2pos <= in2pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in3pos <= 2'h3; // @[Fifo4e.scala 71:12]
- end else if (ivalid) begin // @[Fifo4e.scala 48:23]
- in3pos <= in3pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 74:17]
- outpos <= 2'h0; // @[Fifo4e.scala 75:12]
- end else if (dec) begin // @[Fifo4e.scala 49:23]
- outpos <= outpos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 81:27]
- mcount <= 3'h0; // @[Fifo4e.scala 83:12]
- end else if (ivalid | dec) begin // @[Fifo4e.scala 50:23]
- mcount <= nxtcount;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 126:69]
- active <= 4'h0; // @[Fifo4e.scala 127:12]
- end else if (_T) begin // @[Fifo4e.scala 118:23]
- active <= _active_T_2;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_MEM_INIT
- _RAND_0 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_conv[initvar] = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_init[initvar] = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_tran[initvar] = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_wclr[initvar] = _RAND_3[0:0];
- _RAND_4 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_addr1[initvar] = _RAND_4[5:0];
- _RAND_5 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_addr2[initvar] = _RAND_5[5:0];
- _RAND_6 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_base2[initvar] = _RAND_6[5:0];
- _RAND_7 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_mode[initvar] = _RAND_7[1:0];
- _RAND_8 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_mark2[initvar] = _RAND_8[7:0];
- _RAND_9 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_index[initvar] = _RAND_9[2:0];
- _RAND_10 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_end[initvar] = _RAND_10[2:0];
- _RAND_11 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_abias[initvar] = _RAND_11[8:0];
- _RAND_12 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_bbias[initvar] = _RAND_12[8:0];
- _RAND_13 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_asign[initvar] = _RAND_13[0:0];
- _RAND_14 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_tin_bsign[initvar] = _RAND_14[0:0];
- _RAND_15 = {1{`RANDOM}};
- for (initvar = 0; initvar < 4; initvar = initvar+1)
- mem_m[initvar] = _RAND_15[0:0];
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- _RAND_16 = {1{`RANDOM}};
- in0pos = _RAND_16[1:0];
- _RAND_17 = {1{`RANDOM}};
- in1pos = _RAND_17[1:0];
- _RAND_18 = {1{`RANDOM}};
- in2pos = _RAND_18[1:0];
- _RAND_19 = {1{`RANDOM}};
- in3pos = _RAND_19[1:0];
- _RAND_20 = {1{`RANDOM}};
- outpos = _RAND_20[1:0];
- _RAND_21 = {1{`RANDOM}};
- mcount = _RAND_21[2:0];
- _RAND_22 = {1{`RANDOM}};
- active = _RAND_22[3:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- in0pos = 2'h0;
- end
- if (reset) begin
- in1pos = 2'h1;
- end
- if (reset) begin
- in2pos = 2'h2;
- end
- if (reset) begin
- in3pos = 2'h3;
- end
- if (reset) begin
- outpos = 2'h0;
- end
- if (reset) begin
- mcount = 3'h0;
- end
- if (reset) begin
- active = 4'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VCmdq_2(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_op,
- input io_in_bits_0_bits_m,
- input [5:0] io_in_bits_0_bits_vs_addr,
- input [5:0] io_in_bits_0_bits_vu_addr,
- input [31:0] io_in_bits_0_bits_sv_data,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_op,
- input io_in_bits_1_bits_m,
- input [5:0] io_in_bits_1_bits_vs_addr,
- input [5:0] io_in_bits_1_bits_vu_addr,
- input [31:0] io_in_bits_1_bits_sv_data,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_op,
- input io_in_bits_2_bits_m,
- input [5:0] io_in_bits_2_bits_vs_addr,
- input [5:0] io_in_bits_2_bits_vu_addr,
- input [31:0] io_in_bits_2_bits_sv_data,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_op,
- input io_in_bits_3_bits_m,
- input [5:0] io_in_bits_3_bits_vs_addr,
- input [5:0] io_in_bits_3_bits_vu_addr,
- input [31:0] io_in_bits_3_bits_sv_data,
- input io_out_ready,
- output io_out_valid,
- output io_out_bits_conv,
- output io_out_bits_init,
- output io_out_bits_tran,
- output io_out_bits_wclr,
- output [5:0] io_out_bits_addr1,
- output [5:0] io_out_bits_addr2,
- output [5:0] io_out_bits_base2,
- output [1:0] io_out_bits_mode,
- output [7:0] io_out_bits_mark2,
- output [2:0] io_out_bits_index,
- output [8:0] io_out_bits_abias,
- output [8:0] io_out_bits_bbias,
- output io_out_bits_asign,
- output io_out_bits_bsign,
- output [63:0] io_active
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [63:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
-`endif // RANDOMIZE_REG_INIT
- wire f__clock; // @[Fifo4e.scala 24:11]
- wire f__reset; // @[Fifo4e.scala 24:11]
- wire f__io_in_ready; // @[Fifo4e.scala 24:11]
- wire f__io_in_valid; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_0_valid; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_0_bits_tin_conv; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_0_bits_tin_init; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_0_bits_tin_tran; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_0_bits_tin_wclr; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_in_bits_0_bits_tin_addr1; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_in_bits_0_bits_tin_addr2; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_in_bits_0_bits_tin_base2; // @[Fifo4e.scala 24:11]
- wire [1:0] f__io_in_bits_0_bits_tin_mode; // @[Fifo4e.scala 24:11]
- wire [7:0] f__io_in_bits_0_bits_tin_mark2; // @[Fifo4e.scala 24:11]
- wire [2:0] f__io_in_bits_0_bits_tin_index; // @[Fifo4e.scala 24:11]
- wire [2:0] f__io_in_bits_0_bits_tin_end; // @[Fifo4e.scala 24:11]
- wire [8:0] f__io_in_bits_0_bits_tin_abias; // @[Fifo4e.scala 24:11]
- wire [8:0] f__io_in_bits_0_bits_tin_bbias; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_0_bits_tin_asign; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_0_bits_tin_bsign; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_0_bits_m; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_1_valid; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_1_bits_tin_conv; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_1_bits_tin_init; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_1_bits_tin_tran; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_1_bits_tin_wclr; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_in_bits_1_bits_tin_addr1; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_in_bits_1_bits_tin_addr2; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_in_bits_1_bits_tin_base2; // @[Fifo4e.scala 24:11]
- wire [1:0] f__io_in_bits_1_bits_tin_mode; // @[Fifo4e.scala 24:11]
- wire [7:0] f__io_in_bits_1_bits_tin_mark2; // @[Fifo4e.scala 24:11]
- wire [2:0] f__io_in_bits_1_bits_tin_index; // @[Fifo4e.scala 24:11]
- wire [2:0] f__io_in_bits_1_bits_tin_end; // @[Fifo4e.scala 24:11]
- wire [8:0] f__io_in_bits_1_bits_tin_abias; // @[Fifo4e.scala 24:11]
- wire [8:0] f__io_in_bits_1_bits_tin_bbias; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_1_bits_tin_asign; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_1_bits_tin_bsign; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_1_bits_m; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_2_valid; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_2_bits_tin_conv; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_2_bits_tin_init; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_2_bits_tin_tran; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_2_bits_tin_wclr; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_in_bits_2_bits_tin_addr1; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_in_bits_2_bits_tin_addr2; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_in_bits_2_bits_tin_base2; // @[Fifo4e.scala 24:11]
- wire [1:0] f__io_in_bits_2_bits_tin_mode; // @[Fifo4e.scala 24:11]
- wire [7:0] f__io_in_bits_2_bits_tin_mark2; // @[Fifo4e.scala 24:11]
- wire [2:0] f__io_in_bits_2_bits_tin_index; // @[Fifo4e.scala 24:11]
- wire [2:0] f__io_in_bits_2_bits_tin_end; // @[Fifo4e.scala 24:11]
- wire [8:0] f__io_in_bits_2_bits_tin_abias; // @[Fifo4e.scala 24:11]
- wire [8:0] f__io_in_bits_2_bits_tin_bbias; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_2_bits_tin_asign; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_2_bits_tin_bsign; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_2_bits_m; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_3_valid; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_3_bits_tin_conv; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_3_bits_tin_init; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_3_bits_tin_tran; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_3_bits_tin_wclr; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_in_bits_3_bits_tin_addr1; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_in_bits_3_bits_tin_addr2; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_in_bits_3_bits_tin_base2; // @[Fifo4e.scala 24:11]
- wire [1:0] f__io_in_bits_3_bits_tin_mode; // @[Fifo4e.scala 24:11]
- wire [7:0] f__io_in_bits_3_bits_tin_mark2; // @[Fifo4e.scala 24:11]
- wire [2:0] f__io_in_bits_3_bits_tin_index; // @[Fifo4e.scala 24:11]
- wire [2:0] f__io_in_bits_3_bits_tin_end; // @[Fifo4e.scala 24:11]
- wire [8:0] f__io_in_bits_3_bits_tin_abias; // @[Fifo4e.scala 24:11]
- wire [8:0] f__io_in_bits_3_bits_tin_bbias; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_3_bits_tin_asign; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_3_bits_tin_bsign; // @[Fifo4e.scala 24:11]
- wire f__io_in_bits_3_bits_m; // @[Fifo4e.scala 24:11]
- wire f__io_out_ready; // @[Fifo4e.scala 24:11]
- wire f__io_out_valid; // @[Fifo4e.scala 24:11]
- wire f__io_out_bits_tin_conv; // @[Fifo4e.scala 24:11]
- wire f__io_out_bits_tin_init; // @[Fifo4e.scala 24:11]
- wire f__io_out_bits_tin_tran; // @[Fifo4e.scala 24:11]
- wire f__io_out_bits_tin_wclr; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_out_bits_tin_addr1; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_out_bits_tin_addr2; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_out_bits_tin_base2; // @[Fifo4e.scala 24:11]
- wire [1:0] f__io_out_bits_tin_mode; // @[Fifo4e.scala 24:11]
- wire [7:0] f__io_out_bits_tin_mark2; // @[Fifo4e.scala 24:11]
- wire [2:0] f__io_out_bits_tin_index; // @[Fifo4e.scala 24:11]
- wire [2:0] f__io_out_bits_tin_end; // @[Fifo4e.scala 24:11]
- wire [8:0] f__io_out_bits_tin_abias; // @[Fifo4e.scala 24:11]
- wire [8:0] f__io_out_bits_tin_bbias; // @[Fifo4e.scala 24:11]
- wire f__io_out_bits_tin_asign; // @[Fifo4e.scala 24:11]
- wire f__io_out_bits_tin_bsign; // @[Fifo4e.scala 24:11]
- wire f__io_out_bits_m; // @[Fifo4e.scala 24:11]
- wire f__io_entry_0_valid; // @[Fifo4e.scala 24:11]
- wire f__io_entry_0_bits_tin_conv; // @[Fifo4e.scala 24:11]
- wire f__io_entry_0_bits_tin_init; // @[Fifo4e.scala 24:11]
- wire f__io_entry_0_bits_tin_tran; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_entry_0_bits_tin_addr1; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_entry_0_bits_tin_base2; // @[Fifo4e.scala 24:11]
- wire [7:0] f__io_entry_0_bits_tin_mark2; // @[Fifo4e.scala 24:11]
- wire f__io_entry_1_valid; // @[Fifo4e.scala 24:11]
- wire f__io_entry_1_bits_tin_conv; // @[Fifo4e.scala 24:11]
- wire f__io_entry_1_bits_tin_init; // @[Fifo4e.scala 24:11]
- wire f__io_entry_1_bits_tin_tran; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_entry_1_bits_tin_addr1; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_entry_1_bits_tin_base2; // @[Fifo4e.scala 24:11]
- wire [7:0] f__io_entry_1_bits_tin_mark2; // @[Fifo4e.scala 24:11]
- wire f__io_entry_2_valid; // @[Fifo4e.scala 24:11]
- wire f__io_entry_2_bits_tin_conv; // @[Fifo4e.scala 24:11]
- wire f__io_entry_2_bits_tin_init; // @[Fifo4e.scala 24:11]
- wire f__io_entry_2_bits_tin_tran; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_entry_2_bits_tin_addr1; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_entry_2_bits_tin_base2; // @[Fifo4e.scala 24:11]
- wire [7:0] f__io_entry_2_bits_tin_mark2; // @[Fifo4e.scala 24:11]
- wire f__io_entry_3_valid; // @[Fifo4e.scala 24:11]
- wire f__io_entry_3_bits_tin_conv; // @[Fifo4e.scala 24:11]
- wire f__io_entry_3_bits_tin_init; // @[Fifo4e.scala 24:11]
- wire f__io_entry_3_bits_tin_tran; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_entry_3_bits_tin_addr1; // @[Fifo4e.scala 24:11]
- wire [5:0] f__io_entry_3_bits_tin_base2; // @[Fifo4e.scala 24:11]
- wire [7:0] f__io_entry_3_bits_tin_mark2; // @[Fifo4e.scala 24:11]
- reg [63:0] active; // @[VCmdq.scala 49:23]
- reg valid; // @[VCmdq.scala 51:22]
- reg value_tin_conv; // @[VCmdq.scala 53:18]
- reg value_tin_init; // @[VCmdq.scala 53:18]
- reg value_tin_tran; // @[VCmdq.scala 53:18]
- reg value_tin_wclr; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_addr1; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_addr2; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_base2; // @[VCmdq.scala 53:18]
- reg [1:0] value_tin_mode; // @[VCmdq.scala 53:18]
- reg [7:0] value_tin_mark2; // @[VCmdq.scala 53:18]
- reg [2:0] value_tin_index; // @[VCmdq.scala 53:18]
- reg [2:0] value_tin_end; // @[VCmdq.scala 53:18]
- reg [8:0] value_tin_abias; // @[VCmdq.scala 53:18]
- reg [8:0] value_tin_bbias; // @[VCmdq.scala 53:18]
- reg value_tin_asign; // @[VCmdq.scala 53:18]
- reg value_tin_bsign; // @[VCmdq.scala 53:18]
- reg value_m; // @[VCmdq.scala 53:18]
- reg [4:0] step; // @[VCmdq.scala 58:21]
- wire last = value_tin_index == value_tin_end | value_tin_wclr; // @[VConvCtrl.scala 125:36]
- wire [2:0] tin_index = value_tin_index + 3'h1; // @[VConvCtrl.scala 128:27]
- wire [5:0] tin_addr2 = value_tin_addr2 + 6'h1; // @[VConvCtrl.scala 129:27]
- wire f_io_in_bits_0_bits_tin_acset = io_in_bits_0_bits_op == 7'h1f; // @[VConvCtrl.scala 69:24]
- wire f_io_in_bits_0_bits_tin_actr = io_in_bits_0_bits_op == 7'h20; // @[VConvCtrl.scala 70:24]
- wire _f_io_in_bits_0_bits_tin_start_T = f_io_in_bits_0_bits_tin_acset | f_io_in_bits_0_bits_tin_actr; // @[VConvCtrl.scala 78:27]
- wire [4:0] f_io_in_bits_0_bits_tin_start = f_io_in_bits_0_bits_tin_acset | f_io_in_bits_0_bits_tin_actr ? 5'h0 :
- io_in_bits_0_bits_sv_data[6:2]; // @[VConvCtrl.scala 78:20]
- wire [4:0] f_io_in_bits_0_bits_tin_stop = _f_io_in_bits_0_bits_tin_start_T ? 5'h7 : io_in_bits_0_bits_sv_data[11:7]; // @[VConvCtrl.scala 79:20]
- wire [2:0] _f_io_in_bits_0_bits_tin_mark2_T_3 = f_io_in_bits_0_bits_tin_stop[2:0] - f_io_in_bits_0_bits_tin_start[2:0]
- ; // @[VConvCtrl.scala 84:44]
- wire [2:0] _f_io_in_bits_0_bits_tin_mark2_T_5 = 3'h7 - _f_io_in_bits_0_bits_tin_mark2_T_3; // @[VConvCtrl.scala 84:31]
- wire f_io_in_bits_1_bits_tin_acset = io_in_bits_1_bits_op == 7'h1f; // @[VConvCtrl.scala 69:24]
- wire f_io_in_bits_1_bits_tin_actr = io_in_bits_1_bits_op == 7'h20; // @[VConvCtrl.scala 70:24]
- wire _f_io_in_bits_1_bits_tin_start_T = f_io_in_bits_1_bits_tin_acset | f_io_in_bits_1_bits_tin_actr; // @[VConvCtrl.scala 78:27]
- wire [4:0] f_io_in_bits_1_bits_tin_start = f_io_in_bits_1_bits_tin_acset | f_io_in_bits_1_bits_tin_actr ? 5'h0 :
- io_in_bits_1_bits_sv_data[6:2]; // @[VConvCtrl.scala 78:20]
- wire [4:0] f_io_in_bits_1_bits_tin_stop = _f_io_in_bits_1_bits_tin_start_T ? 5'h7 : io_in_bits_1_bits_sv_data[11:7]; // @[VConvCtrl.scala 79:20]
- wire [2:0] _f_io_in_bits_1_bits_tin_mark2_T_3 = f_io_in_bits_1_bits_tin_stop[2:0] - f_io_in_bits_1_bits_tin_start[2:0]
- ; // @[VConvCtrl.scala 84:44]
- wire [2:0] _f_io_in_bits_1_bits_tin_mark2_T_5 = 3'h7 - _f_io_in_bits_1_bits_tin_mark2_T_3; // @[VConvCtrl.scala 84:31]
- wire f_io_in_bits_2_bits_tin_acset = io_in_bits_2_bits_op == 7'h1f; // @[VConvCtrl.scala 69:24]
- wire f_io_in_bits_2_bits_tin_actr = io_in_bits_2_bits_op == 7'h20; // @[VConvCtrl.scala 70:24]
- wire _f_io_in_bits_2_bits_tin_start_T = f_io_in_bits_2_bits_tin_acset | f_io_in_bits_2_bits_tin_actr; // @[VConvCtrl.scala 78:27]
- wire [4:0] f_io_in_bits_2_bits_tin_start = f_io_in_bits_2_bits_tin_acset | f_io_in_bits_2_bits_tin_actr ? 5'h0 :
- io_in_bits_2_bits_sv_data[6:2]; // @[VConvCtrl.scala 78:20]
- wire [4:0] f_io_in_bits_2_bits_tin_stop = _f_io_in_bits_2_bits_tin_start_T ? 5'h7 : io_in_bits_2_bits_sv_data[11:7]; // @[VConvCtrl.scala 79:20]
- wire [2:0] _f_io_in_bits_2_bits_tin_mark2_T_3 = f_io_in_bits_2_bits_tin_stop[2:0] - f_io_in_bits_2_bits_tin_start[2:0]
- ; // @[VConvCtrl.scala 84:44]
- wire [2:0] _f_io_in_bits_2_bits_tin_mark2_T_5 = 3'h7 - _f_io_in_bits_2_bits_tin_mark2_T_3; // @[VConvCtrl.scala 84:31]
- wire f_io_in_bits_3_bits_tin_acset = io_in_bits_3_bits_op == 7'h1f; // @[VConvCtrl.scala 69:24]
- wire f_io_in_bits_3_bits_tin_actr = io_in_bits_3_bits_op == 7'h20; // @[VConvCtrl.scala 70:24]
- wire _f_io_in_bits_3_bits_tin_start_T = f_io_in_bits_3_bits_tin_acset | f_io_in_bits_3_bits_tin_actr; // @[VConvCtrl.scala 78:27]
- wire [4:0] f_io_in_bits_3_bits_tin_start = f_io_in_bits_3_bits_tin_acset | f_io_in_bits_3_bits_tin_actr ? 5'h0 :
- io_in_bits_3_bits_sv_data[6:2]; // @[VConvCtrl.scala 78:20]
- wire [4:0] f_io_in_bits_3_bits_tin_stop = _f_io_in_bits_3_bits_tin_start_T ? 5'h7 : io_in_bits_3_bits_sv_data[11:7]; // @[VConvCtrl.scala 79:20]
- wire [2:0] _f_io_in_bits_3_bits_tin_mark2_T_3 = f_io_in_bits_3_bits_tin_stop[2:0] - f_io_in_bits_3_bits_tin_start[2:0]
- ; // @[VConvCtrl.scala 84:44]
- wire [2:0] _f_io_in_bits_3_bits_tin_mark2_T_5 = 3'h7 - _f_io_in_bits_3_bits_tin_mark2_T_3; // @[VConvCtrl.scala 84:31]
- wire _T_14 = io_out_valid & io_out_ready; // @[VCmdq.scala 81:29]
- wire _T_15 = ~last; // @[VCmdq.scala 82:11]
- wire [4:0] _step_T_1 = step + 5'h1; // @[VCmdq.scala 86:20]
- wire _GEN_1 = ~last & value_tin_bsign; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_2 = ~last & value_tin_asign; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_12 = ~last & value_tin_wclr; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_13 = ~last & value_tin_tran; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_14 = ~last & value_tin_init; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_15 = ~last & value_tin_conv; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_16 = ~last & value_m; // @[VCmdq.scala 82:18 85:15 91:15]
- wire _GEN_18 = io_out_valid & io_out_ready ? _T_15 : valid; // @[VCmdq.scala 51:22 81:46]
- wire _fvalid_T = f__io_in_valid & f__io_in_ready; // @[VCmdq.scala 119:38]
- wire [3:0] _fvalid_T_1 = {f__io_in_bits_3_valid,f__io_in_bits_2_valid,f__io_in_bits_1_valid,f__io_in_bits_0_valid}; // @[Cat.scala 31:58]
- wire [3:0] fvalid = _fvalid_T ? _fvalid_T_1 : 4'h0; // @[Library.scala 22:8]
- wire [5:0] _active_active1_T_1 = {f__io_in_bits_0_bits_tin_addr1[5:3],3'h0}; // @[Cat.scala 31:58]
- wire [70:0] _active_active1_T_2 = 71'hff << _active_active1_T_1; // @[VConvCtrl.scala 146:25]
- wire [14:0] _active_active2_T = {{7'd0}, f__io_in_bits_0_bits_tin_mark2}; // @[VConvCtrl.scala 147:41]
- wire [14:0] _active_active2_T_1 = _active_active2_T & _active_active2_T; // @[VConvCtrl.scala 147:29]
- wire [77:0] _GEN_0 = {{63'd0}, _active_active2_T_1}; // @[VConvCtrl.scala 147:56]
- wire [77:0] _active_active2_T_2 = _GEN_0 << f__io_in_bits_0_bits_tin_base2; // @[VConvCtrl.scala 147:56]
- wire [63:0] active_active2 = _active_active2_T_2[63:0]; // @[VConvCtrl.scala 147:68]
- wire _active_active_T = f__io_in_bits_0_bits_tin_conv | f__io_in_bits_0_bits_tin_tran; // @[VConvCtrl.scala 156:32]
- wire [63:0] active_active1 = _active_active1_T_2[63:0]; // @[VConvCtrl.scala 135:23 146:15]
- wire [63:0] _active_active_T_1 = _active_active_T ? active_active1 : 64'h0; // @[Library.scala 22:8]
- wire _active_active_T_2 = f__io_in_bits_0_bits_tin_conv | f__io_in_bits_0_bits_tin_init; // @[VConvCtrl.scala 157:32]
- wire [63:0] _active_active_T_3 = _active_active_T_2 ? active_active2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active = _active_active_T_1 | _active_active_T_3; // @[VConvCtrl.scala 156:53]
- wire [63:0] _active_T_1 = fvalid[0] ? active_active : 64'h0; // @[Library.scala 22:8]
- wire [5:0] _active_active1_T_4 = {f__io_in_bits_1_bits_tin_addr1[5:3],3'h0}; // @[Cat.scala 31:58]
- wire [70:0] _active_active1_T_5 = 71'hff << _active_active1_T_4; // @[VConvCtrl.scala 146:25]
- wire [14:0] _active_active2_T_4 = {{7'd0}, f__io_in_bits_1_bits_tin_mark2}; // @[VConvCtrl.scala 147:41]
- wire [14:0] _active_active2_T_5 = _active_active2_T_4 & _active_active2_T_4; // @[VConvCtrl.scala 147:29]
- wire [77:0] _GEN_36 = {{63'd0}, _active_active2_T_5}; // @[VConvCtrl.scala 147:56]
- wire [77:0] _active_active2_T_6 = _GEN_36 << f__io_in_bits_1_bits_tin_base2; // @[VConvCtrl.scala 147:56]
- wire [63:0] active_active2_1 = _active_active2_T_6[63:0]; // @[VConvCtrl.scala 147:68]
- wire _active_active_T_4 = f__io_in_bits_1_bits_tin_conv | f__io_in_bits_1_bits_tin_tran; // @[VConvCtrl.scala 156:32]
- wire [63:0] active_active1_1 = _active_active1_T_5[63:0]; // @[VConvCtrl.scala 135:23 146:15]
- wire [63:0] _active_active_T_5 = _active_active_T_4 ? active_active1_1 : 64'h0; // @[Library.scala 22:8]
- wire _active_active_T_6 = f__io_in_bits_1_bits_tin_conv | f__io_in_bits_1_bits_tin_init; // @[VConvCtrl.scala 157:32]
- wire [63:0] _active_active_T_7 = _active_active_T_6 ? active_active2_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_1 = _active_active_T_5 | _active_active_T_7; // @[VConvCtrl.scala 156:53]
- wire [63:0] _active_T_3 = fvalid[1] ? active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_4 = _active_T_1 | _active_T_3; // @[VCmdq.scala 124:90]
- wire [5:0] _active_active1_T_7 = {f__io_in_bits_2_bits_tin_addr1[5:3],3'h0}; // @[Cat.scala 31:58]
- wire [70:0] _active_active1_T_8 = 71'hff << _active_active1_T_7; // @[VConvCtrl.scala 146:25]
- wire [14:0] _active_active2_T_8 = {{7'd0}, f__io_in_bits_2_bits_tin_mark2}; // @[VConvCtrl.scala 147:41]
- wire [14:0] _active_active2_T_9 = _active_active2_T_8 & _active_active2_T_8; // @[VConvCtrl.scala 147:29]
- wire [77:0] _GEN_53 = {{63'd0}, _active_active2_T_9}; // @[VConvCtrl.scala 147:56]
- wire [77:0] _active_active2_T_10 = _GEN_53 << f__io_in_bits_2_bits_tin_base2; // @[VConvCtrl.scala 147:56]
- wire [63:0] active_active2_2 = _active_active2_T_10[63:0]; // @[VConvCtrl.scala 147:68]
- wire _active_active_T_8 = f__io_in_bits_2_bits_tin_conv | f__io_in_bits_2_bits_tin_tran; // @[VConvCtrl.scala 156:32]
- wire [63:0] active_active1_2 = _active_active1_T_8[63:0]; // @[VConvCtrl.scala 135:23 146:15]
- wire [63:0] _active_active_T_9 = _active_active_T_8 ? active_active1_2 : 64'h0; // @[Library.scala 22:8]
- wire _active_active_T_10 = f__io_in_bits_2_bits_tin_conv | f__io_in_bits_2_bits_tin_init; // @[VConvCtrl.scala 157:32]
- wire [63:0] _active_active_T_11 = _active_active_T_10 ? active_active2_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_2 = _active_active_T_9 | _active_active_T_11; // @[VConvCtrl.scala 156:53]
- wire [63:0] _active_T_6 = fvalid[2] ? active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_7 = _active_T_4 | _active_T_6; // @[VCmdq.scala 125:90]
- wire [5:0] _active_active1_T_10 = {f__io_in_bits_3_bits_tin_addr1[5:3],3'h0}; // @[Cat.scala 31:58]
- wire [70:0] _active_active1_T_11 = 71'hff << _active_active1_T_10; // @[VConvCtrl.scala 146:25]
- wire [14:0] _active_active2_T_12 = {{7'd0}, f__io_in_bits_3_bits_tin_mark2}; // @[VConvCtrl.scala 147:41]
- wire [14:0] _active_active2_T_13 = _active_active2_T_12 & _active_active2_T_12; // @[VConvCtrl.scala 147:29]
- wire [77:0] _GEN_54 = {{63'd0}, _active_active2_T_13}; // @[VConvCtrl.scala 147:56]
- wire [77:0] _active_active2_T_14 = _GEN_54 << f__io_in_bits_3_bits_tin_base2; // @[VConvCtrl.scala 147:56]
- wire [63:0] active_active2_3 = _active_active2_T_14[63:0]; // @[VConvCtrl.scala 147:68]
- wire _active_active_T_12 = f__io_in_bits_3_bits_tin_conv | f__io_in_bits_3_bits_tin_tran; // @[VConvCtrl.scala 156:32]
- wire [63:0] active_active1_3 = _active_active1_T_11[63:0]; // @[VConvCtrl.scala 135:23 146:15]
- wire [63:0] _active_active_T_13 = _active_active_T_12 ? active_active1_3 : 64'h0; // @[Library.scala 22:8]
- wire _active_active_T_14 = f__io_in_bits_3_bits_tin_conv | f__io_in_bits_3_bits_tin_init; // @[VConvCtrl.scala 157:32]
- wire [63:0] _active_active_T_15 = _active_active_T_14 ? active_active2_3 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_3 = _active_active_T_13 | _active_active_T_15; // @[VConvCtrl.scala 156:53]
- wire [63:0] _active_T_9 = fvalid[3] ? active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_10 = _active_T_7 | _active_T_9; // @[VCmdq.scala 126:90]
- wire [5:0] _active_active_active1_T_1 = {f__io_entry_0_bits_tin_addr1[5:3],3'h0}; // @[Cat.scala 31:58]
- wire [70:0] _active_active_active1_T_2 = 71'hff << _active_active_active1_T_1; // @[VConvCtrl.scala 146:25]
- wire [14:0] _active_active_active2_T = {{7'd0}, f__io_entry_0_bits_tin_mark2}; // @[VConvCtrl.scala 147:41]
- wire [14:0] _active_active_active2_T_1 = _active_active_active2_T & _active_active_active2_T; // @[VConvCtrl.scala 147:29]
- wire [77:0] _GEN_55 = {{63'd0}, _active_active_active2_T_1}; // @[VConvCtrl.scala 147:56]
- wire [77:0] _active_active_active2_T_2 = _GEN_55 << f__io_entry_0_bits_tin_base2; // @[VConvCtrl.scala 147:56]
- wire [63:0] active_active_active2 = _active_active_active2_T_2[63:0]; // @[VConvCtrl.scala 147:68]
- wire _active_active_active_T = f__io_entry_0_bits_tin_conv | f__io_entry_0_bits_tin_tran; // @[VConvCtrl.scala 156:32]
- wire [63:0] active_active_active1 = _active_active_active1_T_2[63:0]; // @[VConvCtrl.scala 135:23 146:15]
- wire [63:0] _active_active_active_T_1 = _active_active_active_T ? active_active_active1 : 64'h0; // @[Library.scala 22:8]
- wire _active_active_active_T_2 = f__io_entry_0_bits_tin_conv | f__io_entry_0_bits_tin_init; // @[VConvCtrl.scala 157:32]
- wire [63:0] _active_active_active_T_3 = _active_active_active_T_2 ? active_active_active2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active = _active_active_active_T_1 | _active_active_active_T_3; // @[VConvCtrl.scala 156:53]
- wire [63:0] active_active_4 = f__io_entry_0_valid ? active_active_active : 64'h0; // @[Library.scala 22:8]
- wire [5:0] _active_active_active1_T_4 = {f__io_entry_1_bits_tin_addr1[5:3],3'h0}; // @[Cat.scala 31:58]
- wire [70:0] _active_active_active1_T_5 = 71'hff << _active_active_active1_T_4; // @[VConvCtrl.scala 146:25]
- wire [14:0] _active_active_active2_T_4 = {{7'd0}, f__io_entry_1_bits_tin_mark2}; // @[VConvCtrl.scala 147:41]
- wire [14:0] _active_active_active2_T_5 = _active_active_active2_T_4 & _active_active_active2_T_4; // @[VConvCtrl.scala 147:29]
- wire [77:0] _GEN_56 = {{63'd0}, _active_active_active2_T_5}; // @[VConvCtrl.scala 147:56]
- wire [77:0] _active_active_active2_T_6 = _GEN_56 << f__io_entry_1_bits_tin_base2; // @[VConvCtrl.scala 147:56]
- wire [63:0] active_active_active2_1 = _active_active_active2_T_6[63:0]; // @[VConvCtrl.scala 147:68]
- wire _active_active_active_T_4 = f__io_entry_1_bits_tin_conv | f__io_entry_1_bits_tin_tran; // @[VConvCtrl.scala 156:32]
- wire [63:0] active_active_active1_1 = _active_active_active1_T_5[63:0]; // @[VConvCtrl.scala 135:23 146:15]
- wire [63:0] _active_active_active_T_5 = _active_active_active_T_4 ? active_active_active1_1 : 64'h0; // @[Library.scala 22:8]
- wire _active_active_active_T_6 = f__io_entry_1_bits_tin_conv | f__io_entry_1_bits_tin_init; // @[VConvCtrl.scala 157:32]
- wire [63:0] _active_active_active_T_7 = _active_active_active_T_6 ? active_active_active2_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_1 = _active_active_active_T_5 | _active_active_active_T_7; // @[VConvCtrl.scala 156:53]
- wire [63:0] active_active_5 = f__io_entry_1_valid ? active_active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_12 = active_active_4 | active_active_5; // @[VCmdq.scala 107:24]
- wire [5:0] _active_active_active1_T_7 = {f__io_entry_2_bits_tin_addr1[5:3],3'h0}; // @[Cat.scala 31:58]
- wire [70:0] _active_active_active1_T_8 = 71'hff << _active_active_active1_T_7; // @[VConvCtrl.scala 146:25]
- wire [14:0] _active_active_active2_T_8 = {{7'd0}, f__io_entry_2_bits_tin_mark2}; // @[VConvCtrl.scala 147:41]
- wire [14:0] _active_active_active2_T_9 = _active_active_active2_T_8 & _active_active_active2_T_8; // @[VConvCtrl.scala 147:29]
- wire [77:0] _GEN_57 = {{63'd0}, _active_active_active2_T_9}; // @[VConvCtrl.scala 147:56]
- wire [77:0] _active_active_active2_T_10 = _GEN_57 << f__io_entry_2_bits_tin_base2; // @[VConvCtrl.scala 147:56]
- wire [63:0] active_active_active2_2 = _active_active_active2_T_10[63:0]; // @[VConvCtrl.scala 147:68]
- wire _active_active_active_T_8 = f__io_entry_2_bits_tin_conv | f__io_entry_2_bits_tin_tran; // @[VConvCtrl.scala 156:32]
- wire [63:0] active_active_active1_2 = _active_active_active1_T_8[63:0]; // @[VConvCtrl.scala 135:23 146:15]
- wire [63:0] _active_active_active_T_9 = _active_active_active_T_8 ? active_active_active1_2 : 64'h0; // @[Library.scala 22:8]
- wire _active_active_active_T_10 = f__io_entry_2_bits_tin_conv | f__io_entry_2_bits_tin_init; // @[VConvCtrl.scala 157:32]
- wire [63:0] _active_active_active_T_11 = _active_active_active_T_10 ? active_active_active2_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_2 = _active_active_active_T_9 | _active_active_active_T_11; // @[VConvCtrl.scala 156:53]
- wire [63:0] active_active_6 = f__io_entry_2_valid ? active_active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_13 = _active_T_12 | active_active_6; // @[VCmdq.scala 107:24]
- wire [5:0] _active_active_active1_T_10 = {f__io_entry_3_bits_tin_addr1[5:3],3'h0}; // @[Cat.scala 31:58]
- wire [70:0] _active_active_active1_T_11 = 71'hff << _active_active_active1_T_10; // @[VConvCtrl.scala 146:25]
- wire [14:0] _active_active_active2_T_12 = {{7'd0}, f__io_entry_3_bits_tin_mark2}; // @[VConvCtrl.scala 147:41]
- wire [14:0] _active_active_active2_T_13 = _active_active_active2_T_12 & _active_active_active2_T_12; // @[VConvCtrl.scala 147:29]
- wire [77:0] _GEN_58 = {{63'd0}, _active_active_active2_T_13}; // @[VConvCtrl.scala 147:56]
- wire [77:0] _active_active_active2_T_14 = _GEN_58 << f__io_entry_3_bits_tin_base2; // @[VConvCtrl.scala 147:56]
- wire [63:0] active_active_active2_3 = _active_active_active2_T_14[63:0]; // @[VConvCtrl.scala 147:68]
- wire _active_active_active_T_12 = f__io_entry_3_bits_tin_conv | f__io_entry_3_bits_tin_tran; // @[VConvCtrl.scala 156:32]
- wire [63:0] active_active_active1_3 = _active_active_active1_T_11[63:0]; // @[VConvCtrl.scala 135:23 146:15]
- wire [63:0] _active_active_active_T_13 = _active_active_active_T_12 ? active_active_active1_3 : 64'h0; // @[Library.scala 22:8]
- wire _active_active_active_T_14 = f__io_entry_3_bits_tin_conv | f__io_entry_3_bits_tin_init; // @[VConvCtrl.scala 157:32]
- wire [63:0] _active_active_active_T_15 = _active_active_active_T_14 ? active_active_active2_3 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_active_3 = _active_active_active_T_13 | _active_active_active_T_15; // @[VConvCtrl.scala 156:53]
- wire [63:0] active_active_7 = f__io_entry_3_valid ? active_active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_14 = _active_T_13 | active_active_7; // @[VCmdq.scala 107:24]
- wire [5:0] _active_active0_T = {{1'd0}, step}; // @[VCmdq.scala 110:48]
- wire [5:0] _active_active0_active1_T_1 = {value_tin_addr1[5:3],3'h0}; // @[Cat.scala 31:58]
- wire [70:0] _active_active0_active1_T_2 = 71'hff << _active_active0_active1_T_1; // @[VConvCtrl.scala 146:25]
- wire [14:0] _GEN_59 = {{7'd0}, value_tin_mark2}; // @[VConvCtrl.scala 147:41]
- wire [14:0] _active_active0_active2_T_1 = _GEN_59 << _active_active0_T[2:0]; // @[VConvCtrl.scala 147:41]
- wire [14:0] _GEN_79 = {{7'd0}, value_tin_mark2}; // @[VConvCtrl.scala 147:29]
- wire [14:0] _active_active0_active2_T_2 = _GEN_79 & _active_active0_active2_T_1; // @[VConvCtrl.scala 147:29]
- wire [77:0] _GEN_60 = {{63'd0}, _active_active0_active2_T_2}; // @[VConvCtrl.scala 147:56]
- wire [77:0] _active_active0_active2_T_3 = _GEN_60 << value_tin_base2; // @[VConvCtrl.scala 147:56]
- wire [63:0] active_active0_active2 = _active_active0_active2_T_3[63:0]; // @[VConvCtrl.scala 147:68]
- wire _active_active0_active_T = value_tin_conv | value_tin_tran; // @[VConvCtrl.scala 156:32]
- wire [63:0] active_active0_active1 = _active_active0_active1_T_2[63:0]; // @[VConvCtrl.scala 135:23 146:15]
- wire [63:0] _active_active0_active_T_1 = _active_active0_active_T ? active_active0_active1 : 64'h0; // @[Library.scala 22:8]
- wire _active_active0_active_T_2 = value_tin_conv | value_tin_init; // @[VConvCtrl.scala 157:32]
- wire [63:0] _active_active0_active_T_3 = _active_active0_active_T_2 ? active_active0_active2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active0 = _active_active0_active_T_1 | _active_active0_active_T_3; // @[VConvCtrl.scala 156:53]
- wire [14:0] _GEN_61 = {{7'd0}, value_tin_mark2}; // @[VConvCtrl.scala 147:41]
- wire [14:0] _active_active1_active2_T_1 = _GEN_61 << _step_T_1[2:0]; // @[VConvCtrl.scala 147:41]
- wire [14:0] _active_active1_active2_T_2 = _GEN_79 & _active_active1_active2_T_1; // @[VConvCtrl.scala 147:29]
- wire [77:0] _GEN_62 = {{63'd0}, _active_active1_active2_T_2}; // @[VConvCtrl.scala 147:56]
- wire [77:0] _active_active1_active2_T_3 = _GEN_62 << value_tin_base2; // @[VConvCtrl.scala 147:56]
- wire [63:0] active_active1_active2 = _active_active1_active2_T_3[63:0]; // @[VConvCtrl.scala 147:68]
- wire [63:0] _active_active1_active_T_3 = _active_active0_active_T_2 ? active_active1_active2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active1_4 = _active_active0_active_T_1 | _active_active1_active_T_3; // @[VConvCtrl.scala 156:53]
- wire _active_active_T_16 = ~io_out_ready; // @[VCmdq.scala 112:36]
- wire _active_active_T_19 = valid & (~io_out_ready | _T_15); // @[VCmdq.scala 112:32]
- wire [63:0] _active_active_T_21 = _active_active_T_16 ? active_active0 : active_active1_4; // @[VCmdq.scala 113:29]
- wire [63:0] active_active_8 = _active_active_T_19 ? _active_active_T_21 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_15 = _active_T_14 | active_active_8; // @[VCmdq.scala 114:12]
- wire [63:0] _active_T_16 = _active_T_10 | _active_T_15; // @[VCmdq.scala 127:90]
- wire _GEN_81 = valid & ~reset; // @[VConvCtrl.scala 112:13]
- Fifo4e_2 f_ ( // @[Fifo4e.scala 24:11]
- .clock(f__clock),
- .reset(f__reset),
- .io_in_ready(f__io_in_ready),
- .io_in_valid(f__io_in_valid),
- .io_in_bits_0_valid(f__io_in_bits_0_valid),
- .io_in_bits_0_bits_tin_conv(f__io_in_bits_0_bits_tin_conv),
- .io_in_bits_0_bits_tin_init(f__io_in_bits_0_bits_tin_init),
- .io_in_bits_0_bits_tin_tran(f__io_in_bits_0_bits_tin_tran),
- .io_in_bits_0_bits_tin_wclr(f__io_in_bits_0_bits_tin_wclr),
- .io_in_bits_0_bits_tin_addr1(f__io_in_bits_0_bits_tin_addr1),
- .io_in_bits_0_bits_tin_addr2(f__io_in_bits_0_bits_tin_addr2),
- .io_in_bits_0_bits_tin_base2(f__io_in_bits_0_bits_tin_base2),
- .io_in_bits_0_bits_tin_mode(f__io_in_bits_0_bits_tin_mode),
- .io_in_bits_0_bits_tin_mark2(f__io_in_bits_0_bits_tin_mark2),
- .io_in_bits_0_bits_tin_index(f__io_in_bits_0_bits_tin_index),
- .io_in_bits_0_bits_tin_end(f__io_in_bits_0_bits_tin_end),
- .io_in_bits_0_bits_tin_abias(f__io_in_bits_0_bits_tin_abias),
- .io_in_bits_0_bits_tin_bbias(f__io_in_bits_0_bits_tin_bbias),
- .io_in_bits_0_bits_tin_asign(f__io_in_bits_0_bits_tin_asign),
- .io_in_bits_0_bits_tin_bsign(f__io_in_bits_0_bits_tin_bsign),
- .io_in_bits_0_bits_m(f__io_in_bits_0_bits_m),
- .io_in_bits_1_valid(f__io_in_bits_1_valid),
- .io_in_bits_1_bits_tin_conv(f__io_in_bits_1_bits_tin_conv),
- .io_in_bits_1_bits_tin_init(f__io_in_bits_1_bits_tin_init),
- .io_in_bits_1_bits_tin_tran(f__io_in_bits_1_bits_tin_tran),
- .io_in_bits_1_bits_tin_wclr(f__io_in_bits_1_bits_tin_wclr),
- .io_in_bits_1_bits_tin_addr1(f__io_in_bits_1_bits_tin_addr1),
- .io_in_bits_1_bits_tin_addr2(f__io_in_bits_1_bits_tin_addr2),
- .io_in_bits_1_bits_tin_base2(f__io_in_bits_1_bits_tin_base2),
- .io_in_bits_1_bits_tin_mode(f__io_in_bits_1_bits_tin_mode),
- .io_in_bits_1_bits_tin_mark2(f__io_in_bits_1_bits_tin_mark2),
- .io_in_bits_1_bits_tin_index(f__io_in_bits_1_bits_tin_index),
- .io_in_bits_1_bits_tin_end(f__io_in_bits_1_bits_tin_end),
- .io_in_bits_1_bits_tin_abias(f__io_in_bits_1_bits_tin_abias),
- .io_in_bits_1_bits_tin_bbias(f__io_in_bits_1_bits_tin_bbias),
- .io_in_bits_1_bits_tin_asign(f__io_in_bits_1_bits_tin_asign),
- .io_in_bits_1_bits_tin_bsign(f__io_in_bits_1_bits_tin_bsign),
- .io_in_bits_1_bits_m(f__io_in_bits_1_bits_m),
- .io_in_bits_2_valid(f__io_in_bits_2_valid),
- .io_in_bits_2_bits_tin_conv(f__io_in_bits_2_bits_tin_conv),
- .io_in_bits_2_bits_tin_init(f__io_in_bits_2_bits_tin_init),
- .io_in_bits_2_bits_tin_tran(f__io_in_bits_2_bits_tin_tran),
- .io_in_bits_2_bits_tin_wclr(f__io_in_bits_2_bits_tin_wclr),
- .io_in_bits_2_bits_tin_addr1(f__io_in_bits_2_bits_tin_addr1),
- .io_in_bits_2_bits_tin_addr2(f__io_in_bits_2_bits_tin_addr2),
- .io_in_bits_2_bits_tin_base2(f__io_in_bits_2_bits_tin_base2),
- .io_in_bits_2_bits_tin_mode(f__io_in_bits_2_bits_tin_mode),
- .io_in_bits_2_bits_tin_mark2(f__io_in_bits_2_bits_tin_mark2),
- .io_in_bits_2_bits_tin_index(f__io_in_bits_2_bits_tin_index),
- .io_in_bits_2_bits_tin_end(f__io_in_bits_2_bits_tin_end),
- .io_in_bits_2_bits_tin_abias(f__io_in_bits_2_bits_tin_abias),
- .io_in_bits_2_bits_tin_bbias(f__io_in_bits_2_bits_tin_bbias),
- .io_in_bits_2_bits_tin_asign(f__io_in_bits_2_bits_tin_asign),
- .io_in_bits_2_bits_tin_bsign(f__io_in_bits_2_bits_tin_bsign),
- .io_in_bits_2_bits_m(f__io_in_bits_2_bits_m),
- .io_in_bits_3_valid(f__io_in_bits_3_valid),
- .io_in_bits_3_bits_tin_conv(f__io_in_bits_3_bits_tin_conv),
- .io_in_bits_3_bits_tin_init(f__io_in_bits_3_bits_tin_init),
- .io_in_bits_3_bits_tin_tran(f__io_in_bits_3_bits_tin_tran),
- .io_in_bits_3_bits_tin_wclr(f__io_in_bits_3_bits_tin_wclr),
- .io_in_bits_3_bits_tin_addr1(f__io_in_bits_3_bits_tin_addr1),
- .io_in_bits_3_bits_tin_addr2(f__io_in_bits_3_bits_tin_addr2),
- .io_in_bits_3_bits_tin_base2(f__io_in_bits_3_bits_tin_base2),
- .io_in_bits_3_bits_tin_mode(f__io_in_bits_3_bits_tin_mode),
- .io_in_bits_3_bits_tin_mark2(f__io_in_bits_3_bits_tin_mark2),
- .io_in_bits_3_bits_tin_index(f__io_in_bits_3_bits_tin_index),
- .io_in_bits_3_bits_tin_end(f__io_in_bits_3_bits_tin_end),
- .io_in_bits_3_bits_tin_abias(f__io_in_bits_3_bits_tin_abias),
- .io_in_bits_3_bits_tin_bbias(f__io_in_bits_3_bits_tin_bbias),
- .io_in_bits_3_bits_tin_asign(f__io_in_bits_3_bits_tin_asign),
- .io_in_bits_3_bits_tin_bsign(f__io_in_bits_3_bits_tin_bsign),
- .io_in_bits_3_bits_m(f__io_in_bits_3_bits_m),
- .io_out_ready(f__io_out_ready),
- .io_out_valid(f__io_out_valid),
- .io_out_bits_tin_conv(f__io_out_bits_tin_conv),
- .io_out_bits_tin_init(f__io_out_bits_tin_init),
- .io_out_bits_tin_tran(f__io_out_bits_tin_tran),
- .io_out_bits_tin_wclr(f__io_out_bits_tin_wclr),
- .io_out_bits_tin_addr1(f__io_out_bits_tin_addr1),
- .io_out_bits_tin_addr2(f__io_out_bits_tin_addr2),
- .io_out_bits_tin_base2(f__io_out_bits_tin_base2),
- .io_out_bits_tin_mode(f__io_out_bits_tin_mode),
- .io_out_bits_tin_mark2(f__io_out_bits_tin_mark2),
- .io_out_bits_tin_index(f__io_out_bits_tin_index),
- .io_out_bits_tin_end(f__io_out_bits_tin_end),
- .io_out_bits_tin_abias(f__io_out_bits_tin_abias),
- .io_out_bits_tin_bbias(f__io_out_bits_tin_bbias),
- .io_out_bits_tin_asign(f__io_out_bits_tin_asign),
- .io_out_bits_tin_bsign(f__io_out_bits_tin_bsign),
- .io_out_bits_m(f__io_out_bits_m),
- .io_entry_0_valid(f__io_entry_0_valid),
- .io_entry_0_bits_tin_conv(f__io_entry_0_bits_tin_conv),
- .io_entry_0_bits_tin_init(f__io_entry_0_bits_tin_init),
- .io_entry_0_bits_tin_tran(f__io_entry_0_bits_tin_tran),
- .io_entry_0_bits_tin_addr1(f__io_entry_0_bits_tin_addr1),
- .io_entry_0_bits_tin_base2(f__io_entry_0_bits_tin_base2),
- .io_entry_0_bits_tin_mark2(f__io_entry_0_bits_tin_mark2),
- .io_entry_1_valid(f__io_entry_1_valid),
- .io_entry_1_bits_tin_conv(f__io_entry_1_bits_tin_conv),
- .io_entry_1_bits_tin_init(f__io_entry_1_bits_tin_init),
- .io_entry_1_bits_tin_tran(f__io_entry_1_bits_tin_tran),
- .io_entry_1_bits_tin_addr1(f__io_entry_1_bits_tin_addr1),
- .io_entry_1_bits_tin_base2(f__io_entry_1_bits_tin_base2),
- .io_entry_1_bits_tin_mark2(f__io_entry_1_bits_tin_mark2),
- .io_entry_2_valid(f__io_entry_2_valid),
- .io_entry_2_bits_tin_conv(f__io_entry_2_bits_tin_conv),
- .io_entry_2_bits_tin_init(f__io_entry_2_bits_tin_init),
- .io_entry_2_bits_tin_tran(f__io_entry_2_bits_tin_tran),
- .io_entry_2_bits_tin_addr1(f__io_entry_2_bits_tin_addr1),
- .io_entry_2_bits_tin_base2(f__io_entry_2_bits_tin_base2),
- .io_entry_2_bits_tin_mark2(f__io_entry_2_bits_tin_mark2),
- .io_entry_3_valid(f__io_entry_3_valid),
- .io_entry_3_bits_tin_conv(f__io_entry_3_bits_tin_conv),
- .io_entry_3_bits_tin_init(f__io_entry_3_bits_tin_init),
- .io_entry_3_bits_tin_tran(f__io_entry_3_bits_tin_tran),
- .io_entry_3_bits_tin_addr1(f__io_entry_3_bits_tin_addr1),
- .io_entry_3_bits_tin_base2(f__io_entry_3_bits_tin_base2),
- .io_entry_3_bits_tin_mark2(f__io_entry_3_bits_tin_mark2)
- );
- assign io_in_ready = f__io_in_ready; // @[VCmdq.scala 65:15]
- assign io_out_valid = valid; // @[VCmdq.scala 133:16]
- assign io_out_bits_conv = value_tin_conv; // @[VCmdq.scala 134:15]
- assign io_out_bits_init = value_tin_init; // @[VCmdq.scala 134:15]
- assign io_out_bits_tran = value_tin_tran; // @[VCmdq.scala 134:15]
- assign io_out_bits_wclr = value_tin_wclr; // @[VCmdq.scala 134:15]
- assign io_out_bits_addr1 = value_tin_addr1; // @[VCmdq.scala 134:15]
- assign io_out_bits_addr2 = value_tin_addr2; // @[VCmdq.scala 134:15]
- assign io_out_bits_base2 = value_tin_base2; // @[VCmdq.scala 134:15]
- assign io_out_bits_mode = value_tin_mode; // @[VCmdq.scala 134:15]
- assign io_out_bits_mark2 = value_tin_mark2; // @[VCmdq.scala 134:15]
- assign io_out_bits_index = value_tin_index; // @[VCmdq.scala 134:15]
- assign io_out_bits_abias = value_tin_abias; // @[VCmdq.scala 134:15]
- assign io_out_bits_bbias = value_tin_bbias; // @[VCmdq.scala 134:15]
- assign io_out_bits_asign = value_tin_asign; // @[VCmdq.scala 134:15]
- assign io_out_bits_bsign = value_tin_bsign; // @[VCmdq.scala 134:15]
- assign io_active = active; // @[VCmdq.scala 136:13]
- assign f__clock = clock;
- assign f__reset = reset;
- assign f__io_in_valid = io_in_valid; // @[VCmdq.scala 64:17]
- assign f__io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 68:27]
- assign f__io_in_bits_0_bits_tin_conv = io_in_bits_0_bits_op == 7'h45; // @[VConvCtrl.scala 71:24]
- assign f__io_in_bits_0_bits_tin_init = io_in_bits_0_bits_op == 7'h1f; // @[VConvCtrl.scala 69:24]
- assign f__io_in_bits_0_bits_tin_tran = io_in_bits_0_bits_op == 7'h20; // @[VConvCtrl.scala 70:24]
- assign f__io_in_bits_0_bits_tin_wclr = io_in_bits_0_bits_op == 7'h5; // @[VConvCtrl.scala 68:24]
- assign f__io_in_bits_0_bits_tin_addr1 = io_in_bits_0_bits_vs_addr; // @[VConvCtrl.scala 66:19 95:15]
- assign f__io_in_bits_0_bits_tin_addr2 = f_io_in_bits_0_bits_tin_acset ? io_in_bits_0_bits_vs_addr :
- io_in_bits_0_bits_vu_addr; // @[VConvCtrl.scala 74:20]
- assign f__io_in_bits_0_bits_tin_base2 = f_io_in_bits_0_bits_tin_acset ? io_in_bits_0_bits_vs_addr :
- io_in_bits_0_bits_vu_addr; // @[VConvCtrl.scala 74:20]
- assign f__io_in_bits_0_bits_tin_mode = io_in_bits_0_bits_sv_data[1:0]; // @[VConvCtrl.scala 98:22]
- assign f__io_in_bits_0_bits_tin_mark2 = 8'hff >> _f_io_in_bits_0_bits_tin_mark2_T_5; // @[VConvCtrl.scala 84:23]
- assign f__io_in_bits_0_bits_tin_index = f_io_in_bits_0_bits_tin_start[2:0]; // @[VConvCtrl.scala 100:15 66:19]
- assign f__io_in_bits_0_bits_tin_end = f_io_in_bits_0_bits_tin_stop[2:0]; // @[VConvCtrl.scala 101:15 66:19]
- assign f__io_in_bits_0_bits_tin_abias = io_in_bits_0_bits_sv_data[20:12]; // @[VConvCtrl.scala 102:22]
- assign f__io_in_bits_0_bits_tin_bbias = io_in_bits_0_bits_sv_data[30:22]; // @[VConvCtrl.scala 104:22]
- assign f__io_in_bits_0_bits_tin_asign = io_in_bits_0_bits_sv_data[21]; // @[VConvCtrl.scala 103:22]
- assign f__io_in_bits_0_bits_tin_bsign = io_in_bits_0_bits_sv_data[31]; // @[VConvCtrl.scala 105:22]
- assign f__io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 70:28]
- assign f__io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 68:27]
- assign f__io_in_bits_1_bits_tin_conv = io_in_bits_1_bits_op == 7'h45; // @[VConvCtrl.scala 71:24]
- assign f__io_in_bits_1_bits_tin_init = io_in_bits_1_bits_op == 7'h1f; // @[VConvCtrl.scala 69:24]
- assign f__io_in_bits_1_bits_tin_tran = io_in_bits_1_bits_op == 7'h20; // @[VConvCtrl.scala 70:24]
- assign f__io_in_bits_1_bits_tin_wclr = io_in_bits_1_bits_op == 7'h5; // @[VConvCtrl.scala 68:24]
- assign f__io_in_bits_1_bits_tin_addr1 = io_in_bits_1_bits_vs_addr; // @[VConvCtrl.scala 66:19 95:15]
- assign f__io_in_bits_1_bits_tin_addr2 = f_io_in_bits_1_bits_tin_acset ? io_in_bits_1_bits_vs_addr :
- io_in_bits_1_bits_vu_addr; // @[VConvCtrl.scala 74:20]
- assign f__io_in_bits_1_bits_tin_base2 = f_io_in_bits_1_bits_tin_acset ? io_in_bits_1_bits_vs_addr :
- io_in_bits_1_bits_vu_addr; // @[VConvCtrl.scala 74:20]
- assign f__io_in_bits_1_bits_tin_mode = io_in_bits_1_bits_sv_data[1:0]; // @[VConvCtrl.scala 98:22]
- assign f__io_in_bits_1_bits_tin_mark2 = 8'hff >> _f_io_in_bits_1_bits_tin_mark2_T_5; // @[VConvCtrl.scala 84:23]
- assign f__io_in_bits_1_bits_tin_index = f_io_in_bits_1_bits_tin_start[2:0]; // @[VConvCtrl.scala 100:15 66:19]
- assign f__io_in_bits_1_bits_tin_end = f_io_in_bits_1_bits_tin_stop[2:0]; // @[VConvCtrl.scala 101:15 66:19]
- assign f__io_in_bits_1_bits_tin_abias = io_in_bits_1_bits_sv_data[20:12]; // @[VConvCtrl.scala 102:22]
- assign f__io_in_bits_1_bits_tin_bbias = io_in_bits_1_bits_sv_data[30:22]; // @[VConvCtrl.scala 104:22]
- assign f__io_in_bits_1_bits_tin_asign = io_in_bits_1_bits_sv_data[21]; // @[VConvCtrl.scala 103:22]
- assign f__io_in_bits_1_bits_tin_bsign = io_in_bits_1_bits_sv_data[31]; // @[VConvCtrl.scala 105:22]
- assign f__io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 70:28]
- assign f__io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 68:27]
- assign f__io_in_bits_2_bits_tin_conv = io_in_bits_2_bits_op == 7'h45; // @[VConvCtrl.scala 71:24]
- assign f__io_in_bits_2_bits_tin_init = io_in_bits_2_bits_op == 7'h1f; // @[VConvCtrl.scala 69:24]
- assign f__io_in_bits_2_bits_tin_tran = io_in_bits_2_bits_op == 7'h20; // @[VConvCtrl.scala 70:24]
- assign f__io_in_bits_2_bits_tin_wclr = io_in_bits_2_bits_op == 7'h5; // @[VConvCtrl.scala 68:24]
- assign f__io_in_bits_2_bits_tin_addr1 = io_in_bits_2_bits_vs_addr; // @[VConvCtrl.scala 66:19 95:15]
- assign f__io_in_bits_2_bits_tin_addr2 = f_io_in_bits_2_bits_tin_acset ? io_in_bits_2_bits_vs_addr :
- io_in_bits_2_bits_vu_addr; // @[VConvCtrl.scala 74:20]
- assign f__io_in_bits_2_bits_tin_base2 = f_io_in_bits_2_bits_tin_acset ? io_in_bits_2_bits_vs_addr :
- io_in_bits_2_bits_vu_addr; // @[VConvCtrl.scala 74:20]
- assign f__io_in_bits_2_bits_tin_mode = io_in_bits_2_bits_sv_data[1:0]; // @[VConvCtrl.scala 98:22]
- assign f__io_in_bits_2_bits_tin_mark2 = 8'hff >> _f_io_in_bits_2_bits_tin_mark2_T_5; // @[VConvCtrl.scala 84:23]
- assign f__io_in_bits_2_bits_tin_index = f_io_in_bits_2_bits_tin_start[2:0]; // @[VConvCtrl.scala 100:15 66:19]
- assign f__io_in_bits_2_bits_tin_end = f_io_in_bits_2_bits_tin_stop[2:0]; // @[VConvCtrl.scala 101:15 66:19]
- assign f__io_in_bits_2_bits_tin_abias = io_in_bits_2_bits_sv_data[20:12]; // @[VConvCtrl.scala 102:22]
- assign f__io_in_bits_2_bits_tin_bbias = io_in_bits_2_bits_sv_data[30:22]; // @[VConvCtrl.scala 104:22]
- assign f__io_in_bits_2_bits_tin_asign = io_in_bits_2_bits_sv_data[21]; // @[VConvCtrl.scala 103:22]
- assign f__io_in_bits_2_bits_tin_bsign = io_in_bits_2_bits_sv_data[31]; // @[VConvCtrl.scala 105:22]
- assign f__io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 70:28]
- assign f__io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 68:27]
- assign f__io_in_bits_3_bits_tin_conv = io_in_bits_3_bits_op == 7'h45; // @[VConvCtrl.scala 71:24]
- assign f__io_in_bits_3_bits_tin_init = io_in_bits_3_bits_op == 7'h1f; // @[VConvCtrl.scala 69:24]
- assign f__io_in_bits_3_bits_tin_tran = io_in_bits_3_bits_op == 7'h20; // @[VConvCtrl.scala 70:24]
- assign f__io_in_bits_3_bits_tin_wclr = io_in_bits_3_bits_op == 7'h5; // @[VConvCtrl.scala 68:24]
- assign f__io_in_bits_3_bits_tin_addr1 = io_in_bits_3_bits_vs_addr; // @[VConvCtrl.scala 66:19 95:15]
- assign f__io_in_bits_3_bits_tin_addr2 = f_io_in_bits_3_bits_tin_acset ? io_in_bits_3_bits_vs_addr :
- io_in_bits_3_bits_vu_addr; // @[VConvCtrl.scala 74:20]
- assign f__io_in_bits_3_bits_tin_base2 = f_io_in_bits_3_bits_tin_acset ? io_in_bits_3_bits_vs_addr :
- io_in_bits_3_bits_vu_addr; // @[VConvCtrl.scala 74:20]
- assign f__io_in_bits_3_bits_tin_mode = io_in_bits_3_bits_sv_data[1:0]; // @[VConvCtrl.scala 98:22]
- assign f__io_in_bits_3_bits_tin_mark2 = 8'hff >> _f_io_in_bits_3_bits_tin_mark2_T_5; // @[VConvCtrl.scala 84:23]
- assign f__io_in_bits_3_bits_tin_index = f_io_in_bits_3_bits_tin_start[2:0]; // @[VConvCtrl.scala 100:15 66:19]
- assign f__io_in_bits_3_bits_tin_end = f_io_in_bits_3_bits_tin_stop[2:0]; // @[VConvCtrl.scala 101:15 66:19]
- assign f__io_in_bits_3_bits_tin_abias = io_in_bits_3_bits_sv_data[20:12]; // @[VConvCtrl.scala 102:22]
- assign f__io_in_bits_3_bits_tin_bbias = io_in_bits_3_bits_sv_data[30:22]; // @[VConvCtrl.scala 104:22]
- assign f__io_in_bits_3_bits_tin_asign = io_in_bits_3_bits_sv_data[21]; // @[VConvCtrl.scala 103:22]
- assign f__io_in_bits_3_bits_tin_bsign = io_in_bits_3_bits_sv_data[31]; // @[VConvCtrl.scala 105:22]
- assign f__io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 70:28]
- assign f__io_out_ready = ~valid | io_out_ready & last; // @[VCmdq.scala 73:28]
- always @(posedge clock) begin
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_conv <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_conv <= f__io_out_bits_tin_conv; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_conv <= _GEN_15;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_init <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_init <= f__io_out_bits_tin_init; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_init <= _GEN_14;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_tran <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_tran <= f__io_out_bits_tin_tran; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_tran <= _GEN_13;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_wclr <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_wclr <= f__io_out_bits_tin_wclr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_wclr <= _GEN_12;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_addr1 <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_addr1 <= f__io_out_bits_tin_addr1; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_addr1 <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_addr2 <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_addr2 <= f__io_out_bits_tin_addr2; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_addr2 <= tin_addr2; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_addr2 <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_base2 <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_base2 <= f__io_out_bits_tin_base2; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_base2 <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_mode <= 2'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_mode <= f__io_out_bits_tin_mode; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_mode <= 2'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_mark2 <= 8'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_mark2 <= f__io_out_bits_tin_mark2; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_mark2 <= 8'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_index <= 3'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_index <= f__io_out_bits_tin_index; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_index <= tin_index; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_index <= 3'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_end <= 3'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_end <= f__io_out_bits_tin_end; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_end <= 3'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_abias <= 9'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_abias <= f__io_out_bits_tin_abias; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_abias <= 9'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_bbias <= 9'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_bbias <= f__io_out_bits_tin_bbias; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_bbias <= 9'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_asign <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_asign <= f__io_out_bits_tin_asign; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_asign <= _GEN_2;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_bsign <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_bsign <= f__io_out_bits_tin_bsign; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_bsign <= _GEN_1;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_m <= 1'h0; // @[VCmdq.scala 98:13]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 77:43]
- value_m <= f__io_out_bits_m; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_m <= _GEN_16;
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (valid & ~reset & ~(~value_m)) begin
- $fatal; // @[VConvCtrl.scala 112:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (valid & ~reset & ~(~value_m)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VConvCtrl.scala:112 assert(m === false.B)\n"); // @[VConvCtrl.scala 112:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_81 & ~(value_tin_index <= value_tin_end)) begin
- $fatal; // @[VConvCtrl.scala 113:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_81 & ~(value_tin_index <= value_tin_end)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VConvCtrl.scala:113 assert(in.index <= in.end)\n"); // @[VConvCtrl.scala 113:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_81 & ~(value_tin_addr1[2:0] == 3'h0)) begin
- $fatal; // @[VConvCtrl.scala 118:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_81 & ~(value_tin_addr1[2:0] == 3'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VConvCtrl.scala:118 assert(in.addr1(2,0) === 0.U)\n"); // @[VConvCtrl.scala 118:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 118:69]
- active <= 64'h0; // @[VCmdq.scala 123:12]
- end else if (io_in_valid & io_in_ready | _T_14) begin // @[VCmdq.scala 49:23]
- active <= _active_T_16;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 77:43]
- valid <= 1'h0; // @[VCmdq.scala 78:11]
- end else begin
- valid <= f__io_out_valid & f__io_out_ready | _GEN_18;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 77:43]
- step <= 5'h0; // @[VCmdq.scala 80:10]
- end else if (f__io_out_valid & f__io_out_ready) begin // @[VCmdq.scala 81:46]
- step <= 5'h0; // @[VCmdq.scala 82:18 86:12 92:12]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 58:21]
- if (~last) begin
- step <= _step_T_1;
- end else begin
- step <= 5'h0;
- end
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {2{`RANDOM}};
- active = _RAND_0[63:0];
- _RAND_1 = {1{`RANDOM}};
- valid = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- value_tin_conv = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- value_tin_init = _RAND_3[0:0];
- _RAND_4 = {1{`RANDOM}};
- value_tin_tran = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- value_tin_wclr = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- value_tin_addr1 = _RAND_6[5:0];
- _RAND_7 = {1{`RANDOM}};
- value_tin_addr2 = _RAND_7[5:0];
- _RAND_8 = {1{`RANDOM}};
- value_tin_base2 = _RAND_8[5:0];
- _RAND_9 = {1{`RANDOM}};
- value_tin_mode = _RAND_9[1:0];
- _RAND_10 = {1{`RANDOM}};
- value_tin_mark2 = _RAND_10[7:0];
- _RAND_11 = {1{`RANDOM}};
- value_tin_index = _RAND_11[2:0];
- _RAND_12 = {1{`RANDOM}};
- value_tin_end = _RAND_12[2:0];
- _RAND_13 = {1{`RANDOM}};
- value_tin_abias = _RAND_13[8:0];
- _RAND_14 = {1{`RANDOM}};
- value_tin_bbias = _RAND_14[8:0];
- _RAND_15 = {1{`RANDOM}};
- value_tin_asign = _RAND_15[0:0];
- _RAND_16 = {1{`RANDOM}};
- value_tin_bsign = _RAND_16[0:0];
- _RAND_17 = {1{`RANDOM}};
- value_m = _RAND_17[0:0];
- _RAND_18 = {1{`RANDOM}};
- step = _RAND_18[4:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- active = 64'h0;
- end
- if (reset) begin
- valid = 1'h0;
- end
- if (reset) begin
- step = 5'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VConvCtrl(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_op,
- input io_in_bits_0_bits_m,
- input [5:0] io_in_bits_0_bits_vs_addr,
- input [5:0] io_in_bits_0_bits_vu_addr,
- input [31:0] io_in_bits_0_bits_sv_data,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_op,
- input io_in_bits_1_bits_m,
- input [5:0] io_in_bits_1_bits_vs_addr,
- input [5:0] io_in_bits_1_bits_vu_addr,
- input [31:0] io_in_bits_1_bits_sv_data,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_op,
- input io_in_bits_2_bits_m,
- input [5:0] io_in_bits_2_bits_vs_addr,
- input [5:0] io_in_bits_2_bits_vu_addr,
- input [31:0] io_in_bits_2_bits_sv_data,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_op,
- input io_in_bits_3_bits_m,
- input [5:0] io_in_bits_3_bits_vs_addr,
- input [5:0] io_in_bits_3_bits_vu_addr,
- input [31:0] io_in_bits_3_bits_sv_data,
- output [63:0] io_active,
- input [127:0] io_vrfsb,
- output io_out_valid,
- output io_out_ready,
- output io_out_op_conv,
- output io_out_op_init,
- output io_out_op_tran,
- output io_out_op_wclr,
- output [5:0] io_out_addr1,
- output [5:0] io_out_addr2,
- output [1:0] io_out_mode,
- output [2:0] io_out_index,
- output [8:0] io_out_abias,
- output [8:0] io_out_bbias,
- output io_out_asign,
- output io_out_bsign
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [63:0] _RAND_0;
- reg [63:0] _RAND_1;
-`endif // RANDOMIZE_REG_INIT
- wire q_clock; // @[VCmdq.scala 30:11]
- wire q_reset; // @[VCmdq.scala 30:11]
- wire q_io_in_ready; // @[VCmdq.scala 30:11]
- wire q_io_in_valid; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_0_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_0_bits_op; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_0_bits_m; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_0_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_0_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_0_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_1_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_1_bits_op; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_1_bits_m; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_1_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_1_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_1_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_2_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_2_bits_op; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_2_bits_m; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_2_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_2_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_2_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_3_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_3_bits_op; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_3_bits_m; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_3_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_3_bits_vu_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_3_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_out_ready; // @[VCmdq.scala 30:11]
- wire q_io_out_valid; // @[VCmdq.scala 30:11]
- wire q_io_out_bits_conv; // @[VCmdq.scala 30:11]
- wire q_io_out_bits_init; // @[VCmdq.scala 30:11]
- wire q_io_out_bits_tran; // @[VCmdq.scala 30:11]
- wire q_io_out_bits_wclr; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_out_bits_addr1; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_out_bits_addr2; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_out_bits_base2; // @[VCmdq.scala 30:11]
- wire [1:0] q_io_out_bits_mode; // @[VCmdq.scala 30:11]
- wire [7:0] q_io_out_bits_mark2; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_out_bits_index; // @[VCmdq.scala 30:11]
- wire [8:0] q_io_out_bits_abias; // @[VCmdq.scala 30:11]
- wire [8:0] q_io_out_bits_bbias; // @[VCmdq.scala 30:11]
- wire q_io_out_bits_asign; // @[VCmdq.scala 30:11]
- wire q_io_out_bits_bsign; // @[VCmdq.scala 30:11]
- wire [63:0] q_io_active; // @[VCmdq.scala 30:11]
- wire [5:0] _active_active1_T_1 = {q_io_out_bits_addr1[5:3],3'h0}; // @[Cat.scala 31:58]
- wire [70:0] _active_active1_T_2 = 71'hff << _active_active1_T_1; // @[VConvCtrl.scala 146:25]
- wire [14:0] _active_active2_T = {{7'd0}, q_io_out_bits_mark2}; // @[VConvCtrl.scala 147:41]
- wire [14:0] _active_active2_T_1 = _active_active2_T & _active_active2_T; // @[VConvCtrl.scala 147:29]
- wire [77:0] _GEN_0 = {{63'd0}, _active_active2_T_1}; // @[VConvCtrl.scala 147:56]
- wire [77:0] _active_active2_T_2 = _GEN_0 << q_io_out_bits_base2; // @[VConvCtrl.scala 147:56]
- wire [63:0] active_active2 = _active_active2_T_2[63:0]; // @[VConvCtrl.scala 147:68]
- wire _active_active_T = q_io_out_bits_conv | q_io_out_bits_tran; // @[VConvCtrl.scala 156:32]
- wire [63:0] active_active1 = _active_active1_T_2[63:0]; // @[VConvCtrl.scala 135:23 146:15]
- wire [63:0] _active_active_T_1 = _active_active_T ? active_active1 : 64'h0; // @[Library.scala 22:8]
- wire _active_active_T_2 = q_io_out_bits_conv | q_io_out_bits_init; // @[VConvCtrl.scala 157:32]
- wire [63:0] _active_active_T_3 = _active_active_T_2 ? active_active2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active = _active_active_T_1 | _active_active_T_3; // @[VConvCtrl.scala 156:53]
- wire [63:0] vrfsb0 = io_vrfsb[63:0] | io_vrfsb[127:64]; // @[VConvCtrl.scala 172:31]
- reg [63:0] vrfsb1; // @[VConvCtrl.scala 173:23]
- reg [63:0] vrfsb2; // @[VConvCtrl.scala 174:23]
- wire [63:0] _vrfsb_T = vrfsb0 | vrfsb1; // @[VConvCtrl.scala 175:22]
- wire [63:0] vrfsb = _vrfsb_T | vrfsb2; // @[VConvCtrl.scala 175:31]
- wire [63:0] _ready_T = active & vrfsb; // @[VConvCtrl.scala 179:23]
- wire _T_4 = ~reset; // @[VConvCtrl.scala 200:9]
- wire [3:0] _T_8 = {io_out_op_conv,io_out_op_init,io_out_op_tran,io_out_op_wclr}; // @[Cat.scala 31:58]
- wire [1:0] _T_13 = _T_8[0] + _T_8[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_15 = _T_8[2] + _T_8[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_17 = _T_13 + _T_15; // @[Bitwise.scala 48:55]
- wire _T_19 = _T_17 == 3'h1; // @[VConvCtrl.scala 203:88]
- VCmdq_2 q ( // @[VCmdq.scala 30:11]
- .clock(q_clock),
- .reset(q_reset),
- .io_in_ready(q_io_in_ready),
- .io_in_valid(q_io_in_valid),
- .io_in_bits_0_valid(q_io_in_bits_0_valid),
- .io_in_bits_0_bits_op(q_io_in_bits_0_bits_op),
- .io_in_bits_0_bits_m(q_io_in_bits_0_bits_m),
- .io_in_bits_0_bits_vs_addr(q_io_in_bits_0_bits_vs_addr),
- .io_in_bits_0_bits_vu_addr(q_io_in_bits_0_bits_vu_addr),
- .io_in_bits_0_bits_sv_data(q_io_in_bits_0_bits_sv_data),
- .io_in_bits_1_valid(q_io_in_bits_1_valid),
- .io_in_bits_1_bits_op(q_io_in_bits_1_bits_op),
- .io_in_bits_1_bits_m(q_io_in_bits_1_bits_m),
- .io_in_bits_1_bits_vs_addr(q_io_in_bits_1_bits_vs_addr),
- .io_in_bits_1_bits_vu_addr(q_io_in_bits_1_bits_vu_addr),
- .io_in_bits_1_bits_sv_data(q_io_in_bits_1_bits_sv_data),
- .io_in_bits_2_valid(q_io_in_bits_2_valid),
- .io_in_bits_2_bits_op(q_io_in_bits_2_bits_op),
- .io_in_bits_2_bits_m(q_io_in_bits_2_bits_m),
- .io_in_bits_2_bits_vs_addr(q_io_in_bits_2_bits_vs_addr),
- .io_in_bits_2_bits_vu_addr(q_io_in_bits_2_bits_vu_addr),
- .io_in_bits_2_bits_sv_data(q_io_in_bits_2_bits_sv_data),
- .io_in_bits_3_valid(q_io_in_bits_3_valid),
- .io_in_bits_3_bits_op(q_io_in_bits_3_bits_op),
- .io_in_bits_3_bits_m(q_io_in_bits_3_bits_m),
- .io_in_bits_3_bits_vs_addr(q_io_in_bits_3_bits_vs_addr),
- .io_in_bits_3_bits_vu_addr(q_io_in_bits_3_bits_vu_addr),
- .io_in_bits_3_bits_sv_data(q_io_in_bits_3_bits_sv_data),
- .io_out_ready(q_io_out_ready),
- .io_out_valid(q_io_out_valid),
- .io_out_bits_conv(q_io_out_bits_conv),
- .io_out_bits_init(q_io_out_bits_init),
- .io_out_bits_tran(q_io_out_bits_tran),
- .io_out_bits_wclr(q_io_out_bits_wclr),
- .io_out_bits_addr1(q_io_out_bits_addr1),
- .io_out_bits_addr2(q_io_out_bits_addr2),
- .io_out_bits_base2(q_io_out_bits_base2),
- .io_out_bits_mode(q_io_out_bits_mode),
- .io_out_bits_mark2(q_io_out_bits_mark2),
- .io_out_bits_index(q_io_out_bits_index),
- .io_out_bits_abias(q_io_out_bits_abias),
- .io_out_bits_bbias(q_io_out_bits_bbias),
- .io_out_bits_asign(q_io_out_bits_asign),
- .io_out_bits_bsign(q_io_out_bits_bsign),
- .io_active(q_io_active)
- );
- assign io_in_ready = q_io_in_ready; // @[VConvCtrl.scala 164:11]
- assign io_active = q_io_active; // @[VConvCtrl.scala 207:13]
- assign io_out_valid = q_io_out_valid; // @[VConvCtrl.scala 183:16]
- assign io_out_ready = _ready_T == 64'h0; // @[VConvCtrl.scala 179:32]
- assign io_out_op_conv = q_io_out_bits_conv; // @[VConvCtrl.scala 186:18]
- assign io_out_op_init = q_io_out_bits_init; // @[VConvCtrl.scala 187:18]
- assign io_out_op_tran = q_io_out_bits_tran; // @[VConvCtrl.scala 188:18]
- assign io_out_op_wclr = q_io_out_bits_wclr; // @[VConvCtrl.scala 189:18]
- assign io_out_addr1 = q_io_out_bits_addr1; // @[VConvCtrl.scala 193:16]
- assign io_out_addr2 = q_io_out_bits_addr2; // @[VConvCtrl.scala 194:16]
- assign io_out_mode = q_io_out_bits_mode; // @[VConvCtrl.scala 191:16]
- assign io_out_index = q_io_out_bits_index; // @[VConvCtrl.scala 192:16]
- assign io_out_abias = q_io_out_bits_abias; // @[VConvCtrl.scala 195:16]
- assign io_out_bbias = q_io_out_bits_bbias; // @[VConvCtrl.scala 197:16]
- assign io_out_asign = q_io_out_bits_asign; // @[VConvCtrl.scala 196:16]
- assign io_out_bsign = q_io_out_bits_bsign; // @[VConvCtrl.scala 198:16]
- assign q_clock = clock;
- assign q_reset = reset;
- assign q_io_in_valid = io_in_valid; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_0_valid = io_in_bits_0_valid; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_0_bits_vu_addr = io_in_bits_0_bits_vu_addr; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_1_valid = io_in_bits_1_valid; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_1_bits_vu_addr = io_in_bits_1_bits_vu_addr; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_2_valid = io_in_bits_2_valid; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_2_bits_vu_addr = io_in_bits_2_bits_vu_addr; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_3_valid = io_in_bits_3_valid; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_3_bits_vu_addr = io_in_bits_3_bits_vu_addr; // @[VConvCtrl.scala 164:11]
- assign q_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VConvCtrl.scala 164:11]
- assign q_io_out_ready = _ready_T == 64'h0; // @[VConvCtrl.scala 179:32]
- always @(posedge clock) begin
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(q_io_out_bits_wclr & ~q_io_out_ready))) begin
- $fatal; // @[VConvCtrl.scala 200:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(q_io_out_bits_wclr & ~q_io_out_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VConvCtrl.scala:200 assert(!(q.io.out.bits.wclr && !q.io.out.ready))\n"); // @[VConvCtrl.scala 200:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(io_out_valid & io_out_ready) | _T_19)) begin
- $fatal; // @[VConvCtrl.scala 202:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(io_out_valid & io_out_ready) | _T_19)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VConvCtrl.scala:202 assert(!(io.out.valid && io.out.ready) ||\n"); // @[VConvCtrl.scala 202:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VConvCtrl.scala 172:31]
- vrfsb1 <= 64'h0;
- end else begin
- vrfsb1 <= io_vrfsb[63:0] | io_vrfsb[127:64];
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VConvCtrl.scala 174:23]
- vrfsb2 <= 64'h0; // @[VConvCtrl.scala 174:23]
- end else begin
- vrfsb2 <= vrfsb1; // @[VConvCtrl.scala 177:10]
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {2{`RANDOM}};
- vrfsb1 = _RAND_0[63:0];
- _RAND_1 = {2{`RANDOM}};
- vrfsb2 = _RAND_1[63:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- vrfsb1 = 64'h0;
- end
- if (reset) begin
- vrfsb2 = 64'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Fifo4e_3(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_tin_op,
- input [31:0] io_in_bits_0_bits_tin_addr,
- input [31:0] io_in_bits_0_bits_tin_offset,
- input [7:0] io_in_bits_0_bits_tin_remain,
- input [5:0] io_in_bits_0_bits_tin_vd_addr,
- input io_in_bits_0_bits_tin_vs_valid,
- input [5:0] io_in_bits_0_bits_tin_vs_addr,
- input [3:0] io_in_bits_0_bits_tin_vs_tag,
- input io_in_bits_0_bits_tin_last,
- input io_in_bits_0_bits_m,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_tin_op,
- input [31:0] io_in_bits_1_bits_tin_addr,
- input [31:0] io_in_bits_1_bits_tin_offset,
- input [7:0] io_in_bits_1_bits_tin_remain,
- input [5:0] io_in_bits_1_bits_tin_vd_addr,
- input io_in_bits_1_bits_tin_vs_valid,
- input [5:0] io_in_bits_1_bits_tin_vs_addr,
- input [3:0] io_in_bits_1_bits_tin_vs_tag,
- input io_in_bits_1_bits_tin_last,
- input io_in_bits_1_bits_m,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_tin_op,
- input [31:0] io_in_bits_2_bits_tin_addr,
- input [31:0] io_in_bits_2_bits_tin_offset,
- input [7:0] io_in_bits_2_bits_tin_remain,
- input [5:0] io_in_bits_2_bits_tin_vd_addr,
- input io_in_bits_2_bits_tin_vs_valid,
- input [5:0] io_in_bits_2_bits_tin_vs_addr,
- input [3:0] io_in_bits_2_bits_tin_vs_tag,
- input io_in_bits_2_bits_tin_last,
- input io_in_bits_2_bits_m,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_tin_op,
- input [31:0] io_in_bits_3_bits_tin_addr,
- input [31:0] io_in_bits_3_bits_tin_offset,
- input [7:0] io_in_bits_3_bits_tin_remain,
- input [5:0] io_in_bits_3_bits_tin_vd_addr,
- input io_in_bits_3_bits_tin_vs_valid,
- input [5:0] io_in_bits_3_bits_tin_vs_addr,
- input [3:0] io_in_bits_3_bits_tin_vs_tag,
- input io_in_bits_3_bits_tin_last,
- input io_in_bits_3_bits_m,
- input io_out_ready,
- output io_out_valid,
- output [6:0] io_out_bits_tin_op,
- output [31:0] io_out_bits_tin_addr,
- output [31:0] io_out_bits_tin_offset,
- output [7:0] io_out_bits_tin_remain,
- output [5:0] io_out_bits_tin_vd_addr,
- output io_out_bits_tin_vs_valid,
- output [5:0] io_out_bits_tin_vs_addr,
- output [3:0] io_out_bits_tin_vs_tag,
- output [1:0] io_out_bits_tin_quad,
- output io_out_bits_tin_last,
- output io_out_bits_m,
- output io_entry_0_valid,
- output io_entry_0_bits_tin_vs_valid,
- output [5:0] io_entry_0_bits_tin_vs_addr,
- output io_entry_0_bits_m,
- output io_entry_1_valid,
- output io_entry_1_bits_tin_vs_valid,
- output [5:0] io_entry_1_bits_tin_vs_addr,
- output io_entry_1_bits_m,
- output io_entry_2_valid,
- output io_entry_2_bits_tin_vs_valid,
- output [5:0] io_entry_2_bits_tin_vs_addr,
- output io_entry_2_bits_m,
- output io_entry_3_valid,
- output io_entry_3_bits_tin_vs_valid,
- output [5:0] io_entry_3_bits_tin_vs_addr,
- output io_entry_3_bits_m,
- output io_entry_4_valid,
- output io_entry_4_bits_tin_vs_valid,
- output [5:0] io_entry_4_bits_tin_vs_addr,
- output io_entry_4_bits_m,
- output io_entry_5_valid,
- output io_entry_5_bits_tin_vs_valid,
- output [5:0] io_entry_5_bits_tin_vs_addr,
- output io_entry_5_bits_m,
- output io_entry_6_valid,
- output io_entry_6_bits_tin_vs_valid,
- output [5:0] io_entry_6_bits_tin_vs_addr,
- output io_entry_6_bits_m,
- output io_entry_7_valid,
- output io_entry_7_bits_tin_vs_valid,
- output [5:0] io_entry_7_bits_tin_vs_addr,
- output io_entry_7_bits_m
-);
-`ifdef RANDOMIZE_MEM_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
-`endif // RANDOMIZE_REG_INIT
- reg [6:0] mem_tin_op [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [31:0] mem_tin_addr [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [31:0] mem_tin_offset [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [7:0] mem_tin_remain [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [5:0] mem_tin_vd_addr [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg mem_tin_vs_valid [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [5:0] mem_tin_vs_addr [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [3:0] mem_tin_vs_tag [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [1:0] mem_tin_quad [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg mem_tin_last [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_last_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_last_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg mem_m [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_m_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [2:0] in0pos; // @[Fifo4e.scala 45:23]
- reg [2:0] in1pos; // @[Fifo4e.scala 46:23]
- reg [2:0] in2pos; // @[Fifo4e.scala 47:23]
- reg [2:0] in3pos; // @[Fifo4e.scala 48:23]
- reg [2:0] outpos; // @[Fifo4e.scala 49:23]
- reg [3:0] mcount; // @[Fifo4e.scala 50:23]
- wire ivalid = io_in_valid & io_in_ready; // @[Fifo4e.scala 56:28]
- wire dec = io_out_valid & io_out_ready; // @[Fifo4e.scala 57:29]
- wire [3:0] iactive = {io_in_bits_3_valid,io_in_bits_2_valid,io_in_bits_1_valid,io_in_bits_0_valid}; // @[Cat.scala 31:58]
- wire [1:0] _icount_T = io_in_bits_0_valid + io_in_bits_1_valid; // @[Fifo4e.scala 62:36]
- wire [1:0] _GEN_2010 = {{1'd0}, io_in_bits_2_valid}; // @[Fifo4e.scala 62:59]
- wire [1:0] _icount_T_2 = _icount_T + _GEN_2010; // @[Fifo4e.scala 62:59]
- wire [1:0] _GEN_2011 = {{1'd0}, io_in_bits_3_valid}; // @[Fifo4e.scala 63:36]
- wire [2:0] icount = _icount_T_2 + _GEN_2011; // @[Fifo4e.scala 63:36]
- wire [3:0] in0pos_c = in0pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in0pos_d_T_2 = in0pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in0pos_d_T_3 = in0pos_c < 4'h8 ? in0pos_c : _in0pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in0pos_d = _in0pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] in1pos_c = in1pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in1pos_d_T_2 = in1pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in1pos_d_T_3 = in1pos_c < 4'h8 ? in1pos_c : _in1pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in1pos_d = _in1pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] in2pos_c = in2pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in2pos_d_T_2 = in2pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in2pos_d_T_3 = in2pos_c < 4'h8 ? in2pos_c : _in2pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in2pos_d = _in2pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] in3pos_c = in3pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in3pos_d_T_2 = in3pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in3pos_d_T_3 = in3pos_c < 4'h8 ? in3pos_c : _in3pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in3pos_d = _in3pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] outpos_c = outpos + 3'h1; // @[Fifo4e.scala 38:15]
- wire [3:0] _outpos_d_T_2 = outpos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _outpos_d_T_3 = outpos_c < 4'h8 ? outpos_c : _outpos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] outpos_d = _outpos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [2:0] inc = ivalid ? icount : 3'h0; // @[Library.scala 22:8]
- wire _T = ivalid | dec; // @[Fifo4e.scala 81:16]
- wire [3:0] _GEN_2012 = {{1'd0}, inc}; // @[Fifo4e.scala 82:27]
- wire [3:0] _nxtcount_T_1 = mcount + _GEN_2012; // @[Fifo4e.scala 82:27]
- wire [3:0] _GEN_2013 = {{3'd0}, dec}; // @[Fifo4e.scala 82:33]
- wire [3:0] nxtcount = _nxtcount_T_1 - _GEN_2013; // @[Fifo4e.scala 82:33]
- wire _in0_T_1 = iactive == 4'h8; // @[Fifo4.scala 31:27]
- wire _in0_T_3 = iactive[2:0] == 3'h4; // @[Fifo4.scala 32:27]
- wire _in0_T_5 = iactive[1:0] == 2'h2; // @[Fifo4.scala 33:27]
- wire [3:0] in0valid = {_in0_T_1,_in0_T_3,_in0_T_5,iactive[0]}; // @[Cat.scala 31:58]
- wire _in1_T_3 = iactive == 4'ha; // @[Fifo4.scala 37:27]
- wire _in1_T_4 = iactive == 4'hc | _in1_T_3; // @[Fifo4.scala 36:36]
- wire _in1_T_6 = iactive == 4'h9; // @[Fifo4.scala 38:27]
- wire _in1_T_7 = _in1_T_4 | _in1_T_6; // @[Fifo4.scala 37:36]
- wire _in1_T_11 = iactive[2:0] == 3'h5; // @[Fifo4.scala 40:27]
- wire _in1_T_12 = iactive[2:0] == 3'h6 | _in1_T_11; // @[Fifo4.scala 39:35]
- wire _in1_T_14 = iactive[1:0] == 2'h3; // @[Fifo4.scala 41:27]
- wire [3:0] in1valid = {_in1_T_7,_in1_T_12,_in1_T_14,1'h0}; // @[Cat.scala 31:58]
- wire _in2_T_3 = iactive == 4'hd; // @[Fifo4.scala 45:27]
- wire _in2_T_4 = iactive == 4'he | _in2_T_3; // @[Fifo4.scala 44:36]
- wire _in2_T_6 = iactive == 4'hb; // @[Fifo4.scala 46:27]
- wire _in2_T_7 = _in2_T_4 | _in2_T_6; // @[Fifo4.scala 45:36]
- wire [3:0] _GEN_2014 = {{1'd0}, iactive[2:0]}; // @[Fifo4.scala 47:27]
- wire _in2_T_11 = iactive[2:0] == 3'h7; // @[Fifo4.scala 48:27]
- wire _in2_T_12 = _GEN_2014 == 4'hf | _in2_T_11; // @[Fifo4.scala 47:36]
- wire [3:0] in2valid = {_in2_T_7,_in2_T_12,2'h0}; // @[Cat.scala 31:58]
- wire _in3_T_1 = iactive == 4'hf; // @[Fifo4.scala 51:27]
- wire [3:0] in3valid = {_in3_T_1,1'h0,2'h0}; // @[Cat.scala 31:58]
- wire _valid_T = in0pos == 3'h0; // @[Fifo4e.scala 92:28]
- wire _valid_T_3 = in1pos == 3'h0; // @[Fifo4e.scala 93:28]
- wire _valid_T_5 = in1pos == 3'h0 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_6 = in0pos == 3'h0 & in0valid[3] | _valid_T_5; // @[Fifo4e.scala 92:51]
- wire _valid_T_7 = in2pos == 3'h0; // @[Fifo4e.scala 94:28]
- wire _valid_T_9 = in2pos == 3'h0 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_10 = _valid_T_6 | _valid_T_9; // @[Fifo4e.scala 93:51]
- wire _valid_T_13 = in3pos == 3'h0 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_14 = _valid_T_10 | _valid_T_13; // @[Fifo4e.scala 94:51]
- wire _valid_T_20 = _valid_T_3 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_21 = _valid_T & in0valid[2] | _valid_T_20; // @[Fifo4e.scala 96:51]
- wire _valid_T_24 = _valid_T_7 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_25 = _valid_T_21 | _valid_T_24; // @[Fifo4e.scala 97:51]
- wire _valid_T_31 = _valid_T_3 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_32 = _valid_T & in0valid[1] | _valid_T_31; // @[Fifo4e.scala 99:51]
- wire _valid_T_35 = _valid_T & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid = {_valid_T_14,_valid_T_25,_valid_T_32,_valid_T_35}; // @[Cat.scala 31:58]
- wire _GEN_45 = valid[2] ? 1'h0 : valid[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_81 = valid[1] ? 1'h0 : valid[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_99 = valid[1] ? 1'h0 : _GEN_45; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_135 = valid[0] ? 1'h0 : valid[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_153 = valid[0] ? 1'h0 : _GEN_81; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_171 = valid[0] ? 1'h0 : _GEN_99; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_36 = in0pos == 3'h1; // @[Fifo4e.scala 92:28]
- wire _valid_T_39 = in1pos == 3'h1; // @[Fifo4e.scala 93:28]
- wire _valid_T_41 = in1pos == 3'h1 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_42 = in0pos == 3'h1 & in0valid[3] | _valid_T_41; // @[Fifo4e.scala 92:51]
- wire _valid_T_43 = in2pos == 3'h1; // @[Fifo4e.scala 94:28]
- wire _valid_T_45 = in2pos == 3'h1 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_46 = _valid_T_42 | _valid_T_45; // @[Fifo4e.scala 93:51]
- wire _valid_T_49 = in3pos == 3'h1 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_50 = _valid_T_46 | _valid_T_49; // @[Fifo4e.scala 94:51]
- wire _valid_T_56 = _valid_T_39 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_57 = _valid_T_36 & in0valid[2] | _valid_T_56; // @[Fifo4e.scala 96:51]
- wire _valid_T_60 = _valid_T_43 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_61 = _valid_T_57 | _valid_T_60; // @[Fifo4e.scala 97:51]
- wire _valid_T_67 = _valid_T_39 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_68 = _valid_T_36 & in0valid[1] | _valid_T_67; // @[Fifo4e.scala 99:51]
- wire _valid_T_71 = _valid_T_36 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_1 = {_valid_T_50,_valid_T_61,_valid_T_68,_valid_T_71}; // @[Cat.scala 31:58]
- wire _GEN_295 = valid_1[2] ? 1'h0 : valid_1[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_329 = valid_1[1] ? 1'h0 : valid_1[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_346 = valid_1[1] ? 1'h0 : _GEN_295; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_380 = valid_1[0] ? 1'h0 : valid_1[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_397 = valid_1[0] ? 1'h0 : _GEN_329; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_414 = valid_1[0] ? 1'h0 : _GEN_346; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_72 = in0pos == 3'h2; // @[Fifo4e.scala 92:28]
- wire _valid_T_75 = in1pos == 3'h2; // @[Fifo4e.scala 93:28]
- wire _valid_T_77 = in1pos == 3'h2 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_78 = in0pos == 3'h2 & in0valid[3] | _valid_T_77; // @[Fifo4e.scala 92:51]
- wire _valid_T_79 = in2pos == 3'h2; // @[Fifo4e.scala 94:28]
- wire _valid_T_81 = in2pos == 3'h2 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_82 = _valid_T_78 | _valid_T_81; // @[Fifo4e.scala 93:51]
- wire _valid_T_85 = in3pos == 3'h2 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_86 = _valid_T_82 | _valid_T_85; // @[Fifo4e.scala 94:51]
- wire _valid_T_92 = _valid_T_75 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_93 = _valid_T_72 & in0valid[2] | _valid_T_92; // @[Fifo4e.scala 96:51]
- wire _valid_T_96 = _valid_T_79 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_97 = _valid_T_93 | _valid_T_96; // @[Fifo4e.scala 97:51]
- wire _valid_T_103 = _valid_T_75 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_104 = _valid_T_72 & in0valid[1] | _valid_T_103; // @[Fifo4e.scala 99:51]
- wire _valid_T_107 = _valid_T_72 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_2 = {_valid_T_86,_valid_T_97,_valid_T_104,_valid_T_107}; // @[Cat.scala 31:58]
- wire _GEN_535 = valid_2[2] ? 1'h0 : valid_2[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_571 = valid_2[1] ? 1'h0 : valid_2[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_589 = valid_2[1] ? 1'h0 : _GEN_535; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_625 = valid_2[0] ? 1'h0 : valid_2[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_643 = valid_2[0] ? 1'h0 : _GEN_571; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_661 = valid_2[0] ? 1'h0 : _GEN_589; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_108 = in0pos == 3'h3; // @[Fifo4e.scala 92:28]
- wire _valid_T_111 = in1pos == 3'h3; // @[Fifo4e.scala 93:28]
- wire _valid_T_113 = in1pos == 3'h3 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_114 = in0pos == 3'h3 & in0valid[3] | _valid_T_113; // @[Fifo4e.scala 92:51]
- wire _valid_T_115 = in2pos == 3'h3; // @[Fifo4e.scala 94:28]
- wire _valid_T_117 = in2pos == 3'h3 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_118 = _valid_T_114 | _valid_T_117; // @[Fifo4e.scala 93:51]
- wire _valid_T_121 = in3pos == 3'h3 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_122 = _valid_T_118 | _valid_T_121; // @[Fifo4e.scala 94:51]
- wire _valid_T_128 = _valid_T_111 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_129 = _valid_T_108 & in0valid[2] | _valid_T_128; // @[Fifo4e.scala 96:51]
- wire _valid_T_132 = _valid_T_115 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_133 = _valid_T_129 | _valid_T_132; // @[Fifo4e.scala 97:51]
- wire _valid_T_139 = _valid_T_111 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_140 = _valid_T_108 & in0valid[1] | _valid_T_139; // @[Fifo4e.scala 99:51]
- wire _valid_T_143 = _valid_T_108 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_3 = {_valid_T_122,_valid_T_133,_valid_T_140,_valid_T_143}; // @[Cat.scala 31:58]
- wire _GEN_787 = valid_3[2] ? 1'h0 : valid_3[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_823 = valid_3[1] ? 1'h0 : valid_3[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_841 = valid_3[1] ? 1'h0 : _GEN_787; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_877 = valid_3[0] ? 1'h0 : valid_3[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_895 = valid_3[0] ? 1'h0 : _GEN_823; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_913 = valid_3[0] ? 1'h0 : _GEN_841; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_144 = in0pos == 3'h4; // @[Fifo4e.scala 92:28]
- wire _valid_T_147 = in1pos == 3'h4; // @[Fifo4e.scala 93:28]
- wire _valid_T_149 = in1pos == 3'h4 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_150 = in0pos == 3'h4 & in0valid[3] | _valid_T_149; // @[Fifo4e.scala 92:51]
- wire _valid_T_151 = in2pos == 3'h4; // @[Fifo4e.scala 94:28]
- wire _valid_T_153 = in2pos == 3'h4 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_154 = _valid_T_150 | _valid_T_153; // @[Fifo4e.scala 93:51]
- wire _valid_T_157 = in3pos == 3'h4 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_158 = _valid_T_154 | _valid_T_157; // @[Fifo4e.scala 94:51]
- wire _valid_T_164 = _valid_T_147 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_165 = _valid_T_144 & in0valid[2] | _valid_T_164; // @[Fifo4e.scala 96:51]
- wire _valid_T_168 = _valid_T_151 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_169 = _valid_T_165 | _valid_T_168; // @[Fifo4e.scala 97:51]
- wire _valid_T_175 = _valid_T_147 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_176 = _valid_T_144 & in0valid[1] | _valid_T_175; // @[Fifo4e.scala 99:51]
- wire _valid_T_179 = _valid_T_144 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_4 = {_valid_T_158,_valid_T_169,_valid_T_176,_valid_T_179}; // @[Cat.scala 31:58]
- wire _GEN_1039 = valid_4[2] ? 1'h0 : valid_4[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_1075 = valid_4[1] ? 1'h0 : valid_4[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1093 = valid_4[1] ? 1'h0 : _GEN_1039; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1129 = valid_4[0] ? 1'h0 : valid_4[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1147 = valid_4[0] ? 1'h0 : _GEN_1075; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1165 = valid_4[0] ? 1'h0 : _GEN_1093; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_180 = in0pos == 3'h5; // @[Fifo4e.scala 92:28]
- wire _valid_T_183 = in1pos == 3'h5; // @[Fifo4e.scala 93:28]
- wire _valid_T_185 = in1pos == 3'h5 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_186 = in0pos == 3'h5 & in0valid[3] | _valid_T_185; // @[Fifo4e.scala 92:51]
- wire _valid_T_187 = in2pos == 3'h5; // @[Fifo4e.scala 94:28]
- wire _valid_T_189 = in2pos == 3'h5 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_190 = _valid_T_186 | _valid_T_189; // @[Fifo4e.scala 93:51]
- wire _valid_T_193 = in3pos == 3'h5 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_194 = _valid_T_190 | _valid_T_193; // @[Fifo4e.scala 94:51]
- wire _valid_T_200 = _valid_T_183 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_201 = _valid_T_180 & in0valid[2] | _valid_T_200; // @[Fifo4e.scala 96:51]
- wire _valid_T_204 = _valid_T_187 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_205 = _valid_T_201 | _valid_T_204; // @[Fifo4e.scala 97:51]
- wire _valid_T_211 = _valid_T_183 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_212 = _valid_T_180 & in0valid[1] | _valid_T_211; // @[Fifo4e.scala 99:51]
- wire _valid_T_215 = _valid_T_180 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_5 = {_valid_T_194,_valid_T_205,_valid_T_212,_valid_T_215}; // @[Cat.scala 31:58]
- wire _GEN_1291 = valid_5[2] ? 1'h0 : valid_5[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_1327 = valid_5[1] ? 1'h0 : valid_5[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1345 = valid_5[1] ? 1'h0 : _GEN_1291; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1381 = valid_5[0] ? 1'h0 : valid_5[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1399 = valid_5[0] ? 1'h0 : _GEN_1327; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1417 = valid_5[0] ? 1'h0 : _GEN_1345; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_216 = in0pos == 3'h6; // @[Fifo4e.scala 92:28]
- wire _valid_T_219 = in1pos == 3'h6; // @[Fifo4e.scala 93:28]
- wire _valid_T_221 = in1pos == 3'h6 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_222 = in0pos == 3'h6 & in0valid[3] | _valid_T_221; // @[Fifo4e.scala 92:51]
- wire _valid_T_223 = in2pos == 3'h6; // @[Fifo4e.scala 94:28]
- wire _valid_T_225 = in2pos == 3'h6 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_226 = _valid_T_222 | _valid_T_225; // @[Fifo4e.scala 93:51]
- wire _valid_T_229 = in3pos == 3'h6 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_230 = _valid_T_226 | _valid_T_229; // @[Fifo4e.scala 94:51]
- wire _valid_T_236 = _valid_T_219 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_237 = _valid_T_216 & in0valid[2] | _valid_T_236; // @[Fifo4e.scala 96:51]
- wire _valid_T_240 = _valid_T_223 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_241 = _valid_T_237 | _valid_T_240; // @[Fifo4e.scala 97:51]
- wire _valid_T_247 = _valid_T_219 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_248 = _valid_T_216 & in0valid[1] | _valid_T_247; // @[Fifo4e.scala 99:51]
- wire _valid_T_251 = _valid_T_216 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_6 = {_valid_T_230,_valid_T_241,_valid_T_248,_valid_T_251}; // @[Cat.scala 31:58]
- wire _GEN_1543 = valid_6[2] ? 1'h0 : valid_6[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_1579 = valid_6[1] ? 1'h0 : valid_6[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1597 = valid_6[1] ? 1'h0 : _GEN_1543; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1633 = valid_6[0] ? 1'h0 : valid_6[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1651 = valid_6[0] ? 1'h0 : _GEN_1579; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1669 = valid_6[0] ? 1'h0 : _GEN_1597; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_252 = in0pos == 3'h7; // @[Fifo4e.scala 92:28]
- wire _valid_T_255 = in1pos == 3'h7; // @[Fifo4e.scala 93:28]
- wire _valid_T_257 = in1pos == 3'h7 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_258 = in0pos == 3'h7 & in0valid[3] | _valid_T_257; // @[Fifo4e.scala 92:51]
- wire _valid_T_259 = in2pos == 3'h7; // @[Fifo4e.scala 94:28]
- wire _valid_T_261 = in2pos == 3'h7 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_262 = _valid_T_258 | _valid_T_261; // @[Fifo4e.scala 93:51]
- wire _valid_T_265 = in3pos == 3'h7 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_266 = _valid_T_262 | _valid_T_265; // @[Fifo4e.scala 94:51]
- wire _valid_T_272 = _valid_T_255 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_273 = _valid_T_252 & in0valid[2] | _valid_T_272; // @[Fifo4e.scala 96:51]
- wire _valid_T_276 = _valid_T_259 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_277 = _valid_T_273 | _valid_T_276; // @[Fifo4e.scala 97:51]
- wire _valid_T_283 = _valid_T_255 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_284 = _valid_T_252 & in0valid[1] | _valid_T_283; // @[Fifo4e.scala 99:51]
- wire _valid_T_287 = _valid_T_252 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_7 = {_valid_T_266,_valid_T_277,_valid_T_284,_valid_T_287}; // @[Cat.scala 31:58]
- wire _GEN_1795 = valid_7[2] ? 1'h0 : valid_7[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_1831 = valid_7[1] ? 1'h0 : valid_7[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1849 = valid_7[1] ? 1'h0 : _GEN_1795; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1885 = valid_7[0] ? 1'h0 : valid_7[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1903 = valid_7[0] ? 1'h0 : _GEN_1831; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1921 = valid_7[0] ? 1'h0 : _GEN_1849; // @[Fifo4e.scala 104:23 43:16]
- reg [7:0] active; // @[Fifo4e.scala 118:23]
- wire [7:0] _GEN_0 = {{7'd0}, icount >= 3'h1}; // @[Fifo4e.scala 121:24]
- wire [7:0] _activeSet_T_1 = _GEN_0 << in0pos; // @[Fifo4e.scala 121:24]
- wire [7:0] _GEN_1 = {{7'd0}, icount >= 3'h2}; // @[Fifo4e.scala 121:54]
- wire [7:0] _activeSet_T_3 = _GEN_1 << in1pos; // @[Fifo4e.scala 121:54]
- wire [7:0] _activeSet_T_4 = _activeSet_T_1 | _activeSet_T_3; // @[Fifo4e.scala 121:35]
- wire [7:0] _GEN_2 = {{7'd0}, icount >= 3'h3}; // @[Fifo4e.scala 122:24]
- wire [7:0] _activeSet_T_6 = _GEN_2 << in2pos; // @[Fifo4e.scala 122:24]
- wire [7:0] _activeSet_T_7 = _activeSet_T_4 | _activeSet_T_6; // @[Fifo4e.scala 121:65]
- wire [7:0] _GEN_3 = {{7'd0}, icount >= 3'h4}; // @[Fifo4e.scala 122:54]
- wire [7:0] _activeSet_T_9 = _GEN_3 << in3pos; // @[Fifo4e.scala 122:54]
- wire [7:0] _activeSet_T_10 = _activeSet_T_7 | _activeSet_T_9; // @[Fifo4e.scala 122:35]
- wire [7:0] activeSet = ivalid ? _activeSet_T_10 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _activeClr_T_1 = 8'h1 << outpos; // @[Fifo4e.scala 124:59]
- wire [7:0] activeClr = dec ? _activeClr_T_1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _active_T = active | activeSet; // @[Fifo4e.scala 127:23]
- wire [7:0] _active_T_1 = ~activeClr; // @[Fifo4e.scala 127:38]
- wire [7:0] _active_T_2 = _active_T & _active_T_1; // @[Fifo4e.scala 127:36]
- wire [3:0] _GEN_2015 = {{1'd0}, icount}; // @[Fifo4e.scala 132:33]
- wire [3:0] _io_in_ready_T_1 = 4'h8 - _GEN_2015; // @[Fifo4e.scala 132:33]
- assign mem_tin_op_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_op_io_out_bits_MPORT_data = mem_tin_op[mem_tin_op_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_op_io_entry_0_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_op_io_entry_1_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_op_io_entry_2_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_op_io_entry_3_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_op_io_entry_4_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_op_io_entry_5_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_op_io_entry_6_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_op_io_entry_7_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_MPORT_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_addr = 3'h0;
- assign mem_tin_op_MPORT_mask = 1'h1;
- assign mem_tin_op_MPORT_en = ivalid & valid[0];
- assign mem_tin_op_MPORT_1_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_1_addr = 3'h0;
- assign mem_tin_op_MPORT_1_mask = 1'h1;
- assign mem_tin_op_MPORT_1_en = ivalid & _GEN_135;
- assign mem_tin_op_MPORT_2_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_2_addr = 3'h0;
- assign mem_tin_op_MPORT_2_mask = 1'h1;
- assign mem_tin_op_MPORT_2_en = ivalid & _GEN_153;
- assign mem_tin_op_MPORT_3_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_3_addr = 3'h0;
- assign mem_tin_op_MPORT_3_mask = 1'h1;
- assign mem_tin_op_MPORT_3_en = ivalid & _GEN_171;
- assign mem_tin_op_MPORT_4_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_4_addr = 3'h1;
- assign mem_tin_op_MPORT_4_mask = 1'h1;
- assign mem_tin_op_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_op_MPORT_5_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_5_addr = 3'h1;
- assign mem_tin_op_MPORT_5_mask = 1'h1;
- assign mem_tin_op_MPORT_5_en = ivalid & _GEN_380;
- assign mem_tin_op_MPORT_6_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_6_addr = 3'h1;
- assign mem_tin_op_MPORT_6_mask = 1'h1;
- assign mem_tin_op_MPORT_6_en = ivalid & _GEN_397;
- assign mem_tin_op_MPORT_7_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_7_addr = 3'h1;
- assign mem_tin_op_MPORT_7_mask = 1'h1;
- assign mem_tin_op_MPORT_7_en = ivalid & _GEN_414;
- assign mem_tin_op_MPORT_8_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_8_addr = 3'h2;
- assign mem_tin_op_MPORT_8_mask = 1'h1;
- assign mem_tin_op_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_op_MPORT_9_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_9_addr = 3'h2;
- assign mem_tin_op_MPORT_9_mask = 1'h1;
- assign mem_tin_op_MPORT_9_en = ivalid & _GEN_625;
- assign mem_tin_op_MPORT_10_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_10_addr = 3'h2;
- assign mem_tin_op_MPORT_10_mask = 1'h1;
- assign mem_tin_op_MPORT_10_en = ivalid & _GEN_643;
- assign mem_tin_op_MPORT_11_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_11_addr = 3'h2;
- assign mem_tin_op_MPORT_11_mask = 1'h1;
- assign mem_tin_op_MPORT_11_en = ivalid & _GEN_661;
- assign mem_tin_op_MPORT_12_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_12_addr = 3'h3;
- assign mem_tin_op_MPORT_12_mask = 1'h1;
- assign mem_tin_op_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_op_MPORT_13_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_13_addr = 3'h3;
- assign mem_tin_op_MPORT_13_mask = 1'h1;
- assign mem_tin_op_MPORT_13_en = ivalid & _GEN_877;
- assign mem_tin_op_MPORT_14_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_14_addr = 3'h3;
- assign mem_tin_op_MPORT_14_mask = 1'h1;
- assign mem_tin_op_MPORT_14_en = ivalid & _GEN_895;
- assign mem_tin_op_MPORT_15_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_15_addr = 3'h3;
- assign mem_tin_op_MPORT_15_mask = 1'h1;
- assign mem_tin_op_MPORT_15_en = ivalid & _GEN_913;
- assign mem_tin_op_MPORT_16_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_16_addr = 3'h4;
- assign mem_tin_op_MPORT_16_mask = 1'h1;
- assign mem_tin_op_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_op_MPORT_17_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_17_addr = 3'h4;
- assign mem_tin_op_MPORT_17_mask = 1'h1;
- assign mem_tin_op_MPORT_17_en = ivalid & _GEN_1129;
- assign mem_tin_op_MPORT_18_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_18_addr = 3'h4;
- assign mem_tin_op_MPORT_18_mask = 1'h1;
- assign mem_tin_op_MPORT_18_en = ivalid & _GEN_1147;
- assign mem_tin_op_MPORT_19_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_19_addr = 3'h4;
- assign mem_tin_op_MPORT_19_mask = 1'h1;
- assign mem_tin_op_MPORT_19_en = ivalid & _GEN_1165;
- assign mem_tin_op_MPORT_20_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_20_addr = 3'h5;
- assign mem_tin_op_MPORT_20_mask = 1'h1;
- assign mem_tin_op_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_op_MPORT_21_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_21_addr = 3'h5;
- assign mem_tin_op_MPORT_21_mask = 1'h1;
- assign mem_tin_op_MPORT_21_en = ivalid & _GEN_1381;
- assign mem_tin_op_MPORT_22_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_22_addr = 3'h5;
- assign mem_tin_op_MPORT_22_mask = 1'h1;
- assign mem_tin_op_MPORT_22_en = ivalid & _GEN_1399;
- assign mem_tin_op_MPORT_23_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_23_addr = 3'h5;
- assign mem_tin_op_MPORT_23_mask = 1'h1;
- assign mem_tin_op_MPORT_23_en = ivalid & _GEN_1417;
- assign mem_tin_op_MPORT_24_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_24_addr = 3'h6;
- assign mem_tin_op_MPORT_24_mask = 1'h1;
- assign mem_tin_op_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_op_MPORT_25_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_25_addr = 3'h6;
- assign mem_tin_op_MPORT_25_mask = 1'h1;
- assign mem_tin_op_MPORT_25_en = ivalid & _GEN_1633;
- assign mem_tin_op_MPORT_26_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_26_addr = 3'h6;
- assign mem_tin_op_MPORT_26_mask = 1'h1;
- assign mem_tin_op_MPORT_26_en = ivalid & _GEN_1651;
- assign mem_tin_op_MPORT_27_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_27_addr = 3'h6;
- assign mem_tin_op_MPORT_27_mask = 1'h1;
- assign mem_tin_op_MPORT_27_en = ivalid & _GEN_1669;
- assign mem_tin_op_MPORT_28_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_28_addr = 3'h7;
- assign mem_tin_op_MPORT_28_mask = 1'h1;
- assign mem_tin_op_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_op_MPORT_29_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_29_addr = 3'h7;
- assign mem_tin_op_MPORT_29_mask = 1'h1;
- assign mem_tin_op_MPORT_29_en = ivalid & _GEN_1885;
- assign mem_tin_op_MPORT_30_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_30_addr = 3'h7;
- assign mem_tin_op_MPORT_30_mask = 1'h1;
- assign mem_tin_op_MPORT_30_en = ivalid & _GEN_1903;
- assign mem_tin_op_MPORT_31_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_31_addr = 3'h7;
- assign mem_tin_op_MPORT_31_mask = 1'h1;
- assign mem_tin_op_MPORT_31_en = ivalid & _GEN_1921;
- assign mem_tin_addr_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_addr_io_out_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_addr_io_entry_0_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_addr_io_entry_1_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_addr_io_entry_2_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_addr_io_entry_3_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_addr_io_entry_4_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_addr_io_entry_5_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_addr_io_entry_6_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_addr_io_entry_7_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_MPORT_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_addr = 3'h0;
- assign mem_tin_addr_MPORT_mask = 1'h1;
- assign mem_tin_addr_MPORT_en = ivalid & valid[0];
- assign mem_tin_addr_MPORT_1_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_1_addr = 3'h0;
- assign mem_tin_addr_MPORT_1_mask = 1'h1;
- assign mem_tin_addr_MPORT_1_en = ivalid & _GEN_135;
- assign mem_tin_addr_MPORT_2_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_2_addr = 3'h0;
- assign mem_tin_addr_MPORT_2_mask = 1'h1;
- assign mem_tin_addr_MPORT_2_en = ivalid & _GEN_153;
- assign mem_tin_addr_MPORT_3_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_3_addr = 3'h0;
- assign mem_tin_addr_MPORT_3_mask = 1'h1;
- assign mem_tin_addr_MPORT_3_en = ivalid & _GEN_171;
- assign mem_tin_addr_MPORT_4_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_4_addr = 3'h1;
- assign mem_tin_addr_MPORT_4_mask = 1'h1;
- assign mem_tin_addr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_addr_MPORT_5_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_5_addr = 3'h1;
- assign mem_tin_addr_MPORT_5_mask = 1'h1;
- assign mem_tin_addr_MPORT_5_en = ivalid & _GEN_380;
- assign mem_tin_addr_MPORT_6_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_6_addr = 3'h1;
- assign mem_tin_addr_MPORT_6_mask = 1'h1;
- assign mem_tin_addr_MPORT_6_en = ivalid & _GEN_397;
- assign mem_tin_addr_MPORT_7_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_7_addr = 3'h1;
- assign mem_tin_addr_MPORT_7_mask = 1'h1;
- assign mem_tin_addr_MPORT_7_en = ivalid & _GEN_414;
- assign mem_tin_addr_MPORT_8_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_8_addr = 3'h2;
- assign mem_tin_addr_MPORT_8_mask = 1'h1;
- assign mem_tin_addr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_addr_MPORT_9_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_9_addr = 3'h2;
- assign mem_tin_addr_MPORT_9_mask = 1'h1;
- assign mem_tin_addr_MPORT_9_en = ivalid & _GEN_625;
- assign mem_tin_addr_MPORT_10_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_10_addr = 3'h2;
- assign mem_tin_addr_MPORT_10_mask = 1'h1;
- assign mem_tin_addr_MPORT_10_en = ivalid & _GEN_643;
- assign mem_tin_addr_MPORT_11_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_11_addr = 3'h2;
- assign mem_tin_addr_MPORT_11_mask = 1'h1;
- assign mem_tin_addr_MPORT_11_en = ivalid & _GEN_661;
- assign mem_tin_addr_MPORT_12_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_12_addr = 3'h3;
- assign mem_tin_addr_MPORT_12_mask = 1'h1;
- assign mem_tin_addr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_addr_MPORT_13_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_13_addr = 3'h3;
- assign mem_tin_addr_MPORT_13_mask = 1'h1;
- assign mem_tin_addr_MPORT_13_en = ivalid & _GEN_877;
- assign mem_tin_addr_MPORT_14_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_14_addr = 3'h3;
- assign mem_tin_addr_MPORT_14_mask = 1'h1;
- assign mem_tin_addr_MPORT_14_en = ivalid & _GEN_895;
- assign mem_tin_addr_MPORT_15_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_15_addr = 3'h3;
- assign mem_tin_addr_MPORT_15_mask = 1'h1;
- assign mem_tin_addr_MPORT_15_en = ivalid & _GEN_913;
- assign mem_tin_addr_MPORT_16_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_16_addr = 3'h4;
- assign mem_tin_addr_MPORT_16_mask = 1'h1;
- assign mem_tin_addr_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_addr_MPORT_17_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_17_addr = 3'h4;
- assign mem_tin_addr_MPORT_17_mask = 1'h1;
- assign mem_tin_addr_MPORT_17_en = ivalid & _GEN_1129;
- assign mem_tin_addr_MPORT_18_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_18_addr = 3'h4;
- assign mem_tin_addr_MPORT_18_mask = 1'h1;
- assign mem_tin_addr_MPORT_18_en = ivalid & _GEN_1147;
- assign mem_tin_addr_MPORT_19_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_19_addr = 3'h4;
- assign mem_tin_addr_MPORT_19_mask = 1'h1;
- assign mem_tin_addr_MPORT_19_en = ivalid & _GEN_1165;
- assign mem_tin_addr_MPORT_20_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_20_addr = 3'h5;
- assign mem_tin_addr_MPORT_20_mask = 1'h1;
- assign mem_tin_addr_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_addr_MPORT_21_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_21_addr = 3'h5;
- assign mem_tin_addr_MPORT_21_mask = 1'h1;
- assign mem_tin_addr_MPORT_21_en = ivalid & _GEN_1381;
- assign mem_tin_addr_MPORT_22_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_22_addr = 3'h5;
- assign mem_tin_addr_MPORT_22_mask = 1'h1;
- assign mem_tin_addr_MPORT_22_en = ivalid & _GEN_1399;
- assign mem_tin_addr_MPORT_23_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_23_addr = 3'h5;
- assign mem_tin_addr_MPORT_23_mask = 1'h1;
- assign mem_tin_addr_MPORT_23_en = ivalid & _GEN_1417;
- assign mem_tin_addr_MPORT_24_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_24_addr = 3'h6;
- assign mem_tin_addr_MPORT_24_mask = 1'h1;
- assign mem_tin_addr_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_addr_MPORT_25_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_25_addr = 3'h6;
- assign mem_tin_addr_MPORT_25_mask = 1'h1;
- assign mem_tin_addr_MPORT_25_en = ivalid & _GEN_1633;
- assign mem_tin_addr_MPORT_26_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_26_addr = 3'h6;
- assign mem_tin_addr_MPORT_26_mask = 1'h1;
- assign mem_tin_addr_MPORT_26_en = ivalid & _GEN_1651;
- assign mem_tin_addr_MPORT_27_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_27_addr = 3'h6;
- assign mem_tin_addr_MPORT_27_mask = 1'h1;
- assign mem_tin_addr_MPORT_27_en = ivalid & _GEN_1669;
- assign mem_tin_addr_MPORT_28_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_28_addr = 3'h7;
- assign mem_tin_addr_MPORT_28_mask = 1'h1;
- assign mem_tin_addr_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_addr_MPORT_29_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_29_addr = 3'h7;
- assign mem_tin_addr_MPORT_29_mask = 1'h1;
- assign mem_tin_addr_MPORT_29_en = ivalid & _GEN_1885;
- assign mem_tin_addr_MPORT_30_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_30_addr = 3'h7;
- assign mem_tin_addr_MPORT_30_mask = 1'h1;
- assign mem_tin_addr_MPORT_30_en = ivalid & _GEN_1903;
- assign mem_tin_addr_MPORT_31_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_31_addr = 3'h7;
- assign mem_tin_addr_MPORT_31_mask = 1'h1;
- assign mem_tin_addr_MPORT_31_en = ivalid & _GEN_1921;
- assign mem_tin_offset_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_offset_io_out_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_offset_io_entry_0_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_offset_io_entry_1_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_offset_io_entry_2_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_offset_io_entry_3_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_offset_io_entry_4_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_offset_io_entry_5_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_offset_io_entry_6_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_offset_io_entry_7_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_MPORT_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_addr = 3'h0;
- assign mem_tin_offset_MPORT_mask = 1'h1;
- assign mem_tin_offset_MPORT_en = ivalid & valid[0];
- assign mem_tin_offset_MPORT_1_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_1_addr = 3'h0;
- assign mem_tin_offset_MPORT_1_mask = 1'h1;
- assign mem_tin_offset_MPORT_1_en = ivalid & _GEN_135;
- assign mem_tin_offset_MPORT_2_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_2_addr = 3'h0;
- assign mem_tin_offset_MPORT_2_mask = 1'h1;
- assign mem_tin_offset_MPORT_2_en = ivalid & _GEN_153;
- assign mem_tin_offset_MPORT_3_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_3_addr = 3'h0;
- assign mem_tin_offset_MPORT_3_mask = 1'h1;
- assign mem_tin_offset_MPORT_3_en = ivalid & _GEN_171;
- assign mem_tin_offset_MPORT_4_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_4_addr = 3'h1;
- assign mem_tin_offset_MPORT_4_mask = 1'h1;
- assign mem_tin_offset_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_offset_MPORT_5_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_5_addr = 3'h1;
- assign mem_tin_offset_MPORT_5_mask = 1'h1;
- assign mem_tin_offset_MPORT_5_en = ivalid & _GEN_380;
- assign mem_tin_offset_MPORT_6_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_6_addr = 3'h1;
- assign mem_tin_offset_MPORT_6_mask = 1'h1;
- assign mem_tin_offset_MPORT_6_en = ivalid & _GEN_397;
- assign mem_tin_offset_MPORT_7_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_7_addr = 3'h1;
- assign mem_tin_offset_MPORT_7_mask = 1'h1;
- assign mem_tin_offset_MPORT_7_en = ivalid & _GEN_414;
- assign mem_tin_offset_MPORT_8_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_8_addr = 3'h2;
- assign mem_tin_offset_MPORT_8_mask = 1'h1;
- assign mem_tin_offset_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_offset_MPORT_9_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_9_addr = 3'h2;
- assign mem_tin_offset_MPORT_9_mask = 1'h1;
- assign mem_tin_offset_MPORT_9_en = ivalid & _GEN_625;
- assign mem_tin_offset_MPORT_10_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_10_addr = 3'h2;
- assign mem_tin_offset_MPORT_10_mask = 1'h1;
- assign mem_tin_offset_MPORT_10_en = ivalid & _GEN_643;
- assign mem_tin_offset_MPORT_11_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_11_addr = 3'h2;
- assign mem_tin_offset_MPORT_11_mask = 1'h1;
- assign mem_tin_offset_MPORT_11_en = ivalid & _GEN_661;
- assign mem_tin_offset_MPORT_12_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_12_addr = 3'h3;
- assign mem_tin_offset_MPORT_12_mask = 1'h1;
- assign mem_tin_offset_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_offset_MPORT_13_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_13_addr = 3'h3;
- assign mem_tin_offset_MPORT_13_mask = 1'h1;
- assign mem_tin_offset_MPORT_13_en = ivalid & _GEN_877;
- assign mem_tin_offset_MPORT_14_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_14_addr = 3'h3;
- assign mem_tin_offset_MPORT_14_mask = 1'h1;
- assign mem_tin_offset_MPORT_14_en = ivalid & _GEN_895;
- assign mem_tin_offset_MPORT_15_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_15_addr = 3'h3;
- assign mem_tin_offset_MPORT_15_mask = 1'h1;
- assign mem_tin_offset_MPORT_15_en = ivalid & _GEN_913;
- assign mem_tin_offset_MPORT_16_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_16_addr = 3'h4;
- assign mem_tin_offset_MPORT_16_mask = 1'h1;
- assign mem_tin_offset_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_offset_MPORT_17_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_17_addr = 3'h4;
- assign mem_tin_offset_MPORT_17_mask = 1'h1;
- assign mem_tin_offset_MPORT_17_en = ivalid & _GEN_1129;
- assign mem_tin_offset_MPORT_18_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_18_addr = 3'h4;
- assign mem_tin_offset_MPORT_18_mask = 1'h1;
- assign mem_tin_offset_MPORT_18_en = ivalid & _GEN_1147;
- assign mem_tin_offset_MPORT_19_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_19_addr = 3'h4;
- assign mem_tin_offset_MPORT_19_mask = 1'h1;
- assign mem_tin_offset_MPORT_19_en = ivalid & _GEN_1165;
- assign mem_tin_offset_MPORT_20_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_20_addr = 3'h5;
- assign mem_tin_offset_MPORT_20_mask = 1'h1;
- assign mem_tin_offset_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_offset_MPORT_21_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_21_addr = 3'h5;
- assign mem_tin_offset_MPORT_21_mask = 1'h1;
- assign mem_tin_offset_MPORT_21_en = ivalid & _GEN_1381;
- assign mem_tin_offset_MPORT_22_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_22_addr = 3'h5;
- assign mem_tin_offset_MPORT_22_mask = 1'h1;
- assign mem_tin_offset_MPORT_22_en = ivalid & _GEN_1399;
- assign mem_tin_offset_MPORT_23_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_23_addr = 3'h5;
- assign mem_tin_offset_MPORT_23_mask = 1'h1;
- assign mem_tin_offset_MPORT_23_en = ivalid & _GEN_1417;
- assign mem_tin_offset_MPORT_24_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_24_addr = 3'h6;
- assign mem_tin_offset_MPORT_24_mask = 1'h1;
- assign mem_tin_offset_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_offset_MPORT_25_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_25_addr = 3'h6;
- assign mem_tin_offset_MPORT_25_mask = 1'h1;
- assign mem_tin_offset_MPORT_25_en = ivalid & _GEN_1633;
- assign mem_tin_offset_MPORT_26_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_26_addr = 3'h6;
- assign mem_tin_offset_MPORT_26_mask = 1'h1;
- assign mem_tin_offset_MPORT_26_en = ivalid & _GEN_1651;
- assign mem_tin_offset_MPORT_27_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_27_addr = 3'h6;
- assign mem_tin_offset_MPORT_27_mask = 1'h1;
- assign mem_tin_offset_MPORT_27_en = ivalid & _GEN_1669;
- assign mem_tin_offset_MPORT_28_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_28_addr = 3'h7;
- assign mem_tin_offset_MPORT_28_mask = 1'h1;
- assign mem_tin_offset_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_offset_MPORT_29_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_29_addr = 3'h7;
- assign mem_tin_offset_MPORT_29_mask = 1'h1;
- assign mem_tin_offset_MPORT_29_en = ivalid & _GEN_1885;
- assign mem_tin_offset_MPORT_30_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_30_addr = 3'h7;
- assign mem_tin_offset_MPORT_30_mask = 1'h1;
- assign mem_tin_offset_MPORT_30_en = ivalid & _GEN_1903;
- assign mem_tin_offset_MPORT_31_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_31_addr = 3'h7;
- assign mem_tin_offset_MPORT_31_mask = 1'h1;
- assign mem_tin_offset_MPORT_31_en = ivalid & _GEN_1921;
- assign mem_tin_remain_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_remain_io_out_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_remain_io_entry_0_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_remain_io_entry_1_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_remain_io_entry_2_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_remain_io_entry_3_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_remain_io_entry_4_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_remain_io_entry_5_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_remain_io_entry_6_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_remain_io_entry_7_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_MPORT_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_addr = 3'h0;
- assign mem_tin_remain_MPORT_mask = 1'h1;
- assign mem_tin_remain_MPORT_en = ivalid & valid[0];
- assign mem_tin_remain_MPORT_1_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_1_addr = 3'h0;
- assign mem_tin_remain_MPORT_1_mask = 1'h1;
- assign mem_tin_remain_MPORT_1_en = ivalid & _GEN_135;
- assign mem_tin_remain_MPORT_2_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_2_addr = 3'h0;
- assign mem_tin_remain_MPORT_2_mask = 1'h1;
- assign mem_tin_remain_MPORT_2_en = ivalid & _GEN_153;
- assign mem_tin_remain_MPORT_3_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_3_addr = 3'h0;
- assign mem_tin_remain_MPORT_3_mask = 1'h1;
- assign mem_tin_remain_MPORT_3_en = ivalid & _GEN_171;
- assign mem_tin_remain_MPORT_4_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_4_addr = 3'h1;
- assign mem_tin_remain_MPORT_4_mask = 1'h1;
- assign mem_tin_remain_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_remain_MPORT_5_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_5_addr = 3'h1;
- assign mem_tin_remain_MPORT_5_mask = 1'h1;
- assign mem_tin_remain_MPORT_5_en = ivalid & _GEN_380;
- assign mem_tin_remain_MPORT_6_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_6_addr = 3'h1;
- assign mem_tin_remain_MPORT_6_mask = 1'h1;
- assign mem_tin_remain_MPORT_6_en = ivalid & _GEN_397;
- assign mem_tin_remain_MPORT_7_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_7_addr = 3'h1;
- assign mem_tin_remain_MPORT_7_mask = 1'h1;
- assign mem_tin_remain_MPORT_7_en = ivalid & _GEN_414;
- assign mem_tin_remain_MPORT_8_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_8_addr = 3'h2;
- assign mem_tin_remain_MPORT_8_mask = 1'h1;
- assign mem_tin_remain_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_remain_MPORT_9_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_9_addr = 3'h2;
- assign mem_tin_remain_MPORT_9_mask = 1'h1;
- assign mem_tin_remain_MPORT_9_en = ivalid & _GEN_625;
- assign mem_tin_remain_MPORT_10_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_10_addr = 3'h2;
- assign mem_tin_remain_MPORT_10_mask = 1'h1;
- assign mem_tin_remain_MPORT_10_en = ivalid & _GEN_643;
- assign mem_tin_remain_MPORT_11_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_11_addr = 3'h2;
- assign mem_tin_remain_MPORT_11_mask = 1'h1;
- assign mem_tin_remain_MPORT_11_en = ivalid & _GEN_661;
- assign mem_tin_remain_MPORT_12_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_12_addr = 3'h3;
- assign mem_tin_remain_MPORT_12_mask = 1'h1;
- assign mem_tin_remain_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_remain_MPORT_13_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_13_addr = 3'h3;
- assign mem_tin_remain_MPORT_13_mask = 1'h1;
- assign mem_tin_remain_MPORT_13_en = ivalid & _GEN_877;
- assign mem_tin_remain_MPORT_14_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_14_addr = 3'h3;
- assign mem_tin_remain_MPORT_14_mask = 1'h1;
- assign mem_tin_remain_MPORT_14_en = ivalid & _GEN_895;
- assign mem_tin_remain_MPORT_15_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_15_addr = 3'h3;
- assign mem_tin_remain_MPORT_15_mask = 1'h1;
- assign mem_tin_remain_MPORT_15_en = ivalid & _GEN_913;
- assign mem_tin_remain_MPORT_16_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_16_addr = 3'h4;
- assign mem_tin_remain_MPORT_16_mask = 1'h1;
- assign mem_tin_remain_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_remain_MPORT_17_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_17_addr = 3'h4;
- assign mem_tin_remain_MPORT_17_mask = 1'h1;
- assign mem_tin_remain_MPORT_17_en = ivalid & _GEN_1129;
- assign mem_tin_remain_MPORT_18_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_18_addr = 3'h4;
- assign mem_tin_remain_MPORT_18_mask = 1'h1;
- assign mem_tin_remain_MPORT_18_en = ivalid & _GEN_1147;
- assign mem_tin_remain_MPORT_19_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_19_addr = 3'h4;
- assign mem_tin_remain_MPORT_19_mask = 1'h1;
- assign mem_tin_remain_MPORT_19_en = ivalid & _GEN_1165;
- assign mem_tin_remain_MPORT_20_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_20_addr = 3'h5;
- assign mem_tin_remain_MPORT_20_mask = 1'h1;
- assign mem_tin_remain_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_remain_MPORT_21_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_21_addr = 3'h5;
- assign mem_tin_remain_MPORT_21_mask = 1'h1;
- assign mem_tin_remain_MPORT_21_en = ivalid & _GEN_1381;
- assign mem_tin_remain_MPORT_22_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_22_addr = 3'h5;
- assign mem_tin_remain_MPORT_22_mask = 1'h1;
- assign mem_tin_remain_MPORT_22_en = ivalid & _GEN_1399;
- assign mem_tin_remain_MPORT_23_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_23_addr = 3'h5;
- assign mem_tin_remain_MPORT_23_mask = 1'h1;
- assign mem_tin_remain_MPORT_23_en = ivalid & _GEN_1417;
- assign mem_tin_remain_MPORT_24_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_24_addr = 3'h6;
- assign mem_tin_remain_MPORT_24_mask = 1'h1;
- assign mem_tin_remain_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_remain_MPORT_25_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_25_addr = 3'h6;
- assign mem_tin_remain_MPORT_25_mask = 1'h1;
- assign mem_tin_remain_MPORT_25_en = ivalid & _GEN_1633;
- assign mem_tin_remain_MPORT_26_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_26_addr = 3'h6;
- assign mem_tin_remain_MPORT_26_mask = 1'h1;
- assign mem_tin_remain_MPORT_26_en = ivalid & _GEN_1651;
- assign mem_tin_remain_MPORT_27_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_27_addr = 3'h6;
- assign mem_tin_remain_MPORT_27_mask = 1'h1;
- assign mem_tin_remain_MPORT_27_en = ivalid & _GEN_1669;
- assign mem_tin_remain_MPORT_28_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_28_addr = 3'h7;
- assign mem_tin_remain_MPORT_28_mask = 1'h1;
- assign mem_tin_remain_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_remain_MPORT_29_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_29_addr = 3'h7;
- assign mem_tin_remain_MPORT_29_mask = 1'h1;
- assign mem_tin_remain_MPORT_29_en = ivalid & _GEN_1885;
- assign mem_tin_remain_MPORT_30_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_30_addr = 3'h7;
- assign mem_tin_remain_MPORT_30_mask = 1'h1;
- assign mem_tin_remain_MPORT_30_en = ivalid & _GEN_1903;
- assign mem_tin_remain_MPORT_31_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_31_addr = 3'h7;
- assign mem_tin_remain_MPORT_31_mask = 1'h1;
- assign mem_tin_remain_MPORT_31_en = ivalid & _GEN_1921;
- assign mem_tin_vd_addr_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vd_addr_io_out_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vd_addr_io_entry_0_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vd_addr_io_entry_1_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vd_addr_io_entry_2_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vd_addr_io_entry_3_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vd_addr_io_entry_4_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vd_addr_io_entry_5_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vd_addr_io_entry_6_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vd_addr_io_entry_7_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_MPORT_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_addr = 3'h0;
- assign mem_tin_vd_addr_MPORT_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_en = ivalid & valid[0];
- assign mem_tin_vd_addr_MPORT_1_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_1_addr = 3'h0;
- assign mem_tin_vd_addr_MPORT_1_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_1_en = ivalid & _GEN_135;
- assign mem_tin_vd_addr_MPORT_2_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_2_addr = 3'h0;
- assign mem_tin_vd_addr_MPORT_2_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_2_en = ivalid & _GEN_153;
- assign mem_tin_vd_addr_MPORT_3_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_3_addr = 3'h0;
- assign mem_tin_vd_addr_MPORT_3_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_3_en = ivalid & _GEN_171;
- assign mem_tin_vd_addr_MPORT_4_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_4_addr = 3'h1;
- assign mem_tin_vd_addr_MPORT_4_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vd_addr_MPORT_5_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_5_addr = 3'h1;
- assign mem_tin_vd_addr_MPORT_5_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_5_en = ivalid & _GEN_380;
- assign mem_tin_vd_addr_MPORT_6_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_6_addr = 3'h1;
- assign mem_tin_vd_addr_MPORT_6_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_6_en = ivalid & _GEN_397;
- assign mem_tin_vd_addr_MPORT_7_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_7_addr = 3'h1;
- assign mem_tin_vd_addr_MPORT_7_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_7_en = ivalid & _GEN_414;
- assign mem_tin_vd_addr_MPORT_8_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_8_addr = 3'h2;
- assign mem_tin_vd_addr_MPORT_8_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vd_addr_MPORT_9_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_9_addr = 3'h2;
- assign mem_tin_vd_addr_MPORT_9_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_9_en = ivalid & _GEN_625;
- assign mem_tin_vd_addr_MPORT_10_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_10_addr = 3'h2;
- assign mem_tin_vd_addr_MPORT_10_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_10_en = ivalid & _GEN_643;
- assign mem_tin_vd_addr_MPORT_11_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_11_addr = 3'h2;
- assign mem_tin_vd_addr_MPORT_11_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_11_en = ivalid & _GEN_661;
- assign mem_tin_vd_addr_MPORT_12_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_12_addr = 3'h3;
- assign mem_tin_vd_addr_MPORT_12_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vd_addr_MPORT_13_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_13_addr = 3'h3;
- assign mem_tin_vd_addr_MPORT_13_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_13_en = ivalid & _GEN_877;
- assign mem_tin_vd_addr_MPORT_14_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_14_addr = 3'h3;
- assign mem_tin_vd_addr_MPORT_14_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_14_en = ivalid & _GEN_895;
- assign mem_tin_vd_addr_MPORT_15_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_15_addr = 3'h3;
- assign mem_tin_vd_addr_MPORT_15_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_15_en = ivalid & _GEN_913;
- assign mem_tin_vd_addr_MPORT_16_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_16_addr = 3'h4;
- assign mem_tin_vd_addr_MPORT_16_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vd_addr_MPORT_17_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_17_addr = 3'h4;
- assign mem_tin_vd_addr_MPORT_17_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_17_en = ivalid & _GEN_1129;
- assign mem_tin_vd_addr_MPORT_18_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_18_addr = 3'h4;
- assign mem_tin_vd_addr_MPORT_18_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_18_en = ivalid & _GEN_1147;
- assign mem_tin_vd_addr_MPORT_19_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_19_addr = 3'h4;
- assign mem_tin_vd_addr_MPORT_19_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_19_en = ivalid & _GEN_1165;
- assign mem_tin_vd_addr_MPORT_20_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_20_addr = 3'h5;
- assign mem_tin_vd_addr_MPORT_20_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vd_addr_MPORT_21_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_21_addr = 3'h5;
- assign mem_tin_vd_addr_MPORT_21_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_21_en = ivalid & _GEN_1381;
- assign mem_tin_vd_addr_MPORT_22_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_22_addr = 3'h5;
- assign mem_tin_vd_addr_MPORT_22_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_22_en = ivalid & _GEN_1399;
- assign mem_tin_vd_addr_MPORT_23_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_23_addr = 3'h5;
- assign mem_tin_vd_addr_MPORT_23_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_23_en = ivalid & _GEN_1417;
- assign mem_tin_vd_addr_MPORT_24_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_24_addr = 3'h6;
- assign mem_tin_vd_addr_MPORT_24_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vd_addr_MPORT_25_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_25_addr = 3'h6;
- assign mem_tin_vd_addr_MPORT_25_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_25_en = ivalid & _GEN_1633;
- assign mem_tin_vd_addr_MPORT_26_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_26_addr = 3'h6;
- assign mem_tin_vd_addr_MPORT_26_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_26_en = ivalid & _GEN_1651;
- assign mem_tin_vd_addr_MPORT_27_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_27_addr = 3'h6;
- assign mem_tin_vd_addr_MPORT_27_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_27_en = ivalid & _GEN_1669;
- assign mem_tin_vd_addr_MPORT_28_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_28_addr = 3'h7;
- assign mem_tin_vd_addr_MPORT_28_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vd_addr_MPORT_29_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_29_addr = 3'h7;
- assign mem_tin_vd_addr_MPORT_29_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_29_en = ivalid & _GEN_1885;
- assign mem_tin_vd_addr_MPORT_30_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_30_addr = 3'h7;
- assign mem_tin_vd_addr_MPORT_30_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_30_en = ivalid & _GEN_1903;
- assign mem_tin_vd_addr_MPORT_31_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_31_addr = 3'h7;
- assign mem_tin_vd_addr_MPORT_31_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_31_en = ivalid & _GEN_1921;
- assign mem_tin_vs_valid_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vs_valid_io_out_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vs_valid_io_entry_0_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vs_valid_io_entry_1_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vs_valid_io_entry_2_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vs_valid_io_entry_3_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vs_valid_io_entry_4_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vs_valid_io_entry_5_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vs_valid_io_entry_6_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vs_valid_io_entry_7_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_MPORT_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_addr = 3'h0;
- assign mem_tin_vs_valid_MPORT_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_en = ivalid & valid[0];
- assign mem_tin_vs_valid_MPORT_1_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_1_addr = 3'h0;
- assign mem_tin_vs_valid_MPORT_1_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_1_en = ivalid & _GEN_135;
- assign mem_tin_vs_valid_MPORT_2_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_2_addr = 3'h0;
- assign mem_tin_vs_valid_MPORT_2_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_2_en = ivalid & _GEN_153;
- assign mem_tin_vs_valid_MPORT_3_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_3_addr = 3'h0;
- assign mem_tin_vs_valid_MPORT_3_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_3_en = ivalid & _GEN_171;
- assign mem_tin_vs_valid_MPORT_4_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_4_addr = 3'h1;
- assign mem_tin_vs_valid_MPORT_4_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vs_valid_MPORT_5_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_5_addr = 3'h1;
- assign mem_tin_vs_valid_MPORT_5_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_5_en = ivalid & _GEN_380;
- assign mem_tin_vs_valid_MPORT_6_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_6_addr = 3'h1;
- assign mem_tin_vs_valid_MPORT_6_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_6_en = ivalid & _GEN_397;
- assign mem_tin_vs_valid_MPORT_7_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_7_addr = 3'h1;
- assign mem_tin_vs_valid_MPORT_7_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_7_en = ivalid & _GEN_414;
- assign mem_tin_vs_valid_MPORT_8_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_8_addr = 3'h2;
- assign mem_tin_vs_valid_MPORT_8_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vs_valid_MPORT_9_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_9_addr = 3'h2;
- assign mem_tin_vs_valid_MPORT_9_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_9_en = ivalid & _GEN_625;
- assign mem_tin_vs_valid_MPORT_10_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_10_addr = 3'h2;
- assign mem_tin_vs_valid_MPORT_10_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_10_en = ivalid & _GEN_643;
- assign mem_tin_vs_valid_MPORT_11_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_11_addr = 3'h2;
- assign mem_tin_vs_valid_MPORT_11_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_11_en = ivalid & _GEN_661;
- assign mem_tin_vs_valid_MPORT_12_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_12_addr = 3'h3;
- assign mem_tin_vs_valid_MPORT_12_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vs_valid_MPORT_13_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_13_addr = 3'h3;
- assign mem_tin_vs_valid_MPORT_13_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_13_en = ivalid & _GEN_877;
- assign mem_tin_vs_valid_MPORT_14_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_14_addr = 3'h3;
- assign mem_tin_vs_valid_MPORT_14_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_14_en = ivalid & _GEN_895;
- assign mem_tin_vs_valid_MPORT_15_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_15_addr = 3'h3;
- assign mem_tin_vs_valid_MPORT_15_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_15_en = ivalid & _GEN_913;
- assign mem_tin_vs_valid_MPORT_16_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_16_addr = 3'h4;
- assign mem_tin_vs_valid_MPORT_16_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vs_valid_MPORT_17_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_17_addr = 3'h4;
- assign mem_tin_vs_valid_MPORT_17_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_17_en = ivalid & _GEN_1129;
- assign mem_tin_vs_valid_MPORT_18_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_18_addr = 3'h4;
- assign mem_tin_vs_valid_MPORT_18_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_18_en = ivalid & _GEN_1147;
- assign mem_tin_vs_valid_MPORT_19_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_19_addr = 3'h4;
- assign mem_tin_vs_valid_MPORT_19_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_19_en = ivalid & _GEN_1165;
- assign mem_tin_vs_valid_MPORT_20_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_20_addr = 3'h5;
- assign mem_tin_vs_valid_MPORT_20_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vs_valid_MPORT_21_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_21_addr = 3'h5;
- assign mem_tin_vs_valid_MPORT_21_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_21_en = ivalid & _GEN_1381;
- assign mem_tin_vs_valid_MPORT_22_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_22_addr = 3'h5;
- assign mem_tin_vs_valid_MPORT_22_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_22_en = ivalid & _GEN_1399;
- assign mem_tin_vs_valid_MPORT_23_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_23_addr = 3'h5;
- assign mem_tin_vs_valid_MPORT_23_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_23_en = ivalid & _GEN_1417;
- assign mem_tin_vs_valid_MPORT_24_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_24_addr = 3'h6;
- assign mem_tin_vs_valid_MPORT_24_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vs_valid_MPORT_25_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_25_addr = 3'h6;
- assign mem_tin_vs_valid_MPORT_25_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_25_en = ivalid & _GEN_1633;
- assign mem_tin_vs_valid_MPORT_26_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_26_addr = 3'h6;
- assign mem_tin_vs_valid_MPORT_26_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_26_en = ivalid & _GEN_1651;
- assign mem_tin_vs_valid_MPORT_27_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_27_addr = 3'h6;
- assign mem_tin_vs_valid_MPORT_27_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_27_en = ivalid & _GEN_1669;
- assign mem_tin_vs_valid_MPORT_28_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_28_addr = 3'h7;
- assign mem_tin_vs_valid_MPORT_28_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vs_valid_MPORT_29_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_29_addr = 3'h7;
- assign mem_tin_vs_valid_MPORT_29_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_29_en = ivalid & _GEN_1885;
- assign mem_tin_vs_valid_MPORT_30_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_30_addr = 3'h7;
- assign mem_tin_vs_valid_MPORT_30_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_30_en = ivalid & _GEN_1903;
- assign mem_tin_vs_valid_MPORT_31_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_31_addr = 3'h7;
- assign mem_tin_vs_valid_MPORT_31_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_31_en = ivalid & _GEN_1921;
- assign mem_tin_vs_addr_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vs_addr_io_out_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vs_addr_io_entry_0_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vs_addr_io_entry_1_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vs_addr_io_entry_2_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vs_addr_io_entry_3_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vs_addr_io_entry_4_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vs_addr_io_entry_5_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vs_addr_io_entry_6_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vs_addr_io_entry_7_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_MPORT_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_addr = 3'h0;
- assign mem_tin_vs_addr_MPORT_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_en = ivalid & valid[0];
- assign mem_tin_vs_addr_MPORT_1_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_1_addr = 3'h0;
- assign mem_tin_vs_addr_MPORT_1_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_1_en = ivalid & _GEN_135;
- assign mem_tin_vs_addr_MPORT_2_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_2_addr = 3'h0;
- assign mem_tin_vs_addr_MPORT_2_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_2_en = ivalid & _GEN_153;
- assign mem_tin_vs_addr_MPORT_3_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_3_addr = 3'h0;
- assign mem_tin_vs_addr_MPORT_3_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_3_en = ivalid & _GEN_171;
- assign mem_tin_vs_addr_MPORT_4_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_4_addr = 3'h1;
- assign mem_tin_vs_addr_MPORT_4_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vs_addr_MPORT_5_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_5_addr = 3'h1;
- assign mem_tin_vs_addr_MPORT_5_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_5_en = ivalid & _GEN_380;
- assign mem_tin_vs_addr_MPORT_6_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_6_addr = 3'h1;
- assign mem_tin_vs_addr_MPORT_6_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_6_en = ivalid & _GEN_397;
- assign mem_tin_vs_addr_MPORT_7_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_7_addr = 3'h1;
- assign mem_tin_vs_addr_MPORT_7_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_7_en = ivalid & _GEN_414;
- assign mem_tin_vs_addr_MPORT_8_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_8_addr = 3'h2;
- assign mem_tin_vs_addr_MPORT_8_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vs_addr_MPORT_9_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_9_addr = 3'h2;
- assign mem_tin_vs_addr_MPORT_9_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_9_en = ivalid & _GEN_625;
- assign mem_tin_vs_addr_MPORT_10_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_10_addr = 3'h2;
- assign mem_tin_vs_addr_MPORT_10_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_10_en = ivalid & _GEN_643;
- assign mem_tin_vs_addr_MPORT_11_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_11_addr = 3'h2;
- assign mem_tin_vs_addr_MPORT_11_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_11_en = ivalid & _GEN_661;
- assign mem_tin_vs_addr_MPORT_12_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_12_addr = 3'h3;
- assign mem_tin_vs_addr_MPORT_12_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vs_addr_MPORT_13_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_13_addr = 3'h3;
- assign mem_tin_vs_addr_MPORT_13_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_13_en = ivalid & _GEN_877;
- assign mem_tin_vs_addr_MPORT_14_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_14_addr = 3'h3;
- assign mem_tin_vs_addr_MPORT_14_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_14_en = ivalid & _GEN_895;
- assign mem_tin_vs_addr_MPORT_15_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_15_addr = 3'h3;
- assign mem_tin_vs_addr_MPORT_15_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_15_en = ivalid & _GEN_913;
- assign mem_tin_vs_addr_MPORT_16_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_16_addr = 3'h4;
- assign mem_tin_vs_addr_MPORT_16_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vs_addr_MPORT_17_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_17_addr = 3'h4;
- assign mem_tin_vs_addr_MPORT_17_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_17_en = ivalid & _GEN_1129;
- assign mem_tin_vs_addr_MPORT_18_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_18_addr = 3'h4;
- assign mem_tin_vs_addr_MPORT_18_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_18_en = ivalid & _GEN_1147;
- assign mem_tin_vs_addr_MPORT_19_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_19_addr = 3'h4;
- assign mem_tin_vs_addr_MPORT_19_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_19_en = ivalid & _GEN_1165;
- assign mem_tin_vs_addr_MPORT_20_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_20_addr = 3'h5;
- assign mem_tin_vs_addr_MPORT_20_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vs_addr_MPORT_21_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_21_addr = 3'h5;
- assign mem_tin_vs_addr_MPORT_21_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_21_en = ivalid & _GEN_1381;
- assign mem_tin_vs_addr_MPORT_22_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_22_addr = 3'h5;
- assign mem_tin_vs_addr_MPORT_22_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_22_en = ivalid & _GEN_1399;
- assign mem_tin_vs_addr_MPORT_23_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_23_addr = 3'h5;
- assign mem_tin_vs_addr_MPORT_23_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_23_en = ivalid & _GEN_1417;
- assign mem_tin_vs_addr_MPORT_24_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_24_addr = 3'h6;
- assign mem_tin_vs_addr_MPORT_24_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vs_addr_MPORT_25_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_25_addr = 3'h6;
- assign mem_tin_vs_addr_MPORT_25_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_25_en = ivalid & _GEN_1633;
- assign mem_tin_vs_addr_MPORT_26_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_26_addr = 3'h6;
- assign mem_tin_vs_addr_MPORT_26_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_26_en = ivalid & _GEN_1651;
- assign mem_tin_vs_addr_MPORT_27_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_27_addr = 3'h6;
- assign mem_tin_vs_addr_MPORT_27_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_27_en = ivalid & _GEN_1669;
- assign mem_tin_vs_addr_MPORT_28_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_28_addr = 3'h7;
- assign mem_tin_vs_addr_MPORT_28_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vs_addr_MPORT_29_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_29_addr = 3'h7;
- assign mem_tin_vs_addr_MPORT_29_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_29_en = ivalid & _GEN_1885;
- assign mem_tin_vs_addr_MPORT_30_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_30_addr = 3'h7;
- assign mem_tin_vs_addr_MPORT_30_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_30_en = ivalid & _GEN_1903;
- assign mem_tin_vs_addr_MPORT_31_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_31_addr = 3'h7;
- assign mem_tin_vs_addr_MPORT_31_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_31_en = ivalid & _GEN_1921;
- assign mem_tin_vs_tag_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vs_tag_io_out_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vs_tag_io_entry_0_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vs_tag_io_entry_1_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vs_tag_io_entry_2_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vs_tag_io_entry_3_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vs_tag_io_entry_4_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vs_tag_io_entry_5_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vs_tag_io_entry_6_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vs_tag_io_entry_7_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_MPORT_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_addr = 3'h0;
- assign mem_tin_vs_tag_MPORT_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_en = ivalid & valid[0];
- assign mem_tin_vs_tag_MPORT_1_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_1_addr = 3'h0;
- assign mem_tin_vs_tag_MPORT_1_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_1_en = ivalid & _GEN_135;
- assign mem_tin_vs_tag_MPORT_2_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_2_addr = 3'h0;
- assign mem_tin_vs_tag_MPORT_2_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_2_en = ivalid & _GEN_153;
- assign mem_tin_vs_tag_MPORT_3_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_3_addr = 3'h0;
- assign mem_tin_vs_tag_MPORT_3_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_3_en = ivalid & _GEN_171;
- assign mem_tin_vs_tag_MPORT_4_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_4_addr = 3'h1;
- assign mem_tin_vs_tag_MPORT_4_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vs_tag_MPORT_5_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_5_addr = 3'h1;
- assign mem_tin_vs_tag_MPORT_5_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_5_en = ivalid & _GEN_380;
- assign mem_tin_vs_tag_MPORT_6_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_6_addr = 3'h1;
- assign mem_tin_vs_tag_MPORT_6_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_6_en = ivalid & _GEN_397;
- assign mem_tin_vs_tag_MPORT_7_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_7_addr = 3'h1;
- assign mem_tin_vs_tag_MPORT_7_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_7_en = ivalid & _GEN_414;
- assign mem_tin_vs_tag_MPORT_8_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_8_addr = 3'h2;
- assign mem_tin_vs_tag_MPORT_8_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vs_tag_MPORT_9_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_9_addr = 3'h2;
- assign mem_tin_vs_tag_MPORT_9_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_9_en = ivalid & _GEN_625;
- assign mem_tin_vs_tag_MPORT_10_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_10_addr = 3'h2;
- assign mem_tin_vs_tag_MPORT_10_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_10_en = ivalid & _GEN_643;
- assign mem_tin_vs_tag_MPORT_11_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_11_addr = 3'h2;
- assign mem_tin_vs_tag_MPORT_11_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_11_en = ivalid & _GEN_661;
- assign mem_tin_vs_tag_MPORT_12_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_12_addr = 3'h3;
- assign mem_tin_vs_tag_MPORT_12_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vs_tag_MPORT_13_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_13_addr = 3'h3;
- assign mem_tin_vs_tag_MPORT_13_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_13_en = ivalid & _GEN_877;
- assign mem_tin_vs_tag_MPORT_14_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_14_addr = 3'h3;
- assign mem_tin_vs_tag_MPORT_14_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_14_en = ivalid & _GEN_895;
- assign mem_tin_vs_tag_MPORT_15_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_15_addr = 3'h3;
- assign mem_tin_vs_tag_MPORT_15_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_15_en = ivalid & _GEN_913;
- assign mem_tin_vs_tag_MPORT_16_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_16_addr = 3'h4;
- assign mem_tin_vs_tag_MPORT_16_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vs_tag_MPORT_17_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_17_addr = 3'h4;
- assign mem_tin_vs_tag_MPORT_17_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_17_en = ivalid & _GEN_1129;
- assign mem_tin_vs_tag_MPORT_18_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_18_addr = 3'h4;
- assign mem_tin_vs_tag_MPORT_18_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_18_en = ivalid & _GEN_1147;
- assign mem_tin_vs_tag_MPORT_19_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_19_addr = 3'h4;
- assign mem_tin_vs_tag_MPORT_19_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_19_en = ivalid & _GEN_1165;
- assign mem_tin_vs_tag_MPORT_20_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_20_addr = 3'h5;
- assign mem_tin_vs_tag_MPORT_20_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vs_tag_MPORT_21_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_21_addr = 3'h5;
- assign mem_tin_vs_tag_MPORT_21_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_21_en = ivalid & _GEN_1381;
- assign mem_tin_vs_tag_MPORT_22_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_22_addr = 3'h5;
- assign mem_tin_vs_tag_MPORT_22_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_22_en = ivalid & _GEN_1399;
- assign mem_tin_vs_tag_MPORT_23_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_23_addr = 3'h5;
- assign mem_tin_vs_tag_MPORT_23_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_23_en = ivalid & _GEN_1417;
- assign mem_tin_vs_tag_MPORT_24_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_24_addr = 3'h6;
- assign mem_tin_vs_tag_MPORT_24_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vs_tag_MPORT_25_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_25_addr = 3'h6;
- assign mem_tin_vs_tag_MPORT_25_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_25_en = ivalid & _GEN_1633;
- assign mem_tin_vs_tag_MPORT_26_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_26_addr = 3'h6;
- assign mem_tin_vs_tag_MPORT_26_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_26_en = ivalid & _GEN_1651;
- assign mem_tin_vs_tag_MPORT_27_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_27_addr = 3'h6;
- assign mem_tin_vs_tag_MPORT_27_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_27_en = ivalid & _GEN_1669;
- assign mem_tin_vs_tag_MPORT_28_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_28_addr = 3'h7;
- assign mem_tin_vs_tag_MPORT_28_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vs_tag_MPORT_29_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_29_addr = 3'h7;
- assign mem_tin_vs_tag_MPORT_29_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_29_en = ivalid & _GEN_1885;
- assign mem_tin_vs_tag_MPORT_30_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_30_addr = 3'h7;
- assign mem_tin_vs_tag_MPORT_30_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_30_en = ivalid & _GEN_1903;
- assign mem_tin_vs_tag_MPORT_31_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_31_addr = 3'h7;
- assign mem_tin_vs_tag_MPORT_31_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_31_en = ivalid & _GEN_1921;
- assign mem_tin_quad_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_quad_io_out_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_quad_io_entry_0_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_quad_io_entry_1_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_quad_io_entry_2_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_quad_io_entry_3_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_quad_io_entry_4_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_quad_io_entry_5_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_quad_io_entry_6_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_quad_io_entry_7_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_MPORT_data = 2'h0;
- assign mem_tin_quad_MPORT_addr = 3'h0;
- assign mem_tin_quad_MPORT_mask = 1'h1;
- assign mem_tin_quad_MPORT_en = ivalid & valid[0];
- assign mem_tin_quad_MPORT_1_data = 2'h0;
- assign mem_tin_quad_MPORT_1_addr = 3'h0;
- assign mem_tin_quad_MPORT_1_mask = 1'h1;
- assign mem_tin_quad_MPORT_1_en = ivalid & _GEN_135;
- assign mem_tin_quad_MPORT_2_data = 2'h0;
- assign mem_tin_quad_MPORT_2_addr = 3'h0;
- assign mem_tin_quad_MPORT_2_mask = 1'h1;
- assign mem_tin_quad_MPORT_2_en = ivalid & _GEN_153;
- assign mem_tin_quad_MPORT_3_data = 2'h0;
- assign mem_tin_quad_MPORT_3_addr = 3'h0;
- assign mem_tin_quad_MPORT_3_mask = 1'h1;
- assign mem_tin_quad_MPORT_3_en = ivalid & _GEN_171;
- assign mem_tin_quad_MPORT_4_data = 2'h0;
- assign mem_tin_quad_MPORT_4_addr = 3'h1;
- assign mem_tin_quad_MPORT_4_mask = 1'h1;
- assign mem_tin_quad_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_quad_MPORT_5_data = 2'h0;
- assign mem_tin_quad_MPORT_5_addr = 3'h1;
- assign mem_tin_quad_MPORT_5_mask = 1'h1;
- assign mem_tin_quad_MPORT_5_en = ivalid & _GEN_380;
- assign mem_tin_quad_MPORT_6_data = 2'h0;
- assign mem_tin_quad_MPORT_6_addr = 3'h1;
- assign mem_tin_quad_MPORT_6_mask = 1'h1;
- assign mem_tin_quad_MPORT_6_en = ivalid & _GEN_397;
- assign mem_tin_quad_MPORT_7_data = 2'h0;
- assign mem_tin_quad_MPORT_7_addr = 3'h1;
- assign mem_tin_quad_MPORT_7_mask = 1'h1;
- assign mem_tin_quad_MPORT_7_en = ivalid & _GEN_414;
- assign mem_tin_quad_MPORT_8_data = 2'h0;
- assign mem_tin_quad_MPORT_8_addr = 3'h2;
- assign mem_tin_quad_MPORT_8_mask = 1'h1;
- assign mem_tin_quad_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_quad_MPORT_9_data = 2'h0;
- assign mem_tin_quad_MPORT_9_addr = 3'h2;
- assign mem_tin_quad_MPORT_9_mask = 1'h1;
- assign mem_tin_quad_MPORT_9_en = ivalid & _GEN_625;
- assign mem_tin_quad_MPORT_10_data = 2'h0;
- assign mem_tin_quad_MPORT_10_addr = 3'h2;
- assign mem_tin_quad_MPORT_10_mask = 1'h1;
- assign mem_tin_quad_MPORT_10_en = ivalid & _GEN_643;
- assign mem_tin_quad_MPORT_11_data = 2'h0;
- assign mem_tin_quad_MPORT_11_addr = 3'h2;
- assign mem_tin_quad_MPORT_11_mask = 1'h1;
- assign mem_tin_quad_MPORT_11_en = ivalid & _GEN_661;
- assign mem_tin_quad_MPORT_12_data = 2'h0;
- assign mem_tin_quad_MPORT_12_addr = 3'h3;
- assign mem_tin_quad_MPORT_12_mask = 1'h1;
- assign mem_tin_quad_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_quad_MPORT_13_data = 2'h0;
- assign mem_tin_quad_MPORT_13_addr = 3'h3;
- assign mem_tin_quad_MPORT_13_mask = 1'h1;
- assign mem_tin_quad_MPORT_13_en = ivalid & _GEN_877;
- assign mem_tin_quad_MPORT_14_data = 2'h0;
- assign mem_tin_quad_MPORT_14_addr = 3'h3;
- assign mem_tin_quad_MPORT_14_mask = 1'h1;
- assign mem_tin_quad_MPORT_14_en = ivalid & _GEN_895;
- assign mem_tin_quad_MPORT_15_data = 2'h0;
- assign mem_tin_quad_MPORT_15_addr = 3'h3;
- assign mem_tin_quad_MPORT_15_mask = 1'h1;
- assign mem_tin_quad_MPORT_15_en = ivalid & _GEN_913;
- assign mem_tin_quad_MPORT_16_data = 2'h0;
- assign mem_tin_quad_MPORT_16_addr = 3'h4;
- assign mem_tin_quad_MPORT_16_mask = 1'h1;
- assign mem_tin_quad_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_quad_MPORT_17_data = 2'h0;
- assign mem_tin_quad_MPORT_17_addr = 3'h4;
- assign mem_tin_quad_MPORT_17_mask = 1'h1;
- assign mem_tin_quad_MPORT_17_en = ivalid & _GEN_1129;
- assign mem_tin_quad_MPORT_18_data = 2'h0;
- assign mem_tin_quad_MPORT_18_addr = 3'h4;
- assign mem_tin_quad_MPORT_18_mask = 1'h1;
- assign mem_tin_quad_MPORT_18_en = ivalid & _GEN_1147;
- assign mem_tin_quad_MPORT_19_data = 2'h0;
- assign mem_tin_quad_MPORT_19_addr = 3'h4;
- assign mem_tin_quad_MPORT_19_mask = 1'h1;
- assign mem_tin_quad_MPORT_19_en = ivalid & _GEN_1165;
- assign mem_tin_quad_MPORT_20_data = 2'h0;
- assign mem_tin_quad_MPORT_20_addr = 3'h5;
- assign mem_tin_quad_MPORT_20_mask = 1'h1;
- assign mem_tin_quad_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_quad_MPORT_21_data = 2'h0;
- assign mem_tin_quad_MPORT_21_addr = 3'h5;
- assign mem_tin_quad_MPORT_21_mask = 1'h1;
- assign mem_tin_quad_MPORT_21_en = ivalid & _GEN_1381;
- assign mem_tin_quad_MPORT_22_data = 2'h0;
- assign mem_tin_quad_MPORT_22_addr = 3'h5;
- assign mem_tin_quad_MPORT_22_mask = 1'h1;
- assign mem_tin_quad_MPORT_22_en = ivalid & _GEN_1399;
- assign mem_tin_quad_MPORT_23_data = 2'h0;
- assign mem_tin_quad_MPORT_23_addr = 3'h5;
- assign mem_tin_quad_MPORT_23_mask = 1'h1;
- assign mem_tin_quad_MPORT_23_en = ivalid & _GEN_1417;
- assign mem_tin_quad_MPORT_24_data = 2'h0;
- assign mem_tin_quad_MPORT_24_addr = 3'h6;
- assign mem_tin_quad_MPORT_24_mask = 1'h1;
- assign mem_tin_quad_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_quad_MPORT_25_data = 2'h0;
- assign mem_tin_quad_MPORT_25_addr = 3'h6;
- assign mem_tin_quad_MPORT_25_mask = 1'h1;
- assign mem_tin_quad_MPORT_25_en = ivalid & _GEN_1633;
- assign mem_tin_quad_MPORT_26_data = 2'h0;
- assign mem_tin_quad_MPORT_26_addr = 3'h6;
- assign mem_tin_quad_MPORT_26_mask = 1'h1;
- assign mem_tin_quad_MPORT_26_en = ivalid & _GEN_1651;
- assign mem_tin_quad_MPORT_27_data = 2'h0;
- assign mem_tin_quad_MPORT_27_addr = 3'h6;
- assign mem_tin_quad_MPORT_27_mask = 1'h1;
- assign mem_tin_quad_MPORT_27_en = ivalid & _GEN_1669;
- assign mem_tin_quad_MPORT_28_data = 2'h0;
- assign mem_tin_quad_MPORT_28_addr = 3'h7;
- assign mem_tin_quad_MPORT_28_mask = 1'h1;
- assign mem_tin_quad_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_quad_MPORT_29_data = 2'h0;
- assign mem_tin_quad_MPORT_29_addr = 3'h7;
- assign mem_tin_quad_MPORT_29_mask = 1'h1;
- assign mem_tin_quad_MPORT_29_en = ivalid & _GEN_1885;
- assign mem_tin_quad_MPORT_30_data = 2'h0;
- assign mem_tin_quad_MPORT_30_addr = 3'h7;
- assign mem_tin_quad_MPORT_30_mask = 1'h1;
- assign mem_tin_quad_MPORT_30_en = ivalid & _GEN_1903;
- assign mem_tin_quad_MPORT_31_data = 2'h0;
- assign mem_tin_quad_MPORT_31_addr = 3'h7;
- assign mem_tin_quad_MPORT_31_mask = 1'h1;
- assign mem_tin_quad_MPORT_31_en = ivalid & _GEN_1921;
- assign mem_tin_last_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_last_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_last_io_out_bits_MPORT_data = mem_tin_last[mem_tin_last_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_last_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_last_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_last_io_entry_0_bits_MPORT_data = mem_tin_last[mem_tin_last_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_last_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_last_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_last_io_entry_1_bits_MPORT_data = mem_tin_last[mem_tin_last_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_last_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_last_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_last_io_entry_2_bits_MPORT_data = mem_tin_last[mem_tin_last_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_last_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_last_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_last_io_entry_3_bits_MPORT_data = mem_tin_last[mem_tin_last_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_last_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_last_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_last_io_entry_4_bits_MPORT_data = mem_tin_last[mem_tin_last_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_last_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_last_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_last_io_entry_5_bits_MPORT_data = mem_tin_last[mem_tin_last_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_last_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_last_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_last_io_entry_6_bits_MPORT_data = mem_tin_last[mem_tin_last_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_last_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_last_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_last_io_entry_7_bits_MPORT_data = mem_tin_last[mem_tin_last_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_last_MPORT_data = io_in_bits_0_bits_tin_last;
- assign mem_tin_last_MPORT_addr = 3'h0;
- assign mem_tin_last_MPORT_mask = 1'h1;
- assign mem_tin_last_MPORT_en = ivalid & valid[0];
- assign mem_tin_last_MPORT_1_data = io_in_bits_1_bits_tin_last;
- assign mem_tin_last_MPORT_1_addr = 3'h0;
- assign mem_tin_last_MPORT_1_mask = 1'h1;
- assign mem_tin_last_MPORT_1_en = ivalid & _GEN_135;
- assign mem_tin_last_MPORT_2_data = io_in_bits_2_bits_tin_last;
- assign mem_tin_last_MPORT_2_addr = 3'h0;
- assign mem_tin_last_MPORT_2_mask = 1'h1;
- assign mem_tin_last_MPORT_2_en = ivalid & _GEN_153;
- assign mem_tin_last_MPORT_3_data = io_in_bits_3_bits_tin_last;
- assign mem_tin_last_MPORT_3_addr = 3'h0;
- assign mem_tin_last_MPORT_3_mask = 1'h1;
- assign mem_tin_last_MPORT_3_en = ivalid & _GEN_171;
- assign mem_tin_last_MPORT_4_data = io_in_bits_0_bits_tin_last;
- assign mem_tin_last_MPORT_4_addr = 3'h1;
- assign mem_tin_last_MPORT_4_mask = 1'h1;
- assign mem_tin_last_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_last_MPORT_5_data = io_in_bits_1_bits_tin_last;
- assign mem_tin_last_MPORT_5_addr = 3'h1;
- assign mem_tin_last_MPORT_5_mask = 1'h1;
- assign mem_tin_last_MPORT_5_en = ivalid & _GEN_380;
- assign mem_tin_last_MPORT_6_data = io_in_bits_2_bits_tin_last;
- assign mem_tin_last_MPORT_6_addr = 3'h1;
- assign mem_tin_last_MPORT_6_mask = 1'h1;
- assign mem_tin_last_MPORT_6_en = ivalid & _GEN_397;
- assign mem_tin_last_MPORT_7_data = io_in_bits_3_bits_tin_last;
- assign mem_tin_last_MPORT_7_addr = 3'h1;
- assign mem_tin_last_MPORT_7_mask = 1'h1;
- assign mem_tin_last_MPORT_7_en = ivalid & _GEN_414;
- assign mem_tin_last_MPORT_8_data = io_in_bits_0_bits_tin_last;
- assign mem_tin_last_MPORT_8_addr = 3'h2;
- assign mem_tin_last_MPORT_8_mask = 1'h1;
- assign mem_tin_last_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_last_MPORT_9_data = io_in_bits_1_bits_tin_last;
- assign mem_tin_last_MPORT_9_addr = 3'h2;
- assign mem_tin_last_MPORT_9_mask = 1'h1;
- assign mem_tin_last_MPORT_9_en = ivalid & _GEN_625;
- assign mem_tin_last_MPORT_10_data = io_in_bits_2_bits_tin_last;
- assign mem_tin_last_MPORT_10_addr = 3'h2;
- assign mem_tin_last_MPORT_10_mask = 1'h1;
- assign mem_tin_last_MPORT_10_en = ivalid & _GEN_643;
- assign mem_tin_last_MPORT_11_data = io_in_bits_3_bits_tin_last;
- assign mem_tin_last_MPORT_11_addr = 3'h2;
- assign mem_tin_last_MPORT_11_mask = 1'h1;
- assign mem_tin_last_MPORT_11_en = ivalid & _GEN_661;
- assign mem_tin_last_MPORT_12_data = io_in_bits_0_bits_tin_last;
- assign mem_tin_last_MPORT_12_addr = 3'h3;
- assign mem_tin_last_MPORT_12_mask = 1'h1;
- assign mem_tin_last_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_last_MPORT_13_data = io_in_bits_1_bits_tin_last;
- assign mem_tin_last_MPORT_13_addr = 3'h3;
- assign mem_tin_last_MPORT_13_mask = 1'h1;
- assign mem_tin_last_MPORT_13_en = ivalid & _GEN_877;
- assign mem_tin_last_MPORT_14_data = io_in_bits_2_bits_tin_last;
- assign mem_tin_last_MPORT_14_addr = 3'h3;
- assign mem_tin_last_MPORT_14_mask = 1'h1;
- assign mem_tin_last_MPORT_14_en = ivalid & _GEN_895;
- assign mem_tin_last_MPORT_15_data = io_in_bits_3_bits_tin_last;
- assign mem_tin_last_MPORT_15_addr = 3'h3;
- assign mem_tin_last_MPORT_15_mask = 1'h1;
- assign mem_tin_last_MPORT_15_en = ivalid & _GEN_913;
- assign mem_tin_last_MPORT_16_data = io_in_bits_0_bits_tin_last;
- assign mem_tin_last_MPORT_16_addr = 3'h4;
- assign mem_tin_last_MPORT_16_mask = 1'h1;
- assign mem_tin_last_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_last_MPORT_17_data = io_in_bits_1_bits_tin_last;
- assign mem_tin_last_MPORT_17_addr = 3'h4;
- assign mem_tin_last_MPORT_17_mask = 1'h1;
- assign mem_tin_last_MPORT_17_en = ivalid & _GEN_1129;
- assign mem_tin_last_MPORT_18_data = io_in_bits_2_bits_tin_last;
- assign mem_tin_last_MPORT_18_addr = 3'h4;
- assign mem_tin_last_MPORT_18_mask = 1'h1;
- assign mem_tin_last_MPORT_18_en = ivalid & _GEN_1147;
- assign mem_tin_last_MPORT_19_data = io_in_bits_3_bits_tin_last;
- assign mem_tin_last_MPORT_19_addr = 3'h4;
- assign mem_tin_last_MPORT_19_mask = 1'h1;
- assign mem_tin_last_MPORT_19_en = ivalid & _GEN_1165;
- assign mem_tin_last_MPORT_20_data = io_in_bits_0_bits_tin_last;
- assign mem_tin_last_MPORT_20_addr = 3'h5;
- assign mem_tin_last_MPORT_20_mask = 1'h1;
- assign mem_tin_last_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_last_MPORT_21_data = io_in_bits_1_bits_tin_last;
- assign mem_tin_last_MPORT_21_addr = 3'h5;
- assign mem_tin_last_MPORT_21_mask = 1'h1;
- assign mem_tin_last_MPORT_21_en = ivalid & _GEN_1381;
- assign mem_tin_last_MPORT_22_data = io_in_bits_2_bits_tin_last;
- assign mem_tin_last_MPORT_22_addr = 3'h5;
- assign mem_tin_last_MPORT_22_mask = 1'h1;
- assign mem_tin_last_MPORT_22_en = ivalid & _GEN_1399;
- assign mem_tin_last_MPORT_23_data = io_in_bits_3_bits_tin_last;
- assign mem_tin_last_MPORT_23_addr = 3'h5;
- assign mem_tin_last_MPORT_23_mask = 1'h1;
- assign mem_tin_last_MPORT_23_en = ivalid & _GEN_1417;
- assign mem_tin_last_MPORT_24_data = io_in_bits_0_bits_tin_last;
- assign mem_tin_last_MPORT_24_addr = 3'h6;
- assign mem_tin_last_MPORT_24_mask = 1'h1;
- assign mem_tin_last_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_last_MPORT_25_data = io_in_bits_1_bits_tin_last;
- assign mem_tin_last_MPORT_25_addr = 3'h6;
- assign mem_tin_last_MPORT_25_mask = 1'h1;
- assign mem_tin_last_MPORT_25_en = ivalid & _GEN_1633;
- assign mem_tin_last_MPORT_26_data = io_in_bits_2_bits_tin_last;
- assign mem_tin_last_MPORT_26_addr = 3'h6;
- assign mem_tin_last_MPORT_26_mask = 1'h1;
- assign mem_tin_last_MPORT_26_en = ivalid & _GEN_1651;
- assign mem_tin_last_MPORT_27_data = io_in_bits_3_bits_tin_last;
- assign mem_tin_last_MPORT_27_addr = 3'h6;
- assign mem_tin_last_MPORT_27_mask = 1'h1;
- assign mem_tin_last_MPORT_27_en = ivalid & _GEN_1669;
- assign mem_tin_last_MPORT_28_data = io_in_bits_0_bits_tin_last;
- assign mem_tin_last_MPORT_28_addr = 3'h7;
- assign mem_tin_last_MPORT_28_mask = 1'h1;
- assign mem_tin_last_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_last_MPORT_29_data = io_in_bits_1_bits_tin_last;
- assign mem_tin_last_MPORT_29_addr = 3'h7;
- assign mem_tin_last_MPORT_29_mask = 1'h1;
- assign mem_tin_last_MPORT_29_en = ivalid & _GEN_1885;
- assign mem_tin_last_MPORT_30_data = io_in_bits_2_bits_tin_last;
- assign mem_tin_last_MPORT_30_addr = 3'h7;
- assign mem_tin_last_MPORT_30_mask = 1'h1;
- assign mem_tin_last_MPORT_30_en = ivalid & _GEN_1903;
- assign mem_tin_last_MPORT_31_data = io_in_bits_3_bits_tin_last;
- assign mem_tin_last_MPORT_31_addr = 3'h7;
- assign mem_tin_last_MPORT_31_mask = 1'h1;
- assign mem_tin_last_MPORT_31_en = ivalid & _GEN_1921;
- assign mem_m_io_out_bits_MPORT_en = 1'h1;
- assign mem_m_io_out_bits_MPORT_addr = outpos;
- assign mem_m_io_out_bits_MPORT_data = mem_m[mem_m_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_m_io_entry_0_bits_MPORT_data = mem_m[mem_m_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_m_io_entry_1_bits_MPORT_data = mem_m[mem_m_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_m_io_entry_2_bits_MPORT_data = mem_m[mem_m_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_m_io_entry_3_bits_MPORT_data = mem_m[mem_m_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_m_io_entry_4_bits_MPORT_data = mem_m[mem_m_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_m_io_entry_5_bits_MPORT_data = mem_m[mem_m_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_m_io_entry_6_bits_MPORT_data = mem_m[mem_m_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_m_io_entry_7_bits_MPORT_data = mem_m[mem_m_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_MPORT_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_addr = 3'h0;
- assign mem_m_MPORT_mask = 1'h1;
- assign mem_m_MPORT_en = ivalid & valid[0];
- assign mem_m_MPORT_1_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_1_addr = 3'h0;
- assign mem_m_MPORT_1_mask = 1'h1;
- assign mem_m_MPORT_1_en = ivalid & _GEN_135;
- assign mem_m_MPORT_2_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_2_addr = 3'h0;
- assign mem_m_MPORT_2_mask = 1'h1;
- assign mem_m_MPORT_2_en = ivalid & _GEN_153;
- assign mem_m_MPORT_3_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_3_addr = 3'h0;
- assign mem_m_MPORT_3_mask = 1'h1;
- assign mem_m_MPORT_3_en = ivalid & _GEN_171;
- assign mem_m_MPORT_4_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_4_addr = 3'h1;
- assign mem_m_MPORT_4_mask = 1'h1;
- assign mem_m_MPORT_4_en = ivalid & valid_1[0];
- assign mem_m_MPORT_5_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_5_addr = 3'h1;
- assign mem_m_MPORT_5_mask = 1'h1;
- assign mem_m_MPORT_5_en = ivalid & _GEN_380;
- assign mem_m_MPORT_6_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_6_addr = 3'h1;
- assign mem_m_MPORT_6_mask = 1'h1;
- assign mem_m_MPORT_6_en = ivalid & _GEN_397;
- assign mem_m_MPORT_7_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_7_addr = 3'h1;
- assign mem_m_MPORT_7_mask = 1'h1;
- assign mem_m_MPORT_7_en = ivalid & _GEN_414;
- assign mem_m_MPORT_8_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_8_addr = 3'h2;
- assign mem_m_MPORT_8_mask = 1'h1;
- assign mem_m_MPORT_8_en = ivalid & valid_2[0];
- assign mem_m_MPORT_9_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_9_addr = 3'h2;
- assign mem_m_MPORT_9_mask = 1'h1;
- assign mem_m_MPORT_9_en = ivalid & _GEN_625;
- assign mem_m_MPORT_10_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_10_addr = 3'h2;
- assign mem_m_MPORT_10_mask = 1'h1;
- assign mem_m_MPORT_10_en = ivalid & _GEN_643;
- assign mem_m_MPORT_11_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_11_addr = 3'h2;
- assign mem_m_MPORT_11_mask = 1'h1;
- assign mem_m_MPORT_11_en = ivalid & _GEN_661;
- assign mem_m_MPORT_12_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_12_addr = 3'h3;
- assign mem_m_MPORT_12_mask = 1'h1;
- assign mem_m_MPORT_12_en = ivalid & valid_3[0];
- assign mem_m_MPORT_13_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_13_addr = 3'h3;
- assign mem_m_MPORT_13_mask = 1'h1;
- assign mem_m_MPORT_13_en = ivalid & _GEN_877;
- assign mem_m_MPORT_14_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_14_addr = 3'h3;
- assign mem_m_MPORT_14_mask = 1'h1;
- assign mem_m_MPORT_14_en = ivalid & _GEN_895;
- assign mem_m_MPORT_15_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_15_addr = 3'h3;
- assign mem_m_MPORT_15_mask = 1'h1;
- assign mem_m_MPORT_15_en = ivalid & _GEN_913;
- assign mem_m_MPORT_16_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_16_addr = 3'h4;
- assign mem_m_MPORT_16_mask = 1'h1;
- assign mem_m_MPORT_16_en = ivalid & valid_4[0];
- assign mem_m_MPORT_17_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_17_addr = 3'h4;
- assign mem_m_MPORT_17_mask = 1'h1;
- assign mem_m_MPORT_17_en = ivalid & _GEN_1129;
- assign mem_m_MPORT_18_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_18_addr = 3'h4;
- assign mem_m_MPORT_18_mask = 1'h1;
- assign mem_m_MPORT_18_en = ivalid & _GEN_1147;
- assign mem_m_MPORT_19_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_19_addr = 3'h4;
- assign mem_m_MPORT_19_mask = 1'h1;
- assign mem_m_MPORT_19_en = ivalid & _GEN_1165;
- assign mem_m_MPORT_20_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_20_addr = 3'h5;
- assign mem_m_MPORT_20_mask = 1'h1;
- assign mem_m_MPORT_20_en = ivalid & valid_5[0];
- assign mem_m_MPORT_21_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_21_addr = 3'h5;
- assign mem_m_MPORT_21_mask = 1'h1;
- assign mem_m_MPORT_21_en = ivalid & _GEN_1381;
- assign mem_m_MPORT_22_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_22_addr = 3'h5;
- assign mem_m_MPORT_22_mask = 1'h1;
- assign mem_m_MPORT_22_en = ivalid & _GEN_1399;
- assign mem_m_MPORT_23_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_23_addr = 3'h5;
- assign mem_m_MPORT_23_mask = 1'h1;
- assign mem_m_MPORT_23_en = ivalid & _GEN_1417;
- assign mem_m_MPORT_24_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_24_addr = 3'h6;
- assign mem_m_MPORT_24_mask = 1'h1;
- assign mem_m_MPORT_24_en = ivalid & valid_6[0];
- assign mem_m_MPORT_25_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_25_addr = 3'h6;
- assign mem_m_MPORT_25_mask = 1'h1;
- assign mem_m_MPORT_25_en = ivalid & _GEN_1633;
- assign mem_m_MPORT_26_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_26_addr = 3'h6;
- assign mem_m_MPORT_26_mask = 1'h1;
- assign mem_m_MPORT_26_en = ivalid & _GEN_1651;
- assign mem_m_MPORT_27_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_27_addr = 3'h6;
- assign mem_m_MPORT_27_mask = 1'h1;
- assign mem_m_MPORT_27_en = ivalid & _GEN_1669;
- assign mem_m_MPORT_28_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_28_addr = 3'h7;
- assign mem_m_MPORT_28_mask = 1'h1;
- assign mem_m_MPORT_28_en = ivalid & valid_7[0];
- assign mem_m_MPORT_29_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_29_addr = 3'h7;
- assign mem_m_MPORT_29_mask = 1'h1;
- assign mem_m_MPORT_29_en = ivalid & _GEN_1885;
- assign mem_m_MPORT_30_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_30_addr = 3'h7;
- assign mem_m_MPORT_30_mask = 1'h1;
- assign mem_m_MPORT_30_en = ivalid & _GEN_1903;
- assign mem_m_MPORT_31_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_31_addr = 3'h7;
- assign mem_m_MPORT_31_mask = 1'h1;
- assign mem_m_MPORT_31_en = ivalid & _GEN_1921;
- assign io_in_ready = mcount <= _io_in_ready_T_1; // @[Fifo4e.scala 132:25]
- assign io_out_valid = mcount != 4'h0; // @[Fifo4e.scala 134:26]
- assign io_out_bits_tin_op = mem_tin_op_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_addr = mem_tin_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_offset = mem_tin_offset_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_remain = mem_tin_remain_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vd_addr = mem_tin_vd_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vs_valid = mem_tin_vs_valid_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vs_addr = mem_tin_vs_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vs_tag = mem_tin_vs_tag_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_quad = mem_tin_quad_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_last = mem_tin_last_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_m = mem_m_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_entry_0_valid = active[0]; // @[Fifo4e.scala 140:32]
- assign io_entry_0_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_m = mem_m_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_valid = active[1]; // @[Fifo4e.scala 140:32]
- assign io_entry_1_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_m = mem_m_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_valid = active[2]; // @[Fifo4e.scala 140:32]
- assign io_entry_2_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_m = mem_m_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_valid = active[3]; // @[Fifo4e.scala 140:32]
- assign io_entry_3_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_m = mem_m_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_4_valid = active[4]; // @[Fifo4e.scala 140:32]
- assign io_entry_4_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_4_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_4_bits_m = mem_m_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_5_valid = active[5]; // @[Fifo4e.scala 140:32]
- assign io_entry_5_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_5_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_5_bits_m = mem_m_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_6_valid = active[6]; // @[Fifo4e.scala 140:32]
- assign io_entry_6_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_6_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_6_bits_m = mem_m_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_7_valid = active[7]; // @[Fifo4e.scala 140:32]
- assign io_entry_7_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_7_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_7_bits_m = mem_m_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- always @(posedge clock) begin
- if (mem_tin_op_MPORT_en & mem_tin_op_MPORT_mask) begin
- mem_tin_op[mem_tin_op_MPORT_addr] <= mem_tin_op_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_1_en & mem_tin_op_MPORT_1_mask) begin
- mem_tin_op[mem_tin_op_MPORT_1_addr] <= mem_tin_op_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_2_en & mem_tin_op_MPORT_2_mask) begin
- mem_tin_op[mem_tin_op_MPORT_2_addr] <= mem_tin_op_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_3_en & mem_tin_op_MPORT_3_mask) begin
- mem_tin_op[mem_tin_op_MPORT_3_addr] <= mem_tin_op_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_4_en & mem_tin_op_MPORT_4_mask) begin
- mem_tin_op[mem_tin_op_MPORT_4_addr] <= mem_tin_op_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_5_en & mem_tin_op_MPORT_5_mask) begin
- mem_tin_op[mem_tin_op_MPORT_5_addr] <= mem_tin_op_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_6_en & mem_tin_op_MPORT_6_mask) begin
- mem_tin_op[mem_tin_op_MPORT_6_addr] <= mem_tin_op_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_7_en & mem_tin_op_MPORT_7_mask) begin
- mem_tin_op[mem_tin_op_MPORT_7_addr] <= mem_tin_op_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_8_en & mem_tin_op_MPORT_8_mask) begin
- mem_tin_op[mem_tin_op_MPORT_8_addr] <= mem_tin_op_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_9_en & mem_tin_op_MPORT_9_mask) begin
- mem_tin_op[mem_tin_op_MPORT_9_addr] <= mem_tin_op_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_10_en & mem_tin_op_MPORT_10_mask) begin
- mem_tin_op[mem_tin_op_MPORT_10_addr] <= mem_tin_op_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_11_en & mem_tin_op_MPORT_11_mask) begin
- mem_tin_op[mem_tin_op_MPORT_11_addr] <= mem_tin_op_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_12_en & mem_tin_op_MPORT_12_mask) begin
- mem_tin_op[mem_tin_op_MPORT_12_addr] <= mem_tin_op_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_13_en & mem_tin_op_MPORT_13_mask) begin
- mem_tin_op[mem_tin_op_MPORT_13_addr] <= mem_tin_op_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_14_en & mem_tin_op_MPORT_14_mask) begin
- mem_tin_op[mem_tin_op_MPORT_14_addr] <= mem_tin_op_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_15_en & mem_tin_op_MPORT_15_mask) begin
- mem_tin_op[mem_tin_op_MPORT_15_addr] <= mem_tin_op_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_16_en & mem_tin_op_MPORT_16_mask) begin
- mem_tin_op[mem_tin_op_MPORT_16_addr] <= mem_tin_op_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_17_en & mem_tin_op_MPORT_17_mask) begin
- mem_tin_op[mem_tin_op_MPORT_17_addr] <= mem_tin_op_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_18_en & mem_tin_op_MPORT_18_mask) begin
- mem_tin_op[mem_tin_op_MPORT_18_addr] <= mem_tin_op_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_19_en & mem_tin_op_MPORT_19_mask) begin
- mem_tin_op[mem_tin_op_MPORT_19_addr] <= mem_tin_op_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_20_en & mem_tin_op_MPORT_20_mask) begin
- mem_tin_op[mem_tin_op_MPORT_20_addr] <= mem_tin_op_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_21_en & mem_tin_op_MPORT_21_mask) begin
- mem_tin_op[mem_tin_op_MPORT_21_addr] <= mem_tin_op_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_22_en & mem_tin_op_MPORT_22_mask) begin
- mem_tin_op[mem_tin_op_MPORT_22_addr] <= mem_tin_op_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_23_en & mem_tin_op_MPORT_23_mask) begin
- mem_tin_op[mem_tin_op_MPORT_23_addr] <= mem_tin_op_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_24_en & mem_tin_op_MPORT_24_mask) begin
- mem_tin_op[mem_tin_op_MPORT_24_addr] <= mem_tin_op_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_25_en & mem_tin_op_MPORT_25_mask) begin
- mem_tin_op[mem_tin_op_MPORT_25_addr] <= mem_tin_op_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_26_en & mem_tin_op_MPORT_26_mask) begin
- mem_tin_op[mem_tin_op_MPORT_26_addr] <= mem_tin_op_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_27_en & mem_tin_op_MPORT_27_mask) begin
- mem_tin_op[mem_tin_op_MPORT_27_addr] <= mem_tin_op_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_28_en & mem_tin_op_MPORT_28_mask) begin
- mem_tin_op[mem_tin_op_MPORT_28_addr] <= mem_tin_op_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_29_en & mem_tin_op_MPORT_29_mask) begin
- mem_tin_op[mem_tin_op_MPORT_29_addr] <= mem_tin_op_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_30_en & mem_tin_op_MPORT_30_mask) begin
- mem_tin_op[mem_tin_op_MPORT_30_addr] <= mem_tin_op_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_31_en & mem_tin_op_MPORT_31_mask) begin
- mem_tin_op[mem_tin_op_MPORT_31_addr] <= mem_tin_op_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_en & mem_tin_addr_MPORT_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_addr] <= mem_tin_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_1_en & mem_tin_addr_MPORT_1_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_1_addr] <= mem_tin_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_2_en & mem_tin_addr_MPORT_2_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_2_addr] <= mem_tin_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_3_en & mem_tin_addr_MPORT_3_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_3_addr] <= mem_tin_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_4_en & mem_tin_addr_MPORT_4_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_4_addr] <= mem_tin_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_5_en & mem_tin_addr_MPORT_5_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_5_addr] <= mem_tin_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_6_en & mem_tin_addr_MPORT_6_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_6_addr] <= mem_tin_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_7_en & mem_tin_addr_MPORT_7_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_7_addr] <= mem_tin_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_8_en & mem_tin_addr_MPORT_8_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_8_addr] <= mem_tin_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_9_en & mem_tin_addr_MPORT_9_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_9_addr] <= mem_tin_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_10_en & mem_tin_addr_MPORT_10_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_10_addr] <= mem_tin_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_11_en & mem_tin_addr_MPORT_11_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_11_addr] <= mem_tin_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_12_en & mem_tin_addr_MPORT_12_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_12_addr] <= mem_tin_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_13_en & mem_tin_addr_MPORT_13_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_13_addr] <= mem_tin_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_14_en & mem_tin_addr_MPORT_14_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_14_addr] <= mem_tin_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_15_en & mem_tin_addr_MPORT_15_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_15_addr] <= mem_tin_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_16_en & mem_tin_addr_MPORT_16_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_16_addr] <= mem_tin_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_17_en & mem_tin_addr_MPORT_17_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_17_addr] <= mem_tin_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_18_en & mem_tin_addr_MPORT_18_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_18_addr] <= mem_tin_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_19_en & mem_tin_addr_MPORT_19_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_19_addr] <= mem_tin_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_20_en & mem_tin_addr_MPORT_20_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_20_addr] <= mem_tin_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_21_en & mem_tin_addr_MPORT_21_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_21_addr] <= mem_tin_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_22_en & mem_tin_addr_MPORT_22_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_22_addr] <= mem_tin_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_23_en & mem_tin_addr_MPORT_23_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_23_addr] <= mem_tin_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_24_en & mem_tin_addr_MPORT_24_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_24_addr] <= mem_tin_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_25_en & mem_tin_addr_MPORT_25_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_25_addr] <= mem_tin_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_26_en & mem_tin_addr_MPORT_26_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_26_addr] <= mem_tin_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_27_en & mem_tin_addr_MPORT_27_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_27_addr] <= mem_tin_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_28_en & mem_tin_addr_MPORT_28_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_28_addr] <= mem_tin_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_29_en & mem_tin_addr_MPORT_29_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_29_addr] <= mem_tin_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_30_en & mem_tin_addr_MPORT_30_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_30_addr] <= mem_tin_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_31_en & mem_tin_addr_MPORT_31_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_31_addr] <= mem_tin_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_en & mem_tin_offset_MPORT_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_addr] <= mem_tin_offset_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_1_en & mem_tin_offset_MPORT_1_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_1_addr] <= mem_tin_offset_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_2_en & mem_tin_offset_MPORT_2_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_2_addr] <= mem_tin_offset_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_3_en & mem_tin_offset_MPORT_3_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_3_addr] <= mem_tin_offset_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_4_en & mem_tin_offset_MPORT_4_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_4_addr] <= mem_tin_offset_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_5_en & mem_tin_offset_MPORT_5_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_5_addr] <= mem_tin_offset_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_6_en & mem_tin_offset_MPORT_6_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_6_addr] <= mem_tin_offset_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_7_en & mem_tin_offset_MPORT_7_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_7_addr] <= mem_tin_offset_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_8_en & mem_tin_offset_MPORT_8_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_8_addr] <= mem_tin_offset_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_9_en & mem_tin_offset_MPORT_9_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_9_addr] <= mem_tin_offset_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_10_en & mem_tin_offset_MPORT_10_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_10_addr] <= mem_tin_offset_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_11_en & mem_tin_offset_MPORT_11_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_11_addr] <= mem_tin_offset_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_12_en & mem_tin_offset_MPORT_12_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_12_addr] <= mem_tin_offset_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_13_en & mem_tin_offset_MPORT_13_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_13_addr] <= mem_tin_offset_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_14_en & mem_tin_offset_MPORT_14_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_14_addr] <= mem_tin_offset_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_15_en & mem_tin_offset_MPORT_15_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_15_addr] <= mem_tin_offset_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_16_en & mem_tin_offset_MPORT_16_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_16_addr] <= mem_tin_offset_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_17_en & mem_tin_offset_MPORT_17_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_17_addr] <= mem_tin_offset_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_18_en & mem_tin_offset_MPORT_18_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_18_addr] <= mem_tin_offset_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_19_en & mem_tin_offset_MPORT_19_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_19_addr] <= mem_tin_offset_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_20_en & mem_tin_offset_MPORT_20_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_20_addr] <= mem_tin_offset_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_21_en & mem_tin_offset_MPORT_21_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_21_addr] <= mem_tin_offset_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_22_en & mem_tin_offset_MPORT_22_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_22_addr] <= mem_tin_offset_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_23_en & mem_tin_offset_MPORT_23_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_23_addr] <= mem_tin_offset_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_24_en & mem_tin_offset_MPORT_24_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_24_addr] <= mem_tin_offset_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_25_en & mem_tin_offset_MPORT_25_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_25_addr] <= mem_tin_offset_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_26_en & mem_tin_offset_MPORT_26_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_26_addr] <= mem_tin_offset_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_27_en & mem_tin_offset_MPORT_27_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_27_addr] <= mem_tin_offset_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_28_en & mem_tin_offset_MPORT_28_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_28_addr] <= mem_tin_offset_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_29_en & mem_tin_offset_MPORT_29_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_29_addr] <= mem_tin_offset_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_30_en & mem_tin_offset_MPORT_30_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_30_addr] <= mem_tin_offset_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_31_en & mem_tin_offset_MPORT_31_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_31_addr] <= mem_tin_offset_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_en & mem_tin_remain_MPORT_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_addr] <= mem_tin_remain_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_1_en & mem_tin_remain_MPORT_1_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_1_addr] <= mem_tin_remain_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_2_en & mem_tin_remain_MPORT_2_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_2_addr] <= mem_tin_remain_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_3_en & mem_tin_remain_MPORT_3_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_3_addr] <= mem_tin_remain_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_4_en & mem_tin_remain_MPORT_4_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_4_addr] <= mem_tin_remain_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_5_en & mem_tin_remain_MPORT_5_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_5_addr] <= mem_tin_remain_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_6_en & mem_tin_remain_MPORT_6_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_6_addr] <= mem_tin_remain_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_7_en & mem_tin_remain_MPORT_7_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_7_addr] <= mem_tin_remain_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_8_en & mem_tin_remain_MPORT_8_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_8_addr] <= mem_tin_remain_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_9_en & mem_tin_remain_MPORT_9_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_9_addr] <= mem_tin_remain_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_10_en & mem_tin_remain_MPORT_10_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_10_addr] <= mem_tin_remain_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_11_en & mem_tin_remain_MPORT_11_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_11_addr] <= mem_tin_remain_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_12_en & mem_tin_remain_MPORT_12_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_12_addr] <= mem_tin_remain_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_13_en & mem_tin_remain_MPORT_13_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_13_addr] <= mem_tin_remain_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_14_en & mem_tin_remain_MPORT_14_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_14_addr] <= mem_tin_remain_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_15_en & mem_tin_remain_MPORT_15_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_15_addr] <= mem_tin_remain_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_16_en & mem_tin_remain_MPORT_16_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_16_addr] <= mem_tin_remain_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_17_en & mem_tin_remain_MPORT_17_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_17_addr] <= mem_tin_remain_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_18_en & mem_tin_remain_MPORT_18_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_18_addr] <= mem_tin_remain_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_19_en & mem_tin_remain_MPORT_19_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_19_addr] <= mem_tin_remain_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_20_en & mem_tin_remain_MPORT_20_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_20_addr] <= mem_tin_remain_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_21_en & mem_tin_remain_MPORT_21_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_21_addr] <= mem_tin_remain_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_22_en & mem_tin_remain_MPORT_22_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_22_addr] <= mem_tin_remain_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_23_en & mem_tin_remain_MPORT_23_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_23_addr] <= mem_tin_remain_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_24_en & mem_tin_remain_MPORT_24_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_24_addr] <= mem_tin_remain_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_25_en & mem_tin_remain_MPORT_25_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_25_addr] <= mem_tin_remain_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_26_en & mem_tin_remain_MPORT_26_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_26_addr] <= mem_tin_remain_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_27_en & mem_tin_remain_MPORT_27_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_27_addr] <= mem_tin_remain_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_28_en & mem_tin_remain_MPORT_28_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_28_addr] <= mem_tin_remain_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_29_en & mem_tin_remain_MPORT_29_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_29_addr] <= mem_tin_remain_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_30_en & mem_tin_remain_MPORT_30_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_30_addr] <= mem_tin_remain_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_31_en & mem_tin_remain_MPORT_31_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_31_addr] <= mem_tin_remain_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_en & mem_tin_vd_addr_MPORT_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_addr] <= mem_tin_vd_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_1_en & mem_tin_vd_addr_MPORT_1_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_1_addr] <= mem_tin_vd_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_2_en & mem_tin_vd_addr_MPORT_2_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_2_addr] <= mem_tin_vd_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_3_en & mem_tin_vd_addr_MPORT_3_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_3_addr] <= mem_tin_vd_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_4_en & mem_tin_vd_addr_MPORT_4_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_4_addr] <= mem_tin_vd_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_5_en & mem_tin_vd_addr_MPORT_5_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_5_addr] <= mem_tin_vd_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_6_en & mem_tin_vd_addr_MPORT_6_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_6_addr] <= mem_tin_vd_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_7_en & mem_tin_vd_addr_MPORT_7_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_7_addr] <= mem_tin_vd_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_8_en & mem_tin_vd_addr_MPORT_8_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_8_addr] <= mem_tin_vd_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_9_en & mem_tin_vd_addr_MPORT_9_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_9_addr] <= mem_tin_vd_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_10_en & mem_tin_vd_addr_MPORT_10_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_10_addr] <= mem_tin_vd_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_11_en & mem_tin_vd_addr_MPORT_11_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_11_addr] <= mem_tin_vd_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_12_en & mem_tin_vd_addr_MPORT_12_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_12_addr] <= mem_tin_vd_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_13_en & mem_tin_vd_addr_MPORT_13_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_13_addr] <= mem_tin_vd_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_14_en & mem_tin_vd_addr_MPORT_14_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_14_addr] <= mem_tin_vd_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_15_en & mem_tin_vd_addr_MPORT_15_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_15_addr] <= mem_tin_vd_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_16_en & mem_tin_vd_addr_MPORT_16_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_16_addr] <= mem_tin_vd_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_17_en & mem_tin_vd_addr_MPORT_17_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_17_addr] <= mem_tin_vd_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_18_en & mem_tin_vd_addr_MPORT_18_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_18_addr] <= mem_tin_vd_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_19_en & mem_tin_vd_addr_MPORT_19_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_19_addr] <= mem_tin_vd_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_20_en & mem_tin_vd_addr_MPORT_20_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_20_addr] <= mem_tin_vd_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_21_en & mem_tin_vd_addr_MPORT_21_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_21_addr] <= mem_tin_vd_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_22_en & mem_tin_vd_addr_MPORT_22_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_22_addr] <= mem_tin_vd_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_23_en & mem_tin_vd_addr_MPORT_23_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_23_addr] <= mem_tin_vd_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_24_en & mem_tin_vd_addr_MPORT_24_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_24_addr] <= mem_tin_vd_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_25_en & mem_tin_vd_addr_MPORT_25_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_25_addr] <= mem_tin_vd_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_26_en & mem_tin_vd_addr_MPORT_26_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_26_addr] <= mem_tin_vd_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_27_en & mem_tin_vd_addr_MPORT_27_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_27_addr] <= mem_tin_vd_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_28_en & mem_tin_vd_addr_MPORT_28_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_28_addr] <= mem_tin_vd_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_29_en & mem_tin_vd_addr_MPORT_29_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_29_addr] <= mem_tin_vd_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_30_en & mem_tin_vd_addr_MPORT_30_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_30_addr] <= mem_tin_vd_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_31_en & mem_tin_vd_addr_MPORT_31_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_31_addr] <= mem_tin_vd_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_en & mem_tin_vs_valid_MPORT_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_addr] <= mem_tin_vs_valid_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_1_en & mem_tin_vs_valid_MPORT_1_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_1_addr] <= mem_tin_vs_valid_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_2_en & mem_tin_vs_valid_MPORT_2_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_2_addr] <= mem_tin_vs_valid_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_3_en & mem_tin_vs_valid_MPORT_3_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_3_addr] <= mem_tin_vs_valid_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_4_en & mem_tin_vs_valid_MPORT_4_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_4_addr] <= mem_tin_vs_valid_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_5_en & mem_tin_vs_valid_MPORT_5_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_5_addr] <= mem_tin_vs_valid_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_6_en & mem_tin_vs_valid_MPORT_6_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_6_addr] <= mem_tin_vs_valid_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_7_en & mem_tin_vs_valid_MPORT_7_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_7_addr] <= mem_tin_vs_valid_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_8_en & mem_tin_vs_valid_MPORT_8_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_8_addr] <= mem_tin_vs_valid_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_9_en & mem_tin_vs_valid_MPORT_9_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_9_addr] <= mem_tin_vs_valid_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_10_en & mem_tin_vs_valid_MPORT_10_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_10_addr] <= mem_tin_vs_valid_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_11_en & mem_tin_vs_valid_MPORT_11_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_11_addr] <= mem_tin_vs_valid_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_12_en & mem_tin_vs_valid_MPORT_12_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_12_addr] <= mem_tin_vs_valid_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_13_en & mem_tin_vs_valid_MPORT_13_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_13_addr] <= mem_tin_vs_valid_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_14_en & mem_tin_vs_valid_MPORT_14_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_14_addr] <= mem_tin_vs_valid_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_15_en & mem_tin_vs_valid_MPORT_15_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_15_addr] <= mem_tin_vs_valid_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_16_en & mem_tin_vs_valid_MPORT_16_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_16_addr] <= mem_tin_vs_valid_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_17_en & mem_tin_vs_valid_MPORT_17_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_17_addr] <= mem_tin_vs_valid_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_18_en & mem_tin_vs_valid_MPORT_18_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_18_addr] <= mem_tin_vs_valid_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_19_en & mem_tin_vs_valid_MPORT_19_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_19_addr] <= mem_tin_vs_valid_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_20_en & mem_tin_vs_valid_MPORT_20_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_20_addr] <= mem_tin_vs_valid_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_21_en & mem_tin_vs_valid_MPORT_21_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_21_addr] <= mem_tin_vs_valid_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_22_en & mem_tin_vs_valid_MPORT_22_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_22_addr] <= mem_tin_vs_valid_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_23_en & mem_tin_vs_valid_MPORT_23_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_23_addr] <= mem_tin_vs_valid_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_24_en & mem_tin_vs_valid_MPORT_24_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_24_addr] <= mem_tin_vs_valid_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_25_en & mem_tin_vs_valid_MPORT_25_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_25_addr] <= mem_tin_vs_valid_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_26_en & mem_tin_vs_valid_MPORT_26_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_26_addr] <= mem_tin_vs_valid_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_27_en & mem_tin_vs_valid_MPORT_27_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_27_addr] <= mem_tin_vs_valid_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_28_en & mem_tin_vs_valid_MPORT_28_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_28_addr] <= mem_tin_vs_valid_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_29_en & mem_tin_vs_valid_MPORT_29_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_29_addr] <= mem_tin_vs_valid_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_30_en & mem_tin_vs_valid_MPORT_30_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_30_addr] <= mem_tin_vs_valid_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_31_en & mem_tin_vs_valid_MPORT_31_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_31_addr] <= mem_tin_vs_valid_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_en & mem_tin_vs_addr_MPORT_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_addr] <= mem_tin_vs_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_1_en & mem_tin_vs_addr_MPORT_1_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_1_addr] <= mem_tin_vs_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_2_en & mem_tin_vs_addr_MPORT_2_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_2_addr] <= mem_tin_vs_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_3_en & mem_tin_vs_addr_MPORT_3_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_3_addr] <= mem_tin_vs_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_4_en & mem_tin_vs_addr_MPORT_4_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_4_addr] <= mem_tin_vs_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_5_en & mem_tin_vs_addr_MPORT_5_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_5_addr] <= mem_tin_vs_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_6_en & mem_tin_vs_addr_MPORT_6_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_6_addr] <= mem_tin_vs_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_7_en & mem_tin_vs_addr_MPORT_7_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_7_addr] <= mem_tin_vs_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_8_en & mem_tin_vs_addr_MPORT_8_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_8_addr] <= mem_tin_vs_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_9_en & mem_tin_vs_addr_MPORT_9_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_9_addr] <= mem_tin_vs_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_10_en & mem_tin_vs_addr_MPORT_10_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_10_addr] <= mem_tin_vs_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_11_en & mem_tin_vs_addr_MPORT_11_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_11_addr] <= mem_tin_vs_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_12_en & mem_tin_vs_addr_MPORT_12_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_12_addr] <= mem_tin_vs_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_13_en & mem_tin_vs_addr_MPORT_13_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_13_addr] <= mem_tin_vs_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_14_en & mem_tin_vs_addr_MPORT_14_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_14_addr] <= mem_tin_vs_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_15_en & mem_tin_vs_addr_MPORT_15_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_15_addr] <= mem_tin_vs_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_16_en & mem_tin_vs_addr_MPORT_16_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_16_addr] <= mem_tin_vs_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_17_en & mem_tin_vs_addr_MPORT_17_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_17_addr] <= mem_tin_vs_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_18_en & mem_tin_vs_addr_MPORT_18_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_18_addr] <= mem_tin_vs_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_19_en & mem_tin_vs_addr_MPORT_19_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_19_addr] <= mem_tin_vs_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_20_en & mem_tin_vs_addr_MPORT_20_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_20_addr] <= mem_tin_vs_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_21_en & mem_tin_vs_addr_MPORT_21_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_21_addr] <= mem_tin_vs_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_22_en & mem_tin_vs_addr_MPORT_22_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_22_addr] <= mem_tin_vs_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_23_en & mem_tin_vs_addr_MPORT_23_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_23_addr] <= mem_tin_vs_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_24_en & mem_tin_vs_addr_MPORT_24_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_24_addr] <= mem_tin_vs_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_25_en & mem_tin_vs_addr_MPORT_25_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_25_addr] <= mem_tin_vs_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_26_en & mem_tin_vs_addr_MPORT_26_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_26_addr] <= mem_tin_vs_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_27_en & mem_tin_vs_addr_MPORT_27_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_27_addr] <= mem_tin_vs_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_28_en & mem_tin_vs_addr_MPORT_28_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_28_addr] <= mem_tin_vs_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_29_en & mem_tin_vs_addr_MPORT_29_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_29_addr] <= mem_tin_vs_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_30_en & mem_tin_vs_addr_MPORT_30_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_30_addr] <= mem_tin_vs_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_31_en & mem_tin_vs_addr_MPORT_31_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_31_addr] <= mem_tin_vs_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_en & mem_tin_vs_tag_MPORT_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_addr] <= mem_tin_vs_tag_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_1_en & mem_tin_vs_tag_MPORT_1_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_1_addr] <= mem_tin_vs_tag_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_2_en & mem_tin_vs_tag_MPORT_2_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_2_addr] <= mem_tin_vs_tag_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_3_en & mem_tin_vs_tag_MPORT_3_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_3_addr] <= mem_tin_vs_tag_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_4_en & mem_tin_vs_tag_MPORT_4_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_4_addr] <= mem_tin_vs_tag_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_5_en & mem_tin_vs_tag_MPORT_5_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_5_addr] <= mem_tin_vs_tag_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_6_en & mem_tin_vs_tag_MPORT_6_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_6_addr] <= mem_tin_vs_tag_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_7_en & mem_tin_vs_tag_MPORT_7_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_7_addr] <= mem_tin_vs_tag_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_8_en & mem_tin_vs_tag_MPORT_8_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_8_addr] <= mem_tin_vs_tag_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_9_en & mem_tin_vs_tag_MPORT_9_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_9_addr] <= mem_tin_vs_tag_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_10_en & mem_tin_vs_tag_MPORT_10_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_10_addr] <= mem_tin_vs_tag_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_11_en & mem_tin_vs_tag_MPORT_11_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_11_addr] <= mem_tin_vs_tag_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_12_en & mem_tin_vs_tag_MPORT_12_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_12_addr] <= mem_tin_vs_tag_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_13_en & mem_tin_vs_tag_MPORT_13_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_13_addr] <= mem_tin_vs_tag_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_14_en & mem_tin_vs_tag_MPORT_14_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_14_addr] <= mem_tin_vs_tag_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_15_en & mem_tin_vs_tag_MPORT_15_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_15_addr] <= mem_tin_vs_tag_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_16_en & mem_tin_vs_tag_MPORT_16_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_16_addr] <= mem_tin_vs_tag_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_17_en & mem_tin_vs_tag_MPORT_17_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_17_addr] <= mem_tin_vs_tag_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_18_en & mem_tin_vs_tag_MPORT_18_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_18_addr] <= mem_tin_vs_tag_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_19_en & mem_tin_vs_tag_MPORT_19_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_19_addr] <= mem_tin_vs_tag_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_20_en & mem_tin_vs_tag_MPORT_20_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_20_addr] <= mem_tin_vs_tag_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_21_en & mem_tin_vs_tag_MPORT_21_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_21_addr] <= mem_tin_vs_tag_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_22_en & mem_tin_vs_tag_MPORT_22_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_22_addr] <= mem_tin_vs_tag_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_23_en & mem_tin_vs_tag_MPORT_23_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_23_addr] <= mem_tin_vs_tag_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_24_en & mem_tin_vs_tag_MPORT_24_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_24_addr] <= mem_tin_vs_tag_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_25_en & mem_tin_vs_tag_MPORT_25_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_25_addr] <= mem_tin_vs_tag_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_26_en & mem_tin_vs_tag_MPORT_26_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_26_addr] <= mem_tin_vs_tag_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_27_en & mem_tin_vs_tag_MPORT_27_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_27_addr] <= mem_tin_vs_tag_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_28_en & mem_tin_vs_tag_MPORT_28_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_28_addr] <= mem_tin_vs_tag_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_29_en & mem_tin_vs_tag_MPORT_29_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_29_addr] <= mem_tin_vs_tag_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_30_en & mem_tin_vs_tag_MPORT_30_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_30_addr] <= mem_tin_vs_tag_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_31_en & mem_tin_vs_tag_MPORT_31_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_31_addr] <= mem_tin_vs_tag_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_en & mem_tin_quad_MPORT_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_addr] <= mem_tin_quad_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_1_en & mem_tin_quad_MPORT_1_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_1_addr] <= mem_tin_quad_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_2_en & mem_tin_quad_MPORT_2_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_2_addr] <= mem_tin_quad_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_3_en & mem_tin_quad_MPORT_3_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_3_addr] <= mem_tin_quad_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_4_en & mem_tin_quad_MPORT_4_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_4_addr] <= mem_tin_quad_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_5_en & mem_tin_quad_MPORT_5_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_5_addr] <= mem_tin_quad_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_6_en & mem_tin_quad_MPORT_6_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_6_addr] <= mem_tin_quad_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_7_en & mem_tin_quad_MPORT_7_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_7_addr] <= mem_tin_quad_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_8_en & mem_tin_quad_MPORT_8_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_8_addr] <= mem_tin_quad_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_9_en & mem_tin_quad_MPORT_9_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_9_addr] <= mem_tin_quad_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_10_en & mem_tin_quad_MPORT_10_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_10_addr] <= mem_tin_quad_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_11_en & mem_tin_quad_MPORT_11_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_11_addr] <= mem_tin_quad_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_12_en & mem_tin_quad_MPORT_12_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_12_addr] <= mem_tin_quad_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_13_en & mem_tin_quad_MPORT_13_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_13_addr] <= mem_tin_quad_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_14_en & mem_tin_quad_MPORT_14_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_14_addr] <= mem_tin_quad_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_15_en & mem_tin_quad_MPORT_15_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_15_addr] <= mem_tin_quad_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_16_en & mem_tin_quad_MPORT_16_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_16_addr] <= mem_tin_quad_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_17_en & mem_tin_quad_MPORT_17_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_17_addr] <= mem_tin_quad_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_18_en & mem_tin_quad_MPORT_18_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_18_addr] <= mem_tin_quad_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_19_en & mem_tin_quad_MPORT_19_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_19_addr] <= mem_tin_quad_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_20_en & mem_tin_quad_MPORT_20_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_20_addr] <= mem_tin_quad_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_21_en & mem_tin_quad_MPORT_21_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_21_addr] <= mem_tin_quad_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_22_en & mem_tin_quad_MPORT_22_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_22_addr] <= mem_tin_quad_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_23_en & mem_tin_quad_MPORT_23_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_23_addr] <= mem_tin_quad_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_24_en & mem_tin_quad_MPORT_24_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_24_addr] <= mem_tin_quad_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_25_en & mem_tin_quad_MPORT_25_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_25_addr] <= mem_tin_quad_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_26_en & mem_tin_quad_MPORT_26_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_26_addr] <= mem_tin_quad_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_27_en & mem_tin_quad_MPORT_27_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_27_addr] <= mem_tin_quad_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_28_en & mem_tin_quad_MPORT_28_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_28_addr] <= mem_tin_quad_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_29_en & mem_tin_quad_MPORT_29_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_29_addr] <= mem_tin_quad_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_30_en & mem_tin_quad_MPORT_30_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_30_addr] <= mem_tin_quad_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_31_en & mem_tin_quad_MPORT_31_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_31_addr] <= mem_tin_quad_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_en & mem_tin_last_MPORT_mask) begin
- mem_tin_last[mem_tin_last_MPORT_addr] <= mem_tin_last_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_1_en & mem_tin_last_MPORT_1_mask) begin
- mem_tin_last[mem_tin_last_MPORT_1_addr] <= mem_tin_last_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_2_en & mem_tin_last_MPORT_2_mask) begin
- mem_tin_last[mem_tin_last_MPORT_2_addr] <= mem_tin_last_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_3_en & mem_tin_last_MPORT_3_mask) begin
- mem_tin_last[mem_tin_last_MPORT_3_addr] <= mem_tin_last_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_4_en & mem_tin_last_MPORT_4_mask) begin
- mem_tin_last[mem_tin_last_MPORT_4_addr] <= mem_tin_last_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_5_en & mem_tin_last_MPORT_5_mask) begin
- mem_tin_last[mem_tin_last_MPORT_5_addr] <= mem_tin_last_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_6_en & mem_tin_last_MPORT_6_mask) begin
- mem_tin_last[mem_tin_last_MPORT_6_addr] <= mem_tin_last_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_7_en & mem_tin_last_MPORT_7_mask) begin
- mem_tin_last[mem_tin_last_MPORT_7_addr] <= mem_tin_last_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_8_en & mem_tin_last_MPORT_8_mask) begin
- mem_tin_last[mem_tin_last_MPORT_8_addr] <= mem_tin_last_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_9_en & mem_tin_last_MPORT_9_mask) begin
- mem_tin_last[mem_tin_last_MPORT_9_addr] <= mem_tin_last_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_10_en & mem_tin_last_MPORT_10_mask) begin
- mem_tin_last[mem_tin_last_MPORT_10_addr] <= mem_tin_last_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_11_en & mem_tin_last_MPORT_11_mask) begin
- mem_tin_last[mem_tin_last_MPORT_11_addr] <= mem_tin_last_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_12_en & mem_tin_last_MPORT_12_mask) begin
- mem_tin_last[mem_tin_last_MPORT_12_addr] <= mem_tin_last_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_13_en & mem_tin_last_MPORT_13_mask) begin
- mem_tin_last[mem_tin_last_MPORT_13_addr] <= mem_tin_last_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_14_en & mem_tin_last_MPORT_14_mask) begin
- mem_tin_last[mem_tin_last_MPORT_14_addr] <= mem_tin_last_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_15_en & mem_tin_last_MPORT_15_mask) begin
- mem_tin_last[mem_tin_last_MPORT_15_addr] <= mem_tin_last_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_16_en & mem_tin_last_MPORT_16_mask) begin
- mem_tin_last[mem_tin_last_MPORT_16_addr] <= mem_tin_last_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_17_en & mem_tin_last_MPORT_17_mask) begin
- mem_tin_last[mem_tin_last_MPORT_17_addr] <= mem_tin_last_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_18_en & mem_tin_last_MPORT_18_mask) begin
- mem_tin_last[mem_tin_last_MPORT_18_addr] <= mem_tin_last_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_19_en & mem_tin_last_MPORT_19_mask) begin
- mem_tin_last[mem_tin_last_MPORT_19_addr] <= mem_tin_last_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_20_en & mem_tin_last_MPORT_20_mask) begin
- mem_tin_last[mem_tin_last_MPORT_20_addr] <= mem_tin_last_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_21_en & mem_tin_last_MPORT_21_mask) begin
- mem_tin_last[mem_tin_last_MPORT_21_addr] <= mem_tin_last_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_22_en & mem_tin_last_MPORT_22_mask) begin
- mem_tin_last[mem_tin_last_MPORT_22_addr] <= mem_tin_last_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_23_en & mem_tin_last_MPORT_23_mask) begin
- mem_tin_last[mem_tin_last_MPORT_23_addr] <= mem_tin_last_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_24_en & mem_tin_last_MPORT_24_mask) begin
- mem_tin_last[mem_tin_last_MPORT_24_addr] <= mem_tin_last_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_25_en & mem_tin_last_MPORT_25_mask) begin
- mem_tin_last[mem_tin_last_MPORT_25_addr] <= mem_tin_last_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_26_en & mem_tin_last_MPORT_26_mask) begin
- mem_tin_last[mem_tin_last_MPORT_26_addr] <= mem_tin_last_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_27_en & mem_tin_last_MPORT_27_mask) begin
- mem_tin_last[mem_tin_last_MPORT_27_addr] <= mem_tin_last_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_28_en & mem_tin_last_MPORT_28_mask) begin
- mem_tin_last[mem_tin_last_MPORT_28_addr] <= mem_tin_last_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_29_en & mem_tin_last_MPORT_29_mask) begin
- mem_tin_last[mem_tin_last_MPORT_29_addr] <= mem_tin_last_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_30_en & mem_tin_last_MPORT_30_mask) begin
- mem_tin_last[mem_tin_last_MPORT_30_addr] <= mem_tin_last_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_last_MPORT_31_en & mem_tin_last_MPORT_31_mask) begin
- mem_tin_last[mem_tin_last_MPORT_31_addr] <= mem_tin_last_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_en & mem_m_MPORT_mask) begin
- mem_m[mem_m_MPORT_addr] <= mem_m_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_1_en & mem_m_MPORT_1_mask) begin
- mem_m[mem_m_MPORT_1_addr] <= mem_m_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_2_en & mem_m_MPORT_2_mask) begin
- mem_m[mem_m_MPORT_2_addr] <= mem_m_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_3_en & mem_m_MPORT_3_mask) begin
- mem_m[mem_m_MPORT_3_addr] <= mem_m_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_4_en & mem_m_MPORT_4_mask) begin
- mem_m[mem_m_MPORT_4_addr] <= mem_m_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_5_en & mem_m_MPORT_5_mask) begin
- mem_m[mem_m_MPORT_5_addr] <= mem_m_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_6_en & mem_m_MPORT_6_mask) begin
- mem_m[mem_m_MPORT_6_addr] <= mem_m_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_7_en & mem_m_MPORT_7_mask) begin
- mem_m[mem_m_MPORT_7_addr] <= mem_m_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_8_en & mem_m_MPORT_8_mask) begin
- mem_m[mem_m_MPORT_8_addr] <= mem_m_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_9_en & mem_m_MPORT_9_mask) begin
- mem_m[mem_m_MPORT_9_addr] <= mem_m_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_10_en & mem_m_MPORT_10_mask) begin
- mem_m[mem_m_MPORT_10_addr] <= mem_m_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_11_en & mem_m_MPORT_11_mask) begin
- mem_m[mem_m_MPORT_11_addr] <= mem_m_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_12_en & mem_m_MPORT_12_mask) begin
- mem_m[mem_m_MPORT_12_addr] <= mem_m_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_13_en & mem_m_MPORT_13_mask) begin
- mem_m[mem_m_MPORT_13_addr] <= mem_m_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_14_en & mem_m_MPORT_14_mask) begin
- mem_m[mem_m_MPORT_14_addr] <= mem_m_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_15_en & mem_m_MPORT_15_mask) begin
- mem_m[mem_m_MPORT_15_addr] <= mem_m_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_16_en & mem_m_MPORT_16_mask) begin
- mem_m[mem_m_MPORT_16_addr] <= mem_m_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_17_en & mem_m_MPORT_17_mask) begin
- mem_m[mem_m_MPORT_17_addr] <= mem_m_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_18_en & mem_m_MPORT_18_mask) begin
- mem_m[mem_m_MPORT_18_addr] <= mem_m_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_19_en & mem_m_MPORT_19_mask) begin
- mem_m[mem_m_MPORT_19_addr] <= mem_m_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_20_en & mem_m_MPORT_20_mask) begin
- mem_m[mem_m_MPORT_20_addr] <= mem_m_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_21_en & mem_m_MPORT_21_mask) begin
- mem_m[mem_m_MPORT_21_addr] <= mem_m_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_22_en & mem_m_MPORT_22_mask) begin
- mem_m[mem_m_MPORT_22_addr] <= mem_m_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_23_en & mem_m_MPORT_23_mask) begin
- mem_m[mem_m_MPORT_23_addr] <= mem_m_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_24_en & mem_m_MPORT_24_mask) begin
- mem_m[mem_m_MPORT_24_addr] <= mem_m_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_25_en & mem_m_MPORT_25_mask) begin
- mem_m[mem_m_MPORT_25_addr] <= mem_m_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_26_en & mem_m_MPORT_26_mask) begin
- mem_m[mem_m_MPORT_26_addr] <= mem_m_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_27_en & mem_m_MPORT_27_mask) begin
- mem_m[mem_m_MPORT_27_addr] <= mem_m_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_28_en & mem_m_MPORT_28_mask) begin
- mem_m[mem_m_MPORT_28_addr] <= mem_m_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_29_en & mem_m_MPORT_29_mask) begin
- mem_m[mem_m_MPORT_29_addr] <= mem_m_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_30_en & mem_m_MPORT_30_mask) begin
- mem_m[mem_m_MPORT_30_addr] <= mem_m_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_31_en & mem_m_MPORT_31_mask) begin
- mem_m[mem_m_MPORT_31_addr] <= mem_m_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(mcount <= 4'h8)) begin
- $fatal; // @[Fifo4e.scala 137:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(mcount <= 4'h8)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Fifo4e.scala:137 assert(mcount <= n.U)\n"); // @[Fifo4e.scala 137:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in0pos <= 3'h0; // @[Fifo4e.scala 68:12]
- end else if (ivalid) begin // @[Fifo4e.scala 45:23]
- in0pos <= in0pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in1pos <= 3'h1; // @[Fifo4e.scala 69:12]
- end else if (ivalid) begin // @[Fifo4e.scala 46:23]
- in1pos <= in1pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in2pos <= 3'h2; // @[Fifo4e.scala 70:12]
- end else if (ivalid) begin // @[Fifo4e.scala 47:23]
- in2pos <= in2pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in3pos <= 3'h3; // @[Fifo4e.scala 71:12]
- end else if (ivalid) begin // @[Fifo4e.scala 48:23]
- in3pos <= in3pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 74:17]
- outpos <= 3'h0; // @[Fifo4e.scala 75:12]
- end else if (dec) begin // @[Fifo4e.scala 49:23]
- outpos <= outpos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 81:27]
- mcount <= 4'h0; // @[Fifo4e.scala 83:12]
- end else if (ivalid | dec) begin // @[Fifo4e.scala 50:23]
- mcount <= nxtcount;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 126:69]
- active <= 8'h0; // @[Fifo4e.scala 127:12]
- end else if (_T) begin // @[Fifo4e.scala 118:23]
- active <= _active_T_2;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_MEM_INIT
- _RAND_0 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_op[initvar] = _RAND_0[6:0];
- _RAND_1 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_addr[initvar] = _RAND_1[31:0];
- _RAND_2 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_offset[initvar] = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_remain[initvar] = _RAND_3[7:0];
- _RAND_4 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vd_addr[initvar] = _RAND_4[5:0];
- _RAND_5 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vs_valid[initvar] = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vs_addr[initvar] = _RAND_6[5:0];
- _RAND_7 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vs_tag[initvar] = _RAND_7[3:0];
- _RAND_8 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_quad[initvar] = _RAND_8[1:0];
- _RAND_9 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_last[initvar] = _RAND_9[0:0];
- _RAND_10 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_m[initvar] = _RAND_10[0:0];
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- _RAND_11 = {1{`RANDOM}};
- in0pos = _RAND_11[2:0];
- _RAND_12 = {1{`RANDOM}};
- in1pos = _RAND_12[2:0];
- _RAND_13 = {1{`RANDOM}};
- in2pos = _RAND_13[2:0];
- _RAND_14 = {1{`RANDOM}};
- in3pos = _RAND_14[2:0];
- _RAND_15 = {1{`RANDOM}};
- outpos = _RAND_15[2:0];
- _RAND_16 = {1{`RANDOM}};
- mcount = _RAND_16[3:0];
- _RAND_17 = {1{`RANDOM}};
- active = _RAND_17[7:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- in0pos = 3'h0;
- end
- if (reset) begin
- in1pos = 3'h1;
- end
- if (reset) begin
- in2pos = 3'h2;
- end
- if (reset) begin
- in3pos = 3'h3;
- end
- if (reset) begin
- outpos = 3'h0;
- end
- if (reset) begin
- mcount = 4'h0;
- end
- if (reset) begin
- active = 8'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VCmdq_3(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_op,
- input [2:0] io_in_bits_0_bits_f2,
- input [2:0] io_in_bits_0_bits_sz,
- input io_in_bits_0_bits_m,
- input io_in_bits_0_bits_vd_valid,
- input [5:0] io_in_bits_0_bits_vd_addr,
- input io_in_bits_0_bits_vs_valid,
- input [5:0] io_in_bits_0_bits_vs_addr,
- input [3:0] io_in_bits_0_bits_vs_tag,
- input [31:0] io_in_bits_0_bits_sv_addr,
- input [31:0] io_in_bits_0_bits_sv_data,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_op,
- input [2:0] io_in_bits_1_bits_f2,
- input [2:0] io_in_bits_1_bits_sz,
- input io_in_bits_1_bits_m,
- input io_in_bits_1_bits_vd_valid,
- input [5:0] io_in_bits_1_bits_vd_addr,
- input io_in_bits_1_bits_vs_valid,
- input [5:0] io_in_bits_1_bits_vs_addr,
- input [3:0] io_in_bits_1_bits_vs_tag,
- input [31:0] io_in_bits_1_bits_sv_addr,
- input [31:0] io_in_bits_1_bits_sv_data,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_op,
- input [2:0] io_in_bits_2_bits_f2,
- input [2:0] io_in_bits_2_bits_sz,
- input io_in_bits_2_bits_m,
- input io_in_bits_2_bits_vd_valid,
- input [5:0] io_in_bits_2_bits_vd_addr,
- input io_in_bits_2_bits_vs_valid,
- input [5:0] io_in_bits_2_bits_vs_addr,
- input [3:0] io_in_bits_2_bits_vs_tag,
- input [31:0] io_in_bits_2_bits_sv_addr,
- input [31:0] io_in_bits_2_bits_sv_data,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_op,
- input [2:0] io_in_bits_3_bits_f2,
- input [2:0] io_in_bits_3_bits_sz,
- input io_in_bits_3_bits_m,
- input io_in_bits_3_bits_vd_valid,
- input [5:0] io_in_bits_3_bits_vd_addr,
- input io_in_bits_3_bits_vs_valid,
- input [5:0] io_in_bits_3_bits_vs_addr,
- input [3:0] io_in_bits_3_bits_vs_tag,
- input [31:0] io_in_bits_3_bits_sv_addr,
- input [31:0] io_in_bits_3_bits_sv_data,
- input io_out_ready,
- output io_out_valid,
- output [6:0] io_out_bits_op,
- output [31:0] io_out_bits_addr,
- output [7:0] io_out_bits_remain,
- output [5:0] io_out_bits_vd_addr,
- output io_out_bits_vs_valid,
- output [5:0] io_out_bits_vs_addr,
- output [3:0] io_out_bits_vs_tag,
- output [1:0] io_out_bits_quad,
- output io_out_bits_last,
- output [63:0] io_active
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [63:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
-`endif // RANDOMIZE_REG_INIT
- wire f_clock; // @[Fifo4e.scala 24:11]
- wire f_reset; // @[Fifo4e.scala 24:11]
- wire f_io_in_ready; // @[Fifo4e.scala 24:11]
- wire f_io_in_valid; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_0_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_0_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_0_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [7:0] f_io_in_bits_0_bits_tin_remain; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_0_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_tin_last; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_1_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_1_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_1_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [7:0] f_io_in_bits_1_bits_tin_remain; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_1_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_tin_last; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_2_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_2_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_2_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [7:0] f_io_in_bits_2_bits_tin_remain; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_2_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_tin_last; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_3_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_3_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_3_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [7:0] f_io_in_bits_3_bits_tin_remain; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_3_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_tin_last; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_out_ready; // @[Fifo4e.scala 24:11]
- wire f_io_out_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_out_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_out_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_out_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [7:0] f_io_out_bits_tin_remain; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_out_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire [1:0] f_io_out_bits_tin_quad; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_tin_last; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_0_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_1_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_2_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_3_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_4_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_5_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_6_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_7_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_bits_m; // @[Fifo4e.scala 24:11]
- reg [63:0] active; // @[VCmdq.scala 49:23]
- reg valid; // @[VCmdq.scala 51:22]
- reg [6:0] value_tin_op; // @[VCmdq.scala 53:18]
- reg [31:0] value_tin_addr; // @[VCmdq.scala 53:18]
- reg [31:0] value_tin_offset; // @[VCmdq.scala 53:18]
- reg [7:0] value_tin_remain; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_vd_addr; // @[VCmdq.scala 53:18]
- reg value_tin_vs_valid; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_vs_addr; // @[VCmdq.scala 53:18]
- reg [3:0] value_tin_vs_tag; // @[VCmdq.scala 53:18]
- reg [1:0] value_tin_quad; // @[VCmdq.scala 53:18]
- reg value_tin_last; // @[VCmdq.scala 53:18]
- reg value_m; // @[VCmdq.scala 53:18]
- reg [4:0] step; // @[VCmdq.scala 58:21]
- wire _T = ~valid; // @[VLdSt.scala 138:12]
- wire _T_5 = value_tin_op == 7'h4; // @[VLdSt.scala 138:70]
- wire _T_8 = ~reset; // @[VLdSt.scala 138:11]
- wire [7:0] fmaxvlb = _T_5 ? 8'h8 : 8'h20; // @[VLdSt.scala 144:22]
- wire _outlast1_T = ~value_m; // @[VLdSt.scala 146:20]
- wire _outlast1_T_1 = step == 5'h2; // @[VLdSt.scala 146:31]
- wire outlast1 = ~value_m | step == 5'h2; // @[VLdSt.scala 146:23]
- wire outlast2 = value_m ? step == 5'he : _outlast1_T_1; // @[VLdSt.scala 147:23]
- wire outlast = _T_5 ? outlast2 : outlast1; // @[VLdSt.scala 148:22]
- wire _last1_T_1 = step == 5'h3; // @[VLdSt.scala 150:28]
- wire last1 = _outlast1_T | step == 5'h3; // @[VLdSt.scala 150:20]
- wire last2 = value_m ? step == 5'hf : _last1_T_1; // @[VLdSt.scala 151:20]
- wire last = _T_5 ? last2 : last1; // @[VLdSt.scala 152:19]
- wire _out_vd_addr_T_2 = _T_5 & step[1:0] != 2'h3; // @[VLdSt.scala 156:29]
- wire [5:0] _out_vd_addr_T_4 = value_tin_vd_addr + 6'h1; // @[VLdSt.scala 156:74]
- wire [5:0] tin_vd_addr = _T_5 & step[1:0] != 2'h3 ? value_tin_vd_addr : _out_vd_addr_T_4; // @[VLdSt.scala 156:23]
- wire [5:0] _out_vs_addr_T_4 = value_tin_vs_addr + 6'h1; // @[VLdSt.scala 157:74]
- wire [5:0] tin_vs_addr = _out_vd_addr_T_2 ? value_tin_vs_addr : _out_vs_addr_T_4; // @[VLdSt.scala 157:23]
- wire [31:0] tin_addr = value_tin_addr + value_tin_offset; // @[VLdSt.scala 159:27]
- wire [7:0] _out_remain_T_2 = value_tin_remain - fmaxvlb; // @[VLdSt.scala 160:60]
- wire [7:0] tin_remain = value_tin_remain <= fmaxvlb ? 8'h0 : _out_remain_T_2; // @[VLdSt.scala 160:22]
- wire [4:0] _out_quad_T_2 = step + 5'h1; // @[VLdSt.scala 164:46]
- wire [4:0] _out_quad_T_3 = _T_5 ? _out_quad_T_2 : 5'h0; // @[VLdSt.scala 164:20]
- wire f_io_in_bits_0_bits_tin_stride = io_in_bits_0_bits_f2[1]; // @[VLdSt.scala 104:23]
- wire f_io_in_bits_0_bits_tin_length = io_in_bits_0_bits_f2[0]; // @[VLdSt.scala 105:23]
- wire [1:0] _f_io_in_bits_0_bits_tin_T_3 = io_in_bits_0_bits_sz[1] + io_in_bits_0_bits_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_63 = {{1'd0}, io_in_bits_0_bits_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _f_io_in_bits_0_bits_tin_T_5 = _GEN_63 + _f_io_in_bits_0_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_0_bits_tin_T_13 = io_in_bits_0_bits_vd_valid | ~io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 107:50]
- wire _f_io_in_bits_0_bits_tin_T_19 = io_in_bits_0_bits_op == 7'h4; // @[VLdSt.scala 108:20]
- wire [7:0] f_io_in_bits_0_bits_tin_limit = io_in_bits_0_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 111:20]
- wire [31:0] _f_io_in_bits_0_bits_tin_data_T_1 = io_in_bits_0_bits_sz[0] ? io_in_bits_0_bits_sv_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _f_io_in_bits_0_bits_tin_data_T_3 = {io_in_bits_0_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _f_io_in_bits_0_bits_tin_data_T_4 = io_in_bits_0_bits_sz[1] ? _f_io_in_bits_0_bits_tin_data_T_3 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_64 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_1}; // @[VLdSt.scala 113:44]
- wire [32:0] _f_io_in_bits_0_bits_tin_data_T_5 = _GEN_64 | _f_io_in_bits_0_bits_tin_data_T_4; // @[VLdSt.scala 113:44]
- wire [33:0] _f_io_in_bits_0_bits_tin_data_T_7 = {io_in_bits_0_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _f_io_in_bits_0_bits_tin_data_T_8 = io_in_bits_0_bits_sz[2] ? _f_io_in_bits_0_bits_tin_data_T_7 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_65 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_5}; // @[VLdSt.scala 114:59]
- wire [33:0] f_io_in_bits_0_bits_tin_data = _GEN_65 | _f_io_in_bits_0_bits_tin_data_T_8; // @[VLdSt.scala 114:59]
- wire [33:0] _GEN_66 = {{26'd0}, f_io_in_bits_0_bits_tin_limit}; // @[VLdSt.scala 118:28]
- wire [33:0] _f_io_in_bits_0_bits_tin_remain1_T_1 = f_io_in_bits_0_bits_tin_data > _GEN_66 ? {{26'd0},
- f_io_in_bits_0_bits_tin_limit} : f_io_in_bits_0_bits_tin_data; // @[VLdSt.scala 118:22]
- wire [7:0] f_io_in_bits_0_bits_tin_remain1 = _f_io_in_bits_0_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 118:49]
- wire [7:0] _f_io_in_bits_0_bits_tin_out_offset_T_3 = _f_io_in_bits_0_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 126:46]
- wire f_io_in_bits_1_bits_tin_stride = io_in_bits_1_bits_f2[1]; // @[VLdSt.scala 104:23]
- wire f_io_in_bits_1_bits_tin_length = io_in_bits_1_bits_f2[0]; // @[VLdSt.scala 105:23]
- wire [1:0] _f_io_in_bits_1_bits_tin_T_3 = io_in_bits_1_bits_sz[1] + io_in_bits_1_bits_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_67 = {{1'd0}, io_in_bits_1_bits_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _f_io_in_bits_1_bits_tin_T_5 = _GEN_67 + _f_io_in_bits_1_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_1_bits_tin_T_13 = io_in_bits_1_bits_vd_valid | ~io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 107:50]
- wire _f_io_in_bits_1_bits_tin_T_19 = io_in_bits_1_bits_op == 7'h4; // @[VLdSt.scala 108:20]
- wire [7:0] f_io_in_bits_1_bits_tin_limit = io_in_bits_1_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 111:20]
- wire [31:0] _f_io_in_bits_1_bits_tin_data_T_1 = io_in_bits_1_bits_sz[0] ? io_in_bits_1_bits_sv_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _f_io_in_bits_1_bits_tin_data_T_3 = {io_in_bits_1_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _f_io_in_bits_1_bits_tin_data_T_4 = io_in_bits_1_bits_sz[1] ? _f_io_in_bits_1_bits_tin_data_T_3 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_68 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_1}; // @[VLdSt.scala 113:44]
- wire [32:0] _f_io_in_bits_1_bits_tin_data_T_5 = _GEN_68 | _f_io_in_bits_1_bits_tin_data_T_4; // @[VLdSt.scala 113:44]
- wire [33:0] _f_io_in_bits_1_bits_tin_data_T_7 = {io_in_bits_1_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _f_io_in_bits_1_bits_tin_data_T_8 = io_in_bits_1_bits_sz[2] ? _f_io_in_bits_1_bits_tin_data_T_7 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_69 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_5}; // @[VLdSt.scala 114:59]
- wire [33:0] f_io_in_bits_1_bits_tin_data = _GEN_69 | _f_io_in_bits_1_bits_tin_data_T_8; // @[VLdSt.scala 114:59]
- wire [33:0] _GEN_70 = {{26'd0}, f_io_in_bits_1_bits_tin_limit}; // @[VLdSt.scala 118:28]
- wire [33:0] _f_io_in_bits_1_bits_tin_remain1_T_1 = f_io_in_bits_1_bits_tin_data > _GEN_70 ? {{26'd0},
- f_io_in_bits_1_bits_tin_limit} : f_io_in_bits_1_bits_tin_data; // @[VLdSt.scala 118:22]
- wire [7:0] f_io_in_bits_1_bits_tin_remain1 = _f_io_in_bits_1_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 118:49]
- wire [7:0] _f_io_in_bits_1_bits_tin_out_offset_T_3 = _f_io_in_bits_1_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 126:46]
- wire f_io_in_bits_2_bits_tin_stride = io_in_bits_2_bits_f2[1]; // @[VLdSt.scala 104:23]
- wire f_io_in_bits_2_bits_tin_length = io_in_bits_2_bits_f2[0]; // @[VLdSt.scala 105:23]
- wire [1:0] _f_io_in_bits_2_bits_tin_T_3 = io_in_bits_2_bits_sz[1] + io_in_bits_2_bits_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_71 = {{1'd0}, io_in_bits_2_bits_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _f_io_in_bits_2_bits_tin_T_5 = _GEN_71 + _f_io_in_bits_2_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_2_bits_tin_T_13 = io_in_bits_2_bits_vd_valid | ~io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 107:50]
- wire _f_io_in_bits_2_bits_tin_T_19 = io_in_bits_2_bits_op == 7'h4; // @[VLdSt.scala 108:20]
- wire [7:0] f_io_in_bits_2_bits_tin_limit = io_in_bits_2_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 111:20]
- wire [31:0] _f_io_in_bits_2_bits_tin_data_T_1 = io_in_bits_2_bits_sz[0] ? io_in_bits_2_bits_sv_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _f_io_in_bits_2_bits_tin_data_T_3 = {io_in_bits_2_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _f_io_in_bits_2_bits_tin_data_T_4 = io_in_bits_2_bits_sz[1] ? _f_io_in_bits_2_bits_tin_data_T_3 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_72 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_1}; // @[VLdSt.scala 113:44]
- wire [32:0] _f_io_in_bits_2_bits_tin_data_T_5 = _GEN_72 | _f_io_in_bits_2_bits_tin_data_T_4; // @[VLdSt.scala 113:44]
- wire [33:0] _f_io_in_bits_2_bits_tin_data_T_7 = {io_in_bits_2_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _f_io_in_bits_2_bits_tin_data_T_8 = io_in_bits_2_bits_sz[2] ? _f_io_in_bits_2_bits_tin_data_T_7 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_73 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_5}; // @[VLdSt.scala 114:59]
- wire [33:0] f_io_in_bits_2_bits_tin_data = _GEN_73 | _f_io_in_bits_2_bits_tin_data_T_8; // @[VLdSt.scala 114:59]
- wire [33:0] _GEN_74 = {{26'd0}, f_io_in_bits_2_bits_tin_limit}; // @[VLdSt.scala 118:28]
- wire [33:0] _f_io_in_bits_2_bits_tin_remain1_T_1 = f_io_in_bits_2_bits_tin_data > _GEN_74 ? {{26'd0},
- f_io_in_bits_2_bits_tin_limit} : f_io_in_bits_2_bits_tin_data; // @[VLdSt.scala 118:22]
- wire [7:0] f_io_in_bits_2_bits_tin_remain1 = _f_io_in_bits_2_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 118:49]
- wire [7:0] _f_io_in_bits_2_bits_tin_out_offset_T_3 = _f_io_in_bits_2_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 126:46]
- wire f_io_in_bits_3_bits_tin_stride = io_in_bits_3_bits_f2[1]; // @[VLdSt.scala 104:23]
- wire f_io_in_bits_3_bits_tin_length = io_in_bits_3_bits_f2[0]; // @[VLdSt.scala 105:23]
- wire [1:0] _f_io_in_bits_3_bits_tin_T_3 = io_in_bits_3_bits_sz[1] + io_in_bits_3_bits_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_75 = {{1'd0}, io_in_bits_3_bits_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _f_io_in_bits_3_bits_tin_T_5 = _GEN_75 + _f_io_in_bits_3_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_3_bits_tin_T_13 = io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 107:50]
- wire _f_io_in_bits_3_bits_tin_T_19 = io_in_bits_3_bits_op == 7'h4; // @[VLdSt.scala 108:20]
- wire [7:0] f_io_in_bits_3_bits_tin_limit = io_in_bits_3_bits_m ? 8'h80 : 8'h20; // @[VLdSt.scala 111:20]
- wire [31:0] _f_io_in_bits_3_bits_tin_data_T_1 = io_in_bits_3_bits_sz[0] ? io_in_bits_3_bits_sv_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _f_io_in_bits_3_bits_tin_data_T_3 = {io_in_bits_3_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _f_io_in_bits_3_bits_tin_data_T_4 = io_in_bits_3_bits_sz[1] ? _f_io_in_bits_3_bits_tin_data_T_3 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_76 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_1}; // @[VLdSt.scala 113:44]
- wire [32:0] _f_io_in_bits_3_bits_tin_data_T_5 = _GEN_76 | _f_io_in_bits_3_bits_tin_data_T_4; // @[VLdSt.scala 113:44]
- wire [33:0] _f_io_in_bits_3_bits_tin_data_T_7 = {io_in_bits_3_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _f_io_in_bits_3_bits_tin_data_T_8 = io_in_bits_3_bits_sz[2] ? _f_io_in_bits_3_bits_tin_data_T_7 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_77 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_5}; // @[VLdSt.scala 114:59]
- wire [33:0] f_io_in_bits_3_bits_tin_data = _GEN_77 | _f_io_in_bits_3_bits_tin_data_T_8; // @[VLdSt.scala 114:59]
- wire [33:0] _GEN_78 = {{26'd0}, f_io_in_bits_3_bits_tin_limit}; // @[VLdSt.scala 118:28]
- wire [33:0] _f_io_in_bits_3_bits_tin_remain1_T_1 = f_io_in_bits_3_bits_tin_data > _GEN_78 ? {{26'd0},
- f_io_in_bits_3_bits_tin_limit} : f_io_in_bits_3_bits_tin_data; // @[VLdSt.scala 118:22]
- wire [7:0] f_io_in_bits_3_bits_tin_remain1 = _f_io_in_bits_3_bits_tin_remain1_T_1[7:0]; // @[VLdSt.scala 118:49]
- wire [7:0] _f_io_in_bits_3_bits_tin_out_offset_T_3 = _f_io_in_bits_3_bits_tin_T_19 ? 8'h8 : 8'h20; // @[VLdSt.scala 126:46]
- wire _T_11 = io_out_valid & io_out_ready; // @[VCmdq.scala 81:29]
- wire _T_12 = ~last; // @[VCmdq.scala 82:11]
- wire _GEN_1 = ~last & outlast; // @[VCmdq.scala 82:18 84:17 90:17]
- wire [1:0] tin_quad = _out_quad_T_3[1:0]; // @[VLdSt.scala 140:19 164:14]
- wire _GEN_5 = ~last & value_tin_vs_valid; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_14 = ~last & value_m; // @[VCmdq.scala 82:18 85:15 91:15]
- wire _GEN_16 = io_out_valid & io_out_ready ? _T_12 : valid; // @[VCmdq.scala 51:22 81:46]
- wire _T_16 = io_in_valid & io_in_ready | _T_11; // @[VCmdq.scala 118:36]
- wire _fvalid_T = f_io_in_valid & f_io_in_ready; // @[VCmdq.scala 119:38]
- wire [3:0] _fvalid_T_1 = {f_io_in_bits_3_valid,f_io_in_bits_2_valid,f_io_in_bits_1_valid,f_io_in_bits_0_valid}; // @[Cat.scala 31:58]
- wire [3:0] fvalid = _fvalid_T ? _fvalid_T_1 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount = f_io_in_bits_0_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh = 16'h1 << active_active_oh_shiftAmount; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo = {3'h0,active_active_oh[3],3'h0,active_active_oh[2],3'h0,active_active_oh[1],3'h0
- ,active_active_oh[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo = {3'h0,active_active_oh[7],3'h0,active_active_oh[6],3'h0,active_active_oh[5],3'h0,
- active_active_oh[4],active_active_oh0_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo = {3'h0,active_active_oh[11],3'h0,active_active_oh[10],3'h0,active_active_oh[9],3'h0
- ,active_active_oh[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0 = {3'h0,active_active_oh[15],3'h0,active_active_oh[14],3'h0,active_active_oh[13],3'h0,
- active_active_oh[12],active_active_oh0_hi_lo,active_active_oh0_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo = {2'h0,active_active_oh[1],1'h0,2'h0,active_active_oh[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo = {2'h0,active_active_oh[3],1'h0,2'h0,active_active_oh[2],1'h0,
- active_active_oh1_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo = {2'h0,active_active_oh[5],1'h0,2'h0,active_active_oh[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo = {2'h0,active_active_oh[7],1'h0,2'h0,active_active_oh[6],1'h0,
- active_active_oh1_lo_hi_lo,active_active_oh1_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo = {2'h0,active_active_oh[9],1'h0,2'h0,active_active_oh[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo = {2'h0,active_active_oh[11],1'h0,2'h0,active_active_oh[10],1'h0,
- active_active_oh1_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo = {2'h0,active_active_oh[13],1'h0,2'h0,active_active_oh[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1 = {2'h0,active_active_oh[15],1'h0,2'h0,active_active_oh[14],1'h0,
- active_active_oh1_hi_hi_lo,active_active_oh1_hi_lo,active_active_oh1_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo = {1'h0,active_active_oh[1],2'h0,1'h0,active_active_oh[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo = {1'h0,active_active_oh[3],2'h0,1'h0,active_active_oh[2],2'h0,
- active_active_oh2_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo = {1'h0,active_active_oh[5],2'h0,1'h0,active_active_oh[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo = {1'h0,active_active_oh[7],2'h0,1'h0,active_active_oh[6],2'h0,
- active_active_oh2_lo_hi_lo,active_active_oh2_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo = {1'h0,active_active_oh[9],2'h0,1'h0,active_active_oh[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo = {1'h0,active_active_oh[11],2'h0,1'h0,active_active_oh[10],2'h0,
- active_active_oh2_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo = {1'h0,active_active_oh[13],2'h0,1'h0,active_active_oh[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2 = {1'h0,active_active_oh[15],2'h0,1'h0,active_active_oh[14],2'h0,
- active_active_oh2_hi_hi_lo,active_active_oh2_hi_lo,active_active_oh2_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo = {active_active_oh[3],3'h0,active_active_oh[2],3'h0,active_active_oh[1],3'h0,
- active_active_oh[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo = {active_active_oh[7],3'h0,active_active_oh[6],3'h0,active_active_oh[5],3'h0,
- active_active_oh[4],3'h0,active_active_oh3_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo = {active_active_oh[11],3'h0,active_active_oh[10],3'h0,active_active_oh[9],3'h0,
- active_active_oh[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3 = {active_active_oh[15],3'h0,active_active_oh[14],3'h0,active_active_oh[13],3'h0,
- active_active_oh[12],3'h0,active_active_oh3_hi_lo,active_active_oh3_lo}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx = f_io_in_bits_0_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T = ~f_io_in_bits_0_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_4 = f_io_in_bits_0_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_5 = ~f_io_in_bits_0_bits_m & active_active_idx == 2'h0 | f_io_in_bits_0_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_6 = _active_active_active_T_5 ? active_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_12 = _active_active_active_T & active_active_idx == 2'h1 | _active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_13 = _active_active_active_T_12 ? active_active_oh1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_14 = _active_active_active_T_6 | _active_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active_active_T_20 = _active_active_active_T & active_active_idx == 2'h2 | _active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_21 = _active_active_active_T_20 ? active_active_oh2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_22 = _active_active_active_T_14 | _active_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active_active_T_28 = _active_active_active_T & active_active_idx == 2'h3 | _active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_29 = _active_active_active_T_28 ? active_active_oh3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active = _active_active_active_T_22 | _active_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] active_active = f_io_in_bits_0_bits_tin_vs_valid ? active_active_active : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_1 = fvalid[0] ? active_active : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount_1 = f_io_in_bits_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_1 = 16'h1 << active_active_oh_shiftAmount_1; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_1 = {3'h0,active_active_oh_1[3],3'h0,active_active_oh_1[2],3'h0,active_active_oh_1
- [1],3'h0,active_active_oh_1[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_1 = {3'h0,active_active_oh_1[7],3'h0,active_active_oh_1[6],3'h0,active_active_oh_1[5]
- ,3'h0,active_active_oh_1[4],active_active_oh0_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_1 = {3'h0,active_active_oh_1[11],3'h0,active_active_oh_1[10],3'h0,
- active_active_oh_1[9],3'h0,active_active_oh_1[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_1 = {3'h0,active_active_oh_1[15],3'h0,active_active_oh_1[14],3'h0,active_active_oh_1[13]
- ,3'h0,active_active_oh_1[12],active_active_oh0_hi_lo_1,active_active_oh0_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_1 = {2'h0,active_active_oh_1[1],1'h0,2'h0,active_active_oh_1[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_1 = {2'h0,active_active_oh_1[3],1'h0,2'h0,active_active_oh_1[2],1'h0,
- active_active_oh1_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_1 = {2'h0,active_active_oh_1[5],1'h0,2'h0,active_active_oh_1[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_1 = {2'h0,active_active_oh_1[7],1'h0,2'h0,active_active_oh_1[6],1'h0,
- active_active_oh1_lo_hi_lo_1,active_active_oh1_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_1 = {2'h0,active_active_oh_1[9],1'h0,2'h0,active_active_oh_1[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_1 = {2'h0,active_active_oh_1[11],1'h0,2'h0,active_active_oh_1[10],1'h0,
- active_active_oh1_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_1 = {2'h0,active_active_oh_1[13],1'h0,2'h0,active_active_oh_1[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_1 = {2'h0,active_active_oh_1[15],1'h0,2'h0,active_active_oh_1[14],1'h0,
- active_active_oh1_hi_hi_lo_1,active_active_oh1_hi_lo_1,active_active_oh1_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_1 = {1'h0,active_active_oh_1[1],2'h0,1'h0,active_active_oh_1[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_1 = {1'h0,active_active_oh_1[3],2'h0,1'h0,active_active_oh_1[2],2'h0,
- active_active_oh2_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_1 = {1'h0,active_active_oh_1[5],2'h0,1'h0,active_active_oh_1[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_1 = {1'h0,active_active_oh_1[7],2'h0,1'h0,active_active_oh_1[6],2'h0,
- active_active_oh2_lo_hi_lo_1,active_active_oh2_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_1 = {1'h0,active_active_oh_1[9],2'h0,1'h0,active_active_oh_1[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_1 = {1'h0,active_active_oh_1[11],2'h0,1'h0,active_active_oh_1[10],2'h0,
- active_active_oh2_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_1 = {1'h0,active_active_oh_1[13],2'h0,1'h0,active_active_oh_1[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_1 = {1'h0,active_active_oh_1[15],2'h0,1'h0,active_active_oh_1[14],2'h0,
- active_active_oh2_hi_hi_lo_1,active_active_oh2_hi_lo_1,active_active_oh2_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_1 = {active_active_oh_1[3],3'h0,active_active_oh_1[2],3'h0,active_active_oh_1[1],3'h0
- ,active_active_oh_1[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_1 = {active_active_oh_1[7],3'h0,active_active_oh_1[6],3'h0,active_active_oh_1[5],3'h0
- ,active_active_oh_1[4],3'h0,active_active_oh3_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_1 = {active_active_oh_1[11],3'h0,active_active_oh_1[10],3'h0,active_active_oh_1[9]
- ,3'h0,active_active_oh_1[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_1 = {active_active_oh_1[15],3'h0,active_active_oh_1[14],3'h0,active_active_oh_1[13],3'h0
- ,active_active_oh_1[12],3'h0,active_active_oh3_hi_lo_1,active_active_oh3_lo_1}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_1 = f_io_in_bits_1_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_30 = ~f_io_in_bits_1_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_34 = f_io_in_bits_1_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_35 = ~f_io_in_bits_1_bits_m & active_active_idx_1 == 2'h0 | f_io_in_bits_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_36 = _active_active_active_T_35 ? active_active_oh0_1 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_42 = _active_active_active_T_30 & active_active_idx_1 == 2'h1 |
- _active_active_active_T_34; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_43 = _active_active_active_T_42 ? active_active_oh1_1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_44 = _active_active_active_T_36 | _active_active_active_T_43; // @[VCommon.scala 107:68]
- wire _active_active_active_T_50 = _active_active_active_T_30 & active_active_idx_1 == 2'h2 |
- _active_active_active_T_34; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_51 = _active_active_active_T_50 ? active_active_oh2_1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_52 = _active_active_active_T_44 | _active_active_active_T_51; // @[VCommon.scala 108:68]
- wire _active_active_active_T_58 = _active_active_active_T_30 & active_active_idx_1 == 2'h3 |
- _active_active_active_T_34; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_59 = _active_active_active_T_58 ? active_active_oh3_1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_1 = _active_active_active_T_52 | _active_active_active_T_59; // @[VCommon.scala 109:68]
- wire [63:0] active_active_1 = f_io_in_bits_1_bits_tin_vs_valid ? active_active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_3 = fvalid[1] ? active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_4 = _active_T_1 | _active_T_3; // @[VCmdq.scala 124:90]
- wire [3:0] active_active_oh_shiftAmount_2 = f_io_in_bits_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_2 = 16'h1 << active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_2 = {3'h0,active_active_oh_2[3],3'h0,active_active_oh_2[2],3'h0,active_active_oh_2
- [1],3'h0,active_active_oh_2[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_2 = {3'h0,active_active_oh_2[7],3'h0,active_active_oh_2[6],3'h0,active_active_oh_2[5]
- ,3'h0,active_active_oh_2[4],active_active_oh0_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_2 = {3'h0,active_active_oh_2[11],3'h0,active_active_oh_2[10],3'h0,
- active_active_oh_2[9],3'h0,active_active_oh_2[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_2 = {3'h0,active_active_oh_2[15],3'h0,active_active_oh_2[14],3'h0,active_active_oh_2[13]
- ,3'h0,active_active_oh_2[12],active_active_oh0_hi_lo_2,active_active_oh0_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_2 = {2'h0,active_active_oh_2[1],1'h0,2'h0,active_active_oh_2[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_2 = {2'h0,active_active_oh_2[3],1'h0,2'h0,active_active_oh_2[2],1'h0,
- active_active_oh1_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_2 = {2'h0,active_active_oh_2[5],1'h0,2'h0,active_active_oh_2[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_2 = {2'h0,active_active_oh_2[7],1'h0,2'h0,active_active_oh_2[6],1'h0,
- active_active_oh1_lo_hi_lo_2,active_active_oh1_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_2 = {2'h0,active_active_oh_2[9],1'h0,2'h0,active_active_oh_2[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_2 = {2'h0,active_active_oh_2[11],1'h0,2'h0,active_active_oh_2[10],1'h0,
- active_active_oh1_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_2 = {2'h0,active_active_oh_2[13],1'h0,2'h0,active_active_oh_2[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_2 = {2'h0,active_active_oh_2[15],1'h0,2'h0,active_active_oh_2[14],1'h0,
- active_active_oh1_hi_hi_lo_2,active_active_oh1_hi_lo_2,active_active_oh1_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_2 = {1'h0,active_active_oh_2[1],2'h0,1'h0,active_active_oh_2[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_2 = {1'h0,active_active_oh_2[3],2'h0,1'h0,active_active_oh_2[2],2'h0,
- active_active_oh2_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_2 = {1'h0,active_active_oh_2[5],2'h0,1'h0,active_active_oh_2[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_2 = {1'h0,active_active_oh_2[7],2'h0,1'h0,active_active_oh_2[6],2'h0,
- active_active_oh2_lo_hi_lo_2,active_active_oh2_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_2 = {1'h0,active_active_oh_2[9],2'h0,1'h0,active_active_oh_2[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_2 = {1'h0,active_active_oh_2[11],2'h0,1'h0,active_active_oh_2[10],2'h0,
- active_active_oh2_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_2 = {1'h0,active_active_oh_2[13],2'h0,1'h0,active_active_oh_2[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_2 = {1'h0,active_active_oh_2[15],2'h0,1'h0,active_active_oh_2[14],2'h0,
- active_active_oh2_hi_hi_lo_2,active_active_oh2_hi_lo_2,active_active_oh2_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_2 = {active_active_oh_2[3],3'h0,active_active_oh_2[2],3'h0,active_active_oh_2[1],3'h0
- ,active_active_oh_2[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_2 = {active_active_oh_2[7],3'h0,active_active_oh_2[6],3'h0,active_active_oh_2[5],3'h0
- ,active_active_oh_2[4],3'h0,active_active_oh3_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_2 = {active_active_oh_2[11],3'h0,active_active_oh_2[10],3'h0,active_active_oh_2[9]
- ,3'h0,active_active_oh_2[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_2 = {active_active_oh_2[15],3'h0,active_active_oh_2[14],3'h0,active_active_oh_2[13],3'h0
- ,active_active_oh_2[12],3'h0,active_active_oh3_hi_lo_2,active_active_oh3_lo_2}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_2 = f_io_in_bits_2_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_60 = ~f_io_in_bits_2_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_64 = f_io_in_bits_2_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_65 = ~f_io_in_bits_2_bits_m & active_active_idx_2 == 2'h0 | f_io_in_bits_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_66 = _active_active_active_T_65 ? active_active_oh0_2 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_72 = _active_active_active_T_60 & active_active_idx_2 == 2'h1 |
- _active_active_active_T_64; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_73 = _active_active_active_T_72 ? active_active_oh1_2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_74 = _active_active_active_T_66 | _active_active_active_T_73; // @[VCommon.scala 107:68]
- wire _active_active_active_T_80 = _active_active_active_T_60 & active_active_idx_2 == 2'h2 |
- _active_active_active_T_64; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_81 = _active_active_active_T_80 ? active_active_oh2_2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_82 = _active_active_active_T_74 | _active_active_active_T_81; // @[VCommon.scala 108:68]
- wire _active_active_active_T_88 = _active_active_active_T_60 & active_active_idx_2 == 2'h3 |
- _active_active_active_T_64; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_89 = _active_active_active_T_88 ? active_active_oh3_2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_2 = _active_active_active_T_82 | _active_active_active_T_89; // @[VCommon.scala 109:68]
- wire [63:0] active_active_2 = f_io_in_bits_2_bits_tin_vs_valid ? active_active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_6 = fvalid[2] ? active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_7 = _active_T_4 | _active_T_6; // @[VCmdq.scala 125:90]
- wire [3:0] active_active_oh_shiftAmount_3 = f_io_in_bits_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_3 = 16'h1 << active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_3 = {3'h0,active_active_oh_3[3],3'h0,active_active_oh_3[2],3'h0,active_active_oh_3
- [1],3'h0,active_active_oh_3[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_3 = {3'h0,active_active_oh_3[7],3'h0,active_active_oh_3[6],3'h0,active_active_oh_3[5]
- ,3'h0,active_active_oh_3[4],active_active_oh0_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_3 = {3'h0,active_active_oh_3[11],3'h0,active_active_oh_3[10],3'h0,
- active_active_oh_3[9],3'h0,active_active_oh_3[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_3 = {3'h0,active_active_oh_3[15],3'h0,active_active_oh_3[14],3'h0,active_active_oh_3[13]
- ,3'h0,active_active_oh_3[12],active_active_oh0_hi_lo_3,active_active_oh0_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_3 = {2'h0,active_active_oh_3[1],1'h0,2'h0,active_active_oh_3[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_3 = {2'h0,active_active_oh_3[3],1'h0,2'h0,active_active_oh_3[2],1'h0,
- active_active_oh1_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_3 = {2'h0,active_active_oh_3[5],1'h0,2'h0,active_active_oh_3[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_3 = {2'h0,active_active_oh_3[7],1'h0,2'h0,active_active_oh_3[6],1'h0,
- active_active_oh1_lo_hi_lo_3,active_active_oh1_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_3 = {2'h0,active_active_oh_3[9],1'h0,2'h0,active_active_oh_3[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_3 = {2'h0,active_active_oh_3[11],1'h0,2'h0,active_active_oh_3[10],1'h0,
- active_active_oh1_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_3 = {2'h0,active_active_oh_3[13],1'h0,2'h0,active_active_oh_3[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_3 = {2'h0,active_active_oh_3[15],1'h0,2'h0,active_active_oh_3[14],1'h0,
- active_active_oh1_hi_hi_lo_3,active_active_oh1_hi_lo_3,active_active_oh1_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_3 = {1'h0,active_active_oh_3[1],2'h0,1'h0,active_active_oh_3[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_3 = {1'h0,active_active_oh_3[3],2'h0,1'h0,active_active_oh_3[2],2'h0,
- active_active_oh2_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_3 = {1'h0,active_active_oh_3[5],2'h0,1'h0,active_active_oh_3[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_3 = {1'h0,active_active_oh_3[7],2'h0,1'h0,active_active_oh_3[6],2'h0,
- active_active_oh2_lo_hi_lo_3,active_active_oh2_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_3 = {1'h0,active_active_oh_3[9],2'h0,1'h0,active_active_oh_3[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_3 = {1'h0,active_active_oh_3[11],2'h0,1'h0,active_active_oh_3[10],2'h0,
- active_active_oh2_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_3 = {1'h0,active_active_oh_3[13],2'h0,1'h0,active_active_oh_3[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_3 = {1'h0,active_active_oh_3[15],2'h0,1'h0,active_active_oh_3[14],2'h0,
- active_active_oh2_hi_hi_lo_3,active_active_oh2_hi_lo_3,active_active_oh2_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_3 = {active_active_oh_3[3],3'h0,active_active_oh_3[2],3'h0,active_active_oh_3[1],3'h0
- ,active_active_oh_3[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_3 = {active_active_oh_3[7],3'h0,active_active_oh_3[6],3'h0,active_active_oh_3[5],3'h0
- ,active_active_oh_3[4],3'h0,active_active_oh3_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_3 = {active_active_oh_3[11],3'h0,active_active_oh_3[10],3'h0,active_active_oh_3[9]
- ,3'h0,active_active_oh_3[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_3 = {active_active_oh_3[15],3'h0,active_active_oh_3[14],3'h0,active_active_oh_3[13],3'h0
- ,active_active_oh_3[12],3'h0,active_active_oh3_hi_lo_3,active_active_oh3_lo_3}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_3 = f_io_in_bits_3_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_90 = ~f_io_in_bits_3_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_94 = f_io_in_bits_3_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_95 = ~f_io_in_bits_3_bits_m & active_active_idx_3 == 2'h0 | f_io_in_bits_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_96 = _active_active_active_T_95 ? active_active_oh0_3 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_102 = _active_active_active_T_90 & active_active_idx_3 == 2'h1 |
- _active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_103 = _active_active_active_T_102 ? active_active_oh1_3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_104 = _active_active_active_T_96 | _active_active_active_T_103; // @[VCommon.scala 107:68]
- wire _active_active_active_T_110 = _active_active_active_T_90 & active_active_idx_3 == 2'h2 |
- _active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_111 = _active_active_active_T_110 ? active_active_oh2_3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_112 = _active_active_active_T_104 | _active_active_active_T_111; // @[VCommon.scala 108:68]
- wire _active_active_active_T_118 = _active_active_active_T_90 & active_active_idx_3 == 2'h3 |
- _active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_119 = _active_active_active_T_118 ? active_active_oh3_3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_3 = _active_active_active_T_112 | _active_active_active_T_119; // @[VCommon.scala 109:68]
- wire [63:0] active_active_3 = f_io_in_bits_3_bits_tin_vs_valid ? active_active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_9 = fvalid[3] ? active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_10 = _active_T_7 | _active_T_9; // @[VCmdq.scala 126:90]
- wire [3:0] active_active_active_oh_shiftAmount = f_io_entry_0_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh = 16'h1 << active_active_active_oh_shiftAmount; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo = {3'h0,active_active_active_oh[3],3'h0,active_active_active_oh[2],3'h0,
- active_active_active_oh[1],3'h0,active_active_active_oh[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo = {3'h0,active_active_active_oh[7],3'h0,active_active_active_oh[6],3'h0,
- active_active_active_oh[5],3'h0,active_active_active_oh[4],active_active_active_oh0_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo = {3'h0,active_active_active_oh[11],3'h0,active_active_active_oh[10],3'h0,
- active_active_active_oh[9],3'h0,active_active_active_oh[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0 = {3'h0,active_active_active_oh[15],3'h0,active_active_active_oh[14],3'h0,
- active_active_active_oh[13],3'h0,active_active_active_oh[12],active_active_active_oh0_hi_lo,
- active_active_active_oh0_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo = {2'h0,active_active_active_oh[1],1'h0,2'h0,active_active_active_oh[0],1'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo = {2'h0,active_active_active_oh[3],1'h0,2'h0,active_active_active_oh[2],1'h0
- ,active_active_active_oh1_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo = {2'h0,active_active_active_oh[5],1'h0,2'h0,active_active_active_oh[4],1'h0
- }; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo = {2'h0,active_active_active_oh[7],1'h0,2'h0,active_active_active_oh[6],1'h0,
- active_active_active_oh1_lo_hi_lo,active_active_active_oh1_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo = {2'h0,active_active_active_oh[9],1'h0,2'h0,active_active_active_oh[8],1'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo = {2'h0,active_active_active_oh[11],1'h0,2'h0,active_active_active_oh[10],1'h0
- ,active_active_active_oh1_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo = {2'h0,active_active_active_oh[13],1'h0,2'h0,active_active_active_oh[12]
- ,1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1 = {2'h0,active_active_active_oh[15],1'h0,2'h0,active_active_active_oh[14],1'h0,
- active_active_active_oh1_hi_hi_lo,active_active_active_oh1_hi_lo,active_active_active_oh1_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo = {1'h0,active_active_active_oh[1],2'h0,1'h0,active_active_active_oh[0],2'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo = {1'h0,active_active_active_oh[3],2'h0,1'h0,active_active_active_oh[2],2'h0
- ,active_active_active_oh2_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo = {1'h0,active_active_active_oh[5],2'h0,1'h0,active_active_active_oh[4],2'h0
- }; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo = {1'h0,active_active_active_oh[7],2'h0,1'h0,active_active_active_oh[6],2'h0,
- active_active_active_oh2_lo_hi_lo,active_active_active_oh2_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo = {1'h0,active_active_active_oh[9],2'h0,1'h0,active_active_active_oh[8],2'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo = {1'h0,active_active_active_oh[11],2'h0,1'h0,active_active_active_oh[10],2'h0
- ,active_active_active_oh2_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo = {1'h0,active_active_active_oh[13],2'h0,1'h0,active_active_active_oh[12]
- ,2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2 = {1'h0,active_active_active_oh[15],2'h0,1'h0,active_active_active_oh[14],2'h0,
- active_active_active_oh2_hi_hi_lo,active_active_active_oh2_hi_lo,active_active_active_oh2_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo = {active_active_active_oh[3],3'h0,active_active_active_oh[2],3'h0,
- active_active_active_oh[1],3'h0,active_active_active_oh[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo = {active_active_active_oh[7],3'h0,active_active_active_oh[6],3'h0,
- active_active_active_oh[5],3'h0,active_active_active_oh[4],3'h0,active_active_active_oh3_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo = {active_active_active_oh[11],3'h0,active_active_active_oh[10],3'h0,
- active_active_active_oh[9],3'h0,active_active_active_oh[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3 = {active_active_active_oh[15],3'h0,active_active_active_oh[14],3'h0,
- active_active_active_oh[13],3'h0,active_active_active_oh[12],3'h0,active_active_active_oh3_hi_lo,
- active_active_active_oh3_lo}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx = f_io_entry_0_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T = ~f_io_entry_0_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_4 = f_io_entry_0_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_5 = ~f_io_entry_0_bits_m & active_active_active_idx == 2'h0 | f_io_entry_0_bits_m
- ; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_6 = _active_active_active_active_T_5 ? active_active_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_active_T_12 = _active_active_active_active_T & active_active_active_idx == 2'h1 |
- _active_active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_13 = _active_active_active_active_T_12 ? active_active_active_oh1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_14 = _active_active_active_active_T_6 | _active_active_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_20 = _active_active_active_active_T & active_active_active_idx == 2'h2 |
- _active_active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_21 = _active_active_active_active_T_20 ? active_active_active_oh2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_22 = _active_active_active_active_T_14 | _active_active_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_28 = _active_active_active_active_T & active_active_active_idx == 2'h3 |
- _active_active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_29 = _active_active_active_active_T_28 ? active_active_active_oh3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active = _active_active_active_active_T_22 | _active_active_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_4 = f_io_entry_0_bits_tin_vs_valid ? active_active_active_active : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_4 = f_io_entry_0_valid ? active_active_active_4 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_1 = f_io_entry_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_1 = 16'h1 << active_active_active_oh_shiftAmount_1; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_1 = {3'h0,active_active_active_oh_1[3],3'h0,active_active_active_oh_1[2],3'h0
- ,active_active_active_oh_1[1],3'h0,active_active_active_oh_1[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_1 = {3'h0,active_active_active_oh_1[7],3'h0,active_active_active_oh_1[6],3'h0,
- active_active_active_oh_1[5],3'h0,active_active_active_oh_1[4],active_active_active_oh0_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_1 = {3'h0,active_active_active_oh_1[11],3'h0,active_active_active_oh_1[10],3'h0
- ,active_active_active_oh_1[9],3'h0,active_active_active_oh_1[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_1 = {3'h0,active_active_active_oh_1[15],3'h0,active_active_active_oh_1[14],3'h0,
- active_active_active_oh_1[13],3'h0,active_active_active_oh_1[12],active_active_active_oh0_hi_lo_1,
- active_active_active_oh0_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_1 = {2'h0,active_active_active_oh_1[1],1'h0,2'h0,
- active_active_active_oh_1[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_1 = {2'h0,active_active_active_oh_1[3],1'h0,2'h0,active_active_active_oh_1[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_1 = {2'h0,active_active_active_oh_1[5],1'h0,2'h0,
- active_active_active_oh_1[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_1 = {2'h0,active_active_active_oh_1[7],1'h0,2'h0,active_active_active_oh_1[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_1,active_active_active_oh1_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_1 = {2'h0,active_active_active_oh_1[9],1'h0,2'h0,
- active_active_active_oh_1[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_1 = {2'h0,active_active_active_oh_1[11],1'h0,2'h0,active_active_active_oh_1
- [10],1'h0,active_active_active_oh1_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_1 = {2'h0,active_active_active_oh_1[13],1'h0,2'h0,
- active_active_active_oh_1[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_1 = {2'h0,active_active_active_oh_1[15],1'h0,2'h0,active_active_active_oh_1[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_1,active_active_active_oh1_hi_lo_1,active_active_active_oh1_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_1 = {1'h0,active_active_active_oh_1[1],2'h0,1'h0,
- active_active_active_oh_1[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_1 = {1'h0,active_active_active_oh_1[3],2'h0,1'h0,active_active_active_oh_1[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_1 = {1'h0,active_active_active_oh_1[5],2'h0,1'h0,
- active_active_active_oh_1[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_1 = {1'h0,active_active_active_oh_1[7],2'h0,1'h0,active_active_active_oh_1[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_1,active_active_active_oh2_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_1 = {1'h0,active_active_active_oh_1[9],2'h0,1'h0,
- active_active_active_oh_1[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_1 = {1'h0,active_active_active_oh_1[11],2'h0,1'h0,active_active_active_oh_1
- [10],2'h0,active_active_active_oh2_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_1 = {1'h0,active_active_active_oh_1[13],2'h0,1'h0,
- active_active_active_oh_1[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_1 = {1'h0,active_active_active_oh_1[15],2'h0,1'h0,active_active_active_oh_1[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_1,active_active_active_oh2_hi_lo_1,active_active_active_oh2_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_1 = {active_active_active_oh_1[3],3'h0,active_active_active_oh_1[2],3'h0,
- active_active_active_oh_1[1],3'h0,active_active_active_oh_1[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_1 = {active_active_active_oh_1[7],3'h0,active_active_active_oh_1[6],3'h0,
- active_active_active_oh_1[5],3'h0,active_active_active_oh_1[4],3'h0,active_active_active_oh3_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_1 = {active_active_active_oh_1[11],3'h0,active_active_active_oh_1[10],3'h0,
- active_active_active_oh_1[9],3'h0,active_active_active_oh_1[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_1 = {active_active_active_oh_1[15],3'h0,active_active_active_oh_1[14],3'h0,
- active_active_active_oh_1[13],3'h0,active_active_active_oh_1[12],3'h0,active_active_active_oh3_hi_lo_1,
- active_active_active_oh3_lo_1}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_1 = f_io_entry_1_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_30 = ~f_io_entry_1_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_34 = f_io_entry_1_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_35 = ~f_io_entry_1_bits_m & active_active_active_idx_1 == 2'h0 |
- f_io_entry_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_36 = _active_active_active_active_T_35 ? active_active_active_oh0_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_42 = _active_active_active_active_T_30 & active_active_active_idx_1 == 2'h1 |
- _active_active_active_active_T_34; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_43 = _active_active_active_active_T_42 ? active_active_active_oh1_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_44 = _active_active_active_active_T_36 | _active_active_active_active_T_43; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_50 = _active_active_active_active_T_30 & active_active_active_idx_1 == 2'h2 |
- _active_active_active_active_T_34; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_51 = _active_active_active_active_T_50 ? active_active_active_oh2_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_52 = _active_active_active_active_T_44 | _active_active_active_active_T_51; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_58 = _active_active_active_active_T_30 & active_active_active_idx_1 == 2'h3 |
- _active_active_active_active_T_34; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_59 = _active_active_active_active_T_58 ? active_active_active_oh3_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_1 = _active_active_active_active_T_52 | _active_active_active_active_T_59; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_5 = f_io_entry_1_bits_tin_vs_valid ? active_active_active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_5 = f_io_entry_1_valid ? active_active_active_5 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_12 = active_active_4 | active_active_5; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_2 = f_io_entry_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_2 = 16'h1 << active_active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_2 = {3'h0,active_active_active_oh_2[3],3'h0,active_active_active_oh_2[2],3'h0
- ,active_active_active_oh_2[1],3'h0,active_active_active_oh_2[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_2 = {3'h0,active_active_active_oh_2[7],3'h0,active_active_active_oh_2[6],3'h0,
- active_active_active_oh_2[5],3'h0,active_active_active_oh_2[4],active_active_active_oh0_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_2 = {3'h0,active_active_active_oh_2[11],3'h0,active_active_active_oh_2[10],3'h0
- ,active_active_active_oh_2[9],3'h0,active_active_active_oh_2[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_2 = {3'h0,active_active_active_oh_2[15],3'h0,active_active_active_oh_2[14],3'h0,
- active_active_active_oh_2[13],3'h0,active_active_active_oh_2[12],active_active_active_oh0_hi_lo_2,
- active_active_active_oh0_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_2 = {2'h0,active_active_active_oh_2[1],1'h0,2'h0,
- active_active_active_oh_2[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_2 = {2'h0,active_active_active_oh_2[3],1'h0,2'h0,active_active_active_oh_2[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_2 = {2'h0,active_active_active_oh_2[5],1'h0,2'h0,
- active_active_active_oh_2[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_2 = {2'h0,active_active_active_oh_2[7],1'h0,2'h0,active_active_active_oh_2[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_2,active_active_active_oh1_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_2 = {2'h0,active_active_active_oh_2[9],1'h0,2'h0,
- active_active_active_oh_2[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_2 = {2'h0,active_active_active_oh_2[11],1'h0,2'h0,active_active_active_oh_2
- [10],1'h0,active_active_active_oh1_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_2 = {2'h0,active_active_active_oh_2[13],1'h0,2'h0,
- active_active_active_oh_2[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_2 = {2'h0,active_active_active_oh_2[15],1'h0,2'h0,active_active_active_oh_2[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_2,active_active_active_oh1_hi_lo_2,active_active_active_oh1_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_2 = {1'h0,active_active_active_oh_2[1],2'h0,1'h0,
- active_active_active_oh_2[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_2 = {1'h0,active_active_active_oh_2[3],2'h0,1'h0,active_active_active_oh_2[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_2 = {1'h0,active_active_active_oh_2[5],2'h0,1'h0,
- active_active_active_oh_2[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_2 = {1'h0,active_active_active_oh_2[7],2'h0,1'h0,active_active_active_oh_2[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_2,active_active_active_oh2_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_2 = {1'h0,active_active_active_oh_2[9],2'h0,1'h0,
- active_active_active_oh_2[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_2 = {1'h0,active_active_active_oh_2[11],2'h0,1'h0,active_active_active_oh_2
- [10],2'h0,active_active_active_oh2_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_2 = {1'h0,active_active_active_oh_2[13],2'h0,1'h0,
- active_active_active_oh_2[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_2 = {1'h0,active_active_active_oh_2[15],2'h0,1'h0,active_active_active_oh_2[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_2,active_active_active_oh2_hi_lo_2,active_active_active_oh2_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_2 = {active_active_active_oh_2[3],3'h0,active_active_active_oh_2[2],3'h0,
- active_active_active_oh_2[1],3'h0,active_active_active_oh_2[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_2 = {active_active_active_oh_2[7],3'h0,active_active_active_oh_2[6],3'h0,
- active_active_active_oh_2[5],3'h0,active_active_active_oh_2[4],3'h0,active_active_active_oh3_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_2 = {active_active_active_oh_2[11],3'h0,active_active_active_oh_2[10],3'h0,
- active_active_active_oh_2[9],3'h0,active_active_active_oh_2[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_2 = {active_active_active_oh_2[15],3'h0,active_active_active_oh_2[14],3'h0,
- active_active_active_oh_2[13],3'h0,active_active_active_oh_2[12],3'h0,active_active_active_oh3_hi_lo_2,
- active_active_active_oh3_lo_2}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_2 = f_io_entry_2_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_60 = ~f_io_entry_2_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_64 = f_io_entry_2_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_65 = ~f_io_entry_2_bits_m & active_active_active_idx_2 == 2'h0 |
- f_io_entry_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_66 = _active_active_active_active_T_65 ? active_active_active_oh0_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_72 = _active_active_active_active_T_60 & active_active_active_idx_2 == 2'h1 |
- _active_active_active_active_T_64; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_73 = _active_active_active_active_T_72 ? active_active_active_oh1_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_74 = _active_active_active_active_T_66 | _active_active_active_active_T_73; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_80 = _active_active_active_active_T_60 & active_active_active_idx_2 == 2'h2 |
- _active_active_active_active_T_64; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_81 = _active_active_active_active_T_80 ? active_active_active_oh2_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_82 = _active_active_active_active_T_74 | _active_active_active_active_T_81; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_88 = _active_active_active_active_T_60 & active_active_active_idx_2 == 2'h3 |
- _active_active_active_active_T_64; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_89 = _active_active_active_active_T_88 ? active_active_active_oh3_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_2 = _active_active_active_active_T_82 | _active_active_active_active_T_89; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_6 = f_io_entry_2_bits_tin_vs_valid ? active_active_active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_6 = f_io_entry_2_valid ? active_active_active_6 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_13 = _active_T_12 | active_active_6; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_3 = f_io_entry_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_3 = 16'h1 << active_active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_3 = {3'h0,active_active_active_oh_3[3],3'h0,active_active_active_oh_3[2],3'h0
- ,active_active_active_oh_3[1],3'h0,active_active_active_oh_3[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_3 = {3'h0,active_active_active_oh_3[7],3'h0,active_active_active_oh_3[6],3'h0,
- active_active_active_oh_3[5],3'h0,active_active_active_oh_3[4],active_active_active_oh0_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_3 = {3'h0,active_active_active_oh_3[11],3'h0,active_active_active_oh_3[10],3'h0
- ,active_active_active_oh_3[9],3'h0,active_active_active_oh_3[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_3 = {3'h0,active_active_active_oh_3[15],3'h0,active_active_active_oh_3[14],3'h0,
- active_active_active_oh_3[13],3'h0,active_active_active_oh_3[12],active_active_active_oh0_hi_lo_3,
- active_active_active_oh0_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_3 = {2'h0,active_active_active_oh_3[1],1'h0,2'h0,
- active_active_active_oh_3[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_3 = {2'h0,active_active_active_oh_3[3],1'h0,2'h0,active_active_active_oh_3[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_3 = {2'h0,active_active_active_oh_3[5],1'h0,2'h0,
- active_active_active_oh_3[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_3 = {2'h0,active_active_active_oh_3[7],1'h0,2'h0,active_active_active_oh_3[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_3,active_active_active_oh1_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_3 = {2'h0,active_active_active_oh_3[9],1'h0,2'h0,
- active_active_active_oh_3[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_3 = {2'h0,active_active_active_oh_3[11],1'h0,2'h0,active_active_active_oh_3
- [10],1'h0,active_active_active_oh1_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_3 = {2'h0,active_active_active_oh_3[13],1'h0,2'h0,
- active_active_active_oh_3[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_3 = {2'h0,active_active_active_oh_3[15],1'h0,2'h0,active_active_active_oh_3[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_3,active_active_active_oh1_hi_lo_3,active_active_active_oh1_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_3 = {1'h0,active_active_active_oh_3[1],2'h0,1'h0,
- active_active_active_oh_3[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_3 = {1'h0,active_active_active_oh_3[3],2'h0,1'h0,active_active_active_oh_3[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_3 = {1'h0,active_active_active_oh_3[5],2'h0,1'h0,
- active_active_active_oh_3[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_3 = {1'h0,active_active_active_oh_3[7],2'h0,1'h0,active_active_active_oh_3[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_3,active_active_active_oh2_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_3 = {1'h0,active_active_active_oh_3[9],2'h0,1'h0,
- active_active_active_oh_3[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_3 = {1'h0,active_active_active_oh_3[11],2'h0,1'h0,active_active_active_oh_3
- [10],2'h0,active_active_active_oh2_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_3 = {1'h0,active_active_active_oh_3[13],2'h0,1'h0,
- active_active_active_oh_3[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_3 = {1'h0,active_active_active_oh_3[15],2'h0,1'h0,active_active_active_oh_3[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_3,active_active_active_oh2_hi_lo_3,active_active_active_oh2_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_3 = {active_active_active_oh_3[3],3'h0,active_active_active_oh_3[2],3'h0,
- active_active_active_oh_3[1],3'h0,active_active_active_oh_3[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_3 = {active_active_active_oh_3[7],3'h0,active_active_active_oh_3[6],3'h0,
- active_active_active_oh_3[5],3'h0,active_active_active_oh_3[4],3'h0,active_active_active_oh3_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_3 = {active_active_active_oh_3[11],3'h0,active_active_active_oh_3[10],3'h0,
- active_active_active_oh_3[9],3'h0,active_active_active_oh_3[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_3 = {active_active_active_oh_3[15],3'h0,active_active_active_oh_3[14],3'h0,
- active_active_active_oh_3[13],3'h0,active_active_active_oh_3[12],3'h0,active_active_active_oh3_hi_lo_3,
- active_active_active_oh3_lo_3}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_3 = f_io_entry_3_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_90 = ~f_io_entry_3_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_94 = f_io_entry_3_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_95 = ~f_io_entry_3_bits_m & active_active_active_idx_3 == 2'h0 |
- f_io_entry_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_96 = _active_active_active_active_T_95 ? active_active_active_oh0_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_102 = _active_active_active_active_T_90 & active_active_active_idx_3 == 2'h1 |
- _active_active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_103 = _active_active_active_active_T_102 ? active_active_active_oh1_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_104 = _active_active_active_active_T_96 |
- _active_active_active_active_T_103; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_110 = _active_active_active_active_T_90 & active_active_active_idx_3 == 2'h2 |
- _active_active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_111 = _active_active_active_active_T_110 ? active_active_active_oh2_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_112 = _active_active_active_active_T_104 |
- _active_active_active_active_T_111; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_118 = _active_active_active_active_T_90 & active_active_active_idx_3 == 2'h3 |
- _active_active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_119 = _active_active_active_active_T_118 ? active_active_active_oh3_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_3 = _active_active_active_active_T_112 | _active_active_active_active_T_119; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_7 = f_io_entry_3_bits_tin_vs_valid ? active_active_active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_7 = f_io_entry_3_valid ? active_active_active_7 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_14 = _active_T_13 | active_active_7; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_4 = f_io_entry_4_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_4 = 16'h1 << active_active_active_oh_shiftAmount_4; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_4 = {3'h0,active_active_active_oh_4[3],3'h0,active_active_active_oh_4[2],3'h0
- ,active_active_active_oh_4[1],3'h0,active_active_active_oh_4[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_4 = {3'h0,active_active_active_oh_4[7],3'h0,active_active_active_oh_4[6],3'h0,
- active_active_active_oh_4[5],3'h0,active_active_active_oh_4[4],active_active_active_oh0_lo_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_4 = {3'h0,active_active_active_oh_4[11],3'h0,active_active_active_oh_4[10],3'h0
- ,active_active_active_oh_4[9],3'h0,active_active_active_oh_4[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_4 = {3'h0,active_active_active_oh_4[15],3'h0,active_active_active_oh_4[14],3'h0,
- active_active_active_oh_4[13],3'h0,active_active_active_oh_4[12],active_active_active_oh0_hi_lo_4,
- active_active_active_oh0_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_4 = {2'h0,active_active_active_oh_4[1],1'h0,2'h0,
- active_active_active_oh_4[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_4 = {2'h0,active_active_active_oh_4[3],1'h0,2'h0,active_active_active_oh_4[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_4 = {2'h0,active_active_active_oh_4[5],1'h0,2'h0,
- active_active_active_oh_4[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_4 = {2'h0,active_active_active_oh_4[7],1'h0,2'h0,active_active_active_oh_4[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_4,active_active_active_oh1_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_4 = {2'h0,active_active_active_oh_4[9],1'h0,2'h0,
- active_active_active_oh_4[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_4 = {2'h0,active_active_active_oh_4[11],1'h0,2'h0,active_active_active_oh_4
- [10],1'h0,active_active_active_oh1_hi_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_4 = {2'h0,active_active_active_oh_4[13],1'h0,2'h0,
- active_active_active_oh_4[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_4 = {2'h0,active_active_active_oh_4[15],1'h0,2'h0,active_active_active_oh_4[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_4,active_active_active_oh1_hi_lo_4,active_active_active_oh1_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_4 = {1'h0,active_active_active_oh_4[1],2'h0,1'h0,
- active_active_active_oh_4[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_4 = {1'h0,active_active_active_oh_4[3],2'h0,1'h0,active_active_active_oh_4[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_4 = {1'h0,active_active_active_oh_4[5],2'h0,1'h0,
- active_active_active_oh_4[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_4 = {1'h0,active_active_active_oh_4[7],2'h0,1'h0,active_active_active_oh_4[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_4,active_active_active_oh2_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_4 = {1'h0,active_active_active_oh_4[9],2'h0,1'h0,
- active_active_active_oh_4[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_4 = {1'h0,active_active_active_oh_4[11],2'h0,1'h0,active_active_active_oh_4
- [10],2'h0,active_active_active_oh2_hi_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_4 = {1'h0,active_active_active_oh_4[13],2'h0,1'h0,
- active_active_active_oh_4[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_4 = {1'h0,active_active_active_oh_4[15],2'h0,1'h0,active_active_active_oh_4[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_4,active_active_active_oh2_hi_lo_4,active_active_active_oh2_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_4 = {active_active_active_oh_4[3],3'h0,active_active_active_oh_4[2],3'h0,
- active_active_active_oh_4[1],3'h0,active_active_active_oh_4[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_4 = {active_active_active_oh_4[7],3'h0,active_active_active_oh_4[6],3'h0,
- active_active_active_oh_4[5],3'h0,active_active_active_oh_4[4],3'h0,active_active_active_oh3_lo_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_4 = {active_active_active_oh_4[11],3'h0,active_active_active_oh_4[10],3'h0,
- active_active_active_oh_4[9],3'h0,active_active_active_oh_4[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_4 = {active_active_active_oh_4[15],3'h0,active_active_active_oh_4[14],3'h0,
- active_active_active_oh_4[13],3'h0,active_active_active_oh_4[12],3'h0,active_active_active_oh3_hi_lo_4,
- active_active_active_oh3_lo_4}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_4 = f_io_entry_4_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_120 = ~f_io_entry_4_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_124 = f_io_entry_4_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_125 = ~f_io_entry_4_bits_m & active_active_active_idx_4 == 2'h0 |
- f_io_entry_4_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_126 = _active_active_active_active_T_125 ? active_active_active_oh0_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_132 = _active_active_active_active_T_120 & active_active_active_idx_4 == 2'h1 |
- _active_active_active_active_T_124; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_133 = _active_active_active_active_T_132 ? active_active_active_oh1_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_134 = _active_active_active_active_T_126 |
- _active_active_active_active_T_133; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_140 = _active_active_active_active_T_120 & active_active_active_idx_4 == 2'h2 |
- _active_active_active_active_T_124; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_141 = _active_active_active_active_T_140 ? active_active_active_oh2_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_142 = _active_active_active_active_T_134 |
- _active_active_active_active_T_141; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_148 = _active_active_active_active_T_120 & active_active_active_idx_4 == 2'h3 |
- _active_active_active_active_T_124; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_149 = _active_active_active_active_T_148 ? active_active_active_oh3_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_4 = _active_active_active_active_T_142 | _active_active_active_active_T_149; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_8 = f_io_entry_4_bits_tin_vs_valid ? active_active_active_active_4 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_8 = f_io_entry_4_valid ? active_active_active_8 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_15 = _active_T_14 | active_active_8; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_5 = f_io_entry_5_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_5 = 16'h1 << active_active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_5 = {3'h0,active_active_active_oh_5[3],3'h0,active_active_active_oh_5[2],3'h0
- ,active_active_active_oh_5[1],3'h0,active_active_active_oh_5[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_5 = {3'h0,active_active_active_oh_5[7],3'h0,active_active_active_oh_5[6],3'h0,
- active_active_active_oh_5[5],3'h0,active_active_active_oh_5[4],active_active_active_oh0_lo_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_5 = {3'h0,active_active_active_oh_5[11],3'h0,active_active_active_oh_5[10],3'h0
- ,active_active_active_oh_5[9],3'h0,active_active_active_oh_5[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_5 = {3'h0,active_active_active_oh_5[15],3'h0,active_active_active_oh_5[14],3'h0,
- active_active_active_oh_5[13],3'h0,active_active_active_oh_5[12],active_active_active_oh0_hi_lo_5,
- active_active_active_oh0_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_5 = {2'h0,active_active_active_oh_5[1],1'h0,2'h0,
- active_active_active_oh_5[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_5 = {2'h0,active_active_active_oh_5[3],1'h0,2'h0,active_active_active_oh_5[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_5 = {2'h0,active_active_active_oh_5[5],1'h0,2'h0,
- active_active_active_oh_5[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_5 = {2'h0,active_active_active_oh_5[7],1'h0,2'h0,active_active_active_oh_5[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_5,active_active_active_oh1_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_5 = {2'h0,active_active_active_oh_5[9],1'h0,2'h0,
- active_active_active_oh_5[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_5 = {2'h0,active_active_active_oh_5[11],1'h0,2'h0,active_active_active_oh_5
- [10],1'h0,active_active_active_oh1_hi_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_5 = {2'h0,active_active_active_oh_5[13],1'h0,2'h0,
- active_active_active_oh_5[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_5 = {2'h0,active_active_active_oh_5[15],1'h0,2'h0,active_active_active_oh_5[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_5,active_active_active_oh1_hi_lo_5,active_active_active_oh1_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_5 = {1'h0,active_active_active_oh_5[1],2'h0,1'h0,
- active_active_active_oh_5[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_5 = {1'h0,active_active_active_oh_5[3],2'h0,1'h0,active_active_active_oh_5[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_5 = {1'h0,active_active_active_oh_5[5],2'h0,1'h0,
- active_active_active_oh_5[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_5 = {1'h0,active_active_active_oh_5[7],2'h0,1'h0,active_active_active_oh_5[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_5,active_active_active_oh2_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_5 = {1'h0,active_active_active_oh_5[9],2'h0,1'h0,
- active_active_active_oh_5[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_5 = {1'h0,active_active_active_oh_5[11],2'h0,1'h0,active_active_active_oh_5
- [10],2'h0,active_active_active_oh2_hi_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_5 = {1'h0,active_active_active_oh_5[13],2'h0,1'h0,
- active_active_active_oh_5[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_5 = {1'h0,active_active_active_oh_5[15],2'h0,1'h0,active_active_active_oh_5[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_5,active_active_active_oh2_hi_lo_5,active_active_active_oh2_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_5 = {active_active_active_oh_5[3],3'h0,active_active_active_oh_5[2],3'h0,
- active_active_active_oh_5[1],3'h0,active_active_active_oh_5[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_5 = {active_active_active_oh_5[7],3'h0,active_active_active_oh_5[6],3'h0,
- active_active_active_oh_5[5],3'h0,active_active_active_oh_5[4],3'h0,active_active_active_oh3_lo_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_5 = {active_active_active_oh_5[11],3'h0,active_active_active_oh_5[10],3'h0,
- active_active_active_oh_5[9],3'h0,active_active_active_oh_5[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_5 = {active_active_active_oh_5[15],3'h0,active_active_active_oh_5[14],3'h0,
- active_active_active_oh_5[13],3'h0,active_active_active_oh_5[12],3'h0,active_active_active_oh3_hi_lo_5,
- active_active_active_oh3_lo_5}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_5 = f_io_entry_5_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_150 = ~f_io_entry_5_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_154 = f_io_entry_5_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_155 = ~f_io_entry_5_bits_m & active_active_active_idx_5 == 2'h0 |
- f_io_entry_5_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_156 = _active_active_active_active_T_155 ? active_active_active_oh0_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_162 = _active_active_active_active_T_150 & active_active_active_idx_5 == 2'h1 |
- _active_active_active_active_T_154; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_163 = _active_active_active_active_T_162 ? active_active_active_oh1_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_164 = _active_active_active_active_T_156 |
- _active_active_active_active_T_163; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_170 = _active_active_active_active_T_150 & active_active_active_idx_5 == 2'h2 |
- _active_active_active_active_T_154; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_171 = _active_active_active_active_T_170 ? active_active_active_oh2_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_172 = _active_active_active_active_T_164 |
- _active_active_active_active_T_171; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_178 = _active_active_active_active_T_150 & active_active_active_idx_5 == 2'h3 |
- _active_active_active_active_T_154; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_179 = _active_active_active_active_T_178 ? active_active_active_oh3_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_5 = _active_active_active_active_T_172 | _active_active_active_active_T_179; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_9 = f_io_entry_5_bits_tin_vs_valid ? active_active_active_active_5 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_9 = f_io_entry_5_valid ? active_active_active_9 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_16 = _active_T_15 | active_active_9; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_6 = f_io_entry_6_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_6 = 16'h1 << active_active_active_oh_shiftAmount_6; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_6 = {3'h0,active_active_active_oh_6[3],3'h0,active_active_active_oh_6[2],3'h0
- ,active_active_active_oh_6[1],3'h0,active_active_active_oh_6[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_6 = {3'h0,active_active_active_oh_6[7],3'h0,active_active_active_oh_6[6],3'h0,
- active_active_active_oh_6[5],3'h0,active_active_active_oh_6[4],active_active_active_oh0_lo_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_6 = {3'h0,active_active_active_oh_6[11],3'h0,active_active_active_oh_6[10],3'h0
- ,active_active_active_oh_6[9],3'h0,active_active_active_oh_6[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_6 = {3'h0,active_active_active_oh_6[15],3'h0,active_active_active_oh_6[14],3'h0,
- active_active_active_oh_6[13],3'h0,active_active_active_oh_6[12],active_active_active_oh0_hi_lo_6,
- active_active_active_oh0_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_6 = {2'h0,active_active_active_oh_6[1],1'h0,2'h0,
- active_active_active_oh_6[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_6 = {2'h0,active_active_active_oh_6[3],1'h0,2'h0,active_active_active_oh_6[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_6 = {2'h0,active_active_active_oh_6[5],1'h0,2'h0,
- active_active_active_oh_6[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_6 = {2'h0,active_active_active_oh_6[7],1'h0,2'h0,active_active_active_oh_6[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_6,active_active_active_oh1_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_6 = {2'h0,active_active_active_oh_6[9],1'h0,2'h0,
- active_active_active_oh_6[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_6 = {2'h0,active_active_active_oh_6[11],1'h0,2'h0,active_active_active_oh_6
- [10],1'h0,active_active_active_oh1_hi_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_6 = {2'h0,active_active_active_oh_6[13],1'h0,2'h0,
- active_active_active_oh_6[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_6 = {2'h0,active_active_active_oh_6[15],1'h0,2'h0,active_active_active_oh_6[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_6,active_active_active_oh1_hi_lo_6,active_active_active_oh1_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_6 = {1'h0,active_active_active_oh_6[1],2'h0,1'h0,
- active_active_active_oh_6[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_6 = {1'h0,active_active_active_oh_6[3],2'h0,1'h0,active_active_active_oh_6[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_6 = {1'h0,active_active_active_oh_6[5],2'h0,1'h0,
- active_active_active_oh_6[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_6 = {1'h0,active_active_active_oh_6[7],2'h0,1'h0,active_active_active_oh_6[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_6,active_active_active_oh2_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_6 = {1'h0,active_active_active_oh_6[9],2'h0,1'h0,
- active_active_active_oh_6[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_6 = {1'h0,active_active_active_oh_6[11],2'h0,1'h0,active_active_active_oh_6
- [10],2'h0,active_active_active_oh2_hi_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_6 = {1'h0,active_active_active_oh_6[13],2'h0,1'h0,
- active_active_active_oh_6[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_6 = {1'h0,active_active_active_oh_6[15],2'h0,1'h0,active_active_active_oh_6[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_6,active_active_active_oh2_hi_lo_6,active_active_active_oh2_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_6 = {active_active_active_oh_6[3],3'h0,active_active_active_oh_6[2],3'h0,
- active_active_active_oh_6[1],3'h0,active_active_active_oh_6[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_6 = {active_active_active_oh_6[7],3'h0,active_active_active_oh_6[6],3'h0,
- active_active_active_oh_6[5],3'h0,active_active_active_oh_6[4],3'h0,active_active_active_oh3_lo_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_6 = {active_active_active_oh_6[11],3'h0,active_active_active_oh_6[10],3'h0,
- active_active_active_oh_6[9],3'h0,active_active_active_oh_6[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_6 = {active_active_active_oh_6[15],3'h0,active_active_active_oh_6[14],3'h0,
- active_active_active_oh_6[13],3'h0,active_active_active_oh_6[12],3'h0,active_active_active_oh3_hi_lo_6,
- active_active_active_oh3_lo_6}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_6 = f_io_entry_6_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_180 = ~f_io_entry_6_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_184 = f_io_entry_6_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_185 = ~f_io_entry_6_bits_m & active_active_active_idx_6 == 2'h0 |
- f_io_entry_6_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_186 = _active_active_active_active_T_185 ? active_active_active_oh0_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_192 = _active_active_active_active_T_180 & active_active_active_idx_6 == 2'h1 |
- _active_active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_193 = _active_active_active_active_T_192 ? active_active_active_oh1_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_194 = _active_active_active_active_T_186 |
- _active_active_active_active_T_193; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_200 = _active_active_active_active_T_180 & active_active_active_idx_6 == 2'h2 |
- _active_active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_201 = _active_active_active_active_T_200 ? active_active_active_oh2_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_202 = _active_active_active_active_T_194 |
- _active_active_active_active_T_201; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_208 = _active_active_active_active_T_180 & active_active_active_idx_6 == 2'h3 |
- _active_active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_209 = _active_active_active_active_T_208 ? active_active_active_oh3_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_6 = _active_active_active_active_T_202 | _active_active_active_active_T_209; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_10 = f_io_entry_6_bits_tin_vs_valid ? active_active_active_active_6 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_10 = f_io_entry_6_valid ? active_active_active_10 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_17 = _active_T_16 | active_active_10; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_7 = f_io_entry_7_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_7 = 16'h1 << active_active_active_oh_shiftAmount_7; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_7 = {3'h0,active_active_active_oh_7[3],3'h0,active_active_active_oh_7[2],3'h0
- ,active_active_active_oh_7[1],3'h0,active_active_active_oh_7[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_7 = {3'h0,active_active_active_oh_7[7],3'h0,active_active_active_oh_7[6],3'h0,
- active_active_active_oh_7[5],3'h0,active_active_active_oh_7[4],active_active_active_oh0_lo_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_7 = {3'h0,active_active_active_oh_7[11],3'h0,active_active_active_oh_7[10],3'h0
- ,active_active_active_oh_7[9],3'h0,active_active_active_oh_7[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_7 = {3'h0,active_active_active_oh_7[15],3'h0,active_active_active_oh_7[14],3'h0,
- active_active_active_oh_7[13],3'h0,active_active_active_oh_7[12],active_active_active_oh0_hi_lo_7,
- active_active_active_oh0_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_7 = {2'h0,active_active_active_oh_7[1],1'h0,2'h0,
- active_active_active_oh_7[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_7 = {2'h0,active_active_active_oh_7[3],1'h0,2'h0,active_active_active_oh_7[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_7 = {2'h0,active_active_active_oh_7[5],1'h0,2'h0,
- active_active_active_oh_7[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_7 = {2'h0,active_active_active_oh_7[7],1'h0,2'h0,active_active_active_oh_7[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_7,active_active_active_oh1_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_7 = {2'h0,active_active_active_oh_7[9],1'h0,2'h0,
- active_active_active_oh_7[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_7 = {2'h0,active_active_active_oh_7[11],1'h0,2'h0,active_active_active_oh_7
- [10],1'h0,active_active_active_oh1_hi_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_7 = {2'h0,active_active_active_oh_7[13],1'h0,2'h0,
- active_active_active_oh_7[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_7 = {2'h0,active_active_active_oh_7[15],1'h0,2'h0,active_active_active_oh_7[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_7,active_active_active_oh1_hi_lo_7,active_active_active_oh1_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_7 = {1'h0,active_active_active_oh_7[1],2'h0,1'h0,
- active_active_active_oh_7[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_7 = {1'h0,active_active_active_oh_7[3],2'h0,1'h0,active_active_active_oh_7[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_7 = {1'h0,active_active_active_oh_7[5],2'h0,1'h0,
- active_active_active_oh_7[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_7 = {1'h0,active_active_active_oh_7[7],2'h0,1'h0,active_active_active_oh_7[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_7,active_active_active_oh2_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_7 = {1'h0,active_active_active_oh_7[9],2'h0,1'h0,
- active_active_active_oh_7[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_7 = {1'h0,active_active_active_oh_7[11],2'h0,1'h0,active_active_active_oh_7
- [10],2'h0,active_active_active_oh2_hi_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_7 = {1'h0,active_active_active_oh_7[13],2'h0,1'h0,
- active_active_active_oh_7[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_7 = {1'h0,active_active_active_oh_7[15],2'h0,1'h0,active_active_active_oh_7[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_7,active_active_active_oh2_hi_lo_7,active_active_active_oh2_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_7 = {active_active_active_oh_7[3],3'h0,active_active_active_oh_7[2],3'h0,
- active_active_active_oh_7[1],3'h0,active_active_active_oh_7[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_7 = {active_active_active_oh_7[7],3'h0,active_active_active_oh_7[6],3'h0,
- active_active_active_oh_7[5],3'h0,active_active_active_oh_7[4],3'h0,active_active_active_oh3_lo_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_7 = {active_active_active_oh_7[11],3'h0,active_active_active_oh_7[10],3'h0,
- active_active_active_oh_7[9],3'h0,active_active_active_oh_7[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_7 = {active_active_active_oh_7[15],3'h0,active_active_active_oh_7[14],3'h0,
- active_active_active_oh_7[13],3'h0,active_active_active_oh_7[12],3'h0,active_active_active_oh3_hi_lo_7,
- active_active_active_oh3_lo_7}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_7 = f_io_entry_7_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_210 = ~f_io_entry_7_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_214 = f_io_entry_7_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_215 = ~f_io_entry_7_bits_m & active_active_active_idx_7 == 2'h0 |
- f_io_entry_7_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_216 = _active_active_active_active_T_215 ? active_active_active_oh0_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_222 = _active_active_active_active_T_210 & active_active_active_idx_7 == 2'h1 |
- _active_active_active_active_T_214; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_223 = _active_active_active_active_T_222 ? active_active_active_oh1_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_224 = _active_active_active_active_T_216 |
- _active_active_active_active_T_223; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_230 = _active_active_active_active_T_210 & active_active_active_idx_7 == 2'h2 |
- _active_active_active_active_T_214; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_231 = _active_active_active_active_T_230 ? active_active_active_oh2_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_232 = _active_active_active_active_T_224 |
- _active_active_active_active_T_231; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_238 = _active_active_active_active_T_210 & active_active_active_idx_7 == 2'h3 |
- _active_active_active_active_T_214; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_239 = _active_active_active_active_T_238 ? active_active_active_oh3_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_7 = _active_active_active_active_T_232 | _active_active_active_active_T_239; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_11 = f_io_entry_7_bits_tin_vs_valid ? active_active_active_active_7 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_11 = f_io_entry_7_valid ? active_active_active_11 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_18 = _active_T_17 | active_active_11; // @[VCmdq.scala 107:24]
- wire [5:0] _active_active0_T = {{1'd0}, step}; // @[VCmdq.scala 110:48]
- wire [2:0] active_active0_stepq = _T_5 ? _active_active0_T[4:2] : _active_active0_T[2:0]; // @[VLdSt.scala 172:20]
- wire [3:0] active_active0_active_oh_shiftAmount = value_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active0_active_oh = 16'h1 << active_active0_active_oh_shiftAmount; // @[OneHot.scala 64:12]
- wire [15:0] active_active0_active_oh0_lo_lo = {3'h0,active_active0_active_oh[3],3'h0,active_active0_active_oh[2],3'h0,
- active_active0_active_oh[1],3'h0,active_active0_active_oh[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh0_lo = {3'h0,active_active0_active_oh[7],3'h0,active_active0_active_oh[6],3'h0,
- active_active0_active_oh[5],3'h0,active_active0_active_oh[4],active_active0_active_oh0_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh0_hi_lo = {3'h0,active_active0_active_oh[11],3'h0,active_active0_active_oh[10],3'h0
- ,active_active0_active_oh[9],3'h0,active_active0_active_oh[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh0 = {3'h0,active_active0_active_oh[15],3'h0,active_active0_active_oh[14],3'h0,
- active_active0_active_oh[13],3'h0,active_active0_active_oh[12],active_active0_active_oh0_hi_lo,
- active_active0_active_oh0_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_lo_lo = {2'h0,active_active0_active_oh[1],1'h0,2'h0,active_active0_active_oh[0
- ],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_lo_lo = {2'h0,active_active0_active_oh[3],1'h0,2'h0,active_active0_active_oh[2],1'h0
- ,active_active0_active_oh1_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_hi_lo = {2'h0,active_active0_active_oh[5],1'h0,2'h0,active_active0_active_oh[4
- ],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh1_lo = {2'h0,active_active0_active_oh[7],1'h0,2'h0,active_active0_active_oh[6],1'h0
- ,active_active0_active_oh1_lo_hi_lo,active_active0_active_oh1_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_lo_lo = {2'h0,active_active0_active_oh[9],1'h0,2'h0,active_active0_active_oh[8
- ],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_hi_lo = {2'h0,active_active0_active_oh[11],1'h0,2'h0,active_active0_active_oh[10
- ],1'h0,active_active0_active_oh1_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_hi_lo = {2'h0,active_active0_active_oh[13],1'h0,2'h0,active_active0_active_oh[
- 12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh1 = {2'h0,active_active0_active_oh[15],1'h0,2'h0,active_active0_active_oh[14],1'h0
- ,active_active0_active_oh1_hi_hi_lo,active_active0_active_oh1_hi_lo,active_active0_active_oh1_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_lo_lo = {1'h0,active_active0_active_oh[1],2'h0,1'h0,active_active0_active_oh[0
- ],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_lo_lo = {1'h0,active_active0_active_oh[3],2'h0,1'h0,active_active0_active_oh[2],2'h0
- ,active_active0_active_oh2_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_hi_lo = {1'h0,active_active0_active_oh[5],2'h0,1'h0,active_active0_active_oh[4
- ],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh2_lo = {1'h0,active_active0_active_oh[7],2'h0,1'h0,active_active0_active_oh[6],2'h0
- ,active_active0_active_oh2_lo_hi_lo,active_active0_active_oh2_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_lo_lo = {1'h0,active_active0_active_oh[9],2'h0,1'h0,active_active0_active_oh[8
- ],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_hi_lo = {1'h0,active_active0_active_oh[11],2'h0,1'h0,active_active0_active_oh[10
- ],2'h0,active_active0_active_oh2_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_hi_lo = {1'h0,active_active0_active_oh[13],2'h0,1'h0,active_active0_active_oh[
- 12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh2 = {1'h0,active_active0_active_oh[15],2'h0,1'h0,active_active0_active_oh[14],2'h0
- ,active_active0_active_oh2_hi_hi_lo,active_active0_active_oh2_hi_lo,active_active0_active_oh2_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_lo_lo = {active_active0_active_oh[3],3'h0,active_active0_active_oh[2],3'h0,
- active_active0_active_oh[1],3'h0,active_active0_active_oh[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh3_lo = {active_active0_active_oh[7],3'h0,active_active0_active_oh[6],3'h0,
- active_active0_active_oh[5],3'h0,active_active0_active_oh[4],3'h0,active_active0_active_oh3_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_hi_lo = {active_active0_active_oh[11],3'h0,active_active0_active_oh[10],3'h0,
- active_active0_active_oh[9],3'h0,active_active0_active_oh[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh3 = {active_active0_active_oh[15],3'h0,active_active0_active_oh[14],3'h0,
- active_active0_active_oh[13],3'h0,active_active0_active_oh[12],3'h0,active_active0_active_oh3_hi_lo,
- active_active0_active_oh3_lo}; // @[Cat.scala 31:58]
- wire [1:0] active_active0_active_idx = value_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active0_active_active_T_5 = _outlast1_T & active_active0_active_idx == 2'h0 | value_m &
- active_active0_stepq <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active0_active_active_T_6 = _active_active0_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active0_active_active_T_12 = _outlast1_T & active_active0_active_idx == 2'h1 | value_m &
- active_active0_stepq <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active0_active_active_T_13 = _active_active0_active_active_T_12 ? active_active0_active_oh1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_14 = _active_active0_active_active_T_6 |
- _active_active0_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active0_active_active_T_20 = _outlast1_T & active_active0_active_idx == 2'h2 | value_m &
- active_active0_stepq <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active0_active_active_T_21 = _active_active0_active_active_T_20 ? active_active0_active_oh2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_22 = _active_active0_active_active_T_14 |
- _active_active0_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active0_active_active_T_28 = _outlast1_T & active_active0_active_idx == 2'h3 | value_m &
- active_active0_stepq <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active0_active_active_T_29 = _active_active0_active_active_T_28 ? active_active0_active_oh3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active0_active_active = _active_active0_active_active_T_22 | _active_active0_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] active_active0 = value_tin_vs_valid ? active_active0_active_active : 64'h0; // @[Library.scala 22:8]
- wire [2:0] active_active1_stepq = _T_5 ? _out_quad_T_2[4:2] : _out_quad_T_2[2:0]; // @[VLdSt.scala 172:20]
- wire _active_active1_active_active_T_5 = _outlast1_T & active_active0_active_idx == 2'h0 | value_m &
- active_active1_stepq <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active1_active_active_T_6 = _active_active1_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active1_active_active_T_12 = _outlast1_T & active_active0_active_idx == 2'h1 | value_m &
- active_active1_stepq <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active1_active_active_T_13 = _active_active1_active_active_T_12 ? active_active0_active_oh1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_14 = _active_active1_active_active_T_6 |
- _active_active1_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active1_active_active_T_20 = _outlast1_T & active_active0_active_idx == 2'h2 | value_m &
- active_active1_stepq <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active1_active_active_T_21 = _active_active1_active_active_T_20 ? active_active0_active_oh2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_22 = _active_active1_active_active_T_14 |
- _active_active1_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active1_active_active_T_28 = _outlast1_T & active_active0_active_idx == 2'h3 | value_m &
- active_active1_stepq <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active1_active_active_T_29 = _active_active1_active_active_T_28 ? active_active0_active_oh3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active1_active_active = _active_active1_active_active_T_22 | _active_active1_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] active_active1 = value_tin_vs_valid ? active_active1_active_active : 64'h0; // @[Library.scala 22:8]
- wire _active_active_T_16 = ~io_out_ready; // @[VCmdq.scala 112:36]
- wire _active_active_T_19 = valid & (~io_out_ready | _T_12); // @[VCmdq.scala 112:32]
- wire [63:0] _active_active_T_21 = _active_active_T_16 ? active_active0 : active_active1; // @[VCmdq.scala 113:29]
- wire [63:0] active_active_12 = _active_active_T_19 ? _active_active_T_21 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_19 = _active_T_18 | active_active_12; // @[VCmdq.scala 114:12]
- wire [63:0] _active_T_20 = _active_T_10 | _active_T_19; // @[VCmdq.scala 127:90]
- Fifo4e_3 f ( // @[Fifo4e.scala 24:11]
- .clock(f_clock),
- .reset(f_reset),
- .io_in_ready(f_io_in_ready),
- .io_in_valid(f_io_in_valid),
- .io_in_bits_0_valid(f_io_in_bits_0_valid),
- .io_in_bits_0_bits_tin_op(f_io_in_bits_0_bits_tin_op),
- .io_in_bits_0_bits_tin_addr(f_io_in_bits_0_bits_tin_addr),
- .io_in_bits_0_bits_tin_offset(f_io_in_bits_0_bits_tin_offset),
- .io_in_bits_0_bits_tin_remain(f_io_in_bits_0_bits_tin_remain),
- .io_in_bits_0_bits_tin_vd_addr(f_io_in_bits_0_bits_tin_vd_addr),
- .io_in_bits_0_bits_tin_vs_valid(f_io_in_bits_0_bits_tin_vs_valid),
- .io_in_bits_0_bits_tin_vs_addr(f_io_in_bits_0_bits_tin_vs_addr),
- .io_in_bits_0_bits_tin_vs_tag(f_io_in_bits_0_bits_tin_vs_tag),
- .io_in_bits_0_bits_tin_last(f_io_in_bits_0_bits_tin_last),
- .io_in_bits_0_bits_m(f_io_in_bits_0_bits_m),
- .io_in_bits_1_valid(f_io_in_bits_1_valid),
- .io_in_bits_1_bits_tin_op(f_io_in_bits_1_bits_tin_op),
- .io_in_bits_1_bits_tin_addr(f_io_in_bits_1_bits_tin_addr),
- .io_in_bits_1_bits_tin_offset(f_io_in_bits_1_bits_tin_offset),
- .io_in_bits_1_bits_tin_remain(f_io_in_bits_1_bits_tin_remain),
- .io_in_bits_1_bits_tin_vd_addr(f_io_in_bits_1_bits_tin_vd_addr),
- .io_in_bits_1_bits_tin_vs_valid(f_io_in_bits_1_bits_tin_vs_valid),
- .io_in_bits_1_bits_tin_vs_addr(f_io_in_bits_1_bits_tin_vs_addr),
- .io_in_bits_1_bits_tin_vs_tag(f_io_in_bits_1_bits_tin_vs_tag),
- .io_in_bits_1_bits_tin_last(f_io_in_bits_1_bits_tin_last),
- .io_in_bits_1_bits_m(f_io_in_bits_1_bits_m),
- .io_in_bits_2_valid(f_io_in_bits_2_valid),
- .io_in_bits_2_bits_tin_op(f_io_in_bits_2_bits_tin_op),
- .io_in_bits_2_bits_tin_addr(f_io_in_bits_2_bits_tin_addr),
- .io_in_bits_2_bits_tin_offset(f_io_in_bits_2_bits_tin_offset),
- .io_in_bits_2_bits_tin_remain(f_io_in_bits_2_bits_tin_remain),
- .io_in_bits_2_bits_tin_vd_addr(f_io_in_bits_2_bits_tin_vd_addr),
- .io_in_bits_2_bits_tin_vs_valid(f_io_in_bits_2_bits_tin_vs_valid),
- .io_in_bits_2_bits_tin_vs_addr(f_io_in_bits_2_bits_tin_vs_addr),
- .io_in_bits_2_bits_tin_vs_tag(f_io_in_bits_2_bits_tin_vs_tag),
- .io_in_bits_2_bits_tin_last(f_io_in_bits_2_bits_tin_last),
- .io_in_bits_2_bits_m(f_io_in_bits_2_bits_m),
- .io_in_bits_3_valid(f_io_in_bits_3_valid),
- .io_in_bits_3_bits_tin_op(f_io_in_bits_3_bits_tin_op),
- .io_in_bits_3_bits_tin_addr(f_io_in_bits_3_bits_tin_addr),
- .io_in_bits_3_bits_tin_offset(f_io_in_bits_3_bits_tin_offset),
- .io_in_bits_3_bits_tin_remain(f_io_in_bits_3_bits_tin_remain),
- .io_in_bits_3_bits_tin_vd_addr(f_io_in_bits_3_bits_tin_vd_addr),
- .io_in_bits_3_bits_tin_vs_valid(f_io_in_bits_3_bits_tin_vs_valid),
- .io_in_bits_3_bits_tin_vs_addr(f_io_in_bits_3_bits_tin_vs_addr),
- .io_in_bits_3_bits_tin_vs_tag(f_io_in_bits_3_bits_tin_vs_tag),
- .io_in_bits_3_bits_tin_last(f_io_in_bits_3_bits_tin_last),
- .io_in_bits_3_bits_m(f_io_in_bits_3_bits_m),
- .io_out_ready(f_io_out_ready),
- .io_out_valid(f_io_out_valid),
- .io_out_bits_tin_op(f_io_out_bits_tin_op),
- .io_out_bits_tin_addr(f_io_out_bits_tin_addr),
- .io_out_bits_tin_offset(f_io_out_bits_tin_offset),
- .io_out_bits_tin_remain(f_io_out_bits_tin_remain),
- .io_out_bits_tin_vd_addr(f_io_out_bits_tin_vd_addr),
- .io_out_bits_tin_vs_valid(f_io_out_bits_tin_vs_valid),
- .io_out_bits_tin_vs_addr(f_io_out_bits_tin_vs_addr),
- .io_out_bits_tin_vs_tag(f_io_out_bits_tin_vs_tag),
- .io_out_bits_tin_quad(f_io_out_bits_tin_quad),
- .io_out_bits_tin_last(f_io_out_bits_tin_last),
- .io_out_bits_m(f_io_out_bits_m),
- .io_entry_0_valid(f_io_entry_0_valid),
- .io_entry_0_bits_tin_vs_valid(f_io_entry_0_bits_tin_vs_valid),
- .io_entry_0_bits_tin_vs_addr(f_io_entry_0_bits_tin_vs_addr),
- .io_entry_0_bits_m(f_io_entry_0_bits_m),
- .io_entry_1_valid(f_io_entry_1_valid),
- .io_entry_1_bits_tin_vs_valid(f_io_entry_1_bits_tin_vs_valid),
- .io_entry_1_bits_tin_vs_addr(f_io_entry_1_bits_tin_vs_addr),
- .io_entry_1_bits_m(f_io_entry_1_bits_m),
- .io_entry_2_valid(f_io_entry_2_valid),
- .io_entry_2_bits_tin_vs_valid(f_io_entry_2_bits_tin_vs_valid),
- .io_entry_2_bits_tin_vs_addr(f_io_entry_2_bits_tin_vs_addr),
- .io_entry_2_bits_m(f_io_entry_2_bits_m),
- .io_entry_3_valid(f_io_entry_3_valid),
- .io_entry_3_bits_tin_vs_valid(f_io_entry_3_bits_tin_vs_valid),
- .io_entry_3_bits_tin_vs_addr(f_io_entry_3_bits_tin_vs_addr),
- .io_entry_3_bits_m(f_io_entry_3_bits_m),
- .io_entry_4_valid(f_io_entry_4_valid),
- .io_entry_4_bits_tin_vs_valid(f_io_entry_4_bits_tin_vs_valid),
- .io_entry_4_bits_tin_vs_addr(f_io_entry_4_bits_tin_vs_addr),
- .io_entry_4_bits_m(f_io_entry_4_bits_m),
- .io_entry_5_valid(f_io_entry_5_valid),
- .io_entry_5_bits_tin_vs_valid(f_io_entry_5_bits_tin_vs_valid),
- .io_entry_5_bits_tin_vs_addr(f_io_entry_5_bits_tin_vs_addr),
- .io_entry_5_bits_m(f_io_entry_5_bits_m),
- .io_entry_6_valid(f_io_entry_6_valid),
- .io_entry_6_bits_tin_vs_valid(f_io_entry_6_bits_tin_vs_valid),
- .io_entry_6_bits_tin_vs_addr(f_io_entry_6_bits_tin_vs_addr),
- .io_entry_6_bits_m(f_io_entry_6_bits_m),
- .io_entry_7_valid(f_io_entry_7_valid),
- .io_entry_7_bits_tin_vs_valid(f_io_entry_7_bits_tin_vs_valid),
- .io_entry_7_bits_tin_vs_addr(f_io_entry_7_bits_tin_vs_addr),
- .io_entry_7_bits_m(f_io_entry_7_bits_m)
- );
- assign io_in_ready = f_io_in_ready; // @[VCmdq.scala 65:15]
- assign io_out_valid = valid; // @[VCmdq.scala 133:16]
- assign io_out_bits_op = value_tin_op; // @[VCmdq.scala 134:15]
- assign io_out_bits_addr = value_tin_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_remain = value_tin_remain; // @[VCmdq.scala 134:15]
- assign io_out_bits_vd_addr = value_tin_vd_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_vs_valid = value_tin_vs_valid; // @[VCmdq.scala 134:15]
- assign io_out_bits_vs_addr = value_tin_vs_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_vs_tag = value_tin_vs_tag; // @[VCmdq.scala 134:15]
- assign io_out_bits_quad = value_tin_quad; // @[VCmdq.scala 134:15]
- assign io_out_bits_last = value_tin_last; // @[VCmdq.scala 134:15]
- assign io_active = active; // @[VCmdq.scala 136:13]
- assign f_clock = clock;
- assign f_reset = reset;
- assign f_io_in_valid = io_in_valid; // @[VCmdq.scala 64:17]
- assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VLdSt.scala 103:19 122:12]
- assign f_io_in_bits_0_bits_tin_addr = io_in_bits_0_bits_sv_addr; // @[VLdSt.scala 103:19 125:14]
- assign f_io_in_bits_0_bits_tin_offset = f_io_in_bits_0_bits_tin_stride ? f_io_in_bits_0_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_0_bits_tin_out_offset_T_3}; // @[VLdSt.scala 126:22]
- assign f_io_in_bits_0_bits_tin_remain = f_io_in_bits_0_bits_tin_length ? f_io_in_bits_0_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 127:22]
- assign f_io_in_bits_0_bits_tin_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLdSt.scala 103:19 128:12]
- assign f_io_in_bits_0_bits_tin_vs_valid = io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 103:19 129:12]
- assign f_io_in_bits_0_bits_tin_vs_addr = io_in_bits_0_bits_vs_addr; // @[VLdSt.scala 103:19 129:12]
- assign f_io_in_bits_0_bits_tin_vs_tag = io_in_bits_0_bits_vs_tag; // @[VLdSt.scala 103:19 129:12]
- assign f_io_in_bits_0_bits_tin_last = ~io_in_bits_0_bits_m & io_in_bits_0_bits_op != 7'h4; // @[VLdSt.scala 130:23]
- assign f_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VLdSt.scala 103:19 122:12]
- assign f_io_in_bits_1_bits_tin_addr = io_in_bits_1_bits_sv_addr; // @[VLdSt.scala 103:19 125:14]
- assign f_io_in_bits_1_bits_tin_offset = f_io_in_bits_1_bits_tin_stride ? f_io_in_bits_1_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_1_bits_tin_out_offset_T_3}; // @[VLdSt.scala 126:22]
- assign f_io_in_bits_1_bits_tin_remain = f_io_in_bits_1_bits_tin_length ? f_io_in_bits_1_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 127:22]
- assign f_io_in_bits_1_bits_tin_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLdSt.scala 103:19 128:12]
- assign f_io_in_bits_1_bits_tin_vs_valid = io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 103:19 129:12]
- assign f_io_in_bits_1_bits_tin_vs_addr = io_in_bits_1_bits_vs_addr; // @[VLdSt.scala 103:19 129:12]
- assign f_io_in_bits_1_bits_tin_vs_tag = io_in_bits_1_bits_vs_tag; // @[VLdSt.scala 103:19 129:12]
- assign f_io_in_bits_1_bits_tin_last = ~io_in_bits_1_bits_m & io_in_bits_1_bits_op != 7'h4; // @[VLdSt.scala 130:23]
- assign f_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VLdSt.scala 103:19 122:12]
- assign f_io_in_bits_2_bits_tin_addr = io_in_bits_2_bits_sv_addr; // @[VLdSt.scala 103:19 125:14]
- assign f_io_in_bits_2_bits_tin_offset = f_io_in_bits_2_bits_tin_stride ? f_io_in_bits_2_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_2_bits_tin_out_offset_T_3}; // @[VLdSt.scala 126:22]
- assign f_io_in_bits_2_bits_tin_remain = f_io_in_bits_2_bits_tin_length ? f_io_in_bits_2_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 127:22]
- assign f_io_in_bits_2_bits_tin_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLdSt.scala 103:19 128:12]
- assign f_io_in_bits_2_bits_tin_vs_valid = io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 103:19 129:12]
- assign f_io_in_bits_2_bits_tin_vs_addr = io_in_bits_2_bits_vs_addr; // @[VLdSt.scala 103:19 129:12]
- assign f_io_in_bits_2_bits_tin_vs_tag = io_in_bits_2_bits_vs_tag; // @[VLdSt.scala 103:19 129:12]
- assign f_io_in_bits_2_bits_tin_last = ~io_in_bits_2_bits_m & io_in_bits_2_bits_op != 7'h4; // @[VLdSt.scala 130:23]
- assign f_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VLdSt.scala 103:19 122:12]
- assign f_io_in_bits_3_bits_tin_addr = io_in_bits_3_bits_sv_addr; // @[VLdSt.scala 103:19 125:14]
- assign f_io_in_bits_3_bits_tin_offset = f_io_in_bits_3_bits_tin_stride ? f_io_in_bits_3_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_3_bits_tin_out_offset_T_3}; // @[VLdSt.scala 126:22]
- assign f_io_in_bits_3_bits_tin_remain = f_io_in_bits_3_bits_tin_length ? f_io_in_bits_3_bits_tin_remain1 : 8'h80; // @[VLdSt.scala 127:22]
- assign f_io_in_bits_3_bits_tin_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLdSt.scala 103:19 128:12]
- assign f_io_in_bits_3_bits_tin_vs_valid = io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 103:19 129:12]
- assign f_io_in_bits_3_bits_tin_vs_addr = io_in_bits_3_bits_vs_addr; // @[VLdSt.scala 103:19 129:12]
- assign f_io_in_bits_3_bits_tin_vs_tag = io_in_bits_3_bits_vs_tag; // @[VLdSt.scala 103:19 129:12]
- assign f_io_in_bits_3_bits_tin_last = ~io_in_bits_3_bits_m & io_in_bits_3_bits_op != 7'h4; // @[VLdSt.scala 130:23]
- assign f_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_out_ready = _T | io_out_ready & last; // @[VCmdq.scala 73:28]
- always @(posedge clock) begin
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_op <= 7'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_op <= f_io_out_bits_tin_op; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_op <= 7'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_addr <= 32'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_addr <= f_io_out_bits_tin_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_addr <= tin_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_addr <= 32'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_offset <= 32'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_offset <= f_io_out_bits_tin_offset; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_offset <= 32'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_remain <= 8'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_remain <= f_io_out_bits_tin_remain; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_remain <= tin_remain; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_remain <= 8'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vd_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vd_addr <= f_io_out_bits_tin_vd_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_vd_addr <= tin_vd_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_vd_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vs_valid <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vs_valid <= f_io_out_bits_tin_vs_valid; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_vs_valid <= _GEN_5;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vs_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vs_addr <= f_io_out_bits_tin_vs_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_vs_addr <= tin_vs_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_vs_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vs_tag <= 4'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vs_tag <= f_io_out_bits_tin_vs_tag; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_vs_tag <= 4'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_quad <= 2'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_quad <= f_io_out_bits_tin_quad; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_quad <= tin_quad; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_quad <= 2'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_last <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_last <= f_io_out_bits_tin_last; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_last <= _GEN_1;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_m <= 1'h0; // @[VCmdq.scala 98:13]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_m <= f_io_out_bits_m; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_m <= _GEN_14;
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~valid | value_tin_op == 7'h2 | value_tin_op == 7'h3 | value_tin_op == 7'h4)) begin
- $fatal; // @[VLdSt.scala 138:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~valid | value_tin_op == 7'h2 | value_tin_op == 7'h3 | value_tin_op == 7'h4)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:138 assert(!valid || in.op === e.vld.U || in.op === e.vst.U || in.op === e.vstq.U)\n"
- ); // @[VLdSt.scala 138:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLdSt.scala 106:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:106 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 106:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h3 & (io_in_bits_0_bits_vd_valid | ~io_in_bits_0_bits_vs_valid)))
- ) begin
- $fatal; // @[VLdSt.scala 107:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h3 & (io_in_bits_0_bits_vd_valid | ~io_in_bits_0_bits_vs_valid)))
- ) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:107 assert(!(in.op === e.vst.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 107:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h4 & _f_io_in_bits_0_bits_tin_T_13))) begin
- $fatal; // @[VLdSt.scala 108:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h4 & _f_io_in_bits_0_bits_tin_T_13))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:108 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 108:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h2 & (~io_in_bits_0_bits_vd_valid | io_in_bits_0_bits_vs_valid)))
- ) begin
- $fatal; // @[VLdSt.scala 109:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_0_bits_op == 7'h2 & (~io_in_bits_0_bits_vd_valid | io_in_bits_0_bits_vs_valid)))
- ) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:109 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"
- ); // @[VLdSt.scala 109:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLdSt.scala 106:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:106 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 106:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h3 & (io_in_bits_1_bits_vd_valid | ~io_in_bits_1_bits_vs_valid)))
- ) begin
- $fatal; // @[VLdSt.scala 107:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h3 & (io_in_bits_1_bits_vd_valid | ~io_in_bits_1_bits_vs_valid)))
- ) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:107 assert(!(in.op === e.vst.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 107:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h4 & _f_io_in_bits_1_bits_tin_T_13))) begin
- $fatal; // @[VLdSt.scala 108:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h4 & _f_io_in_bits_1_bits_tin_T_13))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:108 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 108:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h2 & (~io_in_bits_1_bits_vd_valid | io_in_bits_1_bits_vs_valid)))
- ) begin
- $fatal; // @[VLdSt.scala 109:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_1_bits_op == 7'h2 & (~io_in_bits_1_bits_vd_valid | io_in_bits_1_bits_vs_valid)))
- ) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:109 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"
- ); // @[VLdSt.scala 109:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLdSt.scala 106:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:106 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 106:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h3 & (io_in_bits_2_bits_vd_valid | ~io_in_bits_2_bits_vs_valid)))
- ) begin
- $fatal; // @[VLdSt.scala 107:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h3 & (io_in_bits_2_bits_vd_valid | ~io_in_bits_2_bits_vs_valid)))
- ) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:107 assert(!(in.op === e.vst.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 107:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h4 & _f_io_in_bits_2_bits_tin_T_13))) begin
- $fatal; // @[VLdSt.scala 108:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h4 & _f_io_in_bits_2_bits_tin_T_13))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:108 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 108:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h2 & (~io_in_bits_2_bits_vd_valid | io_in_bits_2_bits_vs_valid)))
- ) begin
- $fatal; // @[VLdSt.scala 109:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_2_bits_op == 7'h2 & (~io_in_bits_2_bits_vd_valid | io_in_bits_2_bits_vs_valid)))
- ) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:109 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"
- ); // @[VLdSt.scala 109:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLdSt.scala 106:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:106 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLdSt.scala 106:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h3 & (io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid)))
- ) begin
- $fatal; // @[VLdSt.scala 107:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h3 & (io_in_bits_3_bits_vd_valid | ~io_in_bits_3_bits_vs_valid)))
- ) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:107 assert(!(in.op === e.vst.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 107:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_13))) begin
- $fatal; // @[VLdSt.scala 108:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_13))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:108 assert(!(in.op === e.vstq.U && ( in.vd.valid || !in.vs.valid)))\n"
- ); // @[VLdSt.scala 108:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h2 & (~io_in_bits_3_bits_vd_valid | io_in_bits_3_bits_vs_valid)))
- ) begin
- $fatal; // @[VLdSt.scala 109:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_8 & ~(~(io_in_bits_3_bits_op == 7'h2 & (~io_in_bits_3_bits_vd_valid | io_in_bits_3_bits_vs_valid)))
- ) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:109 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"
- ); // @[VLdSt.scala 109:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_16 & _T_8 & ~(active_active0_stepq <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_16 & _T_8 & ~(active_active0_stepq <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_16 & _T_8 & ~(active_active1_stepq <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_16 & _T_8 & ~(active_active1_stepq <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 118:69]
- active <= 64'h0; // @[VCmdq.scala 123:12]
- end else if (io_in_valid & io_in_ready | _T_11) begin // @[VCmdq.scala 49:23]
- active <= _active_T_20;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 77:43]
- valid <= 1'h0; // @[VCmdq.scala 78:11]
- end else begin
- valid <= f_io_out_valid & f_io_out_ready | _GEN_16;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 77:43]
- step <= 5'h0; // @[VCmdq.scala 80:10]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 81:46]
- step <= 5'h0; // @[VCmdq.scala 82:18 86:12 92:12]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 58:21]
- if (~last) begin
- step <= _out_quad_T_2;
- end else begin
- step <= 5'h0;
- end
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {2{`RANDOM}};
- active = _RAND_0[63:0];
- _RAND_1 = {1{`RANDOM}};
- valid = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- value_tin_op = _RAND_2[6:0];
- _RAND_3 = {1{`RANDOM}};
- value_tin_addr = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- value_tin_offset = _RAND_4[31:0];
- _RAND_5 = {1{`RANDOM}};
- value_tin_remain = _RAND_5[7:0];
- _RAND_6 = {1{`RANDOM}};
- value_tin_vd_addr = _RAND_6[5:0];
- _RAND_7 = {1{`RANDOM}};
- value_tin_vs_valid = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- value_tin_vs_addr = _RAND_8[5:0];
- _RAND_9 = {1{`RANDOM}};
- value_tin_vs_tag = _RAND_9[3:0];
- _RAND_10 = {1{`RANDOM}};
- value_tin_quad = _RAND_10[1:0];
- _RAND_11 = {1{`RANDOM}};
- value_tin_last = _RAND_11[0:0];
- _RAND_12 = {1{`RANDOM}};
- value_m = _RAND_12[0:0];
- _RAND_13 = {1{`RANDOM}};
- step = _RAND_13[4:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- active = 64'h0;
- end
- if (reset) begin
- valid = 1'h0;
- end
- if (reset) begin
- step = 5'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Fifo(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_last,
- input io_in_bits_write,
- input [31:0] io_in_bits_addr,
- input [31:0] io_in_bits_adrx,
- input [5:0] io_in_bits_size,
- input [5:0] io_in_bits_widx,
- input io_out_ready,
- output io_out_valid,
- output io_out_bits_last,
- output io_out_bits_write,
- output [31:0] io_out_bits_addr,
- output [31:0] io_out_bits_adrx,
- output [5:0] io_out_bits_size,
- output [5:0] io_out_bits_widx
-);
-`ifdef RANDOMIZE_MEM_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
-`endif // RANDOMIZE_REG_INIT
- reg mem_last [0:1]; // @[Fifo.scala 36:16]
- wire mem_last_rdata_MPORT_en; // @[Fifo.scala 36:16]
- wire mem_last_rdata_MPORT_addr; // @[Fifo.scala 36:16]
- wire mem_last_rdata_MPORT_data; // @[Fifo.scala 36:16]
- wire mem_last_MPORT_data; // @[Fifo.scala 36:16]
- wire mem_last_MPORT_addr; // @[Fifo.scala 36:16]
- wire mem_last_MPORT_mask; // @[Fifo.scala 36:16]
- wire mem_last_MPORT_en; // @[Fifo.scala 36:16]
- reg mem_write [0:1]; // @[Fifo.scala 36:16]
- wire mem_write_rdata_MPORT_en; // @[Fifo.scala 36:16]
- wire mem_write_rdata_MPORT_addr; // @[Fifo.scala 36:16]
- wire mem_write_rdata_MPORT_data; // @[Fifo.scala 36:16]
- wire mem_write_MPORT_data; // @[Fifo.scala 36:16]
- wire mem_write_MPORT_addr; // @[Fifo.scala 36:16]
- wire mem_write_MPORT_mask; // @[Fifo.scala 36:16]
- wire mem_write_MPORT_en; // @[Fifo.scala 36:16]
- reg [31:0] mem_addr [0:1]; // @[Fifo.scala 36:16]
- wire mem_addr_rdata_MPORT_en; // @[Fifo.scala 36:16]
- wire mem_addr_rdata_MPORT_addr; // @[Fifo.scala 36:16]
- wire [31:0] mem_addr_rdata_MPORT_data; // @[Fifo.scala 36:16]
- wire [31:0] mem_addr_MPORT_data; // @[Fifo.scala 36:16]
- wire mem_addr_MPORT_addr; // @[Fifo.scala 36:16]
- wire mem_addr_MPORT_mask; // @[Fifo.scala 36:16]
- wire mem_addr_MPORT_en; // @[Fifo.scala 36:16]
- reg [31:0] mem_adrx [0:1]; // @[Fifo.scala 36:16]
- wire mem_adrx_rdata_MPORT_en; // @[Fifo.scala 36:16]
- wire mem_adrx_rdata_MPORT_addr; // @[Fifo.scala 36:16]
- wire [31:0] mem_adrx_rdata_MPORT_data; // @[Fifo.scala 36:16]
- wire [31:0] mem_adrx_MPORT_data; // @[Fifo.scala 36:16]
- wire mem_adrx_MPORT_addr; // @[Fifo.scala 36:16]
- wire mem_adrx_MPORT_mask; // @[Fifo.scala 36:16]
- wire mem_adrx_MPORT_en; // @[Fifo.scala 36:16]
- reg [5:0] mem_size [0:1]; // @[Fifo.scala 36:16]
- wire mem_size_rdata_MPORT_en; // @[Fifo.scala 36:16]
- wire mem_size_rdata_MPORT_addr; // @[Fifo.scala 36:16]
- wire [5:0] mem_size_rdata_MPORT_data; // @[Fifo.scala 36:16]
- wire [5:0] mem_size_MPORT_data; // @[Fifo.scala 36:16]
- wire mem_size_MPORT_addr; // @[Fifo.scala 36:16]
- wire mem_size_MPORT_mask; // @[Fifo.scala 36:16]
- wire mem_size_MPORT_en; // @[Fifo.scala 36:16]
- reg [5:0] mem_widx [0:1]; // @[Fifo.scala 36:16]
- wire mem_widx_rdata_MPORT_en; // @[Fifo.scala 36:16]
- wire mem_widx_rdata_MPORT_addr; // @[Fifo.scala 36:16]
- wire [5:0] mem_widx_rdata_MPORT_data; // @[Fifo.scala 36:16]
- wire [5:0] mem_widx_MPORT_data; // @[Fifo.scala 36:16]
- wire mem_widx_MPORT_addr; // @[Fifo.scala 36:16]
- wire mem_widx_MPORT_mask; // @[Fifo.scala 36:16]
- wire mem_widx_MPORT_en; // @[Fifo.scala 36:16]
- reg rdata_last; // @[Fifo.scala 37:18]
- reg rdata_write; // @[Fifo.scala 37:18]
- reg [31:0] rdata_addr; // @[Fifo.scala 37:18]
- reg [31:0] rdata_adrx; // @[Fifo.scala 37:18]
- reg [5:0] rdata_size; // @[Fifo.scala 37:18]
- reg [5:0] rdata_widx; // @[Fifo.scala 37:18]
- reg rvalid; // @[Fifo.scala 39:23]
- reg wready; // @[Fifo.scala 40:23]
- reg raddr; // @[Fifo.scala 41:22]
- reg waddr; // @[Fifo.scala 42:22]
- reg [1:0] count; // @[Fifo.scala 43:22]
- wire winc = io_in_valid & io_in_ready; // @[Fifo.scala 47:26]
- wire rinc = (~rvalid | io_out_ready) & (winc | count > 2'h1); // @[Fifo.scala 48:40]
- wire forward = rinc & winc & count <= 2'h1; // @[Fifo.scala 58:30]
- wire oen = io_out_valid & io_out_ready; // @[Fifo.scala 63:26]
- wire _T_1 = winc & ~oen; // @[Fifo.scala 65:13]
- wire [1:0] _count_T_1 = count + 2'h1; // @[Fifo.scala 66:20]
- wire _T_2 = ~winc; // @[Fifo.scala 67:16]
- wire [1:0] _count_T_3 = count - 2'h1; // @[Fifo.scala 68:20]
- wire _GEN_4 = io_out_ready & count == 2'h1 ? 1'h0 : rvalid; // @[Fifo.scala 73:47 74:12 39:23]
- wire _wready_T_5 = count == 2'h2 & ~_T_1; // @[Fifo.scala 78:33]
- wire _wready_T_6 = count < 2'h2 | _wready_T_5; // @[Fifo.scala 77:31]
- wire _wready_T_8 = oen & _T_2; // @[Fifo.scala 79:18]
- wire _T_6 = ~forward; // @[Fifo.scala 83:17]
- wire _T_10 = ~reset; // @[Fifo.scala 106:9]
- assign mem_last_rdata_MPORT_en = forward ? 1'h0 : rinc;
- assign mem_last_rdata_MPORT_addr = raddr;
- assign mem_last_rdata_MPORT_data = mem_last[mem_last_rdata_MPORT_addr]; // @[Fifo.scala 36:16]
- assign mem_last_MPORT_data = io_in_bits_last;
- assign mem_last_MPORT_addr = waddr;
- assign mem_last_MPORT_mask = 1'h1;
- assign mem_last_MPORT_en = winc & _T_6;
- assign mem_write_rdata_MPORT_en = forward ? 1'h0 : rinc;
- assign mem_write_rdata_MPORT_addr = raddr;
- assign mem_write_rdata_MPORT_data = mem_write[mem_write_rdata_MPORT_addr]; // @[Fifo.scala 36:16]
- assign mem_write_MPORT_data = io_in_bits_write;
- assign mem_write_MPORT_addr = waddr;
- assign mem_write_MPORT_mask = 1'h1;
- assign mem_write_MPORT_en = winc & _T_6;
- assign mem_addr_rdata_MPORT_en = forward ? 1'h0 : rinc;
- assign mem_addr_rdata_MPORT_addr = raddr;
- assign mem_addr_rdata_MPORT_data = mem_addr[mem_addr_rdata_MPORT_addr]; // @[Fifo.scala 36:16]
- assign mem_addr_MPORT_data = io_in_bits_addr;
- assign mem_addr_MPORT_addr = waddr;
- assign mem_addr_MPORT_mask = 1'h1;
- assign mem_addr_MPORT_en = winc & _T_6;
- assign mem_adrx_rdata_MPORT_en = forward ? 1'h0 : rinc;
- assign mem_adrx_rdata_MPORT_addr = raddr;
- assign mem_adrx_rdata_MPORT_data = mem_adrx[mem_adrx_rdata_MPORT_addr]; // @[Fifo.scala 36:16]
- assign mem_adrx_MPORT_data = io_in_bits_adrx;
- assign mem_adrx_MPORT_addr = waddr;
- assign mem_adrx_MPORT_mask = 1'h1;
- assign mem_adrx_MPORT_en = winc & _T_6;
- assign mem_size_rdata_MPORT_en = forward ? 1'h0 : rinc;
- assign mem_size_rdata_MPORT_addr = raddr;
- assign mem_size_rdata_MPORT_data = mem_size[mem_size_rdata_MPORT_addr]; // @[Fifo.scala 36:16]
- assign mem_size_MPORT_data = io_in_bits_size;
- assign mem_size_MPORT_addr = waddr;
- assign mem_size_MPORT_mask = 1'h1;
- assign mem_size_MPORT_en = winc & _T_6;
- assign mem_widx_rdata_MPORT_en = forward ? 1'h0 : rinc;
- assign mem_widx_rdata_MPORT_addr = raddr;
- assign mem_widx_rdata_MPORT_data = mem_widx[mem_widx_rdata_MPORT_addr]; // @[Fifo.scala 36:16]
- assign mem_widx_MPORT_data = io_in_bits_widx;
- assign mem_widx_MPORT_addr = waddr;
- assign mem_widx_MPORT_mask = 1'h1;
- assign mem_widx_MPORT_en = winc & _T_6;
- assign io_in_ready = wready; // @[Fifo.scala 101:17]
- assign io_out_valid = rvalid; // @[Fifo.scala 95:16]
- assign io_out_bits_last = rdata_last; // @[Fifo.scala 96:15]
- assign io_out_bits_write = rdata_write; // @[Fifo.scala 96:15]
- assign io_out_bits_addr = rdata_addr; // @[Fifo.scala 96:15]
- assign io_out_bits_adrx = rdata_adrx; // @[Fifo.scala 96:15]
- assign io_out_bits_size = rdata_size; // @[Fifo.scala 96:15]
- assign io_out_bits_widx = rdata_widx; // @[Fifo.scala 96:15]
- always @(posedge clock) begin
- if (mem_last_MPORT_en & mem_last_MPORT_mask) begin
- mem_last[mem_last_MPORT_addr] <= mem_last_MPORT_data; // @[Fifo.scala 36:16]
- end
- if (mem_write_MPORT_en & mem_write_MPORT_mask) begin
- mem_write[mem_write_MPORT_addr] <= mem_write_MPORT_data; // @[Fifo.scala 36:16]
- end
- if (mem_addr_MPORT_en & mem_addr_MPORT_mask) begin
- mem_addr[mem_addr_MPORT_addr] <= mem_addr_MPORT_data; // @[Fifo.scala 36:16]
- end
- if (mem_adrx_MPORT_en & mem_adrx_MPORT_mask) begin
- mem_adrx[mem_adrx_MPORT_addr] <= mem_adrx_MPORT_data; // @[Fifo.scala 36:16]
- end
- if (mem_size_MPORT_en & mem_size_MPORT_mask) begin
- mem_size[mem_size_MPORT_addr] <= mem_size_MPORT_data; // @[Fifo.scala 36:16]
- end
- if (mem_widx_MPORT_en & mem_widx_MPORT_mask) begin
- mem_widx[mem_widx_MPORT_addr] <= mem_widx_MPORT_data; // @[Fifo.scala 36:16]
- end
- if (forward) begin // @[Fifo.scala 87:18]
- rdata_last <= io_in_bits_last; // @[Fifo.scala 88:11]
- end else if (rinc) begin // @[Fifo.scala 89:22]
- rdata_last <= mem_last_rdata_MPORT_data; // @[Fifo.scala 90:11]
- end
- if (forward) begin // @[Fifo.scala 87:18]
- rdata_write <= io_in_bits_write; // @[Fifo.scala 88:11]
- end else if (rinc) begin // @[Fifo.scala 89:22]
- rdata_write <= mem_write_rdata_MPORT_data; // @[Fifo.scala 90:11]
- end
- if (forward) begin // @[Fifo.scala 87:18]
- rdata_addr <= io_in_bits_addr; // @[Fifo.scala 88:11]
- end else if (rinc) begin // @[Fifo.scala 89:22]
- rdata_addr <= mem_addr_rdata_MPORT_data; // @[Fifo.scala 90:11]
- end
- if (forward) begin // @[Fifo.scala 87:18]
- rdata_adrx <= io_in_bits_adrx; // @[Fifo.scala 88:11]
- end else if (rinc) begin // @[Fifo.scala 89:22]
- rdata_adrx <= mem_adrx_rdata_MPORT_data; // @[Fifo.scala 90:11]
- end
- if (forward) begin // @[Fifo.scala 87:18]
- rdata_size <= io_in_bits_size; // @[Fifo.scala 88:11]
- end else if (rinc) begin // @[Fifo.scala 89:22]
- rdata_size <= mem_size_rdata_MPORT_data; // @[Fifo.scala 90:11]
- end
- if (forward) begin // @[Fifo.scala 87:18]
- rdata_widx <= io_in_bits_widx; // @[Fifo.scala 88:11]
- end else if (rinc) begin // @[Fifo.scala 89:22]
- rdata_widx <= mem_widx_rdata_MPORT_data; // @[Fifo.scala 90:11]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_10 & ~(~(io_in_ready & count == 2'h3))) begin
- $fatal; // @[Fifo.scala 107:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_10 & ~(~(io_in_ready & count == 2'h3))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fifo.scala:107 assert(!(!passReady.B && io.in.ready && count === n.U))\n"); // @[Fifo.scala 107:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo.scala 71:14]
- rvalid <= 1'h0; // @[Fifo.scala 72:12]
- end else begin
- rvalid <= winc | _GEN_4;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo.scala 78:51]
- wready <= 1'h0;
- end else begin
- wready <= _wready_T_6 | _wready_T_8;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo.scala 54:15]
- raddr <= 1'h0; // @[Fifo.scala 55:17]
- end else if (rinc) begin // @[Fifo.scala 41:22]
- if (raddr) begin
- raddr <= 1'h0;
- end else begin
- raddr <= raddr + 1'h1;
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo.scala 50:15]
- waddr <= 1'h0; // @[Fifo.scala 51:17]
- end else if (winc) begin // @[Fifo.scala 42:22]
- if (waddr) begin
- waddr <= 1'h0;
- end else begin
- waddr <= waddr + 1'h1;
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo.scala 65:22]
- count <= 2'h0; // @[Fifo.scala 66:11]
- end else if (winc & ~oen) begin // @[Fifo.scala 67:29]
- count <= _count_T_1; // @[Fifo.scala 68:11]
- end else if (~winc & oen) begin // @[Fifo.scala 43:22]
- count <= _count_T_3;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_MEM_INIT
- _RAND_0 = {1{`RANDOM}};
- for (initvar = 0; initvar < 2; initvar = initvar+1)
- mem_last[initvar] = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- for (initvar = 0; initvar < 2; initvar = initvar+1)
- mem_write[initvar] = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- for (initvar = 0; initvar < 2; initvar = initvar+1)
- mem_addr[initvar] = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- for (initvar = 0; initvar < 2; initvar = initvar+1)
- mem_adrx[initvar] = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- for (initvar = 0; initvar < 2; initvar = initvar+1)
- mem_size[initvar] = _RAND_4[5:0];
- _RAND_5 = {1{`RANDOM}};
- for (initvar = 0; initvar < 2; initvar = initvar+1)
- mem_widx[initvar] = _RAND_5[5:0];
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- _RAND_6 = {1{`RANDOM}};
- rdata_last = _RAND_6[0:0];
- _RAND_7 = {1{`RANDOM}};
- rdata_write = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- rdata_addr = _RAND_8[31:0];
- _RAND_9 = {1{`RANDOM}};
- rdata_adrx = _RAND_9[31:0];
- _RAND_10 = {1{`RANDOM}};
- rdata_size = _RAND_10[5:0];
- _RAND_11 = {1{`RANDOM}};
- rdata_widx = _RAND_11[5:0];
- _RAND_12 = {1{`RANDOM}};
- rvalid = _RAND_12[0:0];
- _RAND_13 = {1{`RANDOM}};
- wready = _RAND_13[0:0];
- _RAND_14 = {1{`RANDOM}};
- raddr = _RAND_14[0:0];
- _RAND_15 = {1{`RANDOM}};
- waddr = _RAND_15[0:0];
- _RAND_16 = {1{`RANDOM}};
- count = _RAND_16[1:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- rvalid = 1'h0;
- end
- if (reset) begin
- wready = 1'h0;
- end
- if (reset) begin
- raddr = 1'h0;
- end
- if (reset) begin
- waddr = 1'h0;
- end
- if (reset) begin
- count = 2'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Fifo_1(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input [255:0] io_in_bits_wdata,
- input [31:0] io_in_bits_wmask,
- input io_out_ready,
- output io_out_valid,
- output [255:0] io_out_bits_wdata,
- output [31:0] io_out_bits_wmask
-);
-`ifdef RANDOMIZE_MEM_INIT
- reg [255:0] _RAND_0;
- reg [31:0] _RAND_1;
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- reg [255:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
-`endif // RANDOMIZE_REG_INIT
- reg [255:0] mem_wdata [0:1]; // @[Fifo.scala 36:16]
- wire mem_wdata_rdata_MPORT_en; // @[Fifo.scala 36:16]
- wire mem_wdata_rdata_MPORT_addr; // @[Fifo.scala 36:16]
- wire [255:0] mem_wdata_rdata_MPORT_data; // @[Fifo.scala 36:16]
- wire [255:0] mem_wdata_MPORT_data; // @[Fifo.scala 36:16]
- wire mem_wdata_MPORT_addr; // @[Fifo.scala 36:16]
- wire mem_wdata_MPORT_mask; // @[Fifo.scala 36:16]
- wire mem_wdata_MPORT_en; // @[Fifo.scala 36:16]
- reg [31:0] mem_wmask [0:1]; // @[Fifo.scala 36:16]
- wire mem_wmask_rdata_MPORT_en; // @[Fifo.scala 36:16]
- wire mem_wmask_rdata_MPORT_addr; // @[Fifo.scala 36:16]
- wire [31:0] mem_wmask_rdata_MPORT_data; // @[Fifo.scala 36:16]
- wire [31:0] mem_wmask_MPORT_data; // @[Fifo.scala 36:16]
- wire mem_wmask_MPORT_addr; // @[Fifo.scala 36:16]
- wire mem_wmask_MPORT_mask; // @[Fifo.scala 36:16]
- wire mem_wmask_MPORT_en; // @[Fifo.scala 36:16]
- reg [255:0] rdata_wdata; // @[Fifo.scala 37:18]
- reg [31:0] rdata_wmask; // @[Fifo.scala 37:18]
- reg rvalid; // @[Fifo.scala 39:23]
- reg wready; // @[Fifo.scala 40:23]
- reg raddr; // @[Fifo.scala 41:22]
- reg waddr; // @[Fifo.scala 42:22]
- reg [1:0] count; // @[Fifo.scala 43:22]
- wire winc = io_in_valid & io_in_ready; // @[Fifo.scala 47:26]
- wire rinc = (~rvalid | io_out_ready) & (winc | count > 2'h1); // @[Fifo.scala 48:40]
- wire forward = rinc & winc & count <= 2'h1; // @[Fifo.scala 58:30]
- wire oen = io_out_valid & io_out_ready; // @[Fifo.scala 63:26]
- wire _T_1 = winc & ~oen; // @[Fifo.scala 65:13]
- wire [1:0] _count_T_1 = count + 2'h1; // @[Fifo.scala 66:20]
- wire _T_2 = ~winc; // @[Fifo.scala 67:16]
- wire [1:0] _count_T_3 = count - 2'h1; // @[Fifo.scala 68:20]
- wire _GEN_4 = io_out_ready & count == 2'h1 ? 1'h0 : rvalid; // @[Fifo.scala 73:47 74:12 39:23]
- wire _wready_T_5 = count == 2'h2 & ~_T_1; // @[Fifo.scala 78:33]
- wire _wready_T_6 = count < 2'h2 | _wready_T_5; // @[Fifo.scala 77:31]
- wire _wready_T_8 = oen & _T_2; // @[Fifo.scala 79:18]
- wire _T_6 = ~forward; // @[Fifo.scala 83:17]
- wire _T_10 = ~reset; // @[Fifo.scala 106:9]
- assign mem_wdata_rdata_MPORT_en = forward ? 1'h0 : rinc;
- assign mem_wdata_rdata_MPORT_addr = raddr;
- assign mem_wdata_rdata_MPORT_data = mem_wdata[mem_wdata_rdata_MPORT_addr]; // @[Fifo.scala 36:16]
- assign mem_wdata_MPORT_data = io_in_bits_wdata;
- assign mem_wdata_MPORT_addr = waddr;
- assign mem_wdata_MPORT_mask = 1'h1;
- assign mem_wdata_MPORT_en = winc & _T_6;
- assign mem_wmask_rdata_MPORT_en = forward ? 1'h0 : rinc;
- assign mem_wmask_rdata_MPORT_addr = raddr;
- assign mem_wmask_rdata_MPORT_data = mem_wmask[mem_wmask_rdata_MPORT_addr]; // @[Fifo.scala 36:16]
- assign mem_wmask_MPORT_data = io_in_bits_wmask;
- assign mem_wmask_MPORT_addr = waddr;
- assign mem_wmask_MPORT_mask = 1'h1;
- assign mem_wmask_MPORT_en = winc & _T_6;
- assign io_in_ready = wready; // @[Fifo.scala 101:17]
- assign io_out_valid = rvalid; // @[Fifo.scala 95:16]
- assign io_out_bits_wdata = rdata_wdata; // @[Fifo.scala 96:15]
- assign io_out_bits_wmask = rdata_wmask; // @[Fifo.scala 96:15]
- always @(posedge clock) begin
- if (mem_wdata_MPORT_en & mem_wdata_MPORT_mask) begin
- mem_wdata[mem_wdata_MPORT_addr] <= mem_wdata_MPORT_data; // @[Fifo.scala 36:16]
- end
- if (mem_wmask_MPORT_en & mem_wmask_MPORT_mask) begin
- mem_wmask[mem_wmask_MPORT_addr] <= mem_wmask_MPORT_data; // @[Fifo.scala 36:16]
- end
- if (forward) begin // @[Fifo.scala 87:18]
- rdata_wdata <= io_in_bits_wdata; // @[Fifo.scala 88:11]
- end else if (rinc) begin // @[Fifo.scala 89:22]
- rdata_wdata <= mem_wdata_rdata_MPORT_data; // @[Fifo.scala 90:11]
- end
- if (forward) begin // @[Fifo.scala 87:18]
- rdata_wmask <= io_in_bits_wmask; // @[Fifo.scala 88:11]
- end else if (rinc) begin // @[Fifo.scala 89:22]
- rdata_wmask <= mem_wmask_rdata_MPORT_data; // @[Fifo.scala 90:11]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_10 & ~(~(io_in_ready & count == 2'h3))) begin
- $fatal; // @[Fifo.scala 107:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_10 & ~(~(io_in_ready & count == 2'h3))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Fifo.scala:107 assert(!(!passReady.B && io.in.ready && count === n.U))\n"); // @[Fifo.scala 107:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo.scala 71:14]
- rvalid <= 1'h0; // @[Fifo.scala 72:12]
- end else begin
- rvalid <= winc | _GEN_4;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo.scala 78:51]
- wready <= 1'h0;
- end else begin
- wready <= _wready_T_6 | _wready_T_8;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo.scala 54:15]
- raddr <= 1'h0; // @[Fifo.scala 55:17]
- end else if (rinc) begin // @[Fifo.scala 41:22]
- if (raddr) begin
- raddr <= 1'h0;
- end else begin
- raddr <= raddr + 1'h1;
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo.scala 50:15]
- waddr <= 1'h0; // @[Fifo.scala 51:17]
- end else if (winc) begin // @[Fifo.scala 42:22]
- if (waddr) begin
- waddr <= 1'h0;
- end else begin
- waddr <= waddr + 1'h1;
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo.scala 65:22]
- count <= 2'h0; // @[Fifo.scala 66:11]
- end else if (winc & ~oen) begin // @[Fifo.scala 67:29]
- count <= _count_T_1; // @[Fifo.scala 68:11]
- end else if (~winc & oen) begin // @[Fifo.scala 43:22]
- count <= _count_T_3;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_MEM_INIT
- _RAND_0 = {8{`RANDOM}};
- for (initvar = 0; initvar < 2; initvar = initvar+1)
- mem_wdata[initvar] = _RAND_0[255:0];
- _RAND_1 = {1{`RANDOM}};
- for (initvar = 0; initvar < 2; initvar = initvar+1)
- mem_wmask[initvar] = _RAND_1[31:0];
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- _RAND_2 = {8{`RANDOM}};
- rdata_wdata = _RAND_2[255:0];
- _RAND_3 = {1{`RANDOM}};
- rdata_wmask = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- rvalid = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- wready = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- raddr = _RAND_6[0:0];
- _RAND_7 = {1{`RANDOM}};
- waddr = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- count = _RAND_8[1:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- rvalid = 1'h0;
- end
- if (reset) begin
- wready = 1'h0;
- end
- if (reset) begin
- raddr = 1'h0;
- end
- if (reset) begin
- waddr = 1'h0;
- end
- if (reset) begin
- count = 2'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Slice_4(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input [5:0] io_in_bits_widx,
- input [4:0] io_in_bits_addr,
- input [5:0] io_in_bits_size,
- input io_out_ready,
- output io_out_valid,
- output [5:0] io_out_bits_widx,
- output [4:0] io_out_bits_addr,
- output [5:0] io_out_bits_size
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
-`endif // RANDOMIZE_REG_INIT
- reg [1:0] ipos; // @[Slice.scala 38:21]
- reg [1:0] opos; // @[Slice.scala 39:21]
- reg [5:0] mem_0_widx; // @[Slice.scala 41:16]
- reg [4:0] mem_0_addr; // @[Slice.scala 41:16]
- reg [5:0] mem_0_size; // @[Slice.scala 41:16]
- reg [5:0] mem_1_widx; // @[Slice.scala 41:16]
- reg [4:0] mem_1_addr; // @[Slice.scala 41:16]
- reg [5:0] mem_1_size; // @[Slice.scala 41:16]
- wire empty = ipos == opos; // @[Slice.scala 43:20]
- wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 45:28]
- wire ovalid = io_out_valid & io_out_ready; // @[Slice.scala 46:29]
- wire [1:0] _ipos_T_1 = ipos + 2'h1; // @[Slice.scala 49:18]
- wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 53:18]
- wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 61:36]
- wire _io_in_ready_T = ~full; // @[Slice.scala 63:22]
- wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 72:18]
- wire _T_5 = ivalid & ovalid; // @[Slice.scala 73:18]
- wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 73:28]
- wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 72:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 78:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 77:39]
- assign io_in_ready = ~full | io_out_ready; // @[Slice.scala 63:28]
- assign io_out_valid = ~empty; // @[Slice.scala 102:21]
- assign io_out_bits_widx = mem_0_widx; // @[Slice.scala 103:18]
- assign io_out_bits_addr = mem_0_addr; // @[Slice.scala 103:18]
- assign io_out_bits_size = mem_0_size; // @[Slice.scala 103:18]
- always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_widx <= io_in_bits_widx; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_widx <= mem_1_widx; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_addr <= io_in_bits_addr; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_addr <= mem_1_addr; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_size <= io_in_bits_size; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_size <= mem_1_size; // @[Slice.scala 69:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_widx <= io_in_bits_widx; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_addr <= io_in_bits_addr; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_size <= io_in_bits_size; // @[Slice.scala 79:14]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 48:17]
- ipos <= 2'h0; // @[Slice.scala 49:10]
- end else if (ivalid) begin // @[Slice.scala 38:21]
- ipos <= _ipos_T_1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 52:17]
- opos <= 2'h0; // @[Slice.scala 53:10]
- end else if (ovalid) begin // @[Slice.scala 39:21]
- opos <= _opos_T_1;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- ipos = _RAND_0[1:0];
- _RAND_1 = {1{`RANDOM}};
- opos = _RAND_1[1:0];
- _RAND_2 = {1{`RANDOM}};
- mem_0_widx = _RAND_2[5:0];
- _RAND_3 = {1{`RANDOM}};
- mem_0_addr = _RAND_3[4:0];
- _RAND_4 = {1{`RANDOM}};
- mem_0_size = _RAND_4[5:0];
- _RAND_5 = {1{`RANDOM}};
- mem_1_widx = _RAND_5[5:0];
- _RAND_6 = {1{`RANDOM}};
- mem_1_addr = _RAND_6[4:0];
- _RAND_7 = {1{`RANDOM}};
- mem_1_size = _RAND_7[5:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- ipos = 2'h0;
- end
- if (reset) begin
- opos = 2'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Slice_5(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input [255:0] io_in_bits,
- input io_out_ready,
- output io_out_valid,
- output [255:0] io_out_bits
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [255:0] _RAND_2;
-`endif // RANDOMIZE_REG_INIT
- reg ipos; // @[Slice.scala 38:21]
- reg opos; // @[Slice.scala 39:21]
- reg [255:0] mem_0; // @[Slice.scala 41:16]
- wire empty = ipos == opos; // @[Slice.scala 43:20]
- wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 45:28]
- wire ovalid = io_out_valid & io_out_ready; // @[Slice.scala 46:29]
- assign io_in_ready = empty | io_out_ready; // @[Slice.scala 88:28]
- assign io_out_valid = ~empty; // @[Slice.scala 102:21]
- assign io_out_bits = mem_0; // @[Slice.scala 103:18]
- always @(posedge clock) begin
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0 <= io_in_bits; // @[Slice.scala 94:14]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 48:17]
- ipos <= 1'h0; // @[Slice.scala 49:10]
- end else if (ivalid) begin // @[Slice.scala 38:21]
- ipos <= ipos + 1'h1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 52:17]
- opos <= 1'h0; // @[Slice.scala 53:10]
- end else if (ovalid) begin // @[Slice.scala 39:21]
- opos <= opos + 1'h1;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- ipos = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- opos = _RAND_1[0:0];
- _RAND_2 = {8{`RANDOM}};
- mem_0 = _RAND_2[255:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- ipos = 1'h0;
- end
- if (reset) begin
- opos = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VLdSt(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_op,
- input [2:0] io_in_bits_0_bits_f2,
- input [2:0] io_in_bits_0_bits_sz,
- input io_in_bits_0_bits_m,
- input io_in_bits_0_bits_vd_valid,
- input [5:0] io_in_bits_0_bits_vd_addr,
- input io_in_bits_0_bits_vs_valid,
- input [5:0] io_in_bits_0_bits_vs_addr,
- input [3:0] io_in_bits_0_bits_vs_tag,
- input [31:0] io_in_bits_0_bits_sv_addr,
- input [31:0] io_in_bits_0_bits_sv_data,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_op,
- input [2:0] io_in_bits_1_bits_f2,
- input [2:0] io_in_bits_1_bits_sz,
- input io_in_bits_1_bits_m,
- input io_in_bits_1_bits_vd_valid,
- input [5:0] io_in_bits_1_bits_vd_addr,
- input io_in_bits_1_bits_vs_valid,
- input [5:0] io_in_bits_1_bits_vs_addr,
- input [3:0] io_in_bits_1_bits_vs_tag,
- input [31:0] io_in_bits_1_bits_sv_addr,
- input [31:0] io_in_bits_1_bits_sv_data,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_op,
- input [2:0] io_in_bits_2_bits_f2,
- input [2:0] io_in_bits_2_bits_sz,
- input io_in_bits_2_bits_m,
- input io_in_bits_2_bits_vd_valid,
- input [5:0] io_in_bits_2_bits_vd_addr,
- input io_in_bits_2_bits_vs_valid,
- input [5:0] io_in_bits_2_bits_vs_addr,
- input [3:0] io_in_bits_2_bits_vs_tag,
- input [31:0] io_in_bits_2_bits_sv_addr,
- input [31:0] io_in_bits_2_bits_sv_data,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_op,
- input [2:0] io_in_bits_3_bits_f2,
- input [2:0] io_in_bits_3_bits_sz,
- input io_in_bits_3_bits_m,
- input io_in_bits_3_bits_vd_valid,
- input [5:0] io_in_bits_3_bits_vd_addr,
- input io_in_bits_3_bits_vs_valid,
- input [5:0] io_in_bits_3_bits_vs_addr,
- input [3:0] io_in_bits_3_bits_vs_tag,
- input [31:0] io_in_bits_3_bits_sv_addr,
- input [31:0] io_in_bits_3_bits_sv_data,
- output [63:0] io_active,
- input [127:0] io_vrfsb,
- output io_read_valid,
- input io_read_ready,
- output [5:0] io_read_addr,
- input [255:0] io_read_data,
- output io_write_valid,
- output [5:0] io_write_addr,
- output [255:0] io_write_data,
- output io_dbus_valid,
- input io_dbus_ready,
- output io_dbus_write,
- output [31:0] io_dbus_addr,
- output [31:0] io_dbus_adrx,
- output [5:0] io_dbus_size,
- output [255:0] io_dbus_wdata,
- output [31:0] io_dbus_wmask,
- input [255:0] io_dbus_rdata,
- output io_last
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
-`endif // RANDOMIZE_REG_INIT
- wire q_clock; // @[VCmdq.scala 30:11]
- wire q_reset; // @[VCmdq.scala 30:11]
- wire q_io_in_ready; // @[VCmdq.scala 30:11]
- wire q_io_in_valid; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_0_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_0_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_0_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_0_bits_sz; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_0_bits_m; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_0_bits_vd_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_0_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_0_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_0_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q_io_in_bits_0_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_0_bits_sv_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_0_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_1_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_1_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_1_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_1_bits_sz; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_1_bits_m; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_1_bits_vd_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_1_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_1_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_1_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q_io_in_bits_1_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_1_bits_sv_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_1_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_2_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_2_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_2_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_2_bits_sz; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_2_bits_m; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_2_bits_vd_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_2_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_2_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_2_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q_io_in_bits_2_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_2_bits_sv_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_2_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_3_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_3_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_3_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_3_bits_sz; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_3_bits_m; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_3_bits_vd_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_3_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_3_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_3_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q_io_in_bits_3_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_3_bits_sv_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_3_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_out_ready; // @[VCmdq.scala 30:11]
- wire q_io_out_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_out_bits_op; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_out_bits_addr; // @[VCmdq.scala 30:11]
- wire [7:0] q_io_out_bits_remain; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_out_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire q_io_out_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_out_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q_io_out_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire [1:0] q_io_out_bits_quad; // @[VCmdq.scala 30:11]
- wire q_io_out_bits_last; // @[VCmdq.scala 30:11]
- wire [63:0] q_io_active; // @[VCmdq.scala 30:11]
- wire ctrl_clock; // @[Fifo.scala 22:11]
- wire ctrl_reset; // @[Fifo.scala 22:11]
- wire ctrl_io_in_ready; // @[Fifo.scala 22:11]
- wire ctrl_io_in_valid; // @[Fifo.scala 22:11]
- wire ctrl_io_in_bits_last; // @[Fifo.scala 22:11]
- wire ctrl_io_in_bits_write; // @[Fifo.scala 22:11]
- wire [31:0] ctrl_io_in_bits_addr; // @[Fifo.scala 22:11]
- wire [31:0] ctrl_io_in_bits_adrx; // @[Fifo.scala 22:11]
- wire [5:0] ctrl_io_in_bits_size; // @[Fifo.scala 22:11]
- wire [5:0] ctrl_io_in_bits_widx; // @[Fifo.scala 22:11]
- wire ctrl_io_out_ready; // @[Fifo.scala 22:11]
- wire ctrl_io_out_valid; // @[Fifo.scala 22:11]
- wire ctrl_io_out_bits_last; // @[Fifo.scala 22:11]
- wire ctrl_io_out_bits_write; // @[Fifo.scala 22:11]
- wire [31:0] ctrl_io_out_bits_addr; // @[Fifo.scala 22:11]
- wire [31:0] ctrl_io_out_bits_adrx; // @[Fifo.scala 22:11]
- wire [5:0] ctrl_io_out_bits_size; // @[Fifo.scala 22:11]
- wire [5:0] ctrl_io_out_bits_widx; // @[Fifo.scala 22:11]
- wire data_clock; // @[Fifo.scala 22:11]
- wire data_reset; // @[Fifo.scala 22:11]
- wire data_io_in_ready; // @[Fifo.scala 22:11]
- wire data_io_in_valid; // @[Fifo.scala 22:11]
- wire [255:0] data_io_in_bits_wdata; // @[Fifo.scala 22:11]
- wire [31:0] data_io_in_bits_wmask; // @[Fifo.scala 22:11]
- wire data_io_out_ready; // @[Fifo.scala 22:11]
- wire data_io_out_valid; // @[Fifo.scala 22:11]
- wire [255:0] data_io_out_bits_wdata; // @[Fifo.scala 22:11]
- wire [31:0] data_io_out_bits_wmask; // @[Fifo.scala 22:11]
- wire wrega_clock; // @[Slice.scala 23:11]
- wire wrega_reset; // @[Slice.scala 23:11]
- wire wrega_io_in_ready; // @[Slice.scala 23:11]
- wire wrega_io_in_valid; // @[Slice.scala 23:11]
- wire [5:0] wrega_io_in_bits_widx; // @[Slice.scala 23:11]
- wire [4:0] wrega_io_in_bits_addr; // @[Slice.scala 23:11]
- wire [5:0] wrega_io_in_bits_size; // @[Slice.scala 23:11]
- wire wrega_io_out_ready; // @[Slice.scala 23:11]
- wire wrega_io_out_valid; // @[Slice.scala 23:11]
- wire [5:0] wrega_io_out_bits_widx; // @[Slice.scala 23:11]
- wire [4:0] wrega_io_out_bits_addr; // @[Slice.scala 23:11]
- wire [5:0] wrega_io_out_bits_size; // @[Slice.scala 23:11]
- wire wregd_clock; // @[Slice.scala 23:11]
- wire wregd_reset; // @[Slice.scala 23:11]
- wire wregd_io_in_ready; // @[Slice.scala 23:11]
- wire wregd_io_in_valid; // @[Slice.scala 23:11]
- wire [255:0] wregd_io_in_bits; // @[Slice.scala 23:11]
- wire wregd_io_out_ready; // @[Slice.scala 23:11]
- wire wregd_io_out_valid; // @[Slice.scala 23:11]
- wire [255:0] wregd_io_out_bits; // @[Slice.scala 23:11]
- wire [3:0] _q_io_out_ready_tag_T_1 = q_io_out_bits_vs_tag >> q_io_out_bits_vs_addr[1:0]; // @[VCommon.scala 135:20]
- wire q_io_out_ready_tag = _q_io_out_ready_tag_T_1[0]; // @[VCommon.scala 135:20]
- wire [6:0] q_io_out_ready_idx = {q_io_out_ready_tag,q_io_out_bits_vs_addr}; // @[Cat.scala 31:58]
- wire [127:0] _q_io_out_ready_T_1 = io_vrfsb >> q_io_out_ready_idx; // @[VCommon.scala 138:21]
- wire _q_io_out_ready_T_4 = ~q_io_out_bits_vs_valid | ~_q_io_out_ready_T_1[0]; // @[VCommon.scala 138:15]
- wire ctrlready = ctrl_io_in_ready & (io_read_ready | ~ctrl_io_in_bits_write); // @[VLdSt.scala 225:33]
- reg rdataEn; // @[VLdSt.scala 220:24]
- reg [7:0] rdataSize; // @[VLdSt.scala 221:22]
- reg [4:0] rdataAddr; // @[VLdSt.scala 222:22]
- reg [4:0] rdataAshf; // @[VLdSt.scala 223:22]
- wire qoutEn = q_io_out_valid & q_io_out_ready; // @[VLdSt.scala 227:31]
- wire rdataEnNxt = qoutEn & ctrl_io_in_bits_write; // @[VLdSt.scala 228:27]
- wire _qmaxvlb_T = q_io_out_bits_op == 7'h4; // @[VLdSt.scala 230:38]
- wire [7:0] qmaxvlb = q_io_out_bits_op == 7'h4 ? 8'h8 : 8'h20; // @[VLdSt.scala 230:20]
- wire [7:0] qsize = q_io_out_bits_remain > qmaxvlb ? qmaxvlb : q_io_out_bits_remain; // @[VLdSt.scala 231:18]
- wire [1:0] quad = q_io_out_bits_quad; // @[VLdSt.scala 235:34]
- wire [9:0] _rdataAshf_T_1 = quad * 8'h8; // @[VLdSt.scala 238:45]
- wire [31:0] _GEN_3 = {{22'd0}, _rdataAshf_T_1}; // @[VLdSt.scala 238:37]
- wire [31:0] _rdataAshf_T_3 = q_io_out_bits_addr - _GEN_3; // @[VLdSt.scala 238:37]
- wire [31:0] _GEN_1 = rdataEnNxt ? q_io_out_bits_addr : {{27'd0}, rdataAddr}; // @[VLdSt.scala 234:21 237:15 222:22]
- wire [31:0] _GEN_2 = rdataEnNxt ? _rdataAshf_T_3 : {{27'd0}, rdataAshf}; // @[VLdSt.scala 234:21 238:15 223:22]
- wire rdataWmask_0 = rdataSize > 8'h0; // @[VLdSt.scala 242:32]
- wire rdataWmask_1 = rdataSize > 8'h1; // @[VLdSt.scala 242:32]
- wire rdataWmask_2 = rdataSize > 8'h2; // @[VLdSt.scala 242:32]
- wire rdataWmask_3 = rdataSize > 8'h3; // @[VLdSt.scala 242:32]
- wire rdataWmask_4 = rdataSize > 8'h4; // @[VLdSt.scala 242:32]
- wire rdataWmask_5 = rdataSize > 8'h5; // @[VLdSt.scala 242:32]
- wire rdataWmask_6 = rdataSize > 8'h6; // @[VLdSt.scala 242:32]
- wire rdataWmask_7 = rdataSize > 8'h7; // @[VLdSt.scala 242:32]
- wire rdataWmask_8 = rdataSize > 8'h8; // @[VLdSt.scala 242:32]
- wire rdataWmask_9 = rdataSize > 8'h9; // @[VLdSt.scala 242:32]
- wire rdataWmask_10 = rdataSize > 8'ha; // @[VLdSt.scala 242:32]
- wire rdataWmask_11 = rdataSize > 8'hb; // @[VLdSt.scala 242:32]
- wire rdataWmask_12 = rdataSize > 8'hc; // @[VLdSt.scala 242:32]
- wire rdataWmask_13 = rdataSize > 8'hd; // @[VLdSt.scala 242:32]
- wire rdataWmask_14 = rdataSize > 8'he; // @[VLdSt.scala 242:32]
- wire rdataWmask_15 = rdataSize > 8'hf; // @[VLdSt.scala 242:32]
- wire rdataWmask_16 = rdataSize > 8'h10; // @[VLdSt.scala 242:32]
- wire rdataWmask_17 = rdataSize > 8'h11; // @[VLdSt.scala 242:32]
- wire rdataWmask_18 = rdataSize > 8'h12; // @[VLdSt.scala 242:32]
- wire rdataWmask_19 = rdataSize > 8'h13; // @[VLdSt.scala 242:32]
- wire rdataWmask_20 = rdataSize > 8'h14; // @[VLdSt.scala 242:32]
- wire rdataWmask_21 = rdataSize > 8'h15; // @[VLdSt.scala 242:32]
- wire rdataWmask_22 = rdataSize > 8'h16; // @[VLdSt.scala 242:32]
- wire rdataWmask_23 = rdataSize > 8'h17; // @[VLdSt.scala 242:32]
- wire rdataWmask_24 = rdataSize > 8'h18; // @[VLdSt.scala 242:32]
- wire rdataWmask_25 = rdataSize > 8'h19; // @[VLdSt.scala 242:32]
- wire rdataWmask_26 = rdataSize > 8'h1a; // @[VLdSt.scala 242:32]
- wire rdataWmask_27 = rdataSize > 8'h1b; // @[VLdSt.scala 242:32]
- wire rdataWmask_28 = rdataSize > 8'h1c; // @[VLdSt.scala 242:32]
- wire rdataWmask_29 = rdataSize > 8'h1d; // @[VLdSt.scala 242:32]
- wire rdataWmask_30 = rdataSize > 8'h1e; // @[VLdSt.scala 242:32]
- wire rdataWmask_31 = rdataSize > 8'h1f; // @[VLdSt.scala 242:32]
- wire _T_4 = ~reset; // @[VLdSt.scala 254:9]
- wire [7:0] data_io_in_bits_wdata_datain_0 = io_read_data[7:0]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_1 = io_read_data[15:8]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_2 = io_read_data[23:16]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_3 = io_read_data[31:24]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_4 = io_read_data[39:32]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_5 = io_read_data[47:40]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_6 = io_read_data[55:48]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_7 = io_read_data[63:56]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_8 = io_read_data[71:64]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_9 = io_read_data[79:72]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_10 = io_read_data[87:80]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_11 = io_read_data[95:88]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_12 = io_read_data[103:96]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_13 = io_read_data[111:104]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_14 = io_read_data[119:112]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_15 = io_read_data[127:120]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_16 = io_read_data[135:128]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_17 = io_read_data[143:136]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_18 = io_read_data[151:144]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_19 = io_read_data[159:152]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_20 = io_read_data[167:160]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_21 = io_read_data[175:168]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_22 = io_read_data[183:176]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_23 = io_read_data[191:184]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_24 = io_read_data[199:192]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_25 = io_read_data[207:200]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_26 = io_read_data[215:208]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_27 = io_read_data[223:216]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_28 = io_read_data[231:224]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_29 = io_read_data[239:232]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_30 = io_read_data[247:240]; // @[VLdSt.scala 66:24]
- wire [7:0] data_io_in_bits_wdata_datain_31 = io_read_data[255:248]; // @[VLdSt.scala 66:24]
- wire [4:0] data_io_in_bits_wdata_idx = 5'h0 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__0 = 5'h0 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__1 = 5'h1 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__2 = 5'h2 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__3 = 5'h3 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__4 = 5'h4 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__5 = 5'h5 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__6 = 5'h6 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__7 = 5'h7 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__8 = 5'h8 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__9 = 5'h9 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__10 = 5'ha == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__11 = 5'hb == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__12 = 5'hc == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__13 = 5'hd == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__14 = 5'he == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__15 = 5'hf == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__16 = 5'h10 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__17 = 5'h11 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__18 = 5'h12 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__19 = 5'h13 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__20 = 5'h14 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__21 = 5'h15 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__22 = 5'h16 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__23 = 5'h17 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__24 = 5'h18 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__25 = 5'h19 == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__26 = 5'h1a == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__27 = 5'h1b == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__28 = 5'h1c == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__29 = 5'h1d == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__30 = 5'h1e == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value__31 = 5'h1f == data_io_in_bits_wdata_idx ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_0 = data_io_in_bits_wdata_dataout_0_value__0 |
- data_io_in_bits_wdata_dataout_0_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_1 = data_io_in_bits_wdata_dataout_0_value__2 |
- data_io_in_bits_wdata_dataout_0_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_2 = data_io_in_bits_wdata_dataout_0_value__4 |
- data_io_in_bits_wdata_dataout_0_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_3 = data_io_in_bits_wdata_dataout_0_value__6 |
- data_io_in_bits_wdata_dataout_0_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_4 = data_io_in_bits_wdata_dataout_0_value__8 |
- data_io_in_bits_wdata_dataout_0_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_5 = data_io_in_bits_wdata_dataout_0_value__10 |
- data_io_in_bits_wdata_dataout_0_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_6 = data_io_in_bits_wdata_dataout_0_value__12 |
- data_io_in_bits_wdata_dataout_0_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_7 = data_io_in_bits_wdata_dataout_0_value__14 |
- data_io_in_bits_wdata_dataout_0_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_8 = data_io_in_bits_wdata_dataout_0_value__16 |
- data_io_in_bits_wdata_dataout_0_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_9 = data_io_in_bits_wdata_dataout_0_value__18 |
- data_io_in_bits_wdata_dataout_0_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_10 = data_io_in_bits_wdata_dataout_0_value__20 |
- data_io_in_bits_wdata_dataout_0_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_11 = data_io_in_bits_wdata_dataout_0_value__22 |
- data_io_in_bits_wdata_dataout_0_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_12 = data_io_in_bits_wdata_dataout_0_value__24 |
- data_io_in_bits_wdata_dataout_0_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_13 = data_io_in_bits_wdata_dataout_0_value__26 |
- data_io_in_bits_wdata_dataout_0_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_14 = data_io_in_bits_wdata_dataout_0_value__28 |
- data_io_in_bits_wdata_dataout_0_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_1_15 = data_io_in_bits_wdata_dataout_0_value__30 |
- data_io_in_bits_wdata_dataout_0_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_2_0 = data_io_in_bits_wdata_dataout_0_value_1_0 |
- data_io_in_bits_wdata_dataout_0_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_2_1 = data_io_in_bits_wdata_dataout_0_value_1_2 |
- data_io_in_bits_wdata_dataout_0_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_2_2 = data_io_in_bits_wdata_dataout_0_value_1_4 |
- data_io_in_bits_wdata_dataout_0_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_2_3 = data_io_in_bits_wdata_dataout_0_value_1_6 |
- data_io_in_bits_wdata_dataout_0_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_2_4 = data_io_in_bits_wdata_dataout_0_value_1_8 |
- data_io_in_bits_wdata_dataout_0_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_2_5 = data_io_in_bits_wdata_dataout_0_value_1_10 |
- data_io_in_bits_wdata_dataout_0_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_2_6 = data_io_in_bits_wdata_dataout_0_value_1_12 |
- data_io_in_bits_wdata_dataout_0_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_2_7 = data_io_in_bits_wdata_dataout_0_value_1_14 |
- data_io_in_bits_wdata_dataout_0_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_3_0 = data_io_in_bits_wdata_dataout_0_value_2_0 |
- data_io_in_bits_wdata_dataout_0_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_3_1 = data_io_in_bits_wdata_dataout_0_value_2_2 |
- data_io_in_bits_wdata_dataout_0_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_3_2 = data_io_in_bits_wdata_dataout_0_value_2_4 |
- data_io_in_bits_wdata_dataout_0_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_3_3 = data_io_in_bits_wdata_dataout_0_value_2_6 |
- data_io_in_bits_wdata_dataout_0_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_4_0 = data_io_in_bits_wdata_dataout_0_value_3_0 |
- data_io_in_bits_wdata_dataout_0_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_4_1 = data_io_in_bits_wdata_dataout_0_value_3_2 |
- data_io_in_bits_wdata_dataout_0_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_0_value_5_0 = data_io_in_bits_wdata_dataout_0_value_4_0 |
- data_io_in_bits_wdata_dataout_0_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_1 = 5'h1 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__0 = 5'h0 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__1 = 5'h1 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__2 = 5'h2 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__3 = 5'h3 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__4 = 5'h4 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__5 = 5'h5 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__6 = 5'h6 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__7 = 5'h7 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__8 = 5'h8 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__9 = 5'h9 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__10 = 5'ha == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__11 = 5'hb == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__12 = 5'hc == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__13 = 5'hd == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__14 = 5'he == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__15 = 5'hf == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__16 = 5'h10 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__17 = 5'h11 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__18 = 5'h12 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__19 = 5'h13 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__20 = 5'h14 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__21 = 5'h15 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__22 = 5'h16 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__23 = 5'h17 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__24 = 5'h18 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__25 = 5'h19 == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__26 = 5'h1a == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__27 = 5'h1b == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__28 = 5'h1c == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__29 = 5'h1d == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__30 = 5'h1e == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value__31 = 5'h1f == data_io_in_bits_wdata_idx_1 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_0 = data_io_in_bits_wdata_dataout_1_value__0 |
- data_io_in_bits_wdata_dataout_1_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_1 = data_io_in_bits_wdata_dataout_1_value__2 |
- data_io_in_bits_wdata_dataout_1_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_2 = data_io_in_bits_wdata_dataout_1_value__4 |
- data_io_in_bits_wdata_dataout_1_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_3 = data_io_in_bits_wdata_dataout_1_value__6 |
- data_io_in_bits_wdata_dataout_1_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_4 = data_io_in_bits_wdata_dataout_1_value__8 |
- data_io_in_bits_wdata_dataout_1_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_5 = data_io_in_bits_wdata_dataout_1_value__10 |
- data_io_in_bits_wdata_dataout_1_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_6 = data_io_in_bits_wdata_dataout_1_value__12 |
- data_io_in_bits_wdata_dataout_1_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_7 = data_io_in_bits_wdata_dataout_1_value__14 |
- data_io_in_bits_wdata_dataout_1_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_8 = data_io_in_bits_wdata_dataout_1_value__16 |
- data_io_in_bits_wdata_dataout_1_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_9 = data_io_in_bits_wdata_dataout_1_value__18 |
- data_io_in_bits_wdata_dataout_1_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_10 = data_io_in_bits_wdata_dataout_1_value__20 |
- data_io_in_bits_wdata_dataout_1_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_11 = data_io_in_bits_wdata_dataout_1_value__22 |
- data_io_in_bits_wdata_dataout_1_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_12 = data_io_in_bits_wdata_dataout_1_value__24 |
- data_io_in_bits_wdata_dataout_1_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_13 = data_io_in_bits_wdata_dataout_1_value__26 |
- data_io_in_bits_wdata_dataout_1_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_14 = data_io_in_bits_wdata_dataout_1_value__28 |
- data_io_in_bits_wdata_dataout_1_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_1_15 = data_io_in_bits_wdata_dataout_1_value__30 |
- data_io_in_bits_wdata_dataout_1_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_2_0 = data_io_in_bits_wdata_dataout_1_value_1_0 |
- data_io_in_bits_wdata_dataout_1_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_2_1 = data_io_in_bits_wdata_dataout_1_value_1_2 |
- data_io_in_bits_wdata_dataout_1_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_2_2 = data_io_in_bits_wdata_dataout_1_value_1_4 |
- data_io_in_bits_wdata_dataout_1_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_2_3 = data_io_in_bits_wdata_dataout_1_value_1_6 |
- data_io_in_bits_wdata_dataout_1_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_2_4 = data_io_in_bits_wdata_dataout_1_value_1_8 |
- data_io_in_bits_wdata_dataout_1_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_2_5 = data_io_in_bits_wdata_dataout_1_value_1_10 |
- data_io_in_bits_wdata_dataout_1_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_2_6 = data_io_in_bits_wdata_dataout_1_value_1_12 |
- data_io_in_bits_wdata_dataout_1_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_2_7 = data_io_in_bits_wdata_dataout_1_value_1_14 |
- data_io_in_bits_wdata_dataout_1_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_3_0 = data_io_in_bits_wdata_dataout_1_value_2_0 |
- data_io_in_bits_wdata_dataout_1_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_3_1 = data_io_in_bits_wdata_dataout_1_value_2_2 |
- data_io_in_bits_wdata_dataout_1_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_3_2 = data_io_in_bits_wdata_dataout_1_value_2_4 |
- data_io_in_bits_wdata_dataout_1_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_3_3 = data_io_in_bits_wdata_dataout_1_value_2_6 |
- data_io_in_bits_wdata_dataout_1_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_4_0 = data_io_in_bits_wdata_dataout_1_value_3_0 |
- data_io_in_bits_wdata_dataout_1_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_4_1 = data_io_in_bits_wdata_dataout_1_value_3_2 |
- data_io_in_bits_wdata_dataout_1_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_1_value_5_0 = data_io_in_bits_wdata_dataout_1_value_4_0 |
- data_io_in_bits_wdata_dataout_1_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_2 = 5'h2 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__0 = 5'h0 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__1 = 5'h1 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__2 = 5'h2 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__3 = 5'h3 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__4 = 5'h4 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__5 = 5'h5 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__6 = 5'h6 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__7 = 5'h7 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__8 = 5'h8 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__9 = 5'h9 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__10 = 5'ha == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__11 = 5'hb == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__12 = 5'hc == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__13 = 5'hd == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__14 = 5'he == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__15 = 5'hf == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__16 = 5'h10 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__17 = 5'h11 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__18 = 5'h12 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__19 = 5'h13 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__20 = 5'h14 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__21 = 5'h15 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__22 = 5'h16 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__23 = 5'h17 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__24 = 5'h18 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__25 = 5'h19 == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__26 = 5'h1a == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__27 = 5'h1b == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__28 = 5'h1c == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__29 = 5'h1d == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__30 = 5'h1e == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value__31 = 5'h1f == data_io_in_bits_wdata_idx_2 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_0 = data_io_in_bits_wdata_dataout_2_value__0 |
- data_io_in_bits_wdata_dataout_2_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_1 = data_io_in_bits_wdata_dataout_2_value__2 |
- data_io_in_bits_wdata_dataout_2_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_2 = data_io_in_bits_wdata_dataout_2_value__4 |
- data_io_in_bits_wdata_dataout_2_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_3 = data_io_in_bits_wdata_dataout_2_value__6 |
- data_io_in_bits_wdata_dataout_2_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_4 = data_io_in_bits_wdata_dataout_2_value__8 |
- data_io_in_bits_wdata_dataout_2_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_5 = data_io_in_bits_wdata_dataout_2_value__10 |
- data_io_in_bits_wdata_dataout_2_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_6 = data_io_in_bits_wdata_dataout_2_value__12 |
- data_io_in_bits_wdata_dataout_2_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_7 = data_io_in_bits_wdata_dataout_2_value__14 |
- data_io_in_bits_wdata_dataout_2_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_8 = data_io_in_bits_wdata_dataout_2_value__16 |
- data_io_in_bits_wdata_dataout_2_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_9 = data_io_in_bits_wdata_dataout_2_value__18 |
- data_io_in_bits_wdata_dataout_2_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_10 = data_io_in_bits_wdata_dataout_2_value__20 |
- data_io_in_bits_wdata_dataout_2_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_11 = data_io_in_bits_wdata_dataout_2_value__22 |
- data_io_in_bits_wdata_dataout_2_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_12 = data_io_in_bits_wdata_dataout_2_value__24 |
- data_io_in_bits_wdata_dataout_2_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_13 = data_io_in_bits_wdata_dataout_2_value__26 |
- data_io_in_bits_wdata_dataout_2_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_14 = data_io_in_bits_wdata_dataout_2_value__28 |
- data_io_in_bits_wdata_dataout_2_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_1_15 = data_io_in_bits_wdata_dataout_2_value__30 |
- data_io_in_bits_wdata_dataout_2_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_2_0 = data_io_in_bits_wdata_dataout_2_value_1_0 |
- data_io_in_bits_wdata_dataout_2_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_2_1 = data_io_in_bits_wdata_dataout_2_value_1_2 |
- data_io_in_bits_wdata_dataout_2_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_2_2 = data_io_in_bits_wdata_dataout_2_value_1_4 |
- data_io_in_bits_wdata_dataout_2_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_2_3 = data_io_in_bits_wdata_dataout_2_value_1_6 |
- data_io_in_bits_wdata_dataout_2_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_2_4 = data_io_in_bits_wdata_dataout_2_value_1_8 |
- data_io_in_bits_wdata_dataout_2_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_2_5 = data_io_in_bits_wdata_dataout_2_value_1_10 |
- data_io_in_bits_wdata_dataout_2_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_2_6 = data_io_in_bits_wdata_dataout_2_value_1_12 |
- data_io_in_bits_wdata_dataout_2_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_2_7 = data_io_in_bits_wdata_dataout_2_value_1_14 |
- data_io_in_bits_wdata_dataout_2_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_3_0 = data_io_in_bits_wdata_dataout_2_value_2_0 |
- data_io_in_bits_wdata_dataout_2_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_3_1 = data_io_in_bits_wdata_dataout_2_value_2_2 |
- data_io_in_bits_wdata_dataout_2_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_3_2 = data_io_in_bits_wdata_dataout_2_value_2_4 |
- data_io_in_bits_wdata_dataout_2_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_3_3 = data_io_in_bits_wdata_dataout_2_value_2_6 |
- data_io_in_bits_wdata_dataout_2_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_4_0 = data_io_in_bits_wdata_dataout_2_value_3_0 |
- data_io_in_bits_wdata_dataout_2_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_4_1 = data_io_in_bits_wdata_dataout_2_value_3_2 |
- data_io_in_bits_wdata_dataout_2_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_2_value_5_0 = data_io_in_bits_wdata_dataout_2_value_4_0 |
- data_io_in_bits_wdata_dataout_2_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_3 = 5'h3 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__0 = 5'h0 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__1 = 5'h1 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__2 = 5'h2 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__3 = 5'h3 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__4 = 5'h4 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__5 = 5'h5 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__6 = 5'h6 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__7 = 5'h7 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__8 = 5'h8 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__9 = 5'h9 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__10 = 5'ha == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__11 = 5'hb == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__12 = 5'hc == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__13 = 5'hd == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__14 = 5'he == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__15 = 5'hf == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__16 = 5'h10 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__17 = 5'h11 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__18 = 5'h12 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__19 = 5'h13 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__20 = 5'h14 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__21 = 5'h15 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__22 = 5'h16 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__23 = 5'h17 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__24 = 5'h18 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__25 = 5'h19 == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__26 = 5'h1a == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__27 = 5'h1b == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__28 = 5'h1c == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__29 = 5'h1d == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__30 = 5'h1e == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value__31 = 5'h1f == data_io_in_bits_wdata_idx_3 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_0 = data_io_in_bits_wdata_dataout_3_value__0 |
- data_io_in_bits_wdata_dataout_3_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_1 = data_io_in_bits_wdata_dataout_3_value__2 |
- data_io_in_bits_wdata_dataout_3_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_2 = data_io_in_bits_wdata_dataout_3_value__4 |
- data_io_in_bits_wdata_dataout_3_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_3 = data_io_in_bits_wdata_dataout_3_value__6 |
- data_io_in_bits_wdata_dataout_3_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_4 = data_io_in_bits_wdata_dataout_3_value__8 |
- data_io_in_bits_wdata_dataout_3_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_5 = data_io_in_bits_wdata_dataout_3_value__10 |
- data_io_in_bits_wdata_dataout_3_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_6 = data_io_in_bits_wdata_dataout_3_value__12 |
- data_io_in_bits_wdata_dataout_3_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_7 = data_io_in_bits_wdata_dataout_3_value__14 |
- data_io_in_bits_wdata_dataout_3_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_8 = data_io_in_bits_wdata_dataout_3_value__16 |
- data_io_in_bits_wdata_dataout_3_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_9 = data_io_in_bits_wdata_dataout_3_value__18 |
- data_io_in_bits_wdata_dataout_3_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_10 = data_io_in_bits_wdata_dataout_3_value__20 |
- data_io_in_bits_wdata_dataout_3_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_11 = data_io_in_bits_wdata_dataout_3_value__22 |
- data_io_in_bits_wdata_dataout_3_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_12 = data_io_in_bits_wdata_dataout_3_value__24 |
- data_io_in_bits_wdata_dataout_3_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_13 = data_io_in_bits_wdata_dataout_3_value__26 |
- data_io_in_bits_wdata_dataout_3_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_14 = data_io_in_bits_wdata_dataout_3_value__28 |
- data_io_in_bits_wdata_dataout_3_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_1_15 = data_io_in_bits_wdata_dataout_3_value__30 |
- data_io_in_bits_wdata_dataout_3_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_2_0 = data_io_in_bits_wdata_dataout_3_value_1_0 |
- data_io_in_bits_wdata_dataout_3_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_2_1 = data_io_in_bits_wdata_dataout_3_value_1_2 |
- data_io_in_bits_wdata_dataout_3_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_2_2 = data_io_in_bits_wdata_dataout_3_value_1_4 |
- data_io_in_bits_wdata_dataout_3_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_2_3 = data_io_in_bits_wdata_dataout_3_value_1_6 |
- data_io_in_bits_wdata_dataout_3_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_2_4 = data_io_in_bits_wdata_dataout_3_value_1_8 |
- data_io_in_bits_wdata_dataout_3_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_2_5 = data_io_in_bits_wdata_dataout_3_value_1_10 |
- data_io_in_bits_wdata_dataout_3_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_2_6 = data_io_in_bits_wdata_dataout_3_value_1_12 |
- data_io_in_bits_wdata_dataout_3_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_2_7 = data_io_in_bits_wdata_dataout_3_value_1_14 |
- data_io_in_bits_wdata_dataout_3_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_3_0 = data_io_in_bits_wdata_dataout_3_value_2_0 |
- data_io_in_bits_wdata_dataout_3_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_3_1 = data_io_in_bits_wdata_dataout_3_value_2_2 |
- data_io_in_bits_wdata_dataout_3_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_3_2 = data_io_in_bits_wdata_dataout_3_value_2_4 |
- data_io_in_bits_wdata_dataout_3_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_3_3 = data_io_in_bits_wdata_dataout_3_value_2_6 |
- data_io_in_bits_wdata_dataout_3_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_4_0 = data_io_in_bits_wdata_dataout_3_value_3_0 |
- data_io_in_bits_wdata_dataout_3_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_4_1 = data_io_in_bits_wdata_dataout_3_value_3_2 |
- data_io_in_bits_wdata_dataout_3_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_3_value_5_0 = data_io_in_bits_wdata_dataout_3_value_4_0 |
- data_io_in_bits_wdata_dataout_3_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_4 = 5'h4 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__0 = 5'h0 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__1 = 5'h1 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__2 = 5'h2 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__3 = 5'h3 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__4 = 5'h4 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__5 = 5'h5 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__6 = 5'h6 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__7 = 5'h7 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__8 = 5'h8 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__9 = 5'h9 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__10 = 5'ha == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__11 = 5'hb == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__12 = 5'hc == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__13 = 5'hd == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__14 = 5'he == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__15 = 5'hf == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__16 = 5'h10 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__17 = 5'h11 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__18 = 5'h12 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__19 = 5'h13 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__20 = 5'h14 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__21 = 5'h15 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__22 = 5'h16 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__23 = 5'h17 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__24 = 5'h18 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__25 = 5'h19 == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__26 = 5'h1a == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__27 = 5'h1b == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__28 = 5'h1c == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__29 = 5'h1d == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__30 = 5'h1e == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value__31 = 5'h1f == data_io_in_bits_wdata_idx_4 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_0 = data_io_in_bits_wdata_dataout_4_value__0 |
- data_io_in_bits_wdata_dataout_4_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_1 = data_io_in_bits_wdata_dataout_4_value__2 |
- data_io_in_bits_wdata_dataout_4_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_2 = data_io_in_bits_wdata_dataout_4_value__4 |
- data_io_in_bits_wdata_dataout_4_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_3 = data_io_in_bits_wdata_dataout_4_value__6 |
- data_io_in_bits_wdata_dataout_4_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_4 = data_io_in_bits_wdata_dataout_4_value__8 |
- data_io_in_bits_wdata_dataout_4_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_5 = data_io_in_bits_wdata_dataout_4_value__10 |
- data_io_in_bits_wdata_dataout_4_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_6 = data_io_in_bits_wdata_dataout_4_value__12 |
- data_io_in_bits_wdata_dataout_4_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_7 = data_io_in_bits_wdata_dataout_4_value__14 |
- data_io_in_bits_wdata_dataout_4_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_8 = data_io_in_bits_wdata_dataout_4_value__16 |
- data_io_in_bits_wdata_dataout_4_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_9 = data_io_in_bits_wdata_dataout_4_value__18 |
- data_io_in_bits_wdata_dataout_4_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_10 = data_io_in_bits_wdata_dataout_4_value__20 |
- data_io_in_bits_wdata_dataout_4_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_11 = data_io_in_bits_wdata_dataout_4_value__22 |
- data_io_in_bits_wdata_dataout_4_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_12 = data_io_in_bits_wdata_dataout_4_value__24 |
- data_io_in_bits_wdata_dataout_4_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_13 = data_io_in_bits_wdata_dataout_4_value__26 |
- data_io_in_bits_wdata_dataout_4_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_14 = data_io_in_bits_wdata_dataout_4_value__28 |
- data_io_in_bits_wdata_dataout_4_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_1_15 = data_io_in_bits_wdata_dataout_4_value__30 |
- data_io_in_bits_wdata_dataout_4_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_2_0 = data_io_in_bits_wdata_dataout_4_value_1_0 |
- data_io_in_bits_wdata_dataout_4_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_2_1 = data_io_in_bits_wdata_dataout_4_value_1_2 |
- data_io_in_bits_wdata_dataout_4_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_2_2 = data_io_in_bits_wdata_dataout_4_value_1_4 |
- data_io_in_bits_wdata_dataout_4_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_2_3 = data_io_in_bits_wdata_dataout_4_value_1_6 |
- data_io_in_bits_wdata_dataout_4_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_2_4 = data_io_in_bits_wdata_dataout_4_value_1_8 |
- data_io_in_bits_wdata_dataout_4_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_2_5 = data_io_in_bits_wdata_dataout_4_value_1_10 |
- data_io_in_bits_wdata_dataout_4_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_2_6 = data_io_in_bits_wdata_dataout_4_value_1_12 |
- data_io_in_bits_wdata_dataout_4_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_2_7 = data_io_in_bits_wdata_dataout_4_value_1_14 |
- data_io_in_bits_wdata_dataout_4_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_3_0 = data_io_in_bits_wdata_dataout_4_value_2_0 |
- data_io_in_bits_wdata_dataout_4_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_3_1 = data_io_in_bits_wdata_dataout_4_value_2_2 |
- data_io_in_bits_wdata_dataout_4_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_3_2 = data_io_in_bits_wdata_dataout_4_value_2_4 |
- data_io_in_bits_wdata_dataout_4_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_3_3 = data_io_in_bits_wdata_dataout_4_value_2_6 |
- data_io_in_bits_wdata_dataout_4_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_4_0 = data_io_in_bits_wdata_dataout_4_value_3_0 |
- data_io_in_bits_wdata_dataout_4_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_4_1 = data_io_in_bits_wdata_dataout_4_value_3_2 |
- data_io_in_bits_wdata_dataout_4_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_4_value_5_0 = data_io_in_bits_wdata_dataout_4_value_4_0 |
- data_io_in_bits_wdata_dataout_4_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_5 = 5'h5 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__0 = 5'h0 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__1 = 5'h1 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__2 = 5'h2 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__3 = 5'h3 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__4 = 5'h4 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__5 = 5'h5 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__6 = 5'h6 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__7 = 5'h7 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__8 = 5'h8 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__9 = 5'h9 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__10 = 5'ha == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__11 = 5'hb == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__12 = 5'hc == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__13 = 5'hd == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__14 = 5'he == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__15 = 5'hf == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__16 = 5'h10 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__17 = 5'h11 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__18 = 5'h12 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__19 = 5'h13 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__20 = 5'h14 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__21 = 5'h15 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__22 = 5'h16 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__23 = 5'h17 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__24 = 5'h18 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__25 = 5'h19 == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__26 = 5'h1a == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__27 = 5'h1b == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__28 = 5'h1c == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__29 = 5'h1d == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__30 = 5'h1e == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value__31 = 5'h1f == data_io_in_bits_wdata_idx_5 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_0 = data_io_in_bits_wdata_dataout_5_value__0 |
- data_io_in_bits_wdata_dataout_5_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_1 = data_io_in_bits_wdata_dataout_5_value__2 |
- data_io_in_bits_wdata_dataout_5_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_2 = data_io_in_bits_wdata_dataout_5_value__4 |
- data_io_in_bits_wdata_dataout_5_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_3 = data_io_in_bits_wdata_dataout_5_value__6 |
- data_io_in_bits_wdata_dataout_5_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_4 = data_io_in_bits_wdata_dataout_5_value__8 |
- data_io_in_bits_wdata_dataout_5_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_5 = data_io_in_bits_wdata_dataout_5_value__10 |
- data_io_in_bits_wdata_dataout_5_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_6 = data_io_in_bits_wdata_dataout_5_value__12 |
- data_io_in_bits_wdata_dataout_5_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_7 = data_io_in_bits_wdata_dataout_5_value__14 |
- data_io_in_bits_wdata_dataout_5_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_8 = data_io_in_bits_wdata_dataout_5_value__16 |
- data_io_in_bits_wdata_dataout_5_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_9 = data_io_in_bits_wdata_dataout_5_value__18 |
- data_io_in_bits_wdata_dataout_5_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_10 = data_io_in_bits_wdata_dataout_5_value__20 |
- data_io_in_bits_wdata_dataout_5_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_11 = data_io_in_bits_wdata_dataout_5_value__22 |
- data_io_in_bits_wdata_dataout_5_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_12 = data_io_in_bits_wdata_dataout_5_value__24 |
- data_io_in_bits_wdata_dataout_5_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_13 = data_io_in_bits_wdata_dataout_5_value__26 |
- data_io_in_bits_wdata_dataout_5_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_14 = data_io_in_bits_wdata_dataout_5_value__28 |
- data_io_in_bits_wdata_dataout_5_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_1_15 = data_io_in_bits_wdata_dataout_5_value__30 |
- data_io_in_bits_wdata_dataout_5_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_2_0 = data_io_in_bits_wdata_dataout_5_value_1_0 |
- data_io_in_bits_wdata_dataout_5_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_2_1 = data_io_in_bits_wdata_dataout_5_value_1_2 |
- data_io_in_bits_wdata_dataout_5_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_2_2 = data_io_in_bits_wdata_dataout_5_value_1_4 |
- data_io_in_bits_wdata_dataout_5_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_2_3 = data_io_in_bits_wdata_dataout_5_value_1_6 |
- data_io_in_bits_wdata_dataout_5_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_2_4 = data_io_in_bits_wdata_dataout_5_value_1_8 |
- data_io_in_bits_wdata_dataout_5_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_2_5 = data_io_in_bits_wdata_dataout_5_value_1_10 |
- data_io_in_bits_wdata_dataout_5_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_2_6 = data_io_in_bits_wdata_dataout_5_value_1_12 |
- data_io_in_bits_wdata_dataout_5_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_2_7 = data_io_in_bits_wdata_dataout_5_value_1_14 |
- data_io_in_bits_wdata_dataout_5_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_3_0 = data_io_in_bits_wdata_dataout_5_value_2_0 |
- data_io_in_bits_wdata_dataout_5_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_3_1 = data_io_in_bits_wdata_dataout_5_value_2_2 |
- data_io_in_bits_wdata_dataout_5_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_3_2 = data_io_in_bits_wdata_dataout_5_value_2_4 |
- data_io_in_bits_wdata_dataout_5_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_3_3 = data_io_in_bits_wdata_dataout_5_value_2_6 |
- data_io_in_bits_wdata_dataout_5_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_4_0 = data_io_in_bits_wdata_dataout_5_value_3_0 |
- data_io_in_bits_wdata_dataout_5_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_4_1 = data_io_in_bits_wdata_dataout_5_value_3_2 |
- data_io_in_bits_wdata_dataout_5_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_5_value_5_0 = data_io_in_bits_wdata_dataout_5_value_4_0 |
- data_io_in_bits_wdata_dataout_5_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_6 = 5'h6 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__0 = 5'h0 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__1 = 5'h1 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__2 = 5'h2 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__3 = 5'h3 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__4 = 5'h4 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__5 = 5'h5 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__6 = 5'h6 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__7 = 5'h7 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__8 = 5'h8 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__9 = 5'h9 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__10 = 5'ha == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__11 = 5'hb == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__12 = 5'hc == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__13 = 5'hd == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__14 = 5'he == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__15 = 5'hf == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__16 = 5'h10 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__17 = 5'h11 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__18 = 5'h12 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__19 = 5'h13 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__20 = 5'h14 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__21 = 5'h15 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__22 = 5'h16 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__23 = 5'h17 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__24 = 5'h18 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__25 = 5'h19 == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__26 = 5'h1a == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__27 = 5'h1b == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__28 = 5'h1c == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__29 = 5'h1d == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__30 = 5'h1e == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value__31 = 5'h1f == data_io_in_bits_wdata_idx_6 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_0 = data_io_in_bits_wdata_dataout_6_value__0 |
- data_io_in_bits_wdata_dataout_6_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_1 = data_io_in_bits_wdata_dataout_6_value__2 |
- data_io_in_bits_wdata_dataout_6_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_2 = data_io_in_bits_wdata_dataout_6_value__4 |
- data_io_in_bits_wdata_dataout_6_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_3 = data_io_in_bits_wdata_dataout_6_value__6 |
- data_io_in_bits_wdata_dataout_6_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_4 = data_io_in_bits_wdata_dataout_6_value__8 |
- data_io_in_bits_wdata_dataout_6_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_5 = data_io_in_bits_wdata_dataout_6_value__10 |
- data_io_in_bits_wdata_dataout_6_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_6 = data_io_in_bits_wdata_dataout_6_value__12 |
- data_io_in_bits_wdata_dataout_6_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_7 = data_io_in_bits_wdata_dataout_6_value__14 |
- data_io_in_bits_wdata_dataout_6_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_8 = data_io_in_bits_wdata_dataout_6_value__16 |
- data_io_in_bits_wdata_dataout_6_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_9 = data_io_in_bits_wdata_dataout_6_value__18 |
- data_io_in_bits_wdata_dataout_6_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_10 = data_io_in_bits_wdata_dataout_6_value__20 |
- data_io_in_bits_wdata_dataout_6_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_11 = data_io_in_bits_wdata_dataout_6_value__22 |
- data_io_in_bits_wdata_dataout_6_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_12 = data_io_in_bits_wdata_dataout_6_value__24 |
- data_io_in_bits_wdata_dataout_6_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_13 = data_io_in_bits_wdata_dataout_6_value__26 |
- data_io_in_bits_wdata_dataout_6_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_14 = data_io_in_bits_wdata_dataout_6_value__28 |
- data_io_in_bits_wdata_dataout_6_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_1_15 = data_io_in_bits_wdata_dataout_6_value__30 |
- data_io_in_bits_wdata_dataout_6_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_2_0 = data_io_in_bits_wdata_dataout_6_value_1_0 |
- data_io_in_bits_wdata_dataout_6_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_2_1 = data_io_in_bits_wdata_dataout_6_value_1_2 |
- data_io_in_bits_wdata_dataout_6_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_2_2 = data_io_in_bits_wdata_dataout_6_value_1_4 |
- data_io_in_bits_wdata_dataout_6_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_2_3 = data_io_in_bits_wdata_dataout_6_value_1_6 |
- data_io_in_bits_wdata_dataout_6_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_2_4 = data_io_in_bits_wdata_dataout_6_value_1_8 |
- data_io_in_bits_wdata_dataout_6_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_2_5 = data_io_in_bits_wdata_dataout_6_value_1_10 |
- data_io_in_bits_wdata_dataout_6_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_2_6 = data_io_in_bits_wdata_dataout_6_value_1_12 |
- data_io_in_bits_wdata_dataout_6_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_2_7 = data_io_in_bits_wdata_dataout_6_value_1_14 |
- data_io_in_bits_wdata_dataout_6_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_3_0 = data_io_in_bits_wdata_dataout_6_value_2_0 |
- data_io_in_bits_wdata_dataout_6_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_3_1 = data_io_in_bits_wdata_dataout_6_value_2_2 |
- data_io_in_bits_wdata_dataout_6_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_3_2 = data_io_in_bits_wdata_dataout_6_value_2_4 |
- data_io_in_bits_wdata_dataout_6_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_3_3 = data_io_in_bits_wdata_dataout_6_value_2_6 |
- data_io_in_bits_wdata_dataout_6_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_4_0 = data_io_in_bits_wdata_dataout_6_value_3_0 |
- data_io_in_bits_wdata_dataout_6_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_4_1 = data_io_in_bits_wdata_dataout_6_value_3_2 |
- data_io_in_bits_wdata_dataout_6_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_6_value_5_0 = data_io_in_bits_wdata_dataout_6_value_4_0 |
- data_io_in_bits_wdata_dataout_6_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_7 = 5'h7 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__0 = 5'h0 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__1 = 5'h1 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__2 = 5'h2 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__3 = 5'h3 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__4 = 5'h4 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__5 = 5'h5 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__6 = 5'h6 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__7 = 5'h7 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__8 = 5'h8 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__9 = 5'h9 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__10 = 5'ha == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__11 = 5'hb == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__12 = 5'hc == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__13 = 5'hd == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__14 = 5'he == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__15 = 5'hf == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__16 = 5'h10 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__17 = 5'h11 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__18 = 5'h12 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__19 = 5'h13 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__20 = 5'h14 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__21 = 5'h15 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__22 = 5'h16 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__23 = 5'h17 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__24 = 5'h18 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__25 = 5'h19 == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__26 = 5'h1a == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__27 = 5'h1b == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__28 = 5'h1c == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__29 = 5'h1d == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__30 = 5'h1e == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value__31 = 5'h1f == data_io_in_bits_wdata_idx_7 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_0 = data_io_in_bits_wdata_dataout_7_value__0 |
- data_io_in_bits_wdata_dataout_7_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_1 = data_io_in_bits_wdata_dataout_7_value__2 |
- data_io_in_bits_wdata_dataout_7_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_2 = data_io_in_bits_wdata_dataout_7_value__4 |
- data_io_in_bits_wdata_dataout_7_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_3 = data_io_in_bits_wdata_dataout_7_value__6 |
- data_io_in_bits_wdata_dataout_7_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_4 = data_io_in_bits_wdata_dataout_7_value__8 |
- data_io_in_bits_wdata_dataout_7_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_5 = data_io_in_bits_wdata_dataout_7_value__10 |
- data_io_in_bits_wdata_dataout_7_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_6 = data_io_in_bits_wdata_dataout_7_value__12 |
- data_io_in_bits_wdata_dataout_7_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_7 = data_io_in_bits_wdata_dataout_7_value__14 |
- data_io_in_bits_wdata_dataout_7_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_8 = data_io_in_bits_wdata_dataout_7_value__16 |
- data_io_in_bits_wdata_dataout_7_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_9 = data_io_in_bits_wdata_dataout_7_value__18 |
- data_io_in_bits_wdata_dataout_7_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_10 = data_io_in_bits_wdata_dataout_7_value__20 |
- data_io_in_bits_wdata_dataout_7_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_11 = data_io_in_bits_wdata_dataout_7_value__22 |
- data_io_in_bits_wdata_dataout_7_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_12 = data_io_in_bits_wdata_dataout_7_value__24 |
- data_io_in_bits_wdata_dataout_7_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_13 = data_io_in_bits_wdata_dataout_7_value__26 |
- data_io_in_bits_wdata_dataout_7_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_14 = data_io_in_bits_wdata_dataout_7_value__28 |
- data_io_in_bits_wdata_dataout_7_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_1_15 = data_io_in_bits_wdata_dataout_7_value__30 |
- data_io_in_bits_wdata_dataout_7_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_2_0 = data_io_in_bits_wdata_dataout_7_value_1_0 |
- data_io_in_bits_wdata_dataout_7_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_2_1 = data_io_in_bits_wdata_dataout_7_value_1_2 |
- data_io_in_bits_wdata_dataout_7_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_2_2 = data_io_in_bits_wdata_dataout_7_value_1_4 |
- data_io_in_bits_wdata_dataout_7_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_2_3 = data_io_in_bits_wdata_dataout_7_value_1_6 |
- data_io_in_bits_wdata_dataout_7_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_2_4 = data_io_in_bits_wdata_dataout_7_value_1_8 |
- data_io_in_bits_wdata_dataout_7_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_2_5 = data_io_in_bits_wdata_dataout_7_value_1_10 |
- data_io_in_bits_wdata_dataout_7_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_2_6 = data_io_in_bits_wdata_dataout_7_value_1_12 |
- data_io_in_bits_wdata_dataout_7_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_2_7 = data_io_in_bits_wdata_dataout_7_value_1_14 |
- data_io_in_bits_wdata_dataout_7_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_3_0 = data_io_in_bits_wdata_dataout_7_value_2_0 |
- data_io_in_bits_wdata_dataout_7_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_3_1 = data_io_in_bits_wdata_dataout_7_value_2_2 |
- data_io_in_bits_wdata_dataout_7_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_3_2 = data_io_in_bits_wdata_dataout_7_value_2_4 |
- data_io_in_bits_wdata_dataout_7_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_3_3 = data_io_in_bits_wdata_dataout_7_value_2_6 |
- data_io_in_bits_wdata_dataout_7_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_4_0 = data_io_in_bits_wdata_dataout_7_value_3_0 |
- data_io_in_bits_wdata_dataout_7_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_4_1 = data_io_in_bits_wdata_dataout_7_value_3_2 |
- data_io_in_bits_wdata_dataout_7_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_7_value_5_0 = data_io_in_bits_wdata_dataout_7_value_4_0 |
- data_io_in_bits_wdata_dataout_7_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_8 = 5'h8 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__0 = 5'h0 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__1 = 5'h1 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__2 = 5'h2 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__3 = 5'h3 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__4 = 5'h4 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__5 = 5'h5 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__6 = 5'h6 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__7 = 5'h7 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__8 = 5'h8 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__9 = 5'h9 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__10 = 5'ha == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__11 = 5'hb == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__12 = 5'hc == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__13 = 5'hd == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__14 = 5'he == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__15 = 5'hf == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__16 = 5'h10 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__17 = 5'h11 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__18 = 5'h12 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__19 = 5'h13 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__20 = 5'h14 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__21 = 5'h15 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__22 = 5'h16 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__23 = 5'h17 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__24 = 5'h18 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__25 = 5'h19 == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__26 = 5'h1a == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__27 = 5'h1b == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__28 = 5'h1c == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__29 = 5'h1d == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__30 = 5'h1e == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value__31 = 5'h1f == data_io_in_bits_wdata_idx_8 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_0 = data_io_in_bits_wdata_dataout_8_value__0 |
- data_io_in_bits_wdata_dataout_8_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_1 = data_io_in_bits_wdata_dataout_8_value__2 |
- data_io_in_bits_wdata_dataout_8_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_2 = data_io_in_bits_wdata_dataout_8_value__4 |
- data_io_in_bits_wdata_dataout_8_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_3 = data_io_in_bits_wdata_dataout_8_value__6 |
- data_io_in_bits_wdata_dataout_8_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_4 = data_io_in_bits_wdata_dataout_8_value__8 |
- data_io_in_bits_wdata_dataout_8_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_5 = data_io_in_bits_wdata_dataout_8_value__10 |
- data_io_in_bits_wdata_dataout_8_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_6 = data_io_in_bits_wdata_dataout_8_value__12 |
- data_io_in_bits_wdata_dataout_8_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_7 = data_io_in_bits_wdata_dataout_8_value__14 |
- data_io_in_bits_wdata_dataout_8_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_8 = data_io_in_bits_wdata_dataout_8_value__16 |
- data_io_in_bits_wdata_dataout_8_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_9 = data_io_in_bits_wdata_dataout_8_value__18 |
- data_io_in_bits_wdata_dataout_8_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_10 = data_io_in_bits_wdata_dataout_8_value__20 |
- data_io_in_bits_wdata_dataout_8_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_11 = data_io_in_bits_wdata_dataout_8_value__22 |
- data_io_in_bits_wdata_dataout_8_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_12 = data_io_in_bits_wdata_dataout_8_value__24 |
- data_io_in_bits_wdata_dataout_8_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_13 = data_io_in_bits_wdata_dataout_8_value__26 |
- data_io_in_bits_wdata_dataout_8_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_14 = data_io_in_bits_wdata_dataout_8_value__28 |
- data_io_in_bits_wdata_dataout_8_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_1_15 = data_io_in_bits_wdata_dataout_8_value__30 |
- data_io_in_bits_wdata_dataout_8_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_2_0 = data_io_in_bits_wdata_dataout_8_value_1_0 |
- data_io_in_bits_wdata_dataout_8_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_2_1 = data_io_in_bits_wdata_dataout_8_value_1_2 |
- data_io_in_bits_wdata_dataout_8_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_2_2 = data_io_in_bits_wdata_dataout_8_value_1_4 |
- data_io_in_bits_wdata_dataout_8_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_2_3 = data_io_in_bits_wdata_dataout_8_value_1_6 |
- data_io_in_bits_wdata_dataout_8_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_2_4 = data_io_in_bits_wdata_dataout_8_value_1_8 |
- data_io_in_bits_wdata_dataout_8_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_2_5 = data_io_in_bits_wdata_dataout_8_value_1_10 |
- data_io_in_bits_wdata_dataout_8_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_2_6 = data_io_in_bits_wdata_dataout_8_value_1_12 |
- data_io_in_bits_wdata_dataout_8_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_2_7 = data_io_in_bits_wdata_dataout_8_value_1_14 |
- data_io_in_bits_wdata_dataout_8_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_3_0 = data_io_in_bits_wdata_dataout_8_value_2_0 |
- data_io_in_bits_wdata_dataout_8_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_3_1 = data_io_in_bits_wdata_dataout_8_value_2_2 |
- data_io_in_bits_wdata_dataout_8_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_3_2 = data_io_in_bits_wdata_dataout_8_value_2_4 |
- data_io_in_bits_wdata_dataout_8_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_3_3 = data_io_in_bits_wdata_dataout_8_value_2_6 |
- data_io_in_bits_wdata_dataout_8_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_4_0 = data_io_in_bits_wdata_dataout_8_value_3_0 |
- data_io_in_bits_wdata_dataout_8_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_4_1 = data_io_in_bits_wdata_dataout_8_value_3_2 |
- data_io_in_bits_wdata_dataout_8_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_8_value_5_0 = data_io_in_bits_wdata_dataout_8_value_4_0 |
- data_io_in_bits_wdata_dataout_8_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_9 = 5'h9 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__0 = 5'h0 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__1 = 5'h1 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__2 = 5'h2 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__3 = 5'h3 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__4 = 5'h4 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__5 = 5'h5 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__6 = 5'h6 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__7 = 5'h7 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__8 = 5'h8 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__9 = 5'h9 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__10 = 5'ha == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__11 = 5'hb == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__12 = 5'hc == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__13 = 5'hd == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__14 = 5'he == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__15 = 5'hf == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__16 = 5'h10 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__17 = 5'h11 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__18 = 5'h12 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__19 = 5'h13 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__20 = 5'h14 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__21 = 5'h15 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__22 = 5'h16 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__23 = 5'h17 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__24 = 5'h18 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__25 = 5'h19 == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__26 = 5'h1a == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__27 = 5'h1b == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__28 = 5'h1c == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__29 = 5'h1d == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__30 = 5'h1e == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value__31 = 5'h1f == data_io_in_bits_wdata_idx_9 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_0 = data_io_in_bits_wdata_dataout_9_value__0 |
- data_io_in_bits_wdata_dataout_9_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_1 = data_io_in_bits_wdata_dataout_9_value__2 |
- data_io_in_bits_wdata_dataout_9_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_2 = data_io_in_bits_wdata_dataout_9_value__4 |
- data_io_in_bits_wdata_dataout_9_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_3 = data_io_in_bits_wdata_dataout_9_value__6 |
- data_io_in_bits_wdata_dataout_9_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_4 = data_io_in_bits_wdata_dataout_9_value__8 |
- data_io_in_bits_wdata_dataout_9_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_5 = data_io_in_bits_wdata_dataout_9_value__10 |
- data_io_in_bits_wdata_dataout_9_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_6 = data_io_in_bits_wdata_dataout_9_value__12 |
- data_io_in_bits_wdata_dataout_9_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_7 = data_io_in_bits_wdata_dataout_9_value__14 |
- data_io_in_bits_wdata_dataout_9_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_8 = data_io_in_bits_wdata_dataout_9_value__16 |
- data_io_in_bits_wdata_dataout_9_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_9 = data_io_in_bits_wdata_dataout_9_value__18 |
- data_io_in_bits_wdata_dataout_9_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_10 = data_io_in_bits_wdata_dataout_9_value__20 |
- data_io_in_bits_wdata_dataout_9_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_11 = data_io_in_bits_wdata_dataout_9_value__22 |
- data_io_in_bits_wdata_dataout_9_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_12 = data_io_in_bits_wdata_dataout_9_value__24 |
- data_io_in_bits_wdata_dataout_9_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_13 = data_io_in_bits_wdata_dataout_9_value__26 |
- data_io_in_bits_wdata_dataout_9_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_14 = data_io_in_bits_wdata_dataout_9_value__28 |
- data_io_in_bits_wdata_dataout_9_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_1_15 = data_io_in_bits_wdata_dataout_9_value__30 |
- data_io_in_bits_wdata_dataout_9_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_2_0 = data_io_in_bits_wdata_dataout_9_value_1_0 |
- data_io_in_bits_wdata_dataout_9_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_2_1 = data_io_in_bits_wdata_dataout_9_value_1_2 |
- data_io_in_bits_wdata_dataout_9_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_2_2 = data_io_in_bits_wdata_dataout_9_value_1_4 |
- data_io_in_bits_wdata_dataout_9_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_2_3 = data_io_in_bits_wdata_dataout_9_value_1_6 |
- data_io_in_bits_wdata_dataout_9_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_2_4 = data_io_in_bits_wdata_dataout_9_value_1_8 |
- data_io_in_bits_wdata_dataout_9_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_2_5 = data_io_in_bits_wdata_dataout_9_value_1_10 |
- data_io_in_bits_wdata_dataout_9_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_2_6 = data_io_in_bits_wdata_dataout_9_value_1_12 |
- data_io_in_bits_wdata_dataout_9_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_2_7 = data_io_in_bits_wdata_dataout_9_value_1_14 |
- data_io_in_bits_wdata_dataout_9_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_3_0 = data_io_in_bits_wdata_dataout_9_value_2_0 |
- data_io_in_bits_wdata_dataout_9_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_3_1 = data_io_in_bits_wdata_dataout_9_value_2_2 |
- data_io_in_bits_wdata_dataout_9_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_3_2 = data_io_in_bits_wdata_dataout_9_value_2_4 |
- data_io_in_bits_wdata_dataout_9_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_3_3 = data_io_in_bits_wdata_dataout_9_value_2_6 |
- data_io_in_bits_wdata_dataout_9_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_4_0 = data_io_in_bits_wdata_dataout_9_value_3_0 |
- data_io_in_bits_wdata_dataout_9_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_4_1 = data_io_in_bits_wdata_dataout_9_value_3_2 |
- data_io_in_bits_wdata_dataout_9_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_9_value_5_0 = data_io_in_bits_wdata_dataout_9_value_4_0 |
- data_io_in_bits_wdata_dataout_9_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_10 = 5'ha - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__0 = 5'h0 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__1 = 5'h1 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__2 = 5'h2 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__3 = 5'h3 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__4 = 5'h4 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__5 = 5'h5 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__6 = 5'h6 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__7 = 5'h7 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__8 = 5'h8 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__9 = 5'h9 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__10 = 5'ha == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__11 = 5'hb == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__12 = 5'hc == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__13 = 5'hd == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__14 = 5'he == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__15 = 5'hf == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__16 = 5'h10 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__17 = 5'h11 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__18 = 5'h12 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__19 = 5'h13 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__20 = 5'h14 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__21 = 5'h15 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__22 = 5'h16 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__23 = 5'h17 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__24 = 5'h18 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__25 = 5'h19 == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__26 = 5'h1a == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__27 = 5'h1b == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__28 = 5'h1c == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__29 = 5'h1d == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__30 = 5'h1e == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value__31 = 5'h1f == data_io_in_bits_wdata_idx_10 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_0 = data_io_in_bits_wdata_dataout_10_value__0 |
- data_io_in_bits_wdata_dataout_10_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_1 = data_io_in_bits_wdata_dataout_10_value__2 |
- data_io_in_bits_wdata_dataout_10_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_2 = data_io_in_bits_wdata_dataout_10_value__4 |
- data_io_in_bits_wdata_dataout_10_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_3 = data_io_in_bits_wdata_dataout_10_value__6 |
- data_io_in_bits_wdata_dataout_10_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_4 = data_io_in_bits_wdata_dataout_10_value__8 |
- data_io_in_bits_wdata_dataout_10_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_5 = data_io_in_bits_wdata_dataout_10_value__10 |
- data_io_in_bits_wdata_dataout_10_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_6 = data_io_in_bits_wdata_dataout_10_value__12 |
- data_io_in_bits_wdata_dataout_10_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_7 = data_io_in_bits_wdata_dataout_10_value__14 |
- data_io_in_bits_wdata_dataout_10_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_8 = data_io_in_bits_wdata_dataout_10_value__16 |
- data_io_in_bits_wdata_dataout_10_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_9 = data_io_in_bits_wdata_dataout_10_value__18 |
- data_io_in_bits_wdata_dataout_10_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_10 = data_io_in_bits_wdata_dataout_10_value__20 |
- data_io_in_bits_wdata_dataout_10_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_11 = data_io_in_bits_wdata_dataout_10_value__22 |
- data_io_in_bits_wdata_dataout_10_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_12 = data_io_in_bits_wdata_dataout_10_value__24 |
- data_io_in_bits_wdata_dataout_10_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_13 = data_io_in_bits_wdata_dataout_10_value__26 |
- data_io_in_bits_wdata_dataout_10_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_14 = data_io_in_bits_wdata_dataout_10_value__28 |
- data_io_in_bits_wdata_dataout_10_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_1_15 = data_io_in_bits_wdata_dataout_10_value__30 |
- data_io_in_bits_wdata_dataout_10_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_2_0 = data_io_in_bits_wdata_dataout_10_value_1_0 |
- data_io_in_bits_wdata_dataout_10_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_2_1 = data_io_in_bits_wdata_dataout_10_value_1_2 |
- data_io_in_bits_wdata_dataout_10_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_2_2 = data_io_in_bits_wdata_dataout_10_value_1_4 |
- data_io_in_bits_wdata_dataout_10_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_2_3 = data_io_in_bits_wdata_dataout_10_value_1_6 |
- data_io_in_bits_wdata_dataout_10_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_2_4 = data_io_in_bits_wdata_dataout_10_value_1_8 |
- data_io_in_bits_wdata_dataout_10_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_2_5 = data_io_in_bits_wdata_dataout_10_value_1_10 |
- data_io_in_bits_wdata_dataout_10_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_2_6 = data_io_in_bits_wdata_dataout_10_value_1_12 |
- data_io_in_bits_wdata_dataout_10_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_2_7 = data_io_in_bits_wdata_dataout_10_value_1_14 |
- data_io_in_bits_wdata_dataout_10_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_3_0 = data_io_in_bits_wdata_dataout_10_value_2_0 |
- data_io_in_bits_wdata_dataout_10_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_3_1 = data_io_in_bits_wdata_dataout_10_value_2_2 |
- data_io_in_bits_wdata_dataout_10_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_3_2 = data_io_in_bits_wdata_dataout_10_value_2_4 |
- data_io_in_bits_wdata_dataout_10_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_3_3 = data_io_in_bits_wdata_dataout_10_value_2_6 |
- data_io_in_bits_wdata_dataout_10_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_4_0 = data_io_in_bits_wdata_dataout_10_value_3_0 |
- data_io_in_bits_wdata_dataout_10_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_4_1 = data_io_in_bits_wdata_dataout_10_value_3_2 |
- data_io_in_bits_wdata_dataout_10_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_10_value_5_0 = data_io_in_bits_wdata_dataout_10_value_4_0 |
- data_io_in_bits_wdata_dataout_10_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_11 = 5'hb - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__0 = 5'h0 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__1 = 5'h1 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__2 = 5'h2 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__3 = 5'h3 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__4 = 5'h4 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__5 = 5'h5 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__6 = 5'h6 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__7 = 5'h7 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__8 = 5'h8 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__9 = 5'h9 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__10 = 5'ha == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__11 = 5'hb == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__12 = 5'hc == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__13 = 5'hd == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__14 = 5'he == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__15 = 5'hf == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__16 = 5'h10 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__17 = 5'h11 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__18 = 5'h12 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__19 = 5'h13 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__20 = 5'h14 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__21 = 5'h15 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__22 = 5'h16 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__23 = 5'h17 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__24 = 5'h18 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__25 = 5'h19 == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__26 = 5'h1a == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__27 = 5'h1b == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__28 = 5'h1c == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__29 = 5'h1d == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__30 = 5'h1e == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value__31 = 5'h1f == data_io_in_bits_wdata_idx_11 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_0 = data_io_in_bits_wdata_dataout_11_value__0 |
- data_io_in_bits_wdata_dataout_11_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_1 = data_io_in_bits_wdata_dataout_11_value__2 |
- data_io_in_bits_wdata_dataout_11_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_2 = data_io_in_bits_wdata_dataout_11_value__4 |
- data_io_in_bits_wdata_dataout_11_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_3 = data_io_in_bits_wdata_dataout_11_value__6 |
- data_io_in_bits_wdata_dataout_11_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_4 = data_io_in_bits_wdata_dataout_11_value__8 |
- data_io_in_bits_wdata_dataout_11_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_5 = data_io_in_bits_wdata_dataout_11_value__10 |
- data_io_in_bits_wdata_dataout_11_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_6 = data_io_in_bits_wdata_dataout_11_value__12 |
- data_io_in_bits_wdata_dataout_11_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_7 = data_io_in_bits_wdata_dataout_11_value__14 |
- data_io_in_bits_wdata_dataout_11_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_8 = data_io_in_bits_wdata_dataout_11_value__16 |
- data_io_in_bits_wdata_dataout_11_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_9 = data_io_in_bits_wdata_dataout_11_value__18 |
- data_io_in_bits_wdata_dataout_11_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_10 = data_io_in_bits_wdata_dataout_11_value__20 |
- data_io_in_bits_wdata_dataout_11_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_11 = data_io_in_bits_wdata_dataout_11_value__22 |
- data_io_in_bits_wdata_dataout_11_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_12 = data_io_in_bits_wdata_dataout_11_value__24 |
- data_io_in_bits_wdata_dataout_11_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_13 = data_io_in_bits_wdata_dataout_11_value__26 |
- data_io_in_bits_wdata_dataout_11_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_14 = data_io_in_bits_wdata_dataout_11_value__28 |
- data_io_in_bits_wdata_dataout_11_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_1_15 = data_io_in_bits_wdata_dataout_11_value__30 |
- data_io_in_bits_wdata_dataout_11_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_2_0 = data_io_in_bits_wdata_dataout_11_value_1_0 |
- data_io_in_bits_wdata_dataout_11_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_2_1 = data_io_in_bits_wdata_dataout_11_value_1_2 |
- data_io_in_bits_wdata_dataout_11_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_2_2 = data_io_in_bits_wdata_dataout_11_value_1_4 |
- data_io_in_bits_wdata_dataout_11_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_2_3 = data_io_in_bits_wdata_dataout_11_value_1_6 |
- data_io_in_bits_wdata_dataout_11_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_2_4 = data_io_in_bits_wdata_dataout_11_value_1_8 |
- data_io_in_bits_wdata_dataout_11_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_2_5 = data_io_in_bits_wdata_dataout_11_value_1_10 |
- data_io_in_bits_wdata_dataout_11_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_2_6 = data_io_in_bits_wdata_dataout_11_value_1_12 |
- data_io_in_bits_wdata_dataout_11_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_2_7 = data_io_in_bits_wdata_dataout_11_value_1_14 |
- data_io_in_bits_wdata_dataout_11_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_3_0 = data_io_in_bits_wdata_dataout_11_value_2_0 |
- data_io_in_bits_wdata_dataout_11_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_3_1 = data_io_in_bits_wdata_dataout_11_value_2_2 |
- data_io_in_bits_wdata_dataout_11_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_3_2 = data_io_in_bits_wdata_dataout_11_value_2_4 |
- data_io_in_bits_wdata_dataout_11_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_3_3 = data_io_in_bits_wdata_dataout_11_value_2_6 |
- data_io_in_bits_wdata_dataout_11_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_4_0 = data_io_in_bits_wdata_dataout_11_value_3_0 |
- data_io_in_bits_wdata_dataout_11_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_4_1 = data_io_in_bits_wdata_dataout_11_value_3_2 |
- data_io_in_bits_wdata_dataout_11_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_11_value_5_0 = data_io_in_bits_wdata_dataout_11_value_4_0 |
- data_io_in_bits_wdata_dataout_11_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_12 = 5'hc - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__0 = 5'h0 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__1 = 5'h1 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__2 = 5'h2 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__3 = 5'h3 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__4 = 5'h4 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__5 = 5'h5 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__6 = 5'h6 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__7 = 5'h7 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__8 = 5'h8 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__9 = 5'h9 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__10 = 5'ha == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__11 = 5'hb == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__12 = 5'hc == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__13 = 5'hd == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__14 = 5'he == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__15 = 5'hf == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__16 = 5'h10 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__17 = 5'h11 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__18 = 5'h12 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__19 = 5'h13 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__20 = 5'h14 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__21 = 5'h15 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__22 = 5'h16 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__23 = 5'h17 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__24 = 5'h18 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__25 = 5'h19 == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__26 = 5'h1a == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__27 = 5'h1b == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__28 = 5'h1c == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__29 = 5'h1d == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__30 = 5'h1e == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value__31 = 5'h1f == data_io_in_bits_wdata_idx_12 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_0 = data_io_in_bits_wdata_dataout_12_value__0 |
- data_io_in_bits_wdata_dataout_12_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_1 = data_io_in_bits_wdata_dataout_12_value__2 |
- data_io_in_bits_wdata_dataout_12_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_2 = data_io_in_bits_wdata_dataout_12_value__4 |
- data_io_in_bits_wdata_dataout_12_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_3 = data_io_in_bits_wdata_dataout_12_value__6 |
- data_io_in_bits_wdata_dataout_12_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_4 = data_io_in_bits_wdata_dataout_12_value__8 |
- data_io_in_bits_wdata_dataout_12_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_5 = data_io_in_bits_wdata_dataout_12_value__10 |
- data_io_in_bits_wdata_dataout_12_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_6 = data_io_in_bits_wdata_dataout_12_value__12 |
- data_io_in_bits_wdata_dataout_12_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_7 = data_io_in_bits_wdata_dataout_12_value__14 |
- data_io_in_bits_wdata_dataout_12_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_8 = data_io_in_bits_wdata_dataout_12_value__16 |
- data_io_in_bits_wdata_dataout_12_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_9 = data_io_in_bits_wdata_dataout_12_value__18 |
- data_io_in_bits_wdata_dataout_12_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_10 = data_io_in_bits_wdata_dataout_12_value__20 |
- data_io_in_bits_wdata_dataout_12_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_11 = data_io_in_bits_wdata_dataout_12_value__22 |
- data_io_in_bits_wdata_dataout_12_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_12 = data_io_in_bits_wdata_dataout_12_value__24 |
- data_io_in_bits_wdata_dataout_12_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_13 = data_io_in_bits_wdata_dataout_12_value__26 |
- data_io_in_bits_wdata_dataout_12_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_14 = data_io_in_bits_wdata_dataout_12_value__28 |
- data_io_in_bits_wdata_dataout_12_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_1_15 = data_io_in_bits_wdata_dataout_12_value__30 |
- data_io_in_bits_wdata_dataout_12_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_2_0 = data_io_in_bits_wdata_dataout_12_value_1_0 |
- data_io_in_bits_wdata_dataout_12_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_2_1 = data_io_in_bits_wdata_dataout_12_value_1_2 |
- data_io_in_bits_wdata_dataout_12_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_2_2 = data_io_in_bits_wdata_dataout_12_value_1_4 |
- data_io_in_bits_wdata_dataout_12_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_2_3 = data_io_in_bits_wdata_dataout_12_value_1_6 |
- data_io_in_bits_wdata_dataout_12_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_2_4 = data_io_in_bits_wdata_dataout_12_value_1_8 |
- data_io_in_bits_wdata_dataout_12_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_2_5 = data_io_in_bits_wdata_dataout_12_value_1_10 |
- data_io_in_bits_wdata_dataout_12_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_2_6 = data_io_in_bits_wdata_dataout_12_value_1_12 |
- data_io_in_bits_wdata_dataout_12_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_2_7 = data_io_in_bits_wdata_dataout_12_value_1_14 |
- data_io_in_bits_wdata_dataout_12_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_3_0 = data_io_in_bits_wdata_dataout_12_value_2_0 |
- data_io_in_bits_wdata_dataout_12_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_3_1 = data_io_in_bits_wdata_dataout_12_value_2_2 |
- data_io_in_bits_wdata_dataout_12_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_3_2 = data_io_in_bits_wdata_dataout_12_value_2_4 |
- data_io_in_bits_wdata_dataout_12_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_3_3 = data_io_in_bits_wdata_dataout_12_value_2_6 |
- data_io_in_bits_wdata_dataout_12_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_4_0 = data_io_in_bits_wdata_dataout_12_value_3_0 |
- data_io_in_bits_wdata_dataout_12_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_4_1 = data_io_in_bits_wdata_dataout_12_value_3_2 |
- data_io_in_bits_wdata_dataout_12_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_12_value_5_0 = data_io_in_bits_wdata_dataout_12_value_4_0 |
- data_io_in_bits_wdata_dataout_12_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_13 = 5'hd - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__0 = 5'h0 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__1 = 5'h1 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__2 = 5'h2 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__3 = 5'h3 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__4 = 5'h4 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__5 = 5'h5 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__6 = 5'h6 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__7 = 5'h7 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__8 = 5'h8 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__9 = 5'h9 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__10 = 5'ha == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__11 = 5'hb == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__12 = 5'hc == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__13 = 5'hd == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__14 = 5'he == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__15 = 5'hf == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__16 = 5'h10 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__17 = 5'h11 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__18 = 5'h12 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__19 = 5'h13 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__20 = 5'h14 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__21 = 5'h15 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__22 = 5'h16 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__23 = 5'h17 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__24 = 5'h18 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__25 = 5'h19 == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__26 = 5'h1a == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__27 = 5'h1b == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__28 = 5'h1c == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__29 = 5'h1d == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__30 = 5'h1e == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value__31 = 5'h1f == data_io_in_bits_wdata_idx_13 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_0 = data_io_in_bits_wdata_dataout_13_value__0 |
- data_io_in_bits_wdata_dataout_13_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_1 = data_io_in_bits_wdata_dataout_13_value__2 |
- data_io_in_bits_wdata_dataout_13_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_2 = data_io_in_bits_wdata_dataout_13_value__4 |
- data_io_in_bits_wdata_dataout_13_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_3 = data_io_in_bits_wdata_dataout_13_value__6 |
- data_io_in_bits_wdata_dataout_13_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_4 = data_io_in_bits_wdata_dataout_13_value__8 |
- data_io_in_bits_wdata_dataout_13_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_5 = data_io_in_bits_wdata_dataout_13_value__10 |
- data_io_in_bits_wdata_dataout_13_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_6 = data_io_in_bits_wdata_dataout_13_value__12 |
- data_io_in_bits_wdata_dataout_13_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_7 = data_io_in_bits_wdata_dataout_13_value__14 |
- data_io_in_bits_wdata_dataout_13_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_8 = data_io_in_bits_wdata_dataout_13_value__16 |
- data_io_in_bits_wdata_dataout_13_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_9 = data_io_in_bits_wdata_dataout_13_value__18 |
- data_io_in_bits_wdata_dataout_13_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_10 = data_io_in_bits_wdata_dataout_13_value__20 |
- data_io_in_bits_wdata_dataout_13_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_11 = data_io_in_bits_wdata_dataout_13_value__22 |
- data_io_in_bits_wdata_dataout_13_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_12 = data_io_in_bits_wdata_dataout_13_value__24 |
- data_io_in_bits_wdata_dataout_13_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_13 = data_io_in_bits_wdata_dataout_13_value__26 |
- data_io_in_bits_wdata_dataout_13_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_14 = data_io_in_bits_wdata_dataout_13_value__28 |
- data_io_in_bits_wdata_dataout_13_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_1_15 = data_io_in_bits_wdata_dataout_13_value__30 |
- data_io_in_bits_wdata_dataout_13_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_2_0 = data_io_in_bits_wdata_dataout_13_value_1_0 |
- data_io_in_bits_wdata_dataout_13_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_2_1 = data_io_in_bits_wdata_dataout_13_value_1_2 |
- data_io_in_bits_wdata_dataout_13_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_2_2 = data_io_in_bits_wdata_dataout_13_value_1_4 |
- data_io_in_bits_wdata_dataout_13_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_2_3 = data_io_in_bits_wdata_dataout_13_value_1_6 |
- data_io_in_bits_wdata_dataout_13_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_2_4 = data_io_in_bits_wdata_dataout_13_value_1_8 |
- data_io_in_bits_wdata_dataout_13_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_2_5 = data_io_in_bits_wdata_dataout_13_value_1_10 |
- data_io_in_bits_wdata_dataout_13_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_2_6 = data_io_in_bits_wdata_dataout_13_value_1_12 |
- data_io_in_bits_wdata_dataout_13_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_2_7 = data_io_in_bits_wdata_dataout_13_value_1_14 |
- data_io_in_bits_wdata_dataout_13_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_3_0 = data_io_in_bits_wdata_dataout_13_value_2_0 |
- data_io_in_bits_wdata_dataout_13_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_3_1 = data_io_in_bits_wdata_dataout_13_value_2_2 |
- data_io_in_bits_wdata_dataout_13_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_3_2 = data_io_in_bits_wdata_dataout_13_value_2_4 |
- data_io_in_bits_wdata_dataout_13_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_3_3 = data_io_in_bits_wdata_dataout_13_value_2_6 |
- data_io_in_bits_wdata_dataout_13_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_4_0 = data_io_in_bits_wdata_dataout_13_value_3_0 |
- data_io_in_bits_wdata_dataout_13_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_4_1 = data_io_in_bits_wdata_dataout_13_value_3_2 |
- data_io_in_bits_wdata_dataout_13_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_13_value_5_0 = data_io_in_bits_wdata_dataout_13_value_4_0 |
- data_io_in_bits_wdata_dataout_13_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_14 = 5'he - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__0 = 5'h0 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__1 = 5'h1 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__2 = 5'h2 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__3 = 5'h3 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__4 = 5'h4 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__5 = 5'h5 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__6 = 5'h6 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__7 = 5'h7 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__8 = 5'h8 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__9 = 5'h9 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__10 = 5'ha == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__11 = 5'hb == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__12 = 5'hc == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__13 = 5'hd == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__14 = 5'he == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__15 = 5'hf == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__16 = 5'h10 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__17 = 5'h11 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__18 = 5'h12 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__19 = 5'h13 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__20 = 5'h14 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__21 = 5'h15 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__22 = 5'h16 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__23 = 5'h17 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__24 = 5'h18 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__25 = 5'h19 == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__26 = 5'h1a == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__27 = 5'h1b == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__28 = 5'h1c == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__29 = 5'h1d == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__30 = 5'h1e == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value__31 = 5'h1f == data_io_in_bits_wdata_idx_14 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_0 = data_io_in_bits_wdata_dataout_14_value__0 |
- data_io_in_bits_wdata_dataout_14_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_1 = data_io_in_bits_wdata_dataout_14_value__2 |
- data_io_in_bits_wdata_dataout_14_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_2 = data_io_in_bits_wdata_dataout_14_value__4 |
- data_io_in_bits_wdata_dataout_14_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_3 = data_io_in_bits_wdata_dataout_14_value__6 |
- data_io_in_bits_wdata_dataout_14_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_4 = data_io_in_bits_wdata_dataout_14_value__8 |
- data_io_in_bits_wdata_dataout_14_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_5 = data_io_in_bits_wdata_dataout_14_value__10 |
- data_io_in_bits_wdata_dataout_14_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_6 = data_io_in_bits_wdata_dataout_14_value__12 |
- data_io_in_bits_wdata_dataout_14_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_7 = data_io_in_bits_wdata_dataout_14_value__14 |
- data_io_in_bits_wdata_dataout_14_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_8 = data_io_in_bits_wdata_dataout_14_value__16 |
- data_io_in_bits_wdata_dataout_14_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_9 = data_io_in_bits_wdata_dataout_14_value__18 |
- data_io_in_bits_wdata_dataout_14_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_10 = data_io_in_bits_wdata_dataout_14_value__20 |
- data_io_in_bits_wdata_dataout_14_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_11 = data_io_in_bits_wdata_dataout_14_value__22 |
- data_io_in_bits_wdata_dataout_14_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_12 = data_io_in_bits_wdata_dataout_14_value__24 |
- data_io_in_bits_wdata_dataout_14_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_13 = data_io_in_bits_wdata_dataout_14_value__26 |
- data_io_in_bits_wdata_dataout_14_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_14 = data_io_in_bits_wdata_dataout_14_value__28 |
- data_io_in_bits_wdata_dataout_14_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_1_15 = data_io_in_bits_wdata_dataout_14_value__30 |
- data_io_in_bits_wdata_dataout_14_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_2_0 = data_io_in_bits_wdata_dataout_14_value_1_0 |
- data_io_in_bits_wdata_dataout_14_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_2_1 = data_io_in_bits_wdata_dataout_14_value_1_2 |
- data_io_in_bits_wdata_dataout_14_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_2_2 = data_io_in_bits_wdata_dataout_14_value_1_4 |
- data_io_in_bits_wdata_dataout_14_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_2_3 = data_io_in_bits_wdata_dataout_14_value_1_6 |
- data_io_in_bits_wdata_dataout_14_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_2_4 = data_io_in_bits_wdata_dataout_14_value_1_8 |
- data_io_in_bits_wdata_dataout_14_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_2_5 = data_io_in_bits_wdata_dataout_14_value_1_10 |
- data_io_in_bits_wdata_dataout_14_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_2_6 = data_io_in_bits_wdata_dataout_14_value_1_12 |
- data_io_in_bits_wdata_dataout_14_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_2_7 = data_io_in_bits_wdata_dataout_14_value_1_14 |
- data_io_in_bits_wdata_dataout_14_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_3_0 = data_io_in_bits_wdata_dataout_14_value_2_0 |
- data_io_in_bits_wdata_dataout_14_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_3_1 = data_io_in_bits_wdata_dataout_14_value_2_2 |
- data_io_in_bits_wdata_dataout_14_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_3_2 = data_io_in_bits_wdata_dataout_14_value_2_4 |
- data_io_in_bits_wdata_dataout_14_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_3_3 = data_io_in_bits_wdata_dataout_14_value_2_6 |
- data_io_in_bits_wdata_dataout_14_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_4_0 = data_io_in_bits_wdata_dataout_14_value_3_0 |
- data_io_in_bits_wdata_dataout_14_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_4_1 = data_io_in_bits_wdata_dataout_14_value_3_2 |
- data_io_in_bits_wdata_dataout_14_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_14_value_5_0 = data_io_in_bits_wdata_dataout_14_value_4_0 |
- data_io_in_bits_wdata_dataout_14_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_15 = 5'hf - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__0 = 5'h0 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__1 = 5'h1 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__2 = 5'h2 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__3 = 5'h3 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__4 = 5'h4 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__5 = 5'h5 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__6 = 5'h6 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__7 = 5'h7 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__8 = 5'h8 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__9 = 5'h9 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__10 = 5'ha == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__11 = 5'hb == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__12 = 5'hc == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__13 = 5'hd == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__14 = 5'he == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__15 = 5'hf == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__16 = 5'h10 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__17 = 5'h11 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__18 = 5'h12 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__19 = 5'h13 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__20 = 5'h14 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__21 = 5'h15 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__22 = 5'h16 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__23 = 5'h17 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__24 = 5'h18 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__25 = 5'h19 == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__26 = 5'h1a == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__27 = 5'h1b == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__28 = 5'h1c == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__29 = 5'h1d == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__30 = 5'h1e == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value__31 = 5'h1f == data_io_in_bits_wdata_idx_15 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_0 = data_io_in_bits_wdata_dataout_15_value__0 |
- data_io_in_bits_wdata_dataout_15_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_1 = data_io_in_bits_wdata_dataout_15_value__2 |
- data_io_in_bits_wdata_dataout_15_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_2 = data_io_in_bits_wdata_dataout_15_value__4 |
- data_io_in_bits_wdata_dataout_15_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_3 = data_io_in_bits_wdata_dataout_15_value__6 |
- data_io_in_bits_wdata_dataout_15_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_4 = data_io_in_bits_wdata_dataout_15_value__8 |
- data_io_in_bits_wdata_dataout_15_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_5 = data_io_in_bits_wdata_dataout_15_value__10 |
- data_io_in_bits_wdata_dataout_15_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_6 = data_io_in_bits_wdata_dataout_15_value__12 |
- data_io_in_bits_wdata_dataout_15_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_7 = data_io_in_bits_wdata_dataout_15_value__14 |
- data_io_in_bits_wdata_dataout_15_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_8 = data_io_in_bits_wdata_dataout_15_value__16 |
- data_io_in_bits_wdata_dataout_15_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_9 = data_io_in_bits_wdata_dataout_15_value__18 |
- data_io_in_bits_wdata_dataout_15_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_10 = data_io_in_bits_wdata_dataout_15_value__20 |
- data_io_in_bits_wdata_dataout_15_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_11 = data_io_in_bits_wdata_dataout_15_value__22 |
- data_io_in_bits_wdata_dataout_15_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_12 = data_io_in_bits_wdata_dataout_15_value__24 |
- data_io_in_bits_wdata_dataout_15_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_13 = data_io_in_bits_wdata_dataout_15_value__26 |
- data_io_in_bits_wdata_dataout_15_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_14 = data_io_in_bits_wdata_dataout_15_value__28 |
- data_io_in_bits_wdata_dataout_15_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_1_15 = data_io_in_bits_wdata_dataout_15_value__30 |
- data_io_in_bits_wdata_dataout_15_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_2_0 = data_io_in_bits_wdata_dataout_15_value_1_0 |
- data_io_in_bits_wdata_dataout_15_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_2_1 = data_io_in_bits_wdata_dataout_15_value_1_2 |
- data_io_in_bits_wdata_dataout_15_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_2_2 = data_io_in_bits_wdata_dataout_15_value_1_4 |
- data_io_in_bits_wdata_dataout_15_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_2_3 = data_io_in_bits_wdata_dataout_15_value_1_6 |
- data_io_in_bits_wdata_dataout_15_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_2_4 = data_io_in_bits_wdata_dataout_15_value_1_8 |
- data_io_in_bits_wdata_dataout_15_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_2_5 = data_io_in_bits_wdata_dataout_15_value_1_10 |
- data_io_in_bits_wdata_dataout_15_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_2_6 = data_io_in_bits_wdata_dataout_15_value_1_12 |
- data_io_in_bits_wdata_dataout_15_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_2_7 = data_io_in_bits_wdata_dataout_15_value_1_14 |
- data_io_in_bits_wdata_dataout_15_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_3_0 = data_io_in_bits_wdata_dataout_15_value_2_0 |
- data_io_in_bits_wdata_dataout_15_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_3_1 = data_io_in_bits_wdata_dataout_15_value_2_2 |
- data_io_in_bits_wdata_dataout_15_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_3_2 = data_io_in_bits_wdata_dataout_15_value_2_4 |
- data_io_in_bits_wdata_dataout_15_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_3_3 = data_io_in_bits_wdata_dataout_15_value_2_6 |
- data_io_in_bits_wdata_dataout_15_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_4_0 = data_io_in_bits_wdata_dataout_15_value_3_0 |
- data_io_in_bits_wdata_dataout_15_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_4_1 = data_io_in_bits_wdata_dataout_15_value_3_2 |
- data_io_in_bits_wdata_dataout_15_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_15_value_5_0 = data_io_in_bits_wdata_dataout_15_value_4_0 |
- data_io_in_bits_wdata_dataout_15_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_16 = 5'h10 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__0 = 5'h0 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__1 = 5'h1 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__2 = 5'h2 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__3 = 5'h3 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__4 = 5'h4 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__5 = 5'h5 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__6 = 5'h6 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__7 = 5'h7 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__8 = 5'h8 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__9 = 5'h9 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__10 = 5'ha == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__11 = 5'hb == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__12 = 5'hc == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__13 = 5'hd == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__14 = 5'he == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__15 = 5'hf == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__16 = 5'h10 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__17 = 5'h11 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__18 = 5'h12 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__19 = 5'h13 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__20 = 5'h14 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__21 = 5'h15 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__22 = 5'h16 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__23 = 5'h17 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__24 = 5'h18 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__25 = 5'h19 == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__26 = 5'h1a == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__27 = 5'h1b == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__28 = 5'h1c == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__29 = 5'h1d == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__30 = 5'h1e == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value__31 = 5'h1f == data_io_in_bits_wdata_idx_16 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_0 = data_io_in_bits_wdata_dataout_16_value__0 |
- data_io_in_bits_wdata_dataout_16_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_1 = data_io_in_bits_wdata_dataout_16_value__2 |
- data_io_in_bits_wdata_dataout_16_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_2 = data_io_in_bits_wdata_dataout_16_value__4 |
- data_io_in_bits_wdata_dataout_16_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_3 = data_io_in_bits_wdata_dataout_16_value__6 |
- data_io_in_bits_wdata_dataout_16_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_4 = data_io_in_bits_wdata_dataout_16_value__8 |
- data_io_in_bits_wdata_dataout_16_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_5 = data_io_in_bits_wdata_dataout_16_value__10 |
- data_io_in_bits_wdata_dataout_16_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_6 = data_io_in_bits_wdata_dataout_16_value__12 |
- data_io_in_bits_wdata_dataout_16_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_7 = data_io_in_bits_wdata_dataout_16_value__14 |
- data_io_in_bits_wdata_dataout_16_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_8 = data_io_in_bits_wdata_dataout_16_value__16 |
- data_io_in_bits_wdata_dataout_16_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_9 = data_io_in_bits_wdata_dataout_16_value__18 |
- data_io_in_bits_wdata_dataout_16_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_10 = data_io_in_bits_wdata_dataout_16_value__20 |
- data_io_in_bits_wdata_dataout_16_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_11 = data_io_in_bits_wdata_dataout_16_value__22 |
- data_io_in_bits_wdata_dataout_16_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_12 = data_io_in_bits_wdata_dataout_16_value__24 |
- data_io_in_bits_wdata_dataout_16_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_13 = data_io_in_bits_wdata_dataout_16_value__26 |
- data_io_in_bits_wdata_dataout_16_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_14 = data_io_in_bits_wdata_dataout_16_value__28 |
- data_io_in_bits_wdata_dataout_16_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_1_15 = data_io_in_bits_wdata_dataout_16_value__30 |
- data_io_in_bits_wdata_dataout_16_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_2_0 = data_io_in_bits_wdata_dataout_16_value_1_0 |
- data_io_in_bits_wdata_dataout_16_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_2_1 = data_io_in_bits_wdata_dataout_16_value_1_2 |
- data_io_in_bits_wdata_dataout_16_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_2_2 = data_io_in_bits_wdata_dataout_16_value_1_4 |
- data_io_in_bits_wdata_dataout_16_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_2_3 = data_io_in_bits_wdata_dataout_16_value_1_6 |
- data_io_in_bits_wdata_dataout_16_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_2_4 = data_io_in_bits_wdata_dataout_16_value_1_8 |
- data_io_in_bits_wdata_dataout_16_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_2_5 = data_io_in_bits_wdata_dataout_16_value_1_10 |
- data_io_in_bits_wdata_dataout_16_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_2_6 = data_io_in_bits_wdata_dataout_16_value_1_12 |
- data_io_in_bits_wdata_dataout_16_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_2_7 = data_io_in_bits_wdata_dataout_16_value_1_14 |
- data_io_in_bits_wdata_dataout_16_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_3_0 = data_io_in_bits_wdata_dataout_16_value_2_0 |
- data_io_in_bits_wdata_dataout_16_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_3_1 = data_io_in_bits_wdata_dataout_16_value_2_2 |
- data_io_in_bits_wdata_dataout_16_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_3_2 = data_io_in_bits_wdata_dataout_16_value_2_4 |
- data_io_in_bits_wdata_dataout_16_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_3_3 = data_io_in_bits_wdata_dataout_16_value_2_6 |
- data_io_in_bits_wdata_dataout_16_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_4_0 = data_io_in_bits_wdata_dataout_16_value_3_0 |
- data_io_in_bits_wdata_dataout_16_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_4_1 = data_io_in_bits_wdata_dataout_16_value_3_2 |
- data_io_in_bits_wdata_dataout_16_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_16_value_5_0 = data_io_in_bits_wdata_dataout_16_value_4_0 |
- data_io_in_bits_wdata_dataout_16_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_17 = 5'h11 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__0 = 5'h0 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__1 = 5'h1 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__2 = 5'h2 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__3 = 5'h3 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__4 = 5'h4 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__5 = 5'h5 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__6 = 5'h6 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__7 = 5'h7 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__8 = 5'h8 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__9 = 5'h9 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__10 = 5'ha == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__11 = 5'hb == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__12 = 5'hc == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__13 = 5'hd == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__14 = 5'he == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__15 = 5'hf == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__16 = 5'h10 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__17 = 5'h11 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__18 = 5'h12 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__19 = 5'h13 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__20 = 5'h14 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__21 = 5'h15 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__22 = 5'h16 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__23 = 5'h17 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__24 = 5'h18 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__25 = 5'h19 == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__26 = 5'h1a == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__27 = 5'h1b == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__28 = 5'h1c == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__29 = 5'h1d == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__30 = 5'h1e == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value__31 = 5'h1f == data_io_in_bits_wdata_idx_17 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_0 = data_io_in_bits_wdata_dataout_17_value__0 |
- data_io_in_bits_wdata_dataout_17_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_1 = data_io_in_bits_wdata_dataout_17_value__2 |
- data_io_in_bits_wdata_dataout_17_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_2 = data_io_in_bits_wdata_dataout_17_value__4 |
- data_io_in_bits_wdata_dataout_17_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_3 = data_io_in_bits_wdata_dataout_17_value__6 |
- data_io_in_bits_wdata_dataout_17_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_4 = data_io_in_bits_wdata_dataout_17_value__8 |
- data_io_in_bits_wdata_dataout_17_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_5 = data_io_in_bits_wdata_dataout_17_value__10 |
- data_io_in_bits_wdata_dataout_17_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_6 = data_io_in_bits_wdata_dataout_17_value__12 |
- data_io_in_bits_wdata_dataout_17_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_7 = data_io_in_bits_wdata_dataout_17_value__14 |
- data_io_in_bits_wdata_dataout_17_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_8 = data_io_in_bits_wdata_dataout_17_value__16 |
- data_io_in_bits_wdata_dataout_17_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_9 = data_io_in_bits_wdata_dataout_17_value__18 |
- data_io_in_bits_wdata_dataout_17_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_10 = data_io_in_bits_wdata_dataout_17_value__20 |
- data_io_in_bits_wdata_dataout_17_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_11 = data_io_in_bits_wdata_dataout_17_value__22 |
- data_io_in_bits_wdata_dataout_17_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_12 = data_io_in_bits_wdata_dataout_17_value__24 |
- data_io_in_bits_wdata_dataout_17_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_13 = data_io_in_bits_wdata_dataout_17_value__26 |
- data_io_in_bits_wdata_dataout_17_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_14 = data_io_in_bits_wdata_dataout_17_value__28 |
- data_io_in_bits_wdata_dataout_17_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_1_15 = data_io_in_bits_wdata_dataout_17_value__30 |
- data_io_in_bits_wdata_dataout_17_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_2_0 = data_io_in_bits_wdata_dataout_17_value_1_0 |
- data_io_in_bits_wdata_dataout_17_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_2_1 = data_io_in_bits_wdata_dataout_17_value_1_2 |
- data_io_in_bits_wdata_dataout_17_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_2_2 = data_io_in_bits_wdata_dataout_17_value_1_4 |
- data_io_in_bits_wdata_dataout_17_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_2_3 = data_io_in_bits_wdata_dataout_17_value_1_6 |
- data_io_in_bits_wdata_dataout_17_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_2_4 = data_io_in_bits_wdata_dataout_17_value_1_8 |
- data_io_in_bits_wdata_dataout_17_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_2_5 = data_io_in_bits_wdata_dataout_17_value_1_10 |
- data_io_in_bits_wdata_dataout_17_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_2_6 = data_io_in_bits_wdata_dataout_17_value_1_12 |
- data_io_in_bits_wdata_dataout_17_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_2_7 = data_io_in_bits_wdata_dataout_17_value_1_14 |
- data_io_in_bits_wdata_dataout_17_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_3_0 = data_io_in_bits_wdata_dataout_17_value_2_0 |
- data_io_in_bits_wdata_dataout_17_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_3_1 = data_io_in_bits_wdata_dataout_17_value_2_2 |
- data_io_in_bits_wdata_dataout_17_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_3_2 = data_io_in_bits_wdata_dataout_17_value_2_4 |
- data_io_in_bits_wdata_dataout_17_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_3_3 = data_io_in_bits_wdata_dataout_17_value_2_6 |
- data_io_in_bits_wdata_dataout_17_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_4_0 = data_io_in_bits_wdata_dataout_17_value_3_0 |
- data_io_in_bits_wdata_dataout_17_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_4_1 = data_io_in_bits_wdata_dataout_17_value_3_2 |
- data_io_in_bits_wdata_dataout_17_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_17_value_5_0 = data_io_in_bits_wdata_dataout_17_value_4_0 |
- data_io_in_bits_wdata_dataout_17_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_18 = 5'h12 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__0 = 5'h0 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__1 = 5'h1 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__2 = 5'h2 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__3 = 5'h3 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__4 = 5'h4 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__5 = 5'h5 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__6 = 5'h6 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__7 = 5'h7 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__8 = 5'h8 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__9 = 5'h9 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__10 = 5'ha == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__11 = 5'hb == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__12 = 5'hc == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__13 = 5'hd == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__14 = 5'he == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__15 = 5'hf == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__16 = 5'h10 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__17 = 5'h11 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__18 = 5'h12 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__19 = 5'h13 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__20 = 5'h14 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__21 = 5'h15 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__22 = 5'h16 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__23 = 5'h17 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__24 = 5'h18 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__25 = 5'h19 == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__26 = 5'h1a == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__27 = 5'h1b == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__28 = 5'h1c == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__29 = 5'h1d == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__30 = 5'h1e == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value__31 = 5'h1f == data_io_in_bits_wdata_idx_18 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_0 = data_io_in_bits_wdata_dataout_18_value__0 |
- data_io_in_bits_wdata_dataout_18_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_1 = data_io_in_bits_wdata_dataout_18_value__2 |
- data_io_in_bits_wdata_dataout_18_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_2 = data_io_in_bits_wdata_dataout_18_value__4 |
- data_io_in_bits_wdata_dataout_18_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_3 = data_io_in_bits_wdata_dataout_18_value__6 |
- data_io_in_bits_wdata_dataout_18_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_4 = data_io_in_bits_wdata_dataout_18_value__8 |
- data_io_in_bits_wdata_dataout_18_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_5 = data_io_in_bits_wdata_dataout_18_value__10 |
- data_io_in_bits_wdata_dataout_18_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_6 = data_io_in_bits_wdata_dataout_18_value__12 |
- data_io_in_bits_wdata_dataout_18_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_7 = data_io_in_bits_wdata_dataout_18_value__14 |
- data_io_in_bits_wdata_dataout_18_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_8 = data_io_in_bits_wdata_dataout_18_value__16 |
- data_io_in_bits_wdata_dataout_18_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_9 = data_io_in_bits_wdata_dataout_18_value__18 |
- data_io_in_bits_wdata_dataout_18_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_10 = data_io_in_bits_wdata_dataout_18_value__20 |
- data_io_in_bits_wdata_dataout_18_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_11 = data_io_in_bits_wdata_dataout_18_value__22 |
- data_io_in_bits_wdata_dataout_18_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_12 = data_io_in_bits_wdata_dataout_18_value__24 |
- data_io_in_bits_wdata_dataout_18_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_13 = data_io_in_bits_wdata_dataout_18_value__26 |
- data_io_in_bits_wdata_dataout_18_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_14 = data_io_in_bits_wdata_dataout_18_value__28 |
- data_io_in_bits_wdata_dataout_18_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_1_15 = data_io_in_bits_wdata_dataout_18_value__30 |
- data_io_in_bits_wdata_dataout_18_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_2_0 = data_io_in_bits_wdata_dataout_18_value_1_0 |
- data_io_in_bits_wdata_dataout_18_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_2_1 = data_io_in_bits_wdata_dataout_18_value_1_2 |
- data_io_in_bits_wdata_dataout_18_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_2_2 = data_io_in_bits_wdata_dataout_18_value_1_4 |
- data_io_in_bits_wdata_dataout_18_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_2_3 = data_io_in_bits_wdata_dataout_18_value_1_6 |
- data_io_in_bits_wdata_dataout_18_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_2_4 = data_io_in_bits_wdata_dataout_18_value_1_8 |
- data_io_in_bits_wdata_dataout_18_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_2_5 = data_io_in_bits_wdata_dataout_18_value_1_10 |
- data_io_in_bits_wdata_dataout_18_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_2_6 = data_io_in_bits_wdata_dataout_18_value_1_12 |
- data_io_in_bits_wdata_dataout_18_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_2_7 = data_io_in_bits_wdata_dataout_18_value_1_14 |
- data_io_in_bits_wdata_dataout_18_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_3_0 = data_io_in_bits_wdata_dataout_18_value_2_0 |
- data_io_in_bits_wdata_dataout_18_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_3_1 = data_io_in_bits_wdata_dataout_18_value_2_2 |
- data_io_in_bits_wdata_dataout_18_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_3_2 = data_io_in_bits_wdata_dataout_18_value_2_4 |
- data_io_in_bits_wdata_dataout_18_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_3_3 = data_io_in_bits_wdata_dataout_18_value_2_6 |
- data_io_in_bits_wdata_dataout_18_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_4_0 = data_io_in_bits_wdata_dataout_18_value_3_0 |
- data_io_in_bits_wdata_dataout_18_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_4_1 = data_io_in_bits_wdata_dataout_18_value_3_2 |
- data_io_in_bits_wdata_dataout_18_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_18_value_5_0 = data_io_in_bits_wdata_dataout_18_value_4_0 |
- data_io_in_bits_wdata_dataout_18_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_19 = 5'h13 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__0 = 5'h0 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__1 = 5'h1 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__2 = 5'h2 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__3 = 5'h3 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__4 = 5'h4 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__5 = 5'h5 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__6 = 5'h6 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__7 = 5'h7 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__8 = 5'h8 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__9 = 5'h9 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__10 = 5'ha == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__11 = 5'hb == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__12 = 5'hc == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__13 = 5'hd == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__14 = 5'he == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__15 = 5'hf == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__16 = 5'h10 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__17 = 5'h11 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__18 = 5'h12 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__19 = 5'h13 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__20 = 5'h14 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__21 = 5'h15 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__22 = 5'h16 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__23 = 5'h17 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__24 = 5'h18 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__25 = 5'h19 == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__26 = 5'h1a == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__27 = 5'h1b == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__28 = 5'h1c == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__29 = 5'h1d == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__30 = 5'h1e == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value__31 = 5'h1f == data_io_in_bits_wdata_idx_19 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_0 = data_io_in_bits_wdata_dataout_19_value__0 |
- data_io_in_bits_wdata_dataout_19_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_1 = data_io_in_bits_wdata_dataout_19_value__2 |
- data_io_in_bits_wdata_dataout_19_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_2 = data_io_in_bits_wdata_dataout_19_value__4 |
- data_io_in_bits_wdata_dataout_19_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_3 = data_io_in_bits_wdata_dataout_19_value__6 |
- data_io_in_bits_wdata_dataout_19_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_4 = data_io_in_bits_wdata_dataout_19_value__8 |
- data_io_in_bits_wdata_dataout_19_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_5 = data_io_in_bits_wdata_dataout_19_value__10 |
- data_io_in_bits_wdata_dataout_19_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_6 = data_io_in_bits_wdata_dataout_19_value__12 |
- data_io_in_bits_wdata_dataout_19_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_7 = data_io_in_bits_wdata_dataout_19_value__14 |
- data_io_in_bits_wdata_dataout_19_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_8 = data_io_in_bits_wdata_dataout_19_value__16 |
- data_io_in_bits_wdata_dataout_19_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_9 = data_io_in_bits_wdata_dataout_19_value__18 |
- data_io_in_bits_wdata_dataout_19_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_10 = data_io_in_bits_wdata_dataout_19_value__20 |
- data_io_in_bits_wdata_dataout_19_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_11 = data_io_in_bits_wdata_dataout_19_value__22 |
- data_io_in_bits_wdata_dataout_19_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_12 = data_io_in_bits_wdata_dataout_19_value__24 |
- data_io_in_bits_wdata_dataout_19_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_13 = data_io_in_bits_wdata_dataout_19_value__26 |
- data_io_in_bits_wdata_dataout_19_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_14 = data_io_in_bits_wdata_dataout_19_value__28 |
- data_io_in_bits_wdata_dataout_19_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_1_15 = data_io_in_bits_wdata_dataout_19_value__30 |
- data_io_in_bits_wdata_dataout_19_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_2_0 = data_io_in_bits_wdata_dataout_19_value_1_0 |
- data_io_in_bits_wdata_dataout_19_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_2_1 = data_io_in_bits_wdata_dataout_19_value_1_2 |
- data_io_in_bits_wdata_dataout_19_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_2_2 = data_io_in_bits_wdata_dataout_19_value_1_4 |
- data_io_in_bits_wdata_dataout_19_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_2_3 = data_io_in_bits_wdata_dataout_19_value_1_6 |
- data_io_in_bits_wdata_dataout_19_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_2_4 = data_io_in_bits_wdata_dataout_19_value_1_8 |
- data_io_in_bits_wdata_dataout_19_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_2_5 = data_io_in_bits_wdata_dataout_19_value_1_10 |
- data_io_in_bits_wdata_dataout_19_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_2_6 = data_io_in_bits_wdata_dataout_19_value_1_12 |
- data_io_in_bits_wdata_dataout_19_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_2_7 = data_io_in_bits_wdata_dataout_19_value_1_14 |
- data_io_in_bits_wdata_dataout_19_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_3_0 = data_io_in_bits_wdata_dataout_19_value_2_0 |
- data_io_in_bits_wdata_dataout_19_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_3_1 = data_io_in_bits_wdata_dataout_19_value_2_2 |
- data_io_in_bits_wdata_dataout_19_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_3_2 = data_io_in_bits_wdata_dataout_19_value_2_4 |
- data_io_in_bits_wdata_dataout_19_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_3_3 = data_io_in_bits_wdata_dataout_19_value_2_6 |
- data_io_in_bits_wdata_dataout_19_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_4_0 = data_io_in_bits_wdata_dataout_19_value_3_0 |
- data_io_in_bits_wdata_dataout_19_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_4_1 = data_io_in_bits_wdata_dataout_19_value_3_2 |
- data_io_in_bits_wdata_dataout_19_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_19_value_5_0 = data_io_in_bits_wdata_dataout_19_value_4_0 |
- data_io_in_bits_wdata_dataout_19_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_20 = 5'h14 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__0 = 5'h0 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__1 = 5'h1 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__2 = 5'h2 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__3 = 5'h3 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__4 = 5'h4 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__5 = 5'h5 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__6 = 5'h6 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__7 = 5'h7 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__8 = 5'h8 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__9 = 5'h9 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__10 = 5'ha == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__11 = 5'hb == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__12 = 5'hc == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__13 = 5'hd == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__14 = 5'he == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__15 = 5'hf == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__16 = 5'h10 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__17 = 5'h11 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__18 = 5'h12 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__19 = 5'h13 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__20 = 5'h14 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__21 = 5'h15 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__22 = 5'h16 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__23 = 5'h17 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__24 = 5'h18 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__25 = 5'h19 == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__26 = 5'h1a == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__27 = 5'h1b == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__28 = 5'h1c == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__29 = 5'h1d == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__30 = 5'h1e == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value__31 = 5'h1f == data_io_in_bits_wdata_idx_20 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_0 = data_io_in_bits_wdata_dataout_20_value__0 |
- data_io_in_bits_wdata_dataout_20_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_1 = data_io_in_bits_wdata_dataout_20_value__2 |
- data_io_in_bits_wdata_dataout_20_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_2 = data_io_in_bits_wdata_dataout_20_value__4 |
- data_io_in_bits_wdata_dataout_20_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_3 = data_io_in_bits_wdata_dataout_20_value__6 |
- data_io_in_bits_wdata_dataout_20_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_4 = data_io_in_bits_wdata_dataout_20_value__8 |
- data_io_in_bits_wdata_dataout_20_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_5 = data_io_in_bits_wdata_dataout_20_value__10 |
- data_io_in_bits_wdata_dataout_20_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_6 = data_io_in_bits_wdata_dataout_20_value__12 |
- data_io_in_bits_wdata_dataout_20_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_7 = data_io_in_bits_wdata_dataout_20_value__14 |
- data_io_in_bits_wdata_dataout_20_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_8 = data_io_in_bits_wdata_dataout_20_value__16 |
- data_io_in_bits_wdata_dataout_20_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_9 = data_io_in_bits_wdata_dataout_20_value__18 |
- data_io_in_bits_wdata_dataout_20_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_10 = data_io_in_bits_wdata_dataout_20_value__20 |
- data_io_in_bits_wdata_dataout_20_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_11 = data_io_in_bits_wdata_dataout_20_value__22 |
- data_io_in_bits_wdata_dataout_20_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_12 = data_io_in_bits_wdata_dataout_20_value__24 |
- data_io_in_bits_wdata_dataout_20_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_13 = data_io_in_bits_wdata_dataout_20_value__26 |
- data_io_in_bits_wdata_dataout_20_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_14 = data_io_in_bits_wdata_dataout_20_value__28 |
- data_io_in_bits_wdata_dataout_20_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_1_15 = data_io_in_bits_wdata_dataout_20_value__30 |
- data_io_in_bits_wdata_dataout_20_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_2_0 = data_io_in_bits_wdata_dataout_20_value_1_0 |
- data_io_in_bits_wdata_dataout_20_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_2_1 = data_io_in_bits_wdata_dataout_20_value_1_2 |
- data_io_in_bits_wdata_dataout_20_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_2_2 = data_io_in_bits_wdata_dataout_20_value_1_4 |
- data_io_in_bits_wdata_dataout_20_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_2_3 = data_io_in_bits_wdata_dataout_20_value_1_6 |
- data_io_in_bits_wdata_dataout_20_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_2_4 = data_io_in_bits_wdata_dataout_20_value_1_8 |
- data_io_in_bits_wdata_dataout_20_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_2_5 = data_io_in_bits_wdata_dataout_20_value_1_10 |
- data_io_in_bits_wdata_dataout_20_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_2_6 = data_io_in_bits_wdata_dataout_20_value_1_12 |
- data_io_in_bits_wdata_dataout_20_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_2_7 = data_io_in_bits_wdata_dataout_20_value_1_14 |
- data_io_in_bits_wdata_dataout_20_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_3_0 = data_io_in_bits_wdata_dataout_20_value_2_0 |
- data_io_in_bits_wdata_dataout_20_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_3_1 = data_io_in_bits_wdata_dataout_20_value_2_2 |
- data_io_in_bits_wdata_dataout_20_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_3_2 = data_io_in_bits_wdata_dataout_20_value_2_4 |
- data_io_in_bits_wdata_dataout_20_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_3_3 = data_io_in_bits_wdata_dataout_20_value_2_6 |
- data_io_in_bits_wdata_dataout_20_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_4_0 = data_io_in_bits_wdata_dataout_20_value_3_0 |
- data_io_in_bits_wdata_dataout_20_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_4_1 = data_io_in_bits_wdata_dataout_20_value_3_2 |
- data_io_in_bits_wdata_dataout_20_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_20_value_5_0 = data_io_in_bits_wdata_dataout_20_value_4_0 |
- data_io_in_bits_wdata_dataout_20_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_21 = 5'h15 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__0 = 5'h0 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__1 = 5'h1 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__2 = 5'h2 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__3 = 5'h3 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__4 = 5'h4 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__5 = 5'h5 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__6 = 5'h6 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__7 = 5'h7 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__8 = 5'h8 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__9 = 5'h9 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__10 = 5'ha == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__11 = 5'hb == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__12 = 5'hc == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__13 = 5'hd == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__14 = 5'he == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__15 = 5'hf == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__16 = 5'h10 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__17 = 5'h11 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__18 = 5'h12 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__19 = 5'h13 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__20 = 5'h14 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__21 = 5'h15 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__22 = 5'h16 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__23 = 5'h17 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__24 = 5'h18 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__25 = 5'h19 == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__26 = 5'h1a == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__27 = 5'h1b == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__28 = 5'h1c == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__29 = 5'h1d == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__30 = 5'h1e == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value__31 = 5'h1f == data_io_in_bits_wdata_idx_21 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_0 = data_io_in_bits_wdata_dataout_21_value__0 |
- data_io_in_bits_wdata_dataout_21_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_1 = data_io_in_bits_wdata_dataout_21_value__2 |
- data_io_in_bits_wdata_dataout_21_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_2 = data_io_in_bits_wdata_dataout_21_value__4 |
- data_io_in_bits_wdata_dataout_21_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_3 = data_io_in_bits_wdata_dataout_21_value__6 |
- data_io_in_bits_wdata_dataout_21_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_4 = data_io_in_bits_wdata_dataout_21_value__8 |
- data_io_in_bits_wdata_dataout_21_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_5 = data_io_in_bits_wdata_dataout_21_value__10 |
- data_io_in_bits_wdata_dataout_21_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_6 = data_io_in_bits_wdata_dataout_21_value__12 |
- data_io_in_bits_wdata_dataout_21_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_7 = data_io_in_bits_wdata_dataout_21_value__14 |
- data_io_in_bits_wdata_dataout_21_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_8 = data_io_in_bits_wdata_dataout_21_value__16 |
- data_io_in_bits_wdata_dataout_21_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_9 = data_io_in_bits_wdata_dataout_21_value__18 |
- data_io_in_bits_wdata_dataout_21_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_10 = data_io_in_bits_wdata_dataout_21_value__20 |
- data_io_in_bits_wdata_dataout_21_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_11 = data_io_in_bits_wdata_dataout_21_value__22 |
- data_io_in_bits_wdata_dataout_21_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_12 = data_io_in_bits_wdata_dataout_21_value__24 |
- data_io_in_bits_wdata_dataout_21_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_13 = data_io_in_bits_wdata_dataout_21_value__26 |
- data_io_in_bits_wdata_dataout_21_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_14 = data_io_in_bits_wdata_dataout_21_value__28 |
- data_io_in_bits_wdata_dataout_21_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_1_15 = data_io_in_bits_wdata_dataout_21_value__30 |
- data_io_in_bits_wdata_dataout_21_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_2_0 = data_io_in_bits_wdata_dataout_21_value_1_0 |
- data_io_in_bits_wdata_dataout_21_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_2_1 = data_io_in_bits_wdata_dataout_21_value_1_2 |
- data_io_in_bits_wdata_dataout_21_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_2_2 = data_io_in_bits_wdata_dataout_21_value_1_4 |
- data_io_in_bits_wdata_dataout_21_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_2_3 = data_io_in_bits_wdata_dataout_21_value_1_6 |
- data_io_in_bits_wdata_dataout_21_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_2_4 = data_io_in_bits_wdata_dataout_21_value_1_8 |
- data_io_in_bits_wdata_dataout_21_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_2_5 = data_io_in_bits_wdata_dataout_21_value_1_10 |
- data_io_in_bits_wdata_dataout_21_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_2_6 = data_io_in_bits_wdata_dataout_21_value_1_12 |
- data_io_in_bits_wdata_dataout_21_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_2_7 = data_io_in_bits_wdata_dataout_21_value_1_14 |
- data_io_in_bits_wdata_dataout_21_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_3_0 = data_io_in_bits_wdata_dataout_21_value_2_0 |
- data_io_in_bits_wdata_dataout_21_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_3_1 = data_io_in_bits_wdata_dataout_21_value_2_2 |
- data_io_in_bits_wdata_dataout_21_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_3_2 = data_io_in_bits_wdata_dataout_21_value_2_4 |
- data_io_in_bits_wdata_dataout_21_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_3_3 = data_io_in_bits_wdata_dataout_21_value_2_6 |
- data_io_in_bits_wdata_dataout_21_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_4_0 = data_io_in_bits_wdata_dataout_21_value_3_0 |
- data_io_in_bits_wdata_dataout_21_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_4_1 = data_io_in_bits_wdata_dataout_21_value_3_2 |
- data_io_in_bits_wdata_dataout_21_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_21_value_5_0 = data_io_in_bits_wdata_dataout_21_value_4_0 |
- data_io_in_bits_wdata_dataout_21_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_22 = 5'h16 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__0 = 5'h0 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__1 = 5'h1 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__2 = 5'h2 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__3 = 5'h3 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__4 = 5'h4 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__5 = 5'h5 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__6 = 5'h6 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__7 = 5'h7 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__8 = 5'h8 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__9 = 5'h9 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__10 = 5'ha == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__11 = 5'hb == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__12 = 5'hc == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__13 = 5'hd == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__14 = 5'he == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__15 = 5'hf == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__16 = 5'h10 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__17 = 5'h11 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__18 = 5'h12 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__19 = 5'h13 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__20 = 5'h14 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__21 = 5'h15 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__22 = 5'h16 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__23 = 5'h17 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__24 = 5'h18 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__25 = 5'h19 == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__26 = 5'h1a == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__27 = 5'h1b == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__28 = 5'h1c == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__29 = 5'h1d == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__30 = 5'h1e == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value__31 = 5'h1f == data_io_in_bits_wdata_idx_22 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_0 = data_io_in_bits_wdata_dataout_22_value__0 |
- data_io_in_bits_wdata_dataout_22_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_1 = data_io_in_bits_wdata_dataout_22_value__2 |
- data_io_in_bits_wdata_dataout_22_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_2 = data_io_in_bits_wdata_dataout_22_value__4 |
- data_io_in_bits_wdata_dataout_22_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_3 = data_io_in_bits_wdata_dataout_22_value__6 |
- data_io_in_bits_wdata_dataout_22_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_4 = data_io_in_bits_wdata_dataout_22_value__8 |
- data_io_in_bits_wdata_dataout_22_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_5 = data_io_in_bits_wdata_dataout_22_value__10 |
- data_io_in_bits_wdata_dataout_22_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_6 = data_io_in_bits_wdata_dataout_22_value__12 |
- data_io_in_bits_wdata_dataout_22_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_7 = data_io_in_bits_wdata_dataout_22_value__14 |
- data_io_in_bits_wdata_dataout_22_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_8 = data_io_in_bits_wdata_dataout_22_value__16 |
- data_io_in_bits_wdata_dataout_22_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_9 = data_io_in_bits_wdata_dataout_22_value__18 |
- data_io_in_bits_wdata_dataout_22_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_10 = data_io_in_bits_wdata_dataout_22_value__20 |
- data_io_in_bits_wdata_dataout_22_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_11 = data_io_in_bits_wdata_dataout_22_value__22 |
- data_io_in_bits_wdata_dataout_22_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_12 = data_io_in_bits_wdata_dataout_22_value__24 |
- data_io_in_bits_wdata_dataout_22_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_13 = data_io_in_bits_wdata_dataout_22_value__26 |
- data_io_in_bits_wdata_dataout_22_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_14 = data_io_in_bits_wdata_dataout_22_value__28 |
- data_io_in_bits_wdata_dataout_22_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_1_15 = data_io_in_bits_wdata_dataout_22_value__30 |
- data_io_in_bits_wdata_dataout_22_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_2_0 = data_io_in_bits_wdata_dataout_22_value_1_0 |
- data_io_in_bits_wdata_dataout_22_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_2_1 = data_io_in_bits_wdata_dataout_22_value_1_2 |
- data_io_in_bits_wdata_dataout_22_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_2_2 = data_io_in_bits_wdata_dataout_22_value_1_4 |
- data_io_in_bits_wdata_dataout_22_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_2_3 = data_io_in_bits_wdata_dataout_22_value_1_6 |
- data_io_in_bits_wdata_dataout_22_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_2_4 = data_io_in_bits_wdata_dataout_22_value_1_8 |
- data_io_in_bits_wdata_dataout_22_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_2_5 = data_io_in_bits_wdata_dataout_22_value_1_10 |
- data_io_in_bits_wdata_dataout_22_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_2_6 = data_io_in_bits_wdata_dataout_22_value_1_12 |
- data_io_in_bits_wdata_dataout_22_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_2_7 = data_io_in_bits_wdata_dataout_22_value_1_14 |
- data_io_in_bits_wdata_dataout_22_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_3_0 = data_io_in_bits_wdata_dataout_22_value_2_0 |
- data_io_in_bits_wdata_dataout_22_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_3_1 = data_io_in_bits_wdata_dataout_22_value_2_2 |
- data_io_in_bits_wdata_dataout_22_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_3_2 = data_io_in_bits_wdata_dataout_22_value_2_4 |
- data_io_in_bits_wdata_dataout_22_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_3_3 = data_io_in_bits_wdata_dataout_22_value_2_6 |
- data_io_in_bits_wdata_dataout_22_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_4_0 = data_io_in_bits_wdata_dataout_22_value_3_0 |
- data_io_in_bits_wdata_dataout_22_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_4_1 = data_io_in_bits_wdata_dataout_22_value_3_2 |
- data_io_in_bits_wdata_dataout_22_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_22_value_5_0 = data_io_in_bits_wdata_dataout_22_value_4_0 |
- data_io_in_bits_wdata_dataout_22_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_23 = 5'h17 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__0 = 5'h0 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__1 = 5'h1 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__2 = 5'h2 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__3 = 5'h3 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__4 = 5'h4 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__5 = 5'h5 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__6 = 5'h6 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__7 = 5'h7 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__8 = 5'h8 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__9 = 5'h9 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__10 = 5'ha == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__11 = 5'hb == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__12 = 5'hc == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__13 = 5'hd == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__14 = 5'he == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__15 = 5'hf == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__16 = 5'h10 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__17 = 5'h11 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__18 = 5'h12 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__19 = 5'h13 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__20 = 5'h14 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__21 = 5'h15 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__22 = 5'h16 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__23 = 5'h17 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__24 = 5'h18 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__25 = 5'h19 == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__26 = 5'h1a == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__27 = 5'h1b == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__28 = 5'h1c == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__29 = 5'h1d == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__30 = 5'h1e == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value__31 = 5'h1f == data_io_in_bits_wdata_idx_23 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_0 = data_io_in_bits_wdata_dataout_23_value__0 |
- data_io_in_bits_wdata_dataout_23_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_1 = data_io_in_bits_wdata_dataout_23_value__2 |
- data_io_in_bits_wdata_dataout_23_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_2 = data_io_in_bits_wdata_dataout_23_value__4 |
- data_io_in_bits_wdata_dataout_23_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_3 = data_io_in_bits_wdata_dataout_23_value__6 |
- data_io_in_bits_wdata_dataout_23_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_4 = data_io_in_bits_wdata_dataout_23_value__8 |
- data_io_in_bits_wdata_dataout_23_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_5 = data_io_in_bits_wdata_dataout_23_value__10 |
- data_io_in_bits_wdata_dataout_23_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_6 = data_io_in_bits_wdata_dataout_23_value__12 |
- data_io_in_bits_wdata_dataout_23_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_7 = data_io_in_bits_wdata_dataout_23_value__14 |
- data_io_in_bits_wdata_dataout_23_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_8 = data_io_in_bits_wdata_dataout_23_value__16 |
- data_io_in_bits_wdata_dataout_23_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_9 = data_io_in_bits_wdata_dataout_23_value__18 |
- data_io_in_bits_wdata_dataout_23_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_10 = data_io_in_bits_wdata_dataout_23_value__20 |
- data_io_in_bits_wdata_dataout_23_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_11 = data_io_in_bits_wdata_dataout_23_value__22 |
- data_io_in_bits_wdata_dataout_23_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_12 = data_io_in_bits_wdata_dataout_23_value__24 |
- data_io_in_bits_wdata_dataout_23_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_13 = data_io_in_bits_wdata_dataout_23_value__26 |
- data_io_in_bits_wdata_dataout_23_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_14 = data_io_in_bits_wdata_dataout_23_value__28 |
- data_io_in_bits_wdata_dataout_23_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_1_15 = data_io_in_bits_wdata_dataout_23_value__30 |
- data_io_in_bits_wdata_dataout_23_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_2_0 = data_io_in_bits_wdata_dataout_23_value_1_0 |
- data_io_in_bits_wdata_dataout_23_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_2_1 = data_io_in_bits_wdata_dataout_23_value_1_2 |
- data_io_in_bits_wdata_dataout_23_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_2_2 = data_io_in_bits_wdata_dataout_23_value_1_4 |
- data_io_in_bits_wdata_dataout_23_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_2_3 = data_io_in_bits_wdata_dataout_23_value_1_6 |
- data_io_in_bits_wdata_dataout_23_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_2_4 = data_io_in_bits_wdata_dataout_23_value_1_8 |
- data_io_in_bits_wdata_dataout_23_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_2_5 = data_io_in_bits_wdata_dataout_23_value_1_10 |
- data_io_in_bits_wdata_dataout_23_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_2_6 = data_io_in_bits_wdata_dataout_23_value_1_12 |
- data_io_in_bits_wdata_dataout_23_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_2_7 = data_io_in_bits_wdata_dataout_23_value_1_14 |
- data_io_in_bits_wdata_dataout_23_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_3_0 = data_io_in_bits_wdata_dataout_23_value_2_0 |
- data_io_in_bits_wdata_dataout_23_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_3_1 = data_io_in_bits_wdata_dataout_23_value_2_2 |
- data_io_in_bits_wdata_dataout_23_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_3_2 = data_io_in_bits_wdata_dataout_23_value_2_4 |
- data_io_in_bits_wdata_dataout_23_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_3_3 = data_io_in_bits_wdata_dataout_23_value_2_6 |
- data_io_in_bits_wdata_dataout_23_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_4_0 = data_io_in_bits_wdata_dataout_23_value_3_0 |
- data_io_in_bits_wdata_dataout_23_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_4_1 = data_io_in_bits_wdata_dataout_23_value_3_2 |
- data_io_in_bits_wdata_dataout_23_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_23_value_5_0 = data_io_in_bits_wdata_dataout_23_value_4_0 |
- data_io_in_bits_wdata_dataout_23_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_24 = 5'h18 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__0 = 5'h0 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__1 = 5'h1 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__2 = 5'h2 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__3 = 5'h3 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__4 = 5'h4 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__5 = 5'h5 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__6 = 5'h6 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__7 = 5'h7 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__8 = 5'h8 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__9 = 5'h9 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__10 = 5'ha == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__11 = 5'hb == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__12 = 5'hc == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__13 = 5'hd == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__14 = 5'he == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__15 = 5'hf == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__16 = 5'h10 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__17 = 5'h11 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__18 = 5'h12 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__19 = 5'h13 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__20 = 5'h14 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__21 = 5'h15 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__22 = 5'h16 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__23 = 5'h17 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__24 = 5'h18 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__25 = 5'h19 == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__26 = 5'h1a == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__27 = 5'h1b == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__28 = 5'h1c == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__29 = 5'h1d == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__30 = 5'h1e == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value__31 = 5'h1f == data_io_in_bits_wdata_idx_24 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_0 = data_io_in_bits_wdata_dataout_24_value__0 |
- data_io_in_bits_wdata_dataout_24_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_1 = data_io_in_bits_wdata_dataout_24_value__2 |
- data_io_in_bits_wdata_dataout_24_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_2 = data_io_in_bits_wdata_dataout_24_value__4 |
- data_io_in_bits_wdata_dataout_24_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_3 = data_io_in_bits_wdata_dataout_24_value__6 |
- data_io_in_bits_wdata_dataout_24_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_4 = data_io_in_bits_wdata_dataout_24_value__8 |
- data_io_in_bits_wdata_dataout_24_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_5 = data_io_in_bits_wdata_dataout_24_value__10 |
- data_io_in_bits_wdata_dataout_24_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_6 = data_io_in_bits_wdata_dataout_24_value__12 |
- data_io_in_bits_wdata_dataout_24_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_7 = data_io_in_bits_wdata_dataout_24_value__14 |
- data_io_in_bits_wdata_dataout_24_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_8 = data_io_in_bits_wdata_dataout_24_value__16 |
- data_io_in_bits_wdata_dataout_24_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_9 = data_io_in_bits_wdata_dataout_24_value__18 |
- data_io_in_bits_wdata_dataout_24_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_10 = data_io_in_bits_wdata_dataout_24_value__20 |
- data_io_in_bits_wdata_dataout_24_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_11 = data_io_in_bits_wdata_dataout_24_value__22 |
- data_io_in_bits_wdata_dataout_24_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_12 = data_io_in_bits_wdata_dataout_24_value__24 |
- data_io_in_bits_wdata_dataout_24_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_13 = data_io_in_bits_wdata_dataout_24_value__26 |
- data_io_in_bits_wdata_dataout_24_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_14 = data_io_in_bits_wdata_dataout_24_value__28 |
- data_io_in_bits_wdata_dataout_24_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_1_15 = data_io_in_bits_wdata_dataout_24_value__30 |
- data_io_in_bits_wdata_dataout_24_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_2_0 = data_io_in_bits_wdata_dataout_24_value_1_0 |
- data_io_in_bits_wdata_dataout_24_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_2_1 = data_io_in_bits_wdata_dataout_24_value_1_2 |
- data_io_in_bits_wdata_dataout_24_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_2_2 = data_io_in_bits_wdata_dataout_24_value_1_4 |
- data_io_in_bits_wdata_dataout_24_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_2_3 = data_io_in_bits_wdata_dataout_24_value_1_6 |
- data_io_in_bits_wdata_dataout_24_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_2_4 = data_io_in_bits_wdata_dataout_24_value_1_8 |
- data_io_in_bits_wdata_dataout_24_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_2_5 = data_io_in_bits_wdata_dataout_24_value_1_10 |
- data_io_in_bits_wdata_dataout_24_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_2_6 = data_io_in_bits_wdata_dataout_24_value_1_12 |
- data_io_in_bits_wdata_dataout_24_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_2_7 = data_io_in_bits_wdata_dataout_24_value_1_14 |
- data_io_in_bits_wdata_dataout_24_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_3_0 = data_io_in_bits_wdata_dataout_24_value_2_0 |
- data_io_in_bits_wdata_dataout_24_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_3_1 = data_io_in_bits_wdata_dataout_24_value_2_2 |
- data_io_in_bits_wdata_dataout_24_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_3_2 = data_io_in_bits_wdata_dataout_24_value_2_4 |
- data_io_in_bits_wdata_dataout_24_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_3_3 = data_io_in_bits_wdata_dataout_24_value_2_6 |
- data_io_in_bits_wdata_dataout_24_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_4_0 = data_io_in_bits_wdata_dataout_24_value_3_0 |
- data_io_in_bits_wdata_dataout_24_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_4_1 = data_io_in_bits_wdata_dataout_24_value_3_2 |
- data_io_in_bits_wdata_dataout_24_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_24_value_5_0 = data_io_in_bits_wdata_dataout_24_value_4_0 |
- data_io_in_bits_wdata_dataout_24_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_25 = 5'h19 - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__0 = 5'h0 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__1 = 5'h1 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__2 = 5'h2 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__3 = 5'h3 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__4 = 5'h4 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__5 = 5'h5 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__6 = 5'h6 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__7 = 5'h7 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__8 = 5'h8 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__9 = 5'h9 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__10 = 5'ha == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__11 = 5'hb == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__12 = 5'hc == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__13 = 5'hd == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__14 = 5'he == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__15 = 5'hf == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__16 = 5'h10 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__17 = 5'h11 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__18 = 5'h12 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__19 = 5'h13 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__20 = 5'h14 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__21 = 5'h15 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__22 = 5'h16 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__23 = 5'h17 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__24 = 5'h18 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__25 = 5'h19 == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__26 = 5'h1a == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__27 = 5'h1b == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__28 = 5'h1c == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__29 = 5'h1d == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__30 = 5'h1e == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value__31 = 5'h1f == data_io_in_bits_wdata_idx_25 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_0 = data_io_in_bits_wdata_dataout_25_value__0 |
- data_io_in_bits_wdata_dataout_25_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_1 = data_io_in_bits_wdata_dataout_25_value__2 |
- data_io_in_bits_wdata_dataout_25_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_2 = data_io_in_bits_wdata_dataout_25_value__4 |
- data_io_in_bits_wdata_dataout_25_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_3 = data_io_in_bits_wdata_dataout_25_value__6 |
- data_io_in_bits_wdata_dataout_25_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_4 = data_io_in_bits_wdata_dataout_25_value__8 |
- data_io_in_bits_wdata_dataout_25_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_5 = data_io_in_bits_wdata_dataout_25_value__10 |
- data_io_in_bits_wdata_dataout_25_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_6 = data_io_in_bits_wdata_dataout_25_value__12 |
- data_io_in_bits_wdata_dataout_25_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_7 = data_io_in_bits_wdata_dataout_25_value__14 |
- data_io_in_bits_wdata_dataout_25_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_8 = data_io_in_bits_wdata_dataout_25_value__16 |
- data_io_in_bits_wdata_dataout_25_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_9 = data_io_in_bits_wdata_dataout_25_value__18 |
- data_io_in_bits_wdata_dataout_25_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_10 = data_io_in_bits_wdata_dataout_25_value__20 |
- data_io_in_bits_wdata_dataout_25_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_11 = data_io_in_bits_wdata_dataout_25_value__22 |
- data_io_in_bits_wdata_dataout_25_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_12 = data_io_in_bits_wdata_dataout_25_value__24 |
- data_io_in_bits_wdata_dataout_25_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_13 = data_io_in_bits_wdata_dataout_25_value__26 |
- data_io_in_bits_wdata_dataout_25_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_14 = data_io_in_bits_wdata_dataout_25_value__28 |
- data_io_in_bits_wdata_dataout_25_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_1_15 = data_io_in_bits_wdata_dataout_25_value__30 |
- data_io_in_bits_wdata_dataout_25_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_2_0 = data_io_in_bits_wdata_dataout_25_value_1_0 |
- data_io_in_bits_wdata_dataout_25_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_2_1 = data_io_in_bits_wdata_dataout_25_value_1_2 |
- data_io_in_bits_wdata_dataout_25_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_2_2 = data_io_in_bits_wdata_dataout_25_value_1_4 |
- data_io_in_bits_wdata_dataout_25_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_2_3 = data_io_in_bits_wdata_dataout_25_value_1_6 |
- data_io_in_bits_wdata_dataout_25_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_2_4 = data_io_in_bits_wdata_dataout_25_value_1_8 |
- data_io_in_bits_wdata_dataout_25_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_2_5 = data_io_in_bits_wdata_dataout_25_value_1_10 |
- data_io_in_bits_wdata_dataout_25_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_2_6 = data_io_in_bits_wdata_dataout_25_value_1_12 |
- data_io_in_bits_wdata_dataout_25_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_2_7 = data_io_in_bits_wdata_dataout_25_value_1_14 |
- data_io_in_bits_wdata_dataout_25_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_3_0 = data_io_in_bits_wdata_dataout_25_value_2_0 |
- data_io_in_bits_wdata_dataout_25_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_3_1 = data_io_in_bits_wdata_dataout_25_value_2_2 |
- data_io_in_bits_wdata_dataout_25_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_3_2 = data_io_in_bits_wdata_dataout_25_value_2_4 |
- data_io_in_bits_wdata_dataout_25_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_3_3 = data_io_in_bits_wdata_dataout_25_value_2_6 |
- data_io_in_bits_wdata_dataout_25_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_4_0 = data_io_in_bits_wdata_dataout_25_value_3_0 |
- data_io_in_bits_wdata_dataout_25_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_4_1 = data_io_in_bits_wdata_dataout_25_value_3_2 |
- data_io_in_bits_wdata_dataout_25_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_25_value_5_0 = data_io_in_bits_wdata_dataout_25_value_4_0 |
- data_io_in_bits_wdata_dataout_25_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_26 = 5'h1a - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__0 = 5'h0 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__1 = 5'h1 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__2 = 5'h2 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__3 = 5'h3 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__4 = 5'h4 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__5 = 5'h5 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__6 = 5'h6 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__7 = 5'h7 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__8 = 5'h8 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__9 = 5'h9 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__10 = 5'ha == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__11 = 5'hb == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__12 = 5'hc == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__13 = 5'hd == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__14 = 5'he == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__15 = 5'hf == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__16 = 5'h10 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__17 = 5'h11 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__18 = 5'h12 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__19 = 5'h13 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__20 = 5'h14 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__21 = 5'h15 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__22 = 5'h16 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__23 = 5'h17 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__24 = 5'h18 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__25 = 5'h19 == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__26 = 5'h1a == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__27 = 5'h1b == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__28 = 5'h1c == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__29 = 5'h1d == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__30 = 5'h1e == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value__31 = 5'h1f == data_io_in_bits_wdata_idx_26 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_0 = data_io_in_bits_wdata_dataout_26_value__0 |
- data_io_in_bits_wdata_dataout_26_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_1 = data_io_in_bits_wdata_dataout_26_value__2 |
- data_io_in_bits_wdata_dataout_26_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_2 = data_io_in_bits_wdata_dataout_26_value__4 |
- data_io_in_bits_wdata_dataout_26_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_3 = data_io_in_bits_wdata_dataout_26_value__6 |
- data_io_in_bits_wdata_dataout_26_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_4 = data_io_in_bits_wdata_dataout_26_value__8 |
- data_io_in_bits_wdata_dataout_26_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_5 = data_io_in_bits_wdata_dataout_26_value__10 |
- data_io_in_bits_wdata_dataout_26_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_6 = data_io_in_bits_wdata_dataout_26_value__12 |
- data_io_in_bits_wdata_dataout_26_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_7 = data_io_in_bits_wdata_dataout_26_value__14 |
- data_io_in_bits_wdata_dataout_26_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_8 = data_io_in_bits_wdata_dataout_26_value__16 |
- data_io_in_bits_wdata_dataout_26_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_9 = data_io_in_bits_wdata_dataout_26_value__18 |
- data_io_in_bits_wdata_dataout_26_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_10 = data_io_in_bits_wdata_dataout_26_value__20 |
- data_io_in_bits_wdata_dataout_26_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_11 = data_io_in_bits_wdata_dataout_26_value__22 |
- data_io_in_bits_wdata_dataout_26_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_12 = data_io_in_bits_wdata_dataout_26_value__24 |
- data_io_in_bits_wdata_dataout_26_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_13 = data_io_in_bits_wdata_dataout_26_value__26 |
- data_io_in_bits_wdata_dataout_26_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_14 = data_io_in_bits_wdata_dataout_26_value__28 |
- data_io_in_bits_wdata_dataout_26_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_1_15 = data_io_in_bits_wdata_dataout_26_value__30 |
- data_io_in_bits_wdata_dataout_26_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_2_0 = data_io_in_bits_wdata_dataout_26_value_1_0 |
- data_io_in_bits_wdata_dataout_26_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_2_1 = data_io_in_bits_wdata_dataout_26_value_1_2 |
- data_io_in_bits_wdata_dataout_26_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_2_2 = data_io_in_bits_wdata_dataout_26_value_1_4 |
- data_io_in_bits_wdata_dataout_26_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_2_3 = data_io_in_bits_wdata_dataout_26_value_1_6 |
- data_io_in_bits_wdata_dataout_26_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_2_4 = data_io_in_bits_wdata_dataout_26_value_1_8 |
- data_io_in_bits_wdata_dataout_26_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_2_5 = data_io_in_bits_wdata_dataout_26_value_1_10 |
- data_io_in_bits_wdata_dataout_26_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_2_6 = data_io_in_bits_wdata_dataout_26_value_1_12 |
- data_io_in_bits_wdata_dataout_26_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_2_7 = data_io_in_bits_wdata_dataout_26_value_1_14 |
- data_io_in_bits_wdata_dataout_26_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_3_0 = data_io_in_bits_wdata_dataout_26_value_2_0 |
- data_io_in_bits_wdata_dataout_26_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_3_1 = data_io_in_bits_wdata_dataout_26_value_2_2 |
- data_io_in_bits_wdata_dataout_26_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_3_2 = data_io_in_bits_wdata_dataout_26_value_2_4 |
- data_io_in_bits_wdata_dataout_26_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_3_3 = data_io_in_bits_wdata_dataout_26_value_2_6 |
- data_io_in_bits_wdata_dataout_26_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_4_0 = data_io_in_bits_wdata_dataout_26_value_3_0 |
- data_io_in_bits_wdata_dataout_26_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_4_1 = data_io_in_bits_wdata_dataout_26_value_3_2 |
- data_io_in_bits_wdata_dataout_26_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_26_value_5_0 = data_io_in_bits_wdata_dataout_26_value_4_0 |
- data_io_in_bits_wdata_dataout_26_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_27 = 5'h1b - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__0 = 5'h0 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__1 = 5'h1 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__2 = 5'h2 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__3 = 5'h3 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__4 = 5'h4 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__5 = 5'h5 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__6 = 5'h6 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__7 = 5'h7 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__8 = 5'h8 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__9 = 5'h9 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__10 = 5'ha == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__11 = 5'hb == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__12 = 5'hc == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__13 = 5'hd == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__14 = 5'he == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__15 = 5'hf == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__16 = 5'h10 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__17 = 5'h11 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__18 = 5'h12 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__19 = 5'h13 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__20 = 5'h14 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__21 = 5'h15 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__22 = 5'h16 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__23 = 5'h17 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__24 = 5'h18 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__25 = 5'h19 == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__26 = 5'h1a == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__27 = 5'h1b == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__28 = 5'h1c == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__29 = 5'h1d == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__30 = 5'h1e == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value__31 = 5'h1f == data_io_in_bits_wdata_idx_27 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_0 = data_io_in_bits_wdata_dataout_27_value__0 |
- data_io_in_bits_wdata_dataout_27_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_1 = data_io_in_bits_wdata_dataout_27_value__2 |
- data_io_in_bits_wdata_dataout_27_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_2 = data_io_in_bits_wdata_dataout_27_value__4 |
- data_io_in_bits_wdata_dataout_27_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_3 = data_io_in_bits_wdata_dataout_27_value__6 |
- data_io_in_bits_wdata_dataout_27_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_4 = data_io_in_bits_wdata_dataout_27_value__8 |
- data_io_in_bits_wdata_dataout_27_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_5 = data_io_in_bits_wdata_dataout_27_value__10 |
- data_io_in_bits_wdata_dataout_27_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_6 = data_io_in_bits_wdata_dataout_27_value__12 |
- data_io_in_bits_wdata_dataout_27_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_7 = data_io_in_bits_wdata_dataout_27_value__14 |
- data_io_in_bits_wdata_dataout_27_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_8 = data_io_in_bits_wdata_dataout_27_value__16 |
- data_io_in_bits_wdata_dataout_27_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_9 = data_io_in_bits_wdata_dataout_27_value__18 |
- data_io_in_bits_wdata_dataout_27_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_10 = data_io_in_bits_wdata_dataout_27_value__20 |
- data_io_in_bits_wdata_dataout_27_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_11 = data_io_in_bits_wdata_dataout_27_value__22 |
- data_io_in_bits_wdata_dataout_27_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_12 = data_io_in_bits_wdata_dataout_27_value__24 |
- data_io_in_bits_wdata_dataout_27_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_13 = data_io_in_bits_wdata_dataout_27_value__26 |
- data_io_in_bits_wdata_dataout_27_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_14 = data_io_in_bits_wdata_dataout_27_value__28 |
- data_io_in_bits_wdata_dataout_27_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_1_15 = data_io_in_bits_wdata_dataout_27_value__30 |
- data_io_in_bits_wdata_dataout_27_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_2_0 = data_io_in_bits_wdata_dataout_27_value_1_0 |
- data_io_in_bits_wdata_dataout_27_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_2_1 = data_io_in_bits_wdata_dataout_27_value_1_2 |
- data_io_in_bits_wdata_dataout_27_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_2_2 = data_io_in_bits_wdata_dataout_27_value_1_4 |
- data_io_in_bits_wdata_dataout_27_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_2_3 = data_io_in_bits_wdata_dataout_27_value_1_6 |
- data_io_in_bits_wdata_dataout_27_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_2_4 = data_io_in_bits_wdata_dataout_27_value_1_8 |
- data_io_in_bits_wdata_dataout_27_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_2_5 = data_io_in_bits_wdata_dataout_27_value_1_10 |
- data_io_in_bits_wdata_dataout_27_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_2_6 = data_io_in_bits_wdata_dataout_27_value_1_12 |
- data_io_in_bits_wdata_dataout_27_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_2_7 = data_io_in_bits_wdata_dataout_27_value_1_14 |
- data_io_in_bits_wdata_dataout_27_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_3_0 = data_io_in_bits_wdata_dataout_27_value_2_0 |
- data_io_in_bits_wdata_dataout_27_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_3_1 = data_io_in_bits_wdata_dataout_27_value_2_2 |
- data_io_in_bits_wdata_dataout_27_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_3_2 = data_io_in_bits_wdata_dataout_27_value_2_4 |
- data_io_in_bits_wdata_dataout_27_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_3_3 = data_io_in_bits_wdata_dataout_27_value_2_6 |
- data_io_in_bits_wdata_dataout_27_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_4_0 = data_io_in_bits_wdata_dataout_27_value_3_0 |
- data_io_in_bits_wdata_dataout_27_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_4_1 = data_io_in_bits_wdata_dataout_27_value_3_2 |
- data_io_in_bits_wdata_dataout_27_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_27_value_5_0 = data_io_in_bits_wdata_dataout_27_value_4_0 |
- data_io_in_bits_wdata_dataout_27_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_28 = 5'h1c - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__0 = 5'h0 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__1 = 5'h1 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__2 = 5'h2 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__3 = 5'h3 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__4 = 5'h4 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__5 = 5'h5 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__6 = 5'h6 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__7 = 5'h7 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__8 = 5'h8 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__9 = 5'h9 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__10 = 5'ha == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__11 = 5'hb == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__12 = 5'hc == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__13 = 5'hd == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__14 = 5'he == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__15 = 5'hf == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__16 = 5'h10 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__17 = 5'h11 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__18 = 5'h12 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__19 = 5'h13 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__20 = 5'h14 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__21 = 5'h15 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__22 = 5'h16 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__23 = 5'h17 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__24 = 5'h18 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__25 = 5'h19 == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__26 = 5'h1a == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__27 = 5'h1b == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__28 = 5'h1c == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__29 = 5'h1d == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__30 = 5'h1e == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value__31 = 5'h1f == data_io_in_bits_wdata_idx_28 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_0 = data_io_in_bits_wdata_dataout_28_value__0 |
- data_io_in_bits_wdata_dataout_28_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_1 = data_io_in_bits_wdata_dataout_28_value__2 |
- data_io_in_bits_wdata_dataout_28_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_2 = data_io_in_bits_wdata_dataout_28_value__4 |
- data_io_in_bits_wdata_dataout_28_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_3 = data_io_in_bits_wdata_dataout_28_value__6 |
- data_io_in_bits_wdata_dataout_28_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_4 = data_io_in_bits_wdata_dataout_28_value__8 |
- data_io_in_bits_wdata_dataout_28_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_5 = data_io_in_bits_wdata_dataout_28_value__10 |
- data_io_in_bits_wdata_dataout_28_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_6 = data_io_in_bits_wdata_dataout_28_value__12 |
- data_io_in_bits_wdata_dataout_28_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_7 = data_io_in_bits_wdata_dataout_28_value__14 |
- data_io_in_bits_wdata_dataout_28_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_8 = data_io_in_bits_wdata_dataout_28_value__16 |
- data_io_in_bits_wdata_dataout_28_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_9 = data_io_in_bits_wdata_dataout_28_value__18 |
- data_io_in_bits_wdata_dataout_28_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_10 = data_io_in_bits_wdata_dataout_28_value__20 |
- data_io_in_bits_wdata_dataout_28_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_11 = data_io_in_bits_wdata_dataout_28_value__22 |
- data_io_in_bits_wdata_dataout_28_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_12 = data_io_in_bits_wdata_dataout_28_value__24 |
- data_io_in_bits_wdata_dataout_28_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_13 = data_io_in_bits_wdata_dataout_28_value__26 |
- data_io_in_bits_wdata_dataout_28_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_14 = data_io_in_bits_wdata_dataout_28_value__28 |
- data_io_in_bits_wdata_dataout_28_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_1_15 = data_io_in_bits_wdata_dataout_28_value__30 |
- data_io_in_bits_wdata_dataout_28_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_2_0 = data_io_in_bits_wdata_dataout_28_value_1_0 |
- data_io_in_bits_wdata_dataout_28_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_2_1 = data_io_in_bits_wdata_dataout_28_value_1_2 |
- data_io_in_bits_wdata_dataout_28_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_2_2 = data_io_in_bits_wdata_dataout_28_value_1_4 |
- data_io_in_bits_wdata_dataout_28_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_2_3 = data_io_in_bits_wdata_dataout_28_value_1_6 |
- data_io_in_bits_wdata_dataout_28_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_2_4 = data_io_in_bits_wdata_dataout_28_value_1_8 |
- data_io_in_bits_wdata_dataout_28_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_2_5 = data_io_in_bits_wdata_dataout_28_value_1_10 |
- data_io_in_bits_wdata_dataout_28_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_2_6 = data_io_in_bits_wdata_dataout_28_value_1_12 |
- data_io_in_bits_wdata_dataout_28_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_2_7 = data_io_in_bits_wdata_dataout_28_value_1_14 |
- data_io_in_bits_wdata_dataout_28_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_3_0 = data_io_in_bits_wdata_dataout_28_value_2_0 |
- data_io_in_bits_wdata_dataout_28_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_3_1 = data_io_in_bits_wdata_dataout_28_value_2_2 |
- data_io_in_bits_wdata_dataout_28_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_3_2 = data_io_in_bits_wdata_dataout_28_value_2_4 |
- data_io_in_bits_wdata_dataout_28_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_3_3 = data_io_in_bits_wdata_dataout_28_value_2_6 |
- data_io_in_bits_wdata_dataout_28_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_4_0 = data_io_in_bits_wdata_dataout_28_value_3_0 |
- data_io_in_bits_wdata_dataout_28_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_4_1 = data_io_in_bits_wdata_dataout_28_value_3_2 |
- data_io_in_bits_wdata_dataout_28_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_28_value_5_0 = data_io_in_bits_wdata_dataout_28_value_4_0 |
- data_io_in_bits_wdata_dataout_28_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_29 = 5'h1d - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__0 = 5'h0 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__1 = 5'h1 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__2 = 5'h2 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__3 = 5'h3 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__4 = 5'h4 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__5 = 5'h5 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__6 = 5'h6 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__7 = 5'h7 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__8 = 5'h8 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__9 = 5'h9 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__10 = 5'ha == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__11 = 5'hb == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__12 = 5'hc == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__13 = 5'hd == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__14 = 5'he == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__15 = 5'hf == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__16 = 5'h10 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__17 = 5'h11 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__18 = 5'h12 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__19 = 5'h13 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__20 = 5'h14 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__21 = 5'h15 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__22 = 5'h16 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__23 = 5'h17 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__24 = 5'h18 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__25 = 5'h19 == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__26 = 5'h1a == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__27 = 5'h1b == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__28 = 5'h1c == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__29 = 5'h1d == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__30 = 5'h1e == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value__31 = 5'h1f == data_io_in_bits_wdata_idx_29 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_0 = data_io_in_bits_wdata_dataout_29_value__0 |
- data_io_in_bits_wdata_dataout_29_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_1 = data_io_in_bits_wdata_dataout_29_value__2 |
- data_io_in_bits_wdata_dataout_29_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_2 = data_io_in_bits_wdata_dataout_29_value__4 |
- data_io_in_bits_wdata_dataout_29_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_3 = data_io_in_bits_wdata_dataout_29_value__6 |
- data_io_in_bits_wdata_dataout_29_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_4 = data_io_in_bits_wdata_dataout_29_value__8 |
- data_io_in_bits_wdata_dataout_29_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_5 = data_io_in_bits_wdata_dataout_29_value__10 |
- data_io_in_bits_wdata_dataout_29_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_6 = data_io_in_bits_wdata_dataout_29_value__12 |
- data_io_in_bits_wdata_dataout_29_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_7 = data_io_in_bits_wdata_dataout_29_value__14 |
- data_io_in_bits_wdata_dataout_29_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_8 = data_io_in_bits_wdata_dataout_29_value__16 |
- data_io_in_bits_wdata_dataout_29_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_9 = data_io_in_bits_wdata_dataout_29_value__18 |
- data_io_in_bits_wdata_dataout_29_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_10 = data_io_in_bits_wdata_dataout_29_value__20 |
- data_io_in_bits_wdata_dataout_29_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_11 = data_io_in_bits_wdata_dataout_29_value__22 |
- data_io_in_bits_wdata_dataout_29_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_12 = data_io_in_bits_wdata_dataout_29_value__24 |
- data_io_in_bits_wdata_dataout_29_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_13 = data_io_in_bits_wdata_dataout_29_value__26 |
- data_io_in_bits_wdata_dataout_29_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_14 = data_io_in_bits_wdata_dataout_29_value__28 |
- data_io_in_bits_wdata_dataout_29_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_1_15 = data_io_in_bits_wdata_dataout_29_value__30 |
- data_io_in_bits_wdata_dataout_29_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_2_0 = data_io_in_bits_wdata_dataout_29_value_1_0 |
- data_io_in_bits_wdata_dataout_29_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_2_1 = data_io_in_bits_wdata_dataout_29_value_1_2 |
- data_io_in_bits_wdata_dataout_29_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_2_2 = data_io_in_bits_wdata_dataout_29_value_1_4 |
- data_io_in_bits_wdata_dataout_29_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_2_3 = data_io_in_bits_wdata_dataout_29_value_1_6 |
- data_io_in_bits_wdata_dataout_29_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_2_4 = data_io_in_bits_wdata_dataout_29_value_1_8 |
- data_io_in_bits_wdata_dataout_29_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_2_5 = data_io_in_bits_wdata_dataout_29_value_1_10 |
- data_io_in_bits_wdata_dataout_29_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_2_6 = data_io_in_bits_wdata_dataout_29_value_1_12 |
- data_io_in_bits_wdata_dataout_29_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_2_7 = data_io_in_bits_wdata_dataout_29_value_1_14 |
- data_io_in_bits_wdata_dataout_29_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_3_0 = data_io_in_bits_wdata_dataout_29_value_2_0 |
- data_io_in_bits_wdata_dataout_29_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_3_1 = data_io_in_bits_wdata_dataout_29_value_2_2 |
- data_io_in_bits_wdata_dataout_29_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_3_2 = data_io_in_bits_wdata_dataout_29_value_2_4 |
- data_io_in_bits_wdata_dataout_29_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_3_3 = data_io_in_bits_wdata_dataout_29_value_2_6 |
- data_io_in_bits_wdata_dataout_29_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_4_0 = data_io_in_bits_wdata_dataout_29_value_3_0 |
- data_io_in_bits_wdata_dataout_29_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_4_1 = data_io_in_bits_wdata_dataout_29_value_3_2 |
- data_io_in_bits_wdata_dataout_29_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_29_value_5_0 = data_io_in_bits_wdata_dataout_29_value_4_0 |
- data_io_in_bits_wdata_dataout_29_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_30 = 5'h1e - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__0 = 5'h0 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__1 = 5'h1 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__2 = 5'h2 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__3 = 5'h3 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__4 = 5'h4 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__5 = 5'h5 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__6 = 5'h6 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__7 = 5'h7 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__8 = 5'h8 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__9 = 5'h9 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__10 = 5'ha == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__11 = 5'hb == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__12 = 5'hc == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__13 = 5'hd == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__14 = 5'he == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__15 = 5'hf == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__16 = 5'h10 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__17 = 5'h11 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__18 = 5'h12 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__19 = 5'h13 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__20 = 5'h14 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__21 = 5'h15 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__22 = 5'h16 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__23 = 5'h17 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__24 = 5'h18 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__25 = 5'h19 == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__26 = 5'h1a == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__27 = 5'h1b == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__28 = 5'h1c == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__29 = 5'h1d == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__30 = 5'h1e == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value__31 = 5'h1f == data_io_in_bits_wdata_idx_30 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_0 = data_io_in_bits_wdata_dataout_30_value__0 |
- data_io_in_bits_wdata_dataout_30_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_1 = data_io_in_bits_wdata_dataout_30_value__2 |
- data_io_in_bits_wdata_dataout_30_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_2 = data_io_in_bits_wdata_dataout_30_value__4 |
- data_io_in_bits_wdata_dataout_30_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_3 = data_io_in_bits_wdata_dataout_30_value__6 |
- data_io_in_bits_wdata_dataout_30_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_4 = data_io_in_bits_wdata_dataout_30_value__8 |
- data_io_in_bits_wdata_dataout_30_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_5 = data_io_in_bits_wdata_dataout_30_value__10 |
- data_io_in_bits_wdata_dataout_30_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_6 = data_io_in_bits_wdata_dataout_30_value__12 |
- data_io_in_bits_wdata_dataout_30_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_7 = data_io_in_bits_wdata_dataout_30_value__14 |
- data_io_in_bits_wdata_dataout_30_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_8 = data_io_in_bits_wdata_dataout_30_value__16 |
- data_io_in_bits_wdata_dataout_30_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_9 = data_io_in_bits_wdata_dataout_30_value__18 |
- data_io_in_bits_wdata_dataout_30_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_10 = data_io_in_bits_wdata_dataout_30_value__20 |
- data_io_in_bits_wdata_dataout_30_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_11 = data_io_in_bits_wdata_dataout_30_value__22 |
- data_io_in_bits_wdata_dataout_30_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_12 = data_io_in_bits_wdata_dataout_30_value__24 |
- data_io_in_bits_wdata_dataout_30_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_13 = data_io_in_bits_wdata_dataout_30_value__26 |
- data_io_in_bits_wdata_dataout_30_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_14 = data_io_in_bits_wdata_dataout_30_value__28 |
- data_io_in_bits_wdata_dataout_30_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_1_15 = data_io_in_bits_wdata_dataout_30_value__30 |
- data_io_in_bits_wdata_dataout_30_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_2_0 = data_io_in_bits_wdata_dataout_30_value_1_0 |
- data_io_in_bits_wdata_dataout_30_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_2_1 = data_io_in_bits_wdata_dataout_30_value_1_2 |
- data_io_in_bits_wdata_dataout_30_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_2_2 = data_io_in_bits_wdata_dataout_30_value_1_4 |
- data_io_in_bits_wdata_dataout_30_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_2_3 = data_io_in_bits_wdata_dataout_30_value_1_6 |
- data_io_in_bits_wdata_dataout_30_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_2_4 = data_io_in_bits_wdata_dataout_30_value_1_8 |
- data_io_in_bits_wdata_dataout_30_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_2_5 = data_io_in_bits_wdata_dataout_30_value_1_10 |
- data_io_in_bits_wdata_dataout_30_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_2_6 = data_io_in_bits_wdata_dataout_30_value_1_12 |
- data_io_in_bits_wdata_dataout_30_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_2_7 = data_io_in_bits_wdata_dataout_30_value_1_14 |
- data_io_in_bits_wdata_dataout_30_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_3_0 = data_io_in_bits_wdata_dataout_30_value_2_0 |
- data_io_in_bits_wdata_dataout_30_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_3_1 = data_io_in_bits_wdata_dataout_30_value_2_2 |
- data_io_in_bits_wdata_dataout_30_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_3_2 = data_io_in_bits_wdata_dataout_30_value_2_4 |
- data_io_in_bits_wdata_dataout_30_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_3_3 = data_io_in_bits_wdata_dataout_30_value_2_6 |
- data_io_in_bits_wdata_dataout_30_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_4_0 = data_io_in_bits_wdata_dataout_30_value_3_0 |
- data_io_in_bits_wdata_dataout_30_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_4_1 = data_io_in_bits_wdata_dataout_30_value_3_2 |
- data_io_in_bits_wdata_dataout_30_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_30_value_5_0 = data_io_in_bits_wdata_dataout_30_value_4_0 |
- data_io_in_bits_wdata_dataout_30_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wdata_idx_31 = 5'h1f - rdataAshf; // @[VLdSt.scala 71:52]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__0 = 5'h0 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__1 = 5'h1 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__2 = 5'h2 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__3 = 5'h3 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__4 = 5'h4 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__5 = 5'h5 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__6 = 5'h6 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__7 = 5'h7 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__8 = 5'h8 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__9 = 5'h9 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__10 = 5'ha == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__11 = 5'hb == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__12 = 5'hc == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__13 = 5'hd == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__14 = 5'he == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__15 = 5'hf == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__16 = 5'h10 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__17 = 5'h11 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__18 = 5'h12 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__19 = 5'h13 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__20 = 5'h14 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__21 = 5'h15 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__22 = 5'h16 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__23 = 5'h17 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__24 = 5'h18 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__25 = 5'h19 == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__26 = 5'h1a == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__27 = 5'h1b == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__28 = 5'h1c == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__29 = 5'h1d == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__30 = 5'h1e == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value__31 = 5'h1f == data_io_in_bits_wdata_idx_31 ?
- data_io_in_bits_wdata_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_0 = data_io_in_bits_wdata_dataout_31_value__0 |
- data_io_in_bits_wdata_dataout_31_value__1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_1 = data_io_in_bits_wdata_dataout_31_value__2 |
- data_io_in_bits_wdata_dataout_31_value__3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_2 = data_io_in_bits_wdata_dataout_31_value__4 |
- data_io_in_bits_wdata_dataout_31_value__5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_3 = data_io_in_bits_wdata_dataout_31_value__6 |
- data_io_in_bits_wdata_dataout_31_value__7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_4 = data_io_in_bits_wdata_dataout_31_value__8 |
- data_io_in_bits_wdata_dataout_31_value__9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_5 = data_io_in_bits_wdata_dataout_31_value__10 |
- data_io_in_bits_wdata_dataout_31_value__11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_6 = data_io_in_bits_wdata_dataout_31_value__12 |
- data_io_in_bits_wdata_dataout_31_value__13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_7 = data_io_in_bits_wdata_dataout_31_value__14 |
- data_io_in_bits_wdata_dataout_31_value__15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_8 = data_io_in_bits_wdata_dataout_31_value__16 |
- data_io_in_bits_wdata_dataout_31_value__17; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_9 = data_io_in_bits_wdata_dataout_31_value__18 |
- data_io_in_bits_wdata_dataout_31_value__19; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_10 = data_io_in_bits_wdata_dataout_31_value__20 |
- data_io_in_bits_wdata_dataout_31_value__21; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_11 = data_io_in_bits_wdata_dataout_31_value__22 |
- data_io_in_bits_wdata_dataout_31_value__23; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_12 = data_io_in_bits_wdata_dataout_31_value__24 |
- data_io_in_bits_wdata_dataout_31_value__25; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_13 = data_io_in_bits_wdata_dataout_31_value__26 |
- data_io_in_bits_wdata_dataout_31_value__27; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_14 = data_io_in_bits_wdata_dataout_31_value__28 |
- data_io_in_bits_wdata_dataout_31_value__29; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_1_15 = data_io_in_bits_wdata_dataout_31_value__30 |
- data_io_in_bits_wdata_dataout_31_value__31; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_2_0 = data_io_in_bits_wdata_dataout_31_value_1_0 |
- data_io_in_bits_wdata_dataout_31_value_1_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_2_1 = data_io_in_bits_wdata_dataout_31_value_1_2 |
- data_io_in_bits_wdata_dataout_31_value_1_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_2_2 = data_io_in_bits_wdata_dataout_31_value_1_4 |
- data_io_in_bits_wdata_dataout_31_value_1_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_2_3 = data_io_in_bits_wdata_dataout_31_value_1_6 |
- data_io_in_bits_wdata_dataout_31_value_1_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_2_4 = data_io_in_bits_wdata_dataout_31_value_1_8 |
- data_io_in_bits_wdata_dataout_31_value_1_9; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_2_5 = data_io_in_bits_wdata_dataout_31_value_1_10 |
- data_io_in_bits_wdata_dataout_31_value_1_11; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_2_6 = data_io_in_bits_wdata_dataout_31_value_1_12 |
- data_io_in_bits_wdata_dataout_31_value_1_13; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_2_7 = data_io_in_bits_wdata_dataout_31_value_1_14 |
- data_io_in_bits_wdata_dataout_31_value_1_15; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_3_0 = data_io_in_bits_wdata_dataout_31_value_2_0 |
- data_io_in_bits_wdata_dataout_31_value_2_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_3_1 = data_io_in_bits_wdata_dataout_31_value_2_2 |
- data_io_in_bits_wdata_dataout_31_value_2_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_3_2 = data_io_in_bits_wdata_dataout_31_value_2_4 |
- data_io_in_bits_wdata_dataout_31_value_2_5; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_3_3 = data_io_in_bits_wdata_dataout_31_value_2_6 |
- data_io_in_bits_wdata_dataout_31_value_2_7; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_4_0 = data_io_in_bits_wdata_dataout_31_value_3_0 |
- data_io_in_bits_wdata_dataout_31_value_3_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_4_1 = data_io_in_bits_wdata_dataout_31_value_3_2 |
- data_io_in_bits_wdata_dataout_31_value_3_3; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wdata_dataout_31_value_5_0 = data_io_in_bits_wdata_dataout_31_value_4_0 |
- data_io_in_bits_wdata_dataout_31_value_4_1; // @[Library.scala 129:37]
- wire [63:0] data_io_in_bits_wdata_lo_lo = {data_io_in_bits_wdata_dataout_7_value_5_0,
- data_io_in_bits_wdata_dataout_6_value_5_0,data_io_in_bits_wdata_dataout_5_value_5_0,
- data_io_in_bits_wdata_dataout_4_value_5_0,data_io_in_bits_wdata_dataout_3_value_5_0,
- data_io_in_bits_wdata_dataout_2_value_5_0,data_io_in_bits_wdata_dataout_1_value_5_0,
- data_io_in_bits_wdata_dataout_0_value_5_0}; // @[VLdSt.scala 76:13]
- wire [127:0] data_io_in_bits_wdata_lo = {data_io_in_bits_wdata_dataout_15_value_5_0,
- data_io_in_bits_wdata_dataout_14_value_5_0,data_io_in_bits_wdata_dataout_13_value_5_0,
- data_io_in_bits_wdata_dataout_12_value_5_0,data_io_in_bits_wdata_dataout_11_value_5_0,
- data_io_in_bits_wdata_dataout_10_value_5_0,data_io_in_bits_wdata_dataout_9_value_5_0,
- data_io_in_bits_wdata_dataout_8_value_5_0,data_io_in_bits_wdata_lo_lo}; // @[VLdSt.scala 76:13]
- wire [63:0] data_io_in_bits_wdata_hi_lo = {data_io_in_bits_wdata_dataout_23_value_5_0,
- data_io_in_bits_wdata_dataout_22_value_5_0,data_io_in_bits_wdata_dataout_21_value_5_0,
- data_io_in_bits_wdata_dataout_20_value_5_0,data_io_in_bits_wdata_dataout_19_value_5_0,
- data_io_in_bits_wdata_dataout_18_value_5_0,data_io_in_bits_wdata_dataout_17_value_5_0,
- data_io_in_bits_wdata_dataout_16_value_5_0}; // @[VLdSt.scala 76:13]
- wire [127:0] data_io_in_bits_wdata_hi = {data_io_in_bits_wdata_dataout_31_value_5_0,
- data_io_in_bits_wdata_dataout_30_value_5_0,data_io_in_bits_wdata_dataout_29_value_5_0,
- data_io_in_bits_wdata_dataout_28_value_5_0,data_io_in_bits_wdata_dataout_27_value_5_0,
- data_io_in_bits_wdata_dataout_26_value_5_0,data_io_in_bits_wdata_dataout_25_value_5_0,
- data_io_in_bits_wdata_dataout_24_value_5_0,data_io_in_bits_wdata_hi_lo}; // @[VLdSt.scala 76:13]
- wire [7:0] data_io_in_bits_wmask_lo_lo = {rdataWmask_7,rdataWmask_6,rdataWmask_5,rdataWmask_4,rdataWmask_3,
- rdataWmask_2,rdataWmask_1,rdataWmask_0}; // @[VLdSt.scala 258:68]
- wire [15:0] data_io_in_bits_wmask_lo = {rdataWmask_15,rdataWmask_14,rdataWmask_13,rdataWmask_12,rdataWmask_11,
- rdataWmask_10,rdataWmask_9,rdataWmask_8,data_io_in_bits_wmask_lo_lo}; // @[VLdSt.scala 258:68]
- wire [7:0] data_io_in_bits_wmask_hi_lo = {rdataWmask_23,rdataWmask_22,rdataWmask_21,rdataWmask_20,rdataWmask_19,
- rdataWmask_18,rdataWmask_17,rdataWmask_16}; // @[VLdSt.scala 258:68]
- wire [31:0] _data_io_in_bits_wmask_T = {rdataWmask_31,rdataWmask_30,rdataWmask_29,rdataWmask_28,rdataWmask_27,
- rdataWmask_26,rdataWmask_25,rdataWmask_24,data_io_in_bits_wmask_hi_lo,data_io_in_bits_wmask_lo}; // @[VLdSt.scala 258:68]
- wire data_io_in_bits_wmask_datain_0 = _data_io_in_bits_wmask_T[0]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_1 = _data_io_in_bits_wmask_T[1]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_2 = _data_io_in_bits_wmask_T[2]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_3 = _data_io_in_bits_wmask_T[3]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_4 = _data_io_in_bits_wmask_T[4]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_5 = _data_io_in_bits_wmask_T[5]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_6 = _data_io_in_bits_wmask_T[6]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_7 = _data_io_in_bits_wmask_T[7]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_8 = _data_io_in_bits_wmask_T[8]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_9 = _data_io_in_bits_wmask_T[9]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_10 = _data_io_in_bits_wmask_T[10]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_11 = _data_io_in_bits_wmask_T[11]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_12 = _data_io_in_bits_wmask_T[12]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_13 = _data_io_in_bits_wmask_T[13]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_14 = _data_io_in_bits_wmask_T[14]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_15 = _data_io_in_bits_wmask_T[15]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_16 = _data_io_in_bits_wmask_T[16]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_17 = _data_io_in_bits_wmask_T[17]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_18 = _data_io_in_bits_wmask_T[18]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_19 = _data_io_in_bits_wmask_T[19]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_20 = _data_io_in_bits_wmask_T[20]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_21 = _data_io_in_bits_wmask_T[21]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_22 = _data_io_in_bits_wmask_T[22]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_23 = _data_io_in_bits_wmask_T[23]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_24 = _data_io_in_bits_wmask_T[24]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_25 = _data_io_in_bits_wmask_T[25]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_26 = _data_io_in_bits_wmask_T[26]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_27 = _data_io_in_bits_wmask_T[27]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_28 = _data_io_in_bits_wmask_T[28]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_29 = _data_io_in_bits_wmask_T[29]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_30 = _data_io_in_bits_wmask_T[30]; // @[VLdSt.scala 66:24]
- wire data_io_in_bits_wmask_datain_31 = _data_io_in_bits_wmask_T[31]; // @[VLdSt.scala 66:24]
- wire [4:0] data_io_in_bits_wmask_idx = 5'h0 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_0_value__0 = 5'h0 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__1 = 5'h1 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__2 = 5'h2 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__3 = 5'h3 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__4 = 5'h4 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__5 = 5'h5 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__6 = 5'h6 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__7 = 5'h7 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__8 = 5'h8 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__9 = 5'h9 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__10 = 5'ha == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__11 = 5'hb == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__12 = 5'hc == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__13 = 5'hd == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__14 = 5'he == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__15 = 5'hf == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__16 = 5'h10 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_16
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__17 = 5'h11 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_17
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__18 = 5'h12 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_18
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__19 = 5'h13 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_19
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__20 = 5'h14 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_20
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__21 = 5'h15 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_21
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__22 = 5'h16 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_22
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__23 = 5'h17 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_23
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__24 = 5'h18 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_24
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__25 = 5'h19 == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_25
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__26 = 5'h1a == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_26
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__27 = 5'h1b == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_27
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__28 = 5'h1c == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_28
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__29 = 5'h1d == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_29
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__30 = 5'h1e == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_30
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value__31 = 5'h1f == data_io_in_bits_wmask_idx & data_io_in_bits_wmask_datain_31
- ; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_0_value_1_0 = data_io_in_bits_wmask_dataout_0_value__0 |
- data_io_in_bits_wmask_dataout_0_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_1 = data_io_in_bits_wmask_dataout_0_value__2 |
- data_io_in_bits_wmask_dataout_0_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_2 = data_io_in_bits_wmask_dataout_0_value__4 |
- data_io_in_bits_wmask_dataout_0_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_3 = data_io_in_bits_wmask_dataout_0_value__6 |
- data_io_in_bits_wmask_dataout_0_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_4 = data_io_in_bits_wmask_dataout_0_value__8 |
- data_io_in_bits_wmask_dataout_0_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_5 = data_io_in_bits_wmask_dataout_0_value__10 |
- data_io_in_bits_wmask_dataout_0_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_6 = data_io_in_bits_wmask_dataout_0_value__12 |
- data_io_in_bits_wmask_dataout_0_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_7 = data_io_in_bits_wmask_dataout_0_value__14 |
- data_io_in_bits_wmask_dataout_0_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_8 = data_io_in_bits_wmask_dataout_0_value__16 |
- data_io_in_bits_wmask_dataout_0_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_9 = data_io_in_bits_wmask_dataout_0_value__18 |
- data_io_in_bits_wmask_dataout_0_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_10 = data_io_in_bits_wmask_dataout_0_value__20 |
- data_io_in_bits_wmask_dataout_0_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_11 = data_io_in_bits_wmask_dataout_0_value__22 |
- data_io_in_bits_wmask_dataout_0_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_12 = data_io_in_bits_wmask_dataout_0_value__24 |
- data_io_in_bits_wmask_dataout_0_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_13 = data_io_in_bits_wmask_dataout_0_value__26 |
- data_io_in_bits_wmask_dataout_0_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_14 = data_io_in_bits_wmask_dataout_0_value__28 |
- data_io_in_bits_wmask_dataout_0_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_1_15 = data_io_in_bits_wmask_dataout_0_value__30 |
- data_io_in_bits_wmask_dataout_0_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_2_0 = data_io_in_bits_wmask_dataout_0_value_1_0 |
- data_io_in_bits_wmask_dataout_0_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_2_1 = data_io_in_bits_wmask_dataout_0_value_1_2 |
- data_io_in_bits_wmask_dataout_0_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_2_2 = data_io_in_bits_wmask_dataout_0_value_1_4 |
- data_io_in_bits_wmask_dataout_0_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_2_3 = data_io_in_bits_wmask_dataout_0_value_1_6 |
- data_io_in_bits_wmask_dataout_0_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_2_4 = data_io_in_bits_wmask_dataout_0_value_1_8 |
- data_io_in_bits_wmask_dataout_0_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_2_5 = data_io_in_bits_wmask_dataout_0_value_1_10 |
- data_io_in_bits_wmask_dataout_0_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_2_6 = data_io_in_bits_wmask_dataout_0_value_1_12 |
- data_io_in_bits_wmask_dataout_0_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_2_7 = data_io_in_bits_wmask_dataout_0_value_1_14 |
- data_io_in_bits_wmask_dataout_0_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_3_0 = data_io_in_bits_wmask_dataout_0_value_2_0 |
- data_io_in_bits_wmask_dataout_0_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_3_1 = data_io_in_bits_wmask_dataout_0_value_2_2 |
- data_io_in_bits_wmask_dataout_0_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_3_2 = data_io_in_bits_wmask_dataout_0_value_2_4 |
- data_io_in_bits_wmask_dataout_0_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_3_3 = data_io_in_bits_wmask_dataout_0_value_2_6 |
- data_io_in_bits_wmask_dataout_0_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_4_0 = data_io_in_bits_wmask_dataout_0_value_3_0 |
- data_io_in_bits_wmask_dataout_0_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_4_1 = data_io_in_bits_wmask_dataout_0_value_3_2 |
- data_io_in_bits_wmask_dataout_0_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_0_value_5_0 = data_io_in_bits_wmask_dataout_0_value_4_0 |
- data_io_in_bits_wmask_dataout_0_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_1 = 5'h1 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_1_value__0 = 5'h0 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__1 = 5'h1 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__2 = 5'h2 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__3 = 5'h3 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__4 = 5'h4 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__5 = 5'h5 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__6 = 5'h6 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__7 = 5'h7 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__8 = 5'h8 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__9 = 5'h9 == data_io_in_bits_wmask_idx_1 & data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__10 = 5'ha == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__11 = 5'hb == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__12 = 5'hc == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__13 = 5'hd == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__14 = 5'he == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__15 = 5'hf == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__16 = 5'h10 == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__17 = 5'h11 == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__18 = 5'h12 == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__19 = 5'h13 == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__20 = 5'h14 == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__21 = 5'h15 == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__22 = 5'h16 == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__23 = 5'h17 == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__24 = 5'h18 == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__25 = 5'h19 == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__26 = 5'h1a == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__27 = 5'h1b == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__28 = 5'h1c == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__29 = 5'h1d == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__30 = 5'h1e == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value__31 = 5'h1f == data_io_in_bits_wmask_idx_1 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_1_value_1_0 = data_io_in_bits_wmask_dataout_1_value__0 |
- data_io_in_bits_wmask_dataout_1_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_1 = data_io_in_bits_wmask_dataout_1_value__2 |
- data_io_in_bits_wmask_dataout_1_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_2 = data_io_in_bits_wmask_dataout_1_value__4 |
- data_io_in_bits_wmask_dataout_1_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_3 = data_io_in_bits_wmask_dataout_1_value__6 |
- data_io_in_bits_wmask_dataout_1_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_4 = data_io_in_bits_wmask_dataout_1_value__8 |
- data_io_in_bits_wmask_dataout_1_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_5 = data_io_in_bits_wmask_dataout_1_value__10 |
- data_io_in_bits_wmask_dataout_1_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_6 = data_io_in_bits_wmask_dataout_1_value__12 |
- data_io_in_bits_wmask_dataout_1_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_7 = data_io_in_bits_wmask_dataout_1_value__14 |
- data_io_in_bits_wmask_dataout_1_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_8 = data_io_in_bits_wmask_dataout_1_value__16 |
- data_io_in_bits_wmask_dataout_1_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_9 = data_io_in_bits_wmask_dataout_1_value__18 |
- data_io_in_bits_wmask_dataout_1_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_10 = data_io_in_bits_wmask_dataout_1_value__20 |
- data_io_in_bits_wmask_dataout_1_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_11 = data_io_in_bits_wmask_dataout_1_value__22 |
- data_io_in_bits_wmask_dataout_1_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_12 = data_io_in_bits_wmask_dataout_1_value__24 |
- data_io_in_bits_wmask_dataout_1_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_13 = data_io_in_bits_wmask_dataout_1_value__26 |
- data_io_in_bits_wmask_dataout_1_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_14 = data_io_in_bits_wmask_dataout_1_value__28 |
- data_io_in_bits_wmask_dataout_1_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_1_15 = data_io_in_bits_wmask_dataout_1_value__30 |
- data_io_in_bits_wmask_dataout_1_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_2_0 = data_io_in_bits_wmask_dataout_1_value_1_0 |
- data_io_in_bits_wmask_dataout_1_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_2_1 = data_io_in_bits_wmask_dataout_1_value_1_2 |
- data_io_in_bits_wmask_dataout_1_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_2_2 = data_io_in_bits_wmask_dataout_1_value_1_4 |
- data_io_in_bits_wmask_dataout_1_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_2_3 = data_io_in_bits_wmask_dataout_1_value_1_6 |
- data_io_in_bits_wmask_dataout_1_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_2_4 = data_io_in_bits_wmask_dataout_1_value_1_8 |
- data_io_in_bits_wmask_dataout_1_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_2_5 = data_io_in_bits_wmask_dataout_1_value_1_10 |
- data_io_in_bits_wmask_dataout_1_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_2_6 = data_io_in_bits_wmask_dataout_1_value_1_12 |
- data_io_in_bits_wmask_dataout_1_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_2_7 = data_io_in_bits_wmask_dataout_1_value_1_14 |
- data_io_in_bits_wmask_dataout_1_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_3_0 = data_io_in_bits_wmask_dataout_1_value_2_0 |
- data_io_in_bits_wmask_dataout_1_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_3_1 = data_io_in_bits_wmask_dataout_1_value_2_2 |
- data_io_in_bits_wmask_dataout_1_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_3_2 = data_io_in_bits_wmask_dataout_1_value_2_4 |
- data_io_in_bits_wmask_dataout_1_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_3_3 = data_io_in_bits_wmask_dataout_1_value_2_6 |
- data_io_in_bits_wmask_dataout_1_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_4_0 = data_io_in_bits_wmask_dataout_1_value_3_0 |
- data_io_in_bits_wmask_dataout_1_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_4_1 = data_io_in_bits_wmask_dataout_1_value_3_2 |
- data_io_in_bits_wmask_dataout_1_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_1_value_5_0 = data_io_in_bits_wmask_dataout_1_value_4_0 |
- data_io_in_bits_wmask_dataout_1_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_2 = 5'h2 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_2_value__0 = 5'h0 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__1 = 5'h1 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__2 = 5'h2 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__3 = 5'h3 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__4 = 5'h4 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__5 = 5'h5 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__6 = 5'h6 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__7 = 5'h7 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__8 = 5'h8 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__9 = 5'h9 == data_io_in_bits_wmask_idx_2 & data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__10 = 5'ha == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__11 = 5'hb == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__12 = 5'hc == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__13 = 5'hd == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__14 = 5'he == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__15 = 5'hf == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__16 = 5'h10 == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__17 = 5'h11 == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__18 = 5'h12 == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__19 = 5'h13 == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__20 = 5'h14 == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__21 = 5'h15 == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__22 = 5'h16 == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__23 = 5'h17 == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__24 = 5'h18 == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__25 = 5'h19 == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__26 = 5'h1a == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__27 = 5'h1b == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__28 = 5'h1c == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__29 = 5'h1d == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__30 = 5'h1e == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value__31 = 5'h1f == data_io_in_bits_wmask_idx_2 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_2_value_1_0 = data_io_in_bits_wmask_dataout_2_value__0 |
- data_io_in_bits_wmask_dataout_2_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_1 = data_io_in_bits_wmask_dataout_2_value__2 |
- data_io_in_bits_wmask_dataout_2_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_2 = data_io_in_bits_wmask_dataout_2_value__4 |
- data_io_in_bits_wmask_dataout_2_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_3 = data_io_in_bits_wmask_dataout_2_value__6 |
- data_io_in_bits_wmask_dataout_2_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_4 = data_io_in_bits_wmask_dataout_2_value__8 |
- data_io_in_bits_wmask_dataout_2_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_5 = data_io_in_bits_wmask_dataout_2_value__10 |
- data_io_in_bits_wmask_dataout_2_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_6 = data_io_in_bits_wmask_dataout_2_value__12 |
- data_io_in_bits_wmask_dataout_2_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_7 = data_io_in_bits_wmask_dataout_2_value__14 |
- data_io_in_bits_wmask_dataout_2_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_8 = data_io_in_bits_wmask_dataout_2_value__16 |
- data_io_in_bits_wmask_dataout_2_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_9 = data_io_in_bits_wmask_dataout_2_value__18 |
- data_io_in_bits_wmask_dataout_2_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_10 = data_io_in_bits_wmask_dataout_2_value__20 |
- data_io_in_bits_wmask_dataout_2_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_11 = data_io_in_bits_wmask_dataout_2_value__22 |
- data_io_in_bits_wmask_dataout_2_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_12 = data_io_in_bits_wmask_dataout_2_value__24 |
- data_io_in_bits_wmask_dataout_2_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_13 = data_io_in_bits_wmask_dataout_2_value__26 |
- data_io_in_bits_wmask_dataout_2_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_14 = data_io_in_bits_wmask_dataout_2_value__28 |
- data_io_in_bits_wmask_dataout_2_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_1_15 = data_io_in_bits_wmask_dataout_2_value__30 |
- data_io_in_bits_wmask_dataout_2_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_2_0 = data_io_in_bits_wmask_dataout_2_value_1_0 |
- data_io_in_bits_wmask_dataout_2_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_2_1 = data_io_in_bits_wmask_dataout_2_value_1_2 |
- data_io_in_bits_wmask_dataout_2_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_2_2 = data_io_in_bits_wmask_dataout_2_value_1_4 |
- data_io_in_bits_wmask_dataout_2_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_2_3 = data_io_in_bits_wmask_dataout_2_value_1_6 |
- data_io_in_bits_wmask_dataout_2_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_2_4 = data_io_in_bits_wmask_dataout_2_value_1_8 |
- data_io_in_bits_wmask_dataout_2_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_2_5 = data_io_in_bits_wmask_dataout_2_value_1_10 |
- data_io_in_bits_wmask_dataout_2_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_2_6 = data_io_in_bits_wmask_dataout_2_value_1_12 |
- data_io_in_bits_wmask_dataout_2_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_2_7 = data_io_in_bits_wmask_dataout_2_value_1_14 |
- data_io_in_bits_wmask_dataout_2_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_3_0 = data_io_in_bits_wmask_dataout_2_value_2_0 |
- data_io_in_bits_wmask_dataout_2_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_3_1 = data_io_in_bits_wmask_dataout_2_value_2_2 |
- data_io_in_bits_wmask_dataout_2_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_3_2 = data_io_in_bits_wmask_dataout_2_value_2_4 |
- data_io_in_bits_wmask_dataout_2_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_3_3 = data_io_in_bits_wmask_dataout_2_value_2_6 |
- data_io_in_bits_wmask_dataout_2_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_4_0 = data_io_in_bits_wmask_dataout_2_value_3_0 |
- data_io_in_bits_wmask_dataout_2_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_4_1 = data_io_in_bits_wmask_dataout_2_value_3_2 |
- data_io_in_bits_wmask_dataout_2_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_2_value_5_0 = data_io_in_bits_wmask_dataout_2_value_4_0 |
- data_io_in_bits_wmask_dataout_2_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_3 = 5'h3 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_3_value__0 = 5'h0 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__1 = 5'h1 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__2 = 5'h2 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__3 = 5'h3 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__4 = 5'h4 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__5 = 5'h5 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__6 = 5'h6 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__7 = 5'h7 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__8 = 5'h8 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__9 = 5'h9 == data_io_in_bits_wmask_idx_3 & data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__10 = 5'ha == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__11 = 5'hb == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__12 = 5'hc == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__13 = 5'hd == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__14 = 5'he == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__15 = 5'hf == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__16 = 5'h10 == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__17 = 5'h11 == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__18 = 5'h12 == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__19 = 5'h13 == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__20 = 5'h14 == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__21 = 5'h15 == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__22 = 5'h16 == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__23 = 5'h17 == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__24 = 5'h18 == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__25 = 5'h19 == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__26 = 5'h1a == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__27 = 5'h1b == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__28 = 5'h1c == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__29 = 5'h1d == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__30 = 5'h1e == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value__31 = 5'h1f == data_io_in_bits_wmask_idx_3 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_3_value_1_0 = data_io_in_bits_wmask_dataout_3_value__0 |
- data_io_in_bits_wmask_dataout_3_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_1 = data_io_in_bits_wmask_dataout_3_value__2 |
- data_io_in_bits_wmask_dataout_3_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_2 = data_io_in_bits_wmask_dataout_3_value__4 |
- data_io_in_bits_wmask_dataout_3_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_3 = data_io_in_bits_wmask_dataout_3_value__6 |
- data_io_in_bits_wmask_dataout_3_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_4 = data_io_in_bits_wmask_dataout_3_value__8 |
- data_io_in_bits_wmask_dataout_3_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_5 = data_io_in_bits_wmask_dataout_3_value__10 |
- data_io_in_bits_wmask_dataout_3_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_6 = data_io_in_bits_wmask_dataout_3_value__12 |
- data_io_in_bits_wmask_dataout_3_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_7 = data_io_in_bits_wmask_dataout_3_value__14 |
- data_io_in_bits_wmask_dataout_3_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_8 = data_io_in_bits_wmask_dataout_3_value__16 |
- data_io_in_bits_wmask_dataout_3_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_9 = data_io_in_bits_wmask_dataout_3_value__18 |
- data_io_in_bits_wmask_dataout_3_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_10 = data_io_in_bits_wmask_dataout_3_value__20 |
- data_io_in_bits_wmask_dataout_3_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_11 = data_io_in_bits_wmask_dataout_3_value__22 |
- data_io_in_bits_wmask_dataout_3_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_12 = data_io_in_bits_wmask_dataout_3_value__24 |
- data_io_in_bits_wmask_dataout_3_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_13 = data_io_in_bits_wmask_dataout_3_value__26 |
- data_io_in_bits_wmask_dataout_3_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_14 = data_io_in_bits_wmask_dataout_3_value__28 |
- data_io_in_bits_wmask_dataout_3_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_1_15 = data_io_in_bits_wmask_dataout_3_value__30 |
- data_io_in_bits_wmask_dataout_3_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_2_0 = data_io_in_bits_wmask_dataout_3_value_1_0 |
- data_io_in_bits_wmask_dataout_3_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_2_1 = data_io_in_bits_wmask_dataout_3_value_1_2 |
- data_io_in_bits_wmask_dataout_3_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_2_2 = data_io_in_bits_wmask_dataout_3_value_1_4 |
- data_io_in_bits_wmask_dataout_3_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_2_3 = data_io_in_bits_wmask_dataout_3_value_1_6 |
- data_io_in_bits_wmask_dataout_3_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_2_4 = data_io_in_bits_wmask_dataout_3_value_1_8 |
- data_io_in_bits_wmask_dataout_3_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_2_5 = data_io_in_bits_wmask_dataout_3_value_1_10 |
- data_io_in_bits_wmask_dataout_3_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_2_6 = data_io_in_bits_wmask_dataout_3_value_1_12 |
- data_io_in_bits_wmask_dataout_3_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_2_7 = data_io_in_bits_wmask_dataout_3_value_1_14 |
- data_io_in_bits_wmask_dataout_3_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_3_0 = data_io_in_bits_wmask_dataout_3_value_2_0 |
- data_io_in_bits_wmask_dataout_3_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_3_1 = data_io_in_bits_wmask_dataout_3_value_2_2 |
- data_io_in_bits_wmask_dataout_3_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_3_2 = data_io_in_bits_wmask_dataout_3_value_2_4 |
- data_io_in_bits_wmask_dataout_3_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_3_3 = data_io_in_bits_wmask_dataout_3_value_2_6 |
- data_io_in_bits_wmask_dataout_3_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_4_0 = data_io_in_bits_wmask_dataout_3_value_3_0 |
- data_io_in_bits_wmask_dataout_3_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_4_1 = data_io_in_bits_wmask_dataout_3_value_3_2 |
- data_io_in_bits_wmask_dataout_3_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_3_value_5_0 = data_io_in_bits_wmask_dataout_3_value_4_0 |
- data_io_in_bits_wmask_dataout_3_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_4 = 5'h4 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_4_value__0 = 5'h0 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__1 = 5'h1 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__2 = 5'h2 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__3 = 5'h3 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__4 = 5'h4 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__5 = 5'h5 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__6 = 5'h6 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__7 = 5'h7 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__8 = 5'h8 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__9 = 5'h9 == data_io_in_bits_wmask_idx_4 & data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__10 = 5'ha == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__11 = 5'hb == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__12 = 5'hc == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__13 = 5'hd == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__14 = 5'he == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__15 = 5'hf == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__16 = 5'h10 == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__17 = 5'h11 == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__18 = 5'h12 == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__19 = 5'h13 == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__20 = 5'h14 == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__21 = 5'h15 == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__22 = 5'h16 == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__23 = 5'h17 == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__24 = 5'h18 == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__25 = 5'h19 == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__26 = 5'h1a == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__27 = 5'h1b == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__28 = 5'h1c == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__29 = 5'h1d == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__30 = 5'h1e == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value__31 = 5'h1f == data_io_in_bits_wmask_idx_4 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_4_value_1_0 = data_io_in_bits_wmask_dataout_4_value__0 |
- data_io_in_bits_wmask_dataout_4_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_1 = data_io_in_bits_wmask_dataout_4_value__2 |
- data_io_in_bits_wmask_dataout_4_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_2 = data_io_in_bits_wmask_dataout_4_value__4 |
- data_io_in_bits_wmask_dataout_4_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_3 = data_io_in_bits_wmask_dataout_4_value__6 |
- data_io_in_bits_wmask_dataout_4_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_4 = data_io_in_bits_wmask_dataout_4_value__8 |
- data_io_in_bits_wmask_dataout_4_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_5 = data_io_in_bits_wmask_dataout_4_value__10 |
- data_io_in_bits_wmask_dataout_4_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_6 = data_io_in_bits_wmask_dataout_4_value__12 |
- data_io_in_bits_wmask_dataout_4_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_7 = data_io_in_bits_wmask_dataout_4_value__14 |
- data_io_in_bits_wmask_dataout_4_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_8 = data_io_in_bits_wmask_dataout_4_value__16 |
- data_io_in_bits_wmask_dataout_4_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_9 = data_io_in_bits_wmask_dataout_4_value__18 |
- data_io_in_bits_wmask_dataout_4_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_10 = data_io_in_bits_wmask_dataout_4_value__20 |
- data_io_in_bits_wmask_dataout_4_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_11 = data_io_in_bits_wmask_dataout_4_value__22 |
- data_io_in_bits_wmask_dataout_4_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_12 = data_io_in_bits_wmask_dataout_4_value__24 |
- data_io_in_bits_wmask_dataout_4_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_13 = data_io_in_bits_wmask_dataout_4_value__26 |
- data_io_in_bits_wmask_dataout_4_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_14 = data_io_in_bits_wmask_dataout_4_value__28 |
- data_io_in_bits_wmask_dataout_4_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_1_15 = data_io_in_bits_wmask_dataout_4_value__30 |
- data_io_in_bits_wmask_dataout_4_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_2_0 = data_io_in_bits_wmask_dataout_4_value_1_0 |
- data_io_in_bits_wmask_dataout_4_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_2_1 = data_io_in_bits_wmask_dataout_4_value_1_2 |
- data_io_in_bits_wmask_dataout_4_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_2_2 = data_io_in_bits_wmask_dataout_4_value_1_4 |
- data_io_in_bits_wmask_dataout_4_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_2_3 = data_io_in_bits_wmask_dataout_4_value_1_6 |
- data_io_in_bits_wmask_dataout_4_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_2_4 = data_io_in_bits_wmask_dataout_4_value_1_8 |
- data_io_in_bits_wmask_dataout_4_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_2_5 = data_io_in_bits_wmask_dataout_4_value_1_10 |
- data_io_in_bits_wmask_dataout_4_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_2_6 = data_io_in_bits_wmask_dataout_4_value_1_12 |
- data_io_in_bits_wmask_dataout_4_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_2_7 = data_io_in_bits_wmask_dataout_4_value_1_14 |
- data_io_in_bits_wmask_dataout_4_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_3_0 = data_io_in_bits_wmask_dataout_4_value_2_0 |
- data_io_in_bits_wmask_dataout_4_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_3_1 = data_io_in_bits_wmask_dataout_4_value_2_2 |
- data_io_in_bits_wmask_dataout_4_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_3_2 = data_io_in_bits_wmask_dataout_4_value_2_4 |
- data_io_in_bits_wmask_dataout_4_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_3_3 = data_io_in_bits_wmask_dataout_4_value_2_6 |
- data_io_in_bits_wmask_dataout_4_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_4_0 = data_io_in_bits_wmask_dataout_4_value_3_0 |
- data_io_in_bits_wmask_dataout_4_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_4_1 = data_io_in_bits_wmask_dataout_4_value_3_2 |
- data_io_in_bits_wmask_dataout_4_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_4_value_5_0 = data_io_in_bits_wmask_dataout_4_value_4_0 |
- data_io_in_bits_wmask_dataout_4_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_5 = 5'h5 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_5_value__0 = 5'h0 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__1 = 5'h1 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__2 = 5'h2 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__3 = 5'h3 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__4 = 5'h4 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__5 = 5'h5 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__6 = 5'h6 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__7 = 5'h7 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__8 = 5'h8 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__9 = 5'h9 == data_io_in_bits_wmask_idx_5 & data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__10 = 5'ha == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__11 = 5'hb == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__12 = 5'hc == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__13 = 5'hd == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__14 = 5'he == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__15 = 5'hf == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__16 = 5'h10 == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__17 = 5'h11 == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__18 = 5'h12 == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__19 = 5'h13 == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__20 = 5'h14 == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__21 = 5'h15 == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__22 = 5'h16 == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__23 = 5'h17 == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__24 = 5'h18 == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__25 = 5'h19 == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__26 = 5'h1a == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__27 = 5'h1b == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__28 = 5'h1c == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__29 = 5'h1d == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__30 = 5'h1e == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value__31 = 5'h1f == data_io_in_bits_wmask_idx_5 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_5_value_1_0 = data_io_in_bits_wmask_dataout_5_value__0 |
- data_io_in_bits_wmask_dataout_5_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_1 = data_io_in_bits_wmask_dataout_5_value__2 |
- data_io_in_bits_wmask_dataout_5_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_2 = data_io_in_bits_wmask_dataout_5_value__4 |
- data_io_in_bits_wmask_dataout_5_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_3 = data_io_in_bits_wmask_dataout_5_value__6 |
- data_io_in_bits_wmask_dataout_5_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_4 = data_io_in_bits_wmask_dataout_5_value__8 |
- data_io_in_bits_wmask_dataout_5_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_5 = data_io_in_bits_wmask_dataout_5_value__10 |
- data_io_in_bits_wmask_dataout_5_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_6 = data_io_in_bits_wmask_dataout_5_value__12 |
- data_io_in_bits_wmask_dataout_5_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_7 = data_io_in_bits_wmask_dataout_5_value__14 |
- data_io_in_bits_wmask_dataout_5_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_8 = data_io_in_bits_wmask_dataout_5_value__16 |
- data_io_in_bits_wmask_dataout_5_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_9 = data_io_in_bits_wmask_dataout_5_value__18 |
- data_io_in_bits_wmask_dataout_5_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_10 = data_io_in_bits_wmask_dataout_5_value__20 |
- data_io_in_bits_wmask_dataout_5_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_11 = data_io_in_bits_wmask_dataout_5_value__22 |
- data_io_in_bits_wmask_dataout_5_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_12 = data_io_in_bits_wmask_dataout_5_value__24 |
- data_io_in_bits_wmask_dataout_5_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_13 = data_io_in_bits_wmask_dataout_5_value__26 |
- data_io_in_bits_wmask_dataout_5_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_14 = data_io_in_bits_wmask_dataout_5_value__28 |
- data_io_in_bits_wmask_dataout_5_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_1_15 = data_io_in_bits_wmask_dataout_5_value__30 |
- data_io_in_bits_wmask_dataout_5_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_2_0 = data_io_in_bits_wmask_dataout_5_value_1_0 |
- data_io_in_bits_wmask_dataout_5_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_2_1 = data_io_in_bits_wmask_dataout_5_value_1_2 |
- data_io_in_bits_wmask_dataout_5_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_2_2 = data_io_in_bits_wmask_dataout_5_value_1_4 |
- data_io_in_bits_wmask_dataout_5_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_2_3 = data_io_in_bits_wmask_dataout_5_value_1_6 |
- data_io_in_bits_wmask_dataout_5_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_2_4 = data_io_in_bits_wmask_dataout_5_value_1_8 |
- data_io_in_bits_wmask_dataout_5_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_2_5 = data_io_in_bits_wmask_dataout_5_value_1_10 |
- data_io_in_bits_wmask_dataout_5_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_2_6 = data_io_in_bits_wmask_dataout_5_value_1_12 |
- data_io_in_bits_wmask_dataout_5_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_2_7 = data_io_in_bits_wmask_dataout_5_value_1_14 |
- data_io_in_bits_wmask_dataout_5_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_3_0 = data_io_in_bits_wmask_dataout_5_value_2_0 |
- data_io_in_bits_wmask_dataout_5_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_3_1 = data_io_in_bits_wmask_dataout_5_value_2_2 |
- data_io_in_bits_wmask_dataout_5_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_3_2 = data_io_in_bits_wmask_dataout_5_value_2_4 |
- data_io_in_bits_wmask_dataout_5_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_3_3 = data_io_in_bits_wmask_dataout_5_value_2_6 |
- data_io_in_bits_wmask_dataout_5_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_4_0 = data_io_in_bits_wmask_dataout_5_value_3_0 |
- data_io_in_bits_wmask_dataout_5_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_4_1 = data_io_in_bits_wmask_dataout_5_value_3_2 |
- data_io_in_bits_wmask_dataout_5_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_5_value_5_0 = data_io_in_bits_wmask_dataout_5_value_4_0 |
- data_io_in_bits_wmask_dataout_5_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_6 = 5'h6 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_6_value__0 = 5'h0 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__1 = 5'h1 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__2 = 5'h2 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__3 = 5'h3 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__4 = 5'h4 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__5 = 5'h5 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__6 = 5'h6 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__7 = 5'h7 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__8 = 5'h8 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__9 = 5'h9 == data_io_in_bits_wmask_idx_6 & data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__10 = 5'ha == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__11 = 5'hb == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__12 = 5'hc == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__13 = 5'hd == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__14 = 5'he == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__15 = 5'hf == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__16 = 5'h10 == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__17 = 5'h11 == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__18 = 5'h12 == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__19 = 5'h13 == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__20 = 5'h14 == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__21 = 5'h15 == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__22 = 5'h16 == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__23 = 5'h17 == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__24 = 5'h18 == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__25 = 5'h19 == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__26 = 5'h1a == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__27 = 5'h1b == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__28 = 5'h1c == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__29 = 5'h1d == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__30 = 5'h1e == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value__31 = 5'h1f == data_io_in_bits_wmask_idx_6 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_6_value_1_0 = data_io_in_bits_wmask_dataout_6_value__0 |
- data_io_in_bits_wmask_dataout_6_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_1 = data_io_in_bits_wmask_dataout_6_value__2 |
- data_io_in_bits_wmask_dataout_6_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_2 = data_io_in_bits_wmask_dataout_6_value__4 |
- data_io_in_bits_wmask_dataout_6_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_3 = data_io_in_bits_wmask_dataout_6_value__6 |
- data_io_in_bits_wmask_dataout_6_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_4 = data_io_in_bits_wmask_dataout_6_value__8 |
- data_io_in_bits_wmask_dataout_6_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_5 = data_io_in_bits_wmask_dataout_6_value__10 |
- data_io_in_bits_wmask_dataout_6_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_6 = data_io_in_bits_wmask_dataout_6_value__12 |
- data_io_in_bits_wmask_dataout_6_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_7 = data_io_in_bits_wmask_dataout_6_value__14 |
- data_io_in_bits_wmask_dataout_6_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_8 = data_io_in_bits_wmask_dataout_6_value__16 |
- data_io_in_bits_wmask_dataout_6_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_9 = data_io_in_bits_wmask_dataout_6_value__18 |
- data_io_in_bits_wmask_dataout_6_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_10 = data_io_in_bits_wmask_dataout_6_value__20 |
- data_io_in_bits_wmask_dataout_6_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_11 = data_io_in_bits_wmask_dataout_6_value__22 |
- data_io_in_bits_wmask_dataout_6_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_12 = data_io_in_bits_wmask_dataout_6_value__24 |
- data_io_in_bits_wmask_dataout_6_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_13 = data_io_in_bits_wmask_dataout_6_value__26 |
- data_io_in_bits_wmask_dataout_6_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_14 = data_io_in_bits_wmask_dataout_6_value__28 |
- data_io_in_bits_wmask_dataout_6_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_1_15 = data_io_in_bits_wmask_dataout_6_value__30 |
- data_io_in_bits_wmask_dataout_6_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_2_0 = data_io_in_bits_wmask_dataout_6_value_1_0 |
- data_io_in_bits_wmask_dataout_6_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_2_1 = data_io_in_bits_wmask_dataout_6_value_1_2 |
- data_io_in_bits_wmask_dataout_6_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_2_2 = data_io_in_bits_wmask_dataout_6_value_1_4 |
- data_io_in_bits_wmask_dataout_6_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_2_3 = data_io_in_bits_wmask_dataout_6_value_1_6 |
- data_io_in_bits_wmask_dataout_6_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_2_4 = data_io_in_bits_wmask_dataout_6_value_1_8 |
- data_io_in_bits_wmask_dataout_6_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_2_5 = data_io_in_bits_wmask_dataout_6_value_1_10 |
- data_io_in_bits_wmask_dataout_6_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_2_6 = data_io_in_bits_wmask_dataout_6_value_1_12 |
- data_io_in_bits_wmask_dataout_6_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_2_7 = data_io_in_bits_wmask_dataout_6_value_1_14 |
- data_io_in_bits_wmask_dataout_6_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_3_0 = data_io_in_bits_wmask_dataout_6_value_2_0 |
- data_io_in_bits_wmask_dataout_6_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_3_1 = data_io_in_bits_wmask_dataout_6_value_2_2 |
- data_io_in_bits_wmask_dataout_6_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_3_2 = data_io_in_bits_wmask_dataout_6_value_2_4 |
- data_io_in_bits_wmask_dataout_6_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_3_3 = data_io_in_bits_wmask_dataout_6_value_2_6 |
- data_io_in_bits_wmask_dataout_6_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_4_0 = data_io_in_bits_wmask_dataout_6_value_3_0 |
- data_io_in_bits_wmask_dataout_6_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_4_1 = data_io_in_bits_wmask_dataout_6_value_3_2 |
- data_io_in_bits_wmask_dataout_6_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_6_value_5_0 = data_io_in_bits_wmask_dataout_6_value_4_0 |
- data_io_in_bits_wmask_dataout_6_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_7 = 5'h7 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_7_value__0 = 5'h0 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__1 = 5'h1 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__2 = 5'h2 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__3 = 5'h3 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__4 = 5'h4 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__5 = 5'h5 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__6 = 5'h6 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__7 = 5'h7 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__8 = 5'h8 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__9 = 5'h9 == data_io_in_bits_wmask_idx_7 & data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__10 = 5'ha == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__11 = 5'hb == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__12 = 5'hc == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__13 = 5'hd == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__14 = 5'he == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__15 = 5'hf == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__16 = 5'h10 == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__17 = 5'h11 == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__18 = 5'h12 == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__19 = 5'h13 == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__20 = 5'h14 == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__21 = 5'h15 == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__22 = 5'h16 == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__23 = 5'h17 == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__24 = 5'h18 == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__25 = 5'h19 == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__26 = 5'h1a == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__27 = 5'h1b == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__28 = 5'h1c == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__29 = 5'h1d == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__30 = 5'h1e == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value__31 = 5'h1f == data_io_in_bits_wmask_idx_7 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_7_value_1_0 = data_io_in_bits_wmask_dataout_7_value__0 |
- data_io_in_bits_wmask_dataout_7_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_1 = data_io_in_bits_wmask_dataout_7_value__2 |
- data_io_in_bits_wmask_dataout_7_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_2 = data_io_in_bits_wmask_dataout_7_value__4 |
- data_io_in_bits_wmask_dataout_7_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_3 = data_io_in_bits_wmask_dataout_7_value__6 |
- data_io_in_bits_wmask_dataout_7_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_4 = data_io_in_bits_wmask_dataout_7_value__8 |
- data_io_in_bits_wmask_dataout_7_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_5 = data_io_in_bits_wmask_dataout_7_value__10 |
- data_io_in_bits_wmask_dataout_7_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_6 = data_io_in_bits_wmask_dataout_7_value__12 |
- data_io_in_bits_wmask_dataout_7_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_7 = data_io_in_bits_wmask_dataout_7_value__14 |
- data_io_in_bits_wmask_dataout_7_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_8 = data_io_in_bits_wmask_dataout_7_value__16 |
- data_io_in_bits_wmask_dataout_7_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_9 = data_io_in_bits_wmask_dataout_7_value__18 |
- data_io_in_bits_wmask_dataout_7_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_10 = data_io_in_bits_wmask_dataout_7_value__20 |
- data_io_in_bits_wmask_dataout_7_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_11 = data_io_in_bits_wmask_dataout_7_value__22 |
- data_io_in_bits_wmask_dataout_7_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_12 = data_io_in_bits_wmask_dataout_7_value__24 |
- data_io_in_bits_wmask_dataout_7_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_13 = data_io_in_bits_wmask_dataout_7_value__26 |
- data_io_in_bits_wmask_dataout_7_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_14 = data_io_in_bits_wmask_dataout_7_value__28 |
- data_io_in_bits_wmask_dataout_7_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_1_15 = data_io_in_bits_wmask_dataout_7_value__30 |
- data_io_in_bits_wmask_dataout_7_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_2_0 = data_io_in_bits_wmask_dataout_7_value_1_0 |
- data_io_in_bits_wmask_dataout_7_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_2_1 = data_io_in_bits_wmask_dataout_7_value_1_2 |
- data_io_in_bits_wmask_dataout_7_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_2_2 = data_io_in_bits_wmask_dataout_7_value_1_4 |
- data_io_in_bits_wmask_dataout_7_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_2_3 = data_io_in_bits_wmask_dataout_7_value_1_6 |
- data_io_in_bits_wmask_dataout_7_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_2_4 = data_io_in_bits_wmask_dataout_7_value_1_8 |
- data_io_in_bits_wmask_dataout_7_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_2_5 = data_io_in_bits_wmask_dataout_7_value_1_10 |
- data_io_in_bits_wmask_dataout_7_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_2_6 = data_io_in_bits_wmask_dataout_7_value_1_12 |
- data_io_in_bits_wmask_dataout_7_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_2_7 = data_io_in_bits_wmask_dataout_7_value_1_14 |
- data_io_in_bits_wmask_dataout_7_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_3_0 = data_io_in_bits_wmask_dataout_7_value_2_0 |
- data_io_in_bits_wmask_dataout_7_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_3_1 = data_io_in_bits_wmask_dataout_7_value_2_2 |
- data_io_in_bits_wmask_dataout_7_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_3_2 = data_io_in_bits_wmask_dataout_7_value_2_4 |
- data_io_in_bits_wmask_dataout_7_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_3_3 = data_io_in_bits_wmask_dataout_7_value_2_6 |
- data_io_in_bits_wmask_dataout_7_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_4_0 = data_io_in_bits_wmask_dataout_7_value_3_0 |
- data_io_in_bits_wmask_dataout_7_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_4_1 = data_io_in_bits_wmask_dataout_7_value_3_2 |
- data_io_in_bits_wmask_dataout_7_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_7_value_5_0 = data_io_in_bits_wmask_dataout_7_value_4_0 |
- data_io_in_bits_wmask_dataout_7_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_8 = 5'h8 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_8_value__0 = 5'h0 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__1 = 5'h1 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__2 = 5'h2 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__3 = 5'h3 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__4 = 5'h4 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__5 = 5'h5 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__6 = 5'h6 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__7 = 5'h7 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__8 = 5'h8 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__9 = 5'h9 == data_io_in_bits_wmask_idx_8 & data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__10 = 5'ha == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__11 = 5'hb == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__12 = 5'hc == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__13 = 5'hd == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__14 = 5'he == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__15 = 5'hf == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__16 = 5'h10 == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__17 = 5'h11 == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__18 = 5'h12 == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__19 = 5'h13 == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__20 = 5'h14 == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__21 = 5'h15 == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__22 = 5'h16 == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__23 = 5'h17 == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__24 = 5'h18 == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__25 = 5'h19 == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__26 = 5'h1a == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__27 = 5'h1b == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__28 = 5'h1c == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__29 = 5'h1d == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__30 = 5'h1e == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value__31 = 5'h1f == data_io_in_bits_wmask_idx_8 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_8_value_1_0 = data_io_in_bits_wmask_dataout_8_value__0 |
- data_io_in_bits_wmask_dataout_8_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_1 = data_io_in_bits_wmask_dataout_8_value__2 |
- data_io_in_bits_wmask_dataout_8_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_2 = data_io_in_bits_wmask_dataout_8_value__4 |
- data_io_in_bits_wmask_dataout_8_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_3 = data_io_in_bits_wmask_dataout_8_value__6 |
- data_io_in_bits_wmask_dataout_8_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_4 = data_io_in_bits_wmask_dataout_8_value__8 |
- data_io_in_bits_wmask_dataout_8_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_5 = data_io_in_bits_wmask_dataout_8_value__10 |
- data_io_in_bits_wmask_dataout_8_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_6 = data_io_in_bits_wmask_dataout_8_value__12 |
- data_io_in_bits_wmask_dataout_8_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_7 = data_io_in_bits_wmask_dataout_8_value__14 |
- data_io_in_bits_wmask_dataout_8_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_8 = data_io_in_bits_wmask_dataout_8_value__16 |
- data_io_in_bits_wmask_dataout_8_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_9 = data_io_in_bits_wmask_dataout_8_value__18 |
- data_io_in_bits_wmask_dataout_8_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_10 = data_io_in_bits_wmask_dataout_8_value__20 |
- data_io_in_bits_wmask_dataout_8_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_11 = data_io_in_bits_wmask_dataout_8_value__22 |
- data_io_in_bits_wmask_dataout_8_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_12 = data_io_in_bits_wmask_dataout_8_value__24 |
- data_io_in_bits_wmask_dataout_8_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_13 = data_io_in_bits_wmask_dataout_8_value__26 |
- data_io_in_bits_wmask_dataout_8_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_14 = data_io_in_bits_wmask_dataout_8_value__28 |
- data_io_in_bits_wmask_dataout_8_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_1_15 = data_io_in_bits_wmask_dataout_8_value__30 |
- data_io_in_bits_wmask_dataout_8_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_2_0 = data_io_in_bits_wmask_dataout_8_value_1_0 |
- data_io_in_bits_wmask_dataout_8_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_2_1 = data_io_in_bits_wmask_dataout_8_value_1_2 |
- data_io_in_bits_wmask_dataout_8_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_2_2 = data_io_in_bits_wmask_dataout_8_value_1_4 |
- data_io_in_bits_wmask_dataout_8_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_2_3 = data_io_in_bits_wmask_dataout_8_value_1_6 |
- data_io_in_bits_wmask_dataout_8_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_2_4 = data_io_in_bits_wmask_dataout_8_value_1_8 |
- data_io_in_bits_wmask_dataout_8_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_2_5 = data_io_in_bits_wmask_dataout_8_value_1_10 |
- data_io_in_bits_wmask_dataout_8_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_2_6 = data_io_in_bits_wmask_dataout_8_value_1_12 |
- data_io_in_bits_wmask_dataout_8_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_2_7 = data_io_in_bits_wmask_dataout_8_value_1_14 |
- data_io_in_bits_wmask_dataout_8_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_3_0 = data_io_in_bits_wmask_dataout_8_value_2_0 |
- data_io_in_bits_wmask_dataout_8_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_3_1 = data_io_in_bits_wmask_dataout_8_value_2_2 |
- data_io_in_bits_wmask_dataout_8_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_3_2 = data_io_in_bits_wmask_dataout_8_value_2_4 |
- data_io_in_bits_wmask_dataout_8_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_3_3 = data_io_in_bits_wmask_dataout_8_value_2_6 |
- data_io_in_bits_wmask_dataout_8_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_4_0 = data_io_in_bits_wmask_dataout_8_value_3_0 |
- data_io_in_bits_wmask_dataout_8_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_4_1 = data_io_in_bits_wmask_dataout_8_value_3_2 |
- data_io_in_bits_wmask_dataout_8_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_8_value_5_0 = data_io_in_bits_wmask_dataout_8_value_4_0 |
- data_io_in_bits_wmask_dataout_8_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_9 = 5'h9 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_9_value__0 = 5'h0 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__1 = 5'h1 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__2 = 5'h2 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__3 = 5'h3 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__4 = 5'h4 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__5 = 5'h5 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__6 = 5'h6 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__7 = 5'h7 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__8 = 5'h8 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__9 = 5'h9 == data_io_in_bits_wmask_idx_9 & data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__10 = 5'ha == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__11 = 5'hb == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__12 = 5'hc == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__13 = 5'hd == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__14 = 5'he == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__15 = 5'hf == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__16 = 5'h10 == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__17 = 5'h11 == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__18 = 5'h12 == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__19 = 5'h13 == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__20 = 5'h14 == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__21 = 5'h15 == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__22 = 5'h16 == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__23 = 5'h17 == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__24 = 5'h18 == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__25 = 5'h19 == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__26 = 5'h1a == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__27 = 5'h1b == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__28 = 5'h1c == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__29 = 5'h1d == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__30 = 5'h1e == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value__31 = 5'h1f == data_io_in_bits_wmask_idx_9 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_9_value_1_0 = data_io_in_bits_wmask_dataout_9_value__0 |
- data_io_in_bits_wmask_dataout_9_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_1 = data_io_in_bits_wmask_dataout_9_value__2 |
- data_io_in_bits_wmask_dataout_9_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_2 = data_io_in_bits_wmask_dataout_9_value__4 |
- data_io_in_bits_wmask_dataout_9_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_3 = data_io_in_bits_wmask_dataout_9_value__6 |
- data_io_in_bits_wmask_dataout_9_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_4 = data_io_in_bits_wmask_dataout_9_value__8 |
- data_io_in_bits_wmask_dataout_9_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_5 = data_io_in_bits_wmask_dataout_9_value__10 |
- data_io_in_bits_wmask_dataout_9_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_6 = data_io_in_bits_wmask_dataout_9_value__12 |
- data_io_in_bits_wmask_dataout_9_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_7 = data_io_in_bits_wmask_dataout_9_value__14 |
- data_io_in_bits_wmask_dataout_9_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_8 = data_io_in_bits_wmask_dataout_9_value__16 |
- data_io_in_bits_wmask_dataout_9_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_9 = data_io_in_bits_wmask_dataout_9_value__18 |
- data_io_in_bits_wmask_dataout_9_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_10 = data_io_in_bits_wmask_dataout_9_value__20 |
- data_io_in_bits_wmask_dataout_9_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_11 = data_io_in_bits_wmask_dataout_9_value__22 |
- data_io_in_bits_wmask_dataout_9_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_12 = data_io_in_bits_wmask_dataout_9_value__24 |
- data_io_in_bits_wmask_dataout_9_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_13 = data_io_in_bits_wmask_dataout_9_value__26 |
- data_io_in_bits_wmask_dataout_9_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_14 = data_io_in_bits_wmask_dataout_9_value__28 |
- data_io_in_bits_wmask_dataout_9_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_1_15 = data_io_in_bits_wmask_dataout_9_value__30 |
- data_io_in_bits_wmask_dataout_9_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_2_0 = data_io_in_bits_wmask_dataout_9_value_1_0 |
- data_io_in_bits_wmask_dataout_9_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_2_1 = data_io_in_bits_wmask_dataout_9_value_1_2 |
- data_io_in_bits_wmask_dataout_9_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_2_2 = data_io_in_bits_wmask_dataout_9_value_1_4 |
- data_io_in_bits_wmask_dataout_9_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_2_3 = data_io_in_bits_wmask_dataout_9_value_1_6 |
- data_io_in_bits_wmask_dataout_9_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_2_4 = data_io_in_bits_wmask_dataout_9_value_1_8 |
- data_io_in_bits_wmask_dataout_9_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_2_5 = data_io_in_bits_wmask_dataout_9_value_1_10 |
- data_io_in_bits_wmask_dataout_9_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_2_6 = data_io_in_bits_wmask_dataout_9_value_1_12 |
- data_io_in_bits_wmask_dataout_9_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_2_7 = data_io_in_bits_wmask_dataout_9_value_1_14 |
- data_io_in_bits_wmask_dataout_9_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_3_0 = data_io_in_bits_wmask_dataout_9_value_2_0 |
- data_io_in_bits_wmask_dataout_9_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_3_1 = data_io_in_bits_wmask_dataout_9_value_2_2 |
- data_io_in_bits_wmask_dataout_9_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_3_2 = data_io_in_bits_wmask_dataout_9_value_2_4 |
- data_io_in_bits_wmask_dataout_9_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_3_3 = data_io_in_bits_wmask_dataout_9_value_2_6 |
- data_io_in_bits_wmask_dataout_9_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_4_0 = data_io_in_bits_wmask_dataout_9_value_3_0 |
- data_io_in_bits_wmask_dataout_9_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_4_1 = data_io_in_bits_wmask_dataout_9_value_3_2 |
- data_io_in_bits_wmask_dataout_9_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_9_value_5_0 = data_io_in_bits_wmask_dataout_9_value_4_0 |
- data_io_in_bits_wmask_dataout_9_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_10 = 5'ha - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_10_value__0 = 5'h0 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__1 = 5'h1 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__2 = 5'h2 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__3 = 5'h3 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__4 = 5'h4 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__5 = 5'h5 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__6 = 5'h6 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__7 = 5'h7 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__8 = 5'h8 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__9 = 5'h9 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__10 = 5'ha == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__11 = 5'hb == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__12 = 5'hc == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__13 = 5'hd == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__14 = 5'he == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__15 = 5'hf == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__16 = 5'h10 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__17 = 5'h11 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__18 = 5'h12 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__19 = 5'h13 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__20 = 5'h14 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__21 = 5'h15 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__22 = 5'h16 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__23 = 5'h17 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__24 = 5'h18 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__25 = 5'h19 == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__26 = 5'h1a == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__27 = 5'h1b == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__28 = 5'h1c == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__29 = 5'h1d == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__30 = 5'h1e == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value__31 = 5'h1f == data_io_in_bits_wmask_idx_10 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_10_value_1_0 = data_io_in_bits_wmask_dataout_10_value__0 |
- data_io_in_bits_wmask_dataout_10_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_1 = data_io_in_bits_wmask_dataout_10_value__2 |
- data_io_in_bits_wmask_dataout_10_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_2 = data_io_in_bits_wmask_dataout_10_value__4 |
- data_io_in_bits_wmask_dataout_10_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_3 = data_io_in_bits_wmask_dataout_10_value__6 |
- data_io_in_bits_wmask_dataout_10_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_4 = data_io_in_bits_wmask_dataout_10_value__8 |
- data_io_in_bits_wmask_dataout_10_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_5 = data_io_in_bits_wmask_dataout_10_value__10 |
- data_io_in_bits_wmask_dataout_10_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_6 = data_io_in_bits_wmask_dataout_10_value__12 |
- data_io_in_bits_wmask_dataout_10_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_7 = data_io_in_bits_wmask_dataout_10_value__14 |
- data_io_in_bits_wmask_dataout_10_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_8 = data_io_in_bits_wmask_dataout_10_value__16 |
- data_io_in_bits_wmask_dataout_10_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_9 = data_io_in_bits_wmask_dataout_10_value__18 |
- data_io_in_bits_wmask_dataout_10_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_10 = data_io_in_bits_wmask_dataout_10_value__20 |
- data_io_in_bits_wmask_dataout_10_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_11 = data_io_in_bits_wmask_dataout_10_value__22 |
- data_io_in_bits_wmask_dataout_10_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_12 = data_io_in_bits_wmask_dataout_10_value__24 |
- data_io_in_bits_wmask_dataout_10_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_13 = data_io_in_bits_wmask_dataout_10_value__26 |
- data_io_in_bits_wmask_dataout_10_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_14 = data_io_in_bits_wmask_dataout_10_value__28 |
- data_io_in_bits_wmask_dataout_10_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_1_15 = data_io_in_bits_wmask_dataout_10_value__30 |
- data_io_in_bits_wmask_dataout_10_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_2_0 = data_io_in_bits_wmask_dataout_10_value_1_0 |
- data_io_in_bits_wmask_dataout_10_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_2_1 = data_io_in_bits_wmask_dataout_10_value_1_2 |
- data_io_in_bits_wmask_dataout_10_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_2_2 = data_io_in_bits_wmask_dataout_10_value_1_4 |
- data_io_in_bits_wmask_dataout_10_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_2_3 = data_io_in_bits_wmask_dataout_10_value_1_6 |
- data_io_in_bits_wmask_dataout_10_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_2_4 = data_io_in_bits_wmask_dataout_10_value_1_8 |
- data_io_in_bits_wmask_dataout_10_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_2_5 = data_io_in_bits_wmask_dataout_10_value_1_10 |
- data_io_in_bits_wmask_dataout_10_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_2_6 = data_io_in_bits_wmask_dataout_10_value_1_12 |
- data_io_in_bits_wmask_dataout_10_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_2_7 = data_io_in_bits_wmask_dataout_10_value_1_14 |
- data_io_in_bits_wmask_dataout_10_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_3_0 = data_io_in_bits_wmask_dataout_10_value_2_0 |
- data_io_in_bits_wmask_dataout_10_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_3_1 = data_io_in_bits_wmask_dataout_10_value_2_2 |
- data_io_in_bits_wmask_dataout_10_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_3_2 = data_io_in_bits_wmask_dataout_10_value_2_4 |
- data_io_in_bits_wmask_dataout_10_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_3_3 = data_io_in_bits_wmask_dataout_10_value_2_6 |
- data_io_in_bits_wmask_dataout_10_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_4_0 = data_io_in_bits_wmask_dataout_10_value_3_0 |
- data_io_in_bits_wmask_dataout_10_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_4_1 = data_io_in_bits_wmask_dataout_10_value_3_2 |
- data_io_in_bits_wmask_dataout_10_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_10_value_5_0 = data_io_in_bits_wmask_dataout_10_value_4_0 |
- data_io_in_bits_wmask_dataout_10_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_11 = 5'hb - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_11_value__0 = 5'h0 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__1 = 5'h1 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__2 = 5'h2 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__3 = 5'h3 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__4 = 5'h4 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__5 = 5'h5 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__6 = 5'h6 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__7 = 5'h7 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__8 = 5'h8 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__9 = 5'h9 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__10 = 5'ha == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__11 = 5'hb == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__12 = 5'hc == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__13 = 5'hd == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__14 = 5'he == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__15 = 5'hf == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__16 = 5'h10 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__17 = 5'h11 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__18 = 5'h12 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__19 = 5'h13 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__20 = 5'h14 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__21 = 5'h15 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__22 = 5'h16 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__23 = 5'h17 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__24 = 5'h18 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__25 = 5'h19 == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__26 = 5'h1a == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__27 = 5'h1b == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__28 = 5'h1c == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__29 = 5'h1d == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__30 = 5'h1e == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value__31 = 5'h1f == data_io_in_bits_wmask_idx_11 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_11_value_1_0 = data_io_in_bits_wmask_dataout_11_value__0 |
- data_io_in_bits_wmask_dataout_11_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_1 = data_io_in_bits_wmask_dataout_11_value__2 |
- data_io_in_bits_wmask_dataout_11_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_2 = data_io_in_bits_wmask_dataout_11_value__4 |
- data_io_in_bits_wmask_dataout_11_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_3 = data_io_in_bits_wmask_dataout_11_value__6 |
- data_io_in_bits_wmask_dataout_11_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_4 = data_io_in_bits_wmask_dataout_11_value__8 |
- data_io_in_bits_wmask_dataout_11_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_5 = data_io_in_bits_wmask_dataout_11_value__10 |
- data_io_in_bits_wmask_dataout_11_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_6 = data_io_in_bits_wmask_dataout_11_value__12 |
- data_io_in_bits_wmask_dataout_11_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_7 = data_io_in_bits_wmask_dataout_11_value__14 |
- data_io_in_bits_wmask_dataout_11_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_8 = data_io_in_bits_wmask_dataout_11_value__16 |
- data_io_in_bits_wmask_dataout_11_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_9 = data_io_in_bits_wmask_dataout_11_value__18 |
- data_io_in_bits_wmask_dataout_11_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_10 = data_io_in_bits_wmask_dataout_11_value__20 |
- data_io_in_bits_wmask_dataout_11_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_11 = data_io_in_bits_wmask_dataout_11_value__22 |
- data_io_in_bits_wmask_dataout_11_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_12 = data_io_in_bits_wmask_dataout_11_value__24 |
- data_io_in_bits_wmask_dataout_11_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_13 = data_io_in_bits_wmask_dataout_11_value__26 |
- data_io_in_bits_wmask_dataout_11_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_14 = data_io_in_bits_wmask_dataout_11_value__28 |
- data_io_in_bits_wmask_dataout_11_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_1_15 = data_io_in_bits_wmask_dataout_11_value__30 |
- data_io_in_bits_wmask_dataout_11_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_2_0 = data_io_in_bits_wmask_dataout_11_value_1_0 |
- data_io_in_bits_wmask_dataout_11_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_2_1 = data_io_in_bits_wmask_dataout_11_value_1_2 |
- data_io_in_bits_wmask_dataout_11_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_2_2 = data_io_in_bits_wmask_dataout_11_value_1_4 |
- data_io_in_bits_wmask_dataout_11_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_2_3 = data_io_in_bits_wmask_dataout_11_value_1_6 |
- data_io_in_bits_wmask_dataout_11_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_2_4 = data_io_in_bits_wmask_dataout_11_value_1_8 |
- data_io_in_bits_wmask_dataout_11_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_2_5 = data_io_in_bits_wmask_dataout_11_value_1_10 |
- data_io_in_bits_wmask_dataout_11_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_2_6 = data_io_in_bits_wmask_dataout_11_value_1_12 |
- data_io_in_bits_wmask_dataout_11_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_2_7 = data_io_in_bits_wmask_dataout_11_value_1_14 |
- data_io_in_bits_wmask_dataout_11_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_3_0 = data_io_in_bits_wmask_dataout_11_value_2_0 |
- data_io_in_bits_wmask_dataout_11_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_3_1 = data_io_in_bits_wmask_dataout_11_value_2_2 |
- data_io_in_bits_wmask_dataout_11_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_3_2 = data_io_in_bits_wmask_dataout_11_value_2_4 |
- data_io_in_bits_wmask_dataout_11_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_3_3 = data_io_in_bits_wmask_dataout_11_value_2_6 |
- data_io_in_bits_wmask_dataout_11_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_4_0 = data_io_in_bits_wmask_dataout_11_value_3_0 |
- data_io_in_bits_wmask_dataout_11_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_4_1 = data_io_in_bits_wmask_dataout_11_value_3_2 |
- data_io_in_bits_wmask_dataout_11_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_11_value_5_0 = data_io_in_bits_wmask_dataout_11_value_4_0 |
- data_io_in_bits_wmask_dataout_11_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_12 = 5'hc - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_12_value__0 = 5'h0 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__1 = 5'h1 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__2 = 5'h2 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__3 = 5'h3 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__4 = 5'h4 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__5 = 5'h5 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__6 = 5'h6 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__7 = 5'h7 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__8 = 5'h8 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__9 = 5'h9 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__10 = 5'ha == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__11 = 5'hb == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__12 = 5'hc == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__13 = 5'hd == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__14 = 5'he == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__15 = 5'hf == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__16 = 5'h10 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__17 = 5'h11 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__18 = 5'h12 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__19 = 5'h13 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__20 = 5'h14 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__21 = 5'h15 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__22 = 5'h16 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__23 = 5'h17 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__24 = 5'h18 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__25 = 5'h19 == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__26 = 5'h1a == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__27 = 5'h1b == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__28 = 5'h1c == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__29 = 5'h1d == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__30 = 5'h1e == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value__31 = 5'h1f == data_io_in_bits_wmask_idx_12 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_12_value_1_0 = data_io_in_bits_wmask_dataout_12_value__0 |
- data_io_in_bits_wmask_dataout_12_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_1 = data_io_in_bits_wmask_dataout_12_value__2 |
- data_io_in_bits_wmask_dataout_12_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_2 = data_io_in_bits_wmask_dataout_12_value__4 |
- data_io_in_bits_wmask_dataout_12_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_3 = data_io_in_bits_wmask_dataout_12_value__6 |
- data_io_in_bits_wmask_dataout_12_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_4 = data_io_in_bits_wmask_dataout_12_value__8 |
- data_io_in_bits_wmask_dataout_12_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_5 = data_io_in_bits_wmask_dataout_12_value__10 |
- data_io_in_bits_wmask_dataout_12_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_6 = data_io_in_bits_wmask_dataout_12_value__12 |
- data_io_in_bits_wmask_dataout_12_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_7 = data_io_in_bits_wmask_dataout_12_value__14 |
- data_io_in_bits_wmask_dataout_12_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_8 = data_io_in_bits_wmask_dataout_12_value__16 |
- data_io_in_bits_wmask_dataout_12_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_9 = data_io_in_bits_wmask_dataout_12_value__18 |
- data_io_in_bits_wmask_dataout_12_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_10 = data_io_in_bits_wmask_dataout_12_value__20 |
- data_io_in_bits_wmask_dataout_12_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_11 = data_io_in_bits_wmask_dataout_12_value__22 |
- data_io_in_bits_wmask_dataout_12_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_12 = data_io_in_bits_wmask_dataout_12_value__24 |
- data_io_in_bits_wmask_dataout_12_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_13 = data_io_in_bits_wmask_dataout_12_value__26 |
- data_io_in_bits_wmask_dataout_12_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_14 = data_io_in_bits_wmask_dataout_12_value__28 |
- data_io_in_bits_wmask_dataout_12_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_1_15 = data_io_in_bits_wmask_dataout_12_value__30 |
- data_io_in_bits_wmask_dataout_12_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_2_0 = data_io_in_bits_wmask_dataout_12_value_1_0 |
- data_io_in_bits_wmask_dataout_12_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_2_1 = data_io_in_bits_wmask_dataout_12_value_1_2 |
- data_io_in_bits_wmask_dataout_12_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_2_2 = data_io_in_bits_wmask_dataout_12_value_1_4 |
- data_io_in_bits_wmask_dataout_12_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_2_3 = data_io_in_bits_wmask_dataout_12_value_1_6 |
- data_io_in_bits_wmask_dataout_12_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_2_4 = data_io_in_bits_wmask_dataout_12_value_1_8 |
- data_io_in_bits_wmask_dataout_12_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_2_5 = data_io_in_bits_wmask_dataout_12_value_1_10 |
- data_io_in_bits_wmask_dataout_12_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_2_6 = data_io_in_bits_wmask_dataout_12_value_1_12 |
- data_io_in_bits_wmask_dataout_12_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_2_7 = data_io_in_bits_wmask_dataout_12_value_1_14 |
- data_io_in_bits_wmask_dataout_12_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_3_0 = data_io_in_bits_wmask_dataout_12_value_2_0 |
- data_io_in_bits_wmask_dataout_12_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_3_1 = data_io_in_bits_wmask_dataout_12_value_2_2 |
- data_io_in_bits_wmask_dataout_12_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_3_2 = data_io_in_bits_wmask_dataout_12_value_2_4 |
- data_io_in_bits_wmask_dataout_12_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_3_3 = data_io_in_bits_wmask_dataout_12_value_2_6 |
- data_io_in_bits_wmask_dataout_12_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_4_0 = data_io_in_bits_wmask_dataout_12_value_3_0 |
- data_io_in_bits_wmask_dataout_12_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_4_1 = data_io_in_bits_wmask_dataout_12_value_3_2 |
- data_io_in_bits_wmask_dataout_12_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_12_value_5_0 = data_io_in_bits_wmask_dataout_12_value_4_0 |
- data_io_in_bits_wmask_dataout_12_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_13 = 5'hd - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_13_value__0 = 5'h0 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__1 = 5'h1 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__2 = 5'h2 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__3 = 5'h3 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__4 = 5'h4 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__5 = 5'h5 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__6 = 5'h6 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__7 = 5'h7 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__8 = 5'h8 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__9 = 5'h9 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__10 = 5'ha == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__11 = 5'hb == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__12 = 5'hc == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__13 = 5'hd == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__14 = 5'he == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__15 = 5'hf == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__16 = 5'h10 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__17 = 5'h11 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__18 = 5'h12 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__19 = 5'h13 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__20 = 5'h14 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__21 = 5'h15 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__22 = 5'h16 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__23 = 5'h17 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__24 = 5'h18 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__25 = 5'h19 == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__26 = 5'h1a == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__27 = 5'h1b == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__28 = 5'h1c == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__29 = 5'h1d == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__30 = 5'h1e == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value__31 = 5'h1f == data_io_in_bits_wmask_idx_13 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_13_value_1_0 = data_io_in_bits_wmask_dataout_13_value__0 |
- data_io_in_bits_wmask_dataout_13_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_1 = data_io_in_bits_wmask_dataout_13_value__2 |
- data_io_in_bits_wmask_dataout_13_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_2 = data_io_in_bits_wmask_dataout_13_value__4 |
- data_io_in_bits_wmask_dataout_13_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_3 = data_io_in_bits_wmask_dataout_13_value__6 |
- data_io_in_bits_wmask_dataout_13_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_4 = data_io_in_bits_wmask_dataout_13_value__8 |
- data_io_in_bits_wmask_dataout_13_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_5 = data_io_in_bits_wmask_dataout_13_value__10 |
- data_io_in_bits_wmask_dataout_13_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_6 = data_io_in_bits_wmask_dataout_13_value__12 |
- data_io_in_bits_wmask_dataout_13_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_7 = data_io_in_bits_wmask_dataout_13_value__14 |
- data_io_in_bits_wmask_dataout_13_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_8 = data_io_in_bits_wmask_dataout_13_value__16 |
- data_io_in_bits_wmask_dataout_13_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_9 = data_io_in_bits_wmask_dataout_13_value__18 |
- data_io_in_bits_wmask_dataout_13_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_10 = data_io_in_bits_wmask_dataout_13_value__20 |
- data_io_in_bits_wmask_dataout_13_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_11 = data_io_in_bits_wmask_dataout_13_value__22 |
- data_io_in_bits_wmask_dataout_13_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_12 = data_io_in_bits_wmask_dataout_13_value__24 |
- data_io_in_bits_wmask_dataout_13_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_13 = data_io_in_bits_wmask_dataout_13_value__26 |
- data_io_in_bits_wmask_dataout_13_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_14 = data_io_in_bits_wmask_dataout_13_value__28 |
- data_io_in_bits_wmask_dataout_13_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_1_15 = data_io_in_bits_wmask_dataout_13_value__30 |
- data_io_in_bits_wmask_dataout_13_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_2_0 = data_io_in_bits_wmask_dataout_13_value_1_0 |
- data_io_in_bits_wmask_dataout_13_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_2_1 = data_io_in_bits_wmask_dataout_13_value_1_2 |
- data_io_in_bits_wmask_dataout_13_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_2_2 = data_io_in_bits_wmask_dataout_13_value_1_4 |
- data_io_in_bits_wmask_dataout_13_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_2_3 = data_io_in_bits_wmask_dataout_13_value_1_6 |
- data_io_in_bits_wmask_dataout_13_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_2_4 = data_io_in_bits_wmask_dataout_13_value_1_8 |
- data_io_in_bits_wmask_dataout_13_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_2_5 = data_io_in_bits_wmask_dataout_13_value_1_10 |
- data_io_in_bits_wmask_dataout_13_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_2_6 = data_io_in_bits_wmask_dataout_13_value_1_12 |
- data_io_in_bits_wmask_dataout_13_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_2_7 = data_io_in_bits_wmask_dataout_13_value_1_14 |
- data_io_in_bits_wmask_dataout_13_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_3_0 = data_io_in_bits_wmask_dataout_13_value_2_0 |
- data_io_in_bits_wmask_dataout_13_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_3_1 = data_io_in_bits_wmask_dataout_13_value_2_2 |
- data_io_in_bits_wmask_dataout_13_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_3_2 = data_io_in_bits_wmask_dataout_13_value_2_4 |
- data_io_in_bits_wmask_dataout_13_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_3_3 = data_io_in_bits_wmask_dataout_13_value_2_6 |
- data_io_in_bits_wmask_dataout_13_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_4_0 = data_io_in_bits_wmask_dataout_13_value_3_0 |
- data_io_in_bits_wmask_dataout_13_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_4_1 = data_io_in_bits_wmask_dataout_13_value_3_2 |
- data_io_in_bits_wmask_dataout_13_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_13_value_5_0 = data_io_in_bits_wmask_dataout_13_value_4_0 |
- data_io_in_bits_wmask_dataout_13_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_14 = 5'he - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_14_value__0 = 5'h0 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__1 = 5'h1 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__2 = 5'h2 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__3 = 5'h3 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__4 = 5'h4 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__5 = 5'h5 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__6 = 5'h6 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__7 = 5'h7 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__8 = 5'h8 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__9 = 5'h9 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__10 = 5'ha == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__11 = 5'hb == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__12 = 5'hc == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__13 = 5'hd == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__14 = 5'he == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__15 = 5'hf == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__16 = 5'h10 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__17 = 5'h11 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__18 = 5'h12 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__19 = 5'h13 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__20 = 5'h14 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__21 = 5'h15 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__22 = 5'h16 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__23 = 5'h17 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__24 = 5'h18 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__25 = 5'h19 == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__26 = 5'h1a == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__27 = 5'h1b == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__28 = 5'h1c == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__29 = 5'h1d == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__30 = 5'h1e == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value__31 = 5'h1f == data_io_in_bits_wmask_idx_14 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_14_value_1_0 = data_io_in_bits_wmask_dataout_14_value__0 |
- data_io_in_bits_wmask_dataout_14_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_1 = data_io_in_bits_wmask_dataout_14_value__2 |
- data_io_in_bits_wmask_dataout_14_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_2 = data_io_in_bits_wmask_dataout_14_value__4 |
- data_io_in_bits_wmask_dataout_14_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_3 = data_io_in_bits_wmask_dataout_14_value__6 |
- data_io_in_bits_wmask_dataout_14_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_4 = data_io_in_bits_wmask_dataout_14_value__8 |
- data_io_in_bits_wmask_dataout_14_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_5 = data_io_in_bits_wmask_dataout_14_value__10 |
- data_io_in_bits_wmask_dataout_14_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_6 = data_io_in_bits_wmask_dataout_14_value__12 |
- data_io_in_bits_wmask_dataout_14_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_7 = data_io_in_bits_wmask_dataout_14_value__14 |
- data_io_in_bits_wmask_dataout_14_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_8 = data_io_in_bits_wmask_dataout_14_value__16 |
- data_io_in_bits_wmask_dataout_14_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_9 = data_io_in_bits_wmask_dataout_14_value__18 |
- data_io_in_bits_wmask_dataout_14_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_10 = data_io_in_bits_wmask_dataout_14_value__20 |
- data_io_in_bits_wmask_dataout_14_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_11 = data_io_in_bits_wmask_dataout_14_value__22 |
- data_io_in_bits_wmask_dataout_14_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_12 = data_io_in_bits_wmask_dataout_14_value__24 |
- data_io_in_bits_wmask_dataout_14_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_13 = data_io_in_bits_wmask_dataout_14_value__26 |
- data_io_in_bits_wmask_dataout_14_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_14 = data_io_in_bits_wmask_dataout_14_value__28 |
- data_io_in_bits_wmask_dataout_14_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_1_15 = data_io_in_bits_wmask_dataout_14_value__30 |
- data_io_in_bits_wmask_dataout_14_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_2_0 = data_io_in_bits_wmask_dataout_14_value_1_0 |
- data_io_in_bits_wmask_dataout_14_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_2_1 = data_io_in_bits_wmask_dataout_14_value_1_2 |
- data_io_in_bits_wmask_dataout_14_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_2_2 = data_io_in_bits_wmask_dataout_14_value_1_4 |
- data_io_in_bits_wmask_dataout_14_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_2_3 = data_io_in_bits_wmask_dataout_14_value_1_6 |
- data_io_in_bits_wmask_dataout_14_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_2_4 = data_io_in_bits_wmask_dataout_14_value_1_8 |
- data_io_in_bits_wmask_dataout_14_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_2_5 = data_io_in_bits_wmask_dataout_14_value_1_10 |
- data_io_in_bits_wmask_dataout_14_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_2_6 = data_io_in_bits_wmask_dataout_14_value_1_12 |
- data_io_in_bits_wmask_dataout_14_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_2_7 = data_io_in_bits_wmask_dataout_14_value_1_14 |
- data_io_in_bits_wmask_dataout_14_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_3_0 = data_io_in_bits_wmask_dataout_14_value_2_0 |
- data_io_in_bits_wmask_dataout_14_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_3_1 = data_io_in_bits_wmask_dataout_14_value_2_2 |
- data_io_in_bits_wmask_dataout_14_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_3_2 = data_io_in_bits_wmask_dataout_14_value_2_4 |
- data_io_in_bits_wmask_dataout_14_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_3_3 = data_io_in_bits_wmask_dataout_14_value_2_6 |
- data_io_in_bits_wmask_dataout_14_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_4_0 = data_io_in_bits_wmask_dataout_14_value_3_0 |
- data_io_in_bits_wmask_dataout_14_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_4_1 = data_io_in_bits_wmask_dataout_14_value_3_2 |
- data_io_in_bits_wmask_dataout_14_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_14_value_5_0 = data_io_in_bits_wmask_dataout_14_value_4_0 |
- data_io_in_bits_wmask_dataout_14_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_15 = 5'hf - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_15_value__0 = 5'h0 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__1 = 5'h1 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__2 = 5'h2 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__3 = 5'h3 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__4 = 5'h4 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__5 = 5'h5 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__6 = 5'h6 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__7 = 5'h7 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__8 = 5'h8 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__9 = 5'h9 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__10 = 5'ha == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__11 = 5'hb == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__12 = 5'hc == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__13 = 5'hd == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__14 = 5'he == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__15 = 5'hf == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__16 = 5'h10 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__17 = 5'h11 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__18 = 5'h12 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__19 = 5'h13 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__20 = 5'h14 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__21 = 5'h15 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__22 = 5'h16 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__23 = 5'h17 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__24 = 5'h18 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__25 = 5'h19 == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__26 = 5'h1a == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__27 = 5'h1b == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__28 = 5'h1c == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__29 = 5'h1d == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__30 = 5'h1e == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value__31 = 5'h1f == data_io_in_bits_wmask_idx_15 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_15_value_1_0 = data_io_in_bits_wmask_dataout_15_value__0 |
- data_io_in_bits_wmask_dataout_15_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_1 = data_io_in_bits_wmask_dataout_15_value__2 |
- data_io_in_bits_wmask_dataout_15_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_2 = data_io_in_bits_wmask_dataout_15_value__4 |
- data_io_in_bits_wmask_dataout_15_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_3 = data_io_in_bits_wmask_dataout_15_value__6 |
- data_io_in_bits_wmask_dataout_15_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_4 = data_io_in_bits_wmask_dataout_15_value__8 |
- data_io_in_bits_wmask_dataout_15_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_5 = data_io_in_bits_wmask_dataout_15_value__10 |
- data_io_in_bits_wmask_dataout_15_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_6 = data_io_in_bits_wmask_dataout_15_value__12 |
- data_io_in_bits_wmask_dataout_15_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_7 = data_io_in_bits_wmask_dataout_15_value__14 |
- data_io_in_bits_wmask_dataout_15_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_8 = data_io_in_bits_wmask_dataout_15_value__16 |
- data_io_in_bits_wmask_dataout_15_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_9 = data_io_in_bits_wmask_dataout_15_value__18 |
- data_io_in_bits_wmask_dataout_15_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_10 = data_io_in_bits_wmask_dataout_15_value__20 |
- data_io_in_bits_wmask_dataout_15_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_11 = data_io_in_bits_wmask_dataout_15_value__22 |
- data_io_in_bits_wmask_dataout_15_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_12 = data_io_in_bits_wmask_dataout_15_value__24 |
- data_io_in_bits_wmask_dataout_15_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_13 = data_io_in_bits_wmask_dataout_15_value__26 |
- data_io_in_bits_wmask_dataout_15_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_14 = data_io_in_bits_wmask_dataout_15_value__28 |
- data_io_in_bits_wmask_dataout_15_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_1_15 = data_io_in_bits_wmask_dataout_15_value__30 |
- data_io_in_bits_wmask_dataout_15_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_2_0 = data_io_in_bits_wmask_dataout_15_value_1_0 |
- data_io_in_bits_wmask_dataout_15_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_2_1 = data_io_in_bits_wmask_dataout_15_value_1_2 |
- data_io_in_bits_wmask_dataout_15_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_2_2 = data_io_in_bits_wmask_dataout_15_value_1_4 |
- data_io_in_bits_wmask_dataout_15_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_2_3 = data_io_in_bits_wmask_dataout_15_value_1_6 |
- data_io_in_bits_wmask_dataout_15_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_2_4 = data_io_in_bits_wmask_dataout_15_value_1_8 |
- data_io_in_bits_wmask_dataout_15_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_2_5 = data_io_in_bits_wmask_dataout_15_value_1_10 |
- data_io_in_bits_wmask_dataout_15_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_2_6 = data_io_in_bits_wmask_dataout_15_value_1_12 |
- data_io_in_bits_wmask_dataout_15_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_2_7 = data_io_in_bits_wmask_dataout_15_value_1_14 |
- data_io_in_bits_wmask_dataout_15_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_3_0 = data_io_in_bits_wmask_dataout_15_value_2_0 |
- data_io_in_bits_wmask_dataout_15_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_3_1 = data_io_in_bits_wmask_dataout_15_value_2_2 |
- data_io_in_bits_wmask_dataout_15_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_3_2 = data_io_in_bits_wmask_dataout_15_value_2_4 |
- data_io_in_bits_wmask_dataout_15_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_3_3 = data_io_in_bits_wmask_dataout_15_value_2_6 |
- data_io_in_bits_wmask_dataout_15_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_4_0 = data_io_in_bits_wmask_dataout_15_value_3_0 |
- data_io_in_bits_wmask_dataout_15_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_4_1 = data_io_in_bits_wmask_dataout_15_value_3_2 |
- data_io_in_bits_wmask_dataout_15_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_15_value_5_0 = data_io_in_bits_wmask_dataout_15_value_4_0 |
- data_io_in_bits_wmask_dataout_15_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_16 = 5'h10 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_16_value__0 = 5'h0 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__1 = 5'h1 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__2 = 5'h2 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__3 = 5'h3 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__4 = 5'h4 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__5 = 5'h5 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__6 = 5'h6 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__7 = 5'h7 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__8 = 5'h8 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__9 = 5'h9 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__10 = 5'ha == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__11 = 5'hb == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__12 = 5'hc == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__13 = 5'hd == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__14 = 5'he == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__15 = 5'hf == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__16 = 5'h10 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__17 = 5'h11 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__18 = 5'h12 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__19 = 5'h13 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__20 = 5'h14 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__21 = 5'h15 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__22 = 5'h16 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__23 = 5'h17 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__24 = 5'h18 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__25 = 5'h19 == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__26 = 5'h1a == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__27 = 5'h1b == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__28 = 5'h1c == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__29 = 5'h1d == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__30 = 5'h1e == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value__31 = 5'h1f == data_io_in_bits_wmask_idx_16 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_16_value_1_0 = data_io_in_bits_wmask_dataout_16_value__0 |
- data_io_in_bits_wmask_dataout_16_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_1 = data_io_in_bits_wmask_dataout_16_value__2 |
- data_io_in_bits_wmask_dataout_16_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_2 = data_io_in_bits_wmask_dataout_16_value__4 |
- data_io_in_bits_wmask_dataout_16_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_3 = data_io_in_bits_wmask_dataout_16_value__6 |
- data_io_in_bits_wmask_dataout_16_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_4 = data_io_in_bits_wmask_dataout_16_value__8 |
- data_io_in_bits_wmask_dataout_16_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_5 = data_io_in_bits_wmask_dataout_16_value__10 |
- data_io_in_bits_wmask_dataout_16_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_6 = data_io_in_bits_wmask_dataout_16_value__12 |
- data_io_in_bits_wmask_dataout_16_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_7 = data_io_in_bits_wmask_dataout_16_value__14 |
- data_io_in_bits_wmask_dataout_16_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_8 = data_io_in_bits_wmask_dataout_16_value__16 |
- data_io_in_bits_wmask_dataout_16_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_9 = data_io_in_bits_wmask_dataout_16_value__18 |
- data_io_in_bits_wmask_dataout_16_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_10 = data_io_in_bits_wmask_dataout_16_value__20 |
- data_io_in_bits_wmask_dataout_16_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_11 = data_io_in_bits_wmask_dataout_16_value__22 |
- data_io_in_bits_wmask_dataout_16_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_12 = data_io_in_bits_wmask_dataout_16_value__24 |
- data_io_in_bits_wmask_dataout_16_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_13 = data_io_in_bits_wmask_dataout_16_value__26 |
- data_io_in_bits_wmask_dataout_16_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_14 = data_io_in_bits_wmask_dataout_16_value__28 |
- data_io_in_bits_wmask_dataout_16_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_1_15 = data_io_in_bits_wmask_dataout_16_value__30 |
- data_io_in_bits_wmask_dataout_16_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_2_0 = data_io_in_bits_wmask_dataout_16_value_1_0 |
- data_io_in_bits_wmask_dataout_16_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_2_1 = data_io_in_bits_wmask_dataout_16_value_1_2 |
- data_io_in_bits_wmask_dataout_16_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_2_2 = data_io_in_bits_wmask_dataout_16_value_1_4 |
- data_io_in_bits_wmask_dataout_16_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_2_3 = data_io_in_bits_wmask_dataout_16_value_1_6 |
- data_io_in_bits_wmask_dataout_16_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_2_4 = data_io_in_bits_wmask_dataout_16_value_1_8 |
- data_io_in_bits_wmask_dataout_16_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_2_5 = data_io_in_bits_wmask_dataout_16_value_1_10 |
- data_io_in_bits_wmask_dataout_16_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_2_6 = data_io_in_bits_wmask_dataout_16_value_1_12 |
- data_io_in_bits_wmask_dataout_16_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_2_7 = data_io_in_bits_wmask_dataout_16_value_1_14 |
- data_io_in_bits_wmask_dataout_16_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_3_0 = data_io_in_bits_wmask_dataout_16_value_2_0 |
- data_io_in_bits_wmask_dataout_16_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_3_1 = data_io_in_bits_wmask_dataout_16_value_2_2 |
- data_io_in_bits_wmask_dataout_16_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_3_2 = data_io_in_bits_wmask_dataout_16_value_2_4 |
- data_io_in_bits_wmask_dataout_16_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_3_3 = data_io_in_bits_wmask_dataout_16_value_2_6 |
- data_io_in_bits_wmask_dataout_16_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_4_0 = data_io_in_bits_wmask_dataout_16_value_3_0 |
- data_io_in_bits_wmask_dataout_16_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_4_1 = data_io_in_bits_wmask_dataout_16_value_3_2 |
- data_io_in_bits_wmask_dataout_16_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_16_value_5_0 = data_io_in_bits_wmask_dataout_16_value_4_0 |
- data_io_in_bits_wmask_dataout_16_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_17 = 5'h11 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_17_value__0 = 5'h0 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__1 = 5'h1 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__2 = 5'h2 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__3 = 5'h3 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__4 = 5'h4 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__5 = 5'h5 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__6 = 5'h6 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__7 = 5'h7 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__8 = 5'h8 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__9 = 5'h9 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__10 = 5'ha == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__11 = 5'hb == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__12 = 5'hc == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__13 = 5'hd == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__14 = 5'he == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__15 = 5'hf == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__16 = 5'h10 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__17 = 5'h11 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__18 = 5'h12 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__19 = 5'h13 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__20 = 5'h14 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__21 = 5'h15 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__22 = 5'h16 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__23 = 5'h17 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__24 = 5'h18 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__25 = 5'h19 == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__26 = 5'h1a == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__27 = 5'h1b == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__28 = 5'h1c == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__29 = 5'h1d == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__30 = 5'h1e == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value__31 = 5'h1f == data_io_in_bits_wmask_idx_17 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_17_value_1_0 = data_io_in_bits_wmask_dataout_17_value__0 |
- data_io_in_bits_wmask_dataout_17_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_1 = data_io_in_bits_wmask_dataout_17_value__2 |
- data_io_in_bits_wmask_dataout_17_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_2 = data_io_in_bits_wmask_dataout_17_value__4 |
- data_io_in_bits_wmask_dataout_17_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_3 = data_io_in_bits_wmask_dataout_17_value__6 |
- data_io_in_bits_wmask_dataout_17_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_4 = data_io_in_bits_wmask_dataout_17_value__8 |
- data_io_in_bits_wmask_dataout_17_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_5 = data_io_in_bits_wmask_dataout_17_value__10 |
- data_io_in_bits_wmask_dataout_17_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_6 = data_io_in_bits_wmask_dataout_17_value__12 |
- data_io_in_bits_wmask_dataout_17_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_7 = data_io_in_bits_wmask_dataout_17_value__14 |
- data_io_in_bits_wmask_dataout_17_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_8 = data_io_in_bits_wmask_dataout_17_value__16 |
- data_io_in_bits_wmask_dataout_17_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_9 = data_io_in_bits_wmask_dataout_17_value__18 |
- data_io_in_bits_wmask_dataout_17_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_10 = data_io_in_bits_wmask_dataout_17_value__20 |
- data_io_in_bits_wmask_dataout_17_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_11 = data_io_in_bits_wmask_dataout_17_value__22 |
- data_io_in_bits_wmask_dataout_17_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_12 = data_io_in_bits_wmask_dataout_17_value__24 |
- data_io_in_bits_wmask_dataout_17_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_13 = data_io_in_bits_wmask_dataout_17_value__26 |
- data_io_in_bits_wmask_dataout_17_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_14 = data_io_in_bits_wmask_dataout_17_value__28 |
- data_io_in_bits_wmask_dataout_17_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_1_15 = data_io_in_bits_wmask_dataout_17_value__30 |
- data_io_in_bits_wmask_dataout_17_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_2_0 = data_io_in_bits_wmask_dataout_17_value_1_0 |
- data_io_in_bits_wmask_dataout_17_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_2_1 = data_io_in_bits_wmask_dataout_17_value_1_2 |
- data_io_in_bits_wmask_dataout_17_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_2_2 = data_io_in_bits_wmask_dataout_17_value_1_4 |
- data_io_in_bits_wmask_dataout_17_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_2_3 = data_io_in_bits_wmask_dataout_17_value_1_6 |
- data_io_in_bits_wmask_dataout_17_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_2_4 = data_io_in_bits_wmask_dataout_17_value_1_8 |
- data_io_in_bits_wmask_dataout_17_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_2_5 = data_io_in_bits_wmask_dataout_17_value_1_10 |
- data_io_in_bits_wmask_dataout_17_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_2_6 = data_io_in_bits_wmask_dataout_17_value_1_12 |
- data_io_in_bits_wmask_dataout_17_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_2_7 = data_io_in_bits_wmask_dataout_17_value_1_14 |
- data_io_in_bits_wmask_dataout_17_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_3_0 = data_io_in_bits_wmask_dataout_17_value_2_0 |
- data_io_in_bits_wmask_dataout_17_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_3_1 = data_io_in_bits_wmask_dataout_17_value_2_2 |
- data_io_in_bits_wmask_dataout_17_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_3_2 = data_io_in_bits_wmask_dataout_17_value_2_4 |
- data_io_in_bits_wmask_dataout_17_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_3_3 = data_io_in_bits_wmask_dataout_17_value_2_6 |
- data_io_in_bits_wmask_dataout_17_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_4_0 = data_io_in_bits_wmask_dataout_17_value_3_0 |
- data_io_in_bits_wmask_dataout_17_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_4_1 = data_io_in_bits_wmask_dataout_17_value_3_2 |
- data_io_in_bits_wmask_dataout_17_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_17_value_5_0 = data_io_in_bits_wmask_dataout_17_value_4_0 |
- data_io_in_bits_wmask_dataout_17_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_18 = 5'h12 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_18_value__0 = 5'h0 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__1 = 5'h1 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__2 = 5'h2 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__3 = 5'h3 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__4 = 5'h4 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__5 = 5'h5 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__6 = 5'h6 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__7 = 5'h7 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__8 = 5'h8 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__9 = 5'h9 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__10 = 5'ha == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__11 = 5'hb == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__12 = 5'hc == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__13 = 5'hd == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__14 = 5'he == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__15 = 5'hf == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__16 = 5'h10 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__17 = 5'h11 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__18 = 5'h12 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__19 = 5'h13 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__20 = 5'h14 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__21 = 5'h15 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__22 = 5'h16 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__23 = 5'h17 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__24 = 5'h18 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__25 = 5'h19 == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__26 = 5'h1a == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__27 = 5'h1b == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__28 = 5'h1c == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__29 = 5'h1d == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__30 = 5'h1e == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value__31 = 5'h1f == data_io_in_bits_wmask_idx_18 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_18_value_1_0 = data_io_in_bits_wmask_dataout_18_value__0 |
- data_io_in_bits_wmask_dataout_18_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_1 = data_io_in_bits_wmask_dataout_18_value__2 |
- data_io_in_bits_wmask_dataout_18_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_2 = data_io_in_bits_wmask_dataout_18_value__4 |
- data_io_in_bits_wmask_dataout_18_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_3 = data_io_in_bits_wmask_dataout_18_value__6 |
- data_io_in_bits_wmask_dataout_18_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_4 = data_io_in_bits_wmask_dataout_18_value__8 |
- data_io_in_bits_wmask_dataout_18_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_5 = data_io_in_bits_wmask_dataout_18_value__10 |
- data_io_in_bits_wmask_dataout_18_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_6 = data_io_in_bits_wmask_dataout_18_value__12 |
- data_io_in_bits_wmask_dataout_18_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_7 = data_io_in_bits_wmask_dataout_18_value__14 |
- data_io_in_bits_wmask_dataout_18_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_8 = data_io_in_bits_wmask_dataout_18_value__16 |
- data_io_in_bits_wmask_dataout_18_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_9 = data_io_in_bits_wmask_dataout_18_value__18 |
- data_io_in_bits_wmask_dataout_18_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_10 = data_io_in_bits_wmask_dataout_18_value__20 |
- data_io_in_bits_wmask_dataout_18_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_11 = data_io_in_bits_wmask_dataout_18_value__22 |
- data_io_in_bits_wmask_dataout_18_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_12 = data_io_in_bits_wmask_dataout_18_value__24 |
- data_io_in_bits_wmask_dataout_18_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_13 = data_io_in_bits_wmask_dataout_18_value__26 |
- data_io_in_bits_wmask_dataout_18_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_14 = data_io_in_bits_wmask_dataout_18_value__28 |
- data_io_in_bits_wmask_dataout_18_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_1_15 = data_io_in_bits_wmask_dataout_18_value__30 |
- data_io_in_bits_wmask_dataout_18_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_2_0 = data_io_in_bits_wmask_dataout_18_value_1_0 |
- data_io_in_bits_wmask_dataout_18_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_2_1 = data_io_in_bits_wmask_dataout_18_value_1_2 |
- data_io_in_bits_wmask_dataout_18_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_2_2 = data_io_in_bits_wmask_dataout_18_value_1_4 |
- data_io_in_bits_wmask_dataout_18_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_2_3 = data_io_in_bits_wmask_dataout_18_value_1_6 |
- data_io_in_bits_wmask_dataout_18_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_2_4 = data_io_in_bits_wmask_dataout_18_value_1_8 |
- data_io_in_bits_wmask_dataout_18_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_2_5 = data_io_in_bits_wmask_dataout_18_value_1_10 |
- data_io_in_bits_wmask_dataout_18_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_2_6 = data_io_in_bits_wmask_dataout_18_value_1_12 |
- data_io_in_bits_wmask_dataout_18_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_2_7 = data_io_in_bits_wmask_dataout_18_value_1_14 |
- data_io_in_bits_wmask_dataout_18_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_3_0 = data_io_in_bits_wmask_dataout_18_value_2_0 |
- data_io_in_bits_wmask_dataout_18_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_3_1 = data_io_in_bits_wmask_dataout_18_value_2_2 |
- data_io_in_bits_wmask_dataout_18_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_3_2 = data_io_in_bits_wmask_dataout_18_value_2_4 |
- data_io_in_bits_wmask_dataout_18_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_3_3 = data_io_in_bits_wmask_dataout_18_value_2_6 |
- data_io_in_bits_wmask_dataout_18_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_4_0 = data_io_in_bits_wmask_dataout_18_value_3_0 |
- data_io_in_bits_wmask_dataout_18_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_4_1 = data_io_in_bits_wmask_dataout_18_value_3_2 |
- data_io_in_bits_wmask_dataout_18_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_18_value_5_0 = data_io_in_bits_wmask_dataout_18_value_4_0 |
- data_io_in_bits_wmask_dataout_18_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_19 = 5'h13 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_19_value__0 = 5'h0 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__1 = 5'h1 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__2 = 5'h2 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__3 = 5'h3 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__4 = 5'h4 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__5 = 5'h5 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__6 = 5'h6 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__7 = 5'h7 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__8 = 5'h8 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__9 = 5'h9 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__10 = 5'ha == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__11 = 5'hb == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__12 = 5'hc == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__13 = 5'hd == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__14 = 5'he == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__15 = 5'hf == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__16 = 5'h10 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__17 = 5'h11 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__18 = 5'h12 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__19 = 5'h13 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__20 = 5'h14 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__21 = 5'h15 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__22 = 5'h16 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__23 = 5'h17 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__24 = 5'h18 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__25 = 5'h19 == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__26 = 5'h1a == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__27 = 5'h1b == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__28 = 5'h1c == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__29 = 5'h1d == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__30 = 5'h1e == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value__31 = 5'h1f == data_io_in_bits_wmask_idx_19 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_19_value_1_0 = data_io_in_bits_wmask_dataout_19_value__0 |
- data_io_in_bits_wmask_dataout_19_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_1 = data_io_in_bits_wmask_dataout_19_value__2 |
- data_io_in_bits_wmask_dataout_19_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_2 = data_io_in_bits_wmask_dataout_19_value__4 |
- data_io_in_bits_wmask_dataout_19_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_3 = data_io_in_bits_wmask_dataout_19_value__6 |
- data_io_in_bits_wmask_dataout_19_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_4 = data_io_in_bits_wmask_dataout_19_value__8 |
- data_io_in_bits_wmask_dataout_19_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_5 = data_io_in_bits_wmask_dataout_19_value__10 |
- data_io_in_bits_wmask_dataout_19_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_6 = data_io_in_bits_wmask_dataout_19_value__12 |
- data_io_in_bits_wmask_dataout_19_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_7 = data_io_in_bits_wmask_dataout_19_value__14 |
- data_io_in_bits_wmask_dataout_19_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_8 = data_io_in_bits_wmask_dataout_19_value__16 |
- data_io_in_bits_wmask_dataout_19_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_9 = data_io_in_bits_wmask_dataout_19_value__18 |
- data_io_in_bits_wmask_dataout_19_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_10 = data_io_in_bits_wmask_dataout_19_value__20 |
- data_io_in_bits_wmask_dataout_19_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_11 = data_io_in_bits_wmask_dataout_19_value__22 |
- data_io_in_bits_wmask_dataout_19_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_12 = data_io_in_bits_wmask_dataout_19_value__24 |
- data_io_in_bits_wmask_dataout_19_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_13 = data_io_in_bits_wmask_dataout_19_value__26 |
- data_io_in_bits_wmask_dataout_19_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_14 = data_io_in_bits_wmask_dataout_19_value__28 |
- data_io_in_bits_wmask_dataout_19_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_1_15 = data_io_in_bits_wmask_dataout_19_value__30 |
- data_io_in_bits_wmask_dataout_19_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_2_0 = data_io_in_bits_wmask_dataout_19_value_1_0 |
- data_io_in_bits_wmask_dataout_19_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_2_1 = data_io_in_bits_wmask_dataout_19_value_1_2 |
- data_io_in_bits_wmask_dataout_19_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_2_2 = data_io_in_bits_wmask_dataout_19_value_1_4 |
- data_io_in_bits_wmask_dataout_19_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_2_3 = data_io_in_bits_wmask_dataout_19_value_1_6 |
- data_io_in_bits_wmask_dataout_19_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_2_4 = data_io_in_bits_wmask_dataout_19_value_1_8 |
- data_io_in_bits_wmask_dataout_19_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_2_5 = data_io_in_bits_wmask_dataout_19_value_1_10 |
- data_io_in_bits_wmask_dataout_19_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_2_6 = data_io_in_bits_wmask_dataout_19_value_1_12 |
- data_io_in_bits_wmask_dataout_19_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_2_7 = data_io_in_bits_wmask_dataout_19_value_1_14 |
- data_io_in_bits_wmask_dataout_19_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_3_0 = data_io_in_bits_wmask_dataout_19_value_2_0 |
- data_io_in_bits_wmask_dataout_19_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_3_1 = data_io_in_bits_wmask_dataout_19_value_2_2 |
- data_io_in_bits_wmask_dataout_19_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_3_2 = data_io_in_bits_wmask_dataout_19_value_2_4 |
- data_io_in_bits_wmask_dataout_19_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_3_3 = data_io_in_bits_wmask_dataout_19_value_2_6 |
- data_io_in_bits_wmask_dataout_19_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_4_0 = data_io_in_bits_wmask_dataout_19_value_3_0 |
- data_io_in_bits_wmask_dataout_19_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_4_1 = data_io_in_bits_wmask_dataout_19_value_3_2 |
- data_io_in_bits_wmask_dataout_19_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_19_value_5_0 = data_io_in_bits_wmask_dataout_19_value_4_0 |
- data_io_in_bits_wmask_dataout_19_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_20 = 5'h14 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_20_value__0 = 5'h0 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__1 = 5'h1 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__2 = 5'h2 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__3 = 5'h3 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__4 = 5'h4 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__5 = 5'h5 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__6 = 5'h6 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__7 = 5'h7 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__8 = 5'h8 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__9 = 5'h9 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__10 = 5'ha == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__11 = 5'hb == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__12 = 5'hc == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__13 = 5'hd == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__14 = 5'he == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__15 = 5'hf == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__16 = 5'h10 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__17 = 5'h11 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__18 = 5'h12 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__19 = 5'h13 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__20 = 5'h14 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__21 = 5'h15 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__22 = 5'h16 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__23 = 5'h17 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__24 = 5'h18 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__25 = 5'h19 == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__26 = 5'h1a == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__27 = 5'h1b == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__28 = 5'h1c == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__29 = 5'h1d == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__30 = 5'h1e == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value__31 = 5'h1f == data_io_in_bits_wmask_idx_20 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_20_value_1_0 = data_io_in_bits_wmask_dataout_20_value__0 |
- data_io_in_bits_wmask_dataout_20_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_1 = data_io_in_bits_wmask_dataout_20_value__2 |
- data_io_in_bits_wmask_dataout_20_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_2 = data_io_in_bits_wmask_dataout_20_value__4 |
- data_io_in_bits_wmask_dataout_20_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_3 = data_io_in_bits_wmask_dataout_20_value__6 |
- data_io_in_bits_wmask_dataout_20_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_4 = data_io_in_bits_wmask_dataout_20_value__8 |
- data_io_in_bits_wmask_dataout_20_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_5 = data_io_in_bits_wmask_dataout_20_value__10 |
- data_io_in_bits_wmask_dataout_20_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_6 = data_io_in_bits_wmask_dataout_20_value__12 |
- data_io_in_bits_wmask_dataout_20_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_7 = data_io_in_bits_wmask_dataout_20_value__14 |
- data_io_in_bits_wmask_dataout_20_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_8 = data_io_in_bits_wmask_dataout_20_value__16 |
- data_io_in_bits_wmask_dataout_20_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_9 = data_io_in_bits_wmask_dataout_20_value__18 |
- data_io_in_bits_wmask_dataout_20_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_10 = data_io_in_bits_wmask_dataout_20_value__20 |
- data_io_in_bits_wmask_dataout_20_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_11 = data_io_in_bits_wmask_dataout_20_value__22 |
- data_io_in_bits_wmask_dataout_20_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_12 = data_io_in_bits_wmask_dataout_20_value__24 |
- data_io_in_bits_wmask_dataout_20_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_13 = data_io_in_bits_wmask_dataout_20_value__26 |
- data_io_in_bits_wmask_dataout_20_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_14 = data_io_in_bits_wmask_dataout_20_value__28 |
- data_io_in_bits_wmask_dataout_20_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_1_15 = data_io_in_bits_wmask_dataout_20_value__30 |
- data_io_in_bits_wmask_dataout_20_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_2_0 = data_io_in_bits_wmask_dataout_20_value_1_0 |
- data_io_in_bits_wmask_dataout_20_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_2_1 = data_io_in_bits_wmask_dataout_20_value_1_2 |
- data_io_in_bits_wmask_dataout_20_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_2_2 = data_io_in_bits_wmask_dataout_20_value_1_4 |
- data_io_in_bits_wmask_dataout_20_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_2_3 = data_io_in_bits_wmask_dataout_20_value_1_6 |
- data_io_in_bits_wmask_dataout_20_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_2_4 = data_io_in_bits_wmask_dataout_20_value_1_8 |
- data_io_in_bits_wmask_dataout_20_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_2_5 = data_io_in_bits_wmask_dataout_20_value_1_10 |
- data_io_in_bits_wmask_dataout_20_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_2_6 = data_io_in_bits_wmask_dataout_20_value_1_12 |
- data_io_in_bits_wmask_dataout_20_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_2_7 = data_io_in_bits_wmask_dataout_20_value_1_14 |
- data_io_in_bits_wmask_dataout_20_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_3_0 = data_io_in_bits_wmask_dataout_20_value_2_0 |
- data_io_in_bits_wmask_dataout_20_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_3_1 = data_io_in_bits_wmask_dataout_20_value_2_2 |
- data_io_in_bits_wmask_dataout_20_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_3_2 = data_io_in_bits_wmask_dataout_20_value_2_4 |
- data_io_in_bits_wmask_dataout_20_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_3_3 = data_io_in_bits_wmask_dataout_20_value_2_6 |
- data_io_in_bits_wmask_dataout_20_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_4_0 = data_io_in_bits_wmask_dataout_20_value_3_0 |
- data_io_in_bits_wmask_dataout_20_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_4_1 = data_io_in_bits_wmask_dataout_20_value_3_2 |
- data_io_in_bits_wmask_dataout_20_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_20_value_5_0 = data_io_in_bits_wmask_dataout_20_value_4_0 |
- data_io_in_bits_wmask_dataout_20_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_21 = 5'h15 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_21_value__0 = 5'h0 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__1 = 5'h1 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__2 = 5'h2 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__3 = 5'h3 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__4 = 5'h4 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__5 = 5'h5 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__6 = 5'h6 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__7 = 5'h7 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__8 = 5'h8 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__9 = 5'h9 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__10 = 5'ha == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__11 = 5'hb == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__12 = 5'hc == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__13 = 5'hd == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__14 = 5'he == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__15 = 5'hf == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__16 = 5'h10 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__17 = 5'h11 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__18 = 5'h12 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__19 = 5'h13 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__20 = 5'h14 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__21 = 5'h15 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__22 = 5'h16 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__23 = 5'h17 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__24 = 5'h18 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__25 = 5'h19 == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__26 = 5'h1a == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__27 = 5'h1b == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__28 = 5'h1c == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__29 = 5'h1d == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__30 = 5'h1e == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value__31 = 5'h1f == data_io_in_bits_wmask_idx_21 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_21_value_1_0 = data_io_in_bits_wmask_dataout_21_value__0 |
- data_io_in_bits_wmask_dataout_21_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_1 = data_io_in_bits_wmask_dataout_21_value__2 |
- data_io_in_bits_wmask_dataout_21_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_2 = data_io_in_bits_wmask_dataout_21_value__4 |
- data_io_in_bits_wmask_dataout_21_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_3 = data_io_in_bits_wmask_dataout_21_value__6 |
- data_io_in_bits_wmask_dataout_21_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_4 = data_io_in_bits_wmask_dataout_21_value__8 |
- data_io_in_bits_wmask_dataout_21_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_5 = data_io_in_bits_wmask_dataout_21_value__10 |
- data_io_in_bits_wmask_dataout_21_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_6 = data_io_in_bits_wmask_dataout_21_value__12 |
- data_io_in_bits_wmask_dataout_21_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_7 = data_io_in_bits_wmask_dataout_21_value__14 |
- data_io_in_bits_wmask_dataout_21_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_8 = data_io_in_bits_wmask_dataout_21_value__16 |
- data_io_in_bits_wmask_dataout_21_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_9 = data_io_in_bits_wmask_dataout_21_value__18 |
- data_io_in_bits_wmask_dataout_21_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_10 = data_io_in_bits_wmask_dataout_21_value__20 |
- data_io_in_bits_wmask_dataout_21_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_11 = data_io_in_bits_wmask_dataout_21_value__22 |
- data_io_in_bits_wmask_dataout_21_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_12 = data_io_in_bits_wmask_dataout_21_value__24 |
- data_io_in_bits_wmask_dataout_21_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_13 = data_io_in_bits_wmask_dataout_21_value__26 |
- data_io_in_bits_wmask_dataout_21_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_14 = data_io_in_bits_wmask_dataout_21_value__28 |
- data_io_in_bits_wmask_dataout_21_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_1_15 = data_io_in_bits_wmask_dataout_21_value__30 |
- data_io_in_bits_wmask_dataout_21_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_2_0 = data_io_in_bits_wmask_dataout_21_value_1_0 |
- data_io_in_bits_wmask_dataout_21_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_2_1 = data_io_in_bits_wmask_dataout_21_value_1_2 |
- data_io_in_bits_wmask_dataout_21_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_2_2 = data_io_in_bits_wmask_dataout_21_value_1_4 |
- data_io_in_bits_wmask_dataout_21_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_2_3 = data_io_in_bits_wmask_dataout_21_value_1_6 |
- data_io_in_bits_wmask_dataout_21_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_2_4 = data_io_in_bits_wmask_dataout_21_value_1_8 |
- data_io_in_bits_wmask_dataout_21_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_2_5 = data_io_in_bits_wmask_dataout_21_value_1_10 |
- data_io_in_bits_wmask_dataout_21_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_2_6 = data_io_in_bits_wmask_dataout_21_value_1_12 |
- data_io_in_bits_wmask_dataout_21_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_2_7 = data_io_in_bits_wmask_dataout_21_value_1_14 |
- data_io_in_bits_wmask_dataout_21_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_3_0 = data_io_in_bits_wmask_dataout_21_value_2_0 |
- data_io_in_bits_wmask_dataout_21_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_3_1 = data_io_in_bits_wmask_dataout_21_value_2_2 |
- data_io_in_bits_wmask_dataout_21_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_3_2 = data_io_in_bits_wmask_dataout_21_value_2_4 |
- data_io_in_bits_wmask_dataout_21_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_3_3 = data_io_in_bits_wmask_dataout_21_value_2_6 |
- data_io_in_bits_wmask_dataout_21_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_4_0 = data_io_in_bits_wmask_dataout_21_value_3_0 |
- data_io_in_bits_wmask_dataout_21_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_4_1 = data_io_in_bits_wmask_dataout_21_value_3_2 |
- data_io_in_bits_wmask_dataout_21_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_21_value_5_0 = data_io_in_bits_wmask_dataout_21_value_4_0 |
- data_io_in_bits_wmask_dataout_21_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_22 = 5'h16 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_22_value__0 = 5'h0 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__1 = 5'h1 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__2 = 5'h2 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__3 = 5'h3 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__4 = 5'h4 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__5 = 5'h5 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__6 = 5'h6 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__7 = 5'h7 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__8 = 5'h8 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__9 = 5'h9 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__10 = 5'ha == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__11 = 5'hb == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__12 = 5'hc == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__13 = 5'hd == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__14 = 5'he == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__15 = 5'hf == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__16 = 5'h10 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__17 = 5'h11 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__18 = 5'h12 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__19 = 5'h13 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__20 = 5'h14 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__21 = 5'h15 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__22 = 5'h16 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__23 = 5'h17 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__24 = 5'h18 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__25 = 5'h19 == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__26 = 5'h1a == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__27 = 5'h1b == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__28 = 5'h1c == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__29 = 5'h1d == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__30 = 5'h1e == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value__31 = 5'h1f == data_io_in_bits_wmask_idx_22 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_22_value_1_0 = data_io_in_bits_wmask_dataout_22_value__0 |
- data_io_in_bits_wmask_dataout_22_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_1 = data_io_in_bits_wmask_dataout_22_value__2 |
- data_io_in_bits_wmask_dataout_22_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_2 = data_io_in_bits_wmask_dataout_22_value__4 |
- data_io_in_bits_wmask_dataout_22_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_3 = data_io_in_bits_wmask_dataout_22_value__6 |
- data_io_in_bits_wmask_dataout_22_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_4 = data_io_in_bits_wmask_dataout_22_value__8 |
- data_io_in_bits_wmask_dataout_22_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_5 = data_io_in_bits_wmask_dataout_22_value__10 |
- data_io_in_bits_wmask_dataout_22_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_6 = data_io_in_bits_wmask_dataout_22_value__12 |
- data_io_in_bits_wmask_dataout_22_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_7 = data_io_in_bits_wmask_dataout_22_value__14 |
- data_io_in_bits_wmask_dataout_22_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_8 = data_io_in_bits_wmask_dataout_22_value__16 |
- data_io_in_bits_wmask_dataout_22_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_9 = data_io_in_bits_wmask_dataout_22_value__18 |
- data_io_in_bits_wmask_dataout_22_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_10 = data_io_in_bits_wmask_dataout_22_value__20 |
- data_io_in_bits_wmask_dataout_22_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_11 = data_io_in_bits_wmask_dataout_22_value__22 |
- data_io_in_bits_wmask_dataout_22_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_12 = data_io_in_bits_wmask_dataout_22_value__24 |
- data_io_in_bits_wmask_dataout_22_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_13 = data_io_in_bits_wmask_dataout_22_value__26 |
- data_io_in_bits_wmask_dataout_22_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_14 = data_io_in_bits_wmask_dataout_22_value__28 |
- data_io_in_bits_wmask_dataout_22_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_1_15 = data_io_in_bits_wmask_dataout_22_value__30 |
- data_io_in_bits_wmask_dataout_22_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_2_0 = data_io_in_bits_wmask_dataout_22_value_1_0 |
- data_io_in_bits_wmask_dataout_22_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_2_1 = data_io_in_bits_wmask_dataout_22_value_1_2 |
- data_io_in_bits_wmask_dataout_22_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_2_2 = data_io_in_bits_wmask_dataout_22_value_1_4 |
- data_io_in_bits_wmask_dataout_22_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_2_3 = data_io_in_bits_wmask_dataout_22_value_1_6 |
- data_io_in_bits_wmask_dataout_22_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_2_4 = data_io_in_bits_wmask_dataout_22_value_1_8 |
- data_io_in_bits_wmask_dataout_22_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_2_5 = data_io_in_bits_wmask_dataout_22_value_1_10 |
- data_io_in_bits_wmask_dataout_22_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_2_6 = data_io_in_bits_wmask_dataout_22_value_1_12 |
- data_io_in_bits_wmask_dataout_22_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_2_7 = data_io_in_bits_wmask_dataout_22_value_1_14 |
- data_io_in_bits_wmask_dataout_22_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_3_0 = data_io_in_bits_wmask_dataout_22_value_2_0 |
- data_io_in_bits_wmask_dataout_22_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_3_1 = data_io_in_bits_wmask_dataout_22_value_2_2 |
- data_io_in_bits_wmask_dataout_22_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_3_2 = data_io_in_bits_wmask_dataout_22_value_2_4 |
- data_io_in_bits_wmask_dataout_22_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_3_3 = data_io_in_bits_wmask_dataout_22_value_2_6 |
- data_io_in_bits_wmask_dataout_22_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_4_0 = data_io_in_bits_wmask_dataout_22_value_3_0 |
- data_io_in_bits_wmask_dataout_22_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_4_1 = data_io_in_bits_wmask_dataout_22_value_3_2 |
- data_io_in_bits_wmask_dataout_22_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_22_value_5_0 = data_io_in_bits_wmask_dataout_22_value_4_0 |
- data_io_in_bits_wmask_dataout_22_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_23 = 5'h17 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_23_value__0 = 5'h0 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__1 = 5'h1 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__2 = 5'h2 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__3 = 5'h3 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__4 = 5'h4 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__5 = 5'h5 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__6 = 5'h6 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__7 = 5'h7 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__8 = 5'h8 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__9 = 5'h9 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__10 = 5'ha == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__11 = 5'hb == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__12 = 5'hc == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__13 = 5'hd == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__14 = 5'he == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__15 = 5'hf == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__16 = 5'h10 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__17 = 5'h11 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__18 = 5'h12 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__19 = 5'h13 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__20 = 5'h14 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__21 = 5'h15 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__22 = 5'h16 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__23 = 5'h17 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__24 = 5'h18 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__25 = 5'h19 == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__26 = 5'h1a == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__27 = 5'h1b == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__28 = 5'h1c == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__29 = 5'h1d == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__30 = 5'h1e == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value__31 = 5'h1f == data_io_in_bits_wmask_idx_23 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_23_value_1_0 = data_io_in_bits_wmask_dataout_23_value__0 |
- data_io_in_bits_wmask_dataout_23_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_1 = data_io_in_bits_wmask_dataout_23_value__2 |
- data_io_in_bits_wmask_dataout_23_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_2 = data_io_in_bits_wmask_dataout_23_value__4 |
- data_io_in_bits_wmask_dataout_23_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_3 = data_io_in_bits_wmask_dataout_23_value__6 |
- data_io_in_bits_wmask_dataout_23_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_4 = data_io_in_bits_wmask_dataout_23_value__8 |
- data_io_in_bits_wmask_dataout_23_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_5 = data_io_in_bits_wmask_dataout_23_value__10 |
- data_io_in_bits_wmask_dataout_23_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_6 = data_io_in_bits_wmask_dataout_23_value__12 |
- data_io_in_bits_wmask_dataout_23_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_7 = data_io_in_bits_wmask_dataout_23_value__14 |
- data_io_in_bits_wmask_dataout_23_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_8 = data_io_in_bits_wmask_dataout_23_value__16 |
- data_io_in_bits_wmask_dataout_23_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_9 = data_io_in_bits_wmask_dataout_23_value__18 |
- data_io_in_bits_wmask_dataout_23_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_10 = data_io_in_bits_wmask_dataout_23_value__20 |
- data_io_in_bits_wmask_dataout_23_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_11 = data_io_in_bits_wmask_dataout_23_value__22 |
- data_io_in_bits_wmask_dataout_23_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_12 = data_io_in_bits_wmask_dataout_23_value__24 |
- data_io_in_bits_wmask_dataout_23_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_13 = data_io_in_bits_wmask_dataout_23_value__26 |
- data_io_in_bits_wmask_dataout_23_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_14 = data_io_in_bits_wmask_dataout_23_value__28 |
- data_io_in_bits_wmask_dataout_23_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_1_15 = data_io_in_bits_wmask_dataout_23_value__30 |
- data_io_in_bits_wmask_dataout_23_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_2_0 = data_io_in_bits_wmask_dataout_23_value_1_0 |
- data_io_in_bits_wmask_dataout_23_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_2_1 = data_io_in_bits_wmask_dataout_23_value_1_2 |
- data_io_in_bits_wmask_dataout_23_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_2_2 = data_io_in_bits_wmask_dataout_23_value_1_4 |
- data_io_in_bits_wmask_dataout_23_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_2_3 = data_io_in_bits_wmask_dataout_23_value_1_6 |
- data_io_in_bits_wmask_dataout_23_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_2_4 = data_io_in_bits_wmask_dataout_23_value_1_8 |
- data_io_in_bits_wmask_dataout_23_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_2_5 = data_io_in_bits_wmask_dataout_23_value_1_10 |
- data_io_in_bits_wmask_dataout_23_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_2_6 = data_io_in_bits_wmask_dataout_23_value_1_12 |
- data_io_in_bits_wmask_dataout_23_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_2_7 = data_io_in_bits_wmask_dataout_23_value_1_14 |
- data_io_in_bits_wmask_dataout_23_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_3_0 = data_io_in_bits_wmask_dataout_23_value_2_0 |
- data_io_in_bits_wmask_dataout_23_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_3_1 = data_io_in_bits_wmask_dataout_23_value_2_2 |
- data_io_in_bits_wmask_dataout_23_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_3_2 = data_io_in_bits_wmask_dataout_23_value_2_4 |
- data_io_in_bits_wmask_dataout_23_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_3_3 = data_io_in_bits_wmask_dataout_23_value_2_6 |
- data_io_in_bits_wmask_dataout_23_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_4_0 = data_io_in_bits_wmask_dataout_23_value_3_0 |
- data_io_in_bits_wmask_dataout_23_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_4_1 = data_io_in_bits_wmask_dataout_23_value_3_2 |
- data_io_in_bits_wmask_dataout_23_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_23_value_5_0 = data_io_in_bits_wmask_dataout_23_value_4_0 |
- data_io_in_bits_wmask_dataout_23_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_24 = 5'h18 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_24_value__0 = 5'h0 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__1 = 5'h1 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__2 = 5'h2 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__3 = 5'h3 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__4 = 5'h4 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__5 = 5'h5 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__6 = 5'h6 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__7 = 5'h7 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__8 = 5'h8 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__9 = 5'h9 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__10 = 5'ha == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__11 = 5'hb == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__12 = 5'hc == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__13 = 5'hd == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__14 = 5'he == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__15 = 5'hf == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__16 = 5'h10 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__17 = 5'h11 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__18 = 5'h12 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__19 = 5'h13 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__20 = 5'h14 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__21 = 5'h15 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__22 = 5'h16 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__23 = 5'h17 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__24 = 5'h18 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__25 = 5'h19 == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__26 = 5'h1a == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__27 = 5'h1b == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__28 = 5'h1c == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__29 = 5'h1d == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__30 = 5'h1e == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value__31 = 5'h1f == data_io_in_bits_wmask_idx_24 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_24_value_1_0 = data_io_in_bits_wmask_dataout_24_value__0 |
- data_io_in_bits_wmask_dataout_24_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_1 = data_io_in_bits_wmask_dataout_24_value__2 |
- data_io_in_bits_wmask_dataout_24_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_2 = data_io_in_bits_wmask_dataout_24_value__4 |
- data_io_in_bits_wmask_dataout_24_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_3 = data_io_in_bits_wmask_dataout_24_value__6 |
- data_io_in_bits_wmask_dataout_24_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_4 = data_io_in_bits_wmask_dataout_24_value__8 |
- data_io_in_bits_wmask_dataout_24_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_5 = data_io_in_bits_wmask_dataout_24_value__10 |
- data_io_in_bits_wmask_dataout_24_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_6 = data_io_in_bits_wmask_dataout_24_value__12 |
- data_io_in_bits_wmask_dataout_24_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_7 = data_io_in_bits_wmask_dataout_24_value__14 |
- data_io_in_bits_wmask_dataout_24_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_8 = data_io_in_bits_wmask_dataout_24_value__16 |
- data_io_in_bits_wmask_dataout_24_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_9 = data_io_in_bits_wmask_dataout_24_value__18 |
- data_io_in_bits_wmask_dataout_24_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_10 = data_io_in_bits_wmask_dataout_24_value__20 |
- data_io_in_bits_wmask_dataout_24_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_11 = data_io_in_bits_wmask_dataout_24_value__22 |
- data_io_in_bits_wmask_dataout_24_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_12 = data_io_in_bits_wmask_dataout_24_value__24 |
- data_io_in_bits_wmask_dataout_24_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_13 = data_io_in_bits_wmask_dataout_24_value__26 |
- data_io_in_bits_wmask_dataout_24_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_14 = data_io_in_bits_wmask_dataout_24_value__28 |
- data_io_in_bits_wmask_dataout_24_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_1_15 = data_io_in_bits_wmask_dataout_24_value__30 |
- data_io_in_bits_wmask_dataout_24_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_2_0 = data_io_in_bits_wmask_dataout_24_value_1_0 |
- data_io_in_bits_wmask_dataout_24_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_2_1 = data_io_in_bits_wmask_dataout_24_value_1_2 |
- data_io_in_bits_wmask_dataout_24_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_2_2 = data_io_in_bits_wmask_dataout_24_value_1_4 |
- data_io_in_bits_wmask_dataout_24_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_2_3 = data_io_in_bits_wmask_dataout_24_value_1_6 |
- data_io_in_bits_wmask_dataout_24_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_2_4 = data_io_in_bits_wmask_dataout_24_value_1_8 |
- data_io_in_bits_wmask_dataout_24_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_2_5 = data_io_in_bits_wmask_dataout_24_value_1_10 |
- data_io_in_bits_wmask_dataout_24_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_2_6 = data_io_in_bits_wmask_dataout_24_value_1_12 |
- data_io_in_bits_wmask_dataout_24_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_2_7 = data_io_in_bits_wmask_dataout_24_value_1_14 |
- data_io_in_bits_wmask_dataout_24_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_3_0 = data_io_in_bits_wmask_dataout_24_value_2_0 |
- data_io_in_bits_wmask_dataout_24_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_3_1 = data_io_in_bits_wmask_dataout_24_value_2_2 |
- data_io_in_bits_wmask_dataout_24_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_3_2 = data_io_in_bits_wmask_dataout_24_value_2_4 |
- data_io_in_bits_wmask_dataout_24_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_3_3 = data_io_in_bits_wmask_dataout_24_value_2_6 |
- data_io_in_bits_wmask_dataout_24_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_4_0 = data_io_in_bits_wmask_dataout_24_value_3_0 |
- data_io_in_bits_wmask_dataout_24_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_4_1 = data_io_in_bits_wmask_dataout_24_value_3_2 |
- data_io_in_bits_wmask_dataout_24_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_24_value_5_0 = data_io_in_bits_wmask_dataout_24_value_4_0 |
- data_io_in_bits_wmask_dataout_24_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_25 = 5'h19 - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_25_value__0 = 5'h0 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__1 = 5'h1 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__2 = 5'h2 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__3 = 5'h3 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__4 = 5'h4 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__5 = 5'h5 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__6 = 5'h6 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__7 = 5'h7 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__8 = 5'h8 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__9 = 5'h9 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__10 = 5'ha == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__11 = 5'hb == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__12 = 5'hc == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__13 = 5'hd == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__14 = 5'he == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__15 = 5'hf == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__16 = 5'h10 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__17 = 5'h11 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__18 = 5'h12 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__19 = 5'h13 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__20 = 5'h14 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__21 = 5'h15 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__22 = 5'h16 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__23 = 5'h17 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__24 = 5'h18 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__25 = 5'h19 == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__26 = 5'h1a == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__27 = 5'h1b == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__28 = 5'h1c == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__29 = 5'h1d == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__30 = 5'h1e == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value__31 = 5'h1f == data_io_in_bits_wmask_idx_25 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_25_value_1_0 = data_io_in_bits_wmask_dataout_25_value__0 |
- data_io_in_bits_wmask_dataout_25_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_1 = data_io_in_bits_wmask_dataout_25_value__2 |
- data_io_in_bits_wmask_dataout_25_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_2 = data_io_in_bits_wmask_dataout_25_value__4 |
- data_io_in_bits_wmask_dataout_25_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_3 = data_io_in_bits_wmask_dataout_25_value__6 |
- data_io_in_bits_wmask_dataout_25_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_4 = data_io_in_bits_wmask_dataout_25_value__8 |
- data_io_in_bits_wmask_dataout_25_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_5 = data_io_in_bits_wmask_dataout_25_value__10 |
- data_io_in_bits_wmask_dataout_25_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_6 = data_io_in_bits_wmask_dataout_25_value__12 |
- data_io_in_bits_wmask_dataout_25_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_7 = data_io_in_bits_wmask_dataout_25_value__14 |
- data_io_in_bits_wmask_dataout_25_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_8 = data_io_in_bits_wmask_dataout_25_value__16 |
- data_io_in_bits_wmask_dataout_25_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_9 = data_io_in_bits_wmask_dataout_25_value__18 |
- data_io_in_bits_wmask_dataout_25_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_10 = data_io_in_bits_wmask_dataout_25_value__20 |
- data_io_in_bits_wmask_dataout_25_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_11 = data_io_in_bits_wmask_dataout_25_value__22 |
- data_io_in_bits_wmask_dataout_25_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_12 = data_io_in_bits_wmask_dataout_25_value__24 |
- data_io_in_bits_wmask_dataout_25_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_13 = data_io_in_bits_wmask_dataout_25_value__26 |
- data_io_in_bits_wmask_dataout_25_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_14 = data_io_in_bits_wmask_dataout_25_value__28 |
- data_io_in_bits_wmask_dataout_25_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_1_15 = data_io_in_bits_wmask_dataout_25_value__30 |
- data_io_in_bits_wmask_dataout_25_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_2_0 = data_io_in_bits_wmask_dataout_25_value_1_0 |
- data_io_in_bits_wmask_dataout_25_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_2_1 = data_io_in_bits_wmask_dataout_25_value_1_2 |
- data_io_in_bits_wmask_dataout_25_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_2_2 = data_io_in_bits_wmask_dataout_25_value_1_4 |
- data_io_in_bits_wmask_dataout_25_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_2_3 = data_io_in_bits_wmask_dataout_25_value_1_6 |
- data_io_in_bits_wmask_dataout_25_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_2_4 = data_io_in_bits_wmask_dataout_25_value_1_8 |
- data_io_in_bits_wmask_dataout_25_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_2_5 = data_io_in_bits_wmask_dataout_25_value_1_10 |
- data_io_in_bits_wmask_dataout_25_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_2_6 = data_io_in_bits_wmask_dataout_25_value_1_12 |
- data_io_in_bits_wmask_dataout_25_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_2_7 = data_io_in_bits_wmask_dataout_25_value_1_14 |
- data_io_in_bits_wmask_dataout_25_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_3_0 = data_io_in_bits_wmask_dataout_25_value_2_0 |
- data_io_in_bits_wmask_dataout_25_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_3_1 = data_io_in_bits_wmask_dataout_25_value_2_2 |
- data_io_in_bits_wmask_dataout_25_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_3_2 = data_io_in_bits_wmask_dataout_25_value_2_4 |
- data_io_in_bits_wmask_dataout_25_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_3_3 = data_io_in_bits_wmask_dataout_25_value_2_6 |
- data_io_in_bits_wmask_dataout_25_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_4_0 = data_io_in_bits_wmask_dataout_25_value_3_0 |
- data_io_in_bits_wmask_dataout_25_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_4_1 = data_io_in_bits_wmask_dataout_25_value_3_2 |
- data_io_in_bits_wmask_dataout_25_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_25_value_5_0 = data_io_in_bits_wmask_dataout_25_value_4_0 |
- data_io_in_bits_wmask_dataout_25_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_26 = 5'h1a - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_26_value__0 = 5'h0 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__1 = 5'h1 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__2 = 5'h2 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__3 = 5'h3 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__4 = 5'h4 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__5 = 5'h5 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__6 = 5'h6 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__7 = 5'h7 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__8 = 5'h8 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__9 = 5'h9 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__10 = 5'ha == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__11 = 5'hb == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__12 = 5'hc == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__13 = 5'hd == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__14 = 5'he == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__15 = 5'hf == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__16 = 5'h10 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__17 = 5'h11 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__18 = 5'h12 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__19 = 5'h13 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__20 = 5'h14 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__21 = 5'h15 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__22 = 5'h16 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__23 = 5'h17 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__24 = 5'h18 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__25 = 5'h19 == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__26 = 5'h1a == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__27 = 5'h1b == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__28 = 5'h1c == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__29 = 5'h1d == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__30 = 5'h1e == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value__31 = 5'h1f == data_io_in_bits_wmask_idx_26 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_26_value_1_0 = data_io_in_bits_wmask_dataout_26_value__0 |
- data_io_in_bits_wmask_dataout_26_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_1 = data_io_in_bits_wmask_dataout_26_value__2 |
- data_io_in_bits_wmask_dataout_26_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_2 = data_io_in_bits_wmask_dataout_26_value__4 |
- data_io_in_bits_wmask_dataout_26_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_3 = data_io_in_bits_wmask_dataout_26_value__6 |
- data_io_in_bits_wmask_dataout_26_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_4 = data_io_in_bits_wmask_dataout_26_value__8 |
- data_io_in_bits_wmask_dataout_26_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_5 = data_io_in_bits_wmask_dataout_26_value__10 |
- data_io_in_bits_wmask_dataout_26_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_6 = data_io_in_bits_wmask_dataout_26_value__12 |
- data_io_in_bits_wmask_dataout_26_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_7 = data_io_in_bits_wmask_dataout_26_value__14 |
- data_io_in_bits_wmask_dataout_26_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_8 = data_io_in_bits_wmask_dataout_26_value__16 |
- data_io_in_bits_wmask_dataout_26_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_9 = data_io_in_bits_wmask_dataout_26_value__18 |
- data_io_in_bits_wmask_dataout_26_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_10 = data_io_in_bits_wmask_dataout_26_value__20 |
- data_io_in_bits_wmask_dataout_26_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_11 = data_io_in_bits_wmask_dataout_26_value__22 |
- data_io_in_bits_wmask_dataout_26_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_12 = data_io_in_bits_wmask_dataout_26_value__24 |
- data_io_in_bits_wmask_dataout_26_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_13 = data_io_in_bits_wmask_dataout_26_value__26 |
- data_io_in_bits_wmask_dataout_26_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_14 = data_io_in_bits_wmask_dataout_26_value__28 |
- data_io_in_bits_wmask_dataout_26_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_1_15 = data_io_in_bits_wmask_dataout_26_value__30 |
- data_io_in_bits_wmask_dataout_26_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_2_0 = data_io_in_bits_wmask_dataout_26_value_1_0 |
- data_io_in_bits_wmask_dataout_26_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_2_1 = data_io_in_bits_wmask_dataout_26_value_1_2 |
- data_io_in_bits_wmask_dataout_26_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_2_2 = data_io_in_bits_wmask_dataout_26_value_1_4 |
- data_io_in_bits_wmask_dataout_26_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_2_3 = data_io_in_bits_wmask_dataout_26_value_1_6 |
- data_io_in_bits_wmask_dataout_26_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_2_4 = data_io_in_bits_wmask_dataout_26_value_1_8 |
- data_io_in_bits_wmask_dataout_26_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_2_5 = data_io_in_bits_wmask_dataout_26_value_1_10 |
- data_io_in_bits_wmask_dataout_26_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_2_6 = data_io_in_bits_wmask_dataout_26_value_1_12 |
- data_io_in_bits_wmask_dataout_26_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_2_7 = data_io_in_bits_wmask_dataout_26_value_1_14 |
- data_io_in_bits_wmask_dataout_26_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_3_0 = data_io_in_bits_wmask_dataout_26_value_2_0 |
- data_io_in_bits_wmask_dataout_26_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_3_1 = data_io_in_bits_wmask_dataout_26_value_2_2 |
- data_io_in_bits_wmask_dataout_26_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_3_2 = data_io_in_bits_wmask_dataout_26_value_2_4 |
- data_io_in_bits_wmask_dataout_26_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_3_3 = data_io_in_bits_wmask_dataout_26_value_2_6 |
- data_io_in_bits_wmask_dataout_26_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_4_0 = data_io_in_bits_wmask_dataout_26_value_3_0 |
- data_io_in_bits_wmask_dataout_26_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_4_1 = data_io_in_bits_wmask_dataout_26_value_3_2 |
- data_io_in_bits_wmask_dataout_26_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_26_value_5_0 = data_io_in_bits_wmask_dataout_26_value_4_0 |
- data_io_in_bits_wmask_dataout_26_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_27 = 5'h1b - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_27_value__0 = 5'h0 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__1 = 5'h1 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__2 = 5'h2 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__3 = 5'h3 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__4 = 5'h4 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__5 = 5'h5 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__6 = 5'h6 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__7 = 5'h7 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__8 = 5'h8 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__9 = 5'h9 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__10 = 5'ha == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__11 = 5'hb == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__12 = 5'hc == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__13 = 5'hd == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__14 = 5'he == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__15 = 5'hf == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__16 = 5'h10 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__17 = 5'h11 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__18 = 5'h12 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__19 = 5'h13 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__20 = 5'h14 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__21 = 5'h15 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__22 = 5'h16 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__23 = 5'h17 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__24 = 5'h18 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__25 = 5'h19 == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__26 = 5'h1a == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__27 = 5'h1b == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__28 = 5'h1c == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__29 = 5'h1d == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__30 = 5'h1e == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value__31 = 5'h1f == data_io_in_bits_wmask_idx_27 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_27_value_1_0 = data_io_in_bits_wmask_dataout_27_value__0 |
- data_io_in_bits_wmask_dataout_27_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_1 = data_io_in_bits_wmask_dataout_27_value__2 |
- data_io_in_bits_wmask_dataout_27_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_2 = data_io_in_bits_wmask_dataout_27_value__4 |
- data_io_in_bits_wmask_dataout_27_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_3 = data_io_in_bits_wmask_dataout_27_value__6 |
- data_io_in_bits_wmask_dataout_27_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_4 = data_io_in_bits_wmask_dataout_27_value__8 |
- data_io_in_bits_wmask_dataout_27_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_5 = data_io_in_bits_wmask_dataout_27_value__10 |
- data_io_in_bits_wmask_dataout_27_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_6 = data_io_in_bits_wmask_dataout_27_value__12 |
- data_io_in_bits_wmask_dataout_27_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_7 = data_io_in_bits_wmask_dataout_27_value__14 |
- data_io_in_bits_wmask_dataout_27_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_8 = data_io_in_bits_wmask_dataout_27_value__16 |
- data_io_in_bits_wmask_dataout_27_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_9 = data_io_in_bits_wmask_dataout_27_value__18 |
- data_io_in_bits_wmask_dataout_27_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_10 = data_io_in_bits_wmask_dataout_27_value__20 |
- data_io_in_bits_wmask_dataout_27_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_11 = data_io_in_bits_wmask_dataout_27_value__22 |
- data_io_in_bits_wmask_dataout_27_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_12 = data_io_in_bits_wmask_dataout_27_value__24 |
- data_io_in_bits_wmask_dataout_27_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_13 = data_io_in_bits_wmask_dataout_27_value__26 |
- data_io_in_bits_wmask_dataout_27_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_14 = data_io_in_bits_wmask_dataout_27_value__28 |
- data_io_in_bits_wmask_dataout_27_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_1_15 = data_io_in_bits_wmask_dataout_27_value__30 |
- data_io_in_bits_wmask_dataout_27_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_2_0 = data_io_in_bits_wmask_dataout_27_value_1_0 |
- data_io_in_bits_wmask_dataout_27_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_2_1 = data_io_in_bits_wmask_dataout_27_value_1_2 |
- data_io_in_bits_wmask_dataout_27_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_2_2 = data_io_in_bits_wmask_dataout_27_value_1_4 |
- data_io_in_bits_wmask_dataout_27_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_2_3 = data_io_in_bits_wmask_dataout_27_value_1_6 |
- data_io_in_bits_wmask_dataout_27_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_2_4 = data_io_in_bits_wmask_dataout_27_value_1_8 |
- data_io_in_bits_wmask_dataout_27_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_2_5 = data_io_in_bits_wmask_dataout_27_value_1_10 |
- data_io_in_bits_wmask_dataout_27_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_2_6 = data_io_in_bits_wmask_dataout_27_value_1_12 |
- data_io_in_bits_wmask_dataout_27_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_2_7 = data_io_in_bits_wmask_dataout_27_value_1_14 |
- data_io_in_bits_wmask_dataout_27_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_3_0 = data_io_in_bits_wmask_dataout_27_value_2_0 |
- data_io_in_bits_wmask_dataout_27_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_3_1 = data_io_in_bits_wmask_dataout_27_value_2_2 |
- data_io_in_bits_wmask_dataout_27_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_3_2 = data_io_in_bits_wmask_dataout_27_value_2_4 |
- data_io_in_bits_wmask_dataout_27_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_3_3 = data_io_in_bits_wmask_dataout_27_value_2_6 |
- data_io_in_bits_wmask_dataout_27_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_4_0 = data_io_in_bits_wmask_dataout_27_value_3_0 |
- data_io_in_bits_wmask_dataout_27_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_4_1 = data_io_in_bits_wmask_dataout_27_value_3_2 |
- data_io_in_bits_wmask_dataout_27_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_27_value_5_0 = data_io_in_bits_wmask_dataout_27_value_4_0 |
- data_io_in_bits_wmask_dataout_27_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_28 = 5'h1c - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_28_value__0 = 5'h0 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__1 = 5'h1 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__2 = 5'h2 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__3 = 5'h3 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__4 = 5'h4 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__5 = 5'h5 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__6 = 5'h6 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__7 = 5'h7 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__8 = 5'h8 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__9 = 5'h9 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__10 = 5'ha == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__11 = 5'hb == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__12 = 5'hc == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__13 = 5'hd == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__14 = 5'he == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__15 = 5'hf == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__16 = 5'h10 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__17 = 5'h11 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__18 = 5'h12 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__19 = 5'h13 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__20 = 5'h14 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__21 = 5'h15 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__22 = 5'h16 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__23 = 5'h17 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__24 = 5'h18 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__25 = 5'h19 == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__26 = 5'h1a == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__27 = 5'h1b == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__28 = 5'h1c == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__29 = 5'h1d == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__30 = 5'h1e == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value__31 = 5'h1f == data_io_in_bits_wmask_idx_28 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_28_value_1_0 = data_io_in_bits_wmask_dataout_28_value__0 |
- data_io_in_bits_wmask_dataout_28_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_1 = data_io_in_bits_wmask_dataout_28_value__2 |
- data_io_in_bits_wmask_dataout_28_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_2 = data_io_in_bits_wmask_dataout_28_value__4 |
- data_io_in_bits_wmask_dataout_28_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_3 = data_io_in_bits_wmask_dataout_28_value__6 |
- data_io_in_bits_wmask_dataout_28_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_4 = data_io_in_bits_wmask_dataout_28_value__8 |
- data_io_in_bits_wmask_dataout_28_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_5 = data_io_in_bits_wmask_dataout_28_value__10 |
- data_io_in_bits_wmask_dataout_28_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_6 = data_io_in_bits_wmask_dataout_28_value__12 |
- data_io_in_bits_wmask_dataout_28_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_7 = data_io_in_bits_wmask_dataout_28_value__14 |
- data_io_in_bits_wmask_dataout_28_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_8 = data_io_in_bits_wmask_dataout_28_value__16 |
- data_io_in_bits_wmask_dataout_28_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_9 = data_io_in_bits_wmask_dataout_28_value__18 |
- data_io_in_bits_wmask_dataout_28_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_10 = data_io_in_bits_wmask_dataout_28_value__20 |
- data_io_in_bits_wmask_dataout_28_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_11 = data_io_in_bits_wmask_dataout_28_value__22 |
- data_io_in_bits_wmask_dataout_28_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_12 = data_io_in_bits_wmask_dataout_28_value__24 |
- data_io_in_bits_wmask_dataout_28_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_13 = data_io_in_bits_wmask_dataout_28_value__26 |
- data_io_in_bits_wmask_dataout_28_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_14 = data_io_in_bits_wmask_dataout_28_value__28 |
- data_io_in_bits_wmask_dataout_28_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_1_15 = data_io_in_bits_wmask_dataout_28_value__30 |
- data_io_in_bits_wmask_dataout_28_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_2_0 = data_io_in_bits_wmask_dataout_28_value_1_0 |
- data_io_in_bits_wmask_dataout_28_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_2_1 = data_io_in_bits_wmask_dataout_28_value_1_2 |
- data_io_in_bits_wmask_dataout_28_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_2_2 = data_io_in_bits_wmask_dataout_28_value_1_4 |
- data_io_in_bits_wmask_dataout_28_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_2_3 = data_io_in_bits_wmask_dataout_28_value_1_6 |
- data_io_in_bits_wmask_dataout_28_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_2_4 = data_io_in_bits_wmask_dataout_28_value_1_8 |
- data_io_in_bits_wmask_dataout_28_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_2_5 = data_io_in_bits_wmask_dataout_28_value_1_10 |
- data_io_in_bits_wmask_dataout_28_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_2_6 = data_io_in_bits_wmask_dataout_28_value_1_12 |
- data_io_in_bits_wmask_dataout_28_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_2_7 = data_io_in_bits_wmask_dataout_28_value_1_14 |
- data_io_in_bits_wmask_dataout_28_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_3_0 = data_io_in_bits_wmask_dataout_28_value_2_0 |
- data_io_in_bits_wmask_dataout_28_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_3_1 = data_io_in_bits_wmask_dataout_28_value_2_2 |
- data_io_in_bits_wmask_dataout_28_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_3_2 = data_io_in_bits_wmask_dataout_28_value_2_4 |
- data_io_in_bits_wmask_dataout_28_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_3_3 = data_io_in_bits_wmask_dataout_28_value_2_6 |
- data_io_in_bits_wmask_dataout_28_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_4_0 = data_io_in_bits_wmask_dataout_28_value_3_0 |
- data_io_in_bits_wmask_dataout_28_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_4_1 = data_io_in_bits_wmask_dataout_28_value_3_2 |
- data_io_in_bits_wmask_dataout_28_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_28_value_5_0 = data_io_in_bits_wmask_dataout_28_value_4_0 |
- data_io_in_bits_wmask_dataout_28_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_29 = 5'h1d - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_29_value__0 = 5'h0 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__1 = 5'h1 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__2 = 5'h2 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__3 = 5'h3 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__4 = 5'h4 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__5 = 5'h5 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__6 = 5'h6 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__7 = 5'h7 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__8 = 5'h8 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__9 = 5'h9 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__10 = 5'ha == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__11 = 5'hb == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__12 = 5'hc == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__13 = 5'hd == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__14 = 5'he == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__15 = 5'hf == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__16 = 5'h10 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__17 = 5'h11 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__18 = 5'h12 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__19 = 5'h13 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__20 = 5'h14 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__21 = 5'h15 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__22 = 5'h16 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__23 = 5'h17 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__24 = 5'h18 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__25 = 5'h19 == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__26 = 5'h1a == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__27 = 5'h1b == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__28 = 5'h1c == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__29 = 5'h1d == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__30 = 5'h1e == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value__31 = 5'h1f == data_io_in_bits_wmask_idx_29 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_29_value_1_0 = data_io_in_bits_wmask_dataout_29_value__0 |
- data_io_in_bits_wmask_dataout_29_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_1 = data_io_in_bits_wmask_dataout_29_value__2 |
- data_io_in_bits_wmask_dataout_29_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_2 = data_io_in_bits_wmask_dataout_29_value__4 |
- data_io_in_bits_wmask_dataout_29_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_3 = data_io_in_bits_wmask_dataout_29_value__6 |
- data_io_in_bits_wmask_dataout_29_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_4 = data_io_in_bits_wmask_dataout_29_value__8 |
- data_io_in_bits_wmask_dataout_29_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_5 = data_io_in_bits_wmask_dataout_29_value__10 |
- data_io_in_bits_wmask_dataout_29_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_6 = data_io_in_bits_wmask_dataout_29_value__12 |
- data_io_in_bits_wmask_dataout_29_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_7 = data_io_in_bits_wmask_dataout_29_value__14 |
- data_io_in_bits_wmask_dataout_29_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_8 = data_io_in_bits_wmask_dataout_29_value__16 |
- data_io_in_bits_wmask_dataout_29_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_9 = data_io_in_bits_wmask_dataout_29_value__18 |
- data_io_in_bits_wmask_dataout_29_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_10 = data_io_in_bits_wmask_dataout_29_value__20 |
- data_io_in_bits_wmask_dataout_29_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_11 = data_io_in_bits_wmask_dataout_29_value__22 |
- data_io_in_bits_wmask_dataout_29_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_12 = data_io_in_bits_wmask_dataout_29_value__24 |
- data_io_in_bits_wmask_dataout_29_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_13 = data_io_in_bits_wmask_dataout_29_value__26 |
- data_io_in_bits_wmask_dataout_29_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_14 = data_io_in_bits_wmask_dataout_29_value__28 |
- data_io_in_bits_wmask_dataout_29_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_1_15 = data_io_in_bits_wmask_dataout_29_value__30 |
- data_io_in_bits_wmask_dataout_29_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_2_0 = data_io_in_bits_wmask_dataout_29_value_1_0 |
- data_io_in_bits_wmask_dataout_29_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_2_1 = data_io_in_bits_wmask_dataout_29_value_1_2 |
- data_io_in_bits_wmask_dataout_29_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_2_2 = data_io_in_bits_wmask_dataout_29_value_1_4 |
- data_io_in_bits_wmask_dataout_29_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_2_3 = data_io_in_bits_wmask_dataout_29_value_1_6 |
- data_io_in_bits_wmask_dataout_29_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_2_4 = data_io_in_bits_wmask_dataout_29_value_1_8 |
- data_io_in_bits_wmask_dataout_29_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_2_5 = data_io_in_bits_wmask_dataout_29_value_1_10 |
- data_io_in_bits_wmask_dataout_29_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_2_6 = data_io_in_bits_wmask_dataout_29_value_1_12 |
- data_io_in_bits_wmask_dataout_29_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_2_7 = data_io_in_bits_wmask_dataout_29_value_1_14 |
- data_io_in_bits_wmask_dataout_29_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_3_0 = data_io_in_bits_wmask_dataout_29_value_2_0 |
- data_io_in_bits_wmask_dataout_29_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_3_1 = data_io_in_bits_wmask_dataout_29_value_2_2 |
- data_io_in_bits_wmask_dataout_29_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_3_2 = data_io_in_bits_wmask_dataout_29_value_2_4 |
- data_io_in_bits_wmask_dataout_29_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_3_3 = data_io_in_bits_wmask_dataout_29_value_2_6 |
- data_io_in_bits_wmask_dataout_29_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_4_0 = data_io_in_bits_wmask_dataout_29_value_3_0 |
- data_io_in_bits_wmask_dataout_29_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_4_1 = data_io_in_bits_wmask_dataout_29_value_3_2 |
- data_io_in_bits_wmask_dataout_29_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_29_value_5_0 = data_io_in_bits_wmask_dataout_29_value_4_0 |
- data_io_in_bits_wmask_dataout_29_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_30 = 5'h1e - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_30_value__0 = 5'h0 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__1 = 5'h1 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__2 = 5'h2 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__3 = 5'h3 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__4 = 5'h4 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__5 = 5'h5 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__6 = 5'h6 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__7 = 5'h7 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__8 = 5'h8 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__9 = 5'h9 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__10 = 5'ha == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__11 = 5'hb == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__12 = 5'hc == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__13 = 5'hd == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__14 = 5'he == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__15 = 5'hf == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__16 = 5'h10 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__17 = 5'h11 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__18 = 5'h12 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__19 = 5'h13 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__20 = 5'h14 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__21 = 5'h15 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__22 = 5'h16 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__23 = 5'h17 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__24 = 5'h18 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__25 = 5'h19 == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__26 = 5'h1a == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__27 = 5'h1b == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__28 = 5'h1c == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__29 = 5'h1d == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__30 = 5'h1e == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value__31 = 5'h1f == data_io_in_bits_wmask_idx_30 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_30_value_1_0 = data_io_in_bits_wmask_dataout_30_value__0 |
- data_io_in_bits_wmask_dataout_30_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_1 = data_io_in_bits_wmask_dataout_30_value__2 |
- data_io_in_bits_wmask_dataout_30_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_2 = data_io_in_bits_wmask_dataout_30_value__4 |
- data_io_in_bits_wmask_dataout_30_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_3 = data_io_in_bits_wmask_dataout_30_value__6 |
- data_io_in_bits_wmask_dataout_30_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_4 = data_io_in_bits_wmask_dataout_30_value__8 |
- data_io_in_bits_wmask_dataout_30_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_5 = data_io_in_bits_wmask_dataout_30_value__10 |
- data_io_in_bits_wmask_dataout_30_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_6 = data_io_in_bits_wmask_dataout_30_value__12 |
- data_io_in_bits_wmask_dataout_30_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_7 = data_io_in_bits_wmask_dataout_30_value__14 |
- data_io_in_bits_wmask_dataout_30_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_8 = data_io_in_bits_wmask_dataout_30_value__16 |
- data_io_in_bits_wmask_dataout_30_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_9 = data_io_in_bits_wmask_dataout_30_value__18 |
- data_io_in_bits_wmask_dataout_30_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_10 = data_io_in_bits_wmask_dataout_30_value__20 |
- data_io_in_bits_wmask_dataout_30_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_11 = data_io_in_bits_wmask_dataout_30_value__22 |
- data_io_in_bits_wmask_dataout_30_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_12 = data_io_in_bits_wmask_dataout_30_value__24 |
- data_io_in_bits_wmask_dataout_30_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_13 = data_io_in_bits_wmask_dataout_30_value__26 |
- data_io_in_bits_wmask_dataout_30_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_14 = data_io_in_bits_wmask_dataout_30_value__28 |
- data_io_in_bits_wmask_dataout_30_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_1_15 = data_io_in_bits_wmask_dataout_30_value__30 |
- data_io_in_bits_wmask_dataout_30_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_2_0 = data_io_in_bits_wmask_dataout_30_value_1_0 |
- data_io_in_bits_wmask_dataout_30_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_2_1 = data_io_in_bits_wmask_dataout_30_value_1_2 |
- data_io_in_bits_wmask_dataout_30_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_2_2 = data_io_in_bits_wmask_dataout_30_value_1_4 |
- data_io_in_bits_wmask_dataout_30_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_2_3 = data_io_in_bits_wmask_dataout_30_value_1_6 |
- data_io_in_bits_wmask_dataout_30_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_2_4 = data_io_in_bits_wmask_dataout_30_value_1_8 |
- data_io_in_bits_wmask_dataout_30_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_2_5 = data_io_in_bits_wmask_dataout_30_value_1_10 |
- data_io_in_bits_wmask_dataout_30_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_2_6 = data_io_in_bits_wmask_dataout_30_value_1_12 |
- data_io_in_bits_wmask_dataout_30_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_2_7 = data_io_in_bits_wmask_dataout_30_value_1_14 |
- data_io_in_bits_wmask_dataout_30_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_3_0 = data_io_in_bits_wmask_dataout_30_value_2_0 |
- data_io_in_bits_wmask_dataout_30_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_3_1 = data_io_in_bits_wmask_dataout_30_value_2_2 |
- data_io_in_bits_wmask_dataout_30_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_3_2 = data_io_in_bits_wmask_dataout_30_value_2_4 |
- data_io_in_bits_wmask_dataout_30_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_3_3 = data_io_in_bits_wmask_dataout_30_value_2_6 |
- data_io_in_bits_wmask_dataout_30_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_4_0 = data_io_in_bits_wmask_dataout_30_value_3_0 |
- data_io_in_bits_wmask_dataout_30_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_4_1 = data_io_in_bits_wmask_dataout_30_value_3_2 |
- data_io_in_bits_wmask_dataout_30_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_30_value_5_0 = data_io_in_bits_wmask_dataout_30_value_4_0 |
- data_io_in_bits_wmask_dataout_30_value_4_1; // @[Library.scala 129:37]
- wire [4:0] data_io_in_bits_wmask_idx_31 = 5'h1f - rdataAddr; // @[VLdSt.scala 71:52]
- wire data_io_in_bits_wmask_dataout_31_value__0 = 5'h0 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_0; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__1 = 5'h1 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_1; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__2 = 5'h2 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_2; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__3 = 5'h3 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_3; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__4 = 5'h4 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_4; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__5 = 5'h5 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_5; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__6 = 5'h6 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_6; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__7 = 5'h7 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_7; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__8 = 5'h8 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_8; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__9 = 5'h9 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_9; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__10 = 5'ha == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_10; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__11 = 5'hb == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_11; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__12 = 5'hc == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_12; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__13 = 5'hd == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_13; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__14 = 5'he == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_14; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__15 = 5'hf == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_15; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__16 = 5'h10 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_16; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__17 = 5'h11 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_17; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__18 = 5'h12 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_18; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__19 = 5'h13 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_19; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__20 = 5'h14 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_20; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__21 = 5'h15 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_21; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__22 = 5'h16 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_22; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__23 = 5'h17 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_23; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__24 = 5'h18 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_24; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__25 = 5'h19 == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_25; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__26 = 5'h1a == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_26; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__27 = 5'h1b == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_27; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__28 = 5'h1c == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_28; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__29 = 5'h1d == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_29; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__30 = 5'h1e == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_30; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value__31 = 5'h1f == data_io_in_bits_wmask_idx_31 &
- data_io_in_bits_wmask_datain_31; // @[Library.scala 115:22]
- wire data_io_in_bits_wmask_dataout_31_value_1_0 = data_io_in_bits_wmask_dataout_31_value__0 |
- data_io_in_bits_wmask_dataout_31_value__1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_1 = data_io_in_bits_wmask_dataout_31_value__2 |
- data_io_in_bits_wmask_dataout_31_value__3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_2 = data_io_in_bits_wmask_dataout_31_value__4 |
- data_io_in_bits_wmask_dataout_31_value__5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_3 = data_io_in_bits_wmask_dataout_31_value__6 |
- data_io_in_bits_wmask_dataout_31_value__7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_4 = data_io_in_bits_wmask_dataout_31_value__8 |
- data_io_in_bits_wmask_dataout_31_value__9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_5 = data_io_in_bits_wmask_dataout_31_value__10 |
- data_io_in_bits_wmask_dataout_31_value__11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_6 = data_io_in_bits_wmask_dataout_31_value__12 |
- data_io_in_bits_wmask_dataout_31_value__13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_7 = data_io_in_bits_wmask_dataout_31_value__14 |
- data_io_in_bits_wmask_dataout_31_value__15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_8 = data_io_in_bits_wmask_dataout_31_value__16 |
- data_io_in_bits_wmask_dataout_31_value__17; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_9 = data_io_in_bits_wmask_dataout_31_value__18 |
- data_io_in_bits_wmask_dataout_31_value__19; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_10 = data_io_in_bits_wmask_dataout_31_value__20 |
- data_io_in_bits_wmask_dataout_31_value__21; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_11 = data_io_in_bits_wmask_dataout_31_value__22 |
- data_io_in_bits_wmask_dataout_31_value__23; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_12 = data_io_in_bits_wmask_dataout_31_value__24 |
- data_io_in_bits_wmask_dataout_31_value__25; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_13 = data_io_in_bits_wmask_dataout_31_value__26 |
- data_io_in_bits_wmask_dataout_31_value__27; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_14 = data_io_in_bits_wmask_dataout_31_value__28 |
- data_io_in_bits_wmask_dataout_31_value__29; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_1_15 = data_io_in_bits_wmask_dataout_31_value__30 |
- data_io_in_bits_wmask_dataout_31_value__31; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_2_0 = data_io_in_bits_wmask_dataout_31_value_1_0 |
- data_io_in_bits_wmask_dataout_31_value_1_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_2_1 = data_io_in_bits_wmask_dataout_31_value_1_2 |
- data_io_in_bits_wmask_dataout_31_value_1_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_2_2 = data_io_in_bits_wmask_dataout_31_value_1_4 |
- data_io_in_bits_wmask_dataout_31_value_1_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_2_3 = data_io_in_bits_wmask_dataout_31_value_1_6 |
- data_io_in_bits_wmask_dataout_31_value_1_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_2_4 = data_io_in_bits_wmask_dataout_31_value_1_8 |
- data_io_in_bits_wmask_dataout_31_value_1_9; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_2_5 = data_io_in_bits_wmask_dataout_31_value_1_10 |
- data_io_in_bits_wmask_dataout_31_value_1_11; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_2_6 = data_io_in_bits_wmask_dataout_31_value_1_12 |
- data_io_in_bits_wmask_dataout_31_value_1_13; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_2_7 = data_io_in_bits_wmask_dataout_31_value_1_14 |
- data_io_in_bits_wmask_dataout_31_value_1_15; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_3_0 = data_io_in_bits_wmask_dataout_31_value_2_0 |
- data_io_in_bits_wmask_dataout_31_value_2_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_3_1 = data_io_in_bits_wmask_dataout_31_value_2_2 |
- data_io_in_bits_wmask_dataout_31_value_2_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_3_2 = data_io_in_bits_wmask_dataout_31_value_2_4 |
- data_io_in_bits_wmask_dataout_31_value_2_5; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_3_3 = data_io_in_bits_wmask_dataout_31_value_2_6 |
- data_io_in_bits_wmask_dataout_31_value_2_7; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_4_0 = data_io_in_bits_wmask_dataout_31_value_3_0 |
- data_io_in_bits_wmask_dataout_31_value_3_1; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_4_1 = data_io_in_bits_wmask_dataout_31_value_3_2 |
- data_io_in_bits_wmask_dataout_31_value_3_3; // @[Library.scala 129:37]
- wire data_io_in_bits_wmask_dataout_31_value_5_0 = data_io_in_bits_wmask_dataout_31_value_4_0 |
- data_io_in_bits_wmask_dataout_31_value_4_1; // @[Library.scala 129:37]
- wire [7:0] data_io_in_bits_wmask_lo_lo_1 = {data_io_in_bits_wmask_dataout_7_value_5_0,
- data_io_in_bits_wmask_dataout_6_value_5_0,data_io_in_bits_wmask_dataout_5_value_5_0,
- data_io_in_bits_wmask_dataout_4_value_5_0,data_io_in_bits_wmask_dataout_3_value_5_0,
- data_io_in_bits_wmask_dataout_2_value_5_0,data_io_in_bits_wmask_dataout_1_value_5_0,
- data_io_in_bits_wmask_dataout_0_value_5_0}; // @[VLdSt.scala 76:13]
- wire [15:0] data_io_in_bits_wmask_lo_1 = {data_io_in_bits_wmask_dataout_15_value_5_0,
- data_io_in_bits_wmask_dataout_14_value_5_0,data_io_in_bits_wmask_dataout_13_value_5_0,
- data_io_in_bits_wmask_dataout_12_value_5_0,data_io_in_bits_wmask_dataout_11_value_5_0,
- data_io_in_bits_wmask_dataout_10_value_5_0,data_io_in_bits_wmask_dataout_9_value_5_0,
- data_io_in_bits_wmask_dataout_8_value_5_0,data_io_in_bits_wmask_lo_lo_1}; // @[VLdSt.scala 76:13]
- wire [7:0] data_io_in_bits_wmask_hi_lo_1 = {data_io_in_bits_wmask_dataout_23_value_5_0,
- data_io_in_bits_wmask_dataout_22_value_5_0,data_io_in_bits_wmask_dataout_21_value_5_0,
- data_io_in_bits_wmask_dataout_20_value_5_0,data_io_in_bits_wmask_dataout_19_value_5_0,
- data_io_in_bits_wmask_dataout_18_value_5_0,data_io_in_bits_wmask_dataout_17_value_5_0,
- data_io_in_bits_wmask_dataout_16_value_5_0}; // @[VLdSt.scala 76:13]
- wire [15:0] data_io_in_bits_wmask_hi_1 = {data_io_in_bits_wmask_dataout_31_value_5_0,
- data_io_in_bits_wmask_dataout_30_value_5_0,data_io_in_bits_wmask_dataout_29_value_5_0,
- data_io_in_bits_wmask_dataout_28_value_5_0,data_io_in_bits_wmask_dataout_27_value_5_0,
- data_io_in_bits_wmask_dataout_26_value_5_0,data_io_in_bits_wmask_dataout_25_value_5_0,
- data_io_in_bits_wmask_dataout_24_value_5_0,data_io_in_bits_wmask_hi_lo_1}; // @[VLdSt.scala 76:13]
- wire _ctrl_io_out_ready_T = ~ctrl_io_out_bits_write; // @[VLdSt.scala 261:63]
- wire _ctrl_io_out_ready_T_1 = data_io_out_valid | ~ctrl_io_out_bits_write; // @[VLdSt.scala 261:60]
- reg wdataEn; // @[VLdSt.scala 283:24]
- wire _maskb_1_T = 6'h1 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_1 = _maskb_1_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_0_T = 6'h0 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_0 = _maskb_0_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_3_T = 6'h3 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_3 = _maskb_3_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_2_T = 6'h2 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_2 = _maskb_2_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_5_T = 6'h5 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_5 = _maskb_5_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_4_T = 6'h4 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_4 = _maskb_4_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_7_T = 6'h7 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_7 = _maskb_7_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_6_T = 6'h6 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_6 = _maskb_6_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire [63:0] mask_lo_lo = {maskb_7,maskb_6,maskb_5,maskb_4,maskb_3,maskb_2,maskb_1,maskb_0}; // @[VLdSt.scala 300:20]
- wire _maskb_9_T = 6'h9 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_9 = _maskb_9_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_8_T = 6'h8 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_8 = _maskb_8_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_11_T = 6'hb < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_11 = _maskb_11_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_10_T = 6'ha < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_10 = _maskb_10_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_13_T = 6'hd < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_13 = _maskb_13_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_12_T = 6'hc < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_12 = _maskb_12_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_15_T = 6'hf < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_15 = _maskb_15_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_14_T = 6'he < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_14 = _maskb_14_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire [127:0] mask_lo = {maskb_15,maskb_14,maskb_13,maskb_12,maskb_11,maskb_10,maskb_9,maskb_8,mask_lo_lo}; // @[VLdSt.scala 300:20]
- wire _maskb_17_T = 6'h11 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_17 = _maskb_17_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_16_T = 6'h10 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_16 = _maskb_16_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_19_T = 6'h13 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_19 = _maskb_19_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_18_T = 6'h12 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_18 = _maskb_18_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_21_T = 6'h15 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_21 = _maskb_21_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_20_T = 6'h14 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_20 = _maskb_20_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_23_T = 6'h17 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_23 = _maskb_23_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_22_T = 6'h16 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_22 = _maskb_22_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire [63:0] mask_hi_lo = {maskb_23,maskb_22,maskb_21,maskb_20,maskb_19,maskb_18,maskb_17,maskb_16}; // @[VLdSt.scala 300:20]
- wire _maskb_25_T = 6'h19 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_25 = _maskb_25_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_24_T = 6'h18 < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_24 = _maskb_24_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_27_T = 6'h1b < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_27 = _maskb_27_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_26_T = 6'h1a < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_26 = _maskb_26_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_29_T = 6'h1d < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_29 = _maskb_29_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_28_T = 6'h1c < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_28 = _maskb_28_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_31_T = 6'h1f < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_31 = _maskb_31_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire _maskb_30_T = 6'h1e < wrega_io_out_bits_size; // @[VLdSt.scala 303:27]
- wire [7:0] maskb_30 = _maskb_30_T ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire [255:0] mask = {maskb_31,maskb_30,maskb_29,maskb_28,maskb_27,maskb_26,maskb_25,maskb_24,mask_hi_lo,mask_lo}; // @[VLdSt.scala 300:20]
- wire [7:0] io_write_data_datain_0 = wregd_io_out_bits[7:0]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_1 = wregd_io_out_bits[15:8]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_2 = wregd_io_out_bits[23:16]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_3 = wregd_io_out_bits[31:24]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_4 = wregd_io_out_bits[39:32]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_5 = wregd_io_out_bits[47:40]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_6 = wregd_io_out_bits[55:48]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_7 = wregd_io_out_bits[63:56]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_8 = wregd_io_out_bits[71:64]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_9 = wregd_io_out_bits[79:72]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_10 = wregd_io_out_bits[87:80]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_11 = wregd_io_out_bits[95:88]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_12 = wregd_io_out_bits[103:96]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_13 = wregd_io_out_bits[111:104]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_14 = wregd_io_out_bits[119:112]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_15 = wregd_io_out_bits[127:120]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_16 = wregd_io_out_bits[135:128]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_17 = wregd_io_out_bits[143:136]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_18 = wregd_io_out_bits[151:144]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_19 = wregd_io_out_bits[159:152]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_20 = wregd_io_out_bits[167:160]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_21 = wregd_io_out_bits[175:168]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_22 = wregd_io_out_bits[183:176]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_23 = wregd_io_out_bits[191:184]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_24 = wregd_io_out_bits[199:192]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_25 = wregd_io_out_bits[207:200]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_26 = wregd_io_out_bits[215:208]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_27 = wregd_io_out_bits[223:216]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_28 = wregd_io_out_bits[231:224]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_29 = wregd_io_out_bits[239:232]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_30 = wregd_io_out_bits[247:240]; // @[VLdSt.scala 66:24]
- wire [7:0] io_write_data_datain_31 = wregd_io_out_bits[255:248]; // @[VLdSt.scala 66:24]
- wire [4:0] io_write_data_index = wrega_io_out_bits_addr; // @[VLdSt.scala 69:21]
- wire [5:0] _io_write_data_idx_T = {{1'd0}, io_write_data_index}; // @[VLdSt.scala 71:35]
- wire [4:0] io_write_data_idx = _io_write_data_idx_T[4:0]; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_0_value__0 = 5'h0 == io_write_data_idx ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__1 = 5'h1 == io_write_data_idx ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__2 = 5'h2 == io_write_data_idx ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__3 = 5'h3 == io_write_data_idx ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__4 = 5'h4 == io_write_data_idx ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__5 = 5'h5 == io_write_data_idx ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__6 = 5'h6 == io_write_data_idx ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__7 = 5'h7 == io_write_data_idx ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__8 = 5'h8 == io_write_data_idx ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__9 = 5'h9 == io_write_data_idx ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__10 = 5'ha == io_write_data_idx ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__11 = 5'hb == io_write_data_idx ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__12 = 5'hc == io_write_data_idx ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__13 = 5'hd == io_write_data_idx ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__14 = 5'he == io_write_data_idx ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__15 = 5'hf == io_write_data_idx ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__16 = 5'h10 == io_write_data_idx ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__17 = 5'h11 == io_write_data_idx ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__18 = 5'h12 == io_write_data_idx ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__19 = 5'h13 == io_write_data_idx ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__20 = 5'h14 == io_write_data_idx ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__21 = 5'h15 == io_write_data_idx ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__22 = 5'h16 == io_write_data_idx ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__23 = 5'h17 == io_write_data_idx ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__24 = 5'h18 == io_write_data_idx ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__25 = 5'h19 == io_write_data_idx ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__26 = 5'h1a == io_write_data_idx ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__27 = 5'h1b == io_write_data_idx ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__28 = 5'h1c == io_write_data_idx ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__29 = 5'h1d == io_write_data_idx ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__30 = 5'h1e == io_write_data_idx ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value__31 = 5'h1f == io_write_data_idx ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_0_value_1_0 = io_write_data_dataout_0_value__0 | io_write_data_dataout_0_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_1 = io_write_data_dataout_0_value__2 | io_write_data_dataout_0_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_2 = io_write_data_dataout_0_value__4 | io_write_data_dataout_0_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_3 = io_write_data_dataout_0_value__6 | io_write_data_dataout_0_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_4 = io_write_data_dataout_0_value__8 | io_write_data_dataout_0_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_5 = io_write_data_dataout_0_value__10 | io_write_data_dataout_0_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_6 = io_write_data_dataout_0_value__12 | io_write_data_dataout_0_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_7 = io_write_data_dataout_0_value__14 | io_write_data_dataout_0_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_8 = io_write_data_dataout_0_value__16 | io_write_data_dataout_0_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_9 = io_write_data_dataout_0_value__18 | io_write_data_dataout_0_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_10 = io_write_data_dataout_0_value__20 | io_write_data_dataout_0_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_11 = io_write_data_dataout_0_value__22 | io_write_data_dataout_0_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_12 = io_write_data_dataout_0_value__24 | io_write_data_dataout_0_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_13 = io_write_data_dataout_0_value__26 | io_write_data_dataout_0_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_14 = io_write_data_dataout_0_value__28 | io_write_data_dataout_0_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_1_15 = io_write_data_dataout_0_value__30 | io_write_data_dataout_0_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_2_0 = io_write_data_dataout_0_value_1_0 | io_write_data_dataout_0_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_2_1 = io_write_data_dataout_0_value_1_2 | io_write_data_dataout_0_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_2_2 = io_write_data_dataout_0_value_1_4 | io_write_data_dataout_0_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_2_3 = io_write_data_dataout_0_value_1_6 | io_write_data_dataout_0_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_2_4 = io_write_data_dataout_0_value_1_8 | io_write_data_dataout_0_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_2_5 = io_write_data_dataout_0_value_1_10 | io_write_data_dataout_0_value_1_11
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_2_6 = io_write_data_dataout_0_value_1_12 | io_write_data_dataout_0_value_1_13
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_2_7 = io_write_data_dataout_0_value_1_14 | io_write_data_dataout_0_value_1_15
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_3_0 = io_write_data_dataout_0_value_2_0 | io_write_data_dataout_0_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_3_1 = io_write_data_dataout_0_value_2_2 | io_write_data_dataout_0_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_3_2 = io_write_data_dataout_0_value_2_4 | io_write_data_dataout_0_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_3_3 = io_write_data_dataout_0_value_2_6 | io_write_data_dataout_0_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_4_0 = io_write_data_dataout_0_value_3_0 | io_write_data_dataout_0_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_4_1 = io_write_data_dataout_0_value_3_2 | io_write_data_dataout_0_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_0_value_5_0 = io_write_data_dataout_0_value_4_0 | io_write_data_dataout_0_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_1 = 5'h1 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_1_value__0 = 5'h0 == io_write_data_idx_1 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__1 = 5'h1 == io_write_data_idx_1 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__2 = 5'h2 == io_write_data_idx_1 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__3 = 5'h3 == io_write_data_idx_1 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__4 = 5'h4 == io_write_data_idx_1 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__5 = 5'h5 == io_write_data_idx_1 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__6 = 5'h6 == io_write_data_idx_1 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__7 = 5'h7 == io_write_data_idx_1 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__8 = 5'h8 == io_write_data_idx_1 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__9 = 5'h9 == io_write_data_idx_1 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__10 = 5'ha == io_write_data_idx_1 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__11 = 5'hb == io_write_data_idx_1 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__12 = 5'hc == io_write_data_idx_1 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__13 = 5'hd == io_write_data_idx_1 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__14 = 5'he == io_write_data_idx_1 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__15 = 5'hf == io_write_data_idx_1 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__16 = 5'h10 == io_write_data_idx_1 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__17 = 5'h11 == io_write_data_idx_1 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__18 = 5'h12 == io_write_data_idx_1 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__19 = 5'h13 == io_write_data_idx_1 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__20 = 5'h14 == io_write_data_idx_1 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__21 = 5'h15 == io_write_data_idx_1 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__22 = 5'h16 == io_write_data_idx_1 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__23 = 5'h17 == io_write_data_idx_1 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__24 = 5'h18 == io_write_data_idx_1 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__25 = 5'h19 == io_write_data_idx_1 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__26 = 5'h1a == io_write_data_idx_1 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__27 = 5'h1b == io_write_data_idx_1 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__28 = 5'h1c == io_write_data_idx_1 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__29 = 5'h1d == io_write_data_idx_1 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__30 = 5'h1e == io_write_data_idx_1 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value__31 = 5'h1f == io_write_data_idx_1 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_1_value_1_0 = io_write_data_dataout_1_value__0 | io_write_data_dataout_1_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_1 = io_write_data_dataout_1_value__2 | io_write_data_dataout_1_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_2 = io_write_data_dataout_1_value__4 | io_write_data_dataout_1_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_3 = io_write_data_dataout_1_value__6 | io_write_data_dataout_1_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_4 = io_write_data_dataout_1_value__8 | io_write_data_dataout_1_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_5 = io_write_data_dataout_1_value__10 | io_write_data_dataout_1_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_6 = io_write_data_dataout_1_value__12 | io_write_data_dataout_1_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_7 = io_write_data_dataout_1_value__14 | io_write_data_dataout_1_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_8 = io_write_data_dataout_1_value__16 | io_write_data_dataout_1_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_9 = io_write_data_dataout_1_value__18 | io_write_data_dataout_1_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_10 = io_write_data_dataout_1_value__20 | io_write_data_dataout_1_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_11 = io_write_data_dataout_1_value__22 | io_write_data_dataout_1_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_12 = io_write_data_dataout_1_value__24 | io_write_data_dataout_1_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_13 = io_write_data_dataout_1_value__26 | io_write_data_dataout_1_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_14 = io_write_data_dataout_1_value__28 | io_write_data_dataout_1_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_1_15 = io_write_data_dataout_1_value__30 | io_write_data_dataout_1_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_2_0 = io_write_data_dataout_1_value_1_0 | io_write_data_dataout_1_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_2_1 = io_write_data_dataout_1_value_1_2 | io_write_data_dataout_1_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_2_2 = io_write_data_dataout_1_value_1_4 | io_write_data_dataout_1_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_2_3 = io_write_data_dataout_1_value_1_6 | io_write_data_dataout_1_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_2_4 = io_write_data_dataout_1_value_1_8 | io_write_data_dataout_1_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_2_5 = io_write_data_dataout_1_value_1_10 | io_write_data_dataout_1_value_1_11
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_2_6 = io_write_data_dataout_1_value_1_12 | io_write_data_dataout_1_value_1_13
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_2_7 = io_write_data_dataout_1_value_1_14 | io_write_data_dataout_1_value_1_15
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_3_0 = io_write_data_dataout_1_value_2_0 | io_write_data_dataout_1_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_3_1 = io_write_data_dataout_1_value_2_2 | io_write_data_dataout_1_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_3_2 = io_write_data_dataout_1_value_2_4 | io_write_data_dataout_1_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_3_3 = io_write_data_dataout_1_value_2_6 | io_write_data_dataout_1_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_4_0 = io_write_data_dataout_1_value_3_0 | io_write_data_dataout_1_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_4_1 = io_write_data_dataout_1_value_3_2 | io_write_data_dataout_1_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_1_value_5_0 = io_write_data_dataout_1_value_4_0 | io_write_data_dataout_1_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_2 = 5'h2 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_2_value__0 = 5'h0 == io_write_data_idx_2 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__1 = 5'h1 == io_write_data_idx_2 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__2 = 5'h2 == io_write_data_idx_2 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__3 = 5'h3 == io_write_data_idx_2 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__4 = 5'h4 == io_write_data_idx_2 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__5 = 5'h5 == io_write_data_idx_2 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__6 = 5'h6 == io_write_data_idx_2 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__7 = 5'h7 == io_write_data_idx_2 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__8 = 5'h8 == io_write_data_idx_2 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__9 = 5'h9 == io_write_data_idx_2 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__10 = 5'ha == io_write_data_idx_2 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__11 = 5'hb == io_write_data_idx_2 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__12 = 5'hc == io_write_data_idx_2 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__13 = 5'hd == io_write_data_idx_2 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__14 = 5'he == io_write_data_idx_2 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__15 = 5'hf == io_write_data_idx_2 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__16 = 5'h10 == io_write_data_idx_2 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__17 = 5'h11 == io_write_data_idx_2 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__18 = 5'h12 == io_write_data_idx_2 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__19 = 5'h13 == io_write_data_idx_2 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__20 = 5'h14 == io_write_data_idx_2 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__21 = 5'h15 == io_write_data_idx_2 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__22 = 5'h16 == io_write_data_idx_2 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__23 = 5'h17 == io_write_data_idx_2 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__24 = 5'h18 == io_write_data_idx_2 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__25 = 5'h19 == io_write_data_idx_2 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__26 = 5'h1a == io_write_data_idx_2 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__27 = 5'h1b == io_write_data_idx_2 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__28 = 5'h1c == io_write_data_idx_2 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__29 = 5'h1d == io_write_data_idx_2 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__30 = 5'h1e == io_write_data_idx_2 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value__31 = 5'h1f == io_write_data_idx_2 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_2_value_1_0 = io_write_data_dataout_2_value__0 | io_write_data_dataout_2_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_1 = io_write_data_dataout_2_value__2 | io_write_data_dataout_2_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_2 = io_write_data_dataout_2_value__4 | io_write_data_dataout_2_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_3 = io_write_data_dataout_2_value__6 | io_write_data_dataout_2_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_4 = io_write_data_dataout_2_value__8 | io_write_data_dataout_2_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_5 = io_write_data_dataout_2_value__10 | io_write_data_dataout_2_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_6 = io_write_data_dataout_2_value__12 | io_write_data_dataout_2_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_7 = io_write_data_dataout_2_value__14 | io_write_data_dataout_2_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_8 = io_write_data_dataout_2_value__16 | io_write_data_dataout_2_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_9 = io_write_data_dataout_2_value__18 | io_write_data_dataout_2_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_10 = io_write_data_dataout_2_value__20 | io_write_data_dataout_2_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_11 = io_write_data_dataout_2_value__22 | io_write_data_dataout_2_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_12 = io_write_data_dataout_2_value__24 | io_write_data_dataout_2_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_13 = io_write_data_dataout_2_value__26 | io_write_data_dataout_2_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_14 = io_write_data_dataout_2_value__28 | io_write_data_dataout_2_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_1_15 = io_write_data_dataout_2_value__30 | io_write_data_dataout_2_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_2_0 = io_write_data_dataout_2_value_1_0 | io_write_data_dataout_2_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_2_1 = io_write_data_dataout_2_value_1_2 | io_write_data_dataout_2_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_2_2 = io_write_data_dataout_2_value_1_4 | io_write_data_dataout_2_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_2_3 = io_write_data_dataout_2_value_1_6 | io_write_data_dataout_2_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_2_4 = io_write_data_dataout_2_value_1_8 | io_write_data_dataout_2_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_2_5 = io_write_data_dataout_2_value_1_10 | io_write_data_dataout_2_value_1_11
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_2_6 = io_write_data_dataout_2_value_1_12 | io_write_data_dataout_2_value_1_13
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_2_7 = io_write_data_dataout_2_value_1_14 | io_write_data_dataout_2_value_1_15
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_3_0 = io_write_data_dataout_2_value_2_0 | io_write_data_dataout_2_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_3_1 = io_write_data_dataout_2_value_2_2 | io_write_data_dataout_2_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_3_2 = io_write_data_dataout_2_value_2_4 | io_write_data_dataout_2_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_3_3 = io_write_data_dataout_2_value_2_6 | io_write_data_dataout_2_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_4_0 = io_write_data_dataout_2_value_3_0 | io_write_data_dataout_2_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_4_1 = io_write_data_dataout_2_value_3_2 | io_write_data_dataout_2_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_2_value_5_0 = io_write_data_dataout_2_value_4_0 | io_write_data_dataout_2_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_3 = 5'h3 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_3_value__0 = 5'h0 == io_write_data_idx_3 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__1 = 5'h1 == io_write_data_idx_3 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__2 = 5'h2 == io_write_data_idx_3 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__3 = 5'h3 == io_write_data_idx_3 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__4 = 5'h4 == io_write_data_idx_3 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__5 = 5'h5 == io_write_data_idx_3 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__6 = 5'h6 == io_write_data_idx_3 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__7 = 5'h7 == io_write_data_idx_3 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__8 = 5'h8 == io_write_data_idx_3 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__9 = 5'h9 == io_write_data_idx_3 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__10 = 5'ha == io_write_data_idx_3 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__11 = 5'hb == io_write_data_idx_3 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__12 = 5'hc == io_write_data_idx_3 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__13 = 5'hd == io_write_data_idx_3 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__14 = 5'he == io_write_data_idx_3 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__15 = 5'hf == io_write_data_idx_3 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__16 = 5'h10 == io_write_data_idx_3 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__17 = 5'h11 == io_write_data_idx_3 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__18 = 5'h12 == io_write_data_idx_3 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__19 = 5'h13 == io_write_data_idx_3 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__20 = 5'h14 == io_write_data_idx_3 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__21 = 5'h15 == io_write_data_idx_3 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__22 = 5'h16 == io_write_data_idx_3 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__23 = 5'h17 == io_write_data_idx_3 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__24 = 5'h18 == io_write_data_idx_3 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__25 = 5'h19 == io_write_data_idx_3 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__26 = 5'h1a == io_write_data_idx_3 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__27 = 5'h1b == io_write_data_idx_3 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__28 = 5'h1c == io_write_data_idx_3 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__29 = 5'h1d == io_write_data_idx_3 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__30 = 5'h1e == io_write_data_idx_3 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value__31 = 5'h1f == io_write_data_idx_3 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_3_value_1_0 = io_write_data_dataout_3_value__0 | io_write_data_dataout_3_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_1 = io_write_data_dataout_3_value__2 | io_write_data_dataout_3_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_2 = io_write_data_dataout_3_value__4 | io_write_data_dataout_3_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_3 = io_write_data_dataout_3_value__6 | io_write_data_dataout_3_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_4 = io_write_data_dataout_3_value__8 | io_write_data_dataout_3_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_5 = io_write_data_dataout_3_value__10 | io_write_data_dataout_3_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_6 = io_write_data_dataout_3_value__12 | io_write_data_dataout_3_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_7 = io_write_data_dataout_3_value__14 | io_write_data_dataout_3_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_8 = io_write_data_dataout_3_value__16 | io_write_data_dataout_3_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_9 = io_write_data_dataout_3_value__18 | io_write_data_dataout_3_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_10 = io_write_data_dataout_3_value__20 | io_write_data_dataout_3_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_11 = io_write_data_dataout_3_value__22 | io_write_data_dataout_3_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_12 = io_write_data_dataout_3_value__24 | io_write_data_dataout_3_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_13 = io_write_data_dataout_3_value__26 | io_write_data_dataout_3_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_14 = io_write_data_dataout_3_value__28 | io_write_data_dataout_3_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_1_15 = io_write_data_dataout_3_value__30 | io_write_data_dataout_3_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_2_0 = io_write_data_dataout_3_value_1_0 | io_write_data_dataout_3_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_2_1 = io_write_data_dataout_3_value_1_2 | io_write_data_dataout_3_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_2_2 = io_write_data_dataout_3_value_1_4 | io_write_data_dataout_3_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_2_3 = io_write_data_dataout_3_value_1_6 | io_write_data_dataout_3_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_2_4 = io_write_data_dataout_3_value_1_8 | io_write_data_dataout_3_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_2_5 = io_write_data_dataout_3_value_1_10 | io_write_data_dataout_3_value_1_11
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_2_6 = io_write_data_dataout_3_value_1_12 | io_write_data_dataout_3_value_1_13
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_2_7 = io_write_data_dataout_3_value_1_14 | io_write_data_dataout_3_value_1_15
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_3_0 = io_write_data_dataout_3_value_2_0 | io_write_data_dataout_3_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_3_1 = io_write_data_dataout_3_value_2_2 | io_write_data_dataout_3_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_3_2 = io_write_data_dataout_3_value_2_4 | io_write_data_dataout_3_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_3_3 = io_write_data_dataout_3_value_2_6 | io_write_data_dataout_3_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_4_0 = io_write_data_dataout_3_value_3_0 | io_write_data_dataout_3_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_4_1 = io_write_data_dataout_3_value_3_2 | io_write_data_dataout_3_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_3_value_5_0 = io_write_data_dataout_3_value_4_0 | io_write_data_dataout_3_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_4 = 5'h4 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_4_value__0 = 5'h0 == io_write_data_idx_4 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__1 = 5'h1 == io_write_data_idx_4 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__2 = 5'h2 == io_write_data_idx_4 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__3 = 5'h3 == io_write_data_idx_4 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__4 = 5'h4 == io_write_data_idx_4 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__5 = 5'h5 == io_write_data_idx_4 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__6 = 5'h6 == io_write_data_idx_4 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__7 = 5'h7 == io_write_data_idx_4 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__8 = 5'h8 == io_write_data_idx_4 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__9 = 5'h9 == io_write_data_idx_4 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__10 = 5'ha == io_write_data_idx_4 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__11 = 5'hb == io_write_data_idx_4 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__12 = 5'hc == io_write_data_idx_4 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__13 = 5'hd == io_write_data_idx_4 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__14 = 5'he == io_write_data_idx_4 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__15 = 5'hf == io_write_data_idx_4 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__16 = 5'h10 == io_write_data_idx_4 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__17 = 5'h11 == io_write_data_idx_4 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__18 = 5'h12 == io_write_data_idx_4 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__19 = 5'h13 == io_write_data_idx_4 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__20 = 5'h14 == io_write_data_idx_4 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__21 = 5'h15 == io_write_data_idx_4 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__22 = 5'h16 == io_write_data_idx_4 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__23 = 5'h17 == io_write_data_idx_4 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__24 = 5'h18 == io_write_data_idx_4 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__25 = 5'h19 == io_write_data_idx_4 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__26 = 5'h1a == io_write_data_idx_4 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__27 = 5'h1b == io_write_data_idx_4 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__28 = 5'h1c == io_write_data_idx_4 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__29 = 5'h1d == io_write_data_idx_4 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__30 = 5'h1e == io_write_data_idx_4 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value__31 = 5'h1f == io_write_data_idx_4 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_4_value_1_0 = io_write_data_dataout_4_value__0 | io_write_data_dataout_4_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_1 = io_write_data_dataout_4_value__2 | io_write_data_dataout_4_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_2 = io_write_data_dataout_4_value__4 | io_write_data_dataout_4_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_3 = io_write_data_dataout_4_value__6 | io_write_data_dataout_4_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_4 = io_write_data_dataout_4_value__8 | io_write_data_dataout_4_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_5 = io_write_data_dataout_4_value__10 | io_write_data_dataout_4_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_6 = io_write_data_dataout_4_value__12 | io_write_data_dataout_4_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_7 = io_write_data_dataout_4_value__14 | io_write_data_dataout_4_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_8 = io_write_data_dataout_4_value__16 | io_write_data_dataout_4_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_9 = io_write_data_dataout_4_value__18 | io_write_data_dataout_4_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_10 = io_write_data_dataout_4_value__20 | io_write_data_dataout_4_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_11 = io_write_data_dataout_4_value__22 | io_write_data_dataout_4_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_12 = io_write_data_dataout_4_value__24 | io_write_data_dataout_4_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_13 = io_write_data_dataout_4_value__26 | io_write_data_dataout_4_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_14 = io_write_data_dataout_4_value__28 | io_write_data_dataout_4_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_1_15 = io_write_data_dataout_4_value__30 | io_write_data_dataout_4_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_2_0 = io_write_data_dataout_4_value_1_0 | io_write_data_dataout_4_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_2_1 = io_write_data_dataout_4_value_1_2 | io_write_data_dataout_4_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_2_2 = io_write_data_dataout_4_value_1_4 | io_write_data_dataout_4_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_2_3 = io_write_data_dataout_4_value_1_6 | io_write_data_dataout_4_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_2_4 = io_write_data_dataout_4_value_1_8 | io_write_data_dataout_4_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_2_5 = io_write_data_dataout_4_value_1_10 | io_write_data_dataout_4_value_1_11
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_2_6 = io_write_data_dataout_4_value_1_12 | io_write_data_dataout_4_value_1_13
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_2_7 = io_write_data_dataout_4_value_1_14 | io_write_data_dataout_4_value_1_15
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_3_0 = io_write_data_dataout_4_value_2_0 | io_write_data_dataout_4_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_3_1 = io_write_data_dataout_4_value_2_2 | io_write_data_dataout_4_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_3_2 = io_write_data_dataout_4_value_2_4 | io_write_data_dataout_4_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_3_3 = io_write_data_dataout_4_value_2_6 | io_write_data_dataout_4_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_4_0 = io_write_data_dataout_4_value_3_0 | io_write_data_dataout_4_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_4_1 = io_write_data_dataout_4_value_3_2 | io_write_data_dataout_4_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_4_value_5_0 = io_write_data_dataout_4_value_4_0 | io_write_data_dataout_4_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_5 = 5'h5 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_5_value__0 = 5'h0 == io_write_data_idx_5 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__1 = 5'h1 == io_write_data_idx_5 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__2 = 5'h2 == io_write_data_idx_5 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__3 = 5'h3 == io_write_data_idx_5 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__4 = 5'h4 == io_write_data_idx_5 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__5 = 5'h5 == io_write_data_idx_5 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__6 = 5'h6 == io_write_data_idx_5 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__7 = 5'h7 == io_write_data_idx_5 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__8 = 5'h8 == io_write_data_idx_5 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__9 = 5'h9 == io_write_data_idx_5 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__10 = 5'ha == io_write_data_idx_5 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__11 = 5'hb == io_write_data_idx_5 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__12 = 5'hc == io_write_data_idx_5 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__13 = 5'hd == io_write_data_idx_5 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__14 = 5'he == io_write_data_idx_5 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__15 = 5'hf == io_write_data_idx_5 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__16 = 5'h10 == io_write_data_idx_5 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__17 = 5'h11 == io_write_data_idx_5 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__18 = 5'h12 == io_write_data_idx_5 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__19 = 5'h13 == io_write_data_idx_5 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__20 = 5'h14 == io_write_data_idx_5 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__21 = 5'h15 == io_write_data_idx_5 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__22 = 5'h16 == io_write_data_idx_5 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__23 = 5'h17 == io_write_data_idx_5 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__24 = 5'h18 == io_write_data_idx_5 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__25 = 5'h19 == io_write_data_idx_5 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__26 = 5'h1a == io_write_data_idx_5 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__27 = 5'h1b == io_write_data_idx_5 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__28 = 5'h1c == io_write_data_idx_5 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__29 = 5'h1d == io_write_data_idx_5 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__30 = 5'h1e == io_write_data_idx_5 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value__31 = 5'h1f == io_write_data_idx_5 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_5_value_1_0 = io_write_data_dataout_5_value__0 | io_write_data_dataout_5_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_1 = io_write_data_dataout_5_value__2 | io_write_data_dataout_5_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_2 = io_write_data_dataout_5_value__4 | io_write_data_dataout_5_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_3 = io_write_data_dataout_5_value__6 | io_write_data_dataout_5_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_4 = io_write_data_dataout_5_value__8 | io_write_data_dataout_5_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_5 = io_write_data_dataout_5_value__10 | io_write_data_dataout_5_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_6 = io_write_data_dataout_5_value__12 | io_write_data_dataout_5_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_7 = io_write_data_dataout_5_value__14 | io_write_data_dataout_5_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_8 = io_write_data_dataout_5_value__16 | io_write_data_dataout_5_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_9 = io_write_data_dataout_5_value__18 | io_write_data_dataout_5_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_10 = io_write_data_dataout_5_value__20 | io_write_data_dataout_5_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_11 = io_write_data_dataout_5_value__22 | io_write_data_dataout_5_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_12 = io_write_data_dataout_5_value__24 | io_write_data_dataout_5_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_13 = io_write_data_dataout_5_value__26 | io_write_data_dataout_5_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_14 = io_write_data_dataout_5_value__28 | io_write_data_dataout_5_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_1_15 = io_write_data_dataout_5_value__30 | io_write_data_dataout_5_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_2_0 = io_write_data_dataout_5_value_1_0 | io_write_data_dataout_5_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_2_1 = io_write_data_dataout_5_value_1_2 | io_write_data_dataout_5_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_2_2 = io_write_data_dataout_5_value_1_4 | io_write_data_dataout_5_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_2_3 = io_write_data_dataout_5_value_1_6 | io_write_data_dataout_5_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_2_4 = io_write_data_dataout_5_value_1_8 | io_write_data_dataout_5_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_2_5 = io_write_data_dataout_5_value_1_10 | io_write_data_dataout_5_value_1_11
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_2_6 = io_write_data_dataout_5_value_1_12 | io_write_data_dataout_5_value_1_13
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_2_7 = io_write_data_dataout_5_value_1_14 | io_write_data_dataout_5_value_1_15
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_3_0 = io_write_data_dataout_5_value_2_0 | io_write_data_dataout_5_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_3_1 = io_write_data_dataout_5_value_2_2 | io_write_data_dataout_5_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_3_2 = io_write_data_dataout_5_value_2_4 | io_write_data_dataout_5_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_3_3 = io_write_data_dataout_5_value_2_6 | io_write_data_dataout_5_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_4_0 = io_write_data_dataout_5_value_3_0 | io_write_data_dataout_5_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_4_1 = io_write_data_dataout_5_value_3_2 | io_write_data_dataout_5_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_5_value_5_0 = io_write_data_dataout_5_value_4_0 | io_write_data_dataout_5_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_6 = 5'h6 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_6_value__0 = 5'h0 == io_write_data_idx_6 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__1 = 5'h1 == io_write_data_idx_6 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__2 = 5'h2 == io_write_data_idx_6 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__3 = 5'h3 == io_write_data_idx_6 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__4 = 5'h4 == io_write_data_idx_6 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__5 = 5'h5 == io_write_data_idx_6 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__6 = 5'h6 == io_write_data_idx_6 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__7 = 5'h7 == io_write_data_idx_6 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__8 = 5'h8 == io_write_data_idx_6 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__9 = 5'h9 == io_write_data_idx_6 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__10 = 5'ha == io_write_data_idx_6 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__11 = 5'hb == io_write_data_idx_6 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__12 = 5'hc == io_write_data_idx_6 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__13 = 5'hd == io_write_data_idx_6 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__14 = 5'he == io_write_data_idx_6 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__15 = 5'hf == io_write_data_idx_6 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__16 = 5'h10 == io_write_data_idx_6 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__17 = 5'h11 == io_write_data_idx_6 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__18 = 5'h12 == io_write_data_idx_6 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__19 = 5'h13 == io_write_data_idx_6 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__20 = 5'h14 == io_write_data_idx_6 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__21 = 5'h15 == io_write_data_idx_6 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__22 = 5'h16 == io_write_data_idx_6 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__23 = 5'h17 == io_write_data_idx_6 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__24 = 5'h18 == io_write_data_idx_6 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__25 = 5'h19 == io_write_data_idx_6 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__26 = 5'h1a == io_write_data_idx_6 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__27 = 5'h1b == io_write_data_idx_6 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__28 = 5'h1c == io_write_data_idx_6 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__29 = 5'h1d == io_write_data_idx_6 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__30 = 5'h1e == io_write_data_idx_6 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value__31 = 5'h1f == io_write_data_idx_6 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_6_value_1_0 = io_write_data_dataout_6_value__0 | io_write_data_dataout_6_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_1 = io_write_data_dataout_6_value__2 | io_write_data_dataout_6_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_2 = io_write_data_dataout_6_value__4 | io_write_data_dataout_6_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_3 = io_write_data_dataout_6_value__6 | io_write_data_dataout_6_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_4 = io_write_data_dataout_6_value__8 | io_write_data_dataout_6_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_5 = io_write_data_dataout_6_value__10 | io_write_data_dataout_6_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_6 = io_write_data_dataout_6_value__12 | io_write_data_dataout_6_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_7 = io_write_data_dataout_6_value__14 | io_write_data_dataout_6_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_8 = io_write_data_dataout_6_value__16 | io_write_data_dataout_6_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_9 = io_write_data_dataout_6_value__18 | io_write_data_dataout_6_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_10 = io_write_data_dataout_6_value__20 | io_write_data_dataout_6_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_11 = io_write_data_dataout_6_value__22 | io_write_data_dataout_6_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_12 = io_write_data_dataout_6_value__24 | io_write_data_dataout_6_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_13 = io_write_data_dataout_6_value__26 | io_write_data_dataout_6_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_14 = io_write_data_dataout_6_value__28 | io_write_data_dataout_6_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_1_15 = io_write_data_dataout_6_value__30 | io_write_data_dataout_6_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_2_0 = io_write_data_dataout_6_value_1_0 | io_write_data_dataout_6_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_2_1 = io_write_data_dataout_6_value_1_2 | io_write_data_dataout_6_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_2_2 = io_write_data_dataout_6_value_1_4 | io_write_data_dataout_6_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_2_3 = io_write_data_dataout_6_value_1_6 | io_write_data_dataout_6_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_2_4 = io_write_data_dataout_6_value_1_8 | io_write_data_dataout_6_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_2_5 = io_write_data_dataout_6_value_1_10 | io_write_data_dataout_6_value_1_11
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_2_6 = io_write_data_dataout_6_value_1_12 | io_write_data_dataout_6_value_1_13
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_2_7 = io_write_data_dataout_6_value_1_14 | io_write_data_dataout_6_value_1_15
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_3_0 = io_write_data_dataout_6_value_2_0 | io_write_data_dataout_6_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_3_1 = io_write_data_dataout_6_value_2_2 | io_write_data_dataout_6_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_3_2 = io_write_data_dataout_6_value_2_4 | io_write_data_dataout_6_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_3_3 = io_write_data_dataout_6_value_2_6 | io_write_data_dataout_6_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_4_0 = io_write_data_dataout_6_value_3_0 | io_write_data_dataout_6_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_4_1 = io_write_data_dataout_6_value_3_2 | io_write_data_dataout_6_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_6_value_5_0 = io_write_data_dataout_6_value_4_0 | io_write_data_dataout_6_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_7 = 5'h7 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_7_value__0 = 5'h0 == io_write_data_idx_7 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__1 = 5'h1 == io_write_data_idx_7 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__2 = 5'h2 == io_write_data_idx_7 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__3 = 5'h3 == io_write_data_idx_7 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__4 = 5'h4 == io_write_data_idx_7 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__5 = 5'h5 == io_write_data_idx_7 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__6 = 5'h6 == io_write_data_idx_7 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__7 = 5'h7 == io_write_data_idx_7 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__8 = 5'h8 == io_write_data_idx_7 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__9 = 5'h9 == io_write_data_idx_7 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__10 = 5'ha == io_write_data_idx_7 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__11 = 5'hb == io_write_data_idx_7 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__12 = 5'hc == io_write_data_idx_7 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__13 = 5'hd == io_write_data_idx_7 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__14 = 5'he == io_write_data_idx_7 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__15 = 5'hf == io_write_data_idx_7 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__16 = 5'h10 == io_write_data_idx_7 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__17 = 5'h11 == io_write_data_idx_7 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__18 = 5'h12 == io_write_data_idx_7 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__19 = 5'h13 == io_write_data_idx_7 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__20 = 5'h14 == io_write_data_idx_7 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__21 = 5'h15 == io_write_data_idx_7 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__22 = 5'h16 == io_write_data_idx_7 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__23 = 5'h17 == io_write_data_idx_7 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__24 = 5'h18 == io_write_data_idx_7 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__25 = 5'h19 == io_write_data_idx_7 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__26 = 5'h1a == io_write_data_idx_7 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__27 = 5'h1b == io_write_data_idx_7 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__28 = 5'h1c == io_write_data_idx_7 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__29 = 5'h1d == io_write_data_idx_7 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__30 = 5'h1e == io_write_data_idx_7 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value__31 = 5'h1f == io_write_data_idx_7 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_7_value_1_0 = io_write_data_dataout_7_value__0 | io_write_data_dataout_7_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_1 = io_write_data_dataout_7_value__2 | io_write_data_dataout_7_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_2 = io_write_data_dataout_7_value__4 | io_write_data_dataout_7_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_3 = io_write_data_dataout_7_value__6 | io_write_data_dataout_7_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_4 = io_write_data_dataout_7_value__8 | io_write_data_dataout_7_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_5 = io_write_data_dataout_7_value__10 | io_write_data_dataout_7_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_6 = io_write_data_dataout_7_value__12 | io_write_data_dataout_7_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_7 = io_write_data_dataout_7_value__14 | io_write_data_dataout_7_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_8 = io_write_data_dataout_7_value__16 | io_write_data_dataout_7_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_9 = io_write_data_dataout_7_value__18 | io_write_data_dataout_7_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_10 = io_write_data_dataout_7_value__20 | io_write_data_dataout_7_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_11 = io_write_data_dataout_7_value__22 | io_write_data_dataout_7_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_12 = io_write_data_dataout_7_value__24 | io_write_data_dataout_7_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_13 = io_write_data_dataout_7_value__26 | io_write_data_dataout_7_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_14 = io_write_data_dataout_7_value__28 | io_write_data_dataout_7_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_1_15 = io_write_data_dataout_7_value__30 | io_write_data_dataout_7_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_2_0 = io_write_data_dataout_7_value_1_0 | io_write_data_dataout_7_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_2_1 = io_write_data_dataout_7_value_1_2 | io_write_data_dataout_7_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_2_2 = io_write_data_dataout_7_value_1_4 | io_write_data_dataout_7_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_2_3 = io_write_data_dataout_7_value_1_6 | io_write_data_dataout_7_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_2_4 = io_write_data_dataout_7_value_1_8 | io_write_data_dataout_7_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_2_5 = io_write_data_dataout_7_value_1_10 | io_write_data_dataout_7_value_1_11
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_2_6 = io_write_data_dataout_7_value_1_12 | io_write_data_dataout_7_value_1_13
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_2_7 = io_write_data_dataout_7_value_1_14 | io_write_data_dataout_7_value_1_15
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_3_0 = io_write_data_dataout_7_value_2_0 | io_write_data_dataout_7_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_3_1 = io_write_data_dataout_7_value_2_2 | io_write_data_dataout_7_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_3_2 = io_write_data_dataout_7_value_2_4 | io_write_data_dataout_7_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_3_3 = io_write_data_dataout_7_value_2_6 | io_write_data_dataout_7_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_4_0 = io_write_data_dataout_7_value_3_0 | io_write_data_dataout_7_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_4_1 = io_write_data_dataout_7_value_3_2 | io_write_data_dataout_7_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_7_value_5_0 = io_write_data_dataout_7_value_4_0 | io_write_data_dataout_7_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_8 = 5'h8 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_8_value__0 = 5'h0 == io_write_data_idx_8 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__1 = 5'h1 == io_write_data_idx_8 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__2 = 5'h2 == io_write_data_idx_8 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__3 = 5'h3 == io_write_data_idx_8 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__4 = 5'h4 == io_write_data_idx_8 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__5 = 5'h5 == io_write_data_idx_8 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__6 = 5'h6 == io_write_data_idx_8 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__7 = 5'h7 == io_write_data_idx_8 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__8 = 5'h8 == io_write_data_idx_8 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__9 = 5'h9 == io_write_data_idx_8 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__10 = 5'ha == io_write_data_idx_8 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__11 = 5'hb == io_write_data_idx_8 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__12 = 5'hc == io_write_data_idx_8 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__13 = 5'hd == io_write_data_idx_8 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__14 = 5'he == io_write_data_idx_8 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__15 = 5'hf == io_write_data_idx_8 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__16 = 5'h10 == io_write_data_idx_8 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__17 = 5'h11 == io_write_data_idx_8 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__18 = 5'h12 == io_write_data_idx_8 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__19 = 5'h13 == io_write_data_idx_8 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__20 = 5'h14 == io_write_data_idx_8 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__21 = 5'h15 == io_write_data_idx_8 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__22 = 5'h16 == io_write_data_idx_8 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__23 = 5'h17 == io_write_data_idx_8 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__24 = 5'h18 == io_write_data_idx_8 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__25 = 5'h19 == io_write_data_idx_8 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__26 = 5'h1a == io_write_data_idx_8 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__27 = 5'h1b == io_write_data_idx_8 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__28 = 5'h1c == io_write_data_idx_8 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__29 = 5'h1d == io_write_data_idx_8 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__30 = 5'h1e == io_write_data_idx_8 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value__31 = 5'h1f == io_write_data_idx_8 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_8_value_1_0 = io_write_data_dataout_8_value__0 | io_write_data_dataout_8_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_1 = io_write_data_dataout_8_value__2 | io_write_data_dataout_8_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_2 = io_write_data_dataout_8_value__4 | io_write_data_dataout_8_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_3 = io_write_data_dataout_8_value__6 | io_write_data_dataout_8_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_4 = io_write_data_dataout_8_value__8 | io_write_data_dataout_8_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_5 = io_write_data_dataout_8_value__10 | io_write_data_dataout_8_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_6 = io_write_data_dataout_8_value__12 | io_write_data_dataout_8_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_7 = io_write_data_dataout_8_value__14 | io_write_data_dataout_8_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_8 = io_write_data_dataout_8_value__16 | io_write_data_dataout_8_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_9 = io_write_data_dataout_8_value__18 | io_write_data_dataout_8_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_10 = io_write_data_dataout_8_value__20 | io_write_data_dataout_8_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_11 = io_write_data_dataout_8_value__22 | io_write_data_dataout_8_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_12 = io_write_data_dataout_8_value__24 | io_write_data_dataout_8_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_13 = io_write_data_dataout_8_value__26 | io_write_data_dataout_8_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_14 = io_write_data_dataout_8_value__28 | io_write_data_dataout_8_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_1_15 = io_write_data_dataout_8_value__30 | io_write_data_dataout_8_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_2_0 = io_write_data_dataout_8_value_1_0 | io_write_data_dataout_8_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_2_1 = io_write_data_dataout_8_value_1_2 | io_write_data_dataout_8_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_2_2 = io_write_data_dataout_8_value_1_4 | io_write_data_dataout_8_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_2_3 = io_write_data_dataout_8_value_1_6 | io_write_data_dataout_8_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_2_4 = io_write_data_dataout_8_value_1_8 | io_write_data_dataout_8_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_2_5 = io_write_data_dataout_8_value_1_10 | io_write_data_dataout_8_value_1_11
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_2_6 = io_write_data_dataout_8_value_1_12 | io_write_data_dataout_8_value_1_13
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_2_7 = io_write_data_dataout_8_value_1_14 | io_write_data_dataout_8_value_1_15
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_3_0 = io_write_data_dataout_8_value_2_0 | io_write_data_dataout_8_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_3_1 = io_write_data_dataout_8_value_2_2 | io_write_data_dataout_8_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_3_2 = io_write_data_dataout_8_value_2_4 | io_write_data_dataout_8_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_3_3 = io_write_data_dataout_8_value_2_6 | io_write_data_dataout_8_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_4_0 = io_write_data_dataout_8_value_3_0 | io_write_data_dataout_8_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_4_1 = io_write_data_dataout_8_value_3_2 | io_write_data_dataout_8_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_8_value_5_0 = io_write_data_dataout_8_value_4_0 | io_write_data_dataout_8_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_9 = 5'h9 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_9_value__0 = 5'h0 == io_write_data_idx_9 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__1 = 5'h1 == io_write_data_idx_9 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__2 = 5'h2 == io_write_data_idx_9 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__3 = 5'h3 == io_write_data_idx_9 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__4 = 5'h4 == io_write_data_idx_9 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__5 = 5'h5 == io_write_data_idx_9 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__6 = 5'h6 == io_write_data_idx_9 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__7 = 5'h7 == io_write_data_idx_9 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__8 = 5'h8 == io_write_data_idx_9 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__9 = 5'h9 == io_write_data_idx_9 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__10 = 5'ha == io_write_data_idx_9 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__11 = 5'hb == io_write_data_idx_9 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__12 = 5'hc == io_write_data_idx_9 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__13 = 5'hd == io_write_data_idx_9 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__14 = 5'he == io_write_data_idx_9 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__15 = 5'hf == io_write_data_idx_9 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__16 = 5'h10 == io_write_data_idx_9 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__17 = 5'h11 == io_write_data_idx_9 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__18 = 5'h12 == io_write_data_idx_9 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__19 = 5'h13 == io_write_data_idx_9 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__20 = 5'h14 == io_write_data_idx_9 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__21 = 5'h15 == io_write_data_idx_9 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__22 = 5'h16 == io_write_data_idx_9 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__23 = 5'h17 == io_write_data_idx_9 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__24 = 5'h18 == io_write_data_idx_9 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__25 = 5'h19 == io_write_data_idx_9 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__26 = 5'h1a == io_write_data_idx_9 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__27 = 5'h1b == io_write_data_idx_9 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__28 = 5'h1c == io_write_data_idx_9 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__29 = 5'h1d == io_write_data_idx_9 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__30 = 5'h1e == io_write_data_idx_9 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value__31 = 5'h1f == io_write_data_idx_9 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_9_value_1_0 = io_write_data_dataout_9_value__0 | io_write_data_dataout_9_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_1 = io_write_data_dataout_9_value__2 | io_write_data_dataout_9_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_2 = io_write_data_dataout_9_value__4 | io_write_data_dataout_9_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_3 = io_write_data_dataout_9_value__6 | io_write_data_dataout_9_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_4 = io_write_data_dataout_9_value__8 | io_write_data_dataout_9_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_5 = io_write_data_dataout_9_value__10 | io_write_data_dataout_9_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_6 = io_write_data_dataout_9_value__12 | io_write_data_dataout_9_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_7 = io_write_data_dataout_9_value__14 | io_write_data_dataout_9_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_8 = io_write_data_dataout_9_value__16 | io_write_data_dataout_9_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_9 = io_write_data_dataout_9_value__18 | io_write_data_dataout_9_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_10 = io_write_data_dataout_9_value__20 | io_write_data_dataout_9_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_11 = io_write_data_dataout_9_value__22 | io_write_data_dataout_9_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_12 = io_write_data_dataout_9_value__24 | io_write_data_dataout_9_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_13 = io_write_data_dataout_9_value__26 | io_write_data_dataout_9_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_14 = io_write_data_dataout_9_value__28 | io_write_data_dataout_9_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_1_15 = io_write_data_dataout_9_value__30 | io_write_data_dataout_9_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_2_0 = io_write_data_dataout_9_value_1_0 | io_write_data_dataout_9_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_2_1 = io_write_data_dataout_9_value_1_2 | io_write_data_dataout_9_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_2_2 = io_write_data_dataout_9_value_1_4 | io_write_data_dataout_9_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_2_3 = io_write_data_dataout_9_value_1_6 | io_write_data_dataout_9_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_2_4 = io_write_data_dataout_9_value_1_8 | io_write_data_dataout_9_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_2_5 = io_write_data_dataout_9_value_1_10 | io_write_data_dataout_9_value_1_11
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_2_6 = io_write_data_dataout_9_value_1_12 | io_write_data_dataout_9_value_1_13
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_2_7 = io_write_data_dataout_9_value_1_14 | io_write_data_dataout_9_value_1_15
- ; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_3_0 = io_write_data_dataout_9_value_2_0 | io_write_data_dataout_9_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_3_1 = io_write_data_dataout_9_value_2_2 | io_write_data_dataout_9_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_3_2 = io_write_data_dataout_9_value_2_4 | io_write_data_dataout_9_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_3_3 = io_write_data_dataout_9_value_2_6 | io_write_data_dataout_9_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_4_0 = io_write_data_dataout_9_value_3_0 | io_write_data_dataout_9_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_4_1 = io_write_data_dataout_9_value_3_2 | io_write_data_dataout_9_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_9_value_5_0 = io_write_data_dataout_9_value_4_0 | io_write_data_dataout_9_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_10 = 5'ha + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_10_value__0 = 5'h0 == io_write_data_idx_10 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__1 = 5'h1 == io_write_data_idx_10 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__2 = 5'h2 == io_write_data_idx_10 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__3 = 5'h3 == io_write_data_idx_10 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__4 = 5'h4 == io_write_data_idx_10 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__5 = 5'h5 == io_write_data_idx_10 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__6 = 5'h6 == io_write_data_idx_10 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__7 = 5'h7 == io_write_data_idx_10 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__8 = 5'h8 == io_write_data_idx_10 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__9 = 5'h9 == io_write_data_idx_10 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__10 = 5'ha == io_write_data_idx_10 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__11 = 5'hb == io_write_data_idx_10 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__12 = 5'hc == io_write_data_idx_10 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__13 = 5'hd == io_write_data_idx_10 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__14 = 5'he == io_write_data_idx_10 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__15 = 5'hf == io_write_data_idx_10 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__16 = 5'h10 == io_write_data_idx_10 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__17 = 5'h11 == io_write_data_idx_10 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__18 = 5'h12 == io_write_data_idx_10 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__19 = 5'h13 == io_write_data_idx_10 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__20 = 5'h14 == io_write_data_idx_10 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__21 = 5'h15 == io_write_data_idx_10 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__22 = 5'h16 == io_write_data_idx_10 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__23 = 5'h17 == io_write_data_idx_10 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__24 = 5'h18 == io_write_data_idx_10 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__25 = 5'h19 == io_write_data_idx_10 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__26 = 5'h1a == io_write_data_idx_10 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__27 = 5'h1b == io_write_data_idx_10 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__28 = 5'h1c == io_write_data_idx_10 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__29 = 5'h1d == io_write_data_idx_10 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__30 = 5'h1e == io_write_data_idx_10 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value__31 = 5'h1f == io_write_data_idx_10 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_10_value_1_0 = io_write_data_dataout_10_value__0 | io_write_data_dataout_10_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_1 = io_write_data_dataout_10_value__2 | io_write_data_dataout_10_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_2 = io_write_data_dataout_10_value__4 | io_write_data_dataout_10_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_3 = io_write_data_dataout_10_value__6 | io_write_data_dataout_10_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_4 = io_write_data_dataout_10_value__8 | io_write_data_dataout_10_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_5 = io_write_data_dataout_10_value__10 |
- io_write_data_dataout_10_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_6 = io_write_data_dataout_10_value__12 |
- io_write_data_dataout_10_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_7 = io_write_data_dataout_10_value__14 |
- io_write_data_dataout_10_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_8 = io_write_data_dataout_10_value__16 |
- io_write_data_dataout_10_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_9 = io_write_data_dataout_10_value__18 |
- io_write_data_dataout_10_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_10 = io_write_data_dataout_10_value__20 |
- io_write_data_dataout_10_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_11 = io_write_data_dataout_10_value__22 |
- io_write_data_dataout_10_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_12 = io_write_data_dataout_10_value__24 |
- io_write_data_dataout_10_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_13 = io_write_data_dataout_10_value__26 |
- io_write_data_dataout_10_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_14 = io_write_data_dataout_10_value__28 |
- io_write_data_dataout_10_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_1_15 = io_write_data_dataout_10_value__30 |
- io_write_data_dataout_10_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_2_0 = io_write_data_dataout_10_value_1_0 |
- io_write_data_dataout_10_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_2_1 = io_write_data_dataout_10_value_1_2 |
- io_write_data_dataout_10_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_2_2 = io_write_data_dataout_10_value_1_4 |
- io_write_data_dataout_10_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_2_3 = io_write_data_dataout_10_value_1_6 |
- io_write_data_dataout_10_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_2_4 = io_write_data_dataout_10_value_1_8 |
- io_write_data_dataout_10_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_2_5 = io_write_data_dataout_10_value_1_10 |
- io_write_data_dataout_10_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_2_6 = io_write_data_dataout_10_value_1_12 |
- io_write_data_dataout_10_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_2_7 = io_write_data_dataout_10_value_1_14 |
- io_write_data_dataout_10_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_3_0 = io_write_data_dataout_10_value_2_0 |
- io_write_data_dataout_10_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_3_1 = io_write_data_dataout_10_value_2_2 |
- io_write_data_dataout_10_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_3_2 = io_write_data_dataout_10_value_2_4 |
- io_write_data_dataout_10_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_3_3 = io_write_data_dataout_10_value_2_6 |
- io_write_data_dataout_10_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_4_0 = io_write_data_dataout_10_value_3_0 |
- io_write_data_dataout_10_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_4_1 = io_write_data_dataout_10_value_3_2 |
- io_write_data_dataout_10_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_10_value_5_0 = io_write_data_dataout_10_value_4_0 |
- io_write_data_dataout_10_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_11 = 5'hb + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_11_value__0 = 5'h0 == io_write_data_idx_11 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__1 = 5'h1 == io_write_data_idx_11 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__2 = 5'h2 == io_write_data_idx_11 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__3 = 5'h3 == io_write_data_idx_11 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__4 = 5'h4 == io_write_data_idx_11 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__5 = 5'h5 == io_write_data_idx_11 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__6 = 5'h6 == io_write_data_idx_11 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__7 = 5'h7 == io_write_data_idx_11 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__8 = 5'h8 == io_write_data_idx_11 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__9 = 5'h9 == io_write_data_idx_11 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__10 = 5'ha == io_write_data_idx_11 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__11 = 5'hb == io_write_data_idx_11 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__12 = 5'hc == io_write_data_idx_11 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__13 = 5'hd == io_write_data_idx_11 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__14 = 5'he == io_write_data_idx_11 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__15 = 5'hf == io_write_data_idx_11 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__16 = 5'h10 == io_write_data_idx_11 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__17 = 5'h11 == io_write_data_idx_11 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__18 = 5'h12 == io_write_data_idx_11 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__19 = 5'h13 == io_write_data_idx_11 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__20 = 5'h14 == io_write_data_idx_11 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__21 = 5'h15 == io_write_data_idx_11 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__22 = 5'h16 == io_write_data_idx_11 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__23 = 5'h17 == io_write_data_idx_11 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__24 = 5'h18 == io_write_data_idx_11 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__25 = 5'h19 == io_write_data_idx_11 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__26 = 5'h1a == io_write_data_idx_11 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__27 = 5'h1b == io_write_data_idx_11 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__28 = 5'h1c == io_write_data_idx_11 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__29 = 5'h1d == io_write_data_idx_11 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__30 = 5'h1e == io_write_data_idx_11 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value__31 = 5'h1f == io_write_data_idx_11 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_11_value_1_0 = io_write_data_dataout_11_value__0 | io_write_data_dataout_11_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_1 = io_write_data_dataout_11_value__2 | io_write_data_dataout_11_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_2 = io_write_data_dataout_11_value__4 | io_write_data_dataout_11_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_3 = io_write_data_dataout_11_value__6 | io_write_data_dataout_11_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_4 = io_write_data_dataout_11_value__8 | io_write_data_dataout_11_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_5 = io_write_data_dataout_11_value__10 |
- io_write_data_dataout_11_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_6 = io_write_data_dataout_11_value__12 |
- io_write_data_dataout_11_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_7 = io_write_data_dataout_11_value__14 |
- io_write_data_dataout_11_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_8 = io_write_data_dataout_11_value__16 |
- io_write_data_dataout_11_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_9 = io_write_data_dataout_11_value__18 |
- io_write_data_dataout_11_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_10 = io_write_data_dataout_11_value__20 |
- io_write_data_dataout_11_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_11 = io_write_data_dataout_11_value__22 |
- io_write_data_dataout_11_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_12 = io_write_data_dataout_11_value__24 |
- io_write_data_dataout_11_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_13 = io_write_data_dataout_11_value__26 |
- io_write_data_dataout_11_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_14 = io_write_data_dataout_11_value__28 |
- io_write_data_dataout_11_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_1_15 = io_write_data_dataout_11_value__30 |
- io_write_data_dataout_11_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_2_0 = io_write_data_dataout_11_value_1_0 |
- io_write_data_dataout_11_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_2_1 = io_write_data_dataout_11_value_1_2 |
- io_write_data_dataout_11_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_2_2 = io_write_data_dataout_11_value_1_4 |
- io_write_data_dataout_11_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_2_3 = io_write_data_dataout_11_value_1_6 |
- io_write_data_dataout_11_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_2_4 = io_write_data_dataout_11_value_1_8 |
- io_write_data_dataout_11_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_2_5 = io_write_data_dataout_11_value_1_10 |
- io_write_data_dataout_11_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_2_6 = io_write_data_dataout_11_value_1_12 |
- io_write_data_dataout_11_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_2_7 = io_write_data_dataout_11_value_1_14 |
- io_write_data_dataout_11_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_3_0 = io_write_data_dataout_11_value_2_0 |
- io_write_data_dataout_11_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_3_1 = io_write_data_dataout_11_value_2_2 |
- io_write_data_dataout_11_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_3_2 = io_write_data_dataout_11_value_2_4 |
- io_write_data_dataout_11_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_3_3 = io_write_data_dataout_11_value_2_6 |
- io_write_data_dataout_11_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_4_0 = io_write_data_dataout_11_value_3_0 |
- io_write_data_dataout_11_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_4_1 = io_write_data_dataout_11_value_3_2 |
- io_write_data_dataout_11_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_11_value_5_0 = io_write_data_dataout_11_value_4_0 |
- io_write_data_dataout_11_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_12 = 5'hc + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_12_value__0 = 5'h0 == io_write_data_idx_12 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__1 = 5'h1 == io_write_data_idx_12 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__2 = 5'h2 == io_write_data_idx_12 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__3 = 5'h3 == io_write_data_idx_12 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__4 = 5'h4 == io_write_data_idx_12 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__5 = 5'h5 == io_write_data_idx_12 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__6 = 5'h6 == io_write_data_idx_12 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__7 = 5'h7 == io_write_data_idx_12 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__8 = 5'h8 == io_write_data_idx_12 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__9 = 5'h9 == io_write_data_idx_12 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__10 = 5'ha == io_write_data_idx_12 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__11 = 5'hb == io_write_data_idx_12 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__12 = 5'hc == io_write_data_idx_12 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__13 = 5'hd == io_write_data_idx_12 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__14 = 5'he == io_write_data_idx_12 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__15 = 5'hf == io_write_data_idx_12 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__16 = 5'h10 == io_write_data_idx_12 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__17 = 5'h11 == io_write_data_idx_12 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__18 = 5'h12 == io_write_data_idx_12 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__19 = 5'h13 == io_write_data_idx_12 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__20 = 5'h14 == io_write_data_idx_12 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__21 = 5'h15 == io_write_data_idx_12 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__22 = 5'h16 == io_write_data_idx_12 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__23 = 5'h17 == io_write_data_idx_12 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__24 = 5'h18 == io_write_data_idx_12 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__25 = 5'h19 == io_write_data_idx_12 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__26 = 5'h1a == io_write_data_idx_12 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__27 = 5'h1b == io_write_data_idx_12 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__28 = 5'h1c == io_write_data_idx_12 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__29 = 5'h1d == io_write_data_idx_12 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__30 = 5'h1e == io_write_data_idx_12 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value__31 = 5'h1f == io_write_data_idx_12 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_12_value_1_0 = io_write_data_dataout_12_value__0 | io_write_data_dataout_12_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_1 = io_write_data_dataout_12_value__2 | io_write_data_dataout_12_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_2 = io_write_data_dataout_12_value__4 | io_write_data_dataout_12_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_3 = io_write_data_dataout_12_value__6 | io_write_data_dataout_12_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_4 = io_write_data_dataout_12_value__8 | io_write_data_dataout_12_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_5 = io_write_data_dataout_12_value__10 |
- io_write_data_dataout_12_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_6 = io_write_data_dataout_12_value__12 |
- io_write_data_dataout_12_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_7 = io_write_data_dataout_12_value__14 |
- io_write_data_dataout_12_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_8 = io_write_data_dataout_12_value__16 |
- io_write_data_dataout_12_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_9 = io_write_data_dataout_12_value__18 |
- io_write_data_dataout_12_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_10 = io_write_data_dataout_12_value__20 |
- io_write_data_dataout_12_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_11 = io_write_data_dataout_12_value__22 |
- io_write_data_dataout_12_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_12 = io_write_data_dataout_12_value__24 |
- io_write_data_dataout_12_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_13 = io_write_data_dataout_12_value__26 |
- io_write_data_dataout_12_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_14 = io_write_data_dataout_12_value__28 |
- io_write_data_dataout_12_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_1_15 = io_write_data_dataout_12_value__30 |
- io_write_data_dataout_12_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_2_0 = io_write_data_dataout_12_value_1_0 |
- io_write_data_dataout_12_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_2_1 = io_write_data_dataout_12_value_1_2 |
- io_write_data_dataout_12_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_2_2 = io_write_data_dataout_12_value_1_4 |
- io_write_data_dataout_12_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_2_3 = io_write_data_dataout_12_value_1_6 |
- io_write_data_dataout_12_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_2_4 = io_write_data_dataout_12_value_1_8 |
- io_write_data_dataout_12_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_2_5 = io_write_data_dataout_12_value_1_10 |
- io_write_data_dataout_12_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_2_6 = io_write_data_dataout_12_value_1_12 |
- io_write_data_dataout_12_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_2_7 = io_write_data_dataout_12_value_1_14 |
- io_write_data_dataout_12_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_3_0 = io_write_data_dataout_12_value_2_0 |
- io_write_data_dataout_12_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_3_1 = io_write_data_dataout_12_value_2_2 |
- io_write_data_dataout_12_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_3_2 = io_write_data_dataout_12_value_2_4 |
- io_write_data_dataout_12_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_3_3 = io_write_data_dataout_12_value_2_6 |
- io_write_data_dataout_12_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_4_0 = io_write_data_dataout_12_value_3_0 |
- io_write_data_dataout_12_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_4_1 = io_write_data_dataout_12_value_3_2 |
- io_write_data_dataout_12_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_12_value_5_0 = io_write_data_dataout_12_value_4_0 |
- io_write_data_dataout_12_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_13 = 5'hd + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_13_value__0 = 5'h0 == io_write_data_idx_13 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__1 = 5'h1 == io_write_data_idx_13 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__2 = 5'h2 == io_write_data_idx_13 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__3 = 5'h3 == io_write_data_idx_13 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__4 = 5'h4 == io_write_data_idx_13 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__5 = 5'h5 == io_write_data_idx_13 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__6 = 5'h6 == io_write_data_idx_13 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__7 = 5'h7 == io_write_data_idx_13 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__8 = 5'h8 == io_write_data_idx_13 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__9 = 5'h9 == io_write_data_idx_13 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__10 = 5'ha == io_write_data_idx_13 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__11 = 5'hb == io_write_data_idx_13 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__12 = 5'hc == io_write_data_idx_13 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__13 = 5'hd == io_write_data_idx_13 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__14 = 5'he == io_write_data_idx_13 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__15 = 5'hf == io_write_data_idx_13 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__16 = 5'h10 == io_write_data_idx_13 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__17 = 5'h11 == io_write_data_idx_13 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__18 = 5'h12 == io_write_data_idx_13 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__19 = 5'h13 == io_write_data_idx_13 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__20 = 5'h14 == io_write_data_idx_13 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__21 = 5'h15 == io_write_data_idx_13 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__22 = 5'h16 == io_write_data_idx_13 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__23 = 5'h17 == io_write_data_idx_13 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__24 = 5'h18 == io_write_data_idx_13 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__25 = 5'h19 == io_write_data_idx_13 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__26 = 5'h1a == io_write_data_idx_13 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__27 = 5'h1b == io_write_data_idx_13 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__28 = 5'h1c == io_write_data_idx_13 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__29 = 5'h1d == io_write_data_idx_13 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__30 = 5'h1e == io_write_data_idx_13 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value__31 = 5'h1f == io_write_data_idx_13 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_13_value_1_0 = io_write_data_dataout_13_value__0 | io_write_data_dataout_13_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_1 = io_write_data_dataout_13_value__2 | io_write_data_dataout_13_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_2 = io_write_data_dataout_13_value__4 | io_write_data_dataout_13_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_3 = io_write_data_dataout_13_value__6 | io_write_data_dataout_13_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_4 = io_write_data_dataout_13_value__8 | io_write_data_dataout_13_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_5 = io_write_data_dataout_13_value__10 |
- io_write_data_dataout_13_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_6 = io_write_data_dataout_13_value__12 |
- io_write_data_dataout_13_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_7 = io_write_data_dataout_13_value__14 |
- io_write_data_dataout_13_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_8 = io_write_data_dataout_13_value__16 |
- io_write_data_dataout_13_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_9 = io_write_data_dataout_13_value__18 |
- io_write_data_dataout_13_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_10 = io_write_data_dataout_13_value__20 |
- io_write_data_dataout_13_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_11 = io_write_data_dataout_13_value__22 |
- io_write_data_dataout_13_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_12 = io_write_data_dataout_13_value__24 |
- io_write_data_dataout_13_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_13 = io_write_data_dataout_13_value__26 |
- io_write_data_dataout_13_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_14 = io_write_data_dataout_13_value__28 |
- io_write_data_dataout_13_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_1_15 = io_write_data_dataout_13_value__30 |
- io_write_data_dataout_13_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_2_0 = io_write_data_dataout_13_value_1_0 |
- io_write_data_dataout_13_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_2_1 = io_write_data_dataout_13_value_1_2 |
- io_write_data_dataout_13_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_2_2 = io_write_data_dataout_13_value_1_4 |
- io_write_data_dataout_13_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_2_3 = io_write_data_dataout_13_value_1_6 |
- io_write_data_dataout_13_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_2_4 = io_write_data_dataout_13_value_1_8 |
- io_write_data_dataout_13_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_2_5 = io_write_data_dataout_13_value_1_10 |
- io_write_data_dataout_13_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_2_6 = io_write_data_dataout_13_value_1_12 |
- io_write_data_dataout_13_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_2_7 = io_write_data_dataout_13_value_1_14 |
- io_write_data_dataout_13_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_3_0 = io_write_data_dataout_13_value_2_0 |
- io_write_data_dataout_13_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_3_1 = io_write_data_dataout_13_value_2_2 |
- io_write_data_dataout_13_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_3_2 = io_write_data_dataout_13_value_2_4 |
- io_write_data_dataout_13_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_3_3 = io_write_data_dataout_13_value_2_6 |
- io_write_data_dataout_13_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_4_0 = io_write_data_dataout_13_value_3_0 |
- io_write_data_dataout_13_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_4_1 = io_write_data_dataout_13_value_3_2 |
- io_write_data_dataout_13_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_13_value_5_0 = io_write_data_dataout_13_value_4_0 |
- io_write_data_dataout_13_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_14 = 5'he + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_14_value__0 = 5'h0 == io_write_data_idx_14 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__1 = 5'h1 == io_write_data_idx_14 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__2 = 5'h2 == io_write_data_idx_14 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__3 = 5'h3 == io_write_data_idx_14 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__4 = 5'h4 == io_write_data_idx_14 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__5 = 5'h5 == io_write_data_idx_14 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__6 = 5'h6 == io_write_data_idx_14 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__7 = 5'h7 == io_write_data_idx_14 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__8 = 5'h8 == io_write_data_idx_14 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__9 = 5'h9 == io_write_data_idx_14 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__10 = 5'ha == io_write_data_idx_14 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__11 = 5'hb == io_write_data_idx_14 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__12 = 5'hc == io_write_data_idx_14 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__13 = 5'hd == io_write_data_idx_14 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__14 = 5'he == io_write_data_idx_14 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__15 = 5'hf == io_write_data_idx_14 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__16 = 5'h10 == io_write_data_idx_14 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__17 = 5'h11 == io_write_data_idx_14 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__18 = 5'h12 == io_write_data_idx_14 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__19 = 5'h13 == io_write_data_idx_14 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__20 = 5'h14 == io_write_data_idx_14 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__21 = 5'h15 == io_write_data_idx_14 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__22 = 5'h16 == io_write_data_idx_14 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__23 = 5'h17 == io_write_data_idx_14 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__24 = 5'h18 == io_write_data_idx_14 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__25 = 5'h19 == io_write_data_idx_14 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__26 = 5'h1a == io_write_data_idx_14 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__27 = 5'h1b == io_write_data_idx_14 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__28 = 5'h1c == io_write_data_idx_14 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__29 = 5'h1d == io_write_data_idx_14 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__30 = 5'h1e == io_write_data_idx_14 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value__31 = 5'h1f == io_write_data_idx_14 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_14_value_1_0 = io_write_data_dataout_14_value__0 | io_write_data_dataout_14_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_1 = io_write_data_dataout_14_value__2 | io_write_data_dataout_14_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_2 = io_write_data_dataout_14_value__4 | io_write_data_dataout_14_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_3 = io_write_data_dataout_14_value__6 | io_write_data_dataout_14_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_4 = io_write_data_dataout_14_value__8 | io_write_data_dataout_14_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_5 = io_write_data_dataout_14_value__10 |
- io_write_data_dataout_14_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_6 = io_write_data_dataout_14_value__12 |
- io_write_data_dataout_14_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_7 = io_write_data_dataout_14_value__14 |
- io_write_data_dataout_14_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_8 = io_write_data_dataout_14_value__16 |
- io_write_data_dataout_14_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_9 = io_write_data_dataout_14_value__18 |
- io_write_data_dataout_14_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_10 = io_write_data_dataout_14_value__20 |
- io_write_data_dataout_14_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_11 = io_write_data_dataout_14_value__22 |
- io_write_data_dataout_14_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_12 = io_write_data_dataout_14_value__24 |
- io_write_data_dataout_14_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_13 = io_write_data_dataout_14_value__26 |
- io_write_data_dataout_14_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_14 = io_write_data_dataout_14_value__28 |
- io_write_data_dataout_14_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_1_15 = io_write_data_dataout_14_value__30 |
- io_write_data_dataout_14_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_2_0 = io_write_data_dataout_14_value_1_0 |
- io_write_data_dataout_14_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_2_1 = io_write_data_dataout_14_value_1_2 |
- io_write_data_dataout_14_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_2_2 = io_write_data_dataout_14_value_1_4 |
- io_write_data_dataout_14_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_2_3 = io_write_data_dataout_14_value_1_6 |
- io_write_data_dataout_14_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_2_4 = io_write_data_dataout_14_value_1_8 |
- io_write_data_dataout_14_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_2_5 = io_write_data_dataout_14_value_1_10 |
- io_write_data_dataout_14_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_2_6 = io_write_data_dataout_14_value_1_12 |
- io_write_data_dataout_14_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_2_7 = io_write_data_dataout_14_value_1_14 |
- io_write_data_dataout_14_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_3_0 = io_write_data_dataout_14_value_2_0 |
- io_write_data_dataout_14_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_3_1 = io_write_data_dataout_14_value_2_2 |
- io_write_data_dataout_14_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_3_2 = io_write_data_dataout_14_value_2_4 |
- io_write_data_dataout_14_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_3_3 = io_write_data_dataout_14_value_2_6 |
- io_write_data_dataout_14_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_4_0 = io_write_data_dataout_14_value_3_0 |
- io_write_data_dataout_14_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_4_1 = io_write_data_dataout_14_value_3_2 |
- io_write_data_dataout_14_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_14_value_5_0 = io_write_data_dataout_14_value_4_0 |
- io_write_data_dataout_14_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_15 = 5'hf + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_15_value__0 = 5'h0 == io_write_data_idx_15 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__1 = 5'h1 == io_write_data_idx_15 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__2 = 5'h2 == io_write_data_idx_15 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__3 = 5'h3 == io_write_data_idx_15 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__4 = 5'h4 == io_write_data_idx_15 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__5 = 5'h5 == io_write_data_idx_15 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__6 = 5'h6 == io_write_data_idx_15 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__7 = 5'h7 == io_write_data_idx_15 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__8 = 5'h8 == io_write_data_idx_15 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__9 = 5'h9 == io_write_data_idx_15 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__10 = 5'ha == io_write_data_idx_15 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__11 = 5'hb == io_write_data_idx_15 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__12 = 5'hc == io_write_data_idx_15 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__13 = 5'hd == io_write_data_idx_15 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__14 = 5'he == io_write_data_idx_15 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__15 = 5'hf == io_write_data_idx_15 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__16 = 5'h10 == io_write_data_idx_15 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__17 = 5'h11 == io_write_data_idx_15 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__18 = 5'h12 == io_write_data_idx_15 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__19 = 5'h13 == io_write_data_idx_15 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__20 = 5'h14 == io_write_data_idx_15 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__21 = 5'h15 == io_write_data_idx_15 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__22 = 5'h16 == io_write_data_idx_15 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__23 = 5'h17 == io_write_data_idx_15 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__24 = 5'h18 == io_write_data_idx_15 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__25 = 5'h19 == io_write_data_idx_15 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__26 = 5'h1a == io_write_data_idx_15 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__27 = 5'h1b == io_write_data_idx_15 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__28 = 5'h1c == io_write_data_idx_15 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__29 = 5'h1d == io_write_data_idx_15 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__30 = 5'h1e == io_write_data_idx_15 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value__31 = 5'h1f == io_write_data_idx_15 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_15_value_1_0 = io_write_data_dataout_15_value__0 | io_write_data_dataout_15_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_1 = io_write_data_dataout_15_value__2 | io_write_data_dataout_15_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_2 = io_write_data_dataout_15_value__4 | io_write_data_dataout_15_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_3 = io_write_data_dataout_15_value__6 | io_write_data_dataout_15_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_4 = io_write_data_dataout_15_value__8 | io_write_data_dataout_15_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_5 = io_write_data_dataout_15_value__10 |
- io_write_data_dataout_15_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_6 = io_write_data_dataout_15_value__12 |
- io_write_data_dataout_15_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_7 = io_write_data_dataout_15_value__14 |
- io_write_data_dataout_15_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_8 = io_write_data_dataout_15_value__16 |
- io_write_data_dataout_15_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_9 = io_write_data_dataout_15_value__18 |
- io_write_data_dataout_15_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_10 = io_write_data_dataout_15_value__20 |
- io_write_data_dataout_15_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_11 = io_write_data_dataout_15_value__22 |
- io_write_data_dataout_15_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_12 = io_write_data_dataout_15_value__24 |
- io_write_data_dataout_15_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_13 = io_write_data_dataout_15_value__26 |
- io_write_data_dataout_15_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_14 = io_write_data_dataout_15_value__28 |
- io_write_data_dataout_15_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_1_15 = io_write_data_dataout_15_value__30 |
- io_write_data_dataout_15_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_2_0 = io_write_data_dataout_15_value_1_0 |
- io_write_data_dataout_15_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_2_1 = io_write_data_dataout_15_value_1_2 |
- io_write_data_dataout_15_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_2_2 = io_write_data_dataout_15_value_1_4 |
- io_write_data_dataout_15_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_2_3 = io_write_data_dataout_15_value_1_6 |
- io_write_data_dataout_15_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_2_4 = io_write_data_dataout_15_value_1_8 |
- io_write_data_dataout_15_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_2_5 = io_write_data_dataout_15_value_1_10 |
- io_write_data_dataout_15_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_2_6 = io_write_data_dataout_15_value_1_12 |
- io_write_data_dataout_15_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_2_7 = io_write_data_dataout_15_value_1_14 |
- io_write_data_dataout_15_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_3_0 = io_write_data_dataout_15_value_2_0 |
- io_write_data_dataout_15_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_3_1 = io_write_data_dataout_15_value_2_2 |
- io_write_data_dataout_15_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_3_2 = io_write_data_dataout_15_value_2_4 |
- io_write_data_dataout_15_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_3_3 = io_write_data_dataout_15_value_2_6 |
- io_write_data_dataout_15_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_4_0 = io_write_data_dataout_15_value_3_0 |
- io_write_data_dataout_15_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_4_1 = io_write_data_dataout_15_value_3_2 |
- io_write_data_dataout_15_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_15_value_5_0 = io_write_data_dataout_15_value_4_0 |
- io_write_data_dataout_15_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_16 = 5'h10 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_16_value__0 = 5'h0 == io_write_data_idx_16 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__1 = 5'h1 == io_write_data_idx_16 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__2 = 5'h2 == io_write_data_idx_16 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__3 = 5'h3 == io_write_data_idx_16 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__4 = 5'h4 == io_write_data_idx_16 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__5 = 5'h5 == io_write_data_idx_16 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__6 = 5'h6 == io_write_data_idx_16 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__7 = 5'h7 == io_write_data_idx_16 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__8 = 5'h8 == io_write_data_idx_16 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__9 = 5'h9 == io_write_data_idx_16 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__10 = 5'ha == io_write_data_idx_16 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__11 = 5'hb == io_write_data_idx_16 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__12 = 5'hc == io_write_data_idx_16 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__13 = 5'hd == io_write_data_idx_16 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__14 = 5'he == io_write_data_idx_16 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__15 = 5'hf == io_write_data_idx_16 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__16 = 5'h10 == io_write_data_idx_16 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__17 = 5'h11 == io_write_data_idx_16 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__18 = 5'h12 == io_write_data_idx_16 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__19 = 5'h13 == io_write_data_idx_16 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__20 = 5'h14 == io_write_data_idx_16 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__21 = 5'h15 == io_write_data_idx_16 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__22 = 5'h16 == io_write_data_idx_16 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__23 = 5'h17 == io_write_data_idx_16 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__24 = 5'h18 == io_write_data_idx_16 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__25 = 5'h19 == io_write_data_idx_16 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__26 = 5'h1a == io_write_data_idx_16 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__27 = 5'h1b == io_write_data_idx_16 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__28 = 5'h1c == io_write_data_idx_16 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__29 = 5'h1d == io_write_data_idx_16 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__30 = 5'h1e == io_write_data_idx_16 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value__31 = 5'h1f == io_write_data_idx_16 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_16_value_1_0 = io_write_data_dataout_16_value__0 | io_write_data_dataout_16_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_1 = io_write_data_dataout_16_value__2 | io_write_data_dataout_16_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_2 = io_write_data_dataout_16_value__4 | io_write_data_dataout_16_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_3 = io_write_data_dataout_16_value__6 | io_write_data_dataout_16_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_4 = io_write_data_dataout_16_value__8 | io_write_data_dataout_16_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_5 = io_write_data_dataout_16_value__10 |
- io_write_data_dataout_16_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_6 = io_write_data_dataout_16_value__12 |
- io_write_data_dataout_16_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_7 = io_write_data_dataout_16_value__14 |
- io_write_data_dataout_16_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_8 = io_write_data_dataout_16_value__16 |
- io_write_data_dataout_16_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_9 = io_write_data_dataout_16_value__18 |
- io_write_data_dataout_16_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_10 = io_write_data_dataout_16_value__20 |
- io_write_data_dataout_16_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_11 = io_write_data_dataout_16_value__22 |
- io_write_data_dataout_16_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_12 = io_write_data_dataout_16_value__24 |
- io_write_data_dataout_16_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_13 = io_write_data_dataout_16_value__26 |
- io_write_data_dataout_16_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_14 = io_write_data_dataout_16_value__28 |
- io_write_data_dataout_16_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_1_15 = io_write_data_dataout_16_value__30 |
- io_write_data_dataout_16_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_2_0 = io_write_data_dataout_16_value_1_0 |
- io_write_data_dataout_16_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_2_1 = io_write_data_dataout_16_value_1_2 |
- io_write_data_dataout_16_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_2_2 = io_write_data_dataout_16_value_1_4 |
- io_write_data_dataout_16_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_2_3 = io_write_data_dataout_16_value_1_6 |
- io_write_data_dataout_16_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_2_4 = io_write_data_dataout_16_value_1_8 |
- io_write_data_dataout_16_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_2_5 = io_write_data_dataout_16_value_1_10 |
- io_write_data_dataout_16_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_2_6 = io_write_data_dataout_16_value_1_12 |
- io_write_data_dataout_16_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_2_7 = io_write_data_dataout_16_value_1_14 |
- io_write_data_dataout_16_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_3_0 = io_write_data_dataout_16_value_2_0 |
- io_write_data_dataout_16_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_3_1 = io_write_data_dataout_16_value_2_2 |
- io_write_data_dataout_16_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_3_2 = io_write_data_dataout_16_value_2_4 |
- io_write_data_dataout_16_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_3_3 = io_write_data_dataout_16_value_2_6 |
- io_write_data_dataout_16_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_4_0 = io_write_data_dataout_16_value_3_0 |
- io_write_data_dataout_16_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_4_1 = io_write_data_dataout_16_value_3_2 |
- io_write_data_dataout_16_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_16_value_5_0 = io_write_data_dataout_16_value_4_0 |
- io_write_data_dataout_16_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_17 = 5'h11 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_17_value__0 = 5'h0 == io_write_data_idx_17 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__1 = 5'h1 == io_write_data_idx_17 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__2 = 5'h2 == io_write_data_idx_17 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__3 = 5'h3 == io_write_data_idx_17 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__4 = 5'h4 == io_write_data_idx_17 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__5 = 5'h5 == io_write_data_idx_17 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__6 = 5'h6 == io_write_data_idx_17 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__7 = 5'h7 == io_write_data_idx_17 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__8 = 5'h8 == io_write_data_idx_17 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__9 = 5'h9 == io_write_data_idx_17 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__10 = 5'ha == io_write_data_idx_17 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__11 = 5'hb == io_write_data_idx_17 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__12 = 5'hc == io_write_data_idx_17 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__13 = 5'hd == io_write_data_idx_17 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__14 = 5'he == io_write_data_idx_17 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__15 = 5'hf == io_write_data_idx_17 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__16 = 5'h10 == io_write_data_idx_17 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__17 = 5'h11 == io_write_data_idx_17 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__18 = 5'h12 == io_write_data_idx_17 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__19 = 5'h13 == io_write_data_idx_17 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__20 = 5'h14 == io_write_data_idx_17 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__21 = 5'h15 == io_write_data_idx_17 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__22 = 5'h16 == io_write_data_idx_17 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__23 = 5'h17 == io_write_data_idx_17 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__24 = 5'h18 == io_write_data_idx_17 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__25 = 5'h19 == io_write_data_idx_17 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__26 = 5'h1a == io_write_data_idx_17 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__27 = 5'h1b == io_write_data_idx_17 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__28 = 5'h1c == io_write_data_idx_17 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__29 = 5'h1d == io_write_data_idx_17 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__30 = 5'h1e == io_write_data_idx_17 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value__31 = 5'h1f == io_write_data_idx_17 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_17_value_1_0 = io_write_data_dataout_17_value__0 | io_write_data_dataout_17_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_1 = io_write_data_dataout_17_value__2 | io_write_data_dataout_17_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_2 = io_write_data_dataout_17_value__4 | io_write_data_dataout_17_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_3 = io_write_data_dataout_17_value__6 | io_write_data_dataout_17_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_4 = io_write_data_dataout_17_value__8 | io_write_data_dataout_17_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_5 = io_write_data_dataout_17_value__10 |
- io_write_data_dataout_17_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_6 = io_write_data_dataout_17_value__12 |
- io_write_data_dataout_17_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_7 = io_write_data_dataout_17_value__14 |
- io_write_data_dataout_17_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_8 = io_write_data_dataout_17_value__16 |
- io_write_data_dataout_17_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_9 = io_write_data_dataout_17_value__18 |
- io_write_data_dataout_17_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_10 = io_write_data_dataout_17_value__20 |
- io_write_data_dataout_17_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_11 = io_write_data_dataout_17_value__22 |
- io_write_data_dataout_17_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_12 = io_write_data_dataout_17_value__24 |
- io_write_data_dataout_17_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_13 = io_write_data_dataout_17_value__26 |
- io_write_data_dataout_17_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_14 = io_write_data_dataout_17_value__28 |
- io_write_data_dataout_17_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_1_15 = io_write_data_dataout_17_value__30 |
- io_write_data_dataout_17_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_2_0 = io_write_data_dataout_17_value_1_0 |
- io_write_data_dataout_17_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_2_1 = io_write_data_dataout_17_value_1_2 |
- io_write_data_dataout_17_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_2_2 = io_write_data_dataout_17_value_1_4 |
- io_write_data_dataout_17_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_2_3 = io_write_data_dataout_17_value_1_6 |
- io_write_data_dataout_17_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_2_4 = io_write_data_dataout_17_value_1_8 |
- io_write_data_dataout_17_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_2_5 = io_write_data_dataout_17_value_1_10 |
- io_write_data_dataout_17_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_2_6 = io_write_data_dataout_17_value_1_12 |
- io_write_data_dataout_17_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_2_7 = io_write_data_dataout_17_value_1_14 |
- io_write_data_dataout_17_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_3_0 = io_write_data_dataout_17_value_2_0 |
- io_write_data_dataout_17_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_3_1 = io_write_data_dataout_17_value_2_2 |
- io_write_data_dataout_17_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_3_2 = io_write_data_dataout_17_value_2_4 |
- io_write_data_dataout_17_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_3_3 = io_write_data_dataout_17_value_2_6 |
- io_write_data_dataout_17_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_4_0 = io_write_data_dataout_17_value_3_0 |
- io_write_data_dataout_17_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_4_1 = io_write_data_dataout_17_value_3_2 |
- io_write_data_dataout_17_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_17_value_5_0 = io_write_data_dataout_17_value_4_0 |
- io_write_data_dataout_17_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_18 = 5'h12 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_18_value__0 = 5'h0 == io_write_data_idx_18 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__1 = 5'h1 == io_write_data_idx_18 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__2 = 5'h2 == io_write_data_idx_18 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__3 = 5'h3 == io_write_data_idx_18 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__4 = 5'h4 == io_write_data_idx_18 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__5 = 5'h5 == io_write_data_idx_18 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__6 = 5'h6 == io_write_data_idx_18 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__7 = 5'h7 == io_write_data_idx_18 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__8 = 5'h8 == io_write_data_idx_18 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__9 = 5'h9 == io_write_data_idx_18 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__10 = 5'ha == io_write_data_idx_18 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__11 = 5'hb == io_write_data_idx_18 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__12 = 5'hc == io_write_data_idx_18 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__13 = 5'hd == io_write_data_idx_18 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__14 = 5'he == io_write_data_idx_18 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__15 = 5'hf == io_write_data_idx_18 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__16 = 5'h10 == io_write_data_idx_18 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__17 = 5'h11 == io_write_data_idx_18 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__18 = 5'h12 == io_write_data_idx_18 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__19 = 5'h13 == io_write_data_idx_18 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__20 = 5'h14 == io_write_data_idx_18 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__21 = 5'h15 == io_write_data_idx_18 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__22 = 5'h16 == io_write_data_idx_18 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__23 = 5'h17 == io_write_data_idx_18 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__24 = 5'h18 == io_write_data_idx_18 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__25 = 5'h19 == io_write_data_idx_18 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__26 = 5'h1a == io_write_data_idx_18 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__27 = 5'h1b == io_write_data_idx_18 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__28 = 5'h1c == io_write_data_idx_18 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__29 = 5'h1d == io_write_data_idx_18 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__30 = 5'h1e == io_write_data_idx_18 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value__31 = 5'h1f == io_write_data_idx_18 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_18_value_1_0 = io_write_data_dataout_18_value__0 | io_write_data_dataout_18_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_1 = io_write_data_dataout_18_value__2 | io_write_data_dataout_18_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_2 = io_write_data_dataout_18_value__4 | io_write_data_dataout_18_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_3 = io_write_data_dataout_18_value__6 | io_write_data_dataout_18_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_4 = io_write_data_dataout_18_value__8 | io_write_data_dataout_18_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_5 = io_write_data_dataout_18_value__10 |
- io_write_data_dataout_18_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_6 = io_write_data_dataout_18_value__12 |
- io_write_data_dataout_18_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_7 = io_write_data_dataout_18_value__14 |
- io_write_data_dataout_18_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_8 = io_write_data_dataout_18_value__16 |
- io_write_data_dataout_18_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_9 = io_write_data_dataout_18_value__18 |
- io_write_data_dataout_18_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_10 = io_write_data_dataout_18_value__20 |
- io_write_data_dataout_18_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_11 = io_write_data_dataout_18_value__22 |
- io_write_data_dataout_18_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_12 = io_write_data_dataout_18_value__24 |
- io_write_data_dataout_18_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_13 = io_write_data_dataout_18_value__26 |
- io_write_data_dataout_18_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_14 = io_write_data_dataout_18_value__28 |
- io_write_data_dataout_18_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_1_15 = io_write_data_dataout_18_value__30 |
- io_write_data_dataout_18_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_2_0 = io_write_data_dataout_18_value_1_0 |
- io_write_data_dataout_18_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_2_1 = io_write_data_dataout_18_value_1_2 |
- io_write_data_dataout_18_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_2_2 = io_write_data_dataout_18_value_1_4 |
- io_write_data_dataout_18_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_2_3 = io_write_data_dataout_18_value_1_6 |
- io_write_data_dataout_18_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_2_4 = io_write_data_dataout_18_value_1_8 |
- io_write_data_dataout_18_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_2_5 = io_write_data_dataout_18_value_1_10 |
- io_write_data_dataout_18_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_2_6 = io_write_data_dataout_18_value_1_12 |
- io_write_data_dataout_18_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_2_7 = io_write_data_dataout_18_value_1_14 |
- io_write_data_dataout_18_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_3_0 = io_write_data_dataout_18_value_2_0 |
- io_write_data_dataout_18_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_3_1 = io_write_data_dataout_18_value_2_2 |
- io_write_data_dataout_18_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_3_2 = io_write_data_dataout_18_value_2_4 |
- io_write_data_dataout_18_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_3_3 = io_write_data_dataout_18_value_2_6 |
- io_write_data_dataout_18_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_4_0 = io_write_data_dataout_18_value_3_0 |
- io_write_data_dataout_18_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_4_1 = io_write_data_dataout_18_value_3_2 |
- io_write_data_dataout_18_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_18_value_5_0 = io_write_data_dataout_18_value_4_0 |
- io_write_data_dataout_18_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_19 = 5'h13 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_19_value__0 = 5'h0 == io_write_data_idx_19 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__1 = 5'h1 == io_write_data_idx_19 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__2 = 5'h2 == io_write_data_idx_19 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__3 = 5'h3 == io_write_data_idx_19 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__4 = 5'h4 == io_write_data_idx_19 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__5 = 5'h5 == io_write_data_idx_19 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__6 = 5'h6 == io_write_data_idx_19 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__7 = 5'h7 == io_write_data_idx_19 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__8 = 5'h8 == io_write_data_idx_19 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__9 = 5'h9 == io_write_data_idx_19 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__10 = 5'ha == io_write_data_idx_19 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__11 = 5'hb == io_write_data_idx_19 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__12 = 5'hc == io_write_data_idx_19 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__13 = 5'hd == io_write_data_idx_19 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__14 = 5'he == io_write_data_idx_19 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__15 = 5'hf == io_write_data_idx_19 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__16 = 5'h10 == io_write_data_idx_19 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__17 = 5'h11 == io_write_data_idx_19 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__18 = 5'h12 == io_write_data_idx_19 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__19 = 5'h13 == io_write_data_idx_19 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__20 = 5'h14 == io_write_data_idx_19 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__21 = 5'h15 == io_write_data_idx_19 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__22 = 5'h16 == io_write_data_idx_19 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__23 = 5'h17 == io_write_data_idx_19 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__24 = 5'h18 == io_write_data_idx_19 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__25 = 5'h19 == io_write_data_idx_19 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__26 = 5'h1a == io_write_data_idx_19 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__27 = 5'h1b == io_write_data_idx_19 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__28 = 5'h1c == io_write_data_idx_19 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__29 = 5'h1d == io_write_data_idx_19 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__30 = 5'h1e == io_write_data_idx_19 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value__31 = 5'h1f == io_write_data_idx_19 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_19_value_1_0 = io_write_data_dataout_19_value__0 | io_write_data_dataout_19_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_1 = io_write_data_dataout_19_value__2 | io_write_data_dataout_19_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_2 = io_write_data_dataout_19_value__4 | io_write_data_dataout_19_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_3 = io_write_data_dataout_19_value__6 | io_write_data_dataout_19_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_4 = io_write_data_dataout_19_value__8 | io_write_data_dataout_19_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_5 = io_write_data_dataout_19_value__10 |
- io_write_data_dataout_19_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_6 = io_write_data_dataout_19_value__12 |
- io_write_data_dataout_19_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_7 = io_write_data_dataout_19_value__14 |
- io_write_data_dataout_19_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_8 = io_write_data_dataout_19_value__16 |
- io_write_data_dataout_19_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_9 = io_write_data_dataout_19_value__18 |
- io_write_data_dataout_19_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_10 = io_write_data_dataout_19_value__20 |
- io_write_data_dataout_19_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_11 = io_write_data_dataout_19_value__22 |
- io_write_data_dataout_19_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_12 = io_write_data_dataout_19_value__24 |
- io_write_data_dataout_19_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_13 = io_write_data_dataout_19_value__26 |
- io_write_data_dataout_19_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_14 = io_write_data_dataout_19_value__28 |
- io_write_data_dataout_19_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_1_15 = io_write_data_dataout_19_value__30 |
- io_write_data_dataout_19_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_2_0 = io_write_data_dataout_19_value_1_0 |
- io_write_data_dataout_19_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_2_1 = io_write_data_dataout_19_value_1_2 |
- io_write_data_dataout_19_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_2_2 = io_write_data_dataout_19_value_1_4 |
- io_write_data_dataout_19_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_2_3 = io_write_data_dataout_19_value_1_6 |
- io_write_data_dataout_19_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_2_4 = io_write_data_dataout_19_value_1_8 |
- io_write_data_dataout_19_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_2_5 = io_write_data_dataout_19_value_1_10 |
- io_write_data_dataout_19_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_2_6 = io_write_data_dataout_19_value_1_12 |
- io_write_data_dataout_19_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_2_7 = io_write_data_dataout_19_value_1_14 |
- io_write_data_dataout_19_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_3_0 = io_write_data_dataout_19_value_2_0 |
- io_write_data_dataout_19_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_3_1 = io_write_data_dataout_19_value_2_2 |
- io_write_data_dataout_19_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_3_2 = io_write_data_dataout_19_value_2_4 |
- io_write_data_dataout_19_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_3_3 = io_write_data_dataout_19_value_2_6 |
- io_write_data_dataout_19_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_4_0 = io_write_data_dataout_19_value_3_0 |
- io_write_data_dataout_19_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_4_1 = io_write_data_dataout_19_value_3_2 |
- io_write_data_dataout_19_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_19_value_5_0 = io_write_data_dataout_19_value_4_0 |
- io_write_data_dataout_19_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_20 = 5'h14 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_20_value__0 = 5'h0 == io_write_data_idx_20 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__1 = 5'h1 == io_write_data_idx_20 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__2 = 5'h2 == io_write_data_idx_20 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__3 = 5'h3 == io_write_data_idx_20 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__4 = 5'h4 == io_write_data_idx_20 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__5 = 5'h5 == io_write_data_idx_20 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__6 = 5'h6 == io_write_data_idx_20 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__7 = 5'h7 == io_write_data_idx_20 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__8 = 5'h8 == io_write_data_idx_20 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__9 = 5'h9 == io_write_data_idx_20 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__10 = 5'ha == io_write_data_idx_20 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__11 = 5'hb == io_write_data_idx_20 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__12 = 5'hc == io_write_data_idx_20 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__13 = 5'hd == io_write_data_idx_20 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__14 = 5'he == io_write_data_idx_20 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__15 = 5'hf == io_write_data_idx_20 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__16 = 5'h10 == io_write_data_idx_20 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__17 = 5'h11 == io_write_data_idx_20 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__18 = 5'h12 == io_write_data_idx_20 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__19 = 5'h13 == io_write_data_idx_20 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__20 = 5'h14 == io_write_data_idx_20 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__21 = 5'h15 == io_write_data_idx_20 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__22 = 5'h16 == io_write_data_idx_20 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__23 = 5'h17 == io_write_data_idx_20 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__24 = 5'h18 == io_write_data_idx_20 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__25 = 5'h19 == io_write_data_idx_20 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__26 = 5'h1a == io_write_data_idx_20 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__27 = 5'h1b == io_write_data_idx_20 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__28 = 5'h1c == io_write_data_idx_20 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__29 = 5'h1d == io_write_data_idx_20 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__30 = 5'h1e == io_write_data_idx_20 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value__31 = 5'h1f == io_write_data_idx_20 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_20_value_1_0 = io_write_data_dataout_20_value__0 | io_write_data_dataout_20_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_1 = io_write_data_dataout_20_value__2 | io_write_data_dataout_20_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_2 = io_write_data_dataout_20_value__4 | io_write_data_dataout_20_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_3 = io_write_data_dataout_20_value__6 | io_write_data_dataout_20_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_4 = io_write_data_dataout_20_value__8 | io_write_data_dataout_20_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_5 = io_write_data_dataout_20_value__10 |
- io_write_data_dataout_20_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_6 = io_write_data_dataout_20_value__12 |
- io_write_data_dataout_20_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_7 = io_write_data_dataout_20_value__14 |
- io_write_data_dataout_20_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_8 = io_write_data_dataout_20_value__16 |
- io_write_data_dataout_20_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_9 = io_write_data_dataout_20_value__18 |
- io_write_data_dataout_20_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_10 = io_write_data_dataout_20_value__20 |
- io_write_data_dataout_20_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_11 = io_write_data_dataout_20_value__22 |
- io_write_data_dataout_20_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_12 = io_write_data_dataout_20_value__24 |
- io_write_data_dataout_20_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_13 = io_write_data_dataout_20_value__26 |
- io_write_data_dataout_20_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_14 = io_write_data_dataout_20_value__28 |
- io_write_data_dataout_20_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_1_15 = io_write_data_dataout_20_value__30 |
- io_write_data_dataout_20_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_2_0 = io_write_data_dataout_20_value_1_0 |
- io_write_data_dataout_20_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_2_1 = io_write_data_dataout_20_value_1_2 |
- io_write_data_dataout_20_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_2_2 = io_write_data_dataout_20_value_1_4 |
- io_write_data_dataout_20_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_2_3 = io_write_data_dataout_20_value_1_6 |
- io_write_data_dataout_20_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_2_4 = io_write_data_dataout_20_value_1_8 |
- io_write_data_dataout_20_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_2_5 = io_write_data_dataout_20_value_1_10 |
- io_write_data_dataout_20_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_2_6 = io_write_data_dataout_20_value_1_12 |
- io_write_data_dataout_20_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_2_7 = io_write_data_dataout_20_value_1_14 |
- io_write_data_dataout_20_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_3_0 = io_write_data_dataout_20_value_2_0 |
- io_write_data_dataout_20_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_3_1 = io_write_data_dataout_20_value_2_2 |
- io_write_data_dataout_20_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_3_2 = io_write_data_dataout_20_value_2_4 |
- io_write_data_dataout_20_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_3_3 = io_write_data_dataout_20_value_2_6 |
- io_write_data_dataout_20_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_4_0 = io_write_data_dataout_20_value_3_0 |
- io_write_data_dataout_20_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_4_1 = io_write_data_dataout_20_value_3_2 |
- io_write_data_dataout_20_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_20_value_5_0 = io_write_data_dataout_20_value_4_0 |
- io_write_data_dataout_20_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_21 = 5'h15 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_21_value__0 = 5'h0 == io_write_data_idx_21 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__1 = 5'h1 == io_write_data_idx_21 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__2 = 5'h2 == io_write_data_idx_21 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__3 = 5'h3 == io_write_data_idx_21 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__4 = 5'h4 == io_write_data_idx_21 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__5 = 5'h5 == io_write_data_idx_21 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__6 = 5'h6 == io_write_data_idx_21 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__7 = 5'h7 == io_write_data_idx_21 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__8 = 5'h8 == io_write_data_idx_21 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__9 = 5'h9 == io_write_data_idx_21 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__10 = 5'ha == io_write_data_idx_21 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__11 = 5'hb == io_write_data_idx_21 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__12 = 5'hc == io_write_data_idx_21 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__13 = 5'hd == io_write_data_idx_21 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__14 = 5'he == io_write_data_idx_21 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__15 = 5'hf == io_write_data_idx_21 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__16 = 5'h10 == io_write_data_idx_21 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__17 = 5'h11 == io_write_data_idx_21 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__18 = 5'h12 == io_write_data_idx_21 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__19 = 5'h13 == io_write_data_idx_21 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__20 = 5'h14 == io_write_data_idx_21 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__21 = 5'h15 == io_write_data_idx_21 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__22 = 5'h16 == io_write_data_idx_21 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__23 = 5'h17 == io_write_data_idx_21 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__24 = 5'h18 == io_write_data_idx_21 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__25 = 5'h19 == io_write_data_idx_21 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__26 = 5'h1a == io_write_data_idx_21 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__27 = 5'h1b == io_write_data_idx_21 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__28 = 5'h1c == io_write_data_idx_21 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__29 = 5'h1d == io_write_data_idx_21 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__30 = 5'h1e == io_write_data_idx_21 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value__31 = 5'h1f == io_write_data_idx_21 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_21_value_1_0 = io_write_data_dataout_21_value__0 | io_write_data_dataout_21_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_1 = io_write_data_dataout_21_value__2 | io_write_data_dataout_21_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_2 = io_write_data_dataout_21_value__4 | io_write_data_dataout_21_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_3 = io_write_data_dataout_21_value__6 | io_write_data_dataout_21_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_4 = io_write_data_dataout_21_value__8 | io_write_data_dataout_21_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_5 = io_write_data_dataout_21_value__10 |
- io_write_data_dataout_21_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_6 = io_write_data_dataout_21_value__12 |
- io_write_data_dataout_21_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_7 = io_write_data_dataout_21_value__14 |
- io_write_data_dataout_21_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_8 = io_write_data_dataout_21_value__16 |
- io_write_data_dataout_21_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_9 = io_write_data_dataout_21_value__18 |
- io_write_data_dataout_21_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_10 = io_write_data_dataout_21_value__20 |
- io_write_data_dataout_21_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_11 = io_write_data_dataout_21_value__22 |
- io_write_data_dataout_21_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_12 = io_write_data_dataout_21_value__24 |
- io_write_data_dataout_21_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_13 = io_write_data_dataout_21_value__26 |
- io_write_data_dataout_21_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_14 = io_write_data_dataout_21_value__28 |
- io_write_data_dataout_21_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_1_15 = io_write_data_dataout_21_value__30 |
- io_write_data_dataout_21_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_2_0 = io_write_data_dataout_21_value_1_0 |
- io_write_data_dataout_21_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_2_1 = io_write_data_dataout_21_value_1_2 |
- io_write_data_dataout_21_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_2_2 = io_write_data_dataout_21_value_1_4 |
- io_write_data_dataout_21_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_2_3 = io_write_data_dataout_21_value_1_6 |
- io_write_data_dataout_21_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_2_4 = io_write_data_dataout_21_value_1_8 |
- io_write_data_dataout_21_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_2_5 = io_write_data_dataout_21_value_1_10 |
- io_write_data_dataout_21_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_2_6 = io_write_data_dataout_21_value_1_12 |
- io_write_data_dataout_21_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_2_7 = io_write_data_dataout_21_value_1_14 |
- io_write_data_dataout_21_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_3_0 = io_write_data_dataout_21_value_2_0 |
- io_write_data_dataout_21_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_3_1 = io_write_data_dataout_21_value_2_2 |
- io_write_data_dataout_21_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_3_2 = io_write_data_dataout_21_value_2_4 |
- io_write_data_dataout_21_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_3_3 = io_write_data_dataout_21_value_2_6 |
- io_write_data_dataout_21_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_4_0 = io_write_data_dataout_21_value_3_0 |
- io_write_data_dataout_21_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_4_1 = io_write_data_dataout_21_value_3_2 |
- io_write_data_dataout_21_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_21_value_5_0 = io_write_data_dataout_21_value_4_0 |
- io_write_data_dataout_21_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_22 = 5'h16 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_22_value__0 = 5'h0 == io_write_data_idx_22 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__1 = 5'h1 == io_write_data_idx_22 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__2 = 5'h2 == io_write_data_idx_22 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__3 = 5'h3 == io_write_data_idx_22 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__4 = 5'h4 == io_write_data_idx_22 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__5 = 5'h5 == io_write_data_idx_22 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__6 = 5'h6 == io_write_data_idx_22 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__7 = 5'h7 == io_write_data_idx_22 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__8 = 5'h8 == io_write_data_idx_22 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__9 = 5'h9 == io_write_data_idx_22 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__10 = 5'ha == io_write_data_idx_22 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__11 = 5'hb == io_write_data_idx_22 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__12 = 5'hc == io_write_data_idx_22 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__13 = 5'hd == io_write_data_idx_22 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__14 = 5'he == io_write_data_idx_22 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__15 = 5'hf == io_write_data_idx_22 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__16 = 5'h10 == io_write_data_idx_22 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__17 = 5'h11 == io_write_data_idx_22 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__18 = 5'h12 == io_write_data_idx_22 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__19 = 5'h13 == io_write_data_idx_22 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__20 = 5'h14 == io_write_data_idx_22 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__21 = 5'h15 == io_write_data_idx_22 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__22 = 5'h16 == io_write_data_idx_22 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__23 = 5'h17 == io_write_data_idx_22 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__24 = 5'h18 == io_write_data_idx_22 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__25 = 5'h19 == io_write_data_idx_22 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__26 = 5'h1a == io_write_data_idx_22 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__27 = 5'h1b == io_write_data_idx_22 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__28 = 5'h1c == io_write_data_idx_22 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__29 = 5'h1d == io_write_data_idx_22 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__30 = 5'h1e == io_write_data_idx_22 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value__31 = 5'h1f == io_write_data_idx_22 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_22_value_1_0 = io_write_data_dataout_22_value__0 | io_write_data_dataout_22_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_1 = io_write_data_dataout_22_value__2 | io_write_data_dataout_22_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_2 = io_write_data_dataout_22_value__4 | io_write_data_dataout_22_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_3 = io_write_data_dataout_22_value__6 | io_write_data_dataout_22_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_4 = io_write_data_dataout_22_value__8 | io_write_data_dataout_22_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_5 = io_write_data_dataout_22_value__10 |
- io_write_data_dataout_22_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_6 = io_write_data_dataout_22_value__12 |
- io_write_data_dataout_22_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_7 = io_write_data_dataout_22_value__14 |
- io_write_data_dataout_22_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_8 = io_write_data_dataout_22_value__16 |
- io_write_data_dataout_22_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_9 = io_write_data_dataout_22_value__18 |
- io_write_data_dataout_22_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_10 = io_write_data_dataout_22_value__20 |
- io_write_data_dataout_22_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_11 = io_write_data_dataout_22_value__22 |
- io_write_data_dataout_22_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_12 = io_write_data_dataout_22_value__24 |
- io_write_data_dataout_22_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_13 = io_write_data_dataout_22_value__26 |
- io_write_data_dataout_22_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_14 = io_write_data_dataout_22_value__28 |
- io_write_data_dataout_22_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_1_15 = io_write_data_dataout_22_value__30 |
- io_write_data_dataout_22_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_2_0 = io_write_data_dataout_22_value_1_0 |
- io_write_data_dataout_22_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_2_1 = io_write_data_dataout_22_value_1_2 |
- io_write_data_dataout_22_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_2_2 = io_write_data_dataout_22_value_1_4 |
- io_write_data_dataout_22_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_2_3 = io_write_data_dataout_22_value_1_6 |
- io_write_data_dataout_22_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_2_4 = io_write_data_dataout_22_value_1_8 |
- io_write_data_dataout_22_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_2_5 = io_write_data_dataout_22_value_1_10 |
- io_write_data_dataout_22_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_2_6 = io_write_data_dataout_22_value_1_12 |
- io_write_data_dataout_22_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_2_7 = io_write_data_dataout_22_value_1_14 |
- io_write_data_dataout_22_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_3_0 = io_write_data_dataout_22_value_2_0 |
- io_write_data_dataout_22_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_3_1 = io_write_data_dataout_22_value_2_2 |
- io_write_data_dataout_22_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_3_2 = io_write_data_dataout_22_value_2_4 |
- io_write_data_dataout_22_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_3_3 = io_write_data_dataout_22_value_2_6 |
- io_write_data_dataout_22_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_4_0 = io_write_data_dataout_22_value_3_0 |
- io_write_data_dataout_22_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_4_1 = io_write_data_dataout_22_value_3_2 |
- io_write_data_dataout_22_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_22_value_5_0 = io_write_data_dataout_22_value_4_0 |
- io_write_data_dataout_22_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_23 = 5'h17 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_23_value__0 = 5'h0 == io_write_data_idx_23 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__1 = 5'h1 == io_write_data_idx_23 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__2 = 5'h2 == io_write_data_idx_23 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__3 = 5'h3 == io_write_data_idx_23 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__4 = 5'h4 == io_write_data_idx_23 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__5 = 5'h5 == io_write_data_idx_23 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__6 = 5'h6 == io_write_data_idx_23 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__7 = 5'h7 == io_write_data_idx_23 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__8 = 5'h8 == io_write_data_idx_23 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__9 = 5'h9 == io_write_data_idx_23 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__10 = 5'ha == io_write_data_idx_23 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__11 = 5'hb == io_write_data_idx_23 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__12 = 5'hc == io_write_data_idx_23 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__13 = 5'hd == io_write_data_idx_23 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__14 = 5'he == io_write_data_idx_23 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__15 = 5'hf == io_write_data_idx_23 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__16 = 5'h10 == io_write_data_idx_23 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__17 = 5'h11 == io_write_data_idx_23 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__18 = 5'h12 == io_write_data_idx_23 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__19 = 5'h13 == io_write_data_idx_23 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__20 = 5'h14 == io_write_data_idx_23 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__21 = 5'h15 == io_write_data_idx_23 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__22 = 5'h16 == io_write_data_idx_23 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__23 = 5'h17 == io_write_data_idx_23 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__24 = 5'h18 == io_write_data_idx_23 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__25 = 5'h19 == io_write_data_idx_23 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__26 = 5'h1a == io_write_data_idx_23 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__27 = 5'h1b == io_write_data_idx_23 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__28 = 5'h1c == io_write_data_idx_23 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__29 = 5'h1d == io_write_data_idx_23 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__30 = 5'h1e == io_write_data_idx_23 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value__31 = 5'h1f == io_write_data_idx_23 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_23_value_1_0 = io_write_data_dataout_23_value__0 | io_write_data_dataout_23_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_1 = io_write_data_dataout_23_value__2 | io_write_data_dataout_23_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_2 = io_write_data_dataout_23_value__4 | io_write_data_dataout_23_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_3 = io_write_data_dataout_23_value__6 | io_write_data_dataout_23_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_4 = io_write_data_dataout_23_value__8 | io_write_data_dataout_23_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_5 = io_write_data_dataout_23_value__10 |
- io_write_data_dataout_23_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_6 = io_write_data_dataout_23_value__12 |
- io_write_data_dataout_23_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_7 = io_write_data_dataout_23_value__14 |
- io_write_data_dataout_23_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_8 = io_write_data_dataout_23_value__16 |
- io_write_data_dataout_23_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_9 = io_write_data_dataout_23_value__18 |
- io_write_data_dataout_23_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_10 = io_write_data_dataout_23_value__20 |
- io_write_data_dataout_23_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_11 = io_write_data_dataout_23_value__22 |
- io_write_data_dataout_23_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_12 = io_write_data_dataout_23_value__24 |
- io_write_data_dataout_23_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_13 = io_write_data_dataout_23_value__26 |
- io_write_data_dataout_23_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_14 = io_write_data_dataout_23_value__28 |
- io_write_data_dataout_23_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_1_15 = io_write_data_dataout_23_value__30 |
- io_write_data_dataout_23_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_2_0 = io_write_data_dataout_23_value_1_0 |
- io_write_data_dataout_23_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_2_1 = io_write_data_dataout_23_value_1_2 |
- io_write_data_dataout_23_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_2_2 = io_write_data_dataout_23_value_1_4 |
- io_write_data_dataout_23_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_2_3 = io_write_data_dataout_23_value_1_6 |
- io_write_data_dataout_23_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_2_4 = io_write_data_dataout_23_value_1_8 |
- io_write_data_dataout_23_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_2_5 = io_write_data_dataout_23_value_1_10 |
- io_write_data_dataout_23_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_2_6 = io_write_data_dataout_23_value_1_12 |
- io_write_data_dataout_23_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_2_7 = io_write_data_dataout_23_value_1_14 |
- io_write_data_dataout_23_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_3_0 = io_write_data_dataout_23_value_2_0 |
- io_write_data_dataout_23_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_3_1 = io_write_data_dataout_23_value_2_2 |
- io_write_data_dataout_23_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_3_2 = io_write_data_dataout_23_value_2_4 |
- io_write_data_dataout_23_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_3_3 = io_write_data_dataout_23_value_2_6 |
- io_write_data_dataout_23_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_4_0 = io_write_data_dataout_23_value_3_0 |
- io_write_data_dataout_23_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_4_1 = io_write_data_dataout_23_value_3_2 |
- io_write_data_dataout_23_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_23_value_5_0 = io_write_data_dataout_23_value_4_0 |
- io_write_data_dataout_23_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_24 = 5'h18 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_24_value__0 = 5'h0 == io_write_data_idx_24 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__1 = 5'h1 == io_write_data_idx_24 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__2 = 5'h2 == io_write_data_idx_24 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__3 = 5'h3 == io_write_data_idx_24 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__4 = 5'h4 == io_write_data_idx_24 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__5 = 5'h5 == io_write_data_idx_24 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__6 = 5'h6 == io_write_data_idx_24 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__7 = 5'h7 == io_write_data_idx_24 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__8 = 5'h8 == io_write_data_idx_24 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__9 = 5'h9 == io_write_data_idx_24 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__10 = 5'ha == io_write_data_idx_24 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__11 = 5'hb == io_write_data_idx_24 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__12 = 5'hc == io_write_data_idx_24 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__13 = 5'hd == io_write_data_idx_24 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__14 = 5'he == io_write_data_idx_24 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__15 = 5'hf == io_write_data_idx_24 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__16 = 5'h10 == io_write_data_idx_24 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__17 = 5'h11 == io_write_data_idx_24 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__18 = 5'h12 == io_write_data_idx_24 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__19 = 5'h13 == io_write_data_idx_24 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__20 = 5'h14 == io_write_data_idx_24 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__21 = 5'h15 == io_write_data_idx_24 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__22 = 5'h16 == io_write_data_idx_24 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__23 = 5'h17 == io_write_data_idx_24 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__24 = 5'h18 == io_write_data_idx_24 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__25 = 5'h19 == io_write_data_idx_24 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__26 = 5'h1a == io_write_data_idx_24 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__27 = 5'h1b == io_write_data_idx_24 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__28 = 5'h1c == io_write_data_idx_24 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__29 = 5'h1d == io_write_data_idx_24 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__30 = 5'h1e == io_write_data_idx_24 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value__31 = 5'h1f == io_write_data_idx_24 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_24_value_1_0 = io_write_data_dataout_24_value__0 | io_write_data_dataout_24_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_1 = io_write_data_dataout_24_value__2 | io_write_data_dataout_24_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_2 = io_write_data_dataout_24_value__4 | io_write_data_dataout_24_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_3 = io_write_data_dataout_24_value__6 | io_write_data_dataout_24_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_4 = io_write_data_dataout_24_value__8 | io_write_data_dataout_24_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_5 = io_write_data_dataout_24_value__10 |
- io_write_data_dataout_24_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_6 = io_write_data_dataout_24_value__12 |
- io_write_data_dataout_24_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_7 = io_write_data_dataout_24_value__14 |
- io_write_data_dataout_24_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_8 = io_write_data_dataout_24_value__16 |
- io_write_data_dataout_24_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_9 = io_write_data_dataout_24_value__18 |
- io_write_data_dataout_24_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_10 = io_write_data_dataout_24_value__20 |
- io_write_data_dataout_24_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_11 = io_write_data_dataout_24_value__22 |
- io_write_data_dataout_24_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_12 = io_write_data_dataout_24_value__24 |
- io_write_data_dataout_24_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_13 = io_write_data_dataout_24_value__26 |
- io_write_data_dataout_24_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_14 = io_write_data_dataout_24_value__28 |
- io_write_data_dataout_24_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_1_15 = io_write_data_dataout_24_value__30 |
- io_write_data_dataout_24_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_2_0 = io_write_data_dataout_24_value_1_0 |
- io_write_data_dataout_24_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_2_1 = io_write_data_dataout_24_value_1_2 |
- io_write_data_dataout_24_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_2_2 = io_write_data_dataout_24_value_1_4 |
- io_write_data_dataout_24_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_2_3 = io_write_data_dataout_24_value_1_6 |
- io_write_data_dataout_24_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_2_4 = io_write_data_dataout_24_value_1_8 |
- io_write_data_dataout_24_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_2_5 = io_write_data_dataout_24_value_1_10 |
- io_write_data_dataout_24_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_2_6 = io_write_data_dataout_24_value_1_12 |
- io_write_data_dataout_24_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_2_7 = io_write_data_dataout_24_value_1_14 |
- io_write_data_dataout_24_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_3_0 = io_write_data_dataout_24_value_2_0 |
- io_write_data_dataout_24_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_3_1 = io_write_data_dataout_24_value_2_2 |
- io_write_data_dataout_24_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_3_2 = io_write_data_dataout_24_value_2_4 |
- io_write_data_dataout_24_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_3_3 = io_write_data_dataout_24_value_2_6 |
- io_write_data_dataout_24_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_4_0 = io_write_data_dataout_24_value_3_0 |
- io_write_data_dataout_24_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_4_1 = io_write_data_dataout_24_value_3_2 |
- io_write_data_dataout_24_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_24_value_5_0 = io_write_data_dataout_24_value_4_0 |
- io_write_data_dataout_24_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_25 = 5'h19 + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_25_value__0 = 5'h0 == io_write_data_idx_25 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__1 = 5'h1 == io_write_data_idx_25 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__2 = 5'h2 == io_write_data_idx_25 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__3 = 5'h3 == io_write_data_idx_25 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__4 = 5'h4 == io_write_data_idx_25 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__5 = 5'h5 == io_write_data_idx_25 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__6 = 5'h6 == io_write_data_idx_25 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__7 = 5'h7 == io_write_data_idx_25 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__8 = 5'h8 == io_write_data_idx_25 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__9 = 5'h9 == io_write_data_idx_25 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__10 = 5'ha == io_write_data_idx_25 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__11 = 5'hb == io_write_data_idx_25 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__12 = 5'hc == io_write_data_idx_25 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__13 = 5'hd == io_write_data_idx_25 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__14 = 5'he == io_write_data_idx_25 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__15 = 5'hf == io_write_data_idx_25 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__16 = 5'h10 == io_write_data_idx_25 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__17 = 5'h11 == io_write_data_idx_25 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__18 = 5'h12 == io_write_data_idx_25 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__19 = 5'h13 == io_write_data_idx_25 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__20 = 5'h14 == io_write_data_idx_25 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__21 = 5'h15 == io_write_data_idx_25 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__22 = 5'h16 == io_write_data_idx_25 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__23 = 5'h17 == io_write_data_idx_25 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__24 = 5'h18 == io_write_data_idx_25 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__25 = 5'h19 == io_write_data_idx_25 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__26 = 5'h1a == io_write_data_idx_25 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__27 = 5'h1b == io_write_data_idx_25 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__28 = 5'h1c == io_write_data_idx_25 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__29 = 5'h1d == io_write_data_idx_25 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__30 = 5'h1e == io_write_data_idx_25 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value__31 = 5'h1f == io_write_data_idx_25 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_25_value_1_0 = io_write_data_dataout_25_value__0 | io_write_data_dataout_25_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_1 = io_write_data_dataout_25_value__2 | io_write_data_dataout_25_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_2 = io_write_data_dataout_25_value__4 | io_write_data_dataout_25_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_3 = io_write_data_dataout_25_value__6 | io_write_data_dataout_25_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_4 = io_write_data_dataout_25_value__8 | io_write_data_dataout_25_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_5 = io_write_data_dataout_25_value__10 |
- io_write_data_dataout_25_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_6 = io_write_data_dataout_25_value__12 |
- io_write_data_dataout_25_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_7 = io_write_data_dataout_25_value__14 |
- io_write_data_dataout_25_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_8 = io_write_data_dataout_25_value__16 |
- io_write_data_dataout_25_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_9 = io_write_data_dataout_25_value__18 |
- io_write_data_dataout_25_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_10 = io_write_data_dataout_25_value__20 |
- io_write_data_dataout_25_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_11 = io_write_data_dataout_25_value__22 |
- io_write_data_dataout_25_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_12 = io_write_data_dataout_25_value__24 |
- io_write_data_dataout_25_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_13 = io_write_data_dataout_25_value__26 |
- io_write_data_dataout_25_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_14 = io_write_data_dataout_25_value__28 |
- io_write_data_dataout_25_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_1_15 = io_write_data_dataout_25_value__30 |
- io_write_data_dataout_25_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_2_0 = io_write_data_dataout_25_value_1_0 |
- io_write_data_dataout_25_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_2_1 = io_write_data_dataout_25_value_1_2 |
- io_write_data_dataout_25_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_2_2 = io_write_data_dataout_25_value_1_4 |
- io_write_data_dataout_25_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_2_3 = io_write_data_dataout_25_value_1_6 |
- io_write_data_dataout_25_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_2_4 = io_write_data_dataout_25_value_1_8 |
- io_write_data_dataout_25_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_2_5 = io_write_data_dataout_25_value_1_10 |
- io_write_data_dataout_25_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_2_6 = io_write_data_dataout_25_value_1_12 |
- io_write_data_dataout_25_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_2_7 = io_write_data_dataout_25_value_1_14 |
- io_write_data_dataout_25_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_3_0 = io_write_data_dataout_25_value_2_0 |
- io_write_data_dataout_25_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_3_1 = io_write_data_dataout_25_value_2_2 |
- io_write_data_dataout_25_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_3_2 = io_write_data_dataout_25_value_2_4 |
- io_write_data_dataout_25_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_3_3 = io_write_data_dataout_25_value_2_6 |
- io_write_data_dataout_25_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_4_0 = io_write_data_dataout_25_value_3_0 |
- io_write_data_dataout_25_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_4_1 = io_write_data_dataout_25_value_3_2 |
- io_write_data_dataout_25_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_25_value_5_0 = io_write_data_dataout_25_value_4_0 |
- io_write_data_dataout_25_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_26 = 5'h1a + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_26_value__0 = 5'h0 == io_write_data_idx_26 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__1 = 5'h1 == io_write_data_idx_26 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__2 = 5'h2 == io_write_data_idx_26 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__3 = 5'h3 == io_write_data_idx_26 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__4 = 5'h4 == io_write_data_idx_26 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__5 = 5'h5 == io_write_data_idx_26 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__6 = 5'h6 == io_write_data_idx_26 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__7 = 5'h7 == io_write_data_idx_26 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__8 = 5'h8 == io_write_data_idx_26 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__9 = 5'h9 == io_write_data_idx_26 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__10 = 5'ha == io_write_data_idx_26 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__11 = 5'hb == io_write_data_idx_26 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__12 = 5'hc == io_write_data_idx_26 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__13 = 5'hd == io_write_data_idx_26 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__14 = 5'he == io_write_data_idx_26 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__15 = 5'hf == io_write_data_idx_26 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__16 = 5'h10 == io_write_data_idx_26 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__17 = 5'h11 == io_write_data_idx_26 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__18 = 5'h12 == io_write_data_idx_26 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__19 = 5'h13 == io_write_data_idx_26 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__20 = 5'h14 == io_write_data_idx_26 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__21 = 5'h15 == io_write_data_idx_26 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__22 = 5'h16 == io_write_data_idx_26 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__23 = 5'h17 == io_write_data_idx_26 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__24 = 5'h18 == io_write_data_idx_26 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__25 = 5'h19 == io_write_data_idx_26 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__26 = 5'h1a == io_write_data_idx_26 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__27 = 5'h1b == io_write_data_idx_26 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__28 = 5'h1c == io_write_data_idx_26 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__29 = 5'h1d == io_write_data_idx_26 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__30 = 5'h1e == io_write_data_idx_26 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value__31 = 5'h1f == io_write_data_idx_26 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_26_value_1_0 = io_write_data_dataout_26_value__0 | io_write_data_dataout_26_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_1 = io_write_data_dataout_26_value__2 | io_write_data_dataout_26_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_2 = io_write_data_dataout_26_value__4 | io_write_data_dataout_26_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_3 = io_write_data_dataout_26_value__6 | io_write_data_dataout_26_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_4 = io_write_data_dataout_26_value__8 | io_write_data_dataout_26_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_5 = io_write_data_dataout_26_value__10 |
- io_write_data_dataout_26_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_6 = io_write_data_dataout_26_value__12 |
- io_write_data_dataout_26_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_7 = io_write_data_dataout_26_value__14 |
- io_write_data_dataout_26_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_8 = io_write_data_dataout_26_value__16 |
- io_write_data_dataout_26_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_9 = io_write_data_dataout_26_value__18 |
- io_write_data_dataout_26_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_10 = io_write_data_dataout_26_value__20 |
- io_write_data_dataout_26_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_11 = io_write_data_dataout_26_value__22 |
- io_write_data_dataout_26_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_12 = io_write_data_dataout_26_value__24 |
- io_write_data_dataout_26_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_13 = io_write_data_dataout_26_value__26 |
- io_write_data_dataout_26_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_14 = io_write_data_dataout_26_value__28 |
- io_write_data_dataout_26_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_1_15 = io_write_data_dataout_26_value__30 |
- io_write_data_dataout_26_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_2_0 = io_write_data_dataout_26_value_1_0 |
- io_write_data_dataout_26_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_2_1 = io_write_data_dataout_26_value_1_2 |
- io_write_data_dataout_26_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_2_2 = io_write_data_dataout_26_value_1_4 |
- io_write_data_dataout_26_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_2_3 = io_write_data_dataout_26_value_1_6 |
- io_write_data_dataout_26_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_2_4 = io_write_data_dataout_26_value_1_8 |
- io_write_data_dataout_26_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_2_5 = io_write_data_dataout_26_value_1_10 |
- io_write_data_dataout_26_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_2_6 = io_write_data_dataout_26_value_1_12 |
- io_write_data_dataout_26_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_2_7 = io_write_data_dataout_26_value_1_14 |
- io_write_data_dataout_26_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_3_0 = io_write_data_dataout_26_value_2_0 |
- io_write_data_dataout_26_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_3_1 = io_write_data_dataout_26_value_2_2 |
- io_write_data_dataout_26_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_3_2 = io_write_data_dataout_26_value_2_4 |
- io_write_data_dataout_26_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_3_3 = io_write_data_dataout_26_value_2_6 |
- io_write_data_dataout_26_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_4_0 = io_write_data_dataout_26_value_3_0 |
- io_write_data_dataout_26_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_4_1 = io_write_data_dataout_26_value_3_2 |
- io_write_data_dataout_26_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_26_value_5_0 = io_write_data_dataout_26_value_4_0 |
- io_write_data_dataout_26_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_27 = 5'h1b + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_27_value__0 = 5'h0 == io_write_data_idx_27 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__1 = 5'h1 == io_write_data_idx_27 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__2 = 5'h2 == io_write_data_idx_27 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__3 = 5'h3 == io_write_data_idx_27 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__4 = 5'h4 == io_write_data_idx_27 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__5 = 5'h5 == io_write_data_idx_27 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__6 = 5'h6 == io_write_data_idx_27 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__7 = 5'h7 == io_write_data_idx_27 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__8 = 5'h8 == io_write_data_idx_27 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__9 = 5'h9 == io_write_data_idx_27 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__10 = 5'ha == io_write_data_idx_27 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__11 = 5'hb == io_write_data_idx_27 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__12 = 5'hc == io_write_data_idx_27 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__13 = 5'hd == io_write_data_idx_27 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__14 = 5'he == io_write_data_idx_27 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__15 = 5'hf == io_write_data_idx_27 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__16 = 5'h10 == io_write_data_idx_27 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__17 = 5'h11 == io_write_data_idx_27 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__18 = 5'h12 == io_write_data_idx_27 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__19 = 5'h13 == io_write_data_idx_27 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__20 = 5'h14 == io_write_data_idx_27 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__21 = 5'h15 == io_write_data_idx_27 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__22 = 5'h16 == io_write_data_idx_27 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__23 = 5'h17 == io_write_data_idx_27 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__24 = 5'h18 == io_write_data_idx_27 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__25 = 5'h19 == io_write_data_idx_27 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__26 = 5'h1a == io_write_data_idx_27 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__27 = 5'h1b == io_write_data_idx_27 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__28 = 5'h1c == io_write_data_idx_27 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__29 = 5'h1d == io_write_data_idx_27 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__30 = 5'h1e == io_write_data_idx_27 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value__31 = 5'h1f == io_write_data_idx_27 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_27_value_1_0 = io_write_data_dataout_27_value__0 | io_write_data_dataout_27_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_1 = io_write_data_dataout_27_value__2 | io_write_data_dataout_27_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_2 = io_write_data_dataout_27_value__4 | io_write_data_dataout_27_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_3 = io_write_data_dataout_27_value__6 | io_write_data_dataout_27_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_4 = io_write_data_dataout_27_value__8 | io_write_data_dataout_27_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_5 = io_write_data_dataout_27_value__10 |
- io_write_data_dataout_27_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_6 = io_write_data_dataout_27_value__12 |
- io_write_data_dataout_27_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_7 = io_write_data_dataout_27_value__14 |
- io_write_data_dataout_27_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_8 = io_write_data_dataout_27_value__16 |
- io_write_data_dataout_27_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_9 = io_write_data_dataout_27_value__18 |
- io_write_data_dataout_27_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_10 = io_write_data_dataout_27_value__20 |
- io_write_data_dataout_27_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_11 = io_write_data_dataout_27_value__22 |
- io_write_data_dataout_27_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_12 = io_write_data_dataout_27_value__24 |
- io_write_data_dataout_27_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_13 = io_write_data_dataout_27_value__26 |
- io_write_data_dataout_27_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_14 = io_write_data_dataout_27_value__28 |
- io_write_data_dataout_27_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_1_15 = io_write_data_dataout_27_value__30 |
- io_write_data_dataout_27_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_2_0 = io_write_data_dataout_27_value_1_0 |
- io_write_data_dataout_27_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_2_1 = io_write_data_dataout_27_value_1_2 |
- io_write_data_dataout_27_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_2_2 = io_write_data_dataout_27_value_1_4 |
- io_write_data_dataout_27_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_2_3 = io_write_data_dataout_27_value_1_6 |
- io_write_data_dataout_27_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_2_4 = io_write_data_dataout_27_value_1_8 |
- io_write_data_dataout_27_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_2_5 = io_write_data_dataout_27_value_1_10 |
- io_write_data_dataout_27_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_2_6 = io_write_data_dataout_27_value_1_12 |
- io_write_data_dataout_27_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_2_7 = io_write_data_dataout_27_value_1_14 |
- io_write_data_dataout_27_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_3_0 = io_write_data_dataout_27_value_2_0 |
- io_write_data_dataout_27_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_3_1 = io_write_data_dataout_27_value_2_2 |
- io_write_data_dataout_27_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_3_2 = io_write_data_dataout_27_value_2_4 |
- io_write_data_dataout_27_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_3_3 = io_write_data_dataout_27_value_2_6 |
- io_write_data_dataout_27_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_4_0 = io_write_data_dataout_27_value_3_0 |
- io_write_data_dataout_27_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_4_1 = io_write_data_dataout_27_value_3_2 |
- io_write_data_dataout_27_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_27_value_5_0 = io_write_data_dataout_27_value_4_0 |
- io_write_data_dataout_27_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_28 = 5'h1c + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_28_value__0 = 5'h0 == io_write_data_idx_28 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__1 = 5'h1 == io_write_data_idx_28 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__2 = 5'h2 == io_write_data_idx_28 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__3 = 5'h3 == io_write_data_idx_28 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__4 = 5'h4 == io_write_data_idx_28 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__5 = 5'h5 == io_write_data_idx_28 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__6 = 5'h6 == io_write_data_idx_28 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__7 = 5'h7 == io_write_data_idx_28 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__8 = 5'h8 == io_write_data_idx_28 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__9 = 5'h9 == io_write_data_idx_28 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__10 = 5'ha == io_write_data_idx_28 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__11 = 5'hb == io_write_data_idx_28 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__12 = 5'hc == io_write_data_idx_28 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__13 = 5'hd == io_write_data_idx_28 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__14 = 5'he == io_write_data_idx_28 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__15 = 5'hf == io_write_data_idx_28 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__16 = 5'h10 == io_write_data_idx_28 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__17 = 5'h11 == io_write_data_idx_28 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__18 = 5'h12 == io_write_data_idx_28 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__19 = 5'h13 == io_write_data_idx_28 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__20 = 5'h14 == io_write_data_idx_28 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__21 = 5'h15 == io_write_data_idx_28 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__22 = 5'h16 == io_write_data_idx_28 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__23 = 5'h17 == io_write_data_idx_28 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__24 = 5'h18 == io_write_data_idx_28 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__25 = 5'h19 == io_write_data_idx_28 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__26 = 5'h1a == io_write_data_idx_28 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__27 = 5'h1b == io_write_data_idx_28 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__28 = 5'h1c == io_write_data_idx_28 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__29 = 5'h1d == io_write_data_idx_28 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__30 = 5'h1e == io_write_data_idx_28 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value__31 = 5'h1f == io_write_data_idx_28 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_28_value_1_0 = io_write_data_dataout_28_value__0 | io_write_data_dataout_28_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_1 = io_write_data_dataout_28_value__2 | io_write_data_dataout_28_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_2 = io_write_data_dataout_28_value__4 | io_write_data_dataout_28_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_3 = io_write_data_dataout_28_value__6 | io_write_data_dataout_28_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_4 = io_write_data_dataout_28_value__8 | io_write_data_dataout_28_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_5 = io_write_data_dataout_28_value__10 |
- io_write_data_dataout_28_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_6 = io_write_data_dataout_28_value__12 |
- io_write_data_dataout_28_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_7 = io_write_data_dataout_28_value__14 |
- io_write_data_dataout_28_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_8 = io_write_data_dataout_28_value__16 |
- io_write_data_dataout_28_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_9 = io_write_data_dataout_28_value__18 |
- io_write_data_dataout_28_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_10 = io_write_data_dataout_28_value__20 |
- io_write_data_dataout_28_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_11 = io_write_data_dataout_28_value__22 |
- io_write_data_dataout_28_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_12 = io_write_data_dataout_28_value__24 |
- io_write_data_dataout_28_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_13 = io_write_data_dataout_28_value__26 |
- io_write_data_dataout_28_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_14 = io_write_data_dataout_28_value__28 |
- io_write_data_dataout_28_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_1_15 = io_write_data_dataout_28_value__30 |
- io_write_data_dataout_28_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_2_0 = io_write_data_dataout_28_value_1_0 |
- io_write_data_dataout_28_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_2_1 = io_write_data_dataout_28_value_1_2 |
- io_write_data_dataout_28_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_2_2 = io_write_data_dataout_28_value_1_4 |
- io_write_data_dataout_28_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_2_3 = io_write_data_dataout_28_value_1_6 |
- io_write_data_dataout_28_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_2_4 = io_write_data_dataout_28_value_1_8 |
- io_write_data_dataout_28_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_2_5 = io_write_data_dataout_28_value_1_10 |
- io_write_data_dataout_28_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_2_6 = io_write_data_dataout_28_value_1_12 |
- io_write_data_dataout_28_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_2_7 = io_write_data_dataout_28_value_1_14 |
- io_write_data_dataout_28_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_3_0 = io_write_data_dataout_28_value_2_0 |
- io_write_data_dataout_28_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_3_1 = io_write_data_dataout_28_value_2_2 |
- io_write_data_dataout_28_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_3_2 = io_write_data_dataout_28_value_2_4 |
- io_write_data_dataout_28_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_3_3 = io_write_data_dataout_28_value_2_6 |
- io_write_data_dataout_28_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_4_0 = io_write_data_dataout_28_value_3_0 |
- io_write_data_dataout_28_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_4_1 = io_write_data_dataout_28_value_3_2 |
- io_write_data_dataout_28_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_28_value_5_0 = io_write_data_dataout_28_value_4_0 |
- io_write_data_dataout_28_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_29 = 5'h1d + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_29_value__0 = 5'h0 == io_write_data_idx_29 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__1 = 5'h1 == io_write_data_idx_29 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__2 = 5'h2 == io_write_data_idx_29 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__3 = 5'h3 == io_write_data_idx_29 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__4 = 5'h4 == io_write_data_idx_29 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__5 = 5'h5 == io_write_data_idx_29 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__6 = 5'h6 == io_write_data_idx_29 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__7 = 5'h7 == io_write_data_idx_29 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__8 = 5'h8 == io_write_data_idx_29 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__9 = 5'h9 == io_write_data_idx_29 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__10 = 5'ha == io_write_data_idx_29 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__11 = 5'hb == io_write_data_idx_29 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__12 = 5'hc == io_write_data_idx_29 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__13 = 5'hd == io_write_data_idx_29 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__14 = 5'he == io_write_data_idx_29 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__15 = 5'hf == io_write_data_idx_29 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__16 = 5'h10 == io_write_data_idx_29 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__17 = 5'h11 == io_write_data_idx_29 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__18 = 5'h12 == io_write_data_idx_29 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__19 = 5'h13 == io_write_data_idx_29 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__20 = 5'h14 == io_write_data_idx_29 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__21 = 5'h15 == io_write_data_idx_29 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__22 = 5'h16 == io_write_data_idx_29 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__23 = 5'h17 == io_write_data_idx_29 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__24 = 5'h18 == io_write_data_idx_29 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__25 = 5'h19 == io_write_data_idx_29 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__26 = 5'h1a == io_write_data_idx_29 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__27 = 5'h1b == io_write_data_idx_29 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__28 = 5'h1c == io_write_data_idx_29 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__29 = 5'h1d == io_write_data_idx_29 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__30 = 5'h1e == io_write_data_idx_29 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value__31 = 5'h1f == io_write_data_idx_29 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_29_value_1_0 = io_write_data_dataout_29_value__0 | io_write_data_dataout_29_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_1 = io_write_data_dataout_29_value__2 | io_write_data_dataout_29_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_2 = io_write_data_dataout_29_value__4 | io_write_data_dataout_29_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_3 = io_write_data_dataout_29_value__6 | io_write_data_dataout_29_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_4 = io_write_data_dataout_29_value__8 | io_write_data_dataout_29_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_5 = io_write_data_dataout_29_value__10 |
- io_write_data_dataout_29_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_6 = io_write_data_dataout_29_value__12 |
- io_write_data_dataout_29_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_7 = io_write_data_dataout_29_value__14 |
- io_write_data_dataout_29_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_8 = io_write_data_dataout_29_value__16 |
- io_write_data_dataout_29_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_9 = io_write_data_dataout_29_value__18 |
- io_write_data_dataout_29_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_10 = io_write_data_dataout_29_value__20 |
- io_write_data_dataout_29_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_11 = io_write_data_dataout_29_value__22 |
- io_write_data_dataout_29_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_12 = io_write_data_dataout_29_value__24 |
- io_write_data_dataout_29_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_13 = io_write_data_dataout_29_value__26 |
- io_write_data_dataout_29_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_14 = io_write_data_dataout_29_value__28 |
- io_write_data_dataout_29_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_1_15 = io_write_data_dataout_29_value__30 |
- io_write_data_dataout_29_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_2_0 = io_write_data_dataout_29_value_1_0 |
- io_write_data_dataout_29_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_2_1 = io_write_data_dataout_29_value_1_2 |
- io_write_data_dataout_29_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_2_2 = io_write_data_dataout_29_value_1_4 |
- io_write_data_dataout_29_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_2_3 = io_write_data_dataout_29_value_1_6 |
- io_write_data_dataout_29_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_2_4 = io_write_data_dataout_29_value_1_8 |
- io_write_data_dataout_29_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_2_5 = io_write_data_dataout_29_value_1_10 |
- io_write_data_dataout_29_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_2_6 = io_write_data_dataout_29_value_1_12 |
- io_write_data_dataout_29_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_2_7 = io_write_data_dataout_29_value_1_14 |
- io_write_data_dataout_29_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_3_0 = io_write_data_dataout_29_value_2_0 |
- io_write_data_dataout_29_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_3_1 = io_write_data_dataout_29_value_2_2 |
- io_write_data_dataout_29_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_3_2 = io_write_data_dataout_29_value_2_4 |
- io_write_data_dataout_29_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_3_3 = io_write_data_dataout_29_value_2_6 |
- io_write_data_dataout_29_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_4_0 = io_write_data_dataout_29_value_3_0 |
- io_write_data_dataout_29_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_4_1 = io_write_data_dataout_29_value_3_2 |
- io_write_data_dataout_29_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_29_value_5_0 = io_write_data_dataout_29_value_4_0 |
- io_write_data_dataout_29_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_30 = 5'h1e + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_30_value__0 = 5'h0 == io_write_data_idx_30 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__1 = 5'h1 == io_write_data_idx_30 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__2 = 5'h2 == io_write_data_idx_30 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__3 = 5'h3 == io_write_data_idx_30 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__4 = 5'h4 == io_write_data_idx_30 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__5 = 5'h5 == io_write_data_idx_30 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__6 = 5'h6 == io_write_data_idx_30 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__7 = 5'h7 == io_write_data_idx_30 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__8 = 5'h8 == io_write_data_idx_30 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__9 = 5'h9 == io_write_data_idx_30 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__10 = 5'ha == io_write_data_idx_30 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__11 = 5'hb == io_write_data_idx_30 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__12 = 5'hc == io_write_data_idx_30 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__13 = 5'hd == io_write_data_idx_30 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__14 = 5'he == io_write_data_idx_30 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__15 = 5'hf == io_write_data_idx_30 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__16 = 5'h10 == io_write_data_idx_30 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__17 = 5'h11 == io_write_data_idx_30 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__18 = 5'h12 == io_write_data_idx_30 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__19 = 5'h13 == io_write_data_idx_30 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__20 = 5'h14 == io_write_data_idx_30 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__21 = 5'h15 == io_write_data_idx_30 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__22 = 5'h16 == io_write_data_idx_30 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__23 = 5'h17 == io_write_data_idx_30 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__24 = 5'h18 == io_write_data_idx_30 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__25 = 5'h19 == io_write_data_idx_30 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__26 = 5'h1a == io_write_data_idx_30 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__27 = 5'h1b == io_write_data_idx_30 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__28 = 5'h1c == io_write_data_idx_30 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__29 = 5'h1d == io_write_data_idx_30 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__30 = 5'h1e == io_write_data_idx_30 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value__31 = 5'h1f == io_write_data_idx_30 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_30_value_1_0 = io_write_data_dataout_30_value__0 | io_write_data_dataout_30_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_1 = io_write_data_dataout_30_value__2 | io_write_data_dataout_30_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_2 = io_write_data_dataout_30_value__4 | io_write_data_dataout_30_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_3 = io_write_data_dataout_30_value__6 | io_write_data_dataout_30_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_4 = io_write_data_dataout_30_value__8 | io_write_data_dataout_30_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_5 = io_write_data_dataout_30_value__10 |
- io_write_data_dataout_30_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_6 = io_write_data_dataout_30_value__12 |
- io_write_data_dataout_30_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_7 = io_write_data_dataout_30_value__14 |
- io_write_data_dataout_30_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_8 = io_write_data_dataout_30_value__16 |
- io_write_data_dataout_30_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_9 = io_write_data_dataout_30_value__18 |
- io_write_data_dataout_30_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_10 = io_write_data_dataout_30_value__20 |
- io_write_data_dataout_30_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_11 = io_write_data_dataout_30_value__22 |
- io_write_data_dataout_30_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_12 = io_write_data_dataout_30_value__24 |
- io_write_data_dataout_30_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_13 = io_write_data_dataout_30_value__26 |
- io_write_data_dataout_30_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_14 = io_write_data_dataout_30_value__28 |
- io_write_data_dataout_30_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_1_15 = io_write_data_dataout_30_value__30 |
- io_write_data_dataout_30_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_2_0 = io_write_data_dataout_30_value_1_0 |
- io_write_data_dataout_30_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_2_1 = io_write_data_dataout_30_value_1_2 |
- io_write_data_dataout_30_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_2_2 = io_write_data_dataout_30_value_1_4 |
- io_write_data_dataout_30_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_2_3 = io_write_data_dataout_30_value_1_6 |
- io_write_data_dataout_30_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_2_4 = io_write_data_dataout_30_value_1_8 |
- io_write_data_dataout_30_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_2_5 = io_write_data_dataout_30_value_1_10 |
- io_write_data_dataout_30_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_2_6 = io_write_data_dataout_30_value_1_12 |
- io_write_data_dataout_30_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_2_7 = io_write_data_dataout_30_value_1_14 |
- io_write_data_dataout_30_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_3_0 = io_write_data_dataout_30_value_2_0 |
- io_write_data_dataout_30_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_3_1 = io_write_data_dataout_30_value_2_2 |
- io_write_data_dataout_30_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_3_2 = io_write_data_dataout_30_value_2_4 |
- io_write_data_dataout_30_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_3_3 = io_write_data_dataout_30_value_2_6 |
- io_write_data_dataout_30_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_4_0 = io_write_data_dataout_30_value_3_0 |
- io_write_data_dataout_30_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_4_1 = io_write_data_dataout_30_value_3_2 |
- io_write_data_dataout_30_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_30_value_5_0 = io_write_data_dataout_30_value_4_0 |
- io_write_data_dataout_30_value_4_1; // @[Library.scala 129:37]
- wire [4:0] io_write_data_idx_31 = 5'h1f + io_write_data_index; // @[VLdSt.scala 71:35]
- wire [7:0] io_write_data_dataout_31_value__0 = 5'h0 == io_write_data_idx_31 ? io_write_data_datain_0 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__1 = 5'h1 == io_write_data_idx_31 ? io_write_data_datain_1 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__2 = 5'h2 == io_write_data_idx_31 ? io_write_data_datain_2 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__3 = 5'h3 == io_write_data_idx_31 ? io_write_data_datain_3 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__4 = 5'h4 == io_write_data_idx_31 ? io_write_data_datain_4 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__5 = 5'h5 == io_write_data_idx_31 ? io_write_data_datain_5 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__6 = 5'h6 == io_write_data_idx_31 ? io_write_data_datain_6 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__7 = 5'h7 == io_write_data_idx_31 ? io_write_data_datain_7 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__8 = 5'h8 == io_write_data_idx_31 ? io_write_data_datain_8 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__9 = 5'h9 == io_write_data_idx_31 ? io_write_data_datain_9 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__10 = 5'ha == io_write_data_idx_31 ? io_write_data_datain_10 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__11 = 5'hb == io_write_data_idx_31 ? io_write_data_datain_11 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__12 = 5'hc == io_write_data_idx_31 ? io_write_data_datain_12 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__13 = 5'hd == io_write_data_idx_31 ? io_write_data_datain_13 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__14 = 5'he == io_write_data_idx_31 ? io_write_data_datain_14 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__15 = 5'hf == io_write_data_idx_31 ? io_write_data_datain_15 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__16 = 5'h10 == io_write_data_idx_31 ? io_write_data_datain_16 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__17 = 5'h11 == io_write_data_idx_31 ? io_write_data_datain_17 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__18 = 5'h12 == io_write_data_idx_31 ? io_write_data_datain_18 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__19 = 5'h13 == io_write_data_idx_31 ? io_write_data_datain_19 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__20 = 5'h14 == io_write_data_idx_31 ? io_write_data_datain_20 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__21 = 5'h15 == io_write_data_idx_31 ? io_write_data_datain_21 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__22 = 5'h16 == io_write_data_idx_31 ? io_write_data_datain_22 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__23 = 5'h17 == io_write_data_idx_31 ? io_write_data_datain_23 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__24 = 5'h18 == io_write_data_idx_31 ? io_write_data_datain_24 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__25 = 5'h19 == io_write_data_idx_31 ? io_write_data_datain_25 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__26 = 5'h1a == io_write_data_idx_31 ? io_write_data_datain_26 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__27 = 5'h1b == io_write_data_idx_31 ? io_write_data_datain_27 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__28 = 5'h1c == io_write_data_idx_31 ? io_write_data_datain_28 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__29 = 5'h1d == io_write_data_idx_31 ? io_write_data_datain_29 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__30 = 5'h1e == io_write_data_idx_31 ? io_write_data_datain_30 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value__31 = 5'h1f == io_write_data_idx_31 ? io_write_data_datain_31 : 8'h0; // @[Library.scala 115:22]
- wire [7:0] io_write_data_dataout_31_value_1_0 = io_write_data_dataout_31_value__0 | io_write_data_dataout_31_value__1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_1 = io_write_data_dataout_31_value__2 | io_write_data_dataout_31_value__3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_2 = io_write_data_dataout_31_value__4 | io_write_data_dataout_31_value__5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_3 = io_write_data_dataout_31_value__6 | io_write_data_dataout_31_value__7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_4 = io_write_data_dataout_31_value__8 | io_write_data_dataout_31_value__9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_5 = io_write_data_dataout_31_value__10 |
- io_write_data_dataout_31_value__11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_6 = io_write_data_dataout_31_value__12 |
- io_write_data_dataout_31_value__13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_7 = io_write_data_dataout_31_value__14 |
- io_write_data_dataout_31_value__15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_8 = io_write_data_dataout_31_value__16 |
- io_write_data_dataout_31_value__17; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_9 = io_write_data_dataout_31_value__18 |
- io_write_data_dataout_31_value__19; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_10 = io_write_data_dataout_31_value__20 |
- io_write_data_dataout_31_value__21; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_11 = io_write_data_dataout_31_value__22 |
- io_write_data_dataout_31_value__23; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_12 = io_write_data_dataout_31_value__24 |
- io_write_data_dataout_31_value__25; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_13 = io_write_data_dataout_31_value__26 |
- io_write_data_dataout_31_value__27; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_14 = io_write_data_dataout_31_value__28 |
- io_write_data_dataout_31_value__29; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_1_15 = io_write_data_dataout_31_value__30 |
- io_write_data_dataout_31_value__31; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_2_0 = io_write_data_dataout_31_value_1_0 |
- io_write_data_dataout_31_value_1_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_2_1 = io_write_data_dataout_31_value_1_2 |
- io_write_data_dataout_31_value_1_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_2_2 = io_write_data_dataout_31_value_1_4 |
- io_write_data_dataout_31_value_1_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_2_3 = io_write_data_dataout_31_value_1_6 |
- io_write_data_dataout_31_value_1_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_2_4 = io_write_data_dataout_31_value_1_8 |
- io_write_data_dataout_31_value_1_9; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_2_5 = io_write_data_dataout_31_value_1_10 |
- io_write_data_dataout_31_value_1_11; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_2_6 = io_write_data_dataout_31_value_1_12 |
- io_write_data_dataout_31_value_1_13; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_2_7 = io_write_data_dataout_31_value_1_14 |
- io_write_data_dataout_31_value_1_15; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_3_0 = io_write_data_dataout_31_value_2_0 |
- io_write_data_dataout_31_value_2_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_3_1 = io_write_data_dataout_31_value_2_2 |
- io_write_data_dataout_31_value_2_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_3_2 = io_write_data_dataout_31_value_2_4 |
- io_write_data_dataout_31_value_2_5; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_3_3 = io_write_data_dataout_31_value_2_6 |
- io_write_data_dataout_31_value_2_7; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_4_0 = io_write_data_dataout_31_value_3_0 |
- io_write_data_dataout_31_value_3_1; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_4_1 = io_write_data_dataout_31_value_3_2 |
- io_write_data_dataout_31_value_3_3; // @[Library.scala 129:37]
- wire [7:0] io_write_data_dataout_31_value_5_0 = io_write_data_dataout_31_value_4_0 |
- io_write_data_dataout_31_value_4_1; // @[Library.scala 129:37]
- wire [63:0] io_write_data_lo_lo = {io_write_data_dataout_7_value_5_0,io_write_data_dataout_6_value_5_0,
- io_write_data_dataout_5_value_5_0,io_write_data_dataout_4_value_5_0,io_write_data_dataout_3_value_5_0,
- io_write_data_dataout_2_value_5_0,io_write_data_dataout_1_value_5_0,io_write_data_dataout_0_value_5_0}; // @[VLdSt.scala 76:13]
- wire [127:0] io_write_data_lo = {io_write_data_dataout_15_value_5_0,io_write_data_dataout_14_value_5_0,
- io_write_data_dataout_13_value_5_0,io_write_data_dataout_12_value_5_0,io_write_data_dataout_11_value_5_0,
- io_write_data_dataout_10_value_5_0,io_write_data_dataout_9_value_5_0,io_write_data_dataout_8_value_5_0,
- io_write_data_lo_lo}; // @[VLdSt.scala 76:13]
- wire [63:0] io_write_data_hi_lo = {io_write_data_dataout_23_value_5_0,io_write_data_dataout_22_value_5_0,
- io_write_data_dataout_21_value_5_0,io_write_data_dataout_20_value_5_0,io_write_data_dataout_19_value_5_0,
- io_write_data_dataout_18_value_5_0,io_write_data_dataout_17_value_5_0,io_write_data_dataout_16_value_5_0}; // @[VLdSt.scala 76:13]
- wire [255:0] _io_write_data_T = {io_write_data_dataout_31_value_5_0,io_write_data_dataout_30_value_5_0,
- io_write_data_dataout_29_value_5_0,io_write_data_dataout_28_value_5_0,io_write_data_dataout_27_value_5_0,
- io_write_data_dataout_26_value_5_0,io_write_data_dataout_25_value_5_0,io_write_data_dataout_24_value_5_0,
- io_write_data_hi_lo,io_write_data_lo}; // @[VLdSt.scala 76:13]
- VCmdq_3 q ( // @[VCmdq.scala 30:11]
- .clock(q_clock),
- .reset(q_reset),
- .io_in_ready(q_io_in_ready),
- .io_in_valid(q_io_in_valid),
- .io_in_bits_0_valid(q_io_in_bits_0_valid),
- .io_in_bits_0_bits_op(q_io_in_bits_0_bits_op),
- .io_in_bits_0_bits_f2(q_io_in_bits_0_bits_f2),
- .io_in_bits_0_bits_sz(q_io_in_bits_0_bits_sz),
- .io_in_bits_0_bits_m(q_io_in_bits_0_bits_m),
- .io_in_bits_0_bits_vd_valid(q_io_in_bits_0_bits_vd_valid),
- .io_in_bits_0_bits_vd_addr(q_io_in_bits_0_bits_vd_addr),
- .io_in_bits_0_bits_vs_valid(q_io_in_bits_0_bits_vs_valid),
- .io_in_bits_0_bits_vs_addr(q_io_in_bits_0_bits_vs_addr),
- .io_in_bits_0_bits_vs_tag(q_io_in_bits_0_bits_vs_tag),
- .io_in_bits_0_bits_sv_addr(q_io_in_bits_0_bits_sv_addr),
- .io_in_bits_0_bits_sv_data(q_io_in_bits_0_bits_sv_data),
- .io_in_bits_1_valid(q_io_in_bits_1_valid),
- .io_in_bits_1_bits_op(q_io_in_bits_1_bits_op),
- .io_in_bits_1_bits_f2(q_io_in_bits_1_bits_f2),
- .io_in_bits_1_bits_sz(q_io_in_bits_1_bits_sz),
- .io_in_bits_1_bits_m(q_io_in_bits_1_bits_m),
- .io_in_bits_1_bits_vd_valid(q_io_in_bits_1_bits_vd_valid),
- .io_in_bits_1_bits_vd_addr(q_io_in_bits_1_bits_vd_addr),
- .io_in_bits_1_bits_vs_valid(q_io_in_bits_1_bits_vs_valid),
- .io_in_bits_1_bits_vs_addr(q_io_in_bits_1_bits_vs_addr),
- .io_in_bits_1_bits_vs_tag(q_io_in_bits_1_bits_vs_tag),
- .io_in_bits_1_bits_sv_addr(q_io_in_bits_1_bits_sv_addr),
- .io_in_bits_1_bits_sv_data(q_io_in_bits_1_bits_sv_data),
- .io_in_bits_2_valid(q_io_in_bits_2_valid),
- .io_in_bits_2_bits_op(q_io_in_bits_2_bits_op),
- .io_in_bits_2_bits_f2(q_io_in_bits_2_bits_f2),
- .io_in_bits_2_bits_sz(q_io_in_bits_2_bits_sz),
- .io_in_bits_2_bits_m(q_io_in_bits_2_bits_m),
- .io_in_bits_2_bits_vd_valid(q_io_in_bits_2_bits_vd_valid),
- .io_in_bits_2_bits_vd_addr(q_io_in_bits_2_bits_vd_addr),
- .io_in_bits_2_bits_vs_valid(q_io_in_bits_2_bits_vs_valid),
- .io_in_bits_2_bits_vs_addr(q_io_in_bits_2_bits_vs_addr),
- .io_in_bits_2_bits_vs_tag(q_io_in_bits_2_bits_vs_tag),
- .io_in_bits_2_bits_sv_addr(q_io_in_bits_2_bits_sv_addr),
- .io_in_bits_2_bits_sv_data(q_io_in_bits_2_bits_sv_data),
- .io_in_bits_3_valid(q_io_in_bits_3_valid),
- .io_in_bits_3_bits_op(q_io_in_bits_3_bits_op),
- .io_in_bits_3_bits_f2(q_io_in_bits_3_bits_f2),
- .io_in_bits_3_bits_sz(q_io_in_bits_3_bits_sz),
- .io_in_bits_3_bits_m(q_io_in_bits_3_bits_m),
- .io_in_bits_3_bits_vd_valid(q_io_in_bits_3_bits_vd_valid),
- .io_in_bits_3_bits_vd_addr(q_io_in_bits_3_bits_vd_addr),
- .io_in_bits_3_bits_vs_valid(q_io_in_bits_3_bits_vs_valid),
- .io_in_bits_3_bits_vs_addr(q_io_in_bits_3_bits_vs_addr),
- .io_in_bits_3_bits_vs_tag(q_io_in_bits_3_bits_vs_tag),
- .io_in_bits_3_bits_sv_addr(q_io_in_bits_3_bits_sv_addr),
- .io_in_bits_3_bits_sv_data(q_io_in_bits_3_bits_sv_data),
- .io_out_ready(q_io_out_ready),
- .io_out_valid(q_io_out_valid),
- .io_out_bits_op(q_io_out_bits_op),
- .io_out_bits_addr(q_io_out_bits_addr),
- .io_out_bits_remain(q_io_out_bits_remain),
- .io_out_bits_vd_addr(q_io_out_bits_vd_addr),
- .io_out_bits_vs_valid(q_io_out_bits_vs_valid),
- .io_out_bits_vs_addr(q_io_out_bits_vs_addr),
- .io_out_bits_vs_tag(q_io_out_bits_vs_tag),
- .io_out_bits_quad(q_io_out_bits_quad),
- .io_out_bits_last(q_io_out_bits_last),
- .io_active(q_io_active)
- );
- Fifo ctrl ( // @[Fifo.scala 22:11]
- .clock(ctrl_clock),
- .reset(ctrl_reset),
- .io_in_ready(ctrl_io_in_ready),
- .io_in_valid(ctrl_io_in_valid),
- .io_in_bits_last(ctrl_io_in_bits_last),
- .io_in_bits_write(ctrl_io_in_bits_write),
- .io_in_bits_addr(ctrl_io_in_bits_addr),
- .io_in_bits_adrx(ctrl_io_in_bits_adrx),
- .io_in_bits_size(ctrl_io_in_bits_size),
- .io_in_bits_widx(ctrl_io_in_bits_widx),
- .io_out_ready(ctrl_io_out_ready),
- .io_out_valid(ctrl_io_out_valid),
- .io_out_bits_last(ctrl_io_out_bits_last),
- .io_out_bits_write(ctrl_io_out_bits_write),
- .io_out_bits_addr(ctrl_io_out_bits_addr),
- .io_out_bits_adrx(ctrl_io_out_bits_adrx),
- .io_out_bits_size(ctrl_io_out_bits_size),
- .io_out_bits_widx(ctrl_io_out_bits_widx)
- );
- Fifo_1 data ( // @[Fifo.scala 22:11]
- .clock(data_clock),
- .reset(data_reset),
- .io_in_ready(data_io_in_ready),
- .io_in_valid(data_io_in_valid),
- .io_in_bits_wdata(data_io_in_bits_wdata),
- .io_in_bits_wmask(data_io_in_bits_wmask),
- .io_out_ready(data_io_out_ready),
- .io_out_valid(data_io_out_valid),
- .io_out_bits_wdata(data_io_out_bits_wdata),
- .io_out_bits_wmask(data_io_out_bits_wmask)
- );
- Slice_4 wrega ( // @[Slice.scala 23:11]
- .clock(wrega_clock),
- .reset(wrega_reset),
- .io_in_ready(wrega_io_in_ready),
- .io_in_valid(wrega_io_in_valid),
- .io_in_bits_widx(wrega_io_in_bits_widx),
- .io_in_bits_addr(wrega_io_in_bits_addr),
- .io_in_bits_size(wrega_io_in_bits_size),
- .io_out_ready(wrega_io_out_ready),
- .io_out_valid(wrega_io_out_valid),
- .io_out_bits_widx(wrega_io_out_bits_widx),
- .io_out_bits_addr(wrega_io_out_bits_addr),
- .io_out_bits_size(wrega_io_out_bits_size)
- );
- Slice_5 wregd ( // @[Slice.scala 23:11]
- .clock(wregd_clock),
- .reset(wregd_reset),
- .io_in_ready(wregd_io_in_ready),
- .io_in_valid(wregd_io_in_valid),
- .io_in_bits(wregd_io_in_bits),
- .io_out_ready(wregd_io_out_ready),
- .io_out_valid(wregd_io_out_valid),
- .io_out_bits(wregd_io_out_bits)
- );
- assign io_in_ready = q_io_in_ready; // @[VLdSt.scala 181:11]
- assign io_active = q_io_active; // @[VLdSt.scala 312:13]
- assign io_read_valid = q_io_out_valid & q_io_out_bits_vs_valid; // @[VLdSt.scala 188:35]
- assign io_read_addr = q_io_out_bits_vs_addr; // @[VLdSt.scala 190:16]
- assign io_write_valid = wrega_io_out_valid & wregd_io_out_valid; // @[VLdSt.scala 306:40]
- assign io_write_addr = wrega_io_out_bits_widx; // @[VLdSt.scala 307:17]
- assign io_write_data = _io_write_data_T & mask; // @[VLdSt.scala 308:80]
- assign io_dbus_valid = ctrl_io_out_valid & _ctrl_io_out_ready_T_1; // @[VLdSt.scala 265:38]
- assign io_dbus_write = ctrl_io_out_bits_write; // @[VLdSt.scala 266:17]
- assign io_dbus_addr = {1'h0,ctrl_io_out_bits_addr[30:0]}; // @[Cat.scala 31:58]
- assign io_dbus_adrx = {1'h0,ctrl_io_out_bits_adrx[30:0]}; // @[Cat.scala 31:58]
- assign io_dbus_size = ctrl_io_out_bits_size; // @[VLdSt.scala 269:16]
- assign io_dbus_wdata = data_io_out_bits_wdata; // @[VLdSt.scala 270:17]
- assign io_dbus_wmask = data_io_out_bits_wmask; // @[VLdSt.scala 271:17]
- assign io_last = ctrl_io_out_bits_last; // @[VLdSt.scala 277:11]
- assign q_clock = clock;
- assign q_reset = reset;
- assign q_io_in_valid = io_in_valid; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_0_valid = io_in_bits_0_valid; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_0_bits_vd_valid = io_in_bits_0_bits_vd_valid; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_0_bits_sv_addr = io_in_bits_0_bits_sv_addr; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_1_valid = io_in_bits_1_valid; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_1_bits_vd_valid = io_in_bits_1_bits_vd_valid; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_1_bits_sv_addr = io_in_bits_1_bits_sv_addr; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_2_valid = io_in_bits_2_valid; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_2_bits_vd_valid = io_in_bits_2_bits_vd_valid; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_2_bits_sv_addr = io_in_bits_2_bits_sv_addr; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_3_valid = io_in_bits_3_valid; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_3_bits_vd_valid = io_in_bits_3_bits_vd_valid; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_3_bits_sv_addr = io_in_bits_3_bits_sv_addr; // @[VLdSt.scala 181:11]
- assign q_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VLdSt.scala 181:11]
- assign q_io_out_ready = _q_io_out_ready_T_4 & ctrlready; // @[VLdSt.scala 184:65]
- assign ctrl_clock = clock;
- assign ctrl_reset = reset;
- assign ctrl_io_in_valid = q_io_out_valid & q_io_out_ready; // @[VLdSt.scala 227:31]
- assign ctrl_io_in_bits_last = q_io_out_bits_last; // @[VLdSt.scala 251:25]
- assign ctrl_io_in_bits_write = q_io_out_bits_op == 7'h3 | _qmaxvlb_T; // @[VLdSt.scala 98:22]
- assign ctrl_io_in_bits_addr = q_io_out_bits_addr; // @[VLdSt.scala 248:25]
- assign ctrl_io_in_bits_adrx = q_io_out_bits_addr + 32'h20; // @[VLdSt.scala 249:47]
- assign ctrl_io_in_bits_size = qsize[5:0]; // @[VLdSt.scala 250:25]
- assign ctrl_io_in_bits_widx = q_io_out_bits_vd_addr; // @[VLdSt.scala 253:25]
- assign ctrl_io_out_ready = io_dbus_ready & (data_io_out_valid | ~ctrl_io_out_bits_write); // @[VLdSt.scala 261:38]
- assign data_clock = clock;
- assign data_reset = reset;
- assign data_io_in_valid = rdataEn; // @[VLdSt.scala 256:20]
- assign data_io_in_bits_wdata = {data_io_in_bits_wdata_hi,data_io_in_bits_wdata_lo}; // @[VLdSt.scala 76:13]
- assign data_io_in_bits_wmask = {data_io_in_bits_wmask_hi_1,data_io_in_bits_wmask_lo_1}; // @[VLdSt.scala 76:13]
- assign data_io_out_ready = io_dbus_ready & (ctrl_io_out_valid & ctrl_io_out_bits_write); // @[VLdSt.scala 262:38]
- assign wrega_clock = clock;
- assign wrega_reset = reset;
- assign wrega_io_in_valid = ctrl_io_out_valid & io_dbus_ready & _ctrl_io_out_ready_T; // @[VLdSt.scala 287:59]
- assign wrega_io_in_bits_widx = ctrl_io_out_bits_widx; // @[VLdSt.scala 288:25]
- assign wrega_io_in_bits_addr = ctrl_io_out_bits_addr[4:0]; // @[VLdSt.scala 289:25]
- assign wrega_io_in_bits_size = ctrl_io_out_bits_size; // @[VLdSt.scala 290:25]
- assign wrega_io_out_ready = wregd_io_out_valid; // @[VLdSt.scala 291:22]
- assign wregd_clock = clock;
- assign wregd_reset = reset;
- assign wregd_io_in_valid = wdataEn; // @[VLdSt.scala 294:21]
- assign wregd_io_in_bits = io_dbus_rdata; // @[VLdSt.scala 295:20]
- assign wregd_io_out_ready = wrega_io_out_valid; // @[VLdSt.scala 296:22]
- always @(posedge clock) begin
- if (rdataEnNxt) begin // @[VLdSt.scala 234:21]
- if (q_io_out_bits_remain > qmaxvlb) begin // @[VLdSt.scala 231:18]
- if (q_io_out_bits_op == 7'h4) begin // @[VLdSt.scala 230:20]
- rdataSize <= 8'h8;
- end else begin
- rdataSize <= 8'h20;
- end
- end else begin
- rdataSize <= q_io_out_bits_remain;
- end
- end
- rdataAddr <= _GEN_1[4:0];
- rdataAshf <= _GEN_2[4:0];
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(ctrl_io_in_valid & ~ctrl_io_in_ready))) begin
- $fatal; // @[VLdSt.scala 254:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(ctrl_io_in_valid & ~ctrl_io_in_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:254 assert(!(ctrl.io.in.valid && !ctrl.io.in.ready))\n"); // @[VLdSt.scala 254:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(data_io_in_valid & ~data_io_in_ready))) begin
- $fatal; // @[VLdSt.scala 259:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(data_io_in_valid & ~data_io_in_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:259 assert(!(data.io.in.valid && !data.io.in.ready))\n"); // @[VLdSt.scala 259:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(data_io_out_valid & ~ctrl_io_out_valid))) begin
- $fatal; // @[VLdSt.scala 263:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(data_io_out_valid & ~ctrl_io_out_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:263 assert(!(data.io.out.valid && !ctrl.io.out.valid))\n"); // @[VLdSt.scala 263:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_addr[31]))) begin
- $fatal; // @[VLdSt.scala 272:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_addr[31]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:272 assert(!(ctrl.io.out.valid && ctrl.io.out.bits.addr(31)))\n"); // @[VLdSt.scala 272:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_adrx[31]))) begin
- $fatal; // @[VLdSt.scala 273:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(ctrl_io_out_valid & ctrl_io_out_bits_adrx[31]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:273 assert(!(ctrl.io.out.valid && ctrl.io.out.bits.adrx(31)))\n"); // @[VLdSt.scala 273:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
- $fatal; // @[VLdSt.scala 274:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(io_dbus_valid & io_dbus_addr[31]))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:274 assert(!(io.dbus.valid && io.dbus.addr(31)))\n"
- ); // @[VLdSt.scala 274:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(io_dbus_valid & io_dbus_adrx[31]))) begin
- $fatal; // @[VLdSt.scala 275:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(io_dbus_valid & io_dbus_adrx[31]))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLdSt.scala:275 assert(!(io.dbus.valid && io.dbus.adrx(31)))\n"
- ); // @[VLdSt.scala 275:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(wrega_io_in_valid & ~wrega_io_in_ready))) begin
- $fatal; // @[VLdSt.scala 292:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(wrega_io_in_valid & ~wrega_io_in_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:292 assert(!(wrega.io.in.valid && !wrega.io.in.ready))\n"); // @[VLdSt.scala 292:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(wregd_io_in_valid & ~wregd_io_in_ready))) begin
- $fatal; // @[VLdSt.scala 297:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(wregd_io_in_valid & ~wregd_io_in_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLdSt.scala:297 assert(!(wregd.io.in.valid && !wregd.io.in.ready))\n"); // @[VLdSt.scala 297:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VLdSt.scala 228:27]
- rdataEn <= 1'h0;
- end else begin
- rdataEn <= qoutEn & ctrl_io_in_bits_write;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VLdSt.scala 285:45]
- wdataEn <= 1'h0;
- end else begin
- wdataEn <= io_dbus_valid & io_dbus_ready & ~io_dbus_write;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- rdataEn = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- rdataSize = _RAND_1[7:0];
- _RAND_2 = {1{`RANDOM}};
- rdataAddr = _RAND_2[4:0];
- _RAND_3 = {1{`RANDOM}};
- rdataAshf = _RAND_3[4:0];
- _RAND_4 = {1{`RANDOM}};
- wdataEn = _RAND_4[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- rdataEn = 1'h0;
- end
- if (reset) begin
- wdataEn = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Fifo4e_4(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_tin_op,
- input [31:0] io_in_bits_0_bits_tin_addr,
- input [31:0] io_in_bits_0_bits_tin_offset,
- input [5:0] io_in_bits_0_bits_tin_vd_addr,
- input io_in_bits_0_bits_m,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_tin_op,
- input [31:0] io_in_bits_1_bits_tin_addr,
- input [31:0] io_in_bits_1_bits_tin_offset,
- input [5:0] io_in_bits_1_bits_tin_vd_addr,
- input io_in_bits_1_bits_m,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_tin_op,
- input [31:0] io_in_bits_2_bits_tin_addr,
- input [31:0] io_in_bits_2_bits_tin_offset,
- input [5:0] io_in_bits_2_bits_tin_vd_addr,
- input io_in_bits_2_bits_m,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_tin_op,
- input [31:0] io_in_bits_3_bits_tin_addr,
- input [31:0] io_in_bits_3_bits_tin_offset,
- input [5:0] io_in_bits_3_bits_tin_vd_addr,
- input io_in_bits_3_bits_m,
- input io_out_ready,
- output io_out_valid,
- output [6:0] io_out_bits_tin_op,
- output [31:0] io_out_bits_tin_addr,
- output [31:0] io_out_bits_tin_offset,
- output [5:0] io_out_bits_tin_vd_addr,
- output io_out_bits_m,
- output io_nempty
-);
-`ifdef RANDOMIZE_MEM_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
-`endif // RANDOMIZE_REG_INIT
- reg [6:0] mem_tin_op [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [31:0] mem_tin_addr [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [31:0] mem_tin_offset [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [5:0] mem_tin_vd_addr [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vd_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vd_addr_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vd_addr_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg mem_m [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_m_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [2:0] in0pos; // @[Fifo4e.scala 45:23]
- reg [2:0] in1pos; // @[Fifo4e.scala 46:23]
- reg [2:0] in2pos; // @[Fifo4e.scala 47:23]
- reg [2:0] in3pos; // @[Fifo4e.scala 48:23]
- reg [2:0] outpos; // @[Fifo4e.scala 49:23]
- reg [3:0] mcount; // @[Fifo4e.scala 50:23]
- reg nempty; // @[Fifo4e.scala 51:23]
- wire ivalid = io_in_valid & io_in_ready; // @[Fifo4e.scala 56:28]
- wire dec = io_out_valid & io_out_ready; // @[Fifo4e.scala 57:29]
- wire [3:0] iactive = {io_in_bits_3_valid,io_in_bits_2_valid,io_in_bits_1_valid,io_in_bits_0_valid}; // @[Cat.scala 31:58]
- wire [1:0] _icount_T = io_in_bits_0_valid + io_in_bits_1_valid; // @[Fifo4e.scala 62:36]
- wire [1:0] _GEN_1562 = {{1'd0}, io_in_bits_2_valid}; // @[Fifo4e.scala 62:59]
- wire [1:0] _icount_T_2 = _icount_T + _GEN_1562; // @[Fifo4e.scala 62:59]
- wire [1:0] _GEN_1563 = {{1'd0}, io_in_bits_3_valid}; // @[Fifo4e.scala 63:36]
- wire [2:0] icount = _icount_T_2 + _GEN_1563; // @[Fifo4e.scala 63:36]
- wire [3:0] in0pos_c = in0pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in0pos_d_T_2 = in0pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in0pos_d_T_3 = in0pos_c < 4'h8 ? in0pos_c : _in0pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in0pos_d = _in0pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] in1pos_c = in1pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in1pos_d_T_2 = in1pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in1pos_d_T_3 = in1pos_c < 4'h8 ? in1pos_c : _in1pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in1pos_d = _in1pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] in2pos_c = in2pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in2pos_d_T_2 = in2pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in2pos_d_T_3 = in2pos_c < 4'h8 ? in2pos_c : _in2pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in2pos_d = _in2pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] in3pos_c = in3pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in3pos_d_T_2 = in3pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in3pos_d_T_3 = in3pos_c < 4'h8 ? in3pos_c : _in3pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in3pos_d = _in3pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] outpos_c = outpos + 3'h1; // @[Fifo4e.scala 38:15]
- wire [3:0] _outpos_d_T_2 = outpos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _outpos_d_T_3 = outpos_c < 4'h8 ? outpos_c : _outpos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] outpos_d = _outpos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [2:0] inc = ivalid ? icount : 3'h0; // @[Library.scala 22:8]
- wire [3:0] _GEN_1564 = {{1'd0}, inc}; // @[Fifo4e.scala 82:27]
- wire [3:0] _nxtcount_T_1 = mcount + _GEN_1564; // @[Fifo4e.scala 82:27]
- wire [3:0] _GEN_1565 = {{3'd0}, dec}; // @[Fifo4e.scala 82:33]
- wire [3:0] nxtcount = _nxtcount_T_1 - _GEN_1565; // @[Fifo4e.scala 82:33]
- wire _in0_T_1 = iactive == 4'h8; // @[Fifo4.scala 31:27]
- wire _in0_T_3 = iactive[2:0] == 3'h4; // @[Fifo4.scala 32:27]
- wire _in0_T_5 = iactive[1:0] == 2'h2; // @[Fifo4.scala 33:27]
- wire [3:0] in0valid = {_in0_T_1,_in0_T_3,_in0_T_5,iactive[0]}; // @[Cat.scala 31:58]
- wire _in1_T_3 = iactive == 4'ha; // @[Fifo4.scala 37:27]
- wire _in1_T_4 = iactive == 4'hc | _in1_T_3; // @[Fifo4.scala 36:36]
- wire _in1_T_6 = iactive == 4'h9; // @[Fifo4.scala 38:27]
- wire _in1_T_7 = _in1_T_4 | _in1_T_6; // @[Fifo4.scala 37:36]
- wire _in1_T_11 = iactive[2:0] == 3'h5; // @[Fifo4.scala 40:27]
- wire _in1_T_12 = iactive[2:0] == 3'h6 | _in1_T_11; // @[Fifo4.scala 39:35]
- wire _in1_T_14 = iactive[1:0] == 2'h3; // @[Fifo4.scala 41:27]
- wire [3:0] in1valid = {_in1_T_7,_in1_T_12,_in1_T_14,1'h0}; // @[Cat.scala 31:58]
- wire _in2_T_3 = iactive == 4'hd; // @[Fifo4.scala 45:27]
- wire _in2_T_4 = iactive == 4'he | _in2_T_3; // @[Fifo4.scala 44:36]
- wire _in2_T_6 = iactive == 4'hb; // @[Fifo4.scala 46:27]
- wire _in2_T_7 = _in2_T_4 | _in2_T_6; // @[Fifo4.scala 45:36]
- wire [3:0] _GEN_1566 = {{1'd0}, iactive[2:0]}; // @[Fifo4.scala 47:27]
- wire _in2_T_11 = iactive[2:0] == 3'h7; // @[Fifo4.scala 48:27]
- wire _in2_T_12 = _GEN_1566 == 4'hf | _in2_T_11; // @[Fifo4.scala 47:36]
- wire [3:0] in2valid = {_in2_T_7,_in2_T_12,2'h0}; // @[Cat.scala 31:58]
- wire _in3_T_1 = iactive == 4'hf; // @[Fifo4.scala 51:27]
- wire [3:0] in3valid = {_in3_T_1,1'h0,2'h0}; // @[Cat.scala 31:58]
- wire _valid_T = in0pos == 3'h0; // @[Fifo4e.scala 92:28]
- wire _valid_T_3 = in1pos == 3'h0; // @[Fifo4e.scala 93:28]
- wire _valid_T_5 = in1pos == 3'h0 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_6 = in0pos == 3'h0 & in0valid[3] | _valid_T_5; // @[Fifo4e.scala 92:51]
- wire _valid_T_7 = in2pos == 3'h0; // @[Fifo4e.scala 94:28]
- wire _valid_T_9 = in2pos == 3'h0 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_10 = _valid_T_6 | _valid_T_9; // @[Fifo4e.scala 93:51]
- wire _valid_T_13 = in3pos == 3'h0 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_14 = _valid_T_10 | _valid_T_13; // @[Fifo4e.scala 94:51]
- wire _valid_T_20 = _valid_T_3 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_21 = _valid_T & in0valid[2] | _valid_T_20; // @[Fifo4e.scala 96:51]
- wire _valid_T_24 = _valid_T_7 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_25 = _valid_T_21 | _valid_T_24; // @[Fifo4e.scala 97:51]
- wire _valid_T_31 = _valid_T_3 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_32 = _valid_T & in0valid[1] | _valid_T_31; // @[Fifo4e.scala 99:51]
- wire _valid_T_35 = _valid_T & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid = {_valid_T_14,_valid_T_25,_valid_T_32,_valid_T_35}; // @[Cat.scala 31:58]
- wire _GEN_37 = valid[2] ? 1'h0 : valid[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_65 = valid[1] ? 1'h0 : valid[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_79 = valid[1] ? 1'h0 : _GEN_37; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_107 = valid[0] ? 1'h0 : valid[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_121 = valid[0] ? 1'h0 : _GEN_65; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_135 = valid[0] ? 1'h0 : _GEN_79; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_36 = in0pos == 3'h1; // @[Fifo4e.scala 92:28]
- wire _valid_T_39 = in1pos == 3'h1; // @[Fifo4e.scala 93:28]
- wire _valid_T_41 = in1pos == 3'h1 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_42 = in0pos == 3'h1 & in0valid[3] | _valid_T_41; // @[Fifo4e.scala 92:51]
- wire _valid_T_43 = in2pos == 3'h1; // @[Fifo4e.scala 94:28]
- wire _valid_T_45 = in2pos == 3'h1 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_46 = _valid_T_42 | _valid_T_45; // @[Fifo4e.scala 93:51]
- wire _valid_T_49 = in3pos == 3'h1 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_50 = _valid_T_46 | _valid_T_49; // @[Fifo4e.scala 94:51]
- wire _valid_T_56 = _valid_T_39 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_57 = _valid_T_36 & in0valid[2] | _valid_T_56; // @[Fifo4e.scala 96:51]
- wire _valid_T_60 = _valid_T_43 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_61 = _valid_T_57 | _valid_T_60; // @[Fifo4e.scala 97:51]
- wire _valid_T_67 = _valid_T_39 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_68 = _valid_T_36 & in0valid[1] | _valid_T_67; // @[Fifo4e.scala 99:51]
- wire _valid_T_71 = _valid_T_36 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_1 = {_valid_T_50,_valid_T_61,_valid_T_68,_valid_T_71}; // @[Cat.scala 31:58]
- wire _GEN_231 = valid_1[2] ? 1'h0 : valid_1[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_257 = valid_1[1] ? 1'h0 : valid_1[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_270 = valid_1[1] ? 1'h0 : _GEN_231; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_296 = valid_1[0] ? 1'h0 : valid_1[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_309 = valid_1[0] ? 1'h0 : _GEN_257; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_322 = valid_1[0] ? 1'h0 : _GEN_270; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_72 = in0pos == 3'h2; // @[Fifo4e.scala 92:28]
- wire _valid_T_75 = in1pos == 3'h2; // @[Fifo4e.scala 93:28]
- wire _valid_T_77 = in1pos == 3'h2 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_78 = in0pos == 3'h2 & in0valid[3] | _valid_T_77; // @[Fifo4e.scala 92:51]
- wire _valid_T_79 = in2pos == 3'h2; // @[Fifo4e.scala 94:28]
- wire _valid_T_81 = in2pos == 3'h2 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_82 = _valid_T_78 | _valid_T_81; // @[Fifo4e.scala 93:51]
- wire _valid_T_85 = in3pos == 3'h2 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_86 = _valid_T_82 | _valid_T_85; // @[Fifo4e.scala 94:51]
- wire _valid_T_92 = _valid_T_75 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_93 = _valid_T_72 & in0valid[2] | _valid_T_92; // @[Fifo4e.scala 96:51]
- wire _valid_T_96 = _valid_T_79 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_97 = _valid_T_93 | _valid_T_96; // @[Fifo4e.scala 97:51]
- wire _valid_T_103 = _valid_T_75 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_104 = _valid_T_72 & in0valid[1] | _valid_T_103; // @[Fifo4e.scala 99:51]
- wire _valid_T_107 = _valid_T_72 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_2 = {_valid_T_86,_valid_T_97,_valid_T_104,_valid_T_107}; // @[Cat.scala 31:58]
- wire _GEN_415 = valid_2[2] ? 1'h0 : valid_2[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_443 = valid_2[1] ? 1'h0 : valid_2[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_457 = valid_2[1] ? 1'h0 : _GEN_415; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_485 = valid_2[0] ? 1'h0 : valid_2[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_499 = valid_2[0] ? 1'h0 : _GEN_443; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_513 = valid_2[0] ? 1'h0 : _GEN_457; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_108 = in0pos == 3'h3; // @[Fifo4e.scala 92:28]
- wire _valid_T_111 = in1pos == 3'h3; // @[Fifo4e.scala 93:28]
- wire _valid_T_113 = in1pos == 3'h3 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_114 = in0pos == 3'h3 & in0valid[3] | _valid_T_113; // @[Fifo4e.scala 92:51]
- wire _valid_T_115 = in2pos == 3'h3; // @[Fifo4e.scala 94:28]
- wire _valid_T_117 = in2pos == 3'h3 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_118 = _valid_T_114 | _valid_T_117; // @[Fifo4e.scala 93:51]
- wire _valid_T_121 = in3pos == 3'h3 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_122 = _valid_T_118 | _valid_T_121; // @[Fifo4e.scala 94:51]
- wire _valid_T_128 = _valid_T_111 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_129 = _valid_T_108 & in0valid[2] | _valid_T_128; // @[Fifo4e.scala 96:51]
- wire _valid_T_132 = _valid_T_115 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_133 = _valid_T_129 | _valid_T_132; // @[Fifo4e.scala 97:51]
- wire _valid_T_139 = _valid_T_111 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_140 = _valid_T_108 & in0valid[1] | _valid_T_139; // @[Fifo4e.scala 99:51]
- wire _valid_T_143 = _valid_T_108 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_3 = {_valid_T_122,_valid_T_133,_valid_T_140,_valid_T_143}; // @[Cat.scala 31:58]
- wire _GEN_611 = valid_3[2] ? 1'h0 : valid_3[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_639 = valid_3[1] ? 1'h0 : valid_3[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_653 = valid_3[1] ? 1'h0 : _GEN_611; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_681 = valid_3[0] ? 1'h0 : valid_3[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_695 = valid_3[0] ? 1'h0 : _GEN_639; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_709 = valid_3[0] ? 1'h0 : _GEN_653; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_144 = in0pos == 3'h4; // @[Fifo4e.scala 92:28]
- wire _valid_T_147 = in1pos == 3'h4; // @[Fifo4e.scala 93:28]
- wire _valid_T_149 = in1pos == 3'h4 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_150 = in0pos == 3'h4 & in0valid[3] | _valid_T_149; // @[Fifo4e.scala 92:51]
- wire _valid_T_151 = in2pos == 3'h4; // @[Fifo4e.scala 94:28]
- wire _valid_T_153 = in2pos == 3'h4 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_154 = _valid_T_150 | _valid_T_153; // @[Fifo4e.scala 93:51]
- wire _valid_T_157 = in3pos == 3'h4 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_158 = _valid_T_154 | _valid_T_157; // @[Fifo4e.scala 94:51]
- wire _valid_T_164 = _valid_T_147 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_165 = _valid_T_144 & in0valid[2] | _valid_T_164; // @[Fifo4e.scala 96:51]
- wire _valid_T_168 = _valid_T_151 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_169 = _valid_T_165 | _valid_T_168; // @[Fifo4e.scala 97:51]
- wire _valid_T_175 = _valid_T_147 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_176 = _valid_T_144 & in0valid[1] | _valid_T_175; // @[Fifo4e.scala 99:51]
- wire _valid_T_179 = _valid_T_144 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_4 = {_valid_T_158,_valid_T_169,_valid_T_176,_valid_T_179}; // @[Cat.scala 31:58]
- wire _GEN_807 = valid_4[2] ? 1'h0 : valid_4[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_835 = valid_4[1] ? 1'h0 : valid_4[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_849 = valid_4[1] ? 1'h0 : _GEN_807; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_877 = valid_4[0] ? 1'h0 : valid_4[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_891 = valid_4[0] ? 1'h0 : _GEN_835; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_905 = valid_4[0] ? 1'h0 : _GEN_849; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_180 = in0pos == 3'h5; // @[Fifo4e.scala 92:28]
- wire _valid_T_183 = in1pos == 3'h5; // @[Fifo4e.scala 93:28]
- wire _valid_T_185 = in1pos == 3'h5 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_186 = in0pos == 3'h5 & in0valid[3] | _valid_T_185; // @[Fifo4e.scala 92:51]
- wire _valid_T_187 = in2pos == 3'h5; // @[Fifo4e.scala 94:28]
- wire _valid_T_189 = in2pos == 3'h5 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_190 = _valid_T_186 | _valid_T_189; // @[Fifo4e.scala 93:51]
- wire _valid_T_193 = in3pos == 3'h5 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_194 = _valid_T_190 | _valid_T_193; // @[Fifo4e.scala 94:51]
- wire _valid_T_200 = _valid_T_183 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_201 = _valid_T_180 & in0valid[2] | _valid_T_200; // @[Fifo4e.scala 96:51]
- wire _valid_T_204 = _valid_T_187 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_205 = _valid_T_201 | _valid_T_204; // @[Fifo4e.scala 97:51]
- wire _valid_T_211 = _valid_T_183 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_212 = _valid_T_180 & in0valid[1] | _valid_T_211; // @[Fifo4e.scala 99:51]
- wire _valid_T_215 = _valid_T_180 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_5 = {_valid_T_194,_valid_T_205,_valid_T_212,_valid_T_215}; // @[Cat.scala 31:58]
- wire _GEN_1003 = valid_5[2] ? 1'h0 : valid_5[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_1031 = valid_5[1] ? 1'h0 : valid_5[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1045 = valid_5[1] ? 1'h0 : _GEN_1003; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1073 = valid_5[0] ? 1'h0 : valid_5[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1087 = valid_5[0] ? 1'h0 : _GEN_1031; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1101 = valid_5[0] ? 1'h0 : _GEN_1045; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_216 = in0pos == 3'h6; // @[Fifo4e.scala 92:28]
- wire _valid_T_219 = in1pos == 3'h6; // @[Fifo4e.scala 93:28]
- wire _valid_T_221 = in1pos == 3'h6 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_222 = in0pos == 3'h6 & in0valid[3] | _valid_T_221; // @[Fifo4e.scala 92:51]
- wire _valid_T_223 = in2pos == 3'h6; // @[Fifo4e.scala 94:28]
- wire _valid_T_225 = in2pos == 3'h6 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_226 = _valid_T_222 | _valid_T_225; // @[Fifo4e.scala 93:51]
- wire _valid_T_229 = in3pos == 3'h6 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_230 = _valid_T_226 | _valid_T_229; // @[Fifo4e.scala 94:51]
- wire _valid_T_236 = _valid_T_219 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_237 = _valid_T_216 & in0valid[2] | _valid_T_236; // @[Fifo4e.scala 96:51]
- wire _valid_T_240 = _valid_T_223 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_241 = _valid_T_237 | _valid_T_240; // @[Fifo4e.scala 97:51]
- wire _valid_T_247 = _valid_T_219 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_248 = _valid_T_216 & in0valid[1] | _valid_T_247; // @[Fifo4e.scala 99:51]
- wire _valid_T_251 = _valid_T_216 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_6 = {_valid_T_230,_valid_T_241,_valid_T_248,_valid_T_251}; // @[Cat.scala 31:58]
- wire _GEN_1199 = valid_6[2] ? 1'h0 : valid_6[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_1227 = valid_6[1] ? 1'h0 : valid_6[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1241 = valid_6[1] ? 1'h0 : _GEN_1199; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1269 = valid_6[0] ? 1'h0 : valid_6[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1283 = valid_6[0] ? 1'h0 : _GEN_1227; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1297 = valid_6[0] ? 1'h0 : _GEN_1241; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_252 = in0pos == 3'h7; // @[Fifo4e.scala 92:28]
- wire _valid_T_255 = in1pos == 3'h7; // @[Fifo4e.scala 93:28]
- wire _valid_T_257 = in1pos == 3'h7 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_258 = in0pos == 3'h7 & in0valid[3] | _valid_T_257; // @[Fifo4e.scala 92:51]
- wire _valid_T_259 = in2pos == 3'h7; // @[Fifo4e.scala 94:28]
- wire _valid_T_261 = in2pos == 3'h7 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_262 = _valid_T_258 | _valid_T_261; // @[Fifo4e.scala 93:51]
- wire _valid_T_265 = in3pos == 3'h7 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_266 = _valid_T_262 | _valid_T_265; // @[Fifo4e.scala 94:51]
- wire _valid_T_272 = _valid_T_255 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_273 = _valid_T_252 & in0valid[2] | _valid_T_272; // @[Fifo4e.scala 96:51]
- wire _valid_T_276 = _valid_T_259 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_277 = _valid_T_273 | _valid_T_276; // @[Fifo4e.scala 97:51]
- wire _valid_T_283 = _valid_T_255 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_284 = _valid_T_252 & in0valid[1] | _valid_T_283; // @[Fifo4e.scala 99:51]
- wire _valid_T_287 = _valid_T_252 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_7 = {_valid_T_266,_valid_T_277,_valid_T_284,_valid_T_287}; // @[Cat.scala 31:58]
- wire _GEN_1395 = valid_7[2] ? 1'h0 : valid_7[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_1423 = valid_7[1] ? 1'h0 : valid_7[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1437 = valid_7[1] ? 1'h0 : _GEN_1395; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1465 = valid_7[0] ? 1'h0 : valid_7[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1479 = valid_7[0] ? 1'h0 : _GEN_1423; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1493 = valid_7[0] ? 1'h0 : _GEN_1437; // @[Fifo4e.scala 104:23 43:16]
- wire [3:0] _GEN_1567 = {{1'd0}, icount}; // @[Fifo4e.scala 132:33]
- wire [3:0] _io_in_ready_T_1 = 4'h8 - _GEN_1567; // @[Fifo4e.scala 132:33]
- assign mem_tin_op_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_op_io_out_bits_MPORT_data = mem_tin_op[mem_tin_op_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_op_io_entry_0_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_op_io_entry_1_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_op_io_entry_2_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_op_io_entry_3_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_op_io_entry_4_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_op_io_entry_5_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_op_io_entry_6_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_op_io_entry_7_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_MPORT_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_addr = 3'h0;
- assign mem_tin_op_MPORT_mask = 1'h1;
- assign mem_tin_op_MPORT_en = ivalid & valid[0];
- assign mem_tin_op_MPORT_1_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_1_addr = 3'h0;
- assign mem_tin_op_MPORT_1_mask = 1'h1;
- assign mem_tin_op_MPORT_1_en = ivalid & _GEN_107;
- assign mem_tin_op_MPORT_2_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_2_addr = 3'h0;
- assign mem_tin_op_MPORT_2_mask = 1'h1;
- assign mem_tin_op_MPORT_2_en = ivalid & _GEN_121;
- assign mem_tin_op_MPORT_3_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_3_addr = 3'h0;
- assign mem_tin_op_MPORT_3_mask = 1'h1;
- assign mem_tin_op_MPORT_3_en = ivalid & _GEN_135;
- assign mem_tin_op_MPORT_4_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_4_addr = 3'h1;
- assign mem_tin_op_MPORT_4_mask = 1'h1;
- assign mem_tin_op_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_op_MPORT_5_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_5_addr = 3'h1;
- assign mem_tin_op_MPORT_5_mask = 1'h1;
- assign mem_tin_op_MPORT_5_en = ivalid & _GEN_296;
- assign mem_tin_op_MPORT_6_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_6_addr = 3'h1;
- assign mem_tin_op_MPORT_6_mask = 1'h1;
- assign mem_tin_op_MPORT_6_en = ivalid & _GEN_309;
- assign mem_tin_op_MPORT_7_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_7_addr = 3'h1;
- assign mem_tin_op_MPORT_7_mask = 1'h1;
- assign mem_tin_op_MPORT_7_en = ivalid & _GEN_322;
- assign mem_tin_op_MPORT_8_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_8_addr = 3'h2;
- assign mem_tin_op_MPORT_8_mask = 1'h1;
- assign mem_tin_op_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_op_MPORT_9_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_9_addr = 3'h2;
- assign mem_tin_op_MPORT_9_mask = 1'h1;
- assign mem_tin_op_MPORT_9_en = ivalid & _GEN_485;
- assign mem_tin_op_MPORT_10_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_10_addr = 3'h2;
- assign mem_tin_op_MPORT_10_mask = 1'h1;
- assign mem_tin_op_MPORT_10_en = ivalid & _GEN_499;
- assign mem_tin_op_MPORT_11_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_11_addr = 3'h2;
- assign mem_tin_op_MPORT_11_mask = 1'h1;
- assign mem_tin_op_MPORT_11_en = ivalid & _GEN_513;
- assign mem_tin_op_MPORT_12_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_12_addr = 3'h3;
- assign mem_tin_op_MPORT_12_mask = 1'h1;
- assign mem_tin_op_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_op_MPORT_13_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_13_addr = 3'h3;
- assign mem_tin_op_MPORT_13_mask = 1'h1;
- assign mem_tin_op_MPORT_13_en = ivalid & _GEN_681;
- assign mem_tin_op_MPORT_14_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_14_addr = 3'h3;
- assign mem_tin_op_MPORT_14_mask = 1'h1;
- assign mem_tin_op_MPORT_14_en = ivalid & _GEN_695;
- assign mem_tin_op_MPORT_15_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_15_addr = 3'h3;
- assign mem_tin_op_MPORT_15_mask = 1'h1;
- assign mem_tin_op_MPORT_15_en = ivalid & _GEN_709;
- assign mem_tin_op_MPORT_16_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_16_addr = 3'h4;
- assign mem_tin_op_MPORT_16_mask = 1'h1;
- assign mem_tin_op_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_op_MPORT_17_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_17_addr = 3'h4;
- assign mem_tin_op_MPORT_17_mask = 1'h1;
- assign mem_tin_op_MPORT_17_en = ivalid & _GEN_877;
- assign mem_tin_op_MPORT_18_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_18_addr = 3'h4;
- assign mem_tin_op_MPORT_18_mask = 1'h1;
- assign mem_tin_op_MPORT_18_en = ivalid & _GEN_891;
- assign mem_tin_op_MPORT_19_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_19_addr = 3'h4;
- assign mem_tin_op_MPORT_19_mask = 1'h1;
- assign mem_tin_op_MPORT_19_en = ivalid & _GEN_905;
- assign mem_tin_op_MPORT_20_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_20_addr = 3'h5;
- assign mem_tin_op_MPORT_20_mask = 1'h1;
- assign mem_tin_op_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_op_MPORT_21_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_21_addr = 3'h5;
- assign mem_tin_op_MPORT_21_mask = 1'h1;
- assign mem_tin_op_MPORT_21_en = ivalid & _GEN_1073;
- assign mem_tin_op_MPORT_22_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_22_addr = 3'h5;
- assign mem_tin_op_MPORT_22_mask = 1'h1;
- assign mem_tin_op_MPORT_22_en = ivalid & _GEN_1087;
- assign mem_tin_op_MPORT_23_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_23_addr = 3'h5;
- assign mem_tin_op_MPORT_23_mask = 1'h1;
- assign mem_tin_op_MPORT_23_en = ivalid & _GEN_1101;
- assign mem_tin_op_MPORT_24_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_24_addr = 3'h6;
- assign mem_tin_op_MPORT_24_mask = 1'h1;
- assign mem_tin_op_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_op_MPORT_25_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_25_addr = 3'h6;
- assign mem_tin_op_MPORT_25_mask = 1'h1;
- assign mem_tin_op_MPORT_25_en = ivalid & _GEN_1269;
- assign mem_tin_op_MPORT_26_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_26_addr = 3'h6;
- assign mem_tin_op_MPORT_26_mask = 1'h1;
- assign mem_tin_op_MPORT_26_en = ivalid & _GEN_1283;
- assign mem_tin_op_MPORT_27_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_27_addr = 3'h6;
- assign mem_tin_op_MPORT_27_mask = 1'h1;
- assign mem_tin_op_MPORT_27_en = ivalid & _GEN_1297;
- assign mem_tin_op_MPORT_28_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_28_addr = 3'h7;
- assign mem_tin_op_MPORT_28_mask = 1'h1;
- assign mem_tin_op_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_op_MPORT_29_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_29_addr = 3'h7;
- assign mem_tin_op_MPORT_29_mask = 1'h1;
- assign mem_tin_op_MPORT_29_en = ivalid & _GEN_1465;
- assign mem_tin_op_MPORT_30_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_30_addr = 3'h7;
- assign mem_tin_op_MPORT_30_mask = 1'h1;
- assign mem_tin_op_MPORT_30_en = ivalid & _GEN_1479;
- assign mem_tin_op_MPORT_31_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_31_addr = 3'h7;
- assign mem_tin_op_MPORT_31_mask = 1'h1;
- assign mem_tin_op_MPORT_31_en = ivalid & _GEN_1493;
- assign mem_tin_addr_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_addr_io_out_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_addr_io_entry_0_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_addr_io_entry_1_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_addr_io_entry_2_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_addr_io_entry_3_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_addr_io_entry_4_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_addr_io_entry_5_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_addr_io_entry_6_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_addr_io_entry_7_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_MPORT_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_addr = 3'h0;
- assign mem_tin_addr_MPORT_mask = 1'h1;
- assign mem_tin_addr_MPORT_en = ivalid & valid[0];
- assign mem_tin_addr_MPORT_1_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_1_addr = 3'h0;
- assign mem_tin_addr_MPORT_1_mask = 1'h1;
- assign mem_tin_addr_MPORT_1_en = ivalid & _GEN_107;
- assign mem_tin_addr_MPORT_2_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_2_addr = 3'h0;
- assign mem_tin_addr_MPORT_2_mask = 1'h1;
- assign mem_tin_addr_MPORT_2_en = ivalid & _GEN_121;
- assign mem_tin_addr_MPORT_3_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_3_addr = 3'h0;
- assign mem_tin_addr_MPORT_3_mask = 1'h1;
- assign mem_tin_addr_MPORT_3_en = ivalid & _GEN_135;
- assign mem_tin_addr_MPORT_4_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_4_addr = 3'h1;
- assign mem_tin_addr_MPORT_4_mask = 1'h1;
- assign mem_tin_addr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_addr_MPORT_5_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_5_addr = 3'h1;
- assign mem_tin_addr_MPORT_5_mask = 1'h1;
- assign mem_tin_addr_MPORT_5_en = ivalid & _GEN_296;
- assign mem_tin_addr_MPORT_6_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_6_addr = 3'h1;
- assign mem_tin_addr_MPORT_6_mask = 1'h1;
- assign mem_tin_addr_MPORT_6_en = ivalid & _GEN_309;
- assign mem_tin_addr_MPORT_7_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_7_addr = 3'h1;
- assign mem_tin_addr_MPORT_7_mask = 1'h1;
- assign mem_tin_addr_MPORT_7_en = ivalid & _GEN_322;
- assign mem_tin_addr_MPORT_8_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_8_addr = 3'h2;
- assign mem_tin_addr_MPORT_8_mask = 1'h1;
- assign mem_tin_addr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_addr_MPORT_9_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_9_addr = 3'h2;
- assign mem_tin_addr_MPORT_9_mask = 1'h1;
- assign mem_tin_addr_MPORT_9_en = ivalid & _GEN_485;
- assign mem_tin_addr_MPORT_10_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_10_addr = 3'h2;
- assign mem_tin_addr_MPORT_10_mask = 1'h1;
- assign mem_tin_addr_MPORT_10_en = ivalid & _GEN_499;
- assign mem_tin_addr_MPORT_11_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_11_addr = 3'h2;
- assign mem_tin_addr_MPORT_11_mask = 1'h1;
- assign mem_tin_addr_MPORT_11_en = ivalid & _GEN_513;
- assign mem_tin_addr_MPORT_12_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_12_addr = 3'h3;
- assign mem_tin_addr_MPORT_12_mask = 1'h1;
- assign mem_tin_addr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_addr_MPORT_13_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_13_addr = 3'h3;
- assign mem_tin_addr_MPORT_13_mask = 1'h1;
- assign mem_tin_addr_MPORT_13_en = ivalid & _GEN_681;
- assign mem_tin_addr_MPORT_14_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_14_addr = 3'h3;
- assign mem_tin_addr_MPORT_14_mask = 1'h1;
- assign mem_tin_addr_MPORT_14_en = ivalid & _GEN_695;
- assign mem_tin_addr_MPORT_15_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_15_addr = 3'h3;
- assign mem_tin_addr_MPORT_15_mask = 1'h1;
- assign mem_tin_addr_MPORT_15_en = ivalid & _GEN_709;
- assign mem_tin_addr_MPORT_16_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_16_addr = 3'h4;
- assign mem_tin_addr_MPORT_16_mask = 1'h1;
- assign mem_tin_addr_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_addr_MPORT_17_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_17_addr = 3'h4;
- assign mem_tin_addr_MPORT_17_mask = 1'h1;
- assign mem_tin_addr_MPORT_17_en = ivalid & _GEN_877;
- assign mem_tin_addr_MPORT_18_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_18_addr = 3'h4;
- assign mem_tin_addr_MPORT_18_mask = 1'h1;
- assign mem_tin_addr_MPORT_18_en = ivalid & _GEN_891;
- assign mem_tin_addr_MPORT_19_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_19_addr = 3'h4;
- assign mem_tin_addr_MPORT_19_mask = 1'h1;
- assign mem_tin_addr_MPORT_19_en = ivalid & _GEN_905;
- assign mem_tin_addr_MPORT_20_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_20_addr = 3'h5;
- assign mem_tin_addr_MPORT_20_mask = 1'h1;
- assign mem_tin_addr_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_addr_MPORT_21_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_21_addr = 3'h5;
- assign mem_tin_addr_MPORT_21_mask = 1'h1;
- assign mem_tin_addr_MPORT_21_en = ivalid & _GEN_1073;
- assign mem_tin_addr_MPORT_22_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_22_addr = 3'h5;
- assign mem_tin_addr_MPORT_22_mask = 1'h1;
- assign mem_tin_addr_MPORT_22_en = ivalid & _GEN_1087;
- assign mem_tin_addr_MPORT_23_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_23_addr = 3'h5;
- assign mem_tin_addr_MPORT_23_mask = 1'h1;
- assign mem_tin_addr_MPORT_23_en = ivalid & _GEN_1101;
- assign mem_tin_addr_MPORT_24_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_24_addr = 3'h6;
- assign mem_tin_addr_MPORT_24_mask = 1'h1;
- assign mem_tin_addr_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_addr_MPORT_25_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_25_addr = 3'h6;
- assign mem_tin_addr_MPORT_25_mask = 1'h1;
- assign mem_tin_addr_MPORT_25_en = ivalid & _GEN_1269;
- assign mem_tin_addr_MPORT_26_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_26_addr = 3'h6;
- assign mem_tin_addr_MPORT_26_mask = 1'h1;
- assign mem_tin_addr_MPORT_26_en = ivalid & _GEN_1283;
- assign mem_tin_addr_MPORT_27_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_27_addr = 3'h6;
- assign mem_tin_addr_MPORT_27_mask = 1'h1;
- assign mem_tin_addr_MPORT_27_en = ivalid & _GEN_1297;
- assign mem_tin_addr_MPORT_28_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_28_addr = 3'h7;
- assign mem_tin_addr_MPORT_28_mask = 1'h1;
- assign mem_tin_addr_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_addr_MPORT_29_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_29_addr = 3'h7;
- assign mem_tin_addr_MPORT_29_mask = 1'h1;
- assign mem_tin_addr_MPORT_29_en = ivalid & _GEN_1465;
- assign mem_tin_addr_MPORT_30_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_30_addr = 3'h7;
- assign mem_tin_addr_MPORT_30_mask = 1'h1;
- assign mem_tin_addr_MPORT_30_en = ivalid & _GEN_1479;
- assign mem_tin_addr_MPORT_31_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_31_addr = 3'h7;
- assign mem_tin_addr_MPORT_31_mask = 1'h1;
- assign mem_tin_addr_MPORT_31_en = ivalid & _GEN_1493;
- assign mem_tin_offset_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_offset_io_out_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_offset_io_entry_0_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_offset_io_entry_1_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_offset_io_entry_2_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_offset_io_entry_3_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_offset_io_entry_4_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_offset_io_entry_5_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_offset_io_entry_6_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_offset_io_entry_7_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_MPORT_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_addr = 3'h0;
- assign mem_tin_offset_MPORT_mask = 1'h1;
- assign mem_tin_offset_MPORT_en = ivalid & valid[0];
- assign mem_tin_offset_MPORT_1_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_1_addr = 3'h0;
- assign mem_tin_offset_MPORT_1_mask = 1'h1;
- assign mem_tin_offset_MPORT_1_en = ivalid & _GEN_107;
- assign mem_tin_offset_MPORT_2_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_2_addr = 3'h0;
- assign mem_tin_offset_MPORT_2_mask = 1'h1;
- assign mem_tin_offset_MPORT_2_en = ivalid & _GEN_121;
- assign mem_tin_offset_MPORT_3_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_3_addr = 3'h0;
- assign mem_tin_offset_MPORT_3_mask = 1'h1;
- assign mem_tin_offset_MPORT_3_en = ivalid & _GEN_135;
- assign mem_tin_offset_MPORT_4_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_4_addr = 3'h1;
- assign mem_tin_offset_MPORT_4_mask = 1'h1;
- assign mem_tin_offset_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_offset_MPORT_5_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_5_addr = 3'h1;
- assign mem_tin_offset_MPORT_5_mask = 1'h1;
- assign mem_tin_offset_MPORT_5_en = ivalid & _GEN_296;
- assign mem_tin_offset_MPORT_6_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_6_addr = 3'h1;
- assign mem_tin_offset_MPORT_6_mask = 1'h1;
- assign mem_tin_offset_MPORT_6_en = ivalid & _GEN_309;
- assign mem_tin_offset_MPORT_7_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_7_addr = 3'h1;
- assign mem_tin_offset_MPORT_7_mask = 1'h1;
- assign mem_tin_offset_MPORT_7_en = ivalid & _GEN_322;
- assign mem_tin_offset_MPORT_8_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_8_addr = 3'h2;
- assign mem_tin_offset_MPORT_8_mask = 1'h1;
- assign mem_tin_offset_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_offset_MPORT_9_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_9_addr = 3'h2;
- assign mem_tin_offset_MPORT_9_mask = 1'h1;
- assign mem_tin_offset_MPORT_9_en = ivalid & _GEN_485;
- assign mem_tin_offset_MPORT_10_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_10_addr = 3'h2;
- assign mem_tin_offset_MPORT_10_mask = 1'h1;
- assign mem_tin_offset_MPORT_10_en = ivalid & _GEN_499;
- assign mem_tin_offset_MPORT_11_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_11_addr = 3'h2;
- assign mem_tin_offset_MPORT_11_mask = 1'h1;
- assign mem_tin_offset_MPORT_11_en = ivalid & _GEN_513;
- assign mem_tin_offset_MPORT_12_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_12_addr = 3'h3;
- assign mem_tin_offset_MPORT_12_mask = 1'h1;
- assign mem_tin_offset_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_offset_MPORT_13_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_13_addr = 3'h3;
- assign mem_tin_offset_MPORT_13_mask = 1'h1;
- assign mem_tin_offset_MPORT_13_en = ivalid & _GEN_681;
- assign mem_tin_offset_MPORT_14_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_14_addr = 3'h3;
- assign mem_tin_offset_MPORT_14_mask = 1'h1;
- assign mem_tin_offset_MPORT_14_en = ivalid & _GEN_695;
- assign mem_tin_offset_MPORT_15_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_15_addr = 3'h3;
- assign mem_tin_offset_MPORT_15_mask = 1'h1;
- assign mem_tin_offset_MPORT_15_en = ivalid & _GEN_709;
- assign mem_tin_offset_MPORT_16_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_16_addr = 3'h4;
- assign mem_tin_offset_MPORT_16_mask = 1'h1;
- assign mem_tin_offset_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_offset_MPORT_17_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_17_addr = 3'h4;
- assign mem_tin_offset_MPORT_17_mask = 1'h1;
- assign mem_tin_offset_MPORT_17_en = ivalid & _GEN_877;
- assign mem_tin_offset_MPORT_18_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_18_addr = 3'h4;
- assign mem_tin_offset_MPORT_18_mask = 1'h1;
- assign mem_tin_offset_MPORT_18_en = ivalid & _GEN_891;
- assign mem_tin_offset_MPORT_19_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_19_addr = 3'h4;
- assign mem_tin_offset_MPORT_19_mask = 1'h1;
- assign mem_tin_offset_MPORT_19_en = ivalid & _GEN_905;
- assign mem_tin_offset_MPORT_20_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_20_addr = 3'h5;
- assign mem_tin_offset_MPORT_20_mask = 1'h1;
- assign mem_tin_offset_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_offset_MPORT_21_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_21_addr = 3'h5;
- assign mem_tin_offset_MPORT_21_mask = 1'h1;
- assign mem_tin_offset_MPORT_21_en = ivalid & _GEN_1073;
- assign mem_tin_offset_MPORT_22_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_22_addr = 3'h5;
- assign mem_tin_offset_MPORT_22_mask = 1'h1;
- assign mem_tin_offset_MPORT_22_en = ivalid & _GEN_1087;
- assign mem_tin_offset_MPORT_23_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_23_addr = 3'h5;
- assign mem_tin_offset_MPORT_23_mask = 1'h1;
- assign mem_tin_offset_MPORT_23_en = ivalid & _GEN_1101;
- assign mem_tin_offset_MPORT_24_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_24_addr = 3'h6;
- assign mem_tin_offset_MPORT_24_mask = 1'h1;
- assign mem_tin_offset_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_offset_MPORT_25_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_25_addr = 3'h6;
- assign mem_tin_offset_MPORT_25_mask = 1'h1;
- assign mem_tin_offset_MPORT_25_en = ivalid & _GEN_1269;
- assign mem_tin_offset_MPORT_26_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_26_addr = 3'h6;
- assign mem_tin_offset_MPORT_26_mask = 1'h1;
- assign mem_tin_offset_MPORT_26_en = ivalid & _GEN_1283;
- assign mem_tin_offset_MPORT_27_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_27_addr = 3'h6;
- assign mem_tin_offset_MPORT_27_mask = 1'h1;
- assign mem_tin_offset_MPORT_27_en = ivalid & _GEN_1297;
- assign mem_tin_offset_MPORT_28_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_28_addr = 3'h7;
- assign mem_tin_offset_MPORT_28_mask = 1'h1;
- assign mem_tin_offset_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_offset_MPORT_29_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_29_addr = 3'h7;
- assign mem_tin_offset_MPORT_29_mask = 1'h1;
- assign mem_tin_offset_MPORT_29_en = ivalid & _GEN_1465;
- assign mem_tin_offset_MPORT_30_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_30_addr = 3'h7;
- assign mem_tin_offset_MPORT_30_mask = 1'h1;
- assign mem_tin_offset_MPORT_30_en = ivalid & _GEN_1479;
- assign mem_tin_offset_MPORT_31_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_31_addr = 3'h7;
- assign mem_tin_offset_MPORT_31_mask = 1'h1;
- assign mem_tin_offset_MPORT_31_en = ivalid & _GEN_1493;
- assign mem_tin_vd_addr_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vd_addr_io_out_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vd_addr_io_entry_0_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vd_addr_io_entry_1_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vd_addr_io_entry_2_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vd_addr_io_entry_3_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vd_addr_io_entry_4_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vd_addr_io_entry_5_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vd_addr_io_entry_6_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vd_addr_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vd_addr_io_entry_7_bits_MPORT_data = mem_tin_vd_addr[mem_tin_vd_addr_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vd_addr_MPORT_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_addr = 3'h0;
- assign mem_tin_vd_addr_MPORT_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_en = ivalid & valid[0];
- assign mem_tin_vd_addr_MPORT_1_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_1_addr = 3'h0;
- assign mem_tin_vd_addr_MPORT_1_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_1_en = ivalid & _GEN_107;
- assign mem_tin_vd_addr_MPORT_2_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_2_addr = 3'h0;
- assign mem_tin_vd_addr_MPORT_2_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_2_en = ivalid & _GEN_121;
- assign mem_tin_vd_addr_MPORT_3_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_3_addr = 3'h0;
- assign mem_tin_vd_addr_MPORT_3_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_3_en = ivalid & _GEN_135;
- assign mem_tin_vd_addr_MPORT_4_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_4_addr = 3'h1;
- assign mem_tin_vd_addr_MPORT_4_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vd_addr_MPORT_5_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_5_addr = 3'h1;
- assign mem_tin_vd_addr_MPORT_5_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_5_en = ivalid & _GEN_296;
- assign mem_tin_vd_addr_MPORT_6_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_6_addr = 3'h1;
- assign mem_tin_vd_addr_MPORT_6_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_6_en = ivalid & _GEN_309;
- assign mem_tin_vd_addr_MPORT_7_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_7_addr = 3'h1;
- assign mem_tin_vd_addr_MPORT_7_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_7_en = ivalid & _GEN_322;
- assign mem_tin_vd_addr_MPORT_8_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_8_addr = 3'h2;
- assign mem_tin_vd_addr_MPORT_8_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vd_addr_MPORT_9_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_9_addr = 3'h2;
- assign mem_tin_vd_addr_MPORT_9_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_9_en = ivalid & _GEN_485;
- assign mem_tin_vd_addr_MPORT_10_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_10_addr = 3'h2;
- assign mem_tin_vd_addr_MPORT_10_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_10_en = ivalid & _GEN_499;
- assign mem_tin_vd_addr_MPORT_11_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_11_addr = 3'h2;
- assign mem_tin_vd_addr_MPORT_11_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_11_en = ivalid & _GEN_513;
- assign mem_tin_vd_addr_MPORT_12_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_12_addr = 3'h3;
- assign mem_tin_vd_addr_MPORT_12_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vd_addr_MPORT_13_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_13_addr = 3'h3;
- assign mem_tin_vd_addr_MPORT_13_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_13_en = ivalid & _GEN_681;
- assign mem_tin_vd_addr_MPORT_14_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_14_addr = 3'h3;
- assign mem_tin_vd_addr_MPORT_14_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_14_en = ivalid & _GEN_695;
- assign mem_tin_vd_addr_MPORT_15_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_15_addr = 3'h3;
- assign mem_tin_vd_addr_MPORT_15_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_15_en = ivalid & _GEN_709;
- assign mem_tin_vd_addr_MPORT_16_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_16_addr = 3'h4;
- assign mem_tin_vd_addr_MPORT_16_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vd_addr_MPORT_17_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_17_addr = 3'h4;
- assign mem_tin_vd_addr_MPORT_17_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_17_en = ivalid & _GEN_877;
- assign mem_tin_vd_addr_MPORT_18_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_18_addr = 3'h4;
- assign mem_tin_vd_addr_MPORT_18_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_18_en = ivalid & _GEN_891;
- assign mem_tin_vd_addr_MPORT_19_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_19_addr = 3'h4;
- assign mem_tin_vd_addr_MPORT_19_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_19_en = ivalid & _GEN_905;
- assign mem_tin_vd_addr_MPORT_20_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_20_addr = 3'h5;
- assign mem_tin_vd_addr_MPORT_20_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vd_addr_MPORT_21_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_21_addr = 3'h5;
- assign mem_tin_vd_addr_MPORT_21_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_21_en = ivalid & _GEN_1073;
- assign mem_tin_vd_addr_MPORT_22_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_22_addr = 3'h5;
- assign mem_tin_vd_addr_MPORT_22_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_22_en = ivalid & _GEN_1087;
- assign mem_tin_vd_addr_MPORT_23_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_23_addr = 3'h5;
- assign mem_tin_vd_addr_MPORT_23_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_23_en = ivalid & _GEN_1101;
- assign mem_tin_vd_addr_MPORT_24_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_24_addr = 3'h6;
- assign mem_tin_vd_addr_MPORT_24_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vd_addr_MPORT_25_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_25_addr = 3'h6;
- assign mem_tin_vd_addr_MPORT_25_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_25_en = ivalid & _GEN_1269;
- assign mem_tin_vd_addr_MPORT_26_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_26_addr = 3'h6;
- assign mem_tin_vd_addr_MPORT_26_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_26_en = ivalid & _GEN_1283;
- assign mem_tin_vd_addr_MPORT_27_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_27_addr = 3'h6;
- assign mem_tin_vd_addr_MPORT_27_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_27_en = ivalid & _GEN_1297;
- assign mem_tin_vd_addr_MPORT_28_data = io_in_bits_0_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_28_addr = 3'h7;
- assign mem_tin_vd_addr_MPORT_28_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vd_addr_MPORT_29_data = io_in_bits_1_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_29_addr = 3'h7;
- assign mem_tin_vd_addr_MPORT_29_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_29_en = ivalid & _GEN_1465;
- assign mem_tin_vd_addr_MPORT_30_data = io_in_bits_2_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_30_addr = 3'h7;
- assign mem_tin_vd_addr_MPORT_30_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_30_en = ivalid & _GEN_1479;
- assign mem_tin_vd_addr_MPORT_31_data = io_in_bits_3_bits_tin_vd_addr;
- assign mem_tin_vd_addr_MPORT_31_addr = 3'h7;
- assign mem_tin_vd_addr_MPORT_31_mask = 1'h1;
- assign mem_tin_vd_addr_MPORT_31_en = ivalid & _GEN_1493;
- assign mem_m_io_out_bits_MPORT_en = 1'h1;
- assign mem_m_io_out_bits_MPORT_addr = outpos;
- assign mem_m_io_out_bits_MPORT_data = mem_m[mem_m_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_m_io_entry_0_bits_MPORT_data = mem_m[mem_m_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_m_io_entry_1_bits_MPORT_data = mem_m[mem_m_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_m_io_entry_2_bits_MPORT_data = mem_m[mem_m_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_m_io_entry_3_bits_MPORT_data = mem_m[mem_m_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_m_io_entry_4_bits_MPORT_data = mem_m[mem_m_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_m_io_entry_5_bits_MPORT_data = mem_m[mem_m_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_m_io_entry_6_bits_MPORT_data = mem_m[mem_m_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_m_io_entry_7_bits_MPORT_data = mem_m[mem_m_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_MPORT_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_addr = 3'h0;
- assign mem_m_MPORT_mask = 1'h1;
- assign mem_m_MPORT_en = ivalid & valid[0];
- assign mem_m_MPORT_1_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_1_addr = 3'h0;
- assign mem_m_MPORT_1_mask = 1'h1;
- assign mem_m_MPORT_1_en = ivalid & _GEN_107;
- assign mem_m_MPORT_2_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_2_addr = 3'h0;
- assign mem_m_MPORT_2_mask = 1'h1;
- assign mem_m_MPORT_2_en = ivalid & _GEN_121;
- assign mem_m_MPORT_3_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_3_addr = 3'h0;
- assign mem_m_MPORT_3_mask = 1'h1;
- assign mem_m_MPORT_3_en = ivalid & _GEN_135;
- assign mem_m_MPORT_4_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_4_addr = 3'h1;
- assign mem_m_MPORT_4_mask = 1'h1;
- assign mem_m_MPORT_4_en = ivalid & valid_1[0];
- assign mem_m_MPORT_5_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_5_addr = 3'h1;
- assign mem_m_MPORT_5_mask = 1'h1;
- assign mem_m_MPORT_5_en = ivalid & _GEN_296;
- assign mem_m_MPORT_6_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_6_addr = 3'h1;
- assign mem_m_MPORT_6_mask = 1'h1;
- assign mem_m_MPORT_6_en = ivalid & _GEN_309;
- assign mem_m_MPORT_7_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_7_addr = 3'h1;
- assign mem_m_MPORT_7_mask = 1'h1;
- assign mem_m_MPORT_7_en = ivalid & _GEN_322;
- assign mem_m_MPORT_8_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_8_addr = 3'h2;
- assign mem_m_MPORT_8_mask = 1'h1;
- assign mem_m_MPORT_8_en = ivalid & valid_2[0];
- assign mem_m_MPORT_9_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_9_addr = 3'h2;
- assign mem_m_MPORT_9_mask = 1'h1;
- assign mem_m_MPORT_9_en = ivalid & _GEN_485;
- assign mem_m_MPORT_10_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_10_addr = 3'h2;
- assign mem_m_MPORT_10_mask = 1'h1;
- assign mem_m_MPORT_10_en = ivalid & _GEN_499;
- assign mem_m_MPORT_11_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_11_addr = 3'h2;
- assign mem_m_MPORT_11_mask = 1'h1;
- assign mem_m_MPORT_11_en = ivalid & _GEN_513;
- assign mem_m_MPORT_12_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_12_addr = 3'h3;
- assign mem_m_MPORT_12_mask = 1'h1;
- assign mem_m_MPORT_12_en = ivalid & valid_3[0];
- assign mem_m_MPORT_13_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_13_addr = 3'h3;
- assign mem_m_MPORT_13_mask = 1'h1;
- assign mem_m_MPORT_13_en = ivalid & _GEN_681;
- assign mem_m_MPORT_14_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_14_addr = 3'h3;
- assign mem_m_MPORT_14_mask = 1'h1;
- assign mem_m_MPORT_14_en = ivalid & _GEN_695;
- assign mem_m_MPORT_15_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_15_addr = 3'h3;
- assign mem_m_MPORT_15_mask = 1'h1;
- assign mem_m_MPORT_15_en = ivalid & _GEN_709;
- assign mem_m_MPORT_16_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_16_addr = 3'h4;
- assign mem_m_MPORT_16_mask = 1'h1;
- assign mem_m_MPORT_16_en = ivalid & valid_4[0];
- assign mem_m_MPORT_17_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_17_addr = 3'h4;
- assign mem_m_MPORT_17_mask = 1'h1;
- assign mem_m_MPORT_17_en = ivalid & _GEN_877;
- assign mem_m_MPORT_18_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_18_addr = 3'h4;
- assign mem_m_MPORT_18_mask = 1'h1;
- assign mem_m_MPORT_18_en = ivalid & _GEN_891;
- assign mem_m_MPORT_19_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_19_addr = 3'h4;
- assign mem_m_MPORT_19_mask = 1'h1;
- assign mem_m_MPORT_19_en = ivalid & _GEN_905;
- assign mem_m_MPORT_20_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_20_addr = 3'h5;
- assign mem_m_MPORT_20_mask = 1'h1;
- assign mem_m_MPORT_20_en = ivalid & valid_5[0];
- assign mem_m_MPORT_21_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_21_addr = 3'h5;
- assign mem_m_MPORT_21_mask = 1'h1;
- assign mem_m_MPORT_21_en = ivalid & _GEN_1073;
- assign mem_m_MPORT_22_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_22_addr = 3'h5;
- assign mem_m_MPORT_22_mask = 1'h1;
- assign mem_m_MPORT_22_en = ivalid & _GEN_1087;
- assign mem_m_MPORT_23_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_23_addr = 3'h5;
- assign mem_m_MPORT_23_mask = 1'h1;
- assign mem_m_MPORT_23_en = ivalid & _GEN_1101;
- assign mem_m_MPORT_24_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_24_addr = 3'h6;
- assign mem_m_MPORT_24_mask = 1'h1;
- assign mem_m_MPORT_24_en = ivalid & valid_6[0];
- assign mem_m_MPORT_25_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_25_addr = 3'h6;
- assign mem_m_MPORT_25_mask = 1'h1;
- assign mem_m_MPORT_25_en = ivalid & _GEN_1269;
- assign mem_m_MPORT_26_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_26_addr = 3'h6;
- assign mem_m_MPORT_26_mask = 1'h1;
- assign mem_m_MPORT_26_en = ivalid & _GEN_1283;
- assign mem_m_MPORT_27_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_27_addr = 3'h6;
- assign mem_m_MPORT_27_mask = 1'h1;
- assign mem_m_MPORT_27_en = ivalid & _GEN_1297;
- assign mem_m_MPORT_28_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_28_addr = 3'h7;
- assign mem_m_MPORT_28_mask = 1'h1;
- assign mem_m_MPORT_28_en = ivalid & valid_7[0];
- assign mem_m_MPORT_29_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_29_addr = 3'h7;
- assign mem_m_MPORT_29_mask = 1'h1;
- assign mem_m_MPORT_29_en = ivalid & _GEN_1465;
- assign mem_m_MPORT_30_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_30_addr = 3'h7;
- assign mem_m_MPORT_30_mask = 1'h1;
- assign mem_m_MPORT_30_en = ivalid & _GEN_1479;
- assign mem_m_MPORT_31_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_31_addr = 3'h7;
- assign mem_m_MPORT_31_mask = 1'h1;
- assign mem_m_MPORT_31_en = ivalid & _GEN_1493;
- assign io_in_ready = mcount <= _io_in_ready_T_1; // @[Fifo4e.scala 132:25]
- assign io_out_valid = mcount != 4'h0; // @[Fifo4e.scala 134:26]
- assign io_out_bits_tin_op = mem_tin_op_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_addr = mem_tin_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_offset = mem_tin_offset_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vd_addr = mem_tin_vd_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_m = mem_m_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_nempty = nempty; // @[Fifo4e.scala 54:13]
- always @(posedge clock) begin
- if (mem_tin_op_MPORT_en & mem_tin_op_MPORT_mask) begin
- mem_tin_op[mem_tin_op_MPORT_addr] <= mem_tin_op_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_1_en & mem_tin_op_MPORT_1_mask) begin
- mem_tin_op[mem_tin_op_MPORT_1_addr] <= mem_tin_op_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_2_en & mem_tin_op_MPORT_2_mask) begin
- mem_tin_op[mem_tin_op_MPORT_2_addr] <= mem_tin_op_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_3_en & mem_tin_op_MPORT_3_mask) begin
- mem_tin_op[mem_tin_op_MPORT_3_addr] <= mem_tin_op_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_4_en & mem_tin_op_MPORT_4_mask) begin
- mem_tin_op[mem_tin_op_MPORT_4_addr] <= mem_tin_op_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_5_en & mem_tin_op_MPORT_5_mask) begin
- mem_tin_op[mem_tin_op_MPORT_5_addr] <= mem_tin_op_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_6_en & mem_tin_op_MPORT_6_mask) begin
- mem_tin_op[mem_tin_op_MPORT_6_addr] <= mem_tin_op_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_7_en & mem_tin_op_MPORT_7_mask) begin
- mem_tin_op[mem_tin_op_MPORT_7_addr] <= mem_tin_op_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_8_en & mem_tin_op_MPORT_8_mask) begin
- mem_tin_op[mem_tin_op_MPORT_8_addr] <= mem_tin_op_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_9_en & mem_tin_op_MPORT_9_mask) begin
- mem_tin_op[mem_tin_op_MPORT_9_addr] <= mem_tin_op_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_10_en & mem_tin_op_MPORT_10_mask) begin
- mem_tin_op[mem_tin_op_MPORT_10_addr] <= mem_tin_op_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_11_en & mem_tin_op_MPORT_11_mask) begin
- mem_tin_op[mem_tin_op_MPORT_11_addr] <= mem_tin_op_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_12_en & mem_tin_op_MPORT_12_mask) begin
- mem_tin_op[mem_tin_op_MPORT_12_addr] <= mem_tin_op_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_13_en & mem_tin_op_MPORT_13_mask) begin
- mem_tin_op[mem_tin_op_MPORT_13_addr] <= mem_tin_op_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_14_en & mem_tin_op_MPORT_14_mask) begin
- mem_tin_op[mem_tin_op_MPORT_14_addr] <= mem_tin_op_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_15_en & mem_tin_op_MPORT_15_mask) begin
- mem_tin_op[mem_tin_op_MPORT_15_addr] <= mem_tin_op_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_16_en & mem_tin_op_MPORT_16_mask) begin
- mem_tin_op[mem_tin_op_MPORT_16_addr] <= mem_tin_op_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_17_en & mem_tin_op_MPORT_17_mask) begin
- mem_tin_op[mem_tin_op_MPORT_17_addr] <= mem_tin_op_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_18_en & mem_tin_op_MPORT_18_mask) begin
- mem_tin_op[mem_tin_op_MPORT_18_addr] <= mem_tin_op_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_19_en & mem_tin_op_MPORT_19_mask) begin
- mem_tin_op[mem_tin_op_MPORT_19_addr] <= mem_tin_op_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_20_en & mem_tin_op_MPORT_20_mask) begin
- mem_tin_op[mem_tin_op_MPORT_20_addr] <= mem_tin_op_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_21_en & mem_tin_op_MPORT_21_mask) begin
- mem_tin_op[mem_tin_op_MPORT_21_addr] <= mem_tin_op_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_22_en & mem_tin_op_MPORT_22_mask) begin
- mem_tin_op[mem_tin_op_MPORT_22_addr] <= mem_tin_op_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_23_en & mem_tin_op_MPORT_23_mask) begin
- mem_tin_op[mem_tin_op_MPORT_23_addr] <= mem_tin_op_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_24_en & mem_tin_op_MPORT_24_mask) begin
- mem_tin_op[mem_tin_op_MPORT_24_addr] <= mem_tin_op_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_25_en & mem_tin_op_MPORT_25_mask) begin
- mem_tin_op[mem_tin_op_MPORT_25_addr] <= mem_tin_op_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_26_en & mem_tin_op_MPORT_26_mask) begin
- mem_tin_op[mem_tin_op_MPORT_26_addr] <= mem_tin_op_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_27_en & mem_tin_op_MPORT_27_mask) begin
- mem_tin_op[mem_tin_op_MPORT_27_addr] <= mem_tin_op_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_28_en & mem_tin_op_MPORT_28_mask) begin
- mem_tin_op[mem_tin_op_MPORT_28_addr] <= mem_tin_op_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_29_en & mem_tin_op_MPORT_29_mask) begin
- mem_tin_op[mem_tin_op_MPORT_29_addr] <= mem_tin_op_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_30_en & mem_tin_op_MPORT_30_mask) begin
- mem_tin_op[mem_tin_op_MPORT_30_addr] <= mem_tin_op_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_31_en & mem_tin_op_MPORT_31_mask) begin
- mem_tin_op[mem_tin_op_MPORT_31_addr] <= mem_tin_op_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_en & mem_tin_addr_MPORT_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_addr] <= mem_tin_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_1_en & mem_tin_addr_MPORT_1_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_1_addr] <= mem_tin_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_2_en & mem_tin_addr_MPORT_2_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_2_addr] <= mem_tin_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_3_en & mem_tin_addr_MPORT_3_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_3_addr] <= mem_tin_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_4_en & mem_tin_addr_MPORT_4_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_4_addr] <= mem_tin_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_5_en & mem_tin_addr_MPORT_5_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_5_addr] <= mem_tin_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_6_en & mem_tin_addr_MPORT_6_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_6_addr] <= mem_tin_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_7_en & mem_tin_addr_MPORT_7_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_7_addr] <= mem_tin_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_8_en & mem_tin_addr_MPORT_8_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_8_addr] <= mem_tin_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_9_en & mem_tin_addr_MPORT_9_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_9_addr] <= mem_tin_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_10_en & mem_tin_addr_MPORT_10_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_10_addr] <= mem_tin_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_11_en & mem_tin_addr_MPORT_11_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_11_addr] <= mem_tin_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_12_en & mem_tin_addr_MPORT_12_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_12_addr] <= mem_tin_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_13_en & mem_tin_addr_MPORT_13_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_13_addr] <= mem_tin_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_14_en & mem_tin_addr_MPORT_14_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_14_addr] <= mem_tin_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_15_en & mem_tin_addr_MPORT_15_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_15_addr] <= mem_tin_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_16_en & mem_tin_addr_MPORT_16_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_16_addr] <= mem_tin_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_17_en & mem_tin_addr_MPORT_17_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_17_addr] <= mem_tin_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_18_en & mem_tin_addr_MPORT_18_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_18_addr] <= mem_tin_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_19_en & mem_tin_addr_MPORT_19_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_19_addr] <= mem_tin_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_20_en & mem_tin_addr_MPORT_20_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_20_addr] <= mem_tin_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_21_en & mem_tin_addr_MPORT_21_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_21_addr] <= mem_tin_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_22_en & mem_tin_addr_MPORT_22_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_22_addr] <= mem_tin_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_23_en & mem_tin_addr_MPORT_23_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_23_addr] <= mem_tin_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_24_en & mem_tin_addr_MPORT_24_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_24_addr] <= mem_tin_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_25_en & mem_tin_addr_MPORT_25_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_25_addr] <= mem_tin_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_26_en & mem_tin_addr_MPORT_26_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_26_addr] <= mem_tin_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_27_en & mem_tin_addr_MPORT_27_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_27_addr] <= mem_tin_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_28_en & mem_tin_addr_MPORT_28_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_28_addr] <= mem_tin_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_29_en & mem_tin_addr_MPORT_29_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_29_addr] <= mem_tin_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_30_en & mem_tin_addr_MPORT_30_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_30_addr] <= mem_tin_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_31_en & mem_tin_addr_MPORT_31_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_31_addr] <= mem_tin_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_en & mem_tin_offset_MPORT_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_addr] <= mem_tin_offset_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_1_en & mem_tin_offset_MPORT_1_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_1_addr] <= mem_tin_offset_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_2_en & mem_tin_offset_MPORT_2_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_2_addr] <= mem_tin_offset_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_3_en & mem_tin_offset_MPORT_3_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_3_addr] <= mem_tin_offset_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_4_en & mem_tin_offset_MPORT_4_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_4_addr] <= mem_tin_offset_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_5_en & mem_tin_offset_MPORT_5_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_5_addr] <= mem_tin_offset_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_6_en & mem_tin_offset_MPORT_6_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_6_addr] <= mem_tin_offset_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_7_en & mem_tin_offset_MPORT_7_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_7_addr] <= mem_tin_offset_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_8_en & mem_tin_offset_MPORT_8_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_8_addr] <= mem_tin_offset_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_9_en & mem_tin_offset_MPORT_9_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_9_addr] <= mem_tin_offset_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_10_en & mem_tin_offset_MPORT_10_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_10_addr] <= mem_tin_offset_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_11_en & mem_tin_offset_MPORT_11_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_11_addr] <= mem_tin_offset_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_12_en & mem_tin_offset_MPORT_12_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_12_addr] <= mem_tin_offset_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_13_en & mem_tin_offset_MPORT_13_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_13_addr] <= mem_tin_offset_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_14_en & mem_tin_offset_MPORT_14_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_14_addr] <= mem_tin_offset_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_15_en & mem_tin_offset_MPORT_15_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_15_addr] <= mem_tin_offset_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_16_en & mem_tin_offset_MPORT_16_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_16_addr] <= mem_tin_offset_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_17_en & mem_tin_offset_MPORT_17_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_17_addr] <= mem_tin_offset_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_18_en & mem_tin_offset_MPORT_18_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_18_addr] <= mem_tin_offset_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_19_en & mem_tin_offset_MPORT_19_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_19_addr] <= mem_tin_offset_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_20_en & mem_tin_offset_MPORT_20_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_20_addr] <= mem_tin_offset_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_21_en & mem_tin_offset_MPORT_21_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_21_addr] <= mem_tin_offset_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_22_en & mem_tin_offset_MPORT_22_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_22_addr] <= mem_tin_offset_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_23_en & mem_tin_offset_MPORT_23_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_23_addr] <= mem_tin_offset_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_24_en & mem_tin_offset_MPORT_24_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_24_addr] <= mem_tin_offset_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_25_en & mem_tin_offset_MPORT_25_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_25_addr] <= mem_tin_offset_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_26_en & mem_tin_offset_MPORT_26_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_26_addr] <= mem_tin_offset_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_27_en & mem_tin_offset_MPORT_27_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_27_addr] <= mem_tin_offset_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_28_en & mem_tin_offset_MPORT_28_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_28_addr] <= mem_tin_offset_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_29_en & mem_tin_offset_MPORT_29_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_29_addr] <= mem_tin_offset_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_30_en & mem_tin_offset_MPORT_30_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_30_addr] <= mem_tin_offset_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_31_en & mem_tin_offset_MPORT_31_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_31_addr] <= mem_tin_offset_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_en & mem_tin_vd_addr_MPORT_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_addr] <= mem_tin_vd_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_1_en & mem_tin_vd_addr_MPORT_1_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_1_addr] <= mem_tin_vd_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_2_en & mem_tin_vd_addr_MPORT_2_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_2_addr] <= mem_tin_vd_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_3_en & mem_tin_vd_addr_MPORT_3_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_3_addr] <= mem_tin_vd_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_4_en & mem_tin_vd_addr_MPORT_4_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_4_addr] <= mem_tin_vd_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_5_en & mem_tin_vd_addr_MPORT_5_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_5_addr] <= mem_tin_vd_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_6_en & mem_tin_vd_addr_MPORT_6_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_6_addr] <= mem_tin_vd_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_7_en & mem_tin_vd_addr_MPORT_7_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_7_addr] <= mem_tin_vd_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_8_en & mem_tin_vd_addr_MPORT_8_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_8_addr] <= mem_tin_vd_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_9_en & mem_tin_vd_addr_MPORT_9_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_9_addr] <= mem_tin_vd_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_10_en & mem_tin_vd_addr_MPORT_10_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_10_addr] <= mem_tin_vd_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_11_en & mem_tin_vd_addr_MPORT_11_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_11_addr] <= mem_tin_vd_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_12_en & mem_tin_vd_addr_MPORT_12_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_12_addr] <= mem_tin_vd_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_13_en & mem_tin_vd_addr_MPORT_13_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_13_addr] <= mem_tin_vd_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_14_en & mem_tin_vd_addr_MPORT_14_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_14_addr] <= mem_tin_vd_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_15_en & mem_tin_vd_addr_MPORT_15_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_15_addr] <= mem_tin_vd_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_16_en & mem_tin_vd_addr_MPORT_16_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_16_addr] <= mem_tin_vd_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_17_en & mem_tin_vd_addr_MPORT_17_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_17_addr] <= mem_tin_vd_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_18_en & mem_tin_vd_addr_MPORT_18_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_18_addr] <= mem_tin_vd_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_19_en & mem_tin_vd_addr_MPORT_19_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_19_addr] <= mem_tin_vd_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_20_en & mem_tin_vd_addr_MPORT_20_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_20_addr] <= mem_tin_vd_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_21_en & mem_tin_vd_addr_MPORT_21_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_21_addr] <= mem_tin_vd_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_22_en & mem_tin_vd_addr_MPORT_22_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_22_addr] <= mem_tin_vd_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_23_en & mem_tin_vd_addr_MPORT_23_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_23_addr] <= mem_tin_vd_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_24_en & mem_tin_vd_addr_MPORT_24_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_24_addr] <= mem_tin_vd_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_25_en & mem_tin_vd_addr_MPORT_25_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_25_addr] <= mem_tin_vd_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_26_en & mem_tin_vd_addr_MPORT_26_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_26_addr] <= mem_tin_vd_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_27_en & mem_tin_vd_addr_MPORT_27_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_27_addr] <= mem_tin_vd_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_28_en & mem_tin_vd_addr_MPORT_28_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_28_addr] <= mem_tin_vd_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_29_en & mem_tin_vd_addr_MPORT_29_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_29_addr] <= mem_tin_vd_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_30_en & mem_tin_vd_addr_MPORT_30_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_30_addr] <= mem_tin_vd_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vd_addr_MPORT_31_en & mem_tin_vd_addr_MPORT_31_mask) begin
- mem_tin_vd_addr[mem_tin_vd_addr_MPORT_31_addr] <= mem_tin_vd_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_en & mem_m_MPORT_mask) begin
- mem_m[mem_m_MPORT_addr] <= mem_m_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_1_en & mem_m_MPORT_1_mask) begin
- mem_m[mem_m_MPORT_1_addr] <= mem_m_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_2_en & mem_m_MPORT_2_mask) begin
- mem_m[mem_m_MPORT_2_addr] <= mem_m_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_3_en & mem_m_MPORT_3_mask) begin
- mem_m[mem_m_MPORT_3_addr] <= mem_m_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_4_en & mem_m_MPORT_4_mask) begin
- mem_m[mem_m_MPORT_4_addr] <= mem_m_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_5_en & mem_m_MPORT_5_mask) begin
- mem_m[mem_m_MPORT_5_addr] <= mem_m_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_6_en & mem_m_MPORT_6_mask) begin
- mem_m[mem_m_MPORT_6_addr] <= mem_m_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_7_en & mem_m_MPORT_7_mask) begin
- mem_m[mem_m_MPORT_7_addr] <= mem_m_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_8_en & mem_m_MPORT_8_mask) begin
- mem_m[mem_m_MPORT_8_addr] <= mem_m_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_9_en & mem_m_MPORT_9_mask) begin
- mem_m[mem_m_MPORT_9_addr] <= mem_m_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_10_en & mem_m_MPORT_10_mask) begin
- mem_m[mem_m_MPORT_10_addr] <= mem_m_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_11_en & mem_m_MPORT_11_mask) begin
- mem_m[mem_m_MPORT_11_addr] <= mem_m_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_12_en & mem_m_MPORT_12_mask) begin
- mem_m[mem_m_MPORT_12_addr] <= mem_m_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_13_en & mem_m_MPORT_13_mask) begin
- mem_m[mem_m_MPORT_13_addr] <= mem_m_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_14_en & mem_m_MPORT_14_mask) begin
- mem_m[mem_m_MPORT_14_addr] <= mem_m_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_15_en & mem_m_MPORT_15_mask) begin
- mem_m[mem_m_MPORT_15_addr] <= mem_m_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_16_en & mem_m_MPORT_16_mask) begin
- mem_m[mem_m_MPORT_16_addr] <= mem_m_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_17_en & mem_m_MPORT_17_mask) begin
- mem_m[mem_m_MPORT_17_addr] <= mem_m_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_18_en & mem_m_MPORT_18_mask) begin
- mem_m[mem_m_MPORT_18_addr] <= mem_m_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_19_en & mem_m_MPORT_19_mask) begin
- mem_m[mem_m_MPORT_19_addr] <= mem_m_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_20_en & mem_m_MPORT_20_mask) begin
- mem_m[mem_m_MPORT_20_addr] <= mem_m_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_21_en & mem_m_MPORT_21_mask) begin
- mem_m[mem_m_MPORT_21_addr] <= mem_m_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_22_en & mem_m_MPORT_22_mask) begin
- mem_m[mem_m_MPORT_22_addr] <= mem_m_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_23_en & mem_m_MPORT_23_mask) begin
- mem_m[mem_m_MPORT_23_addr] <= mem_m_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_24_en & mem_m_MPORT_24_mask) begin
- mem_m[mem_m_MPORT_24_addr] <= mem_m_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_25_en & mem_m_MPORT_25_mask) begin
- mem_m[mem_m_MPORT_25_addr] <= mem_m_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_26_en & mem_m_MPORT_26_mask) begin
- mem_m[mem_m_MPORT_26_addr] <= mem_m_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_27_en & mem_m_MPORT_27_mask) begin
- mem_m[mem_m_MPORT_27_addr] <= mem_m_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_28_en & mem_m_MPORT_28_mask) begin
- mem_m[mem_m_MPORT_28_addr] <= mem_m_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_29_en & mem_m_MPORT_29_mask) begin
- mem_m[mem_m_MPORT_29_addr] <= mem_m_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_30_en & mem_m_MPORT_30_mask) begin
- mem_m[mem_m_MPORT_30_addr] <= mem_m_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_31_en & mem_m_MPORT_31_mask) begin
- mem_m[mem_m_MPORT_31_addr] <= mem_m_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(mcount <= 4'h8)) begin
- $fatal; // @[Fifo4e.scala 137:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(mcount <= 4'h8)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Fifo4e.scala:137 assert(mcount <= n.U)\n"); // @[Fifo4e.scala 137:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in0pos <= 3'h0; // @[Fifo4e.scala 68:12]
- end else if (ivalid) begin // @[Fifo4e.scala 45:23]
- in0pos <= in0pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in1pos <= 3'h1; // @[Fifo4e.scala 69:12]
- end else if (ivalid) begin // @[Fifo4e.scala 46:23]
- in1pos <= in1pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in2pos <= 3'h2; // @[Fifo4e.scala 70:12]
- end else if (ivalid) begin // @[Fifo4e.scala 47:23]
- in2pos <= in2pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in3pos <= 3'h3; // @[Fifo4e.scala 71:12]
- end else if (ivalid) begin // @[Fifo4e.scala 48:23]
- in3pos <= in3pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 74:17]
- outpos <= 3'h0; // @[Fifo4e.scala 75:12]
- end else if (dec) begin // @[Fifo4e.scala 49:23]
- outpos <= outpos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 81:27]
- mcount <= 4'h0; // @[Fifo4e.scala 83:12]
- end else if (ivalid | dec) begin // @[Fifo4e.scala 50:23]
- mcount <= nxtcount;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 81:27]
- nempty <= 1'h0; // @[Fifo4e.scala 84:12]
- end else if (ivalid | dec) begin // @[Fifo4e.scala 51:23]
- nempty <= nxtcount != 4'h0;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_MEM_INIT
- _RAND_0 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_op[initvar] = _RAND_0[6:0];
- _RAND_1 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_addr[initvar] = _RAND_1[31:0];
- _RAND_2 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_offset[initvar] = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vd_addr[initvar] = _RAND_3[5:0];
- _RAND_4 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_m[initvar] = _RAND_4[0:0];
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- _RAND_5 = {1{`RANDOM}};
- in0pos = _RAND_5[2:0];
- _RAND_6 = {1{`RANDOM}};
- in1pos = _RAND_6[2:0];
- _RAND_7 = {1{`RANDOM}};
- in2pos = _RAND_7[2:0];
- _RAND_8 = {1{`RANDOM}};
- in3pos = _RAND_8[2:0];
- _RAND_9 = {1{`RANDOM}};
- outpos = _RAND_9[2:0];
- _RAND_10 = {1{`RANDOM}};
- mcount = _RAND_10[3:0];
- _RAND_11 = {1{`RANDOM}};
- nempty = _RAND_11[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- in0pos = 3'h0;
- end
- if (reset) begin
- in1pos = 3'h1;
- end
- if (reset) begin
- in2pos = 3'h2;
- end
- if (reset) begin
- in3pos = 3'h3;
- end
- if (reset) begin
- outpos = 3'h0;
- end
- if (reset) begin
- mcount = 4'h0;
- end
- if (reset) begin
- nempty = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VCmdq_4(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_op,
- input [2:0] io_in_bits_0_bits_f2,
- input [2:0] io_in_bits_0_bits_sz,
- input io_in_bits_0_bits_m,
- input io_in_bits_0_bits_vd_valid,
- input [5:0] io_in_bits_0_bits_vd_addr,
- input io_in_bits_0_bits_vs_valid,
- input [31:0] io_in_bits_0_bits_sv_addr,
- input [31:0] io_in_bits_0_bits_sv_data,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_op,
- input [2:0] io_in_bits_1_bits_f2,
- input [2:0] io_in_bits_1_bits_sz,
- input io_in_bits_1_bits_m,
- input io_in_bits_1_bits_vd_valid,
- input [5:0] io_in_bits_1_bits_vd_addr,
- input io_in_bits_1_bits_vs_valid,
- input [31:0] io_in_bits_1_bits_sv_addr,
- input [31:0] io_in_bits_1_bits_sv_data,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_op,
- input [2:0] io_in_bits_2_bits_f2,
- input [2:0] io_in_bits_2_bits_sz,
- input io_in_bits_2_bits_m,
- input io_in_bits_2_bits_vd_valid,
- input [5:0] io_in_bits_2_bits_vd_addr,
- input io_in_bits_2_bits_vs_valid,
- input [31:0] io_in_bits_2_bits_sv_addr,
- input [31:0] io_in_bits_2_bits_sv_data,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_op,
- input [2:0] io_in_bits_3_bits_f2,
- input [2:0] io_in_bits_3_bits_sz,
- input io_in_bits_3_bits_m,
- input io_in_bits_3_bits_vd_valid,
- input [5:0] io_in_bits_3_bits_vd_addr,
- input io_in_bits_3_bits_vs_valid,
- input [31:0] io_in_bits_3_bits_sv_addr,
- input [31:0] io_in_bits_3_bits_sv_data,
- input io_out_ready,
- output io_out_valid,
- output [31:0] io_out_bits_addr,
- output [5:0] io_out_bits_vd_addr,
- output io_nempty
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
-`endif // RANDOMIZE_REG_INIT
- wire f_clock; // @[Fifo4e.scala 24:11]
- wire f_reset; // @[Fifo4e.scala 24:11]
- wire f_io_in_ready; // @[Fifo4e.scala 24:11]
- wire f_io_in_valid; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_0_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_0_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_0_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_1_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_1_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_1_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_2_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_2_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_2_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_3_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_3_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_3_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_out_ready; // @[Fifo4e.scala 24:11]
- wire f_io_out_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_out_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_out_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_out_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_vd_addr; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_nempty; // @[Fifo4e.scala 24:11]
- reg valid; // @[VCmdq.scala 51:22]
- reg [6:0] value_tin_op; // @[VCmdq.scala 53:18]
- reg [31:0] value_tin_addr; // @[VCmdq.scala 53:18]
- reg [31:0] value_tin_offset; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_vd_addr; // @[VCmdq.scala 53:18]
- reg value_m; // @[VCmdq.scala 53:18]
- reg [4:0] step; // @[VCmdq.scala 58:21]
- wire [4:0] addrAlign = value_tin_addr[4:0]; // @[VLd.scala 103:28]
- wire [4:0] offsAlign = value_tin_offset[4:0]; // @[VLd.scala 104:30]
- wire _T_2 = ~reset; // @[VLd.scala 105:11]
- wire _T_8 = ~valid; // @[VLd.scala 107:12]
- wire _outlast_T = ~value_m; // @[VLd.scala 112:19]
- wire last = _outlast_T | step == 5'h3; // @[VLd.scala 114:19]
- wire [5:0] tin_vd_addr = value_tin_vd_addr + 6'h1; // @[VLd.scala 118:31]
- wire [31:0] tin_addr = value_tin_addr + value_tin_offset; // @[VLd.scala 120:27]
- wire f_io_in_bits_0_bits_tin_stride = io_in_bits_0_bits_f2[1]; // @[VLd.scala 73:23]
- wire [1:0] _f_io_in_bits_0_bits_tin_T_3 = io_in_bits_0_bits_sz[1] + io_in_bits_0_bits_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_47 = {{1'd0}, io_in_bits_0_bits_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _f_io_in_bits_0_bits_tin_T_5 = _GEN_47 + _f_io_in_bits_0_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire [31:0] _f_io_in_bits_0_bits_tin_data_T_1 = io_in_bits_0_bits_sz[0] ? io_in_bits_0_bits_sv_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _f_io_in_bits_0_bits_tin_data_T_3 = {io_in_bits_0_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _f_io_in_bits_0_bits_tin_data_T_4 = io_in_bits_0_bits_sz[1] ? _f_io_in_bits_0_bits_tin_data_T_3 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_48 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_1}; // @[VLd.scala 80:44]
- wire [32:0] _f_io_in_bits_0_bits_tin_data_T_5 = _GEN_48 | _f_io_in_bits_0_bits_tin_data_T_4; // @[VLd.scala 80:44]
- wire [33:0] _f_io_in_bits_0_bits_tin_data_T_7 = {io_in_bits_0_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _f_io_in_bits_0_bits_tin_data_T_8 = io_in_bits_0_bits_sz[2] ? _f_io_in_bits_0_bits_tin_data_T_7 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_49 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_5}; // @[VLd.scala 81:59]
- wire [33:0] f_io_in_bits_0_bits_tin_data = _GEN_49 | _f_io_in_bits_0_bits_tin_data_T_8; // @[VLd.scala 81:59]
- wire f_io_in_bits_1_bits_tin_stride = io_in_bits_1_bits_f2[1]; // @[VLd.scala 73:23]
- wire [1:0] _f_io_in_bits_1_bits_tin_T_3 = io_in_bits_1_bits_sz[1] + io_in_bits_1_bits_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_51 = {{1'd0}, io_in_bits_1_bits_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _f_io_in_bits_1_bits_tin_T_5 = _GEN_51 + _f_io_in_bits_1_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire [31:0] _f_io_in_bits_1_bits_tin_data_T_1 = io_in_bits_1_bits_sz[0] ? io_in_bits_1_bits_sv_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _f_io_in_bits_1_bits_tin_data_T_3 = {io_in_bits_1_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _f_io_in_bits_1_bits_tin_data_T_4 = io_in_bits_1_bits_sz[1] ? _f_io_in_bits_1_bits_tin_data_T_3 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_52 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_1}; // @[VLd.scala 80:44]
- wire [32:0] _f_io_in_bits_1_bits_tin_data_T_5 = _GEN_52 | _f_io_in_bits_1_bits_tin_data_T_4; // @[VLd.scala 80:44]
- wire [33:0] _f_io_in_bits_1_bits_tin_data_T_7 = {io_in_bits_1_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _f_io_in_bits_1_bits_tin_data_T_8 = io_in_bits_1_bits_sz[2] ? _f_io_in_bits_1_bits_tin_data_T_7 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_53 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_5}; // @[VLd.scala 81:59]
- wire [33:0] f_io_in_bits_1_bits_tin_data = _GEN_53 | _f_io_in_bits_1_bits_tin_data_T_8; // @[VLd.scala 81:59]
- wire f_io_in_bits_2_bits_tin_stride = io_in_bits_2_bits_f2[1]; // @[VLd.scala 73:23]
- wire [1:0] _f_io_in_bits_2_bits_tin_T_3 = io_in_bits_2_bits_sz[1] + io_in_bits_2_bits_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_55 = {{1'd0}, io_in_bits_2_bits_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _f_io_in_bits_2_bits_tin_T_5 = _GEN_55 + _f_io_in_bits_2_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire [31:0] _f_io_in_bits_2_bits_tin_data_T_1 = io_in_bits_2_bits_sz[0] ? io_in_bits_2_bits_sv_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _f_io_in_bits_2_bits_tin_data_T_3 = {io_in_bits_2_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _f_io_in_bits_2_bits_tin_data_T_4 = io_in_bits_2_bits_sz[1] ? _f_io_in_bits_2_bits_tin_data_T_3 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_56 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_1}; // @[VLd.scala 80:44]
- wire [32:0] _f_io_in_bits_2_bits_tin_data_T_5 = _GEN_56 | _f_io_in_bits_2_bits_tin_data_T_4; // @[VLd.scala 80:44]
- wire [33:0] _f_io_in_bits_2_bits_tin_data_T_7 = {io_in_bits_2_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _f_io_in_bits_2_bits_tin_data_T_8 = io_in_bits_2_bits_sz[2] ? _f_io_in_bits_2_bits_tin_data_T_7 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_57 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_5}; // @[VLd.scala 81:59]
- wire [33:0] f_io_in_bits_2_bits_tin_data = _GEN_57 | _f_io_in_bits_2_bits_tin_data_T_8; // @[VLd.scala 81:59]
- wire f_io_in_bits_3_bits_tin_stride = io_in_bits_3_bits_f2[1]; // @[VLd.scala 73:23]
- wire [1:0] _f_io_in_bits_3_bits_tin_T_3 = io_in_bits_3_bits_sz[1] + io_in_bits_3_bits_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_59 = {{1'd0}, io_in_bits_3_bits_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _f_io_in_bits_3_bits_tin_T_5 = _GEN_59 + _f_io_in_bits_3_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire [31:0] _f_io_in_bits_3_bits_tin_data_T_1 = io_in_bits_3_bits_sz[0] ? io_in_bits_3_bits_sv_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _f_io_in_bits_3_bits_tin_data_T_3 = {io_in_bits_3_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _f_io_in_bits_3_bits_tin_data_T_4 = io_in_bits_3_bits_sz[1] ? _f_io_in_bits_3_bits_tin_data_T_3 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_60 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_1}; // @[VLd.scala 80:44]
- wire [32:0] _f_io_in_bits_3_bits_tin_data_T_5 = _GEN_60 | _f_io_in_bits_3_bits_tin_data_T_4; // @[VLd.scala 80:44]
- wire [33:0] _f_io_in_bits_3_bits_tin_data_T_7 = {io_in_bits_3_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _f_io_in_bits_3_bits_tin_data_T_8 = io_in_bits_3_bits_sz[2] ? _f_io_in_bits_3_bits_tin_data_T_7 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_61 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_5}; // @[VLd.scala 81:59]
- wire [33:0] f_io_in_bits_3_bits_tin_data = _GEN_61 | _f_io_in_bits_3_bits_tin_data_T_8; // @[VLd.scala 81:59]
- wire _T_16 = ~last; // @[VCmdq.scala 82:11]
- wire [4:0] _step_T_1 = step + 5'h1; // @[VCmdq.scala 86:20]
- wire _GEN_10 = ~last & value_m; // @[VCmdq.scala 82:18 85:15 91:15]
- wire _GEN_12 = io_out_valid & io_out_ready ? _T_16 : valid; // @[VCmdq.scala 51:22 81:46]
- Fifo4e_4 f ( // @[Fifo4e.scala 24:11]
- .clock(f_clock),
- .reset(f_reset),
- .io_in_ready(f_io_in_ready),
- .io_in_valid(f_io_in_valid),
- .io_in_bits_0_valid(f_io_in_bits_0_valid),
- .io_in_bits_0_bits_tin_op(f_io_in_bits_0_bits_tin_op),
- .io_in_bits_0_bits_tin_addr(f_io_in_bits_0_bits_tin_addr),
- .io_in_bits_0_bits_tin_offset(f_io_in_bits_0_bits_tin_offset),
- .io_in_bits_0_bits_tin_vd_addr(f_io_in_bits_0_bits_tin_vd_addr),
- .io_in_bits_0_bits_m(f_io_in_bits_0_bits_m),
- .io_in_bits_1_valid(f_io_in_bits_1_valid),
- .io_in_bits_1_bits_tin_op(f_io_in_bits_1_bits_tin_op),
- .io_in_bits_1_bits_tin_addr(f_io_in_bits_1_bits_tin_addr),
- .io_in_bits_1_bits_tin_offset(f_io_in_bits_1_bits_tin_offset),
- .io_in_bits_1_bits_tin_vd_addr(f_io_in_bits_1_bits_tin_vd_addr),
- .io_in_bits_1_bits_m(f_io_in_bits_1_bits_m),
- .io_in_bits_2_valid(f_io_in_bits_2_valid),
- .io_in_bits_2_bits_tin_op(f_io_in_bits_2_bits_tin_op),
- .io_in_bits_2_bits_tin_addr(f_io_in_bits_2_bits_tin_addr),
- .io_in_bits_2_bits_tin_offset(f_io_in_bits_2_bits_tin_offset),
- .io_in_bits_2_bits_tin_vd_addr(f_io_in_bits_2_bits_tin_vd_addr),
- .io_in_bits_2_bits_m(f_io_in_bits_2_bits_m),
- .io_in_bits_3_valid(f_io_in_bits_3_valid),
- .io_in_bits_3_bits_tin_op(f_io_in_bits_3_bits_tin_op),
- .io_in_bits_3_bits_tin_addr(f_io_in_bits_3_bits_tin_addr),
- .io_in_bits_3_bits_tin_offset(f_io_in_bits_3_bits_tin_offset),
- .io_in_bits_3_bits_tin_vd_addr(f_io_in_bits_3_bits_tin_vd_addr),
- .io_in_bits_3_bits_m(f_io_in_bits_3_bits_m),
- .io_out_ready(f_io_out_ready),
- .io_out_valid(f_io_out_valid),
- .io_out_bits_tin_op(f_io_out_bits_tin_op),
- .io_out_bits_tin_addr(f_io_out_bits_tin_addr),
- .io_out_bits_tin_offset(f_io_out_bits_tin_offset),
- .io_out_bits_tin_vd_addr(f_io_out_bits_tin_vd_addr),
- .io_out_bits_m(f_io_out_bits_m),
- .io_nempty(f_io_nempty)
- );
- assign io_in_ready = f_io_in_ready; // @[VCmdq.scala 65:15]
- assign io_out_valid = valid; // @[VCmdq.scala 133:16]
- assign io_out_bits_addr = value_tin_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_vd_addr = value_tin_vd_addr; // @[VCmdq.scala 134:15]
- assign io_nempty = f_io_nempty | valid; // @[VCmdq.scala 138:28]
- assign f_clock = clock;
- assign f_reset = reset;
- assign f_io_in_valid = io_in_valid; // @[VCmdq.scala 64:17]
- assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VLd.scala 72:19 89:12]
- assign f_io_in_bits_0_bits_tin_addr = io_in_bits_0_bits_sv_addr; // @[VLd.scala 72:19 92:14]
- assign f_io_in_bits_0_bits_tin_offset = f_io_in_bits_0_bits_tin_stride ? f_io_in_bits_0_bits_tin_data[31:0] : 32'h20; // @[VLd.scala 93:22]
- assign f_io_in_bits_0_bits_tin_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLd.scala 72:19 95:12]
- assign f_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VLd.scala 72:19 89:12]
- assign f_io_in_bits_1_bits_tin_addr = io_in_bits_1_bits_sv_addr; // @[VLd.scala 72:19 92:14]
- assign f_io_in_bits_1_bits_tin_offset = f_io_in_bits_1_bits_tin_stride ? f_io_in_bits_1_bits_tin_data[31:0] : 32'h20; // @[VLd.scala 93:22]
- assign f_io_in_bits_1_bits_tin_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLd.scala 72:19 95:12]
- assign f_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VLd.scala 72:19 89:12]
- assign f_io_in_bits_2_bits_tin_addr = io_in_bits_2_bits_sv_addr; // @[VLd.scala 72:19 92:14]
- assign f_io_in_bits_2_bits_tin_offset = f_io_in_bits_2_bits_tin_stride ? f_io_in_bits_2_bits_tin_data[31:0] : 32'h20; // @[VLd.scala 93:22]
- assign f_io_in_bits_2_bits_tin_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLd.scala 72:19 95:12]
- assign f_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VLd.scala 72:19 89:12]
- assign f_io_in_bits_3_bits_tin_addr = io_in_bits_3_bits_sv_addr; // @[VLd.scala 72:19 92:14]
- assign f_io_in_bits_3_bits_tin_offset = f_io_in_bits_3_bits_tin_stride ? f_io_in_bits_3_bits_tin_data[31:0] : 32'h20; // @[VLd.scala 93:22]
- assign f_io_in_bits_3_bits_tin_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLd.scala 72:19 95:12]
- assign f_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_out_ready = _T_8 | io_out_ready & last; // @[VCmdq.scala 73:28]
- always @(posedge clock) begin
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_op <= 7'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_op <= f_io_out_bits_tin_op; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_op <= 7'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_addr <= 32'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_addr <= f_io_out_bits_tin_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_addr <= tin_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_addr <= 32'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_offset <= 32'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_offset <= f_io_out_bits_tin_offset; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_offset <= 32'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vd_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vd_addr <= f_io_out_bits_tin_vd_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_vd_addr <= tin_vd_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_vd_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_m <= 1'h0; // @[VCmdq.scala 98:13]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_m <= f_io_out_bits_m; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_m <= _GEN_10;
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(addrAlign == 5'h0)) begin
- $fatal; // @[VLd.scala 105:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(addrAlign == 5'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:105 assert(addrAlign === 0.U)\n"); // @[VLd.scala 105:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(offsAlign == 5'h0)) begin
- $fatal; // @[VLd.scala 106:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(offsAlign == 5'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:106 assert(offsAlign === 0.U)\n"); // @[VLd.scala 106:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~valid | value_tin_op == 7'h2)) begin
- $fatal; // @[VLd.scala 107:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~valid | value_tin_op == 7'h2)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:107 assert(!valid || in.op === e.vld.U)\n"); // @[VLd.scala 107:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLd.scala 75:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:75 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLd.scala 75:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_0_bits_op == 7'h2 & (~io_in_bits_0_bits_vd_valid | io_in_bits_0_bits_vs_valid)))
- ) begin
- $fatal; // @[VLd.scala 76:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_0_bits_op == 7'h2 & (~io_in_bits_0_bits_vd_valid | io_in_bits_0_bits_vs_valid)))
- ) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLd.scala:76 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"); // @[VLd.scala 76:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLd.scala 75:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:75 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLd.scala 75:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_1_bits_op == 7'h2 & (~io_in_bits_1_bits_vd_valid | io_in_bits_1_bits_vs_valid)))
- ) begin
- $fatal; // @[VLd.scala 76:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_1_bits_op == 7'h2 & (~io_in_bits_1_bits_vd_valid | io_in_bits_1_bits_vs_valid)))
- ) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLd.scala:76 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"); // @[VLd.scala 76:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLd.scala 75:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:75 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLd.scala 75:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_2_bits_op == 7'h2 & (~io_in_bits_2_bits_vd_valid | io_in_bits_2_bits_vs_valid)))
- ) begin
- $fatal; // @[VLd.scala 76:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_2_bits_op == 7'h2 & (~io_in_bits_2_bits_vd_valid | io_in_bits_2_bits_vs_valid)))
- ) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLd.scala:76 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"); // @[VLd.scala 76:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VLd.scala 75:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:75 assert(PopCount(in.sz) <= 1.U)\n"); // @[VLd.scala 75:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h2 & (~io_in_bits_3_bits_vd_valid | io_in_bits_3_bits_vs_valid)))
- ) begin
- $fatal; // @[VLd.scala 76:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h2 & (~io_in_bits_3_bits_vd_valid | io_in_bits_3_bits_vs_valid)))
- ) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLd.scala:76 assert(!(in.op === e.vld.U && (!in.vd.valid || in.vs.valid)))\n"); // @[VLd.scala 76:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 77:43]
- valid <= 1'h0; // @[VCmdq.scala 78:11]
- end else begin
- valid <= f_io_out_valid & f_io_out_ready | _GEN_12;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 77:43]
- step <= 5'h0; // @[VCmdq.scala 80:10]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 81:46]
- step <= 5'h0; // @[VCmdq.scala 82:18 86:12 92:12]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 58:21]
- if (~last) begin
- step <= _step_T_1;
- end else begin
- step <= 5'h0;
- end
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- valid = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- value_tin_op = _RAND_1[6:0];
- _RAND_2 = {1{`RANDOM}};
- value_tin_addr = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- value_tin_offset = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- value_tin_vd_addr = _RAND_4[5:0];
- _RAND_5 = {1{`RANDOM}};
- value_m = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- step = _RAND_6[4:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- valid = 1'h0;
- end
- if (reset) begin
- step = 5'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VLd(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_op,
- input [2:0] io_in_bits_0_bits_f2,
- input [2:0] io_in_bits_0_bits_sz,
- input io_in_bits_0_bits_m,
- input io_in_bits_0_bits_vd_valid,
- input [5:0] io_in_bits_0_bits_vd_addr,
- input io_in_bits_0_bits_vs_valid,
- input [31:0] io_in_bits_0_bits_sv_addr,
- input [31:0] io_in_bits_0_bits_sv_data,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_op,
- input [2:0] io_in_bits_1_bits_f2,
- input [2:0] io_in_bits_1_bits_sz,
- input io_in_bits_1_bits_m,
- input io_in_bits_1_bits_vd_valid,
- input [5:0] io_in_bits_1_bits_vd_addr,
- input io_in_bits_1_bits_vs_valid,
- input [31:0] io_in_bits_1_bits_sv_addr,
- input [31:0] io_in_bits_1_bits_sv_data,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_op,
- input [2:0] io_in_bits_2_bits_f2,
- input [2:0] io_in_bits_2_bits_sz,
- input io_in_bits_2_bits_m,
- input io_in_bits_2_bits_vd_valid,
- input [5:0] io_in_bits_2_bits_vd_addr,
- input io_in_bits_2_bits_vs_valid,
- input [31:0] io_in_bits_2_bits_sv_addr,
- input [31:0] io_in_bits_2_bits_sv_data,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_op,
- input [2:0] io_in_bits_3_bits_f2,
- input [2:0] io_in_bits_3_bits_sz,
- input io_in_bits_3_bits_m,
- input io_in_bits_3_bits_vd_valid,
- input [5:0] io_in_bits_3_bits_vd_addr,
- input io_in_bits_3_bits_vs_valid,
- input [31:0] io_in_bits_3_bits_sv_addr,
- input [31:0] io_in_bits_3_bits_sv_data,
- output io_write_valid,
- output [5:0] io_write_addr,
- output [255:0] io_write_data,
- input io_axi_addr_ready,
- output io_axi_addr_valid,
- output [31:0] io_axi_addr_bits_addr,
- output [5:0] io_axi_addr_bits_id,
- output io_axi_data_ready,
- input io_axi_data_valid,
- input [5:0] io_axi_data_bits_id,
- input [255:0] io_axi_data_bits_data,
- output io_nempty
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
-`endif // RANDOMIZE_REG_INIT
- wire q_clock; // @[VCmdq.scala 30:11]
- wire q_reset; // @[VCmdq.scala 30:11]
- wire q_io_in_ready; // @[VCmdq.scala 30:11]
- wire q_io_in_valid; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_0_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_0_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_0_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_0_bits_sz; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_0_bits_m; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_0_bits_vd_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_0_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_0_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_0_bits_sv_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_0_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_1_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_1_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_1_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_1_bits_sz; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_1_bits_m; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_1_bits_vd_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_1_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_1_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_1_bits_sv_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_1_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_2_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_2_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_2_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_2_bits_sz; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_2_bits_m; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_2_bits_vd_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_2_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_2_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_2_bits_sv_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_2_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_3_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_3_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_3_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_3_bits_sz; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_3_bits_m; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_3_bits_vd_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_3_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_3_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_3_bits_sv_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_3_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_out_ready; // @[VCmdq.scala 30:11]
- wire q_io_out_valid; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_out_bits_addr; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_out_bits_vd_addr; // @[VCmdq.scala 30:11]
- wire q_io_nempty; // @[VCmdq.scala 30:11]
- wire _T_5 = ~reset; // @[VLd.scala 142:9]
- reg nempty; // @[VLd.scala 157:23]
- reg [6:0] count; // @[VLd.scala 158:22]
- wire inc = io_axi_addr_valid & io_axi_addr_ready; // @[VLd.scala 159:31]
- wire dec = io_axi_data_valid & io_axi_data_ready; // @[VLd.scala 160:31]
- wire _T_13 = inc | dec; // @[VLd.scala 162:13]
- wire [6:0] _GEN_2 = {{6'd0}, inc}; // @[VLd.scala 163:26]
- wire [6:0] _nxtcount_T_1 = count + _GEN_2; // @[VLd.scala 163:26]
- wire [6:0] _GEN_3 = {{6'd0}, dec}; // @[VLd.scala 163:32]
- wire [6:0] nxtcount = _nxtcount_T_1 - _GEN_3; // @[VLd.scala 163:32]
- VCmdq_4 q ( // @[VCmdq.scala 30:11]
- .clock(q_clock),
- .reset(q_reset),
- .io_in_ready(q_io_in_ready),
- .io_in_valid(q_io_in_valid),
- .io_in_bits_0_valid(q_io_in_bits_0_valid),
- .io_in_bits_0_bits_op(q_io_in_bits_0_bits_op),
- .io_in_bits_0_bits_f2(q_io_in_bits_0_bits_f2),
- .io_in_bits_0_bits_sz(q_io_in_bits_0_bits_sz),
- .io_in_bits_0_bits_m(q_io_in_bits_0_bits_m),
- .io_in_bits_0_bits_vd_valid(q_io_in_bits_0_bits_vd_valid),
- .io_in_bits_0_bits_vd_addr(q_io_in_bits_0_bits_vd_addr),
- .io_in_bits_0_bits_vs_valid(q_io_in_bits_0_bits_vs_valid),
- .io_in_bits_0_bits_sv_addr(q_io_in_bits_0_bits_sv_addr),
- .io_in_bits_0_bits_sv_data(q_io_in_bits_0_bits_sv_data),
- .io_in_bits_1_valid(q_io_in_bits_1_valid),
- .io_in_bits_1_bits_op(q_io_in_bits_1_bits_op),
- .io_in_bits_1_bits_f2(q_io_in_bits_1_bits_f2),
- .io_in_bits_1_bits_sz(q_io_in_bits_1_bits_sz),
- .io_in_bits_1_bits_m(q_io_in_bits_1_bits_m),
- .io_in_bits_1_bits_vd_valid(q_io_in_bits_1_bits_vd_valid),
- .io_in_bits_1_bits_vd_addr(q_io_in_bits_1_bits_vd_addr),
- .io_in_bits_1_bits_vs_valid(q_io_in_bits_1_bits_vs_valid),
- .io_in_bits_1_bits_sv_addr(q_io_in_bits_1_bits_sv_addr),
- .io_in_bits_1_bits_sv_data(q_io_in_bits_1_bits_sv_data),
- .io_in_bits_2_valid(q_io_in_bits_2_valid),
- .io_in_bits_2_bits_op(q_io_in_bits_2_bits_op),
- .io_in_bits_2_bits_f2(q_io_in_bits_2_bits_f2),
- .io_in_bits_2_bits_sz(q_io_in_bits_2_bits_sz),
- .io_in_bits_2_bits_m(q_io_in_bits_2_bits_m),
- .io_in_bits_2_bits_vd_valid(q_io_in_bits_2_bits_vd_valid),
- .io_in_bits_2_bits_vd_addr(q_io_in_bits_2_bits_vd_addr),
- .io_in_bits_2_bits_vs_valid(q_io_in_bits_2_bits_vs_valid),
- .io_in_bits_2_bits_sv_addr(q_io_in_bits_2_bits_sv_addr),
- .io_in_bits_2_bits_sv_data(q_io_in_bits_2_bits_sv_data),
- .io_in_bits_3_valid(q_io_in_bits_3_valid),
- .io_in_bits_3_bits_op(q_io_in_bits_3_bits_op),
- .io_in_bits_3_bits_f2(q_io_in_bits_3_bits_f2),
- .io_in_bits_3_bits_sz(q_io_in_bits_3_bits_sz),
- .io_in_bits_3_bits_m(q_io_in_bits_3_bits_m),
- .io_in_bits_3_bits_vd_valid(q_io_in_bits_3_bits_vd_valid),
- .io_in_bits_3_bits_vd_addr(q_io_in_bits_3_bits_vd_addr),
- .io_in_bits_3_bits_vs_valid(q_io_in_bits_3_bits_vs_valid),
- .io_in_bits_3_bits_sv_addr(q_io_in_bits_3_bits_sv_addr),
- .io_in_bits_3_bits_sv_data(q_io_in_bits_3_bits_sv_data),
- .io_out_ready(q_io_out_ready),
- .io_out_valid(q_io_out_valid),
- .io_out_bits_addr(q_io_out_bits_addr),
- .io_out_bits_vd_addr(q_io_out_bits_vd_addr),
- .io_nempty(q_io_nempty)
- );
- assign io_in_ready = q_io_in_ready; // @[VLd.scala 135:11]
- assign io_write_valid = io_axi_data_valid; // @[VLd.scala 149:18]
- assign io_write_addr = io_axi_data_bits_id; // @[VLd.scala 151:17]
- assign io_write_data = io_axi_data_bits_data; // @[VLd.scala 150:17]
- assign io_axi_addr_valid = q_io_out_valid; // @[VLd.scala 139:21]
- assign io_axi_addr_bits_addr = {1'h0,q_io_out_bits_addr[30:0]}; // @[Cat.scala 31:58]
- assign io_axi_addr_bits_id = q_io_out_bits_vd_addr; // @[VLd.scala 141:23]
- assign io_axi_data_ready = 1'h1; // @[VLd.scala 153:21]
- assign io_nempty = q_io_nempty | nempty; // @[VLd.scala 169:28]
- assign q_clock = clock;
- assign q_reset = reset;
- assign q_io_in_valid = io_in_valid; // @[VLd.scala 135:11]
- assign q_io_in_bits_0_valid = io_in_bits_0_valid; // @[VLd.scala 135:11]
- assign q_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VLd.scala 135:11]
- assign q_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VLd.scala 135:11]
- assign q_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VLd.scala 135:11]
- assign q_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VLd.scala 135:11]
- assign q_io_in_bits_0_bits_vd_valid = io_in_bits_0_bits_vd_valid; // @[VLd.scala 135:11]
- assign q_io_in_bits_0_bits_vd_addr = io_in_bits_0_bits_vd_addr; // @[VLd.scala 135:11]
- assign q_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VLd.scala 135:11]
- assign q_io_in_bits_0_bits_sv_addr = io_in_bits_0_bits_sv_addr; // @[VLd.scala 135:11]
- assign q_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VLd.scala 135:11]
- assign q_io_in_bits_1_valid = io_in_bits_1_valid; // @[VLd.scala 135:11]
- assign q_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VLd.scala 135:11]
- assign q_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VLd.scala 135:11]
- assign q_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VLd.scala 135:11]
- assign q_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VLd.scala 135:11]
- assign q_io_in_bits_1_bits_vd_valid = io_in_bits_1_bits_vd_valid; // @[VLd.scala 135:11]
- assign q_io_in_bits_1_bits_vd_addr = io_in_bits_1_bits_vd_addr; // @[VLd.scala 135:11]
- assign q_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VLd.scala 135:11]
- assign q_io_in_bits_1_bits_sv_addr = io_in_bits_1_bits_sv_addr; // @[VLd.scala 135:11]
- assign q_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VLd.scala 135:11]
- assign q_io_in_bits_2_valid = io_in_bits_2_valid; // @[VLd.scala 135:11]
- assign q_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VLd.scala 135:11]
- assign q_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VLd.scala 135:11]
- assign q_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VLd.scala 135:11]
- assign q_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VLd.scala 135:11]
- assign q_io_in_bits_2_bits_vd_valid = io_in_bits_2_bits_vd_valid; // @[VLd.scala 135:11]
- assign q_io_in_bits_2_bits_vd_addr = io_in_bits_2_bits_vd_addr; // @[VLd.scala 135:11]
- assign q_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VLd.scala 135:11]
- assign q_io_in_bits_2_bits_sv_addr = io_in_bits_2_bits_sv_addr; // @[VLd.scala 135:11]
- assign q_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VLd.scala 135:11]
- assign q_io_in_bits_3_valid = io_in_bits_3_valid; // @[VLd.scala 135:11]
- assign q_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VLd.scala 135:11]
- assign q_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VLd.scala 135:11]
- assign q_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VLd.scala 135:11]
- assign q_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VLd.scala 135:11]
- assign q_io_in_bits_3_bits_vd_valid = io_in_bits_3_bits_vd_valid; // @[VLd.scala 135:11]
- assign q_io_in_bits_3_bits_vd_addr = io_in_bits_3_bits_vd_addr; // @[VLd.scala 135:11]
- assign q_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VLd.scala 135:11]
- assign q_io_in_bits_3_bits_sv_addr = io_in_bits_3_bits_sv_addr; // @[VLd.scala 135:11]
- assign q_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VLd.scala 135:11]
- assign q_io_out_ready = io_axi_addr_ready; // @[VLd.scala 145:18]
- always @(posedge clock) begin
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(q_io_out_valid & ~q_io_out_bits_addr[31]))) begin
- $fatal; // @[VLd.scala 142:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(q_io_out_valid & ~q_io_out_bits_addr[31]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLd.scala:142 assert(!(q.io.out.valid && !q.io.out.bits.addr(31)))\n"); // @[VLd.scala 142:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_5 & ~(~(io_axi_addr_valid & io_axi_addr_bits_addr[31]))) begin
- $fatal; // @[VLd.scala 143:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_5 & ~(~(io_axi_addr_valid & io_axi_addr_bits_addr[31]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VLd.scala:143 assert(!(io.axi.addr.valid && io.axi.addr.bits.addr(31)))\n"); // @[VLd.scala 143:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_13 & _T_5 & ~(count <= 7'h40)) begin
- $fatal; // @[VLd.scala 166:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_13 & _T_5 & ~(count <= 7'h40)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VLd.scala:166 assert(count <= 64.U)\n"); // @[VLd.scala 166:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VLd.scala 162:21]
- nempty <= 1'h0; // @[VLd.scala 165:12]
- end else if (inc | dec) begin // @[VLd.scala 157:23]
- nempty <= nxtcount != 7'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VLd.scala 162:21]
- count <= 7'h0; // @[VLd.scala 164:11]
- end else if (inc | dec) begin // @[VLd.scala 158:22]
- count <= nxtcount;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- nempty = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- count = _RAND_1[6:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- nempty = 1'h0;
- end
- if (reset) begin
- count = 7'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Fifo4e_5(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_tin_op,
- input [31:0] io_in_bits_0_bits_tin_addr,
- input [31:0] io_in_bits_0_bits_tin_offset,
- input [7:0] io_in_bits_0_bits_tin_remain,
- input io_in_bits_0_bits_tin_vs_valid,
- input [5:0] io_in_bits_0_bits_tin_vs_addr,
- input [3:0] io_in_bits_0_bits_tin_vs_tag,
- input io_in_bits_0_bits_m,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_tin_op,
- input [31:0] io_in_bits_1_bits_tin_addr,
- input [31:0] io_in_bits_1_bits_tin_offset,
- input [7:0] io_in_bits_1_bits_tin_remain,
- input io_in_bits_1_bits_tin_vs_valid,
- input [5:0] io_in_bits_1_bits_tin_vs_addr,
- input [3:0] io_in_bits_1_bits_tin_vs_tag,
- input io_in_bits_1_bits_m,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_tin_op,
- input [31:0] io_in_bits_2_bits_tin_addr,
- input [31:0] io_in_bits_2_bits_tin_offset,
- input [7:0] io_in_bits_2_bits_tin_remain,
- input io_in_bits_2_bits_tin_vs_valid,
- input [5:0] io_in_bits_2_bits_tin_vs_addr,
- input [3:0] io_in_bits_2_bits_tin_vs_tag,
- input io_in_bits_2_bits_m,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_tin_op,
- input [31:0] io_in_bits_3_bits_tin_addr,
- input [31:0] io_in_bits_3_bits_tin_offset,
- input [7:0] io_in_bits_3_bits_tin_remain,
- input io_in_bits_3_bits_tin_vs_valid,
- input [5:0] io_in_bits_3_bits_tin_vs_addr,
- input [3:0] io_in_bits_3_bits_tin_vs_tag,
- input io_in_bits_3_bits_m,
- input io_out_ready,
- output io_out_valid,
- output [6:0] io_out_bits_tin_op,
- output [31:0] io_out_bits_tin_addr,
- output [31:0] io_out_bits_tin_offset,
- output [7:0] io_out_bits_tin_remain,
- output io_out_bits_tin_vs_valid,
- output [5:0] io_out_bits_tin_vs_addr,
- output [3:0] io_out_bits_tin_vs_tag,
- output [1:0] io_out_bits_tin_quad,
- output io_out_bits_m,
- output io_entry_0_valid,
- output io_entry_0_bits_tin_vs_valid,
- output [5:0] io_entry_0_bits_tin_vs_addr,
- output io_entry_0_bits_m,
- output io_entry_1_valid,
- output io_entry_1_bits_tin_vs_valid,
- output [5:0] io_entry_1_bits_tin_vs_addr,
- output io_entry_1_bits_m,
- output io_entry_2_valid,
- output io_entry_2_bits_tin_vs_valid,
- output [5:0] io_entry_2_bits_tin_vs_addr,
- output io_entry_2_bits_m,
- output io_entry_3_valid,
- output io_entry_3_bits_tin_vs_valid,
- output [5:0] io_entry_3_bits_tin_vs_addr,
- output io_entry_3_bits_m,
- output io_entry_4_valid,
- output io_entry_4_bits_tin_vs_valid,
- output [5:0] io_entry_4_bits_tin_vs_addr,
- output io_entry_4_bits_m,
- output io_entry_5_valid,
- output io_entry_5_bits_tin_vs_valid,
- output [5:0] io_entry_5_bits_tin_vs_addr,
- output io_entry_5_bits_m,
- output io_entry_6_valid,
- output io_entry_6_bits_tin_vs_valid,
- output [5:0] io_entry_6_bits_tin_vs_addr,
- output io_entry_6_bits_m,
- output io_entry_7_valid,
- output io_entry_7_bits_tin_vs_valid,
- output [5:0] io_entry_7_bits_tin_vs_addr,
- output io_entry_7_bits_m,
- output io_nempty
-);
-`ifdef RANDOMIZE_MEM_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
-`endif // RANDOMIZE_REG_INIT
- reg [6:0] mem_tin_op [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [6:0] mem_tin_op_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_op_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_op_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [31:0] mem_tin_addr [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_addr_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_addr_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [31:0] mem_tin_offset [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [31:0] mem_tin_offset_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_offset_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_offset_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [7:0] mem_tin_remain [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [7:0] mem_tin_remain_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_remain_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_remain_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg mem_tin_vs_valid [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_valid_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_valid_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [5:0] mem_tin_vs_addr [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [5:0] mem_tin_vs_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_addr_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_addr_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [3:0] mem_tin_vs_tag [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [3:0] mem_tin_vs_tag_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_vs_tag_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_vs_tag_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [1:0] mem_tin_quad [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire [1:0] mem_tin_quad_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_tin_quad_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_tin_quad_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg mem_m [0:7]; // @[Fifo4e.scala 43:16]
- wire mem_m_io_out_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_out_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_out_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_0_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_0_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_1_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_1_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_2_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_2_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_3_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_3_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_4_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_4_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_5_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_5_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_6_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_6_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_7_bits_MPORT_en; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_io_entry_7_bits_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_1_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_1_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_2_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_2_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_3_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_3_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_4_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_4_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_5_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_5_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_6_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_6_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_7_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_7_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_8_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_8_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_9_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_9_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_10_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_10_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_11_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_11_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_12_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_12_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_13_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_13_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_14_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_14_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_15_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_15_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_16_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_16_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_16_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_16_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_17_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_17_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_17_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_17_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_18_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_18_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_18_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_18_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_19_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_19_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_19_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_19_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_20_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_20_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_20_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_20_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_21_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_21_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_21_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_21_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_22_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_22_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_22_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_22_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_23_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_23_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_23_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_23_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_24_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_24_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_24_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_24_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_25_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_25_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_25_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_25_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_26_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_26_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_26_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_26_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_27_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_27_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_27_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_27_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_28_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_28_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_28_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_28_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_29_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_29_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_29_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_29_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_30_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_30_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_30_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_30_en; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_31_data; // @[Fifo4e.scala 43:16]
- wire [2:0] mem_m_MPORT_31_addr; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_31_mask; // @[Fifo4e.scala 43:16]
- wire mem_m_MPORT_31_en; // @[Fifo4e.scala 43:16]
- reg [2:0] in0pos; // @[Fifo4e.scala 45:23]
- reg [2:0] in1pos; // @[Fifo4e.scala 46:23]
- reg [2:0] in2pos; // @[Fifo4e.scala 47:23]
- reg [2:0] in3pos; // @[Fifo4e.scala 48:23]
- reg [2:0] outpos; // @[Fifo4e.scala 49:23]
- reg [3:0] mcount; // @[Fifo4e.scala 50:23]
- reg nempty; // @[Fifo4e.scala 51:23]
- wire ivalid = io_in_valid & io_in_ready; // @[Fifo4e.scala 56:28]
- wire dec = io_out_valid & io_out_ready; // @[Fifo4e.scala 57:29]
- wire [3:0] iactive = {io_in_bits_3_valid,io_in_bits_2_valid,io_in_bits_1_valid,io_in_bits_0_valid}; // @[Cat.scala 31:58]
- wire [1:0] _icount_T = io_in_bits_0_valid + io_in_bits_1_valid; // @[Fifo4e.scala 62:36]
- wire [1:0] _GEN_1786 = {{1'd0}, io_in_bits_2_valid}; // @[Fifo4e.scala 62:59]
- wire [1:0] _icount_T_2 = _icount_T + _GEN_1786; // @[Fifo4e.scala 62:59]
- wire [1:0] _GEN_1787 = {{1'd0}, io_in_bits_3_valid}; // @[Fifo4e.scala 63:36]
- wire [2:0] icount = _icount_T_2 + _GEN_1787; // @[Fifo4e.scala 63:36]
- wire [3:0] in0pos_c = in0pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in0pos_d_T_2 = in0pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in0pos_d_T_3 = in0pos_c < 4'h8 ? in0pos_c : _in0pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in0pos_d = _in0pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] in1pos_c = in1pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in1pos_d_T_2 = in1pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in1pos_d_T_3 = in1pos_c < 4'h8 ? in1pos_c : _in1pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in1pos_d = _in1pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] in2pos_c = in2pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in2pos_d_T_2 = in2pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in2pos_d_T_3 = in2pos_c < 4'h8 ? in2pos_c : _in2pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in2pos_d = _in2pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] in3pos_c = in3pos + icount; // @[Fifo4e.scala 38:15]
- wire [3:0] _in3pos_d_T_2 = in3pos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _in3pos_d_T_3 = in3pos_c < 4'h8 ? in3pos_c : _in3pos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] in3pos_d = _in3pos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [3:0] outpos_c = outpos + 3'h1; // @[Fifo4e.scala 38:15]
- wire [3:0] _outpos_d_T_2 = outpos_c - 4'h8; // @[Fifo4e.scala 39:31]
- wire [3:0] _outpos_d_T_3 = outpos_c < 4'h8 ? outpos_c : _outpos_d_T_2; // @[Fifo4e.scala 39:16]
- wire [2:0] outpos_d = _outpos_d_T_3[2:0]; // @[Fifo4e.scala 39:37]
- wire [2:0] inc = ivalid ? icount : 3'h0; // @[Library.scala 22:8]
- wire _T = ivalid | dec; // @[Fifo4e.scala 81:16]
- wire [3:0] _GEN_1788 = {{1'd0}, inc}; // @[Fifo4e.scala 82:27]
- wire [3:0] _nxtcount_T_1 = mcount + _GEN_1788; // @[Fifo4e.scala 82:27]
- wire [3:0] _GEN_1789 = {{3'd0}, dec}; // @[Fifo4e.scala 82:33]
- wire [3:0] nxtcount = _nxtcount_T_1 - _GEN_1789; // @[Fifo4e.scala 82:33]
- wire _in0_T_1 = iactive == 4'h8; // @[Fifo4.scala 31:27]
- wire _in0_T_3 = iactive[2:0] == 3'h4; // @[Fifo4.scala 32:27]
- wire _in0_T_5 = iactive[1:0] == 2'h2; // @[Fifo4.scala 33:27]
- wire [3:0] in0valid = {_in0_T_1,_in0_T_3,_in0_T_5,iactive[0]}; // @[Cat.scala 31:58]
- wire _in1_T_3 = iactive == 4'ha; // @[Fifo4.scala 37:27]
- wire _in1_T_4 = iactive == 4'hc | _in1_T_3; // @[Fifo4.scala 36:36]
- wire _in1_T_6 = iactive == 4'h9; // @[Fifo4.scala 38:27]
- wire _in1_T_7 = _in1_T_4 | _in1_T_6; // @[Fifo4.scala 37:36]
- wire _in1_T_11 = iactive[2:0] == 3'h5; // @[Fifo4.scala 40:27]
- wire _in1_T_12 = iactive[2:0] == 3'h6 | _in1_T_11; // @[Fifo4.scala 39:35]
- wire _in1_T_14 = iactive[1:0] == 2'h3; // @[Fifo4.scala 41:27]
- wire [3:0] in1valid = {_in1_T_7,_in1_T_12,_in1_T_14,1'h0}; // @[Cat.scala 31:58]
- wire _in2_T_3 = iactive == 4'hd; // @[Fifo4.scala 45:27]
- wire _in2_T_4 = iactive == 4'he | _in2_T_3; // @[Fifo4.scala 44:36]
- wire _in2_T_6 = iactive == 4'hb; // @[Fifo4.scala 46:27]
- wire _in2_T_7 = _in2_T_4 | _in2_T_6; // @[Fifo4.scala 45:36]
- wire [3:0] _GEN_1790 = {{1'd0}, iactive[2:0]}; // @[Fifo4.scala 47:27]
- wire _in2_T_11 = iactive[2:0] == 3'h7; // @[Fifo4.scala 48:27]
- wire _in2_T_12 = _GEN_1790 == 4'hf | _in2_T_11; // @[Fifo4.scala 47:36]
- wire [3:0] in2valid = {_in2_T_7,_in2_T_12,2'h0}; // @[Cat.scala 31:58]
- wire _in3_T_1 = iactive == 4'hf; // @[Fifo4.scala 51:27]
- wire [3:0] in3valid = {_in3_T_1,1'h0,2'h0}; // @[Cat.scala 31:58]
- wire _valid_T = in0pos == 3'h0; // @[Fifo4e.scala 92:28]
- wire _valid_T_3 = in1pos == 3'h0; // @[Fifo4e.scala 93:28]
- wire _valid_T_5 = in1pos == 3'h0 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_6 = in0pos == 3'h0 & in0valid[3] | _valid_T_5; // @[Fifo4e.scala 92:51]
- wire _valid_T_7 = in2pos == 3'h0; // @[Fifo4e.scala 94:28]
- wire _valid_T_9 = in2pos == 3'h0 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_10 = _valid_T_6 | _valid_T_9; // @[Fifo4e.scala 93:51]
- wire _valid_T_13 = in3pos == 3'h0 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_14 = _valid_T_10 | _valid_T_13; // @[Fifo4e.scala 94:51]
- wire _valid_T_20 = _valid_T_3 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_21 = _valid_T & in0valid[2] | _valid_T_20; // @[Fifo4e.scala 96:51]
- wire _valid_T_24 = _valid_T_7 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_25 = _valid_T_21 | _valid_T_24; // @[Fifo4e.scala 97:51]
- wire _valid_T_31 = _valid_T_3 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_32 = _valid_T & in0valid[1] | _valid_T_31; // @[Fifo4e.scala 99:51]
- wire _valid_T_35 = _valid_T & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid = {_valid_T_14,_valid_T_25,_valid_T_32,_valid_T_35}; // @[Cat.scala 31:58]
- wire _GEN_41 = valid[2] ? 1'h0 : valid[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_73 = valid[1] ? 1'h0 : valid[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_89 = valid[1] ? 1'h0 : _GEN_41; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_121 = valid[0] ? 1'h0 : valid[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_137 = valid[0] ? 1'h0 : _GEN_73; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_153 = valid[0] ? 1'h0 : _GEN_89; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_36 = in0pos == 3'h1; // @[Fifo4e.scala 92:28]
- wire _valid_T_39 = in1pos == 3'h1; // @[Fifo4e.scala 93:28]
- wire _valid_T_41 = in1pos == 3'h1 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_42 = in0pos == 3'h1 & in0valid[3] | _valid_T_41; // @[Fifo4e.scala 92:51]
- wire _valid_T_43 = in2pos == 3'h1; // @[Fifo4e.scala 94:28]
- wire _valid_T_45 = in2pos == 3'h1 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_46 = _valid_T_42 | _valid_T_45; // @[Fifo4e.scala 93:51]
- wire _valid_T_49 = in3pos == 3'h1 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_50 = _valid_T_46 | _valid_T_49; // @[Fifo4e.scala 94:51]
- wire _valid_T_56 = _valid_T_39 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_57 = _valid_T_36 & in0valid[2] | _valid_T_56; // @[Fifo4e.scala 96:51]
- wire _valid_T_60 = _valid_T_43 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_61 = _valid_T_57 | _valid_T_60; // @[Fifo4e.scala 97:51]
- wire _valid_T_67 = _valid_T_39 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_68 = _valid_T_36 & in0valid[1] | _valid_T_67; // @[Fifo4e.scala 99:51]
- wire _valid_T_71 = _valid_T_36 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_1 = {_valid_T_50,_valid_T_61,_valid_T_68,_valid_T_71}; // @[Cat.scala 31:58]
- wire _GEN_263 = valid_1[2] ? 1'h0 : valid_1[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_293 = valid_1[1] ? 1'h0 : valid_1[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_308 = valid_1[1] ? 1'h0 : _GEN_263; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_338 = valid_1[0] ? 1'h0 : valid_1[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_353 = valid_1[0] ? 1'h0 : _GEN_293; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_368 = valid_1[0] ? 1'h0 : _GEN_308; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_72 = in0pos == 3'h2; // @[Fifo4e.scala 92:28]
- wire _valid_T_75 = in1pos == 3'h2; // @[Fifo4e.scala 93:28]
- wire _valid_T_77 = in1pos == 3'h2 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_78 = in0pos == 3'h2 & in0valid[3] | _valid_T_77; // @[Fifo4e.scala 92:51]
- wire _valid_T_79 = in2pos == 3'h2; // @[Fifo4e.scala 94:28]
- wire _valid_T_81 = in2pos == 3'h2 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_82 = _valid_T_78 | _valid_T_81; // @[Fifo4e.scala 93:51]
- wire _valid_T_85 = in3pos == 3'h2 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_86 = _valid_T_82 | _valid_T_85; // @[Fifo4e.scala 94:51]
- wire _valid_T_92 = _valid_T_75 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_93 = _valid_T_72 & in0valid[2] | _valid_T_92; // @[Fifo4e.scala 96:51]
- wire _valid_T_96 = _valid_T_79 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_97 = _valid_T_93 | _valid_T_96; // @[Fifo4e.scala 97:51]
- wire _valid_T_103 = _valid_T_75 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_104 = _valid_T_72 & in0valid[1] | _valid_T_103; // @[Fifo4e.scala 99:51]
- wire _valid_T_107 = _valid_T_72 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_2 = {_valid_T_86,_valid_T_97,_valid_T_104,_valid_T_107}; // @[Cat.scala 31:58]
- wire _GEN_475 = valid_2[2] ? 1'h0 : valid_2[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_507 = valid_2[1] ? 1'h0 : valid_2[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_523 = valid_2[1] ? 1'h0 : _GEN_475; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_555 = valid_2[0] ? 1'h0 : valid_2[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_571 = valid_2[0] ? 1'h0 : _GEN_507; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_587 = valid_2[0] ? 1'h0 : _GEN_523; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_108 = in0pos == 3'h3; // @[Fifo4e.scala 92:28]
- wire _valid_T_111 = in1pos == 3'h3; // @[Fifo4e.scala 93:28]
- wire _valid_T_113 = in1pos == 3'h3 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_114 = in0pos == 3'h3 & in0valid[3] | _valid_T_113; // @[Fifo4e.scala 92:51]
- wire _valid_T_115 = in2pos == 3'h3; // @[Fifo4e.scala 94:28]
- wire _valid_T_117 = in2pos == 3'h3 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_118 = _valid_T_114 | _valid_T_117; // @[Fifo4e.scala 93:51]
- wire _valid_T_121 = in3pos == 3'h3 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_122 = _valid_T_118 | _valid_T_121; // @[Fifo4e.scala 94:51]
- wire _valid_T_128 = _valid_T_111 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_129 = _valid_T_108 & in0valid[2] | _valid_T_128; // @[Fifo4e.scala 96:51]
- wire _valid_T_132 = _valid_T_115 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_133 = _valid_T_129 | _valid_T_132; // @[Fifo4e.scala 97:51]
- wire _valid_T_139 = _valid_T_111 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_140 = _valid_T_108 & in0valid[1] | _valid_T_139; // @[Fifo4e.scala 99:51]
- wire _valid_T_143 = _valid_T_108 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_3 = {_valid_T_122,_valid_T_133,_valid_T_140,_valid_T_143}; // @[Cat.scala 31:58]
- wire _GEN_699 = valid_3[2] ? 1'h0 : valid_3[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_731 = valid_3[1] ? 1'h0 : valid_3[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_747 = valid_3[1] ? 1'h0 : _GEN_699; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_779 = valid_3[0] ? 1'h0 : valid_3[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_795 = valid_3[0] ? 1'h0 : _GEN_731; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_811 = valid_3[0] ? 1'h0 : _GEN_747; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_144 = in0pos == 3'h4; // @[Fifo4e.scala 92:28]
- wire _valid_T_147 = in1pos == 3'h4; // @[Fifo4e.scala 93:28]
- wire _valid_T_149 = in1pos == 3'h4 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_150 = in0pos == 3'h4 & in0valid[3] | _valid_T_149; // @[Fifo4e.scala 92:51]
- wire _valid_T_151 = in2pos == 3'h4; // @[Fifo4e.scala 94:28]
- wire _valid_T_153 = in2pos == 3'h4 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_154 = _valid_T_150 | _valid_T_153; // @[Fifo4e.scala 93:51]
- wire _valid_T_157 = in3pos == 3'h4 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_158 = _valid_T_154 | _valid_T_157; // @[Fifo4e.scala 94:51]
- wire _valid_T_164 = _valid_T_147 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_165 = _valid_T_144 & in0valid[2] | _valid_T_164; // @[Fifo4e.scala 96:51]
- wire _valid_T_168 = _valid_T_151 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_169 = _valid_T_165 | _valid_T_168; // @[Fifo4e.scala 97:51]
- wire _valid_T_175 = _valid_T_147 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_176 = _valid_T_144 & in0valid[1] | _valid_T_175; // @[Fifo4e.scala 99:51]
- wire _valid_T_179 = _valid_T_144 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_4 = {_valid_T_158,_valid_T_169,_valid_T_176,_valid_T_179}; // @[Cat.scala 31:58]
- wire _GEN_923 = valid_4[2] ? 1'h0 : valid_4[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_955 = valid_4[1] ? 1'h0 : valid_4[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_971 = valid_4[1] ? 1'h0 : _GEN_923; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1003 = valid_4[0] ? 1'h0 : valid_4[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1019 = valid_4[0] ? 1'h0 : _GEN_955; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1035 = valid_4[0] ? 1'h0 : _GEN_971; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_180 = in0pos == 3'h5; // @[Fifo4e.scala 92:28]
- wire _valid_T_183 = in1pos == 3'h5; // @[Fifo4e.scala 93:28]
- wire _valid_T_185 = in1pos == 3'h5 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_186 = in0pos == 3'h5 & in0valid[3] | _valid_T_185; // @[Fifo4e.scala 92:51]
- wire _valid_T_187 = in2pos == 3'h5; // @[Fifo4e.scala 94:28]
- wire _valid_T_189 = in2pos == 3'h5 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_190 = _valid_T_186 | _valid_T_189; // @[Fifo4e.scala 93:51]
- wire _valid_T_193 = in3pos == 3'h5 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_194 = _valid_T_190 | _valid_T_193; // @[Fifo4e.scala 94:51]
- wire _valid_T_200 = _valid_T_183 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_201 = _valid_T_180 & in0valid[2] | _valid_T_200; // @[Fifo4e.scala 96:51]
- wire _valid_T_204 = _valid_T_187 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_205 = _valid_T_201 | _valid_T_204; // @[Fifo4e.scala 97:51]
- wire _valid_T_211 = _valid_T_183 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_212 = _valid_T_180 & in0valid[1] | _valid_T_211; // @[Fifo4e.scala 99:51]
- wire _valid_T_215 = _valid_T_180 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_5 = {_valid_T_194,_valid_T_205,_valid_T_212,_valid_T_215}; // @[Cat.scala 31:58]
- wire _GEN_1147 = valid_5[2] ? 1'h0 : valid_5[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_1179 = valid_5[1] ? 1'h0 : valid_5[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1195 = valid_5[1] ? 1'h0 : _GEN_1147; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1227 = valid_5[0] ? 1'h0 : valid_5[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1243 = valid_5[0] ? 1'h0 : _GEN_1179; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1259 = valid_5[0] ? 1'h0 : _GEN_1195; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_216 = in0pos == 3'h6; // @[Fifo4e.scala 92:28]
- wire _valid_T_219 = in1pos == 3'h6; // @[Fifo4e.scala 93:28]
- wire _valid_T_221 = in1pos == 3'h6 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_222 = in0pos == 3'h6 & in0valid[3] | _valid_T_221; // @[Fifo4e.scala 92:51]
- wire _valid_T_223 = in2pos == 3'h6; // @[Fifo4e.scala 94:28]
- wire _valid_T_225 = in2pos == 3'h6 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_226 = _valid_T_222 | _valid_T_225; // @[Fifo4e.scala 93:51]
- wire _valid_T_229 = in3pos == 3'h6 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_230 = _valid_T_226 | _valid_T_229; // @[Fifo4e.scala 94:51]
- wire _valid_T_236 = _valid_T_219 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_237 = _valid_T_216 & in0valid[2] | _valid_T_236; // @[Fifo4e.scala 96:51]
- wire _valid_T_240 = _valid_T_223 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_241 = _valid_T_237 | _valid_T_240; // @[Fifo4e.scala 97:51]
- wire _valid_T_247 = _valid_T_219 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_248 = _valid_T_216 & in0valid[1] | _valid_T_247; // @[Fifo4e.scala 99:51]
- wire _valid_T_251 = _valid_T_216 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_6 = {_valid_T_230,_valid_T_241,_valid_T_248,_valid_T_251}; // @[Cat.scala 31:58]
- wire _GEN_1371 = valid_6[2] ? 1'h0 : valid_6[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_1403 = valid_6[1] ? 1'h0 : valid_6[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1419 = valid_6[1] ? 1'h0 : _GEN_1371; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1451 = valid_6[0] ? 1'h0 : valid_6[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1467 = valid_6[0] ? 1'h0 : _GEN_1403; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1483 = valid_6[0] ? 1'h0 : _GEN_1419; // @[Fifo4e.scala 104:23 43:16]
- wire _valid_T_252 = in0pos == 3'h7; // @[Fifo4e.scala 92:28]
- wire _valid_T_255 = in1pos == 3'h7; // @[Fifo4e.scala 93:28]
- wire _valid_T_257 = in1pos == 3'h7 & in1valid[3]; // @[Fifo4e.scala 93:36]
- wire _valid_T_258 = in0pos == 3'h7 & in0valid[3] | _valid_T_257; // @[Fifo4e.scala 92:51]
- wire _valid_T_259 = in2pos == 3'h7; // @[Fifo4e.scala 94:28]
- wire _valid_T_261 = in2pos == 3'h7 & in2valid[3]; // @[Fifo4e.scala 94:36]
- wire _valid_T_262 = _valid_T_258 | _valid_T_261; // @[Fifo4e.scala 93:51]
- wire _valid_T_265 = in3pos == 3'h7 & in3valid[3]; // @[Fifo4e.scala 95:36]
- wire _valid_T_266 = _valid_T_262 | _valid_T_265; // @[Fifo4e.scala 94:51]
- wire _valid_T_272 = _valid_T_255 & in1valid[2]; // @[Fifo4e.scala 97:36]
- wire _valid_T_273 = _valid_T_252 & in0valid[2] | _valid_T_272; // @[Fifo4e.scala 96:51]
- wire _valid_T_276 = _valid_T_259 & in2valid[2]; // @[Fifo4e.scala 98:36]
- wire _valid_T_277 = _valid_T_273 | _valid_T_276; // @[Fifo4e.scala 97:51]
- wire _valid_T_283 = _valid_T_255 & in1valid[1]; // @[Fifo4e.scala 100:36]
- wire _valid_T_284 = _valid_T_252 & in0valid[1] | _valid_T_283; // @[Fifo4e.scala 99:51]
- wire _valid_T_287 = _valid_T_252 & in0valid[0]; // @[Fifo4e.scala 101:36]
- wire [3:0] valid_7 = {_valid_T_266,_valid_T_277,_valid_T_284,_valid_T_287}; // @[Cat.scala 31:58]
- wire _GEN_1595 = valid_7[2] ? 1'h0 : valid_7[3]; // @[Fifo4e.scala 108:30 43:16]
- wire _GEN_1627 = valid_7[1] ? 1'h0 : valid_7[2]; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1643 = valid_7[1] ? 1'h0 : _GEN_1595; // @[Fifo4e.scala 106:30 43:16]
- wire _GEN_1675 = valid_7[0] ? 1'h0 : valid_7[1]; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1691 = valid_7[0] ? 1'h0 : _GEN_1627; // @[Fifo4e.scala 104:23 43:16]
- wire _GEN_1707 = valid_7[0] ? 1'h0 : _GEN_1643; // @[Fifo4e.scala 104:23 43:16]
- reg [7:0] active; // @[Fifo4e.scala 118:23]
- wire [7:0] _GEN_0 = {{7'd0}, icount >= 3'h1}; // @[Fifo4e.scala 121:24]
- wire [7:0] _activeSet_T_1 = _GEN_0 << in0pos; // @[Fifo4e.scala 121:24]
- wire [7:0] _GEN_1 = {{7'd0}, icount >= 3'h2}; // @[Fifo4e.scala 121:54]
- wire [7:0] _activeSet_T_3 = _GEN_1 << in1pos; // @[Fifo4e.scala 121:54]
- wire [7:0] _activeSet_T_4 = _activeSet_T_1 | _activeSet_T_3; // @[Fifo4e.scala 121:35]
- wire [7:0] _GEN_2 = {{7'd0}, icount >= 3'h3}; // @[Fifo4e.scala 122:24]
- wire [7:0] _activeSet_T_6 = _GEN_2 << in2pos; // @[Fifo4e.scala 122:24]
- wire [7:0] _activeSet_T_7 = _activeSet_T_4 | _activeSet_T_6; // @[Fifo4e.scala 121:65]
- wire [7:0] _GEN_3 = {{7'd0}, icount >= 3'h4}; // @[Fifo4e.scala 122:54]
- wire [7:0] _activeSet_T_9 = _GEN_3 << in3pos; // @[Fifo4e.scala 122:54]
- wire [7:0] _activeSet_T_10 = _activeSet_T_7 | _activeSet_T_9; // @[Fifo4e.scala 122:35]
- wire [7:0] activeSet = ivalid ? _activeSet_T_10 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _activeClr_T_1 = 8'h1 << outpos; // @[Fifo4e.scala 124:59]
- wire [7:0] activeClr = dec ? _activeClr_T_1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] _active_T = active | activeSet; // @[Fifo4e.scala 127:23]
- wire [7:0] _active_T_1 = ~activeClr; // @[Fifo4e.scala 127:38]
- wire [7:0] _active_T_2 = _active_T & _active_T_1; // @[Fifo4e.scala 127:36]
- wire [3:0] _GEN_1791 = {{1'd0}, icount}; // @[Fifo4e.scala 132:33]
- wire [3:0] _io_in_ready_T_1 = 4'h8 - _GEN_1791; // @[Fifo4e.scala 132:33]
- assign mem_tin_op_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_op_io_out_bits_MPORT_data = mem_tin_op[mem_tin_op_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_op_io_entry_0_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_op_io_entry_1_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_op_io_entry_2_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_op_io_entry_3_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_op_io_entry_4_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_op_io_entry_5_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_op_io_entry_6_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_op_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_op_io_entry_7_bits_MPORT_data = mem_tin_op[mem_tin_op_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_op_MPORT_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_addr = 3'h0;
- assign mem_tin_op_MPORT_mask = 1'h1;
- assign mem_tin_op_MPORT_en = ivalid & valid[0];
- assign mem_tin_op_MPORT_1_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_1_addr = 3'h0;
- assign mem_tin_op_MPORT_1_mask = 1'h1;
- assign mem_tin_op_MPORT_1_en = ivalid & _GEN_121;
- assign mem_tin_op_MPORT_2_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_2_addr = 3'h0;
- assign mem_tin_op_MPORT_2_mask = 1'h1;
- assign mem_tin_op_MPORT_2_en = ivalid & _GEN_137;
- assign mem_tin_op_MPORT_3_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_3_addr = 3'h0;
- assign mem_tin_op_MPORT_3_mask = 1'h1;
- assign mem_tin_op_MPORT_3_en = ivalid & _GEN_153;
- assign mem_tin_op_MPORT_4_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_4_addr = 3'h1;
- assign mem_tin_op_MPORT_4_mask = 1'h1;
- assign mem_tin_op_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_op_MPORT_5_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_5_addr = 3'h1;
- assign mem_tin_op_MPORT_5_mask = 1'h1;
- assign mem_tin_op_MPORT_5_en = ivalid & _GEN_338;
- assign mem_tin_op_MPORT_6_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_6_addr = 3'h1;
- assign mem_tin_op_MPORT_6_mask = 1'h1;
- assign mem_tin_op_MPORT_6_en = ivalid & _GEN_353;
- assign mem_tin_op_MPORT_7_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_7_addr = 3'h1;
- assign mem_tin_op_MPORT_7_mask = 1'h1;
- assign mem_tin_op_MPORT_7_en = ivalid & _GEN_368;
- assign mem_tin_op_MPORT_8_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_8_addr = 3'h2;
- assign mem_tin_op_MPORT_8_mask = 1'h1;
- assign mem_tin_op_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_op_MPORT_9_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_9_addr = 3'h2;
- assign mem_tin_op_MPORT_9_mask = 1'h1;
- assign mem_tin_op_MPORT_9_en = ivalid & _GEN_555;
- assign mem_tin_op_MPORT_10_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_10_addr = 3'h2;
- assign mem_tin_op_MPORT_10_mask = 1'h1;
- assign mem_tin_op_MPORT_10_en = ivalid & _GEN_571;
- assign mem_tin_op_MPORT_11_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_11_addr = 3'h2;
- assign mem_tin_op_MPORT_11_mask = 1'h1;
- assign mem_tin_op_MPORT_11_en = ivalid & _GEN_587;
- assign mem_tin_op_MPORT_12_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_12_addr = 3'h3;
- assign mem_tin_op_MPORT_12_mask = 1'h1;
- assign mem_tin_op_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_op_MPORT_13_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_13_addr = 3'h3;
- assign mem_tin_op_MPORT_13_mask = 1'h1;
- assign mem_tin_op_MPORT_13_en = ivalid & _GEN_779;
- assign mem_tin_op_MPORT_14_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_14_addr = 3'h3;
- assign mem_tin_op_MPORT_14_mask = 1'h1;
- assign mem_tin_op_MPORT_14_en = ivalid & _GEN_795;
- assign mem_tin_op_MPORT_15_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_15_addr = 3'h3;
- assign mem_tin_op_MPORT_15_mask = 1'h1;
- assign mem_tin_op_MPORT_15_en = ivalid & _GEN_811;
- assign mem_tin_op_MPORT_16_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_16_addr = 3'h4;
- assign mem_tin_op_MPORT_16_mask = 1'h1;
- assign mem_tin_op_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_op_MPORT_17_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_17_addr = 3'h4;
- assign mem_tin_op_MPORT_17_mask = 1'h1;
- assign mem_tin_op_MPORT_17_en = ivalid & _GEN_1003;
- assign mem_tin_op_MPORT_18_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_18_addr = 3'h4;
- assign mem_tin_op_MPORT_18_mask = 1'h1;
- assign mem_tin_op_MPORT_18_en = ivalid & _GEN_1019;
- assign mem_tin_op_MPORT_19_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_19_addr = 3'h4;
- assign mem_tin_op_MPORT_19_mask = 1'h1;
- assign mem_tin_op_MPORT_19_en = ivalid & _GEN_1035;
- assign mem_tin_op_MPORT_20_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_20_addr = 3'h5;
- assign mem_tin_op_MPORT_20_mask = 1'h1;
- assign mem_tin_op_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_op_MPORT_21_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_21_addr = 3'h5;
- assign mem_tin_op_MPORT_21_mask = 1'h1;
- assign mem_tin_op_MPORT_21_en = ivalid & _GEN_1227;
- assign mem_tin_op_MPORT_22_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_22_addr = 3'h5;
- assign mem_tin_op_MPORT_22_mask = 1'h1;
- assign mem_tin_op_MPORT_22_en = ivalid & _GEN_1243;
- assign mem_tin_op_MPORT_23_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_23_addr = 3'h5;
- assign mem_tin_op_MPORT_23_mask = 1'h1;
- assign mem_tin_op_MPORT_23_en = ivalid & _GEN_1259;
- assign mem_tin_op_MPORT_24_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_24_addr = 3'h6;
- assign mem_tin_op_MPORT_24_mask = 1'h1;
- assign mem_tin_op_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_op_MPORT_25_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_25_addr = 3'h6;
- assign mem_tin_op_MPORT_25_mask = 1'h1;
- assign mem_tin_op_MPORT_25_en = ivalid & _GEN_1451;
- assign mem_tin_op_MPORT_26_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_26_addr = 3'h6;
- assign mem_tin_op_MPORT_26_mask = 1'h1;
- assign mem_tin_op_MPORT_26_en = ivalid & _GEN_1467;
- assign mem_tin_op_MPORT_27_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_27_addr = 3'h6;
- assign mem_tin_op_MPORT_27_mask = 1'h1;
- assign mem_tin_op_MPORT_27_en = ivalid & _GEN_1483;
- assign mem_tin_op_MPORT_28_data = io_in_bits_0_bits_tin_op;
- assign mem_tin_op_MPORT_28_addr = 3'h7;
- assign mem_tin_op_MPORT_28_mask = 1'h1;
- assign mem_tin_op_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_op_MPORT_29_data = io_in_bits_1_bits_tin_op;
- assign mem_tin_op_MPORT_29_addr = 3'h7;
- assign mem_tin_op_MPORT_29_mask = 1'h1;
- assign mem_tin_op_MPORT_29_en = ivalid & _GEN_1675;
- assign mem_tin_op_MPORT_30_data = io_in_bits_2_bits_tin_op;
- assign mem_tin_op_MPORT_30_addr = 3'h7;
- assign mem_tin_op_MPORT_30_mask = 1'h1;
- assign mem_tin_op_MPORT_30_en = ivalid & _GEN_1691;
- assign mem_tin_op_MPORT_31_data = io_in_bits_3_bits_tin_op;
- assign mem_tin_op_MPORT_31_addr = 3'h7;
- assign mem_tin_op_MPORT_31_mask = 1'h1;
- assign mem_tin_op_MPORT_31_en = ivalid & _GEN_1707;
- assign mem_tin_addr_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_addr_io_out_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_addr_io_entry_0_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_addr_io_entry_1_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_addr_io_entry_2_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_addr_io_entry_3_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_addr_io_entry_4_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_addr_io_entry_5_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_addr_io_entry_6_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_addr_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_addr_io_entry_7_bits_MPORT_data = mem_tin_addr[mem_tin_addr_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_addr_MPORT_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_addr = 3'h0;
- assign mem_tin_addr_MPORT_mask = 1'h1;
- assign mem_tin_addr_MPORT_en = ivalid & valid[0];
- assign mem_tin_addr_MPORT_1_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_1_addr = 3'h0;
- assign mem_tin_addr_MPORT_1_mask = 1'h1;
- assign mem_tin_addr_MPORT_1_en = ivalid & _GEN_121;
- assign mem_tin_addr_MPORT_2_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_2_addr = 3'h0;
- assign mem_tin_addr_MPORT_2_mask = 1'h1;
- assign mem_tin_addr_MPORT_2_en = ivalid & _GEN_137;
- assign mem_tin_addr_MPORT_3_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_3_addr = 3'h0;
- assign mem_tin_addr_MPORT_3_mask = 1'h1;
- assign mem_tin_addr_MPORT_3_en = ivalid & _GEN_153;
- assign mem_tin_addr_MPORT_4_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_4_addr = 3'h1;
- assign mem_tin_addr_MPORT_4_mask = 1'h1;
- assign mem_tin_addr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_addr_MPORT_5_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_5_addr = 3'h1;
- assign mem_tin_addr_MPORT_5_mask = 1'h1;
- assign mem_tin_addr_MPORT_5_en = ivalid & _GEN_338;
- assign mem_tin_addr_MPORT_6_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_6_addr = 3'h1;
- assign mem_tin_addr_MPORT_6_mask = 1'h1;
- assign mem_tin_addr_MPORT_6_en = ivalid & _GEN_353;
- assign mem_tin_addr_MPORT_7_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_7_addr = 3'h1;
- assign mem_tin_addr_MPORT_7_mask = 1'h1;
- assign mem_tin_addr_MPORT_7_en = ivalid & _GEN_368;
- assign mem_tin_addr_MPORT_8_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_8_addr = 3'h2;
- assign mem_tin_addr_MPORT_8_mask = 1'h1;
- assign mem_tin_addr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_addr_MPORT_9_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_9_addr = 3'h2;
- assign mem_tin_addr_MPORT_9_mask = 1'h1;
- assign mem_tin_addr_MPORT_9_en = ivalid & _GEN_555;
- assign mem_tin_addr_MPORT_10_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_10_addr = 3'h2;
- assign mem_tin_addr_MPORT_10_mask = 1'h1;
- assign mem_tin_addr_MPORT_10_en = ivalid & _GEN_571;
- assign mem_tin_addr_MPORT_11_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_11_addr = 3'h2;
- assign mem_tin_addr_MPORT_11_mask = 1'h1;
- assign mem_tin_addr_MPORT_11_en = ivalid & _GEN_587;
- assign mem_tin_addr_MPORT_12_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_12_addr = 3'h3;
- assign mem_tin_addr_MPORT_12_mask = 1'h1;
- assign mem_tin_addr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_addr_MPORT_13_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_13_addr = 3'h3;
- assign mem_tin_addr_MPORT_13_mask = 1'h1;
- assign mem_tin_addr_MPORT_13_en = ivalid & _GEN_779;
- assign mem_tin_addr_MPORT_14_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_14_addr = 3'h3;
- assign mem_tin_addr_MPORT_14_mask = 1'h1;
- assign mem_tin_addr_MPORT_14_en = ivalid & _GEN_795;
- assign mem_tin_addr_MPORT_15_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_15_addr = 3'h3;
- assign mem_tin_addr_MPORT_15_mask = 1'h1;
- assign mem_tin_addr_MPORT_15_en = ivalid & _GEN_811;
- assign mem_tin_addr_MPORT_16_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_16_addr = 3'h4;
- assign mem_tin_addr_MPORT_16_mask = 1'h1;
- assign mem_tin_addr_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_addr_MPORT_17_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_17_addr = 3'h4;
- assign mem_tin_addr_MPORT_17_mask = 1'h1;
- assign mem_tin_addr_MPORT_17_en = ivalid & _GEN_1003;
- assign mem_tin_addr_MPORT_18_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_18_addr = 3'h4;
- assign mem_tin_addr_MPORT_18_mask = 1'h1;
- assign mem_tin_addr_MPORT_18_en = ivalid & _GEN_1019;
- assign mem_tin_addr_MPORT_19_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_19_addr = 3'h4;
- assign mem_tin_addr_MPORT_19_mask = 1'h1;
- assign mem_tin_addr_MPORT_19_en = ivalid & _GEN_1035;
- assign mem_tin_addr_MPORT_20_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_20_addr = 3'h5;
- assign mem_tin_addr_MPORT_20_mask = 1'h1;
- assign mem_tin_addr_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_addr_MPORT_21_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_21_addr = 3'h5;
- assign mem_tin_addr_MPORT_21_mask = 1'h1;
- assign mem_tin_addr_MPORT_21_en = ivalid & _GEN_1227;
- assign mem_tin_addr_MPORT_22_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_22_addr = 3'h5;
- assign mem_tin_addr_MPORT_22_mask = 1'h1;
- assign mem_tin_addr_MPORT_22_en = ivalid & _GEN_1243;
- assign mem_tin_addr_MPORT_23_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_23_addr = 3'h5;
- assign mem_tin_addr_MPORT_23_mask = 1'h1;
- assign mem_tin_addr_MPORT_23_en = ivalid & _GEN_1259;
- assign mem_tin_addr_MPORT_24_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_24_addr = 3'h6;
- assign mem_tin_addr_MPORT_24_mask = 1'h1;
- assign mem_tin_addr_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_addr_MPORT_25_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_25_addr = 3'h6;
- assign mem_tin_addr_MPORT_25_mask = 1'h1;
- assign mem_tin_addr_MPORT_25_en = ivalid & _GEN_1451;
- assign mem_tin_addr_MPORT_26_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_26_addr = 3'h6;
- assign mem_tin_addr_MPORT_26_mask = 1'h1;
- assign mem_tin_addr_MPORT_26_en = ivalid & _GEN_1467;
- assign mem_tin_addr_MPORT_27_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_27_addr = 3'h6;
- assign mem_tin_addr_MPORT_27_mask = 1'h1;
- assign mem_tin_addr_MPORT_27_en = ivalid & _GEN_1483;
- assign mem_tin_addr_MPORT_28_data = io_in_bits_0_bits_tin_addr;
- assign mem_tin_addr_MPORT_28_addr = 3'h7;
- assign mem_tin_addr_MPORT_28_mask = 1'h1;
- assign mem_tin_addr_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_addr_MPORT_29_data = io_in_bits_1_bits_tin_addr;
- assign mem_tin_addr_MPORT_29_addr = 3'h7;
- assign mem_tin_addr_MPORT_29_mask = 1'h1;
- assign mem_tin_addr_MPORT_29_en = ivalid & _GEN_1675;
- assign mem_tin_addr_MPORT_30_data = io_in_bits_2_bits_tin_addr;
- assign mem_tin_addr_MPORT_30_addr = 3'h7;
- assign mem_tin_addr_MPORT_30_mask = 1'h1;
- assign mem_tin_addr_MPORT_30_en = ivalid & _GEN_1691;
- assign mem_tin_addr_MPORT_31_data = io_in_bits_3_bits_tin_addr;
- assign mem_tin_addr_MPORT_31_addr = 3'h7;
- assign mem_tin_addr_MPORT_31_mask = 1'h1;
- assign mem_tin_addr_MPORT_31_en = ivalid & _GEN_1707;
- assign mem_tin_offset_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_offset_io_out_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_offset_io_entry_0_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_offset_io_entry_1_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_offset_io_entry_2_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_offset_io_entry_3_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_offset_io_entry_4_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_offset_io_entry_5_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_offset_io_entry_6_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_offset_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_offset_io_entry_7_bits_MPORT_data = mem_tin_offset[mem_tin_offset_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_offset_MPORT_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_addr = 3'h0;
- assign mem_tin_offset_MPORT_mask = 1'h1;
- assign mem_tin_offset_MPORT_en = ivalid & valid[0];
- assign mem_tin_offset_MPORT_1_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_1_addr = 3'h0;
- assign mem_tin_offset_MPORT_1_mask = 1'h1;
- assign mem_tin_offset_MPORT_1_en = ivalid & _GEN_121;
- assign mem_tin_offset_MPORT_2_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_2_addr = 3'h0;
- assign mem_tin_offset_MPORT_2_mask = 1'h1;
- assign mem_tin_offset_MPORT_2_en = ivalid & _GEN_137;
- assign mem_tin_offset_MPORT_3_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_3_addr = 3'h0;
- assign mem_tin_offset_MPORT_3_mask = 1'h1;
- assign mem_tin_offset_MPORT_3_en = ivalid & _GEN_153;
- assign mem_tin_offset_MPORT_4_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_4_addr = 3'h1;
- assign mem_tin_offset_MPORT_4_mask = 1'h1;
- assign mem_tin_offset_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_offset_MPORT_5_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_5_addr = 3'h1;
- assign mem_tin_offset_MPORT_5_mask = 1'h1;
- assign mem_tin_offset_MPORT_5_en = ivalid & _GEN_338;
- assign mem_tin_offset_MPORT_6_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_6_addr = 3'h1;
- assign mem_tin_offset_MPORT_6_mask = 1'h1;
- assign mem_tin_offset_MPORT_6_en = ivalid & _GEN_353;
- assign mem_tin_offset_MPORT_7_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_7_addr = 3'h1;
- assign mem_tin_offset_MPORT_7_mask = 1'h1;
- assign mem_tin_offset_MPORT_7_en = ivalid & _GEN_368;
- assign mem_tin_offset_MPORT_8_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_8_addr = 3'h2;
- assign mem_tin_offset_MPORT_8_mask = 1'h1;
- assign mem_tin_offset_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_offset_MPORT_9_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_9_addr = 3'h2;
- assign mem_tin_offset_MPORT_9_mask = 1'h1;
- assign mem_tin_offset_MPORT_9_en = ivalid & _GEN_555;
- assign mem_tin_offset_MPORT_10_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_10_addr = 3'h2;
- assign mem_tin_offset_MPORT_10_mask = 1'h1;
- assign mem_tin_offset_MPORT_10_en = ivalid & _GEN_571;
- assign mem_tin_offset_MPORT_11_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_11_addr = 3'h2;
- assign mem_tin_offset_MPORT_11_mask = 1'h1;
- assign mem_tin_offset_MPORT_11_en = ivalid & _GEN_587;
- assign mem_tin_offset_MPORT_12_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_12_addr = 3'h3;
- assign mem_tin_offset_MPORT_12_mask = 1'h1;
- assign mem_tin_offset_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_offset_MPORT_13_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_13_addr = 3'h3;
- assign mem_tin_offset_MPORT_13_mask = 1'h1;
- assign mem_tin_offset_MPORT_13_en = ivalid & _GEN_779;
- assign mem_tin_offset_MPORT_14_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_14_addr = 3'h3;
- assign mem_tin_offset_MPORT_14_mask = 1'h1;
- assign mem_tin_offset_MPORT_14_en = ivalid & _GEN_795;
- assign mem_tin_offset_MPORT_15_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_15_addr = 3'h3;
- assign mem_tin_offset_MPORT_15_mask = 1'h1;
- assign mem_tin_offset_MPORT_15_en = ivalid & _GEN_811;
- assign mem_tin_offset_MPORT_16_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_16_addr = 3'h4;
- assign mem_tin_offset_MPORT_16_mask = 1'h1;
- assign mem_tin_offset_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_offset_MPORT_17_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_17_addr = 3'h4;
- assign mem_tin_offset_MPORT_17_mask = 1'h1;
- assign mem_tin_offset_MPORT_17_en = ivalid & _GEN_1003;
- assign mem_tin_offset_MPORT_18_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_18_addr = 3'h4;
- assign mem_tin_offset_MPORT_18_mask = 1'h1;
- assign mem_tin_offset_MPORT_18_en = ivalid & _GEN_1019;
- assign mem_tin_offset_MPORT_19_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_19_addr = 3'h4;
- assign mem_tin_offset_MPORT_19_mask = 1'h1;
- assign mem_tin_offset_MPORT_19_en = ivalid & _GEN_1035;
- assign mem_tin_offset_MPORT_20_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_20_addr = 3'h5;
- assign mem_tin_offset_MPORT_20_mask = 1'h1;
- assign mem_tin_offset_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_offset_MPORT_21_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_21_addr = 3'h5;
- assign mem_tin_offset_MPORT_21_mask = 1'h1;
- assign mem_tin_offset_MPORT_21_en = ivalid & _GEN_1227;
- assign mem_tin_offset_MPORT_22_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_22_addr = 3'h5;
- assign mem_tin_offset_MPORT_22_mask = 1'h1;
- assign mem_tin_offset_MPORT_22_en = ivalid & _GEN_1243;
- assign mem_tin_offset_MPORT_23_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_23_addr = 3'h5;
- assign mem_tin_offset_MPORT_23_mask = 1'h1;
- assign mem_tin_offset_MPORT_23_en = ivalid & _GEN_1259;
- assign mem_tin_offset_MPORT_24_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_24_addr = 3'h6;
- assign mem_tin_offset_MPORT_24_mask = 1'h1;
- assign mem_tin_offset_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_offset_MPORT_25_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_25_addr = 3'h6;
- assign mem_tin_offset_MPORT_25_mask = 1'h1;
- assign mem_tin_offset_MPORT_25_en = ivalid & _GEN_1451;
- assign mem_tin_offset_MPORT_26_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_26_addr = 3'h6;
- assign mem_tin_offset_MPORT_26_mask = 1'h1;
- assign mem_tin_offset_MPORT_26_en = ivalid & _GEN_1467;
- assign mem_tin_offset_MPORT_27_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_27_addr = 3'h6;
- assign mem_tin_offset_MPORT_27_mask = 1'h1;
- assign mem_tin_offset_MPORT_27_en = ivalid & _GEN_1483;
- assign mem_tin_offset_MPORT_28_data = io_in_bits_0_bits_tin_offset;
- assign mem_tin_offset_MPORT_28_addr = 3'h7;
- assign mem_tin_offset_MPORT_28_mask = 1'h1;
- assign mem_tin_offset_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_offset_MPORT_29_data = io_in_bits_1_bits_tin_offset;
- assign mem_tin_offset_MPORT_29_addr = 3'h7;
- assign mem_tin_offset_MPORT_29_mask = 1'h1;
- assign mem_tin_offset_MPORT_29_en = ivalid & _GEN_1675;
- assign mem_tin_offset_MPORT_30_data = io_in_bits_2_bits_tin_offset;
- assign mem_tin_offset_MPORT_30_addr = 3'h7;
- assign mem_tin_offset_MPORT_30_mask = 1'h1;
- assign mem_tin_offset_MPORT_30_en = ivalid & _GEN_1691;
- assign mem_tin_offset_MPORT_31_data = io_in_bits_3_bits_tin_offset;
- assign mem_tin_offset_MPORT_31_addr = 3'h7;
- assign mem_tin_offset_MPORT_31_mask = 1'h1;
- assign mem_tin_offset_MPORT_31_en = ivalid & _GEN_1707;
- assign mem_tin_remain_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_remain_io_out_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_remain_io_entry_0_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_remain_io_entry_1_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_remain_io_entry_2_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_remain_io_entry_3_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_remain_io_entry_4_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_remain_io_entry_5_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_remain_io_entry_6_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_remain_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_remain_io_entry_7_bits_MPORT_data = mem_tin_remain[mem_tin_remain_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_remain_MPORT_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_addr = 3'h0;
- assign mem_tin_remain_MPORT_mask = 1'h1;
- assign mem_tin_remain_MPORT_en = ivalid & valid[0];
- assign mem_tin_remain_MPORT_1_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_1_addr = 3'h0;
- assign mem_tin_remain_MPORT_1_mask = 1'h1;
- assign mem_tin_remain_MPORT_1_en = ivalid & _GEN_121;
- assign mem_tin_remain_MPORT_2_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_2_addr = 3'h0;
- assign mem_tin_remain_MPORT_2_mask = 1'h1;
- assign mem_tin_remain_MPORT_2_en = ivalid & _GEN_137;
- assign mem_tin_remain_MPORT_3_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_3_addr = 3'h0;
- assign mem_tin_remain_MPORT_3_mask = 1'h1;
- assign mem_tin_remain_MPORT_3_en = ivalid & _GEN_153;
- assign mem_tin_remain_MPORT_4_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_4_addr = 3'h1;
- assign mem_tin_remain_MPORT_4_mask = 1'h1;
- assign mem_tin_remain_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_remain_MPORT_5_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_5_addr = 3'h1;
- assign mem_tin_remain_MPORT_5_mask = 1'h1;
- assign mem_tin_remain_MPORT_5_en = ivalid & _GEN_338;
- assign mem_tin_remain_MPORT_6_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_6_addr = 3'h1;
- assign mem_tin_remain_MPORT_6_mask = 1'h1;
- assign mem_tin_remain_MPORT_6_en = ivalid & _GEN_353;
- assign mem_tin_remain_MPORT_7_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_7_addr = 3'h1;
- assign mem_tin_remain_MPORT_7_mask = 1'h1;
- assign mem_tin_remain_MPORT_7_en = ivalid & _GEN_368;
- assign mem_tin_remain_MPORT_8_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_8_addr = 3'h2;
- assign mem_tin_remain_MPORT_8_mask = 1'h1;
- assign mem_tin_remain_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_remain_MPORT_9_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_9_addr = 3'h2;
- assign mem_tin_remain_MPORT_9_mask = 1'h1;
- assign mem_tin_remain_MPORT_9_en = ivalid & _GEN_555;
- assign mem_tin_remain_MPORT_10_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_10_addr = 3'h2;
- assign mem_tin_remain_MPORT_10_mask = 1'h1;
- assign mem_tin_remain_MPORT_10_en = ivalid & _GEN_571;
- assign mem_tin_remain_MPORT_11_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_11_addr = 3'h2;
- assign mem_tin_remain_MPORT_11_mask = 1'h1;
- assign mem_tin_remain_MPORT_11_en = ivalid & _GEN_587;
- assign mem_tin_remain_MPORT_12_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_12_addr = 3'h3;
- assign mem_tin_remain_MPORT_12_mask = 1'h1;
- assign mem_tin_remain_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_remain_MPORT_13_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_13_addr = 3'h3;
- assign mem_tin_remain_MPORT_13_mask = 1'h1;
- assign mem_tin_remain_MPORT_13_en = ivalid & _GEN_779;
- assign mem_tin_remain_MPORT_14_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_14_addr = 3'h3;
- assign mem_tin_remain_MPORT_14_mask = 1'h1;
- assign mem_tin_remain_MPORT_14_en = ivalid & _GEN_795;
- assign mem_tin_remain_MPORT_15_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_15_addr = 3'h3;
- assign mem_tin_remain_MPORT_15_mask = 1'h1;
- assign mem_tin_remain_MPORT_15_en = ivalid & _GEN_811;
- assign mem_tin_remain_MPORT_16_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_16_addr = 3'h4;
- assign mem_tin_remain_MPORT_16_mask = 1'h1;
- assign mem_tin_remain_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_remain_MPORT_17_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_17_addr = 3'h4;
- assign mem_tin_remain_MPORT_17_mask = 1'h1;
- assign mem_tin_remain_MPORT_17_en = ivalid & _GEN_1003;
- assign mem_tin_remain_MPORT_18_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_18_addr = 3'h4;
- assign mem_tin_remain_MPORT_18_mask = 1'h1;
- assign mem_tin_remain_MPORT_18_en = ivalid & _GEN_1019;
- assign mem_tin_remain_MPORT_19_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_19_addr = 3'h4;
- assign mem_tin_remain_MPORT_19_mask = 1'h1;
- assign mem_tin_remain_MPORT_19_en = ivalid & _GEN_1035;
- assign mem_tin_remain_MPORT_20_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_20_addr = 3'h5;
- assign mem_tin_remain_MPORT_20_mask = 1'h1;
- assign mem_tin_remain_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_remain_MPORT_21_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_21_addr = 3'h5;
- assign mem_tin_remain_MPORT_21_mask = 1'h1;
- assign mem_tin_remain_MPORT_21_en = ivalid & _GEN_1227;
- assign mem_tin_remain_MPORT_22_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_22_addr = 3'h5;
- assign mem_tin_remain_MPORT_22_mask = 1'h1;
- assign mem_tin_remain_MPORT_22_en = ivalid & _GEN_1243;
- assign mem_tin_remain_MPORT_23_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_23_addr = 3'h5;
- assign mem_tin_remain_MPORT_23_mask = 1'h1;
- assign mem_tin_remain_MPORT_23_en = ivalid & _GEN_1259;
- assign mem_tin_remain_MPORT_24_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_24_addr = 3'h6;
- assign mem_tin_remain_MPORT_24_mask = 1'h1;
- assign mem_tin_remain_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_remain_MPORT_25_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_25_addr = 3'h6;
- assign mem_tin_remain_MPORT_25_mask = 1'h1;
- assign mem_tin_remain_MPORT_25_en = ivalid & _GEN_1451;
- assign mem_tin_remain_MPORT_26_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_26_addr = 3'h6;
- assign mem_tin_remain_MPORT_26_mask = 1'h1;
- assign mem_tin_remain_MPORT_26_en = ivalid & _GEN_1467;
- assign mem_tin_remain_MPORT_27_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_27_addr = 3'h6;
- assign mem_tin_remain_MPORT_27_mask = 1'h1;
- assign mem_tin_remain_MPORT_27_en = ivalid & _GEN_1483;
- assign mem_tin_remain_MPORT_28_data = io_in_bits_0_bits_tin_remain;
- assign mem_tin_remain_MPORT_28_addr = 3'h7;
- assign mem_tin_remain_MPORT_28_mask = 1'h1;
- assign mem_tin_remain_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_remain_MPORT_29_data = io_in_bits_1_bits_tin_remain;
- assign mem_tin_remain_MPORT_29_addr = 3'h7;
- assign mem_tin_remain_MPORT_29_mask = 1'h1;
- assign mem_tin_remain_MPORT_29_en = ivalid & _GEN_1675;
- assign mem_tin_remain_MPORT_30_data = io_in_bits_2_bits_tin_remain;
- assign mem_tin_remain_MPORT_30_addr = 3'h7;
- assign mem_tin_remain_MPORT_30_mask = 1'h1;
- assign mem_tin_remain_MPORT_30_en = ivalid & _GEN_1691;
- assign mem_tin_remain_MPORT_31_data = io_in_bits_3_bits_tin_remain;
- assign mem_tin_remain_MPORT_31_addr = 3'h7;
- assign mem_tin_remain_MPORT_31_mask = 1'h1;
- assign mem_tin_remain_MPORT_31_en = ivalid & _GEN_1707;
- assign mem_tin_vs_valid_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vs_valid_io_out_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vs_valid_io_entry_0_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vs_valid_io_entry_1_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vs_valid_io_entry_2_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vs_valid_io_entry_3_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vs_valid_io_entry_4_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vs_valid_io_entry_5_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vs_valid_io_entry_6_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_valid_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vs_valid_io_entry_7_bits_MPORT_data = mem_tin_vs_valid[mem_tin_vs_valid_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_valid_MPORT_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_addr = 3'h0;
- assign mem_tin_vs_valid_MPORT_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_en = ivalid & valid[0];
- assign mem_tin_vs_valid_MPORT_1_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_1_addr = 3'h0;
- assign mem_tin_vs_valid_MPORT_1_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_1_en = ivalid & _GEN_121;
- assign mem_tin_vs_valid_MPORT_2_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_2_addr = 3'h0;
- assign mem_tin_vs_valid_MPORT_2_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_2_en = ivalid & _GEN_137;
- assign mem_tin_vs_valid_MPORT_3_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_3_addr = 3'h0;
- assign mem_tin_vs_valid_MPORT_3_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_3_en = ivalid & _GEN_153;
- assign mem_tin_vs_valid_MPORT_4_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_4_addr = 3'h1;
- assign mem_tin_vs_valid_MPORT_4_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vs_valid_MPORT_5_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_5_addr = 3'h1;
- assign mem_tin_vs_valid_MPORT_5_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_5_en = ivalid & _GEN_338;
- assign mem_tin_vs_valid_MPORT_6_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_6_addr = 3'h1;
- assign mem_tin_vs_valid_MPORT_6_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_6_en = ivalid & _GEN_353;
- assign mem_tin_vs_valid_MPORT_7_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_7_addr = 3'h1;
- assign mem_tin_vs_valid_MPORT_7_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_7_en = ivalid & _GEN_368;
- assign mem_tin_vs_valid_MPORT_8_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_8_addr = 3'h2;
- assign mem_tin_vs_valid_MPORT_8_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vs_valid_MPORT_9_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_9_addr = 3'h2;
- assign mem_tin_vs_valid_MPORT_9_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_9_en = ivalid & _GEN_555;
- assign mem_tin_vs_valid_MPORT_10_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_10_addr = 3'h2;
- assign mem_tin_vs_valid_MPORT_10_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_10_en = ivalid & _GEN_571;
- assign mem_tin_vs_valid_MPORT_11_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_11_addr = 3'h2;
- assign mem_tin_vs_valid_MPORT_11_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_11_en = ivalid & _GEN_587;
- assign mem_tin_vs_valid_MPORT_12_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_12_addr = 3'h3;
- assign mem_tin_vs_valid_MPORT_12_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vs_valid_MPORT_13_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_13_addr = 3'h3;
- assign mem_tin_vs_valid_MPORT_13_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_13_en = ivalid & _GEN_779;
- assign mem_tin_vs_valid_MPORT_14_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_14_addr = 3'h3;
- assign mem_tin_vs_valid_MPORT_14_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_14_en = ivalid & _GEN_795;
- assign mem_tin_vs_valid_MPORT_15_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_15_addr = 3'h3;
- assign mem_tin_vs_valid_MPORT_15_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_15_en = ivalid & _GEN_811;
- assign mem_tin_vs_valid_MPORT_16_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_16_addr = 3'h4;
- assign mem_tin_vs_valid_MPORT_16_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vs_valid_MPORT_17_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_17_addr = 3'h4;
- assign mem_tin_vs_valid_MPORT_17_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_17_en = ivalid & _GEN_1003;
- assign mem_tin_vs_valid_MPORT_18_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_18_addr = 3'h4;
- assign mem_tin_vs_valid_MPORT_18_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_18_en = ivalid & _GEN_1019;
- assign mem_tin_vs_valid_MPORT_19_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_19_addr = 3'h4;
- assign mem_tin_vs_valid_MPORT_19_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_19_en = ivalid & _GEN_1035;
- assign mem_tin_vs_valid_MPORT_20_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_20_addr = 3'h5;
- assign mem_tin_vs_valid_MPORT_20_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vs_valid_MPORT_21_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_21_addr = 3'h5;
- assign mem_tin_vs_valid_MPORT_21_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_21_en = ivalid & _GEN_1227;
- assign mem_tin_vs_valid_MPORT_22_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_22_addr = 3'h5;
- assign mem_tin_vs_valid_MPORT_22_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_22_en = ivalid & _GEN_1243;
- assign mem_tin_vs_valid_MPORT_23_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_23_addr = 3'h5;
- assign mem_tin_vs_valid_MPORT_23_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_23_en = ivalid & _GEN_1259;
- assign mem_tin_vs_valid_MPORT_24_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_24_addr = 3'h6;
- assign mem_tin_vs_valid_MPORT_24_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vs_valid_MPORT_25_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_25_addr = 3'h6;
- assign mem_tin_vs_valid_MPORT_25_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_25_en = ivalid & _GEN_1451;
- assign mem_tin_vs_valid_MPORT_26_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_26_addr = 3'h6;
- assign mem_tin_vs_valid_MPORT_26_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_26_en = ivalid & _GEN_1467;
- assign mem_tin_vs_valid_MPORT_27_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_27_addr = 3'h6;
- assign mem_tin_vs_valid_MPORT_27_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_27_en = ivalid & _GEN_1483;
- assign mem_tin_vs_valid_MPORT_28_data = io_in_bits_0_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_28_addr = 3'h7;
- assign mem_tin_vs_valid_MPORT_28_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vs_valid_MPORT_29_data = io_in_bits_1_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_29_addr = 3'h7;
- assign mem_tin_vs_valid_MPORT_29_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_29_en = ivalid & _GEN_1675;
- assign mem_tin_vs_valid_MPORT_30_data = io_in_bits_2_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_30_addr = 3'h7;
- assign mem_tin_vs_valid_MPORT_30_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_30_en = ivalid & _GEN_1691;
- assign mem_tin_vs_valid_MPORT_31_data = io_in_bits_3_bits_tin_vs_valid;
- assign mem_tin_vs_valid_MPORT_31_addr = 3'h7;
- assign mem_tin_vs_valid_MPORT_31_mask = 1'h1;
- assign mem_tin_vs_valid_MPORT_31_en = ivalid & _GEN_1707;
- assign mem_tin_vs_addr_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vs_addr_io_out_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vs_addr_io_entry_0_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vs_addr_io_entry_1_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vs_addr_io_entry_2_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vs_addr_io_entry_3_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vs_addr_io_entry_4_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vs_addr_io_entry_5_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vs_addr_io_entry_6_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_addr_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vs_addr_io_entry_7_bits_MPORT_data = mem_tin_vs_addr[mem_tin_vs_addr_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_addr_MPORT_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_addr = 3'h0;
- assign mem_tin_vs_addr_MPORT_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_en = ivalid & valid[0];
- assign mem_tin_vs_addr_MPORT_1_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_1_addr = 3'h0;
- assign mem_tin_vs_addr_MPORT_1_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_1_en = ivalid & _GEN_121;
- assign mem_tin_vs_addr_MPORT_2_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_2_addr = 3'h0;
- assign mem_tin_vs_addr_MPORT_2_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_2_en = ivalid & _GEN_137;
- assign mem_tin_vs_addr_MPORT_3_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_3_addr = 3'h0;
- assign mem_tin_vs_addr_MPORT_3_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_3_en = ivalid & _GEN_153;
- assign mem_tin_vs_addr_MPORT_4_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_4_addr = 3'h1;
- assign mem_tin_vs_addr_MPORT_4_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vs_addr_MPORT_5_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_5_addr = 3'h1;
- assign mem_tin_vs_addr_MPORT_5_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_5_en = ivalid & _GEN_338;
- assign mem_tin_vs_addr_MPORT_6_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_6_addr = 3'h1;
- assign mem_tin_vs_addr_MPORT_6_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_6_en = ivalid & _GEN_353;
- assign mem_tin_vs_addr_MPORT_7_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_7_addr = 3'h1;
- assign mem_tin_vs_addr_MPORT_7_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_7_en = ivalid & _GEN_368;
- assign mem_tin_vs_addr_MPORT_8_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_8_addr = 3'h2;
- assign mem_tin_vs_addr_MPORT_8_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vs_addr_MPORT_9_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_9_addr = 3'h2;
- assign mem_tin_vs_addr_MPORT_9_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_9_en = ivalid & _GEN_555;
- assign mem_tin_vs_addr_MPORT_10_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_10_addr = 3'h2;
- assign mem_tin_vs_addr_MPORT_10_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_10_en = ivalid & _GEN_571;
- assign mem_tin_vs_addr_MPORT_11_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_11_addr = 3'h2;
- assign mem_tin_vs_addr_MPORT_11_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_11_en = ivalid & _GEN_587;
- assign mem_tin_vs_addr_MPORT_12_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_12_addr = 3'h3;
- assign mem_tin_vs_addr_MPORT_12_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vs_addr_MPORT_13_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_13_addr = 3'h3;
- assign mem_tin_vs_addr_MPORT_13_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_13_en = ivalid & _GEN_779;
- assign mem_tin_vs_addr_MPORT_14_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_14_addr = 3'h3;
- assign mem_tin_vs_addr_MPORT_14_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_14_en = ivalid & _GEN_795;
- assign mem_tin_vs_addr_MPORT_15_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_15_addr = 3'h3;
- assign mem_tin_vs_addr_MPORT_15_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_15_en = ivalid & _GEN_811;
- assign mem_tin_vs_addr_MPORT_16_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_16_addr = 3'h4;
- assign mem_tin_vs_addr_MPORT_16_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vs_addr_MPORT_17_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_17_addr = 3'h4;
- assign mem_tin_vs_addr_MPORT_17_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_17_en = ivalid & _GEN_1003;
- assign mem_tin_vs_addr_MPORT_18_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_18_addr = 3'h4;
- assign mem_tin_vs_addr_MPORT_18_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_18_en = ivalid & _GEN_1019;
- assign mem_tin_vs_addr_MPORT_19_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_19_addr = 3'h4;
- assign mem_tin_vs_addr_MPORT_19_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_19_en = ivalid & _GEN_1035;
- assign mem_tin_vs_addr_MPORT_20_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_20_addr = 3'h5;
- assign mem_tin_vs_addr_MPORT_20_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vs_addr_MPORT_21_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_21_addr = 3'h5;
- assign mem_tin_vs_addr_MPORT_21_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_21_en = ivalid & _GEN_1227;
- assign mem_tin_vs_addr_MPORT_22_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_22_addr = 3'h5;
- assign mem_tin_vs_addr_MPORT_22_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_22_en = ivalid & _GEN_1243;
- assign mem_tin_vs_addr_MPORT_23_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_23_addr = 3'h5;
- assign mem_tin_vs_addr_MPORT_23_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_23_en = ivalid & _GEN_1259;
- assign mem_tin_vs_addr_MPORT_24_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_24_addr = 3'h6;
- assign mem_tin_vs_addr_MPORT_24_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vs_addr_MPORT_25_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_25_addr = 3'h6;
- assign mem_tin_vs_addr_MPORT_25_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_25_en = ivalid & _GEN_1451;
- assign mem_tin_vs_addr_MPORT_26_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_26_addr = 3'h6;
- assign mem_tin_vs_addr_MPORT_26_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_26_en = ivalid & _GEN_1467;
- assign mem_tin_vs_addr_MPORT_27_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_27_addr = 3'h6;
- assign mem_tin_vs_addr_MPORT_27_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_27_en = ivalid & _GEN_1483;
- assign mem_tin_vs_addr_MPORT_28_data = io_in_bits_0_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_28_addr = 3'h7;
- assign mem_tin_vs_addr_MPORT_28_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vs_addr_MPORT_29_data = io_in_bits_1_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_29_addr = 3'h7;
- assign mem_tin_vs_addr_MPORT_29_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_29_en = ivalid & _GEN_1675;
- assign mem_tin_vs_addr_MPORT_30_data = io_in_bits_2_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_30_addr = 3'h7;
- assign mem_tin_vs_addr_MPORT_30_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_30_en = ivalid & _GEN_1691;
- assign mem_tin_vs_addr_MPORT_31_data = io_in_bits_3_bits_tin_vs_addr;
- assign mem_tin_vs_addr_MPORT_31_addr = 3'h7;
- assign mem_tin_vs_addr_MPORT_31_mask = 1'h1;
- assign mem_tin_vs_addr_MPORT_31_en = ivalid & _GEN_1707;
- assign mem_tin_vs_tag_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_vs_tag_io_out_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_vs_tag_io_entry_0_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_vs_tag_io_entry_1_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_vs_tag_io_entry_2_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_vs_tag_io_entry_3_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_vs_tag_io_entry_4_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_vs_tag_io_entry_5_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_vs_tag_io_entry_6_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_vs_tag_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_vs_tag_io_entry_7_bits_MPORT_data = mem_tin_vs_tag[mem_tin_vs_tag_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_vs_tag_MPORT_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_addr = 3'h0;
- assign mem_tin_vs_tag_MPORT_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_en = ivalid & valid[0];
- assign mem_tin_vs_tag_MPORT_1_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_1_addr = 3'h0;
- assign mem_tin_vs_tag_MPORT_1_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_1_en = ivalid & _GEN_121;
- assign mem_tin_vs_tag_MPORT_2_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_2_addr = 3'h0;
- assign mem_tin_vs_tag_MPORT_2_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_2_en = ivalid & _GEN_137;
- assign mem_tin_vs_tag_MPORT_3_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_3_addr = 3'h0;
- assign mem_tin_vs_tag_MPORT_3_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_3_en = ivalid & _GEN_153;
- assign mem_tin_vs_tag_MPORT_4_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_4_addr = 3'h1;
- assign mem_tin_vs_tag_MPORT_4_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_vs_tag_MPORT_5_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_5_addr = 3'h1;
- assign mem_tin_vs_tag_MPORT_5_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_5_en = ivalid & _GEN_338;
- assign mem_tin_vs_tag_MPORT_6_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_6_addr = 3'h1;
- assign mem_tin_vs_tag_MPORT_6_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_6_en = ivalid & _GEN_353;
- assign mem_tin_vs_tag_MPORT_7_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_7_addr = 3'h1;
- assign mem_tin_vs_tag_MPORT_7_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_7_en = ivalid & _GEN_368;
- assign mem_tin_vs_tag_MPORT_8_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_8_addr = 3'h2;
- assign mem_tin_vs_tag_MPORT_8_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_vs_tag_MPORT_9_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_9_addr = 3'h2;
- assign mem_tin_vs_tag_MPORT_9_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_9_en = ivalid & _GEN_555;
- assign mem_tin_vs_tag_MPORT_10_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_10_addr = 3'h2;
- assign mem_tin_vs_tag_MPORT_10_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_10_en = ivalid & _GEN_571;
- assign mem_tin_vs_tag_MPORT_11_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_11_addr = 3'h2;
- assign mem_tin_vs_tag_MPORT_11_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_11_en = ivalid & _GEN_587;
- assign mem_tin_vs_tag_MPORT_12_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_12_addr = 3'h3;
- assign mem_tin_vs_tag_MPORT_12_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_vs_tag_MPORT_13_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_13_addr = 3'h3;
- assign mem_tin_vs_tag_MPORT_13_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_13_en = ivalid & _GEN_779;
- assign mem_tin_vs_tag_MPORT_14_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_14_addr = 3'h3;
- assign mem_tin_vs_tag_MPORT_14_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_14_en = ivalid & _GEN_795;
- assign mem_tin_vs_tag_MPORT_15_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_15_addr = 3'h3;
- assign mem_tin_vs_tag_MPORT_15_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_15_en = ivalid & _GEN_811;
- assign mem_tin_vs_tag_MPORT_16_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_16_addr = 3'h4;
- assign mem_tin_vs_tag_MPORT_16_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_vs_tag_MPORT_17_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_17_addr = 3'h4;
- assign mem_tin_vs_tag_MPORT_17_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_17_en = ivalid & _GEN_1003;
- assign mem_tin_vs_tag_MPORT_18_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_18_addr = 3'h4;
- assign mem_tin_vs_tag_MPORT_18_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_18_en = ivalid & _GEN_1019;
- assign mem_tin_vs_tag_MPORT_19_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_19_addr = 3'h4;
- assign mem_tin_vs_tag_MPORT_19_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_19_en = ivalid & _GEN_1035;
- assign mem_tin_vs_tag_MPORT_20_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_20_addr = 3'h5;
- assign mem_tin_vs_tag_MPORT_20_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_vs_tag_MPORT_21_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_21_addr = 3'h5;
- assign mem_tin_vs_tag_MPORT_21_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_21_en = ivalid & _GEN_1227;
- assign mem_tin_vs_tag_MPORT_22_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_22_addr = 3'h5;
- assign mem_tin_vs_tag_MPORT_22_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_22_en = ivalid & _GEN_1243;
- assign mem_tin_vs_tag_MPORT_23_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_23_addr = 3'h5;
- assign mem_tin_vs_tag_MPORT_23_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_23_en = ivalid & _GEN_1259;
- assign mem_tin_vs_tag_MPORT_24_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_24_addr = 3'h6;
- assign mem_tin_vs_tag_MPORT_24_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_vs_tag_MPORT_25_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_25_addr = 3'h6;
- assign mem_tin_vs_tag_MPORT_25_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_25_en = ivalid & _GEN_1451;
- assign mem_tin_vs_tag_MPORT_26_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_26_addr = 3'h6;
- assign mem_tin_vs_tag_MPORT_26_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_26_en = ivalid & _GEN_1467;
- assign mem_tin_vs_tag_MPORT_27_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_27_addr = 3'h6;
- assign mem_tin_vs_tag_MPORT_27_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_27_en = ivalid & _GEN_1483;
- assign mem_tin_vs_tag_MPORT_28_data = io_in_bits_0_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_28_addr = 3'h7;
- assign mem_tin_vs_tag_MPORT_28_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_vs_tag_MPORT_29_data = io_in_bits_1_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_29_addr = 3'h7;
- assign mem_tin_vs_tag_MPORT_29_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_29_en = ivalid & _GEN_1675;
- assign mem_tin_vs_tag_MPORT_30_data = io_in_bits_2_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_30_addr = 3'h7;
- assign mem_tin_vs_tag_MPORT_30_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_30_en = ivalid & _GEN_1691;
- assign mem_tin_vs_tag_MPORT_31_data = io_in_bits_3_bits_tin_vs_tag;
- assign mem_tin_vs_tag_MPORT_31_addr = 3'h7;
- assign mem_tin_vs_tag_MPORT_31_mask = 1'h1;
- assign mem_tin_vs_tag_MPORT_31_en = ivalid & _GEN_1707;
- assign mem_tin_quad_io_out_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_out_bits_MPORT_addr = outpos;
- assign mem_tin_quad_io_out_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_tin_quad_io_entry_0_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_tin_quad_io_entry_1_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_tin_quad_io_entry_2_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_tin_quad_io_entry_3_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_tin_quad_io_entry_4_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_tin_quad_io_entry_5_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_tin_quad_io_entry_6_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_tin_quad_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_tin_quad_io_entry_7_bits_MPORT_data = mem_tin_quad[mem_tin_quad_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_tin_quad_MPORT_data = 2'h0;
- assign mem_tin_quad_MPORT_addr = 3'h0;
- assign mem_tin_quad_MPORT_mask = 1'h1;
- assign mem_tin_quad_MPORT_en = ivalid & valid[0];
- assign mem_tin_quad_MPORT_1_data = 2'h0;
- assign mem_tin_quad_MPORT_1_addr = 3'h0;
- assign mem_tin_quad_MPORT_1_mask = 1'h1;
- assign mem_tin_quad_MPORT_1_en = ivalid & _GEN_121;
- assign mem_tin_quad_MPORT_2_data = 2'h0;
- assign mem_tin_quad_MPORT_2_addr = 3'h0;
- assign mem_tin_quad_MPORT_2_mask = 1'h1;
- assign mem_tin_quad_MPORT_2_en = ivalid & _GEN_137;
- assign mem_tin_quad_MPORT_3_data = 2'h0;
- assign mem_tin_quad_MPORT_3_addr = 3'h0;
- assign mem_tin_quad_MPORT_3_mask = 1'h1;
- assign mem_tin_quad_MPORT_3_en = ivalid & _GEN_153;
- assign mem_tin_quad_MPORT_4_data = 2'h0;
- assign mem_tin_quad_MPORT_4_addr = 3'h1;
- assign mem_tin_quad_MPORT_4_mask = 1'h1;
- assign mem_tin_quad_MPORT_4_en = ivalid & valid_1[0];
- assign mem_tin_quad_MPORT_5_data = 2'h0;
- assign mem_tin_quad_MPORT_5_addr = 3'h1;
- assign mem_tin_quad_MPORT_5_mask = 1'h1;
- assign mem_tin_quad_MPORT_5_en = ivalid & _GEN_338;
- assign mem_tin_quad_MPORT_6_data = 2'h0;
- assign mem_tin_quad_MPORT_6_addr = 3'h1;
- assign mem_tin_quad_MPORT_6_mask = 1'h1;
- assign mem_tin_quad_MPORT_6_en = ivalid & _GEN_353;
- assign mem_tin_quad_MPORT_7_data = 2'h0;
- assign mem_tin_quad_MPORT_7_addr = 3'h1;
- assign mem_tin_quad_MPORT_7_mask = 1'h1;
- assign mem_tin_quad_MPORT_7_en = ivalid & _GEN_368;
- assign mem_tin_quad_MPORT_8_data = 2'h0;
- assign mem_tin_quad_MPORT_8_addr = 3'h2;
- assign mem_tin_quad_MPORT_8_mask = 1'h1;
- assign mem_tin_quad_MPORT_8_en = ivalid & valid_2[0];
- assign mem_tin_quad_MPORT_9_data = 2'h0;
- assign mem_tin_quad_MPORT_9_addr = 3'h2;
- assign mem_tin_quad_MPORT_9_mask = 1'h1;
- assign mem_tin_quad_MPORT_9_en = ivalid & _GEN_555;
- assign mem_tin_quad_MPORT_10_data = 2'h0;
- assign mem_tin_quad_MPORT_10_addr = 3'h2;
- assign mem_tin_quad_MPORT_10_mask = 1'h1;
- assign mem_tin_quad_MPORT_10_en = ivalid & _GEN_571;
- assign mem_tin_quad_MPORT_11_data = 2'h0;
- assign mem_tin_quad_MPORT_11_addr = 3'h2;
- assign mem_tin_quad_MPORT_11_mask = 1'h1;
- assign mem_tin_quad_MPORT_11_en = ivalid & _GEN_587;
- assign mem_tin_quad_MPORT_12_data = 2'h0;
- assign mem_tin_quad_MPORT_12_addr = 3'h3;
- assign mem_tin_quad_MPORT_12_mask = 1'h1;
- assign mem_tin_quad_MPORT_12_en = ivalid & valid_3[0];
- assign mem_tin_quad_MPORT_13_data = 2'h0;
- assign mem_tin_quad_MPORT_13_addr = 3'h3;
- assign mem_tin_quad_MPORT_13_mask = 1'h1;
- assign mem_tin_quad_MPORT_13_en = ivalid & _GEN_779;
- assign mem_tin_quad_MPORT_14_data = 2'h0;
- assign mem_tin_quad_MPORT_14_addr = 3'h3;
- assign mem_tin_quad_MPORT_14_mask = 1'h1;
- assign mem_tin_quad_MPORT_14_en = ivalid & _GEN_795;
- assign mem_tin_quad_MPORT_15_data = 2'h0;
- assign mem_tin_quad_MPORT_15_addr = 3'h3;
- assign mem_tin_quad_MPORT_15_mask = 1'h1;
- assign mem_tin_quad_MPORT_15_en = ivalid & _GEN_811;
- assign mem_tin_quad_MPORT_16_data = 2'h0;
- assign mem_tin_quad_MPORT_16_addr = 3'h4;
- assign mem_tin_quad_MPORT_16_mask = 1'h1;
- assign mem_tin_quad_MPORT_16_en = ivalid & valid_4[0];
- assign mem_tin_quad_MPORT_17_data = 2'h0;
- assign mem_tin_quad_MPORT_17_addr = 3'h4;
- assign mem_tin_quad_MPORT_17_mask = 1'h1;
- assign mem_tin_quad_MPORT_17_en = ivalid & _GEN_1003;
- assign mem_tin_quad_MPORT_18_data = 2'h0;
- assign mem_tin_quad_MPORT_18_addr = 3'h4;
- assign mem_tin_quad_MPORT_18_mask = 1'h1;
- assign mem_tin_quad_MPORT_18_en = ivalid & _GEN_1019;
- assign mem_tin_quad_MPORT_19_data = 2'h0;
- assign mem_tin_quad_MPORT_19_addr = 3'h4;
- assign mem_tin_quad_MPORT_19_mask = 1'h1;
- assign mem_tin_quad_MPORT_19_en = ivalid & _GEN_1035;
- assign mem_tin_quad_MPORT_20_data = 2'h0;
- assign mem_tin_quad_MPORT_20_addr = 3'h5;
- assign mem_tin_quad_MPORT_20_mask = 1'h1;
- assign mem_tin_quad_MPORT_20_en = ivalid & valid_5[0];
- assign mem_tin_quad_MPORT_21_data = 2'h0;
- assign mem_tin_quad_MPORT_21_addr = 3'h5;
- assign mem_tin_quad_MPORT_21_mask = 1'h1;
- assign mem_tin_quad_MPORT_21_en = ivalid & _GEN_1227;
- assign mem_tin_quad_MPORT_22_data = 2'h0;
- assign mem_tin_quad_MPORT_22_addr = 3'h5;
- assign mem_tin_quad_MPORT_22_mask = 1'h1;
- assign mem_tin_quad_MPORT_22_en = ivalid & _GEN_1243;
- assign mem_tin_quad_MPORT_23_data = 2'h0;
- assign mem_tin_quad_MPORT_23_addr = 3'h5;
- assign mem_tin_quad_MPORT_23_mask = 1'h1;
- assign mem_tin_quad_MPORT_23_en = ivalid & _GEN_1259;
- assign mem_tin_quad_MPORT_24_data = 2'h0;
- assign mem_tin_quad_MPORT_24_addr = 3'h6;
- assign mem_tin_quad_MPORT_24_mask = 1'h1;
- assign mem_tin_quad_MPORT_24_en = ivalid & valid_6[0];
- assign mem_tin_quad_MPORT_25_data = 2'h0;
- assign mem_tin_quad_MPORT_25_addr = 3'h6;
- assign mem_tin_quad_MPORT_25_mask = 1'h1;
- assign mem_tin_quad_MPORT_25_en = ivalid & _GEN_1451;
- assign mem_tin_quad_MPORT_26_data = 2'h0;
- assign mem_tin_quad_MPORT_26_addr = 3'h6;
- assign mem_tin_quad_MPORT_26_mask = 1'h1;
- assign mem_tin_quad_MPORT_26_en = ivalid & _GEN_1467;
- assign mem_tin_quad_MPORT_27_data = 2'h0;
- assign mem_tin_quad_MPORT_27_addr = 3'h6;
- assign mem_tin_quad_MPORT_27_mask = 1'h1;
- assign mem_tin_quad_MPORT_27_en = ivalid & _GEN_1483;
- assign mem_tin_quad_MPORT_28_data = 2'h0;
- assign mem_tin_quad_MPORT_28_addr = 3'h7;
- assign mem_tin_quad_MPORT_28_mask = 1'h1;
- assign mem_tin_quad_MPORT_28_en = ivalid & valid_7[0];
- assign mem_tin_quad_MPORT_29_data = 2'h0;
- assign mem_tin_quad_MPORT_29_addr = 3'h7;
- assign mem_tin_quad_MPORT_29_mask = 1'h1;
- assign mem_tin_quad_MPORT_29_en = ivalid & _GEN_1675;
- assign mem_tin_quad_MPORT_30_data = 2'h0;
- assign mem_tin_quad_MPORT_30_addr = 3'h7;
- assign mem_tin_quad_MPORT_30_mask = 1'h1;
- assign mem_tin_quad_MPORT_30_en = ivalid & _GEN_1691;
- assign mem_tin_quad_MPORT_31_data = 2'h0;
- assign mem_tin_quad_MPORT_31_addr = 3'h7;
- assign mem_tin_quad_MPORT_31_mask = 1'h1;
- assign mem_tin_quad_MPORT_31_en = ivalid & _GEN_1707;
- assign mem_m_io_out_bits_MPORT_en = 1'h1;
- assign mem_m_io_out_bits_MPORT_addr = outpos;
- assign mem_m_io_out_bits_MPORT_data = mem_m[mem_m_io_out_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_0_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_0_bits_MPORT_addr = 3'h0;
- assign mem_m_io_entry_0_bits_MPORT_data = mem_m[mem_m_io_entry_0_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_1_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_1_bits_MPORT_addr = 3'h1;
- assign mem_m_io_entry_1_bits_MPORT_data = mem_m[mem_m_io_entry_1_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_2_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_2_bits_MPORT_addr = 3'h2;
- assign mem_m_io_entry_2_bits_MPORT_data = mem_m[mem_m_io_entry_2_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_3_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_3_bits_MPORT_addr = 3'h3;
- assign mem_m_io_entry_3_bits_MPORT_data = mem_m[mem_m_io_entry_3_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_4_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_4_bits_MPORT_addr = 3'h4;
- assign mem_m_io_entry_4_bits_MPORT_data = mem_m[mem_m_io_entry_4_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_5_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_5_bits_MPORT_addr = 3'h5;
- assign mem_m_io_entry_5_bits_MPORT_data = mem_m[mem_m_io_entry_5_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_6_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_6_bits_MPORT_addr = 3'h6;
- assign mem_m_io_entry_6_bits_MPORT_data = mem_m[mem_m_io_entry_6_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_io_entry_7_bits_MPORT_en = 1'h1;
- assign mem_m_io_entry_7_bits_MPORT_addr = 3'h7;
- assign mem_m_io_entry_7_bits_MPORT_data = mem_m[mem_m_io_entry_7_bits_MPORT_addr]; // @[Fifo4e.scala 43:16]
- assign mem_m_MPORT_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_addr = 3'h0;
- assign mem_m_MPORT_mask = 1'h1;
- assign mem_m_MPORT_en = ivalid & valid[0];
- assign mem_m_MPORT_1_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_1_addr = 3'h0;
- assign mem_m_MPORT_1_mask = 1'h1;
- assign mem_m_MPORT_1_en = ivalid & _GEN_121;
- assign mem_m_MPORT_2_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_2_addr = 3'h0;
- assign mem_m_MPORT_2_mask = 1'h1;
- assign mem_m_MPORT_2_en = ivalid & _GEN_137;
- assign mem_m_MPORT_3_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_3_addr = 3'h0;
- assign mem_m_MPORT_3_mask = 1'h1;
- assign mem_m_MPORT_3_en = ivalid & _GEN_153;
- assign mem_m_MPORT_4_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_4_addr = 3'h1;
- assign mem_m_MPORT_4_mask = 1'h1;
- assign mem_m_MPORT_4_en = ivalid & valid_1[0];
- assign mem_m_MPORT_5_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_5_addr = 3'h1;
- assign mem_m_MPORT_5_mask = 1'h1;
- assign mem_m_MPORT_5_en = ivalid & _GEN_338;
- assign mem_m_MPORT_6_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_6_addr = 3'h1;
- assign mem_m_MPORT_6_mask = 1'h1;
- assign mem_m_MPORT_6_en = ivalid & _GEN_353;
- assign mem_m_MPORT_7_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_7_addr = 3'h1;
- assign mem_m_MPORT_7_mask = 1'h1;
- assign mem_m_MPORT_7_en = ivalid & _GEN_368;
- assign mem_m_MPORT_8_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_8_addr = 3'h2;
- assign mem_m_MPORT_8_mask = 1'h1;
- assign mem_m_MPORT_8_en = ivalid & valid_2[0];
- assign mem_m_MPORT_9_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_9_addr = 3'h2;
- assign mem_m_MPORT_9_mask = 1'h1;
- assign mem_m_MPORT_9_en = ivalid & _GEN_555;
- assign mem_m_MPORT_10_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_10_addr = 3'h2;
- assign mem_m_MPORT_10_mask = 1'h1;
- assign mem_m_MPORT_10_en = ivalid & _GEN_571;
- assign mem_m_MPORT_11_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_11_addr = 3'h2;
- assign mem_m_MPORT_11_mask = 1'h1;
- assign mem_m_MPORT_11_en = ivalid & _GEN_587;
- assign mem_m_MPORT_12_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_12_addr = 3'h3;
- assign mem_m_MPORT_12_mask = 1'h1;
- assign mem_m_MPORT_12_en = ivalid & valid_3[0];
- assign mem_m_MPORT_13_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_13_addr = 3'h3;
- assign mem_m_MPORT_13_mask = 1'h1;
- assign mem_m_MPORT_13_en = ivalid & _GEN_779;
- assign mem_m_MPORT_14_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_14_addr = 3'h3;
- assign mem_m_MPORT_14_mask = 1'h1;
- assign mem_m_MPORT_14_en = ivalid & _GEN_795;
- assign mem_m_MPORT_15_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_15_addr = 3'h3;
- assign mem_m_MPORT_15_mask = 1'h1;
- assign mem_m_MPORT_15_en = ivalid & _GEN_811;
- assign mem_m_MPORT_16_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_16_addr = 3'h4;
- assign mem_m_MPORT_16_mask = 1'h1;
- assign mem_m_MPORT_16_en = ivalid & valid_4[0];
- assign mem_m_MPORT_17_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_17_addr = 3'h4;
- assign mem_m_MPORT_17_mask = 1'h1;
- assign mem_m_MPORT_17_en = ivalid & _GEN_1003;
- assign mem_m_MPORT_18_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_18_addr = 3'h4;
- assign mem_m_MPORT_18_mask = 1'h1;
- assign mem_m_MPORT_18_en = ivalid & _GEN_1019;
- assign mem_m_MPORT_19_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_19_addr = 3'h4;
- assign mem_m_MPORT_19_mask = 1'h1;
- assign mem_m_MPORT_19_en = ivalid & _GEN_1035;
- assign mem_m_MPORT_20_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_20_addr = 3'h5;
- assign mem_m_MPORT_20_mask = 1'h1;
- assign mem_m_MPORT_20_en = ivalid & valid_5[0];
- assign mem_m_MPORT_21_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_21_addr = 3'h5;
- assign mem_m_MPORT_21_mask = 1'h1;
- assign mem_m_MPORT_21_en = ivalid & _GEN_1227;
- assign mem_m_MPORT_22_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_22_addr = 3'h5;
- assign mem_m_MPORT_22_mask = 1'h1;
- assign mem_m_MPORT_22_en = ivalid & _GEN_1243;
- assign mem_m_MPORT_23_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_23_addr = 3'h5;
- assign mem_m_MPORT_23_mask = 1'h1;
- assign mem_m_MPORT_23_en = ivalid & _GEN_1259;
- assign mem_m_MPORT_24_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_24_addr = 3'h6;
- assign mem_m_MPORT_24_mask = 1'h1;
- assign mem_m_MPORT_24_en = ivalid & valid_6[0];
- assign mem_m_MPORT_25_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_25_addr = 3'h6;
- assign mem_m_MPORT_25_mask = 1'h1;
- assign mem_m_MPORT_25_en = ivalid & _GEN_1451;
- assign mem_m_MPORT_26_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_26_addr = 3'h6;
- assign mem_m_MPORT_26_mask = 1'h1;
- assign mem_m_MPORT_26_en = ivalid & _GEN_1467;
- assign mem_m_MPORT_27_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_27_addr = 3'h6;
- assign mem_m_MPORT_27_mask = 1'h1;
- assign mem_m_MPORT_27_en = ivalid & _GEN_1483;
- assign mem_m_MPORT_28_data = io_in_bits_0_bits_m;
- assign mem_m_MPORT_28_addr = 3'h7;
- assign mem_m_MPORT_28_mask = 1'h1;
- assign mem_m_MPORT_28_en = ivalid & valid_7[0];
- assign mem_m_MPORT_29_data = io_in_bits_1_bits_m;
- assign mem_m_MPORT_29_addr = 3'h7;
- assign mem_m_MPORT_29_mask = 1'h1;
- assign mem_m_MPORT_29_en = ivalid & _GEN_1675;
- assign mem_m_MPORT_30_data = io_in_bits_2_bits_m;
- assign mem_m_MPORT_30_addr = 3'h7;
- assign mem_m_MPORT_30_mask = 1'h1;
- assign mem_m_MPORT_30_en = ivalid & _GEN_1691;
- assign mem_m_MPORT_31_data = io_in_bits_3_bits_m;
- assign mem_m_MPORT_31_addr = 3'h7;
- assign mem_m_MPORT_31_mask = 1'h1;
- assign mem_m_MPORT_31_en = ivalid & _GEN_1707;
- assign io_in_ready = mcount <= _io_in_ready_T_1; // @[Fifo4e.scala 132:25]
- assign io_out_valid = mcount != 4'h0; // @[Fifo4e.scala 134:26]
- assign io_out_bits_tin_op = mem_tin_op_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_addr = mem_tin_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_offset = mem_tin_offset_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_remain = mem_tin_remain_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vs_valid = mem_tin_vs_valid_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vs_addr = mem_tin_vs_addr_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_vs_tag = mem_tin_vs_tag_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_tin_quad = mem_tin_quad_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_out_bits_m = mem_m_io_out_bits_MPORT_data; // @[Fifo4e.scala 135:15]
- assign io_entry_0_valid = active[0]; // @[Fifo4e.scala 140:32]
- assign io_entry_0_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_0_bits_m = mem_m_io_entry_0_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_valid = active[1]; // @[Fifo4e.scala 140:32]
- assign io_entry_1_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_1_bits_m = mem_m_io_entry_1_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_valid = active[2]; // @[Fifo4e.scala 140:32]
- assign io_entry_2_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_2_bits_m = mem_m_io_entry_2_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_valid = active[3]; // @[Fifo4e.scala 140:32]
- assign io_entry_3_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_3_bits_m = mem_m_io_entry_3_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_4_valid = active[4]; // @[Fifo4e.scala 140:32]
- assign io_entry_4_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_4_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_4_bits_m = mem_m_io_entry_4_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_5_valid = active[5]; // @[Fifo4e.scala 140:32]
- assign io_entry_5_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_5_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_5_bits_m = mem_m_io_entry_5_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_6_valid = active[6]; // @[Fifo4e.scala 140:32]
- assign io_entry_6_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_6_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_6_bits_m = mem_m_io_entry_6_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_7_valid = active[7]; // @[Fifo4e.scala 140:32]
- assign io_entry_7_bits_tin_vs_valid = mem_tin_vs_valid_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_7_bits_tin_vs_addr = mem_tin_vs_addr_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_entry_7_bits_m = mem_m_io_entry_7_bits_MPORT_data; // @[Fifo4e.scala 141:22]
- assign io_nempty = nempty; // @[Fifo4e.scala 54:13]
- always @(posedge clock) begin
- if (mem_tin_op_MPORT_en & mem_tin_op_MPORT_mask) begin
- mem_tin_op[mem_tin_op_MPORT_addr] <= mem_tin_op_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_1_en & mem_tin_op_MPORT_1_mask) begin
- mem_tin_op[mem_tin_op_MPORT_1_addr] <= mem_tin_op_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_2_en & mem_tin_op_MPORT_2_mask) begin
- mem_tin_op[mem_tin_op_MPORT_2_addr] <= mem_tin_op_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_3_en & mem_tin_op_MPORT_3_mask) begin
- mem_tin_op[mem_tin_op_MPORT_3_addr] <= mem_tin_op_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_4_en & mem_tin_op_MPORT_4_mask) begin
- mem_tin_op[mem_tin_op_MPORT_4_addr] <= mem_tin_op_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_5_en & mem_tin_op_MPORT_5_mask) begin
- mem_tin_op[mem_tin_op_MPORT_5_addr] <= mem_tin_op_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_6_en & mem_tin_op_MPORT_6_mask) begin
- mem_tin_op[mem_tin_op_MPORT_6_addr] <= mem_tin_op_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_7_en & mem_tin_op_MPORT_7_mask) begin
- mem_tin_op[mem_tin_op_MPORT_7_addr] <= mem_tin_op_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_8_en & mem_tin_op_MPORT_8_mask) begin
- mem_tin_op[mem_tin_op_MPORT_8_addr] <= mem_tin_op_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_9_en & mem_tin_op_MPORT_9_mask) begin
- mem_tin_op[mem_tin_op_MPORT_9_addr] <= mem_tin_op_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_10_en & mem_tin_op_MPORT_10_mask) begin
- mem_tin_op[mem_tin_op_MPORT_10_addr] <= mem_tin_op_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_11_en & mem_tin_op_MPORT_11_mask) begin
- mem_tin_op[mem_tin_op_MPORT_11_addr] <= mem_tin_op_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_12_en & mem_tin_op_MPORT_12_mask) begin
- mem_tin_op[mem_tin_op_MPORT_12_addr] <= mem_tin_op_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_13_en & mem_tin_op_MPORT_13_mask) begin
- mem_tin_op[mem_tin_op_MPORT_13_addr] <= mem_tin_op_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_14_en & mem_tin_op_MPORT_14_mask) begin
- mem_tin_op[mem_tin_op_MPORT_14_addr] <= mem_tin_op_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_15_en & mem_tin_op_MPORT_15_mask) begin
- mem_tin_op[mem_tin_op_MPORT_15_addr] <= mem_tin_op_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_16_en & mem_tin_op_MPORT_16_mask) begin
- mem_tin_op[mem_tin_op_MPORT_16_addr] <= mem_tin_op_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_17_en & mem_tin_op_MPORT_17_mask) begin
- mem_tin_op[mem_tin_op_MPORT_17_addr] <= mem_tin_op_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_18_en & mem_tin_op_MPORT_18_mask) begin
- mem_tin_op[mem_tin_op_MPORT_18_addr] <= mem_tin_op_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_19_en & mem_tin_op_MPORT_19_mask) begin
- mem_tin_op[mem_tin_op_MPORT_19_addr] <= mem_tin_op_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_20_en & mem_tin_op_MPORT_20_mask) begin
- mem_tin_op[mem_tin_op_MPORT_20_addr] <= mem_tin_op_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_21_en & mem_tin_op_MPORT_21_mask) begin
- mem_tin_op[mem_tin_op_MPORT_21_addr] <= mem_tin_op_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_22_en & mem_tin_op_MPORT_22_mask) begin
- mem_tin_op[mem_tin_op_MPORT_22_addr] <= mem_tin_op_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_23_en & mem_tin_op_MPORT_23_mask) begin
- mem_tin_op[mem_tin_op_MPORT_23_addr] <= mem_tin_op_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_24_en & mem_tin_op_MPORT_24_mask) begin
- mem_tin_op[mem_tin_op_MPORT_24_addr] <= mem_tin_op_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_25_en & mem_tin_op_MPORT_25_mask) begin
- mem_tin_op[mem_tin_op_MPORT_25_addr] <= mem_tin_op_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_26_en & mem_tin_op_MPORT_26_mask) begin
- mem_tin_op[mem_tin_op_MPORT_26_addr] <= mem_tin_op_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_27_en & mem_tin_op_MPORT_27_mask) begin
- mem_tin_op[mem_tin_op_MPORT_27_addr] <= mem_tin_op_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_28_en & mem_tin_op_MPORT_28_mask) begin
- mem_tin_op[mem_tin_op_MPORT_28_addr] <= mem_tin_op_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_29_en & mem_tin_op_MPORT_29_mask) begin
- mem_tin_op[mem_tin_op_MPORT_29_addr] <= mem_tin_op_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_30_en & mem_tin_op_MPORT_30_mask) begin
- mem_tin_op[mem_tin_op_MPORT_30_addr] <= mem_tin_op_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_op_MPORT_31_en & mem_tin_op_MPORT_31_mask) begin
- mem_tin_op[mem_tin_op_MPORT_31_addr] <= mem_tin_op_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_en & mem_tin_addr_MPORT_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_addr] <= mem_tin_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_1_en & mem_tin_addr_MPORT_1_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_1_addr] <= mem_tin_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_2_en & mem_tin_addr_MPORT_2_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_2_addr] <= mem_tin_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_3_en & mem_tin_addr_MPORT_3_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_3_addr] <= mem_tin_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_4_en & mem_tin_addr_MPORT_4_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_4_addr] <= mem_tin_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_5_en & mem_tin_addr_MPORT_5_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_5_addr] <= mem_tin_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_6_en & mem_tin_addr_MPORT_6_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_6_addr] <= mem_tin_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_7_en & mem_tin_addr_MPORT_7_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_7_addr] <= mem_tin_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_8_en & mem_tin_addr_MPORT_8_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_8_addr] <= mem_tin_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_9_en & mem_tin_addr_MPORT_9_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_9_addr] <= mem_tin_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_10_en & mem_tin_addr_MPORT_10_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_10_addr] <= mem_tin_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_11_en & mem_tin_addr_MPORT_11_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_11_addr] <= mem_tin_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_12_en & mem_tin_addr_MPORT_12_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_12_addr] <= mem_tin_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_13_en & mem_tin_addr_MPORT_13_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_13_addr] <= mem_tin_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_14_en & mem_tin_addr_MPORT_14_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_14_addr] <= mem_tin_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_15_en & mem_tin_addr_MPORT_15_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_15_addr] <= mem_tin_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_16_en & mem_tin_addr_MPORT_16_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_16_addr] <= mem_tin_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_17_en & mem_tin_addr_MPORT_17_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_17_addr] <= mem_tin_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_18_en & mem_tin_addr_MPORT_18_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_18_addr] <= mem_tin_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_19_en & mem_tin_addr_MPORT_19_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_19_addr] <= mem_tin_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_20_en & mem_tin_addr_MPORT_20_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_20_addr] <= mem_tin_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_21_en & mem_tin_addr_MPORT_21_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_21_addr] <= mem_tin_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_22_en & mem_tin_addr_MPORT_22_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_22_addr] <= mem_tin_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_23_en & mem_tin_addr_MPORT_23_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_23_addr] <= mem_tin_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_24_en & mem_tin_addr_MPORT_24_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_24_addr] <= mem_tin_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_25_en & mem_tin_addr_MPORT_25_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_25_addr] <= mem_tin_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_26_en & mem_tin_addr_MPORT_26_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_26_addr] <= mem_tin_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_27_en & mem_tin_addr_MPORT_27_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_27_addr] <= mem_tin_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_28_en & mem_tin_addr_MPORT_28_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_28_addr] <= mem_tin_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_29_en & mem_tin_addr_MPORT_29_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_29_addr] <= mem_tin_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_30_en & mem_tin_addr_MPORT_30_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_30_addr] <= mem_tin_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_addr_MPORT_31_en & mem_tin_addr_MPORT_31_mask) begin
- mem_tin_addr[mem_tin_addr_MPORT_31_addr] <= mem_tin_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_en & mem_tin_offset_MPORT_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_addr] <= mem_tin_offset_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_1_en & mem_tin_offset_MPORT_1_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_1_addr] <= mem_tin_offset_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_2_en & mem_tin_offset_MPORT_2_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_2_addr] <= mem_tin_offset_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_3_en & mem_tin_offset_MPORT_3_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_3_addr] <= mem_tin_offset_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_4_en & mem_tin_offset_MPORT_4_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_4_addr] <= mem_tin_offset_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_5_en & mem_tin_offset_MPORT_5_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_5_addr] <= mem_tin_offset_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_6_en & mem_tin_offset_MPORT_6_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_6_addr] <= mem_tin_offset_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_7_en & mem_tin_offset_MPORT_7_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_7_addr] <= mem_tin_offset_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_8_en & mem_tin_offset_MPORT_8_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_8_addr] <= mem_tin_offset_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_9_en & mem_tin_offset_MPORT_9_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_9_addr] <= mem_tin_offset_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_10_en & mem_tin_offset_MPORT_10_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_10_addr] <= mem_tin_offset_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_11_en & mem_tin_offset_MPORT_11_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_11_addr] <= mem_tin_offset_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_12_en & mem_tin_offset_MPORT_12_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_12_addr] <= mem_tin_offset_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_13_en & mem_tin_offset_MPORT_13_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_13_addr] <= mem_tin_offset_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_14_en & mem_tin_offset_MPORT_14_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_14_addr] <= mem_tin_offset_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_15_en & mem_tin_offset_MPORT_15_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_15_addr] <= mem_tin_offset_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_16_en & mem_tin_offset_MPORT_16_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_16_addr] <= mem_tin_offset_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_17_en & mem_tin_offset_MPORT_17_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_17_addr] <= mem_tin_offset_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_18_en & mem_tin_offset_MPORT_18_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_18_addr] <= mem_tin_offset_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_19_en & mem_tin_offset_MPORT_19_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_19_addr] <= mem_tin_offset_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_20_en & mem_tin_offset_MPORT_20_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_20_addr] <= mem_tin_offset_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_21_en & mem_tin_offset_MPORT_21_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_21_addr] <= mem_tin_offset_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_22_en & mem_tin_offset_MPORT_22_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_22_addr] <= mem_tin_offset_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_23_en & mem_tin_offset_MPORT_23_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_23_addr] <= mem_tin_offset_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_24_en & mem_tin_offset_MPORT_24_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_24_addr] <= mem_tin_offset_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_25_en & mem_tin_offset_MPORT_25_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_25_addr] <= mem_tin_offset_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_26_en & mem_tin_offset_MPORT_26_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_26_addr] <= mem_tin_offset_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_27_en & mem_tin_offset_MPORT_27_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_27_addr] <= mem_tin_offset_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_28_en & mem_tin_offset_MPORT_28_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_28_addr] <= mem_tin_offset_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_29_en & mem_tin_offset_MPORT_29_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_29_addr] <= mem_tin_offset_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_30_en & mem_tin_offset_MPORT_30_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_30_addr] <= mem_tin_offset_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_offset_MPORT_31_en & mem_tin_offset_MPORT_31_mask) begin
- mem_tin_offset[mem_tin_offset_MPORT_31_addr] <= mem_tin_offset_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_en & mem_tin_remain_MPORT_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_addr] <= mem_tin_remain_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_1_en & mem_tin_remain_MPORT_1_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_1_addr] <= mem_tin_remain_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_2_en & mem_tin_remain_MPORT_2_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_2_addr] <= mem_tin_remain_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_3_en & mem_tin_remain_MPORT_3_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_3_addr] <= mem_tin_remain_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_4_en & mem_tin_remain_MPORT_4_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_4_addr] <= mem_tin_remain_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_5_en & mem_tin_remain_MPORT_5_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_5_addr] <= mem_tin_remain_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_6_en & mem_tin_remain_MPORT_6_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_6_addr] <= mem_tin_remain_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_7_en & mem_tin_remain_MPORT_7_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_7_addr] <= mem_tin_remain_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_8_en & mem_tin_remain_MPORT_8_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_8_addr] <= mem_tin_remain_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_9_en & mem_tin_remain_MPORT_9_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_9_addr] <= mem_tin_remain_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_10_en & mem_tin_remain_MPORT_10_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_10_addr] <= mem_tin_remain_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_11_en & mem_tin_remain_MPORT_11_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_11_addr] <= mem_tin_remain_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_12_en & mem_tin_remain_MPORT_12_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_12_addr] <= mem_tin_remain_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_13_en & mem_tin_remain_MPORT_13_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_13_addr] <= mem_tin_remain_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_14_en & mem_tin_remain_MPORT_14_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_14_addr] <= mem_tin_remain_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_15_en & mem_tin_remain_MPORT_15_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_15_addr] <= mem_tin_remain_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_16_en & mem_tin_remain_MPORT_16_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_16_addr] <= mem_tin_remain_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_17_en & mem_tin_remain_MPORT_17_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_17_addr] <= mem_tin_remain_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_18_en & mem_tin_remain_MPORT_18_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_18_addr] <= mem_tin_remain_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_19_en & mem_tin_remain_MPORT_19_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_19_addr] <= mem_tin_remain_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_20_en & mem_tin_remain_MPORT_20_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_20_addr] <= mem_tin_remain_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_21_en & mem_tin_remain_MPORT_21_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_21_addr] <= mem_tin_remain_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_22_en & mem_tin_remain_MPORT_22_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_22_addr] <= mem_tin_remain_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_23_en & mem_tin_remain_MPORT_23_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_23_addr] <= mem_tin_remain_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_24_en & mem_tin_remain_MPORT_24_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_24_addr] <= mem_tin_remain_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_25_en & mem_tin_remain_MPORT_25_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_25_addr] <= mem_tin_remain_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_26_en & mem_tin_remain_MPORT_26_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_26_addr] <= mem_tin_remain_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_27_en & mem_tin_remain_MPORT_27_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_27_addr] <= mem_tin_remain_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_28_en & mem_tin_remain_MPORT_28_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_28_addr] <= mem_tin_remain_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_29_en & mem_tin_remain_MPORT_29_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_29_addr] <= mem_tin_remain_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_30_en & mem_tin_remain_MPORT_30_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_30_addr] <= mem_tin_remain_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_remain_MPORT_31_en & mem_tin_remain_MPORT_31_mask) begin
- mem_tin_remain[mem_tin_remain_MPORT_31_addr] <= mem_tin_remain_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_en & mem_tin_vs_valid_MPORT_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_addr] <= mem_tin_vs_valid_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_1_en & mem_tin_vs_valid_MPORT_1_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_1_addr] <= mem_tin_vs_valid_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_2_en & mem_tin_vs_valid_MPORT_2_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_2_addr] <= mem_tin_vs_valid_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_3_en & mem_tin_vs_valid_MPORT_3_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_3_addr] <= mem_tin_vs_valid_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_4_en & mem_tin_vs_valid_MPORT_4_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_4_addr] <= mem_tin_vs_valid_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_5_en & mem_tin_vs_valid_MPORT_5_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_5_addr] <= mem_tin_vs_valid_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_6_en & mem_tin_vs_valid_MPORT_6_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_6_addr] <= mem_tin_vs_valid_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_7_en & mem_tin_vs_valid_MPORT_7_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_7_addr] <= mem_tin_vs_valid_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_8_en & mem_tin_vs_valid_MPORT_8_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_8_addr] <= mem_tin_vs_valid_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_9_en & mem_tin_vs_valid_MPORT_9_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_9_addr] <= mem_tin_vs_valid_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_10_en & mem_tin_vs_valid_MPORT_10_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_10_addr] <= mem_tin_vs_valid_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_11_en & mem_tin_vs_valid_MPORT_11_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_11_addr] <= mem_tin_vs_valid_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_12_en & mem_tin_vs_valid_MPORT_12_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_12_addr] <= mem_tin_vs_valid_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_13_en & mem_tin_vs_valid_MPORT_13_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_13_addr] <= mem_tin_vs_valid_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_14_en & mem_tin_vs_valid_MPORT_14_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_14_addr] <= mem_tin_vs_valid_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_15_en & mem_tin_vs_valid_MPORT_15_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_15_addr] <= mem_tin_vs_valid_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_16_en & mem_tin_vs_valid_MPORT_16_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_16_addr] <= mem_tin_vs_valid_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_17_en & mem_tin_vs_valid_MPORT_17_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_17_addr] <= mem_tin_vs_valid_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_18_en & mem_tin_vs_valid_MPORT_18_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_18_addr] <= mem_tin_vs_valid_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_19_en & mem_tin_vs_valid_MPORT_19_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_19_addr] <= mem_tin_vs_valid_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_20_en & mem_tin_vs_valid_MPORT_20_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_20_addr] <= mem_tin_vs_valid_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_21_en & mem_tin_vs_valid_MPORT_21_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_21_addr] <= mem_tin_vs_valid_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_22_en & mem_tin_vs_valid_MPORT_22_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_22_addr] <= mem_tin_vs_valid_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_23_en & mem_tin_vs_valid_MPORT_23_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_23_addr] <= mem_tin_vs_valid_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_24_en & mem_tin_vs_valid_MPORT_24_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_24_addr] <= mem_tin_vs_valid_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_25_en & mem_tin_vs_valid_MPORT_25_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_25_addr] <= mem_tin_vs_valid_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_26_en & mem_tin_vs_valid_MPORT_26_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_26_addr] <= mem_tin_vs_valid_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_27_en & mem_tin_vs_valid_MPORT_27_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_27_addr] <= mem_tin_vs_valid_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_28_en & mem_tin_vs_valid_MPORT_28_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_28_addr] <= mem_tin_vs_valid_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_29_en & mem_tin_vs_valid_MPORT_29_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_29_addr] <= mem_tin_vs_valid_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_30_en & mem_tin_vs_valid_MPORT_30_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_30_addr] <= mem_tin_vs_valid_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_valid_MPORT_31_en & mem_tin_vs_valid_MPORT_31_mask) begin
- mem_tin_vs_valid[mem_tin_vs_valid_MPORT_31_addr] <= mem_tin_vs_valid_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_en & mem_tin_vs_addr_MPORT_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_addr] <= mem_tin_vs_addr_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_1_en & mem_tin_vs_addr_MPORT_1_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_1_addr] <= mem_tin_vs_addr_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_2_en & mem_tin_vs_addr_MPORT_2_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_2_addr] <= mem_tin_vs_addr_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_3_en & mem_tin_vs_addr_MPORT_3_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_3_addr] <= mem_tin_vs_addr_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_4_en & mem_tin_vs_addr_MPORT_4_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_4_addr] <= mem_tin_vs_addr_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_5_en & mem_tin_vs_addr_MPORT_5_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_5_addr] <= mem_tin_vs_addr_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_6_en & mem_tin_vs_addr_MPORT_6_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_6_addr] <= mem_tin_vs_addr_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_7_en & mem_tin_vs_addr_MPORT_7_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_7_addr] <= mem_tin_vs_addr_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_8_en & mem_tin_vs_addr_MPORT_8_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_8_addr] <= mem_tin_vs_addr_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_9_en & mem_tin_vs_addr_MPORT_9_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_9_addr] <= mem_tin_vs_addr_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_10_en & mem_tin_vs_addr_MPORT_10_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_10_addr] <= mem_tin_vs_addr_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_11_en & mem_tin_vs_addr_MPORT_11_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_11_addr] <= mem_tin_vs_addr_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_12_en & mem_tin_vs_addr_MPORT_12_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_12_addr] <= mem_tin_vs_addr_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_13_en & mem_tin_vs_addr_MPORT_13_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_13_addr] <= mem_tin_vs_addr_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_14_en & mem_tin_vs_addr_MPORT_14_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_14_addr] <= mem_tin_vs_addr_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_15_en & mem_tin_vs_addr_MPORT_15_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_15_addr] <= mem_tin_vs_addr_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_16_en & mem_tin_vs_addr_MPORT_16_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_16_addr] <= mem_tin_vs_addr_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_17_en & mem_tin_vs_addr_MPORT_17_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_17_addr] <= mem_tin_vs_addr_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_18_en & mem_tin_vs_addr_MPORT_18_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_18_addr] <= mem_tin_vs_addr_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_19_en & mem_tin_vs_addr_MPORT_19_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_19_addr] <= mem_tin_vs_addr_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_20_en & mem_tin_vs_addr_MPORT_20_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_20_addr] <= mem_tin_vs_addr_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_21_en & mem_tin_vs_addr_MPORT_21_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_21_addr] <= mem_tin_vs_addr_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_22_en & mem_tin_vs_addr_MPORT_22_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_22_addr] <= mem_tin_vs_addr_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_23_en & mem_tin_vs_addr_MPORT_23_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_23_addr] <= mem_tin_vs_addr_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_24_en & mem_tin_vs_addr_MPORT_24_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_24_addr] <= mem_tin_vs_addr_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_25_en & mem_tin_vs_addr_MPORT_25_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_25_addr] <= mem_tin_vs_addr_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_26_en & mem_tin_vs_addr_MPORT_26_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_26_addr] <= mem_tin_vs_addr_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_27_en & mem_tin_vs_addr_MPORT_27_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_27_addr] <= mem_tin_vs_addr_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_28_en & mem_tin_vs_addr_MPORT_28_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_28_addr] <= mem_tin_vs_addr_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_29_en & mem_tin_vs_addr_MPORT_29_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_29_addr] <= mem_tin_vs_addr_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_30_en & mem_tin_vs_addr_MPORT_30_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_30_addr] <= mem_tin_vs_addr_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_addr_MPORT_31_en & mem_tin_vs_addr_MPORT_31_mask) begin
- mem_tin_vs_addr[mem_tin_vs_addr_MPORT_31_addr] <= mem_tin_vs_addr_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_en & mem_tin_vs_tag_MPORT_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_addr] <= mem_tin_vs_tag_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_1_en & mem_tin_vs_tag_MPORT_1_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_1_addr] <= mem_tin_vs_tag_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_2_en & mem_tin_vs_tag_MPORT_2_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_2_addr] <= mem_tin_vs_tag_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_3_en & mem_tin_vs_tag_MPORT_3_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_3_addr] <= mem_tin_vs_tag_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_4_en & mem_tin_vs_tag_MPORT_4_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_4_addr] <= mem_tin_vs_tag_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_5_en & mem_tin_vs_tag_MPORT_5_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_5_addr] <= mem_tin_vs_tag_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_6_en & mem_tin_vs_tag_MPORT_6_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_6_addr] <= mem_tin_vs_tag_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_7_en & mem_tin_vs_tag_MPORT_7_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_7_addr] <= mem_tin_vs_tag_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_8_en & mem_tin_vs_tag_MPORT_8_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_8_addr] <= mem_tin_vs_tag_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_9_en & mem_tin_vs_tag_MPORT_9_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_9_addr] <= mem_tin_vs_tag_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_10_en & mem_tin_vs_tag_MPORT_10_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_10_addr] <= mem_tin_vs_tag_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_11_en & mem_tin_vs_tag_MPORT_11_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_11_addr] <= mem_tin_vs_tag_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_12_en & mem_tin_vs_tag_MPORT_12_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_12_addr] <= mem_tin_vs_tag_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_13_en & mem_tin_vs_tag_MPORT_13_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_13_addr] <= mem_tin_vs_tag_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_14_en & mem_tin_vs_tag_MPORT_14_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_14_addr] <= mem_tin_vs_tag_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_15_en & mem_tin_vs_tag_MPORT_15_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_15_addr] <= mem_tin_vs_tag_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_16_en & mem_tin_vs_tag_MPORT_16_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_16_addr] <= mem_tin_vs_tag_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_17_en & mem_tin_vs_tag_MPORT_17_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_17_addr] <= mem_tin_vs_tag_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_18_en & mem_tin_vs_tag_MPORT_18_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_18_addr] <= mem_tin_vs_tag_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_19_en & mem_tin_vs_tag_MPORT_19_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_19_addr] <= mem_tin_vs_tag_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_20_en & mem_tin_vs_tag_MPORT_20_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_20_addr] <= mem_tin_vs_tag_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_21_en & mem_tin_vs_tag_MPORT_21_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_21_addr] <= mem_tin_vs_tag_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_22_en & mem_tin_vs_tag_MPORT_22_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_22_addr] <= mem_tin_vs_tag_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_23_en & mem_tin_vs_tag_MPORT_23_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_23_addr] <= mem_tin_vs_tag_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_24_en & mem_tin_vs_tag_MPORT_24_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_24_addr] <= mem_tin_vs_tag_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_25_en & mem_tin_vs_tag_MPORT_25_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_25_addr] <= mem_tin_vs_tag_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_26_en & mem_tin_vs_tag_MPORT_26_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_26_addr] <= mem_tin_vs_tag_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_27_en & mem_tin_vs_tag_MPORT_27_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_27_addr] <= mem_tin_vs_tag_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_28_en & mem_tin_vs_tag_MPORT_28_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_28_addr] <= mem_tin_vs_tag_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_29_en & mem_tin_vs_tag_MPORT_29_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_29_addr] <= mem_tin_vs_tag_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_30_en & mem_tin_vs_tag_MPORT_30_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_30_addr] <= mem_tin_vs_tag_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_vs_tag_MPORT_31_en & mem_tin_vs_tag_MPORT_31_mask) begin
- mem_tin_vs_tag[mem_tin_vs_tag_MPORT_31_addr] <= mem_tin_vs_tag_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_en & mem_tin_quad_MPORT_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_addr] <= mem_tin_quad_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_1_en & mem_tin_quad_MPORT_1_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_1_addr] <= mem_tin_quad_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_2_en & mem_tin_quad_MPORT_2_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_2_addr] <= mem_tin_quad_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_3_en & mem_tin_quad_MPORT_3_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_3_addr] <= mem_tin_quad_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_4_en & mem_tin_quad_MPORT_4_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_4_addr] <= mem_tin_quad_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_5_en & mem_tin_quad_MPORT_5_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_5_addr] <= mem_tin_quad_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_6_en & mem_tin_quad_MPORT_6_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_6_addr] <= mem_tin_quad_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_7_en & mem_tin_quad_MPORT_7_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_7_addr] <= mem_tin_quad_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_8_en & mem_tin_quad_MPORT_8_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_8_addr] <= mem_tin_quad_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_9_en & mem_tin_quad_MPORT_9_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_9_addr] <= mem_tin_quad_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_10_en & mem_tin_quad_MPORT_10_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_10_addr] <= mem_tin_quad_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_11_en & mem_tin_quad_MPORT_11_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_11_addr] <= mem_tin_quad_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_12_en & mem_tin_quad_MPORT_12_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_12_addr] <= mem_tin_quad_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_13_en & mem_tin_quad_MPORT_13_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_13_addr] <= mem_tin_quad_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_14_en & mem_tin_quad_MPORT_14_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_14_addr] <= mem_tin_quad_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_15_en & mem_tin_quad_MPORT_15_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_15_addr] <= mem_tin_quad_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_16_en & mem_tin_quad_MPORT_16_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_16_addr] <= mem_tin_quad_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_17_en & mem_tin_quad_MPORT_17_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_17_addr] <= mem_tin_quad_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_18_en & mem_tin_quad_MPORT_18_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_18_addr] <= mem_tin_quad_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_19_en & mem_tin_quad_MPORT_19_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_19_addr] <= mem_tin_quad_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_20_en & mem_tin_quad_MPORT_20_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_20_addr] <= mem_tin_quad_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_21_en & mem_tin_quad_MPORT_21_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_21_addr] <= mem_tin_quad_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_22_en & mem_tin_quad_MPORT_22_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_22_addr] <= mem_tin_quad_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_23_en & mem_tin_quad_MPORT_23_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_23_addr] <= mem_tin_quad_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_24_en & mem_tin_quad_MPORT_24_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_24_addr] <= mem_tin_quad_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_25_en & mem_tin_quad_MPORT_25_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_25_addr] <= mem_tin_quad_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_26_en & mem_tin_quad_MPORT_26_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_26_addr] <= mem_tin_quad_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_27_en & mem_tin_quad_MPORT_27_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_27_addr] <= mem_tin_quad_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_28_en & mem_tin_quad_MPORT_28_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_28_addr] <= mem_tin_quad_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_29_en & mem_tin_quad_MPORT_29_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_29_addr] <= mem_tin_quad_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_30_en & mem_tin_quad_MPORT_30_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_30_addr] <= mem_tin_quad_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_tin_quad_MPORT_31_en & mem_tin_quad_MPORT_31_mask) begin
- mem_tin_quad[mem_tin_quad_MPORT_31_addr] <= mem_tin_quad_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_en & mem_m_MPORT_mask) begin
- mem_m[mem_m_MPORT_addr] <= mem_m_MPORT_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_1_en & mem_m_MPORT_1_mask) begin
- mem_m[mem_m_MPORT_1_addr] <= mem_m_MPORT_1_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_2_en & mem_m_MPORT_2_mask) begin
- mem_m[mem_m_MPORT_2_addr] <= mem_m_MPORT_2_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_3_en & mem_m_MPORT_3_mask) begin
- mem_m[mem_m_MPORT_3_addr] <= mem_m_MPORT_3_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_4_en & mem_m_MPORT_4_mask) begin
- mem_m[mem_m_MPORT_4_addr] <= mem_m_MPORT_4_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_5_en & mem_m_MPORT_5_mask) begin
- mem_m[mem_m_MPORT_5_addr] <= mem_m_MPORT_5_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_6_en & mem_m_MPORT_6_mask) begin
- mem_m[mem_m_MPORT_6_addr] <= mem_m_MPORT_6_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_7_en & mem_m_MPORT_7_mask) begin
- mem_m[mem_m_MPORT_7_addr] <= mem_m_MPORT_7_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_8_en & mem_m_MPORT_8_mask) begin
- mem_m[mem_m_MPORT_8_addr] <= mem_m_MPORT_8_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_9_en & mem_m_MPORT_9_mask) begin
- mem_m[mem_m_MPORT_9_addr] <= mem_m_MPORT_9_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_10_en & mem_m_MPORT_10_mask) begin
- mem_m[mem_m_MPORT_10_addr] <= mem_m_MPORT_10_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_11_en & mem_m_MPORT_11_mask) begin
- mem_m[mem_m_MPORT_11_addr] <= mem_m_MPORT_11_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_12_en & mem_m_MPORT_12_mask) begin
- mem_m[mem_m_MPORT_12_addr] <= mem_m_MPORT_12_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_13_en & mem_m_MPORT_13_mask) begin
- mem_m[mem_m_MPORT_13_addr] <= mem_m_MPORT_13_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_14_en & mem_m_MPORT_14_mask) begin
- mem_m[mem_m_MPORT_14_addr] <= mem_m_MPORT_14_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_15_en & mem_m_MPORT_15_mask) begin
- mem_m[mem_m_MPORT_15_addr] <= mem_m_MPORT_15_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_16_en & mem_m_MPORT_16_mask) begin
- mem_m[mem_m_MPORT_16_addr] <= mem_m_MPORT_16_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_17_en & mem_m_MPORT_17_mask) begin
- mem_m[mem_m_MPORT_17_addr] <= mem_m_MPORT_17_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_18_en & mem_m_MPORT_18_mask) begin
- mem_m[mem_m_MPORT_18_addr] <= mem_m_MPORT_18_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_19_en & mem_m_MPORT_19_mask) begin
- mem_m[mem_m_MPORT_19_addr] <= mem_m_MPORT_19_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_20_en & mem_m_MPORT_20_mask) begin
- mem_m[mem_m_MPORT_20_addr] <= mem_m_MPORT_20_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_21_en & mem_m_MPORT_21_mask) begin
- mem_m[mem_m_MPORT_21_addr] <= mem_m_MPORT_21_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_22_en & mem_m_MPORT_22_mask) begin
- mem_m[mem_m_MPORT_22_addr] <= mem_m_MPORT_22_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_23_en & mem_m_MPORT_23_mask) begin
- mem_m[mem_m_MPORT_23_addr] <= mem_m_MPORT_23_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_24_en & mem_m_MPORT_24_mask) begin
- mem_m[mem_m_MPORT_24_addr] <= mem_m_MPORT_24_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_25_en & mem_m_MPORT_25_mask) begin
- mem_m[mem_m_MPORT_25_addr] <= mem_m_MPORT_25_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_26_en & mem_m_MPORT_26_mask) begin
- mem_m[mem_m_MPORT_26_addr] <= mem_m_MPORT_26_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_27_en & mem_m_MPORT_27_mask) begin
- mem_m[mem_m_MPORT_27_addr] <= mem_m_MPORT_27_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_28_en & mem_m_MPORT_28_mask) begin
- mem_m[mem_m_MPORT_28_addr] <= mem_m_MPORT_28_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_29_en & mem_m_MPORT_29_mask) begin
- mem_m[mem_m_MPORT_29_addr] <= mem_m_MPORT_29_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_30_en & mem_m_MPORT_30_mask) begin
- mem_m[mem_m_MPORT_30_addr] <= mem_m_MPORT_30_data; // @[Fifo4e.scala 43:16]
- end
- if (mem_m_MPORT_31_en & mem_m_MPORT_31_mask) begin
- mem_m[mem_m_MPORT_31_addr] <= mem_m_MPORT_31_data; // @[Fifo4e.scala 43:16]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(mcount <= 4'h8)) begin
- $fatal; // @[Fifo4e.scala 137:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(mcount <= 4'h8)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Fifo4e.scala:137 assert(mcount <= n.U)\n"); // @[Fifo4e.scala 137:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in0pos <= 3'h0; // @[Fifo4e.scala 68:12]
- end else if (ivalid) begin // @[Fifo4e.scala 45:23]
- in0pos <= in0pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in1pos <= 3'h1; // @[Fifo4e.scala 69:12]
- end else if (ivalid) begin // @[Fifo4e.scala 46:23]
- in1pos <= in1pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in2pos <= 3'h2; // @[Fifo4e.scala 70:12]
- end else if (ivalid) begin // @[Fifo4e.scala 47:23]
- in2pos <= in2pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 67:17]
- in3pos <= 3'h3; // @[Fifo4e.scala 71:12]
- end else if (ivalid) begin // @[Fifo4e.scala 48:23]
- in3pos <= in3pos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 74:17]
- outpos <= 3'h0; // @[Fifo4e.scala 75:12]
- end else if (dec) begin // @[Fifo4e.scala 49:23]
- outpos <= outpos_d;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 81:27]
- mcount <= 4'h0; // @[Fifo4e.scala 83:12]
- end else if (ivalid | dec) begin // @[Fifo4e.scala 50:23]
- mcount <= nxtcount;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 81:27]
- nempty <= 1'h0; // @[Fifo4e.scala 84:12]
- end else if (ivalid | dec) begin // @[Fifo4e.scala 51:23]
- nempty <= nxtcount != 4'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Fifo4e.scala 126:69]
- active <= 8'h0; // @[Fifo4e.scala 127:12]
- end else if (_T) begin // @[Fifo4e.scala 118:23]
- active <= _active_T_2;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_MEM_INIT
- _RAND_0 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_op[initvar] = _RAND_0[6:0];
- _RAND_1 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_addr[initvar] = _RAND_1[31:0];
- _RAND_2 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_offset[initvar] = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_remain[initvar] = _RAND_3[7:0];
- _RAND_4 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vs_valid[initvar] = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vs_addr[initvar] = _RAND_5[5:0];
- _RAND_6 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_vs_tag[initvar] = _RAND_6[3:0];
- _RAND_7 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_tin_quad[initvar] = _RAND_7[1:0];
- _RAND_8 = {1{`RANDOM}};
- for (initvar = 0; initvar < 8; initvar = initvar+1)
- mem_m[initvar] = _RAND_8[0:0];
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
- _RAND_9 = {1{`RANDOM}};
- in0pos = _RAND_9[2:0];
- _RAND_10 = {1{`RANDOM}};
- in1pos = _RAND_10[2:0];
- _RAND_11 = {1{`RANDOM}};
- in2pos = _RAND_11[2:0];
- _RAND_12 = {1{`RANDOM}};
- in3pos = _RAND_12[2:0];
- _RAND_13 = {1{`RANDOM}};
- outpos = _RAND_13[2:0];
- _RAND_14 = {1{`RANDOM}};
- mcount = _RAND_14[3:0];
- _RAND_15 = {1{`RANDOM}};
- nempty = _RAND_15[0:0];
- _RAND_16 = {1{`RANDOM}};
- active = _RAND_16[7:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- in0pos = 3'h0;
- end
- if (reset) begin
- in1pos = 3'h1;
- end
- if (reset) begin
- in2pos = 3'h2;
- end
- if (reset) begin
- in3pos = 3'h3;
- end
- if (reset) begin
- outpos = 3'h0;
- end
- if (reset) begin
- mcount = 4'h0;
- end
- if (reset) begin
- nempty = 1'h0;
- end
- if (reset) begin
- active = 8'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VCmdq_5(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_op,
- input [2:0] io_in_bits_0_bits_f2,
- input [2:0] io_in_bits_0_bits_sz,
- input io_in_bits_0_bits_m,
- input io_in_bits_0_bits_vs_valid,
- input [5:0] io_in_bits_0_bits_vs_addr,
- input [3:0] io_in_bits_0_bits_vs_tag,
- input [31:0] io_in_bits_0_bits_sv_addr,
- input [31:0] io_in_bits_0_bits_sv_data,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_op,
- input [2:0] io_in_bits_1_bits_f2,
- input [2:0] io_in_bits_1_bits_sz,
- input io_in_bits_1_bits_m,
- input io_in_bits_1_bits_vs_valid,
- input [5:0] io_in_bits_1_bits_vs_addr,
- input [3:0] io_in_bits_1_bits_vs_tag,
- input [31:0] io_in_bits_1_bits_sv_addr,
- input [31:0] io_in_bits_1_bits_sv_data,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_op,
- input [2:0] io_in_bits_2_bits_f2,
- input [2:0] io_in_bits_2_bits_sz,
- input io_in_bits_2_bits_m,
- input io_in_bits_2_bits_vs_valid,
- input [5:0] io_in_bits_2_bits_vs_addr,
- input [3:0] io_in_bits_2_bits_vs_tag,
- input [31:0] io_in_bits_2_bits_sv_addr,
- input [31:0] io_in_bits_2_bits_sv_data,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_op,
- input [2:0] io_in_bits_3_bits_f2,
- input [2:0] io_in_bits_3_bits_sz,
- input io_in_bits_3_bits_m,
- input io_in_bits_3_bits_vs_valid,
- input [5:0] io_in_bits_3_bits_vs_addr,
- input [3:0] io_in_bits_3_bits_vs_tag,
- input [31:0] io_in_bits_3_bits_sv_addr,
- input [31:0] io_in_bits_3_bits_sv_data,
- input io_out_ready,
- output io_out_valid,
- output [6:0] io_out_bits_op,
- output [31:0] io_out_bits_addr,
- output [7:0] io_out_bits_remain,
- output io_out_bits_vs_valid,
- output [5:0] io_out_bits_vs_addr,
- output [3:0] io_out_bits_vs_tag,
- output [1:0] io_out_bits_quad,
- output [63:0] io_active,
- output io_nempty
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [63:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
-`endif // RANDOMIZE_REG_INIT
- wire f_clock; // @[Fifo4e.scala 24:11]
- wire f_reset; // @[Fifo4e.scala 24:11]
- wire f_io_in_ready; // @[Fifo4e.scala 24:11]
- wire f_io_in_valid; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_0_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_0_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_0_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [7:0] f_io_in_bits_0_bits_tin_remain; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_0_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_0_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_0_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_1_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_1_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_1_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [7:0] f_io_in_bits_1_bits_tin_remain; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_1_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_1_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_1_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_2_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_2_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_2_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [7:0] f_io_in_bits_2_bits_tin_remain; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_2_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_2_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_2_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_in_bits_3_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_3_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_in_bits_3_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [7:0] f_io_in_bits_3_bits_tin_remain; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_in_bits_3_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_in_bits_3_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire f_io_in_bits_3_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_out_ready; // @[Fifo4e.scala 24:11]
- wire f_io_out_valid; // @[Fifo4e.scala 24:11]
- wire [6:0] f_io_out_bits_tin_op; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_out_bits_tin_addr; // @[Fifo4e.scala 24:11]
- wire [31:0] f_io_out_bits_tin_offset; // @[Fifo4e.scala 24:11]
- wire [7:0] f_io_out_bits_tin_remain; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_out_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire [3:0] f_io_out_bits_tin_vs_tag; // @[Fifo4e.scala 24:11]
- wire [1:0] f_io_out_bits_tin_quad; // @[Fifo4e.scala 24:11]
- wire f_io_out_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_0_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_0_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_1_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_1_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_2_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_2_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_3_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_3_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_4_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_4_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_5_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_5_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_6_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_6_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_valid; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_bits_tin_vs_valid; // @[Fifo4e.scala 24:11]
- wire [5:0] f_io_entry_7_bits_tin_vs_addr; // @[Fifo4e.scala 24:11]
- wire f_io_entry_7_bits_m; // @[Fifo4e.scala 24:11]
- wire f_io_nempty; // @[Fifo4e.scala 24:11]
- reg [63:0] active; // @[VCmdq.scala 49:23]
- reg valid; // @[VCmdq.scala 51:22]
- reg [6:0] value_tin_op; // @[VCmdq.scala 53:18]
- reg [31:0] value_tin_addr; // @[VCmdq.scala 53:18]
- reg [31:0] value_tin_offset; // @[VCmdq.scala 53:18]
- reg [7:0] value_tin_remain; // @[VCmdq.scala 53:18]
- reg value_tin_vs_valid; // @[VCmdq.scala 53:18]
- reg [5:0] value_tin_vs_addr; // @[VCmdq.scala 53:18]
- reg [3:0] value_tin_vs_tag; // @[VCmdq.scala 53:18]
- reg [1:0] value_tin_quad; // @[VCmdq.scala 53:18]
- reg value_m; // @[VCmdq.scala 53:18]
- reg [4:0] step; // @[VCmdq.scala 58:21]
- wire _addrAlign_T = value_tin_op == 7'h4; // @[VSt.scala 126:31]
- wire [4:0] addrAlign = value_tin_op == 7'h4 ? {{2'd0}, value_tin_addr[2:0]} : value_tin_addr[4:0]; // @[VSt.scala 126:24]
- wire [4:0] offsAlign = _addrAlign_T ? {{2'd0}, value_tin_offset[2:0]} : value_tin_offset[4:0]; // @[VSt.scala 127:24]
- wire _T_2 = ~reset; // @[VSt.scala 128:11]
- wire _T_8 = ~valid; // @[VSt.scala 130:12]
- wire [7:0] fmaxvlb = _addrAlign_T ? 8'h8 : 8'h20; // @[VSt.scala 136:22]
- wire _outlast1_T = ~value_m; // @[VSt.scala 138:20]
- wire _last1_T_1 = step == 5'h3; // @[VSt.scala 142:28]
- wire last1 = _outlast1_T | step == 5'h3; // @[VSt.scala 142:20]
- wire last2 = value_m ? step == 5'hf : _last1_T_1; // @[VSt.scala 143:20]
- wire last = _addrAlign_T ? last2 : last1; // @[VSt.scala 144:19]
- wire [5:0] _out_vs_addr_T_4 = value_tin_vs_addr + 6'h1; // @[VSt.scala 148:74]
- wire [5:0] tin_vs_addr = _addrAlign_T & step[1:0] != 2'h3 ? value_tin_vs_addr : _out_vs_addr_T_4; // @[VSt.scala 148:23]
- wire [31:0] tin_addr = value_tin_addr + value_tin_offset; // @[VSt.scala 150:27]
- wire [7:0] _out_remain_T_2 = value_tin_remain - fmaxvlb; // @[VSt.scala 151:60]
- wire [7:0] tin_remain = value_tin_remain <= fmaxvlb ? 8'h0 : _out_remain_T_2; // @[VSt.scala 151:22]
- wire [4:0] _out_quad_T_2 = step + 5'h1; // @[VSt.scala 155:46]
- wire [4:0] _out_quad_T_3 = _addrAlign_T ? _out_quad_T_2 : 5'h0; // @[VSt.scala 155:20]
- wire f_io_in_bits_0_bits_tin_stride = io_in_bits_0_bits_f2[1]; // @[VSt.scala 94:23]
- wire f_io_in_bits_0_bits_tin_length = io_in_bits_0_bits_f2[0]; // @[VSt.scala 95:23]
- wire [1:0] _f_io_in_bits_0_bits_tin_T_3 = io_in_bits_0_bits_sz[1] + io_in_bits_0_bits_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_55 = {{1'd0}, io_in_bits_0_bits_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _f_io_in_bits_0_bits_tin_T_5 = _GEN_55 + _f_io_in_bits_0_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_0_bits_tin_T_12 = ~io_in_bits_0_bits_vs_valid; // @[VSt.scala 97:36]
- wire _f_io_in_bits_0_bits_tin_T_18 = io_in_bits_0_bits_op == 7'h4; // @[VSt.scala 98:20]
- wire [7:0] f_io_in_bits_0_bits_tin_limit = io_in_bits_0_bits_m ? 8'h80 : 8'h20; // @[VSt.scala 100:20]
- wire [31:0] _f_io_in_bits_0_bits_tin_data_T_1 = io_in_bits_0_bits_sz[0] ? io_in_bits_0_bits_sv_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _f_io_in_bits_0_bits_tin_data_T_3 = {io_in_bits_0_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _f_io_in_bits_0_bits_tin_data_T_4 = io_in_bits_0_bits_sz[1] ? _f_io_in_bits_0_bits_tin_data_T_3 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_56 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_1}; // @[VSt.scala 102:44]
- wire [32:0] _f_io_in_bits_0_bits_tin_data_T_5 = _GEN_56 | _f_io_in_bits_0_bits_tin_data_T_4; // @[VSt.scala 102:44]
- wire [33:0] _f_io_in_bits_0_bits_tin_data_T_7 = {io_in_bits_0_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _f_io_in_bits_0_bits_tin_data_T_8 = io_in_bits_0_bits_sz[2] ? _f_io_in_bits_0_bits_tin_data_T_7 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_57 = {{1'd0}, _f_io_in_bits_0_bits_tin_data_T_5}; // @[VSt.scala 103:59]
- wire [33:0] f_io_in_bits_0_bits_tin_data = _GEN_57 | _f_io_in_bits_0_bits_tin_data_T_8; // @[VSt.scala 103:59]
- wire [33:0] _GEN_58 = {{26'd0}, f_io_in_bits_0_bits_tin_limit}; // @[VSt.scala 107:28]
- wire [33:0] _f_io_in_bits_0_bits_tin_remain1_T_1 = f_io_in_bits_0_bits_tin_data > _GEN_58 ? {{26'd0},
- f_io_in_bits_0_bits_tin_limit} : f_io_in_bits_0_bits_tin_data; // @[VSt.scala 107:22]
- wire [7:0] f_io_in_bits_0_bits_tin_remain1 = _f_io_in_bits_0_bits_tin_remain1_T_1[7:0]; // @[VSt.scala 107:49]
- wire [7:0] _f_io_in_bits_0_bits_tin_out_offset_T_3 = _f_io_in_bits_0_bits_tin_T_18 ? 8'h8 : 8'h20; // @[VSt.scala 115:46]
- wire f_io_in_bits_1_bits_tin_stride = io_in_bits_1_bits_f2[1]; // @[VSt.scala 94:23]
- wire f_io_in_bits_1_bits_tin_length = io_in_bits_1_bits_f2[0]; // @[VSt.scala 95:23]
- wire [1:0] _f_io_in_bits_1_bits_tin_T_3 = io_in_bits_1_bits_sz[1] + io_in_bits_1_bits_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_59 = {{1'd0}, io_in_bits_1_bits_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _f_io_in_bits_1_bits_tin_T_5 = _GEN_59 + _f_io_in_bits_1_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_1_bits_tin_T_12 = ~io_in_bits_1_bits_vs_valid; // @[VSt.scala 97:36]
- wire _f_io_in_bits_1_bits_tin_T_18 = io_in_bits_1_bits_op == 7'h4; // @[VSt.scala 98:20]
- wire [7:0] f_io_in_bits_1_bits_tin_limit = io_in_bits_1_bits_m ? 8'h80 : 8'h20; // @[VSt.scala 100:20]
- wire [31:0] _f_io_in_bits_1_bits_tin_data_T_1 = io_in_bits_1_bits_sz[0] ? io_in_bits_1_bits_sv_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _f_io_in_bits_1_bits_tin_data_T_3 = {io_in_bits_1_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _f_io_in_bits_1_bits_tin_data_T_4 = io_in_bits_1_bits_sz[1] ? _f_io_in_bits_1_bits_tin_data_T_3 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_60 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_1}; // @[VSt.scala 102:44]
- wire [32:0] _f_io_in_bits_1_bits_tin_data_T_5 = _GEN_60 | _f_io_in_bits_1_bits_tin_data_T_4; // @[VSt.scala 102:44]
- wire [33:0] _f_io_in_bits_1_bits_tin_data_T_7 = {io_in_bits_1_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _f_io_in_bits_1_bits_tin_data_T_8 = io_in_bits_1_bits_sz[2] ? _f_io_in_bits_1_bits_tin_data_T_7 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_61 = {{1'd0}, _f_io_in_bits_1_bits_tin_data_T_5}; // @[VSt.scala 103:59]
- wire [33:0] f_io_in_bits_1_bits_tin_data = _GEN_61 | _f_io_in_bits_1_bits_tin_data_T_8; // @[VSt.scala 103:59]
- wire [33:0] _GEN_62 = {{26'd0}, f_io_in_bits_1_bits_tin_limit}; // @[VSt.scala 107:28]
- wire [33:0] _f_io_in_bits_1_bits_tin_remain1_T_1 = f_io_in_bits_1_bits_tin_data > _GEN_62 ? {{26'd0},
- f_io_in_bits_1_bits_tin_limit} : f_io_in_bits_1_bits_tin_data; // @[VSt.scala 107:22]
- wire [7:0] f_io_in_bits_1_bits_tin_remain1 = _f_io_in_bits_1_bits_tin_remain1_T_1[7:0]; // @[VSt.scala 107:49]
- wire [7:0] _f_io_in_bits_1_bits_tin_out_offset_T_3 = _f_io_in_bits_1_bits_tin_T_18 ? 8'h8 : 8'h20; // @[VSt.scala 115:46]
- wire f_io_in_bits_2_bits_tin_stride = io_in_bits_2_bits_f2[1]; // @[VSt.scala 94:23]
- wire f_io_in_bits_2_bits_tin_length = io_in_bits_2_bits_f2[0]; // @[VSt.scala 95:23]
- wire [1:0] _f_io_in_bits_2_bits_tin_T_3 = io_in_bits_2_bits_sz[1] + io_in_bits_2_bits_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_63 = {{1'd0}, io_in_bits_2_bits_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _f_io_in_bits_2_bits_tin_T_5 = _GEN_63 + _f_io_in_bits_2_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_2_bits_tin_T_12 = ~io_in_bits_2_bits_vs_valid; // @[VSt.scala 97:36]
- wire _f_io_in_bits_2_bits_tin_T_18 = io_in_bits_2_bits_op == 7'h4; // @[VSt.scala 98:20]
- wire [7:0] f_io_in_bits_2_bits_tin_limit = io_in_bits_2_bits_m ? 8'h80 : 8'h20; // @[VSt.scala 100:20]
- wire [31:0] _f_io_in_bits_2_bits_tin_data_T_1 = io_in_bits_2_bits_sz[0] ? io_in_bits_2_bits_sv_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _f_io_in_bits_2_bits_tin_data_T_3 = {io_in_bits_2_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _f_io_in_bits_2_bits_tin_data_T_4 = io_in_bits_2_bits_sz[1] ? _f_io_in_bits_2_bits_tin_data_T_3 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_64 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_1}; // @[VSt.scala 102:44]
- wire [32:0] _f_io_in_bits_2_bits_tin_data_T_5 = _GEN_64 | _f_io_in_bits_2_bits_tin_data_T_4; // @[VSt.scala 102:44]
- wire [33:0] _f_io_in_bits_2_bits_tin_data_T_7 = {io_in_bits_2_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _f_io_in_bits_2_bits_tin_data_T_8 = io_in_bits_2_bits_sz[2] ? _f_io_in_bits_2_bits_tin_data_T_7 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_65 = {{1'd0}, _f_io_in_bits_2_bits_tin_data_T_5}; // @[VSt.scala 103:59]
- wire [33:0] f_io_in_bits_2_bits_tin_data = _GEN_65 | _f_io_in_bits_2_bits_tin_data_T_8; // @[VSt.scala 103:59]
- wire [33:0] _GEN_66 = {{26'd0}, f_io_in_bits_2_bits_tin_limit}; // @[VSt.scala 107:28]
- wire [33:0] _f_io_in_bits_2_bits_tin_remain1_T_1 = f_io_in_bits_2_bits_tin_data > _GEN_66 ? {{26'd0},
- f_io_in_bits_2_bits_tin_limit} : f_io_in_bits_2_bits_tin_data; // @[VSt.scala 107:22]
- wire [7:0] f_io_in_bits_2_bits_tin_remain1 = _f_io_in_bits_2_bits_tin_remain1_T_1[7:0]; // @[VSt.scala 107:49]
- wire [7:0] _f_io_in_bits_2_bits_tin_out_offset_T_3 = _f_io_in_bits_2_bits_tin_T_18 ? 8'h8 : 8'h20; // @[VSt.scala 115:46]
- wire f_io_in_bits_3_bits_tin_stride = io_in_bits_3_bits_f2[1]; // @[VSt.scala 94:23]
- wire f_io_in_bits_3_bits_tin_length = io_in_bits_3_bits_f2[0]; // @[VSt.scala 95:23]
- wire [1:0] _f_io_in_bits_3_bits_tin_T_3 = io_in_bits_3_bits_sz[1] + io_in_bits_3_bits_sz[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_67 = {{1'd0}, io_in_bits_3_bits_sz[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _f_io_in_bits_3_bits_tin_T_5 = _GEN_67 + _f_io_in_bits_3_bits_tin_T_3; // @[Bitwise.scala 48:55]
- wire _f_io_in_bits_3_bits_tin_T_12 = ~io_in_bits_3_bits_vs_valid; // @[VSt.scala 97:36]
- wire _f_io_in_bits_3_bits_tin_T_18 = io_in_bits_3_bits_op == 7'h4; // @[VSt.scala 98:20]
- wire [7:0] f_io_in_bits_3_bits_tin_limit = io_in_bits_3_bits_m ? 8'h80 : 8'h20; // @[VSt.scala 100:20]
- wire [31:0] _f_io_in_bits_3_bits_tin_data_T_1 = io_in_bits_3_bits_sz[0] ? io_in_bits_3_bits_sv_data : 32'h0; // @[Library.scala 22:8]
- wire [32:0] _f_io_in_bits_3_bits_tin_data_T_3 = {io_in_bits_3_bits_sv_data,1'h0}; // @[Cat.scala 31:58]
- wire [32:0] _f_io_in_bits_3_bits_tin_data_T_4 = io_in_bits_3_bits_sz[1] ? _f_io_in_bits_3_bits_tin_data_T_3 : 33'h0; // @[Library.scala 22:8]
- wire [32:0] _GEN_68 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_1}; // @[VSt.scala 102:44]
- wire [32:0] _f_io_in_bits_3_bits_tin_data_T_5 = _GEN_68 | _f_io_in_bits_3_bits_tin_data_T_4; // @[VSt.scala 102:44]
- wire [33:0] _f_io_in_bits_3_bits_tin_data_T_7 = {io_in_bits_3_bits_sv_data,2'h0}; // @[Cat.scala 31:58]
- wire [33:0] _f_io_in_bits_3_bits_tin_data_T_8 = io_in_bits_3_bits_sz[2] ? _f_io_in_bits_3_bits_tin_data_T_7 : 34'h0; // @[Library.scala 22:8]
- wire [33:0] _GEN_69 = {{1'd0}, _f_io_in_bits_3_bits_tin_data_T_5}; // @[VSt.scala 103:59]
- wire [33:0] f_io_in_bits_3_bits_tin_data = _GEN_69 | _f_io_in_bits_3_bits_tin_data_T_8; // @[VSt.scala 103:59]
- wire [33:0] _GEN_70 = {{26'd0}, f_io_in_bits_3_bits_tin_limit}; // @[VSt.scala 107:28]
- wire [33:0] _f_io_in_bits_3_bits_tin_remain1_T_1 = f_io_in_bits_3_bits_tin_data > _GEN_70 ? {{26'd0},
- f_io_in_bits_3_bits_tin_limit} : f_io_in_bits_3_bits_tin_data; // @[VSt.scala 107:22]
- wire [7:0] f_io_in_bits_3_bits_tin_remain1 = _f_io_in_bits_3_bits_tin_remain1_T_1[7:0]; // @[VSt.scala 107:49]
- wire [7:0] _f_io_in_bits_3_bits_tin_out_offset_T_3 = _f_io_in_bits_3_bits_tin_T_18 ? 8'h8 : 8'h20; // @[VSt.scala 115:46]
- wire _T_17 = io_out_valid & io_out_ready; // @[VCmdq.scala 81:29]
- wire _T_18 = ~last; // @[VCmdq.scala 82:11]
- wire [1:0] tin_quad = _out_quad_T_3[1:0]; // @[VSt.scala 132:19 155:14]
- wire _GEN_5 = ~last & value_tin_vs_valid; // @[VCmdq.scala 82:18 84:17 90:17]
- wire _GEN_12 = ~last & value_m; // @[VCmdq.scala 82:18 85:15 91:15]
- wire _GEN_14 = io_out_valid & io_out_ready ? _T_18 : valid; // @[VCmdq.scala 51:22 81:46]
- wire _T_22 = io_in_valid & io_in_ready | _T_17; // @[VCmdq.scala 118:36]
- wire _fvalid_T = f_io_in_valid & f_io_in_ready; // @[VCmdq.scala 119:38]
- wire [3:0] _fvalid_T_1 = {f_io_in_bits_3_valid,f_io_in_bits_2_valid,f_io_in_bits_1_valid,f_io_in_bits_0_valid}; // @[Cat.scala 31:58]
- wire [3:0] fvalid = _fvalid_T ? _fvalid_T_1 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount = f_io_in_bits_0_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh = 16'h1 << active_active_oh_shiftAmount; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo = {3'h0,active_active_oh[3],3'h0,active_active_oh[2],3'h0,active_active_oh[1],3'h0
- ,active_active_oh[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo = {3'h0,active_active_oh[7],3'h0,active_active_oh[6],3'h0,active_active_oh[5],3'h0,
- active_active_oh[4],active_active_oh0_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo = {3'h0,active_active_oh[11],3'h0,active_active_oh[10],3'h0,active_active_oh[9],3'h0
- ,active_active_oh[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0 = {3'h0,active_active_oh[15],3'h0,active_active_oh[14],3'h0,active_active_oh[13],3'h0,
- active_active_oh[12],active_active_oh0_hi_lo,active_active_oh0_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo = {2'h0,active_active_oh[1],1'h0,2'h0,active_active_oh[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo = {2'h0,active_active_oh[3],1'h0,2'h0,active_active_oh[2],1'h0,
- active_active_oh1_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo = {2'h0,active_active_oh[5],1'h0,2'h0,active_active_oh[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo = {2'h0,active_active_oh[7],1'h0,2'h0,active_active_oh[6],1'h0,
- active_active_oh1_lo_hi_lo,active_active_oh1_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo = {2'h0,active_active_oh[9],1'h0,2'h0,active_active_oh[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo = {2'h0,active_active_oh[11],1'h0,2'h0,active_active_oh[10],1'h0,
- active_active_oh1_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo = {2'h0,active_active_oh[13],1'h0,2'h0,active_active_oh[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1 = {2'h0,active_active_oh[15],1'h0,2'h0,active_active_oh[14],1'h0,
- active_active_oh1_hi_hi_lo,active_active_oh1_hi_lo,active_active_oh1_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo = {1'h0,active_active_oh[1],2'h0,1'h0,active_active_oh[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo = {1'h0,active_active_oh[3],2'h0,1'h0,active_active_oh[2],2'h0,
- active_active_oh2_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo = {1'h0,active_active_oh[5],2'h0,1'h0,active_active_oh[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo = {1'h0,active_active_oh[7],2'h0,1'h0,active_active_oh[6],2'h0,
- active_active_oh2_lo_hi_lo,active_active_oh2_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo = {1'h0,active_active_oh[9],2'h0,1'h0,active_active_oh[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo = {1'h0,active_active_oh[11],2'h0,1'h0,active_active_oh[10],2'h0,
- active_active_oh2_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo = {1'h0,active_active_oh[13],2'h0,1'h0,active_active_oh[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2 = {1'h0,active_active_oh[15],2'h0,1'h0,active_active_oh[14],2'h0,
- active_active_oh2_hi_hi_lo,active_active_oh2_hi_lo,active_active_oh2_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo = {active_active_oh[3],3'h0,active_active_oh[2],3'h0,active_active_oh[1],3'h0,
- active_active_oh[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo = {active_active_oh[7],3'h0,active_active_oh[6],3'h0,active_active_oh[5],3'h0,
- active_active_oh[4],3'h0,active_active_oh3_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo = {active_active_oh[11],3'h0,active_active_oh[10],3'h0,active_active_oh[9],3'h0,
- active_active_oh[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3 = {active_active_oh[15],3'h0,active_active_oh[14],3'h0,active_active_oh[13],3'h0,
- active_active_oh[12],3'h0,active_active_oh3_hi_lo,active_active_oh3_lo}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx = f_io_in_bits_0_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T = ~f_io_in_bits_0_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_4 = f_io_in_bits_0_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_5 = ~f_io_in_bits_0_bits_m & active_active_idx == 2'h0 | f_io_in_bits_0_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_6 = _active_active_active_T_5 ? active_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_12 = _active_active_active_T & active_active_idx == 2'h1 | _active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_13 = _active_active_active_T_12 ? active_active_oh1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_14 = _active_active_active_T_6 | _active_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active_active_T_20 = _active_active_active_T & active_active_idx == 2'h2 | _active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_21 = _active_active_active_T_20 ? active_active_oh2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_22 = _active_active_active_T_14 | _active_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active_active_T_28 = _active_active_active_T & active_active_idx == 2'h3 | _active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_29 = _active_active_active_T_28 ? active_active_oh3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active = _active_active_active_T_22 | _active_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] active_active = f_io_in_bits_0_bits_tin_vs_valid ? active_active_active : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_1 = fvalid[0] ? active_active : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_oh_shiftAmount_1 = f_io_in_bits_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_1 = 16'h1 << active_active_oh_shiftAmount_1; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_1 = {3'h0,active_active_oh_1[3],3'h0,active_active_oh_1[2],3'h0,active_active_oh_1
- [1],3'h0,active_active_oh_1[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_1 = {3'h0,active_active_oh_1[7],3'h0,active_active_oh_1[6],3'h0,active_active_oh_1[5]
- ,3'h0,active_active_oh_1[4],active_active_oh0_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_1 = {3'h0,active_active_oh_1[11],3'h0,active_active_oh_1[10],3'h0,
- active_active_oh_1[9],3'h0,active_active_oh_1[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_1 = {3'h0,active_active_oh_1[15],3'h0,active_active_oh_1[14],3'h0,active_active_oh_1[13]
- ,3'h0,active_active_oh_1[12],active_active_oh0_hi_lo_1,active_active_oh0_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_1 = {2'h0,active_active_oh_1[1],1'h0,2'h0,active_active_oh_1[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_1 = {2'h0,active_active_oh_1[3],1'h0,2'h0,active_active_oh_1[2],1'h0,
- active_active_oh1_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_1 = {2'h0,active_active_oh_1[5],1'h0,2'h0,active_active_oh_1[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_1 = {2'h0,active_active_oh_1[7],1'h0,2'h0,active_active_oh_1[6],1'h0,
- active_active_oh1_lo_hi_lo_1,active_active_oh1_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_1 = {2'h0,active_active_oh_1[9],1'h0,2'h0,active_active_oh_1[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_1 = {2'h0,active_active_oh_1[11],1'h0,2'h0,active_active_oh_1[10],1'h0,
- active_active_oh1_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_1 = {2'h0,active_active_oh_1[13],1'h0,2'h0,active_active_oh_1[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_1 = {2'h0,active_active_oh_1[15],1'h0,2'h0,active_active_oh_1[14],1'h0,
- active_active_oh1_hi_hi_lo_1,active_active_oh1_hi_lo_1,active_active_oh1_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_1 = {1'h0,active_active_oh_1[1],2'h0,1'h0,active_active_oh_1[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_1 = {1'h0,active_active_oh_1[3],2'h0,1'h0,active_active_oh_1[2],2'h0,
- active_active_oh2_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_1 = {1'h0,active_active_oh_1[5],2'h0,1'h0,active_active_oh_1[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_1 = {1'h0,active_active_oh_1[7],2'h0,1'h0,active_active_oh_1[6],2'h0,
- active_active_oh2_lo_hi_lo_1,active_active_oh2_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_1 = {1'h0,active_active_oh_1[9],2'h0,1'h0,active_active_oh_1[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_1 = {1'h0,active_active_oh_1[11],2'h0,1'h0,active_active_oh_1[10],2'h0,
- active_active_oh2_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_1 = {1'h0,active_active_oh_1[13],2'h0,1'h0,active_active_oh_1[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_1 = {1'h0,active_active_oh_1[15],2'h0,1'h0,active_active_oh_1[14],2'h0,
- active_active_oh2_hi_hi_lo_1,active_active_oh2_hi_lo_1,active_active_oh2_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_1 = {active_active_oh_1[3],3'h0,active_active_oh_1[2],3'h0,active_active_oh_1[1],3'h0
- ,active_active_oh_1[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_1 = {active_active_oh_1[7],3'h0,active_active_oh_1[6],3'h0,active_active_oh_1[5],3'h0
- ,active_active_oh_1[4],3'h0,active_active_oh3_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_1 = {active_active_oh_1[11],3'h0,active_active_oh_1[10],3'h0,active_active_oh_1[9]
- ,3'h0,active_active_oh_1[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_1 = {active_active_oh_1[15],3'h0,active_active_oh_1[14],3'h0,active_active_oh_1[13],3'h0
- ,active_active_oh_1[12],3'h0,active_active_oh3_hi_lo_1,active_active_oh3_lo_1}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_1 = f_io_in_bits_1_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_30 = ~f_io_in_bits_1_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_34 = f_io_in_bits_1_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_35 = ~f_io_in_bits_1_bits_m & active_active_idx_1 == 2'h0 | f_io_in_bits_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_36 = _active_active_active_T_35 ? active_active_oh0_1 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_42 = _active_active_active_T_30 & active_active_idx_1 == 2'h1 |
- _active_active_active_T_34; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_43 = _active_active_active_T_42 ? active_active_oh1_1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_44 = _active_active_active_T_36 | _active_active_active_T_43; // @[VCommon.scala 107:68]
- wire _active_active_active_T_50 = _active_active_active_T_30 & active_active_idx_1 == 2'h2 |
- _active_active_active_T_34; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_51 = _active_active_active_T_50 ? active_active_oh2_1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_52 = _active_active_active_T_44 | _active_active_active_T_51; // @[VCommon.scala 108:68]
- wire _active_active_active_T_58 = _active_active_active_T_30 & active_active_idx_1 == 2'h3 |
- _active_active_active_T_34; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_59 = _active_active_active_T_58 ? active_active_oh3_1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_1 = _active_active_active_T_52 | _active_active_active_T_59; // @[VCommon.scala 109:68]
- wire [63:0] active_active_1 = f_io_in_bits_1_bits_tin_vs_valid ? active_active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_3 = fvalid[1] ? active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_4 = _active_T_1 | _active_T_3; // @[VCmdq.scala 124:90]
- wire [3:0] active_active_oh_shiftAmount_2 = f_io_in_bits_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_2 = 16'h1 << active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_2 = {3'h0,active_active_oh_2[3],3'h0,active_active_oh_2[2],3'h0,active_active_oh_2
- [1],3'h0,active_active_oh_2[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_2 = {3'h0,active_active_oh_2[7],3'h0,active_active_oh_2[6],3'h0,active_active_oh_2[5]
- ,3'h0,active_active_oh_2[4],active_active_oh0_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_2 = {3'h0,active_active_oh_2[11],3'h0,active_active_oh_2[10],3'h0,
- active_active_oh_2[9],3'h0,active_active_oh_2[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_2 = {3'h0,active_active_oh_2[15],3'h0,active_active_oh_2[14],3'h0,active_active_oh_2[13]
- ,3'h0,active_active_oh_2[12],active_active_oh0_hi_lo_2,active_active_oh0_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_2 = {2'h0,active_active_oh_2[1],1'h0,2'h0,active_active_oh_2[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_2 = {2'h0,active_active_oh_2[3],1'h0,2'h0,active_active_oh_2[2],1'h0,
- active_active_oh1_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_2 = {2'h0,active_active_oh_2[5],1'h0,2'h0,active_active_oh_2[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_2 = {2'h0,active_active_oh_2[7],1'h0,2'h0,active_active_oh_2[6],1'h0,
- active_active_oh1_lo_hi_lo_2,active_active_oh1_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_2 = {2'h0,active_active_oh_2[9],1'h0,2'h0,active_active_oh_2[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_2 = {2'h0,active_active_oh_2[11],1'h0,2'h0,active_active_oh_2[10],1'h0,
- active_active_oh1_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_2 = {2'h0,active_active_oh_2[13],1'h0,2'h0,active_active_oh_2[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_2 = {2'h0,active_active_oh_2[15],1'h0,2'h0,active_active_oh_2[14],1'h0,
- active_active_oh1_hi_hi_lo_2,active_active_oh1_hi_lo_2,active_active_oh1_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_2 = {1'h0,active_active_oh_2[1],2'h0,1'h0,active_active_oh_2[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_2 = {1'h0,active_active_oh_2[3],2'h0,1'h0,active_active_oh_2[2],2'h0,
- active_active_oh2_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_2 = {1'h0,active_active_oh_2[5],2'h0,1'h0,active_active_oh_2[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_2 = {1'h0,active_active_oh_2[7],2'h0,1'h0,active_active_oh_2[6],2'h0,
- active_active_oh2_lo_hi_lo_2,active_active_oh2_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_2 = {1'h0,active_active_oh_2[9],2'h0,1'h0,active_active_oh_2[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_2 = {1'h0,active_active_oh_2[11],2'h0,1'h0,active_active_oh_2[10],2'h0,
- active_active_oh2_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_2 = {1'h0,active_active_oh_2[13],2'h0,1'h0,active_active_oh_2[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_2 = {1'h0,active_active_oh_2[15],2'h0,1'h0,active_active_oh_2[14],2'h0,
- active_active_oh2_hi_hi_lo_2,active_active_oh2_hi_lo_2,active_active_oh2_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_2 = {active_active_oh_2[3],3'h0,active_active_oh_2[2],3'h0,active_active_oh_2[1],3'h0
- ,active_active_oh_2[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_2 = {active_active_oh_2[7],3'h0,active_active_oh_2[6],3'h0,active_active_oh_2[5],3'h0
- ,active_active_oh_2[4],3'h0,active_active_oh3_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_2 = {active_active_oh_2[11],3'h0,active_active_oh_2[10],3'h0,active_active_oh_2[9]
- ,3'h0,active_active_oh_2[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_2 = {active_active_oh_2[15],3'h0,active_active_oh_2[14],3'h0,active_active_oh_2[13],3'h0
- ,active_active_oh_2[12],3'h0,active_active_oh3_hi_lo_2,active_active_oh3_lo_2}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_2 = f_io_in_bits_2_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_60 = ~f_io_in_bits_2_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_64 = f_io_in_bits_2_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_65 = ~f_io_in_bits_2_bits_m & active_active_idx_2 == 2'h0 | f_io_in_bits_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_66 = _active_active_active_T_65 ? active_active_oh0_2 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_72 = _active_active_active_T_60 & active_active_idx_2 == 2'h1 |
- _active_active_active_T_64; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_73 = _active_active_active_T_72 ? active_active_oh1_2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_74 = _active_active_active_T_66 | _active_active_active_T_73; // @[VCommon.scala 107:68]
- wire _active_active_active_T_80 = _active_active_active_T_60 & active_active_idx_2 == 2'h2 |
- _active_active_active_T_64; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_81 = _active_active_active_T_80 ? active_active_oh2_2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_82 = _active_active_active_T_74 | _active_active_active_T_81; // @[VCommon.scala 108:68]
- wire _active_active_active_T_88 = _active_active_active_T_60 & active_active_idx_2 == 2'h3 |
- _active_active_active_T_64; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_89 = _active_active_active_T_88 ? active_active_oh3_2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_2 = _active_active_active_T_82 | _active_active_active_T_89; // @[VCommon.scala 109:68]
- wire [63:0] active_active_2 = f_io_in_bits_2_bits_tin_vs_valid ? active_active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_6 = fvalid[2] ? active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_7 = _active_T_4 | _active_T_6; // @[VCmdq.scala 125:90]
- wire [3:0] active_active_oh_shiftAmount_3 = f_io_in_bits_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_oh_3 = 16'h1 << active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
- wire [15:0] active_active_oh0_lo_lo_3 = {3'h0,active_active_oh_3[3],3'h0,active_active_oh_3[2],3'h0,active_active_oh_3
- [1],3'h0,active_active_oh_3[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh0_lo_3 = {3'h0,active_active_oh_3[7],3'h0,active_active_oh_3[6],3'h0,active_active_oh_3[5]
- ,3'h0,active_active_oh_3[4],active_active_oh0_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh0_hi_lo_3 = {3'h0,active_active_oh_3[11],3'h0,active_active_oh_3[10],3'h0,
- active_active_oh_3[9],3'h0,active_active_oh_3[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh0_3 = {3'h0,active_active_oh_3[15],3'h0,active_active_oh_3[14],3'h0,active_active_oh_3[13]
- ,3'h0,active_active_oh_3[12],active_active_oh0_hi_lo_3,active_active_oh0_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_lo_lo_3 = {2'h0,active_active_oh_3[1],1'h0,2'h0,active_active_oh_3[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_lo_lo_3 = {2'h0,active_active_oh_3[3],1'h0,2'h0,active_active_oh_3[2],1'h0,
- active_active_oh1_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_lo_hi_lo_3 = {2'h0,active_active_oh_3[5],1'h0,2'h0,active_active_oh_3[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh1_lo_3 = {2'h0,active_active_oh_3[7],1'h0,2'h0,active_active_oh_3[6],1'h0,
- active_active_oh1_lo_hi_lo_3,active_active_oh1_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_lo_lo_3 = {2'h0,active_active_oh_3[9],1'h0,2'h0,active_active_oh_3[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh1_hi_lo_3 = {2'h0,active_active_oh_3[11],1'h0,2'h0,active_active_oh_3[10],1'h0,
- active_active_oh1_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh1_hi_hi_lo_3 = {2'h0,active_active_oh_3[13],1'h0,2'h0,active_active_oh_3[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh1_3 = {2'h0,active_active_oh_3[15],1'h0,2'h0,active_active_oh_3[14],1'h0,
- active_active_oh1_hi_hi_lo_3,active_active_oh1_hi_lo_3,active_active_oh1_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_lo_lo_3 = {1'h0,active_active_oh_3[1],2'h0,1'h0,active_active_oh_3[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_lo_lo_3 = {1'h0,active_active_oh_3[3],2'h0,1'h0,active_active_oh_3[2],2'h0,
- active_active_oh2_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_lo_hi_lo_3 = {1'h0,active_active_oh_3[5],2'h0,1'h0,active_active_oh_3[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh2_lo_3 = {1'h0,active_active_oh_3[7],2'h0,1'h0,active_active_oh_3[6],2'h0,
- active_active_oh2_lo_hi_lo_3,active_active_oh2_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_lo_lo_3 = {1'h0,active_active_oh_3[9],2'h0,1'h0,active_active_oh_3[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh2_hi_lo_3 = {1'h0,active_active_oh_3[11],2'h0,1'h0,active_active_oh_3[10],2'h0,
- active_active_oh2_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_oh2_hi_hi_lo_3 = {1'h0,active_active_oh_3[13],2'h0,1'h0,active_active_oh_3[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh2_3 = {1'h0,active_active_oh_3[15],2'h0,1'h0,active_active_oh_3[14],2'h0,
- active_active_oh2_hi_hi_lo_3,active_active_oh2_hi_lo_3,active_active_oh2_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_lo_lo_3 = {active_active_oh_3[3],3'h0,active_active_oh_3[2],3'h0,active_active_oh_3[1],3'h0
- ,active_active_oh_3[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_oh3_lo_3 = {active_active_oh_3[7],3'h0,active_active_oh_3[6],3'h0,active_active_oh_3[5],3'h0
- ,active_active_oh_3[4],3'h0,active_active_oh3_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_oh3_hi_lo_3 = {active_active_oh_3[11],3'h0,active_active_oh_3[10],3'h0,active_active_oh_3[9]
- ,3'h0,active_active_oh_3[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_oh3_3 = {active_active_oh_3[15],3'h0,active_active_oh_3[14],3'h0,active_active_oh_3[13],3'h0
- ,active_active_oh_3[12],3'h0,active_active_oh3_hi_lo_3,active_active_oh3_lo_3}; // @[Cat.scala 31:58]
- wire [1:0] active_active_idx_3 = f_io_in_bits_3_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_T_90 = ~f_io_in_bits_3_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_T_94 = f_io_in_bits_3_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_T_95 = ~f_io_in_bits_3_bits_m & active_active_idx_3 == 2'h0 | f_io_in_bits_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_T_96 = _active_active_active_T_95 ? active_active_oh0_3 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_T_102 = _active_active_active_T_90 & active_active_idx_3 == 2'h1 |
- _active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_T_103 = _active_active_active_T_102 ? active_active_oh1_3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_104 = _active_active_active_T_96 | _active_active_active_T_103; // @[VCommon.scala 107:68]
- wire _active_active_active_T_110 = _active_active_active_T_90 & active_active_idx_3 == 2'h2 |
- _active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_T_111 = _active_active_active_T_110 ? active_active_oh2_3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_T_112 = _active_active_active_T_104 | _active_active_active_T_111; // @[VCommon.scala 108:68]
- wire _active_active_active_T_118 = _active_active_active_T_90 & active_active_idx_3 == 2'h3 |
- _active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_T_119 = _active_active_active_T_118 ? active_active_oh3_3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_3 = _active_active_active_T_112 | _active_active_active_T_119; // @[VCommon.scala 109:68]
- wire [63:0] active_active_3 = f_io_in_bits_3_bits_tin_vs_valid ? active_active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_9 = fvalid[3] ? active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_10 = _active_T_7 | _active_T_9; // @[VCmdq.scala 126:90]
- wire [3:0] active_active_active_oh_shiftAmount = f_io_entry_0_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh = 16'h1 << active_active_active_oh_shiftAmount; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo = {3'h0,active_active_active_oh[3],3'h0,active_active_active_oh[2],3'h0,
- active_active_active_oh[1],3'h0,active_active_active_oh[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo = {3'h0,active_active_active_oh[7],3'h0,active_active_active_oh[6],3'h0,
- active_active_active_oh[5],3'h0,active_active_active_oh[4],active_active_active_oh0_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo = {3'h0,active_active_active_oh[11],3'h0,active_active_active_oh[10],3'h0,
- active_active_active_oh[9],3'h0,active_active_active_oh[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0 = {3'h0,active_active_active_oh[15],3'h0,active_active_active_oh[14],3'h0,
- active_active_active_oh[13],3'h0,active_active_active_oh[12],active_active_active_oh0_hi_lo,
- active_active_active_oh0_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo = {2'h0,active_active_active_oh[1],1'h0,2'h0,active_active_active_oh[0],1'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo = {2'h0,active_active_active_oh[3],1'h0,2'h0,active_active_active_oh[2],1'h0
- ,active_active_active_oh1_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo = {2'h0,active_active_active_oh[5],1'h0,2'h0,active_active_active_oh[4],1'h0
- }; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo = {2'h0,active_active_active_oh[7],1'h0,2'h0,active_active_active_oh[6],1'h0,
- active_active_active_oh1_lo_hi_lo,active_active_active_oh1_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo = {2'h0,active_active_active_oh[9],1'h0,2'h0,active_active_active_oh[8],1'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo = {2'h0,active_active_active_oh[11],1'h0,2'h0,active_active_active_oh[10],1'h0
- ,active_active_active_oh1_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo = {2'h0,active_active_active_oh[13],1'h0,2'h0,active_active_active_oh[12]
- ,1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1 = {2'h0,active_active_active_oh[15],1'h0,2'h0,active_active_active_oh[14],1'h0,
- active_active_active_oh1_hi_hi_lo,active_active_active_oh1_hi_lo,active_active_active_oh1_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo = {1'h0,active_active_active_oh[1],2'h0,1'h0,active_active_active_oh[0],2'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo = {1'h0,active_active_active_oh[3],2'h0,1'h0,active_active_active_oh[2],2'h0
- ,active_active_active_oh2_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo = {1'h0,active_active_active_oh[5],2'h0,1'h0,active_active_active_oh[4],2'h0
- }; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo = {1'h0,active_active_active_oh[7],2'h0,1'h0,active_active_active_oh[6],2'h0,
- active_active_active_oh2_lo_hi_lo,active_active_active_oh2_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo = {1'h0,active_active_active_oh[9],2'h0,1'h0,active_active_active_oh[8],2'h0
- }; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo = {1'h0,active_active_active_oh[11],2'h0,1'h0,active_active_active_oh[10],2'h0
- ,active_active_active_oh2_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo = {1'h0,active_active_active_oh[13],2'h0,1'h0,active_active_active_oh[12]
- ,2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2 = {1'h0,active_active_active_oh[15],2'h0,1'h0,active_active_active_oh[14],2'h0,
- active_active_active_oh2_hi_hi_lo,active_active_active_oh2_hi_lo,active_active_active_oh2_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo = {active_active_active_oh[3],3'h0,active_active_active_oh[2],3'h0,
- active_active_active_oh[1],3'h0,active_active_active_oh[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo = {active_active_active_oh[7],3'h0,active_active_active_oh[6],3'h0,
- active_active_active_oh[5],3'h0,active_active_active_oh[4],3'h0,active_active_active_oh3_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo = {active_active_active_oh[11],3'h0,active_active_active_oh[10],3'h0,
- active_active_active_oh[9],3'h0,active_active_active_oh[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3 = {active_active_active_oh[15],3'h0,active_active_active_oh[14],3'h0,
- active_active_active_oh[13],3'h0,active_active_active_oh[12],3'h0,active_active_active_oh3_hi_lo,
- active_active_active_oh3_lo}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx = f_io_entry_0_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T = ~f_io_entry_0_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_4 = f_io_entry_0_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_5 = ~f_io_entry_0_bits_m & active_active_active_idx == 2'h0 | f_io_entry_0_bits_m
- ; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_6 = _active_active_active_active_T_5 ? active_active_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active_active_active_T_12 = _active_active_active_active_T & active_active_active_idx == 2'h1 |
- _active_active_active_active_T_4; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_13 = _active_active_active_active_T_12 ? active_active_active_oh1 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_14 = _active_active_active_active_T_6 | _active_active_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_20 = _active_active_active_active_T & active_active_active_idx == 2'h2 |
- _active_active_active_active_T_4; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_21 = _active_active_active_active_T_20 ? active_active_active_oh2 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_22 = _active_active_active_active_T_14 | _active_active_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_28 = _active_active_active_active_T & active_active_active_idx == 2'h3 |
- _active_active_active_active_T_4; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_29 = _active_active_active_active_T_28 ? active_active_active_oh3 : 64'h0; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active = _active_active_active_active_T_22 | _active_active_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_4 = f_io_entry_0_bits_tin_vs_valid ? active_active_active_active : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_4 = f_io_entry_0_valid ? active_active_active_4 : 64'h0; // @[Library.scala 22:8]
- wire [3:0] active_active_active_oh_shiftAmount_1 = f_io_entry_1_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_1 = 16'h1 << active_active_active_oh_shiftAmount_1; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_1 = {3'h0,active_active_active_oh_1[3],3'h0,active_active_active_oh_1[2],3'h0
- ,active_active_active_oh_1[1],3'h0,active_active_active_oh_1[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_1 = {3'h0,active_active_active_oh_1[7],3'h0,active_active_active_oh_1[6],3'h0,
- active_active_active_oh_1[5],3'h0,active_active_active_oh_1[4],active_active_active_oh0_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_1 = {3'h0,active_active_active_oh_1[11],3'h0,active_active_active_oh_1[10],3'h0
- ,active_active_active_oh_1[9],3'h0,active_active_active_oh_1[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_1 = {3'h0,active_active_active_oh_1[15],3'h0,active_active_active_oh_1[14],3'h0,
- active_active_active_oh_1[13],3'h0,active_active_active_oh_1[12],active_active_active_oh0_hi_lo_1,
- active_active_active_oh0_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_1 = {2'h0,active_active_active_oh_1[1],1'h0,2'h0,
- active_active_active_oh_1[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_1 = {2'h0,active_active_active_oh_1[3],1'h0,2'h0,active_active_active_oh_1[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_1 = {2'h0,active_active_active_oh_1[5],1'h0,2'h0,
- active_active_active_oh_1[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_1 = {2'h0,active_active_active_oh_1[7],1'h0,2'h0,active_active_active_oh_1[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_1,active_active_active_oh1_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_1 = {2'h0,active_active_active_oh_1[9],1'h0,2'h0,
- active_active_active_oh_1[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_1 = {2'h0,active_active_active_oh_1[11],1'h0,2'h0,active_active_active_oh_1
- [10],1'h0,active_active_active_oh1_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_1 = {2'h0,active_active_active_oh_1[13],1'h0,2'h0,
- active_active_active_oh_1[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_1 = {2'h0,active_active_active_oh_1[15],1'h0,2'h0,active_active_active_oh_1[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_1,active_active_active_oh1_hi_lo_1,active_active_active_oh1_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_1 = {1'h0,active_active_active_oh_1[1],2'h0,1'h0,
- active_active_active_oh_1[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_1 = {1'h0,active_active_active_oh_1[3],2'h0,1'h0,active_active_active_oh_1[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_1 = {1'h0,active_active_active_oh_1[5],2'h0,1'h0,
- active_active_active_oh_1[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_1 = {1'h0,active_active_active_oh_1[7],2'h0,1'h0,active_active_active_oh_1[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_1,active_active_active_oh2_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_1 = {1'h0,active_active_active_oh_1[9],2'h0,1'h0,
- active_active_active_oh_1[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_1 = {1'h0,active_active_active_oh_1[11],2'h0,1'h0,active_active_active_oh_1
- [10],2'h0,active_active_active_oh2_hi_lo_lo_1}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_1 = {1'h0,active_active_active_oh_1[13],2'h0,1'h0,
- active_active_active_oh_1[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_1 = {1'h0,active_active_active_oh_1[15],2'h0,1'h0,active_active_active_oh_1[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_1,active_active_active_oh2_hi_lo_1,active_active_active_oh2_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_1 = {active_active_active_oh_1[3],3'h0,active_active_active_oh_1[2],3'h0,
- active_active_active_oh_1[1],3'h0,active_active_active_oh_1[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_1 = {active_active_active_oh_1[7],3'h0,active_active_active_oh_1[6],3'h0,
- active_active_active_oh_1[5],3'h0,active_active_active_oh_1[4],3'h0,active_active_active_oh3_lo_lo_1}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_1 = {active_active_active_oh_1[11],3'h0,active_active_active_oh_1[10],3'h0,
- active_active_active_oh_1[9],3'h0,active_active_active_oh_1[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_1 = {active_active_active_oh_1[15],3'h0,active_active_active_oh_1[14],3'h0,
- active_active_active_oh_1[13],3'h0,active_active_active_oh_1[12],3'h0,active_active_active_oh3_hi_lo_1,
- active_active_active_oh3_lo_1}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_1 = f_io_entry_1_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_30 = ~f_io_entry_1_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_34 = f_io_entry_1_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_35 = ~f_io_entry_1_bits_m & active_active_active_idx_1 == 2'h0 |
- f_io_entry_1_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_36 = _active_active_active_active_T_35 ? active_active_active_oh0_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_42 = _active_active_active_active_T_30 & active_active_active_idx_1 == 2'h1 |
- _active_active_active_active_T_34; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_43 = _active_active_active_active_T_42 ? active_active_active_oh1_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_44 = _active_active_active_active_T_36 | _active_active_active_active_T_43; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_50 = _active_active_active_active_T_30 & active_active_active_idx_1 == 2'h2 |
- _active_active_active_active_T_34; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_51 = _active_active_active_active_T_50 ? active_active_active_oh2_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_52 = _active_active_active_active_T_44 | _active_active_active_active_T_51; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_58 = _active_active_active_active_T_30 & active_active_active_idx_1 == 2'h3 |
- _active_active_active_active_T_34; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_59 = _active_active_active_active_T_58 ? active_active_active_oh3_1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_1 = _active_active_active_active_T_52 | _active_active_active_active_T_59; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_5 = f_io_entry_1_bits_tin_vs_valid ? active_active_active_active_1 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_5 = f_io_entry_1_valid ? active_active_active_5 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_12 = active_active_4 | active_active_5; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_2 = f_io_entry_2_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_2 = 16'h1 << active_active_active_oh_shiftAmount_2; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_2 = {3'h0,active_active_active_oh_2[3],3'h0,active_active_active_oh_2[2],3'h0
- ,active_active_active_oh_2[1],3'h0,active_active_active_oh_2[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_2 = {3'h0,active_active_active_oh_2[7],3'h0,active_active_active_oh_2[6],3'h0,
- active_active_active_oh_2[5],3'h0,active_active_active_oh_2[4],active_active_active_oh0_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_2 = {3'h0,active_active_active_oh_2[11],3'h0,active_active_active_oh_2[10],3'h0
- ,active_active_active_oh_2[9],3'h0,active_active_active_oh_2[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_2 = {3'h0,active_active_active_oh_2[15],3'h0,active_active_active_oh_2[14],3'h0,
- active_active_active_oh_2[13],3'h0,active_active_active_oh_2[12],active_active_active_oh0_hi_lo_2,
- active_active_active_oh0_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_2 = {2'h0,active_active_active_oh_2[1],1'h0,2'h0,
- active_active_active_oh_2[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_2 = {2'h0,active_active_active_oh_2[3],1'h0,2'h0,active_active_active_oh_2[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_2 = {2'h0,active_active_active_oh_2[5],1'h0,2'h0,
- active_active_active_oh_2[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_2 = {2'h0,active_active_active_oh_2[7],1'h0,2'h0,active_active_active_oh_2[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_2,active_active_active_oh1_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_2 = {2'h0,active_active_active_oh_2[9],1'h0,2'h0,
- active_active_active_oh_2[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_2 = {2'h0,active_active_active_oh_2[11],1'h0,2'h0,active_active_active_oh_2
- [10],1'h0,active_active_active_oh1_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_2 = {2'h0,active_active_active_oh_2[13],1'h0,2'h0,
- active_active_active_oh_2[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_2 = {2'h0,active_active_active_oh_2[15],1'h0,2'h0,active_active_active_oh_2[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_2,active_active_active_oh1_hi_lo_2,active_active_active_oh1_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_2 = {1'h0,active_active_active_oh_2[1],2'h0,1'h0,
- active_active_active_oh_2[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_2 = {1'h0,active_active_active_oh_2[3],2'h0,1'h0,active_active_active_oh_2[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_2 = {1'h0,active_active_active_oh_2[5],2'h0,1'h0,
- active_active_active_oh_2[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_2 = {1'h0,active_active_active_oh_2[7],2'h0,1'h0,active_active_active_oh_2[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_2,active_active_active_oh2_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_2 = {1'h0,active_active_active_oh_2[9],2'h0,1'h0,
- active_active_active_oh_2[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_2 = {1'h0,active_active_active_oh_2[11],2'h0,1'h0,active_active_active_oh_2
- [10],2'h0,active_active_active_oh2_hi_lo_lo_2}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_2 = {1'h0,active_active_active_oh_2[13],2'h0,1'h0,
- active_active_active_oh_2[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_2 = {1'h0,active_active_active_oh_2[15],2'h0,1'h0,active_active_active_oh_2[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_2,active_active_active_oh2_hi_lo_2,active_active_active_oh2_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_2 = {active_active_active_oh_2[3],3'h0,active_active_active_oh_2[2],3'h0,
- active_active_active_oh_2[1],3'h0,active_active_active_oh_2[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_2 = {active_active_active_oh_2[7],3'h0,active_active_active_oh_2[6],3'h0,
- active_active_active_oh_2[5],3'h0,active_active_active_oh_2[4],3'h0,active_active_active_oh3_lo_lo_2}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_2 = {active_active_active_oh_2[11],3'h0,active_active_active_oh_2[10],3'h0,
- active_active_active_oh_2[9],3'h0,active_active_active_oh_2[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_2 = {active_active_active_oh_2[15],3'h0,active_active_active_oh_2[14],3'h0,
- active_active_active_oh_2[13],3'h0,active_active_active_oh_2[12],3'h0,active_active_active_oh3_hi_lo_2,
- active_active_active_oh3_lo_2}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_2 = f_io_entry_2_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_60 = ~f_io_entry_2_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_64 = f_io_entry_2_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_65 = ~f_io_entry_2_bits_m & active_active_active_idx_2 == 2'h0 |
- f_io_entry_2_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_66 = _active_active_active_active_T_65 ? active_active_active_oh0_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_72 = _active_active_active_active_T_60 & active_active_active_idx_2 == 2'h1 |
- _active_active_active_active_T_64; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_73 = _active_active_active_active_T_72 ? active_active_active_oh1_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_74 = _active_active_active_active_T_66 | _active_active_active_active_T_73; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_80 = _active_active_active_active_T_60 & active_active_active_idx_2 == 2'h2 |
- _active_active_active_active_T_64; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_81 = _active_active_active_active_T_80 ? active_active_active_oh2_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_82 = _active_active_active_active_T_74 | _active_active_active_active_T_81; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_88 = _active_active_active_active_T_60 & active_active_active_idx_2 == 2'h3 |
- _active_active_active_active_T_64; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_89 = _active_active_active_active_T_88 ? active_active_active_oh3_2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_2 = _active_active_active_active_T_82 | _active_active_active_active_T_89; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_6 = f_io_entry_2_bits_tin_vs_valid ? active_active_active_active_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_6 = f_io_entry_2_valid ? active_active_active_6 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_13 = _active_T_12 | active_active_6; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_3 = f_io_entry_3_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_3 = 16'h1 << active_active_active_oh_shiftAmount_3; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_3 = {3'h0,active_active_active_oh_3[3],3'h0,active_active_active_oh_3[2],3'h0
- ,active_active_active_oh_3[1],3'h0,active_active_active_oh_3[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_3 = {3'h0,active_active_active_oh_3[7],3'h0,active_active_active_oh_3[6],3'h0,
- active_active_active_oh_3[5],3'h0,active_active_active_oh_3[4],active_active_active_oh0_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_3 = {3'h0,active_active_active_oh_3[11],3'h0,active_active_active_oh_3[10],3'h0
- ,active_active_active_oh_3[9],3'h0,active_active_active_oh_3[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_3 = {3'h0,active_active_active_oh_3[15],3'h0,active_active_active_oh_3[14],3'h0,
- active_active_active_oh_3[13],3'h0,active_active_active_oh_3[12],active_active_active_oh0_hi_lo_3,
- active_active_active_oh0_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_3 = {2'h0,active_active_active_oh_3[1],1'h0,2'h0,
- active_active_active_oh_3[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_3 = {2'h0,active_active_active_oh_3[3],1'h0,2'h0,active_active_active_oh_3[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_3 = {2'h0,active_active_active_oh_3[5],1'h0,2'h0,
- active_active_active_oh_3[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_3 = {2'h0,active_active_active_oh_3[7],1'h0,2'h0,active_active_active_oh_3[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_3,active_active_active_oh1_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_3 = {2'h0,active_active_active_oh_3[9],1'h0,2'h0,
- active_active_active_oh_3[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_3 = {2'h0,active_active_active_oh_3[11],1'h0,2'h0,active_active_active_oh_3
- [10],1'h0,active_active_active_oh1_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_3 = {2'h0,active_active_active_oh_3[13],1'h0,2'h0,
- active_active_active_oh_3[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_3 = {2'h0,active_active_active_oh_3[15],1'h0,2'h0,active_active_active_oh_3[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_3,active_active_active_oh1_hi_lo_3,active_active_active_oh1_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_3 = {1'h0,active_active_active_oh_3[1],2'h0,1'h0,
- active_active_active_oh_3[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_3 = {1'h0,active_active_active_oh_3[3],2'h0,1'h0,active_active_active_oh_3[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_3 = {1'h0,active_active_active_oh_3[5],2'h0,1'h0,
- active_active_active_oh_3[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_3 = {1'h0,active_active_active_oh_3[7],2'h0,1'h0,active_active_active_oh_3[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_3,active_active_active_oh2_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_3 = {1'h0,active_active_active_oh_3[9],2'h0,1'h0,
- active_active_active_oh_3[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_3 = {1'h0,active_active_active_oh_3[11],2'h0,1'h0,active_active_active_oh_3
- [10],2'h0,active_active_active_oh2_hi_lo_lo_3}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_3 = {1'h0,active_active_active_oh_3[13],2'h0,1'h0,
- active_active_active_oh_3[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_3 = {1'h0,active_active_active_oh_3[15],2'h0,1'h0,active_active_active_oh_3[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_3,active_active_active_oh2_hi_lo_3,active_active_active_oh2_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_3 = {active_active_active_oh_3[3],3'h0,active_active_active_oh_3[2],3'h0,
- active_active_active_oh_3[1],3'h0,active_active_active_oh_3[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_3 = {active_active_active_oh_3[7],3'h0,active_active_active_oh_3[6],3'h0,
- active_active_active_oh_3[5],3'h0,active_active_active_oh_3[4],3'h0,active_active_active_oh3_lo_lo_3}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_3 = {active_active_active_oh_3[11],3'h0,active_active_active_oh_3[10],3'h0,
- active_active_active_oh_3[9],3'h0,active_active_active_oh_3[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_3 = {active_active_active_oh_3[15],3'h0,active_active_active_oh_3[14],3'h0,
- active_active_active_oh_3[13],3'h0,active_active_active_oh_3[12],3'h0,active_active_active_oh3_hi_lo_3,
- active_active_active_oh3_lo_3}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_3 = f_io_entry_3_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_90 = ~f_io_entry_3_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_94 = f_io_entry_3_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_95 = ~f_io_entry_3_bits_m & active_active_active_idx_3 == 2'h0 |
- f_io_entry_3_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_96 = _active_active_active_active_T_95 ? active_active_active_oh0_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_102 = _active_active_active_active_T_90 & active_active_active_idx_3 == 2'h1 |
- _active_active_active_active_T_94; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_103 = _active_active_active_active_T_102 ? active_active_active_oh1_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_104 = _active_active_active_active_T_96 |
- _active_active_active_active_T_103; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_110 = _active_active_active_active_T_90 & active_active_active_idx_3 == 2'h2 |
- _active_active_active_active_T_94; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_111 = _active_active_active_active_T_110 ? active_active_active_oh2_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_112 = _active_active_active_active_T_104 |
- _active_active_active_active_T_111; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_118 = _active_active_active_active_T_90 & active_active_active_idx_3 == 2'h3 |
- _active_active_active_active_T_94; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_119 = _active_active_active_active_T_118 ? active_active_active_oh3_3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_3 = _active_active_active_active_T_112 | _active_active_active_active_T_119; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_7 = f_io_entry_3_bits_tin_vs_valid ? active_active_active_active_3 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_7 = f_io_entry_3_valid ? active_active_active_7 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_14 = _active_T_13 | active_active_7; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_4 = f_io_entry_4_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_4 = 16'h1 << active_active_active_oh_shiftAmount_4; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_4 = {3'h0,active_active_active_oh_4[3],3'h0,active_active_active_oh_4[2],3'h0
- ,active_active_active_oh_4[1],3'h0,active_active_active_oh_4[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_4 = {3'h0,active_active_active_oh_4[7],3'h0,active_active_active_oh_4[6],3'h0,
- active_active_active_oh_4[5],3'h0,active_active_active_oh_4[4],active_active_active_oh0_lo_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_4 = {3'h0,active_active_active_oh_4[11],3'h0,active_active_active_oh_4[10],3'h0
- ,active_active_active_oh_4[9],3'h0,active_active_active_oh_4[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_4 = {3'h0,active_active_active_oh_4[15],3'h0,active_active_active_oh_4[14],3'h0,
- active_active_active_oh_4[13],3'h0,active_active_active_oh_4[12],active_active_active_oh0_hi_lo_4,
- active_active_active_oh0_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_4 = {2'h0,active_active_active_oh_4[1],1'h0,2'h0,
- active_active_active_oh_4[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_4 = {2'h0,active_active_active_oh_4[3],1'h0,2'h0,active_active_active_oh_4[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_4 = {2'h0,active_active_active_oh_4[5],1'h0,2'h0,
- active_active_active_oh_4[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_4 = {2'h0,active_active_active_oh_4[7],1'h0,2'h0,active_active_active_oh_4[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_4,active_active_active_oh1_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_4 = {2'h0,active_active_active_oh_4[9],1'h0,2'h0,
- active_active_active_oh_4[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_4 = {2'h0,active_active_active_oh_4[11],1'h0,2'h0,active_active_active_oh_4
- [10],1'h0,active_active_active_oh1_hi_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_4 = {2'h0,active_active_active_oh_4[13],1'h0,2'h0,
- active_active_active_oh_4[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_4 = {2'h0,active_active_active_oh_4[15],1'h0,2'h0,active_active_active_oh_4[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_4,active_active_active_oh1_hi_lo_4,active_active_active_oh1_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_4 = {1'h0,active_active_active_oh_4[1],2'h0,1'h0,
- active_active_active_oh_4[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_4 = {1'h0,active_active_active_oh_4[3],2'h0,1'h0,active_active_active_oh_4[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_4 = {1'h0,active_active_active_oh_4[5],2'h0,1'h0,
- active_active_active_oh_4[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_4 = {1'h0,active_active_active_oh_4[7],2'h0,1'h0,active_active_active_oh_4[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_4,active_active_active_oh2_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_4 = {1'h0,active_active_active_oh_4[9],2'h0,1'h0,
- active_active_active_oh_4[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_4 = {1'h0,active_active_active_oh_4[11],2'h0,1'h0,active_active_active_oh_4
- [10],2'h0,active_active_active_oh2_hi_lo_lo_4}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_4 = {1'h0,active_active_active_oh_4[13],2'h0,1'h0,
- active_active_active_oh_4[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_4 = {1'h0,active_active_active_oh_4[15],2'h0,1'h0,active_active_active_oh_4[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_4,active_active_active_oh2_hi_lo_4,active_active_active_oh2_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_4 = {active_active_active_oh_4[3],3'h0,active_active_active_oh_4[2],3'h0,
- active_active_active_oh_4[1],3'h0,active_active_active_oh_4[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_4 = {active_active_active_oh_4[7],3'h0,active_active_active_oh_4[6],3'h0,
- active_active_active_oh_4[5],3'h0,active_active_active_oh_4[4],3'h0,active_active_active_oh3_lo_lo_4}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_4 = {active_active_active_oh_4[11],3'h0,active_active_active_oh_4[10],3'h0,
- active_active_active_oh_4[9],3'h0,active_active_active_oh_4[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_4 = {active_active_active_oh_4[15],3'h0,active_active_active_oh_4[14],3'h0,
- active_active_active_oh_4[13],3'h0,active_active_active_oh_4[12],3'h0,active_active_active_oh3_hi_lo_4,
- active_active_active_oh3_lo_4}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_4 = f_io_entry_4_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_120 = ~f_io_entry_4_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_124 = f_io_entry_4_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_125 = ~f_io_entry_4_bits_m & active_active_active_idx_4 == 2'h0 |
- f_io_entry_4_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_126 = _active_active_active_active_T_125 ? active_active_active_oh0_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_132 = _active_active_active_active_T_120 & active_active_active_idx_4 == 2'h1 |
- _active_active_active_active_T_124; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_133 = _active_active_active_active_T_132 ? active_active_active_oh1_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_134 = _active_active_active_active_T_126 |
- _active_active_active_active_T_133; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_140 = _active_active_active_active_T_120 & active_active_active_idx_4 == 2'h2 |
- _active_active_active_active_T_124; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_141 = _active_active_active_active_T_140 ? active_active_active_oh2_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_142 = _active_active_active_active_T_134 |
- _active_active_active_active_T_141; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_148 = _active_active_active_active_T_120 & active_active_active_idx_4 == 2'h3 |
- _active_active_active_active_T_124; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_149 = _active_active_active_active_T_148 ? active_active_active_oh3_4 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_4 = _active_active_active_active_T_142 | _active_active_active_active_T_149; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_8 = f_io_entry_4_bits_tin_vs_valid ? active_active_active_active_4 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_8 = f_io_entry_4_valid ? active_active_active_8 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_15 = _active_T_14 | active_active_8; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_5 = f_io_entry_5_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_5 = 16'h1 << active_active_active_oh_shiftAmount_5; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_5 = {3'h0,active_active_active_oh_5[3],3'h0,active_active_active_oh_5[2],3'h0
- ,active_active_active_oh_5[1],3'h0,active_active_active_oh_5[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_5 = {3'h0,active_active_active_oh_5[7],3'h0,active_active_active_oh_5[6],3'h0,
- active_active_active_oh_5[5],3'h0,active_active_active_oh_5[4],active_active_active_oh0_lo_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_5 = {3'h0,active_active_active_oh_5[11],3'h0,active_active_active_oh_5[10],3'h0
- ,active_active_active_oh_5[9],3'h0,active_active_active_oh_5[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_5 = {3'h0,active_active_active_oh_5[15],3'h0,active_active_active_oh_5[14],3'h0,
- active_active_active_oh_5[13],3'h0,active_active_active_oh_5[12],active_active_active_oh0_hi_lo_5,
- active_active_active_oh0_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_5 = {2'h0,active_active_active_oh_5[1],1'h0,2'h0,
- active_active_active_oh_5[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_5 = {2'h0,active_active_active_oh_5[3],1'h0,2'h0,active_active_active_oh_5[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_5 = {2'h0,active_active_active_oh_5[5],1'h0,2'h0,
- active_active_active_oh_5[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_5 = {2'h0,active_active_active_oh_5[7],1'h0,2'h0,active_active_active_oh_5[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_5,active_active_active_oh1_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_5 = {2'h0,active_active_active_oh_5[9],1'h0,2'h0,
- active_active_active_oh_5[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_5 = {2'h0,active_active_active_oh_5[11],1'h0,2'h0,active_active_active_oh_5
- [10],1'h0,active_active_active_oh1_hi_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_5 = {2'h0,active_active_active_oh_5[13],1'h0,2'h0,
- active_active_active_oh_5[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_5 = {2'h0,active_active_active_oh_5[15],1'h0,2'h0,active_active_active_oh_5[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_5,active_active_active_oh1_hi_lo_5,active_active_active_oh1_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_5 = {1'h0,active_active_active_oh_5[1],2'h0,1'h0,
- active_active_active_oh_5[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_5 = {1'h0,active_active_active_oh_5[3],2'h0,1'h0,active_active_active_oh_5[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_5 = {1'h0,active_active_active_oh_5[5],2'h0,1'h0,
- active_active_active_oh_5[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_5 = {1'h0,active_active_active_oh_5[7],2'h0,1'h0,active_active_active_oh_5[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_5,active_active_active_oh2_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_5 = {1'h0,active_active_active_oh_5[9],2'h0,1'h0,
- active_active_active_oh_5[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_5 = {1'h0,active_active_active_oh_5[11],2'h0,1'h0,active_active_active_oh_5
- [10],2'h0,active_active_active_oh2_hi_lo_lo_5}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_5 = {1'h0,active_active_active_oh_5[13],2'h0,1'h0,
- active_active_active_oh_5[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_5 = {1'h0,active_active_active_oh_5[15],2'h0,1'h0,active_active_active_oh_5[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_5,active_active_active_oh2_hi_lo_5,active_active_active_oh2_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_5 = {active_active_active_oh_5[3],3'h0,active_active_active_oh_5[2],3'h0,
- active_active_active_oh_5[1],3'h0,active_active_active_oh_5[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_5 = {active_active_active_oh_5[7],3'h0,active_active_active_oh_5[6],3'h0,
- active_active_active_oh_5[5],3'h0,active_active_active_oh_5[4],3'h0,active_active_active_oh3_lo_lo_5}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_5 = {active_active_active_oh_5[11],3'h0,active_active_active_oh_5[10],3'h0,
- active_active_active_oh_5[9],3'h0,active_active_active_oh_5[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_5 = {active_active_active_oh_5[15],3'h0,active_active_active_oh_5[14],3'h0,
- active_active_active_oh_5[13],3'h0,active_active_active_oh_5[12],3'h0,active_active_active_oh3_hi_lo_5,
- active_active_active_oh3_lo_5}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_5 = f_io_entry_5_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_150 = ~f_io_entry_5_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_154 = f_io_entry_5_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_155 = ~f_io_entry_5_bits_m & active_active_active_idx_5 == 2'h0 |
- f_io_entry_5_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_156 = _active_active_active_active_T_155 ? active_active_active_oh0_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_162 = _active_active_active_active_T_150 & active_active_active_idx_5 == 2'h1 |
- _active_active_active_active_T_154; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_163 = _active_active_active_active_T_162 ? active_active_active_oh1_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_164 = _active_active_active_active_T_156 |
- _active_active_active_active_T_163; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_170 = _active_active_active_active_T_150 & active_active_active_idx_5 == 2'h2 |
- _active_active_active_active_T_154; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_171 = _active_active_active_active_T_170 ? active_active_active_oh2_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_172 = _active_active_active_active_T_164 |
- _active_active_active_active_T_171; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_178 = _active_active_active_active_T_150 & active_active_active_idx_5 == 2'h3 |
- _active_active_active_active_T_154; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_179 = _active_active_active_active_T_178 ? active_active_active_oh3_5 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_5 = _active_active_active_active_T_172 | _active_active_active_active_T_179; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_9 = f_io_entry_5_bits_tin_vs_valid ? active_active_active_active_5 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_9 = f_io_entry_5_valid ? active_active_active_9 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_16 = _active_T_15 | active_active_9; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_6 = f_io_entry_6_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_6 = 16'h1 << active_active_active_oh_shiftAmount_6; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_6 = {3'h0,active_active_active_oh_6[3],3'h0,active_active_active_oh_6[2],3'h0
- ,active_active_active_oh_6[1],3'h0,active_active_active_oh_6[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_6 = {3'h0,active_active_active_oh_6[7],3'h0,active_active_active_oh_6[6],3'h0,
- active_active_active_oh_6[5],3'h0,active_active_active_oh_6[4],active_active_active_oh0_lo_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_6 = {3'h0,active_active_active_oh_6[11],3'h0,active_active_active_oh_6[10],3'h0
- ,active_active_active_oh_6[9],3'h0,active_active_active_oh_6[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_6 = {3'h0,active_active_active_oh_6[15],3'h0,active_active_active_oh_6[14],3'h0,
- active_active_active_oh_6[13],3'h0,active_active_active_oh_6[12],active_active_active_oh0_hi_lo_6,
- active_active_active_oh0_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_6 = {2'h0,active_active_active_oh_6[1],1'h0,2'h0,
- active_active_active_oh_6[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_6 = {2'h0,active_active_active_oh_6[3],1'h0,2'h0,active_active_active_oh_6[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_6 = {2'h0,active_active_active_oh_6[5],1'h0,2'h0,
- active_active_active_oh_6[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_6 = {2'h0,active_active_active_oh_6[7],1'h0,2'h0,active_active_active_oh_6[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_6,active_active_active_oh1_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_6 = {2'h0,active_active_active_oh_6[9],1'h0,2'h0,
- active_active_active_oh_6[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_6 = {2'h0,active_active_active_oh_6[11],1'h0,2'h0,active_active_active_oh_6
- [10],1'h0,active_active_active_oh1_hi_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_6 = {2'h0,active_active_active_oh_6[13],1'h0,2'h0,
- active_active_active_oh_6[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_6 = {2'h0,active_active_active_oh_6[15],1'h0,2'h0,active_active_active_oh_6[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_6,active_active_active_oh1_hi_lo_6,active_active_active_oh1_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_6 = {1'h0,active_active_active_oh_6[1],2'h0,1'h0,
- active_active_active_oh_6[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_6 = {1'h0,active_active_active_oh_6[3],2'h0,1'h0,active_active_active_oh_6[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_6 = {1'h0,active_active_active_oh_6[5],2'h0,1'h0,
- active_active_active_oh_6[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_6 = {1'h0,active_active_active_oh_6[7],2'h0,1'h0,active_active_active_oh_6[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_6,active_active_active_oh2_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_6 = {1'h0,active_active_active_oh_6[9],2'h0,1'h0,
- active_active_active_oh_6[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_6 = {1'h0,active_active_active_oh_6[11],2'h0,1'h0,active_active_active_oh_6
- [10],2'h0,active_active_active_oh2_hi_lo_lo_6}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_6 = {1'h0,active_active_active_oh_6[13],2'h0,1'h0,
- active_active_active_oh_6[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_6 = {1'h0,active_active_active_oh_6[15],2'h0,1'h0,active_active_active_oh_6[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_6,active_active_active_oh2_hi_lo_6,active_active_active_oh2_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_6 = {active_active_active_oh_6[3],3'h0,active_active_active_oh_6[2],3'h0,
- active_active_active_oh_6[1],3'h0,active_active_active_oh_6[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_6 = {active_active_active_oh_6[7],3'h0,active_active_active_oh_6[6],3'h0,
- active_active_active_oh_6[5],3'h0,active_active_active_oh_6[4],3'h0,active_active_active_oh3_lo_lo_6}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_6 = {active_active_active_oh_6[11],3'h0,active_active_active_oh_6[10],3'h0,
- active_active_active_oh_6[9],3'h0,active_active_active_oh_6[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_6 = {active_active_active_oh_6[15],3'h0,active_active_active_oh_6[14],3'h0,
- active_active_active_oh_6[13],3'h0,active_active_active_oh_6[12],3'h0,active_active_active_oh3_hi_lo_6,
- active_active_active_oh3_lo_6}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_6 = f_io_entry_6_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_180 = ~f_io_entry_6_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_184 = f_io_entry_6_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_185 = ~f_io_entry_6_bits_m & active_active_active_idx_6 == 2'h0 |
- f_io_entry_6_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_186 = _active_active_active_active_T_185 ? active_active_active_oh0_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_192 = _active_active_active_active_T_180 & active_active_active_idx_6 == 2'h1 |
- _active_active_active_active_T_184; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_193 = _active_active_active_active_T_192 ? active_active_active_oh1_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_194 = _active_active_active_active_T_186 |
- _active_active_active_active_T_193; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_200 = _active_active_active_active_T_180 & active_active_active_idx_6 == 2'h2 |
- _active_active_active_active_T_184; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_201 = _active_active_active_active_T_200 ? active_active_active_oh2_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_202 = _active_active_active_active_T_194 |
- _active_active_active_active_T_201; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_208 = _active_active_active_active_T_180 & active_active_active_idx_6 == 2'h3 |
- _active_active_active_active_T_184; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_209 = _active_active_active_active_T_208 ? active_active_active_oh3_6 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_6 = _active_active_active_active_T_202 | _active_active_active_active_T_209; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_10 = f_io_entry_6_bits_tin_vs_valid ? active_active_active_active_6 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_10 = f_io_entry_6_valid ? active_active_active_10 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_17 = _active_T_16 | active_active_10; // @[VCmdq.scala 107:24]
- wire [3:0] active_active_active_oh_shiftAmount_7 = f_io_entry_7_bits_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active_active_oh_7 = 16'h1 << active_active_active_oh_shiftAmount_7; // @[OneHot.scala 64:12]
- wire [15:0] active_active_active_oh0_lo_lo_7 = {3'h0,active_active_active_oh_7[3],3'h0,active_active_active_oh_7[2],3'h0
- ,active_active_active_oh_7[1],3'h0,active_active_active_oh_7[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh0_lo_7 = {3'h0,active_active_active_oh_7[7],3'h0,active_active_active_oh_7[6],3'h0,
- active_active_active_oh_7[5],3'h0,active_active_active_oh_7[4],active_active_active_oh0_lo_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh0_hi_lo_7 = {3'h0,active_active_active_oh_7[11],3'h0,active_active_active_oh_7[10],3'h0
- ,active_active_active_oh_7[9],3'h0,active_active_active_oh_7[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh0_7 = {3'h0,active_active_active_oh_7[15],3'h0,active_active_active_oh_7[14],3'h0,
- active_active_active_oh_7[13],3'h0,active_active_active_oh_7[12],active_active_active_oh0_hi_lo_7,
- active_active_active_oh0_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_lo_lo_7 = {2'h0,active_active_active_oh_7[1],1'h0,2'h0,
- active_active_active_oh_7[0],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_lo_lo_7 = {2'h0,active_active_active_oh_7[3],1'h0,2'h0,active_active_active_oh_7[
- 2],1'h0,active_active_active_oh1_lo_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_lo_hi_lo_7 = {2'h0,active_active_active_oh_7[5],1'h0,2'h0,
- active_active_active_oh_7[4],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh1_lo_7 = {2'h0,active_active_active_oh_7[7],1'h0,2'h0,active_active_active_oh_7[6],1'h0
- ,active_active_active_oh1_lo_hi_lo_7,active_active_active_oh1_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_lo_lo_7 = {2'h0,active_active_active_oh_7[9],1'h0,2'h0,
- active_active_active_oh_7[8],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh1_hi_lo_7 = {2'h0,active_active_active_oh_7[11],1'h0,2'h0,active_active_active_oh_7
- [10],1'h0,active_active_active_oh1_hi_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh1_hi_hi_lo_7 = {2'h0,active_active_active_oh_7[13],1'h0,2'h0,
- active_active_active_oh_7[12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh1_7 = {2'h0,active_active_active_oh_7[15],1'h0,2'h0,active_active_active_oh_7[14],1'h0
- ,active_active_active_oh1_hi_hi_lo_7,active_active_active_oh1_hi_lo_7,active_active_active_oh1_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_lo_lo_7 = {1'h0,active_active_active_oh_7[1],2'h0,1'h0,
- active_active_active_oh_7[0],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_lo_lo_7 = {1'h0,active_active_active_oh_7[3],2'h0,1'h0,active_active_active_oh_7[
- 2],2'h0,active_active_active_oh2_lo_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_lo_hi_lo_7 = {1'h0,active_active_active_oh_7[5],2'h0,1'h0,
- active_active_active_oh_7[4],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh2_lo_7 = {1'h0,active_active_active_oh_7[7],2'h0,1'h0,active_active_active_oh_7[6],2'h0
- ,active_active_active_oh2_lo_hi_lo_7,active_active_active_oh2_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_lo_lo_7 = {1'h0,active_active_active_oh_7[9],2'h0,1'h0,
- active_active_active_oh_7[8],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh2_hi_lo_7 = {1'h0,active_active_active_oh_7[11],2'h0,1'h0,active_active_active_oh_7
- [10],2'h0,active_active_active_oh2_hi_lo_lo_7}; // @[Cat.scala 31:58]
- wire [7:0] active_active_active_oh2_hi_hi_lo_7 = {1'h0,active_active_active_oh_7[13],2'h0,1'h0,
- active_active_active_oh_7[12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh2_7 = {1'h0,active_active_active_oh_7[15],2'h0,1'h0,active_active_active_oh_7[14],2'h0
- ,active_active_active_oh2_hi_hi_lo_7,active_active_active_oh2_hi_lo_7,active_active_active_oh2_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_lo_lo_7 = {active_active_active_oh_7[3],3'h0,active_active_active_oh_7[2],3'h0,
- active_active_active_oh_7[1],3'h0,active_active_active_oh_7[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active_active_oh3_lo_7 = {active_active_active_oh_7[7],3'h0,active_active_active_oh_7[6],3'h0,
- active_active_active_oh_7[5],3'h0,active_active_active_oh_7[4],3'h0,active_active_active_oh3_lo_lo_7}; // @[Cat.scala 31:58]
- wire [15:0] active_active_active_oh3_hi_lo_7 = {active_active_active_oh_7[11],3'h0,active_active_active_oh_7[10],3'h0,
- active_active_active_oh_7[9],3'h0,active_active_active_oh_7[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active_active_oh3_7 = {active_active_active_oh_7[15],3'h0,active_active_active_oh_7[14],3'h0,
- active_active_active_oh_7[13],3'h0,active_active_active_oh_7[12],3'h0,active_active_active_oh3_hi_lo_7,
- active_active_active_oh3_lo_7}; // @[Cat.scala 31:58]
- wire [1:0] active_active_active_idx_7 = f_io_entry_7_bits_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active_active_active_T_210 = ~f_io_entry_7_bits_m; // @[VCommon.scala 107:24]
- wire _active_active_active_active_T_214 = f_io_entry_7_bits_m; // @[VCommon.scala 107:47]
- wire _active_active_active_active_T_215 = ~f_io_entry_7_bits_m & active_active_active_idx_7 == 2'h0 |
- f_io_entry_7_bits_m; // @[VCommon.scala 107:42]
- wire [63:0] _active_active_active_active_T_216 = _active_active_active_active_T_215 ? active_active_active_oh0_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire _active_active_active_active_T_222 = _active_active_active_active_T_210 & active_active_active_idx_7 == 2'h1 |
- _active_active_active_active_T_214; // @[VCommon.scala 108:42]
- wire [63:0] _active_active_active_active_T_223 = _active_active_active_active_T_222 ? active_active_active_oh1_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_224 = _active_active_active_active_T_216 |
- _active_active_active_active_T_223; // @[VCommon.scala 107:68]
- wire _active_active_active_active_T_230 = _active_active_active_active_T_210 & active_active_active_idx_7 == 2'h2 |
- _active_active_active_active_T_214; // @[VCommon.scala 109:42]
- wire [63:0] _active_active_active_active_T_231 = _active_active_active_active_T_230 ? active_active_active_oh2_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active_active_active_T_232 = _active_active_active_active_T_224 |
- _active_active_active_active_T_231; // @[VCommon.scala 108:68]
- wire _active_active_active_active_T_238 = _active_active_active_active_T_210 & active_active_active_idx_7 == 2'h3 |
- _active_active_active_active_T_214; // @[VCommon.scala 110:42]
- wire [63:0] _active_active_active_active_T_239 = _active_active_active_active_T_238 ? active_active_active_oh3_7 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active_active_active_7 = _active_active_active_active_T_232 | _active_active_active_active_T_239; // @[VCommon.scala 109:68]
- wire [63:0] active_active_active_11 = f_io_entry_7_bits_tin_vs_valid ? active_active_active_active_7 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] active_active_11 = f_io_entry_7_valid ? active_active_active_11 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_18 = _active_T_17 | active_active_11; // @[VCmdq.scala 107:24]
- wire [5:0] _active_active0_T = {{1'd0}, step}; // @[VCmdq.scala 110:48]
- wire [2:0] active_active0_stepq = _addrAlign_T ? _active_active0_T[4:2] : _active_active0_T[2:0]; // @[VSt.scala 163:20]
- wire [3:0] active_active0_active_oh_shiftAmount = value_tin_vs_addr[5:2]; // @[VCommon.scala 29:27]
- wire [15:0] active_active0_active_oh = 16'h1 << active_active0_active_oh_shiftAmount; // @[OneHot.scala 64:12]
- wire [15:0] active_active0_active_oh0_lo_lo = {3'h0,active_active0_active_oh[3],3'h0,active_active0_active_oh[2],3'h0,
- active_active0_active_oh[1],3'h0,active_active0_active_oh[0]}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh0_lo = {3'h0,active_active0_active_oh[7],3'h0,active_active0_active_oh[6],3'h0,
- active_active0_active_oh[5],3'h0,active_active0_active_oh[4],active_active0_active_oh0_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh0_hi_lo = {3'h0,active_active0_active_oh[11],3'h0,active_active0_active_oh[10],3'h0
- ,active_active0_active_oh[9],3'h0,active_active0_active_oh[8]}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh0 = {3'h0,active_active0_active_oh[15],3'h0,active_active0_active_oh[14],3'h0,
- active_active0_active_oh[13],3'h0,active_active0_active_oh[12],active_active0_active_oh0_hi_lo,
- active_active0_active_oh0_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_lo_lo = {2'h0,active_active0_active_oh[1],1'h0,2'h0,active_active0_active_oh[0
- ],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_lo_lo = {2'h0,active_active0_active_oh[3],1'h0,2'h0,active_active0_active_oh[2],1'h0
- ,active_active0_active_oh1_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_lo_hi_lo = {2'h0,active_active0_active_oh[5],1'h0,2'h0,active_active0_active_oh[4
- ],1'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh1_lo = {2'h0,active_active0_active_oh[7],1'h0,2'h0,active_active0_active_oh[6],1'h0
- ,active_active0_active_oh1_lo_hi_lo,active_active0_active_oh1_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_lo_lo = {2'h0,active_active0_active_oh[9],1'h0,2'h0,active_active0_active_oh[8
- ],1'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh1_hi_lo = {2'h0,active_active0_active_oh[11],1'h0,2'h0,active_active0_active_oh[10
- ],1'h0,active_active0_active_oh1_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh1_hi_hi_lo = {2'h0,active_active0_active_oh[13],1'h0,2'h0,active_active0_active_oh[
- 12],1'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh1 = {2'h0,active_active0_active_oh[15],1'h0,2'h0,active_active0_active_oh[14],1'h0
- ,active_active0_active_oh1_hi_hi_lo,active_active0_active_oh1_hi_lo,active_active0_active_oh1_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_lo_lo = {1'h0,active_active0_active_oh[1],2'h0,1'h0,active_active0_active_oh[0
- ],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_lo_lo = {1'h0,active_active0_active_oh[3],2'h0,1'h0,active_active0_active_oh[2],2'h0
- ,active_active0_active_oh2_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_lo_hi_lo = {1'h0,active_active0_active_oh[5],2'h0,1'h0,active_active0_active_oh[4
- ],2'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh2_lo = {1'h0,active_active0_active_oh[7],2'h0,1'h0,active_active0_active_oh[6],2'h0
- ,active_active0_active_oh2_lo_hi_lo,active_active0_active_oh2_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_lo_lo = {1'h0,active_active0_active_oh[9],2'h0,1'h0,active_active0_active_oh[8
- ],2'h0}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh2_hi_lo = {1'h0,active_active0_active_oh[11],2'h0,1'h0,active_active0_active_oh[10
- ],2'h0,active_active0_active_oh2_hi_lo_lo}; // @[Cat.scala 31:58]
- wire [7:0] active_active0_active_oh2_hi_hi_lo = {1'h0,active_active0_active_oh[13],2'h0,1'h0,active_active0_active_oh[
- 12],2'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh2 = {1'h0,active_active0_active_oh[15],2'h0,1'h0,active_active0_active_oh[14],2'h0
- ,active_active0_active_oh2_hi_hi_lo,active_active0_active_oh2_hi_lo,active_active0_active_oh2_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_lo_lo = {active_active0_active_oh[3],3'h0,active_active0_active_oh[2],3'h0,
- active_active0_active_oh[1],3'h0,active_active0_active_oh[0],3'h0}; // @[Cat.scala 31:58]
- wire [31:0] active_active0_active_oh3_lo = {active_active0_active_oh[7],3'h0,active_active0_active_oh[6],3'h0,
- active_active0_active_oh[5],3'h0,active_active0_active_oh[4],3'h0,active_active0_active_oh3_lo_lo}; // @[Cat.scala 31:58]
- wire [15:0] active_active0_active_oh3_hi_lo = {active_active0_active_oh[11],3'h0,active_active0_active_oh[10],3'h0,
- active_active0_active_oh[9],3'h0,active_active0_active_oh[8],3'h0}; // @[Cat.scala 31:58]
- wire [63:0] active_active0_active_oh3 = {active_active0_active_oh[15],3'h0,active_active0_active_oh[14],3'h0,
- active_active0_active_oh[13],3'h0,active_active0_active_oh[12],3'h0,active_active0_active_oh3_hi_lo,
- active_active0_active_oh3_lo}; // @[Cat.scala 31:58]
- wire [1:0] active_active0_active_idx = value_tin_vs_addr[1:0]; // @[VCommon.scala 105:21]
- wire _active_active0_active_active_T_5 = _outlast1_T & active_active0_active_idx == 2'h0 | value_m &
- active_active0_stepq <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active0_active_active_T_6 = _active_active0_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active0_active_active_T_12 = _outlast1_T & active_active0_active_idx == 2'h1 | value_m &
- active_active0_stepq <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active0_active_active_T_13 = _active_active0_active_active_T_12 ? active_active0_active_oh1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_14 = _active_active0_active_active_T_6 |
- _active_active0_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active0_active_active_T_20 = _outlast1_T & active_active0_active_idx == 2'h2 | value_m &
- active_active0_stepq <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active0_active_active_T_21 = _active_active0_active_active_T_20 ? active_active0_active_oh2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active0_active_active_T_22 = _active_active0_active_active_T_14 |
- _active_active0_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active0_active_active_T_28 = _outlast1_T & active_active0_active_idx == 2'h3 | value_m &
- active_active0_stepq <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active0_active_active_T_29 = _active_active0_active_active_T_28 ? active_active0_active_oh3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active0_active_active = _active_active0_active_active_T_22 | _active_active0_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] active_active0 = value_tin_vs_valid ? active_active0_active_active : 64'h0; // @[Library.scala 22:8]
- wire [2:0] active_active1_stepq = _addrAlign_T ? _out_quad_T_2[4:2] : _out_quad_T_2[2:0]; // @[VSt.scala 163:20]
- wire _active_active1_active_active_T_5 = _outlast1_T & active_active0_active_idx == 2'h0 | value_m &
- active_active1_stepq <= 3'h0; // @[VCommon.scala 107:42]
- wire [63:0] _active_active1_active_active_T_6 = _active_active1_active_active_T_5 ? active_active0_active_oh0 : 64'h0; // @[Library.scala 32:8]
- wire _active_active1_active_active_T_12 = _outlast1_T & active_active0_active_idx == 2'h1 | value_m &
- active_active1_stepq <= 3'h1; // @[VCommon.scala 108:42]
- wire [63:0] _active_active1_active_active_T_13 = _active_active1_active_active_T_12 ? active_active0_active_oh1 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_14 = _active_active1_active_active_T_6 |
- _active_active1_active_active_T_13; // @[VCommon.scala 107:68]
- wire _active_active1_active_active_T_20 = _outlast1_T & active_active0_active_idx == 2'h2 | value_m &
- active_active1_stepq <= 3'h2; // @[VCommon.scala 109:42]
- wire [63:0] _active_active1_active_active_T_21 = _active_active1_active_active_T_20 ? active_active0_active_oh2 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] _active_active1_active_active_T_22 = _active_active1_active_active_T_14 |
- _active_active1_active_active_T_21; // @[VCommon.scala 108:68]
- wire _active_active1_active_active_T_28 = _outlast1_T & active_active0_active_idx == 2'h3 | value_m &
- active_active1_stepq <= 3'h3; // @[VCommon.scala 110:42]
- wire [63:0] _active_active1_active_active_T_29 = _active_active1_active_active_T_28 ? active_active0_active_oh3 : 64'h0
- ; // @[Library.scala 32:8]
- wire [63:0] active_active1_active_active = _active_active1_active_active_T_22 | _active_active1_active_active_T_29; // @[VCommon.scala 109:68]
- wire [63:0] active_active1 = value_tin_vs_valid ? active_active1_active_active : 64'h0; // @[Library.scala 22:8]
- wire _active_active_T_16 = ~io_out_ready; // @[VCmdq.scala 112:36]
- wire _active_active_T_19 = valid & (~io_out_ready | _T_18); // @[VCmdq.scala 112:32]
- wire [63:0] _active_active_T_21 = _active_active_T_16 ? active_active0 : active_active1; // @[VCmdq.scala 113:29]
- wire [63:0] active_active_12 = _active_active_T_19 ? _active_active_T_21 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _active_T_19 = _active_T_18 | active_active_12; // @[VCmdq.scala 114:12]
- wire [63:0] _active_T_20 = _active_T_10 | _active_T_19; // @[VCmdq.scala 127:90]
- Fifo4e_5 f ( // @[Fifo4e.scala 24:11]
- .clock(f_clock),
- .reset(f_reset),
- .io_in_ready(f_io_in_ready),
- .io_in_valid(f_io_in_valid),
- .io_in_bits_0_valid(f_io_in_bits_0_valid),
- .io_in_bits_0_bits_tin_op(f_io_in_bits_0_bits_tin_op),
- .io_in_bits_0_bits_tin_addr(f_io_in_bits_0_bits_tin_addr),
- .io_in_bits_0_bits_tin_offset(f_io_in_bits_0_bits_tin_offset),
- .io_in_bits_0_bits_tin_remain(f_io_in_bits_0_bits_tin_remain),
- .io_in_bits_0_bits_tin_vs_valid(f_io_in_bits_0_bits_tin_vs_valid),
- .io_in_bits_0_bits_tin_vs_addr(f_io_in_bits_0_bits_tin_vs_addr),
- .io_in_bits_0_bits_tin_vs_tag(f_io_in_bits_0_bits_tin_vs_tag),
- .io_in_bits_0_bits_m(f_io_in_bits_0_bits_m),
- .io_in_bits_1_valid(f_io_in_bits_1_valid),
- .io_in_bits_1_bits_tin_op(f_io_in_bits_1_bits_tin_op),
- .io_in_bits_1_bits_tin_addr(f_io_in_bits_1_bits_tin_addr),
- .io_in_bits_1_bits_tin_offset(f_io_in_bits_1_bits_tin_offset),
- .io_in_bits_1_bits_tin_remain(f_io_in_bits_1_bits_tin_remain),
- .io_in_bits_1_bits_tin_vs_valid(f_io_in_bits_1_bits_tin_vs_valid),
- .io_in_bits_1_bits_tin_vs_addr(f_io_in_bits_1_bits_tin_vs_addr),
- .io_in_bits_1_bits_tin_vs_tag(f_io_in_bits_1_bits_tin_vs_tag),
- .io_in_bits_1_bits_m(f_io_in_bits_1_bits_m),
- .io_in_bits_2_valid(f_io_in_bits_2_valid),
- .io_in_bits_2_bits_tin_op(f_io_in_bits_2_bits_tin_op),
- .io_in_bits_2_bits_tin_addr(f_io_in_bits_2_bits_tin_addr),
- .io_in_bits_2_bits_tin_offset(f_io_in_bits_2_bits_tin_offset),
- .io_in_bits_2_bits_tin_remain(f_io_in_bits_2_bits_tin_remain),
- .io_in_bits_2_bits_tin_vs_valid(f_io_in_bits_2_bits_tin_vs_valid),
- .io_in_bits_2_bits_tin_vs_addr(f_io_in_bits_2_bits_tin_vs_addr),
- .io_in_bits_2_bits_tin_vs_tag(f_io_in_bits_2_bits_tin_vs_tag),
- .io_in_bits_2_bits_m(f_io_in_bits_2_bits_m),
- .io_in_bits_3_valid(f_io_in_bits_3_valid),
- .io_in_bits_3_bits_tin_op(f_io_in_bits_3_bits_tin_op),
- .io_in_bits_3_bits_tin_addr(f_io_in_bits_3_bits_tin_addr),
- .io_in_bits_3_bits_tin_offset(f_io_in_bits_3_bits_tin_offset),
- .io_in_bits_3_bits_tin_remain(f_io_in_bits_3_bits_tin_remain),
- .io_in_bits_3_bits_tin_vs_valid(f_io_in_bits_3_bits_tin_vs_valid),
- .io_in_bits_3_bits_tin_vs_addr(f_io_in_bits_3_bits_tin_vs_addr),
- .io_in_bits_3_bits_tin_vs_tag(f_io_in_bits_3_bits_tin_vs_tag),
- .io_in_bits_3_bits_m(f_io_in_bits_3_bits_m),
- .io_out_ready(f_io_out_ready),
- .io_out_valid(f_io_out_valid),
- .io_out_bits_tin_op(f_io_out_bits_tin_op),
- .io_out_bits_tin_addr(f_io_out_bits_tin_addr),
- .io_out_bits_tin_offset(f_io_out_bits_tin_offset),
- .io_out_bits_tin_remain(f_io_out_bits_tin_remain),
- .io_out_bits_tin_vs_valid(f_io_out_bits_tin_vs_valid),
- .io_out_bits_tin_vs_addr(f_io_out_bits_tin_vs_addr),
- .io_out_bits_tin_vs_tag(f_io_out_bits_tin_vs_tag),
- .io_out_bits_tin_quad(f_io_out_bits_tin_quad),
- .io_out_bits_m(f_io_out_bits_m),
- .io_entry_0_valid(f_io_entry_0_valid),
- .io_entry_0_bits_tin_vs_valid(f_io_entry_0_bits_tin_vs_valid),
- .io_entry_0_bits_tin_vs_addr(f_io_entry_0_bits_tin_vs_addr),
- .io_entry_0_bits_m(f_io_entry_0_bits_m),
- .io_entry_1_valid(f_io_entry_1_valid),
- .io_entry_1_bits_tin_vs_valid(f_io_entry_1_bits_tin_vs_valid),
- .io_entry_1_bits_tin_vs_addr(f_io_entry_1_bits_tin_vs_addr),
- .io_entry_1_bits_m(f_io_entry_1_bits_m),
- .io_entry_2_valid(f_io_entry_2_valid),
- .io_entry_2_bits_tin_vs_valid(f_io_entry_2_bits_tin_vs_valid),
- .io_entry_2_bits_tin_vs_addr(f_io_entry_2_bits_tin_vs_addr),
- .io_entry_2_bits_m(f_io_entry_2_bits_m),
- .io_entry_3_valid(f_io_entry_3_valid),
- .io_entry_3_bits_tin_vs_valid(f_io_entry_3_bits_tin_vs_valid),
- .io_entry_3_bits_tin_vs_addr(f_io_entry_3_bits_tin_vs_addr),
- .io_entry_3_bits_m(f_io_entry_3_bits_m),
- .io_entry_4_valid(f_io_entry_4_valid),
- .io_entry_4_bits_tin_vs_valid(f_io_entry_4_bits_tin_vs_valid),
- .io_entry_4_bits_tin_vs_addr(f_io_entry_4_bits_tin_vs_addr),
- .io_entry_4_bits_m(f_io_entry_4_bits_m),
- .io_entry_5_valid(f_io_entry_5_valid),
- .io_entry_5_bits_tin_vs_valid(f_io_entry_5_bits_tin_vs_valid),
- .io_entry_5_bits_tin_vs_addr(f_io_entry_5_bits_tin_vs_addr),
- .io_entry_5_bits_m(f_io_entry_5_bits_m),
- .io_entry_6_valid(f_io_entry_6_valid),
- .io_entry_6_bits_tin_vs_valid(f_io_entry_6_bits_tin_vs_valid),
- .io_entry_6_bits_tin_vs_addr(f_io_entry_6_bits_tin_vs_addr),
- .io_entry_6_bits_m(f_io_entry_6_bits_m),
- .io_entry_7_valid(f_io_entry_7_valid),
- .io_entry_7_bits_tin_vs_valid(f_io_entry_7_bits_tin_vs_valid),
- .io_entry_7_bits_tin_vs_addr(f_io_entry_7_bits_tin_vs_addr),
- .io_entry_7_bits_m(f_io_entry_7_bits_m),
- .io_nempty(f_io_nempty)
- );
- assign io_in_ready = f_io_in_ready; // @[VCmdq.scala 65:15]
- assign io_out_valid = valid; // @[VCmdq.scala 133:16]
- assign io_out_bits_op = value_tin_op; // @[VCmdq.scala 134:15]
- assign io_out_bits_addr = value_tin_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_remain = value_tin_remain; // @[VCmdq.scala 134:15]
- assign io_out_bits_vs_valid = value_tin_vs_valid; // @[VCmdq.scala 134:15]
- assign io_out_bits_vs_addr = value_tin_vs_addr; // @[VCmdq.scala 134:15]
- assign io_out_bits_vs_tag = value_tin_vs_tag; // @[VCmdq.scala 134:15]
- assign io_out_bits_quad = value_tin_quad; // @[VCmdq.scala 134:15]
- assign io_active = active; // @[VCmdq.scala 136:13]
- assign io_nempty = f_io_nempty | valid; // @[VCmdq.scala 138:28]
- assign f_clock = clock;
- assign f_reset = reset;
- assign f_io_in_valid = io_in_valid; // @[VCmdq.scala 64:17]
- assign f_io_in_bits_0_valid = io_in_bits_0_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_0_bits_tin_op = io_in_bits_0_bits_op; // @[VSt.scala 111:12 93:19]
- assign f_io_in_bits_0_bits_tin_addr = io_in_bits_0_bits_sv_addr; // @[VSt.scala 114:14 93:19]
- assign f_io_in_bits_0_bits_tin_offset = f_io_in_bits_0_bits_tin_stride ? f_io_in_bits_0_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_0_bits_tin_out_offset_T_3}; // @[VSt.scala 115:22]
- assign f_io_in_bits_0_bits_tin_remain = f_io_in_bits_0_bits_tin_length ? f_io_in_bits_0_bits_tin_remain1 : 8'h80; // @[VSt.scala 116:22]
- assign f_io_in_bits_0_bits_tin_vs_valid = io_in_bits_0_bits_vs_valid; // @[VSt.scala 117:12 93:19]
- assign f_io_in_bits_0_bits_tin_vs_addr = io_in_bits_0_bits_vs_addr; // @[VSt.scala 117:12 93:19]
- assign f_io_in_bits_0_bits_tin_vs_tag = io_in_bits_0_bits_vs_tag; // @[VSt.scala 117:12 93:19]
- assign f_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_1_valid = io_in_bits_1_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_1_bits_tin_op = io_in_bits_1_bits_op; // @[VSt.scala 111:12 93:19]
- assign f_io_in_bits_1_bits_tin_addr = io_in_bits_1_bits_sv_addr; // @[VSt.scala 114:14 93:19]
- assign f_io_in_bits_1_bits_tin_offset = f_io_in_bits_1_bits_tin_stride ? f_io_in_bits_1_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_1_bits_tin_out_offset_T_3}; // @[VSt.scala 115:22]
- assign f_io_in_bits_1_bits_tin_remain = f_io_in_bits_1_bits_tin_length ? f_io_in_bits_1_bits_tin_remain1 : 8'h80; // @[VSt.scala 116:22]
- assign f_io_in_bits_1_bits_tin_vs_valid = io_in_bits_1_bits_vs_valid; // @[VSt.scala 117:12 93:19]
- assign f_io_in_bits_1_bits_tin_vs_addr = io_in_bits_1_bits_vs_addr; // @[VSt.scala 117:12 93:19]
- assign f_io_in_bits_1_bits_tin_vs_tag = io_in_bits_1_bits_vs_tag; // @[VSt.scala 117:12 93:19]
- assign f_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_2_valid = io_in_bits_2_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_2_bits_tin_op = io_in_bits_2_bits_op; // @[VSt.scala 111:12 93:19]
- assign f_io_in_bits_2_bits_tin_addr = io_in_bits_2_bits_sv_addr; // @[VSt.scala 114:14 93:19]
- assign f_io_in_bits_2_bits_tin_offset = f_io_in_bits_2_bits_tin_stride ? f_io_in_bits_2_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_2_bits_tin_out_offset_T_3}; // @[VSt.scala 115:22]
- assign f_io_in_bits_2_bits_tin_remain = f_io_in_bits_2_bits_tin_length ? f_io_in_bits_2_bits_tin_remain1 : 8'h80; // @[VSt.scala 116:22]
- assign f_io_in_bits_2_bits_tin_vs_valid = io_in_bits_2_bits_vs_valid; // @[VSt.scala 117:12 93:19]
- assign f_io_in_bits_2_bits_tin_vs_addr = io_in_bits_2_bits_vs_addr; // @[VSt.scala 117:12 93:19]
- assign f_io_in_bits_2_bits_tin_vs_tag = io_in_bits_2_bits_vs_tag; // @[VSt.scala 117:12 93:19]
- assign f_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_in_bits_3_valid = io_in_bits_3_valid; // @[VCmdq.scala 68:27]
- assign f_io_in_bits_3_bits_tin_op = io_in_bits_3_bits_op; // @[VSt.scala 111:12 93:19]
- assign f_io_in_bits_3_bits_tin_addr = io_in_bits_3_bits_sv_addr; // @[VSt.scala 114:14 93:19]
- assign f_io_in_bits_3_bits_tin_offset = f_io_in_bits_3_bits_tin_stride ? f_io_in_bits_3_bits_tin_data[31:0] : {{24
- 'd0}, _f_io_in_bits_3_bits_tin_out_offset_T_3}; // @[VSt.scala 115:22]
- assign f_io_in_bits_3_bits_tin_remain = f_io_in_bits_3_bits_tin_length ? f_io_in_bits_3_bits_tin_remain1 : 8'h80; // @[VSt.scala 116:22]
- assign f_io_in_bits_3_bits_tin_vs_valid = io_in_bits_3_bits_vs_valid; // @[VSt.scala 117:12 93:19]
- assign f_io_in_bits_3_bits_tin_vs_addr = io_in_bits_3_bits_vs_addr; // @[VSt.scala 117:12 93:19]
- assign f_io_in_bits_3_bits_tin_vs_tag = io_in_bits_3_bits_vs_tag; // @[VSt.scala 117:12 93:19]
- assign f_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VCmdq.scala 70:28]
- assign f_io_out_ready = _T_8 | io_out_ready & last; // @[VCmdq.scala 73:28]
- always @(posedge clock) begin
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_op <= 7'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_op <= f_io_out_bits_tin_op; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_op <= 7'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_addr <= 32'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_addr <= f_io_out_bits_tin_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_addr <= tin_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_addr <= 32'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_offset <= 32'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_offset <= f_io_out_bits_tin_offset; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_offset <= 32'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_remain <= 8'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_remain <= f_io_out_bits_tin_remain; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_remain <= tin_remain; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_remain <= 8'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vs_valid <= 1'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vs_valid <= f_io_out_bits_tin_vs_valid; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_tin_vs_valid <= _GEN_5;
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vs_addr <= 6'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vs_addr <= f_io_out_bits_tin_vs_addr; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_vs_addr <= tin_vs_addr; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_vs_addr <= 6'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_vs_tag <= 4'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_vs_tag <= f_io_out_bits_tin_vs_tag; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (!(~last)) begin // @[VCmdq.scala 82:18]
- value_tin_vs_tag <= 4'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_tin_quad <= 2'h0; // @[VCmdq.scala 97:15]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_tin_quad <= f_io_out_bits_tin_quad; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- if (~last) begin // @[VCmdq.scala 82:18]
- value_tin_quad <= tin_quad; // @[VCmdq.scala 84:17]
- end else begin
- value_tin_quad <= 2'h0; // @[VCmdq.scala 90:17]
- end
- end
- if (reset) begin // @[VCmdq.scala 96:23]
- value_m <= 1'h0; // @[VCmdq.scala 98:13]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 77:43]
- value_m <= f_io_out_bits_m; // @[VCmdq.scala 79:11]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 81:46]
- value_m <= _GEN_12;
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(addrAlign == 5'h0)) begin
- $fatal; // @[VSt.scala 128:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(addrAlign == 5'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:128 assert(addrAlign === 0.U)\n"); // @[VSt.scala 128:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(offsAlign == 5'h0)) begin
- $fatal; // @[VSt.scala 129:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(offsAlign == 5'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:129 assert(offsAlign === 0.U)\n"); // @[VSt.scala 129:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~valid | value_tin_op == 7'h3 | _addrAlign_T)) begin
- $fatal; // @[VSt.scala 130:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~valid | value_tin_op == 7'h3 | _addrAlign_T)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VSt.scala:130 assert(!valid || in.op === e.vst.U || in.op === e.vstq.U)\n"); // @[VSt.scala 130:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VSt.scala 96:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_0_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:96 assert(PopCount(in.sz) <= 1.U)\n"); // @[VSt.scala 96:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_0_bits_op == 7'h3 & ~io_in_bits_0_bits_vs_valid))) begin
- $fatal; // @[VSt.scala 97:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_0_bits_op == 7'h3 & ~io_in_bits_0_bits_vs_valid))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:97 assert(!(in.op === e.vst.U && !in.vs.valid))\n"); // @[VSt.scala 97:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_0_bits_op == 7'h4 & _f_io_in_bits_0_bits_tin_T_12))) begin
- $fatal; // @[VSt.scala 98:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_0_bits_op == 7'h4 & _f_io_in_bits_0_bits_tin_T_12))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:98 assert(!(in.op === e.vstq.U && !in.vs.valid))\n"); // @[VSt.scala 98:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VSt.scala 96:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_1_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:96 assert(PopCount(in.sz) <= 1.U)\n"); // @[VSt.scala 96:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_1_bits_op == 7'h3 & ~io_in_bits_1_bits_vs_valid))) begin
- $fatal; // @[VSt.scala 97:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_1_bits_op == 7'h3 & ~io_in_bits_1_bits_vs_valid))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:97 assert(!(in.op === e.vst.U && !in.vs.valid))\n"); // @[VSt.scala 97:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_1_bits_op == 7'h4 & _f_io_in_bits_1_bits_tin_T_12))) begin
- $fatal; // @[VSt.scala 98:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_1_bits_op == 7'h4 & _f_io_in_bits_1_bits_tin_T_12))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:98 assert(!(in.op === e.vstq.U && !in.vs.valid))\n"); // @[VSt.scala 98:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VSt.scala 96:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_2_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:96 assert(PopCount(in.sz) <= 1.U)\n"); // @[VSt.scala 96:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_2_bits_op == 7'h3 & ~io_in_bits_2_bits_vs_valid))) begin
- $fatal; // @[VSt.scala 97:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_2_bits_op == 7'h3 & ~io_in_bits_2_bits_vs_valid))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:97 assert(!(in.op === e.vst.U && !in.vs.valid))\n"); // @[VSt.scala 97:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_2_bits_op == 7'h4 & _f_io_in_bits_2_bits_tin_T_12))) begin
- $fatal; // @[VSt.scala 98:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_2_bits_op == 7'h4 & _f_io_in_bits_2_bits_tin_T_12))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:98 assert(!(in.op === e.vstq.U && !in.vs.valid))\n"); // @[VSt.scala 98:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fatal; // @[VSt.scala 96:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_f_io_in_bits_3_bits_tin_T_5[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:96 assert(PopCount(in.sz) <= 1.U)\n"); // @[VSt.scala 96:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h3 & ~io_in_bits_3_bits_vs_valid))) begin
- $fatal; // @[VSt.scala 97:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h3 & ~io_in_bits_3_bits_vs_valid))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:97 assert(!(in.op === e.vst.U && !in.vs.valid))\n"); // @[VSt.scala 97:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_12))) begin
- $fatal; // @[VSt.scala 98:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_in_bits_3_bits_op == 7'h4 & _f_io_in_bits_3_bits_tin_T_12))) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:98 assert(!(in.op === e.vstq.U && !in.vs.valid))\n"); // @[VSt.scala 98:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_22 & _T_2 & ~(active_active0_stepq <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_22 & _T_2 & ~(active_active0_stepq <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_22 & _T_2 & ~(active_active1_stepq <= 3'h4)) begin
- $fatal; // @[VCommon.scala 27:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_22 & _T_2 & ~(active_active1_stepq <= 3'h4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VCommon.scala:27 assert(step <= 4.U)\n"); // @[VCommon.scala 27:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 118:69]
- active <= 64'h0; // @[VCmdq.scala 123:12]
- end else if (io_in_valid & io_in_ready | _T_17) begin // @[VCmdq.scala 49:23]
- active <= _active_T_20;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 77:43]
- valid <= 1'h0; // @[VCmdq.scala 78:11]
- end else begin
- valid <= f_io_out_valid & f_io_out_ready | _GEN_14;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VCmdq.scala 77:43]
- step <= 5'h0; // @[VCmdq.scala 80:10]
- end else if (f_io_out_valid & f_io_out_ready) begin // @[VCmdq.scala 81:46]
- step <= 5'h0; // @[VCmdq.scala 82:18 86:12 92:12]
- end else if (io_out_valid & io_out_ready) begin // @[VCmdq.scala 58:21]
- if (~last) begin
- step <= _out_quad_T_2;
- end else begin
- step <= 5'h0;
- end
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {2{`RANDOM}};
- active = _RAND_0[63:0];
- _RAND_1 = {1{`RANDOM}};
- valid = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- value_tin_op = _RAND_2[6:0];
- _RAND_3 = {1{`RANDOM}};
- value_tin_addr = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- value_tin_offset = _RAND_4[31:0];
- _RAND_5 = {1{`RANDOM}};
- value_tin_remain = _RAND_5[7:0];
- _RAND_6 = {1{`RANDOM}};
- value_tin_vs_valid = _RAND_6[0:0];
- _RAND_7 = {1{`RANDOM}};
- value_tin_vs_addr = _RAND_7[5:0];
- _RAND_8 = {1{`RANDOM}};
- value_tin_vs_tag = _RAND_8[3:0];
- _RAND_9 = {1{`RANDOM}};
- value_tin_quad = _RAND_9[1:0];
- _RAND_10 = {1{`RANDOM}};
- value_m = _RAND_10[0:0];
- _RAND_11 = {1{`RANDOM}};
- step = _RAND_11[4:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- active = 64'h0;
- end
- if (reset) begin
- valid = 1'h0;
- end
- if (reset) begin
- step = 5'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Slice_6(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input [31:0] io_in_bits_addr,
- input [5:0] io_in_bits_id,
- input [5:0] io_in_bits_size,
- input io_in_bits_vstq,
- input [1:0] io_in_bits_quad,
- input io_out_ready,
- output io_out_valid,
- output [31:0] io_out_bits_addr,
- output [5:0] io_out_bits_id,
- output [5:0] io_out_bits_size,
- output io_out_bits_vstq,
- output [1:0] io_out_bits_quad
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
-`endif // RANDOMIZE_REG_INIT
- reg ipos; // @[Slice.scala 38:21]
- reg opos; // @[Slice.scala 39:21]
- reg [31:0] mem_0_addr; // @[Slice.scala 41:16]
- reg [5:0] mem_0_id; // @[Slice.scala 41:16]
- reg [5:0] mem_0_size; // @[Slice.scala 41:16]
- reg mem_0_vstq; // @[Slice.scala 41:16]
- reg [1:0] mem_0_quad; // @[Slice.scala 41:16]
- wire empty = ipos == opos; // @[Slice.scala 43:20]
- wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 45:28]
- wire ovalid = io_out_valid & io_out_ready; // @[Slice.scala 46:29]
- assign io_in_ready = empty | io_out_ready; // @[Slice.scala 88:28]
- assign io_out_valid = ~empty; // @[Slice.scala 102:21]
- assign io_out_bits_addr = mem_0_addr; // @[Slice.scala 103:18]
- assign io_out_bits_id = mem_0_id; // @[Slice.scala 103:18]
- assign io_out_bits_size = mem_0_size; // @[Slice.scala 103:18]
- assign io_out_bits_vstq = mem_0_vstq; // @[Slice.scala 103:18]
- assign io_out_bits_quad = mem_0_quad; // @[Slice.scala 103:18]
- always @(posedge clock) begin
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_addr <= io_in_bits_addr; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_id <= io_in_bits_id; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_size <= io_in_bits_size; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_vstq <= io_in_bits_vstq; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_quad <= io_in_bits_quad; // @[Slice.scala 94:14]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 48:17]
- ipos <= 1'h0; // @[Slice.scala 49:10]
- end else if (ivalid) begin // @[Slice.scala 38:21]
- ipos <= ipos + 1'h1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 52:17]
- opos <= 1'h0; // @[Slice.scala 53:10]
- end else if (ovalid) begin // @[Slice.scala 39:21]
- opos <= opos + 1'h1;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- ipos = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- opos = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- mem_0_addr = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- mem_0_id = _RAND_3[5:0];
- _RAND_4 = {1{`RANDOM}};
- mem_0_size = _RAND_4[5:0];
- _RAND_5 = {1{`RANDOM}};
- mem_0_vstq = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- mem_0_quad = _RAND_6[1:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- ipos = 1'h0;
- end
- if (reset) begin
- opos = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Slice_7(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input [255:0] io_in_bits_data,
- input [31:0] io_in_bits_strb,
- input io_out_ready,
- output io_out_valid,
- output [255:0] io_out_bits_data,
- output [31:0] io_out_bits_strb
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [255:0] _RAND_2;
- reg [31:0] _RAND_3;
-`endif // RANDOMIZE_REG_INIT
- reg ipos; // @[Slice.scala 38:21]
- reg opos; // @[Slice.scala 39:21]
- reg [255:0] mem_0_data; // @[Slice.scala 41:16]
- reg [31:0] mem_0_strb; // @[Slice.scala 41:16]
- wire empty = ipos == opos; // @[Slice.scala 43:20]
- wire bypass = io_in_valid & io_out_ready & empty; // @[Slice.scala 44:59]
- wire _ivalid_T_1 = ~bypass; // @[Slice.scala 45:46]
- wire ivalid = io_in_valid & io_in_ready & ~bypass; // @[Slice.scala 45:43]
- wire ovalid = io_out_valid & io_out_ready & _ivalid_T_1; // @[Slice.scala 46:45]
- wire _io_value_0_valid_T = ~empty; // @[Slice.scala 97:26]
- assign io_in_ready = empty | io_out_ready; // @[Slice.scala 88:28]
- assign io_out_valid = _io_value_0_valid_T | io_in_valid; // @[Slice.scala 105:28]
- assign io_out_bits_data = _io_value_0_valid_T ? mem_0_data : io_in_bits_data; // @[Slice.scala 106:24]
- assign io_out_bits_strb = _io_value_0_valid_T ? mem_0_strb : io_in_bits_strb; // @[Slice.scala 106:24]
- always @(posedge clock) begin
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_data <= io_in_bits_data; // @[Slice.scala 94:14]
- end
- if (ivalid) begin // @[Slice.scala 93:19]
- mem_0_strb <= io_in_bits_strb; // @[Slice.scala 94:14]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 48:17]
- ipos <= 1'h0; // @[Slice.scala 49:10]
- end else if (ivalid) begin // @[Slice.scala 38:21]
- ipos <= ipos + 1'h1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 52:17]
- opos <= 1'h0; // @[Slice.scala 53:10]
- end else if (ovalid) begin // @[Slice.scala 39:21]
- opos <= opos + 1'h1;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- ipos = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- opos = _RAND_1[0:0];
- _RAND_2 = {8{`RANDOM}};
- mem_0_data = _RAND_2[255:0];
- _RAND_3 = {1{`RANDOM}};
- mem_0_strb = _RAND_3[31:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- ipos = 1'h0;
- end
- if (reset) begin
- opos = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VSt(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_0_valid,
- input [6:0] io_in_bits_0_bits_op,
- input [2:0] io_in_bits_0_bits_f2,
- input [2:0] io_in_bits_0_bits_sz,
- input io_in_bits_0_bits_m,
- input io_in_bits_0_bits_vs_valid,
- input [5:0] io_in_bits_0_bits_vs_addr,
- input [3:0] io_in_bits_0_bits_vs_tag,
- input [31:0] io_in_bits_0_bits_sv_addr,
- input [31:0] io_in_bits_0_bits_sv_data,
- input io_in_bits_1_valid,
- input [6:0] io_in_bits_1_bits_op,
- input [2:0] io_in_bits_1_bits_f2,
- input [2:0] io_in_bits_1_bits_sz,
- input io_in_bits_1_bits_m,
- input io_in_bits_1_bits_vs_valid,
- input [5:0] io_in_bits_1_bits_vs_addr,
- input [3:0] io_in_bits_1_bits_vs_tag,
- input [31:0] io_in_bits_1_bits_sv_addr,
- input [31:0] io_in_bits_1_bits_sv_data,
- input io_in_bits_2_valid,
- input [6:0] io_in_bits_2_bits_op,
- input [2:0] io_in_bits_2_bits_f2,
- input [2:0] io_in_bits_2_bits_sz,
- input io_in_bits_2_bits_m,
- input io_in_bits_2_bits_vs_valid,
- input [5:0] io_in_bits_2_bits_vs_addr,
- input [3:0] io_in_bits_2_bits_vs_tag,
- input [31:0] io_in_bits_2_bits_sv_addr,
- input [31:0] io_in_bits_2_bits_sv_data,
- input io_in_bits_3_valid,
- input [6:0] io_in_bits_3_bits_op,
- input [2:0] io_in_bits_3_bits_f2,
- input [2:0] io_in_bits_3_bits_sz,
- input io_in_bits_3_bits_m,
- input io_in_bits_3_bits_vs_valid,
- input [5:0] io_in_bits_3_bits_vs_addr,
- input [3:0] io_in_bits_3_bits_vs_tag,
- input [31:0] io_in_bits_3_bits_sv_addr,
- input [31:0] io_in_bits_3_bits_sv_data,
- output [63:0] io_active,
- input [127:0] io_vrfsb,
- output io_read_valid,
- input io_read_ready,
- output [5:0] io_read_addr,
- input [255:0] io_read_data,
- input io_axi_addr_ready,
- output io_axi_addr_valid,
- output [31:0] io_axi_addr_bits_addr,
- output [5:0] io_axi_addr_bits_id,
- input io_axi_data_ready,
- output io_axi_data_valid,
- output [255:0] io_axi_data_bits_data,
- output [31:0] io_axi_data_bits_strb,
- output io_axi_resp_ready,
- input io_axi_resp_valid,
- output io_nempty
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
-`endif // RANDOMIZE_REG_INIT
- wire q_clock; // @[VCmdq.scala 30:11]
- wire q_reset; // @[VCmdq.scala 30:11]
- wire q_io_in_ready; // @[VCmdq.scala 30:11]
- wire q_io_in_valid; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_0_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_0_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_0_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_0_bits_sz; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_0_bits_m; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_0_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_0_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q_io_in_bits_0_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_0_bits_sv_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_0_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_1_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_1_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_1_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_1_bits_sz; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_1_bits_m; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_1_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_1_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q_io_in_bits_1_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_1_bits_sv_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_1_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_2_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_2_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_2_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_2_bits_sz; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_2_bits_m; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_2_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_2_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q_io_in_bits_2_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_2_bits_sv_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_2_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_3_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_in_bits_3_bits_op; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_3_bits_f2; // @[VCmdq.scala 30:11]
- wire [2:0] q_io_in_bits_3_bits_sz; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_3_bits_m; // @[VCmdq.scala 30:11]
- wire q_io_in_bits_3_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_in_bits_3_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q_io_in_bits_3_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_3_bits_sv_addr; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_in_bits_3_bits_sv_data; // @[VCmdq.scala 30:11]
- wire q_io_out_ready; // @[VCmdq.scala 30:11]
- wire q_io_out_valid; // @[VCmdq.scala 30:11]
- wire [6:0] q_io_out_bits_op; // @[VCmdq.scala 30:11]
- wire [31:0] q_io_out_bits_addr; // @[VCmdq.scala 30:11]
- wire [7:0] q_io_out_bits_remain; // @[VCmdq.scala 30:11]
- wire q_io_out_bits_vs_valid; // @[VCmdq.scala 30:11]
- wire [5:0] q_io_out_bits_vs_addr; // @[VCmdq.scala 30:11]
- wire [3:0] q_io_out_bits_vs_tag; // @[VCmdq.scala 30:11]
- wire [1:0] q_io_out_bits_quad; // @[VCmdq.scala 30:11]
- wire [63:0] q_io_active; // @[VCmdq.scala 30:11]
- wire q_io_nempty; // @[VCmdq.scala 30:11]
- wire ctrl_clock; // @[Slice.scala 23:11]
- wire ctrl_reset; // @[Slice.scala 23:11]
- wire ctrl_io_in_ready; // @[Slice.scala 23:11]
- wire ctrl_io_in_valid; // @[Slice.scala 23:11]
- wire [31:0] ctrl_io_in_bits_addr; // @[Slice.scala 23:11]
- wire [5:0] ctrl_io_in_bits_id; // @[Slice.scala 23:11]
- wire [5:0] ctrl_io_in_bits_size; // @[Slice.scala 23:11]
- wire ctrl_io_in_bits_vstq; // @[Slice.scala 23:11]
- wire [1:0] ctrl_io_in_bits_quad; // @[Slice.scala 23:11]
- wire ctrl_io_out_ready; // @[Slice.scala 23:11]
- wire ctrl_io_out_valid; // @[Slice.scala 23:11]
- wire [31:0] ctrl_io_out_bits_addr; // @[Slice.scala 23:11]
- wire [5:0] ctrl_io_out_bits_id; // @[Slice.scala 23:11]
- wire [5:0] ctrl_io_out_bits_size; // @[Slice.scala 23:11]
- wire ctrl_io_out_bits_vstq; // @[Slice.scala 23:11]
- wire [1:0] ctrl_io_out_bits_quad; // @[Slice.scala 23:11]
- wire data_clock; // @[Slice.scala 23:11]
- wire data_reset; // @[Slice.scala 23:11]
- wire data_io_in_ready; // @[Slice.scala 23:11]
- wire data_io_in_valid; // @[Slice.scala 23:11]
- wire [255:0] data_io_in_bits_data; // @[Slice.scala 23:11]
- wire [31:0] data_io_in_bits_strb; // @[Slice.scala 23:11]
- wire data_io_out_ready; // @[Slice.scala 23:11]
- wire data_io_out_valid; // @[Slice.scala 23:11]
- wire [255:0] data_io_out_bits_data; // @[Slice.scala 23:11]
- wire [31:0] data_io_out_bits_strb; // @[Slice.scala 23:11]
- reg dataEn; // @[VSt.scala 187:23]
- wire [3:0] _q_io_out_ready_tag_T_1 = q_io_out_bits_vs_tag >> q_io_out_bits_vs_addr[1:0]; // @[VCommon.scala 135:20]
- wire q_io_out_ready_tag = _q_io_out_ready_tag_T_1[0]; // @[VCommon.scala 135:20]
- wire [6:0] q_io_out_ready_idx = {q_io_out_ready_tag,q_io_out_bits_vs_addr}; // @[Cat.scala 31:58]
- wire [127:0] _q_io_out_ready_T_1 = io_vrfsb >> q_io_out_ready_idx; // @[VCommon.scala 138:21]
- wire _q_io_out_ready_T_4 = ~q_io_out_bits_vs_valid | ~_q_io_out_ready_T_1[0]; // @[VCommon.scala 138:15]
- wire ctrlready = ctrl_io_in_ready & data_io_in_ready; // @[VSt.scala 282:50]
- wire [7:0] qmaxvlb = q_io_out_bits_op == 7'h4 ? 8'h8 : 8'h20; // @[VSt.scala 248:20]
- wire [7:0] qsize = q_io_out_bits_remain > qmaxvlb ? qmaxvlb : q_io_out_bits_remain; // @[VSt.scala 249:18]
- wire _T_4 = ~reset; // @[VSt.scala 263:9]
- wire [63:0] data_io_in_bits_data_d0 = io_read_data[63:0]; // @[VSt.scala 199:18]
- wire [63:0] data_io_in_bits_data_d1 = io_read_data[127:64]; // @[VSt.scala 200:18]
- wire [63:0] data_io_in_bits_data_d2 = io_read_data[191:128]; // @[VSt.scala 201:18]
- wire [63:0] data_io_in_bits_data_d3 = io_read_data[255:192]; // @[VSt.scala 202:18]
- wire _data_io_in_bits_data_dataout_T = ~ctrl_io_out_bits_vstq; // @[VSt.scala 204:25]
- wire [255:0] _data_io_in_bits_data_dataout_T_1 = _data_io_in_bits_data_dataout_T ? io_read_data : 256'h0; // @[Library.scala 22:8]
- wire _data_io_in_bits_data_dataout_T_3 = ctrl_io_out_bits_vstq & ctrl_io_out_bits_quad == 2'h0; // @[VSt.scala 205:30]
- wire [255:0] _data_io_in_bits_data_dataout_T_4 = {data_io_in_bits_data_d0,data_io_in_bits_data_d0,
- data_io_in_bits_data_d0,data_io_in_bits_data_d0}; // @[Cat.scala 31:58]
- wire [255:0] _data_io_in_bits_data_dataout_T_5 = _data_io_in_bits_data_dataout_T_3 ? _data_io_in_bits_data_dataout_T_4
- : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_io_in_bits_data_dataout_T_6 = _data_io_in_bits_data_dataout_T_1 | _data_io_in_bits_data_dataout_T_5
- ; // @[VSt.scala 204:38]
- wire _data_io_in_bits_data_dataout_T_8 = ctrl_io_out_bits_vstq & ctrl_io_out_bits_quad == 2'h1; // @[VSt.scala 206:30]
- wire [255:0] _data_io_in_bits_data_dataout_T_9 = {data_io_in_bits_data_d1,data_io_in_bits_data_d1,
- data_io_in_bits_data_d1,data_io_in_bits_data_d1}; // @[Cat.scala 31:58]
- wire [255:0] _data_io_in_bits_data_dataout_T_10 = _data_io_in_bits_data_dataout_T_8 ?
- _data_io_in_bits_data_dataout_T_9 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_io_in_bits_data_dataout_T_11 = _data_io_in_bits_data_dataout_T_6 |
- _data_io_in_bits_data_dataout_T_10; // @[VSt.scala 205:68]
- wire _data_io_in_bits_data_dataout_T_13 = ctrl_io_out_bits_vstq & ctrl_io_out_bits_quad == 2'h2; // @[VSt.scala 207:30]
- wire [255:0] _data_io_in_bits_data_dataout_T_14 = {data_io_in_bits_data_d2,data_io_in_bits_data_d2,
- data_io_in_bits_data_d2,data_io_in_bits_data_d2}; // @[Cat.scala 31:58]
- wire [255:0] _data_io_in_bits_data_dataout_T_15 = _data_io_in_bits_data_dataout_T_13 ?
- _data_io_in_bits_data_dataout_T_14 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_io_in_bits_data_dataout_T_16 = _data_io_in_bits_data_dataout_T_11 |
- _data_io_in_bits_data_dataout_T_15; // @[VSt.scala 206:68]
- wire _data_io_in_bits_data_dataout_T_18 = ctrl_io_out_bits_vstq & ctrl_io_out_bits_quad == 2'h3; // @[VSt.scala 208:30]
- wire [255:0] _data_io_in_bits_data_dataout_T_19 = {data_io_in_bits_data_d3,data_io_in_bits_data_d3,
- data_io_in_bits_data_d3,data_io_in_bits_data_d3}; // @[Cat.scala 31:58]
- wire [255:0] _data_io_in_bits_data_dataout_T_20 = _data_io_in_bits_data_dataout_T_18 ?
- _data_io_in_bits_data_dataout_T_19 : 256'h0; // @[Library.scala 22:8]
- wire data_io_in_bits_strb_strbB_1 = ctrl_io_out_bits_size > 6'h1; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_0 = ctrl_io_out_bits_size > 6'h0; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_3 = ctrl_io_out_bits_size > 6'h3; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_2 = ctrl_io_out_bits_size > 6'h2; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_5 = ctrl_io_out_bits_size > 6'h5; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_4 = ctrl_io_out_bits_size > 6'h4; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_7 = ctrl_io_out_bits_size > 6'h7; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_6 = ctrl_io_out_bits_size > 6'h6; // @[VSt.scala 228:24]
- wire [7:0] data_io_in_bits_strb_strb_lo_lo = {data_io_in_bits_strb_strbB_7,data_io_in_bits_strb_strbB_6,
- data_io_in_bits_strb_strbB_5,data_io_in_bits_strb_strbB_4,data_io_in_bits_strb_strbB_3,data_io_in_bits_strb_strbB_2,
- data_io_in_bits_strb_strbB_1,data_io_in_bits_strb_strbB_0}; // @[VSt.scala 219:22]
- wire data_io_in_bits_strb_strbB_9 = ctrl_io_out_bits_size > 6'h9; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_8 = ctrl_io_out_bits_size > 6'h8; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_11 = ctrl_io_out_bits_size > 6'hb; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_10 = ctrl_io_out_bits_size > 6'ha; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_13 = ctrl_io_out_bits_size > 6'hd; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_12 = ctrl_io_out_bits_size > 6'hc; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_15 = ctrl_io_out_bits_size > 6'hf; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_14 = ctrl_io_out_bits_size > 6'he; // @[VSt.scala 228:24]
- wire [15:0] data_io_in_bits_strb_strb_lo = {data_io_in_bits_strb_strbB_15,data_io_in_bits_strb_strbB_14,
- data_io_in_bits_strb_strbB_13,data_io_in_bits_strb_strbB_12,data_io_in_bits_strb_strbB_11,
- data_io_in_bits_strb_strbB_10,data_io_in_bits_strb_strbB_9,data_io_in_bits_strb_strbB_8,
- data_io_in_bits_strb_strb_lo_lo}; // @[VSt.scala 219:22]
- wire data_io_in_bits_strb_strbB_17 = ctrl_io_out_bits_size > 6'h11; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_16 = ctrl_io_out_bits_size > 6'h10; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_19 = ctrl_io_out_bits_size > 6'h13; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_18 = ctrl_io_out_bits_size > 6'h12; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_21 = ctrl_io_out_bits_size > 6'h15; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_20 = ctrl_io_out_bits_size > 6'h14; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_23 = ctrl_io_out_bits_size > 6'h17; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_22 = ctrl_io_out_bits_size > 6'h16; // @[VSt.scala 228:24]
- wire [7:0] data_io_in_bits_strb_strb_hi_lo = {data_io_in_bits_strb_strbB_23,data_io_in_bits_strb_strbB_22,
- data_io_in_bits_strb_strbB_21,data_io_in_bits_strb_strbB_20,data_io_in_bits_strb_strbB_19,
- data_io_in_bits_strb_strbB_18,data_io_in_bits_strb_strbB_17,data_io_in_bits_strb_strbB_16}; // @[VSt.scala 219:22]
- wire data_io_in_bits_strb_strbB_25 = ctrl_io_out_bits_size > 6'h19; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_24 = ctrl_io_out_bits_size > 6'h18; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_27 = ctrl_io_out_bits_size > 6'h1b; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_26 = ctrl_io_out_bits_size > 6'h1a; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_29 = ctrl_io_out_bits_size > 6'h1d; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_28 = ctrl_io_out_bits_size > 6'h1c; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_31 = ctrl_io_out_bits_size > 6'h1f; // @[VSt.scala 228:24]
- wire data_io_in_bits_strb_strbB_30 = ctrl_io_out_bits_size > 6'h1e; // @[VSt.scala 228:24]
- wire [31:0] data_io_in_bits_strb_strb = {data_io_in_bits_strb_strbB_31,data_io_in_bits_strb_strbB_30,
- data_io_in_bits_strb_strbB_29,data_io_in_bits_strb_strbB_28,data_io_in_bits_strb_strbB_27,
- data_io_in_bits_strb_strbB_26,data_io_in_bits_strb_strbB_25,data_io_in_bits_strb_strbB_24,
- data_io_in_bits_strb_strb_hi_lo,data_io_in_bits_strb_strb_lo}; // @[VSt.scala 219:22]
- wire [7:0] data_io_in_bits_strb_strbq = data_io_in_bits_strb_strb[7:0]; // @[VSt.scala 220:21]
- wire [1:0] data_io_in_bits_strb_quad = ctrl_io_out_bits_addr[4:3]; // @[VSt.scala 224:20]
- wire [31:0] _data_io_in_bits_strb_strbout_T_1 = _data_io_in_bits_data_dataout_T ? data_io_in_bits_strb_strb : 32'h0; // @[Library.scala 22:8]
- wire _data_io_in_bits_strb_strbout_T_3 = ctrl_io_out_bits_vstq & data_io_in_bits_strb_quad == 2'h0; // @[VSt.scala 232:19]
- wire [31:0] _data_io_in_bits_strb_strbout_T_4 = {16'h0,8'h0,data_io_in_bits_strb_strbq}; // @[Cat.scala 31:58]
- wire [31:0] _data_io_in_bits_strb_strbout_T_5 = _data_io_in_bits_strb_strbout_T_3 ? _data_io_in_bits_strb_strbout_T_4
- : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_io_in_bits_strb_strbout_T_6 = _data_io_in_bits_strb_strbout_T_1 | _data_io_in_bits_strb_strbout_T_5; // @[VSt.scala 231:38]
- wire _data_io_in_bits_strb_strbout_T_8 = ctrl_io_out_bits_vstq & data_io_in_bits_strb_quad == 2'h1; // @[VSt.scala 233:19]
- wire [31:0] _data_io_in_bits_strb_strbout_T_9 = {16'h0,data_io_in_bits_strb_strbq,8'h0}; // @[Cat.scala 31:58]
- wire [31:0] _data_io_in_bits_strb_strbout_T_10 = _data_io_in_bits_strb_strbout_T_8 ? _data_io_in_bits_strb_strbout_T_9
- : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_io_in_bits_strb_strbout_T_11 = _data_io_in_bits_strb_strbout_T_6 |
- _data_io_in_bits_strb_strbout_T_10; // @[VSt.scala 232:69]
- wire _data_io_in_bits_strb_strbout_T_13 = ctrl_io_out_bits_vstq & data_io_in_bits_strb_quad == 2'h2; // @[VSt.scala 234:19]
- wire [31:0] _data_io_in_bits_strb_strbout_T_14 = {8'h0,data_io_in_bits_strb_strbq,16'h0}; // @[Cat.scala 31:58]
- wire [31:0] _data_io_in_bits_strb_strbout_T_15 = _data_io_in_bits_strb_strbout_T_13 ?
- _data_io_in_bits_strb_strbout_T_14 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _data_io_in_bits_strb_strbout_T_16 = _data_io_in_bits_strb_strbout_T_11 |
- _data_io_in_bits_strb_strbout_T_15; // @[VSt.scala 233:69]
- wire _data_io_in_bits_strb_strbout_T_18 = ctrl_io_out_bits_vstq & data_io_in_bits_strb_quad == 2'h3; // @[VSt.scala 235:19]
- wire [31:0] _data_io_in_bits_strb_strbout_T_19 = {data_io_in_bits_strb_strbq,8'h0,16'h0}; // @[Cat.scala 31:58]
- wire [31:0] _data_io_in_bits_strb_strbout_T_20 = _data_io_in_bits_strb_strbout_T_18 ?
- _data_io_in_bits_strb_strbout_T_19 : 32'h0; // @[Library.scala 22:8]
- wire [26:0] io_axi_addr_bits_addr_hi = {1'h0,ctrl_io_out_bits_addr[30:5]}; // @[Cat.scala 31:58]
- reg nempty; // @[VSt.scala 307:23]
- reg [8:0] count; // @[VSt.scala 308:22]
- wire inc = io_axi_addr_valid & io_axi_addr_ready; // @[VSt.scala 309:31]
- wire dec = io_axi_resp_valid & io_axi_resp_ready; // @[VSt.scala 310:31]
- wire _T_27 = inc | dec; // @[VSt.scala 312:13]
- wire [8:0] _GEN_2 = {{8'd0}, inc}; // @[VSt.scala 313:26]
- wire [8:0] _nxtcount_T_1 = count + _GEN_2; // @[VSt.scala 313:26]
- wire [8:0] _GEN_3 = {{8'd0}, dec}; // @[VSt.scala 313:32]
- wire [8:0] nxtcount = _nxtcount_T_1 - _GEN_3; // @[VSt.scala 313:32]
- VCmdq_5 q ( // @[VCmdq.scala 30:11]
- .clock(q_clock),
- .reset(q_reset),
- .io_in_ready(q_io_in_ready),
- .io_in_valid(q_io_in_valid),
- .io_in_bits_0_valid(q_io_in_bits_0_valid),
- .io_in_bits_0_bits_op(q_io_in_bits_0_bits_op),
- .io_in_bits_0_bits_f2(q_io_in_bits_0_bits_f2),
- .io_in_bits_0_bits_sz(q_io_in_bits_0_bits_sz),
- .io_in_bits_0_bits_m(q_io_in_bits_0_bits_m),
- .io_in_bits_0_bits_vs_valid(q_io_in_bits_0_bits_vs_valid),
- .io_in_bits_0_bits_vs_addr(q_io_in_bits_0_bits_vs_addr),
- .io_in_bits_0_bits_vs_tag(q_io_in_bits_0_bits_vs_tag),
- .io_in_bits_0_bits_sv_addr(q_io_in_bits_0_bits_sv_addr),
- .io_in_bits_0_bits_sv_data(q_io_in_bits_0_bits_sv_data),
- .io_in_bits_1_valid(q_io_in_bits_1_valid),
- .io_in_bits_1_bits_op(q_io_in_bits_1_bits_op),
- .io_in_bits_1_bits_f2(q_io_in_bits_1_bits_f2),
- .io_in_bits_1_bits_sz(q_io_in_bits_1_bits_sz),
- .io_in_bits_1_bits_m(q_io_in_bits_1_bits_m),
- .io_in_bits_1_bits_vs_valid(q_io_in_bits_1_bits_vs_valid),
- .io_in_bits_1_bits_vs_addr(q_io_in_bits_1_bits_vs_addr),
- .io_in_bits_1_bits_vs_tag(q_io_in_bits_1_bits_vs_tag),
- .io_in_bits_1_bits_sv_addr(q_io_in_bits_1_bits_sv_addr),
- .io_in_bits_1_bits_sv_data(q_io_in_bits_1_bits_sv_data),
- .io_in_bits_2_valid(q_io_in_bits_2_valid),
- .io_in_bits_2_bits_op(q_io_in_bits_2_bits_op),
- .io_in_bits_2_bits_f2(q_io_in_bits_2_bits_f2),
- .io_in_bits_2_bits_sz(q_io_in_bits_2_bits_sz),
- .io_in_bits_2_bits_m(q_io_in_bits_2_bits_m),
- .io_in_bits_2_bits_vs_valid(q_io_in_bits_2_bits_vs_valid),
- .io_in_bits_2_bits_vs_addr(q_io_in_bits_2_bits_vs_addr),
- .io_in_bits_2_bits_vs_tag(q_io_in_bits_2_bits_vs_tag),
- .io_in_bits_2_bits_sv_addr(q_io_in_bits_2_bits_sv_addr),
- .io_in_bits_2_bits_sv_data(q_io_in_bits_2_bits_sv_data),
- .io_in_bits_3_valid(q_io_in_bits_3_valid),
- .io_in_bits_3_bits_op(q_io_in_bits_3_bits_op),
- .io_in_bits_3_bits_f2(q_io_in_bits_3_bits_f2),
- .io_in_bits_3_bits_sz(q_io_in_bits_3_bits_sz),
- .io_in_bits_3_bits_m(q_io_in_bits_3_bits_m),
- .io_in_bits_3_bits_vs_valid(q_io_in_bits_3_bits_vs_valid),
- .io_in_bits_3_bits_vs_addr(q_io_in_bits_3_bits_vs_addr),
- .io_in_bits_3_bits_vs_tag(q_io_in_bits_3_bits_vs_tag),
- .io_in_bits_3_bits_sv_addr(q_io_in_bits_3_bits_sv_addr),
- .io_in_bits_3_bits_sv_data(q_io_in_bits_3_bits_sv_data),
- .io_out_ready(q_io_out_ready),
- .io_out_valid(q_io_out_valid),
- .io_out_bits_op(q_io_out_bits_op),
- .io_out_bits_addr(q_io_out_bits_addr),
- .io_out_bits_remain(q_io_out_bits_remain),
- .io_out_bits_vs_valid(q_io_out_bits_vs_valid),
- .io_out_bits_vs_addr(q_io_out_bits_vs_addr),
- .io_out_bits_vs_tag(q_io_out_bits_vs_tag),
- .io_out_bits_quad(q_io_out_bits_quad),
- .io_active(q_io_active),
- .io_nempty(q_io_nempty)
- );
- Slice_6 ctrl ( // @[Slice.scala 23:11]
- .clock(ctrl_clock),
- .reset(ctrl_reset),
- .io_in_ready(ctrl_io_in_ready),
- .io_in_valid(ctrl_io_in_valid),
- .io_in_bits_addr(ctrl_io_in_bits_addr),
- .io_in_bits_id(ctrl_io_in_bits_id),
- .io_in_bits_size(ctrl_io_in_bits_size),
- .io_in_bits_vstq(ctrl_io_in_bits_vstq),
- .io_in_bits_quad(ctrl_io_in_bits_quad),
- .io_out_ready(ctrl_io_out_ready),
- .io_out_valid(ctrl_io_out_valid),
- .io_out_bits_addr(ctrl_io_out_bits_addr),
- .io_out_bits_id(ctrl_io_out_bits_id),
- .io_out_bits_size(ctrl_io_out_bits_size),
- .io_out_bits_vstq(ctrl_io_out_bits_vstq),
- .io_out_bits_quad(ctrl_io_out_bits_quad)
- );
- Slice_7 data ( // @[Slice.scala 23:11]
- .clock(data_clock),
- .reset(data_reset),
- .io_in_ready(data_io_in_ready),
- .io_in_valid(data_io_in_valid),
- .io_in_bits_data(data_io_in_bits_data),
- .io_in_bits_strb(data_io_in_bits_strb),
- .io_out_ready(data_io_out_ready),
- .io_out_valid(data_io_out_valid),
- .io_out_bits_data(data_io_out_bits_data),
- .io_out_bits_strb(data_io_out_bits_strb)
- );
- assign io_in_ready = q_io_in_ready; // @[VSt.scala 243:11]
- assign io_active = q_io_active; // @[VSt.scala 303:13]
- assign io_read_valid = q_io_out_valid & q_io_out_bits_vs_valid; // @[VSt.scala 255:35]
- assign io_read_addr = q_io_out_bits_vs_addr; // @[VSt.scala 257:16]
- assign io_axi_addr_valid = ctrl_io_out_valid; // @[VSt.scala 286:21]
- assign io_axi_addr_bits_addr = {io_axi_addr_bits_addr_hi,5'h0}; // @[Cat.scala 31:58]
- assign io_axi_addr_bits_id = ctrl_io_out_bits_id; // @[VSt.scala 288:23]
- assign io_axi_data_valid = ctrl_io_out_valid; // @[VSt.scala 292:21]
- assign io_axi_data_bits_data = data_io_out_bits_data; // @[VSt.scala 293:25]
- assign io_axi_data_bits_strb = data_io_out_bits_strb; // @[VSt.scala 294:25]
- assign io_axi_resp_ready = 1'h1; // @[VSt.scala 296:21]
- assign io_nempty = q_io_nempty | ctrl_io_out_valid | nempty; // @[VSt.scala 319:49]
- assign q_clock = clock;
- assign q_reset = reset;
- assign q_io_in_valid = io_in_valid; // @[VSt.scala 243:11]
- assign q_io_in_bits_0_valid = io_in_bits_0_valid; // @[VSt.scala 243:11]
- assign q_io_in_bits_0_bits_op = io_in_bits_0_bits_op; // @[VSt.scala 243:11]
- assign q_io_in_bits_0_bits_f2 = io_in_bits_0_bits_f2; // @[VSt.scala 243:11]
- assign q_io_in_bits_0_bits_sz = io_in_bits_0_bits_sz; // @[VSt.scala 243:11]
- assign q_io_in_bits_0_bits_m = io_in_bits_0_bits_m; // @[VSt.scala 243:11]
- assign q_io_in_bits_0_bits_vs_valid = io_in_bits_0_bits_vs_valid; // @[VSt.scala 243:11]
- assign q_io_in_bits_0_bits_vs_addr = io_in_bits_0_bits_vs_addr; // @[VSt.scala 243:11]
- assign q_io_in_bits_0_bits_vs_tag = io_in_bits_0_bits_vs_tag; // @[VSt.scala 243:11]
- assign q_io_in_bits_0_bits_sv_addr = io_in_bits_0_bits_sv_addr; // @[VSt.scala 243:11]
- assign q_io_in_bits_0_bits_sv_data = io_in_bits_0_bits_sv_data; // @[VSt.scala 243:11]
- assign q_io_in_bits_1_valid = io_in_bits_1_valid; // @[VSt.scala 243:11]
- assign q_io_in_bits_1_bits_op = io_in_bits_1_bits_op; // @[VSt.scala 243:11]
- assign q_io_in_bits_1_bits_f2 = io_in_bits_1_bits_f2; // @[VSt.scala 243:11]
- assign q_io_in_bits_1_bits_sz = io_in_bits_1_bits_sz; // @[VSt.scala 243:11]
- assign q_io_in_bits_1_bits_m = io_in_bits_1_bits_m; // @[VSt.scala 243:11]
- assign q_io_in_bits_1_bits_vs_valid = io_in_bits_1_bits_vs_valid; // @[VSt.scala 243:11]
- assign q_io_in_bits_1_bits_vs_addr = io_in_bits_1_bits_vs_addr; // @[VSt.scala 243:11]
- assign q_io_in_bits_1_bits_vs_tag = io_in_bits_1_bits_vs_tag; // @[VSt.scala 243:11]
- assign q_io_in_bits_1_bits_sv_addr = io_in_bits_1_bits_sv_addr; // @[VSt.scala 243:11]
- assign q_io_in_bits_1_bits_sv_data = io_in_bits_1_bits_sv_data; // @[VSt.scala 243:11]
- assign q_io_in_bits_2_valid = io_in_bits_2_valid; // @[VSt.scala 243:11]
- assign q_io_in_bits_2_bits_op = io_in_bits_2_bits_op; // @[VSt.scala 243:11]
- assign q_io_in_bits_2_bits_f2 = io_in_bits_2_bits_f2; // @[VSt.scala 243:11]
- assign q_io_in_bits_2_bits_sz = io_in_bits_2_bits_sz; // @[VSt.scala 243:11]
- assign q_io_in_bits_2_bits_m = io_in_bits_2_bits_m; // @[VSt.scala 243:11]
- assign q_io_in_bits_2_bits_vs_valid = io_in_bits_2_bits_vs_valid; // @[VSt.scala 243:11]
- assign q_io_in_bits_2_bits_vs_addr = io_in_bits_2_bits_vs_addr; // @[VSt.scala 243:11]
- assign q_io_in_bits_2_bits_vs_tag = io_in_bits_2_bits_vs_tag; // @[VSt.scala 243:11]
- assign q_io_in_bits_2_bits_sv_addr = io_in_bits_2_bits_sv_addr; // @[VSt.scala 243:11]
- assign q_io_in_bits_2_bits_sv_data = io_in_bits_2_bits_sv_data; // @[VSt.scala 243:11]
- assign q_io_in_bits_3_valid = io_in_bits_3_valid; // @[VSt.scala 243:11]
- assign q_io_in_bits_3_bits_op = io_in_bits_3_bits_op; // @[VSt.scala 243:11]
- assign q_io_in_bits_3_bits_f2 = io_in_bits_3_bits_f2; // @[VSt.scala 243:11]
- assign q_io_in_bits_3_bits_sz = io_in_bits_3_bits_sz; // @[VSt.scala 243:11]
- assign q_io_in_bits_3_bits_m = io_in_bits_3_bits_m; // @[VSt.scala 243:11]
- assign q_io_in_bits_3_bits_vs_valid = io_in_bits_3_bits_vs_valid; // @[VSt.scala 243:11]
- assign q_io_in_bits_3_bits_vs_addr = io_in_bits_3_bits_vs_addr; // @[VSt.scala 243:11]
- assign q_io_in_bits_3_bits_vs_tag = io_in_bits_3_bits_vs_tag; // @[VSt.scala 243:11]
- assign q_io_in_bits_3_bits_sv_addr = io_in_bits_3_bits_sv_addr; // @[VSt.scala 243:11]
- assign q_io_in_bits_3_bits_sv_data = io_in_bits_3_bits_sv_data; // @[VSt.scala 243:11]
- assign q_io_out_ready = _q_io_out_ready_T_4 & ctrlready; // @[VSt.scala 246:65]
- assign ctrl_clock = clock;
- assign ctrl_reset = reset;
- assign ctrl_io_in_valid = q_io_out_valid & q_io_out_ready; // @[VSt.scala 251:31]
- assign ctrl_io_in_bits_addr = q_io_out_bits_addr; // @[VSt.scala 274:24]
- assign ctrl_io_in_bits_id = q_io_out_bits_vs_addr; // @[VSt.scala 275:24]
- assign ctrl_io_in_bits_size = qsize[5:0]; // @[VSt.scala 276:24]
- assign ctrl_io_in_bits_vstq = q_io_out_bits_op == 7'h4; // @[VSt.scala 277:44]
- assign ctrl_io_in_bits_quad = q_io_out_bits_quad; // @[VSt.scala 278:24]
- assign ctrl_io_out_ready = io_axi_addr_ready; // @[VSt.scala 280:21]
- assign data_clock = clock;
- assign data_reset = reset;
- assign data_io_in_valid = dataEn; // @[VSt.scala 262:20]
- assign data_io_in_bits_data = _data_io_in_bits_data_dataout_T_16 | _data_io_in_bits_data_dataout_T_20; // @[VSt.scala 207:68]
- assign data_io_in_bits_strb = _data_io_in_bits_strb_strbout_T_16 | _data_io_in_bits_strb_strbout_T_20; // @[VSt.scala 234:69]
- assign data_io_out_ready = io_axi_addr_ready; // @[VSt.scala 265:21]
- always @(posedge clock) begin
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(data_io_in_valid & ~data_io_in_ready))) begin
- $fatal; // @[VSt.scala 263:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(data_io_in_valid & ~data_io_in_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VSt.scala:263 assert(!(data.io.in.valid && !data.io.in.ready))\n"); // @[VSt.scala 263:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(ctrl_io_out_valid & ~ctrl_io_out_bits_addr[31]))) begin
- $fatal; // @[VSt.scala 289:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(ctrl_io_out_valid & ~ctrl_io_out_bits_addr[31]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VSt.scala:289 assert(!(ctrl.io.out.valid && !ctrl.io.out.bits.addr(31)))\n"); // @[VSt.scala 289:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(~(io_axi_addr_valid & io_axi_addr_bits_addr[31]))) begin
- $fatal; // @[VSt.scala 290:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(~(io_axi_addr_valid & io_axi_addr_bits_addr[31]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VSt.scala:290 assert(!(io.axi.addr.valid && io.axi.addr.bits.addr(31)))\n"); // @[VSt.scala 290:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(io_axi_addr_valid == io_axi_data_valid)) begin
- $fatal; // @[VSt.scala 298:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(io_axi_addr_valid == io_axi_data_valid)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VSt.scala:298 assert(io.axi.addr.valid === io.axi.data.valid)\n"); // @[VSt.scala 298:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4 & ~(io_axi_addr_ready == io_axi_data_ready)) begin
- $fatal; // @[VSt.scala 299:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4 & ~(io_axi_addr_ready == io_axi_data_ready)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VSt.scala:299 assert(io.axi.addr.ready === io.axi.data.ready)\n"); // @[VSt.scala 299:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_27 & _T_4 & ~(count <= 9'h100)) begin
- $fatal; // @[VSt.scala 316:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_27 & _T_4 & ~(count <= 9'h100)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VSt.scala:316 assert(count <= 256.U)\n"); // @[VSt.scala 316:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VSt.scala 251:31]
- dataEn <= 1'h0;
- end else begin
- dataEn <= q_io_out_valid & q_io_out_ready;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VSt.scala 312:21]
- nempty <= 1'h0; // @[VSt.scala 315:12]
- end else if (inc | dec) begin // @[VSt.scala 307:23]
- nempty <= nxtcount != 9'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VSt.scala 312:21]
- count <= 9'h0; // @[VSt.scala 314:11]
- end else if (inc | dec) begin // @[VSt.scala 308:22]
- count <= nxtcount;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- dataEn = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- nempty = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- count = _RAND_2[8:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- dataEn = 1'h0;
- end
- if (reset) begin
- nempty = 1'h0;
- end
- if (reset) begin
- count = 9'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VRegfileSegment(
- input clock,
- input reset,
- input [5:0] io_read_0_addr,
- output [31:0] io_read_0_data,
- input [5:0] io_read_1_addr,
- output [31:0] io_read_1_data,
- input [5:0] io_read_2_addr,
- output [31:0] io_read_2_data,
- input [5:0] io_read_3_addr,
- output [31:0] io_read_3_data,
- input [5:0] io_read_4_addr,
- output [31:0] io_read_4_data,
- input [5:0] io_read_5_addr,
- output [31:0] io_read_5_data,
- input [5:0] io_read_6_addr,
- output [31:0] io_read_6_data,
- input [5:0] io_transpose_addr,
- output [255:0] io_transpose_data,
- input [5:0] io_internal_addr,
- output [31:0] io_internal_data,
- input io_write_0_valid,
- input [5:0] io_write_0_addr,
- input [31:0] io_write_0_data,
- input io_write_1_valid,
- input [5:0] io_write_1_addr,
- input [31:0] io_write_1_data,
- input io_write_2_valid,
- input [5:0] io_write_2_addr,
- input [31:0] io_write_2_data,
- input io_write_3_valid,
- input [5:0] io_write_3_addr,
- input [31:0] io_write_3_data,
- input io_write_4_valid,
- input [5:0] io_write_4_addr,
- input [31:0] io_write_4_data,
- input io_write_5_valid,
- input [5:0] io_write_5_addr,
- input [31:0] io_write_5_data,
- input io_conv_valid,
- input [31:0] io_conv_data_0,
- input [31:0] io_conv_data_1,
- input [31:0] io_conv_data_2,
- input [31:0] io_conv_data_3,
- input [31:0] io_conv_data_4,
- input [31:0] io_conv_data_5,
- input [31:0] io_conv_data_6,
- input [31:0] io_conv_data_7
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
- reg [31:0] _RAND_34;
- reg [31:0] _RAND_35;
- reg [31:0] _RAND_36;
- reg [31:0] _RAND_37;
- reg [31:0] _RAND_38;
- reg [31:0] _RAND_39;
- reg [31:0] _RAND_40;
- reg [31:0] _RAND_41;
- reg [31:0] _RAND_42;
- reg [31:0] _RAND_43;
- reg [31:0] _RAND_44;
- reg [31:0] _RAND_45;
- reg [31:0] _RAND_46;
- reg [31:0] _RAND_47;
- reg [31:0] _RAND_48;
- reg [31:0] _RAND_49;
- reg [31:0] _RAND_50;
- reg [31:0] _RAND_51;
- reg [31:0] _RAND_52;
- reg [31:0] _RAND_53;
- reg [31:0] _RAND_54;
- reg [31:0] _RAND_55;
- reg [31:0] _RAND_56;
- reg [31:0] _RAND_57;
- reg [31:0] _RAND_58;
- reg [31:0] _RAND_59;
- reg [31:0] _RAND_60;
- reg [31:0] _RAND_61;
- reg [31:0] _RAND_62;
- reg [31:0] _RAND_63;
-`endif // RANDOMIZE_REG_INIT
- reg [31:0] vreg_0; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_1; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_2; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_3; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_4; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_5; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_6; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_7; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_8; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_9; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_10; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_11; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_12; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_13; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_14; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_15; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_16; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_17; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_18; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_19; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_20; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_21; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_22; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_23; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_24; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_25; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_26; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_27; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_28; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_29; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_30; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_31; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_32; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_33; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_34; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_35; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_36; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_37; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_38; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_39; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_40; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_41; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_42; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_43; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_44; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_45; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_46; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_47; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_48; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_49; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_50; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_51; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_52; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_53; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_54; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_55; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_56; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_57; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_58; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_59; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_60; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_61; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_62; // @[VRegfileSegment.scala 57:17]
- reg [31:0] vreg_63; // @[VRegfileSegment.scala 57:17]
- wire [31:0] io_read_0_data_value__0 = 6'h0 == io_read_0_addr ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__1 = 6'h1 == io_read_0_addr ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__2 = 6'h2 == io_read_0_addr ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__3 = 6'h3 == io_read_0_addr ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__4 = 6'h4 == io_read_0_addr ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__5 = 6'h5 == io_read_0_addr ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__6 = 6'h6 == io_read_0_addr ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__7 = 6'h7 == io_read_0_addr ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__8 = 6'h8 == io_read_0_addr ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__9 = 6'h9 == io_read_0_addr ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__10 = 6'ha == io_read_0_addr ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__11 = 6'hb == io_read_0_addr ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__12 = 6'hc == io_read_0_addr ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__13 = 6'hd == io_read_0_addr ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__14 = 6'he == io_read_0_addr ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__15 = 6'hf == io_read_0_addr ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__16 = 6'h10 == io_read_0_addr ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__17 = 6'h11 == io_read_0_addr ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__18 = 6'h12 == io_read_0_addr ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__19 = 6'h13 == io_read_0_addr ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__20 = 6'h14 == io_read_0_addr ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__21 = 6'h15 == io_read_0_addr ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__22 = 6'h16 == io_read_0_addr ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__23 = 6'h17 == io_read_0_addr ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__24 = 6'h18 == io_read_0_addr ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__25 = 6'h19 == io_read_0_addr ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__26 = 6'h1a == io_read_0_addr ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__27 = 6'h1b == io_read_0_addr ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__28 = 6'h1c == io_read_0_addr ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__29 = 6'h1d == io_read_0_addr ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__30 = 6'h1e == io_read_0_addr ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__31 = 6'h1f == io_read_0_addr ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__32 = 6'h20 == io_read_0_addr ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__33 = 6'h21 == io_read_0_addr ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__34 = 6'h22 == io_read_0_addr ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__35 = 6'h23 == io_read_0_addr ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__36 = 6'h24 == io_read_0_addr ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__37 = 6'h25 == io_read_0_addr ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__38 = 6'h26 == io_read_0_addr ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__39 = 6'h27 == io_read_0_addr ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__40 = 6'h28 == io_read_0_addr ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__41 = 6'h29 == io_read_0_addr ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__42 = 6'h2a == io_read_0_addr ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__43 = 6'h2b == io_read_0_addr ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__44 = 6'h2c == io_read_0_addr ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__45 = 6'h2d == io_read_0_addr ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__46 = 6'h2e == io_read_0_addr ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__47 = 6'h2f == io_read_0_addr ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__48 = 6'h30 == io_read_0_addr ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__49 = 6'h31 == io_read_0_addr ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__50 = 6'h32 == io_read_0_addr ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__51 = 6'h33 == io_read_0_addr ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__52 = 6'h34 == io_read_0_addr ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__53 = 6'h35 == io_read_0_addr ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__54 = 6'h36 == io_read_0_addr ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__55 = 6'h37 == io_read_0_addr ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__56 = 6'h38 == io_read_0_addr ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__57 = 6'h39 == io_read_0_addr ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__58 = 6'h3a == io_read_0_addr ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__59 = 6'h3b == io_read_0_addr ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__60 = 6'h3c == io_read_0_addr ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__61 = 6'h3d == io_read_0_addr ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__62 = 6'h3e == io_read_0_addr ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value__63 = 6'h3f == io_read_0_addr ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_0_data_value_1_0 = io_read_0_data_value__0 | io_read_0_data_value__1; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_1 = io_read_0_data_value__2 | io_read_0_data_value__3; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_2 = io_read_0_data_value__4 | io_read_0_data_value__5; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_3 = io_read_0_data_value__6 | io_read_0_data_value__7; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_4 = io_read_0_data_value__8 | io_read_0_data_value__9; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_5 = io_read_0_data_value__10 | io_read_0_data_value__11; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_6 = io_read_0_data_value__12 | io_read_0_data_value__13; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_7 = io_read_0_data_value__14 | io_read_0_data_value__15; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_8 = io_read_0_data_value__16 | io_read_0_data_value__17; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_9 = io_read_0_data_value__18 | io_read_0_data_value__19; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_10 = io_read_0_data_value__20 | io_read_0_data_value__21; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_11 = io_read_0_data_value__22 | io_read_0_data_value__23; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_12 = io_read_0_data_value__24 | io_read_0_data_value__25; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_13 = io_read_0_data_value__26 | io_read_0_data_value__27; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_14 = io_read_0_data_value__28 | io_read_0_data_value__29; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_15 = io_read_0_data_value__30 | io_read_0_data_value__31; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_16 = io_read_0_data_value__32 | io_read_0_data_value__33; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_17 = io_read_0_data_value__34 | io_read_0_data_value__35; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_18 = io_read_0_data_value__36 | io_read_0_data_value__37; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_19 = io_read_0_data_value__38 | io_read_0_data_value__39; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_20 = io_read_0_data_value__40 | io_read_0_data_value__41; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_21 = io_read_0_data_value__42 | io_read_0_data_value__43; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_22 = io_read_0_data_value__44 | io_read_0_data_value__45; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_23 = io_read_0_data_value__46 | io_read_0_data_value__47; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_24 = io_read_0_data_value__48 | io_read_0_data_value__49; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_25 = io_read_0_data_value__50 | io_read_0_data_value__51; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_26 = io_read_0_data_value__52 | io_read_0_data_value__53; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_27 = io_read_0_data_value__54 | io_read_0_data_value__55; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_28 = io_read_0_data_value__56 | io_read_0_data_value__57; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_29 = io_read_0_data_value__58 | io_read_0_data_value__59; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_30 = io_read_0_data_value__60 | io_read_0_data_value__61; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_1_31 = io_read_0_data_value__62 | io_read_0_data_value__63; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_0 = io_read_0_data_value_1_0 | io_read_0_data_value_1_1; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_1 = io_read_0_data_value_1_2 | io_read_0_data_value_1_3; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_2 = io_read_0_data_value_1_4 | io_read_0_data_value_1_5; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_3 = io_read_0_data_value_1_6 | io_read_0_data_value_1_7; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_4 = io_read_0_data_value_1_8 | io_read_0_data_value_1_9; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_5 = io_read_0_data_value_1_10 | io_read_0_data_value_1_11; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_6 = io_read_0_data_value_1_12 | io_read_0_data_value_1_13; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_7 = io_read_0_data_value_1_14 | io_read_0_data_value_1_15; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_8 = io_read_0_data_value_1_16 | io_read_0_data_value_1_17; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_9 = io_read_0_data_value_1_18 | io_read_0_data_value_1_19; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_10 = io_read_0_data_value_1_20 | io_read_0_data_value_1_21; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_11 = io_read_0_data_value_1_22 | io_read_0_data_value_1_23; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_12 = io_read_0_data_value_1_24 | io_read_0_data_value_1_25; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_13 = io_read_0_data_value_1_26 | io_read_0_data_value_1_27; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_14 = io_read_0_data_value_1_28 | io_read_0_data_value_1_29; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_2_15 = io_read_0_data_value_1_30 | io_read_0_data_value_1_31; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_3_0 = io_read_0_data_value_2_0 | io_read_0_data_value_2_1; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_3_1 = io_read_0_data_value_2_2 | io_read_0_data_value_2_3; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_3_2 = io_read_0_data_value_2_4 | io_read_0_data_value_2_5; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_3_3 = io_read_0_data_value_2_6 | io_read_0_data_value_2_7; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_3_4 = io_read_0_data_value_2_8 | io_read_0_data_value_2_9; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_3_5 = io_read_0_data_value_2_10 | io_read_0_data_value_2_11; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_3_6 = io_read_0_data_value_2_12 | io_read_0_data_value_2_13; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_3_7 = io_read_0_data_value_2_14 | io_read_0_data_value_2_15; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_4_0 = io_read_0_data_value_3_0 | io_read_0_data_value_3_1; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_4_1 = io_read_0_data_value_3_2 | io_read_0_data_value_3_3; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_4_2 = io_read_0_data_value_3_4 | io_read_0_data_value_3_5; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_4_3 = io_read_0_data_value_3_6 | io_read_0_data_value_3_7; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_5_0 = io_read_0_data_value_4_0 | io_read_0_data_value_4_1; // @[Library.scala 129:37]
- wire [31:0] io_read_0_data_value_5_1 = io_read_0_data_value_4_2 | io_read_0_data_value_4_3; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value__0 = 6'h0 == io_read_1_addr ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__1 = 6'h1 == io_read_1_addr ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__2 = 6'h2 == io_read_1_addr ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__3 = 6'h3 == io_read_1_addr ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__4 = 6'h4 == io_read_1_addr ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__5 = 6'h5 == io_read_1_addr ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__6 = 6'h6 == io_read_1_addr ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__7 = 6'h7 == io_read_1_addr ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__8 = 6'h8 == io_read_1_addr ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__9 = 6'h9 == io_read_1_addr ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__10 = 6'ha == io_read_1_addr ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__11 = 6'hb == io_read_1_addr ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__12 = 6'hc == io_read_1_addr ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__13 = 6'hd == io_read_1_addr ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__14 = 6'he == io_read_1_addr ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__15 = 6'hf == io_read_1_addr ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__16 = 6'h10 == io_read_1_addr ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__17 = 6'h11 == io_read_1_addr ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__18 = 6'h12 == io_read_1_addr ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__19 = 6'h13 == io_read_1_addr ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__20 = 6'h14 == io_read_1_addr ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__21 = 6'h15 == io_read_1_addr ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__22 = 6'h16 == io_read_1_addr ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__23 = 6'h17 == io_read_1_addr ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__24 = 6'h18 == io_read_1_addr ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__25 = 6'h19 == io_read_1_addr ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__26 = 6'h1a == io_read_1_addr ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__27 = 6'h1b == io_read_1_addr ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__28 = 6'h1c == io_read_1_addr ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__29 = 6'h1d == io_read_1_addr ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__30 = 6'h1e == io_read_1_addr ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__31 = 6'h1f == io_read_1_addr ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__32 = 6'h20 == io_read_1_addr ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__33 = 6'h21 == io_read_1_addr ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__34 = 6'h22 == io_read_1_addr ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__35 = 6'h23 == io_read_1_addr ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__36 = 6'h24 == io_read_1_addr ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__37 = 6'h25 == io_read_1_addr ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__38 = 6'h26 == io_read_1_addr ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__39 = 6'h27 == io_read_1_addr ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__40 = 6'h28 == io_read_1_addr ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__41 = 6'h29 == io_read_1_addr ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__42 = 6'h2a == io_read_1_addr ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__43 = 6'h2b == io_read_1_addr ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__44 = 6'h2c == io_read_1_addr ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__45 = 6'h2d == io_read_1_addr ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__46 = 6'h2e == io_read_1_addr ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__47 = 6'h2f == io_read_1_addr ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__48 = 6'h30 == io_read_1_addr ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__49 = 6'h31 == io_read_1_addr ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__50 = 6'h32 == io_read_1_addr ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__51 = 6'h33 == io_read_1_addr ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__52 = 6'h34 == io_read_1_addr ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__53 = 6'h35 == io_read_1_addr ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__54 = 6'h36 == io_read_1_addr ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__55 = 6'h37 == io_read_1_addr ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__56 = 6'h38 == io_read_1_addr ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__57 = 6'h39 == io_read_1_addr ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__58 = 6'h3a == io_read_1_addr ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__59 = 6'h3b == io_read_1_addr ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__60 = 6'h3c == io_read_1_addr ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__61 = 6'h3d == io_read_1_addr ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__62 = 6'h3e == io_read_1_addr ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value__63 = 6'h3f == io_read_1_addr ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_1_data_value_1_0 = io_read_1_data_value__0 | io_read_1_data_value__1; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_1 = io_read_1_data_value__2 | io_read_1_data_value__3; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_2 = io_read_1_data_value__4 | io_read_1_data_value__5; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_3 = io_read_1_data_value__6 | io_read_1_data_value__7; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_4 = io_read_1_data_value__8 | io_read_1_data_value__9; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_5 = io_read_1_data_value__10 | io_read_1_data_value__11; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_6 = io_read_1_data_value__12 | io_read_1_data_value__13; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_7 = io_read_1_data_value__14 | io_read_1_data_value__15; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_8 = io_read_1_data_value__16 | io_read_1_data_value__17; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_9 = io_read_1_data_value__18 | io_read_1_data_value__19; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_10 = io_read_1_data_value__20 | io_read_1_data_value__21; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_11 = io_read_1_data_value__22 | io_read_1_data_value__23; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_12 = io_read_1_data_value__24 | io_read_1_data_value__25; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_13 = io_read_1_data_value__26 | io_read_1_data_value__27; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_14 = io_read_1_data_value__28 | io_read_1_data_value__29; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_15 = io_read_1_data_value__30 | io_read_1_data_value__31; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_16 = io_read_1_data_value__32 | io_read_1_data_value__33; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_17 = io_read_1_data_value__34 | io_read_1_data_value__35; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_18 = io_read_1_data_value__36 | io_read_1_data_value__37; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_19 = io_read_1_data_value__38 | io_read_1_data_value__39; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_20 = io_read_1_data_value__40 | io_read_1_data_value__41; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_21 = io_read_1_data_value__42 | io_read_1_data_value__43; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_22 = io_read_1_data_value__44 | io_read_1_data_value__45; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_23 = io_read_1_data_value__46 | io_read_1_data_value__47; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_24 = io_read_1_data_value__48 | io_read_1_data_value__49; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_25 = io_read_1_data_value__50 | io_read_1_data_value__51; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_26 = io_read_1_data_value__52 | io_read_1_data_value__53; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_27 = io_read_1_data_value__54 | io_read_1_data_value__55; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_28 = io_read_1_data_value__56 | io_read_1_data_value__57; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_29 = io_read_1_data_value__58 | io_read_1_data_value__59; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_30 = io_read_1_data_value__60 | io_read_1_data_value__61; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_1_31 = io_read_1_data_value__62 | io_read_1_data_value__63; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_0 = io_read_1_data_value_1_0 | io_read_1_data_value_1_1; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_1 = io_read_1_data_value_1_2 | io_read_1_data_value_1_3; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_2 = io_read_1_data_value_1_4 | io_read_1_data_value_1_5; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_3 = io_read_1_data_value_1_6 | io_read_1_data_value_1_7; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_4 = io_read_1_data_value_1_8 | io_read_1_data_value_1_9; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_5 = io_read_1_data_value_1_10 | io_read_1_data_value_1_11; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_6 = io_read_1_data_value_1_12 | io_read_1_data_value_1_13; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_7 = io_read_1_data_value_1_14 | io_read_1_data_value_1_15; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_8 = io_read_1_data_value_1_16 | io_read_1_data_value_1_17; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_9 = io_read_1_data_value_1_18 | io_read_1_data_value_1_19; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_10 = io_read_1_data_value_1_20 | io_read_1_data_value_1_21; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_11 = io_read_1_data_value_1_22 | io_read_1_data_value_1_23; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_12 = io_read_1_data_value_1_24 | io_read_1_data_value_1_25; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_13 = io_read_1_data_value_1_26 | io_read_1_data_value_1_27; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_14 = io_read_1_data_value_1_28 | io_read_1_data_value_1_29; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_2_15 = io_read_1_data_value_1_30 | io_read_1_data_value_1_31; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_3_0 = io_read_1_data_value_2_0 | io_read_1_data_value_2_1; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_3_1 = io_read_1_data_value_2_2 | io_read_1_data_value_2_3; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_3_2 = io_read_1_data_value_2_4 | io_read_1_data_value_2_5; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_3_3 = io_read_1_data_value_2_6 | io_read_1_data_value_2_7; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_3_4 = io_read_1_data_value_2_8 | io_read_1_data_value_2_9; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_3_5 = io_read_1_data_value_2_10 | io_read_1_data_value_2_11; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_3_6 = io_read_1_data_value_2_12 | io_read_1_data_value_2_13; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_3_7 = io_read_1_data_value_2_14 | io_read_1_data_value_2_15; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_4_0 = io_read_1_data_value_3_0 | io_read_1_data_value_3_1; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_4_1 = io_read_1_data_value_3_2 | io_read_1_data_value_3_3; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_4_2 = io_read_1_data_value_3_4 | io_read_1_data_value_3_5; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_4_3 = io_read_1_data_value_3_6 | io_read_1_data_value_3_7; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_5_0 = io_read_1_data_value_4_0 | io_read_1_data_value_4_1; // @[Library.scala 129:37]
- wire [31:0] io_read_1_data_value_5_1 = io_read_1_data_value_4_2 | io_read_1_data_value_4_3; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value__0 = 6'h0 == io_read_2_addr ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__1 = 6'h1 == io_read_2_addr ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__2 = 6'h2 == io_read_2_addr ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__3 = 6'h3 == io_read_2_addr ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__4 = 6'h4 == io_read_2_addr ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__5 = 6'h5 == io_read_2_addr ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__6 = 6'h6 == io_read_2_addr ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__7 = 6'h7 == io_read_2_addr ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__8 = 6'h8 == io_read_2_addr ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__9 = 6'h9 == io_read_2_addr ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__10 = 6'ha == io_read_2_addr ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__11 = 6'hb == io_read_2_addr ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__12 = 6'hc == io_read_2_addr ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__13 = 6'hd == io_read_2_addr ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__14 = 6'he == io_read_2_addr ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__15 = 6'hf == io_read_2_addr ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__16 = 6'h10 == io_read_2_addr ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__17 = 6'h11 == io_read_2_addr ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__18 = 6'h12 == io_read_2_addr ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__19 = 6'h13 == io_read_2_addr ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__20 = 6'h14 == io_read_2_addr ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__21 = 6'h15 == io_read_2_addr ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__22 = 6'h16 == io_read_2_addr ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__23 = 6'h17 == io_read_2_addr ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__24 = 6'h18 == io_read_2_addr ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__25 = 6'h19 == io_read_2_addr ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__26 = 6'h1a == io_read_2_addr ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__27 = 6'h1b == io_read_2_addr ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__28 = 6'h1c == io_read_2_addr ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__29 = 6'h1d == io_read_2_addr ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__30 = 6'h1e == io_read_2_addr ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__31 = 6'h1f == io_read_2_addr ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__32 = 6'h20 == io_read_2_addr ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__33 = 6'h21 == io_read_2_addr ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__34 = 6'h22 == io_read_2_addr ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__35 = 6'h23 == io_read_2_addr ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__36 = 6'h24 == io_read_2_addr ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__37 = 6'h25 == io_read_2_addr ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__38 = 6'h26 == io_read_2_addr ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__39 = 6'h27 == io_read_2_addr ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__40 = 6'h28 == io_read_2_addr ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__41 = 6'h29 == io_read_2_addr ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__42 = 6'h2a == io_read_2_addr ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__43 = 6'h2b == io_read_2_addr ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__44 = 6'h2c == io_read_2_addr ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__45 = 6'h2d == io_read_2_addr ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__46 = 6'h2e == io_read_2_addr ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__47 = 6'h2f == io_read_2_addr ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__48 = 6'h30 == io_read_2_addr ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__49 = 6'h31 == io_read_2_addr ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__50 = 6'h32 == io_read_2_addr ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__51 = 6'h33 == io_read_2_addr ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__52 = 6'h34 == io_read_2_addr ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__53 = 6'h35 == io_read_2_addr ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__54 = 6'h36 == io_read_2_addr ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__55 = 6'h37 == io_read_2_addr ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__56 = 6'h38 == io_read_2_addr ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__57 = 6'h39 == io_read_2_addr ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__58 = 6'h3a == io_read_2_addr ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__59 = 6'h3b == io_read_2_addr ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__60 = 6'h3c == io_read_2_addr ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__61 = 6'h3d == io_read_2_addr ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__62 = 6'h3e == io_read_2_addr ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value__63 = 6'h3f == io_read_2_addr ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_2_data_value_1_0 = io_read_2_data_value__0 | io_read_2_data_value__1; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_1 = io_read_2_data_value__2 | io_read_2_data_value__3; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_2 = io_read_2_data_value__4 | io_read_2_data_value__5; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_3 = io_read_2_data_value__6 | io_read_2_data_value__7; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_4 = io_read_2_data_value__8 | io_read_2_data_value__9; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_5 = io_read_2_data_value__10 | io_read_2_data_value__11; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_6 = io_read_2_data_value__12 | io_read_2_data_value__13; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_7 = io_read_2_data_value__14 | io_read_2_data_value__15; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_8 = io_read_2_data_value__16 | io_read_2_data_value__17; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_9 = io_read_2_data_value__18 | io_read_2_data_value__19; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_10 = io_read_2_data_value__20 | io_read_2_data_value__21; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_11 = io_read_2_data_value__22 | io_read_2_data_value__23; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_12 = io_read_2_data_value__24 | io_read_2_data_value__25; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_13 = io_read_2_data_value__26 | io_read_2_data_value__27; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_14 = io_read_2_data_value__28 | io_read_2_data_value__29; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_15 = io_read_2_data_value__30 | io_read_2_data_value__31; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_16 = io_read_2_data_value__32 | io_read_2_data_value__33; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_17 = io_read_2_data_value__34 | io_read_2_data_value__35; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_18 = io_read_2_data_value__36 | io_read_2_data_value__37; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_19 = io_read_2_data_value__38 | io_read_2_data_value__39; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_20 = io_read_2_data_value__40 | io_read_2_data_value__41; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_21 = io_read_2_data_value__42 | io_read_2_data_value__43; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_22 = io_read_2_data_value__44 | io_read_2_data_value__45; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_23 = io_read_2_data_value__46 | io_read_2_data_value__47; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_24 = io_read_2_data_value__48 | io_read_2_data_value__49; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_25 = io_read_2_data_value__50 | io_read_2_data_value__51; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_26 = io_read_2_data_value__52 | io_read_2_data_value__53; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_27 = io_read_2_data_value__54 | io_read_2_data_value__55; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_28 = io_read_2_data_value__56 | io_read_2_data_value__57; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_29 = io_read_2_data_value__58 | io_read_2_data_value__59; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_30 = io_read_2_data_value__60 | io_read_2_data_value__61; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_1_31 = io_read_2_data_value__62 | io_read_2_data_value__63; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_0 = io_read_2_data_value_1_0 | io_read_2_data_value_1_1; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_1 = io_read_2_data_value_1_2 | io_read_2_data_value_1_3; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_2 = io_read_2_data_value_1_4 | io_read_2_data_value_1_5; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_3 = io_read_2_data_value_1_6 | io_read_2_data_value_1_7; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_4 = io_read_2_data_value_1_8 | io_read_2_data_value_1_9; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_5 = io_read_2_data_value_1_10 | io_read_2_data_value_1_11; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_6 = io_read_2_data_value_1_12 | io_read_2_data_value_1_13; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_7 = io_read_2_data_value_1_14 | io_read_2_data_value_1_15; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_8 = io_read_2_data_value_1_16 | io_read_2_data_value_1_17; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_9 = io_read_2_data_value_1_18 | io_read_2_data_value_1_19; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_10 = io_read_2_data_value_1_20 | io_read_2_data_value_1_21; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_11 = io_read_2_data_value_1_22 | io_read_2_data_value_1_23; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_12 = io_read_2_data_value_1_24 | io_read_2_data_value_1_25; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_13 = io_read_2_data_value_1_26 | io_read_2_data_value_1_27; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_14 = io_read_2_data_value_1_28 | io_read_2_data_value_1_29; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_2_15 = io_read_2_data_value_1_30 | io_read_2_data_value_1_31; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_3_0 = io_read_2_data_value_2_0 | io_read_2_data_value_2_1; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_3_1 = io_read_2_data_value_2_2 | io_read_2_data_value_2_3; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_3_2 = io_read_2_data_value_2_4 | io_read_2_data_value_2_5; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_3_3 = io_read_2_data_value_2_6 | io_read_2_data_value_2_7; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_3_4 = io_read_2_data_value_2_8 | io_read_2_data_value_2_9; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_3_5 = io_read_2_data_value_2_10 | io_read_2_data_value_2_11; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_3_6 = io_read_2_data_value_2_12 | io_read_2_data_value_2_13; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_3_7 = io_read_2_data_value_2_14 | io_read_2_data_value_2_15; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_4_0 = io_read_2_data_value_3_0 | io_read_2_data_value_3_1; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_4_1 = io_read_2_data_value_3_2 | io_read_2_data_value_3_3; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_4_2 = io_read_2_data_value_3_4 | io_read_2_data_value_3_5; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_4_3 = io_read_2_data_value_3_6 | io_read_2_data_value_3_7; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_5_0 = io_read_2_data_value_4_0 | io_read_2_data_value_4_1; // @[Library.scala 129:37]
- wire [31:0] io_read_2_data_value_5_1 = io_read_2_data_value_4_2 | io_read_2_data_value_4_3; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value__0 = 6'h0 == io_read_3_addr ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__1 = 6'h1 == io_read_3_addr ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__2 = 6'h2 == io_read_3_addr ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__3 = 6'h3 == io_read_3_addr ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__4 = 6'h4 == io_read_3_addr ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__5 = 6'h5 == io_read_3_addr ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__6 = 6'h6 == io_read_3_addr ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__7 = 6'h7 == io_read_3_addr ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__8 = 6'h8 == io_read_3_addr ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__9 = 6'h9 == io_read_3_addr ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__10 = 6'ha == io_read_3_addr ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__11 = 6'hb == io_read_3_addr ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__12 = 6'hc == io_read_3_addr ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__13 = 6'hd == io_read_3_addr ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__14 = 6'he == io_read_3_addr ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__15 = 6'hf == io_read_3_addr ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__16 = 6'h10 == io_read_3_addr ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__17 = 6'h11 == io_read_3_addr ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__18 = 6'h12 == io_read_3_addr ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__19 = 6'h13 == io_read_3_addr ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__20 = 6'h14 == io_read_3_addr ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__21 = 6'h15 == io_read_3_addr ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__22 = 6'h16 == io_read_3_addr ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__23 = 6'h17 == io_read_3_addr ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__24 = 6'h18 == io_read_3_addr ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__25 = 6'h19 == io_read_3_addr ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__26 = 6'h1a == io_read_3_addr ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__27 = 6'h1b == io_read_3_addr ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__28 = 6'h1c == io_read_3_addr ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__29 = 6'h1d == io_read_3_addr ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__30 = 6'h1e == io_read_3_addr ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__31 = 6'h1f == io_read_3_addr ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__32 = 6'h20 == io_read_3_addr ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__33 = 6'h21 == io_read_3_addr ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__34 = 6'h22 == io_read_3_addr ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__35 = 6'h23 == io_read_3_addr ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__36 = 6'h24 == io_read_3_addr ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__37 = 6'h25 == io_read_3_addr ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__38 = 6'h26 == io_read_3_addr ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__39 = 6'h27 == io_read_3_addr ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__40 = 6'h28 == io_read_3_addr ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__41 = 6'h29 == io_read_3_addr ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__42 = 6'h2a == io_read_3_addr ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__43 = 6'h2b == io_read_3_addr ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__44 = 6'h2c == io_read_3_addr ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__45 = 6'h2d == io_read_3_addr ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__46 = 6'h2e == io_read_3_addr ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__47 = 6'h2f == io_read_3_addr ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__48 = 6'h30 == io_read_3_addr ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__49 = 6'h31 == io_read_3_addr ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__50 = 6'h32 == io_read_3_addr ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__51 = 6'h33 == io_read_3_addr ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__52 = 6'h34 == io_read_3_addr ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__53 = 6'h35 == io_read_3_addr ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__54 = 6'h36 == io_read_3_addr ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__55 = 6'h37 == io_read_3_addr ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__56 = 6'h38 == io_read_3_addr ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__57 = 6'h39 == io_read_3_addr ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__58 = 6'h3a == io_read_3_addr ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__59 = 6'h3b == io_read_3_addr ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__60 = 6'h3c == io_read_3_addr ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__61 = 6'h3d == io_read_3_addr ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__62 = 6'h3e == io_read_3_addr ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value__63 = 6'h3f == io_read_3_addr ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_3_data_value_1_0 = io_read_3_data_value__0 | io_read_3_data_value__1; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_1 = io_read_3_data_value__2 | io_read_3_data_value__3; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_2 = io_read_3_data_value__4 | io_read_3_data_value__5; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_3 = io_read_3_data_value__6 | io_read_3_data_value__7; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_4 = io_read_3_data_value__8 | io_read_3_data_value__9; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_5 = io_read_3_data_value__10 | io_read_3_data_value__11; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_6 = io_read_3_data_value__12 | io_read_3_data_value__13; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_7 = io_read_3_data_value__14 | io_read_3_data_value__15; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_8 = io_read_3_data_value__16 | io_read_3_data_value__17; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_9 = io_read_3_data_value__18 | io_read_3_data_value__19; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_10 = io_read_3_data_value__20 | io_read_3_data_value__21; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_11 = io_read_3_data_value__22 | io_read_3_data_value__23; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_12 = io_read_3_data_value__24 | io_read_3_data_value__25; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_13 = io_read_3_data_value__26 | io_read_3_data_value__27; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_14 = io_read_3_data_value__28 | io_read_3_data_value__29; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_15 = io_read_3_data_value__30 | io_read_3_data_value__31; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_16 = io_read_3_data_value__32 | io_read_3_data_value__33; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_17 = io_read_3_data_value__34 | io_read_3_data_value__35; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_18 = io_read_3_data_value__36 | io_read_3_data_value__37; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_19 = io_read_3_data_value__38 | io_read_3_data_value__39; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_20 = io_read_3_data_value__40 | io_read_3_data_value__41; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_21 = io_read_3_data_value__42 | io_read_3_data_value__43; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_22 = io_read_3_data_value__44 | io_read_3_data_value__45; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_23 = io_read_3_data_value__46 | io_read_3_data_value__47; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_24 = io_read_3_data_value__48 | io_read_3_data_value__49; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_25 = io_read_3_data_value__50 | io_read_3_data_value__51; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_26 = io_read_3_data_value__52 | io_read_3_data_value__53; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_27 = io_read_3_data_value__54 | io_read_3_data_value__55; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_28 = io_read_3_data_value__56 | io_read_3_data_value__57; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_29 = io_read_3_data_value__58 | io_read_3_data_value__59; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_30 = io_read_3_data_value__60 | io_read_3_data_value__61; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_1_31 = io_read_3_data_value__62 | io_read_3_data_value__63; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_0 = io_read_3_data_value_1_0 | io_read_3_data_value_1_1; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_1 = io_read_3_data_value_1_2 | io_read_3_data_value_1_3; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_2 = io_read_3_data_value_1_4 | io_read_3_data_value_1_5; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_3 = io_read_3_data_value_1_6 | io_read_3_data_value_1_7; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_4 = io_read_3_data_value_1_8 | io_read_3_data_value_1_9; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_5 = io_read_3_data_value_1_10 | io_read_3_data_value_1_11; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_6 = io_read_3_data_value_1_12 | io_read_3_data_value_1_13; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_7 = io_read_3_data_value_1_14 | io_read_3_data_value_1_15; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_8 = io_read_3_data_value_1_16 | io_read_3_data_value_1_17; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_9 = io_read_3_data_value_1_18 | io_read_3_data_value_1_19; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_10 = io_read_3_data_value_1_20 | io_read_3_data_value_1_21; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_11 = io_read_3_data_value_1_22 | io_read_3_data_value_1_23; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_12 = io_read_3_data_value_1_24 | io_read_3_data_value_1_25; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_13 = io_read_3_data_value_1_26 | io_read_3_data_value_1_27; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_14 = io_read_3_data_value_1_28 | io_read_3_data_value_1_29; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_2_15 = io_read_3_data_value_1_30 | io_read_3_data_value_1_31; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_3_0 = io_read_3_data_value_2_0 | io_read_3_data_value_2_1; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_3_1 = io_read_3_data_value_2_2 | io_read_3_data_value_2_3; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_3_2 = io_read_3_data_value_2_4 | io_read_3_data_value_2_5; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_3_3 = io_read_3_data_value_2_6 | io_read_3_data_value_2_7; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_3_4 = io_read_3_data_value_2_8 | io_read_3_data_value_2_9; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_3_5 = io_read_3_data_value_2_10 | io_read_3_data_value_2_11; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_3_6 = io_read_3_data_value_2_12 | io_read_3_data_value_2_13; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_3_7 = io_read_3_data_value_2_14 | io_read_3_data_value_2_15; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_4_0 = io_read_3_data_value_3_0 | io_read_3_data_value_3_1; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_4_1 = io_read_3_data_value_3_2 | io_read_3_data_value_3_3; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_4_2 = io_read_3_data_value_3_4 | io_read_3_data_value_3_5; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_4_3 = io_read_3_data_value_3_6 | io_read_3_data_value_3_7; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_5_0 = io_read_3_data_value_4_0 | io_read_3_data_value_4_1; // @[Library.scala 129:37]
- wire [31:0] io_read_3_data_value_5_1 = io_read_3_data_value_4_2 | io_read_3_data_value_4_3; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value__0 = 6'h0 == io_read_4_addr ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__1 = 6'h1 == io_read_4_addr ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__2 = 6'h2 == io_read_4_addr ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__3 = 6'h3 == io_read_4_addr ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__4 = 6'h4 == io_read_4_addr ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__5 = 6'h5 == io_read_4_addr ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__6 = 6'h6 == io_read_4_addr ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__7 = 6'h7 == io_read_4_addr ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__8 = 6'h8 == io_read_4_addr ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__9 = 6'h9 == io_read_4_addr ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__10 = 6'ha == io_read_4_addr ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__11 = 6'hb == io_read_4_addr ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__12 = 6'hc == io_read_4_addr ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__13 = 6'hd == io_read_4_addr ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__14 = 6'he == io_read_4_addr ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__15 = 6'hf == io_read_4_addr ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__16 = 6'h10 == io_read_4_addr ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__17 = 6'h11 == io_read_4_addr ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__18 = 6'h12 == io_read_4_addr ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__19 = 6'h13 == io_read_4_addr ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__20 = 6'h14 == io_read_4_addr ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__21 = 6'h15 == io_read_4_addr ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__22 = 6'h16 == io_read_4_addr ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__23 = 6'h17 == io_read_4_addr ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__24 = 6'h18 == io_read_4_addr ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__25 = 6'h19 == io_read_4_addr ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__26 = 6'h1a == io_read_4_addr ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__27 = 6'h1b == io_read_4_addr ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__28 = 6'h1c == io_read_4_addr ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__29 = 6'h1d == io_read_4_addr ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__30 = 6'h1e == io_read_4_addr ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__31 = 6'h1f == io_read_4_addr ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__32 = 6'h20 == io_read_4_addr ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__33 = 6'h21 == io_read_4_addr ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__34 = 6'h22 == io_read_4_addr ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__35 = 6'h23 == io_read_4_addr ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__36 = 6'h24 == io_read_4_addr ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__37 = 6'h25 == io_read_4_addr ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__38 = 6'h26 == io_read_4_addr ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__39 = 6'h27 == io_read_4_addr ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__40 = 6'h28 == io_read_4_addr ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__41 = 6'h29 == io_read_4_addr ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__42 = 6'h2a == io_read_4_addr ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__43 = 6'h2b == io_read_4_addr ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__44 = 6'h2c == io_read_4_addr ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__45 = 6'h2d == io_read_4_addr ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__46 = 6'h2e == io_read_4_addr ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__47 = 6'h2f == io_read_4_addr ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__48 = 6'h30 == io_read_4_addr ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__49 = 6'h31 == io_read_4_addr ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__50 = 6'h32 == io_read_4_addr ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__51 = 6'h33 == io_read_4_addr ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__52 = 6'h34 == io_read_4_addr ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__53 = 6'h35 == io_read_4_addr ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__54 = 6'h36 == io_read_4_addr ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__55 = 6'h37 == io_read_4_addr ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__56 = 6'h38 == io_read_4_addr ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__57 = 6'h39 == io_read_4_addr ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__58 = 6'h3a == io_read_4_addr ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__59 = 6'h3b == io_read_4_addr ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__60 = 6'h3c == io_read_4_addr ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__61 = 6'h3d == io_read_4_addr ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__62 = 6'h3e == io_read_4_addr ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value__63 = 6'h3f == io_read_4_addr ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_4_data_value_1_0 = io_read_4_data_value__0 | io_read_4_data_value__1; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_1 = io_read_4_data_value__2 | io_read_4_data_value__3; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_2 = io_read_4_data_value__4 | io_read_4_data_value__5; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_3 = io_read_4_data_value__6 | io_read_4_data_value__7; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_4 = io_read_4_data_value__8 | io_read_4_data_value__9; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_5 = io_read_4_data_value__10 | io_read_4_data_value__11; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_6 = io_read_4_data_value__12 | io_read_4_data_value__13; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_7 = io_read_4_data_value__14 | io_read_4_data_value__15; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_8 = io_read_4_data_value__16 | io_read_4_data_value__17; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_9 = io_read_4_data_value__18 | io_read_4_data_value__19; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_10 = io_read_4_data_value__20 | io_read_4_data_value__21; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_11 = io_read_4_data_value__22 | io_read_4_data_value__23; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_12 = io_read_4_data_value__24 | io_read_4_data_value__25; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_13 = io_read_4_data_value__26 | io_read_4_data_value__27; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_14 = io_read_4_data_value__28 | io_read_4_data_value__29; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_15 = io_read_4_data_value__30 | io_read_4_data_value__31; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_16 = io_read_4_data_value__32 | io_read_4_data_value__33; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_17 = io_read_4_data_value__34 | io_read_4_data_value__35; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_18 = io_read_4_data_value__36 | io_read_4_data_value__37; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_19 = io_read_4_data_value__38 | io_read_4_data_value__39; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_20 = io_read_4_data_value__40 | io_read_4_data_value__41; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_21 = io_read_4_data_value__42 | io_read_4_data_value__43; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_22 = io_read_4_data_value__44 | io_read_4_data_value__45; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_23 = io_read_4_data_value__46 | io_read_4_data_value__47; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_24 = io_read_4_data_value__48 | io_read_4_data_value__49; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_25 = io_read_4_data_value__50 | io_read_4_data_value__51; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_26 = io_read_4_data_value__52 | io_read_4_data_value__53; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_27 = io_read_4_data_value__54 | io_read_4_data_value__55; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_28 = io_read_4_data_value__56 | io_read_4_data_value__57; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_29 = io_read_4_data_value__58 | io_read_4_data_value__59; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_30 = io_read_4_data_value__60 | io_read_4_data_value__61; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_1_31 = io_read_4_data_value__62 | io_read_4_data_value__63; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_0 = io_read_4_data_value_1_0 | io_read_4_data_value_1_1; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_1 = io_read_4_data_value_1_2 | io_read_4_data_value_1_3; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_2 = io_read_4_data_value_1_4 | io_read_4_data_value_1_5; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_3 = io_read_4_data_value_1_6 | io_read_4_data_value_1_7; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_4 = io_read_4_data_value_1_8 | io_read_4_data_value_1_9; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_5 = io_read_4_data_value_1_10 | io_read_4_data_value_1_11; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_6 = io_read_4_data_value_1_12 | io_read_4_data_value_1_13; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_7 = io_read_4_data_value_1_14 | io_read_4_data_value_1_15; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_8 = io_read_4_data_value_1_16 | io_read_4_data_value_1_17; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_9 = io_read_4_data_value_1_18 | io_read_4_data_value_1_19; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_10 = io_read_4_data_value_1_20 | io_read_4_data_value_1_21; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_11 = io_read_4_data_value_1_22 | io_read_4_data_value_1_23; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_12 = io_read_4_data_value_1_24 | io_read_4_data_value_1_25; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_13 = io_read_4_data_value_1_26 | io_read_4_data_value_1_27; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_14 = io_read_4_data_value_1_28 | io_read_4_data_value_1_29; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_2_15 = io_read_4_data_value_1_30 | io_read_4_data_value_1_31; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_3_0 = io_read_4_data_value_2_0 | io_read_4_data_value_2_1; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_3_1 = io_read_4_data_value_2_2 | io_read_4_data_value_2_3; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_3_2 = io_read_4_data_value_2_4 | io_read_4_data_value_2_5; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_3_3 = io_read_4_data_value_2_6 | io_read_4_data_value_2_7; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_3_4 = io_read_4_data_value_2_8 | io_read_4_data_value_2_9; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_3_5 = io_read_4_data_value_2_10 | io_read_4_data_value_2_11; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_3_6 = io_read_4_data_value_2_12 | io_read_4_data_value_2_13; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_3_7 = io_read_4_data_value_2_14 | io_read_4_data_value_2_15; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_4_0 = io_read_4_data_value_3_0 | io_read_4_data_value_3_1; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_4_1 = io_read_4_data_value_3_2 | io_read_4_data_value_3_3; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_4_2 = io_read_4_data_value_3_4 | io_read_4_data_value_3_5; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_4_3 = io_read_4_data_value_3_6 | io_read_4_data_value_3_7; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_5_0 = io_read_4_data_value_4_0 | io_read_4_data_value_4_1; // @[Library.scala 129:37]
- wire [31:0] io_read_4_data_value_5_1 = io_read_4_data_value_4_2 | io_read_4_data_value_4_3; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value__0 = 6'h0 == io_read_5_addr ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__1 = 6'h1 == io_read_5_addr ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__2 = 6'h2 == io_read_5_addr ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__3 = 6'h3 == io_read_5_addr ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__4 = 6'h4 == io_read_5_addr ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__5 = 6'h5 == io_read_5_addr ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__6 = 6'h6 == io_read_5_addr ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__7 = 6'h7 == io_read_5_addr ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__8 = 6'h8 == io_read_5_addr ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__9 = 6'h9 == io_read_5_addr ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__10 = 6'ha == io_read_5_addr ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__11 = 6'hb == io_read_5_addr ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__12 = 6'hc == io_read_5_addr ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__13 = 6'hd == io_read_5_addr ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__14 = 6'he == io_read_5_addr ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__15 = 6'hf == io_read_5_addr ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__16 = 6'h10 == io_read_5_addr ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__17 = 6'h11 == io_read_5_addr ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__18 = 6'h12 == io_read_5_addr ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__19 = 6'h13 == io_read_5_addr ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__20 = 6'h14 == io_read_5_addr ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__21 = 6'h15 == io_read_5_addr ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__22 = 6'h16 == io_read_5_addr ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__23 = 6'h17 == io_read_5_addr ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__24 = 6'h18 == io_read_5_addr ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__25 = 6'h19 == io_read_5_addr ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__26 = 6'h1a == io_read_5_addr ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__27 = 6'h1b == io_read_5_addr ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__28 = 6'h1c == io_read_5_addr ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__29 = 6'h1d == io_read_5_addr ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__30 = 6'h1e == io_read_5_addr ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__31 = 6'h1f == io_read_5_addr ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__32 = 6'h20 == io_read_5_addr ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__33 = 6'h21 == io_read_5_addr ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__34 = 6'h22 == io_read_5_addr ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__35 = 6'h23 == io_read_5_addr ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__36 = 6'h24 == io_read_5_addr ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__37 = 6'h25 == io_read_5_addr ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__38 = 6'h26 == io_read_5_addr ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__39 = 6'h27 == io_read_5_addr ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__40 = 6'h28 == io_read_5_addr ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__41 = 6'h29 == io_read_5_addr ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__42 = 6'h2a == io_read_5_addr ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__43 = 6'h2b == io_read_5_addr ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__44 = 6'h2c == io_read_5_addr ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__45 = 6'h2d == io_read_5_addr ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__46 = 6'h2e == io_read_5_addr ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__47 = 6'h2f == io_read_5_addr ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__48 = 6'h30 == io_read_5_addr ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__49 = 6'h31 == io_read_5_addr ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__50 = 6'h32 == io_read_5_addr ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__51 = 6'h33 == io_read_5_addr ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__52 = 6'h34 == io_read_5_addr ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__53 = 6'h35 == io_read_5_addr ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__54 = 6'h36 == io_read_5_addr ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__55 = 6'h37 == io_read_5_addr ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__56 = 6'h38 == io_read_5_addr ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__57 = 6'h39 == io_read_5_addr ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__58 = 6'h3a == io_read_5_addr ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__59 = 6'h3b == io_read_5_addr ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__60 = 6'h3c == io_read_5_addr ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__61 = 6'h3d == io_read_5_addr ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__62 = 6'h3e == io_read_5_addr ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value__63 = 6'h3f == io_read_5_addr ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_5_data_value_1_0 = io_read_5_data_value__0 | io_read_5_data_value__1; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_1 = io_read_5_data_value__2 | io_read_5_data_value__3; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_2 = io_read_5_data_value__4 | io_read_5_data_value__5; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_3 = io_read_5_data_value__6 | io_read_5_data_value__7; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_4 = io_read_5_data_value__8 | io_read_5_data_value__9; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_5 = io_read_5_data_value__10 | io_read_5_data_value__11; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_6 = io_read_5_data_value__12 | io_read_5_data_value__13; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_7 = io_read_5_data_value__14 | io_read_5_data_value__15; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_8 = io_read_5_data_value__16 | io_read_5_data_value__17; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_9 = io_read_5_data_value__18 | io_read_5_data_value__19; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_10 = io_read_5_data_value__20 | io_read_5_data_value__21; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_11 = io_read_5_data_value__22 | io_read_5_data_value__23; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_12 = io_read_5_data_value__24 | io_read_5_data_value__25; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_13 = io_read_5_data_value__26 | io_read_5_data_value__27; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_14 = io_read_5_data_value__28 | io_read_5_data_value__29; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_15 = io_read_5_data_value__30 | io_read_5_data_value__31; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_16 = io_read_5_data_value__32 | io_read_5_data_value__33; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_17 = io_read_5_data_value__34 | io_read_5_data_value__35; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_18 = io_read_5_data_value__36 | io_read_5_data_value__37; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_19 = io_read_5_data_value__38 | io_read_5_data_value__39; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_20 = io_read_5_data_value__40 | io_read_5_data_value__41; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_21 = io_read_5_data_value__42 | io_read_5_data_value__43; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_22 = io_read_5_data_value__44 | io_read_5_data_value__45; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_23 = io_read_5_data_value__46 | io_read_5_data_value__47; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_24 = io_read_5_data_value__48 | io_read_5_data_value__49; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_25 = io_read_5_data_value__50 | io_read_5_data_value__51; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_26 = io_read_5_data_value__52 | io_read_5_data_value__53; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_27 = io_read_5_data_value__54 | io_read_5_data_value__55; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_28 = io_read_5_data_value__56 | io_read_5_data_value__57; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_29 = io_read_5_data_value__58 | io_read_5_data_value__59; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_30 = io_read_5_data_value__60 | io_read_5_data_value__61; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_1_31 = io_read_5_data_value__62 | io_read_5_data_value__63; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_0 = io_read_5_data_value_1_0 | io_read_5_data_value_1_1; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_1 = io_read_5_data_value_1_2 | io_read_5_data_value_1_3; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_2 = io_read_5_data_value_1_4 | io_read_5_data_value_1_5; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_3 = io_read_5_data_value_1_6 | io_read_5_data_value_1_7; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_4 = io_read_5_data_value_1_8 | io_read_5_data_value_1_9; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_5 = io_read_5_data_value_1_10 | io_read_5_data_value_1_11; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_6 = io_read_5_data_value_1_12 | io_read_5_data_value_1_13; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_7 = io_read_5_data_value_1_14 | io_read_5_data_value_1_15; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_8 = io_read_5_data_value_1_16 | io_read_5_data_value_1_17; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_9 = io_read_5_data_value_1_18 | io_read_5_data_value_1_19; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_10 = io_read_5_data_value_1_20 | io_read_5_data_value_1_21; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_11 = io_read_5_data_value_1_22 | io_read_5_data_value_1_23; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_12 = io_read_5_data_value_1_24 | io_read_5_data_value_1_25; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_13 = io_read_5_data_value_1_26 | io_read_5_data_value_1_27; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_14 = io_read_5_data_value_1_28 | io_read_5_data_value_1_29; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_2_15 = io_read_5_data_value_1_30 | io_read_5_data_value_1_31; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_3_0 = io_read_5_data_value_2_0 | io_read_5_data_value_2_1; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_3_1 = io_read_5_data_value_2_2 | io_read_5_data_value_2_3; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_3_2 = io_read_5_data_value_2_4 | io_read_5_data_value_2_5; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_3_3 = io_read_5_data_value_2_6 | io_read_5_data_value_2_7; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_3_4 = io_read_5_data_value_2_8 | io_read_5_data_value_2_9; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_3_5 = io_read_5_data_value_2_10 | io_read_5_data_value_2_11; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_3_6 = io_read_5_data_value_2_12 | io_read_5_data_value_2_13; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_3_7 = io_read_5_data_value_2_14 | io_read_5_data_value_2_15; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_4_0 = io_read_5_data_value_3_0 | io_read_5_data_value_3_1; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_4_1 = io_read_5_data_value_3_2 | io_read_5_data_value_3_3; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_4_2 = io_read_5_data_value_3_4 | io_read_5_data_value_3_5; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_4_3 = io_read_5_data_value_3_6 | io_read_5_data_value_3_7; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_5_0 = io_read_5_data_value_4_0 | io_read_5_data_value_4_1; // @[Library.scala 129:37]
- wire [31:0] io_read_5_data_value_5_1 = io_read_5_data_value_4_2 | io_read_5_data_value_4_3; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value__0 = 6'h0 == io_read_6_addr ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__1 = 6'h1 == io_read_6_addr ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__2 = 6'h2 == io_read_6_addr ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__3 = 6'h3 == io_read_6_addr ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__4 = 6'h4 == io_read_6_addr ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__5 = 6'h5 == io_read_6_addr ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__6 = 6'h6 == io_read_6_addr ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__7 = 6'h7 == io_read_6_addr ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__8 = 6'h8 == io_read_6_addr ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__9 = 6'h9 == io_read_6_addr ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__10 = 6'ha == io_read_6_addr ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__11 = 6'hb == io_read_6_addr ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__12 = 6'hc == io_read_6_addr ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__13 = 6'hd == io_read_6_addr ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__14 = 6'he == io_read_6_addr ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__15 = 6'hf == io_read_6_addr ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__16 = 6'h10 == io_read_6_addr ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__17 = 6'h11 == io_read_6_addr ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__18 = 6'h12 == io_read_6_addr ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__19 = 6'h13 == io_read_6_addr ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__20 = 6'h14 == io_read_6_addr ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__21 = 6'h15 == io_read_6_addr ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__22 = 6'h16 == io_read_6_addr ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__23 = 6'h17 == io_read_6_addr ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__24 = 6'h18 == io_read_6_addr ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__25 = 6'h19 == io_read_6_addr ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__26 = 6'h1a == io_read_6_addr ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__27 = 6'h1b == io_read_6_addr ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__28 = 6'h1c == io_read_6_addr ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__29 = 6'h1d == io_read_6_addr ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__30 = 6'h1e == io_read_6_addr ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__31 = 6'h1f == io_read_6_addr ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__32 = 6'h20 == io_read_6_addr ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__33 = 6'h21 == io_read_6_addr ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__34 = 6'h22 == io_read_6_addr ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__35 = 6'h23 == io_read_6_addr ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__36 = 6'h24 == io_read_6_addr ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__37 = 6'h25 == io_read_6_addr ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__38 = 6'h26 == io_read_6_addr ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__39 = 6'h27 == io_read_6_addr ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__40 = 6'h28 == io_read_6_addr ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__41 = 6'h29 == io_read_6_addr ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__42 = 6'h2a == io_read_6_addr ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__43 = 6'h2b == io_read_6_addr ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__44 = 6'h2c == io_read_6_addr ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__45 = 6'h2d == io_read_6_addr ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__46 = 6'h2e == io_read_6_addr ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__47 = 6'h2f == io_read_6_addr ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__48 = 6'h30 == io_read_6_addr ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__49 = 6'h31 == io_read_6_addr ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__50 = 6'h32 == io_read_6_addr ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__51 = 6'h33 == io_read_6_addr ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__52 = 6'h34 == io_read_6_addr ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__53 = 6'h35 == io_read_6_addr ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__54 = 6'h36 == io_read_6_addr ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__55 = 6'h37 == io_read_6_addr ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__56 = 6'h38 == io_read_6_addr ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__57 = 6'h39 == io_read_6_addr ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__58 = 6'h3a == io_read_6_addr ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__59 = 6'h3b == io_read_6_addr ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__60 = 6'h3c == io_read_6_addr ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__61 = 6'h3d == io_read_6_addr ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__62 = 6'h3e == io_read_6_addr ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value__63 = 6'h3f == io_read_6_addr ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_read_6_data_value_1_0 = io_read_6_data_value__0 | io_read_6_data_value__1; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_1 = io_read_6_data_value__2 | io_read_6_data_value__3; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_2 = io_read_6_data_value__4 | io_read_6_data_value__5; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_3 = io_read_6_data_value__6 | io_read_6_data_value__7; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_4 = io_read_6_data_value__8 | io_read_6_data_value__9; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_5 = io_read_6_data_value__10 | io_read_6_data_value__11; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_6 = io_read_6_data_value__12 | io_read_6_data_value__13; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_7 = io_read_6_data_value__14 | io_read_6_data_value__15; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_8 = io_read_6_data_value__16 | io_read_6_data_value__17; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_9 = io_read_6_data_value__18 | io_read_6_data_value__19; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_10 = io_read_6_data_value__20 | io_read_6_data_value__21; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_11 = io_read_6_data_value__22 | io_read_6_data_value__23; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_12 = io_read_6_data_value__24 | io_read_6_data_value__25; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_13 = io_read_6_data_value__26 | io_read_6_data_value__27; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_14 = io_read_6_data_value__28 | io_read_6_data_value__29; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_15 = io_read_6_data_value__30 | io_read_6_data_value__31; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_16 = io_read_6_data_value__32 | io_read_6_data_value__33; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_17 = io_read_6_data_value__34 | io_read_6_data_value__35; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_18 = io_read_6_data_value__36 | io_read_6_data_value__37; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_19 = io_read_6_data_value__38 | io_read_6_data_value__39; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_20 = io_read_6_data_value__40 | io_read_6_data_value__41; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_21 = io_read_6_data_value__42 | io_read_6_data_value__43; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_22 = io_read_6_data_value__44 | io_read_6_data_value__45; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_23 = io_read_6_data_value__46 | io_read_6_data_value__47; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_24 = io_read_6_data_value__48 | io_read_6_data_value__49; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_25 = io_read_6_data_value__50 | io_read_6_data_value__51; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_26 = io_read_6_data_value__52 | io_read_6_data_value__53; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_27 = io_read_6_data_value__54 | io_read_6_data_value__55; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_28 = io_read_6_data_value__56 | io_read_6_data_value__57; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_29 = io_read_6_data_value__58 | io_read_6_data_value__59; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_30 = io_read_6_data_value__60 | io_read_6_data_value__61; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_1_31 = io_read_6_data_value__62 | io_read_6_data_value__63; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_0 = io_read_6_data_value_1_0 | io_read_6_data_value_1_1; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_1 = io_read_6_data_value_1_2 | io_read_6_data_value_1_3; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_2 = io_read_6_data_value_1_4 | io_read_6_data_value_1_5; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_3 = io_read_6_data_value_1_6 | io_read_6_data_value_1_7; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_4 = io_read_6_data_value_1_8 | io_read_6_data_value_1_9; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_5 = io_read_6_data_value_1_10 | io_read_6_data_value_1_11; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_6 = io_read_6_data_value_1_12 | io_read_6_data_value_1_13; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_7 = io_read_6_data_value_1_14 | io_read_6_data_value_1_15; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_8 = io_read_6_data_value_1_16 | io_read_6_data_value_1_17; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_9 = io_read_6_data_value_1_18 | io_read_6_data_value_1_19; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_10 = io_read_6_data_value_1_20 | io_read_6_data_value_1_21; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_11 = io_read_6_data_value_1_22 | io_read_6_data_value_1_23; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_12 = io_read_6_data_value_1_24 | io_read_6_data_value_1_25; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_13 = io_read_6_data_value_1_26 | io_read_6_data_value_1_27; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_14 = io_read_6_data_value_1_28 | io_read_6_data_value_1_29; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_2_15 = io_read_6_data_value_1_30 | io_read_6_data_value_1_31; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_3_0 = io_read_6_data_value_2_0 | io_read_6_data_value_2_1; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_3_1 = io_read_6_data_value_2_2 | io_read_6_data_value_2_3; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_3_2 = io_read_6_data_value_2_4 | io_read_6_data_value_2_5; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_3_3 = io_read_6_data_value_2_6 | io_read_6_data_value_2_7; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_3_4 = io_read_6_data_value_2_8 | io_read_6_data_value_2_9; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_3_5 = io_read_6_data_value_2_10 | io_read_6_data_value_2_11; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_3_6 = io_read_6_data_value_2_12 | io_read_6_data_value_2_13; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_3_7 = io_read_6_data_value_2_14 | io_read_6_data_value_2_15; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_4_0 = io_read_6_data_value_3_0 | io_read_6_data_value_3_1; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_4_1 = io_read_6_data_value_3_2 | io_read_6_data_value_3_3; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_4_2 = io_read_6_data_value_3_4 | io_read_6_data_value_3_5; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_4_3 = io_read_6_data_value_3_6 | io_read_6_data_value_3_7; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_5_0 = io_read_6_data_value_4_0 | io_read_6_data_value_4_1; // @[Library.scala 129:37]
- wire [31:0] io_read_6_data_value_5_1 = io_read_6_data_value_4_2 | io_read_6_data_value_4_3; // @[Library.scala 129:37]
- wire [5:0] tidx = {io_transpose_addr[5:4],4'h0}; // @[Cat.scala 31:58]
- wire [31:0] tdata_0_value__0 = 6'h0 == tidx ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__1 = 6'h1 == tidx ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__2 = 6'h2 == tidx ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__3 = 6'h3 == tidx ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__4 = 6'h4 == tidx ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__5 = 6'h5 == tidx ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__6 = 6'h6 == tidx ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__7 = 6'h7 == tidx ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__8 = 6'h8 == tidx ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__9 = 6'h9 == tidx ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__10 = 6'ha == tidx ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__11 = 6'hb == tidx ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__12 = 6'hc == tidx ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__13 = 6'hd == tidx ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__14 = 6'he == tidx ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__15 = 6'hf == tidx ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__16 = 6'h10 == tidx ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__17 = 6'h11 == tidx ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__18 = 6'h12 == tidx ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__19 = 6'h13 == tidx ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__20 = 6'h14 == tidx ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__21 = 6'h15 == tidx ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__22 = 6'h16 == tidx ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__23 = 6'h17 == tidx ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__24 = 6'h18 == tidx ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__25 = 6'h19 == tidx ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__26 = 6'h1a == tidx ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__27 = 6'h1b == tidx ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__28 = 6'h1c == tidx ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__29 = 6'h1d == tidx ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__30 = 6'h1e == tidx ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__31 = 6'h1f == tidx ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__32 = 6'h20 == tidx ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__33 = 6'h21 == tidx ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__34 = 6'h22 == tidx ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__35 = 6'h23 == tidx ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__36 = 6'h24 == tidx ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__37 = 6'h25 == tidx ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__38 = 6'h26 == tidx ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__39 = 6'h27 == tidx ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__40 = 6'h28 == tidx ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__41 = 6'h29 == tidx ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__42 = 6'h2a == tidx ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__43 = 6'h2b == tidx ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__44 = 6'h2c == tidx ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__45 = 6'h2d == tidx ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__46 = 6'h2e == tidx ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__47 = 6'h2f == tidx ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__48 = 6'h30 == tidx ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__49 = 6'h31 == tidx ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__50 = 6'h32 == tidx ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__51 = 6'h33 == tidx ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__52 = 6'h34 == tidx ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__53 = 6'h35 == tidx ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__54 = 6'h36 == tidx ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__55 = 6'h37 == tidx ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__56 = 6'h38 == tidx ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__57 = 6'h39 == tidx ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__58 = 6'h3a == tidx ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__59 = 6'h3b == tidx ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__60 = 6'h3c == tidx ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__61 = 6'h3d == tidx ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__62 = 6'h3e == tidx ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value__63 = 6'h3f == tidx ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_0_value_1_0 = tdata_0_value__0 | tdata_0_value__1; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_1 = tdata_0_value__2 | tdata_0_value__3; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_2 = tdata_0_value__4 | tdata_0_value__5; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_3 = tdata_0_value__6 | tdata_0_value__7; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_4 = tdata_0_value__8 | tdata_0_value__9; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_5 = tdata_0_value__10 | tdata_0_value__11; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_6 = tdata_0_value__12 | tdata_0_value__13; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_7 = tdata_0_value__14 | tdata_0_value__15; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_8 = tdata_0_value__16 | tdata_0_value__17; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_9 = tdata_0_value__18 | tdata_0_value__19; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_10 = tdata_0_value__20 | tdata_0_value__21; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_11 = tdata_0_value__22 | tdata_0_value__23; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_12 = tdata_0_value__24 | tdata_0_value__25; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_13 = tdata_0_value__26 | tdata_0_value__27; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_14 = tdata_0_value__28 | tdata_0_value__29; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_15 = tdata_0_value__30 | tdata_0_value__31; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_16 = tdata_0_value__32 | tdata_0_value__33; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_17 = tdata_0_value__34 | tdata_0_value__35; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_18 = tdata_0_value__36 | tdata_0_value__37; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_19 = tdata_0_value__38 | tdata_0_value__39; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_20 = tdata_0_value__40 | tdata_0_value__41; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_21 = tdata_0_value__42 | tdata_0_value__43; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_22 = tdata_0_value__44 | tdata_0_value__45; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_23 = tdata_0_value__46 | tdata_0_value__47; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_24 = tdata_0_value__48 | tdata_0_value__49; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_25 = tdata_0_value__50 | tdata_0_value__51; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_26 = tdata_0_value__52 | tdata_0_value__53; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_27 = tdata_0_value__54 | tdata_0_value__55; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_28 = tdata_0_value__56 | tdata_0_value__57; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_29 = tdata_0_value__58 | tdata_0_value__59; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_30 = tdata_0_value__60 | tdata_0_value__61; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_1_31 = tdata_0_value__62 | tdata_0_value__63; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_0 = tdata_0_value_1_0 | tdata_0_value_1_1; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_1 = tdata_0_value_1_2 | tdata_0_value_1_3; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_2 = tdata_0_value_1_4 | tdata_0_value_1_5; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_3 = tdata_0_value_1_6 | tdata_0_value_1_7; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_4 = tdata_0_value_1_8 | tdata_0_value_1_9; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_5 = tdata_0_value_1_10 | tdata_0_value_1_11; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_6 = tdata_0_value_1_12 | tdata_0_value_1_13; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_7 = tdata_0_value_1_14 | tdata_0_value_1_15; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_8 = tdata_0_value_1_16 | tdata_0_value_1_17; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_9 = tdata_0_value_1_18 | tdata_0_value_1_19; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_10 = tdata_0_value_1_20 | tdata_0_value_1_21; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_11 = tdata_0_value_1_22 | tdata_0_value_1_23; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_12 = tdata_0_value_1_24 | tdata_0_value_1_25; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_13 = tdata_0_value_1_26 | tdata_0_value_1_27; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_14 = tdata_0_value_1_28 | tdata_0_value_1_29; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_2_15 = tdata_0_value_1_30 | tdata_0_value_1_31; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_3_0 = tdata_0_value_2_0 | tdata_0_value_2_1; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_3_1 = tdata_0_value_2_2 | tdata_0_value_2_3; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_3_2 = tdata_0_value_2_4 | tdata_0_value_2_5; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_3_3 = tdata_0_value_2_6 | tdata_0_value_2_7; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_3_4 = tdata_0_value_2_8 | tdata_0_value_2_9; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_3_5 = tdata_0_value_2_10 | tdata_0_value_2_11; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_3_6 = tdata_0_value_2_12 | tdata_0_value_2_13; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_3_7 = tdata_0_value_2_14 | tdata_0_value_2_15; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_4_0 = tdata_0_value_3_0 | tdata_0_value_3_1; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_4_1 = tdata_0_value_3_2 | tdata_0_value_3_3; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_4_2 = tdata_0_value_3_4 | tdata_0_value_3_5; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_4_3 = tdata_0_value_3_6 | tdata_0_value_3_7; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_5_0 = tdata_0_value_4_0 | tdata_0_value_4_1; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_5_1 = tdata_0_value_4_2 | tdata_0_value_4_3; // @[Library.scala 129:37]
- wire [31:0] tdata_0_value_6_0 = tdata_0_value_5_0 | tdata_0_value_5_1; // @[Library.scala 129:37]
- wire [5:0] tidx_1 = {io_transpose_addr[5:4],4'h1}; // @[Cat.scala 31:58]
- wire [31:0] tdata_1_value__0 = 6'h0 == tidx_1 ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__1 = 6'h1 == tidx_1 ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__2 = 6'h2 == tidx_1 ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__3 = 6'h3 == tidx_1 ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__4 = 6'h4 == tidx_1 ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__5 = 6'h5 == tidx_1 ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__6 = 6'h6 == tidx_1 ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__7 = 6'h7 == tidx_1 ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__8 = 6'h8 == tidx_1 ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__9 = 6'h9 == tidx_1 ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__10 = 6'ha == tidx_1 ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__11 = 6'hb == tidx_1 ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__12 = 6'hc == tidx_1 ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__13 = 6'hd == tidx_1 ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__14 = 6'he == tidx_1 ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__15 = 6'hf == tidx_1 ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__16 = 6'h10 == tidx_1 ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__17 = 6'h11 == tidx_1 ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__18 = 6'h12 == tidx_1 ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__19 = 6'h13 == tidx_1 ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__20 = 6'h14 == tidx_1 ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__21 = 6'h15 == tidx_1 ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__22 = 6'h16 == tidx_1 ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__23 = 6'h17 == tidx_1 ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__24 = 6'h18 == tidx_1 ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__25 = 6'h19 == tidx_1 ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__26 = 6'h1a == tidx_1 ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__27 = 6'h1b == tidx_1 ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__28 = 6'h1c == tidx_1 ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__29 = 6'h1d == tidx_1 ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__30 = 6'h1e == tidx_1 ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__31 = 6'h1f == tidx_1 ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__32 = 6'h20 == tidx_1 ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__33 = 6'h21 == tidx_1 ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__34 = 6'h22 == tidx_1 ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__35 = 6'h23 == tidx_1 ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__36 = 6'h24 == tidx_1 ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__37 = 6'h25 == tidx_1 ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__38 = 6'h26 == tidx_1 ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__39 = 6'h27 == tidx_1 ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__40 = 6'h28 == tidx_1 ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__41 = 6'h29 == tidx_1 ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__42 = 6'h2a == tidx_1 ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__43 = 6'h2b == tidx_1 ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__44 = 6'h2c == tidx_1 ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__45 = 6'h2d == tidx_1 ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__46 = 6'h2e == tidx_1 ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__47 = 6'h2f == tidx_1 ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__48 = 6'h30 == tidx_1 ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__49 = 6'h31 == tidx_1 ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__50 = 6'h32 == tidx_1 ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__51 = 6'h33 == tidx_1 ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__52 = 6'h34 == tidx_1 ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__53 = 6'h35 == tidx_1 ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__54 = 6'h36 == tidx_1 ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__55 = 6'h37 == tidx_1 ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__56 = 6'h38 == tidx_1 ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__57 = 6'h39 == tidx_1 ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__58 = 6'h3a == tidx_1 ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__59 = 6'h3b == tidx_1 ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__60 = 6'h3c == tidx_1 ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__61 = 6'h3d == tidx_1 ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__62 = 6'h3e == tidx_1 ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value__63 = 6'h3f == tidx_1 ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_1_value_1_0 = tdata_1_value__0 | tdata_1_value__1; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_1 = tdata_1_value__2 | tdata_1_value__3; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_2 = tdata_1_value__4 | tdata_1_value__5; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_3 = tdata_1_value__6 | tdata_1_value__7; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_4 = tdata_1_value__8 | tdata_1_value__9; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_5 = tdata_1_value__10 | tdata_1_value__11; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_6 = tdata_1_value__12 | tdata_1_value__13; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_7 = tdata_1_value__14 | tdata_1_value__15; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_8 = tdata_1_value__16 | tdata_1_value__17; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_9 = tdata_1_value__18 | tdata_1_value__19; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_10 = tdata_1_value__20 | tdata_1_value__21; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_11 = tdata_1_value__22 | tdata_1_value__23; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_12 = tdata_1_value__24 | tdata_1_value__25; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_13 = tdata_1_value__26 | tdata_1_value__27; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_14 = tdata_1_value__28 | tdata_1_value__29; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_15 = tdata_1_value__30 | tdata_1_value__31; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_16 = tdata_1_value__32 | tdata_1_value__33; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_17 = tdata_1_value__34 | tdata_1_value__35; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_18 = tdata_1_value__36 | tdata_1_value__37; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_19 = tdata_1_value__38 | tdata_1_value__39; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_20 = tdata_1_value__40 | tdata_1_value__41; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_21 = tdata_1_value__42 | tdata_1_value__43; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_22 = tdata_1_value__44 | tdata_1_value__45; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_23 = tdata_1_value__46 | tdata_1_value__47; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_24 = tdata_1_value__48 | tdata_1_value__49; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_25 = tdata_1_value__50 | tdata_1_value__51; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_26 = tdata_1_value__52 | tdata_1_value__53; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_27 = tdata_1_value__54 | tdata_1_value__55; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_28 = tdata_1_value__56 | tdata_1_value__57; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_29 = tdata_1_value__58 | tdata_1_value__59; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_30 = tdata_1_value__60 | tdata_1_value__61; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_1_31 = tdata_1_value__62 | tdata_1_value__63; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_0 = tdata_1_value_1_0 | tdata_1_value_1_1; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_1 = tdata_1_value_1_2 | tdata_1_value_1_3; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_2 = tdata_1_value_1_4 | tdata_1_value_1_5; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_3 = tdata_1_value_1_6 | tdata_1_value_1_7; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_4 = tdata_1_value_1_8 | tdata_1_value_1_9; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_5 = tdata_1_value_1_10 | tdata_1_value_1_11; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_6 = tdata_1_value_1_12 | tdata_1_value_1_13; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_7 = tdata_1_value_1_14 | tdata_1_value_1_15; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_8 = tdata_1_value_1_16 | tdata_1_value_1_17; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_9 = tdata_1_value_1_18 | tdata_1_value_1_19; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_10 = tdata_1_value_1_20 | tdata_1_value_1_21; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_11 = tdata_1_value_1_22 | tdata_1_value_1_23; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_12 = tdata_1_value_1_24 | tdata_1_value_1_25; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_13 = tdata_1_value_1_26 | tdata_1_value_1_27; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_14 = tdata_1_value_1_28 | tdata_1_value_1_29; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_2_15 = tdata_1_value_1_30 | tdata_1_value_1_31; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_3_0 = tdata_1_value_2_0 | tdata_1_value_2_1; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_3_1 = tdata_1_value_2_2 | tdata_1_value_2_3; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_3_2 = tdata_1_value_2_4 | tdata_1_value_2_5; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_3_3 = tdata_1_value_2_6 | tdata_1_value_2_7; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_3_4 = tdata_1_value_2_8 | tdata_1_value_2_9; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_3_5 = tdata_1_value_2_10 | tdata_1_value_2_11; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_3_6 = tdata_1_value_2_12 | tdata_1_value_2_13; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_3_7 = tdata_1_value_2_14 | tdata_1_value_2_15; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_4_0 = tdata_1_value_3_0 | tdata_1_value_3_1; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_4_1 = tdata_1_value_3_2 | tdata_1_value_3_3; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_4_2 = tdata_1_value_3_4 | tdata_1_value_3_5; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_4_3 = tdata_1_value_3_6 | tdata_1_value_3_7; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_5_0 = tdata_1_value_4_0 | tdata_1_value_4_1; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_5_1 = tdata_1_value_4_2 | tdata_1_value_4_3; // @[Library.scala 129:37]
- wire [31:0] tdata_1_value_6_0 = tdata_1_value_5_0 | tdata_1_value_5_1; // @[Library.scala 129:37]
- wire [5:0] tidx_2 = {io_transpose_addr[5:4],4'h2}; // @[Cat.scala 31:58]
- wire [31:0] tdata_2_value__0 = 6'h0 == tidx_2 ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__1 = 6'h1 == tidx_2 ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__2 = 6'h2 == tidx_2 ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__3 = 6'h3 == tidx_2 ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__4 = 6'h4 == tidx_2 ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__5 = 6'h5 == tidx_2 ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__6 = 6'h6 == tidx_2 ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__7 = 6'h7 == tidx_2 ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__8 = 6'h8 == tidx_2 ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__9 = 6'h9 == tidx_2 ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__10 = 6'ha == tidx_2 ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__11 = 6'hb == tidx_2 ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__12 = 6'hc == tidx_2 ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__13 = 6'hd == tidx_2 ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__14 = 6'he == tidx_2 ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__15 = 6'hf == tidx_2 ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__16 = 6'h10 == tidx_2 ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__17 = 6'h11 == tidx_2 ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__18 = 6'h12 == tidx_2 ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__19 = 6'h13 == tidx_2 ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__20 = 6'h14 == tidx_2 ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__21 = 6'h15 == tidx_2 ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__22 = 6'h16 == tidx_2 ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__23 = 6'h17 == tidx_2 ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__24 = 6'h18 == tidx_2 ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__25 = 6'h19 == tidx_2 ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__26 = 6'h1a == tidx_2 ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__27 = 6'h1b == tidx_2 ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__28 = 6'h1c == tidx_2 ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__29 = 6'h1d == tidx_2 ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__30 = 6'h1e == tidx_2 ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__31 = 6'h1f == tidx_2 ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__32 = 6'h20 == tidx_2 ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__33 = 6'h21 == tidx_2 ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__34 = 6'h22 == tidx_2 ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__35 = 6'h23 == tidx_2 ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__36 = 6'h24 == tidx_2 ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__37 = 6'h25 == tidx_2 ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__38 = 6'h26 == tidx_2 ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__39 = 6'h27 == tidx_2 ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__40 = 6'h28 == tidx_2 ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__41 = 6'h29 == tidx_2 ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__42 = 6'h2a == tidx_2 ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__43 = 6'h2b == tidx_2 ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__44 = 6'h2c == tidx_2 ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__45 = 6'h2d == tidx_2 ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__46 = 6'h2e == tidx_2 ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__47 = 6'h2f == tidx_2 ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__48 = 6'h30 == tidx_2 ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__49 = 6'h31 == tidx_2 ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__50 = 6'h32 == tidx_2 ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__51 = 6'h33 == tidx_2 ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__52 = 6'h34 == tidx_2 ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__53 = 6'h35 == tidx_2 ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__54 = 6'h36 == tidx_2 ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__55 = 6'h37 == tidx_2 ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__56 = 6'h38 == tidx_2 ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__57 = 6'h39 == tidx_2 ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__58 = 6'h3a == tidx_2 ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__59 = 6'h3b == tidx_2 ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__60 = 6'h3c == tidx_2 ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__61 = 6'h3d == tidx_2 ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__62 = 6'h3e == tidx_2 ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value__63 = 6'h3f == tidx_2 ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_2_value_1_0 = tdata_2_value__0 | tdata_2_value__1; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_1 = tdata_2_value__2 | tdata_2_value__3; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_2 = tdata_2_value__4 | tdata_2_value__5; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_3 = tdata_2_value__6 | tdata_2_value__7; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_4 = tdata_2_value__8 | tdata_2_value__9; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_5 = tdata_2_value__10 | tdata_2_value__11; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_6 = tdata_2_value__12 | tdata_2_value__13; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_7 = tdata_2_value__14 | tdata_2_value__15; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_8 = tdata_2_value__16 | tdata_2_value__17; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_9 = tdata_2_value__18 | tdata_2_value__19; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_10 = tdata_2_value__20 | tdata_2_value__21; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_11 = tdata_2_value__22 | tdata_2_value__23; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_12 = tdata_2_value__24 | tdata_2_value__25; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_13 = tdata_2_value__26 | tdata_2_value__27; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_14 = tdata_2_value__28 | tdata_2_value__29; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_15 = tdata_2_value__30 | tdata_2_value__31; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_16 = tdata_2_value__32 | tdata_2_value__33; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_17 = tdata_2_value__34 | tdata_2_value__35; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_18 = tdata_2_value__36 | tdata_2_value__37; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_19 = tdata_2_value__38 | tdata_2_value__39; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_20 = tdata_2_value__40 | tdata_2_value__41; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_21 = tdata_2_value__42 | tdata_2_value__43; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_22 = tdata_2_value__44 | tdata_2_value__45; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_23 = tdata_2_value__46 | tdata_2_value__47; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_24 = tdata_2_value__48 | tdata_2_value__49; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_25 = tdata_2_value__50 | tdata_2_value__51; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_26 = tdata_2_value__52 | tdata_2_value__53; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_27 = tdata_2_value__54 | tdata_2_value__55; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_28 = tdata_2_value__56 | tdata_2_value__57; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_29 = tdata_2_value__58 | tdata_2_value__59; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_30 = tdata_2_value__60 | tdata_2_value__61; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_1_31 = tdata_2_value__62 | tdata_2_value__63; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_0 = tdata_2_value_1_0 | tdata_2_value_1_1; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_1 = tdata_2_value_1_2 | tdata_2_value_1_3; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_2 = tdata_2_value_1_4 | tdata_2_value_1_5; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_3 = tdata_2_value_1_6 | tdata_2_value_1_7; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_4 = tdata_2_value_1_8 | tdata_2_value_1_9; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_5 = tdata_2_value_1_10 | tdata_2_value_1_11; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_6 = tdata_2_value_1_12 | tdata_2_value_1_13; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_7 = tdata_2_value_1_14 | tdata_2_value_1_15; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_8 = tdata_2_value_1_16 | tdata_2_value_1_17; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_9 = tdata_2_value_1_18 | tdata_2_value_1_19; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_10 = tdata_2_value_1_20 | tdata_2_value_1_21; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_11 = tdata_2_value_1_22 | tdata_2_value_1_23; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_12 = tdata_2_value_1_24 | tdata_2_value_1_25; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_13 = tdata_2_value_1_26 | tdata_2_value_1_27; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_14 = tdata_2_value_1_28 | tdata_2_value_1_29; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_2_15 = tdata_2_value_1_30 | tdata_2_value_1_31; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_3_0 = tdata_2_value_2_0 | tdata_2_value_2_1; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_3_1 = tdata_2_value_2_2 | tdata_2_value_2_3; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_3_2 = tdata_2_value_2_4 | tdata_2_value_2_5; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_3_3 = tdata_2_value_2_6 | tdata_2_value_2_7; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_3_4 = tdata_2_value_2_8 | tdata_2_value_2_9; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_3_5 = tdata_2_value_2_10 | tdata_2_value_2_11; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_3_6 = tdata_2_value_2_12 | tdata_2_value_2_13; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_3_7 = tdata_2_value_2_14 | tdata_2_value_2_15; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_4_0 = tdata_2_value_3_0 | tdata_2_value_3_1; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_4_1 = tdata_2_value_3_2 | tdata_2_value_3_3; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_4_2 = tdata_2_value_3_4 | tdata_2_value_3_5; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_4_3 = tdata_2_value_3_6 | tdata_2_value_3_7; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_5_0 = tdata_2_value_4_0 | tdata_2_value_4_1; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_5_1 = tdata_2_value_4_2 | tdata_2_value_4_3; // @[Library.scala 129:37]
- wire [31:0] tdata_2_value_6_0 = tdata_2_value_5_0 | tdata_2_value_5_1; // @[Library.scala 129:37]
- wire [5:0] tidx_3 = {io_transpose_addr[5:4],4'h3}; // @[Cat.scala 31:58]
- wire [31:0] tdata_3_value__0 = 6'h0 == tidx_3 ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__1 = 6'h1 == tidx_3 ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__2 = 6'h2 == tidx_3 ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__3 = 6'h3 == tidx_3 ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__4 = 6'h4 == tidx_3 ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__5 = 6'h5 == tidx_3 ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__6 = 6'h6 == tidx_3 ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__7 = 6'h7 == tidx_3 ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__8 = 6'h8 == tidx_3 ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__9 = 6'h9 == tidx_3 ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__10 = 6'ha == tidx_3 ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__11 = 6'hb == tidx_3 ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__12 = 6'hc == tidx_3 ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__13 = 6'hd == tidx_3 ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__14 = 6'he == tidx_3 ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__15 = 6'hf == tidx_3 ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__16 = 6'h10 == tidx_3 ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__17 = 6'h11 == tidx_3 ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__18 = 6'h12 == tidx_3 ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__19 = 6'h13 == tidx_3 ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__20 = 6'h14 == tidx_3 ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__21 = 6'h15 == tidx_3 ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__22 = 6'h16 == tidx_3 ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__23 = 6'h17 == tidx_3 ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__24 = 6'h18 == tidx_3 ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__25 = 6'h19 == tidx_3 ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__26 = 6'h1a == tidx_3 ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__27 = 6'h1b == tidx_3 ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__28 = 6'h1c == tidx_3 ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__29 = 6'h1d == tidx_3 ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__30 = 6'h1e == tidx_3 ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__31 = 6'h1f == tidx_3 ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__32 = 6'h20 == tidx_3 ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__33 = 6'h21 == tidx_3 ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__34 = 6'h22 == tidx_3 ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__35 = 6'h23 == tidx_3 ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__36 = 6'h24 == tidx_3 ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__37 = 6'h25 == tidx_3 ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__38 = 6'h26 == tidx_3 ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__39 = 6'h27 == tidx_3 ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__40 = 6'h28 == tidx_3 ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__41 = 6'h29 == tidx_3 ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__42 = 6'h2a == tidx_3 ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__43 = 6'h2b == tidx_3 ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__44 = 6'h2c == tidx_3 ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__45 = 6'h2d == tidx_3 ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__46 = 6'h2e == tidx_3 ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__47 = 6'h2f == tidx_3 ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__48 = 6'h30 == tidx_3 ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__49 = 6'h31 == tidx_3 ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__50 = 6'h32 == tidx_3 ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__51 = 6'h33 == tidx_3 ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__52 = 6'h34 == tidx_3 ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__53 = 6'h35 == tidx_3 ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__54 = 6'h36 == tidx_3 ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__55 = 6'h37 == tidx_3 ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__56 = 6'h38 == tidx_3 ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__57 = 6'h39 == tidx_3 ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__58 = 6'h3a == tidx_3 ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__59 = 6'h3b == tidx_3 ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__60 = 6'h3c == tidx_3 ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__61 = 6'h3d == tidx_3 ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__62 = 6'h3e == tidx_3 ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value__63 = 6'h3f == tidx_3 ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_3_value_1_0 = tdata_3_value__0 | tdata_3_value__1; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_1 = tdata_3_value__2 | tdata_3_value__3; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_2 = tdata_3_value__4 | tdata_3_value__5; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_3 = tdata_3_value__6 | tdata_3_value__7; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_4 = tdata_3_value__8 | tdata_3_value__9; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_5 = tdata_3_value__10 | tdata_3_value__11; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_6 = tdata_3_value__12 | tdata_3_value__13; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_7 = tdata_3_value__14 | tdata_3_value__15; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_8 = tdata_3_value__16 | tdata_3_value__17; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_9 = tdata_3_value__18 | tdata_3_value__19; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_10 = tdata_3_value__20 | tdata_3_value__21; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_11 = tdata_3_value__22 | tdata_3_value__23; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_12 = tdata_3_value__24 | tdata_3_value__25; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_13 = tdata_3_value__26 | tdata_3_value__27; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_14 = tdata_3_value__28 | tdata_3_value__29; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_15 = tdata_3_value__30 | tdata_3_value__31; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_16 = tdata_3_value__32 | tdata_3_value__33; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_17 = tdata_3_value__34 | tdata_3_value__35; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_18 = tdata_3_value__36 | tdata_3_value__37; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_19 = tdata_3_value__38 | tdata_3_value__39; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_20 = tdata_3_value__40 | tdata_3_value__41; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_21 = tdata_3_value__42 | tdata_3_value__43; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_22 = tdata_3_value__44 | tdata_3_value__45; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_23 = tdata_3_value__46 | tdata_3_value__47; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_24 = tdata_3_value__48 | tdata_3_value__49; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_25 = tdata_3_value__50 | tdata_3_value__51; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_26 = tdata_3_value__52 | tdata_3_value__53; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_27 = tdata_3_value__54 | tdata_3_value__55; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_28 = tdata_3_value__56 | tdata_3_value__57; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_29 = tdata_3_value__58 | tdata_3_value__59; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_30 = tdata_3_value__60 | tdata_3_value__61; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_1_31 = tdata_3_value__62 | tdata_3_value__63; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_0 = tdata_3_value_1_0 | tdata_3_value_1_1; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_1 = tdata_3_value_1_2 | tdata_3_value_1_3; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_2 = tdata_3_value_1_4 | tdata_3_value_1_5; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_3 = tdata_3_value_1_6 | tdata_3_value_1_7; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_4 = tdata_3_value_1_8 | tdata_3_value_1_9; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_5 = tdata_3_value_1_10 | tdata_3_value_1_11; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_6 = tdata_3_value_1_12 | tdata_3_value_1_13; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_7 = tdata_3_value_1_14 | tdata_3_value_1_15; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_8 = tdata_3_value_1_16 | tdata_3_value_1_17; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_9 = tdata_3_value_1_18 | tdata_3_value_1_19; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_10 = tdata_3_value_1_20 | tdata_3_value_1_21; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_11 = tdata_3_value_1_22 | tdata_3_value_1_23; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_12 = tdata_3_value_1_24 | tdata_3_value_1_25; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_13 = tdata_3_value_1_26 | tdata_3_value_1_27; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_14 = tdata_3_value_1_28 | tdata_3_value_1_29; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_2_15 = tdata_3_value_1_30 | tdata_3_value_1_31; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_3_0 = tdata_3_value_2_0 | tdata_3_value_2_1; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_3_1 = tdata_3_value_2_2 | tdata_3_value_2_3; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_3_2 = tdata_3_value_2_4 | tdata_3_value_2_5; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_3_3 = tdata_3_value_2_6 | tdata_3_value_2_7; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_3_4 = tdata_3_value_2_8 | tdata_3_value_2_9; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_3_5 = tdata_3_value_2_10 | tdata_3_value_2_11; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_3_6 = tdata_3_value_2_12 | tdata_3_value_2_13; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_3_7 = tdata_3_value_2_14 | tdata_3_value_2_15; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_4_0 = tdata_3_value_3_0 | tdata_3_value_3_1; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_4_1 = tdata_3_value_3_2 | tdata_3_value_3_3; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_4_2 = tdata_3_value_3_4 | tdata_3_value_3_5; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_4_3 = tdata_3_value_3_6 | tdata_3_value_3_7; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_5_0 = tdata_3_value_4_0 | tdata_3_value_4_1; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_5_1 = tdata_3_value_4_2 | tdata_3_value_4_3; // @[Library.scala 129:37]
- wire [31:0] tdata_3_value_6_0 = tdata_3_value_5_0 | tdata_3_value_5_1; // @[Library.scala 129:37]
- wire [5:0] tidx_4 = {io_transpose_addr[5:4],4'h4}; // @[Cat.scala 31:58]
- wire [31:0] tdata_4_value__0 = 6'h0 == tidx_4 ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__1 = 6'h1 == tidx_4 ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__2 = 6'h2 == tidx_4 ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__3 = 6'h3 == tidx_4 ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__4 = 6'h4 == tidx_4 ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__5 = 6'h5 == tidx_4 ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__6 = 6'h6 == tidx_4 ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__7 = 6'h7 == tidx_4 ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__8 = 6'h8 == tidx_4 ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__9 = 6'h9 == tidx_4 ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__10 = 6'ha == tidx_4 ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__11 = 6'hb == tidx_4 ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__12 = 6'hc == tidx_4 ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__13 = 6'hd == tidx_4 ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__14 = 6'he == tidx_4 ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__15 = 6'hf == tidx_4 ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__16 = 6'h10 == tidx_4 ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__17 = 6'h11 == tidx_4 ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__18 = 6'h12 == tidx_4 ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__19 = 6'h13 == tidx_4 ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__20 = 6'h14 == tidx_4 ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__21 = 6'h15 == tidx_4 ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__22 = 6'h16 == tidx_4 ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__23 = 6'h17 == tidx_4 ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__24 = 6'h18 == tidx_4 ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__25 = 6'h19 == tidx_4 ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__26 = 6'h1a == tidx_4 ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__27 = 6'h1b == tidx_4 ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__28 = 6'h1c == tidx_4 ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__29 = 6'h1d == tidx_4 ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__30 = 6'h1e == tidx_4 ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__31 = 6'h1f == tidx_4 ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__32 = 6'h20 == tidx_4 ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__33 = 6'h21 == tidx_4 ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__34 = 6'h22 == tidx_4 ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__35 = 6'h23 == tidx_4 ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__36 = 6'h24 == tidx_4 ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__37 = 6'h25 == tidx_4 ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__38 = 6'h26 == tidx_4 ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__39 = 6'h27 == tidx_4 ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__40 = 6'h28 == tidx_4 ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__41 = 6'h29 == tidx_4 ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__42 = 6'h2a == tidx_4 ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__43 = 6'h2b == tidx_4 ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__44 = 6'h2c == tidx_4 ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__45 = 6'h2d == tidx_4 ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__46 = 6'h2e == tidx_4 ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__47 = 6'h2f == tidx_4 ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__48 = 6'h30 == tidx_4 ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__49 = 6'h31 == tidx_4 ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__50 = 6'h32 == tidx_4 ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__51 = 6'h33 == tidx_4 ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__52 = 6'h34 == tidx_4 ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__53 = 6'h35 == tidx_4 ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__54 = 6'h36 == tidx_4 ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__55 = 6'h37 == tidx_4 ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__56 = 6'h38 == tidx_4 ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__57 = 6'h39 == tidx_4 ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__58 = 6'h3a == tidx_4 ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__59 = 6'h3b == tidx_4 ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__60 = 6'h3c == tidx_4 ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__61 = 6'h3d == tidx_4 ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__62 = 6'h3e == tidx_4 ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value__63 = 6'h3f == tidx_4 ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_4_value_1_0 = tdata_4_value__0 | tdata_4_value__1; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_1 = tdata_4_value__2 | tdata_4_value__3; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_2 = tdata_4_value__4 | tdata_4_value__5; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_3 = tdata_4_value__6 | tdata_4_value__7; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_4 = tdata_4_value__8 | tdata_4_value__9; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_5 = tdata_4_value__10 | tdata_4_value__11; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_6 = tdata_4_value__12 | tdata_4_value__13; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_7 = tdata_4_value__14 | tdata_4_value__15; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_8 = tdata_4_value__16 | tdata_4_value__17; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_9 = tdata_4_value__18 | tdata_4_value__19; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_10 = tdata_4_value__20 | tdata_4_value__21; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_11 = tdata_4_value__22 | tdata_4_value__23; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_12 = tdata_4_value__24 | tdata_4_value__25; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_13 = tdata_4_value__26 | tdata_4_value__27; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_14 = tdata_4_value__28 | tdata_4_value__29; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_15 = tdata_4_value__30 | tdata_4_value__31; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_16 = tdata_4_value__32 | tdata_4_value__33; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_17 = tdata_4_value__34 | tdata_4_value__35; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_18 = tdata_4_value__36 | tdata_4_value__37; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_19 = tdata_4_value__38 | tdata_4_value__39; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_20 = tdata_4_value__40 | tdata_4_value__41; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_21 = tdata_4_value__42 | tdata_4_value__43; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_22 = tdata_4_value__44 | tdata_4_value__45; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_23 = tdata_4_value__46 | tdata_4_value__47; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_24 = tdata_4_value__48 | tdata_4_value__49; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_25 = tdata_4_value__50 | tdata_4_value__51; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_26 = tdata_4_value__52 | tdata_4_value__53; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_27 = tdata_4_value__54 | tdata_4_value__55; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_28 = tdata_4_value__56 | tdata_4_value__57; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_29 = tdata_4_value__58 | tdata_4_value__59; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_30 = tdata_4_value__60 | tdata_4_value__61; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_1_31 = tdata_4_value__62 | tdata_4_value__63; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_0 = tdata_4_value_1_0 | tdata_4_value_1_1; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_1 = tdata_4_value_1_2 | tdata_4_value_1_3; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_2 = tdata_4_value_1_4 | tdata_4_value_1_5; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_3 = tdata_4_value_1_6 | tdata_4_value_1_7; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_4 = tdata_4_value_1_8 | tdata_4_value_1_9; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_5 = tdata_4_value_1_10 | tdata_4_value_1_11; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_6 = tdata_4_value_1_12 | tdata_4_value_1_13; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_7 = tdata_4_value_1_14 | tdata_4_value_1_15; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_8 = tdata_4_value_1_16 | tdata_4_value_1_17; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_9 = tdata_4_value_1_18 | tdata_4_value_1_19; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_10 = tdata_4_value_1_20 | tdata_4_value_1_21; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_11 = tdata_4_value_1_22 | tdata_4_value_1_23; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_12 = tdata_4_value_1_24 | tdata_4_value_1_25; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_13 = tdata_4_value_1_26 | tdata_4_value_1_27; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_14 = tdata_4_value_1_28 | tdata_4_value_1_29; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_2_15 = tdata_4_value_1_30 | tdata_4_value_1_31; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_3_0 = tdata_4_value_2_0 | tdata_4_value_2_1; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_3_1 = tdata_4_value_2_2 | tdata_4_value_2_3; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_3_2 = tdata_4_value_2_4 | tdata_4_value_2_5; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_3_3 = tdata_4_value_2_6 | tdata_4_value_2_7; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_3_4 = tdata_4_value_2_8 | tdata_4_value_2_9; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_3_5 = tdata_4_value_2_10 | tdata_4_value_2_11; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_3_6 = tdata_4_value_2_12 | tdata_4_value_2_13; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_3_7 = tdata_4_value_2_14 | tdata_4_value_2_15; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_4_0 = tdata_4_value_3_0 | tdata_4_value_3_1; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_4_1 = tdata_4_value_3_2 | tdata_4_value_3_3; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_4_2 = tdata_4_value_3_4 | tdata_4_value_3_5; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_4_3 = tdata_4_value_3_6 | tdata_4_value_3_7; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_5_0 = tdata_4_value_4_0 | tdata_4_value_4_1; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_5_1 = tdata_4_value_4_2 | tdata_4_value_4_3; // @[Library.scala 129:37]
- wire [31:0] tdata_4_value_6_0 = tdata_4_value_5_0 | tdata_4_value_5_1; // @[Library.scala 129:37]
- wire [5:0] tidx_5 = {io_transpose_addr[5:4],4'h5}; // @[Cat.scala 31:58]
- wire [31:0] tdata_5_value__0 = 6'h0 == tidx_5 ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__1 = 6'h1 == tidx_5 ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__2 = 6'h2 == tidx_5 ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__3 = 6'h3 == tidx_5 ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__4 = 6'h4 == tidx_5 ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__5 = 6'h5 == tidx_5 ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__6 = 6'h6 == tidx_5 ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__7 = 6'h7 == tidx_5 ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__8 = 6'h8 == tidx_5 ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__9 = 6'h9 == tidx_5 ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__10 = 6'ha == tidx_5 ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__11 = 6'hb == tidx_5 ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__12 = 6'hc == tidx_5 ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__13 = 6'hd == tidx_5 ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__14 = 6'he == tidx_5 ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__15 = 6'hf == tidx_5 ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__16 = 6'h10 == tidx_5 ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__17 = 6'h11 == tidx_5 ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__18 = 6'h12 == tidx_5 ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__19 = 6'h13 == tidx_5 ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__20 = 6'h14 == tidx_5 ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__21 = 6'h15 == tidx_5 ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__22 = 6'h16 == tidx_5 ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__23 = 6'h17 == tidx_5 ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__24 = 6'h18 == tidx_5 ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__25 = 6'h19 == tidx_5 ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__26 = 6'h1a == tidx_5 ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__27 = 6'h1b == tidx_5 ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__28 = 6'h1c == tidx_5 ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__29 = 6'h1d == tidx_5 ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__30 = 6'h1e == tidx_5 ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__31 = 6'h1f == tidx_5 ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__32 = 6'h20 == tidx_5 ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__33 = 6'h21 == tidx_5 ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__34 = 6'h22 == tidx_5 ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__35 = 6'h23 == tidx_5 ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__36 = 6'h24 == tidx_5 ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__37 = 6'h25 == tidx_5 ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__38 = 6'h26 == tidx_5 ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__39 = 6'h27 == tidx_5 ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__40 = 6'h28 == tidx_5 ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__41 = 6'h29 == tidx_5 ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__42 = 6'h2a == tidx_5 ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__43 = 6'h2b == tidx_5 ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__44 = 6'h2c == tidx_5 ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__45 = 6'h2d == tidx_5 ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__46 = 6'h2e == tidx_5 ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__47 = 6'h2f == tidx_5 ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__48 = 6'h30 == tidx_5 ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__49 = 6'h31 == tidx_5 ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__50 = 6'h32 == tidx_5 ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__51 = 6'h33 == tidx_5 ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__52 = 6'h34 == tidx_5 ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__53 = 6'h35 == tidx_5 ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__54 = 6'h36 == tidx_5 ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__55 = 6'h37 == tidx_5 ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__56 = 6'h38 == tidx_5 ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__57 = 6'h39 == tidx_5 ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__58 = 6'h3a == tidx_5 ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__59 = 6'h3b == tidx_5 ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__60 = 6'h3c == tidx_5 ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__61 = 6'h3d == tidx_5 ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__62 = 6'h3e == tidx_5 ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value__63 = 6'h3f == tidx_5 ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_5_value_1_0 = tdata_5_value__0 | tdata_5_value__1; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_1 = tdata_5_value__2 | tdata_5_value__3; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_2 = tdata_5_value__4 | tdata_5_value__5; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_3 = tdata_5_value__6 | tdata_5_value__7; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_4 = tdata_5_value__8 | tdata_5_value__9; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_5 = tdata_5_value__10 | tdata_5_value__11; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_6 = tdata_5_value__12 | tdata_5_value__13; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_7 = tdata_5_value__14 | tdata_5_value__15; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_8 = tdata_5_value__16 | tdata_5_value__17; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_9 = tdata_5_value__18 | tdata_5_value__19; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_10 = tdata_5_value__20 | tdata_5_value__21; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_11 = tdata_5_value__22 | tdata_5_value__23; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_12 = tdata_5_value__24 | tdata_5_value__25; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_13 = tdata_5_value__26 | tdata_5_value__27; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_14 = tdata_5_value__28 | tdata_5_value__29; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_15 = tdata_5_value__30 | tdata_5_value__31; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_16 = tdata_5_value__32 | tdata_5_value__33; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_17 = tdata_5_value__34 | tdata_5_value__35; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_18 = tdata_5_value__36 | tdata_5_value__37; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_19 = tdata_5_value__38 | tdata_5_value__39; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_20 = tdata_5_value__40 | tdata_5_value__41; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_21 = tdata_5_value__42 | tdata_5_value__43; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_22 = tdata_5_value__44 | tdata_5_value__45; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_23 = tdata_5_value__46 | tdata_5_value__47; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_24 = tdata_5_value__48 | tdata_5_value__49; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_25 = tdata_5_value__50 | tdata_5_value__51; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_26 = tdata_5_value__52 | tdata_5_value__53; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_27 = tdata_5_value__54 | tdata_5_value__55; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_28 = tdata_5_value__56 | tdata_5_value__57; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_29 = tdata_5_value__58 | tdata_5_value__59; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_30 = tdata_5_value__60 | tdata_5_value__61; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_1_31 = tdata_5_value__62 | tdata_5_value__63; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_0 = tdata_5_value_1_0 | tdata_5_value_1_1; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_1 = tdata_5_value_1_2 | tdata_5_value_1_3; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_2 = tdata_5_value_1_4 | tdata_5_value_1_5; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_3 = tdata_5_value_1_6 | tdata_5_value_1_7; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_4 = tdata_5_value_1_8 | tdata_5_value_1_9; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_5 = tdata_5_value_1_10 | tdata_5_value_1_11; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_6 = tdata_5_value_1_12 | tdata_5_value_1_13; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_7 = tdata_5_value_1_14 | tdata_5_value_1_15; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_8 = tdata_5_value_1_16 | tdata_5_value_1_17; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_9 = tdata_5_value_1_18 | tdata_5_value_1_19; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_10 = tdata_5_value_1_20 | tdata_5_value_1_21; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_11 = tdata_5_value_1_22 | tdata_5_value_1_23; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_12 = tdata_5_value_1_24 | tdata_5_value_1_25; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_13 = tdata_5_value_1_26 | tdata_5_value_1_27; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_14 = tdata_5_value_1_28 | tdata_5_value_1_29; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_2_15 = tdata_5_value_1_30 | tdata_5_value_1_31; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_3_0 = tdata_5_value_2_0 | tdata_5_value_2_1; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_3_1 = tdata_5_value_2_2 | tdata_5_value_2_3; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_3_2 = tdata_5_value_2_4 | tdata_5_value_2_5; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_3_3 = tdata_5_value_2_6 | tdata_5_value_2_7; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_3_4 = tdata_5_value_2_8 | tdata_5_value_2_9; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_3_5 = tdata_5_value_2_10 | tdata_5_value_2_11; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_3_6 = tdata_5_value_2_12 | tdata_5_value_2_13; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_3_7 = tdata_5_value_2_14 | tdata_5_value_2_15; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_4_0 = tdata_5_value_3_0 | tdata_5_value_3_1; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_4_1 = tdata_5_value_3_2 | tdata_5_value_3_3; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_4_2 = tdata_5_value_3_4 | tdata_5_value_3_5; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_4_3 = tdata_5_value_3_6 | tdata_5_value_3_7; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_5_0 = tdata_5_value_4_0 | tdata_5_value_4_1; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_5_1 = tdata_5_value_4_2 | tdata_5_value_4_3; // @[Library.scala 129:37]
- wire [31:0] tdata_5_value_6_0 = tdata_5_value_5_0 | tdata_5_value_5_1; // @[Library.scala 129:37]
- wire [5:0] tidx_6 = {io_transpose_addr[5:4],4'h6}; // @[Cat.scala 31:58]
- wire [31:0] tdata_6_value__0 = 6'h0 == tidx_6 ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__1 = 6'h1 == tidx_6 ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__2 = 6'h2 == tidx_6 ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__3 = 6'h3 == tidx_6 ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__4 = 6'h4 == tidx_6 ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__5 = 6'h5 == tidx_6 ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__6 = 6'h6 == tidx_6 ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__7 = 6'h7 == tidx_6 ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__8 = 6'h8 == tidx_6 ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__9 = 6'h9 == tidx_6 ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__10 = 6'ha == tidx_6 ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__11 = 6'hb == tidx_6 ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__12 = 6'hc == tidx_6 ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__13 = 6'hd == tidx_6 ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__14 = 6'he == tidx_6 ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__15 = 6'hf == tidx_6 ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__16 = 6'h10 == tidx_6 ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__17 = 6'h11 == tidx_6 ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__18 = 6'h12 == tidx_6 ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__19 = 6'h13 == tidx_6 ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__20 = 6'h14 == tidx_6 ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__21 = 6'h15 == tidx_6 ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__22 = 6'h16 == tidx_6 ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__23 = 6'h17 == tidx_6 ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__24 = 6'h18 == tidx_6 ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__25 = 6'h19 == tidx_6 ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__26 = 6'h1a == tidx_6 ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__27 = 6'h1b == tidx_6 ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__28 = 6'h1c == tidx_6 ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__29 = 6'h1d == tidx_6 ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__30 = 6'h1e == tidx_6 ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__31 = 6'h1f == tidx_6 ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__32 = 6'h20 == tidx_6 ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__33 = 6'h21 == tidx_6 ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__34 = 6'h22 == tidx_6 ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__35 = 6'h23 == tidx_6 ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__36 = 6'h24 == tidx_6 ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__37 = 6'h25 == tidx_6 ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__38 = 6'h26 == tidx_6 ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__39 = 6'h27 == tidx_6 ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__40 = 6'h28 == tidx_6 ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__41 = 6'h29 == tidx_6 ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__42 = 6'h2a == tidx_6 ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__43 = 6'h2b == tidx_6 ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__44 = 6'h2c == tidx_6 ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__45 = 6'h2d == tidx_6 ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__46 = 6'h2e == tidx_6 ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__47 = 6'h2f == tidx_6 ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__48 = 6'h30 == tidx_6 ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__49 = 6'h31 == tidx_6 ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__50 = 6'h32 == tidx_6 ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__51 = 6'h33 == tidx_6 ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__52 = 6'h34 == tidx_6 ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__53 = 6'h35 == tidx_6 ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__54 = 6'h36 == tidx_6 ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__55 = 6'h37 == tidx_6 ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__56 = 6'h38 == tidx_6 ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__57 = 6'h39 == tidx_6 ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__58 = 6'h3a == tidx_6 ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__59 = 6'h3b == tidx_6 ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__60 = 6'h3c == tidx_6 ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__61 = 6'h3d == tidx_6 ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__62 = 6'h3e == tidx_6 ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value__63 = 6'h3f == tidx_6 ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_6_value_1_0 = tdata_6_value__0 | tdata_6_value__1; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_1 = tdata_6_value__2 | tdata_6_value__3; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_2 = tdata_6_value__4 | tdata_6_value__5; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_3 = tdata_6_value__6 | tdata_6_value__7; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_4 = tdata_6_value__8 | tdata_6_value__9; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_5 = tdata_6_value__10 | tdata_6_value__11; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_6 = tdata_6_value__12 | tdata_6_value__13; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_7 = tdata_6_value__14 | tdata_6_value__15; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_8 = tdata_6_value__16 | tdata_6_value__17; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_9 = tdata_6_value__18 | tdata_6_value__19; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_10 = tdata_6_value__20 | tdata_6_value__21; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_11 = tdata_6_value__22 | tdata_6_value__23; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_12 = tdata_6_value__24 | tdata_6_value__25; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_13 = tdata_6_value__26 | tdata_6_value__27; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_14 = tdata_6_value__28 | tdata_6_value__29; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_15 = tdata_6_value__30 | tdata_6_value__31; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_16 = tdata_6_value__32 | tdata_6_value__33; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_17 = tdata_6_value__34 | tdata_6_value__35; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_18 = tdata_6_value__36 | tdata_6_value__37; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_19 = tdata_6_value__38 | tdata_6_value__39; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_20 = tdata_6_value__40 | tdata_6_value__41; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_21 = tdata_6_value__42 | tdata_6_value__43; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_22 = tdata_6_value__44 | tdata_6_value__45; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_23 = tdata_6_value__46 | tdata_6_value__47; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_24 = tdata_6_value__48 | tdata_6_value__49; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_25 = tdata_6_value__50 | tdata_6_value__51; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_26 = tdata_6_value__52 | tdata_6_value__53; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_27 = tdata_6_value__54 | tdata_6_value__55; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_28 = tdata_6_value__56 | tdata_6_value__57; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_29 = tdata_6_value__58 | tdata_6_value__59; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_30 = tdata_6_value__60 | tdata_6_value__61; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_1_31 = tdata_6_value__62 | tdata_6_value__63; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_0 = tdata_6_value_1_0 | tdata_6_value_1_1; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_1 = tdata_6_value_1_2 | tdata_6_value_1_3; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_2 = tdata_6_value_1_4 | tdata_6_value_1_5; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_3 = tdata_6_value_1_6 | tdata_6_value_1_7; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_4 = tdata_6_value_1_8 | tdata_6_value_1_9; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_5 = tdata_6_value_1_10 | tdata_6_value_1_11; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_6 = tdata_6_value_1_12 | tdata_6_value_1_13; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_7 = tdata_6_value_1_14 | tdata_6_value_1_15; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_8 = tdata_6_value_1_16 | tdata_6_value_1_17; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_9 = tdata_6_value_1_18 | tdata_6_value_1_19; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_10 = tdata_6_value_1_20 | tdata_6_value_1_21; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_11 = tdata_6_value_1_22 | tdata_6_value_1_23; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_12 = tdata_6_value_1_24 | tdata_6_value_1_25; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_13 = tdata_6_value_1_26 | tdata_6_value_1_27; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_14 = tdata_6_value_1_28 | tdata_6_value_1_29; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_2_15 = tdata_6_value_1_30 | tdata_6_value_1_31; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_3_0 = tdata_6_value_2_0 | tdata_6_value_2_1; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_3_1 = tdata_6_value_2_2 | tdata_6_value_2_3; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_3_2 = tdata_6_value_2_4 | tdata_6_value_2_5; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_3_3 = tdata_6_value_2_6 | tdata_6_value_2_7; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_3_4 = tdata_6_value_2_8 | tdata_6_value_2_9; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_3_5 = tdata_6_value_2_10 | tdata_6_value_2_11; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_3_6 = tdata_6_value_2_12 | tdata_6_value_2_13; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_3_7 = tdata_6_value_2_14 | tdata_6_value_2_15; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_4_0 = tdata_6_value_3_0 | tdata_6_value_3_1; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_4_1 = tdata_6_value_3_2 | tdata_6_value_3_3; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_4_2 = tdata_6_value_3_4 | tdata_6_value_3_5; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_4_3 = tdata_6_value_3_6 | tdata_6_value_3_7; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_5_0 = tdata_6_value_4_0 | tdata_6_value_4_1; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_5_1 = tdata_6_value_4_2 | tdata_6_value_4_3; // @[Library.scala 129:37]
- wire [31:0] tdata_6_value_6_0 = tdata_6_value_5_0 | tdata_6_value_5_1; // @[Library.scala 129:37]
- wire [5:0] tidx_7 = {io_transpose_addr[5:4],4'h7}; // @[Cat.scala 31:58]
- wire [31:0] tdata_7_value__0 = 6'h0 == tidx_7 ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__1 = 6'h1 == tidx_7 ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__2 = 6'h2 == tidx_7 ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__3 = 6'h3 == tidx_7 ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__4 = 6'h4 == tidx_7 ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__5 = 6'h5 == tidx_7 ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__6 = 6'h6 == tidx_7 ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__7 = 6'h7 == tidx_7 ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__8 = 6'h8 == tidx_7 ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__9 = 6'h9 == tidx_7 ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__10 = 6'ha == tidx_7 ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__11 = 6'hb == tidx_7 ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__12 = 6'hc == tidx_7 ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__13 = 6'hd == tidx_7 ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__14 = 6'he == tidx_7 ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__15 = 6'hf == tidx_7 ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__16 = 6'h10 == tidx_7 ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__17 = 6'h11 == tidx_7 ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__18 = 6'h12 == tidx_7 ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__19 = 6'h13 == tidx_7 ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__20 = 6'h14 == tidx_7 ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__21 = 6'h15 == tidx_7 ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__22 = 6'h16 == tidx_7 ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__23 = 6'h17 == tidx_7 ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__24 = 6'h18 == tidx_7 ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__25 = 6'h19 == tidx_7 ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__26 = 6'h1a == tidx_7 ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__27 = 6'h1b == tidx_7 ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__28 = 6'h1c == tidx_7 ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__29 = 6'h1d == tidx_7 ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__30 = 6'h1e == tidx_7 ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__31 = 6'h1f == tidx_7 ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__32 = 6'h20 == tidx_7 ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__33 = 6'h21 == tidx_7 ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__34 = 6'h22 == tidx_7 ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__35 = 6'h23 == tidx_7 ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__36 = 6'h24 == tidx_7 ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__37 = 6'h25 == tidx_7 ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__38 = 6'h26 == tidx_7 ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__39 = 6'h27 == tidx_7 ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__40 = 6'h28 == tidx_7 ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__41 = 6'h29 == tidx_7 ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__42 = 6'h2a == tidx_7 ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__43 = 6'h2b == tidx_7 ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__44 = 6'h2c == tidx_7 ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__45 = 6'h2d == tidx_7 ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__46 = 6'h2e == tidx_7 ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__47 = 6'h2f == tidx_7 ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__48 = 6'h30 == tidx_7 ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__49 = 6'h31 == tidx_7 ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__50 = 6'h32 == tidx_7 ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__51 = 6'h33 == tidx_7 ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__52 = 6'h34 == tidx_7 ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__53 = 6'h35 == tidx_7 ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__54 = 6'h36 == tidx_7 ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__55 = 6'h37 == tidx_7 ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__56 = 6'h38 == tidx_7 ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__57 = 6'h39 == tidx_7 ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__58 = 6'h3a == tidx_7 ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__59 = 6'h3b == tidx_7 ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__60 = 6'h3c == tidx_7 ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__61 = 6'h3d == tidx_7 ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__62 = 6'h3e == tidx_7 ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value__63 = 6'h3f == tidx_7 ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] tdata_7_value_1_0 = tdata_7_value__0 | tdata_7_value__1; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_1 = tdata_7_value__2 | tdata_7_value__3; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_2 = tdata_7_value__4 | tdata_7_value__5; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_3 = tdata_7_value__6 | tdata_7_value__7; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_4 = tdata_7_value__8 | tdata_7_value__9; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_5 = tdata_7_value__10 | tdata_7_value__11; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_6 = tdata_7_value__12 | tdata_7_value__13; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_7 = tdata_7_value__14 | tdata_7_value__15; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_8 = tdata_7_value__16 | tdata_7_value__17; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_9 = tdata_7_value__18 | tdata_7_value__19; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_10 = tdata_7_value__20 | tdata_7_value__21; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_11 = tdata_7_value__22 | tdata_7_value__23; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_12 = tdata_7_value__24 | tdata_7_value__25; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_13 = tdata_7_value__26 | tdata_7_value__27; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_14 = tdata_7_value__28 | tdata_7_value__29; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_15 = tdata_7_value__30 | tdata_7_value__31; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_16 = tdata_7_value__32 | tdata_7_value__33; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_17 = tdata_7_value__34 | tdata_7_value__35; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_18 = tdata_7_value__36 | tdata_7_value__37; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_19 = tdata_7_value__38 | tdata_7_value__39; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_20 = tdata_7_value__40 | tdata_7_value__41; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_21 = tdata_7_value__42 | tdata_7_value__43; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_22 = tdata_7_value__44 | tdata_7_value__45; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_23 = tdata_7_value__46 | tdata_7_value__47; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_24 = tdata_7_value__48 | tdata_7_value__49; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_25 = tdata_7_value__50 | tdata_7_value__51; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_26 = tdata_7_value__52 | tdata_7_value__53; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_27 = tdata_7_value__54 | tdata_7_value__55; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_28 = tdata_7_value__56 | tdata_7_value__57; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_29 = tdata_7_value__58 | tdata_7_value__59; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_30 = tdata_7_value__60 | tdata_7_value__61; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_1_31 = tdata_7_value__62 | tdata_7_value__63; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_0 = tdata_7_value_1_0 | tdata_7_value_1_1; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_1 = tdata_7_value_1_2 | tdata_7_value_1_3; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_2 = tdata_7_value_1_4 | tdata_7_value_1_5; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_3 = tdata_7_value_1_6 | tdata_7_value_1_7; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_4 = tdata_7_value_1_8 | tdata_7_value_1_9; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_5 = tdata_7_value_1_10 | tdata_7_value_1_11; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_6 = tdata_7_value_1_12 | tdata_7_value_1_13; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_7 = tdata_7_value_1_14 | tdata_7_value_1_15; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_8 = tdata_7_value_1_16 | tdata_7_value_1_17; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_9 = tdata_7_value_1_18 | tdata_7_value_1_19; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_10 = tdata_7_value_1_20 | tdata_7_value_1_21; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_11 = tdata_7_value_1_22 | tdata_7_value_1_23; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_12 = tdata_7_value_1_24 | tdata_7_value_1_25; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_13 = tdata_7_value_1_26 | tdata_7_value_1_27; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_14 = tdata_7_value_1_28 | tdata_7_value_1_29; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_2_15 = tdata_7_value_1_30 | tdata_7_value_1_31; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_3_0 = tdata_7_value_2_0 | tdata_7_value_2_1; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_3_1 = tdata_7_value_2_2 | tdata_7_value_2_3; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_3_2 = tdata_7_value_2_4 | tdata_7_value_2_5; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_3_3 = tdata_7_value_2_6 | tdata_7_value_2_7; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_3_4 = tdata_7_value_2_8 | tdata_7_value_2_9; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_3_5 = tdata_7_value_2_10 | tdata_7_value_2_11; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_3_6 = tdata_7_value_2_12 | tdata_7_value_2_13; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_3_7 = tdata_7_value_2_14 | tdata_7_value_2_15; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_4_0 = tdata_7_value_3_0 | tdata_7_value_3_1; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_4_1 = tdata_7_value_3_2 | tdata_7_value_3_3; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_4_2 = tdata_7_value_3_4 | tdata_7_value_3_5; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_4_3 = tdata_7_value_3_6 | tdata_7_value_3_7; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_5_0 = tdata_7_value_4_0 | tdata_7_value_4_1; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_5_1 = tdata_7_value_4_2 | tdata_7_value_4_3; // @[Library.scala 129:37]
- wire [31:0] tdata_7_value_6_0 = tdata_7_value_5_0 | tdata_7_value_5_1; // @[Library.scala 129:37]
- wire [127:0] io_transpose_data_lo = {tdata_3_value_6_0,tdata_2_value_6_0,tdata_1_value_6_0,tdata_0_value_6_0}; // @[VRegfileSegment.scala 74:30]
- wire [127:0] io_transpose_data_hi = {tdata_7_value_6_0,tdata_6_value_6_0,tdata_5_value_6_0,tdata_4_value_6_0}; // @[VRegfileSegment.scala 74:30]
- wire _T_3 = ~reset; // @[VRegfileSegment.scala 75:9]
- wire [31:0] io_internal_data_value__0 = 6'h0 == io_internal_addr ? vreg_0 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__1 = 6'h1 == io_internal_addr ? vreg_1 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__2 = 6'h2 == io_internal_addr ? vreg_2 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__3 = 6'h3 == io_internal_addr ? vreg_3 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__4 = 6'h4 == io_internal_addr ? vreg_4 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__5 = 6'h5 == io_internal_addr ? vreg_5 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__6 = 6'h6 == io_internal_addr ? vreg_6 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__7 = 6'h7 == io_internal_addr ? vreg_7 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__8 = 6'h8 == io_internal_addr ? vreg_8 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__9 = 6'h9 == io_internal_addr ? vreg_9 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__10 = 6'ha == io_internal_addr ? vreg_10 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__11 = 6'hb == io_internal_addr ? vreg_11 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__12 = 6'hc == io_internal_addr ? vreg_12 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__13 = 6'hd == io_internal_addr ? vreg_13 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__14 = 6'he == io_internal_addr ? vreg_14 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__15 = 6'hf == io_internal_addr ? vreg_15 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__16 = 6'h10 == io_internal_addr ? vreg_16 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__17 = 6'h11 == io_internal_addr ? vreg_17 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__18 = 6'h12 == io_internal_addr ? vreg_18 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__19 = 6'h13 == io_internal_addr ? vreg_19 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__20 = 6'h14 == io_internal_addr ? vreg_20 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__21 = 6'h15 == io_internal_addr ? vreg_21 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__22 = 6'h16 == io_internal_addr ? vreg_22 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__23 = 6'h17 == io_internal_addr ? vreg_23 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__24 = 6'h18 == io_internal_addr ? vreg_24 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__25 = 6'h19 == io_internal_addr ? vreg_25 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__26 = 6'h1a == io_internal_addr ? vreg_26 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__27 = 6'h1b == io_internal_addr ? vreg_27 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__28 = 6'h1c == io_internal_addr ? vreg_28 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__29 = 6'h1d == io_internal_addr ? vreg_29 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__30 = 6'h1e == io_internal_addr ? vreg_30 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__31 = 6'h1f == io_internal_addr ? vreg_31 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__32 = 6'h20 == io_internal_addr ? vreg_32 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__33 = 6'h21 == io_internal_addr ? vreg_33 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__34 = 6'h22 == io_internal_addr ? vreg_34 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__35 = 6'h23 == io_internal_addr ? vreg_35 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__36 = 6'h24 == io_internal_addr ? vreg_36 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__37 = 6'h25 == io_internal_addr ? vreg_37 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__38 = 6'h26 == io_internal_addr ? vreg_38 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__39 = 6'h27 == io_internal_addr ? vreg_39 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__40 = 6'h28 == io_internal_addr ? vreg_40 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__41 = 6'h29 == io_internal_addr ? vreg_41 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__42 = 6'h2a == io_internal_addr ? vreg_42 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__43 = 6'h2b == io_internal_addr ? vreg_43 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__44 = 6'h2c == io_internal_addr ? vreg_44 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__45 = 6'h2d == io_internal_addr ? vreg_45 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__46 = 6'h2e == io_internal_addr ? vreg_46 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__47 = 6'h2f == io_internal_addr ? vreg_47 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__48 = 6'h30 == io_internal_addr ? vreg_48 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__49 = 6'h31 == io_internal_addr ? vreg_49 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__50 = 6'h32 == io_internal_addr ? vreg_50 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__51 = 6'h33 == io_internal_addr ? vreg_51 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__52 = 6'h34 == io_internal_addr ? vreg_52 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__53 = 6'h35 == io_internal_addr ? vreg_53 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__54 = 6'h36 == io_internal_addr ? vreg_54 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__55 = 6'h37 == io_internal_addr ? vreg_55 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__56 = 6'h38 == io_internal_addr ? vreg_56 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__57 = 6'h39 == io_internal_addr ? vreg_57 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__58 = 6'h3a == io_internal_addr ? vreg_58 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__59 = 6'h3b == io_internal_addr ? vreg_59 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__60 = 6'h3c == io_internal_addr ? vreg_60 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__61 = 6'h3d == io_internal_addr ? vreg_61 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__62 = 6'h3e == io_internal_addr ? vreg_62 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value__63 = 6'h3f == io_internal_addr ? vreg_63 : 32'h0; // @[Library.scala 115:22]
- wire [31:0] io_internal_data_value_1_0 = io_internal_data_value__0 | io_internal_data_value__1; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_1 = io_internal_data_value__2 | io_internal_data_value__3; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_2 = io_internal_data_value__4 | io_internal_data_value__5; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_3 = io_internal_data_value__6 | io_internal_data_value__7; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_4 = io_internal_data_value__8 | io_internal_data_value__9; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_5 = io_internal_data_value__10 | io_internal_data_value__11; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_6 = io_internal_data_value__12 | io_internal_data_value__13; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_7 = io_internal_data_value__14 | io_internal_data_value__15; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_8 = io_internal_data_value__16 | io_internal_data_value__17; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_9 = io_internal_data_value__18 | io_internal_data_value__19; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_10 = io_internal_data_value__20 | io_internal_data_value__21; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_11 = io_internal_data_value__22 | io_internal_data_value__23; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_12 = io_internal_data_value__24 | io_internal_data_value__25; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_13 = io_internal_data_value__26 | io_internal_data_value__27; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_14 = io_internal_data_value__28 | io_internal_data_value__29; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_15 = io_internal_data_value__30 | io_internal_data_value__31; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_16 = io_internal_data_value__32 | io_internal_data_value__33; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_17 = io_internal_data_value__34 | io_internal_data_value__35; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_18 = io_internal_data_value__36 | io_internal_data_value__37; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_19 = io_internal_data_value__38 | io_internal_data_value__39; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_20 = io_internal_data_value__40 | io_internal_data_value__41; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_21 = io_internal_data_value__42 | io_internal_data_value__43; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_22 = io_internal_data_value__44 | io_internal_data_value__45; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_23 = io_internal_data_value__46 | io_internal_data_value__47; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_24 = io_internal_data_value__48 | io_internal_data_value__49; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_25 = io_internal_data_value__50 | io_internal_data_value__51; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_26 = io_internal_data_value__52 | io_internal_data_value__53; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_27 = io_internal_data_value__54 | io_internal_data_value__55; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_28 = io_internal_data_value__56 | io_internal_data_value__57; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_29 = io_internal_data_value__58 | io_internal_data_value__59; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_30 = io_internal_data_value__60 | io_internal_data_value__61; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_1_31 = io_internal_data_value__62 | io_internal_data_value__63; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_0 = io_internal_data_value_1_0 | io_internal_data_value_1_1; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_1 = io_internal_data_value_1_2 | io_internal_data_value_1_3; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_2 = io_internal_data_value_1_4 | io_internal_data_value_1_5; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_3 = io_internal_data_value_1_6 | io_internal_data_value_1_7; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_4 = io_internal_data_value_1_8 | io_internal_data_value_1_9; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_5 = io_internal_data_value_1_10 | io_internal_data_value_1_11; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_6 = io_internal_data_value_1_12 | io_internal_data_value_1_13; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_7 = io_internal_data_value_1_14 | io_internal_data_value_1_15; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_8 = io_internal_data_value_1_16 | io_internal_data_value_1_17; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_9 = io_internal_data_value_1_18 | io_internal_data_value_1_19; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_10 = io_internal_data_value_1_20 | io_internal_data_value_1_21; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_11 = io_internal_data_value_1_22 | io_internal_data_value_1_23; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_12 = io_internal_data_value_1_24 | io_internal_data_value_1_25; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_13 = io_internal_data_value_1_26 | io_internal_data_value_1_27; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_14 = io_internal_data_value_1_28 | io_internal_data_value_1_29; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_2_15 = io_internal_data_value_1_30 | io_internal_data_value_1_31; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_3_0 = io_internal_data_value_2_0 | io_internal_data_value_2_1; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_3_1 = io_internal_data_value_2_2 | io_internal_data_value_2_3; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_3_2 = io_internal_data_value_2_4 | io_internal_data_value_2_5; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_3_3 = io_internal_data_value_2_6 | io_internal_data_value_2_7; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_3_4 = io_internal_data_value_2_8 | io_internal_data_value_2_9; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_3_5 = io_internal_data_value_2_10 | io_internal_data_value_2_11; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_3_6 = io_internal_data_value_2_12 | io_internal_data_value_2_13; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_3_7 = io_internal_data_value_2_14 | io_internal_data_value_2_15; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_4_0 = io_internal_data_value_3_0 | io_internal_data_value_3_1; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_4_1 = io_internal_data_value_3_2 | io_internal_data_value_3_3; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_4_2 = io_internal_data_value_3_4 | io_internal_data_value_3_5; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_4_3 = io_internal_data_value_3_6 | io_internal_data_value_3_7; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_5_0 = io_internal_data_value_4_0 | io_internal_data_value_4_1; // @[Library.scala 129:37]
- wire [31:0] io_internal_data_value_5_1 = io_internal_data_value_4_2 | io_internal_data_value_4_3; // @[Library.scala 129:37]
- wire wvalidBits__2 = io_write_2_valid & io_write_2_addr == 6'h0; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits__1 = io_write_1_valid & io_write_1_addr == 6'h0; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits__0 = io_write_0_valid & io_write_0_addr == 6'h0; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits__5 = io_write_5_valid & io_write_5_addr == 6'h0; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits__4 = io_write_4_valid & io_write_4_addr == 6'h0; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits__3 = io_write_3_valid & io_write_3_addr == 6'h0; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_5 = {wvalidBits__5,wvalidBits__4,wvalidBits__3,wvalidBits__2,wvalidBits__1,wvalidBits__0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_12 = _T_5[1] + _T_5[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_72 = {{1'd0}, _T_5[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_14 = _GEN_72 + _T_12; // @[Bitwise.scala 48:55]
- wire [1:0] _T_16 = _T_5[4] + _T_5[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_73 = {{1'd0}, _T_5[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_18 = _GEN_73 + _T_16; // @[Bitwise.scala 48:55]
- wire [2:0] _T_20 = _T_14[1:0] + _T_18[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits__0 = wvalidBits__0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits__1 = wvalidBits__1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits__2 = wvalidBits__2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits__3 = wvalidBits__3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits__4 = wvalidBits__4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits__5 = wvalidBits__5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid = wvalidBits__0 | wvalidBits__1 | wvalidBits__2 | wvalidBits__3 | wvalidBits__4 | wvalidBits__5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_1 = wdataBits__0 | wdataBits__1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_2 = _wdata_T_1 | wdataBits__2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_3 = _wdata_T_2 | wdataBits__3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_4 = _wdata_T_3 | wdataBits__4; // @[Library.scala 76:39]
- wire [31:0] wdata = _wdata_T_4 | wdataBits__5; // @[Library.scala 76:39]
- wire wvalidBits_1_2 = io_write_2_valid & io_write_2_addr == 6'h1; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_1_1 = io_write_1_valid & io_write_1_addr == 6'h1; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_1_0 = io_write_0_valid & io_write_0_addr == 6'h1; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_1_5 = io_write_5_valid & io_write_5_addr == 6'h1; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_1_4 = io_write_4_valid & io_write_4_addr == 6'h1; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_1_3 = io_write_3_valid & io_write_3_addr == 6'h1; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_26 = {wvalidBits_1_5,wvalidBits_1_4,wvalidBits_1_3,wvalidBits_1_2,wvalidBits_1_1,wvalidBits_1_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_33 = _T_26[1] + _T_26[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_74 = {{1'd0}, _T_26[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_35 = _GEN_74 + _T_33; // @[Bitwise.scala 48:55]
- wire [1:0] _T_37 = _T_26[4] + _T_26[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_75 = {{1'd0}, _T_26[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_39 = _GEN_75 + _T_37; // @[Bitwise.scala 48:55]
- wire [2:0] _T_41 = _T_35[1:0] + _T_39[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_1_0 = wvalidBits_1_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_1_1 = wvalidBits_1_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_1_2 = wvalidBits_1_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_1_3 = wvalidBits_1_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_1_4 = wvalidBits_1_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_1_5 = wvalidBits_1_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_1 = wvalidBits_1_0 | wvalidBits_1_1 | wvalidBits_1_2 | wvalidBits_1_3 | wvalidBits_1_4 | wvalidBits_1_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_6 = wdataBits_1_0 | wdataBits_1_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_7 = _wdata_T_6 | wdataBits_1_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_8 = _wdata_T_7 | wdataBits_1_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_9 = _wdata_T_8 | wdataBits_1_4; // @[Library.scala 76:39]
- wire [31:0] wdata_1 = _wdata_T_9 | wdataBits_1_5; // @[Library.scala 76:39]
- wire wvalidBits_2_2 = io_write_2_valid & io_write_2_addr == 6'h2; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_2_1 = io_write_1_valid & io_write_1_addr == 6'h2; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_2_0 = io_write_0_valid & io_write_0_addr == 6'h2; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_2_5 = io_write_5_valid & io_write_5_addr == 6'h2; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_2_4 = io_write_4_valid & io_write_4_addr == 6'h2; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_2_3 = io_write_3_valid & io_write_3_addr == 6'h2; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_47 = {wvalidBits_2_5,wvalidBits_2_4,wvalidBits_2_3,wvalidBits_2_2,wvalidBits_2_1,wvalidBits_2_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_54 = _T_47[1] + _T_47[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_76 = {{1'd0}, _T_47[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_56 = _GEN_76 + _T_54; // @[Bitwise.scala 48:55]
- wire [1:0] _T_58 = _T_47[4] + _T_47[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_77 = {{1'd0}, _T_47[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_60 = _GEN_77 + _T_58; // @[Bitwise.scala 48:55]
- wire [2:0] _T_62 = _T_56[1:0] + _T_60[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_2_0 = wvalidBits_2_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_2_1 = wvalidBits_2_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_2_2 = wvalidBits_2_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_2_3 = wvalidBits_2_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_2_4 = wvalidBits_2_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_2_5 = wvalidBits_2_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_2 = wvalidBits_2_0 | wvalidBits_2_1 | wvalidBits_2_2 | wvalidBits_2_3 | wvalidBits_2_4 | wvalidBits_2_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_11 = wdataBits_2_0 | wdataBits_2_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_12 = _wdata_T_11 | wdataBits_2_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_13 = _wdata_T_12 | wdataBits_2_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_14 = _wdata_T_13 | wdataBits_2_4; // @[Library.scala 76:39]
- wire [31:0] wdata_2 = _wdata_T_14 | wdataBits_2_5; // @[Library.scala 76:39]
- wire wvalidBits_3_2 = io_write_2_valid & io_write_2_addr == 6'h3; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_3_1 = io_write_1_valid & io_write_1_addr == 6'h3; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_3_0 = io_write_0_valid & io_write_0_addr == 6'h3; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_3_5 = io_write_5_valid & io_write_5_addr == 6'h3; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_3_4 = io_write_4_valid & io_write_4_addr == 6'h3; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_3_3 = io_write_3_valid & io_write_3_addr == 6'h3; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_68 = {wvalidBits_3_5,wvalidBits_3_4,wvalidBits_3_3,wvalidBits_3_2,wvalidBits_3_1,wvalidBits_3_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_75 = _T_68[1] + _T_68[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_78 = {{1'd0}, _T_68[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_77 = _GEN_78 + _T_75; // @[Bitwise.scala 48:55]
- wire [1:0] _T_79 = _T_68[4] + _T_68[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_79 = {{1'd0}, _T_68[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_81 = _GEN_79 + _T_79; // @[Bitwise.scala 48:55]
- wire [2:0] _T_83 = _T_77[1:0] + _T_81[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_3_0 = wvalidBits_3_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_3_1 = wvalidBits_3_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_3_2 = wvalidBits_3_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_3_3 = wvalidBits_3_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_3_4 = wvalidBits_3_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_3_5 = wvalidBits_3_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_3 = wvalidBits_3_0 | wvalidBits_3_1 | wvalidBits_3_2 | wvalidBits_3_3 | wvalidBits_3_4 | wvalidBits_3_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_16 = wdataBits_3_0 | wdataBits_3_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_17 = _wdata_T_16 | wdataBits_3_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_18 = _wdata_T_17 | wdataBits_3_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_19 = _wdata_T_18 | wdataBits_3_4; // @[Library.scala 76:39]
- wire [31:0] wdata_3 = _wdata_T_19 | wdataBits_3_5; // @[Library.scala 76:39]
- wire wvalidBits_4_2 = io_write_2_valid & io_write_2_addr == 6'h4; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_4_1 = io_write_1_valid & io_write_1_addr == 6'h4; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_4_0 = io_write_0_valid & io_write_0_addr == 6'h4; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_4_5 = io_write_5_valid & io_write_5_addr == 6'h4; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_4_4 = io_write_4_valid & io_write_4_addr == 6'h4; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_4_3 = io_write_3_valid & io_write_3_addr == 6'h4; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_89 = {wvalidBits_4_5,wvalidBits_4_4,wvalidBits_4_3,wvalidBits_4_2,wvalidBits_4_1,wvalidBits_4_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_96 = _T_89[1] + _T_89[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_80 = {{1'd0}, _T_89[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_98 = _GEN_80 + _T_96; // @[Bitwise.scala 48:55]
- wire [1:0] _T_100 = _T_89[4] + _T_89[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_81 = {{1'd0}, _T_89[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_102 = _GEN_81 + _T_100; // @[Bitwise.scala 48:55]
- wire [2:0] _T_104 = _T_98[1:0] + _T_102[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_4_0 = wvalidBits_4_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_4_1 = wvalidBits_4_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_4_2 = wvalidBits_4_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_4_3 = wvalidBits_4_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_4_4 = wvalidBits_4_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_4_5 = wvalidBits_4_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_4 = wvalidBits_4_0 | wvalidBits_4_1 | wvalidBits_4_2 | wvalidBits_4_3 | wvalidBits_4_4 | wvalidBits_4_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_21 = wdataBits_4_0 | wdataBits_4_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_22 = _wdata_T_21 | wdataBits_4_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_23 = _wdata_T_22 | wdataBits_4_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_24 = _wdata_T_23 | wdataBits_4_4; // @[Library.scala 76:39]
- wire [31:0] wdata_4 = _wdata_T_24 | wdataBits_4_5; // @[Library.scala 76:39]
- wire wvalidBits_5_2 = io_write_2_valid & io_write_2_addr == 6'h5; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_5_1 = io_write_1_valid & io_write_1_addr == 6'h5; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_5_0 = io_write_0_valid & io_write_0_addr == 6'h5; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_5_5 = io_write_5_valid & io_write_5_addr == 6'h5; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_5_4 = io_write_4_valid & io_write_4_addr == 6'h5; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_5_3 = io_write_3_valid & io_write_3_addr == 6'h5; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_110 = {wvalidBits_5_5,wvalidBits_5_4,wvalidBits_5_3,wvalidBits_5_2,wvalidBits_5_1,wvalidBits_5_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_117 = _T_110[1] + _T_110[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_82 = {{1'd0}, _T_110[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_119 = _GEN_82 + _T_117; // @[Bitwise.scala 48:55]
- wire [1:0] _T_121 = _T_110[4] + _T_110[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_83 = {{1'd0}, _T_110[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_123 = _GEN_83 + _T_121; // @[Bitwise.scala 48:55]
- wire [2:0] _T_125 = _T_119[1:0] + _T_123[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_5_0 = wvalidBits_5_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_5_1 = wvalidBits_5_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_5_2 = wvalidBits_5_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_5_3 = wvalidBits_5_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_5_4 = wvalidBits_5_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_5_5 = wvalidBits_5_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_5 = wvalidBits_5_0 | wvalidBits_5_1 | wvalidBits_5_2 | wvalidBits_5_3 | wvalidBits_5_4 | wvalidBits_5_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_26 = wdataBits_5_0 | wdataBits_5_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_27 = _wdata_T_26 | wdataBits_5_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_28 = _wdata_T_27 | wdataBits_5_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_29 = _wdata_T_28 | wdataBits_5_4; // @[Library.scala 76:39]
- wire [31:0] wdata_5 = _wdata_T_29 | wdataBits_5_5; // @[Library.scala 76:39]
- wire wvalidBits_6_2 = io_write_2_valid & io_write_2_addr == 6'h6; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_6_1 = io_write_1_valid & io_write_1_addr == 6'h6; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_6_0 = io_write_0_valid & io_write_0_addr == 6'h6; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_6_5 = io_write_5_valid & io_write_5_addr == 6'h6; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_6_4 = io_write_4_valid & io_write_4_addr == 6'h6; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_6_3 = io_write_3_valid & io_write_3_addr == 6'h6; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_131 = {wvalidBits_6_5,wvalidBits_6_4,wvalidBits_6_3,wvalidBits_6_2,wvalidBits_6_1,wvalidBits_6_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_138 = _T_131[1] + _T_131[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_84 = {{1'd0}, _T_131[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_140 = _GEN_84 + _T_138; // @[Bitwise.scala 48:55]
- wire [1:0] _T_142 = _T_131[4] + _T_131[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_85 = {{1'd0}, _T_131[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_144 = _GEN_85 + _T_142; // @[Bitwise.scala 48:55]
- wire [2:0] _T_146 = _T_140[1:0] + _T_144[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_6_0 = wvalidBits_6_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_6_1 = wvalidBits_6_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_6_2 = wvalidBits_6_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_6_3 = wvalidBits_6_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_6_4 = wvalidBits_6_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_6_5 = wvalidBits_6_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_6 = wvalidBits_6_0 | wvalidBits_6_1 | wvalidBits_6_2 | wvalidBits_6_3 | wvalidBits_6_4 | wvalidBits_6_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_31 = wdataBits_6_0 | wdataBits_6_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_32 = _wdata_T_31 | wdataBits_6_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_33 = _wdata_T_32 | wdataBits_6_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_34 = _wdata_T_33 | wdataBits_6_4; // @[Library.scala 76:39]
- wire [31:0] wdata_6 = _wdata_T_34 | wdataBits_6_5; // @[Library.scala 76:39]
- wire wvalidBits_7_2 = io_write_2_valid & io_write_2_addr == 6'h7; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_7_1 = io_write_1_valid & io_write_1_addr == 6'h7; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_7_0 = io_write_0_valid & io_write_0_addr == 6'h7; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_7_5 = io_write_5_valid & io_write_5_addr == 6'h7; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_7_4 = io_write_4_valid & io_write_4_addr == 6'h7; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_7_3 = io_write_3_valid & io_write_3_addr == 6'h7; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_152 = {wvalidBits_7_5,wvalidBits_7_4,wvalidBits_7_3,wvalidBits_7_2,wvalidBits_7_1,wvalidBits_7_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_159 = _T_152[1] + _T_152[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_86 = {{1'd0}, _T_152[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_161 = _GEN_86 + _T_159; // @[Bitwise.scala 48:55]
- wire [1:0] _T_163 = _T_152[4] + _T_152[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_87 = {{1'd0}, _T_152[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_165 = _GEN_87 + _T_163; // @[Bitwise.scala 48:55]
- wire [2:0] _T_167 = _T_161[1:0] + _T_165[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_7_0 = wvalidBits_7_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_7_1 = wvalidBits_7_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_7_2 = wvalidBits_7_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_7_3 = wvalidBits_7_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_7_4 = wvalidBits_7_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_7_5 = wvalidBits_7_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_7 = wvalidBits_7_0 | wvalidBits_7_1 | wvalidBits_7_2 | wvalidBits_7_3 | wvalidBits_7_4 | wvalidBits_7_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_36 = wdataBits_7_0 | wdataBits_7_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_37 = _wdata_T_36 | wdataBits_7_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_38 = _wdata_T_37 | wdataBits_7_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_39 = _wdata_T_38 | wdataBits_7_4; // @[Library.scala 76:39]
- wire [31:0] wdata_7 = _wdata_T_39 | wdataBits_7_5; // @[Library.scala 76:39]
- wire wvalidBits_8_2 = io_write_2_valid & io_write_2_addr == 6'h8; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_8_1 = io_write_1_valid & io_write_1_addr == 6'h8; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_8_0 = io_write_0_valid & io_write_0_addr == 6'h8; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_8_5 = io_write_5_valid & io_write_5_addr == 6'h8; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_8_4 = io_write_4_valid & io_write_4_addr == 6'h8; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_8_3 = io_write_3_valid & io_write_3_addr == 6'h8; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_173 = {wvalidBits_8_5,wvalidBits_8_4,wvalidBits_8_3,wvalidBits_8_2,wvalidBits_8_1,wvalidBits_8_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_180 = _T_173[1] + _T_173[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_88 = {{1'd0}, _T_173[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_182 = _GEN_88 + _T_180; // @[Bitwise.scala 48:55]
- wire [1:0] _T_184 = _T_173[4] + _T_173[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_89 = {{1'd0}, _T_173[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_186 = _GEN_89 + _T_184; // @[Bitwise.scala 48:55]
- wire [2:0] _T_188 = _T_182[1:0] + _T_186[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_8_0 = wvalidBits_8_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_8_1 = wvalidBits_8_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_8_2 = wvalidBits_8_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_8_3 = wvalidBits_8_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_8_4 = wvalidBits_8_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_8_5 = wvalidBits_8_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_8 = wvalidBits_8_0 | wvalidBits_8_1 | wvalidBits_8_2 | wvalidBits_8_3 | wvalidBits_8_4 | wvalidBits_8_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_41 = wdataBits_8_0 | wdataBits_8_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_42 = _wdata_T_41 | wdataBits_8_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_43 = _wdata_T_42 | wdataBits_8_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_44 = _wdata_T_43 | wdataBits_8_4; // @[Library.scala 76:39]
- wire [31:0] wdata_8 = _wdata_T_44 | wdataBits_8_5; // @[Library.scala 76:39]
- wire wvalidBits_9_2 = io_write_2_valid & io_write_2_addr == 6'h9; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_9_1 = io_write_1_valid & io_write_1_addr == 6'h9; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_9_0 = io_write_0_valid & io_write_0_addr == 6'h9; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_9_5 = io_write_5_valid & io_write_5_addr == 6'h9; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_9_4 = io_write_4_valid & io_write_4_addr == 6'h9; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_9_3 = io_write_3_valid & io_write_3_addr == 6'h9; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_194 = {wvalidBits_9_5,wvalidBits_9_4,wvalidBits_9_3,wvalidBits_9_2,wvalidBits_9_1,wvalidBits_9_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_201 = _T_194[1] + _T_194[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_90 = {{1'd0}, _T_194[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_203 = _GEN_90 + _T_201; // @[Bitwise.scala 48:55]
- wire [1:0] _T_205 = _T_194[4] + _T_194[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_91 = {{1'd0}, _T_194[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_207 = _GEN_91 + _T_205; // @[Bitwise.scala 48:55]
- wire [2:0] _T_209 = _T_203[1:0] + _T_207[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_9_0 = wvalidBits_9_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_9_1 = wvalidBits_9_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_9_2 = wvalidBits_9_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_9_3 = wvalidBits_9_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_9_4 = wvalidBits_9_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_9_5 = wvalidBits_9_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_9 = wvalidBits_9_0 | wvalidBits_9_1 | wvalidBits_9_2 | wvalidBits_9_3 | wvalidBits_9_4 | wvalidBits_9_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_46 = wdataBits_9_0 | wdataBits_9_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_47 = _wdata_T_46 | wdataBits_9_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_48 = _wdata_T_47 | wdataBits_9_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_49 = _wdata_T_48 | wdataBits_9_4; // @[Library.scala 76:39]
- wire [31:0] wdata_9 = _wdata_T_49 | wdataBits_9_5; // @[Library.scala 76:39]
- wire wvalidBits_10_2 = io_write_2_valid & io_write_2_addr == 6'ha; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_10_1 = io_write_1_valid & io_write_1_addr == 6'ha; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_10_0 = io_write_0_valid & io_write_0_addr == 6'ha; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_10_5 = io_write_5_valid & io_write_5_addr == 6'ha; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_10_4 = io_write_4_valid & io_write_4_addr == 6'ha; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_10_3 = io_write_3_valid & io_write_3_addr == 6'ha; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_215 = {wvalidBits_10_5,wvalidBits_10_4,wvalidBits_10_3,wvalidBits_10_2,wvalidBits_10_1,wvalidBits_10_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_222 = _T_215[1] + _T_215[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_92 = {{1'd0}, _T_215[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_224 = _GEN_92 + _T_222; // @[Bitwise.scala 48:55]
- wire [1:0] _T_226 = _T_215[4] + _T_215[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_93 = {{1'd0}, _T_215[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_228 = _GEN_93 + _T_226; // @[Bitwise.scala 48:55]
- wire [2:0] _T_230 = _T_224[1:0] + _T_228[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_10_0 = wvalidBits_10_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_10_1 = wvalidBits_10_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_10_2 = wvalidBits_10_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_10_3 = wvalidBits_10_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_10_4 = wvalidBits_10_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_10_5 = wvalidBits_10_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_10 = wvalidBits_10_0 | wvalidBits_10_1 | wvalidBits_10_2 | wvalidBits_10_3 | wvalidBits_10_4 |
- wvalidBits_10_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_51 = wdataBits_10_0 | wdataBits_10_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_52 = _wdata_T_51 | wdataBits_10_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_53 = _wdata_T_52 | wdataBits_10_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_54 = _wdata_T_53 | wdataBits_10_4; // @[Library.scala 76:39]
- wire [31:0] wdata_10 = _wdata_T_54 | wdataBits_10_5; // @[Library.scala 76:39]
- wire wvalidBits_11_2 = io_write_2_valid & io_write_2_addr == 6'hb; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_11_1 = io_write_1_valid & io_write_1_addr == 6'hb; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_11_0 = io_write_0_valid & io_write_0_addr == 6'hb; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_11_5 = io_write_5_valid & io_write_5_addr == 6'hb; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_11_4 = io_write_4_valid & io_write_4_addr == 6'hb; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_11_3 = io_write_3_valid & io_write_3_addr == 6'hb; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_236 = {wvalidBits_11_5,wvalidBits_11_4,wvalidBits_11_3,wvalidBits_11_2,wvalidBits_11_1,wvalidBits_11_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_243 = _T_236[1] + _T_236[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_94 = {{1'd0}, _T_236[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_245 = _GEN_94 + _T_243; // @[Bitwise.scala 48:55]
- wire [1:0] _T_247 = _T_236[4] + _T_236[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_95 = {{1'd0}, _T_236[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_249 = _GEN_95 + _T_247; // @[Bitwise.scala 48:55]
- wire [2:0] _T_251 = _T_245[1:0] + _T_249[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_11_0 = wvalidBits_11_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_11_1 = wvalidBits_11_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_11_2 = wvalidBits_11_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_11_3 = wvalidBits_11_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_11_4 = wvalidBits_11_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_11_5 = wvalidBits_11_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_11 = wvalidBits_11_0 | wvalidBits_11_1 | wvalidBits_11_2 | wvalidBits_11_3 | wvalidBits_11_4 |
- wvalidBits_11_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_56 = wdataBits_11_0 | wdataBits_11_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_57 = _wdata_T_56 | wdataBits_11_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_58 = _wdata_T_57 | wdataBits_11_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_59 = _wdata_T_58 | wdataBits_11_4; // @[Library.scala 76:39]
- wire [31:0] wdata_11 = _wdata_T_59 | wdataBits_11_5; // @[Library.scala 76:39]
- wire wvalidBits_12_2 = io_write_2_valid & io_write_2_addr == 6'hc; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_12_1 = io_write_1_valid & io_write_1_addr == 6'hc; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_12_0 = io_write_0_valid & io_write_0_addr == 6'hc; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_12_5 = io_write_5_valid & io_write_5_addr == 6'hc; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_12_4 = io_write_4_valid & io_write_4_addr == 6'hc; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_12_3 = io_write_3_valid & io_write_3_addr == 6'hc; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_257 = {wvalidBits_12_5,wvalidBits_12_4,wvalidBits_12_3,wvalidBits_12_2,wvalidBits_12_1,wvalidBits_12_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_264 = _T_257[1] + _T_257[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_96 = {{1'd0}, _T_257[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_266 = _GEN_96 + _T_264; // @[Bitwise.scala 48:55]
- wire [1:0] _T_268 = _T_257[4] + _T_257[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_97 = {{1'd0}, _T_257[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_270 = _GEN_97 + _T_268; // @[Bitwise.scala 48:55]
- wire [2:0] _T_272 = _T_266[1:0] + _T_270[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_12_0 = wvalidBits_12_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_12_1 = wvalidBits_12_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_12_2 = wvalidBits_12_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_12_3 = wvalidBits_12_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_12_4 = wvalidBits_12_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_12_5 = wvalidBits_12_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_12 = wvalidBits_12_0 | wvalidBits_12_1 | wvalidBits_12_2 | wvalidBits_12_3 | wvalidBits_12_4 |
- wvalidBits_12_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_61 = wdataBits_12_0 | wdataBits_12_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_62 = _wdata_T_61 | wdataBits_12_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_63 = _wdata_T_62 | wdataBits_12_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_64 = _wdata_T_63 | wdataBits_12_4; // @[Library.scala 76:39]
- wire [31:0] wdata_12 = _wdata_T_64 | wdataBits_12_5; // @[Library.scala 76:39]
- wire wvalidBits_13_2 = io_write_2_valid & io_write_2_addr == 6'hd; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_13_1 = io_write_1_valid & io_write_1_addr == 6'hd; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_13_0 = io_write_0_valid & io_write_0_addr == 6'hd; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_13_5 = io_write_5_valid & io_write_5_addr == 6'hd; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_13_4 = io_write_4_valid & io_write_4_addr == 6'hd; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_13_3 = io_write_3_valid & io_write_3_addr == 6'hd; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_278 = {wvalidBits_13_5,wvalidBits_13_4,wvalidBits_13_3,wvalidBits_13_2,wvalidBits_13_1,wvalidBits_13_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_285 = _T_278[1] + _T_278[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_98 = {{1'd0}, _T_278[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_287 = _GEN_98 + _T_285; // @[Bitwise.scala 48:55]
- wire [1:0] _T_289 = _T_278[4] + _T_278[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_99 = {{1'd0}, _T_278[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_291 = _GEN_99 + _T_289; // @[Bitwise.scala 48:55]
- wire [2:0] _T_293 = _T_287[1:0] + _T_291[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_13_0 = wvalidBits_13_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_13_1 = wvalidBits_13_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_13_2 = wvalidBits_13_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_13_3 = wvalidBits_13_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_13_4 = wvalidBits_13_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_13_5 = wvalidBits_13_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_13 = wvalidBits_13_0 | wvalidBits_13_1 | wvalidBits_13_2 | wvalidBits_13_3 | wvalidBits_13_4 |
- wvalidBits_13_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_66 = wdataBits_13_0 | wdataBits_13_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_67 = _wdata_T_66 | wdataBits_13_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_68 = _wdata_T_67 | wdataBits_13_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_69 = _wdata_T_68 | wdataBits_13_4; // @[Library.scala 76:39]
- wire [31:0] wdata_13 = _wdata_T_69 | wdataBits_13_5; // @[Library.scala 76:39]
- wire wvalidBits_14_2 = io_write_2_valid & io_write_2_addr == 6'he; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_14_1 = io_write_1_valid & io_write_1_addr == 6'he; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_14_0 = io_write_0_valid & io_write_0_addr == 6'he; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_14_5 = io_write_5_valid & io_write_5_addr == 6'he; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_14_4 = io_write_4_valid & io_write_4_addr == 6'he; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_14_3 = io_write_3_valid & io_write_3_addr == 6'he; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_299 = {wvalidBits_14_5,wvalidBits_14_4,wvalidBits_14_3,wvalidBits_14_2,wvalidBits_14_1,wvalidBits_14_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_306 = _T_299[1] + _T_299[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_100 = {{1'd0}, _T_299[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_308 = _GEN_100 + _T_306; // @[Bitwise.scala 48:55]
- wire [1:0] _T_310 = _T_299[4] + _T_299[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_101 = {{1'd0}, _T_299[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_312 = _GEN_101 + _T_310; // @[Bitwise.scala 48:55]
- wire [2:0] _T_314 = _T_308[1:0] + _T_312[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_14_0 = wvalidBits_14_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_14_1 = wvalidBits_14_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_14_2 = wvalidBits_14_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_14_3 = wvalidBits_14_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_14_4 = wvalidBits_14_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_14_5 = wvalidBits_14_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_14 = wvalidBits_14_0 | wvalidBits_14_1 | wvalidBits_14_2 | wvalidBits_14_3 | wvalidBits_14_4 |
- wvalidBits_14_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_71 = wdataBits_14_0 | wdataBits_14_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_72 = _wdata_T_71 | wdataBits_14_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_73 = _wdata_T_72 | wdataBits_14_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_74 = _wdata_T_73 | wdataBits_14_4; // @[Library.scala 76:39]
- wire [31:0] wdata_14 = _wdata_T_74 | wdataBits_14_5; // @[Library.scala 76:39]
- wire wvalidBits_15_2 = io_write_2_valid & io_write_2_addr == 6'hf; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_15_1 = io_write_1_valid & io_write_1_addr == 6'hf; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_15_0 = io_write_0_valid & io_write_0_addr == 6'hf; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_15_5 = io_write_5_valid & io_write_5_addr == 6'hf; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_15_4 = io_write_4_valid & io_write_4_addr == 6'hf; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_15_3 = io_write_3_valid & io_write_3_addr == 6'hf; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_320 = {wvalidBits_15_5,wvalidBits_15_4,wvalidBits_15_3,wvalidBits_15_2,wvalidBits_15_1,wvalidBits_15_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_327 = _T_320[1] + _T_320[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_102 = {{1'd0}, _T_320[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_329 = _GEN_102 + _T_327; // @[Bitwise.scala 48:55]
- wire [1:0] _T_331 = _T_320[4] + _T_320[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_103 = {{1'd0}, _T_320[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_333 = _GEN_103 + _T_331; // @[Bitwise.scala 48:55]
- wire [2:0] _T_335 = _T_329[1:0] + _T_333[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_15_0 = wvalidBits_15_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_15_1 = wvalidBits_15_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_15_2 = wvalidBits_15_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_15_3 = wvalidBits_15_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_15_4 = wvalidBits_15_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_15_5 = wvalidBits_15_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_15 = wvalidBits_15_0 | wvalidBits_15_1 | wvalidBits_15_2 | wvalidBits_15_3 | wvalidBits_15_4 |
- wvalidBits_15_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_76 = wdataBits_15_0 | wdataBits_15_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_77 = _wdata_T_76 | wdataBits_15_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_78 = _wdata_T_77 | wdataBits_15_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_79 = _wdata_T_78 | wdataBits_15_4; // @[Library.scala 76:39]
- wire [31:0] wdata_15 = _wdata_T_79 | wdataBits_15_5; // @[Library.scala 76:39]
- wire wvalidBits_16_2 = io_write_2_valid & io_write_2_addr == 6'h10; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_16_1 = io_write_1_valid & io_write_1_addr == 6'h10; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_16_0 = io_write_0_valid & io_write_0_addr == 6'h10; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_16_5 = io_write_5_valid & io_write_5_addr == 6'h10; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_16_4 = io_write_4_valid & io_write_4_addr == 6'h10; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_16_3 = io_write_3_valid & io_write_3_addr == 6'h10; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_341 = {wvalidBits_16_5,wvalidBits_16_4,wvalidBits_16_3,wvalidBits_16_2,wvalidBits_16_1,wvalidBits_16_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_348 = _T_341[1] + _T_341[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_104 = {{1'd0}, _T_341[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_350 = _GEN_104 + _T_348; // @[Bitwise.scala 48:55]
- wire [1:0] _T_352 = _T_341[4] + _T_341[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_105 = {{1'd0}, _T_341[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_354 = _GEN_105 + _T_352; // @[Bitwise.scala 48:55]
- wire [2:0] _T_356 = _T_350[1:0] + _T_354[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_16_0 = wvalidBits_16_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_16_1 = wvalidBits_16_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_16_2 = wvalidBits_16_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_16_3 = wvalidBits_16_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_16_4 = wvalidBits_16_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_16_5 = wvalidBits_16_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_16 = wvalidBits_16_0 | wvalidBits_16_1 | wvalidBits_16_2 | wvalidBits_16_3 | wvalidBits_16_4 |
- wvalidBits_16_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_81 = wdataBits_16_0 | wdataBits_16_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_82 = _wdata_T_81 | wdataBits_16_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_83 = _wdata_T_82 | wdataBits_16_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_84 = _wdata_T_83 | wdataBits_16_4; // @[Library.scala 76:39]
- wire [31:0] wdata_16 = _wdata_T_84 | wdataBits_16_5; // @[Library.scala 76:39]
- wire wvalidBits_17_2 = io_write_2_valid & io_write_2_addr == 6'h11; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_17_1 = io_write_1_valid & io_write_1_addr == 6'h11; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_17_0 = io_write_0_valid & io_write_0_addr == 6'h11; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_17_5 = io_write_5_valid & io_write_5_addr == 6'h11; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_17_4 = io_write_4_valid & io_write_4_addr == 6'h11; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_17_3 = io_write_3_valid & io_write_3_addr == 6'h11; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_362 = {wvalidBits_17_5,wvalidBits_17_4,wvalidBits_17_3,wvalidBits_17_2,wvalidBits_17_1,wvalidBits_17_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_369 = _T_362[1] + _T_362[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_106 = {{1'd0}, _T_362[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_371 = _GEN_106 + _T_369; // @[Bitwise.scala 48:55]
- wire [1:0] _T_373 = _T_362[4] + _T_362[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_107 = {{1'd0}, _T_362[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_375 = _GEN_107 + _T_373; // @[Bitwise.scala 48:55]
- wire [2:0] _T_377 = _T_371[1:0] + _T_375[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_17_0 = wvalidBits_17_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_17_1 = wvalidBits_17_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_17_2 = wvalidBits_17_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_17_3 = wvalidBits_17_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_17_4 = wvalidBits_17_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_17_5 = wvalidBits_17_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_17 = wvalidBits_17_0 | wvalidBits_17_1 | wvalidBits_17_2 | wvalidBits_17_3 | wvalidBits_17_4 |
- wvalidBits_17_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_86 = wdataBits_17_0 | wdataBits_17_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_87 = _wdata_T_86 | wdataBits_17_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_88 = _wdata_T_87 | wdataBits_17_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_89 = _wdata_T_88 | wdataBits_17_4; // @[Library.scala 76:39]
- wire [31:0] wdata_17 = _wdata_T_89 | wdataBits_17_5; // @[Library.scala 76:39]
- wire wvalidBits_18_2 = io_write_2_valid & io_write_2_addr == 6'h12; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_18_1 = io_write_1_valid & io_write_1_addr == 6'h12; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_18_0 = io_write_0_valid & io_write_0_addr == 6'h12; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_18_5 = io_write_5_valid & io_write_5_addr == 6'h12; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_18_4 = io_write_4_valid & io_write_4_addr == 6'h12; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_18_3 = io_write_3_valid & io_write_3_addr == 6'h12; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_383 = {wvalidBits_18_5,wvalidBits_18_4,wvalidBits_18_3,wvalidBits_18_2,wvalidBits_18_1,wvalidBits_18_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_390 = _T_383[1] + _T_383[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_108 = {{1'd0}, _T_383[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_392 = _GEN_108 + _T_390; // @[Bitwise.scala 48:55]
- wire [1:0] _T_394 = _T_383[4] + _T_383[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_109 = {{1'd0}, _T_383[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_396 = _GEN_109 + _T_394; // @[Bitwise.scala 48:55]
- wire [2:0] _T_398 = _T_392[1:0] + _T_396[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_18_0 = wvalidBits_18_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_18_1 = wvalidBits_18_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_18_2 = wvalidBits_18_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_18_3 = wvalidBits_18_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_18_4 = wvalidBits_18_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_18_5 = wvalidBits_18_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_18 = wvalidBits_18_0 | wvalidBits_18_1 | wvalidBits_18_2 | wvalidBits_18_3 | wvalidBits_18_4 |
- wvalidBits_18_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_91 = wdataBits_18_0 | wdataBits_18_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_92 = _wdata_T_91 | wdataBits_18_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_93 = _wdata_T_92 | wdataBits_18_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_94 = _wdata_T_93 | wdataBits_18_4; // @[Library.scala 76:39]
- wire [31:0] wdata_18 = _wdata_T_94 | wdataBits_18_5; // @[Library.scala 76:39]
- wire wvalidBits_19_2 = io_write_2_valid & io_write_2_addr == 6'h13; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_19_1 = io_write_1_valid & io_write_1_addr == 6'h13; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_19_0 = io_write_0_valid & io_write_0_addr == 6'h13; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_19_5 = io_write_5_valid & io_write_5_addr == 6'h13; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_19_4 = io_write_4_valid & io_write_4_addr == 6'h13; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_19_3 = io_write_3_valid & io_write_3_addr == 6'h13; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_404 = {wvalidBits_19_5,wvalidBits_19_4,wvalidBits_19_3,wvalidBits_19_2,wvalidBits_19_1,wvalidBits_19_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_411 = _T_404[1] + _T_404[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_110 = {{1'd0}, _T_404[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_413 = _GEN_110 + _T_411; // @[Bitwise.scala 48:55]
- wire [1:0] _T_415 = _T_404[4] + _T_404[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_111 = {{1'd0}, _T_404[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_417 = _GEN_111 + _T_415; // @[Bitwise.scala 48:55]
- wire [2:0] _T_419 = _T_413[1:0] + _T_417[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_19_0 = wvalidBits_19_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_19_1 = wvalidBits_19_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_19_2 = wvalidBits_19_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_19_3 = wvalidBits_19_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_19_4 = wvalidBits_19_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_19_5 = wvalidBits_19_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_19 = wvalidBits_19_0 | wvalidBits_19_1 | wvalidBits_19_2 | wvalidBits_19_3 | wvalidBits_19_4 |
- wvalidBits_19_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_96 = wdataBits_19_0 | wdataBits_19_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_97 = _wdata_T_96 | wdataBits_19_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_98 = _wdata_T_97 | wdataBits_19_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_99 = _wdata_T_98 | wdataBits_19_4; // @[Library.scala 76:39]
- wire [31:0] wdata_19 = _wdata_T_99 | wdataBits_19_5; // @[Library.scala 76:39]
- wire wvalidBits_20_2 = io_write_2_valid & io_write_2_addr == 6'h14; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_20_1 = io_write_1_valid & io_write_1_addr == 6'h14; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_20_0 = io_write_0_valid & io_write_0_addr == 6'h14; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_20_5 = io_write_5_valid & io_write_5_addr == 6'h14; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_20_4 = io_write_4_valid & io_write_4_addr == 6'h14; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_20_3 = io_write_3_valid & io_write_3_addr == 6'h14; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_425 = {wvalidBits_20_5,wvalidBits_20_4,wvalidBits_20_3,wvalidBits_20_2,wvalidBits_20_1,wvalidBits_20_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_432 = _T_425[1] + _T_425[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_112 = {{1'd0}, _T_425[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_434 = _GEN_112 + _T_432; // @[Bitwise.scala 48:55]
- wire [1:0] _T_436 = _T_425[4] + _T_425[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_113 = {{1'd0}, _T_425[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_438 = _GEN_113 + _T_436; // @[Bitwise.scala 48:55]
- wire [2:0] _T_440 = _T_434[1:0] + _T_438[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_20_0 = wvalidBits_20_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_20_1 = wvalidBits_20_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_20_2 = wvalidBits_20_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_20_3 = wvalidBits_20_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_20_4 = wvalidBits_20_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_20_5 = wvalidBits_20_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_20 = wvalidBits_20_0 | wvalidBits_20_1 | wvalidBits_20_2 | wvalidBits_20_3 | wvalidBits_20_4 |
- wvalidBits_20_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_101 = wdataBits_20_0 | wdataBits_20_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_102 = _wdata_T_101 | wdataBits_20_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_103 = _wdata_T_102 | wdataBits_20_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_104 = _wdata_T_103 | wdataBits_20_4; // @[Library.scala 76:39]
- wire [31:0] wdata_20 = _wdata_T_104 | wdataBits_20_5; // @[Library.scala 76:39]
- wire wvalidBits_21_2 = io_write_2_valid & io_write_2_addr == 6'h15; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_21_1 = io_write_1_valid & io_write_1_addr == 6'h15; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_21_0 = io_write_0_valid & io_write_0_addr == 6'h15; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_21_5 = io_write_5_valid & io_write_5_addr == 6'h15; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_21_4 = io_write_4_valid & io_write_4_addr == 6'h15; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_21_3 = io_write_3_valid & io_write_3_addr == 6'h15; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_446 = {wvalidBits_21_5,wvalidBits_21_4,wvalidBits_21_3,wvalidBits_21_2,wvalidBits_21_1,wvalidBits_21_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_453 = _T_446[1] + _T_446[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_114 = {{1'd0}, _T_446[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_455 = _GEN_114 + _T_453; // @[Bitwise.scala 48:55]
- wire [1:0] _T_457 = _T_446[4] + _T_446[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_115 = {{1'd0}, _T_446[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_459 = _GEN_115 + _T_457; // @[Bitwise.scala 48:55]
- wire [2:0] _T_461 = _T_455[1:0] + _T_459[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_21_0 = wvalidBits_21_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_21_1 = wvalidBits_21_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_21_2 = wvalidBits_21_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_21_3 = wvalidBits_21_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_21_4 = wvalidBits_21_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_21_5 = wvalidBits_21_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_21 = wvalidBits_21_0 | wvalidBits_21_1 | wvalidBits_21_2 | wvalidBits_21_3 | wvalidBits_21_4 |
- wvalidBits_21_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_106 = wdataBits_21_0 | wdataBits_21_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_107 = _wdata_T_106 | wdataBits_21_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_108 = _wdata_T_107 | wdataBits_21_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_109 = _wdata_T_108 | wdataBits_21_4; // @[Library.scala 76:39]
- wire [31:0] wdata_21 = _wdata_T_109 | wdataBits_21_5; // @[Library.scala 76:39]
- wire wvalidBits_22_2 = io_write_2_valid & io_write_2_addr == 6'h16; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_22_1 = io_write_1_valid & io_write_1_addr == 6'h16; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_22_0 = io_write_0_valid & io_write_0_addr == 6'h16; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_22_5 = io_write_5_valid & io_write_5_addr == 6'h16; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_22_4 = io_write_4_valid & io_write_4_addr == 6'h16; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_22_3 = io_write_3_valid & io_write_3_addr == 6'h16; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_467 = {wvalidBits_22_5,wvalidBits_22_4,wvalidBits_22_3,wvalidBits_22_2,wvalidBits_22_1,wvalidBits_22_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_474 = _T_467[1] + _T_467[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_116 = {{1'd0}, _T_467[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_476 = _GEN_116 + _T_474; // @[Bitwise.scala 48:55]
- wire [1:0] _T_478 = _T_467[4] + _T_467[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_117 = {{1'd0}, _T_467[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_480 = _GEN_117 + _T_478; // @[Bitwise.scala 48:55]
- wire [2:0] _T_482 = _T_476[1:0] + _T_480[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_22_0 = wvalidBits_22_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_22_1 = wvalidBits_22_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_22_2 = wvalidBits_22_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_22_3 = wvalidBits_22_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_22_4 = wvalidBits_22_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_22_5 = wvalidBits_22_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_22 = wvalidBits_22_0 | wvalidBits_22_1 | wvalidBits_22_2 | wvalidBits_22_3 | wvalidBits_22_4 |
- wvalidBits_22_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_111 = wdataBits_22_0 | wdataBits_22_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_112 = _wdata_T_111 | wdataBits_22_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_113 = _wdata_T_112 | wdataBits_22_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_114 = _wdata_T_113 | wdataBits_22_4; // @[Library.scala 76:39]
- wire [31:0] wdata_22 = _wdata_T_114 | wdataBits_22_5; // @[Library.scala 76:39]
- wire wvalidBits_23_2 = io_write_2_valid & io_write_2_addr == 6'h17; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_23_1 = io_write_1_valid & io_write_1_addr == 6'h17; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_23_0 = io_write_0_valid & io_write_0_addr == 6'h17; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_23_5 = io_write_5_valid & io_write_5_addr == 6'h17; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_23_4 = io_write_4_valid & io_write_4_addr == 6'h17; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_23_3 = io_write_3_valid & io_write_3_addr == 6'h17; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_488 = {wvalidBits_23_5,wvalidBits_23_4,wvalidBits_23_3,wvalidBits_23_2,wvalidBits_23_1,wvalidBits_23_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_495 = _T_488[1] + _T_488[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_118 = {{1'd0}, _T_488[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_497 = _GEN_118 + _T_495; // @[Bitwise.scala 48:55]
- wire [1:0] _T_499 = _T_488[4] + _T_488[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_119 = {{1'd0}, _T_488[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_501 = _GEN_119 + _T_499; // @[Bitwise.scala 48:55]
- wire [2:0] _T_503 = _T_497[1:0] + _T_501[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_23_0 = wvalidBits_23_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_23_1 = wvalidBits_23_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_23_2 = wvalidBits_23_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_23_3 = wvalidBits_23_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_23_4 = wvalidBits_23_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_23_5 = wvalidBits_23_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_23 = wvalidBits_23_0 | wvalidBits_23_1 | wvalidBits_23_2 | wvalidBits_23_3 | wvalidBits_23_4 |
- wvalidBits_23_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_116 = wdataBits_23_0 | wdataBits_23_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_117 = _wdata_T_116 | wdataBits_23_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_118 = _wdata_T_117 | wdataBits_23_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_119 = _wdata_T_118 | wdataBits_23_4; // @[Library.scala 76:39]
- wire [31:0] wdata_23 = _wdata_T_119 | wdataBits_23_5; // @[Library.scala 76:39]
- wire wvalidBits_24_2 = io_write_2_valid & io_write_2_addr == 6'h18; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_24_1 = io_write_1_valid & io_write_1_addr == 6'h18; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_24_0 = io_write_0_valid & io_write_0_addr == 6'h18; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_24_5 = io_write_5_valid & io_write_5_addr == 6'h18; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_24_4 = io_write_4_valid & io_write_4_addr == 6'h18; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_24_3 = io_write_3_valid & io_write_3_addr == 6'h18; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_509 = {wvalidBits_24_5,wvalidBits_24_4,wvalidBits_24_3,wvalidBits_24_2,wvalidBits_24_1,wvalidBits_24_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_516 = _T_509[1] + _T_509[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_120 = {{1'd0}, _T_509[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_518 = _GEN_120 + _T_516; // @[Bitwise.scala 48:55]
- wire [1:0] _T_520 = _T_509[4] + _T_509[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_121 = {{1'd0}, _T_509[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_522 = _GEN_121 + _T_520; // @[Bitwise.scala 48:55]
- wire [2:0] _T_524 = _T_518[1:0] + _T_522[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_24_0 = wvalidBits_24_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_24_1 = wvalidBits_24_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_24_2 = wvalidBits_24_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_24_3 = wvalidBits_24_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_24_4 = wvalidBits_24_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_24_5 = wvalidBits_24_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_24 = wvalidBits_24_0 | wvalidBits_24_1 | wvalidBits_24_2 | wvalidBits_24_3 | wvalidBits_24_4 |
- wvalidBits_24_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_121 = wdataBits_24_0 | wdataBits_24_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_122 = _wdata_T_121 | wdataBits_24_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_123 = _wdata_T_122 | wdataBits_24_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_124 = _wdata_T_123 | wdataBits_24_4; // @[Library.scala 76:39]
- wire [31:0] wdata_24 = _wdata_T_124 | wdataBits_24_5; // @[Library.scala 76:39]
- wire wvalidBits_25_2 = io_write_2_valid & io_write_2_addr == 6'h19; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_25_1 = io_write_1_valid & io_write_1_addr == 6'h19; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_25_0 = io_write_0_valid & io_write_0_addr == 6'h19; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_25_5 = io_write_5_valid & io_write_5_addr == 6'h19; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_25_4 = io_write_4_valid & io_write_4_addr == 6'h19; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_25_3 = io_write_3_valid & io_write_3_addr == 6'h19; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_530 = {wvalidBits_25_5,wvalidBits_25_4,wvalidBits_25_3,wvalidBits_25_2,wvalidBits_25_1,wvalidBits_25_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_537 = _T_530[1] + _T_530[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_122 = {{1'd0}, _T_530[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_539 = _GEN_122 + _T_537; // @[Bitwise.scala 48:55]
- wire [1:0] _T_541 = _T_530[4] + _T_530[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_123 = {{1'd0}, _T_530[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_543 = _GEN_123 + _T_541; // @[Bitwise.scala 48:55]
- wire [2:0] _T_545 = _T_539[1:0] + _T_543[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_25_0 = wvalidBits_25_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_25_1 = wvalidBits_25_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_25_2 = wvalidBits_25_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_25_3 = wvalidBits_25_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_25_4 = wvalidBits_25_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_25_5 = wvalidBits_25_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_25 = wvalidBits_25_0 | wvalidBits_25_1 | wvalidBits_25_2 | wvalidBits_25_3 | wvalidBits_25_4 |
- wvalidBits_25_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_126 = wdataBits_25_0 | wdataBits_25_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_127 = _wdata_T_126 | wdataBits_25_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_128 = _wdata_T_127 | wdataBits_25_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_129 = _wdata_T_128 | wdataBits_25_4; // @[Library.scala 76:39]
- wire [31:0] wdata_25 = _wdata_T_129 | wdataBits_25_5; // @[Library.scala 76:39]
- wire wvalidBits_26_2 = io_write_2_valid & io_write_2_addr == 6'h1a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_26_1 = io_write_1_valid & io_write_1_addr == 6'h1a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_26_0 = io_write_0_valid & io_write_0_addr == 6'h1a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_26_5 = io_write_5_valid & io_write_5_addr == 6'h1a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_26_4 = io_write_4_valid & io_write_4_addr == 6'h1a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_26_3 = io_write_3_valid & io_write_3_addr == 6'h1a; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_551 = {wvalidBits_26_5,wvalidBits_26_4,wvalidBits_26_3,wvalidBits_26_2,wvalidBits_26_1,wvalidBits_26_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_558 = _T_551[1] + _T_551[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_124 = {{1'd0}, _T_551[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_560 = _GEN_124 + _T_558; // @[Bitwise.scala 48:55]
- wire [1:0] _T_562 = _T_551[4] + _T_551[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_125 = {{1'd0}, _T_551[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_564 = _GEN_125 + _T_562; // @[Bitwise.scala 48:55]
- wire [2:0] _T_566 = _T_560[1:0] + _T_564[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_26_0 = wvalidBits_26_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_26_1 = wvalidBits_26_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_26_2 = wvalidBits_26_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_26_3 = wvalidBits_26_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_26_4 = wvalidBits_26_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_26_5 = wvalidBits_26_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_26 = wvalidBits_26_0 | wvalidBits_26_1 | wvalidBits_26_2 | wvalidBits_26_3 | wvalidBits_26_4 |
- wvalidBits_26_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_131 = wdataBits_26_0 | wdataBits_26_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_132 = _wdata_T_131 | wdataBits_26_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_133 = _wdata_T_132 | wdataBits_26_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_134 = _wdata_T_133 | wdataBits_26_4; // @[Library.scala 76:39]
- wire [31:0] wdata_26 = _wdata_T_134 | wdataBits_26_5; // @[Library.scala 76:39]
- wire wvalidBits_27_2 = io_write_2_valid & io_write_2_addr == 6'h1b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_27_1 = io_write_1_valid & io_write_1_addr == 6'h1b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_27_0 = io_write_0_valid & io_write_0_addr == 6'h1b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_27_5 = io_write_5_valid & io_write_5_addr == 6'h1b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_27_4 = io_write_4_valid & io_write_4_addr == 6'h1b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_27_3 = io_write_3_valid & io_write_3_addr == 6'h1b; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_572 = {wvalidBits_27_5,wvalidBits_27_4,wvalidBits_27_3,wvalidBits_27_2,wvalidBits_27_1,wvalidBits_27_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_579 = _T_572[1] + _T_572[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_126 = {{1'd0}, _T_572[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_581 = _GEN_126 + _T_579; // @[Bitwise.scala 48:55]
- wire [1:0] _T_583 = _T_572[4] + _T_572[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_127 = {{1'd0}, _T_572[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_585 = _GEN_127 + _T_583; // @[Bitwise.scala 48:55]
- wire [2:0] _T_587 = _T_581[1:0] + _T_585[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_27_0 = wvalidBits_27_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_27_1 = wvalidBits_27_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_27_2 = wvalidBits_27_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_27_3 = wvalidBits_27_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_27_4 = wvalidBits_27_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_27_5 = wvalidBits_27_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_27 = wvalidBits_27_0 | wvalidBits_27_1 | wvalidBits_27_2 | wvalidBits_27_3 | wvalidBits_27_4 |
- wvalidBits_27_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_136 = wdataBits_27_0 | wdataBits_27_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_137 = _wdata_T_136 | wdataBits_27_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_138 = _wdata_T_137 | wdataBits_27_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_139 = _wdata_T_138 | wdataBits_27_4; // @[Library.scala 76:39]
- wire [31:0] wdata_27 = _wdata_T_139 | wdataBits_27_5; // @[Library.scala 76:39]
- wire wvalidBits_28_2 = io_write_2_valid & io_write_2_addr == 6'h1c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_28_1 = io_write_1_valid & io_write_1_addr == 6'h1c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_28_0 = io_write_0_valid & io_write_0_addr == 6'h1c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_28_5 = io_write_5_valid & io_write_5_addr == 6'h1c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_28_4 = io_write_4_valid & io_write_4_addr == 6'h1c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_28_3 = io_write_3_valid & io_write_3_addr == 6'h1c; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_593 = {wvalidBits_28_5,wvalidBits_28_4,wvalidBits_28_3,wvalidBits_28_2,wvalidBits_28_1,wvalidBits_28_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_600 = _T_593[1] + _T_593[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_128 = {{1'd0}, _T_593[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_602 = _GEN_128 + _T_600; // @[Bitwise.scala 48:55]
- wire [1:0] _T_604 = _T_593[4] + _T_593[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_129 = {{1'd0}, _T_593[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_606 = _GEN_129 + _T_604; // @[Bitwise.scala 48:55]
- wire [2:0] _T_608 = _T_602[1:0] + _T_606[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_28_0 = wvalidBits_28_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_28_1 = wvalidBits_28_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_28_2 = wvalidBits_28_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_28_3 = wvalidBits_28_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_28_4 = wvalidBits_28_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_28_5 = wvalidBits_28_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_28 = wvalidBits_28_0 | wvalidBits_28_1 | wvalidBits_28_2 | wvalidBits_28_3 | wvalidBits_28_4 |
- wvalidBits_28_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_141 = wdataBits_28_0 | wdataBits_28_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_142 = _wdata_T_141 | wdataBits_28_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_143 = _wdata_T_142 | wdataBits_28_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_144 = _wdata_T_143 | wdataBits_28_4; // @[Library.scala 76:39]
- wire [31:0] wdata_28 = _wdata_T_144 | wdataBits_28_5; // @[Library.scala 76:39]
- wire wvalidBits_29_2 = io_write_2_valid & io_write_2_addr == 6'h1d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_29_1 = io_write_1_valid & io_write_1_addr == 6'h1d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_29_0 = io_write_0_valid & io_write_0_addr == 6'h1d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_29_5 = io_write_5_valid & io_write_5_addr == 6'h1d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_29_4 = io_write_4_valid & io_write_4_addr == 6'h1d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_29_3 = io_write_3_valid & io_write_3_addr == 6'h1d; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_614 = {wvalidBits_29_5,wvalidBits_29_4,wvalidBits_29_3,wvalidBits_29_2,wvalidBits_29_1,wvalidBits_29_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_621 = _T_614[1] + _T_614[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_130 = {{1'd0}, _T_614[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_623 = _GEN_130 + _T_621; // @[Bitwise.scala 48:55]
- wire [1:0] _T_625 = _T_614[4] + _T_614[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_131 = {{1'd0}, _T_614[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_627 = _GEN_131 + _T_625; // @[Bitwise.scala 48:55]
- wire [2:0] _T_629 = _T_623[1:0] + _T_627[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_29_0 = wvalidBits_29_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_29_1 = wvalidBits_29_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_29_2 = wvalidBits_29_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_29_3 = wvalidBits_29_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_29_4 = wvalidBits_29_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_29_5 = wvalidBits_29_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_29 = wvalidBits_29_0 | wvalidBits_29_1 | wvalidBits_29_2 | wvalidBits_29_3 | wvalidBits_29_4 |
- wvalidBits_29_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_146 = wdataBits_29_0 | wdataBits_29_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_147 = _wdata_T_146 | wdataBits_29_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_148 = _wdata_T_147 | wdataBits_29_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_149 = _wdata_T_148 | wdataBits_29_4; // @[Library.scala 76:39]
- wire [31:0] wdata_29 = _wdata_T_149 | wdataBits_29_5; // @[Library.scala 76:39]
- wire wvalidBits_30_2 = io_write_2_valid & io_write_2_addr == 6'h1e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_30_1 = io_write_1_valid & io_write_1_addr == 6'h1e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_30_0 = io_write_0_valid & io_write_0_addr == 6'h1e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_30_5 = io_write_5_valid & io_write_5_addr == 6'h1e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_30_4 = io_write_4_valid & io_write_4_addr == 6'h1e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_30_3 = io_write_3_valid & io_write_3_addr == 6'h1e; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_635 = {wvalidBits_30_5,wvalidBits_30_4,wvalidBits_30_3,wvalidBits_30_2,wvalidBits_30_1,wvalidBits_30_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_642 = _T_635[1] + _T_635[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_132 = {{1'd0}, _T_635[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_644 = _GEN_132 + _T_642; // @[Bitwise.scala 48:55]
- wire [1:0] _T_646 = _T_635[4] + _T_635[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_133 = {{1'd0}, _T_635[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_648 = _GEN_133 + _T_646; // @[Bitwise.scala 48:55]
- wire [2:0] _T_650 = _T_644[1:0] + _T_648[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_30_0 = wvalidBits_30_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_30_1 = wvalidBits_30_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_30_2 = wvalidBits_30_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_30_3 = wvalidBits_30_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_30_4 = wvalidBits_30_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_30_5 = wvalidBits_30_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_30 = wvalidBits_30_0 | wvalidBits_30_1 | wvalidBits_30_2 | wvalidBits_30_3 | wvalidBits_30_4 |
- wvalidBits_30_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_151 = wdataBits_30_0 | wdataBits_30_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_152 = _wdata_T_151 | wdataBits_30_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_153 = _wdata_T_152 | wdataBits_30_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_154 = _wdata_T_153 | wdataBits_30_4; // @[Library.scala 76:39]
- wire [31:0] wdata_30 = _wdata_T_154 | wdataBits_30_5; // @[Library.scala 76:39]
- wire wvalidBits_31_2 = io_write_2_valid & io_write_2_addr == 6'h1f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_31_1 = io_write_1_valid & io_write_1_addr == 6'h1f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_31_0 = io_write_0_valid & io_write_0_addr == 6'h1f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_31_5 = io_write_5_valid & io_write_5_addr == 6'h1f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_31_4 = io_write_4_valid & io_write_4_addr == 6'h1f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_31_3 = io_write_3_valid & io_write_3_addr == 6'h1f; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_656 = {wvalidBits_31_5,wvalidBits_31_4,wvalidBits_31_3,wvalidBits_31_2,wvalidBits_31_1,wvalidBits_31_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_663 = _T_656[1] + _T_656[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_134 = {{1'd0}, _T_656[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_665 = _GEN_134 + _T_663; // @[Bitwise.scala 48:55]
- wire [1:0] _T_667 = _T_656[4] + _T_656[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_135 = {{1'd0}, _T_656[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_669 = _GEN_135 + _T_667; // @[Bitwise.scala 48:55]
- wire [2:0] _T_671 = _T_665[1:0] + _T_669[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_31_0 = wvalidBits_31_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_31_1 = wvalidBits_31_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_31_2 = wvalidBits_31_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_31_3 = wvalidBits_31_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_31_4 = wvalidBits_31_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_31_5 = wvalidBits_31_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_31 = wvalidBits_31_0 | wvalidBits_31_1 | wvalidBits_31_2 | wvalidBits_31_3 | wvalidBits_31_4 |
- wvalidBits_31_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_156 = wdataBits_31_0 | wdataBits_31_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_157 = _wdata_T_156 | wdataBits_31_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_158 = _wdata_T_157 | wdataBits_31_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_159 = _wdata_T_158 | wdataBits_31_4; // @[Library.scala 76:39]
- wire [31:0] wdata_31 = _wdata_T_159 | wdataBits_31_5; // @[Library.scala 76:39]
- wire wvalidBits_32_2 = io_write_2_valid & io_write_2_addr == 6'h20; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_32_1 = io_write_1_valid & io_write_1_addr == 6'h20; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_32_0 = io_write_0_valid & io_write_0_addr == 6'h20; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_32_5 = io_write_5_valid & io_write_5_addr == 6'h20; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_32_4 = io_write_4_valid & io_write_4_addr == 6'h20; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_32_3 = io_write_3_valid & io_write_3_addr == 6'h20; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_677 = {wvalidBits_32_5,wvalidBits_32_4,wvalidBits_32_3,wvalidBits_32_2,wvalidBits_32_1,wvalidBits_32_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_684 = _T_677[1] + _T_677[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_136 = {{1'd0}, _T_677[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_686 = _GEN_136 + _T_684; // @[Bitwise.scala 48:55]
- wire [1:0] _T_688 = _T_677[4] + _T_677[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_137 = {{1'd0}, _T_677[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_690 = _GEN_137 + _T_688; // @[Bitwise.scala 48:55]
- wire [2:0] _T_692 = _T_686[1:0] + _T_690[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_32_0 = wvalidBits_32_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_32_1 = wvalidBits_32_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_32_2 = wvalidBits_32_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_32_3 = wvalidBits_32_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_32_4 = wvalidBits_32_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_32_5 = wvalidBits_32_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_32 = wvalidBits_32_0 | wvalidBits_32_1 | wvalidBits_32_2 | wvalidBits_32_3 | wvalidBits_32_4 |
- wvalidBits_32_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_161 = wdataBits_32_0 | wdataBits_32_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_162 = _wdata_T_161 | wdataBits_32_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_163 = _wdata_T_162 | wdataBits_32_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_164 = _wdata_T_163 | wdataBits_32_4; // @[Library.scala 76:39]
- wire [31:0] wdata_32 = _wdata_T_164 | wdataBits_32_5; // @[Library.scala 76:39]
- wire wvalidBits_33_2 = io_write_2_valid & io_write_2_addr == 6'h21; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_33_1 = io_write_1_valid & io_write_1_addr == 6'h21; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_33_0 = io_write_0_valid & io_write_0_addr == 6'h21; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_33_5 = io_write_5_valid & io_write_5_addr == 6'h21; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_33_4 = io_write_4_valid & io_write_4_addr == 6'h21; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_33_3 = io_write_3_valid & io_write_3_addr == 6'h21; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_698 = {wvalidBits_33_5,wvalidBits_33_4,wvalidBits_33_3,wvalidBits_33_2,wvalidBits_33_1,wvalidBits_33_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_705 = _T_698[1] + _T_698[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_138 = {{1'd0}, _T_698[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_707 = _GEN_138 + _T_705; // @[Bitwise.scala 48:55]
- wire [1:0] _T_709 = _T_698[4] + _T_698[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_139 = {{1'd0}, _T_698[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_711 = _GEN_139 + _T_709; // @[Bitwise.scala 48:55]
- wire [2:0] _T_713 = _T_707[1:0] + _T_711[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_33_0 = wvalidBits_33_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_33_1 = wvalidBits_33_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_33_2 = wvalidBits_33_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_33_3 = wvalidBits_33_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_33_4 = wvalidBits_33_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_33_5 = wvalidBits_33_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_33 = wvalidBits_33_0 | wvalidBits_33_1 | wvalidBits_33_2 | wvalidBits_33_3 | wvalidBits_33_4 |
- wvalidBits_33_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_166 = wdataBits_33_0 | wdataBits_33_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_167 = _wdata_T_166 | wdataBits_33_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_168 = _wdata_T_167 | wdataBits_33_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_169 = _wdata_T_168 | wdataBits_33_4; // @[Library.scala 76:39]
- wire [31:0] wdata_33 = _wdata_T_169 | wdataBits_33_5; // @[Library.scala 76:39]
- wire wvalidBits_34_2 = io_write_2_valid & io_write_2_addr == 6'h22; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_34_1 = io_write_1_valid & io_write_1_addr == 6'h22; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_34_0 = io_write_0_valid & io_write_0_addr == 6'h22; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_34_5 = io_write_5_valid & io_write_5_addr == 6'h22; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_34_4 = io_write_4_valid & io_write_4_addr == 6'h22; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_34_3 = io_write_3_valid & io_write_3_addr == 6'h22; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_719 = {wvalidBits_34_5,wvalidBits_34_4,wvalidBits_34_3,wvalidBits_34_2,wvalidBits_34_1,wvalidBits_34_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_726 = _T_719[1] + _T_719[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_140 = {{1'd0}, _T_719[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_728 = _GEN_140 + _T_726; // @[Bitwise.scala 48:55]
- wire [1:0] _T_730 = _T_719[4] + _T_719[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_141 = {{1'd0}, _T_719[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_732 = _GEN_141 + _T_730; // @[Bitwise.scala 48:55]
- wire [2:0] _T_734 = _T_728[1:0] + _T_732[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_34_0 = wvalidBits_34_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_34_1 = wvalidBits_34_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_34_2 = wvalidBits_34_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_34_3 = wvalidBits_34_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_34_4 = wvalidBits_34_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_34_5 = wvalidBits_34_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_34 = wvalidBits_34_0 | wvalidBits_34_1 | wvalidBits_34_2 | wvalidBits_34_3 | wvalidBits_34_4 |
- wvalidBits_34_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_171 = wdataBits_34_0 | wdataBits_34_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_172 = _wdata_T_171 | wdataBits_34_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_173 = _wdata_T_172 | wdataBits_34_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_174 = _wdata_T_173 | wdataBits_34_4; // @[Library.scala 76:39]
- wire [31:0] wdata_34 = _wdata_T_174 | wdataBits_34_5; // @[Library.scala 76:39]
- wire wvalidBits_35_2 = io_write_2_valid & io_write_2_addr == 6'h23; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_35_1 = io_write_1_valid & io_write_1_addr == 6'h23; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_35_0 = io_write_0_valid & io_write_0_addr == 6'h23; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_35_5 = io_write_5_valid & io_write_5_addr == 6'h23; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_35_4 = io_write_4_valid & io_write_4_addr == 6'h23; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_35_3 = io_write_3_valid & io_write_3_addr == 6'h23; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_740 = {wvalidBits_35_5,wvalidBits_35_4,wvalidBits_35_3,wvalidBits_35_2,wvalidBits_35_1,wvalidBits_35_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_747 = _T_740[1] + _T_740[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_142 = {{1'd0}, _T_740[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_749 = _GEN_142 + _T_747; // @[Bitwise.scala 48:55]
- wire [1:0] _T_751 = _T_740[4] + _T_740[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_143 = {{1'd0}, _T_740[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_753 = _GEN_143 + _T_751; // @[Bitwise.scala 48:55]
- wire [2:0] _T_755 = _T_749[1:0] + _T_753[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_35_0 = wvalidBits_35_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_35_1 = wvalidBits_35_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_35_2 = wvalidBits_35_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_35_3 = wvalidBits_35_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_35_4 = wvalidBits_35_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_35_5 = wvalidBits_35_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_35 = wvalidBits_35_0 | wvalidBits_35_1 | wvalidBits_35_2 | wvalidBits_35_3 | wvalidBits_35_4 |
- wvalidBits_35_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_176 = wdataBits_35_0 | wdataBits_35_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_177 = _wdata_T_176 | wdataBits_35_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_178 = _wdata_T_177 | wdataBits_35_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_179 = _wdata_T_178 | wdataBits_35_4; // @[Library.scala 76:39]
- wire [31:0] wdata_35 = _wdata_T_179 | wdataBits_35_5; // @[Library.scala 76:39]
- wire wvalidBits_36_2 = io_write_2_valid & io_write_2_addr == 6'h24; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_36_1 = io_write_1_valid & io_write_1_addr == 6'h24; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_36_0 = io_write_0_valid & io_write_0_addr == 6'h24; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_36_5 = io_write_5_valid & io_write_5_addr == 6'h24; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_36_4 = io_write_4_valid & io_write_4_addr == 6'h24; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_36_3 = io_write_3_valid & io_write_3_addr == 6'h24; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_761 = {wvalidBits_36_5,wvalidBits_36_4,wvalidBits_36_3,wvalidBits_36_2,wvalidBits_36_1,wvalidBits_36_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_768 = _T_761[1] + _T_761[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_144 = {{1'd0}, _T_761[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_770 = _GEN_144 + _T_768; // @[Bitwise.scala 48:55]
- wire [1:0] _T_772 = _T_761[4] + _T_761[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_145 = {{1'd0}, _T_761[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_774 = _GEN_145 + _T_772; // @[Bitwise.scala 48:55]
- wire [2:0] _T_776 = _T_770[1:0] + _T_774[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_36_0 = wvalidBits_36_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_36_1 = wvalidBits_36_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_36_2 = wvalidBits_36_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_36_3 = wvalidBits_36_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_36_4 = wvalidBits_36_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_36_5 = wvalidBits_36_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_36 = wvalidBits_36_0 | wvalidBits_36_1 | wvalidBits_36_2 | wvalidBits_36_3 | wvalidBits_36_4 |
- wvalidBits_36_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_181 = wdataBits_36_0 | wdataBits_36_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_182 = _wdata_T_181 | wdataBits_36_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_183 = _wdata_T_182 | wdataBits_36_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_184 = _wdata_T_183 | wdataBits_36_4; // @[Library.scala 76:39]
- wire [31:0] wdata_36 = _wdata_T_184 | wdataBits_36_5; // @[Library.scala 76:39]
- wire wvalidBits_37_2 = io_write_2_valid & io_write_2_addr == 6'h25; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_37_1 = io_write_1_valid & io_write_1_addr == 6'h25; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_37_0 = io_write_0_valid & io_write_0_addr == 6'h25; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_37_5 = io_write_5_valid & io_write_5_addr == 6'h25; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_37_4 = io_write_4_valid & io_write_4_addr == 6'h25; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_37_3 = io_write_3_valid & io_write_3_addr == 6'h25; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_782 = {wvalidBits_37_5,wvalidBits_37_4,wvalidBits_37_3,wvalidBits_37_2,wvalidBits_37_1,wvalidBits_37_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_789 = _T_782[1] + _T_782[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_146 = {{1'd0}, _T_782[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_791 = _GEN_146 + _T_789; // @[Bitwise.scala 48:55]
- wire [1:0] _T_793 = _T_782[4] + _T_782[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_147 = {{1'd0}, _T_782[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_795 = _GEN_147 + _T_793; // @[Bitwise.scala 48:55]
- wire [2:0] _T_797 = _T_791[1:0] + _T_795[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_37_0 = wvalidBits_37_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_37_1 = wvalidBits_37_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_37_2 = wvalidBits_37_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_37_3 = wvalidBits_37_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_37_4 = wvalidBits_37_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_37_5 = wvalidBits_37_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_37 = wvalidBits_37_0 | wvalidBits_37_1 | wvalidBits_37_2 | wvalidBits_37_3 | wvalidBits_37_4 |
- wvalidBits_37_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_186 = wdataBits_37_0 | wdataBits_37_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_187 = _wdata_T_186 | wdataBits_37_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_188 = _wdata_T_187 | wdataBits_37_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_189 = _wdata_T_188 | wdataBits_37_4; // @[Library.scala 76:39]
- wire [31:0] wdata_37 = _wdata_T_189 | wdataBits_37_5; // @[Library.scala 76:39]
- wire wvalidBits_38_2 = io_write_2_valid & io_write_2_addr == 6'h26; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_38_1 = io_write_1_valid & io_write_1_addr == 6'h26; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_38_0 = io_write_0_valid & io_write_0_addr == 6'h26; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_38_5 = io_write_5_valid & io_write_5_addr == 6'h26; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_38_4 = io_write_4_valid & io_write_4_addr == 6'h26; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_38_3 = io_write_3_valid & io_write_3_addr == 6'h26; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_803 = {wvalidBits_38_5,wvalidBits_38_4,wvalidBits_38_3,wvalidBits_38_2,wvalidBits_38_1,wvalidBits_38_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_810 = _T_803[1] + _T_803[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_148 = {{1'd0}, _T_803[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_812 = _GEN_148 + _T_810; // @[Bitwise.scala 48:55]
- wire [1:0] _T_814 = _T_803[4] + _T_803[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_149 = {{1'd0}, _T_803[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_816 = _GEN_149 + _T_814; // @[Bitwise.scala 48:55]
- wire [2:0] _T_818 = _T_812[1:0] + _T_816[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_38_0 = wvalidBits_38_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_38_1 = wvalidBits_38_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_38_2 = wvalidBits_38_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_38_3 = wvalidBits_38_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_38_4 = wvalidBits_38_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_38_5 = wvalidBits_38_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_38 = wvalidBits_38_0 | wvalidBits_38_1 | wvalidBits_38_2 | wvalidBits_38_3 | wvalidBits_38_4 |
- wvalidBits_38_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_191 = wdataBits_38_0 | wdataBits_38_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_192 = _wdata_T_191 | wdataBits_38_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_193 = _wdata_T_192 | wdataBits_38_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_194 = _wdata_T_193 | wdataBits_38_4; // @[Library.scala 76:39]
- wire [31:0] wdata_38 = _wdata_T_194 | wdataBits_38_5; // @[Library.scala 76:39]
- wire wvalidBits_39_2 = io_write_2_valid & io_write_2_addr == 6'h27; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_39_1 = io_write_1_valid & io_write_1_addr == 6'h27; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_39_0 = io_write_0_valid & io_write_0_addr == 6'h27; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_39_5 = io_write_5_valid & io_write_5_addr == 6'h27; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_39_4 = io_write_4_valid & io_write_4_addr == 6'h27; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_39_3 = io_write_3_valid & io_write_3_addr == 6'h27; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_824 = {wvalidBits_39_5,wvalidBits_39_4,wvalidBits_39_3,wvalidBits_39_2,wvalidBits_39_1,wvalidBits_39_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_831 = _T_824[1] + _T_824[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_150 = {{1'd0}, _T_824[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_833 = _GEN_150 + _T_831; // @[Bitwise.scala 48:55]
- wire [1:0] _T_835 = _T_824[4] + _T_824[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_151 = {{1'd0}, _T_824[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_837 = _GEN_151 + _T_835; // @[Bitwise.scala 48:55]
- wire [2:0] _T_839 = _T_833[1:0] + _T_837[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_39_0 = wvalidBits_39_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_39_1 = wvalidBits_39_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_39_2 = wvalidBits_39_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_39_3 = wvalidBits_39_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_39_4 = wvalidBits_39_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_39_5 = wvalidBits_39_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_39 = wvalidBits_39_0 | wvalidBits_39_1 | wvalidBits_39_2 | wvalidBits_39_3 | wvalidBits_39_4 |
- wvalidBits_39_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_196 = wdataBits_39_0 | wdataBits_39_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_197 = _wdata_T_196 | wdataBits_39_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_198 = _wdata_T_197 | wdataBits_39_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_199 = _wdata_T_198 | wdataBits_39_4; // @[Library.scala 76:39]
- wire [31:0] wdata_39 = _wdata_T_199 | wdataBits_39_5; // @[Library.scala 76:39]
- wire wvalidBits_40_2 = io_write_2_valid & io_write_2_addr == 6'h28; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_40_1 = io_write_1_valid & io_write_1_addr == 6'h28; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_40_0 = io_write_0_valid & io_write_0_addr == 6'h28; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_40_5 = io_write_5_valid & io_write_5_addr == 6'h28; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_40_4 = io_write_4_valid & io_write_4_addr == 6'h28; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_40_3 = io_write_3_valid & io_write_3_addr == 6'h28; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_845 = {wvalidBits_40_5,wvalidBits_40_4,wvalidBits_40_3,wvalidBits_40_2,wvalidBits_40_1,wvalidBits_40_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_852 = _T_845[1] + _T_845[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_152 = {{1'd0}, _T_845[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_854 = _GEN_152 + _T_852; // @[Bitwise.scala 48:55]
- wire [1:0] _T_856 = _T_845[4] + _T_845[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_153 = {{1'd0}, _T_845[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_858 = _GEN_153 + _T_856; // @[Bitwise.scala 48:55]
- wire [2:0] _T_860 = _T_854[1:0] + _T_858[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_40_0 = wvalidBits_40_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_40_1 = wvalidBits_40_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_40_2 = wvalidBits_40_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_40_3 = wvalidBits_40_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_40_4 = wvalidBits_40_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_40_5 = wvalidBits_40_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_40 = wvalidBits_40_0 | wvalidBits_40_1 | wvalidBits_40_2 | wvalidBits_40_3 | wvalidBits_40_4 |
- wvalidBits_40_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_201 = wdataBits_40_0 | wdataBits_40_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_202 = _wdata_T_201 | wdataBits_40_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_203 = _wdata_T_202 | wdataBits_40_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_204 = _wdata_T_203 | wdataBits_40_4; // @[Library.scala 76:39]
- wire [31:0] wdata_40 = _wdata_T_204 | wdataBits_40_5; // @[Library.scala 76:39]
- wire wvalidBits_41_2 = io_write_2_valid & io_write_2_addr == 6'h29; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_41_1 = io_write_1_valid & io_write_1_addr == 6'h29; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_41_0 = io_write_0_valid & io_write_0_addr == 6'h29; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_41_5 = io_write_5_valid & io_write_5_addr == 6'h29; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_41_4 = io_write_4_valid & io_write_4_addr == 6'h29; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_41_3 = io_write_3_valid & io_write_3_addr == 6'h29; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_866 = {wvalidBits_41_5,wvalidBits_41_4,wvalidBits_41_3,wvalidBits_41_2,wvalidBits_41_1,wvalidBits_41_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_873 = _T_866[1] + _T_866[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_154 = {{1'd0}, _T_866[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_875 = _GEN_154 + _T_873; // @[Bitwise.scala 48:55]
- wire [1:0] _T_877 = _T_866[4] + _T_866[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_155 = {{1'd0}, _T_866[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_879 = _GEN_155 + _T_877; // @[Bitwise.scala 48:55]
- wire [2:0] _T_881 = _T_875[1:0] + _T_879[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_41_0 = wvalidBits_41_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_41_1 = wvalidBits_41_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_41_2 = wvalidBits_41_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_41_3 = wvalidBits_41_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_41_4 = wvalidBits_41_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_41_5 = wvalidBits_41_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_41 = wvalidBits_41_0 | wvalidBits_41_1 | wvalidBits_41_2 | wvalidBits_41_3 | wvalidBits_41_4 |
- wvalidBits_41_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_206 = wdataBits_41_0 | wdataBits_41_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_207 = _wdata_T_206 | wdataBits_41_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_208 = _wdata_T_207 | wdataBits_41_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_209 = _wdata_T_208 | wdataBits_41_4; // @[Library.scala 76:39]
- wire [31:0] wdata_41 = _wdata_T_209 | wdataBits_41_5; // @[Library.scala 76:39]
- wire wvalidBits_42_2 = io_write_2_valid & io_write_2_addr == 6'h2a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_42_1 = io_write_1_valid & io_write_1_addr == 6'h2a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_42_0 = io_write_0_valid & io_write_0_addr == 6'h2a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_42_5 = io_write_5_valid & io_write_5_addr == 6'h2a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_42_4 = io_write_4_valid & io_write_4_addr == 6'h2a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_42_3 = io_write_3_valid & io_write_3_addr == 6'h2a; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_887 = {wvalidBits_42_5,wvalidBits_42_4,wvalidBits_42_3,wvalidBits_42_2,wvalidBits_42_1,wvalidBits_42_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_894 = _T_887[1] + _T_887[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_156 = {{1'd0}, _T_887[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_896 = _GEN_156 + _T_894; // @[Bitwise.scala 48:55]
- wire [1:0] _T_898 = _T_887[4] + _T_887[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_157 = {{1'd0}, _T_887[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_900 = _GEN_157 + _T_898; // @[Bitwise.scala 48:55]
- wire [2:0] _T_902 = _T_896[1:0] + _T_900[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_42_0 = wvalidBits_42_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_42_1 = wvalidBits_42_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_42_2 = wvalidBits_42_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_42_3 = wvalidBits_42_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_42_4 = wvalidBits_42_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_42_5 = wvalidBits_42_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_42 = wvalidBits_42_0 | wvalidBits_42_1 | wvalidBits_42_2 | wvalidBits_42_3 | wvalidBits_42_4 |
- wvalidBits_42_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_211 = wdataBits_42_0 | wdataBits_42_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_212 = _wdata_T_211 | wdataBits_42_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_213 = _wdata_T_212 | wdataBits_42_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_214 = _wdata_T_213 | wdataBits_42_4; // @[Library.scala 76:39]
- wire [31:0] wdata_42 = _wdata_T_214 | wdataBits_42_5; // @[Library.scala 76:39]
- wire wvalidBits_43_2 = io_write_2_valid & io_write_2_addr == 6'h2b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_43_1 = io_write_1_valid & io_write_1_addr == 6'h2b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_43_0 = io_write_0_valid & io_write_0_addr == 6'h2b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_43_5 = io_write_5_valid & io_write_5_addr == 6'h2b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_43_4 = io_write_4_valid & io_write_4_addr == 6'h2b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_43_3 = io_write_3_valid & io_write_3_addr == 6'h2b; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_908 = {wvalidBits_43_5,wvalidBits_43_4,wvalidBits_43_3,wvalidBits_43_2,wvalidBits_43_1,wvalidBits_43_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_915 = _T_908[1] + _T_908[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_158 = {{1'd0}, _T_908[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_917 = _GEN_158 + _T_915; // @[Bitwise.scala 48:55]
- wire [1:0] _T_919 = _T_908[4] + _T_908[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_159 = {{1'd0}, _T_908[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_921 = _GEN_159 + _T_919; // @[Bitwise.scala 48:55]
- wire [2:0] _T_923 = _T_917[1:0] + _T_921[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_43_0 = wvalidBits_43_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_43_1 = wvalidBits_43_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_43_2 = wvalidBits_43_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_43_3 = wvalidBits_43_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_43_4 = wvalidBits_43_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_43_5 = wvalidBits_43_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_43 = wvalidBits_43_0 | wvalidBits_43_1 | wvalidBits_43_2 | wvalidBits_43_3 | wvalidBits_43_4 |
- wvalidBits_43_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_216 = wdataBits_43_0 | wdataBits_43_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_217 = _wdata_T_216 | wdataBits_43_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_218 = _wdata_T_217 | wdataBits_43_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_219 = _wdata_T_218 | wdataBits_43_4; // @[Library.scala 76:39]
- wire [31:0] wdata_43 = _wdata_T_219 | wdataBits_43_5; // @[Library.scala 76:39]
- wire wvalidBits_44_2 = io_write_2_valid & io_write_2_addr == 6'h2c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_44_1 = io_write_1_valid & io_write_1_addr == 6'h2c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_44_0 = io_write_0_valid & io_write_0_addr == 6'h2c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_44_5 = io_write_5_valid & io_write_5_addr == 6'h2c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_44_4 = io_write_4_valid & io_write_4_addr == 6'h2c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_44_3 = io_write_3_valid & io_write_3_addr == 6'h2c; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_929 = {wvalidBits_44_5,wvalidBits_44_4,wvalidBits_44_3,wvalidBits_44_2,wvalidBits_44_1,wvalidBits_44_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_936 = _T_929[1] + _T_929[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_160 = {{1'd0}, _T_929[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_938 = _GEN_160 + _T_936; // @[Bitwise.scala 48:55]
- wire [1:0] _T_940 = _T_929[4] + _T_929[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_161 = {{1'd0}, _T_929[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_942 = _GEN_161 + _T_940; // @[Bitwise.scala 48:55]
- wire [2:0] _T_944 = _T_938[1:0] + _T_942[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_44_0 = wvalidBits_44_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_44_1 = wvalidBits_44_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_44_2 = wvalidBits_44_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_44_3 = wvalidBits_44_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_44_4 = wvalidBits_44_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_44_5 = wvalidBits_44_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_44 = wvalidBits_44_0 | wvalidBits_44_1 | wvalidBits_44_2 | wvalidBits_44_3 | wvalidBits_44_4 |
- wvalidBits_44_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_221 = wdataBits_44_0 | wdataBits_44_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_222 = _wdata_T_221 | wdataBits_44_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_223 = _wdata_T_222 | wdataBits_44_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_224 = _wdata_T_223 | wdataBits_44_4; // @[Library.scala 76:39]
- wire [31:0] wdata_44 = _wdata_T_224 | wdataBits_44_5; // @[Library.scala 76:39]
- wire wvalidBits_45_2 = io_write_2_valid & io_write_2_addr == 6'h2d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_45_1 = io_write_1_valid & io_write_1_addr == 6'h2d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_45_0 = io_write_0_valid & io_write_0_addr == 6'h2d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_45_5 = io_write_5_valid & io_write_5_addr == 6'h2d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_45_4 = io_write_4_valid & io_write_4_addr == 6'h2d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_45_3 = io_write_3_valid & io_write_3_addr == 6'h2d; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_950 = {wvalidBits_45_5,wvalidBits_45_4,wvalidBits_45_3,wvalidBits_45_2,wvalidBits_45_1,wvalidBits_45_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_957 = _T_950[1] + _T_950[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_162 = {{1'd0}, _T_950[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_959 = _GEN_162 + _T_957; // @[Bitwise.scala 48:55]
- wire [1:0] _T_961 = _T_950[4] + _T_950[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_163 = {{1'd0}, _T_950[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_963 = _GEN_163 + _T_961; // @[Bitwise.scala 48:55]
- wire [2:0] _T_965 = _T_959[1:0] + _T_963[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_45_0 = wvalidBits_45_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_45_1 = wvalidBits_45_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_45_2 = wvalidBits_45_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_45_3 = wvalidBits_45_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_45_4 = wvalidBits_45_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_45_5 = wvalidBits_45_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_45 = wvalidBits_45_0 | wvalidBits_45_1 | wvalidBits_45_2 | wvalidBits_45_3 | wvalidBits_45_4 |
- wvalidBits_45_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_226 = wdataBits_45_0 | wdataBits_45_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_227 = _wdata_T_226 | wdataBits_45_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_228 = _wdata_T_227 | wdataBits_45_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_229 = _wdata_T_228 | wdataBits_45_4; // @[Library.scala 76:39]
- wire [31:0] wdata_45 = _wdata_T_229 | wdataBits_45_5; // @[Library.scala 76:39]
- wire wvalidBits_46_2 = io_write_2_valid & io_write_2_addr == 6'h2e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_46_1 = io_write_1_valid & io_write_1_addr == 6'h2e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_46_0 = io_write_0_valid & io_write_0_addr == 6'h2e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_46_5 = io_write_5_valid & io_write_5_addr == 6'h2e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_46_4 = io_write_4_valid & io_write_4_addr == 6'h2e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_46_3 = io_write_3_valid & io_write_3_addr == 6'h2e; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_971 = {wvalidBits_46_5,wvalidBits_46_4,wvalidBits_46_3,wvalidBits_46_2,wvalidBits_46_1,wvalidBits_46_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_978 = _T_971[1] + _T_971[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_164 = {{1'd0}, _T_971[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_980 = _GEN_164 + _T_978; // @[Bitwise.scala 48:55]
- wire [1:0] _T_982 = _T_971[4] + _T_971[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_165 = {{1'd0}, _T_971[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_984 = _GEN_165 + _T_982; // @[Bitwise.scala 48:55]
- wire [2:0] _T_986 = _T_980[1:0] + _T_984[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_46_0 = wvalidBits_46_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_46_1 = wvalidBits_46_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_46_2 = wvalidBits_46_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_46_3 = wvalidBits_46_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_46_4 = wvalidBits_46_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_46_5 = wvalidBits_46_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_46 = wvalidBits_46_0 | wvalidBits_46_1 | wvalidBits_46_2 | wvalidBits_46_3 | wvalidBits_46_4 |
- wvalidBits_46_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_231 = wdataBits_46_0 | wdataBits_46_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_232 = _wdata_T_231 | wdataBits_46_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_233 = _wdata_T_232 | wdataBits_46_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_234 = _wdata_T_233 | wdataBits_46_4; // @[Library.scala 76:39]
- wire [31:0] wdata_46 = _wdata_T_234 | wdataBits_46_5; // @[Library.scala 76:39]
- wire wvalidBits_47_2 = io_write_2_valid & io_write_2_addr == 6'h2f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_47_1 = io_write_1_valid & io_write_1_addr == 6'h2f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_47_0 = io_write_0_valid & io_write_0_addr == 6'h2f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_47_5 = io_write_5_valid & io_write_5_addr == 6'h2f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_47_4 = io_write_4_valid & io_write_4_addr == 6'h2f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_47_3 = io_write_3_valid & io_write_3_addr == 6'h2f; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_992 = {wvalidBits_47_5,wvalidBits_47_4,wvalidBits_47_3,wvalidBits_47_2,wvalidBits_47_1,wvalidBits_47_0}; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_999 = _T_992[1] + _T_992[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_166 = {{1'd0}, _T_992[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1001 = _GEN_166 + _T_999; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1003 = _T_992[4] + _T_992[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_167 = {{1'd0}, _T_992[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1005 = _GEN_167 + _T_1003; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1007 = _T_1001[1:0] + _T_1005[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_47_0 = wvalidBits_47_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_47_1 = wvalidBits_47_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_47_2 = wvalidBits_47_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_47_3 = wvalidBits_47_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_47_4 = wvalidBits_47_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_47_5 = wvalidBits_47_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_47 = wvalidBits_47_0 | wvalidBits_47_1 | wvalidBits_47_2 | wvalidBits_47_3 | wvalidBits_47_4 |
- wvalidBits_47_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_236 = wdataBits_47_0 | wdataBits_47_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_237 = _wdata_T_236 | wdataBits_47_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_238 = _wdata_T_237 | wdataBits_47_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_239 = _wdata_T_238 | wdataBits_47_4; // @[Library.scala 76:39]
- wire [31:0] wdata_47 = _wdata_T_239 | wdataBits_47_5; // @[Library.scala 76:39]
- wire wvalidBits_48_2 = io_write_2_valid & io_write_2_addr == 6'h30; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_48_1 = io_write_1_valid & io_write_1_addr == 6'h30; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_48_0 = io_write_0_valid & io_write_0_addr == 6'h30; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_48_5 = io_write_5_valid & io_write_5_addr == 6'h30; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_48_4 = io_write_4_valid & io_write_4_addr == 6'h30; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_48_3 = io_write_3_valid & io_write_3_addr == 6'h30; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1013 = {wvalidBits_48_5,wvalidBits_48_4,wvalidBits_48_3,wvalidBits_48_2,wvalidBits_48_1,wvalidBits_48_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1020 = _T_1013[1] + _T_1013[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_168 = {{1'd0}, _T_1013[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1022 = _GEN_168 + _T_1020; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1024 = _T_1013[4] + _T_1013[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_169 = {{1'd0}, _T_1013[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1026 = _GEN_169 + _T_1024; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1028 = _T_1022[1:0] + _T_1026[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_48_0 = wvalidBits_48_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_48_1 = wvalidBits_48_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_48_2 = wvalidBits_48_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_48_3 = wvalidBits_48_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_48_4 = wvalidBits_48_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_48_5 = wvalidBits_48_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_48 = wvalidBits_48_0 | wvalidBits_48_1 | wvalidBits_48_2 | wvalidBits_48_3 | wvalidBits_48_4 |
- wvalidBits_48_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_241 = wdataBits_48_0 | wdataBits_48_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_242 = _wdata_T_241 | wdataBits_48_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_243 = _wdata_T_242 | wdataBits_48_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_244 = _wdata_T_243 | wdataBits_48_4; // @[Library.scala 76:39]
- wire [31:0] wdata_48 = _wdata_T_244 | wdataBits_48_5; // @[Library.scala 76:39]
- wire wvalidBits_49_2 = io_write_2_valid & io_write_2_addr == 6'h31; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_49_1 = io_write_1_valid & io_write_1_addr == 6'h31; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_49_0 = io_write_0_valid & io_write_0_addr == 6'h31; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_49_5 = io_write_5_valid & io_write_5_addr == 6'h31; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_49_4 = io_write_4_valid & io_write_4_addr == 6'h31; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_49_3 = io_write_3_valid & io_write_3_addr == 6'h31; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1034 = {wvalidBits_49_5,wvalidBits_49_4,wvalidBits_49_3,wvalidBits_49_2,wvalidBits_49_1,wvalidBits_49_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1041 = _T_1034[1] + _T_1034[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_170 = {{1'd0}, _T_1034[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1043 = _GEN_170 + _T_1041; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1045 = _T_1034[4] + _T_1034[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_171 = {{1'd0}, _T_1034[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1047 = _GEN_171 + _T_1045; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1049 = _T_1043[1:0] + _T_1047[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_49_0 = wvalidBits_49_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_49_1 = wvalidBits_49_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_49_2 = wvalidBits_49_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_49_3 = wvalidBits_49_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_49_4 = wvalidBits_49_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_49_5 = wvalidBits_49_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_49 = wvalidBits_49_0 | wvalidBits_49_1 | wvalidBits_49_2 | wvalidBits_49_3 | wvalidBits_49_4 |
- wvalidBits_49_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_246 = wdataBits_49_0 | wdataBits_49_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_247 = _wdata_T_246 | wdataBits_49_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_248 = _wdata_T_247 | wdataBits_49_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_249 = _wdata_T_248 | wdataBits_49_4; // @[Library.scala 76:39]
- wire [31:0] wdata_49 = _wdata_T_249 | wdataBits_49_5; // @[Library.scala 76:39]
- wire wvalidBits_50_2 = io_write_2_valid & io_write_2_addr == 6'h32; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_50_1 = io_write_1_valid & io_write_1_addr == 6'h32; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_50_0 = io_write_0_valid & io_write_0_addr == 6'h32; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_50_5 = io_write_5_valid & io_write_5_addr == 6'h32; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_50_4 = io_write_4_valid & io_write_4_addr == 6'h32; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_50_3 = io_write_3_valid & io_write_3_addr == 6'h32; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1055 = {wvalidBits_50_5,wvalidBits_50_4,wvalidBits_50_3,wvalidBits_50_2,wvalidBits_50_1,wvalidBits_50_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1062 = _T_1055[1] + _T_1055[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_172 = {{1'd0}, _T_1055[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1064 = _GEN_172 + _T_1062; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1066 = _T_1055[4] + _T_1055[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_173 = {{1'd0}, _T_1055[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1068 = _GEN_173 + _T_1066; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1070 = _T_1064[1:0] + _T_1068[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_50_0 = wvalidBits_50_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_50_1 = wvalidBits_50_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_50_2 = wvalidBits_50_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_50_3 = wvalidBits_50_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_50_4 = wvalidBits_50_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_50_5 = wvalidBits_50_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_50 = wvalidBits_50_0 | wvalidBits_50_1 | wvalidBits_50_2 | wvalidBits_50_3 | wvalidBits_50_4 |
- wvalidBits_50_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_251 = wdataBits_50_0 | wdataBits_50_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_252 = _wdata_T_251 | wdataBits_50_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_253 = _wdata_T_252 | wdataBits_50_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_254 = _wdata_T_253 | wdataBits_50_4; // @[Library.scala 76:39]
- wire [31:0] wdata_50 = _wdata_T_254 | wdataBits_50_5; // @[Library.scala 76:39]
- wire wvalidBits_51_2 = io_write_2_valid & io_write_2_addr == 6'h33; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_51_1 = io_write_1_valid & io_write_1_addr == 6'h33; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_51_0 = io_write_0_valid & io_write_0_addr == 6'h33; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_51_5 = io_write_5_valid & io_write_5_addr == 6'h33; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_51_4 = io_write_4_valid & io_write_4_addr == 6'h33; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_51_3 = io_write_3_valid & io_write_3_addr == 6'h33; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1076 = {wvalidBits_51_5,wvalidBits_51_4,wvalidBits_51_3,wvalidBits_51_2,wvalidBits_51_1,wvalidBits_51_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1083 = _T_1076[1] + _T_1076[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_174 = {{1'd0}, _T_1076[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1085 = _GEN_174 + _T_1083; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1087 = _T_1076[4] + _T_1076[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_175 = {{1'd0}, _T_1076[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1089 = _GEN_175 + _T_1087; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1091 = _T_1085[1:0] + _T_1089[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_51_0 = wvalidBits_51_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_51_1 = wvalidBits_51_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_51_2 = wvalidBits_51_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_51_3 = wvalidBits_51_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_51_4 = wvalidBits_51_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_51_5 = wvalidBits_51_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_51 = wvalidBits_51_0 | wvalidBits_51_1 | wvalidBits_51_2 | wvalidBits_51_3 | wvalidBits_51_4 |
- wvalidBits_51_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_256 = wdataBits_51_0 | wdataBits_51_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_257 = _wdata_T_256 | wdataBits_51_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_258 = _wdata_T_257 | wdataBits_51_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_259 = _wdata_T_258 | wdataBits_51_4; // @[Library.scala 76:39]
- wire [31:0] wdata_51 = _wdata_T_259 | wdataBits_51_5; // @[Library.scala 76:39]
- wire wvalidBits_52_2 = io_write_2_valid & io_write_2_addr == 6'h34; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_52_1 = io_write_1_valid & io_write_1_addr == 6'h34; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_52_0 = io_write_0_valid & io_write_0_addr == 6'h34; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_52_5 = io_write_5_valid & io_write_5_addr == 6'h34; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_52_4 = io_write_4_valid & io_write_4_addr == 6'h34; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_52_3 = io_write_3_valid & io_write_3_addr == 6'h34; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1097 = {wvalidBits_52_5,wvalidBits_52_4,wvalidBits_52_3,wvalidBits_52_2,wvalidBits_52_1,wvalidBits_52_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1104 = _T_1097[1] + _T_1097[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_176 = {{1'd0}, _T_1097[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1106 = _GEN_176 + _T_1104; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1108 = _T_1097[4] + _T_1097[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_177 = {{1'd0}, _T_1097[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1110 = _GEN_177 + _T_1108; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1112 = _T_1106[1:0] + _T_1110[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_52_0 = wvalidBits_52_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_52_1 = wvalidBits_52_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_52_2 = wvalidBits_52_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_52_3 = wvalidBits_52_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_52_4 = wvalidBits_52_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_52_5 = wvalidBits_52_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_52 = wvalidBits_52_0 | wvalidBits_52_1 | wvalidBits_52_2 | wvalidBits_52_3 | wvalidBits_52_4 |
- wvalidBits_52_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_261 = wdataBits_52_0 | wdataBits_52_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_262 = _wdata_T_261 | wdataBits_52_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_263 = _wdata_T_262 | wdataBits_52_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_264 = _wdata_T_263 | wdataBits_52_4; // @[Library.scala 76:39]
- wire [31:0] wdata_52 = _wdata_T_264 | wdataBits_52_5; // @[Library.scala 76:39]
- wire wvalidBits_53_2 = io_write_2_valid & io_write_2_addr == 6'h35; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_53_1 = io_write_1_valid & io_write_1_addr == 6'h35; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_53_0 = io_write_0_valid & io_write_0_addr == 6'h35; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_53_5 = io_write_5_valid & io_write_5_addr == 6'h35; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_53_4 = io_write_4_valid & io_write_4_addr == 6'h35; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_53_3 = io_write_3_valid & io_write_3_addr == 6'h35; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1118 = {wvalidBits_53_5,wvalidBits_53_4,wvalidBits_53_3,wvalidBits_53_2,wvalidBits_53_1,wvalidBits_53_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1125 = _T_1118[1] + _T_1118[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_178 = {{1'd0}, _T_1118[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1127 = _GEN_178 + _T_1125; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1129 = _T_1118[4] + _T_1118[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_179 = {{1'd0}, _T_1118[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1131 = _GEN_179 + _T_1129; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1133 = _T_1127[1:0] + _T_1131[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_53_0 = wvalidBits_53_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_53_1 = wvalidBits_53_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_53_2 = wvalidBits_53_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_53_3 = wvalidBits_53_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_53_4 = wvalidBits_53_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_53_5 = wvalidBits_53_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_53 = wvalidBits_53_0 | wvalidBits_53_1 | wvalidBits_53_2 | wvalidBits_53_3 | wvalidBits_53_4 |
- wvalidBits_53_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_266 = wdataBits_53_0 | wdataBits_53_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_267 = _wdata_T_266 | wdataBits_53_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_268 = _wdata_T_267 | wdataBits_53_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_269 = _wdata_T_268 | wdataBits_53_4; // @[Library.scala 76:39]
- wire [31:0] wdata_53 = _wdata_T_269 | wdataBits_53_5; // @[Library.scala 76:39]
- wire wvalidBits_54_2 = io_write_2_valid & io_write_2_addr == 6'h36; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_54_1 = io_write_1_valid & io_write_1_addr == 6'h36; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_54_0 = io_write_0_valid & io_write_0_addr == 6'h36; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_54_5 = io_write_5_valid & io_write_5_addr == 6'h36; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_54_4 = io_write_4_valid & io_write_4_addr == 6'h36; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_54_3 = io_write_3_valid & io_write_3_addr == 6'h36; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1139 = {wvalidBits_54_5,wvalidBits_54_4,wvalidBits_54_3,wvalidBits_54_2,wvalidBits_54_1,wvalidBits_54_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1146 = _T_1139[1] + _T_1139[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_180 = {{1'd0}, _T_1139[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1148 = _GEN_180 + _T_1146; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1150 = _T_1139[4] + _T_1139[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_181 = {{1'd0}, _T_1139[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1152 = _GEN_181 + _T_1150; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1154 = _T_1148[1:0] + _T_1152[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_54_0 = wvalidBits_54_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_54_1 = wvalidBits_54_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_54_2 = wvalidBits_54_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_54_3 = wvalidBits_54_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_54_4 = wvalidBits_54_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_54_5 = wvalidBits_54_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_54 = wvalidBits_54_0 | wvalidBits_54_1 | wvalidBits_54_2 | wvalidBits_54_3 | wvalidBits_54_4 |
- wvalidBits_54_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_271 = wdataBits_54_0 | wdataBits_54_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_272 = _wdata_T_271 | wdataBits_54_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_273 = _wdata_T_272 | wdataBits_54_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_274 = _wdata_T_273 | wdataBits_54_4; // @[Library.scala 76:39]
- wire [31:0] wdata_54 = _wdata_T_274 | wdataBits_54_5; // @[Library.scala 76:39]
- wire wvalidBits_55_2 = io_write_2_valid & io_write_2_addr == 6'h37; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_55_1 = io_write_1_valid & io_write_1_addr == 6'h37; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_55_0 = io_write_0_valid & io_write_0_addr == 6'h37; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_55_5 = io_write_5_valid & io_write_5_addr == 6'h37; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_55_4 = io_write_4_valid & io_write_4_addr == 6'h37; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_55_3 = io_write_3_valid & io_write_3_addr == 6'h37; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1160 = {wvalidBits_55_5,wvalidBits_55_4,wvalidBits_55_3,wvalidBits_55_2,wvalidBits_55_1,wvalidBits_55_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1167 = _T_1160[1] + _T_1160[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_182 = {{1'd0}, _T_1160[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1169 = _GEN_182 + _T_1167; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1171 = _T_1160[4] + _T_1160[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_183 = {{1'd0}, _T_1160[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1173 = _GEN_183 + _T_1171; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1175 = _T_1169[1:0] + _T_1173[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_55_0 = wvalidBits_55_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_55_1 = wvalidBits_55_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_55_2 = wvalidBits_55_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_55_3 = wvalidBits_55_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_55_4 = wvalidBits_55_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_55_5 = wvalidBits_55_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_55 = wvalidBits_55_0 | wvalidBits_55_1 | wvalidBits_55_2 | wvalidBits_55_3 | wvalidBits_55_4 |
- wvalidBits_55_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_276 = wdataBits_55_0 | wdataBits_55_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_277 = _wdata_T_276 | wdataBits_55_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_278 = _wdata_T_277 | wdataBits_55_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_279 = _wdata_T_278 | wdataBits_55_4; // @[Library.scala 76:39]
- wire [31:0] wdata_55 = _wdata_T_279 | wdataBits_55_5; // @[Library.scala 76:39]
- wire wvalidBits_56_2 = io_write_2_valid & io_write_2_addr == 6'h38; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_56_1 = io_write_1_valid & io_write_1_addr == 6'h38; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_56_0 = io_write_0_valid & io_write_0_addr == 6'h38; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_56_5 = io_write_5_valid & io_write_5_addr == 6'h38; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_56_4 = io_write_4_valid & io_write_4_addr == 6'h38; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_56_3 = io_write_3_valid & io_write_3_addr == 6'h38; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1181 = {wvalidBits_56_5,wvalidBits_56_4,wvalidBits_56_3,wvalidBits_56_2,wvalidBits_56_1,wvalidBits_56_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1188 = _T_1181[1] + _T_1181[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_184 = {{1'd0}, _T_1181[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1190 = _GEN_184 + _T_1188; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1192 = _T_1181[4] + _T_1181[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_185 = {{1'd0}, _T_1181[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1194 = _GEN_185 + _T_1192; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1196 = _T_1190[1:0] + _T_1194[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_56_0 = wvalidBits_56_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_56_1 = wvalidBits_56_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_56_2 = wvalidBits_56_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_56_3 = wvalidBits_56_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_56_4 = wvalidBits_56_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_56_5 = wvalidBits_56_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_56 = wvalidBits_56_0 | wvalidBits_56_1 | wvalidBits_56_2 | wvalidBits_56_3 | wvalidBits_56_4 |
- wvalidBits_56_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_281 = wdataBits_56_0 | wdataBits_56_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_282 = _wdata_T_281 | wdataBits_56_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_283 = _wdata_T_282 | wdataBits_56_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_284 = _wdata_T_283 | wdataBits_56_4; // @[Library.scala 76:39]
- wire [31:0] wdata_56 = _wdata_T_284 | wdataBits_56_5; // @[Library.scala 76:39]
- wire wvalidBits_57_2 = io_write_2_valid & io_write_2_addr == 6'h39; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_57_1 = io_write_1_valid & io_write_1_addr == 6'h39; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_57_0 = io_write_0_valid & io_write_0_addr == 6'h39; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_57_5 = io_write_5_valid & io_write_5_addr == 6'h39; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_57_4 = io_write_4_valid & io_write_4_addr == 6'h39; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_57_3 = io_write_3_valid & io_write_3_addr == 6'h39; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1202 = {wvalidBits_57_5,wvalidBits_57_4,wvalidBits_57_3,wvalidBits_57_2,wvalidBits_57_1,wvalidBits_57_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1209 = _T_1202[1] + _T_1202[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_186 = {{1'd0}, _T_1202[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1211 = _GEN_186 + _T_1209; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1213 = _T_1202[4] + _T_1202[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_187 = {{1'd0}, _T_1202[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1215 = _GEN_187 + _T_1213; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1217 = _T_1211[1:0] + _T_1215[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_57_0 = wvalidBits_57_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_57_1 = wvalidBits_57_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_57_2 = wvalidBits_57_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_57_3 = wvalidBits_57_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_57_4 = wvalidBits_57_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_57_5 = wvalidBits_57_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_57 = wvalidBits_57_0 | wvalidBits_57_1 | wvalidBits_57_2 | wvalidBits_57_3 | wvalidBits_57_4 |
- wvalidBits_57_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_286 = wdataBits_57_0 | wdataBits_57_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_287 = _wdata_T_286 | wdataBits_57_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_288 = _wdata_T_287 | wdataBits_57_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_289 = _wdata_T_288 | wdataBits_57_4; // @[Library.scala 76:39]
- wire [31:0] wdata_57 = _wdata_T_289 | wdataBits_57_5; // @[Library.scala 76:39]
- wire wvalidBits_58_2 = io_write_2_valid & io_write_2_addr == 6'h3a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_58_1 = io_write_1_valid & io_write_1_addr == 6'h3a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_58_0 = io_write_0_valid & io_write_0_addr == 6'h3a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_58_5 = io_write_5_valid & io_write_5_addr == 6'h3a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_58_4 = io_write_4_valid & io_write_4_addr == 6'h3a; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_58_3 = io_write_3_valid & io_write_3_addr == 6'h3a; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1223 = {wvalidBits_58_5,wvalidBits_58_4,wvalidBits_58_3,wvalidBits_58_2,wvalidBits_58_1,wvalidBits_58_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1230 = _T_1223[1] + _T_1223[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_188 = {{1'd0}, _T_1223[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1232 = _GEN_188 + _T_1230; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1234 = _T_1223[4] + _T_1223[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_189 = {{1'd0}, _T_1223[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1236 = _GEN_189 + _T_1234; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1238 = _T_1232[1:0] + _T_1236[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_58_0 = wvalidBits_58_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_58_1 = wvalidBits_58_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_58_2 = wvalidBits_58_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_58_3 = wvalidBits_58_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_58_4 = wvalidBits_58_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_58_5 = wvalidBits_58_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_58 = wvalidBits_58_0 | wvalidBits_58_1 | wvalidBits_58_2 | wvalidBits_58_3 | wvalidBits_58_4 |
- wvalidBits_58_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_291 = wdataBits_58_0 | wdataBits_58_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_292 = _wdata_T_291 | wdataBits_58_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_293 = _wdata_T_292 | wdataBits_58_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_294 = _wdata_T_293 | wdataBits_58_4; // @[Library.scala 76:39]
- wire [31:0] wdata_58 = _wdata_T_294 | wdataBits_58_5; // @[Library.scala 76:39]
- wire wvalidBits_59_2 = io_write_2_valid & io_write_2_addr == 6'h3b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_59_1 = io_write_1_valid & io_write_1_addr == 6'h3b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_59_0 = io_write_0_valid & io_write_0_addr == 6'h3b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_59_5 = io_write_5_valid & io_write_5_addr == 6'h3b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_59_4 = io_write_4_valid & io_write_4_addr == 6'h3b; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_59_3 = io_write_3_valid & io_write_3_addr == 6'h3b; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1244 = {wvalidBits_59_5,wvalidBits_59_4,wvalidBits_59_3,wvalidBits_59_2,wvalidBits_59_1,wvalidBits_59_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1251 = _T_1244[1] + _T_1244[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_190 = {{1'd0}, _T_1244[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1253 = _GEN_190 + _T_1251; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1255 = _T_1244[4] + _T_1244[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_191 = {{1'd0}, _T_1244[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1257 = _GEN_191 + _T_1255; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1259 = _T_1253[1:0] + _T_1257[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_59_0 = wvalidBits_59_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_59_1 = wvalidBits_59_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_59_2 = wvalidBits_59_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_59_3 = wvalidBits_59_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_59_4 = wvalidBits_59_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_59_5 = wvalidBits_59_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_59 = wvalidBits_59_0 | wvalidBits_59_1 | wvalidBits_59_2 | wvalidBits_59_3 | wvalidBits_59_4 |
- wvalidBits_59_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_296 = wdataBits_59_0 | wdataBits_59_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_297 = _wdata_T_296 | wdataBits_59_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_298 = _wdata_T_297 | wdataBits_59_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_299 = _wdata_T_298 | wdataBits_59_4; // @[Library.scala 76:39]
- wire [31:0] wdata_59 = _wdata_T_299 | wdataBits_59_5; // @[Library.scala 76:39]
- wire wvalidBits_60_2 = io_write_2_valid & io_write_2_addr == 6'h3c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_60_1 = io_write_1_valid & io_write_1_addr == 6'h3c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_60_0 = io_write_0_valid & io_write_0_addr == 6'h3c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_60_5 = io_write_5_valid & io_write_5_addr == 6'h3c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_60_4 = io_write_4_valid & io_write_4_addr == 6'h3c; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_60_3 = io_write_3_valid & io_write_3_addr == 6'h3c; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1265 = {wvalidBits_60_5,wvalidBits_60_4,wvalidBits_60_3,wvalidBits_60_2,wvalidBits_60_1,wvalidBits_60_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1272 = _T_1265[1] + _T_1265[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_192 = {{1'd0}, _T_1265[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1274 = _GEN_192 + _T_1272; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1276 = _T_1265[4] + _T_1265[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_193 = {{1'd0}, _T_1265[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1278 = _GEN_193 + _T_1276; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1280 = _T_1274[1:0] + _T_1278[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_60_0 = wvalidBits_60_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_60_1 = wvalidBits_60_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_60_2 = wvalidBits_60_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_60_3 = wvalidBits_60_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_60_4 = wvalidBits_60_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_60_5 = wvalidBits_60_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_60 = wvalidBits_60_0 | wvalidBits_60_1 | wvalidBits_60_2 | wvalidBits_60_3 | wvalidBits_60_4 |
- wvalidBits_60_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_301 = wdataBits_60_0 | wdataBits_60_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_302 = _wdata_T_301 | wdataBits_60_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_303 = _wdata_T_302 | wdataBits_60_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_304 = _wdata_T_303 | wdataBits_60_4; // @[Library.scala 76:39]
- wire [31:0] wdata_60 = _wdata_T_304 | wdataBits_60_5; // @[Library.scala 76:39]
- wire wvalidBits_61_2 = io_write_2_valid & io_write_2_addr == 6'h3d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_61_1 = io_write_1_valid & io_write_1_addr == 6'h3d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_61_0 = io_write_0_valid & io_write_0_addr == 6'h3d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_61_5 = io_write_5_valid & io_write_5_addr == 6'h3d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_61_4 = io_write_4_valid & io_write_4_addr == 6'h3d; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_61_3 = io_write_3_valid & io_write_3_addr == 6'h3d; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1286 = {wvalidBits_61_5,wvalidBits_61_4,wvalidBits_61_3,wvalidBits_61_2,wvalidBits_61_1,wvalidBits_61_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1293 = _T_1286[1] + _T_1286[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_194 = {{1'd0}, _T_1286[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1295 = _GEN_194 + _T_1293; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1297 = _T_1286[4] + _T_1286[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_195 = {{1'd0}, _T_1286[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1299 = _GEN_195 + _T_1297; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1301 = _T_1295[1:0] + _T_1299[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_61_0 = wvalidBits_61_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_61_1 = wvalidBits_61_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_61_2 = wvalidBits_61_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_61_3 = wvalidBits_61_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_61_4 = wvalidBits_61_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_61_5 = wvalidBits_61_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_61 = wvalidBits_61_0 | wvalidBits_61_1 | wvalidBits_61_2 | wvalidBits_61_3 | wvalidBits_61_4 |
- wvalidBits_61_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_306 = wdataBits_61_0 | wdataBits_61_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_307 = _wdata_T_306 | wdataBits_61_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_308 = _wdata_T_307 | wdataBits_61_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_309 = _wdata_T_308 | wdataBits_61_4; // @[Library.scala 76:39]
- wire [31:0] wdata_61 = _wdata_T_309 | wdataBits_61_5; // @[Library.scala 76:39]
- wire wvalidBits_62_2 = io_write_2_valid & io_write_2_addr == 6'h3e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_62_1 = io_write_1_valid & io_write_1_addr == 6'h3e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_62_0 = io_write_0_valid & io_write_0_addr == 6'h3e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_62_5 = io_write_5_valid & io_write_5_addr == 6'h3e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_62_4 = io_write_4_valid & io_write_4_addr == 6'h3e; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_62_3 = io_write_3_valid & io_write_3_addr == 6'h3e; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1307 = {wvalidBits_62_5,wvalidBits_62_4,wvalidBits_62_3,wvalidBits_62_2,wvalidBits_62_1,wvalidBits_62_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1314 = _T_1307[1] + _T_1307[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_196 = {{1'd0}, _T_1307[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1316 = _GEN_196 + _T_1314; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1318 = _T_1307[4] + _T_1307[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_197 = {{1'd0}, _T_1307[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1320 = _GEN_197 + _T_1318; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1322 = _T_1316[1:0] + _T_1320[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_62_0 = wvalidBits_62_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_62_1 = wvalidBits_62_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_62_2 = wvalidBits_62_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_62_3 = wvalidBits_62_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_62_4 = wvalidBits_62_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_62_5 = wvalidBits_62_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_62 = wvalidBits_62_0 | wvalidBits_62_1 | wvalidBits_62_2 | wvalidBits_62_3 | wvalidBits_62_4 |
- wvalidBits_62_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_311 = wdataBits_62_0 | wdataBits_62_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_312 = _wdata_T_311 | wdataBits_62_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_313 = _wdata_T_312 | wdataBits_62_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_314 = _wdata_T_313 | wdataBits_62_4; // @[Library.scala 76:39]
- wire [31:0] wdata_62 = _wdata_T_314 | wdataBits_62_5; // @[Library.scala 76:39]
- wire wvalidBits_63_2 = io_write_2_valid & io_write_2_addr == 6'h3f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_63_1 = io_write_1_valid & io_write_1_addr == 6'h3f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_63_0 = io_write_0_valid & io_write_0_addr == 6'h3f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_63_5 = io_write_5_valid & io_write_5_addr == 6'h3f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_63_4 = io_write_4_valid & io_write_4_addr == 6'h3f; // @[VRegfileSegment.scala 89:42]
- wire wvalidBits_63_3 = io_write_3_valid & io_write_3_addr == 6'h3f; // @[VRegfileSegment.scala 89:42]
- wire [5:0] _T_1328 = {wvalidBits_63_5,wvalidBits_63_4,wvalidBits_63_3,wvalidBits_63_2,wvalidBits_63_1,wvalidBits_63_0}
- ; // @[VRegfileSegment.scala 86:32]
- wire [1:0] _T_1335 = _T_1328[1] + _T_1328[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_198 = {{1'd0}, _T_1328[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1337 = _GEN_198 + _T_1335; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1339 = _T_1328[4] + _T_1328[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_199 = {{1'd0}, _T_1328[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1341 = _GEN_199 + _T_1339; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1343 = _T_1337[1:0] + _T_1341[1:0]; // @[Bitwise.scala 48:55]
- wire [31:0] wdataBits_63_0 = wvalidBits_63_0 ? io_write_0_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_63_1 = wvalidBits_63_1 ? io_write_1_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_63_2 = wvalidBits_63_2 ? io_write_2_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_63_3 = wvalidBits_63_3 ? io_write_3_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_63_4 = wvalidBits_63_4 ? io_write_4_data : 32'h0; // @[Library.scala 32:8]
- wire [31:0] wdataBits_63_5 = wvalidBits_63_5 ? io_write_5_data : 32'h0; // @[Library.scala 32:8]
- wire wvalid_63 = wvalidBits_63_0 | wvalidBits_63_1 | wvalidBits_63_2 | wvalidBits_63_3 | wvalidBits_63_4 |
- wvalidBits_63_5; // @[Library.scala 84:39]
- wire [31:0] _wdata_T_316 = wdataBits_63_0 | wdataBits_63_1; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_317 = _wdata_T_316 | wdataBits_63_2; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_318 = _wdata_T_317 | wdataBits_63_3; // @[Library.scala 76:39]
- wire [31:0] _wdata_T_319 = _wdata_T_318 | wdataBits_63_4; // @[Library.scala 76:39]
- wire [31:0] wdata_63 = _wdata_T_319 | wdataBits_63_5; // @[Library.scala 76:39]
- assign io_read_0_data = io_read_0_data_value_5_0 | io_read_0_data_value_5_1; // @[Library.scala 129:37]
- assign io_read_1_data = io_read_1_data_value_5_0 | io_read_1_data_value_5_1; // @[Library.scala 129:37]
- assign io_read_2_data = io_read_2_data_value_5_0 | io_read_2_data_value_5_1; // @[Library.scala 129:37]
- assign io_read_3_data = io_read_3_data_value_5_0 | io_read_3_data_value_5_1; // @[Library.scala 129:37]
- assign io_read_4_data = io_read_4_data_value_5_0 | io_read_4_data_value_5_1; // @[Library.scala 129:37]
- assign io_read_5_data = io_read_5_data_value_5_0 | io_read_5_data_value_5_1; // @[Library.scala 129:37]
- assign io_read_6_data = io_read_6_data_value_5_0 | io_read_6_data_value_5_1; // @[Library.scala 129:37]
- assign io_transpose_data = {io_transpose_data_hi,io_transpose_data_lo}; // @[VRegfileSegment.scala 74:30]
- assign io_internal_data = io_internal_data_value_5_0 | io_internal_data_value_5_1; // @[Library.scala 129:37]
- always @(posedge clock) begin
- if (wvalid) begin // @[VRegfileSegment.scala 96:19]
- vreg_0 <= wdata; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_1) begin // @[VRegfileSegment.scala 96:19]
- vreg_1 <= wdata_1; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_2) begin // @[VRegfileSegment.scala 96:19]
- vreg_2 <= wdata_2; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_3) begin // @[VRegfileSegment.scala 96:19]
- vreg_3 <= wdata_3; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_4) begin // @[VRegfileSegment.scala 96:19]
- vreg_4 <= wdata_4; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_5) begin // @[VRegfileSegment.scala 96:19]
- vreg_5 <= wdata_5; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_6) begin // @[VRegfileSegment.scala 96:19]
- vreg_6 <= wdata_6; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_7) begin // @[VRegfileSegment.scala 96:19]
- vreg_7 <= wdata_7; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_8) begin // @[VRegfileSegment.scala 96:19]
- vreg_8 <= wdata_8; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_9) begin // @[VRegfileSegment.scala 96:19]
- vreg_9 <= wdata_9; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_10) begin // @[VRegfileSegment.scala 96:19]
- vreg_10 <= wdata_10; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_11) begin // @[VRegfileSegment.scala 96:19]
- vreg_11 <= wdata_11; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_12) begin // @[VRegfileSegment.scala 96:19]
- vreg_12 <= wdata_12; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_13) begin // @[VRegfileSegment.scala 96:19]
- vreg_13 <= wdata_13; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_14) begin // @[VRegfileSegment.scala 96:19]
- vreg_14 <= wdata_14; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_15) begin // @[VRegfileSegment.scala 96:19]
- vreg_15 <= wdata_15; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_16) begin // @[VRegfileSegment.scala 96:19]
- vreg_16 <= wdata_16; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_17) begin // @[VRegfileSegment.scala 96:19]
- vreg_17 <= wdata_17; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_18) begin // @[VRegfileSegment.scala 96:19]
- vreg_18 <= wdata_18; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_19) begin // @[VRegfileSegment.scala 96:19]
- vreg_19 <= wdata_19; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_20) begin // @[VRegfileSegment.scala 96:19]
- vreg_20 <= wdata_20; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_21) begin // @[VRegfileSegment.scala 96:19]
- vreg_21 <= wdata_21; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_22) begin // @[VRegfileSegment.scala 96:19]
- vreg_22 <= wdata_22; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_23) begin // @[VRegfileSegment.scala 96:19]
- vreg_23 <= wdata_23; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_24) begin // @[VRegfileSegment.scala 96:19]
- vreg_24 <= wdata_24; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_25) begin // @[VRegfileSegment.scala 96:19]
- vreg_25 <= wdata_25; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_26) begin // @[VRegfileSegment.scala 96:19]
- vreg_26 <= wdata_26; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_27) begin // @[VRegfileSegment.scala 96:19]
- vreg_27 <= wdata_27; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_28) begin // @[VRegfileSegment.scala 96:19]
- vreg_28 <= wdata_28; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_29) begin // @[VRegfileSegment.scala 96:19]
- vreg_29 <= wdata_29; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_30) begin // @[VRegfileSegment.scala 96:19]
- vreg_30 <= wdata_30; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_31) begin // @[VRegfileSegment.scala 96:19]
- vreg_31 <= wdata_31; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_32) begin // @[VRegfileSegment.scala 96:19]
- vreg_32 <= wdata_32; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_33) begin // @[VRegfileSegment.scala 96:19]
- vreg_33 <= wdata_33; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_34) begin // @[VRegfileSegment.scala 96:19]
- vreg_34 <= wdata_34; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_35) begin // @[VRegfileSegment.scala 96:19]
- vreg_35 <= wdata_35; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_36) begin // @[VRegfileSegment.scala 96:19]
- vreg_36 <= wdata_36; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_37) begin // @[VRegfileSegment.scala 96:19]
- vreg_37 <= wdata_37; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_38) begin // @[VRegfileSegment.scala 96:19]
- vreg_38 <= wdata_38; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_39) begin // @[VRegfileSegment.scala 96:19]
- vreg_39 <= wdata_39; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_40) begin // @[VRegfileSegment.scala 96:19]
- vreg_40 <= wdata_40; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_41) begin // @[VRegfileSegment.scala 96:19]
- vreg_41 <= wdata_41; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_42) begin // @[VRegfileSegment.scala 96:19]
- vreg_42 <= wdata_42; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_43) begin // @[VRegfileSegment.scala 96:19]
- vreg_43 <= wdata_43; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_44) begin // @[VRegfileSegment.scala 96:19]
- vreg_44 <= wdata_44; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_45) begin // @[VRegfileSegment.scala 96:19]
- vreg_45 <= wdata_45; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_46) begin // @[VRegfileSegment.scala 96:19]
- vreg_46 <= wdata_46; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_47) begin // @[VRegfileSegment.scala 96:19]
- vreg_47 <= wdata_47; // @[VRegfileSegment.scala 97:15]
- end
- if (io_conv_valid) begin // @[VRegfileSegment.scala 105:24]
- vreg_48 <= io_conv_data_0; // @[VRegfileSegment.scala 107:20]
- end else if (wvalid_48) begin // @[VRegfileSegment.scala 96:19]
- vreg_48 <= wdata_48; // @[VRegfileSegment.scala 97:15]
- end
- if (io_conv_valid) begin // @[VRegfileSegment.scala 105:24]
- vreg_49 <= io_conv_data_1; // @[VRegfileSegment.scala 107:20]
- end else if (wvalid_49) begin // @[VRegfileSegment.scala 96:19]
- vreg_49 <= wdata_49; // @[VRegfileSegment.scala 97:15]
- end
- if (io_conv_valid) begin // @[VRegfileSegment.scala 105:24]
- vreg_50 <= io_conv_data_2; // @[VRegfileSegment.scala 107:20]
- end else if (wvalid_50) begin // @[VRegfileSegment.scala 96:19]
- vreg_50 <= wdata_50; // @[VRegfileSegment.scala 97:15]
- end
- if (io_conv_valid) begin // @[VRegfileSegment.scala 105:24]
- vreg_51 <= io_conv_data_3; // @[VRegfileSegment.scala 107:20]
- end else if (wvalid_51) begin // @[VRegfileSegment.scala 96:19]
- vreg_51 <= wdata_51; // @[VRegfileSegment.scala 97:15]
- end
- if (io_conv_valid) begin // @[VRegfileSegment.scala 105:24]
- vreg_52 <= io_conv_data_4; // @[VRegfileSegment.scala 107:20]
- end else if (wvalid_52) begin // @[VRegfileSegment.scala 96:19]
- vreg_52 <= wdata_52; // @[VRegfileSegment.scala 97:15]
- end
- if (io_conv_valid) begin // @[VRegfileSegment.scala 105:24]
- vreg_53 <= io_conv_data_5; // @[VRegfileSegment.scala 107:20]
- end else if (wvalid_53) begin // @[VRegfileSegment.scala 96:19]
- vreg_53 <= wdata_53; // @[VRegfileSegment.scala 97:15]
- end
- if (io_conv_valid) begin // @[VRegfileSegment.scala 105:24]
- vreg_54 <= io_conv_data_6; // @[VRegfileSegment.scala 107:20]
- end else if (wvalid_54) begin // @[VRegfileSegment.scala 96:19]
- vreg_54 <= wdata_54; // @[VRegfileSegment.scala 97:15]
- end
- if (io_conv_valid) begin // @[VRegfileSegment.scala 105:24]
- vreg_55 <= io_conv_data_7; // @[VRegfileSegment.scala 107:20]
- end else if (wvalid_55) begin // @[VRegfileSegment.scala 96:19]
- vreg_55 <= wdata_55; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_56) begin // @[VRegfileSegment.scala 96:19]
- vreg_56 <= wdata_56; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_57) begin // @[VRegfileSegment.scala 96:19]
- vreg_57 <= wdata_57; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_58) begin // @[VRegfileSegment.scala 96:19]
- vreg_58 <= wdata_58; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_59) begin // @[VRegfileSegment.scala 96:19]
- vreg_59 <= wdata_59; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_60) begin // @[VRegfileSegment.scala 96:19]
- vreg_60 <= wdata_60; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_61) begin // @[VRegfileSegment.scala 96:19]
- vreg_61 <= wdata_61; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_62) begin // @[VRegfileSegment.scala 96:19]
- vreg_62 <= wdata_62; // @[VRegfileSegment.scala 97:15]
- end
- if (wvalid_63) begin // @[VRegfileSegment.scala 96:19]
- vreg_63 <= wdata_63; // @[VRegfileSegment.scala 97:15]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(io_transpose_addr[3:0] == 4'h0)) begin
- $fatal; // @[VRegfileSegment.scala 75:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(io_transpose_addr[3:0] == 4'h0)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:75 assert(io.transpose.addr(3,0) === 0.U)\n"); // @[VRegfileSegment.scala 75:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_20 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_20 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_41 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_41 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_62 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_62 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_83 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_83 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_104 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_104 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_125 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_125 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_146 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_146 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_167 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_167 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_188 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_188 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_209 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_209 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_230 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_230 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_251 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_251 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_272 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_272 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_293 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_293 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_314 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_314 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_335 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_335 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_356 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_356 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_377 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_377 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_398 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_398 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_419 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_419 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_440 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_440 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_461 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_461 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_482 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_482 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_503 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_503 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_524 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_524 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_545 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_545 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_566 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_566 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_587 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_587 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_608 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_608 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_629 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_629 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_650 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_650 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_671 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_671 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_692 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_692 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_713 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_713 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_734 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_734 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_755 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_755 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_776 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_776 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_797 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_797 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_818 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_818 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_839 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_839 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_860 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_860 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_881 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_881 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_902 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_902 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_923 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_923 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_944 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_944 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_965 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_965 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_986 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_986 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1007 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1007 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1028 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1028 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1049 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1049 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1070 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1070 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1091 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1091 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1112 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1112 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1133 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1133 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1154 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1154 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1175 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1175 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1196 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1196 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1217 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1217 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1238 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1238 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1259 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1259 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1280 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1280 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1301 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1301 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1322 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1322 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(_T_1343 <= 3'h1)) begin
- $fatal; // @[VRegfileSegment.scala 86:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(_T_1343 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:86 assert(PopCount(wvalidBits.asUInt) <= 1.U)\n"); // @[VRegfileSegment.scala 86:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(~(io_conv_valid & io_write_0_valid & io_write_0_addr >= 6'h30))) begin
- $fatal; // @[VRegfileSegment.scala 112:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(~(io_conv_valid & io_write_0_valid & io_write_0_addr >= 6'h30))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:112 assert(!(io.conv.valid && io.write(i).valid && io.write(i).addr >= 48.U))\n"
- ); // @[VRegfileSegment.scala 112:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(~(io_conv_valid & io_write_1_valid & io_write_1_addr >= 6'h30))) begin
- $fatal; // @[VRegfileSegment.scala 112:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(~(io_conv_valid & io_write_1_valid & io_write_1_addr >= 6'h30))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:112 assert(!(io.conv.valid && io.write(i).valid && io.write(i).addr >= 48.U))\n"
- ); // @[VRegfileSegment.scala 112:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(~(io_conv_valid & io_write_2_valid & io_write_2_addr >= 6'h30))) begin
- $fatal; // @[VRegfileSegment.scala 112:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(~(io_conv_valid & io_write_2_valid & io_write_2_addr >= 6'h30))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:112 assert(!(io.conv.valid && io.write(i).valid && io.write(i).addr >= 48.U))\n"
- ); // @[VRegfileSegment.scala 112:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(~(io_conv_valid & io_write_3_valid & io_write_3_addr >= 6'h30))) begin
- $fatal; // @[VRegfileSegment.scala 112:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(~(io_conv_valid & io_write_3_valid & io_write_3_addr >= 6'h30))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:112 assert(!(io.conv.valid && io.write(i).valid && io.write(i).addr >= 48.U))\n"
- ); // @[VRegfileSegment.scala 112:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(~(io_conv_valid & io_write_4_valid & io_write_4_addr >= 6'h30))) begin
- $fatal; // @[VRegfileSegment.scala 112:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(~(io_conv_valid & io_write_4_valid & io_write_4_addr >= 6'h30))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:112 assert(!(io.conv.valid && io.write(i).valid && io.write(i).addr >= 48.U))\n"
- ); // @[VRegfileSegment.scala 112:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3 & ~(~(io_conv_valid & io_write_5_valid & io_write_5_addr >= 6'h30))) begin
- $fatal; // @[VRegfileSegment.scala 112:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3 & ~(~(io_conv_valid & io_write_5_valid & io_write_5_addr >= 6'h30))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfileSegment.scala:112 assert(!(io.conv.valid && io.write(i).valid && io.write(i).addr >= 48.U))\n"
- ); // @[VRegfileSegment.scala 112:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- vreg_0 = _RAND_0[31:0];
- _RAND_1 = {1{`RANDOM}};
- vreg_1 = _RAND_1[31:0];
- _RAND_2 = {1{`RANDOM}};
- vreg_2 = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- vreg_3 = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- vreg_4 = _RAND_4[31:0];
- _RAND_5 = {1{`RANDOM}};
- vreg_5 = _RAND_5[31:0];
- _RAND_6 = {1{`RANDOM}};
- vreg_6 = _RAND_6[31:0];
- _RAND_7 = {1{`RANDOM}};
- vreg_7 = _RAND_7[31:0];
- _RAND_8 = {1{`RANDOM}};
- vreg_8 = _RAND_8[31:0];
- _RAND_9 = {1{`RANDOM}};
- vreg_9 = _RAND_9[31:0];
- _RAND_10 = {1{`RANDOM}};
- vreg_10 = _RAND_10[31:0];
- _RAND_11 = {1{`RANDOM}};
- vreg_11 = _RAND_11[31:0];
- _RAND_12 = {1{`RANDOM}};
- vreg_12 = _RAND_12[31:0];
- _RAND_13 = {1{`RANDOM}};
- vreg_13 = _RAND_13[31:0];
- _RAND_14 = {1{`RANDOM}};
- vreg_14 = _RAND_14[31:0];
- _RAND_15 = {1{`RANDOM}};
- vreg_15 = _RAND_15[31:0];
- _RAND_16 = {1{`RANDOM}};
- vreg_16 = _RAND_16[31:0];
- _RAND_17 = {1{`RANDOM}};
- vreg_17 = _RAND_17[31:0];
- _RAND_18 = {1{`RANDOM}};
- vreg_18 = _RAND_18[31:0];
- _RAND_19 = {1{`RANDOM}};
- vreg_19 = _RAND_19[31:0];
- _RAND_20 = {1{`RANDOM}};
- vreg_20 = _RAND_20[31:0];
- _RAND_21 = {1{`RANDOM}};
- vreg_21 = _RAND_21[31:0];
- _RAND_22 = {1{`RANDOM}};
- vreg_22 = _RAND_22[31:0];
- _RAND_23 = {1{`RANDOM}};
- vreg_23 = _RAND_23[31:0];
- _RAND_24 = {1{`RANDOM}};
- vreg_24 = _RAND_24[31:0];
- _RAND_25 = {1{`RANDOM}};
- vreg_25 = _RAND_25[31:0];
- _RAND_26 = {1{`RANDOM}};
- vreg_26 = _RAND_26[31:0];
- _RAND_27 = {1{`RANDOM}};
- vreg_27 = _RAND_27[31:0];
- _RAND_28 = {1{`RANDOM}};
- vreg_28 = _RAND_28[31:0];
- _RAND_29 = {1{`RANDOM}};
- vreg_29 = _RAND_29[31:0];
- _RAND_30 = {1{`RANDOM}};
- vreg_30 = _RAND_30[31:0];
- _RAND_31 = {1{`RANDOM}};
- vreg_31 = _RAND_31[31:0];
- _RAND_32 = {1{`RANDOM}};
- vreg_32 = _RAND_32[31:0];
- _RAND_33 = {1{`RANDOM}};
- vreg_33 = _RAND_33[31:0];
- _RAND_34 = {1{`RANDOM}};
- vreg_34 = _RAND_34[31:0];
- _RAND_35 = {1{`RANDOM}};
- vreg_35 = _RAND_35[31:0];
- _RAND_36 = {1{`RANDOM}};
- vreg_36 = _RAND_36[31:0];
- _RAND_37 = {1{`RANDOM}};
- vreg_37 = _RAND_37[31:0];
- _RAND_38 = {1{`RANDOM}};
- vreg_38 = _RAND_38[31:0];
- _RAND_39 = {1{`RANDOM}};
- vreg_39 = _RAND_39[31:0];
- _RAND_40 = {1{`RANDOM}};
- vreg_40 = _RAND_40[31:0];
- _RAND_41 = {1{`RANDOM}};
- vreg_41 = _RAND_41[31:0];
- _RAND_42 = {1{`RANDOM}};
- vreg_42 = _RAND_42[31:0];
- _RAND_43 = {1{`RANDOM}};
- vreg_43 = _RAND_43[31:0];
- _RAND_44 = {1{`RANDOM}};
- vreg_44 = _RAND_44[31:0];
- _RAND_45 = {1{`RANDOM}};
- vreg_45 = _RAND_45[31:0];
- _RAND_46 = {1{`RANDOM}};
- vreg_46 = _RAND_46[31:0];
- _RAND_47 = {1{`RANDOM}};
- vreg_47 = _RAND_47[31:0];
- _RAND_48 = {1{`RANDOM}};
- vreg_48 = _RAND_48[31:0];
- _RAND_49 = {1{`RANDOM}};
- vreg_49 = _RAND_49[31:0];
- _RAND_50 = {1{`RANDOM}};
- vreg_50 = _RAND_50[31:0];
- _RAND_51 = {1{`RANDOM}};
- vreg_51 = _RAND_51[31:0];
- _RAND_52 = {1{`RANDOM}};
- vreg_52 = _RAND_52[31:0];
- _RAND_53 = {1{`RANDOM}};
- vreg_53 = _RAND_53[31:0];
- _RAND_54 = {1{`RANDOM}};
- vreg_54 = _RAND_54[31:0];
- _RAND_55 = {1{`RANDOM}};
- vreg_55 = _RAND_55[31:0];
- _RAND_56 = {1{`RANDOM}};
- vreg_56 = _RAND_56[31:0];
- _RAND_57 = {1{`RANDOM}};
- vreg_57 = _RAND_57[31:0];
- _RAND_58 = {1{`RANDOM}};
- vreg_58 = _RAND_58[31:0];
- _RAND_59 = {1{`RANDOM}};
- vreg_59 = _RAND_59[31:0];
- _RAND_60 = {1{`RANDOM}};
- vreg_60 = _RAND_60[31:0];
- _RAND_61 = {1{`RANDOM}};
- vreg_61 = _RAND_61[31:0];
- _RAND_62 = {1{`RANDOM}};
- vreg_62 = _RAND_62[31:0];
- _RAND_63 = {1{`RANDOM}};
- vreg_63 = _RAND_63[31:0];
-`endif // RANDOMIZE_REG_INIT
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VConvAlu(
- input clock,
- input reset,
- input io_op_conv,
- input io_op_init,
- input io_op_tran,
- input io_op_clear,
- input [2:0] io_index,
- input [255:0] io_adata,
- input [255:0] io_bdata,
- input [8:0] io_abias,
- input [8:0] io_bbias,
- input io_asign,
- input io_bsign,
- output [255:0] io_out_0,
- output [255:0] io_out_1,
- output [255:0] io_out_2,
- output [255:0] io_out_3,
- output [255:0] io_out_4,
- output [255:0] io_out_5,
- output [255:0] io_out_6,
- output [255:0] io_out_7
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
- reg [31:0] _RAND_34;
- reg [31:0] _RAND_35;
- reg [31:0] _RAND_36;
- reg [31:0] _RAND_37;
- reg [31:0] _RAND_38;
- reg [31:0] _RAND_39;
- reg [31:0] _RAND_40;
- reg [31:0] _RAND_41;
- reg [31:0] _RAND_42;
- reg [31:0] _RAND_43;
- reg [31:0] _RAND_44;
- reg [31:0] _RAND_45;
- reg [31:0] _RAND_46;
- reg [31:0] _RAND_47;
- reg [31:0] _RAND_48;
- reg [31:0] _RAND_49;
- reg [31:0] _RAND_50;
- reg [31:0] _RAND_51;
- reg [31:0] _RAND_52;
- reg [31:0] _RAND_53;
- reg [31:0] _RAND_54;
- reg [31:0] _RAND_55;
- reg [31:0] _RAND_56;
- reg [31:0] _RAND_57;
- reg [31:0] _RAND_58;
- reg [31:0] _RAND_59;
- reg [31:0] _RAND_60;
- reg [31:0] _RAND_61;
- reg [31:0] _RAND_62;
- reg [31:0] _RAND_63;
-`endif // RANDOMIZE_REG_INIT
- reg [31:0] acc_0_0; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_0_1; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_0_2; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_0_3; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_0_4; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_0_5; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_0_6; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_0_7; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_1_0; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_1_1; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_1_2; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_1_3; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_1_4; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_1_5; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_1_6; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_1_7; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_2_0; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_2_1; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_2_2; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_2_3; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_2_4; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_2_5; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_2_6; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_2_7; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_3_0; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_3_1; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_3_2; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_3_3; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_3_4; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_3_5; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_3_6; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_3_7; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_4_0; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_4_1; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_4_2; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_4_3; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_4_4; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_4_5; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_4_6; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_4_7; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_5_0; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_5_1; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_5_2; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_5_3; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_5_4; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_5_5; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_5_6; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_5_7; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_6_0; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_6_1; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_6_2; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_6_3; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_6_4; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_6_5; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_6_6; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_6_7; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_7_0; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_7_1; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_7_2; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_7_3; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_7_4; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_7_5; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_7_6; // @[VConvAlu.scala 55:16]
- reg [31:0] acc_7_7; // @[VConvAlu.scala 55:16]
- wire [2:0] _T = {io_op_conv,io_op_tran,io_op_clear}; // @[Cat.scala 31:58]
- wire [1:0] _T_4 = _T[1] + _T[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_64 = {{1'd0}, _T[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_6 = _GEN_64 + _T_4; // @[Bitwise.scala 48:55]
- wire [31:0] accum = io_op_conv ? acc_0_0 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_0_0_adatac = io_op_conv ? io_adata[31:0] : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_0_0_bdatac = io_op_conv ? io_bdata[31:0] : 32'h0; // @[Library.scala 32:8]
- wire dpa_0_0_as = dpa_0_0_adatac[7] & io_asign; // @[VDot.scala 40:34]
- wire dpa_0_0_bs = dpa_0_0_bdatac[7] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_0_aval_T_2 = {dpa_0_0_as,dpa_0_0_adatac[7:0]}; // @[VDot.scala 42:52]
- wire [8:0] _dpa_0_0_aval_T_3 = io_op_conv ? io_abias : 9'h0; // @[VDot.scala 42:69]
- wire [9:0] dpa_0_0_aval = $signed(_dpa_0_0_aval_T_2) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [8:0] _dpa_0_0_bval_T_2 = {dpa_0_0_bs,dpa_0_0_bdatac[7:0]}; // @[VDot.scala 43:52]
- wire [8:0] _dpa_0_0_bval_T_3 = io_op_conv ? io_bbias : 9'h0; // @[VDot.scala 43:69]
- wire [9:0] dpa_0_0_bval = $signed(_dpa_0_0_bval_T_2) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_0_mval = $signed(dpa_0_0_aval) * $signed(dpa_0_0_bval); // @[VDot.scala 44:23]
- wire dpa_0_0_as_1 = dpa_0_0_adatac[15] & io_asign; // @[VDot.scala 40:34]
- wire dpa_0_0_bs_1 = dpa_0_0_bdatac[15] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_0_aval_T_6 = {dpa_0_0_as_1,dpa_0_0_adatac[15:8]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_0_0_aval_1 = $signed(_dpa_0_0_aval_T_6) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [8:0] _dpa_0_0_bval_T_6 = {dpa_0_0_bs_1,dpa_0_0_bdatac[15:8]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_0_bval_1 = $signed(_dpa_0_0_bval_T_6) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_0_mval_1 = $signed(dpa_0_0_aval_1) * $signed(dpa_0_0_bval_1); // @[VDot.scala 44:23]
- wire dpa_0_0_as_2 = dpa_0_0_adatac[23] & io_asign; // @[VDot.scala 40:34]
- wire dpa_0_0_bs_2 = dpa_0_0_bdatac[23] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_0_aval_T_10 = {dpa_0_0_as_2,dpa_0_0_adatac[23:16]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_0_0_aval_2 = $signed(_dpa_0_0_aval_T_10) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [8:0] _dpa_0_0_bval_T_10 = {dpa_0_0_bs_2,dpa_0_0_bdatac[23:16]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_0_bval_2 = $signed(_dpa_0_0_bval_T_10) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_0_mval_2 = $signed(dpa_0_0_aval_2) * $signed(dpa_0_0_bval_2); // @[VDot.scala 44:23]
- wire dpa_0_0_as_3 = dpa_0_0_adatac[31] & io_asign; // @[VDot.scala 40:34]
- wire dpa_0_0_bs_3 = dpa_0_0_bdatac[31] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_0_aval_T_14 = {dpa_0_0_as_3,dpa_0_0_adatac[31:24]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_0_0_aval_3 = $signed(_dpa_0_0_aval_T_14) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [8:0] _dpa_0_0_bval_T_14 = {dpa_0_0_bs_3,dpa_0_0_bdatac[31:24]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_0_bval_3 = $signed(_dpa_0_0_bval_T_14) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_0_mval_3 = $signed(dpa_0_0_aval_3) * $signed(dpa_0_0_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_0_0_dotp_T = $signed(dpa_0_0_mval) + $signed(dpa_0_0_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_0_0_dotp_T_1 = $signed(dpa_0_0_mval_2) + $signed(dpa_0_0_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_0_0_dotp = $signed(_dpa_0_0_dotp_T) + $signed(_dpa_0_0_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_0_0_sdotp_T_2 = dpa_0_0_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_0_0_sdotp_lo = $signed(_dpa_0_0_dotp_T) + $signed(_dpa_0_0_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_0_0_sdotp = {_dpa_0_0_sdotp_T_2,dpa_0_0_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_0_0 = accum + dpa_0_0_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_1 = io_op_conv ? acc_0_1 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_0_1_bdatac = io_op_conv ? io_bdata[63:32] : 32'h0; // @[Library.scala 32:8]
- wire dpa_0_1_bs = dpa_0_1_bdatac[7] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_1_bval_T_2 = {dpa_0_1_bs,dpa_0_1_bdatac[7:0]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_1_bval = $signed(_dpa_0_1_bval_T_2) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_1_mval = $signed(dpa_0_0_aval) * $signed(dpa_0_1_bval); // @[VDot.scala 44:23]
- wire dpa_0_1_bs_1 = dpa_0_1_bdatac[15] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_1_bval_T_6 = {dpa_0_1_bs_1,dpa_0_1_bdatac[15:8]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_1_bval_1 = $signed(_dpa_0_1_bval_T_6) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_1_mval_1 = $signed(dpa_0_0_aval_1) * $signed(dpa_0_1_bval_1); // @[VDot.scala 44:23]
- wire dpa_0_1_bs_2 = dpa_0_1_bdatac[23] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_1_bval_T_10 = {dpa_0_1_bs_2,dpa_0_1_bdatac[23:16]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_1_bval_2 = $signed(_dpa_0_1_bval_T_10) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_1_mval_2 = $signed(dpa_0_0_aval_2) * $signed(dpa_0_1_bval_2); // @[VDot.scala 44:23]
- wire dpa_0_1_bs_3 = dpa_0_1_bdatac[31] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_1_bval_T_14 = {dpa_0_1_bs_3,dpa_0_1_bdatac[31:24]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_1_bval_3 = $signed(_dpa_0_1_bval_T_14) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_1_mval_3 = $signed(dpa_0_0_aval_3) * $signed(dpa_0_1_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_0_1_dotp_T = $signed(dpa_0_1_mval) + $signed(dpa_0_1_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_0_1_dotp_T_1 = $signed(dpa_0_1_mval_2) + $signed(dpa_0_1_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_0_1_dotp = $signed(_dpa_0_1_dotp_T) + $signed(_dpa_0_1_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_0_1_sdotp_T_2 = dpa_0_1_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_0_1_sdotp_lo = $signed(_dpa_0_1_dotp_T) + $signed(_dpa_0_1_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_0_1_sdotp = {_dpa_0_1_sdotp_T_2,dpa_0_1_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_0_1 = accum_1 + dpa_0_1_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_2 = io_op_conv ? acc_0_2 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_0_2_bdatac = io_op_conv ? io_bdata[95:64] : 32'h0; // @[Library.scala 32:8]
- wire dpa_0_2_bs = dpa_0_2_bdatac[7] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_2_bval_T_2 = {dpa_0_2_bs,dpa_0_2_bdatac[7:0]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_2_bval = $signed(_dpa_0_2_bval_T_2) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_2_mval = $signed(dpa_0_0_aval) * $signed(dpa_0_2_bval); // @[VDot.scala 44:23]
- wire dpa_0_2_bs_1 = dpa_0_2_bdatac[15] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_2_bval_T_6 = {dpa_0_2_bs_1,dpa_0_2_bdatac[15:8]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_2_bval_1 = $signed(_dpa_0_2_bval_T_6) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_2_mval_1 = $signed(dpa_0_0_aval_1) * $signed(dpa_0_2_bval_1); // @[VDot.scala 44:23]
- wire dpa_0_2_bs_2 = dpa_0_2_bdatac[23] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_2_bval_T_10 = {dpa_0_2_bs_2,dpa_0_2_bdatac[23:16]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_2_bval_2 = $signed(_dpa_0_2_bval_T_10) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_2_mval_2 = $signed(dpa_0_0_aval_2) * $signed(dpa_0_2_bval_2); // @[VDot.scala 44:23]
- wire dpa_0_2_bs_3 = dpa_0_2_bdatac[31] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_2_bval_T_14 = {dpa_0_2_bs_3,dpa_0_2_bdatac[31:24]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_2_bval_3 = $signed(_dpa_0_2_bval_T_14) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_2_mval_3 = $signed(dpa_0_0_aval_3) * $signed(dpa_0_2_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_0_2_dotp_T = $signed(dpa_0_2_mval) + $signed(dpa_0_2_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_0_2_dotp_T_1 = $signed(dpa_0_2_mval_2) + $signed(dpa_0_2_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_0_2_dotp = $signed(_dpa_0_2_dotp_T) + $signed(_dpa_0_2_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_0_2_sdotp_T_2 = dpa_0_2_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_0_2_sdotp_lo = $signed(_dpa_0_2_dotp_T) + $signed(_dpa_0_2_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_0_2_sdotp = {_dpa_0_2_sdotp_T_2,dpa_0_2_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_0_2 = accum_2 + dpa_0_2_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_3 = io_op_conv ? acc_0_3 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_0_3_bdatac = io_op_conv ? io_bdata[127:96] : 32'h0; // @[Library.scala 32:8]
- wire dpa_0_3_bs = dpa_0_3_bdatac[7] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_3_bval_T_2 = {dpa_0_3_bs,dpa_0_3_bdatac[7:0]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_3_bval = $signed(_dpa_0_3_bval_T_2) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_3_mval = $signed(dpa_0_0_aval) * $signed(dpa_0_3_bval); // @[VDot.scala 44:23]
- wire dpa_0_3_bs_1 = dpa_0_3_bdatac[15] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_3_bval_T_6 = {dpa_0_3_bs_1,dpa_0_3_bdatac[15:8]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_3_bval_1 = $signed(_dpa_0_3_bval_T_6) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_3_mval_1 = $signed(dpa_0_0_aval_1) * $signed(dpa_0_3_bval_1); // @[VDot.scala 44:23]
- wire dpa_0_3_bs_2 = dpa_0_3_bdatac[23] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_3_bval_T_10 = {dpa_0_3_bs_2,dpa_0_3_bdatac[23:16]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_3_bval_2 = $signed(_dpa_0_3_bval_T_10) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_3_mval_2 = $signed(dpa_0_0_aval_2) * $signed(dpa_0_3_bval_2); // @[VDot.scala 44:23]
- wire dpa_0_3_bs_3 = dpa_0_3_bdatac[31] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_3_bval_T_14 = {dpa_0_3_bs_3,dpa_0_3_bdatac[31:24]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_3_bval_3 = $signed(_dpa_0_3_bval_T_14) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_3_mval_3 = $signed(dpa_0_0_aval_3) * $signed(dpa_0_3_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_0_3_dotp_T = $signed(dpa_0_3_mval) + $signed(dpa_0_3_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_0_3_dotp_T_1 = $signed(dpa_0_3_mval_2) + $signed(dpa_0_3_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_0_3_dotp = $signed(_dpa_0_3_dotp_T) + $signed(_dpa_0_3_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_0_3_sdotp_T_2 = dpa_0_3_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_0_3_sdotp_lo = $signed(_dpa_0_3_dotp_T) + $signed(_dpa_0_3_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_0_3_sdotp = {_dpa_0_3_sdotp_T_2,dpa_0_3_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_0_3 = accum_3 + dpa_0_3_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_4 = io_op_conv ? acc_0_4 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_0_4_bdatac = io_op_conv ? io_bdata[159:128] : 32'h0; // @[Library.scala 32:8]
- wire dpa_0_4_bs = dpa_0_4_bdatac[7] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_4_bval_T_2 = {dpa_0_4_bs,dpa_0_4_bdatac[7:0]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_4_bval = $signed(_dpa_0_4_bval_T_2) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_4_mval = $signed(dpa_0_0_aval) * $signed(dpa_0_4_bval); // @[VDot.scala 44:23]
- wire dpa_0_4_bs_1 = dpa_0_4_bdatac[15] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_4_bval_T_6 = {dpa_0_4_bs_1,dpa_0_4_bdatac[15:8]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_4_bval_1 = $signed(_dpa_0_4_bval_T_6) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_4_mval_1 = $signed(dpa_0_0_aval_1) * $signed(dpa_0_4_bval_1); // @[VDot.scala 44:23]
- wire dpa_0_4_bs_2 = dpa_0_4_bdatac[23] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_4_bval_T_10 = {dpa_0_4_bs_2,dpa_0_4_bdatac[23:16]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_4_bval_2 = $signed(_dpa_0_4_bval_T_10) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_4_mval_2 = $signed(dpa_0_0_aval_2) * $signed(dpa_0_4_bval_2); // @[VDot.scala 44:23]
- wire dpa_0_4_bs_3 = dpa_0_4_bdatac[31] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_4_bval_T_14 = {dpa_0_4_bs_3,dpa_0_4_bdatac[31:24]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_4_bval_3 = $signed(_dpa_0_4_bval_T_14) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_4_mval_3 = $signed(dpa_0_0_aval_3) * $signed(dpa_0_4_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_0_4_dotp_T = $signed(dpa_0_4_mval) + $signed(dpa_0_4_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_0_4_dotp_T_1 = $signed(dpa_0_4_mval_2) + $signed(dpa_0_4_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_0_4_dotp = $signed(_dpa_0_4_dotp_T) + $signed(_dpa_0_4_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_0_4_sdotp_T_2 = dpa_0_4_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_0_4_sdotp_lo = $signed(_dpa_0_4_dotp_T) + $signed(_dpa_0_4_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_0_4_sdotp = {_dpa_0_4_sdotp_T_2,dpa_0_4_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_0_4 = accum_4 + dpa_0_4_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_5 = io_op_conv ? acc_0_5 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_0_5_bdatac = io_op_conv ? io_bdata[191:160] : 32'h0; // @[Library.scala 32:8]
- wire dpa_0_5_bs = dpa_0_5_bdatac[7] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_5_bval_T_2 = {dpa_0_5_bs,dpa_0_5_bdatac[7:0]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_5_bval = $signed(_dpa_0_5_bval_T_2) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_5_mval = $signed(dpa_0_0_aval) * $signed(dpa_0_5_bval); // @[VDot.scala 44:23]
- wire dpa_0_5_bs_1 = dpa_0_5_bdatac[15] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_5_bval_T_6 = {dpa_0_5_bs_1,dpa_0_5_bdatac[15:8]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_5_bval_1 = $signed(_dpa_0_5_bval_T_6) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_5_mval_1 = $signed(dpa_0_0_aval_1) * $signed(dpa_0_5_bval_1); // @[VDot.scala 44:23]
- wire dpa_0_5_bs_2 = dpa_0_5_bdatac[23] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_5_bval_T_10 = {dpa_0_5_bs_2,dpa_0_5_bdatac[23:16]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_5_bval_2 = $signed(_dpa_0_5_bval_T_10) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_5_mval_2 = $signed(dpa_0_0_aval_2) * $signed(dpa_0_5_bval_2); // @[VDot.scala 44:23]
- wire dpa_0_5_bs_3 = dpa_0_5_bdatac[31] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_5_bval_T_14 = {dpa_0_5_bs_3,dpa_0_5_bdatac[31:24]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_5_bval_3 = $signed(_dpa_0_5_bval_T_14) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_5_mval_3 = $signed(dpa_0_0_aval_3) * $signed(dpa_0_5_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_0_5_dotp_T = $signed(dpa_0_5_mval) + $signed(dpa_0_5_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_0_5_dotp_T_1 = $signed(dpa_0_5_mval_2) + $signed(dpa_0_5_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_0_5_dotp = $signed(_dpa_0_5_dotp_T) + $signed(_dpa_0_5_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_0_5_sdotp_T_2 = dpa_0_5_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_0_5_sdotp_lo = $signed(_dpa_0_5_dotp_T) + $signed(_dpa_0_5_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_0_5_sdotp = {_dpa_0_5_sdotp_T_2,dpa_0_5_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_0_5 = accum_5 + dpa_0_5_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_6 = io_op_conv ? acc_0_6 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_0_6_bdatac = io_op_conv ? io_bdata[223:192] : 32'h0; // @[Library.scala 32:8]
- wire dpa_0_6_bs = dpa_0_6_bdatac[7] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_6_bval_T_2 = {dpa_0_6_bs,dpa_0_6_bdatac[7:0]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_6_bval = $signed(_dpa_0_6_bval_T_2) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_6_mval = $signed(dpa_0_0_aval) * $signed(dpa_0_6_bval); // @[VDot.scala 44:23]
- wire dpa_0_6_bs_1 = dpa_0_6_bdatac[15] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_6_bval_T_6 = {dpa_0_6_bs_1,dpa_0_6_bdatac[15:8]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_6_bval_1 = $signed(_dpa_0_6_bval_T_6) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_6_mval_1 = $signed(dpa_0_0_aval_1) * $signed(dpa_0_6_bval_1); // @[VDot.scala 44:23]
- wire dpa_0_6_bs_2 = dpa_0_6_bdatac[23] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_6_bval_T_10 = {dpa_0_6_bs_2,dpa_0_6_bdatac[23:16]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_6_bval_2 = $signed(_dpa_0_6_bval_T_10) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_6_mval_2 = $signed(dpa_0_0_aval_2) * $signed(dpa_0_6_bval_2); // @[VDot.scala 44:23]
- wire dpa_0_6_bs_3 = dpa_0_6_bdatac[31] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_6_bval_T_14 = {dpa_0_6_bs_3,dpa_0_6_bdatac[31:24]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_6_bval_3 = $signed(_dpa_0_6_bval_T_14) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_6_mval_3 = $signed(dpa_0_0_aval_3) * $signed(dpa_0_6_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_0_6_dotp_T = $signed(dpa_0_6_mval) + $signed(dpa_0_6_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_0_6_dotp_T_1 = $signed(dpa_0_6_mval_2) + $signed(dpa_0_6_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_0_6_dotp = $signed(_dpa_0_6_dotp_T) + $signed(_dpa_0_6_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_0_6_sdotp_T_2 = dpa_0_6_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_0_6_sdotp_lo = $signed(_dpa_0_6_dotp_T) + $signed(_dpa_0_6_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_0_6_sdotp = {_dpa_0_6_sdotp_T_2,dpa_0_6_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_0_6 = accum_6 + dpa_0_6_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_7 = io_op_conv ? acc_0_7 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_0_7_bdatac = io_op_conv ? io_bdata[255:224] : 32'h0; // @[Library.scala 32:8]
- wire dpa_0_7_bs = dpa_0_7_bdatac[7] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_7_bval_T_2 = {dpa_0_7_bs,dpa_0_7_bdatac[7:0]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_7_bval = $signed(_dpa_0_7_bval_T_2) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_7_mval = $signed(dpa_0_0_aval) * $signed(dpa_0_7_bval); // @[VDot.scala 44:23]
- wire dpa_0_7_bs_1 = dpa_0_7_bdatac[15] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_7_bval_T_6 = {dpa_0_7_bs_1,dpa_0_7_bdatac[15:8]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_7_bval_1 = $signed(_dpa_0_7_bval_T_6) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_7_mval_1 = $signed(dpa_0_0_aval_1) * $signed(dpa_0_7_bval_1); // @[VDot.scala 44:23]
- wire dpa_0_7_bs_2 = dpa_0_7_bdatac[23] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_7_bval_T_10 = {dpa_0_7_bs_2,dpa_0_7_bdatac[23:16]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_7_bval_2 = $signed(_dpa_0_7_bval_T_10) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_7_mval_2 = $signed(dpa_0_0_aval_2) * $signed(dpa_0_7_bval_2); // @[VDot.scala 44:23]
- wire dpa_0_7_bs_3 = dpa_0_7_bdatac[31] & io_bsign; // @[VDot.scala 41:34]
- wire [8:0] _dpa_0_7_bval_T_14 = {dpa_0_7_bs_3,dpa_0_7_bdatac[31:24]}; // @[VDot.scala 43:52]
- wire [9:0] dpa_0_7_bval_3 = $signed(_dpa_0_7_bval_T_14) + $signed(_dpa_0_0_bval_T_3); // @[VDot.scala 43:59]
- wire [19:0] dpa_0_7_mval_3 = $signed(dpa_0_0_aval_3) * $signed(dpa_0_7_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_0_7_dotp_T = $signed(dpa_0_7_mval) + $signed(dpa_0_7_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_0_7_dotp_T_1 = $signed(dpa_0_7_mval_2) + $signed(dpa_0_7_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_0_7_dotp = $signed(_dpa_0_7_dotp_T) + $signed(_dpa_0_7_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_0_7_sdotp_T_2 = dpa_0_7_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_0_7_sdotp_lo = $signed(_dpa_0_7_dotp_T) + $signed(_dpa_0_7_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_0_7_sdotp = {_dpa_0_7_sdotp_T_2,dpa_0_7_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_0_7 = accum_7 + dpa_0_7_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_8 = io_op_conv ? acc_1_0 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_1_0_adatac = io_op_conv ? io_adata[63:32] : 32'h0; // @[Library.scala 32:8]
- wire dpa_1_0_as = dpa_1_0_adatac[7] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_1_0_aval_T_2 = {dpa_1_0_as,dpa_1_0_adatac[7:0]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_1_0_aval = $signed(_dpa_1_0_aval_T_2) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_1_0_mval = $signed(dpa_1_0_aval) * $signed(dpa_0_0_bval); // @[VDot.scala 44:23]
- wire dpa_1_0_as_1 = dpa_1_0_adatac[15] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_1_0_aval_T_6 = {dpa_1_0_as_1,dpa_1_0_adatac[15:8]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_1_0_aval_1 = $signed(_dpa_1_0_aval_T_6) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_1_0_mval_1 = $signed(dpa_1_0_aval_1) * $signed(dpa_0_0_bval_1); // @[VDot.scala 44:23]
- wire dpa_1_0_as_2 = dpa_1_0_adatac[23] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_1_0_aval_T_10 = {dpa_1_0_as_2,dpa_1_0_adatac[23:16]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_1_0_aval_2 = $signed(_dpa_1_0_aval_T_10) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_1_0_mval_2 = $signed(dpa_1_0_aval_2) * $signed(dpa_0_0_bval_2); // @[VDot.scala 44:23]
- wire dpa_1_0_as_3 = dpa_1_0_adatac[31] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_1_0_aval_T_14 = {dpa_1_0_as_3,dpa_1_0_adatac[31:24]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_1_0_aval_3 = $signed(_dpa_1_0_aval_T_14) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_1_0_mval_3 = $signed(dpa_1_0_aval_3) * $signed(dpa_0_0_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_1_0_dotp_T = $signed(dpa_1_0_mval) + $signed(dpa_1_0_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_1_0_dotp_T_1 = $signed(dpa_1_0_mval_2) + $signed(dpa_1_0_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_1_0_dotp = $signed(_dpa_1_0_dotp_T) + $signed(_dpa_1_0_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_1_0_sdotp_T_2 = dpa_1_0_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_1_0_sdotp_lo = $signed(_dpa_1_0_dotp_T) + $signed(_dpa_1_0_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_1_0_sdotp = {_dpa_1_0_sdotp_T_2,dpa_1_0_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_1_0 = accum_8 + dpa_1_0_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_9 = io_op_conv ? acc_1_1 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_1_1_mval = $signed(dpa_1_0_aval) * $signed(dpa_0_1_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_1_mval_1 = $signed(dpa_1_0_aval_1) * $signed(dpa_0_1_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_1_mval_2 = $signed(dpa_1_0_aval_2) * $signed(dpa_0_1_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_1_mval_3 = $signed(dpa_1_0_aval_3) * $signed(dpa_0_1_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_1_1_dotp_T = $signed(dpa_1_1_mval) + $signed(dpa_1_1_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_1_1_dotp_T_1 = $signed(dpa_1_1_mval_2) + $signed(dpa_1_1_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_1_1_dotp = $signed(_dpa_1_1_dotp_T) + $signed(_dpa_1_1_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_1_1_sdotp_T_2 = dpa_1_1_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_1_1_sdotp_lo = $signed(_dpa_1_1_dotp_T) + $signed(_dpa_1_1_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_1_1_sdotp = {_dpa_1_1_sdotp_T_2,dpa_1_1_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_1_1 = accum_9 + dpa_1_1_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_10 = io_op_conv ? acc_1_2 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_1_2_mval = $signed(dpa_1_0_aval) * $signed(dpa_0_2_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_2_mval_1 = $signed(dpa_1_0_aval_1) * $signed(dpa_0_2_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_2_mval_2 = $signed(dpa_1_0_aval_2) * $signed(dpa_0_2_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_2_mval_3 = $signed(dpa_1_0_aval_3) * $signed(dpa_0_2_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_1_2_dotp_T = $signed(dpa_1_2_mval) + $signed(dpa_1_2_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_1_2_dotp_T_1 = $signed(dpa_1_2_mval_2) + $signed(dpa_1_2_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_1_2_dotp = $signed(_dpa_1_2_dotp_T) + $signed(_dpa_1_2_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_1_2_sdotp_T_2 = dpa_1_2_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_1_2_sdotp_lo = $signed(_dpa_1_2_dotp_T) + $signed(_dpa_1_2_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_1_2_sdotp = {_dpa_1_2_sdotp_T_2,dpa_1_2_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_1_2 = accum_10 + dpa_1_2_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_11 = io_op_conv ? acc_1_3 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_1_3_mval = $signed(dpa_1_0_aval) * $signed(dpa_0_3_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_3_mval_1 = $signed(dpa_1_0_aval_1) * $signed(dpa_0_3_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_3_mval_2 = $signed(dpa_1_0_aval_2) * $signed(dpa_0_3_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_3_mval_3 = $signed(dpa_1_0_aval_3) * $signed(dpa_0_3_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_1_3_dotp_T = $signed(dpa_1_3_mval) + $signed(dpa_1_3_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_1_3_dotp_T_1 = $signed(dpa_1_3_mval_2) + $signed(dpa_1_3_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_1_3_dotp = $signed(_dpa_1_3_dotp_T) + $signed(_dpa_1_3_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_1_3_sdotp_T_2 = dpa_1_3_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_1_3_sdotp_lo = $signed(_dpa_1_3_dotp_T) + $signed(_dpa_1_3_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_1_3_sdotp = {_dpa_1_3_sdotp_T_2,dpa_1_3_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_1_3 = accum_11 + dpa_1_3_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_12 = io_op_conv ? acc_1_4 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_1_4_mval = $signed(dpa_1_0_aval) * $signed(dpa_0_4_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_4_mval_1 = $signed(dpa_1_0_aval_1) * $signed(dpa_0_4_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_4_mval_2 = $signed(dpa_1_0_aval_2) * $signed(dpa_0_4_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_4_mval_3 = $signed(dpa_1_0_aval_3) * $signed(dpa_0_4_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_1_4_dotp_T = $signed(dpa_1_4_mval) + $signed(dpa_1_4_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_1_4_dotp_T_1 = $signed(dpa_1_4_mval_2) + $signed(dpa_1_4_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_1_4_dotp = $signed(_dpa_1_4_dotp_T) + $signed(_dpa_1_4_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_1_4_sdotp_T_2 = dpa_1_4_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_1_4_sdotp_lo = $signed(_dpa_1_4_dotp_T) + $signed(_dpa_1_4_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_1_4_sdotp = {_dpa_1_4_sdotp_T_2,dpa_1_4_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_1_4 = accum_12 + dpa_1_4_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_13 = io_op_conv ? acc_1_5 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_1_5_mval = $signed(dpa_1_0_aval) * $signed(dpa_0_5_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_5_mval_1 = $signed(dpa_1_0_aval_1) * $signed(dpa_0_5_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_5_mval_2 = $signed(dpa_1_0_aval_2) * $signed(dpa_0_5_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_5_mval_3 = $signed(dpa_1_0_aval_3) * $signed(dpa_0_5_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_1_5_dotp_T = $signed(dpa_1_5_mval) + $signed(dpa_1_5_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_1_5_dotp_T_1 = $signed(dpa_1_5_mval_2) + $signed(dpa_1_5_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_1_5_dotp = $signed(_dpa_1_5_dotp_T) + $signed(_dpa_1_5_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_1_5_sdotp_T_2 = dpa_1_5_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_1_5_sdotp_lo = $signed(_dpa_1_5_dotp_T) + $signed(_dpa_1_5_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_1_5_sdotp = {_dpa_1_5_sdotp_T_2,dpa_1_5_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_1_5 = accum_13 + dpa_1_5_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_14 = io_op_conv ? acc_1_6 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_1_6_mval = $signed(dpa_1_0_aval) * $signed(dpa_0_6_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_6_mval_1 = $signed(dpa_1_0_aval_1) * $signed(dpa_0_6_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_6_mval_2 = $signed(dpa_1_0_aval_2) * $signed(dpa_0_6_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_6_mval_3 = $signed(dpa_1_0_aval_3) * $signed(dpa_0_6_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_1_6_dotp_T = $signed(dpa_1_6_mval) + $signed(dpa_1_6_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_1_6_dotp_T_1 = $signed(dpa_1_6_mval_2) + $signed(dpa_1_6_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_1_6_dotp = $signed(_dpa_1_6_dotp_T) + $signed(_dpa_1_6_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_1_6_sdotp_T_2 = dpa_1_6_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_1_6_sdotp_lo = $signed(_dpa_1_6_dotp_T) + $signed(_dpa_1_6_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_1_6_sdotp = {_dpa_1_6_sdotp_T_2,dpa_1_6_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_1_6 = accum_14 + dpa_1_6_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_15 = io_op_conv ? acc_1_7 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_1_7_mval = $signed(dpa_1_0_aval) * $signed(dpa_0_7_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_7_mval_1 = $signed(dpa_1_0_aval_1) * $signed(dpa_0_7_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_7_mval_2 = $signed(dpa_1_0_aval_2) * $signed(dpa_0_7_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_1_7_mval_3 = $signed(dpa_1_0_aval_3) * $signed(dpa_0_7_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_1_7_dotp_T = $signed(dpa_1_7_mval) + $signed(dpa_1_7_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_1_7_dotp_T_1 = $signed(dpa_1_7_mval_2) + $signed(dpa_1_7_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_1_7_dotp = $signed(_dpa_1_7_dotp_T) + $signed(_dpa_1_7_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_1_7_sdotp_T_2 = dpa_1_7_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_1_7_sdotp_lo = $signed(_dpa_1_7_dotp_T) + $signed(_dpa_1_7_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_1_7_sdotp = {_dpa_1_7_sdotp_T_2,dpa_1_7_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_1_7 = accum_15 + dpa_1_7_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_16 = io_op_conv ? acc_2_0 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_2_0_adatac = io_op_conv ? io_adata[95:64] : 32'h0; // @[Library.scala 32:8]
- wire dpa_2_0_as = dpa_2_0_adatac[7] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_2_0_aval_T_2 = {dpa_2_0_as,dpa_2_0_adatac[7:0]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_2_0_aval = $signed(_dpa_2_0_aval_T_2) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_2_0_mval = $signed(dpa_2_0_aval) * $signed(dpa_0_0_bval); // @[VDot.scala 44:23]
- wire dpa_2_0_as_1 = dpa_2_0_adatac[15] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_2_0_aval_T_6 = {dpa_2_0_as_1,dpa_2_0_adatac[15:8]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_2_0_aval_1 = $signed(_dpa_2_0_aval_T_6) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_2_0_mval_1 = $signed(dpa_2_0_aval_1) * $signed(dpa_0_0_bval_1); // @[VDot.scala 44:23]
- wire dpa_2_0_as_2 = dpa_2_0_adatac[23] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_2_0_aval_T_10 = {dpa_2_0_as_2,dpa_2_0_adatac[23:16]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_2_0_aval_2 = $signed(_dpa_2_0_aval_T_10) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_2_0_mval_2 = $signed(dpa_2_0_aval_2) * $signed(dpa_0_0_bval_2); // @[VDot.scala 44:23]
- wire dpa_2_0_as_3 = dpa_2_0_adatac[31] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_2_0_aval_T_14 = {dpa_2_0_as_3,dpa_2_0_adatac[31:24]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_2_0_aval_3 = $signed(_dpa_2_0_aval_T_14) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_2_0_mval_3 = $signed(dpa_2_0_aval_3) * $signed(dpa_0_0_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_2_0_dotp_T = $signed(dpa_2_0_mval) + $signed(dpa_2_0_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_2_0_dotp_T_1 = $signed(dpa_2_0_mval_2) + $signed(dpa_2_0_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_2_0_dotp = $signed(_dpa_2_0_dotp_T) + $signed(_dpa_2_0_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_2_0_sdotp_T_2 = dpa_2_0_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_2_0_sdotp_lo = $signed(_dpa_2_0_dotp_T) + $signed(_dpa_2_0_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_2_0_sdotp = {_dpa_2_0_sdotp_T_2,dpa_2_0_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_2_0 = accum_16 + dpa_2_0_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_17 = io_op_conv ? acc_2_1 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_2_1_mval = $signed(dpa_2_0_aval) * $signed(dpa_0_1_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_1_mval_1 = $signed(dpa_2_0_aval_1) * $signed(dpa_0_1_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_1_mval_2 = $signed(dpa_2_0_aval_2) * $signed(dpa_0_1_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_1_mval_3 = $signed(dpa_2_0_aval_3) * $signed(dpa_0_1_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_2_1_dotp_T = $signed(dpa_2_1_mval) + $signed(dpa_2_1_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_2_1_dotp_T_1 = $signed(dpa_2_1_mval_2) + $signed(dpa_2_1_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_2_1_dotp = $signed(_dpa_2_1_dotp_T) + $signed(_dpa_2_1_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_2_1_sdotp_T_2 = dpa_2_1_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_2_1_sdotp_lo = $signed(_dpa_2_1_dotp_T) + $signed(_dpa_2_1_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_2_1_sdotp = {_dpa_2_1_sdotp_T_2,dpa_2_1_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_2_1 = accum_17 + dpa_2_1_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_18 = io_op_conv ? acc_2_2 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_2_2_mval = $signed(dpa_2_0_aval) * $signed(dpa_0_2_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_2_mval_1 = $signed(dpa_2_0_aval_1) * $signed(dpa_0_2_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_2_mval_2 = $signed(dpa_2_0_aval_2) * $signed(dpa_0_2_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_2_mval_3 = $signed(dpa_2_0_aval_3) * $signed(dpa_0_2_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_2_2_dotp_T = $signed(dpa_2_2_mval) + $signed(dpa_2_2_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_2_2_dotp_T_1 = $signed(dpa_2_2_mval_2) + $signed(dpa_2_2_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_2_2_dotp = $signed(_dpa_2_2_dotp_T) + $signed(_dpa_2_2_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_2_2_sdotp_T_2 = dpa_2_2_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_2_2_sdotp_lo = $signed(_dpa_2_2_dotp_T) + $signed(_dpa_2_2_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_2_2_sdotp = {_dpa_2_2_sdotp_T_2,dpa_2_2_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_2_2 = accum_18 + dpa_2_2_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_19 = io_op_conv ? acc_2_3 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_2_3_mval = $signed(dpa_2_0_aval) * $signed(dpa_0_3_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_3_mval_1 = $signed(dpa_2_0_aval_1) * $signed(dpa_0_3_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_3_mval_2 = $signed(dpa_2_0_aval_2) * $signed(dpa_0_3_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_3_mval_3 = $signed(dpa_2_0_aval_3) * $signed(dpa_0_3_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_2_3_dotp_T = $signed(dpa_2_3_mval) + $signed(dpa_2_3_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_2_3_dotp_T_1 = $signed(dpa_2_3_mval_2) + $signed(dpa_2_3_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_2_3_dotp = $signed(_dpa_2_3_dotp_T) + $signed(_dpa_2_3_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_2_3_sdotp_T_2 = dpa_2_3_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_2_3_sdotp_lo = $signed(_dpa_2_3_dotp_T) + $signed(_dpa_2_3_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_2_3_sdotp = {_dpa_2_3_sdotp_T_2,dpa_2_3_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_2_3 = accum_19 + dpa_2_3_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_20 = io_op_conv ? acc_2_4 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_2_4_mval = $signed(dpa_2_0_aval) * $signed(dpa_0_4_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_4_mval_1 = $signed(dpa_2_0_aval_1) * $signed(dpa_0_4_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_4_mval_2 = $signed(dpa_2_0_aval_2) * $signed(dpa_0_4_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_4_mval_3 = $signed(dpa_2_0_aval_3) * $signed(dpa_0_4_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_2_4_dotp_T = $signed(dpa_2_4_mval) + $signed(dpa_2_4_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_2_4_dotp_T_1 = $signed(dpa_2_4_mval_2) + $signed(dpa_2_4_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_2_4_dotp = $signed(_dpa_2_4_dotp_T) + $signed(_dpa_2_4_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_2_4_sdotp_T_2 = dpa_2_4_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_2_4_sdotp_lo = $signed(_dpa_2_4_dotp_T) + $signed(_dpa_2_4_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_2_4_sdotp = {_dpa_2_4_sdotp_T_2,dpa_2_4_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_2_4 = accum_20 + dpa_2_4_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_21 = io_op_conv ? acc_2_5 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_2_5_mval = $signed(dpa_2_0_aval) * $signed(dpa_0_5_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_5_mval_1 = $signed(dpa_2_0_aval_1) * $signed(dpa_0_5_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_5_mval_2 = $signed(dpa_2_0_aval_2) * $signed(dpa_0_5_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_5_mval_3 = $signed(dpa_2_0_aval_3) * $signed(dpa_0_5_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_2_5_dotp_T = $signed(dpa_2_5_mval) + $signed(dpa_2_5_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_2_5_dotp_T_1 = $signed(dpa_2_5_mval_2) + $signed(dpa_2_5_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_2_5_dotp = $signed(_dpa_2_5_dotp_T) + $signed(_dpa_2_5_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_2_5_sdotp_T_2 = dpa_2_5_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_2_5_sdotp_lo = $signed(_dpa_2_5_dotp_T) + $signed(_dpa_2_5_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_2_5_sdotp = {_dpa_2_5_sdotp_T_2,dpa_2_5_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_2_5 = accum_21 + dpa_2_5_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_22 = io_op_conv ? acc_2_6 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_2_6_mval = $signed(dpa_2_0_aval) * $signed(dpa_0_6_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_6_mval_1 = $signed(dpa_2_0_aval_1) * $signed(dpa_0_6_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_6_mval_2 = $signed(dpa_2_0_aval_2) * $signed(dpa_0_6_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_6_mval_3 = $signed(dpa_2_0_aval_3) * $signed(dpa_0_6_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_2_6_dotp_T = $signed(dpa_2_6_mval) + $signed(dpa_2_6_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_2_6_dotp_T_1 = $signed(dpa_2_6_mval_2) + $signed(dpa_2_6_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_2_6_dotp = $signed(_dpa_2_6_dotp_T) + $signed(_dpa_2_6_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_2_6_sdotp_T_2 = dpa_2_6_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_2_6_sdotp_lo = $signed(_dpa_2_6_dotp_T) + $signed(_dpa_2_6_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_2_6_sdotp = {_dpa_2_6_sdotp_T_2,dpa_2_6_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_2_6 = accum_22 + dpa_2_6_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_23 = io_op_conv ? acc_2_7 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_2_7_mval = $signed(dpa_2_0_aval) * $signed(dpa_0_7_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_7_mval_1 = $signed(dpa_2_0_aval_1) * $signed(dpa_0_7_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_7_mval_2 = $signed(dpa_2_0_aval_2) * $signed(dpa_0_7_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_2_7_mval_3 = $signed(dpa_2_0_aval_3) * $signed(dpa_0_7_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_2_7_dotp_T = $signed(dpa_2_7_mval) + $signed(dpa_2_7_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_2_7_dotp_T_1 = $signed(dpa_2_7_mval_2) + $signed(dpa_2_7_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_2_7_dotp = $signed(_dpa_2_7_dotp_T) + $signed(_dpa_2_7_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_2_7_sdotp_T_2 = dpa_2_7_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_2_7_sdotp_lo = $signed(_dpa_2_7_dotp_T) + $signed(_dpa_2_7_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_2_7_sdotp = {_dpa_2_7_sdotp_T_2,dpa_2_7_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_2_7 = accum_23 + dpa_2_7_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_24 = io_op_conv ? acc_3_0 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_3_0_adatac = io_op_conv ? io_adata[127:96] : 32'h0; // @[Library.scala 32:8]
- wire dpa_3_0_as = dpa_3_0_adatac[7] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_3_0_aval_T_2 = {dpa_3_0_as,dpa_3_0_adatac[7:0]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_3_0_aval = $signed(_dpa_3_0_aval_T_2) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_3_0_mval = $signed(dpa_3_0_aval) * $signed(dpa_0_0_bval); // @[VDot.scala 44:23]
- wire dpa_3_0_as_1 = dpa_3_0_adatac[15] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_3_0_aval_T_6 = {dpa_3_0_as_1,dpa_3_0_adatac[15:8]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_3_0_aval_1 = $signed(_dpa_3_0_aval_T_6) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_3_0_mval_1 = $signed(dpa_3_0_aval_1) * $signed(dpa_0_0_bval_1); // @[VDot.scala 44:23]
- wire dpa_3_0_as_2 = dpa_3_0_adatac[23] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_3_0_aval_T_10 = {dpa_3_0_as_2,dpa_3_0_adatac[23:16]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_3_0_aval_2 = $signed(_dpa_3_0_aval_T_10) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_3_0_mval_2 = $signed(dpa_3_0_aval_2) * $signed(dpa_0_0_bval_2); // @[VDot.scala 44:23]
- wire dpa_3_0_as_3 = dpa_3_0_adatac[31] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_3_0_aval_T_14 = {dpa_3_0_as_3,dpa_3_0_adatac[31:24]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_3_0_aval_3 = $signed(_dpa_3_0_aval_T_14) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_3_0_mval_3 = $signed(dpa_3_0_aval_3) * $signed(dpa_0_0_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_3_0_dotp_T = $signed(dpa_3_0_mval) + $signed(dpa_3_0_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_3_0_dotp_T_1 = $signed(dpa_3_0_mval_2) + $signed(dpa_3_0_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_3_0_dotp = $signed(_dpa_3_0_dotp_T) + $signed(_dpa_3_0_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_3_0_sdotp_T_2 = dpa_3_0_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_3_0_sdotp_lo = $signed(_dpa_3_0_dotp_T) + $signed(_dpa_3_0_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_3_0_sdotp = {_dpa_3_0_sdotp_T_2,dpa_3_0_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_3_0 = accum_24 + dpa_3_0_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_25 = io_op_conv ? acc_3_1 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_3_1_mval = $signed(dpa_3_0_aval) * $signed(dpa_0_1_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_1_mval_1 = $signed(dpa_3_0_aval_1) * $signed(dpa_0_1_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_1_mval_2 = $signed(dpa_3_0_aval_2) * $signed(dpa_0_1_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_1_mval_3 = $signed(dpa_3_0_aval_3) * $signed(dpa_0_1_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_3_1_dotp_T = $signed(dpa_3_1_mval) + $signed(dpa_3_1_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_3_1_dotp_T_1 = $signed(dpa_3_1_mval_2) + $signed(dpa_3_1_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_3_1_dotp = $signed(_dpa_3_1_dotp_T) + $signed(_dpa_3_1_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_3_1_sdotp_T_2 = dpa_3_1_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_3_1_sdotp_lo = $signed(_dpa_3_1_dotp_T) + $signed(_dpa_3_1_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_3_1_sdotp = {_dpa_3_1_sdotp_T_2,dpa_3_1_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_3_1 = accum_25 + dpa_3_1_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_26 = io_op_conv ? acc_3_2 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_3_2_mval = $signed(dpa_3_0_aval) * $signed(dpa_0_2_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_2_mval_1 = $signed(dpa_3_0_aval_1) * $signed(dpa_0_2_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_2_mval_2 = $signed(dpa_3_0_aval_2) * $signed(dpa_0_2_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_2_mval_3 = $signed(dpa_3_0_aval_3) * $signed(dpa_0_2_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_3_2_dotp_T = $signed(dpa_3_2_mval) + $signed(dpa_3_2_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_3_2_dotp_T_1 = $signed(dpa_3_2_mval_2) + $signed(dpa_3_2_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_3_2_dotp = $signed(_dpa_3_2_dotp_T) + $signed(_dpa_3_2_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_3_2_sdotp_T_2 = dpa_3_2_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_3_2_sdotp_lo = $signed(_dpa_3_2_dotp_T) + $signed(_dpa_3_2_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_3_2_sdotp = {_dpa_3_2_sdotp_T_2,dpa_3_2_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_3_2 = accum_26 + dpa_3_2_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_27 = io_op_conv ? acc_3_3 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_3_3_mval = $signed(dpa_3_0_aval) * $signed(dpa_0_3_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_3_mval_1 = $signed(dpa_3_0_aval_1) * $signed(dpa_0_3_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_3_mval_2 = $signed(dpa_3_0_aval_2) * $signed(dpa_0_3_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_3_mval_3 = $signed(dpa_3_0_aval_3) * $signed(dpa_0_3_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_3_3_dotp_T = $signed(dpa_3_3_mval) + $signed(dpa_3_3_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_3_3_dotp_T_1 = $signed(dpa_3_3_mval_2) + $signed(dpa_3_3_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_3_3_dotp = $signed(_dpa_3_3_dotp_T) + $signed(_dpa_3_3_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_3_3_sdotp_T_2 = dpa_3_3_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_3_3_sdotp_lo = $signed(_dpa_3_3_dotp_T) + $signed(_dpa_3_3_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_3_3_sdotp = {_dpa_3_3_sdotp_T_2,dpa_3_3_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_3_3 = accum_27 + dpa_3_3_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_28 = io_op_conv ? acc_3_4 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_3_4_mval = $signed(dpa_3_0_aval) * $signed(dpa_0_4_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_4_mval_1 = $signed(dpa_3_0_aval_1) * $signed(dpa_0_4_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_4_mval_2 = $signed(dpa_3_0_aval_2) * $signed(dpa_0_4_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_4_mval_3 = $signed(dpa_3_0_aval_3) * $signed(dpa_0_4_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_3_4_dotp_T = $signed(dpa_3_4_mval) + $signed(dpa_3_4_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_3_4_dotp_T_1 = $signed(dpa_3_4_mval_2) + $signed(dpa_3_4_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_3_4_dotp = $signed(_dpa_3_4_dotp_T) + $signed(_dpa_3_4_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_3_4_sdotp_T_2 = dpa_3_4_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_3_4_sdotp_lo = $signed(_dpa_3_4_dotp_T) + $signed(_dpa_3_4_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_3_4_sdotp = {_dpa_3_4_sdotp_T_2,dpa_3_4_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_3_4 = accum_28 + dpa_3_4_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_29 = io_op_conv ? acc_3_5 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_3_5_mval = $signed(dpa_3_0_aval) * $signed(dpa_0_5_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_5_mval_1 = $signed(dpa_3_0_aval_1) * $signed(dpa_0_5_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_5_mval_2 = $signed(dpa_3_0_aval_2) * $signed(dpa_0_5_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_5_mval_3 = $signed(dpa_3_0_aval_3) * $signed(dpa_0_5_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_3_5_dotp_T = $signed(dpa_3_5_mval) + $signed(dpa_3_5_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_3_5_dotp_T_1 = $signed(dpa_3_5_mval_2) + $signed(dpa_3_5_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_3_5_dotp = $signed(_dpa_3_5_dotp_T) + $signed(_dpa_3_5_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_3_5_sdotp_T_2 = dpa_3_5_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_3_5_sdotp_lo = $signed(_dpa_3_5_dotp_T) + $signed(_dpa_3_5_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_3_5_sdotp = {_dpa_3_5_sdotp_T_2,dpa_3_5_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_3_5 = accum_29 + dpa_3_5_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_30 = io_op_conv ? acc_3_6 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_3_6_mval = $signed(dpa_3_0_aval) * $signed(dpa_0_6_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_6_mval_1 = $signed(dpa_3_0_aval_1) * $signed(dpa_0_6_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_6_mval_2 = $signed(dpa_3_0_aval_2) * $signed(dpa_0_6_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_6_mval_3 = $signed(dpa_3_0_aval_3) * $signed(dpa_0_6_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_3_6_dotp_T = $signed(dpa_3_6_mval) + $signed(dpa_3_6_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_3_6_dotp_T_1 = $signed(dpa_3_6_mval_2) + $signed(dpa_3_6_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_3_6_dotp = $signed(_dpa_3_6_dotp_T) + $signed(_dpa_3_6_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_3_6_sdotp_T_2 = dpa_3_6_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_3_6_sdotp_lo = $signed(_dpa_3_6_dotp_T) + $signed(_dpa_3_6_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_3_6_sdotp = {_dpa_3_6_sdotp_T_2,dpa_3_6_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_3_6 = accum_30 + dpa_3_6_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_31 = io_op_conv ? acc_3_7 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_3_7_mval = $signed(dpa_3_0_aval) * $signed(dpa_0_7_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_7_mval_1 = $signed(dpa_3_0_aval_1) * $signed(dpa_0_7_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_7_mval_2 = $signed(dpa_3_0_aval_2) * $signed(dpa_0_7_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_3_7_mval_3 = $signed(dpa_3_0_aval_3) * $signed(dpa_0_7_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_3_7_dotp_T = $signed(dpa_3_7_mval) + $signed(dpa_3_7_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_3_7_dotp_T_1 = $signed(dpa_3_7_mval_2) + $signed(dpa_3_7_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_3_7_dotp = $signed(_dpa_3_7_dotp_T) + $signed(_dpa_3_7_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_3_7_sdotp_T_2 = dpa_3_7_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_3_7_sdotp_lo = $signed(_dpa_3_7_dotp_T) + $signed(_dpa_3_7_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_3_7_sdotp = {_dpa_3_7_sdotp_T_2,dpa_3_7_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_3_7 = accum_31 + dpa_3_7_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_32 = io_op_conv ? acc_4_0 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_4_0_adatac = io_op_conv ? io_adata[159:128] : 32'h0; // @[Library.scala 32:8]
- wire dpa_4_0_as = dpa_4_0_adatac[7] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_4_0_aval_T_2 = {dpa_4_0_as,dpa_4_0_adatac[7:0]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_4_0_aval = $signed(_dpa_4_0_aval_T_2) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_4_0_mval = $signed(dpa_4_0_aval) * $signed(dpa_0_0_bval); // @[VDot.scala 44:23]
- wire dpa_4_0_as_1 = dpa_4_0_adatac[15] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_4_0_aval_T_6 = {dpa_4_0_as_1,dpa_4_0_adatac[15:8]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_4_0_aval_1 = $signed(_dpa_4_0_aval_T_6) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_4_0_mval_1 = $signed(dpa_4_0_aval_1) * $signed(dpa_0_0_bval_1); // @[VDot.scala 44:23]
- wire dpa_4_0_as_2 = dpa_4_0_adatac[23] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_4_0_aval_T_10 = {dpa_4_0_as_2,dpa_4_0_adatac[23:16]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_4_0_aval_2 = $signed(_dpa_4_0_aval_T_10) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_4_0_mval_2 = $signed(dpa_4_0_aval_2) * $signed(dpa_0_0_bval_2); // @[VDot.scala 44:23]
- wire dpa_4_0_as_3 = dpa_4_0_adatac[31] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_4_0_aval_T_14 = {dpa_4_0_as_3,dpa_4_0_adatac[31:24]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_4_0_aval_3 = $signed(_dpa_4_0_aval_T_14) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_4_0_mval_3 = $signed(dpa_4_0_aval_3) * $signed(dpa_0_0_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_4_0_dotp_T = $signed(dpa_4_0_mval) + $signed(dpa_4_0_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_4_0_dotp_T_1 = $signed(dpa_4_0_mval_2) + $signed(dpa_4_0_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_4_0_dotp = $signed(_dpa_4_0_dotp_T) + $signed(_dpa_4_0_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_4_0_sdotp_T_2 = dpa_4_0_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_4_0_sdotp_lo = $signed(_dpa_4_0_dotp_T) + $signed(_dpa_4_0_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_4_0_sdotp = {_dpa_4_0_sdotp_T_2,dpa_4_0_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_4_0 = accum_32 + dpa_4_0_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_33 = io_op_conv ? acc_4_1 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_4_1_mval = $signed(dpa_4_0_aval) * $signed(dpa_0_1_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_1_mval_1 = $signed(dpa_4_0_aval_1) * $signed(dpa_0_1_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_1_mval_2 = $signed(dpa_4_0_aval_2) * $signed(dpa_0_1_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_1_mval_3 = $signed(dpa_4_0_aval_3) * $signed(dpa_0_1_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_4_1_dotp_T = $signed(dpa_4_1_mval) + $signed(dpa_4_1_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_4_1_dotp_T_1 = $signed(dpa_4_1_mval_2) + $signed(dpa_4_1_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_4_1_dotp = $signed(_dpa_4_1_dotp_T) + $signed(_dpa_4_1_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_4_1_sdotp_T_2 = dpa_4_1_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_4_1_sdotp_lo = $signed(_dpa_4_1_dotp_T) + $signed(_dpa_4_1_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_4_1_sdotp = {_dpa_4_1_sdotp_T_2,dpa_4_1_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_4_1 = accum_33 + dpa_4_1_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_34 = io_op_conv ? acc_4_2 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_4_2_mval = $signed(dpa_4_0_aval) * $signed(dpa_0_2_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_2_mval_1 = $signed(dpa_4_0_aval_1) * $signed(dpa_0_2_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_2_mval_2 = $signed(dpa_4_0_aval_2) * $signed(dpa_0_2_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_2_mval_3 = $signed(dpa_4_0_aval_3) * $signed(dpa_0_2_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_4_2_dotp_T = $signed(dpa_4_2_mval) + $signed(dpa_4_2_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_4_2_dotp_T_1 = $signed(dpa_4_2_mval_2) + $signed(dpa_4_2_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_4_2_dotp = $signed(_dpa_4_2_dotp_T) + $signed(_dpa_4_2_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_4_2_sdotp_T_2 = dpa_4_2_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_4_2_sdotp_lo = $signed(_dpa_4_2_dotp_T) + $signed(_dpa_4_2_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_4_2_sdotp = {_dpa_4_2_sdotp_T_2,dpa_4_2_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_4_2 = accum_34 + dpa_4_2_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_35 = io_op_conv ? acc_4_3 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_4_3_mval = $signed(dpa_4_0_aval) * $signed(dpa_0_3_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_3_mval_1 = $signed(dpa_4_0_aval_1) * $signed(dpa_0_3_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_3_mval_2 = $signed(dpa_4_0_aval_2) * $signed(dpa_0_3_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_3_mval_3 = $signed(dpa_4_0_aval_3) * $signed(dpa_0_3_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_4_3_dotp_T = $signed(dpa_4_3_mval) + $signed(dpa_4_3_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_4_3_dotp_T_1 = $signed(dpa_4_3_mval_2) + $signed(dpa_4_3_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_4_3_dotp = $signed(_dpa_4_3_dotp_T) + $signed(_dpa_4_3_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_4_3_sdotp_T_2 = dpa_4_3_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_4_3_sdotp_lo = $signed(_dpa_4_3_dotp_T) + $signed(_dpa_4_3_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_4_3_sdotp = {_dpa_4_3_sdotp_T_2,dpa_4_3_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_4_3 = accum_35 + dpa_4_3_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_36 = io_op_conv ? acc_4_4 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_4_4_mval = $signed(dpa_4_0_aval) * $signed(dpa_0_4_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_4_mval_1 = $signed(dpa_4_0_aval_1) * $signed(dpa_0_4_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_4_mval_2 = $signed(dpa_4_0_aval_2) * $signed(dpa_0_4_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_4_mval_3 = $signed(dpa_4_0_aval_3) * $signed(dpa_0_4_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_4_4_dotp_T = $signed(dpa_4_4_mval) + $signed(dpa_4_4_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_4_4_dotp_T_1 = $signed(dpa_4_4_mval_2) + $signed(dpa_4_4_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_4_4_dotp = $signed(_dpa_4_4_dotp_T) + $signed(_dpa_4_4_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_4_4_sdotp_T_2 = dpa_4_4_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_4_4_sdotp_lo = $signed(_dpa_4_4_dotp_T) + $signed(_dpa_4_4_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_4_4_sdotp = {_dpa_4_4_sdotp_T_2,dpa_4_4_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_4_4 = accum_36 + dpa_4_4_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_37 = io_op_conv ? acc_4_5 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_4_5_mval = $signed(dpa_4_0_aval) * $signed(dpa_0_5_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_5_mval_1 = $signed(dpa_4_0_aval_1) * $signed(dpa_0_5_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_5_mval_2 = $signed(dpa_4_0_aval_2) * $signed(dpa_0_5_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_5_mval_3 = $signed(dpa_4_0_aval_3) * $signed(dpa_0_5_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_4_5_dotp_T = $signed(dpa_4_5_mval) + $signed(dpa_4_5_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_4_5_dotp_T_1 = $signed(dpa_4_5_mval_2) + $signed(dpa_4_5_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_4_5_dotp = $signed(_dpa_4_5_dotp_T) + $signed(_dpa_4_5_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_4_5_sdotp_T_2 = dpa_4_5_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_4_5_sdotp_lo = $signed(_dpa_4_5_dotp_T) + $signed(_dpa_4_5_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_4_5_sdotp = {_dpa_4_5_sdotp_T_2,dpa_4_5_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_4_5 = accum_37 + dpa_4_5_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_38 = io_op_conv ? acc_4_6 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_4_6_mval = $signed(dpa_4_0_aval) * $signed(dpa_0_6_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_6_mval_1 = $signed(dpa_4_0_aval_1) * $signed(dpa_0_6_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_6_mval_2 = $signed(dpa_4_0_aval_2) * $signed(dpa_0_6_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_6_mval_3 = $signed(dpa_4_0_aval_3) * $signed(dpa_0_6_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_4_6_dotp_T = $signed(dpa_4_6_mval) + $signed(dpa_4_6_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_4_6_dotp_T_1 = $signed(dpa_4_6_mval_2) + $signed(dpa_4_6_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_4_6_dotp = $signed(_dpa_4_6_dotp_T) + $signed(_dpa_4_6_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_4_6_sdotp_T_2 = dpa_4_6_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_4_6_sdotp_lo = $signed(_dpa_4_6_dotp_T) + $signed(_dpa_4_6_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_4_6_sdotp = {_dpa_4_6_sdotp_T_2,dpa_4_6_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_4_6 = accum_38 + dpa_4_6_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_39 = io_op_conv ? acc_4_7 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_4_7_mval = $signed(dpa_4_0_aval) * $signed(dpa_0_7_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_7_mval_1 = $signed(dpa_4_0_aval_1) * $signed(dpa_0_7_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_7_mval_2 = $signed(dpa_4_0_aval_2) * $signed(dpa_0_7_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_4_7_mval_3 = $signed(dpa_4_0_aval_3) * $signed(dpa_0_7_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_4_7_dotp_T = $signed(dpa_4_7_mval) + $signed(dpa_4_7_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_4_7_dotp_T_1 = $signed(dpa_4_7_mval_2) + $signed(dpa_4_7_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_4_7_dotp = $signed(_dpa_4_7_dotp_T) + $signed(_dpa_4_7_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_4_7_sdotp_T_2 = dpa_4_7_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_4_7_sdotp_lo = $signed(_dpa_4_7_dotp_T) + $signed(_dpa_4_7_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_4_7_sdotp = {_dpa_4_7_sdotp_T_2,dpa_4_7_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_4_7 = accum_39 + dpa_4_7_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_40 = io_op_conv ? acc_5_0 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_5_0_adatac = io_op_conv ? io_adata[191:160] : 32'h0; // @[Library.scala 32:8]
- wire dpa_5_0_as = dpa_5_0_adatac[7] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_5_0_aval_T_2 = {dpa_5_0_as,dpa_5_0_adatac[7:0]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_5_0_aval = $signed(_dpa_5_0_aval_T_2) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_5_0_mval = $signed(dpa_5_0_aval) * $signed(dpa_0_0_bval); // @[VDot.scala 44:23]
- wire dpa_5_0_as_1 = dpa_5_0_adatac[15] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_5_0_aval_T_6 = {dpa_5_0_as_1,dpa_5_0_adatac[15:8]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_5_0_aval_1 = $signed(_dpa_5_0_aval_T_6) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_5_0_mval_1 = $signed(dpa_5_0_aval_1) * $signed(dpa_0_0_bval_1); // @[VDot.scala 44:23]
- wire dpa_5_0_as_2 = dpa_5_0_adatac[23] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_5_0_aval_T_10 = {dpa_5_0_as_2,dpa_5_0_adatac[23:16]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_5_0_aval_2 = $signed(_dpa_5_0_aval_T_10) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_5_0_mval_2 = $signed(dpa_5_0_aval_2) * $signed(dpa_0_0_bval_2); // @[VDot.scala 44:23]
- wire dpa_5_0_as_3 = dpa_5_0_adatac[31] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_5_0_aval_T_14 = {dpa_5_0_as_3,dpa_5_0_adatac[31:24]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_5_0_aval_3 = $signed(_dpa_5_0_aval_T_14) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_5_0_mval_3 = $signed(dpa_5_0_aval_3) * $signed(dpa_0_0_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_5_0_dotp_T = $signed(dpa_5_0_mval) + $signed(dpa_5_0_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_5_0_dotp_T_1 = $signed(dpa_5_0_mval_2) + $signed(dpa_5_0_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_5_0_dotp = $signed(_dpa_5_0_dotp_T) + $signed(_dpa_5_0_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_5_0_sdotp_T_2 = dpa_5_0_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_5_0_sdotp_lo = $signed(_dpa_5_0_dotp_T) + $signed(_dpa_5_0_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_5_0_sdotp = {_dpa_5_0_sdotp_T_2,dpa_5_0_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_5_0 = accum_40 + dpa_5_0_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_41 = io_op_conv ? acc_5_1 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_5_1_mval = $signed(dpa_5_0_aval) * $signed(dpa_0_1_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_1_mval_1 = $signed(dpa_5_0_aval_1) * $signed(dpa_0_1_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_1_mval_2 = $signed(dpa_5_0_aval_2) * $signed(dpa_0_1_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_1_mval_3 = $signed(dpa_5_0_aval_3) * $signed(dpa_0_1_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_5_1_dotp_T = $signed(dpa_5_1_mval) + $signed(dpa_5_1_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_5_1_dotp_T_1 = $signed(dpa_5_1_mval_2) + $signed(dpa_5_1_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_5_1_dotp = $signed(_dpa_5_1_dotp_T) + $signed(_dpa_5_1_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_5_1_sdotp_T_2 = dpa_5_1_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_5_1_sdotp_lo = $signed(_dpa_5_1_dotp_T) + $signed(_dpa_5_1_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_5_1_sdotp = {_dpa_5_1_sdotp_T_2,dpa_5_1_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_5_1 = accum_41 + dpa_5_1_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_42 = io_op_conv ? acc_5_2 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_5_2_mval = $signed(dpa_5_0_aval) * $signed(dpa_0_2_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_2_mval_1 = $signed(dpa_5_0_aval_1) * $signed(dpa_0_2_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_2_mval_2 = $signed(dpa_5_0_aval_2) * $signed(dpa_0_2_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_2_mval_3 = $signed(dpa_5_0_aval_3) * $signed(dpa_0_2_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_5_2_dotp_T = $signed(dpa_5_2_mval) + $signed(dpa_5_2_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_5_2_dotp_T_1 = $signed(dpa_5_2_mval_2) + $signed(dpa_5_2_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_5_2_dotp = $signed(_dpa_5_2_dotp_T) + $signed(_dpa_5_2_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_5_2_sdotp_T_2 = dpa_5_2_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_5_2_sdotp_lo = $signed(_dpa_5_2_dotp_T) + $signed(_dpa_5_2_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_5_2_sdotp = {_dpa_5_2_sdotp_T_2,dpa_5_2_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_5_2 = accum_42 + dpa_5_2_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_43 = io_op_conv ? acc_5_3 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_5_3_mval = $signed(dpa_5_0_aval) * $signed(dpa_0_3_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_3_mval_1 = $signed(dpa_5_0_aval_1) * $signed(dpa_0_3_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_3_mval_2 = $signed(dpa_5_0_aval_2) * $signed(dpa_0_3_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_3_mval_3 = $signed(dpa_5_0_aval_3) * $signed(dpa_0_3_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_5_3_dotp_T = $signed(dpa_5_3_mval) + $signed(dpa_5_3_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_5_3_dotp_T_1 = $signed(dpa_5_3_mval_2) + $signed(dpa_5_3_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_5_3_dotp = $signed(_dpa_5_3_dotp_T) + $signed(_dpa_5_3_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_5_3_sdotp_T_2 = dpa_5_3_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_5_3_sdotp_lo = $signed(_dpa_5_3_dotp_T) + $signed(_dpa_5_3_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_5_3_sdotp = {_dpa_5_3_sdotp_T_2,dpa_5_3_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_5_3 = accum_43 + dpa_5_3_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_44 = io_op_conv ? acc_5_4 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_5_4_mval = $signed(dpa_5_0_aval) * $signed(dpa_0_4_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_4_mval_1 = $signed(dpa_5_0_aval_1) * $signed(dpa_0_4_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_4_mval_2 = $signed(dpa_5_0_aval_2) * $signed(dpa_0_4_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_4_mval_3 = $signed(dpa_5_0_aval_3) * $signed(dpa_0_4_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_5_4_dotp_T = $signed(dpa_5_4_mval) + $signed(dpa_5_4_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_5_4_dotp_T_1 = $signed(dpa_5_4_mval_2) + $signed(dpa_5_4_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_5_4_dotp = $signed(_dpa_5_4_dotp_T) + $signed(_dpa_5_4_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_5_4_sdotp_T_2 = dpa_5_4_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_5_4_sdotp_lo = $signed(_dpa_5_4_dotp_T) + $signed(_dpa_5_4_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_5_4_sdotp = {_dpa_5_4_sdotp_T_2,dpa_5_4_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_5_4 = accum_44 + dpa_5_4_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_45 = io_op_conv ? acc_5_5 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_5_5_mval = $signed(dpa_5_0_aval) * $signed(dpa_0_5_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_5_mval_1 = $signed(dpa_5_0_aval_1) * $signed(dpa_0_5_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_5_mval_2 = $signed(dpa_5_0_aval_2) * $signed(dpa_0_5_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_5_mval_3 = $signed(dpa_5_0_aval_3) * $signed(dpa_0_5_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_5_5_dotp_T = $signed(dpa_5_5_mval) + $signed(dpa_5_5_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_5_5_dotp_T_1 = $signed(dpa_5_5_mval_2) + $signed(dpa_5_5_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_5_5_dotp = $signed(_dpa_5_5_dotp_T) + $signed(_dpa_5_5_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_5_5_sdotp_T_2 = dpa_5_5_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_5_5_sdotp_lo = $signed(_dpa_5_5_dotp_T) + $signed(_dpa_5_5_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_5_5_sdotp = {_dpa_5_5_sdotp_T_2,dpa_5_5_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_5_5 = accum_45 + dpa_5_5_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_46 = io_op_conv ? acc_5_6 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_5_6_mval = $signed(dpa_5_0_aval) * $signed(dpa_0_6_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_6_mval_1 = $signed(dpa_5_0_aval_1) * $signed(dpa_0_6_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_6_mval_2 = $signed(dpa_5_0_aval_2) * $signed(dpa_0_6_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_6_mval_3 = $signed(dpa_5_0_aval_3) * $signed(dpa_0_6_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_5_6_dotp_T = $signed(dpa_5_6_mval) + $signed(dpa_5_6_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_5_6_dotp_T_1 = $signed(dpa_5_6_mval_2) + $signed(dpa_5_6_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_5_6_dotp = $signed(_dpa_5_6_dotp_T) + $signed(_dpa_5_6_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_5_6_sdotp_T_2 = dpa_5_6_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_5_6_sdotp_lo = $signed(_dpa_5_6_dotp_T) + $signed(_dpa_5_6_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_5_6_sdotp = {_dpa_5_6_sdotp_T_2,dpa_5_6_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_5_6 = accum_46 + dpa_5_6_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_47 = io_op_conv ? acc_5_7 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_5_7_mval = $signed(dpa_5_0_aval) * $signed(dpa_0_7_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_7_mval_1 = $signed(dpa_5_0_aval_1) * $signed(dpa_0_7_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_7_mval_2 = $signed(dpa_5_0_aval_2) * $signed(dpa_0_7_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_5_7_mval_3 = $signed(dpa_5_0_aval_3) * $signed(dpa_0_7_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_5_7_dotp_T = $signed(dpa_5_7_mval) + $signed(dpa_5_7_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_5_7_dotp_T_1 = $signed(dpa_5_7_mval_2) + $signed(dpa_5_7_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_5_7_dotp = $signed(_dpa_5_7_dotp_T) + $signed(_dpa_5_7_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_5_7_sdotp_T_2 = dpa_5_7_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_5_7_sdotp_lo = $signed(_dpa_5_7_dotp_T) + $signed(_dpa_5_7_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_5_7_sdotp = {_dpa_5_7_sdotp_T_2,dpa_5_7_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_5_7 = accum_47 + dpa_5_7_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_48 = io_op_conv ? acc_6_0 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_6_0_adatac = io_op_conv ? io_adata[223:192] : 32'h0; // @[Library.scala 32:8]
- wire dpa_6_0_as = dpa_6_0_adatac[7] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_6_0_aval_T_2 = {dpa_6_0_as,dpa_6_0_adatac[7:0]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_6_0_aval = $signed(_dpa_6_0_aval_T_2) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_6_0_mval = $signed(dpa_6_0_aval) * $signed(dpa_0_0_bval); // @[VDot.scala 44:23]
- wire dpa_6_0_as_1 = dpa_6_0_adatac[15] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_6_0_aval_T_6 = {dpa_6_0_as_1,dpa_6_0_adatac[15:8]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_6_0_aval_1 = $signed(_dpa_6_0_aval_T_6) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_6_0_mval_1 = $signed(dpa_6_0_aval_1) * $signed(dpa_0_0_bval_1); // @[VDot.scala 44:23]
- wire dpa_6_0_as_2 = dpa_6_0_adatac[23] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_6_0_aval_T_10 = {dpa_6_0_as_2,dpa_6_0_adatac[23:16]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_6_0_aval_2 = $signed(_dpa_6_0_aval_T_10) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_6_0_mval_2 = $signed(dpa_6_0_aval_2) * $signed(dpa_0_0_bval_2); // @[VDot.scala 44:23]
- wire dpa_6_0_as_3 = dpa_6_0_adatac[31] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_6_0_aval_T_14 = {dpa_6_0_as_3,dpa_6_0_adatac[31:24]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_6_0_aval_3 = $signed(_dpa_6_0_aval_T_14) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_6_0_mval_3 = $signed(dpa_6_0_aval_3) * $signed(dpa_0_0_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_6_0_dotp_T = $signed(dpa_6_0_mval) + $signed(dpa_6_0_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_6_0_dotp_T_1 = $signed(dpa_6_0_mval_2) + $signed(dpa_6_0_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_6_0_dotp = $signed(_dpa_6_0_dotp_T) + $signed(_dpa_6_0_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_6_0_sdotp_T_2 = dpa_6_0_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_6_0_sdotp_lo = $signed(_dpa_6_0_dotp_T) + $signed(_dpa_6_0_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_6_0_sdotp = {_dpa_6_0_sdotp_T_2,dpa_6_0_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_6_0 = accum_48 + dpa_6_0_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_49 = io_op_conv ? acc_6_1 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_6_1_mval = $signed(dpa_6_0_aval) * $signed(dpa_0_1_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_1_mval_1 = $signed(dpa_6_0_aval_1) * $signed(dpa_0_1_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_1_mval_2 = $signed(dpa_6_0_aval_2) * $signed(dpa_0_1_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_1_mval_3 = $signed(dpa_6_0_aval_3) * $signed(dpa_0_1_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_6_1_dotp_T = $signed(dpa_6_1_mval) + $signed(dpa_6_1_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_6_1_dotp_T_1 = $signed(dpa_6_1_mval_2) + $signed(dpa_6_1_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_6_1_dotp = $signed(_dpa_6_1_dotp_T) + $signed(_dpa_6_1_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_6_1_sdotp_T_2 = dpa_6_1_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_6_1_sdotp_lo = $signed(_dpa_6_1_dotp_T) + $signed(_dpa_6_1_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_6_1_sdotp = {_dpa_6_1_sdotp_T_2,dpa_6_1_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_6_1 = accum_49 + dpa_6_1_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_50 = io_op_conv ? acc_6_2 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_6_2_mval = $signed(dpa_6_0_aval) * $signed(dpa_0_2_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_2_mval_1 = $signed(dpa_6_0_aval_1) * $signed(dpa_0_2_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_2_mval_2 = $signed(dpa_6_0_aval_2) * $signed(dpa_0_2_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_2_mval_3 = $signed(dpa_6_0_aval_3) * $signed(dpa_0_2_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_6_2_dotp_T = $signed(dpa_6_2_mval) + $signed(dpa_6_2_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_6_2_dotp_T_1 = $signed(dpa_6_2_mval_2) + $signed(dpa_6_2_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_6_2_dotp = $signed(_dpa_6_2_dotp_T) + $signed(_dpa_6_2_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_6_2_sdotp_T_2 = dpa_6_2_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_6_2_sdotp_lo = $signed(_dpa_6_2_dotp_T) + $signed(_dpa_6_2_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_6_2_sdotp = {_dpa_6_2_sdotp_T_2,dpa_6_2_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_6_2 = accum_50 + dpa_6_2_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_51 = io_op_conv ? acc_6_3 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_6_3_mval = $signed(dpa_6_0_aval) * $signed(dpa_0_3_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_3_mval_1 = $signed(dpa_6_0_aval_1) * $signed(dpa_0_3_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_3_mval_2 = $signed(dpa_6_0_aval_2) * $signed(dpa_0_3_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_3_mval_3 = $signed(dpa_6_0_aval_3) * $signed(dpa_0_3_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_6_3_dotp_T = $signed(dpa_6_3_mval) + $signed(dpa_6_3_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_6_3_dotp_T_1 = $signed(dpa_6_3_mval_2) + $signed(dpa_6_3_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_6_3_dotp = $signed(_dpa_6_3_dotp_T) + $signed(_dpa_6_3_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_6_3_sdotp_T_2 = dpa_6_3_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_6_3_sdotp_lo = $signed(_dpa_6_3_dotp_T) + $signed(_dpa_6_3_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_6_3_sdotp = {_dpa_6_3_sdotp_T_2,dpa_6_3_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_6_3 = accum_51 + dpa_6_3_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_52 = io_op_conv ? acc_6_4 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_6_4_mval = $signed(dpa_6_0_aval) * $signed(dpa_0_4_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_4_mval_1 = $signed(dpa_6_0_aval_1) * $signed(dpa_0_4_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_4_mval_2 = $signed(dpa_6_0_aval_2) * $signed(dpa_0_4_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_4_mval_3 = $signed(dpa_6_0_aval_3) * $signed(dpa_0_4_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_6_4_dotp_T = $signed(dpa_6_4_mval) + $signed(dpa_6_4_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_6_4_dotp_T_1 = $signed(dpa_6_4_mval_2) + $signed(dpa_6_4_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_6_4_dotp = $signed(_dpa_6_4_dotp_T) + $signed(_dpa_6_4_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_6_4_sdotp_T_2 = dpa_6_4_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_6_4_sdotp_lo = $signed(_dpa_6_4_dotp_T) + $signed(_dpa_6_4_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_6_4_sdotp = {_dpa_6_4_sdotp_T_2,dpa_6_4_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_6_4 = accum_52 + dpa_6_4_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_53 = io_op_conv ? acc_6_5 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_6_5_mval = $signed(dpa_6_0_aval) * $signed(dpa_0_5_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_5_mval_1 = $signed(dpa_6_0_aval_1) * $signed(dpa_0_5_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_5_mval_2 = $signed(dpa_6_0_aval_2) * $signed(dpa_0_5_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_5_mval_3 = $signed(dpa_6_0_aval_3) * $signed(dpa_0_5_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_6_5_dotp_T = $signed(dpa_6_5_mval) + $signed(dpa_6_5_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_6_5_dotp_T_1 = $signed(dpa_6_5_mval_2) + $signed(dpa_6_5_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_6_5_dotp = $signed(_dpa_6_5_dotp_T) + $signed(_dpa_6_5_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_6_5_sdotp_T_2 = dpa_6_5_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_6_5_sdotp_lo = $signed(_dpa_6_5_dotp_T) + $signed(_dpa_6_5_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_6_5_sdotp = {_dpa_6_5_sdotp_T_2,dpa_6_5_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_6_5 = accum_53 + dpa_6_5_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_54 = io_op_conv ? acc_6_6 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_6_6_mval = $signed(dpa_6_0_aval) * $signed(dpa_0_6_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_6_mval_1 = $signed(dpa_6_0_aval_1) * $signed(dpa_0_6_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_6_mval_2 = $signed(dpa_6_0_aval_2) * $signed(dpa_0_6_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_6_mval_3 = $signed(dpa_6_0_aval_3) * $signed(dpa_0_6_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_6_6_dotp_T = $signed(dpa_6_6_mval) + $signed(dpa_6_6_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_6_6_dotp_T_1 = $signed(dpa_6_6_mval_2) + $signed(dpa_6_6_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_6_6_dotp = $signed(_dpa_6_6_dotp_T) + $signed(_dpa_6_6_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_6_6_sdotp_T_2 = dpa_6_6_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_6_6_sdotp_lo = $signed(_dpa_6_6_dotp_T) + $signed(_dpa_6_6_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_6_6_sdotp = {_dpa_6_6_sdotp_T_2,dpa_6_6_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_6_6 = accum_54 + dpa_6_6_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_55 = io_op_conv ? acc_6_7 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_6_7_mval = $signed(dpa_6_0_aval) * $signed(dpa_0_7_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_7_mval_1 = $signed(dpa_6_0_aval_1) * $signed(dpa_0_7_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_7_mval_2 = $signed(dpa_6_0_aval_2) * $signed(dpa_0_7_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_6_7_mval_3 = $signed(dpa_6_0_aval_3) * $signed(dpa_0_7_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_6_7_dotp_T = $signed(dpa_6_7_mval) + $signed(dpa_6_7_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_6_7_dotp_T_1 = $signed(dpa_6_7_mval_2) + $signed(dpa_6_7_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_6_7_dotp = $signed(_dpa_6_7_dotp_T) + $signed(_dpa_6_7_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_6_7_sdotp_T_2 = dpa_6_7_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_6_7_sdotp_lo = $signed(_dpa_6_7_dotp_T) + $signed(_dpa_6_7_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_6_7_sdotp = {_dpa_6_7_sdotp_T_2,dpa_6_7_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_6_7 = accum_55 + dpa_6_7_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_56 = io_op_conv ? acc_7_0 : 32'h0; // @[Library.scala 32:8]
- wire [31:0] dpa_7_0_adatac = io_op_conv ? io_adata[255:224] : 32'h0; // @[Library.scala 32:8]
- wire dpa_7_0_as = dpa_7_0_adatac[7] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_7_0_aval_T_2 = {dpa_7_0_as,dpa_7_0_adatac[7:0]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_7_0_aval = $signed(_dpa_7_0_aval_T_2) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_7_0_mval = $signed(dpa_7_0_aval) * $signed(dpa_0_0_bval); // @[VDot.scala 44:23]
- wire dpa_7_0_as_1 = dpa_7_0_adatac[15] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_7_0_aval_T_6 = {dpa_7_0_as_1,dpa_7_0_adatac[15:8]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_7_0_aval_1 = $signed(_dpa_7_0_aval_T_6) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_7_0_mval_1 = $signed(dpa_7_0_aval_1) * $signed(dpa_0_0_bval_1); // @[VDot.scala 44:23]
- wire dpa_7_0_as_2 = dpa_7_0_adatac[23] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_7_0_aval_T_10 = {dpa_7_0_as_2,dpa_7_0_adatac[23:16]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_7_0_aval_2 = $signed(_dpa_7_0_aval_T_10) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_7_0_mval_2 = $signed(dpa_7_0_aval_2) * $signed(dpa_0_0_bval_2); // @[VDot.scala 44:23]
- wire dpa_7_0_as_3 = dpa_7_0_adatac[31] & io_asign; // @[VDot.scala 40:34]
- wire [8:0] _dpa_7_0_aval_T_14 = {dpa_7_0_as_3,dpa_7_0_adatac[31:24]}; // @[VDot.scala 42:52]
- wire [9:0] dpa_7_0_aval_3 = $signed(_dpa_7_0_aval_T_14) + $signed(_dpa_0_0_aval_T_3); // @[VDot.scala 42:59]
- wire [19:0] dpa_7_0_mval_3 = $signed(dpa_7_0_aval_3) * $signed(dpa_0_0_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_7_0_dotp_T = $signed(dpa_7_0_mval) + $signed(dpa_7_0_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_7_0_dotp_T_1 = $signed(dpa_7_0_mval_2) + $signed(dpa_7_0_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_7_0_dotp = $signed(_dpa_7_0_dotp_T) + $signed(_dpa_7_0_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_7_0_sdotp_T_2 = dpa_7_0_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_7_0_sdotp_lo = $signed(_dpa_7_0_dotp_T) + $signed(_dpa_7_0_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_7_0_sdotp = {_dpa_7_0_sdotp_T_2,dpa_7_0_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_7_0 = accum_56 + dpa_7_0_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_57 = io_op_conv ? acc_7_1 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_7_1_mval = $signed(dpa_7_0_aval) * $signed(dpa_0_1_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_1_mval_1 = $signed(dpa_7_0_aval_1) * $signed(dpa_0_1_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_1_mval_2 = $signed(dpa_7_0_aval_2) * $signed(dpa_0_1_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_1_mval_3 = $signed(dpa_7_0_aval_3) * $signed(dpa_0_1_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_7_1_dotp_T = $signed(dpa_7_1_mval) + $signed(dpa_7_1_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_7_1_dotp_T_1 = $signed(dpa_7_1_mval_2) + $signed(dpa_7_1_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_7_1_dotp = $signed(_dpa_7_1_dotp_T) + $signed(_dpa_7_1_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_7_1_sdotp_T_2 = dpa_7_1_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_7_1_sdotp_lo = $signed(_dpa_7_1_dotp_T) + $signed(_dpa_7_1_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_7_1_sdotp = {_dpa_7_1_sdotp_T_2,dpa_7_1_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_7_1 = accum_57 + dpa_7_1_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_58 = io_op_conv ? acc_7_2 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_7_2_mval = $signed(dpa_7_0_aval) * $signed(dpa_0_2_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_2_mval_1 = $signed(dpa_7_0_aval_1) * $signed(dpa_0_2_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_2_mval_2 = $signed(dpa_7_0_aval_2) * $signed(dpa_0_2_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_2_mval_3 = $signed(dpa_7_0_aval_3) * $signed(dpa_0_2_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_7_2_dotp_T = $signed(dpa_7_2_mval) + $signed(dpa_7_2_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_7_2_dotp_T_1 = $signed(dpa_7_2_mval_2) + $signed(dpa_7_2_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_7_2_dotp = $signed(_dpa_7_2_dotp_T) + $signed(_dpa_7_2_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_7_2_sdotp_T_2 = dpa_7_2_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_7_2_sdotp_lo = $signed(_dpa_7_2_dotp_T) + $signed(_dpa_7_2_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_7_2_sdotp = {_dpa_7_2_sdotp_T_2,dpa_7_2_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_7_2 = accum_58 + dpa_7_2_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_59 = io_op_conv ? acc_7_3 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_7_3_mval = $signed(dpa_7_0_aval) * $signed(dpa_0_3_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_3_mval_1 = $signed(dpa_7_0_aval_1) * $signed(dpa_0_3_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_3_mval_2 = $signed(dpa_7_0_aval_2) * $signed(dpa_0_3_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_3_mval_3 = $signed(dpa_7_0_aval_3) * $signed(dpa_0_3_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_7_3_dotp_T = $signed(dpa_7_3_mval) + $signed(dpa_7_3_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_7_3_dotp_T_1 = $signed(dpa_7_3_mval_2) + $signed(dpa_7_3_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_7_3_dotp = $signed(_dpa_7_3_dotp_T) + $signed(_dpa_7_3_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_7_3_sdotp_T_2 = dpa_7_3_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_7_3_sdotp_lo = $signed(_dpa_7_3_dotp_T) + $signed(_dpa_7_3_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_7_3_sdotp = {_dpa_7_3_sdotp_T_2,dpa_7_3_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_7_3 = accum_59 + dpa_7_3_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_60 = io_op_conv ? acc_7_4 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_7_4_mval = $signed(dpa_7_0_aval) * $signed(dpa_0_4_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_4_mval_1 = $signed(dpa_7_0_aval_1) * $signed(dpa_0_4_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_4_mval_2 = $signed(dpa_7_0_aval_2) * $signed(dpa_0_4_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_4_mval_3 = $signed(dpa_7_0_aval_3) * $signed(dpa_0_4_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_7_4_dotp_T = $signed(dpa_7_4_mval) + $signed(dpa_7_4_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_7_4_dotp_T_1 = $signed(dpa_7_4_mval_2) + $signed(dpa_7_4_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_7_4_dotp = $signed(_dpa_7_4_dotp_T) + $signed(_dpa_7_4_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_7_4_sdotp_T_2 = dpa_7_4_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_7_4_sdotp_lo = $signed(_dpa_7_4_dotp_T) + $signed(_dpa_7_4_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_7_4_sdotp = {_dpa_7_4_sdotp_T_2,dpa_7_4_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_7_4 = accum_60 + dpa_7_4_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_61 = io_op_conv ? acc_7_5 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_7_5_mval = $signed(dpa_7_0_aval) * $signed(dpa_0_5_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_5_mval_1 = $signed(dpa_7_0_aval_1) * $signed(dpa_0_5_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_5_mval_2 = $signed(dpa_7_0_aval_2) * $signed(dpa_0_5_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_5_mval_3 = $signed(dpa_7_0_aval_3) * $signed(dpa_0_5_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_7_5_dotp_T = $signed(dpa_7_5_mval) + $signed(dpa_7_5_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_7_5_dotp_T_1 = $signed(dpa_7_5_mval_2) + $signed(dpa_7_5_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_7_5_dotp = $signed(_dpa_7_5_dotp_T) + $signed(_dpa_7_5_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_7_5_sdotp_T_2 = dpa_7_5_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_7_5_sdotp_lo = $signed(_dpa_7_5_dotp_T) + $signed(_dpa_7_5_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_7_5_sdotp = {_dpa_7_5_sdotp_T_2,dpa_7_5_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_7_5 = accum_61 + dpa_7_5_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_62 = io_op_conv ? acc_7_6 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_7_6_mval = $signed(dpa_7_0_aval) * $signed(dpa_0_6_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_6_mval_1 = $signed(dpa_7_0_aval_1) * $signed(dpa_0_6_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_6_mval_2 = $signed(dpa_7_0_aval_2) * $signed(dpa_0_6_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_6_mval_3 = $signed(dpa_7_0_aval_3) * $signed(dpa_0_6_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_7_6_dotp_T = $signed(dpa_7_6_mval) + $signed(dpa_7_6_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_7_6_dotp_T_1 = $signed(dpa_7_6_mval_2) + $signed(dpa_7_6_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_7_6_dotp = $signed(_dpa_7_6_dotp_T) + $signed(_dpa_7_6_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_7_6_sdotp_T_2 = dpa_7_6_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_7_6_sdotp_lo = $signed(_dpa_7_6_dotp_T) + $signed(_dpa_7_6_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_7_6_sdotp = {_dpa_7_6_sdotp_T_2,dpa_7_6_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_7_6 = accum_62 + dpa_7_6_sdotp; // @[VConvAlu.scala 78:26]
- wire [31:0] accum_63 = io_op_conv ? acc_7_7 : 32'h0; // @[Library.scala 32:8]
- wire [19:0] dpa_7_7_mval = $signed(dpa_7_0_aval) * $signed(dpa_0_7_bval); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_7_mval_1 = $signed(dpa_7_0_aval_1) * $signed(dpa_0_7_bval_1); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_7_mval_2 = $signed(dpa_7_0_aval_2) * $signed(dpa_0_7_bval_2); // @[VDot.scala 44:23]
- wire [19:0] dpa_7_7_mval_3 = $signed(dpa_7_0_aval_3) * $signed(dpa_0_7_bval_3); // @[VDot.scala 44:23]
- wire [20:0] _dpa_7_7_dotp_T = $signed(dpa_7_7_mval) + $signed(dpa_7_7_mval_1); // @[VDot.scala 52:24]
- wire [20:0] _dpa_7_7_dotp_T_1 = $signed(dpa_7_7_mval_2) + $signed(dpa_7_7_mval_3); // @[VDot.scala 52:46]
- wire [21:0] dpa_7_7_dotp = $signed(_dpa_7_7_dotp_T) + $signed(_dpa_7_7_dotp_T_1); // @[VDot.scala 52:35]
- wire [9:0] _dpa_7_7_sdotp_T_2 = dpa_7_7_dotp[21] ? 10'h3ff : 10'h0; // @[Library.scala 32:8]
- wire [21:0] dpa_7_7_sdotp_lo = $signed(_dpa_7_7_dotp_T) + $signed(_dpa_7_7_dotp_T_1); // @[Cat.scala 31:58]
- wire [31:0] dpa_7_7_sdotp = {_dpa_7_7_sdotp_T_2,dpa_7_7_sdotp_lo}; // @[Cat.scala 31:58]
- wire [31:0] dpa_7_7 = accum_63 + dpa_7_7_sdotp; // @[VConvAlu.scala 78:26]
- wire [255:0] _pload_T = io_op_tran ? io_adata : 256'h0; // @[Library.scala 32:8]
- wire [255:0] _pload_T_1 = io_op_init ? io_bdata : 256'h0; // @[Library.scala 32:8]
- wire [255:0] pload = _pload_T | _pload_T_1; // @[VConvAlu.scala 86:43]
- wire aclr = io_op_clear | reset; // @[VConvAlu.scala 95:30]
- wire load = (io_op_init | io_op_tran) & 3'h0 == io_index; // @[VConvAlu.scala 97:45]
- wire load_1 = (io_op_init | io_op_tran) & 3'h2 == io_index; // @[VConvAlu.scala 97:45]
- wire load_2 = (io_op_init | io_op_tran) & 3'h1 == io_index; // @[VConvAlu.scala 97:45]
- wire load_3 = (io_op_init | io_op_tran) & 3'h3 == io_index; // @[VConvAlu.scala 97:45]
- wire load_32 = (io_op_init | io_op_tran) & 3'h4 == io_index; // @[VConvAlu.scala 97:45]
- wire load_33 = (io_op_init | io_op_tran) & 3'h6 == io_index; // @[VConvAlu.scala 97:45]
- wire load_34 = (io_op_init | io_op_tran) & 3'h5 == io_index; // @[VConvAlu.scala 97:45]
- wire load_35 = (io_op_init | io_op_tran) & 3'h7 == io_index; // @[VConvAlu.scala 97:45]
- wire [127:0] io_out_0_lo = {acc_1_4,acc_1_0,acc_0_4,acc_0_0}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_0_hi = {acc_3_4,acc_3_0,acc_2_4,acc_2_0}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_1_lo = {acc_1_6,acc_1_2,acc_0_6,acc_0_2}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_1_hi = {acc_3_6,acc_3_2,acc_2_6,acc_2_2}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_2_lo = {acc_1_5,acc_1_1,acc_0_5,acc_0_1}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_2_hi = {acc_3_5,acc_3_1,acc_2_5,acc_2_1}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_3_lo = {acc_1_7,acc_1_3,acc_0_7,acc_0_3}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_3_hi = {acc_3_7,acc_3_3,acc_2_7,acc_2_3}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_4_lo = {acc_5_4,acc_5_0,acc_4_4,acc_4_0}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_4_hi = {acc_7_4,acc_7_0,acc_6_4,acc_6_0}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_5_lo = {acc_5_6,acc_5_2,acc_4_6,acc_4_2}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_5_hi = {acc_7_6,acc_7_2,acc_6_6,acc_6_2}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_6_lo = {acc_5_5,acc_5_1,acc_4_5,acc_4_1}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_6_hi = {acc_7_5,acc_7_1,acc_6_5,acc_6_1}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_7_lo = {acc_5_7,acc_5_3,acc_4_7,acc_4_3}; // @[VConvAlu.scala 118:25]
- wire [127:0] io_out_7_hi = {acc_7_7,acc_7_3,acc_6_7,acc_6_3}; // @[VConvAlu.scala 118:25]
- assign io_out_0 = {io_out_0_hi,io_out_0_lo}; // @[VConvAlu.scala 118:25]
- assign io_out_1 = {io_out_1_hi,io_out_1_lo}; // @[VConvAlu.scala 118:25]
- assign io_out_2 = {io_out_2_hi,io_out_2_lo}; // @[VConvAlu.scala 118:25]
- assign io_out_3 = {io_out_3_hi,io_out_3_lo}; // @[VConvAlu.scala 118:25]
- assign io_out_4 = {io_out_4_hi,io_out_4_lo}; // @[VConvAlu.scala 118:25]
- assign io_out_5 = {io_out_5_hi,io_out_5_lo}; // @[VConvAlu.scala 118:25]
- assign io_out_6 = {io_out_6_hi,io_out_6_lo}; // @[VConvAlu.scala 118:25]
- assign io_out_7 = {io_out_7_hi,io_out_7_lo}; // @[VConvAlu.scala 118:25]
- always @(posedge clock) begin
- if (aclr | io_op_conv | load) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_0_0 <= dpa_0_0;
- end else begin
- acc_0_0 <= pload[31:0];
- end
- end
- if (aclr | io_op_conv | load_1) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_0_1 <= dpa_0_1;
- end else begin
- acc_0_1 <= pload[31:0];
- end
- end
- if (aclr | io_op_conv | load_2) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_0_2 <= dpa_0_2;
- end else begin
- acc_0_2 <= pload[31:0];
- end
- end
- if (aclr | io_op_conv | load_3) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_0_3 <= dpa_0_3;
- end else begin
- acc_0_3 <= pload[31:0];
- end
- end
- if (aclr | io_op_conv | load) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_0_4 <= dpa_0_4;
- end else begin
- acc_0_4 <= pload[63:32];
- end
- end
- if (aclr | io_op_conv | load_1) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_0_5 <= dpa_0_5;
- end else begin
- acc_0_5 <= pload[63:32];
- end
- end
- if (aclr | io_op_conv | load_2) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_0_6 <= dpa_0_6;
- end else begin
- acc_0_6 <= pload[63:32];
- end
- end
- if (aclr | io_op_conv | load_3) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_0_7 <= dpa_0_7;
- end else begin
- acc_0_7 <= pload[63:32];
- end
- end
- if (aclr | io_op_conv | load) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_1_0 <= dpa_1_0;
- end else begin
- acc_1_0 <= pload[95:64];
- end
- end
- if (aclr | io_op_conv | load_1) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_1_1 <= dpa_1_1;
- end else begin
- acc_1_1 <= pload[95:64];
- end
- end
- if (aclr | io_op_conv | load_2) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_1_2 <= dpa_1_2;
- end else begin
- acc_1_2 <= pload[95:64];
- end
- end
- if (aclr | io_op_conv | load_3) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_1_3 <= dpa_1_3;
- end else begin
- acc_1_3 <= pload[95:64];
- end
- end
- if (aclr | io_op_conv | load) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_1_4 <= dpa_1_4;
- end else begin
- acc_1_4 <= pload[127:96];
- end
- end
- if (aclr | io_op_conv | load_1) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_1_5 <= dpa_1_5;
- end else begin
- acc_1_5 <= pload[127:96];
- end
- end
- if (aclr | io_op_conv | load_2) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_1_6 <= dpa_1_6;
- end else begin
- acc_1_6 <= pload[127:96];
- end
- end
- if (aclr | io_op_conv | load_3) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_1_7 <= dpa_1_7;
- end else begin
- acc_1_7 <= pload[127:96];
- end
- end
- if (aclr | io_op_conv | load) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_2_0 <= dpa_2_0;
- end else begin
- acc_2_0 <= pload[159:128];
- end
- end
- if (aclr | io_op_conv | load_1) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_2_1 <= dpa_2_1;
- end else begin
- acc_2_1 <= pload[159:128];
- end
- end
- if (aclr | io_op_conv | load_2) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_2_2 <= dpa_2_2;
- end else begin
- acc_2_2 <= pload[159:128];
- end
- end
- if (aclr | io_op_conv | load_3) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_2_3 <= dpa_2_3;
- end else begin
- acc_2_3 <= pload[159:128];
- end
- end
- if (aclr | io_op_conv | load) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_2_4 <= dpa_2_4;
- end else begin
- acc_2_4 <= pload[191:160];
- end
- end
- if (aclr | io_op_conv | load_1) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_2_5 <= dpa_2_5;
- end else begin
- acc_2_5 <= pload[191:160];
- end
- end
- if (aclr | io_op_conv | load_2) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_2_6 <= dpa_2_6;
- end else begin
- acc_2_6 <= pload[191:160];
- end
- end
- if (aclr | io_op_conv | load_3) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_2_7 <= dpa_2_7;
- end else begin
- acc_2_7 <= pload[191:160];
- end
- end
- if (aclr | io_op_conv | load) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_3_0 <= dpa_3_0;
- end else begin
- acc_3_0 <= pload[223:192];
- end
- end
- if (aclr | io_op_conv | load_1) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_3_1 <= dpa_3_1;
- end else begin
- acc_3_1 <= pload[223:192];
- end
- end
- if (aclr | io_op_conv | load_2) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_3_2 <= dpa_3_2;
- end else begin
- acc_3_2 <= pload[223:192];
- end
- end
- if (aclr | io_op_conv | load_3) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_3_3 <= dpa_3_3;
- end else begin
- acc_3_3 <= pload[223:192];
- end
- end
- if (aclr | io_op_conv | load) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_3_4 <= dpa_3_4;
- end else begin
- acc_3_4 <= pload[255:224];
- end
- end
- if (aclr | io_op_conv | load_1) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_3_5 <= dpa_3_5;
- end else begin
- acc_3_5 <= pload[255:224];
- end
- end
- if (aclr | io_op_conv | load_2) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_3_6 <= dpa_3_6;
- end else begin
- acc_3_6 <= pload[255:224];
- end
- end
- if (aclr | io_op_conv | load_3) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_3_7 <= dpa_3_7;
- end else begin
- acc_3_7 <= pload[255:224];
- end
- end
- if (aclr | io_op_conv | load_32) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_4_0 <= dpa_4_0;
- end else begin
- acc_4_0 <= pload[31:0];
- end
- end
- if (aclr | io_op_conv | load_33) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_4_1 <= dpa_4_1;
- end else begin
- acc_4_1 <= pload[31:0];
- end
- end
- if (aclr | io_op_conv | load_34) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_4_2 <= dpa_4_2;
- end else begin
- acc_4_2 <= pload[31:0];
- end
- end
- if (aclr | io_op_conv | load_35) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_4_3 <= dpa_4_3;
- end else begin
- acc_4_3 <= pload[31:0];
- end
- end
- if (aclr | io_op_conv | load_32) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_4_4 <= dpa_4_4;
- end else begin
- acc_4_4 <= pload[63:32];
- end
- end
- if (aclr | io_op_conv | load_33) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_4_5 <= dpa_4_5;
- end else begin
- acc_4_5 <= pload[63:32];
- end
- end
- if (aclr | io_op_conv | load_34) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_4_6 <= dpa_4_6;
- end else begin
- acc_4_6 <= pload[63:32];
- end
- end
- if (aclr | io_op_conv | load_35) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_4_7 <= dpa_4_7;
- end else begin
- acc_4_7 <= pload[63:32];
- end
- end
- if (aclr | io_op_conv | load_32) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_5_0 <= dpa_5_0;
- end else begin
- acc_5_0 <= pload[95:64];
- end
- end
- if (aclr | io_op_conv | load_33) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_5_1 <= dpa_5_1;
- end else begin
- acc_5_1 <= pload[95:64];
- end
- end
- if (aclr | io_op_conv | load_34) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_5_2 <= dpa_5_2;
- end else begin
- acc_5_2 <= pload[95:64];
- end
- end
- if (aclr | io_op_conv | load_35) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_5_3 <= dpa_5_3;
- end else begin
- acc_5_3 <= pload[95:64];
- end
- end
- if (aclr | io_op_conv | load_32) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_5_4 <= dpa_5_4;
- end else begin
- acc_5_4 <= pload[127:96];
- end
- end
- if (aclr | io_op_conv | load_33) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_5_5 <= dpa_5_5;
- end else begin
- acc_5_5 <= pload[127:96];
- end
- end
- if (aclr | io_op_conv | load_34) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_5_6 <= dpa_5_6;
- end else begin
- acc_5_6 <= pload[127:96];
- end
- end
- if (aclr | io_op_conv | load_35) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_5_7 <= dpa_5_7;
- end else begin
- acc_5_7 <= pload[127:96];
- end
- end
- if (aclr | io_op_conv | load_32) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_6_0 <= dpa_6_0;
- end else begin
- acc_6_0 <= pload[159:128];
- end
- end
- if (aclr | io_op_conv | load_33) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_6_1 <= dpa_6_1;
- end else begin
- acc_6_1 <= pload[159:128];
- end
- end
- if (aclr | io_op_conv | load_34) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_6_2 <= dpa_6_2;
- end else begin
- acc_6_2 <= pload[159:128];
- end
- end
- if (aclr | io_op_conv | load_35) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_6_3 <= dpa_6_3;
- end else begin
- acc_6_3 <= pload[159:128];
- end
- end
- if (aclr | io_op_conv | load_32) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_6_4 <= dpa_6_4;
- end else begin
- acc_6_4 <= pload[191:160];
- end
- end
- if (aclr | io_op_conv | load_33) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_6_5 <= dpa_6_5;
- end else begin
- acc_6_5 <= pload[191:160];
- end
- end
- if (aclr | io_op_conv | load_34) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_6_6 <= dpa_6_6;
- end else begin
- acc_6_6 <= pload[191:160];
- end
- end
- if (aclr | io_op_conv | load_35) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_6_7 <= dpa_6_7;
- end else begin
- acc_6_7 <= pload[191:160];
- end
- end
- if (aclr | io_op_conv | load_32) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_7_0 <= dpa_7_0;
- end else begin
- acc_7_0 <= pload[223:192];
- end
- end
- if (aclr | io_op_conv | load_33) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_7_1 <= dpa_7_1;
- end else begin
- acc_7_1 <= pload[223:192];
- end
- end
- if (aclr | io_op_conv | load_34) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_7_2 <= dpa_7_2;
- end else begin
- acc_7_2 <= pload[223:192];
- end
- end
- if (aclr | io_op_conv | load_35) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_7_3 <= dpa_7_3;
- end else begin
- acc_7_3 <= pload[223:192];
- end
- end
- if (aclr | io_op_conv | load_32) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_7_4 <= dpa_7_4;
- end else begin
- acc_7_4 <= pload[255:224];
- end
- end
- if (aclr | io_op_conv | load_33) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_7_5 <= dpa_7_5;
- end else begin
- acc_7_5 <= pload[255:224];
- end
- end
- if (aclr | io_op_conv | load_34) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_7_6 <= dpa_7_6;
- end else begin
- acc_7_6 <= pload[255:224];
- end
- end
- if (aclr | io_op_conv | load_35) begin // @[VConvAlu.scala 99:35]
- if (io_op_conv) begin // @[VConvAlu.scala 100:25]
- acc_7_7 <= dpa_7_7;
- end else begin
- acc_7_7 <= pload[255:224];
- end
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_6[1:0] <= 2'h1)) begin
- $fatal; // @[VConvAlu.scala 57:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_6[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VConvAlu.scala:57 assert(PopCount(Cat(io.op.conv, io.op.tran, io.op.clear)) <= 1.U)\n"
- ); // @[VConvAlu.scala 57:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- acc_0_0 = _RAND_0[31:0];
- _RAND_1 = {1{`RANDOM}};
- acc_0_1 = _RAND_1[31:0];
- _RAND_2 = {1{`RANDOM}};
- acc_0_2 = _RAND_2[31:0];
- _RAND_3 = {1{`RANDOM}};
- acc_0_3 = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- acc_0_4 = _RAND_4[31:0];
- _RAND_5 = {1{`RANDOM}};
- acc_0_5 = _RAND_5[31:0];
- _RAND_6 = {1{`RANDOM}};
- acc_0_6 = _RAND_6[31:0];
- _RAND_7 = {1{`RANDOM}};
- acc_0_7 = _RAND_7[31:0];
- _RAND_8 = {1{`RANDOM}};
- acc_1_0 = _RAND_8[31:0];
- _RAND_9 = {1{`RANDOM}};
- acc_1_1 = _RAND_9[31:0];
- _RAND_10 = {1{`RANDOM}};
- acc_1_2 = _RAND_10[31:0];
- _RAND_11 = {1{`RANDOM}};
- acc_1_3 = _RAND_11[31:0];
- _RAND_12 = {1{`RANDOM}};
- acc_1_4 = _RAND_12[31:0];
- _RAND_13 = {1{`RANDOM}};
- acc_1_5 = _RAND_13[31:0];
- _RAND_14 = {1{`RANDOM}};
- acc_1_6 = _RAND_14[31:0];
- _RAND_15 = {1{`RANDOM}};
- acc_1_7 = _RAND_15[31:0];
- _RAND_16 = {1{`RANDOM}};
- acc_2_0 = _RAND_16[31:0];
- _RAND_17 = {1{`RANDOM}};
- acc_2_1 = _RAND_17[31:0];
- _RAND_18 = {1{`RANDOM}};
- acc_2_2 = _RAND_18[31:0];
- _RAND_19 = {1{`RANDOM}};
- acc_2_3 = _RAND_19[31:0];
- _RAND_20 = {1{`RANDOM}};
- acc_2_4 = _RAND_20[31:0];
- _RAND_21 = {1{`RANDOM}};
- acc_2_5 = _RAND_21[31:0];
- _RAND_22 = {1{`RANDOM}};
- acc_2_6 = _RAND_22[31:0];
- _RAND_23 = {1{`RANDOM}};
- acc_2_7 = _RAND_23[31:0];
- _RAND_24 = {1{`RANDOM}};
- acc_3_0 = _RAND_24[31:0];
- _RAND_25 = {1{`RANDOM}};
- acc_3_1 = _RAND_25[31:0];
- _RAND_26 = {1{`RANDOM}};
- acc_3_2 = _RAND_26[31:0];
- _RAND_27 = {1{`RANDOM}};
- acc_3_3 = _RAND_27[31:0];
- _RAND_28 = {1{`RANDOM}};
- acc_3_4 = _RAND_28[31:0];
- _RAND_29 = {1{`RANDOM}};
- acc_3_5 = _RAND_29[31:0];
- _RAND_30 = {1{`RANDOM}};
- acc_3_6 = _RAND_30[31:0];
- _RAND_31 = {1{`RANDOM}};
- acc_3_7 = _RAND_31[31:0];
- _RAND_32 = {1{`RANDOM}};
- acc_4_0 = _RAND_32[31:0];
- _RAND_33 = {1{`RANDOM}};
- acc_4_1 = _RAND_33[31:0];
- _RAND_34 = {1{`RANDOM}};
- acc_4_2 = _RAND_34[31:0];
- _RAND_35 = {1{`RANDOM}};
- acc_4_3 = _RAND_35[31:0];
- _RAND_36 = {1{`RANDOM}};
- acc_4_4 = _RAND_36[31:0];
- _RAND_37 = {1{`RANDOM}};
- acc_4_5 = _RAND_37[31:0];
- _RAND_38 = {1{`RANDOM}};
- acc_4_6 = _RAND_38[31:0];
- _RAND_39 = {1{`RANDOM}};
- acc_4_7 = _RAND_39[31:0];
- _RAND_40 = {1{`RANDOM}};
- acc_5_0 = _RAND_40[31:0];
- _RAND_41 = {1{`RANDOM}};
- acc_5_1 = _RAND_41[31:0];
- _RAND_42 = {1{`RANDOM}};
- acc_5_2 = _RAND_42[31:0];
- _RAND_43 = {1{`RANDOM}};
- acc_5_3 = _RAND_43[31:0];
- _RAND_44 = {1{`RANDOM}};
- acc_5_4 = _RAND_44[31:0];
- _RAND_45 = {1{`RANDOM}};
- acc_5_5 = _RAND_45[31:0];
- _RAND_46 = {1{`RANDOM}};
- acc_5_6 = _RAND_46[31:0];
- _RAND_47 = {1{`RANDOM}};
- acc_5_7 = _RAND_47[31:0];
- _RAND_48 = {1{`RANDOM}};
- acc_6_0 = _RAND_48[31:0];
- _RAND_49 = {1{`RANDOM}};
- acc_6_1 = _RAND_49[31:0];
- _RAND_50 = {1{`RANDOM}};
- acc_6_2 = _RAND_50[31:0];
- _RAND_51 = {1{`RANDOM}};
- acc_6_3 = _RAND_51[31:0];
- _RAND_52 = {1{`RANDOM}};
- acc_6_4 = _RAND_52[31:0];
- _RAND_53 = {1{`RANDOM}};
- acc_6_5 = _RAND_53[31:0];
- _RAND_54 = {1{`RANDOM}};
- acc_6_6 = _RAND_54[31:0];
- _RAND_55 = {1{`RANDOM}};
- acc_6_7 = _RAND_55[31:0];
- _RAND_56 = {1{`RANDOM}};
- acc_7_0 = _RAND_56[31:0];
- _RAND_57 = {1{`RANDOM}};
- acc_7_1 = _RAND_57[31:0];
- _RAND_58 = {1{`RANDOM}};
- acc_7_2 = _RAND_58[31:0];
- _RAND_59 = {1{`RANDOM}};
- acc_7_3 = _RAND_59[31:0];
- _RAND_60 = {1{`RANDOM}};
- acc_7_4 = _RAND_60[31:0];
- _RAND_61 = {1{`RANDOM}};
- acc_7_5 = _RAND_61[31:0];
- _RAND_62 = {1{`RANDOM}};
- acc_7_6 = _RAND_62[31:0];
- _RAND_63 = {1{`RANDOM}};
- acc_7_7 = _RAND_63[31:0];
-`endif // RANDOMIZE_REG_INIT
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VRegfile(
- input clock,
- input reset,
- input io_read_0_valid,
- input [5:0] io_read_0_addr,
- output [255:0] io_read_0_data,
- input io_read_1_valid,
- input [5:0] io_read_1_addr,
- output [255:0] io_read_1_data,
- input io_read_2_valid,
- input [5:0] io_read_2_addr,
- output [255:0] io_read_2_data,
- input io_read_3_valid,
- input [5:0] io_read_3_addr,
- output [255:0] io_read_3_data,
- input io_read_4_valid,
- input [5:0] io_read_4_addr,
- output [255:0] io_read_4_data,
- input io_read_5_valid,
- input [5:0] io_read_5_addr,
- output [255:0] io_read_5_data,
- input io_read_6_valid,
- input [5:0] io_read_6_addr,
- output [255:0] io_read_6_data,
- input io_scalar_0_valid,
- input [31:0] io_scalar_0_data,
- input io_scalar_1_valid,
- input [31:0] io_scalar_1_data,
- input io_write_0_valid,
- input [5:0] io_write_0_addr,
- input [255:0] io_write_0_data,
- input io_write_1_valid,
- input [5:0] io_write_1_addr,
- input [255:0] io_write_1_data,
- input io_write_2_valid,
- input [5:0] io_write_2_addr,
- input [255:0] io_write_2_data,
- input io_write_3_valid,
- input [5:0] io_write_3_addr,
- input [255:0] io_write_3_data,
- input io_write_4_valid,
- input [5:0] io_write_4_addr,
- input [255:0] io_write_4_data,
- input io_write_5_valid,
- input [5:0] io_write_5_addr,
- input [255:0] io_write_5_data,
- input io_whint_0_valid,
- input [5:0] io_whint_0_addr,
- input io_whint_1_valid,
- input [5:0] io_whint_1_addr,
- input io_whint_2_valid,
- input [5:0] io_whint_2_addr,
- input io_whint_3_valid,
- input [5:0] io_whint_3_addr,
- input io_conv_valid,
- input io_conv_ready,
- input io_conv_op_conv,
- input io_conv_op_init,
- input io_conv_op_tran,
- input io_conv_op_wclr,
- input [5:0] io_conv_addr1,
- input [5:0] io_conv_addr2,
- input [1:0] io_conv_mode,
- input [2:0] io_conv_index,
- input [8:0] io_conv_abias,
- input [8:0] io_conv_bbias,
- input io_conv_asign,
- input io_conv_bsign,
- output [255:0] io_transpose_data,
- input io_vrfsb_set_valid,
- input [127:0] io_vrfsb_set_bits,
- output [127:0] io_vrfsb_data
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [63:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [255:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [255:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [255:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [255:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [255:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [255:0] _RAND_13;
- reg [255:0] _RAND_14;
- reg [255:0] _RAND_15;
- reg [255:0] _RAND_16;
- reg [255:0] _RAND_17;
- reg [255:0] _RAND_18;
- reg [255:0] _RAND_19;
- reg [255:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [255:0] _RAND_30;
- reg [255:0] _RAND_31;
- reg [127:0] _RAND_32;
-`endif // RANDOMIZE_REG_INIT
- wire vreg_0_clock; // @[VRegfile.scala 135:11]
- wire vreg_0_reset; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_read_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_read_0_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_read_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_read_1_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_read_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_read_2_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_read_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_read_3_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_read_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_read_4_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_read_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_read_5_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_read_6_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_read_6_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_transpose_addr; // @[VRegfile.scala 135:11]
- wire [255:0] vreg_0_io_transpose_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_internal_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_internal_data; // @[VRegfile.scala 135:11]
- wire vreg_0_io_write_0_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_write_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_write_0_data; // @[VRegfile.scala 135:11]
- wire vreg_0_io_write_1_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_write_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_write_1_data; // @[VRegfile.scala 135:11]
- wire vreg_0_io_write_2_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_write_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_write_2_data; // @[VRegfile.scala 135:11]
- wire vreg_0_io_write_3_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_write_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_write_3_data; // @[VRegfile.scala 135:11]
- wire vreg_0_io_write_4_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_write_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_write_4_data; // @[VRegfile.scala 135:11]
- wire vreg_0_io_write_5_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_0_io_write_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_write_5_data; // @[VRegfile.scala 135:11]
- wire vreg_0_io_conv_valid; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_conv_data_0; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_conv_data_1; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_conv_data_2; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_conv_data_3; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_conv_data_4; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_conv_data_5; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_conv_data_6; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_0_io_conv_data_7; // @[VRegfile.scala 135:11]
- wire vreg_1_clock; // @[VRegfile.scala 135:11]
- wire vreg_1_reset; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_read_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_read_0_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_read_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_read_1_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_read_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_read_2_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_read_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_read_3_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_read_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_read_4_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_read_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_read_5_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_read_6_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_read_6_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_transpose_addr; // @[VRegfile.scala 135:11]
- wire [255:0] vreg_1_io_transpose_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_internal_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_internal_data; // @[VRegfile.scala 135:11]
- wire vreg_1_io_write_0_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_write_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_write_0_data; // @[VRegfile.scala 135:11]
- wire vreg_1_io_write_1_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_write_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_write_1_data; // @[VRegfile.scala 135:11]
- wire vreg_1_io_write_2_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_write_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_write_2_data; // @[VRegfile.scala 135:11]
- wire vreg_1_io_write_3_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_write_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_write_3_data; // @[VRegfile.scala 135:11]
- wire vreg_1_io_write_4_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_write_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_write_4_data; // @[VRegfile.scala 135:11]
- wire vreg_1_io_write_5_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_1_io_write_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_write_5_data; // @[VRegfile.scala 135:11]
- wire vreg_1_io_conv_valid; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_conv_data_0; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_conv_data_1; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_conv_data_2; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_conv_data_3; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_conv_data_4; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_conv_data_5; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_conv_data_6; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_1_io_conv_data_7; // @[VRegfile.scala 135:11]
- wire vreg_2_clock; // @[VRegfile.scala 135:11]
- wire vreg_2_reset; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_read_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_read_0_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_read_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_read_1_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_read_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_read_2_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_read_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_read_3_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_read_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_read_4_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_read_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_read_5_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_read_6_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_read_6_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_transpose_addr; // @[VRegfile.scala 135:11]
- wire [255:0] vreg_2_io_transpose_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_internal_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_internal_data; // @[VRegfile.scala 135:11]
- wire vreg_2_io_write_0_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_write_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_write_0_data; // @[VRegfile.scala 135:11]
- wire vreg_2_io_write_1_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_write_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_write_1_data; // @[VRegfile.scala 135:11]
- wire vreg_2_io_write_2_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_write_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_write_2_data; // @[VRegfile.scala 135:11]
- wire vreg_2_io_write_3_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_write_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_write_3_data; // @[VRegfile.scala 135:11]
- wire vreg_2_io_write_4_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_write_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_write_4_data; // @[VRegfile.scala 135:11]
- wire vreg_2_io_write_5_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_2_io_write_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_write_5_data; // @[VRegfile.scala 135:11]
- wire vreg_2_io_conv_valid; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_conv_data_0; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_conv_data_1; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_conv_data_2; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_conv_data_3; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_conv_data_4; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_conv_data_5; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_conv_data_6; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_2_io_conv_data_7; // @[VRegfile.scala 135:11]
- wire vreg_3_clock; // @[VRegfile.scala 135:11]
- wire vreg_3_reset; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_read_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_read_0_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_read_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_read_1_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_read_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_read_2_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_read_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_read_3_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_read_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_read_4_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_read_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_read_5_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_read_6_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_read_6_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_transpose_addr; // @[VRegfile.scala 135:11]
- wire [255:0] vreg_3_io_transpose_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_internal_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_internal_data; // @[VRegfile.scala 135:11]
- wire vreg_3_io_write_0_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_write_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_write_0_data; // @[VRegfile.scala 135:11]
- wire vreg_3_io_write_1_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_write_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_write_1_data; // @[VRegfile.scala 135:11]
- wire vreg_3_io_write_2_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_write_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_write_2_data; // @[VRegfile.scala 135:11]
- wire vreg_3_io_write_3_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_write_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_write_3_data; // @[VRegfile.scala 135:11]
- wire vreg_3_io_write_4_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_write_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_write_4_data; // @[VRegfile.scala 135:11]
- wire vreg_3_io_write_5_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_3_io_write_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_write_5_data; // @[VRegfile.scala 135:11]
- wire vreg_3_io_conv_valid; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_conv_data_0; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_conv_data_1; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_conv_data_2; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_conv_data_3; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_conv_data_4; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_conv_data_5; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_conv_data_6; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_3_io_conv_data_7; // @[VRegfile.scala 135:11]
- wire vreg_4_clock; // @[VRegfile.scala 135:11]
- wire vreg_4_reset; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_read_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_read_0_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_read_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_read_1_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_read_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_read_2_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_read_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_read_3_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_read_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_read_4_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_read_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_read_5_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_read_6_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_read_6_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_transpose_addr; // @[VRegfile.scala 135:11]
- wire [255:0] vreg_4_io_transpose_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_internal_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_internal_data; // @[VRegfile.scala 135:11]
- wire vreg_4_io_write_0_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_write_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_write_0_data; // @[VRegfile.scala 135:11]
- wire vreg_4_io_write_1_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_write_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_write_1_data; // @[VRegfile.scala 135:11]
- wire vreg_4_io_write_2_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_write_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_write_2_data; // @[VRegfile.scala 135:11]
- wire vreg_4_io_write_3_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_write_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_write_3_data; // @[VRegfile.scala 135:11]
- wire vreg_4_io_write_4_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_write_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_write_4_data; // @[VRegfile.scala 135:11]
- wire vreg_4_io_write_5_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_4_io_write_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_write_5_data; // @[VRegfile.scala 135:11]
- wire vreg_4_io_conv_valid; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_conv_data_0; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_conv_data_1; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_conv_data_2; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_conv_data_3; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_conv_data_4; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_conv_data_5; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_conv_data_6; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_4_io_conv_data_7; // @[VRegfile.scala 135:11]
- wire vreg_5_clock; // @[VRegfile.scala 135:11]
- wire vreg_5_reset; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_read_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_read_0_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_read_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_read_1_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_read_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_read_2_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_read_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_read_3_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_read_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_read_4_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_read_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_read_5_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_read_6_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_read_6_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_transpose_addr; // @[VRegfile.scala 135:11]
- wire [255:0] vreg_5_io_transpose_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_internal_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_internal_data; // @[VRegfile.scala 135:11]
- wire vreg_5_io_write_0_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_write_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_write_0_data; // @[VRegfile.scala 135:11]
- wire vreg_5_io_write_1_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_write_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_write_1_data; // @[VRegfile.scala 135:11]
- wire vreg_5_io_write_2_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_write_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_write_2_data; // @[VRegfile.scala 135:11]
- wire vreg_5_io_write_3_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_write_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_write_3_data; // @[VRegfile.scala 135:11]
- wire vreg_5_io_write_4_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_write_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_write_4_data; // @[VRegfile.scala 135:11]
- wire vreg_5_io_write_5_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_5_io_write_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_write_5_data; // @[VRegfile.scala 135:11]
- wire vreg_5_io_conv_valid; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_conv_data_0; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_conv_data_1; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_conv_data_2; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_conv_data_3; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_conv_data_4; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_conv_data_5; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_conv_data_6; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_5_io_conv_data_7; // @[VRegfile.scala 135:11]
- wire vreg_6_clock; // @[VRegfile.scala 135:11]
- wire vreg_6_reset; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_read_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_read_0_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_read_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_read_1_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_read_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_read_2_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_read_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_read_3_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_read_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_read_4_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_read_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_read_5_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_read_6_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_read_6_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_transpose_addr; // @[VRegfile.scala 135:11]
- wire [255:0] vreg_6_io_transpose_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_internal_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_internal_data; // @[VRegfile.scala 135:11]
- wire vreg_6_io_write_0_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_write_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_write_0_data; // @[VRegfile.scala 135:11]
- wire vreg_6_io_write_1_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_write_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_write_1_data; // @[VRegfile.scala 135:11]
- wire vreg_6_io_write_2_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_write_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_write_2_data; // @[VRegfile.scala 135:11]
- wire vreg_6_io_write_3_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_write_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_write_3_data; // @[VRegfile.scala 135:11]
- wire vreg_6_io_write_4_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_write_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_write_4_data; // @[VRegfile.scala 135:11]
- wire vreg_6_io_write_5_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_6_io_write_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_write_5_data; // @[VRegfile.scala 135:11]
- wire vreg_6_io_conv_valid; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_conv_data_0; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_conv_data_1; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_conv_data_2; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_conv_data_3; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_conv_data_4; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_conv_data_5; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_conv_data_6; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_6_io_conv_data_7; // @[VRegfile.scala 135:11]
- wire vreg_7_clock; // @[VRegfile.scala 135:11]
- wire vreg_7_reset; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_read_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_read_0_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_read_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_read_1_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_read_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_read_2_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_read_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_read_3_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_read_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_read_4_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_read_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_read_5_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_read_6_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_read_6_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_transpose_addr; // @[VRegfile.scala 135:11]
- wire [255:0] vreg_7_io_transpose_data; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_internal_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_internal_data; // @[VRegfile.scala 135:11]
- wire vreg_7_io_write_0_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_write_0_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_write_0_data; // @[VRegfile.scala 135:11]
- wire vreg_7_io_write_1_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_write_1_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_write_1_data; // @[VRegfile.scala 135:11]
- wire vreg_7_io_write_2_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_write_2_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_write_2_data; // @[VRegfile.scala 135:11]
- wire vreg_7_io_write_3_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_write_3_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_write_3_data; // @[VRegfile.scala 135:11]
- wire vreg_7_io_write_4_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_write_4_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_write_4_data; // @[VRegfile.scala 135:11]
- wire vreg_7_io_write_5_valid; // @[VRegfile.scala 135:11]
- wire [5:0] vreg_7_io_write_5_addr; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_write_5_data; // @[VRegfile.scala 135:11]
- wire vreg_7_io_conv_valid; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_conv_data_0; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_conv_data_1; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_conv_data_2; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_conv_data_3; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_conv_data_4; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_conv_data_5; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_conv_data_6; // @[VRegfile.scala 135:11]
- wire [31:0] vreg_7_io_conv_data_7; // @[VRegfile.scala 135:11]
- wire vconv_clock; // @[VConvAlu.scala 24:18]
- wire vconv_reset; // @[VConvAlu.scala 24:18]
- wire vconv_io_op_conv; // @[VConvAlu.scala 24:18]
- wire vconv_io_op_init; // @[VConvAlu.scala 24:18]
- wire vconv_io_op_tran; // @[VConvAlu.scala 24:18]
- wire vconv_io_op_clear; // @[VConvAlu.scala 24:18]
- wire [2:0] vconv_io_index; // @[VConvAlu.scala 24:18]
- wire [255:0] vconv_io_adata; // @[VConvAlu.scala 24:18]
- wire [255:0] vconv_io_bdata; // @[VConvAlu.scala 24:18]
- wire [8:0] vconv_io_abias; // @[VConvAlu.scala 24:18]
- wire [8:0] vconv_io_bbias; // @[VConvAlu.scala 24:18]
- wire vconv_io_asign; // @[VConvAlu.scala 24:18]
- wire vconv_io_bsign; // @[VConvAlu.scala 24:18]
- wire [255:0] vconv_io_out_0; // @[VConvAlu.scala 24:18]
- wire [255:0] vconv_io_out_1; // @[VConvAlu.scala 24:18]
- wire [255:0] vconv_io_out_2; // @[VConvAlu.scala 24:18]
- wire [255:0] vconv_io_out_3; // @[VConvAlu.scala 24:18]
- wire [255:0] vconv_io_out_4; // @[VConvAlu.scala 24:18]
- wire [255:0] vconv_io_out_5; // @[VConvAlu.scala 24:18]
- wire [255:0] vconv_io_out_6; // @[VConvAlu.scala 24:18]
- wire [255:0] vconv_io_out_7; // @[VConvAlu.scala 24:18]
- reg [63:0] writePrev; // @[VRegfile.scala 145:26]
- wire [63:0] _writeSet_0_T = 64'h1 << io_write_0_addr; // @[VRegfile.scala 149:49]
- wire [63:0] writeSet_0 = io_write_0_valid ? _writeSet_0_T : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _writeSet_1_T = 64'h1 << io_write_1_addr; // @[VRegfile.scala 149:49]
- wire [63:0] writeSet_1 = io_write_1_valid ? _writeSet_1_T : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _writeSet_2_T = 64'h1 << io_write_2_addr; // @[VRegfile.scala 149:49]
- wire [63:0] writeSet_2 = io_write_2_valid ? _writeSet_2_T : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _writeSet_3_T = 64'h1 << io_write_3_addr; // @[VRegfile.scala 149:49]
- wire [63:0] writeSet_3 = io_write_3_valid ? _writeSet_3_T : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _writeSet_4_T = 64'h1 << io_write_4_addr; // @[VRegfile.scala 149:49]
- wire [63:0] writeSet_4 = io_write_4_valid ? _writeSet_4_T : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _writeSet_5_T = 64'h1 << io_write_5_addr; // @[VRegfile.scala 149:49]
- wire [63:0] writeSet_5 = io_write_5_valid ? _writeSet_5_T : 64'h0; // @[Library.scala 22:8]
- wire [63:0] _writeCurr_T_1 = writeSet_0 | writeSet_1; // @[Library.scala 76:39]
- wire [63:0] _writeCurr_T_2 = _writeCurr_T_1 | writeSet_2; // @[Library.scala 76:39]
- wire [63:0] _writeCurr_T_3 = _writeCurr_T_2 | writeSet_3; // @[Library.scala 76:39]
- wire [63:0] _writeCurr_T_4 = _writeCurr_T_3 | writeSet_4; // @[Library.scala 76:39]
- wire [63:0] writeCurr = _writeCurr_T_4 | writeSet_5; // @[Library.scala 76:39]
- wire [2:0] writevalid_lo = {io_write_2_valid,io_write_1_valid,io_write_0_valid}; // @[VRegfile.scala 158:35]
- wire [2:0] writevalid_hi = {io_write_5_valid,io_write_4_valid,io_write_3_valid}; // @[VRegfile.scala 158:35]
- wire [5:0] writevalid = {io_write_5_valid,io_write_4_valid,io_write_3_valid,io_write_2_valid,io_write_1_valid,
- io_write_0_valid}; // @[VRegfile.scala 158:35]
- reg [5:0] writevalidReg; // @[VRegfile.scala 160:30]
- reg [5:0] writebitsReg_0_addr; // @[VRegfile.scala 161:25]
- reg [255:0] writebitsReg_0_data; // @[VRegfile.scala 161:25]
- reg [5:0] writebitsReg_1_addr; // @[VRegfile.scala 161:25]
- reg [255:0] writebitsReg_1_data; // @[VRegfile.scala 161:25]
- reg [5:0] writebitsReg_2_addr; // @[VRegfile.scala 161:25]
- reg [255:0] writebitsReg_2_data; // @[VRegfile.scala 161:25]
- reg [5:0] writebitsReg_3_addr; // @[VRegfile.scala 161:25]
- reg [255:0] writebitsReg_3_data; // @[VRegfile.scala 161:25]
- reg [5:0] writebitsReg_4_addr; // @[VRegfile.scala 161:25]
- reg [255:0] writebitsReg_4_data; // @[VRegfile.scala 161:25]
- reg [5:0] writebitsReg_5_addr; // @[VRegfile.scala 161:25]
- reg [255:0] writebitsReg_5_data; // @[VRegfile.scala 161:25]
- reg [255:0] readData_0; // @[VRegfile.scala 190:21]
- reg [255:0] readData_1; // @[VRegfile.scala 190:21]
- reg [255:0] readData_2; // @[VRegfile.scala 190:21]
- reg [255:0] readData_3; // @[VRegfile.scala 190:21]
- reg [255:0] readData_4; // @[VRegfile.scala 190:21]
- reg [255:0] readData_5; // @[VRegfile.scala 190:21]
- reg [255:0] readData_6; // @[VRegfile.scala 190:21]
- wire _f1validBits_2_T_1 = io_write_2_addr == io_read_0_addr; // @[VRegfile.scala 236:43]
- wire f1validBits__2 = writevalid[2] & _f1validBits_2_T_1; // @[VRegfile.scala 235:39]
- wire _f1validBits_1_T_1 = io_write_1_addr == io_read_0_addr; // @[VRegfile.scala 236:43]
- wire f1validBits__1 = writevalid[1] & _f1validBits_1_T_1; // @[VRegfile.scala 235:39]
- wire _f1validBits_0_T_1 = io_write_0_addr == io_read_0_addr; // @[VRegfile.scala 236:43]
- wire f1validBits__0 = writevalid[0] & _f1validBits_0_T_1; // @[VRegfile.scala 235:39]
- wire _f1validBits_5_T_1 = io_write_5_addr == io_read_0_addr; // @[VRegfile.scala 236:43]
- wire f1validBits__5 = writevalid[5] & _f1validBits_5_T_1; // @[VRegfile.scala 235:39]
- wire _f1validBits_4_T_1 = io_write_4_addr == io_read_0_addr; // @[VRegfile.scala 236:43]
- wire f1validBits__4 = writevalid[4] & _f1validBits_4_T_1; // @[VRegfile.scala 235:39]
- wire _f1validBits_3_T_1 = io_write_3_addr == io_read_0_addr; // @[VRegfile.scala 236:43]
- wire f1validBits__3 = writevalid[3] & _f1validBits_3_T_1; // @[VRegfile.scala 235:39]
- wire [5:0] f1valid = {f1validBits__5,f1validBits__4,f1validBits__3,f1validBits__2,f1validBits__1,f1validBits__0}; // @[VRegfile.scala 227:31]
- wire [1:0] _T_6 = f1valid[1] + f1valid[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_26 = {{1'd0}, f1valid[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_8 = _GEN_26 + _T_6; // @[Bitwise.scala 48:55]
- wire [1:0] _T_10 = f1valid[4] + f1valid[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_27 = {{1'd0}, f1valid[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_12 = _GEN_27 + _T_10; // @[Bitwise.scala 48:55]
- wire [2:0] _T_14 = _T_8[1:0] + _T_12[1:0]; // @[Bitwise.scala 48:55]
- wire _T_18 = ~reset; // @[VRegfile.scala 228:11]
- wire _f2validBits_2_T_1 = writebitsReg_2_addr == io_read_0_addr; // @[VRegfile.scala 241:46]
- wire f2validBits__2 = writevalidReg[2] & _f2validBits_2_T_1; // @[VRegfile.scala 240:42]
- wire _f2validBits_1_T_1 = writebitsReg_1_addr == io_read_0_addr; // @[VRegfile.scala 241:46]
- wire f2validBits__1 = writevalidReg[1] & _f2validBits_1_T_1; // @[VRegfile.scala 240:42]
- wire _f2validBits_0_T_1 = writebitsReg_0_addr == io_read_0_addr; // @[VRegfile.scala 241:46]
- wire f2validBits__0 = writevalidReg[0] & _f2validBits_0_T_1; // @[VRegfile.scala 240:42]
- wire _f2validBits_5_T_1 = writebitsReg_5_addr == io_read_0_addr; // @[VRegfile.scala 241:46]
- wire f2validBits__5 = writevalidReg[5] & _f2validBits_5_T_1; // @[VRegfile.scala 240:42]
- wire _f2validBits_4_T_1 = writebitsReg_4_addr == io_read_0_addr; // @[VRegfile.scala 241:46]
- wire f2validBits__4 = writevalidReg[4] & _f2validBits_4_T_1; // @[VRegfile.scala 240:42]
- wire _f2validBits_3_T_1 = writebitsReg_3_addr == io_read_0_addr; // @[VRegfile.scala 241:46]
- wire f2validBits__3 = writevalidReg[3] & _f2validBits_3_T_1; // @[VRegfile.scala 240:42]
- wire [5:0] f2valid = {f2validBits__5,f2validBits__4,f2validBits__3,f2validBits__2,f2validBits__1,f2validBits__0}; // @[VRegfile.scala 231:31]
- wire [1:0] _T_26 = f2valid[1] + f2valid[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_28 = {{1'd0}, f2valid[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_28 = _GEN_28 + _T_26; // @[Bitwise.scala 48:55]
- wire [1:0] _T_30 = f2valid[4] + f2valid[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_29 = {{1'd0}, f2valid[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_32 = _GEN_29 + _T_30; // @[Bitwise.scala 48:55]
- wire [2:0] _T_34 = _T_28[1:0] + _T_32[1:0]; // @[Bitwise.scala 48:55]
- wire [255:0] f1dataBits__0 = f1valid[0] ? io_write_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1dataBits__1 = f1valid[1] ? io_write_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_1 = f1dataBits__0 | f1dataBits__1; // @[Library.scala 76:39]
- wire [255:0] f1dataBits__2 = f1valid[2] ? io_write_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_2 = _f1data_T_1 | f1dataBits__2; // @[Library.scala 76:39]
- wire [255:0] f1dataBits__3 = f1valid[3] ? io_write_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_3 = _f1data_T_2 | f1dataBits__3; // @[Library.scala 76:39]
- wire [255:0] f1dataBits__4 = f1valid[4] ? io_write_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_4 = _f1data_T_3 | f1dataBits__4; // @[Library.scala 76:39]
- wire [255:0] f1dataBits__5 = f1valid[5] ? io_write_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1data = _f1data_T_4 | f1dataBits__5; // @[Library.scala 76:39]
- wire [255:0] f2dataBits__0 = f2valid[0] ? writebitsReg_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2dataBits__1 = f2valid[1] ? writebitsReg_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_1 = f2dataBits__0 | f2dataBits__1; // @[Library.scala 76:39]
- wire [255:0] f2dataBits__2 = f2valid[2] ? writebitsReg_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_2 = _f2data_T_1 | f2dataBits__2; // @[Library.scala 76:39]
- wire [255:0] f2dataBits__3 = f2valid[3] ? writebitsReg_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_3 = _f2data_T_2 | f2dataBits__3; // @[Library.scala 76:39]
- wire [255:0] f2dataBits__4 = f2valid[4] ? writebitsReg_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_4 = _f2data_T_3 | f2dataBits__4; // @[Library.scala 76:39]
- wire [255:0] f2dataBits__5 = f2valid[5] ? writebitsReg_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2data = _f2data_T_4 | f2dataBits__5; // @[Library.scala 76:39]
- wire _sel_T_1 = f1valid != 6'h0; // @[VRegfile.scala 261:43]
- wire _sel_T_4 = f1valid == 6'h0; // @[VRegfile.scala 262:43]
- wire _sel_T_7 = f1valid == 6'h0 & f2valid != 6'h0; // @[VRegfile.scala 262:51]
- wire _sel_T_12 = _sel_T_4 & f2valid == 6'h0; // @[VRegfile.scala 263:51]
- wire [3:0] sel = {1'h0,_sel_T_1,_sel_T_7,_sel_T_12}; // @[Cat.scala 31:58]
- wire [1:0] _T_44 = sel[0] + sel[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_46 = sel[2] + sel[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_48 = _T_44 + _T_46; // @[Bitwise.scala 48:55]
- wire [255:0] _data_T_3 = sel[2] ? f1data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_6 = sel[1] ? f2data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_7 = _data_T_3 | _data_T_6; // @[VRegfile.scala 267:38]
- wire [31:0] rdata_0_1 = vreg_1_io_read_0_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_0_0 = vreg_0_io_read_0_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_0_3 = vreg_3_io_read_0_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_0_2 = vreg_2_io_read_0_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_0_5 = vreg_5_io_read_0_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_0_4 = vreg_4_io_read_0_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_0_7 = vreg_7_io_read_0_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_0_6 = vreg_6_io_read_0_data; // @[VRegfile.scala 215:19 220:19]
- wire [255:0] _data_T_9 = {rdata_0_7,rdata_0_6,rdata_0_5,rdata_0_4,rdata_0_3,rdata_0_2,rdata_0_1,rdata_0_0}; // @[VRegfile.scala 269:39]
- wire [255:0] _data_T_10 = sel[0] ? _data_T_9 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] data = _data_T_7 | _data_T_10; // @[VRegfile.scala 268:38]
- wire _f1validBits_2_T_4 = io_write_2_addr == io_read_1_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_1_2 = writevalid[2] & _f1validBits_2_T_4; // @[VRegfile.scala 235:39]
- wire _f1validBits_1_T_4 = io_write_1_addr == io_read_1_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_1_1 = writevalid[1] & _f1validBits_1_T_4; // @[VRegfile.scala 235:39]
- wire _f1validBits_0_T_4 = io_write_0_addr == io_read_1_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_1_0 = writevalid[0] & _f1validBits_0_T_4; // @[VRegfile.scala 235:39]
- wire _f1validBits_5_T_4 = io_write_5_addr == io_read_1_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_1_5 = writevalid[5] & _f1validBits_5_T_4; // @[VRegfile.scala 235:39]
- wire _f1validBits_4_T_4 = io_write_4_addr == io_read_1_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_1_4 = writevalid[4] & _f1validBits_4_T_4; // @[VRegfile.scala 235:39]
- wire _f1validBits_3_T_4 = io_write_3_addr == io_read_1_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_1_3 = writevalid[3] & _f1validBits_3_T_4; // @[VRegfile.scala 235:39]
- wire [5:0] f1valid_1 = {f1validBits_1_5,f1validBits_1_4,f1validBits_1_3,f1validBits_1_2,f1validBits_1_1,
- f1validBits_1_0}; // @[VRegfile.scala 227:31]
- wire [1:0] _T_60 = f1valid_1[1] + f1valid_1[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_30 = {{1'd0}, f1valid_1[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_62 = _GEN_30 + _T_60; // @[Bitwise.scala 48:55]
- wire [1:0] _T_64 = f1valid_1[4] + f1valid_1[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_31 = {{1'd0}, f1valid_1[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_66 = _GEN_31 + _T_64; // @[Bitwise.scala 48:55]
- wire [2:0] _T_68 = _T_62[1:0] + _T_66[1:0]; // @[Bitwise.scala 48:55]
- wire _f2validBits_2_T_4 = writebitsReg_2_addr == io_read_1_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_1_2 = writevalidReg[2] & _f2validBits_2_T_4; // @[VRegfile.scala 240:42]
- wire _f2validBits_1_T_4 = writebitsReg_1_addr == io_read_1_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_1_1 = writevalidReg[1] & _f2validBits_1_T_4; // @[VRegfile.scala 240:42]
- wire _f2validBits_0_T_4 = writebitsReg_0_addr == io_read_1_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_1_0 = writevalidReg[0] & _f2validBits_0_T_4; // @[VRegfile.scala 240:42]
- wire _f2validBits_5_T_4 = writebitsReg_5_addr == io_read_1_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_1_5 = writevalidReg[5] & _f2validBits_5_T_4; // @[VRegfile.scala 240:42]
- wire _f2validBits_4_T_4 = writebitsReg_4_addr == io_read_1_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_1_4 = writevalidReg[4] & _f2validBits_4_T_4; // @[VRegfile.scala 240:42]
- wire _f2validBits_3_T_4 = writebitsReg_3_addr == io_read_1_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_1_3 = writevalidReg[3] & _f2validBits_3_T_4; // @[VRegfile.scala 240:42]
- wire [5:0] f2valid_1 = {f2validBits_1_5,f2validBits_1_4,f2validBits_1_3,f2validBits_1_2,f2validBits_1_1,
- f2validBits_1_0}; // @[VRegfile.scala 231:31]
- wire [1:0] _T_80 = f2valid_1[1] + f2valid_1[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_32 = {{1'd0}, f2valid_1[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_82 = _GEN_32 + _T_80; // @[Bitwise.scala 48:55]
- wire [1:0] _T_84 = f2valid_1[4] + f2valid_1[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_33 = {{1'd0}, f2valid_1[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_86 = _GEN_33 + _T_84; // @[Bitwise.scala 48:55]
- wire [2:0] _T_88 = _T_82[1:0] + _T_86[1:0]; // @[Bitwise.scala 48:55]
- wire [255:0] f1dataBits_1_0 = f1valid_1[0] ? io_write_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1dataBits_1_1 = f1valid_1[1] ? io_write_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_6 = f1dataBits_1_0 | f1dataBits_1_1; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_1_2 = f1valid_1[2] ? io_write_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_7 = _f1data_T_6 | f1dataBits_1_2; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_1_3 = f1valid_1[3] ? io_write_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_8 = _f1data_T_7 | f1dataBits_1_3; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_1_4 = f1valid_1[4] ? io_write_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_9 = _f1data_T_8 | f1dataBits_1_4; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_1_5 = f1valid_1[5] ? io_write_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1data_1 = _f1data_T_9 | f1dataBits_1_5; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_1_0 = f2valid_1[0] ? writebitsReg_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2dataBits_1_1 = f2valid_1[1] ? writebitsReg_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_6 = f2dataBits_1_0 | f2dataBits_1_1; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_1_2 = f2valid_1[2] ? writebitsReg_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_7 = _f2data_T_6 | f2dataBits_1_2; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_1_3 = f2valid_1[3] ? writebitsReg_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_8 = _f2data_T_7 | f2dataBits_1_3; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_1_4 = f2valid_1[4] ? writebitsReg_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_9 = _f2data_T_8 | f2dataBits_1_4; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_1_5 = f2valid_1[5] ? writebitsReg_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2data_1 = _f2data_T_9 | f2dataBits_1_5; // @[Library.scala 76:39]
- wire [255:0] scalarData_1 = {io_scalar_0_data,io_scalar_0_data,io_scalar_0_data,io_scalar_0_data,io_scalar_0_data,
- io_scalar_0_data,io_scalar_0_data,io_scalar_0_data}; // @[VRegfile.scala 210:25]
- wire _sel_T_13 = ~io_scalar_0_valid; // @[VRegfile.scala 261:19]
- wire _sel_T_15 = ~io_scalar_0_valid & f1valid_1 != 6'h0; // @[VRegfile.scala 261:32]
- wire _sel_T_18 = _sel_T_13 & f1valid_1 == 6'h0; // @[VRegfile.scala 262:32]
- wire _sel_T_20 = _sel_T_13 & f1valid_1 == 6'h0 & f2valid_1 != 6'h0; // @[VRegfile.scala 262:51]
- wire _sel_T_25 = _sel_T_18 & f2valid_1 == 6'h0; // @[VRegfile.scala 263:51]
- wire [3:0] sel_1 = {io_scalar_0_valid,_sel_T_15,_sel_T_20,_sel_T_25}; // @[Cat.scala 31:58]
- wire [1:0] _T_98 = sel_1[0] + sel_1[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_100 = sel_1[2] + sel_1[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_102 = _T_98 + _T_100; // @[Bitwise.scala 48:55]
- wire [255:0] _data_T_12 = sel_1[3] ? scalarData_1 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_14 = sel_1[2] ? f1data_1 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_15 = _data_T_12 | _data_T_14; // @[VRegfile.scala 266:42]
- wire [255:0] _data_T_17 = sel_1[1] ? f2data_1 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_18 = _data_T_15 | _data_T_17; // @[VRegfile.scala 267:38]
- wire [31:0] rdata_1_1 = vreg_1_io_read_1_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_1_0 = vreg_0_io_read_1_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_1_3 = vreg_3_io_read_1_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_1_2 = vreg_2_io_read_1_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_1_5 = vreg_5_io_read_1_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_1_4 = vreg_4_io_read_1_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_1_7 = vreg_7_io_read_1_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_1_6 = vreg_6_io_read_1_data; // @[VRegfile.scala 215:19 220:19]
- wire [255:0] _data_T_20 = {rdata_1_7,rdata_1_6,rdata_1_5,rdata_1_4,rdata_1_3,rdata_1_2,rdata_1_1,rdata_1_0}; // @[VRegfile.scala 269:39]
- wire [255:0] _data_T_21 = sel_1[0] ? _data_T_20 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] data_1 = _data_T_18 | _data_T_21; // @[VRegfile.scala 268:38]
- wire rvalid = io_read_1_valid | io_scalar_0_valid; // @[VRegfile.scala 274:26]
- wire _f1validBits_2_T_7 = io_write_2_addr == io_read_2_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_2_2 = writevalid[2] & _f1validBits_2_T_7; // @[VRegfile.scala 235:39]
- wire _f1validBits_1_T_7 = io_write_1_addr == io_read_2_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_2_1 = writevalid[1] & _f1validBits_1_T_7; // @[VRegfile.scala 235:39]
- wire _f1validBits_0_T_7 = io_write_0_addr == io_read_2_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_2_0 = writevalid[0] & _f1validBits_0_T_7; // @[VRegfile.scala 235:39]
- wire _f1validBits_5_T_7 = io_write_5_addr == io_read_2_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_2_5 = writevalid[5] & _f1validBits_5_T_7; // @[VRegfile.scala 235:39]
- wire _f1validBits_4_T_7 = io_write_4_addr == io_read_2_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_2_4 = writevalid[4] & _f1validBits_4_T_7; // @[VRegfile.scala 235:39]
- wire _f1validBits_3_T_7 = io_write_3_addr == io_read_2_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_2_3 = writevalid[3] & _f1validBits_3_T_7; // @[VRegfile.scala 235:39]
- wire [5:0] f1valid_2 = {f1validBits_2_5,f1validBits_2_4,f1validBits_2_3,f1validBits_2_2,f1validBits_2_1,
- f1validBits_2_0}; // @[VRegfile.scala 227:31]
- wire [1:0] _T_114 = f1valid_2[1] + f1valid_2[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_34 = {{1'd0}, f1valid_2[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_116 = _GEN_34 + _T_114; // @[Bitwise.scala 48:55]
- wire [1:0] _T_118 = f1valid_2[4] + f1valid_2[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_35 = {{1'd0}, f1valid_2[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_120 = _GEN_35 + _T_118; // @[Bitwise.scala 48:55]
- wire [2:0] _T_122 = _T_116[1:0] + _T_120[1:0]; // @[Bitwise.scala 48:55]
- wire _f2validBits_2_T_7 = writebitsReg_2_addr == io_read_2_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_2_2 = writevalidReg[2] & _f2validBits_2_T_7; // @[VRegfile.scala 240:42]
- wire _f2validBits_1_T_7 = writebitsReg_1_addr == io_read_2_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_2_1 = writevalidReg[1] & _f2validBits_1_T_7; // @[VRegfile.scala 240:42]
- wire _f2validBits_0_T_7 = writebitsReg_0_addr == io_read_2_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_2_0 = writevalidReg[0] & _f2validBits_0_T_7; // @[VRegfile.scala 240:42]
- wire _f2validBits_5_T_7 = writebitsReg_5_addr == io_read_2_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_2_5 = writevalidReg[5] & _f2validBits_5_T_7; // @[VRegfile.scala 240:42]
- wire _f2validBits_4_T_7 = writebitsReg_4_addr == io_read_2_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_2_4 = writevalidReg[4] & _f2validBits_4_T_7; // @[VRegfile.scala 240:42]
- wire _f2validBits_3_T_7 = writebitsReg_3_addr == io_read_2_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_2_3 = writevalidReg[3] & _f2validBits_3_T_7; // @[VRegfile.scala 240:42]
- wire [5:0] f2valid_2 = {f2validBits_2_5,f2validBits_2_4,f2validBits_2_3,f2validBits_2_2,f2validBits_2_1,
- f2validBits_2_0}; // @[VRegfile.scala 231:31]
- wire [1:0] _T_134 = f2valid_2[1] + f2valid_2[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_36 = {{1'd0}, f2valid_2[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_136 = _GEN_36 + _T_134; // @[Bitwise.scala 48:55]
- wire [1:0] _T_138 = f2valid_2[4] + f2valid_2[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_37 = {{1'd0}, f2valid_2[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_140 = _GEN_37 + _T_138; // @[Bitwise.scala 48:55]
- wire [2:0] _T_142 = _T_136[1:0] + _T_140[1:0]; // @[Bitwise.scala 48:55]
- wire [255:0] f1dataBits_2_0 = f1valid_2[0] ? io_write_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1dataBits_2_1 = f1valid_2[1] ? io_write_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_11 = f1dataBits_2_0 | f1dataBits_2_1; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_2_2 = f1valid_2[2] ? io_write_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_12 = _f1data_T_11 | f1dataBits_2_2; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_2_3 = f1valid_2[3] ? io_write_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_13 = _f1data_T_12 | f1dataBits_2_3; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_2_4 = f1valid_2[4] ? io_write_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_14 = _f1data_T_13 | f1dataBits_2_4; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_2_5 = f1valid_2[5] ? io_write_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1data_2 = _f1data_T_14 | f1dataBits_2_5; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_2_0 = f2valid_2[0] ? writebitsReg_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2dataBits_2_1 = f2valid_2[1] ? writebitsReg_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_11 = f2dataBits_2_0 | f2dataBits_2_1; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_2_2 = f2valid_2[2] ? writebitsReg_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_12 = _f2data_T_11 | f2dataBits_2_2; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_2_3 = f2valid_2[3] ? writebitsReg_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_13 = _f2data_T_12 | f2dataBits_2_3; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_2_4 = f2valid_2[4] ? writebitsReg_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_14 = _f2data_T_13 | f2dataBits_2_4; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_2_5 = f2valid_2[5] ? writebitsReg_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2data_2 = _f2data_T_14 | f2dataBits_2_5; // @[Library.scala 76:39]
- wire _sel_T_27 = f1valid_2 != 6'h0; // @[VRegfile.scala 261:43]
- wire _sel_T_30 = f1valid_2 == 6'h0; // @[VRegfile.scala 262:43]
- wire _sel_T_33 = f1valid_2 == 6'h0 & f2valid_2 != 6'h0; // @[VRegfile.scala 262:51]
- wire _sel_T_38 = _sel_T_30 & f2valid_2 == 6'h0; // @[VRegfile.scala 263:51]
- wire [3:0] sel_2 = {1'h0,_sel_T_27,_sel_T_33,_sel_T_38}; // @[Cat.scala 31:58]
- wire [1:0] _T_152 = sel_2[0] + sel_2[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_154 = sel_2[2] + sel_2[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_156 = _T_152 + _T_154; // @[Bitwise.scala 48:55]
- wire [255:0] _data_T_25 = sel_2[2] ? f1data_2 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_28 = sel_2[1] ? f2data_2 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_29 = _data_T_25 | _data_T_28; // @[VRegfile.scala 267:38]
- wire [31:0] rdata_2_1 = vreg_1_io_read_2_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_2_0 = vreg_0_io_read_2_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_2_3 = vreg_3_io_read_2_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_2_2 = vreg_2_io_read_2_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_2_5 = vreg_5_io_read_2_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_2_4 = vreg_4_io_read_2_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_2_7 = vreg_7_io_read_2_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_2_6 = vreg_6_io_read_2_data; // @[VRegfile.scala 215:19 220:19]
- wire [255:0] _data_T_31 = {rdata_2_7,rdata_2_6,rdata_2_5,rdata_2_4,rdata_2_3,rdata_2_2,rdata_2_1,rdata_2_0}; // @[VRegfile.scala 269:39]
- wire [255:0] _data_T_32 = sel_2[0] ? _data_T_31 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] data_2 = _data_T_29 | _data_T_32; // @[VRegfile.scala 268:38]
- wire _f1validBits_2_T_10 = io_write_2_addr == io_read_3_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_3_2 = writevalid[2] & _f1validBits_2_T_10; // @[VRegfile.scala 235:39]
- wire _f1validBits_1_T_10 = io_write_1_addr == io_read_3_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_3_1 = writevalid[1] & _f1validBits_1_T_10; // @[VRegfile.scala 235:39]
- wire _f1validBits_0_T_10 = io_write_0_addr == io_read_3_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_3_0 = writevalid[0] & _f1validBits_0_T_10; // @[VRegfile.scala 235:39]
- wire _f1validBits_5_T_10 = io_write_5_addr == io_read_3_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_3_5 = writevalid[5] & _f1validBits_5_T_10; // @[VRegfile.scala 235:39]
- wire _f1validBits_4_T_10 = io_write_4_addr == io_read_3_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_3_4 = writevalid[4] & _f1validBits_4_T_10; // @[VRegfile.scala 235:39]
- wire _f1validBits_3_T_10 = io_write_3_addr == io_read_3_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_3_3 = writevalid[3] & _f1validBits_3_T_10; // @[VRegfile.scala 235:39]
- wire [5:0] f1valid_3 = {f1validBits_3_5,f1validBits_3_4,f1validBits_3_3,f1validBits_3_2,f1validBits_3_1,
- f1validBits_3_0}; // @[VRegfile.scala 227:31]
- wire [1:0] _T_168 = f1valid_3[1] + f1valid_3[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_38 = {{1'd0}, f1valid_3[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_170 = _GEN_38 + _T_168; // @[Bitwise.scala 48:55]
- wire [1:0] _T_172 = f1valid_3[4] + f1valid_3[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_39 = {{1'd0}, f1valid_3[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_174 = _GEN_39 + _T_172; // @[Bitwise.scala 48:55]
- wire [2:0] _T_176 = _T_170[1:0] + _T_174[1:0]; // @[Bitwise.scala 48:55]
- wire _f2validBits_2_T_10 = writebitsReg_2_addr == io_read_3_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_3_2 = writevalidReg[2] & _f2validBits_2_T_10; // @[VRegfile.scala 240:42]
- wire _f2validBits_1_T_10 = writebitsReg_1_addr == io_read_3_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_3_1 = writevalidReg[1] & _f2validBits_1_T_10; // @[VRegfile.scala 240:42]
- wire _f2validBits_0_T_10 = writebitsReg_0_addr == io_read_3_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_3_0 = writevalidReg[0] & _f2validBits_0_T_10; // @[VRegfile.scala 240:42]
- wire _f2validBits_5_T_10 = writebitsReg_5_addr == io_read_3_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_3_5 = writevalidReg[5] & _f2validBits_5_T_10; // @[VRegfile.scala 240:42]
- wire _f2validBits_4_T_10 = writebitsReg_4_addr == io_read_3_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_3_4 = writevalidReg[4] & _f2validBits_4_T_10; // @[VRegfile.scala 240:42]
- wire _f2validBits_3_T_10 = writebitsReg_3_addr == io_read_3_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_3_3 = writevalidReg[3] & _f2validBits_3_T_10; // @[VRegfile.scala 240:42]
- wire [5:0] f2valid_3 = {f2validBits_3_5,f2validBits_3_4,f2validBits_3_3,f2validBits_3_2,f2validBits_3_1,
- f2validBits_3_0}; // @[VRegfile.scala 231:31]
- wire [1:0] _T_188 = f2valid_3[1] + f2valid_3[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_40 = {{1'd0}, f2valid_3[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_190 = _GEN_40 + _T_188; // @[Bitwise.scala 48:55]
- wire [1:0] _T_192 = f2valid_3[4] + f2valid_3[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_41 = {{1'd0}, f2valid_3[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_194 = _GEN_41 + _T_192; // @[Bitwise.scala 48:55]
- wire [2:0] _T_196 = _T_190[1:0] + _T_194[1:0]; // @[Bitwise.scala 48:55]
- wire [255:0] f1dataBits_3_0 = f1valid_3[0] ? io_write_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1dataBits_3_1 = f1valid_3[1] ? io_write_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_16 = f1dataBits_3_0 | f1dataBits_3_1; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_3_2 = f1valid_3[2] ? io_write_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_17 = _f1data_T_16 | f1dataBits_3_2; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_3_3 = f1valid_3[3] ? io_write_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_18 = _f1data_T_17 | f1dataBits_3_3; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_3_4 = f1valid_3[4] ? io_write_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_19 = _f1data_T_18 | f1dataBits_3_4; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_3_5 = f1valid_3[5] ? io_write_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1data_3 = _f1data_T_19 | f1dataBits_3_5; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_3_0 = f2valid_3[0] ? writebitsReg_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2dataBits_3_1 = f2valid_3[1] ? writebitsReg_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_16 = f2dataBits_3_0 | f2dataBits_3_1; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_3_2 = f2valid_3[2] ? writebitsReg_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_17 = _f2data_T_16 | f2dataBits_3_2; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_3_3 = f2valid_3[3] ? writebitsReg_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_18 = _f2data_T_17 | f2dataBits_3_3; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_3_4 = f2valid_3[4] ? writebitsReg_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_19 = _f2data_T_18 | f2dataBits_3_4; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_3_5 = f2valid_3[5] ? writebitsReg_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2data_3 = _f2data_T_19 | f2dataBits_3_5; // @[Library.scala 76:39]
- wire _sel_T_40 = f1valid_3 != 6'h0; // @[VRegfile.scala 261:43]
- wire _sel_T_43 = f1valid_3 == 6'h0; // @[VRegfile.scala 262:43]
- wire _sel_T_46 = f1valid_3 == 6'h0 & f2valid_3 != 6'h0; // @[VRegfile.scala 262:51]
- wire _sel_T_51 = _sel_T_43 & f2valid_3 == 6'h0; // @[VRegfile.scala 263:51]
- wire [3:0] sel_3 = {1'h0,_sel_T_40,_sel_T_46,_sel_T_51}; // @[Cat.scala 31:58]
- wire [1:0] _T_206 = sel_3[0] + sel_3[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_208 = sel_3[2] + sel_3[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_210 = _T_206 + _T_208; // @[Bitwise.scala 48:55]
- wire [255:0] _data_T_36 = sel_3[2] ? f1data_3 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_39 = sel_3[1] ? f2data_3 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_40 = _data_T_36 | _data_T_39; // @[VRegfile.scala 267:38]
- wire [31:0] rdata_3_1 = vreg_1_io_read_3_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_3_0 = vreg_0_io_read_3_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_3_3 = vreg_3_io_read_3_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_3_2 = vreg_2_io_read_3_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_3_5 = vreg_5_io_read_3_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_3_4 = vreg_4_io_read_3_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_3_7 = vreg_7_io_read_3_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_3_6 = vreg_6_io_read_3_data; // @[VRegfile.scala 215:19 220:19]
- wire [255:0] _data_T_42 = {rdata_3_7,rdata_3_6,rdata_3_5,rdata_3_4,rdata_3_3,rdata_3_2,rdata_3_1,rdata_3_0}; // @[VRegfile.scala 269:39]
- wire [255:0] _data_T_43 = sel_3[0] ? _data_T_42 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] data_3 = _data_T_40 | _data_T_43; // @[VRegfile.scala 268:38]
- wire _f1validBits_2_T_13 = io_write_2_addr == io_read_4_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_4_2 = writevalid[2] & _f1validBits_2_T_13; // @[VRegfile.scala 235:39]
- wire _f1validBits_1_T_13 = io_write_1_addr == io_read_4_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_4_1 = writevalid[1] & _f1validBits_1_T_13; // @[VRegfile.scala 235:39]
- wire _f1validBits_0_T_13 = io_write_0_addr == io_read_4_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_4_0 = writevalid[0] & _f1validBits_0_T_13; // @[VRegfile.scala 235:39]
- wire _f1validBits_5_T_13 = io_write_5_addr == io_read_4_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_4_5 = writevalid[5] & _f1validBits_5_T_13; // @[VRegfile.scala 235:39]
- wire _f1validBits_4_T_13 = io_write_4_addr == io_read_4_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_4_4 = writevalid[4] & _f1validBits_4_T_13; // @[VRegfile.scala 235:39]
- wire _f1validBits_3_T_13 = io_write_3_addr == io_read_4_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_4_3 = writevalid[3] & _f1validBits_3_T_13; // @[VRegfile.scala 235:39]
- wire [5:0] f1valid_4 = {f1validBits_4_5,f1validBits_4_4,f1validBits_4_3,f1validBits_4_2,f1validBits_4_1,
- f1validBits_4_0}; // @[VRegfile.scala 227:31]
- wire [1:0] _T_222 = f1valid_4[1] + f1valid_4[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_42 = {{1'd0}, f1valid_4[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_224 = _GEN_42 + _T_222; // @[Bitwise.scala 48:55]
- wire [1:0] _T_226 = f1valid_4[4] + f1valid_4[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_43 = {{1'd0}, f1valid_4[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_228 = _GEN_43 + _T_226; // @[Bitwise.scala 48:55]
- wire [2:0] _T_230 = _T_224[1:0] + _T_228[1:0]; // @[Bitwise.scala 48:55]
- wire _f2validBits_2_T_13 = writebitsReg_2_addr == io_read_4_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_4_2 = writevalidReg[2] & _f2validBits_2_T_13; // @[VRegfile.scala 240:42]
- wire _f2validBits_1_T_13 = writebitsReg_1_addr == io_read_4_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_4_1 = writevalidReg[1] & _f2validBits_1_T_13; // @[VRegfile.scala 240:42]
- wire _f2validBits_0_T_13 = writebitsReg_0_addr == io_read_4_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_4_0 = writevalidReg[0] & _f2validBits_0_T_13; // @[VRegfile.scala 240:42]
- wire _f2validBits_5_T_13 = writebitsReg_5_addr == io_read_4_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_4_5 = writevalidReg[5] & _f2validBits_5_T_13; // @[VRegfile.scala 240:42]
- wire _f2validBits_4_T_13 = writebitsReg_4_addr == io_read_4_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_4_4 = writevalidReg[4] & _f2validBits_4_T_13; // @[VRegfile.scala 240:42]
- wire _f2validBits_3_T_13 = writebitsReg_3_addr == io_read_4_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_4_3 = writevalidReg[3] & _f2validBits_3_T_13; // @[VRegfile.scala 240:42]
- wire [5:0] f2valid_4 = {f2validBits_4_5,f2validBits_4_4,f2validBits_4_3,f2validBits_4_2,f2validBits_4_1,
- f2validBits_4_0}; // @[VRegfile.scala 231:31]
- wire [1:0] _T_242 = f2valid_4[1] + f2valid_4[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_44 = {{1'd0}, f2valid_4[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_244 = _GEN_44 + _T_242; // @[Bitwise.scala 48:55]
- wire [1:0] _T_246 = f2valid_4[4] + f2valid_4[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_45 = {{1'd0}, f2valid_4[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_248 = _GEN_45 + _T_246; // @[Bitwise.scala 48:55]
- wire [2:0] _T_250 = _T_244[1:0] + _T_248[1:0]; // @[Bitwise.scala 48:55]
- wire [255:0] f1dataBits_4_0 = f1valid_4[0] ? io_write_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1dataBits_4_1 = f1valid_4[1] ? io_write_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_21 = f1dataBits_4_0 | f1dataBits_4_1; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_4_2 = f1valid_4[2] ? io_write_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_22 = _f1data_T_21 | f1dataBits_4_2; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_4_3 = f1valid_4[3] ? io_write_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_23 = _f1data_T_22 | f1dataBits_4_3; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_4_4 = f1valid_4[4] ? io_write_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_24 = _f1data_T_23 | f1dataBits_4_4; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_4_5 = f1valid_4[5] ? io_write_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1data_4 = _f1data_T_24 | f1dataBits_4_5; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_4_0 = f2valid_4[0] ? writebitsReg_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2dataBits_4_1 = f2valid_4[1] ? writebitsReg_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_21 = f2dataBits_4_0 | f2dataBits_4_1; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_4_2 = f2valid_4[2] ? writebitsReg_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_22 = _f2data_T_21 | f2dataBits_4_2; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_4_3 = f2valid_4[3] ? writebitsReg_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_23 = _f2data_T_22 | f2dataBits_4_3; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_4_4 = f2valid_4[4] ? writebitsReg_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_24 = _f2data_T_23 | f2dataBits_4_4; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_4_5 = f2valid_4[5] ? writebitsReg_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2data_4 = _f2data_T_24 | f2dataBits_4_5; // @[Library.scala 76:39]
- wire [255:0] scalarData_4 = {io_scalar_1_data,io_scalar_1_data,io_scalar_1_data,io_scalar_1_data,io_scalar_1_data,
- io_scalar_1_data,io_scalar_1_data,io_scalar_1_data}; // @[VRegfile.scala 210:25]
- wire _sel_T_52 = ~io_scalar_1_valid; // @[VRegfile.scala 261:19]
- wire _sel_T_54 = ~io_scalar_1_valid & f1valid_4 != 6'h0; // @[VRegfile.scala 261:32]
- wire _sel_T_57 = _sel_T_52 & f1valid_4 == 6'h0; // @[VRegfile.scala 262:32]
- wire _sel_T_59 = _sel_T_52 & f1valid_4 == 6'h0 & f2valid_4 != 6'h0; // @[VRegfile.scala 262:51]
- wire _sel_T_64 = _sel_T_57 & f2valid_4 == 6'h0; // @[VRegfile.scala 263:51]
- wire [3:0] sel_4 = {io_scalar_1_valid,_sel_T_54,_sel_T_59,_sel_T_64}; // @[Cat.scala 31:58]
- wire [1:0] _T_260 = sel_4[0] + sel_4[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_262 = sel_4[2] + sel_4[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_264 = _T_260 + _T_262; // @[Bitwise.scala 48:55]
- wire [255:0] _data_T_45 = sel_4[3] ? scalarData_4 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_47 = sel_4[2] ? f1data_4 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_48 = _data_T_45 | _data_T_47; // @[VRegfile.scala 266:42]
- wire [255:0] _data_T_50 = sel_4[1] ? f2data_4 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_51 = _data_T_48 | _data_T_50; // @[VRegfile.scala 267:38]
- wire [31:0] rdata_4_1 = vreg_1_io_read_4_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_4_0 = vreg_0_io_read_4_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_4_3 = vreg_3_io_read_4_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_4_2 = vreg_2_io_read_4_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_4_5 = vreg_5_io_read_4_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_4_4 = vreg_4_io_read_4_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_4_7 = vreg_7_io_read_4_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_4_6 = vreg_6_io_read_4_data; // @[VRegfile.scala 215:19 220:19]
- wire [255:0] _data_T_53 = {rdata_4_7,rdata_4_6,rdata_4_5,rdata_4_4,rdata_4_3,rdata_4_2,rdata_4_1,rdata_4_0}; // @[VRegfile.scala 269:39]
- wire [255:0] _data_T_54 = sel_4[0] ? _data_T_53 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] data_4 = _data_T_51 | _data_T_54; // @[VRegfile.scala 268:38]
- wire rvalid_1 = io_read_4_valid | io_scalar_1_valid; // @[VRegfile.scala 274:26]
- wire _f1validBits_2_T_16 = io_write_2_addr == io_read_5_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_5_2 = writevalid[2] & _f1validBits_2_T_16; // @[VRegfile.scala 235:39]
- wire _f1validBits_1_T_16 = io_write_1_addr == io_read_5_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_5_1 = writevalid[1] & _f1validBits_1_T_16; // @[VRegfile.scala 235:39]
- wire _f1validBits_0_T_16 = io_write_0_addr == io_read_5_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_5_0 = writevalid[0] & _f1validBits_0_T_16; // @[VRegfile.scala 235:39]
- wire _f1validBits_5_T_16 = io_write_5_addr == io_read_5_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_5_5 = writevalid[5] & _f1validBits_5_T_16; // @[VRegfile.scala 235:39]
- wire _f1validBits_4_T_16 = io_write_4_addr == io_read_5_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_5_4 = writevalid[4] & _f1validBits_4_T_16; // @[VRegfile.scala 235:39]
- wire _f1validBits_3_T_16 = io_write_3_addr == io_read_5_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_5_3 = writevalid[3] & _f1validBits_3_T_16; // @[VRegfile.scala 235:39]
- wire [5:0] f1valid_5 = {f1validBits_5_5,f1validBits_5_4,f1validBits_5_3,f1validBits_5_2,f1validBits_5_1,
- f1validBits_5_0}; // @[VRegfile.scala 227:31]
- wire [1:0] _T_276 = f1valid_5[1] + f1valid_5[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_46 = {{1'd0}, f1valid_5[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_278 = _GEN_46 + _T_276; // @[Bitwise.scala 48:55]
- wire [1:0] _T_280 = f1valid_5[4] + f1valid_5[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_47 = {{1'd0}, f1valid_5[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_282 = _GEN_47 + _T_280; // @[Bitwise.scala 48:55]
- wire [2:0] _T_284 = _T_278[1:0] + _T_282[1:0]; // @[Bitwise.scala 48:55]
- wire _f2validBits_2_T_16 = writebitsReg_2_addr == io_read_5_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_5_2 = writevalidReg[2] & _f2validBits_2_T_16; // @[VRegfile.scala 240:42]
- wire _f2validBits_1_T_16 = writebitsReg_1_addr == io_read_5_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_5_1 = writevalidReg[1] & _f2validBits_1_T_16; // @[VRegfile.scala 240:42]
- wire _f2validBits_0_T_16 = writebitsReg_0_addr == io_read_5_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_5_0 = writevalidReg[0] & _f2validBits_0_T_16; // @[VRegfile.scala 240:42]
- wire _f2validBits_5_T_16 = writebitsReg_5_addr == io_read_5_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_5_5 = writevalidReg[5] & _f2validBits_5_T_16; // @[VRegfile.scala 240:42]
- wire _f2validBits_4_T_16 = writebitsReg_4_addr == io_read_5_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_5_4 = writevalidReg[4] & _f2validBits_4_T_16; // @[VRegfile.scala 240:42]
- wire _f2validBits_3_T_16 = writebitsReg_3_addr == io_read_5_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_5_3 = writevalidReg[3] & _f2validBits_3_T_16; // @[VRegfile.scala 240:42]
- wire [5:0] f2valid_5 = {f2validBits_5_5,f2validBits_5_4,f2validBits_5_3,f2validBits_5_2,f2validBits_5_1,
- f2validBits_5_0}; // @[VRegfile.scala 231:31]
- wire [1:0] _T_296 = f2valid_5[1] + f2valid_5[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_48 = {{1'd0}, f2valid_5[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_298 = _GEN_48 + _T_296; // @[Bitwise.scala 48:55]
- wire [1:0] _T_300 = f2valid_5[4] + f2valid_5[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_49 = {{1'd0}, f2valid_5[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_302 = _GEN_49 + _T_300; // @[Bitwise.scala 48:55]
- wire [2:0] _T_304 = _T_298[1:0] + _T_302[1:0]; // @[Bitwise.scala 48:55]
- wire [255:0] f1dataBits_5_0 = f1valid_5[0] ? io_write_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1dataBits_5_1 = f1valid_5[1] ? io_write_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_26 = f1dataBits_5_0 | f1dataBits_5_1; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_5_2 = f1valid_5[2] ? io_write_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_27 = _f1data_T_26 | f1dataBits_5_2; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_5_3 = f1valid_5[3] ? io_write_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_28 = _f1data_T_27 | f1dataBits_5_3; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_5_4 = f1valid_5[4] ? io_write_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_29 = _f1data_T_28 | f1dataBits_5_4; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_5_5 = f1valid_5[5] ? io_write_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1data_5 = _f1data_T_29 | f1dataBits_5_5; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_5_0 = f2valid_5[0] ? writebitsReg_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2dataBits_5_1 = f2valid_5[1] ? writebitsReg_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_26 = f2dataBits_5_0 | f2dataBits_5_1; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_5_2 = f2valid_5[2] ? writebitsReg_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_27 = _f2data_T_26 | f2dataBits_5_2; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_5_3 = f2valid_5[3] ? writebitsReg_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_28 = _f2data_T_27 | f2dataBits_5_3; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_5_4 = f2valid_5[4] ? writebitsReg_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_29 = _f2data_T_28 | f2dataBits_5_4; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_5_5 = f2valid_5[5] ? writebitsReg_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2data_5 = _f2data_T_29 | f2dataBits_5_5; // @[Library.scala 76:39]
- wire _sel_T_66 = f1valid_5 != 6'h0; // @[VRegfile.scala 261:43]
- wire _sel_T_69 = f1valid_5 == 6'h0; // @[VRegfile.scala 262:43]
- wire _sel_T_72 = f1valid_5 == 6'h0 & f2valid_5 != 6'h0; // @[VRegfile.scala 262:51]
- wire _sel_T_77 = _sel_T_69 & f2valid_5 == 6'h0; // @[VRegfile.scala 263:51]
- wire [3:0] sel_5 = {1'h0,_sel_T_66,_sel_T_72,_sel_T_77}; // @[Cat.scala 31:58]
- wire [1:0] _T_314 = sel_5[0] + sel_5[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_316 = sel_5[2] + sel_5[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_318 = _T_314 + _T_316; // @[Bitwise.scala 48:55]
- wire [255:0] _data_T_58 = sel_5[2] ? f1data_5 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_61 = sel_5[1] ? f2data_5 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_62 = _data_T_58 | _data_T_61; // @[VRegfile.scala 267:38]
- wire [31:0] rdata_5_1 = vreg_1_io_read_5_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_5_0 = vreg_0_io_read_5_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_5_3 = vreg_3_io_read_5_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_5_2 = vreg_2_io_read_5_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_5_5 = vreg_5_io_read_5_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_5_4 = vreg_4_io_read_5_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_5_7 = vreg_7_io_read_5_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_5_6 = vreg_6_io_read_5_data; // @[VRegfile.scala 215:19 220:19]
- wire [255:0] _data_T_64 = {rdata_5_7,rdata_5_6,rdata_5_5,rdata_5_4,rdata_5_3,rdata_5_2,rdata_5_1,rdata_5_0}; // @[VRegfile.scala 269:39]
- wire [255:0] _data_T_65 = sel_5[0] ? _data_T_64 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] data_5 = _data_T_62 | _data_T_65; // @[VRegfile.scala 268:38]
- wire _f1validBits_2_T_19 = io_write_2_addr == io_read_6_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_6_2 = writevalid[2] & _f1validBits_2_T_19; // @[VRegfile.scala 235:39]
- wire _f1validBits_1_T_19 = io_write_1_addr == io_read_6_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_6_1 = writevalid[1] & _f1validBits_1_T_19; // @[VRegfile.scala 235:39]
- wire _f1validBits_0_T_19 = io_write_0_addr == io_read_6_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_6_0 = writevalid[0] & _f1validBits_0_T_19; // @[VRegfile.scala 235:39]
- wire _f1validBits_5_T_19 = io_write_5_addr == io_read_6_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_6_5 = writevalid[5] & _f1validBits_5_T_19; // @[VRegfile.scala 235:39]
- wire _f1validBits_4_T_19 = io_write_4_addr == io_read_6_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_6_4 = writevalid[4] & _f1validBits_4_T_19; // @[VRegfile.scala 235:39]
- wire _f1validBits_3_T_19 = io_write_3_addr == io_read_6_addr; // @[VRegfile.scala 236:43]
- wire f1validBits_6_3 = writevalid[3] & _f1validBits_3_T_19; // @[VRegfile.scala 235:39]
- wire [5:0] f1valid_6 = {f1validBits_6_5,f1validBits_6_4,f1validBits_6_3,f1validBits_6_2,f1validBits_6_1,
- f1validBits_6_0}; // @[VRegfile.scala 227:31]
- wire [1:0] _T_330 = f1valid_6[1] + f1valid_6[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_50 = {{1'd0}, f1valid_6[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_332 = _GEN_50 + _T_330; // @[Bitwise.scala 48:55]
- wire [1:0] _T_334 = f1valid_6[4] + f1valid_6[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_51 = {{1'd0}, f1valid_6[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_336 = _GEN_51 + _T_334; // @[Bitwise.scala 48:55]
- wire [2:0] _T_338 = _T_332[1:0] + _T_336[1:0]; // @[Bitwise.scala 48:55]
- wire _f2validBits_2_T_19 = writebitsReg_2_addr == io_read_6_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_6_2 = writevalidReg[2] & _f2validBits_2_T_19; // @[VRegfile.scala 240:42]
- wire _f2validBits_1_T_19 = writebitsReg_1_addr == io_read_6_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_6_1 = writevalidReg[1] & _f2validBits_1_T_19; // @[VRegfile.scala 240:42]
- wire _f2validBits_0_T_19 = writebitsReg_0_addr == io_read_6_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_6_0 = writevalidReg[0] & _f2validBits_0_T_19; // @[VRegfile.scala 240:42]
- wire _f2validBits_5_T_19 = writebitsReg_5_addr == io_read_6_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_6_5 = writevalidReg[5] & _f2validBits_5_T_19; // @[VRegfile.scala 240:42]
- wire _f2validBits_4_T_19 = writebitsReg_4_addr == io_read_6_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_6_4 = writevalidReg[4] & _f2validBits_4_T_19; // @[VRegfile.scala 240:42]
- wire _f2validBits_3_T_19 = writebitsReg_3_addr == io_read_6_addr; // @[VRegfile.scala 241:46]
- wire f2validBits_6_3 = writevalidReg[3] & _f2validBits_3_T_19; // @[VRegfile.scala 240:42]
- wire [5:0] f2valid_6 = {f2validBits_6_5,f2validBits_6_4,f2validBits_6_3,f2validBits_6_2,f2validBits_6_1,
- f2validBits_6_0}; // @[VRegfile.scala 231:31]
- wire [1:0] _T_350 = f2valid_6[1] + f2valid_6[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_52 = {{1'd0}, f2valid_6[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_352 = _GEN_52 + _T_350; // @[Bitwise.scala 48:55]
- wire [1:0] _T_354 = f2valid_6[4] + f2valid_6[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_53 = {{1'd0}, f2valid_6[3]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_356 = _GEN_53 + _T_354; // @[Bitwise.scala 48:55]
- wire [2:0] _T_358 = _T_352[1:0] + _T_356[1:0]; // @[Bitwise.scala 48:55]
- wire [255:0] f1dataBits_6_0 = f1valid_6[0] ? io_write_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1dataBits_6_1 = f1valid_6[1] ? io_write_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_31 = f1dataBits_6_0 | f1dataBits_6_1; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_6_2 = f1valid_6[2] ? io_write_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_32 = _f1data_T_31 | f1dataBits_6_2; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_6_3 = f1valid_6[3] ? io_write_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_33 = _f1data_T_32 | f1dataBits_6_3; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_6_4 = f1valid_6[4] ? io_write_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f1data_T_34 = _f1data_T_33 | f1dataBits_6_4; // @[Library.scala 76:39]
- wire [255:0] f1dataBits_6_5 = f1valid_6[5] ? io_write_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f1data_6 = _f1data_T_34 | f1dataBits_6_5; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_6_0 = f2valid_6[0] ? writebitsReg_0_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2dataBits_6_1 = f2valid_6[1] ? writebitsReg_1_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_31 = f2dataBits_6_0 | f2dataBits_6_1; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_6_2 = f2valid_6[2] ? writebitsReg_2_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_32 = _f2data_T_31 | f2dataBits_6_2; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_6_3 = f2valid_6[3] ? writebitsReg_3_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_33 = _f2data_T_32 | f2dataBits_6_3; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_6_4 = f2valid_6[4] ? writebitsReg_4_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _f2data_T_34 = _f2data_T_33 | f2dataBits_6_4; // @[Library.scala 76:39]
- wire [255:0] f2dataBits_6_5 = f2valid_6[5] ? writebitsReg_5_data : 256'h0; // @[Library.scala 22:8]
- wire [255:0] f2data_6 = _f2data_T_34 | f2dataBits_6_5; // @[Library.scala 76:39]
- wire _sel_T_79 = f1valid_6 != 6'h0; // @[VRegfile.scala 261:43]
- wire _sel_T_82 = f1valid_6 == 6'h0; // @[VRegfile.scala 262:43]
- wire _sel_T_85 = f1valid_6 == 6'h0 & f2valid_6 != 6'h0; // @[VRegfile.scala 262:51]
- wire _sel_T_90 = _sel_T_82 & f2valid_6 == 6'h0; // @[VRegfile.scala 263:51]
- wire [3:0] sel_6 = {1'h0,_sel_T_79,_sel_T_85,_sel_T_90}; // @[Cat.scala 31:58]
- wire [1:0] _T_368 = sel_6[0] + sel_6[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_370 = sel_6[2] + sel_6[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_372 = _T_368 + _T_370; // @[Bitwise.scala 48:55]
- wire [255:0] _data_T_69 = sel_6[2] ? f1data_6 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_72 = sel_6[1] ? f2data_6 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] _data_T_73 = _data_T_69 | _data_T_72; // @[VRegfile.scala 267:38]
- wire [31:0] rdata_6_1 = vreg_1_io_read_6_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_6_0 = vreg_0_io_read_6_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_6_3 = vreg_3_io_read_6_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_6_2 = vreg_2_io_read_6_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_6_5 = vreg_5_io_read_6_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_6_4 = vreg_4_io_read_6_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_6_7 = vreg_7_io_read_6_data; // @[VRegfile.scala 215:19 220:19]
- wire [31:0] rdata_6_6 = vreg_6_io_read_6_data; // @[VRegfile.scala 215:19 220:19]
- wire [255:0] _data_T_75 = {rdata_6_7,rdata_6_6,rdata_6_5,rdata_6_4,rdata_6_3,rdata_6_2,rdata_6_1,rdata_6_0}; // @[VRegfile.scala 269:39]
- wire [255:0] _data_T_76 = sel_6[0] ? _data_T_75 : 256'h0; // @[Library.scala 22:8]
- wire [255:0] data_6 = _data_T_73 | _data_T_76; // @[VRegfile.scala 268:38]
- reg convConv; // @[VRegfile.scala 290:25]
- reg convInit; // @[VRegfile.scala 291:25]
- reg convTran; // @[VRegfile.scala 292:25]
- reg convClear; // @[VRegfile.scala 293:26]
- reg [2:0] convIndex; // @[VRegfile.scala 294:22]
- reg [8:0] convAbias; // @[VRegfile.scala 295:22]
- reg [8:0] convBbias; // @[VRegfile.scala 296:22]
- reg convAsign; // @[VRegfile.scala 297:22]
- reg convBsign; // @[VRegfile.scala 298:22]
- reg [255:0] internalData; // @[VRegfile.scala 299:25]
- wire _convConv_T = io_conv_valid & io_conv_ready; // @[VRegfile.scala 303:30]
- wire _convConv_T_1 = io_conv_valid & io_conv_ready & io_conv_op_conv; // @[VRegfile.scala 303:47]
- wire _convClear_T_1 = _convConv_T & io_conv_op_wclr; // @[VRegfile.scala 306:47]
- wire [3:0] _T_380 = {io_conv_op_conv,io_conv_op_wclr,io_conv_op_init,io_conv_op_tran}; // @[Cat.scala 31:58]
- wire [1:0] _T_385 = _T_380[0] + _T_380[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_387 = _T_380[2] + _T_380[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_389 = _T_385 + _T_387; // @[Bitwise.scala 48:55]
- wire _T_391 = _T_389 == 3'h1; // @[VRegfile.scala 310:92]
- wire [31:0] idata_1 = vreg_1_io_internal_data; // @[VRegfile.scala 312:19 314:14]
- wire [31:0] idata_0 = vreg_0_io_internal_data; // @[VRegfile.scala 312:19 314:14]
- wire [31:0] idata_3 = vreg_3_io_internal_data; // @[VRegfile.scala 312:19 314:14]
- wire [31:0] idata_2 = vreg_2_io_internal_data; // @[VRegfile.scala 312:19 314:14]
- wire [31:0] idata_5 = vreg_5_io_internal_data; // @[VRegfile.scala 312:19 314:14]
- wire [31:0] idata_4 = vreg_4_io_internal_data; // @[VRegfile.scala 312:19 314:14]
- wire [31:0] idata_7 = vreg_7_io_internal_data; // @[VRegfile.scala 312:19 314:14]
- wire [31:0] idata_6 = vreg_6_io_internal_data; // @[VRegfile.scala 312:19 314:14]
- wire [255:0] _internalData_T = {idata_7,idata_6,idata_5,idata_4,idata_3,idata_2,idata_1,idata_0}; // @[VRegfile.scala 322:27]
- wire [63:0] _T_436 = writeCurr >> io_conv_addr2; // @[VRegfile.scala 353:34]
- wire [63:0] _T_443 = writePrev >> io_conv_addr2; // @[VRegfile.scala 354:34]
- wire [78:0] _GEN_54 = {{15'd0}, writeCurr}; // @[VRegfile.scala 357:37]
- wire [78:0] _T_450 = _GEN_54 & 79'hffff000000000000; // @[VRegfile.scala 357:37]
- wire [78:0] _GEN_55 = {{15'd0}, writePrev}; // @[VRegfile.scala 358:37]
- wire [78:0] _T_457 = _GEN_55 & 79'hffff000000000000; // @[VRegfile.scala 358:37]
- reg [255:0] transposeData; // @[VRegfile.scala 382:26]
- wire [2:0] index = io_conv_valid ? io_conv_index : 3'h0; // @[VRegfile.scala 391:20]
- wire [255:0] transposeDataMux_0 = vreg_0_io_transpose_data; // @[VRegfile.scala 383:30 387:25]
- wire [255:0] transposeData_value__0 = 3'h0 == index ? transposeDataMux_0 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] transposeDataMux_1 = vreg_1_io_transpose_data; // @[VRegfile.scala 383:30 387:25]
- wire [255:0] transposeData_value__1 = 3'h1 == index ? transposeDataMux_1 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] transposeDataMux_2 = vreg_2_io_transpose_data; // @[VRegfile.scala 383:30 387:25]
- wire [255:0] transposeData_value__2 = 3'h2 == index ? transposeDataMux_2 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] transposeDataMux_3 = vreg_3_io_transpose_data; // @[VRegfile.scala 383:30 387:25]
- wire [255:0] transposeData_value__3 = 3'h3 == index ? transposeDataMux_3 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] transposeDataMux_4 = vreg_4_io_transpose_data; // @[VRegfile.scala 383:30 387:25]
- wire [255:0] transposeData_value__4 = 3'h4 == index ? transposeDataMux_4 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] transposeDataMux_5 = vreg_5_io_transpose_data; // @[VRegfile.scala 383:30 387:25]
- wire [255:0] transposeData_value__5 = 3'h5 == index ? transposeDataMux_5 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] transposeDataMux_6 = vreg_6_io_transpose_data; // @[VRegfile.scala 383:30 387:25]
- wire [255:0] transposeData_value__6 = 3'h6 == index ? transposeDataMux_6 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] transposeDataMux_7 = vreg_7_io_transpose_data; // @[VRegfile.scala 383:30 387:25]
- wire [255:0] transposeData_value__7 = 3'h7 == index ? transposeDataMux_7 : 256'h0; // @[Library.scala 115:22]
- wire [255:0] transposeData_value_1_0 = transposeData_value__0 | transposeData_value__1; // @[Library.scala 129:37]
- wire [255:0] transposeData_value_1_1 = transposeData_value__2 | transposeData_value__3; // @[Library.scala 129:37]
- wire [255:0] transposeData_value_1_2 = transposeData_value__4 | transposeData_value__5; // @[Library.scala 129:37]
- wire [255:0] transposeData_value_1_3 = transposeData_value__6 | transposeData_value__7; // @[Library.scala 129:37]
- wire [255:0] transposeData_value_2_0 = transposeData_value_1_0 | transposeData_value_1_1; // @[Library.scala 129:37]
- wire [255:0] transposeData_value_2_1 = transposeData_value_1_2 | transposeData_value_1_3; // @[Library.scala 129:37]
- wire [255:0] transposeData_value_3_0 = transposeData_value_2_0 | transposeData_value_2_1; // @[Library.scala 129:37]
- reg [127:0] vrfsb; // @[VRegfile.scala 431:22]
- wire [127:0] vrfsbSet = io_vrfsb_set_valid ? io_vrfsb_set_bits : 128'h0; // @[Library.scala 22:8]
- wire [63:0] _hoh_T = 64'h1 << io_whint_0_addr; // @[OneHot.scala 64:12]
- wire [63:0] hoh = io_whint_0_valid ? _hoh_T : 64'h0; // @[Library.scala 22:8]
- wire [63:0] whoh = writeSet_0 | hoh; // @[VRegfile.scala 414:22]
- wire [127:0] whdata = {whoh,whoh}; // @[Cat.scala 31:58]
- wire [63:0] _hoh_T_2 = 64'h1 << io_whint_1_addr; // @[OneHot.scala 64:12]
- wire [63:0] hoh_1 = io_whint_1_valid ? _hoh_T_2 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] whoh_1 = writeSet_1 | hoh_1; // @[VRegfile.scala 414:22]
- wire [127:0] whdata_1 = {whoh_1,whoh_1}; // @[Cat.scala 31:58]
- wire [127:0] _T_672 = whdata | whdata_1; // @[VRegfile.scala 417:45]
- wire [63:0] _hoh_T_4 = 64'h1 << io_whint_2_addr; // @[OneHot.scala 64:12]
- wire [63:0] hoh_2 = io_whint_2_valid ? _hoh_T_4 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] whoh_2 = writeSet_2 | hoh_2; // @[VRegfile.scala 414:22]
- wire [127:0] whdata_2 = {whoh_2,whoh_2}; // @[Cat.scala 31:58]
- wire [127:0] _T_675 = _T_672 | whdata_2; // @[VRegfile.scala 417:45]
- wire [63:0] _hoh_T_6 = 64'h1 << io_whint_3_addr; // @[OneHot.scala 64:12]
- wire [63:0] hoh_3 = io_whint_3_valid ? _hoh_T_6 : 64'h0; // @[Library.scala 22:8]
- wire [63:0] whoh_3 = writeSet_3 | hoh_3; // @[VRegfile.scala 414:22]
- wire [127:0] whdata_3 = {whoh_3,whoh_3}; // @[Cat.scala 31:58]
- wire [127:0] _T_678 = _T_675 | whdata_3; // @[VRegfile.scala 417:45]
- wire [127:0] whdata_4 = {writeSet_4,writeSet_4}; // @[Cat.scala 31:58]
- wire [127:0] _T_681 = _T_678 | whdata_4; // @[VRegfile.scala 417:45]
- wire [127:0] whdata_5 = {writeSet_5,writeSet_5}; // @[Cat.scala 31:58]
- wire _T_682 = io_write_0_valid | io_whint_0_valid | io_write_1_valid | io_whint_1_valid | io_write_2_valid |
- io_whint_2_valid | io_write_3_valid | io_whint_3_valid | io_write_4_valid | io_write_5_valid; // @[VRegfile.scala 417:19]
- wire [127:0] _T_684 = _T_681 | whdata_5; // @[VRegfile.scala 417:45]
- wire [127:0] cdata = convClear ? 128'hff00000000000000ff000000000000 : 128'h0; // @[Library.scala 22:8]
- wire vrfsbClrEn = _T_682 | convClear; // @[VRegfile.scala 427:14]
- wire [127:0] vrfsbClr = _T_684 | cdata; // @[VRegfile.scala 427:30]
- wire [127:0] _vrfsb_T = ~vrfsbClr; // @[VRegfile.scala 437:23]
- wire [127:0] _vrfsb_T_1 = vrfsb & _vrfsb_T; // @[VRegfile.scala 437:21]
- wire [127:0] _vrfsb_T_2 = _vrfsb_T_1 | vrfsbSet; // @[VRegfile.scala 437:34]
- VRegfileSegment vreg_0 ( // @[VRegfile.scala 135:11]
- .clock(vreg_0_clock),
- .reset(vreg_0_reset),
- .io_read_0_addr(vreg_0_io_read_0_addr),
- .io_read_0_data(vreg_0_io_read_0_data),
- .io_read_1_addr(vreg_0_io_read_1_addr),
- .io_read_1_data(vreg_0_io_read_1_data),
- .io_read_2_addr(vreg_0_io_read_2_addr),
- .io_read_2_data(vreg_0_io_read_2_data),
- .io_read_3_addr(vreg_0_io_read_3_addr),
- .io_read_3_data(vreg_0_io_read_3_data),
- .io_read_4_addr(vreg_0_io_read_4_addr),
- .io_read_4_data(vreg_0_io_read_4_data),
- .io_read_5_addr(vreg_0_io_read_5_addr),
- .io_read_5_data(vreg_0_io_read_5_data),
- .io_read_6_addr(vreg_0_io_read_6_addr),
- .io_read_6_data(vreg_0_io_read_6_data),
- .io_transpose_addr(vreg_0_io_transpose_addr),
- .io_transpose_data(vreg_0_io_transpose_data),
- .io_internal_addr(vreg_0_io_internal_addr),
- .io_internal_data(vreg_0_io_internal_data),
- .io_write_0_valid(vreg_0_io_write_0_valid),
- .io_write_0_addr(vreg_0_io_write_0_addr),
- .io_write_0_data(vreg_0_io_write_0_data),
- .io_write_1_valid(vreg_0_io_write_1_valid),
- .io_write_1_addr(vreg_0_io_write_1_addr),
- .io_write_1_data(vreg_0_io_write_1_data),
- .io_write_2_valid(vreg_0_io_write_2_valid),
- .io_write_2_addr(vreg_0_io_write_2_addr),
- .io_write_2_data(vreg_0_io_write_2_data),
- .io_write_3_valid(vreg_0_io_write_3_valid),
- .io_write_3_addr(vreg_0_io_write_3_addr),
- .io_write_3_data(vreg_0_io_write_3_data),
- .io_write_4_valid(vreg_0_io_write_4_valid),
- .io_write_4_addr(vreg_0_io_write_4_addr),
- .io_write_4_data(vreg_0_io_write_4_data),
- .io_write_5_valid(vreg_0_io_write_5_valid),
- .io_write_5_addr(vreg_0_io_write_5_addr),
- .io_write_5_data(vreg_0_io_write_5_data),
- .io_conv_valid(vreg_0_io_conv_valid),
- .io_conv_data_0(vreg_0_io_conv_data_0),
- .io_conv_data_1(vreg_0_io_conv_data_1),
- .io_conv_data_2(vreg_0_io_conv_data_2),
- .io_conv_data_3(vreg_0_io_conv_data_3),
- .io_conv_data_4(vreg_0_io_conv_data_4),
- .io_conv_data_5(vreg_0_io_conv_data_5),
- .io_conv_data_6(vreg_0_io_conv_data_6),
- .io_conv_data_7(vreg_0_io_conv_data_7)
- );
- VRegfileSegment vreg_1 ( // @[VRegfile.scala 135:11]
- .clock(vreg_1_clock),
- .reset(vreg_1_reset),
- .io_read_0_addr(vreg_1_io_read_0_addr),
- .io_read_0_data(vreg_1_io_read_0_data),
- .io_read_1_addr(vreg_1_io_read_1_addr),
- .io_read_1_data(vreg_1_io_read_1_data),
- .io_read_2_addr(vreg_1_io_read_2_addr),
- .io_read_2_data(vreg_1_io_read_2_data),
- .io_read_3_addr(vreg_1_io_read_3_addr),
- .io_read_3_data(vreg_1_io_read_3_data),
- .io_read_4_addr(vreg_1_io_read_4_addr),
- .io_read_4_data(vreg_1_io_read_4_data),
- .io_read_5_addr(vreg_1_io_read_5_addr),
- .io_read_5_data(vreg_1_io_read_5_data),
- .io_read_6_addr(vreg_1_io_read_6_addr),
- .io_read_6_data(vreg_1_io_read_6_data),
- .io_transpose_addr(vreg_1_io_transpose_addr),
- .io_transpose_data(vreg_1_io_transpose_data),
- .io_internal_addr(vreg_1_io_internal_addr),
- .io_internal_data(vreg_1_io_internal_data),
- .io_write_0_valid(vreg_1_io_write_0_valid),
- .io_write_0_addr(vreg_1_io_write_0_addr),
- .io_write_0_data(vreg_1_io_write_0_data),
- .io_write_1_valid(vreg_1_io_write_1_valid),
- .io_write_1_addr(vreg_1_io_write_1_addr),
- .io_write_1_data(vreg_1_io_write_1_data),
- .io_write_2_valid(vreg_1_io_write_2_valid),
- .io_write_2_addr(vreg_1_io_write_2_addr),
- .io_write_2_data(vreg_1_io_write_2_data),
- .io_write_3_valid(vreg_1_io_write_3_valid),
- .io_write_3_addr(vreg_1_io_write_3_addr),
- .io_write_3_data(vreg_1_io_write_3_data),
- .io_write_4_valid(vreg_1_io_write_4_valid),
- .io_write_4_addr(vreg_1_io_write_4_addr),
- .io_write_4_data(vreg_1_io_write_4_data),
- .io_write_5_valid(vreg_1_io_write_5_valid),
- .io_write_5_addr(vreg_1_io_write_5_addr),
- .io_write_5_data(vreg_1_io_write_5_data),
- .io_conv_valid(vreg_1_io_conv_valid),
- .io_conv_data_0(vreg_1_io_conv_data_0),
- .io_conv_data_1(vreg_1_io_conv_data_1),
- .io_conv_data_2(vreg_1_io_conv_data_2),
- .io_conv_data_3(vreg_1_io_conv_data_3),
- .io_conv_data_4(vreg_1_io_conv_data_4),
- .io_conv_data_5(vreg_1_io_conv_data_5),
- .io_conv_data_6(vreg_1_io_conv_data_6),
- .io_conv_data_7(vreg_1_io_conv_data_7)
- );
- VRegfileSegment vreg_2 ( // @[VRegfile.scala 135:11]
- .clock(vreg_2_clock),
- .reset(vreg_2_reset),
- .io_read_0_addr(vreg_2_io_read_0_addr),
- .io_read_0_data(vreg_2_io_read_0_data),
- .io_read_1_addr(vreg_2_io_read_1_addr),
- .io_read_1_data(vreg_2_io_read_1_data),
- .io_read_2_addr(vreg_2_io_read_2_addr),
- .io_read_2_data(vreg_2_io_read_2_data),
- .io_read_3_addr(vreg_2_io_read_3_addr),
- .io_read_3_data(vreg_2_io_read_3_data),
- .io_read_4_addr(vreg_2_io_read_4_addr),
- .io_read_4_data(vreg_2_io_read_4_data),
- .io_read_5_addr(vreg_2_io_read_5_addr),
- .io_read_5_data(vreg_2_io_read_5_data),
- .io_read_6_addr(vreg_2_io_read_6_addr),
- .io_read_6_data(vreg_2_io_read_6_data),
- .io_transpose_addr(vreg_2_io_transpose_addr),
- .io_transpose_data(vreg_2_io_transpose_data),
- .io_internal_addr(vreg_2_io_internal_addr),
- .io_internal_data(vreg_2_io_internal_data),
- .io_write_0_valid(vreg_2_io_write_0_valid),
- .io_write_0_addr(vreg_2_io_write_0_addr),
- .io_write_0_data(vreg_2_io_write_0_data),
- .io_write_1_valid(vreg_2_io_write_1_valid),
- .io_write_1_addr(vreg_2_io_write_1_addr),
- .io_write_1_data(vreg_2_io_write_1_data),
- .io_write_2_valid(vreg_2_io_write_2_valid),
- .io_write_2_addr(vreg_2_io_write_2_addr),
- .io_write_2_data(vreg_2_io_write_2_data),
- .io_write_3_valid(vreg_2_io_write_3_valid),
- .io_write_3_addr(vreg_2_io_write_3_addr),
- .io_write_3_data(vreg_2_io_write_3_data),
- .io_write_4_valid(vreg_2_io_write_4_valid),
- .io_write_4_addr(vreg_2_io_write_4_addr),
- .io_write_4_data(vreg_2_io_write_4_data),
- .io_write_5_valid(vreg_2_io_write_5_valid),
- .io_write_5_addr(vreg_2_io_write_5_addr),
- .io_write_5_data(vreg_2_io_write_5_data),
- .io_conv_valid(vreg_2_io_conv_valid),
- .io_conv_data_0(vreg_2_io_conv_data_0),
- .io_conv_data_1(vreg_2_io_conv_data_1),
- .io_conv_data_2(vreg_2_io_conv_data_2),
- .io_conv_data_3(vreg_2_io_conv_data_3),
- .io_conv_data_4(vreg_2_io_conv_data_4),
- .io_conv_data_5(vreg_2_io_conv_data_5),
- .io_conv_data_6(vreg_2_io_conv_data_6),
- .io_conv_data_7(vreg_2_io_conv_data_7)
- );
- VRegfileSegment vreg_3 ( // @[VRegfile.scala 135:11]
- .clock(vreg_3_clock),
- .reset(vreg_3_reset),
- .io_read_0_addr(vreg_3_io_read_0_addr),
- .io_read_0_data(vreg_3_io_read_0_data),
- .io_read_1_addr(vreg_3_io_read_1_addr),
- .io_read_1_data(vreg_3_io_read_1_data),
- .io_read_2_addr(vreg_3_io_read_2_addr),
- .io_read_2_data(vreg_3_io_read_2_data),
- .io_read_3_addr(vreg_3_io_read_3_addr),
- .io_read_3_data(vreg_3_io_read_3_data),
- .io_read_4_addr(vreg_3_io_read_4_addr),
- .io_read_4_data(vreg_3_io_read_4_data),
- .io_read_5_addr(vreg_3_io_read_5_addr),
- .io_read_5_data(vreg_3_io_read_5_data),
- .io_read_6_addr(vreg_3_io_read_6_addr),
- .io_read_6_data(vreg_3_io_read_6_data),
- .io_transpose_addr(vreg_3_io_transpose_addr),
- .io_transpose_data(vreg_3_io_transpose_data),
- .io_internal_addr(vreg_3_io_internal_addr),
- .io_internal_data(vreg_3_io_internal_data),
- .io_write_0_valid(vreg_3_io_write_0_valid),
- .io_write_0_addr(vreg_3_io_write_0_addr),
- .io_write_0_data(vreg_3_io_write_0_data),
- .io_write_1_valid(vreg_3_io_write_1_valid),
- .io_write_1_addr(vreg_3_io_write_1_addr),
- .io_write_1_data(vreg_3_io_write_1_data),
- .io_write_2_valid(vreg_3_io_write_2_valid),
- .io_write_2_addr(vreg_3_io_write_2_addr),
- .io_write_2_data(vreg_3_io_write_2_data),
- .io_write_3_valid(vreg_3_io_write_3_valid),
- .io_write_3_addr(vreg_3_io_write_3_addr),
- .io_write_3_data(vreg_3_io_write_3_data),
- .io_write_4_valid(vreg_3_io_write_4_valid),
- .io_write_4_addr(vreg_3_io_write_4_addr),
- .io_write_4_data(vreg_3_io_write_4_data),
- .io_write_5_valid(vreg_3_io_write_5_valid),
- .io_write_5_addr(vreg_3_io_write_5_addr),
- .io_write_5_data(vreg_3_io_write_5_data),
- .io_conv_valid(vreg_3_io_conv_valid),
- .io_conv_data_0(vreg_3_io_conv_data_0),
- .io_conv_data_1(vreg_3_io_conv_data_1),
- .io_conv_data_2(vreg_3_io_conv_data_2),
- .io_conv_data_3(vreg_3_io_conv_data_3),
- .io_conv_data_4(vreg_3_io_conv_data_4),
- .io_conv_data_5(vreg_3_io_conv_data_5),
- .io_conv_data_6(vreg_3_io_conv_data_6),
- .io_conv_data_7(vreg_3_io_conv_data_7)
- );
- VRegfileSegment vreg_4 ( // @[VRegfile.scala 135:11]
- .clock(vreg_4_clock),
- .reset(vreg_4_reset),
- .io_read_0_addr(vreg_4_io_read_0_addr),
- .io_read_0_data(vreg_4_io_read_0_data),
- .io_read_1_addr(vreg_4_io_read_1_addr),
- .io_read_1_data(vreg_4_io_read_1_data),
- .io_read_2_addr(vreg_4_io_read_2_addr),
- .io_read_2_data(vreg_4_io_read_2_data),
- .io_read_3_addr(vreg_4_io_read_3_addr),
- .io_read_3_data(vreg_4_io_read_3_data),
- .io_read_4_addr(vreg_4_io_read_4_addr),
- .io_read_4_data(vreg_4_io_read_4_data),
- .io_read_5_addr(vreg_4_io_read_5_addr),
- .io_read_5_data(vreg_4_io_read_5_data),
- .io_read_6_addr(vreg_4_io_read_6_addr),
- .io_read_6_data(vreg_4_io_read_6_data),
- .io_transpose_addr(vreg_4_io_transpose_addr),
- .io_transpose_data(vreg_4_io_transpose_data),
- .io_internal_addr(vreg_4_io_internal_addr),
- .io_internal_data(vreg_4_io_internal_data),
- .io_write_0_valid(vreg_4_io_write_0_valid),
- .io_write_0_addr(vreg_4_io_write_0_addr),
- .io_write_0_data(vreg_4_io_write_0_data),
- .io_write_1_valid(vreg_4_io_write_1_valid),
- .io_write_1_addr(vreg_4_io_write_1_addr),
- .io_write_1_data(vreg_4_io_write_1_data),
- .io_write_2_valid(vreg_4_io_write_2_valid),
- .io_write_2_addr(vreg_4_io_write_2_addr),
- .io_write_2_data(vreg_4_io_write_2_data),
- .io_write_3_valid(vreg_4_io_write_3_valid),
- .io_write_3_addr(vreg_4_io_write_3_addr),
- .io_write_3_data(vreg_4_io_write_3_data),
- .io_write_4_valid(vreg_4_io_write_4_valid),
- .io_write_4_addr(vreg_4_io_write_4_addr),
- .io_write_4_data(vreg_4_io_write_4_data),
- .io_write_5_valid(vreg_4_io_write_5_valid),
- .io_write_5_addr(vreg_4_io_write_5_addr),
- .io_write_5_data(vreg_4_io_write_5_data),
- .io_conv_valid(vreg_4_io_conv_valid),
- .io_conv_data_0(vreg_4_io_conv_data_0),
- .io_conv_data_1(vreg_4_io_conv_data_1),
- .io_conv_data_2(vreg_4_io_conv_data_2),
- .io_conv_data_3(vreg_4_io_conv_data_3),
- .io_conv_data_4(vreg_4_io_conv_data_4),
- .io_conv_data_5(vreg_4_io_conv_data_5),
- .io_conv_data_6(vreg_4_io_conv_data_6),
- .io_conv_data_7(vreg_4_io_conv_data_7)
- );
- VRegfileSegment vreg_5 ( // @[VRegfile.scala 135:11]
- .clock(vreg_5_clock),
- .reset(vreg_5_reset),
- .io_read_0_addr(vreg_5_io_read_0_addr),
- .io_read_0_data(vreg_5_io_read_0_data),
- .io_read_1_addr(vreg_5_io_read_1_addr),
- .io_read_1_data(vreg_5_io_read_1_data),
- .io_read_2_addr(vreg_5_io_read_2_addr),
- .io_read_2_data(vreg_5_io_read_2_data),
- .io_read_3_addr(vreg_5_io_read_3_addr),
- .io_read_3_data(vreg_5_io_read_3_data),
- .io_read_4_addr(vreg_5_io_read_4_addr),
- .io_read_4_data(vreg_5_io_read_4_data),
- .io_read_5_addr(vreg_5_io_read_5_addr),
- .io_read_5_data(vreg_5_io_read_5_data),
- .io_read_6_addr(vreg_5_io_read_6_addr),
- .io_read_6_data(vreg_5_io_read_6_data),
- .io_transpose_addr(vreg_5_io_transpose_addr),
- .io_transpose_data(vreg_5_io_transpose_data),
- .io_internal_addr(vreg_5_io_internal_addr),
- .io_internal_data(vreg_5_io_internal_data),
- .io_write_0_valid(vreg_5_io_write_0_valid),
- .io_write_0_addr(vreg_5_io_write_0_addr),
- .io_write_0_data(vreg_5_io_write_0_data),
- .io_write_1_valid(vreg_5_io_write_1_valid),
- .io_write_1_addr(vreg_5_io_write_1_addr),
- .io_write_1_data(vreg_5_io_write_1_data),
- .io_write_2_valid(vreg_5_io_write_2_valid),
- .io_write_2_addr(vreg_5_io_write_2_addr),
- .io_write_2_data(vreg_5_io_write_2_data),
- .io_write_3_valid(vreg_5_io_write_3_valid),
- .io_write_3_addr(vreg_5_io_write_3_addr),
- .io_write_3_data(vreg_5_io_write_3_data),
- .io_write_4_valid(vreg_5_io_write_4_valid),
- .io_write_4_addr(vreg_5_io_write_4_addr),
- .io_write_4_data(vreg_5_io_write_4_data),
- .io_write_5_valid(vreg_5_io_write_5_valid),
- .io_write_5_addr(vreg_5_io_write_5_addr),
- .io_write_5_data(vreg_5_io_write_5_data),
- .io_conv_valid(vreg_5_io_conv_valid),
- .io_conv_data_0(vreg_5_io_conv_data_0),
- .io_conv_data_1(vreg_5_io_conv_data_1),
- .io_conv_data_2(vreg_5_io_conv_data_2),
- .io_conv_data_3(vreg_5_io_conv_data_3),
- .io_conv_data_4(vreg_5_io_conv_data_4),
- .io_conv_data_5(vreg_5_io_conv_data_5),
- .io_conv_data_6(vreg_5_io_conv_data_6),
- .io_conv_data_7(vreg_5_io_conv_data_7)
- );
- VRegfileSegment vreg_6 ( // @[VRegfile.scala 135:11]
- .clock(vreg_6_clock),
- .reset(vreg_6_reset),
- .io_read_0_addr(vreg_6_io_read_0_addr),
- .io_read_0_data(vreg_6_io_read_0_data),
- .io_read_1_addr(vreg_6_io_read_1_addr),
- .io_read_1_data(vreg_6_io_read_1_data),
- .io_read_2_addr(vreg_6_io_read_2_addr),
- .io_read_2_data(vreg_6_io_read_2_data),
- .io_read_3_addr(vreg_6_io_read_3_addr),
- .io_read_3_data(vreg_6_io_read_3_data),
- .io_read_4_addr(vreg_6_io_read_4_addr),
- .io_read_4_data(vreg_6_io_read_4_data),
- .io_read_5_addr(vreg_6_io_read_5_addr),
- .io_read_5_data(vreg_6_io_read_5_data),
- .io_read_6_addr(vreg_6_io_read_6_addr),
- .io_read_6_data(vreg_6_io_read_6_data),
- .io_transpose_addr(vreg_6_io_transpose_addr),
- .io_transpose_data(vreg_6_io_transpose_data),
- .io_internal_addr(vreg_6_io_internal_addr),
- .io_internal_data(vreg_6_io_internal_data),
- .io_write_0_valid(vreg_6_io_write_0_valid),
- .io_write_0_addr(vreg_6_io_write_0_addr),
- .io_write_0_data(vreg_6_io_write_0_data),
- .io_write_1_valid(vreg_6_io_write_1_valid),
- .io_write_1_addr(vreg_6_io_write_1_addr),
- .io_write_1_data(vreg_6_io_write_1_data),
- .io_write_2_valid(vreg_6_io_write_2_valid),
- .io_write_2_addr(vreg_6_io_write_2_addr),
- .io_write_2_data(vreg_6_io_write_2_data),
- .io_write_3_valid(vreg_6_io_write_3_valid),
- .io_write_3_addr(vreg_6_io_write_3_addr),
- .io_write_3_data(vreg_6_io_write_3_data),
- .io_write_4_valid(vreg_6_io_write_4_valid),
- .io_write_4_addr(vreg_6_io_write_4_addr),
- .io_write_4_data(vreg_6_io_write_4_data),
- .io_write_5_valid(vreg_6_io_write_5_valid),
- .io_write_5_addr(vreg_6_io_write_5_addr),
- .io_write_5_data(vreg_6_io_write_5_data),
- .io_conv_valid(vreg_6_io_conv_valid),
- .io_conv_data_0(vreg_6_io_conv_data_0),
- .io_conv_data_1(vreg_6_io_conv_data_1),
- .io_conv_data_2(vreg_6_io_conv_data_2),
- .io_conv_data_3(vreg_6_io_conv_data_3),
- .io_conv_data_4(vreg_6_io_conv_data_4),
- .io_conv_data_5(vreg_6_io_conv_data_5),
- .io_conv_data_6(vreg_6_io_conv_data_6),
- .io_conv_data_7(vreg_6_io_conv_data_7)
- );
- VRegfileSegment vreg_7 ( // @[VRegfile.scala 135:11]
- .clock(vreg_7_clock),
- .reset(vreg_7_reset),
- .io_read_0_addr(vreg_7_io_read_0_addr),
- .io_read_0_data(vreg_7_io_read_0_data),
- .io_read_1_addr(vreg_7_io_read_1_addr),
- .io_read_1_data(vreg_7_io_read_1_data),
- .io_read_2_addr(vreg_7_io_read_2_addr),
- .io_read_2_data(vreg_7_io_read_2_data),
- .io_read_3_addr(vreg_7_io_read_3_addr),
- .io_read_3_data(vreg_7_io_read_3_data),
- .io_read_4_addr(vreg_7_io_read_4_addr),
- .io_read_4_data(vreg_7_io_read_4_data),
- .io_read_5_addr(vreg_7_io_read_5_addr),
- .io_read_5_data(vreg_7_io_read_5_data),
- .io_read_6_addr(vreg_7_io_read_6_addr),
- .io_read_6_data(vreg_7_io_read_6_data),
- .io_transpose_addr(vreg_7_io_transpose_addr),
- .io_transpose_data(vreg_7_io_transpose_data),
- .io_internal_addr(vreg_7_io_internal_addr),
- .io_internal_data(vreg_7_io_internal_data),
- .io_write_0_valid(vreg_7_io_write_0_valid),
- .io_write_0_addr(vreg_7_io_write_0_addr),
- .io_write_0_data(vreg_7_io_write_0_data),
- .io_write_1_valid(vreg_7_io_write_1_valid),
- .io_write_1_addr(vreg_7_io_write_1_addr),
- .io_write_1_data(vreg_7_io_write_1_data),
- .io_write_2_valid(vreg_7_io_write_2_valid),
- .io_write_2_addr(vreg_7_io_write_2_addr),
- .io_write_2_data(vreg_7_io_write_2_data),
- .io_write_3_valid(vreg_7_io_write_3_valid),
- .io_write_3_addr(vreg_7_io_write_3_addr),
- .io_write_3_data(vreg_7_io_write_3_data),
- .io_write_4_valid(vreg_7_io_write_4_valid),
- .io_write_4_addr(vreg_7_io_write_4_addr),
- .io_write_4_data(vreg_7_io_write_4_data),
- .io_write_5_valid(vreg_7_io_write_5_valid),
- .io_write_5_addr(vreg_7_io_write_5_addr),
- .io_write_5_data(vreg_7_io_write_5_data),
- .io_conv_valid(vreg_7_io_conv_valid),
- .io_conv_data_0(vreg_7_io_conv_data_0),
- .io_conv_data_1(vreg_7_io_conv_data_1),
- .io_conv_data_2(vreg_7_io_conv_data_2),
- .io_conv_data_3(vreg_7_io_conv_data_3),
- .io_conv_data_4(vreg_7_io_conv_data_4),
- .io_conv_data_5(vreg_7_io_conv_data_5),
- .io_conv_data_6(vreg_7_io_conv_data_6),
- .io_conv_data_7(vreg_7_io_conv_data_7)
- );
- VConvAlu vconv ( // @[VConvAlu.scala 24:18]
- .clock(vconv_clock),
- .reset(vconv_reset),
- .io_op_conv(vconv_io_op_conv),
- .io_op_init(vconv_io_op_init),
- .io_op_tran(vconv_io_op_tran),
- .io_op_clear(vconv_io_op_clear),
- .io_index(vconv_io_index),
- .io_adata(vconv_io_adata),
- .io_bdata(vconv_io_bdata),
- .io_abias(vconv_io_abias),
- .io_bbias(vconv_io_bbias),
- .io_asign(vconv_io_asign),
- .io_bsign(vconv_io_bsign),
- .io_out_0(vconv_io_out_0),
- .io_out_1(vconv_io_out_1),
- .io_out_2(vconv_io_out_2),
- .io_out_3(vconv_io_out_3),
- .io_out_4(vconv_io_out_4),
- .io_out_5(vconv_io_out_5),
- .io_out_6(vconv_io_out_6),
- .io_out_7(vconv_io_out_7)
- );
- assign io_read_0_data = readData_0; // @[VRegfile.scala 285:21]
- assign io_read_1_data = readData_1; // @[VRegfile.scala 285:21]
- assign io_read_2_data = readData_2; // @[VRegfile.scala 285:21]
- assign io_read_3_data = readData_3; // @[VRegfile.scala 285:21]
- assign io_read_4_data = readData_4; // @[VRegfile.scala 285:21]
- assign io_read_5_data = readData_5; // @[VRegfile.scala 285:21]
- assign io_read_6_data = readData_6; // @[VRegfile.scala 285:21]
- assign io_transpose_data = transposeData; // @[VRegfile.scala 395:21]
- assign io_vrfsb_data = vrfsb; // @[VRegfile.scala 440:17]
- assign vreg_0_clock = clock;
- assign vreg_0_reset = reset;
- assign vreg_0_io_read_0_addr = io_read_0_addr; // @[VRegfile.scala 219:31]
- assign vreg_0_io_read_1_addr = io_read_1_addr; // @[VRegfile.scala 219:31]
- assign vreg_0_io_read_2_addr = io_read_2_addr; // @[VRegfile.scala 219:31]
- assign vreg_0_io_read_3_addr = io_read_3_addr; // @[VRegfile.scala 219:31]
- assign vreg_0_io_read_4_addr = io_read_4_addr; // @[VRegfile.scala 219:31]
- assign vreg_0_io_read_5_addr = io_read_5_addr; // @[VRegfile.scala 219:31]
- assign vreg_0_io_read_6_addr = io_read_6_addr; // @[VRegfile.scala 219:31]
- assign vreg_0_io_transpose_addr = io_conv_valid ? io_conv_addr1 : 6'h0; // @[VRegfile.scala 386:37]
- assign vreg_0_io_internal_addr = io_conv_addr2; // @[VRegfile.scala 318:30]
- assign vreg_0_io_write_0_valid = writevalidReg[0]; // @[VRegfile.scala 182:49]
- assign vreg_0_io_write_0_addr = writebitsReg_0_addr; // @[VRegfile.scala 183:32]
- assign vreg_0_io_write_0_data = writebitsReg_0_data[31:0]; // @[VRegfile.scala 184:55]
- assign vreg_0_io_write_1_valid = writevalidReg[1]; // @[VRegfile.scala 182:49]
- assign vreg_0_io_write_1_addr = writebitsReg_1_addr; // @[VRegfile.scala 183:32]
- assign vreg_0_io_write_1_data = writebitsReg_1_data[31:0]; // @[VRegfile.scala 184:55]
- assign vreg_0_io_write_2_valid = writevalidReg[2]; // @[VRegfile.scala 182:49]
- assign vreg_0_io_write_2_addr = writebitsReg_2_addr; // @[VRegfile.scala 183:32]
- assign vreg_0_io_write_2_data = writebitsReg_2_data[31:0]; // @[VRegfile.scala 184:55]
- assign vreg_0_io_write_3_valid = writevalidReg[3]; // @[VRegfile.scala 182:49]
- assign vreg_0_io_write_3_addr = writebitsReg_3_addr; // @[VRegfile.scala 183:32]
- assign vreg_0_io_write_3_data = writebitsReg_3_data[31:0]; // @[VRegfile.scala 184:55]
- assign vreg_0_io_write_4_valid = writevalidReg[4]; // @[VRegfile.scala 182:49]
- assign vreg_0_io_write_4_addr = writebitsReg_4_addr; // @[VRegfile.scala 183:32]
- assign vreg_0_io_write_4_data = writebitsReg_4_data[31:0]; // @[VRegfile.scala 184:55]
- assign vreg_0_io_write_5_valid = writevalidReg[5]; // @[VRegfile.scala 182:49]
- assign vreg_0_io_write_5_addr = writebitsReg_5_addr; // @[VRegfile.scala 183:32]
- assign vreg_0_io_write_5_data = writebitsReg_5_data[31:0]; // @[VRegfile.scala 184:55]
- assign vreg_0_io_conv_valid = convClear; // @[VRegfile.scala 333:27]
- assign vreg_0_io_conv_data_0 = vconv_io_out_0[31:0]; // @[VRegfile.scala 335:49]
- assign vreg_0_io_conv_data_1 = vconv_io_out_1[31:0]; // @[VRegfile.scala 335:49]
- assign vreg_0_io_conv_data_2 = vconv_io_out_2[31:0]; // @[VRegfile.scala 335:49]
- assign vreg_0_io_conv_data_3 = vconv_io_out_3[31:0]; // @[VRegfile.scala 335:49]
- assign vreg_0_io_conv_data_4 = vconv_io_out_4[31:0]; // @[VRegfile.scala 335:49]
- assign vreg_0_io_conv_data_5 = vconv_io_out_5[31:0]; // @[VRegfile.scala 335:49]
- assign vreg_0_io_conv_data_6 = vconv_io_out_6[31:0]; // @[VRegfile.scala 335:49]
- assign vreg_0_io_conv_data_7 = vconv_io_out_7[31:0]; // @[VRegfile.scala 335:49]
- assign vreg_1_clock = clock;
- assign vreg_1_reset = reset;
- assign vreg_1_io_read_0_addr = io_read_0_addr; // @[VRegfile.scala 219:31]
- assign vreg_1_io_read_1_addr = io_read_1_addr; // @[VRegfile.scala 219:31]
- assign vreg_1_io_read_2_addr = io_read_2_addr; // @[VRegfile.scala 219:31]
- assign vreg_1_io_read_3_addr = io_read_3_addr; // @[VRegfile.scala 219:31]
- assign vreg_1_io_read_4_addr = io_read_4_addr; // @[VRegfile.scala 219:31]
- assign vreg_1_io_read_5_addr = io_read_5_addr; // @[VRegfile.scala 219:31]
- assign vreg_1_io_read_6_addr = io_read_6_addr; // @[VRegfile.scala 219:31]
- assign vreg_1_io_transpose_addr = io_conv_valid ? io_conv_addr1 : 6'h0; // @[VRegfile.scala 386:37]
- assign vreg_1_io_internal_addr = io_conv_addr2; // @[VRegfile.scala 318:30]
- assign vreg_1_io_write_0_valid = writevalidReg[0]; // @[VRegfile.scala 182:49]
- assign vreg_1_io_write_0_addr = writebitsReg_0_addr; // @[VRegfile.scala 183:32]
- assign vreg_1_io_write_0_data = writebitsReg_0_data[63:32]; // @[VRegfile.scala 184:55]
- assign vreg_1_io_write_1_valid = writevalidReg[1]; // @[VRegfile.scala 182:49]
- assign vreg_1_io_write_1_addr = writebitsReg_1_addr; // @[VRegfile.scala 183:32]
- assign vreg_1_io_write_1_data = writebitsReg_1_data[63:32]; // @[VRegfile.scala 184:55]
- assign vreg_1_io_write_2_valid = writevalidReg[2]; // @[VRegfile.scala 182:49]
- assign vreg_1_io_write_2_addr = writebitsReg_2_addr; // @[VRegfile.scala 183:32]
- assign vreg_1_io_write_2_data = writebitsReg_2_data[63:32]; // @[VRegfile.scala 184:55]
- assign vreg_1_io_write_3_valid = writevalidReg[3]; // @[VRegfile.scala 182:49]
- assign vreg_1_io_write_3_addr = writebitsReg_3_addr; // @[VRegfile.scala 183:32]
- assign vreg_1_io_write_3_data = writebitsReg_3_data[63:32]; // @[VRegfile.scala 184:55]
- assign vreg_1_io_write_4_valid = writevalidReg[4]; // @[VRegfile.scala 182:49]
- assign vreg_1_io_write_4_addr = writebitsReg_4_addr; // @[VRegfile.scala 183:32]
- assign vreg_1_io_write_4_data = writebitsReg_4_data[63:32]; // @[VRegfile.scala 184:55]
- assign vreg_1_io_write_5_valid = writevalidReg[5]; // @[VRegfile.scala 182:49]
- assign vreg_1_io_write_5_addr = writebitsReg_5_addr; // @[VRegfile.scala 183:32]
- assign vreg_1_io_write_5_data = writebitsReg_5_data[63:32]; // @[VRegfile.scala 184:55]
- assign vreg_1_io_conv_valid = convClear; // @[VRegfile.scala 333:27]
- assign vreg_1_io_conv_data_0 = vconv_io_out_0[63:32]; // @[VRegfile.scala 335:49]
- assign vreg_1_io_conv_data_1 = vconv_io_out_1[63:32]; // @[VRegfile.scala 335:49]
- assign vreg_1_io_conv_data_2 = vconv_io_out_2[63:32]; // @[VRegfile.scala 335:49]
- assign vreg_1_io_conv_data_3 = vconv_io_out_3[63:32]; // @[VRegfile.scala 335:49]
- assign vreg_1_io_conv_data_4 = vconv_io_out_4[63:32]; // @[VRegfile.scala 335:49]
- assign vreg_1_io_conv_data_5 = vconv_io_out_5[63:32]; // @[VRegfile.scala 335:49]
- assign vreg_1_io_conv_data_6 = vconv_io_out_6[63:32]; // @[VRegfile.scala 335:49]
- assign vreg_1_io_conv_data_7 = vconv_io_out_7[63:32]; // @[VRegfile.scala 335:49]
- assign vreg_2_clock = clock;
- assign vreg_2_reset = reset;
- assign vreg_2_io_read_0_addr = io_read_0_addr; // @[VRegfile.scala 219:31]
- assign vreg_2_io_read_1_addr = io_read_1_addr; // @[VRegfile.scala 219:31]
- assign vreg_2_io_read_2_addr = io_read_2_addr; // @[VRegfile.scala 219:31]
- assign vreg_2_io_read_3_addr = io_read_3_addr; // @[VRegfile.scala 219:31]
- assign vreg_2_io_read_4_addr = io_read_4_addr; // @[VRegfile.scala 219:31]
- assign vreg_2_io_read_5_addr = io_read_5_addr; // @[VRegfile.scala 219:31]
- assign vreg_2_io_read_6_addr = io_read_6_addr; // @[VRegfile.scala 219:31]
- assign vreg_2_io_transpose_addr = io_conv_valid ? io_conv_addr1 : 6'h0; // @[VRegfile.scala 386:37]
- assign vreg_2_io_internal_addr = io_conv_addr2; // @[VRegfile.scala 318:30]
- assign vreg_2_io_write_0_valid = writevalidReg[0]; // @[VRegfile.scala 182:49]
- assign vreg_2_io_write_0_addr = writebitsReg_0_addr; // @[VRegfile.scala 183:32]
- assign vreg_2_io_write_0_data = writebitsReg_0_data[95:64]; // @[VRegfile.scala 184:55]
- assign vreg_2_io_write_1_valid = writevalidReg[1]; // @[VRegfile.scala 182:49]
- assign vreg_2_io_write_1_addr = writebitsReg_1_addr; // @[VRegfile.scala 183:32]
- assign vreg_2_io_write_1_data = writebitsReg_1_data[95:64]; // @[VRegfile.scala 184:55]
- assign vreg_2_io_write_2_valid = writevalidReg[2]; // @[VRegfile.scala 182:49]
- assign vreg_2_io_write_2_addr = writebitsReg_2_addr; // @[VRegfile.scala 183:32]
- assign vreg_2_io_write_2_data = writebitsReg_2_data[95:64]; // @[VRegfile.scala 184:55]
- assign vreg_2_io_write_3_valid = writevalidReg[3]; // @[VRegfile.scala 182:49]
- assign vreg_2_io_write_3_addr = writebitsReg_3_addr; // @[VRegfile.scala 183:32]
- assign vreg_2_io_write_3_data = writebitsReg_3_data[95:64]; // @[VRegfile.scala 184:55]
- assign vreg_2_io_write_4_valid = writevalidReg[4]; // @[VRegfile.scala 182:49]
- assign vreg_2_io_write_4_addr = writebitsReg_4_addr; // @[VRegfile.scala 183:32]
- assign vreg_2_io_write_4_data = writebitsReg_4_data[95:64]; // @[VRegfile.scala 184:55]
- assign vreg_2_io_write_5_valid = writevalidReg[5]; // @[VRegfile.scala 182:49]
- assign vreg_2_io_write_5_addr = writebitsReg_5_addr; // @[VRegfile.scala 183:32]
- assign vreg_2_io_write_5_data = writebitsReg_5_data[95:64]; // @[VRegfile.scala 184:55]
- assign vreg_2_io_conv_valid = convClear; // @[VRegfile.scala 333:27]
- assign vreg_2_io_conv_data_0 = vconv_io_out_0[95:64]; // @[VRegfile.scala 335:49]
- assign vreg_2_io_conv_data_1 = vconv_io_out_1[95:64]; // @[VRegfile.scala 335:49]
- assign vreg_2_io_conv_data_2 = vconv_io_out_2[95:64]; // @[VRegfile.scala 335:49]
- assign vreg_2_io_conv_data_3 = vconv_io_out_3[95:64]; // @[VRegfile.scala 335:49]
- assign vreg_2_io_conv_data_4 = vconv_io_out_4[95:64]; // @[VRegfile.scala 335:49]
- assign vreg_2_io_conv_data_5 = vconv_io_out_5[95:64]; // @[VRegfile.scala 335:49]
- assign vreg_2_io_conv_data_6 = vconv_io_out_6[95:64]; // @[VRegfile.scala 335:49]
- assign vreg_2_io_conv_data_7 = vconv_io_out_7[95:64]; // @[VRegfile.scala 335:49]
- assign vreg_3_clock = clock;
- assign vreg_3_reset = reset;
- assign vreg_3_io_read_0_addr = io_read_0_addr; // @[VRegfile.scala 219:31]
- assign vreg_3_io_read_1_addr = io_read_1_addr; // @[VRegfile.scala 219:31]
- assign vreg_3_io_read_2_addr = io_read_2_addr; // @[VRegfile.scala 219:31]
- assign vreg_3_io_read_3_addr = io_read_3_addr; // @[VRegfile.scala 219:31]
- assign vreg_3_io_read_4_addr = io_read_4_addr; // @[VRegfile.scala 219:31]
- assign vreg_3_io_read_5_addr = io_read_5_addr; // @[VRegfile.scala 219:31]
- assign vreg_3_io_read_6_addr = io_read_6_addr; // @[VRegfile.scala 219:31]
- assign vreg_3_io_transpose_addr = io_conv_valid ? io_conv_addr1 : 6'h0; // @[VRegfile.scala 386:37]
- assign vreg_3_io_internal_addr = io_conv_addr2; // @[VRegfile.scala 318:30]
- assign vreg_3_io_write_0_valid = writevalidReg[0]; // @[VRegfile.scala 182:49]
- assign vreg_3_io_write_0_addr = writebitsReg_0_addr; // @[VRegfile.scala 183:32]
- assign vreg_3_io_write_0_data = writebitsReg_0_data[127:96]; // @[VRegfile.scala 184:55]
- assign vreg_3_io_write_1_valid = writevalidReg[1]; // @[VRegfile.scala 182:49]
- assign vreg_3_io_write_1_addr = writebitsReg_1_addr; // @[VRegfile.scala 183:32]
- assign vreg_3_io_write_1_data = writebitsReg_1_data[127:96]; // @[VRegfile.scala 184:55]
- assign vreg_3_io_write_2_valid = writevalidReg[2]; // @[VRegfile.scala 182:49]
- assign vreg_3_io_write_2_addr = writebitsReg_2_addr; // @[VRegfile.scala 183:32]
- assign vreg_3_io_write_2_data = writebitsReg_2_data[127:96]; // @[VRegfile.scala 184:55]
- assign vreg_3_io_write_3_valid = writevalidReg[3]; // @[VRegfile.scala 182:49]
- assign vreg_3_io_write_3_addr = writebitsReg_3_addr; // @[VRegfile.scala 183:32]
- assign vreg_3_io_write_3_data = writebitsReg_3_data[127:96]; // @[VRegfile.scala 184:55]
- assign vreg_3_io_write_4_valid = writevalidReg[4]; // @[VRegfile.scala 182:49]
- assign vreg_3_io_write_4_addr = writebitsReg_4_addr; // @[VRegfile.scala 183:32]
- assign vreg_3_io_write_4_data = writebitsReg_4_data[127:96]; // @[VRegfile.scala 184:55]
- assign vreg_3_io_write_5_valid = writevalidReg[5]; // @[VRegfile.scala 182:49]
- assign vreg_3_io_write_5_addr = writebitsReg_5_addr; // @[VRegfile.scala 183:32]
- assign vreg_3_io_write_5_data = writebitsReg_5_data[127:96]; // @[VRegfile.scala 184:55]
- assign vreg_3_io_conv_valid = convClear; // @[VRegfile.scala 333:27]
- assign vreg_3_io_conv_data_0 = vconv_io_out_0[127:96]; // @[VRegfile.scala 335:49]
- assign vreg_3_io_conv_data_1 = vconv_io_out_1[127:96]; // @[VRegfile.scala 335:49]
- assign vreg_3_io_conv_data_2 = vconv_io_out_2[127:96]; // @[VRegfile.scala 335:49]
- assign vreg_3_io_conv_data_3 = vconv_io_out_3[127:96]; // @[VRegfile.scala 335:49]
- assign vreg_3_io_conv_data_4 = vconv_io_out_4[127:96]; // @[VRegfile.scala 335:49]
- assign vreg_3_io_conv_data_5 = vconv_io_out_5[127:96]; // @[VRegfile.scala 335:49]
- assign vreg_3_io_conv_data_6 = vconv_io_out_6[127:96]; // @[VRegfile.scala 335:49]
- assign vreg_3_io_conv_data_7 = vconv_io_out_7[127:96]; // @[VRegfile.scala 335:49]
- assign vreg_4_clock = clock;
- assign vreg_4_reset = reset;
- assign vreg_4_io_read_0_addr = io_read_0_addr; // @[VRegfile.scala 219:31]
- assign vreg_4_io_read_1_addr = io_read_1_addr; // @[VRegfile.scala 219:31]
- assign vreg_4_io_read_2_addr = io_read_2_addr; // @[VRegfile.scala 219:31]
- assign vreg_4_io_read_3_addr = io_read_3_addr; // @[VRegfile.scala 219:31]
- assign vreg_4_io_read_4_addr = io_read_4_addr; // @[VRegfile.scala 219:31]
- assign vreg_4_io_read_5_addr = io_read_5_addr; // @[VRegfile.scala 219:31]
- assign vreg_4_io_read_6_addr = io_read_6_addr; // @[VRegfile.scala 219:31]
- assign vreg_4_io_transpose_addr = io_conv_valid ? io_conv_addr1 : 6'h0; // @[VRegfile.scala 386:37]
- assign vreg_4_io_internal_addr = io_conv_addr2; // @[VRegfile.scala 318:30]
- assign vreg_4_io_write_0_valid = writevalidReg[0]; // @[VRegfile.scala 182:49]
- assign vreg_4_io_write_0_addr = writebitsReg_0_addr; // @[VRegfile.scala 183:32]
- assign vreg_4_io_write_0_data = writebitsReg_0_data[159:128]; // @[VRegfile.scala 184:55]
- assign vreg_4_io_write_1_valid = writevalidReg[1]; // @[VRegfile.scala 182:49]
- assign vreg_4_io_write_1_addr = writebitsReg_1_addr; // @[VRegfile.scala 183:32]
- assign vreg_4_io_write_1_data = writebitsReg_1_data[159:128]; // @[VRegfile.scala 184:55]
- assign vreg_4_io_write_2_valid = writevalidReg[2]; // @[VRegfile.scala 182:49]
- assign vreg_4_io_write_2_addr = writebitsReg_2_addr; // @[VRegfile.scala 183:32]
- assign vreg_4_io_write_2_data = writebitsReg_2_data[159:128]; // @[VRegfile.scala 184:55]
- assign vreg_4_io_write_3_valid = writevalidReg[3]; // @[VRegfile.scala 182:49]
- assign vreg_4_io_write_3_addr = writebitsReg_3_addr; // @[VRegfile.scala 183:32]
- assign vreg_4_io_write_3_data = writebitsReg_3_data[159:128]; // @[VRegfile.scala 184:55]
- assign vreg_4_io_write_4_valid = writevalidReg[4]; // @[VRegfile.scala 182:49]
- assign vreg_4_io_write_4_addr = writebitsReg_4_addr; // @[VRegfile.scala 183:32]
- assign vreg_4_io_write_4_data = writebitsReg_4_data[159:128]; // @[VRegfile.scala 184:55]
- assign vreg_4_io_write_5_valid = writevalidReg[5]; // @[VRegfile.scala 182:49]
- assign vreg_4_io_write_5_addr = writebitsReg_5_addr; // @[VRegfile.scala 183:32]
- assign vreg_4_io_write_5_data = writebitsReg_5_data[159:128]; // @[VRegfile.scala 184:55]
- assign vreg_4_io_conv_valid = convClear; // @[VRegfile.scala 333:27]
- assign vreg_4_io_conv_data_0 = vconv_io_out_0[159:128]; // @[VRegfile.scala 335:49]
- assign vreg_4_io_conv_data_1 = vconv_io_out_1[159:128]; // @[VRegfile.scala 335:49]
- assign vreg_4_io_conv_data_2 = vconv_io_out_2[159:128]; // @[VRegfile.scala 335:49]
- assign vreg_4_io_conv_data_3 = vconv_io_out_3[159:128]; // @[VRegfile.scala 335:49]
- assign vreg_4_io_conv_data_4 = vconv_io_out_4[159:128]; // @[VRegfile.scala 335:49]
- assign vreg_4_io_conv_data_5 = vconv_io_out_5[159:128]; // @[VRegfile.scala 335:49]
- assign vreg_4_io_conv_data_6 = vconv_io_out_6[159:128]; // @[VRegfile.scala 335:49]
- assign vreg_4_io_conv_data_7 = vconv_io_out_7[159:128]; // @[VRegfile.scala 335:49]
- assign vreg_5_clock = clock;
- assign vreg_5_reset = reset;
- assign vreg_5_io_read_0_addr = io_read_0_addr; // @[VRegfile.scala 219:31]
- assign vreg_5_io_read_1_addr = io_read_1_addr; // @[VRegfile.scala 219:31]
- assign vreg_5_io_read_2_addr = io_read_2_addr; // @[VRegfile.scala 219:31]
- assign vreg_5_io_read_3_addr = io_read_3_addr; // @[VRegfile.scala 219:31]
- assign vreg_5_io_read_4_addr = io_read_4_addr; // @[VRegfile.scala 219:31]
- assign vreg_5_io_read_5_addr = io_read_5_addr; // @[VRegfile.scala 219:31]
- assign vreg_5_io_read_6_addr = io_read_6_addr; // @[VRegfile.scala 219:31]
- assign vreg_5_io_transpose_addr = io_conv_valid ? io_conv_addr1 : 6'h0; // @[VRegfile.scala 386:37]
- assign vreg_5_io_internal_addr = io_conv_addr2; // @[VRegfile.scala 318:30]
- assign vreg_5_io_write_0_valid = writevalidReg[0]; // @[VRegfile.scala 182:49]
- assign vreg_5_io_write_0_addr = writebitsReg_0_addr; // @[VRegfile.scala 183:32]
- assign vreg_5_io_write_0_data = writebitsReg_0_data[191:160]; // @[VRegfile.scala 184:55]
- assign vreg_5_io_write_1_valid = writevalidReg[1]; // @[VRegfile.scala 182:49]
- assign vreg_5_io_write_1_addr = writebitsReg_1_addr; // @[VRegfile.scala 183:32]
- assign vreg_5_io_write_1_data = writebitsReg_1_data[191:160]; // @[VRegfile.scala 184:55]
- assign vreg_5_io_write_2_valid = writevalidReg[2]; // @[VRegfile.scala 182:49]
- assign vreg_5_io_write_2_addr = writebitsReg_2_addr; // @[VRegfile.scala 183:32]
- assign vreg_5_io_write_2_data = writebitsReg_2_data[191:160]; // @[VRegfile.scala 184:55]
- assign vreg_5_io_write_3_valid = writevalidReg[3]; // @[VRegfile.scala 182:49]
- assign vreg_5_io_write_3_addr = writebitsReg_3_addr; // @[VRegfile.scala 183:32]
- assign vreg_5_io_write_3_data = writebitsReg_3_data[191:160]; // @[VRegfile.scala 184:55]
- assign vreg_5_io_write_4_valid = writevalidReg[4]; // @[VRegfile.scala 182:49]
- assign vreg_5_io_write_4_addr = writebitsReg_4_addr; // @[VRegfile.scala 183:32]
- assign vreg_5_io_write_4_data = writebitsReg_4_data[191:160]; // @[VRegfile.scala 184:55]
- assign vreg_5_io_write_5_valid = writevalidReg[5]; // @[VRegfile.scala 182:49]
- assign vreg_5_io_write_5_addr = writebitsReg_5_addr; // @[VRegfile.scala 183:32]
- assign vreg_5_io_write_5_data = writebitsReg_5_data[191:160]; // @[VRegfile.scala 184:55]
- assign vreg_5_io_conv_valid = convClear; // @[VRegfile.scala 333:27]
- assign vreg_5_io_conv_data_0 = vconv_io_out_0[191:160]; // @[VRegfile.scala 335:49]
- assign vreg_5_io_conv_data_1 = vconv_io_out_1[191:160]; // @[VRegfile.scala 335:49]
- assign vreg_5_io_conv_data_2 = vconv_io_out_2[191:160]; // @[VRegfile.scala 335:49]
- assign vreg_5_io_conv_data_3 = vconv_io_out_3[191:160]; // @[VRegfile.scala 335:49]
- assign vreg_5_io_conv_data_4 = vconv_io_out_4[191:160]; // @[VRegfile.scala 335:49]
- assign vreg_5_io_conv_data_5 = vconv_io_out_5[191:160]; // @[VRegfile.scala 335:49]
- assign vreg_5_io_conv_data_6 = vconv_io_out_6[191:160]; // @[VRegfile.scala 335:49]
- assign vreg_5_io_conv_data_7 = vconv_io_out_7[191:160]; // @[VRegfile.scala 335:49]
- assign vreg_6_clock = clock;
- assign vreg_6_reset = reset;
- assign vreg_6_io_read_0_addr = io_read_0_addr; // @[VRegfile.scala 219:31]
- assign vreg_6_io_read_1_addr = io_read_1_addr; // @[VRegfile.scala 219:31]
- assign vreg_6_io_read_2_addr = io_read_2_addr; // @[VRegfile.scala 219:31]
- assign vreg_6_io_read_3_addr = io_read_3_addr; // @[VRegfile.scala 219:31]
- assign vreg_6_io_read_4_addr = io_read_4_addr; // @[VRegfile.scala 219:31]
- assign vreg_6_io_read_5_addr = io_read_5_addr; // @[VRegfile.scala 219:31]
- assign vreg_6_io_read_6_addr = io_read_6_addr; // @[VRegfile.scala 219:31]
- assign vreg_6_io_transpose_addr = io_conv_valid ? io_conv_addr1 : 6'h0; // @[VRegfile.scala 386:37]
- assign vreg_6_io_internal_addr = io_conv_addr2; // @[VRegfile.scala 318:30]
- assign vreg_6_io_write_0_valid = writevalidReg[0]; // @[VRegfile.scala 182:49]
- assign vreg_6_io_write_0_addr = writebitsReg_0_addr; // @[VRegfile.scala 183:32]
- assign vreg_6_io_write_0_data = writebitsReg_0_data[223:192]; // @[VRegfile.scala 184:55]
- assign vreg_6_io_write_1_valid = writevalidReg[1]; // @[VRegfile.scala 182:49]
- assign vreg_6_io_write_1_addr = writebitsReg_1_addr; // @[VRegfile.scala 183:32]
- assign vreg_6_io_write_1_data = writebitsReg_1_data[223:192]; // @[VRegfile.scala 184:55]
- assign vreg_6_io_write_2_valid = writevalidReg[2]; // @[VRegfile.scala 182:49]
- assign vreg_6_io_write_2_addr = writebitsReg_2_addr; // @[VRegfile.scala 183:32]
- assign vreg_6_io_write_2_data = writebitsReg_2_data[223:192]; // @[VRegfile.scala 184:55]
- assign vreg_6_io_write_3_valid = writevalidReg[3]; // @[VRegfile.scala 182:49]
- assign vreg_6_io_write_3_addr = writebitsReg_3_addr; // @[VRegfile.scala 183:32]
- assign vreg_6_io_write_3_data = writebitsReg_3_data[223:192]; // @[VRegfile.scala 184:55]
- assign vreg_6_io_write_4_valid = writevalidReg[4]; // @[VRegfile.scala 182:49]
- assign vreg_6_io_write_4_addr = writebitsReg_4_addr; // @[VRegfile.scala 183:32]
- assign vreg_6_io_write_4_data = writebitsReg_4_data[223:192]; // @[VRegfile.scala 184:55]
- assign vreg_6_io_write_5_valid = writevalidReg[5]; // @[VRegfile.scala 182:49]
- assign vreg_6_io_write_5_addr = writebitsReg_5_addr; // @[VRegfile.scala 183:32]
- assign vreg_6_io_write_5_data = writebitsReg_5_data[223:192]; // @[VRegfile.scala 184:55]
- assign vreg_6_io_conv_valid = convClear; // @[VRegfile.scala 333:27]
- assign vreg_6_io_conv_data_0 = vconv_io_out_0[223:192]; // @[VRegfile.scala 335:49]
- assign vreg_6_io_conv_data_1 = vconv_io_out_1[223:192]; // @[VRegfile.scala 335:49]
- assign vreg_6_io_conv_data_2 = vconv_io_out_2[223:192]; // @[VRegfile.scala 335:49]
- assign vreg_6_io_conv_data_3 = vconv_io_out_3[223:192]; // @[VRegfile.scala 335:49]
- assign vreg_6_io_conv_data_4 = vconv_io_out_4[223:192]; // @[VRegfile.scala 335:49]
- assign vreg_6_io_conv_data_5 = vconv_io_out_5[223:192]; // @[VRegfile.scala 335:49]
- assign vreg_6_io_conv_data_6 = vconv_io_out_6[223:192]; // @[VRegfile.scala 335:49]
- assign vreg_6_io_conv_data_7 = vconv_io_out_7[223:192]; // @[VRegfile.scala 335:49]
- assign vreg_7_clock = clock;
- assign vreg_7_reset = reset;
- assign vreg_7_io_read_0_addr = io_read_0_addr; // @[VRegfile.scala 219:31]
- assign vreg_7_io_read_1_addr = io_read_1_addr; // @[VRegfile.scala 219:31]
- assign vreg_7_io_read_2_addr = io_read_2_addr; // @[VRegfile.scala 219:31]
- assign vreg_7_io_read_3_addr = io_read_3_addr; // @[VRegfile.scala 219:31]
- assign vreg_7_io_read_4_addr = io_read_4_addr; // @[VRegfile.scala 219:31]
- assign vreg_7_io_read_5_addr = io_read_5_addr; // @[VRegfile.scala 219:31]
- assign vreg_7_io_read_6_addr = io_read_6_addr; // @[VRegfile.scala 219:31]
- assign vreg_7_io_transpose_addr = io_conv_valid ? io_conv_addr1 : 6'h0; // @[VRegfile.scala 386:37]
- assign vreg_7_io_internal_addr = io_conv_addr2; // @[VRegfile.scala 318:30]
- assign vreg_7_io_write_0_valid = writevalidReg[0]; // @[VRegfile.scala 182:49]
- assign vreg_7_io_write_0_addr = writebitsReg_0_addr; // @[VRegfile.scala 183:32]
- assign vreg_7_io_write_0_data = writebitsReg_0_data[255:224]; // @[VRegfile.scala 184:55]
- assign vreg_7_io_write_1_valid = writevalidReg[1]; // @[VRegfile.scala 182:49]
- assign vreg_7_io_write_1_addr = writebitsReg_1_addr; // @[VRegfile.scala 183:32]
- assign vreg_7_io_write_1_data = writebitsReg_1_data[255:224]; // @[VRegfile.scala 184:55]
- assign vreg_7_io_write_2_valid = writevalidReg[2]; // @[VRegfile.scala 182:49]
- assign vreg_7_io_write_2_addr = writebitsReg_2_addr; // @[VRegfile.scala 183:32]
- assign vreg_7_io_write_2_data = writebitsReg_2_data[255:224]; // @[VRegfile.scala 184:55]
- assign vreg_7_io_write_3_valid = writevalidReg[3]; // @[VRegfile.scala 182:49]
- assign vreg_7_io_write_3_addr = writebitsReg_3_addr; // @[VRegfile.scala 183:32]
- assign vreg_7_io_write_3_data = writebitsReg_3_data[255:224]; // @[VRegfile.scala 184:55]
- assign vreg_7_io_write_4_valid = writevalidReg[4]; // @[VRegfile.scala 182:49]
- assign vreg_7_io_write_4_addr = writebitsReg_4_addr; // @[VRegfile.scala 183:32]
- assign vreg_7_io_write_4_data = writebitsReg_4_data[255:224]; // @[VRegfile.scala 184:55]
- assign vreg_7_io_write_5_valid = writevalidReg[5]; // @[VRegfile.scala 182:49]
- assign vreg_7_io_write_5_addr = writebitsReg_5_addr; // @[VRegfile.scala 183:32]
- assign vreg_7_io_write_5_data = writebitsReg_5_data[255:224]; // @[VRegfile.scala 184:55]
- assign vreg_7_io_conv_valid = convClear; // @[VRegfile.scala 333:27]
- assign vreg_7_io_conv_data_0 = vconv_io_out_0[255:224]; // @[VRegfile.scala 335:49]
- assign vreg_7_io_conv_data_1 = vconv_io_out_1[255:224]; // @[VRegfile.scala 335:49]
- assign vreg_7_io_conv_data_2 = vconv_io_out_2[255:224]; // @[VRegfile.scala 335:49]
- assign vreg_7_io_conv_data_3 = vconv_io_out_3[255:224]; // @[VRegfile.scala 335:49]
- assign vreg_7_io_conv_data_4 = vconv_io_out_4[255:224]; // @[VRegfile.scala 335:49]
- assign vreg_7_io_conv_data_5 = vconv_io_out_5[255:224]; // @[VRegfile.scala 335:49]
- assign vreg_7_io_conv_data_6 = vconv_io_out_6[255:224]; // @[VRegfile.scala 335:49]
- assign vreg_7_io_conv_data_7 = vconv_io_out_7[255:224]; // @[VRegfile.scala 335:49]
- assign vconv_clock = clock;
- assign vconv_reset = reset;
- assign vconv_io_op_conv = convConv; // @[VRegfile.scala 368:20]
- assign vconv_io_op_init = convInit; // @[VRegfile.scala 369:20]
- assign vconv_io_op_tran = convTran; // @[VRegfile.scala 370:20]
- assign vconv_io_op_clear = convClear; // @[VRegfile.scala 371:21]
- assign vconv_io_index = convIndex; // @[VRegfile.scala 372:18]
- assign vconv_io_adata = io_transpose_data; // @[VRegfile.scala 373:18]
- assign vconv_io_bdata = internalData; // @[VRegfile.scala 374:18]
- assign vconv_io_abias = convAbias; // @[VRegfile.scala 375:18]
- assign vconv_io_bbias = convBbias; // @[VRegfile.scala 376:18]
- assign vconv_io_asign = convAsign; // @[VRegfile.scala 377:18]
- assign vconv_io_bsign = convBsign; // @[VRegfile.scala 378:18]
- always @(posedge clock) begin
- if (io_write_0_valid) begin // @[VRegfile.scala 172:30]
- writebitsReg_0_addr <= io_write_0_addr; // @[VRegfile.scala 173:28]
- end
- if (io_write_0_valid) begin // @[VRegfile.scala 172:30]
- writebitsReg_0_data <= io_write_0_data; // @[VRegfile.scala 174:28]
- end
- if (io_write_1_valid) begin // @[VRegfile.scala 172:30]
- writebitsReg_1_addr <= io_write_1_addr; // @[VRegfile.scala 173:28]
- end
- if (io_write_1_valid) begin // @[VRegfile.scala 172:30]
- writebitsReg_1_data <= io_write_1_data; // @[VRegfile.scala 174:28]
- end
- if (io_write_2_valid) begin // @[VRegfile.scala 172:30]
- writebitsReg_2_addr <= io_write_2_addr; // @[VRegfile.scala 173:28]
- end
- if (io_write_2_valid) begin // @[VRegfile.scala 172:30]
- writebitsReg_2_data <= io_write_2_data; // @[VRegfile.scala 174:28]
- end
- if (io_write_3_valid) begin // @[VRegfile.scala 172:30]
- writebitsReg_3_addr <= io_write_3_addr; // @[VRegfile.scala 173:28]
- end
- if (io_write_3_valid) begin // @[VRegfile.scala 172:30]
- writebitsReg_3_data <= io_write_3_data; // @[VRegfile.scala 174:28]
- end
- if (io_write_4_valid) begin // @[VRegfile.scala 172:30]
- writebitsReg_4_addr <= io_write_4_addr; // @[VRegfile.scala 173:28]
- end
- if (io_write_4_valid) begin // @[VRegfile.scala 172:30]
- writebitsReg_4_data <= io_write_4_data; // @[VRegfile.scala 174:28]
- end
- if (io_write_5_valid) begin // @[VRegfile.scala 172:30]
- writebitsReg_5_addr <= io_write_5_addr; // @[VRegfile.scala 173:28]
- end
- if (io_write_5_valid) begin // @[VRegfile.scala 172:30]
- writebitsReg_5_data <= io_write_5_data; // @[VRegfile.scala 174:28]
- end
- if (io_read_0_valid) begin // @[VRegfile.scala 279:19]
- readData_0 <= data; // @[VRegfile.scala 280:19]
- end
- if (rvalid) begin // @[VRegfile.scala 279:19]
- readData_1 <= data_1; // @[VRegfile.scala 280:19]
- end
- if (io_read_2_valid) begin // @[VRegfile.scala 279:19]
- readData_2 <= data_2; // @[VRegfile.scala 280:19]
- end
- if (io_read_3_valid) begin // @[VRegfile.scala 279:19]
- readData_3 <= data_3; // @[VRegfile.scala 280:19]
- end
- if (rvalid_1) begin // @[VRegfile.scala 279:19]
- readData_4 <= data_4; // @[VRegfile.scala 280:19]
- end
- if (io_read_5_valid) begin // @[VRegfile.scala 279:19]
- readData_5 <= data_5; // @[VRegfile.scala 280:19]
- end
- if (io_read_6_valid) begin // @[VRegfile.scala 279:19]
- readData_6 <= data_6; // @[VRegfile.scala 280:19]
- end
- convIndex <= io_conv_index; // @[VRegfile.scala 307:13]
- if (io_conv_valid) begin // @[VRegfile.scala 325:24]
- convAbias <= io_conv_abias; // @[VRegfile.scala 326:16]
- end
- if (io_conv_valid) begin // @[VRegfile.scala 325:24]
- convBbias <= io_conv_bbias; // @[VRegfile.scala 327:16]
- end
- if (io_conv_valid) begin // @[VRegfile.scala 325:24]
- convAsign <= io_conv_asign; // @[VRegfile.scala 328:16]
- end
- if (io_conv_valid) begin // @[VRegfile.scala 325:24]
- convBsign <= io_conv_bsign; // @[VRegfile.scala 329:16]
- end
- if (io_conv_valid) begin // @[VRegfile.scala 321:24]
- internalData <= _internalData_T; // @[VRegfile.scala 322:18]
- end
- if (io_conv_valid) begin // @[VRegfile.scala 390:46]
- transposeData <= transposeData_value_3_0; // @[VRegfile.scala 392:19]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_14 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 228:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_14 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:228 assert(PopCount(f1valid) <= 1.U)\n"); // @[VRegfile.scala 228:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_34 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 232:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_34 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:232 assert(PopCount(f2valid) <= 1.U)\n"); // @[VRegfile.scala 232:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_48 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 264:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_48 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:264 assert(PopCount(sel) <= 1.U)\n"); // @[VRegfile.scala 264:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_68 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 228:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_68 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:228 assert(PopCount(f1valid) <= 1.U)\n"); // @[VRegfile.scala 228:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_88 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 232:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_88 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:232 assert(PopCount(f2valid) <= 1.U)\n"); // @[VRegfile.scala 232:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_102 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 264:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_102 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:264 assert(PopCount(sel) <= 1.U)\n"); // @[VRegfile.scala 264:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~(io_read_1_valid & io_scalar_0_valid))) begin
- $fatal; // @[VRegfile.scala 273:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~(io_read_1_valid & io_scalar_0_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:273 assert(!(io.read(i).valid && io.scalar(i / 3).valid))\n"); // @[VRegfile.scala 273:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_122 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 228:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_122 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:228 assert(PopCount(f1valid) <= 1.U)\n"); // @[VRegfile.scala 228:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_142 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 232:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_142 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:232 assert(PopCount(f2valid) <= 1.U)\n"); // @[VRegfile.scala 232:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_156 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 264:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_156 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:264 assert(PopCount(sel) <= 1.U)\n"); // @[VRegfile.scala 264:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_176 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 228:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_176 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:228 assert(PopCount(f1valid) <= 1.U)\n"); // @[VRegfile.scala 228:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_196 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 232:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_196 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:232 assert(PopCount(f2valid) <= 1.U)\n"); // @[VRegfile.scala 232:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_210 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 264:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_210 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:264 assert(PopCount(sel) <= 1.U)\n"); // @[VRegfile.scala 264:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_230 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 228:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_230 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:228 assert(PopCount(f1valid) <= 1.U)\n"); // @[VRegfile.scala 228:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_250 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 232:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_250 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:232 assert(PopCount(f2valid) <= 1.U)\n"); // @[VRegfile.scala 232:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_264 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 264:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_264 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:264 assert(PopCount(sel) <= 1.U)\n"); // @[VRegfile.scala 264:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~(io_read_4_valid & io_scalar_1_valid))) begin
- $fatal; // @[VRegfile.scala 273:15]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~(io_read_4_valid & io_scalar_1_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:273 assert(!(io.read(i).valid && io.scalar(i / 3).valid))\n"); // @[VRegfile.scala 273:15]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_284 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 228:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_284 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:228 assert(PopCount(f1valid) <= 1.U)\n"); // @[VRegfile.scala 228:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_304 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 232:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_304 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:232 assert(PopCount(f2valid) <= 1.U)\n"); // @[VRegfile.scala 232:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_318 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 264:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_318 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:264 assert(PopCount(sel) <= 1.U)\n"); // @[VRegfile.scala 264:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_338 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 228:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_338 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:228 assert(PopCount(f1valid) <= 1.U)\n"); // @[VRegfile.scala 228:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_358 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 232:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_358 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:232 assert(PopCount(f2valid) <= 1.U)\n"); // @[VRegfile.scala 232:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(_T_372 <= 3'h1)) begin
- $fatal; // @[VRegfile.scala 264:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(_T_372 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at VRegfile.scala:264 assert(PopCount(sel) <= 1.U)\n"); // @[VRegfile.scala 264:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~_convConv_T | _T_391)) begin
- $fatal; // @[VRegfile.scala 309:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~_convConv_T | _T_391)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:309 assert(!(io.conv.valid && io.conv.ready) ||\n"); // @[VRegfile.scala 309:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~(_convConv_T_1 & io_conv_mode != 2'h0))) begin
- $fatal; // @[VRegfile.scala 344:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~(_convConv_T_1 & io_conv_mode != 2'h0))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:344 assert(!(convRead0 && io.conv.mode =/= 0.U))\n"); // @[VRegfile.scala 344:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~(_convConv_T_1 & io_conv_addr1[3:0] != 4'h0))) begin
- $fatal; // @[VRegfile.scala 347:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~(_convConv_T_1 & io_conv_addr1[3:0] != 4'h0))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:347 assert(!(convRead0 && io.conv.addr1(3,0) =/= 0.U))\n"); // @[VRegfile.scala 347:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~(_convConv_T_1 & io_conv_addr1[5:3] == io_conv_addr2[5:3]))) begin
- $fatal; // @[VRegfile.scala 349:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~(_convConv_T_1 & io_conv_addr1[5:3] == io_conv_addr2[5:3]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:349 assert(!(convRead0 && io.conv.addr1(5,3) === io.conv.addr2(5,3) && (p.vectorBits == 256).B))\n"
- ); // @[VRegfile.scala 349:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~(_convConv_T_1 & _T_436[0]))) begin
- $fatal; // @[VRegfile.scala 353:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~(_convConv_T_1 & _T_436[0]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:353 assert(!(convRead0 && writeCurr(io.conv.addr2)))\n"); // @[VRegfile.scala 353:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~(_convConv_T_1 & _T_443[0]))) begin
- $fatal; // @[VRegfile.scala 354:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~(_convConv_T_1 & _T_443[0]))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:354 assert(!(convRead0 && writePrev(io.conv.addr2)))\n"); // @[VRegfile.scala 354:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~(_convClear_T_1 & _T_450 != 79'h0))) begin
- $fatal; // @[VRegfile.scala 357:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~(_convClear_T_1 & _T_450 != 79'h0))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:357 assert(!(convClear0 && (writeCurr & convmaska) =/= 0.U))\n"); // @[VRegfile.scala 357:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~(_convClear_T_1 & _T_457 != 79'h0))) begin
- $fatal; // @[VRegfile.scala 358:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~(_convClear_T_1 & _T_457 != 79'h0))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:358 assert(!(convClear0 && (writePrev & convmaska) =/= 0.U))\n"); // @[VRegfile.scala 358:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~((_convClear_T_1 | convClear) & io_write_0_valid & io_write_0_addr >= 6'h30))) begin
- $fatal; // @[VRegfile.scala 363:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~((_convClear_T_1 | convClear) & io_write_0_valid & io_write_0_addr >= 6'h30))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:363 assert(!((convClear0 || convClear) && io.write(i).valid && io.write(i).addr >= 48.U))\n"
- ); // @[VRegfile.scala 363:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~((_convClear_T_1 | convClear) & io_write_1_valid & io_write_1_addr >= 6'h30))) begin
- $fatal; // @[VRegfile.scala 363:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~((_convClear_T_1 | convClear) & io_write_1_valid & io_write_1_addr >= 6'h30))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:363 assert(!((convClear0 || convClear) && io.write(i).valid && io.write(i).addr >= 48.U))\n"
- ); // @[VRegfile.scala 363:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~((_convClear_T_1 | convClear) & io_write_2_valid & io_write_2_addr >= 6'h30))) begin
- $fatal; // @[VRegfile.scala 363:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~((_convClear_T_1 | convClear) & io_write_2_valid & io_write_2_addr >= 6'h30))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:363 assert(!((convClear0 || convClear) && io.write(i).valid && io.write(i).addr >= 48.U))\n"
- ); // @[VRegfile.scala 363:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~((_convClear_T_1 | convClear) & io_write_3_valid & io_write_3_addr >= 6'h30))) begin
- $fatal; // @[VRegfile.scala 363:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~((_convClear_T_1 | convClear) & io_write_3_valid & io_write_3_addr >= 6'h30))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:363 assert(!((convClear0 || convClear) && io.write(i).valid && io.write(i).addr >= 48.U))\n"
- ); // @[VRegfile.scala 363:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~((_convClear_T_1 | convClear) & io_write_4_valid & io_write_4_addr >= 6'h30))) begin
- $fatal; // @[VRegfile.scala 363:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~((_convClear_T_1 | convClear) & io_write_4_valid & io_write_4_addr >= 6'h30))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:363 assert(!((convClear0 || convClear) && io.write(i).valid && io.write(i).addr >= 48.U))\n"
- ); // @[VRegfile.scala 363:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_18 & ~(~((_convClear_T_1 | convClear) & io_write_5_valid & io_write_5_addr >= 6'h30))) begin
- $fatal; // @[VRegfile.scala 363:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_18 & ~(~((_convClear_T_1 | convClear) & io_write_5_valid & io_write_5_addr >= 6'h30))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VRegfile.scala:363 assert(!((convClear0 || convClear) && io.write(i).valid && io.write(i).addr >= 48.U))\n"
- ); // @[VRegfile.scala 363:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Library.scala 76:39]
- writePrev <= 64'h0;
- end else begin
- writePrev <= _writeCurr_T_4 | writeSet_5;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VRegfile.scala 158:35]
- writevalidReg <= 6'h0;
- end else begin
- writevalidReg <= {writevalid_hi,writevalid_lo};
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VRegfile.scala 303:47]
- convConv <= 1'h0;
- end else begin
- convConv <= io_conv_valid & io_conv_ready & io_conv_op_conv;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VRegfile.scala 304:47]
- convInit <= 1'h0;
- end else begin
- convInit <= _convConv_T & io_conv_op_init;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VRegfile.scala 305:47]
- convTran <= 1'h0;
- end else begin
- convTran <= _convConv_T & io_conv_op_tran;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VRegfile.scala 306:47]
- convClear <= 1'h0;
- end else begin
- convClear <= _convConv_T & io_conv_op_wclr;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[VRegfile.scala 436:35]
- vrfsb <= 128'h0; // @[VRegfile.scala 437:11]
- end else if (io_vrfsb_set_valid | vrfsbClrEn) begin // @[VRegfile.scala 431:22]
- vrfsb <= _vrfsb_T_2;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {2{`RANDOM}};
- writePrev = _RAND_0[63:0];
- _RAND_1 = {1{`RANDOM}};
- writevalidReg = _RAND_1[5:0];
- _RAND_2 = {1{`RANDOM}};
- writebitsReg_0_addr = _RAND_2[5:0];
- _RAND_3 = {8{`RANDOM}};
- writebitsReg_0_data = _RAND_3[255:0];
- _RAND_4 = {1{`RANDOM}};
- writebitsReg_1_addr = _RAND_4[5:0];
- _RAND_5 = {8{`RANDOM}};
- writebitsReg_1_data = _RAND_5[255:0];
- _RAND_6 = {1{`RANDOM}};
- writebitsReg_2_addr = _RAND_6[5:0];
- _RAND_7 = {8{`RANDOM}};
- writebitsReg_2_data = _RAND_7[255:0];
- _RAND_8 = {1{`RANDOM}};
- writebitsReg_3_addr = _RAND_8[5:0];
- _RAND_9 = {8{`RANDOM}};
- writebitsReg_3_data = _RAND_9[255:0];
- _RAND_10 = {1{`RANDOM}};
- writebitsReg_4_addr = _RAND_10[5:0];
- _RAND_11 = {8{`RANDOM}};
- writebitsReg_4_data = _RAND_11[255:0];
- _RAND_12 = {1{`RANDOM}};
- writebitsReg_5_addr = _RAND_12[5:0];
- _RAND_13 = {8{`RANDOM}};
- writebitsReg_5_data = _RAND_13[255:0];
- _RAND_14 = {8{`RANDOM}};
- readData_0 = _RAND_14[255:0];
- _RAND_15 = {8{`RANDOM}};
- readData_1 = _RAND_15[255:0];
- _RAND_16 = {8{`RANDOM}};
- readData_2 = _RAND_16[255:0];
- _RAND_17 = {8{`RANDOM}};
- readData_3 = _RAND_17[255:0];
- _RAND_18 = {8{`RANDOM}};
- readData_4 = _RAND_18[255:0];
- _RAND_19 = {8{`RANDOM}};
- readData_5 = _RAND_19[255:0];
- _RAND_20 = {8{`RANDOM}};
- readData_6 = _RAND_20[255:0];
- _RAND_21 = {1{`RANDOM}};
- convConv = _RAND_21[0:0];
- _RAND_22 = {1{`RANDOM}};
- convInit = _RAND_22[0:0];
- _RAND_23 = {1{`RANDOM}};
- convTran = _RAND_23[0:0];
- _RAND_24 = {1{`RANDOM}};
- convClear = _RAND_24[0:0];
- _RAND_25 = {1{`RANDOM}};
- convIndex = _RAND_25[2:0];
- _RAND_26 = {1{`RANDOM}};
- convAbias = _RAND_26[8:0];
- _RAND_27 = {1{`RANDOM}};
- convBbias = _RAND_27[8:0];
- _RAND_28 = {1{`RANDOM}};
- convAsign = _RAND_28[0:0];
- _RAND_29 = {1{`RANDOM}};
- convBsign = _RAND_29[0:0];
- _RAND_30 = {8{`RANDOM}};
- internalData = _RAND_30[255:0];
- _RAND_31 = {8{`RANDOM}};
- transposeData = _RAND_31[255:0];
- _RAND_32 = {4{`RANDOM}};
- vrfsb = _RAND_32[127:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- writePrev = 64'h0;
- end
- if (reset) begin
- writevalidReg = 6'h0;
- end
- if (reset) begin
- convConv = 1'h0;
- end
- if (reset) begin
- convInit = 1'h0;
- end
- if (reset) begin
- convTran = 1'h0;
- end
- if (reset) begin
- convClear = 1'h0;
- end
- if (reset) begin
- vrfsb = 128'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module VCore(
- input clock,
- input reset,
- input io_score_vinst_0_valid,
- output io_score_vinst_0_ready,
- input [4:0] io_score_vinst_0_addr,
- input [31:0] io_score_vinst_0_inst,
- input [4:0] io_score_vinst_0_op,
- input io_score_vinst_1_valid,
- output io_score_vinst_1_ready,
- input [4:0] io_score_vinst_1_addr,
- input [31:0] io_score_vinst_1_inst,
- input [4:0] io_score_vinst_1_op,
- input io_score_vinst_2_valid,
- output io_score_vinst_2_ready,
- input [4:0] io_score_vinst_2_addr,
- input [31:0] io_score_vinst_2_inst,
- input [4:0] io_score_vinst_2_op,
- input io_score_vinst_3_valid,
- output io_score_vinst_3_ready,
- input [4:0] io_score_vinst_3_addr,
- input [31:0] io_score_vinst_3_inst,
- input [4:0] io_score_vinst_3_op,
- input [31:0] io_score_rs_0_data,
- input [31:0] io_score_rs_1_data,
- input [31:0] io_score_rs_2_data,
- input [31:0] io_score_rs_3_data,
- input [31:0] io_score_rs_4_data,
- input [31:0] io_score_rs_5_data,
- input [31:0] io_score_rs_6_data,
- input [31:0] io_score_rs_7_data,
- output io_score_rd_0_valid,
- output [4:0] io_score_rd_0_addr,
- output [31:0] io_score_rd_0_data,
- output io_score_rd_1_valid,
- output [4:0] io_score_rd_1_addr,
- output [31:0] io_score_rd_1_data,
- output io_score_rd_2_valid,
- output [4:0] io_score_rd_2_addr,
- output [31:0] io_score_rd_2_data,
- output io_score_rd_3_valid,
- output [4:0] io_score_rd_3_addr,
- output [31:0] io_score_rd_3_data,
- output io_score_mactive,
- output io_score_undef,
- output io_dbus_valid,
- input io_dbus_ready,
- output io_dbus_write,
- output [31:0] io_dbus_addr,
- output [31:0] io_dbus_adrx,
- output [5:0] io_dbus_size,
- output [255:0] io_dbus_wdata,
- output [31:0] io_dbus_wmask,
- input [255:0] io_dbus_rdata,
- output io_last,
- input io_ld_addr_ready,
- output io_ld_addr_valid,
- output [31:0] io_ld_addr_bits_addr,
- output [5:0] io_ld_addr_bits_id,
- input io_ld_data_valid,
- input [5:0] io_ld_data_bits_id,
- input [255:0] io_ld_data_bits_data,
- input io_st_addr_ready,
- output io_st_addr_valid,
- output [31:0] io_st_addr_bits_addr,
- output [5:0] io_st_addr_bits_id,
- input io_st_data_ready,
- output io_st_data_valid,
- output [255:0] io_st_data_bits_data,
- output [31:0] io_st_data_bits_strb,
- input io_st_resp_valid
-);
- wire vinst_clock; // @[VInst.scala 25:18]
- wire vinst_reset; // @[VInst.scala 25:18]
- wire vinst_io_in_0_valid; // @[VInst.scala 25:18]
- wire vinst_io_in_0_ready; // @[VInst.scala 25:18]
- wire [4:0] vinst_io_in_0_addr; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_in_0_inst; // @[VInst.scala 25:18]
- wire [4:0] vinst_io_in_0_op; // @[VInst.scala 25:18]
- wire vinst_io_in_1_valid; // @[VInst.scala 25:18]
- wire vinst_io_in_1_ready; // @[VInst.scala 25:18]
- wire [4:0] vinst_io_in_1_addr; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_in_1_inst; // @[VInst.scala 25:18]
- wire [4:0] vinst_io_in_1_op; // @[VInst.scala 25:18]
- wire vinst_io_in_2_valid; // @[VInst.scala 25:18]
- wire vinst_io_in_2_ready; // @[VInst.scala 25:18]
- wire [4:0] vinst_io_in_2_addr; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_in_2_inst; // @[VInst.scala 25:18]
- wire [4:0] vinst_io_in_2_op; // @[VInst.scala 25:18]
- wire vinst_io_in_3_valid; // @[VInst.scala 25:18]
- wire vinst_io_in_3_ready; // @[VInst.scala 25:18]
- wire [4:0] vinst_io_in_3_addr; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_in_3_inst; // @[VInst.scala 25:18]
- wire [4:0] vinst_io_in_3_op; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_rs_0_data; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_rs_1_data; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_rs_2_data; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_rs_3_data; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_rs_4_data; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_rs_5_data; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_rs_6_data; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_rs_7_data; // @[VInst.scala 25:18]
- wire vinst_io_rd_0_valid; // @[VInst.scala 25:18]
- wire [4:0] vinst_io_rd_0_addr; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_rd_0_data; // @[VInst.scala 25:18]
- wire vinst_io_rd_1_valid; // @[VInst.scala 25:18]
- wire [4:0] vinst_io_rd_1_addr; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_rd_1_data; // @[VInst.scala 25:18]
- wire vinst_io_rd_2_valid; // @[VInst.scala 25:18]
- wire [4:0] vinst_io_rd_2_addr; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_rd_2_data; // @[VInst.scala 25:18]
- wire vinst_io_rd_3_valid; // @[VInst.scala 25:18]
- wire [4:0] vinst_io_rd_3_addr; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_rd_3_data; // @[VInst.scala 25:18]
- wire vinst_io_out_valid; // @[VInst.scala 25:18]
- wire vinst_io_out_ready; // @[VInst.scala 25:18]
- wire vinst_io_out_stall; // @[VInst.scala 25:18]
- wire vinst_io_out_lane_0_valid; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_out_lane_0_bits_inst; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_out_lane_0_bits_addr; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_out_lane_0_bits_data; // @[VInst.scala 25:18]
- wire vinst_io_out_lane_1_valid; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_out_lane_1_bits_inst; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_out_lane_1_bits_addr; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_out_lane_1_bits_data; // @[VInst.scala 25:18]
- wire vinst_io_out_lane_2_valid; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_out_lane_2_bits_inst; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_out_lane_2_bits_addr; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_out_lane_2_bits_data; // @[VInst.scala 25:18]
- wire vinst_io_out_lane_3_valid; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_out_lane_3_bits_inst; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_out_lane_3_bits_addr; // @[VInst.scala 25:18]
- wire [31:0] vinst_io_out_lane_3_bits_data; // @[VInst.scala 25:18]
- wire vinst_io_nempty; // @[VInst.scala 25:18]
- wire vdec_clock; // @[VDecode.scala 25:18]
- wire vdec_reset; // @[VDecode.scala 25:18]
- wire vdec_io_in_ready; // @[VDecode.scala 25:18]
- wire vdec_io_in_valid; // @[VDecode.scala 25:18]
- wire vdec_io_in_bits_0_valid; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_in_bits_0_bits_inst; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_in_bits_0_bits_addr; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_in_bits_0_bits_data; // @[VDecode.scala 25:18]
- wire vdec_io_in_bits_1_valid; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_in_bits_1_bits_inst; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_in_bits_1_bits_addr; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_in_bits_1_bits_data; // @[VDecode.scala 25:18]
- wire vdec_io_in_bits_2_valid; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_in_bits_2_bits_inst; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_in_bits_2_bits_addr; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_in_bits_2_bits_data; // @[VDecode.scala 25:18]
- wire vdec_io_in_bits_3_valid; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_in_bits_3_bits_inst; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_in_bits_3_bits_addr; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_in_bits_3_bits_data; // @[VDecode.scala 25:18]
- wire vdec_io_out_0_ready; // @[VDecode.scala 25:18]
- wire vdec_io_out_0_valid; // @[VDecode.scala 25:18]
- wire [6:0] vdec_io_out_0_bits_op; // @[VDecode.scala 25:18]
- wire [2:0] vdec_io_out_0_bits_f2; // @[VDecode.scala 25:18]
- wire [2:0] vdec_io_out_0_bits_sz; // @[VDecode.scala 25:18]
- wire vdec_io_out_0_bits_m; // @[VDecode.scala 25:18]
- wire vdec_io_out_0_bits_vd_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_0_bits_vd_addr; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_0_bits_ve_addr; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_0_bits_vf_addr; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_0_bits_vg_addr; // @[VDecode.scala 25:18]
- wire vdec_io_out_0_bits_vs_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_0_bits_vs_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_0_bits_vs_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_0_bits_vt_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_0_bits_vt_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_0_bits_vt_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_0_bits_vu_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_0_bits_vu_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_0_bits_vu_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_0_bits_vx_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_0_bits_vx_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_0_bits_vx_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_0_bits_vy_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_0_bits_vy_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_0_bits_vy_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_0_bits_vz_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_0_bits_vz_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_0_bits_vz_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_0_bits_sv_valid; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_out_0_bits_sv_addr; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_out_0_bits_sv_data; // @[VDecode.scala 25:18]
- wire vdec_io_out_0_bits_cmdsync; // @[VDecode.scala 25:18]
- wire vdec_io_out_1_ready; // @[VDecode.scala 25:18]
- wire vdec_io_out_1_valid; // @[VDecode.scala 25:18]
- wire [6:0] vdec_io_out_1_bits_op; // @[VDecode.scala 25:18]
- wire [2:0] vdec_io_out_1_bits_f2; // @[VDecode.scala 25:18]
- wire [2:0] vdec_io_out_1_bits_sz; // @[VDecode.scala 25:18]
- wire vdec_io_out_1_bits_m; // @[VDecode.scala 25:18]
- wire vdec_io_out_1_bits_vd_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_1_bits_vd_addr; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_1_bits_ve_addr; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_1_bits_vf_addr; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_1_bits_vg_addr; // @[VDecode.scala 25:18]
- wire vdec_io_out_1_bits_vs_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_1_bits_vs_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_1_bits_vs_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_1_bits_vt_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_1_bits_vt_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_1_bits_vt_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_1_bits_vu_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_1_bits_vu_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_1_bits_vu_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_1_bits_vx_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_1_bits_vx_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_1_bits_vx_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_1_bits_vy_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_1_bits_vy_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_1_bits_vy_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_1_bits_vz_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_1_bits_vz_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_1_bits_vz_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_1_bits_sv_valid; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_out_1_bits_sv_addr; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_out_1_bits_sv_data; // @[VDecode.scala 25:18]
- wire vdec_io_out_1_bits_cmdsync; // @[VDecode.scala 25:18]
- wire vdec_io_out_2_ready; // @[VDecode.scala 25:18]
- wire vdec_io_out_2_valid; // @[VDecode.scala 25:18]
- wire [6:0] vdec_io_out_2_bits_op; // @[VDecode.scala 25:18]
- wire [2:0] vdec_io_out_2_bits_f2; // @[VDecode.scala 25:18]
- wire [2:0] vdec_io_out_2_bits_sz; // @[VDecode.scala 25:18]
- wire vdec_io_out_2_bits_m; // @[VDecode.scala 25:18]
- wire vdec_io_out_2_bits_vd_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_2_bits_vd_addr; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_2_bits_ve_addr; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_2_bits_vf_addr; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_2_bits_vg_addr; // @[VDecode.scala 25:18]
- wire vdec_io_out_2_bits_vs_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_2_bits_vs_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_2_bits_vs_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_2_bits_vt_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_2_bits_vt_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_2_bits_vt_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_2_bits_vu_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_2_bits_vu_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_2_bits_vu_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_2_bits_vx_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_2_bits_vx_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_2_bits_vx_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_2_bits_vy_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_2_bits_vy_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_2_bits_vy_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_2_bits_vz_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_2_bits_vz_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_2_bits_vz_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_2_bits_sv_valid; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_out_2_bits_sv_addr; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_out_2_bits_sv_data; // @[VDecode.scala 25:18]
- wire vdec_io_out_2_bits_cmdsync; // @[VDecode.scala 25:18]
- wire vdec_io_out_3_ready; // @[VDecode.scala 25:18]
- wire vdec_io_out_3_valid; // @[VDecode.scala 25:18]
- wire [6:0] vdec_io_out_3_bits_op; // @[VDecode.scala 25:18]
- wire [2:0] vdec_io_out_3_bits_f2; // @[VDecode.scala 25:18]
- wire [2:0] vdec_io_out_3_bits_sz; // @[VDecode.scala 25:18]
- wire vdec_io_out_3_bits_m; // @[VDecode.scala 25:18]
- wire vdec_io_out_3_bits_vd_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_3_bits_vd_addr; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_3_bits_ve_addr; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_3_bits_vf_addr; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_3_bits_vg_addr; // @[VDecode.scala 25:18]
- wire vdec_io_out_3_bits_vs_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_3_bits_vs_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_3_bits_vs_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_3_bits_vt_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_3_bits_vt_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_3_bits_vt_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_3_bits_vu_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_3_bits_vu_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_3_bits_vu_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_3_bits_vx_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_3_bits_vx_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_3_bits_vx_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_3_bits_vy_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_3_bits_vy_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_3_bits_vy_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_3_bits_vz_valid; // @[VDecode.scala 25:18]
- wire [5:0] vdec_io_out_3_bits_vz_addr; // @[VDecode.scala 25:18]
- wire [3:0] vdec_io_out_3_bits_vz_tag; // @[VDecode.scala 25:18]
- wire vdec_io_out_3_bits_sv_valid; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_out_3_bits_sv_addr; // @[VDecode.scala 25:18]
- wire [31:0] vdec_io_out_3_bits_sv_data; // @[VDecode.scala 25:18]
- wire vdec_io_out_3_bits_cmdsync; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_0_alu; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_0_conv; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_0_ldst; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_0_ld; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_0_st; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_1_alu; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_1_conv; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_1_ldst; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_1_ld; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_1_st; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_2_alu; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_2_conv; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_2_ldst; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_2_ld; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_2_st; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_3_alu; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_3_conv; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_3_ldst; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_3_ld; // @[VDecode.scala 25:18]
- wire vdec_io_cmdq_3_st; // @[VDecode.scala 25:18]
- wire vdec_io_stall; // @[VDecode.scala 25:18]
- wire [63:0] vdec_io_active; // @[VDecode.scala 25:18]
- wire vdec_io_vrfsb_set_valid; // @[VDecode.scala 25:18]
- wire [127:0] vdec_io_vrfsb_set_bits; // @[VDecode.scala 25:18]
- wire [127:0] vdec_io_vrfsb_data; // @[VDecode.scala 25:18]
- wire vdec_io_undef; // @[VDecode.scala 25:18]
- wire vdec_io_nempty; // @[VDecode.scala 25:18]
- wire valu_clock; // @[VAlu.scala 25:18]
- wire valu_reset; // @[VAlu.scala 25:18]
- wire valu_io_in_ready; // @[VAlu.scala 25:18]
- wire valu_io_in_valid; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_0_valid; // @[VAlu.scala 25:18]
- wire [6:0] valu_io_in_bits_0_bits_op; // @[VAlu.scala 25:18]
- wire [2:0] valu_io_in_bits_0_bits_f2; // @[VAlu.scala 25:18]
- wire [2:0] valu_io_in_bits_0_bits_sz; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_0_bits_m; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_0_bits_vd_addr; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_0_bits_ve_addr; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_0_bits_vf_addr; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_0_bits_vg_addr; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_0_bits_vs_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_0_bits_vs_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_0_bits_vs_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_0_bits_vt_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_0_bits_vt_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_0_bits_vt_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_0_bits_vu_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_0_bits_vu_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_0_bits_vu_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_0_bits_vx_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_0_bits_vx_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_0_bits_vx_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_0_bits_vy_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_0_bits_vy_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_0_bits_vy_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_0_bits_vz_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_0_bits_vz_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_0_bits_vz_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_0_bits_sv_valid; // @[VAlu.scala 25:18]
- wire [31:0] valu_io_in_bits_0_bits_sv_data; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_0_bits_cmdsync; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_1_valid; // @[VAlu.scala 25:18]
- wire [6:0] valu_io_in_bits_1_bits_op; // @[VAlu.scala 25:18]
- wire [2:0] valu_io_in_bits_1_bits_f2; // @[VAlu.scala 25:18]
- wire [2:0] valu_io_in_bits_1_bits_sz; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_1_bits_m; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_1_bits_vd_addr; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_1_bits_ve_addr; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_1_bits_vf_addr; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_1_bits_vg_addr; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_1_bits_vs_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_1_bits_vs_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_1_bits_vs_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_1_bits_vt_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_1_bits_vt_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_1_bits_vt_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_1_bits_vu_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_1_bits_vu_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_1_bits_vu_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_1_bits_vx_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_1_bits_vx_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_1_bits_vx_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_1_bits_vy_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_1_bits_vy_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_1_bits_vy_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_1_bits_vz_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_1_bits_vz_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_1_bits_vz_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_1_bits_sv_valid; // @[VAlu.scala 25:18]
- wire [31:0] valu_io_in_bits_1_bits_sv_data; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_1_bits_cmdsync; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_2_valid; // @[VAlu.scala 25:18]
- wire [6:0] valu_io_in_bits_2_bits_op; // @[VAlu.scala 25:18]
- wire [2:0] valu_io_in_bits_2_bits_f2; // @[VAlu.scala 25:18]
- wire [2:0] valu_io_in_bits_2_bits_sz; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_2_bits_m; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_2_bits_vd_addr; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_2_bits_ve_addr; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_2_bits_vf_addr; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_2_bits_vg_addr; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_2_bits_vs_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_2_bits_vs_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_2_bits_vs_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_2_bits_vt_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_2_bits_vt_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_2_bits_vt_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_2_bits_vu_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_2_bits_vu_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_2_bits_vu_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_2_bits_vx_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_2_bits_vx_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_2_bits_vx_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_2_bits_vy_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_2_bits_vy_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_2_bits_vy_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_2_bits_vz_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_2_bits_vz_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_2_bits_vz_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_2_bits_sv_valid; // @[VAlu.scala 25:18]
- wire [31:0] valu_io_in_bits_2_bits_sv_data; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_2_bits_cmdsync; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_3_valid; // @[VAlu.scala 25:18]
- wire [6:0] valu_io_in_bits_3_bits_op; // @[VAlu.scala 25:18]
- wire [2:0] valu_io_in_bits_3_bits_f2; // @[VAlu.scala 25:18]
- wire [2:0] valu_io_in_bits_3_bits_sz; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_3_bits_m; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_3_bits_vd_addr; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_3_bits_ve_addr; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_3_bits_vf_addr; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_3_bits_vg_addr; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_3_bits_vs_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_3_bits_vs_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_3_bits_vs_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_3_bits_vt_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_3_bits_vt_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_3_bits_vt_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_3_bits_vu_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_3_bits_vu_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_3_bits_vu_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_3_bits_vx_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_3_bits_vx_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_3_bits_vx_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_3_bits_vy_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_3_bits_vy_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_3_bits_vy_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_3_bits_vz_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_in_bits_3_bits_vz_addr; // @[VAlu.scala 25:18]
- wire [3:0] valu_io_in_bits_3_bits_vz_tag; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_3_bits_sv_valid; // @[VAlu.scala 25:18]
- wire [31:0] valu_io_in_bits_3_bits_sv_data; // @[VAlu.scala 25:18]
- wire valu_io_in_bits_3_bits_cmdsync; // @[VAlu.scala 25:18]
- wire [63:0] valu_io_active; // @[VAlu.scala 25:18]
- wire [127:0] valu_io_vrfsb; // @[VAlu.scala 25:18]
- wire valu_io_read_0_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_read_0_addr; // @[VAlu.scala 25:18]
- wire [255:0] valu_io_read_0_data; // @[VAlu.scala 25:18]
- wire valu_io_read_1_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_read_1_addr; // @[VAlu.scala 25:18]
- wire [255:0] valu_io_read_1_data; // @[VAlu.scala 25:18]
- wire valu_io_read_2_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_read_2_addr; // @[VAlu.scala 25:18]
- wire [255:0] valu_io_read_2_data; // @[VAlu.scala 25:18]
- wire valu_io_read_3_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_read_3_addr; // @[VAlu.scala 25:18]
- wire [255:0] valu_io_read_3_data; // @[VAlu.scala 25:18]
- wire valu_io_read_4_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_read_4_addr; // @[VAlu.scala 25:18]
- wire [255:0] valu_io_read_4_data; // @[VAlu.scala 25:18]
- wire valu_io_read_5_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_read_5_addr; // @[VAlu.scala 25:18]
- wire [255:0] valu_io_read_5_data; // @[VAlu.scala 25:18]
- wire valu_io_write_0_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_write_0_addr; // @[VAlu.scala 25:18]
- wire [255:0] valu_io_write_0_data; // @[VAlu.scala 25:18]
- wire valu_io_write_1_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_write_1_addr; // @[VAlu.scala 25:18]
- wire [255:0] valu_io_write_1_data; // @[VAlu.scala 25:18]
- wire valu_io_write_2_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_write_2_addr; // @[VAlu.scala 25:18]
- wire [255:0] valu_io_write_2_data; // @[VAlu.scala 25:18]
- wire valu_io_write_3_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_write_3_addr; // @[VAlu.scala 25:18]
- wire [255:0] valu_io_write_3_data; // @[VAlu.scala 25:18]
- wire valu_io_whint_0_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_whint_0_addr; // @[VAlu.scala 25:18]
- wire valu_io_whint_1_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_whint_1_addr; // @[VAlu.scala 25:18]
- wire valu_io_whint_2_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_whint_2_addr; // @[VAlu.scala 25:18]
- wire valu_io_whint_3_valid; // @[VAlu.scala 25:18]
- wire [5:0] valu_io_whint_3_addr; // @[VAlu.scala 25:18]
- wire valu_io_scalar_0_valid; // @[VAlu.scala 25:18]
- wire [31:0] valu_io_scalar_0_data; // @[VAlu.scala 25:18]
- wire valu_io_scalar_1_valid; // @[VAlu.scala 25:18]
- wire [31:0] valu_io_scalar_1_data; // @[VAlu.scala 25:18]
- wire vconv_clock; // @[VConvCtrl.scala 25:18]
- wire vconv_reset; // @[VConvCtrl.scala 25:18]
- wire vconv_io_in_ready; // @[VConvCtrl.scala 25:18]
- wire vconv_io_in_valid; // @[VConvCtrl.scala 25:18]
- wire vconv_io_in_bits_0_valid; // @[VConvCtrl.scala 25:18]
- wire [6:0] vconv_io_in_bits_0_bits_op; // @[VConvCtrl.scala 25:18]
- wire vconv_io_in_bits_0_bits_m; // @[VConvCtrl.scala 25:18]
- wire [5:0] vconv_io_in_bits_0_bits_vs_addr; // @[VConvCtrl.scala 25:18]
- wire [5:0] vconv_io_in_bits_0_bits_vu_addr; // @[VConvCtrl.scala 25:18]
- wire [31:0] vconv_io_in_bits_0_bits_sv_data; // @[VConvCtrl.scala 25:18]
- wire vconv_io_in_bits_1_valid; // @[VConvCtrl.scala 25:18]
- wire [6:0] vconv_io_in_bits_1_bits_op; // @[VConvCtrl.scala 25:18]
- wire vconv_io_in_bits_1_bits_m; // @[VConvCtrl.scala 25:18]
- wire [5:0] vconv_io_in_bits_1_bits_vs_addr; // @[VConvCtrl.scala 25:18]
- wire [5:0] vconv_io_in_bits_1_bits_vu_addr; // @[VConvCtrl.scala 25:18]
- wire [31:0] vconv_io_in_bits_1_bits_sv_data; // @[VConvCtrl.scala 25:18]
- wire vconv_io_in_bits_2_valid; // @[VConvCtrl.scala 25:18]
- wire [6:0] vconv_io_in_bits_2_bits_op; // @[VConvCtrl.scala 25:18]
- wire vconv_io_in_bits_2_bits_m; // @[VConvCtrl.scala 25:18]
- wire [5:0] vconv_io_in_bits_2_bits_vs_addr; // @[VConvCtrl.scala 25:18]
- wire [5:0] vconv_io_in_bits_2_bits_vu_addr; // @[VConvCtrl.scala 25:18]
- wire [31:0] vconv_io_in_bits_2_bits_sv_data; // @[VConvCtrl.scala 25:18]
- wire vconv_io_in_bits_3_valid; // @[VConvCtrl.scala 25:18]
- wire [6:0] vconv_io_in_bits_3_bits_op; // @[VConvCtrl.scala 25:18]
- wire vconv_io_in_bits_3_bits_m; // @[VConvCtrl.scala 25:18]
- wire [5:0] vconv_io_in_bits_3_bits_vs_addr; // @[VConvCtrl.scala 25:18]
- wire [5:0] vconv_io_in_bits_3_bits_vu_addr; // @[VConvCtrl.scala 25:18]
- wire [31:0] vconv_io_in_bits_3_bits_sv_data; // @[VConvCtrl.scala 25:18]
- wire [63:0] vconv_io_active; // @[VConvCtrl.scala 25:18]
- wire [127:0] vconv_io_vrfsb; // @[VConvCtrl.scala 25:18]
- wire vconv_io_out_valid; // @[VConvCtrl.scala 25:18]
- wire vconv_io_out_ready; // @[VConvCtrl.scala 25:18]
- wire vconv_io_out_op_conv; // @[VConvCtrl.scala 25:18]
- wire vconv_io_out_op_init; // @[VConvCtrl.scala 25:18]
- wire vconv_io_out_op_tran; // @[VConvCtrl.scala 25:18]
- wire vconv_io_out_op_wclr; // @[VConvCtrl.scala 25:18]
- wire [5:0] vconv_io_out_addr1; // @[VConvCtrl.scala 25:18]
- wire [5:0] vconv_io_out_addr2; // @[VConvCtrl.scala 25:18]
- wire [1:0] vconv_io_out_mode; // @[VConvCtrl.scala 25:18]
- wire [2:0] vconv_io_out_index; // @[VConvCtrl.scala 25:18]
- wire [8:0] vconv_io_out_abias; // @[VConvCtrl.scala 25:18]
- wire [8:0] vconv_io_out_bbias; // @[VConvCtrl.scala 25:18]
- wire vconv_io_out_asign; // @[VConvCtrl.scala 25:18]
- wire vconv_io_out_bsign; // @[VConvCtrl.scala 25:18]
- wire vldst_clock; // @[VLdSt.scala 25:18]
- wire vldst_reset; // @[VLdSt.scala 25:18]
- wire vldst_io_in_ready; // @[VLdSt.scala 25:18]
- wire vldst_io_in_valid; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_0_valid; // @[VLdSt.scala 25:18]
- wire [6:0] vldst_io_in_bits_0_bits_op; // @[VLdSt.scala 25:18]
- wire [2:0] vldst_io_in_bits_0_bits_f2; // @[VLdSt.scala 25:18]
- wire [2:0] vldst_io_in_bits_0_bits_sz; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_0_bits_m; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_0_bits_vd_valid; // @[VLdSt.scala 25:18]
- wire [5:0] vldst_io_in_bits_0_bits_vd_addr; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_0_bits_vs_valid; // @[VLdSt.scala 25:18]
- wire [5:0] vldst_io_in_bits_0_bits_vs_addr; // @[VLdSt.scala 25:18]
- wire [3:0] vldst_io_in_bits_0_bits_vs_tag; // @[VLdSt.scala 25:18]
- wire [31:0] vldst_io_in_bits_0_bits_sv_addr; // @[VLdSt.scala 25:18]
- wire [31:0] vldst_io_in_bits_0_bits_sv_data; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_1_valid; // @[VLdSt.scala 25:18]
- wire [6:0] vldst_io_in_bits_1_bits_op; // @[VLdSt.scala 25:18]
- wire [2:0] vldst_io_in_bits_1_bits_f2; // @[VLdSt.scala 25:18]
- wire [2:0] vldst_io_in_bits_1_bits_sz; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_1_bits_m; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_1_bits_vd_valid; // @[VLdSt.scala 25:18]
- wire [5:0] vldst_io_in_bits_1_bits_vd_addr; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_1_bits_vs_valid; // @[VLdSt.scala 25:18]
- wire [5:0] vldst_io_in_bits_1_bits_vs_addr; // @[VLdSt.scala 25:18]
- wire [3:0] vldst_io_in_bits_1_bits_vs_tag; // @[VLdSt.scala 25:18]
- wire [31:0] vldst_io_in_bits_1_bits_sv_addr; // @[VLdSt.scala 25:18]
- wire [31:0] vldst_io_in_bits_1_bits_sv_data; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_2_valid; // @[VLdSt.scala 25:18]
- wire [6:0] vldst_io_in_bits_2_bits_op; // @[VLdSt.scala 25:18]
- wire [2:0] vldst_io_in_bits_2_bits_f2; // @[VLdSt.scala 25:18]
- wire [2:0] vldst_io_in_bits_2_bits_sz; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_2_bits_m; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_2_bits_vd_valid; // @[VLdSt.scala 25:18]
- wire [5:0] vldst_io_in_bits_2_bits_vd_addr; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_2_bits_vs_valid; // @[VLdSt.scala 25:18]
- wire [5:0] vldst_io_in_bits_2_bits_vs_addr; // @[VLdSt.scala 25:18]
- wire [3:0] vldst_io_in_bits_2_bits_vs_tag; // @[VLdSt.scala 25:18]
- wire [31:0] vldst_io_in_bits_2_bits_sv_addr; // @[VLdSt.scala 25:18]
- wire [31:0] vldst_io_in_bits_2_bits_sv_data; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_3_valid; // @[VLdSt.scala 25:18]
- wire [6:0] vldst_io_in_bits_3_bits_op; // @[VLdSt.scala 25:18]
- wire [2:0] vldst_io_in_bits_3_bits_f2; // @[VLdSt.scala 25:18]
- wire [2:0] vldst_io_in_bits_3_bits_sz; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_3_bits_m; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_3_bits_vd_valid; // @[VLdSt.scala 25:18]
- wire [5:0] vldst_io_in_bits_3_bits_vd_addr; // @[VLdSt.scala 25:18]
- wire vldst_io_in_bits_3_bits_vs_valid; // @[VLdSt.scala 25:18]
- wire [5:0] vldst_io_in_bits_3_bits_vs_addr; // @[VLdSt.scala 25:18]
- wire [3:0] vldst_io_in_bits_3_bits_vs_tag; // @[VLdSt.scala 25:18]
- wire [31:0] vldst_io_in_bits_3_bits_sv_addr; // @[VLdSt.scala 25:18]
- wire [31:0] vldst_io_in_bits_3_bits_sv_data; // @[VLdSt.scala 25:18]
- wire [63:0] vldst_io_active; // @[VLdSt.scala 25:18]
- wire [127:0] vldst_io_vrfsb; // @[VLdSt.scala 25:18]
- wire vldst_io_read_valid; // @[VLdSt.scala 25:18]
- wire vldst_io_read_ready; // @[VLdSt.scala 25:18]
- wire [5:0] vldst_io_read_addr; // @[VLdSt.scala 25:18]
- wire [255:0] vldst_io_read_data; // @[VLdSt.scala 25:18]
- wire vldst_io_write_valid; // @[VLdSt.scala 25:18]
- wire [5:0] vldst_io_write_addr; // @[VLdSt.scala 25:18]
- wire [255:0] vldst_io_write_data; // @[VLdSt.scala 25:18]
- wire vldst_io_dbus_valid; // @[VLdSt.scala 25:18]
- wire vldst_io_dbus_ready; // @[VLdSt.scala 25:18]
- wire vldst_io_dbus_write; // @[VLdSt.scala 25:18]
- wire [31:0] vldst_io_dbus_addr; // @[VLdSt.scala 25:18]
- wire [31:0] vldst_io_dbus_adrx; // @[VLdSt.scala 25:18]
- wire [5:0] vldst_io_dbus_size; // @[VLdSt.scala 25:18]
- wire [255:0] vldst_io_dbus_wdata; // @[VLdSt.scala 25:18]
- wire [31:0] vldst_io_dbus_wmask; // @[VLdSt.scala 25:18]
- wire [255:0] vldst_io_dbus_rdata; // @[VLdSt.scala 25:18]
- wire vldst_io_last; // @[VLdSt.scala 25:18]
- wire vld_clock; // @[VLd.scala 25:18]
- wire vld_reset; // @[VLd.scala 25:18]
- wire vld_io_in_ready; // @[VLd.scala 25:18]
- wire vld_io_in_valid; // @[VLd.scala 25:18]
- wire vld_io_in_bits_0_valid; // @[VLd.scala 25:18]
- wire [6:0] vld_io_in_bits_0_bits_op; // @[VLd.scala 25:18]
- wire [2:0] vld_io_in_bits_0_bits_f2; // @[VLd.scala 25:18]
- wire [2:0] vld_io_in_bits_0_bits_sz; // @[VLd.scala 25:18]
- wire vld_io_in_bits_0_bits_m; // @[VLd.scala 25:18]
- wire vld_io_in_bits_0_bits_vd_valid; // @[VLd.scala 25:18]
- wire [5:0] vld_io_in_bits_0_bits_vd_addr; // @[VLd.scala 25:18]
- wire vld_io_in_bits_0_bits_vs_valid; // @[VLd.scala 25:18]
- wire [31:0] vld_io_in_bits_0_bits_sv_addr; // @[VLd.scala 25:18]
- wire [31:0] vld_io_in_bits_0_bits_sv_data; // @[VLd.scala 25:18]
- wire vld_io_in_bits_1_valid; // @[VLd.scala 25:18]
- wire [6:0] vld_io_in_bits_1_bits_op; // @[VLd.scala 25:18]
- wire [2:0] vld_io_in_bits_1_bits_f2; // @[VLd.scala 25:18]
- wire [2:0] vld_io_in_bits_1_bits_sz; // @[VLd.scala 25:18]
- wire vld_io_in_bits_1_bits_m; // @[VLd.scala 25:18]
- wire vld_io_in_bits_1_bits_vd_valid; // @[VLd.scala 25:18]
- wire [5:0] vld_io_in_bits_1_bits_vd_addr; // @[VLd.scala 25:18]
- wire vld_io_in_bits_1_bits_vs_valid; // @[VLd.scala 25:18]
- wire [31:0] vld_io_in_bits_1_bits_sv_addr; // @[VLd.scala 25:18]
- wire [31:0] vld_io_in_bits_1_bits_sv_data; // @[VLd.scala 25:18]
- wire vld_io_in_bits_2_valid; // @[VLd.scala 25:18]
- wire [6:0] vld_io_in_bits_2_bits_op; // @[VLd.scala 25:18]
- wire [2:0] vld_io_in_bits_2_bits_f2; // @[VLd.scala 25:18]
- wire [2:0] vld_io_in_bits_2_bits_sz; // @[VLd.scala 25:18]
- wire vld_io_in_bits_2_bits_m; // @[VLd.scala 25:18]
- wire vld_io_in_bits_2_bits_vd_valid; // @[VLd.scala 25:18]
- wire [5:0] vld_io_in_bits_2_bits_vd_addr; // @[VLd.scala 25:18]
- wire vld_io_in_bits_2_bits_vs_valid; // @[VLd.scala 25:18]
- wire [31:0] vld_io_in_bits_2_bits_sv_addr; // @[VLd.scala 25:18]
- wire [31:0] vld_io_in_bits_2_bits_sv_data; // @[VLd.scala 25:18]
- wire vld_io_in_bits_3_valid; // @[VLd.scala 25:18]
- wire [6:0] vld_io_in_bits_3_bits_op; // @[VLd.scala 25:18]
- wire [2:0] vld_io_in_bits_3_bits_f2; // @[VLd.scala 25:18]
- wire [2:0] vld_io_in_bits_3_bits_sz; // @[VLd.scala 25:18]
- wire vld_io_in_bits_3_bits_m; // @[VLd.scala 25:18]
- wire vld_io_in_bits_3_bits_vd_valid; // @[VLd.scala 25:18]
- wire [5:0] vld_io_in_bits_3_bits_vd_addr; // @[VLd.scala 25:18]
- wire vld_io_in_bits_3_bits_vs_valid; // @[VLd.scala 25:18]
- wire [31:0] vld_io_in_bits_3_bits_sv_addr; // @[VLd.scala 25:18]
- wire [31:0] vld_io_in_bits_3_bits_sv_data; // @[VLd.scala 25:18]
- wire vld_io_write_valid; // @[VLd.scala 25:18]
- wire [5:0] vld_io_write_addr; // @[VLd.scala 25:18]
- wire [255:0] vld_io_write_data; // @[VLd.scala 25:18]
- wire vld_io_axi_addr_ready; // @[VLd.scala 25:18]
- wire vld_io_axi_addr_valid; // @[VLd.scala 25:18]
- wire [31:0] vld_io_axi_addr_bits_addr; // @[VLd.scala 25:18]
- wire [5:0] vld_io_axi_addr_bits_id; // @[VLd.scala 25:18]
- wire vld_io_axi_data_ready; // @[VLd.scala 25:18]
- wire vld_io_axi_data_valid; // @[VLd.scala 25:18]
- wire [5:0] vld_io_axi_data_bits_id; // @[VLd.scala 25:18]
- wire [255:0] vld_io_axi_data_bits_data; // @[VLd.scala 25:18]
- wire vld_io_nempty; // @[VLd.scala 25:18]
- wire vst_clock; // @[VSt.scala 25:18]
- wire vst_reset; // @[VSt.scala 25:18]
- wire vst_io_in_ready; // @[VSt.scala 25:18]
- wire vst_io_in_valid; // @[VSt.scala 25:18]
- wire vst_io_in_bits_0_valid; // @[VSt.scala 25:18]
- wire [6:0] vst_io_in_bits_0_bits_op; // @[VSt.scala 25:18]
- wire [2:0] vst_io_in_bits_0_bits_f2; // @[VSt.scala 25:18]
- wire [2:0] vst_io_in_bits_0_bits_sz; // @[VSt.scala 25:18]
- wire vst_io_in_bits_0_bits_m; // @[VSt.scala 25:18]
- wire vst_io_in_bits_0_bits_vs_valid; // @[VSt.scala 25:18]
- wire [5:0] vst_io_in_bits_0_bits_vs_addr; // @[VSt.scala 25:18]
- wire [3:0] vst_io_in_bits_0_bits_vs_tag; // @[VSt.scala 25:18]
- wire [31:0] vst_io_in_bits_0_bits_sv_addr; // @[VSt.scala 25:18]
- wire [31:0] vst_io_in_bits_0_bits_sv_data; // @[VSt.scala 25:18]
- wire vst_io_in_bits_1_valid; // @[VSt.scala 25:18]
- wire [6:0] vst_io_in_bits_1_bits_op; // @[VSt.scala 25:18]
- wire [2:0] vst_io_in_bits_1_bits_f2; // @[VSt.scala 25:18]
- wire [2:0] vst_io_in_bits_1_bits_sz; // @[VSt.scala 25:18]
- wire vst_io_in_bits_1_bits_m; // @[VSt.scala 25:18]
- wire vst_io_in_bits_1_bits_vs_valid; // @[VSt.scala 25:18]
- wire [5:0] vst_io_in_bits_1_bits_vs_addr; // @[VSt.scala 25:18]
- wire [3:0] vst_io_in_bits_1_bits_vs_tag; // @[VSt.scala 25:18]
- wire [31:0] vst_io_in_bits_1_bits_sv_addr; // @[VSt.scala 25:18]
- wire [31:0] vst_io_in_bits_1_bits_sv_data; // @[VSt.scala 25:18]
- wire vst_io_in_bits_2_valid; // @[VSt.scala 25:18]
- wire [6:0] vst_io_in_bits_2_bits_op; // @[VSt.scala 25:18]
- wire [2:0] vst_io_in_bits_2_bits_f2; // @[VSt.scala 25:18]
- wire [2:0] vst_io_in_bits_2_bits_sz; // @[VSt.scala 25:18]
- wire vst_io_in_bits_2_bits_m; // @[VSt.scala 25:18]
- wire vst_io_in_bits_2_bits_vs_valid; // @[VSt.scala 25:18]
- wire [5:0] vst_io_in_bits_2_bits_vs_addr; // @[VSt.scala 25:18]
- wire [3:0] vst_io_in_bits_2_bits_vs_tag; // @[VSt.scala 25:18]
- wire [31:0] vst_io_in_bits_2_bits_sv_addr; // @[VSt.scala 25:18]
- wire [31:0] vst_io_in_bits_2_bits_sv_data; // @[VSt.scala 25:18]
- wire vst_io_in_bits_3_valid; // @[VSt.scala 25:18]
- wire [6:0] vst_io_in_bits_3_bits_op; // @[VSt.scala 25:18]
- wire [2:0] vst_io_in_bits_3_bits_f2; // @[VSt.scala 25:18]
- wire [2:0] vst_io_in_bits_3_bits_sz; // @[VSt.scala 25:18]
- wire vst_io_in_bits_3_bits_m; // @[VSt.scala 25:18]
- wire vst_io_in_bits_3_bits_vs_valid; // @[VSt.scala 25:18]
- wire [5:0] vst_io_in_bits_3_bits_vs_addr; // @[VSt.scala 25:18]
- wire [3:0] vst_io_in_bits_3_bits_vs_tag; // @[VSt.scala 25:18]
- wire [31:0] vst_io_in_bits_3_bits_sv_addr; // @[VSt.scala 25:18]
- wire [31:0] vst_io_in_bits_3_bits_sv_data; // @[VSt.scala 25:18]
- wire [63:0] vst_io_active; // @[VSt.scala 25:18]
- wire [127:0] vst_io_vrfsb; // @[VSt.scala 25:18]
- wire vst_io_read_valid; // @[VSt.scala 25:18]
- wire vst_io_read_ready; // @[VSt.scala 25:18]
- wire [5:0] vst_io_read_addr; // @[VSt.scala 25:18]
- wire [255:0] vst_io_read_data; // @[VSt.scala 25:18]
- wire vst_io_axi_addr_ready; // @[VSt.scala 25:18]
- wire vst_io_axi_addr_valid; // @[VSt.scala 25:18]
- wire [31:0] vst_io_axi_addr_bits_addr; // @[VSt.scala 25:18]
- wire [5:0] vst_io_axi_addr_bits_id; // @[VSt.scala 25:18]
- wire vst_io_axi_data_ready; // @[VSt.scala 25:18]
- wire vst_io_axi_data_valid; // @[VSt.scala 25:18]
- wire [255:0] vst_io_axi_data_bits_data; // @[VSt.scala 25:18]
- wire [31:0] vst_io_axi_data_bits_strb; // @[VSt.scala 25:18]
- wire vst_io_axi_resp_ready; // @[VSt.scala 25:18]
- wire vst_io_axi_resp_valid; // @[VSt.scala 25:18]
- wire vst_io_nempty; // @[VSt.scala 25:18]
- wire vrf_clock; // @[VRegfile.scala 25:18]
- wire vrf_reset; // @[VRegfile.scala 25:18]
- wire vrf_io_read_0_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_read_0_addr; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_read_0_data; // @[VRegfile.scala 25:18]
- wire vrf_io_read_1_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_read_1_addr; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_read_1_data; // @[VRegfile.scala 25:18]
- wire vrf_io_read_2_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_read_2_addr; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_read_2_data; // @[VRegfile.scala 25:18]
- wire vrf_io_read_3_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_read_3_addr; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_read_3_data; // @[VRegfile.scala 25:18]
- wire vrf_io_read_4_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_read_4_addr; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_read_4_data; // @[VRegfile.scala 25:18]
- wire vrf_io_read_5_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_read_5_addr; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_read_5_data; // @[VRegfile.scala 25:18]
- wire vrf_io_read_6_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_read_6_addr; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_read_6_data; // @[VRegfile.scala 25:18]
- wire vrf_io_scalar_0_valid; // @[VRegfile.scala 25:18]
- wire [31:0] vrf_io_scalar_0_data; // @[VRegfile.scala 25:18]
- wire vrf_io_scalar_1_valid; // @[VRegfile.scala 25:18]
- wire [31:0] vrf_io_scalar_1_data; // @[VRegfile.scala 25:18]
- wire vrf_io_write_0_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_write_0_addr; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_write_0_data; // @[VRegfile.scala 25:18]
- wire vrf_io_write_1_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_write_1_addr; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_write_1_data; // @[VRegfile.scala 25:18]
- wire vrf_io_write_2_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_write_2_addr; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_write_2_data; // @[VRegfile.scala 25:18]
- wire vrf_io_write_3_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_write_3_addr; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_write_3_data; // @[VRegfile.scala 25:18]
- wire vrf_io_write_4_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_write_4_addr; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_write_4_data; // @[VRegfile.scala 25:18]
- wire vrf_io_write_5_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_write_5_addr; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_write_5_data; // @[VRegfile.scala 25:18]
- wire vrf_io_whint_0_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_whint_0_addr; // @[VRegfile.scala 25:18]
- wire vrf_io_whint_1_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_whint_1_addr; // @[VRegfile.scala 25:18]
- wire vrf_io_whint_2_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_whint_2_addr; // @[VRegfile.scala 25:18]
- wire vrf_io_whint_3_valid; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_whint_3_addr; // @[VRegfile.scala 25:18]
- wire vrf_io_conv_valid; // @[VRegfile.scala 25:18]
- wire vrf_io_conv_ready; // @[VRegfile.scala 25:18]
- wire vrf_io_conv_op_conv; // @[VRegfile.scala 25:18]
- wire vrf_io_conv_op_init; // @[VRegfile.scala 25:18]
- wire vrf_io_conv_op_tran; // @[VRegfile.scala 25:18]
- wire vrf_io_conv_op_wclr; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_conv_addr1; // @[VRegfile.scala 25:18]
- wire [5:0] vrf_io_conv_addr2; // @[VRegfile.scala 25:18]
- wire [1:0] vrf_io_conv_mode; // @[VRegfile.scala 25:18]
- wire [2:0] vrf_io_conv_index; // @[VRegfile.scala 25:18]
- wire [8:0] vrf_io_conv_abias; // @[VRegfile.scala 25:18]
- wire [8:0] vrf_io_conv_bbias; // @[VRegfile.scala 25:18]
- wire vrf_io_conv_asign; // @[VRegfile.scala 25:18]
- wire vrf_io_conv_bsign; // @[VRegfile.scala 25:18]
- wire [255:0] vrf_io_transpose_data; // @[VRegfile.scala 25:18]
- wire vrf_io_vrfsb_set_valid; // @[VRegfile.scala 25:18]
- wire [127:0] vrf_io_vrfsb_set_bits; // @[VRegfile.scala 25:18]
- wire [127:0] vrf_io_vrfsb_data; // @[VRegfile.scala 25:18]
- wire _T = vst_io_read_valid & vst_io_read_ready; // @[VCore.scala 79:41]
- wire _T_1 = vldst_io_read_valid & vldst_io_read_ready; // @[VCore.scala 80:43]
- wire [1:0] _T_2 = {_T,_T_1}; // @[Cat.scala 31:58]
- wire [1:0] _T_5 = _T_2[0] + _T_2[1]; // @[Bitwise.scala 48:55]
- wire _T_7 = _T_5 <= 2'h1; // @[VCore.scala 80:68]
- wire _T_9 = ~reset; // @[VCore.scala 79:9]
- wire [63:0] _vdec_io_active_T = valu_io_active | vconv_io_active; // @[VCore.scala 86:36]
- wire [63:0] _vdec_io_active_T_1 = _vdec_io_active_T | vldst_io_active; // @[VCore.scala 86:54]
- wire _aluvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_alu; // @[VCore.scala 130:43]
- wire _aluvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_alu; // @[VCore.scala 131:43]
- wire _aluvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_alu; // @[VCore.scala 132:43]
- wire _aluvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_alu; // @[VCore.scala 133:43]
- wire [3:0] aluvalid = {_aluvalid_T,_aluvalid_T_1,_aluvalid_T_2,_aluvalid_T_3}; // @[Cat.scala 31:58]
- wire _aluready_T = valu_io_in_ready & vdec_io_cmdq_3_alu; // @[VCore.scala 135:39]
- wire _aluready_T_1 = valu_io_in_ready & vdec_io_cmdq_2_alu; // @[VCore.scala 136:39]
- wire _aluready_T_2 = valu_io_in_ready & vdec_io_cmdq_1_alu; // @[VCore.scala 137:39]
- wire _aluready_T_3 = valu_io_in_ready & vdec_io_cmdq_0_alu; // @[VCore.scala 138:39]
- wire [3:0] aluready = {_aluready_T,_aluready_T_1,_aluready_T_2,_aluready_T_3}; // @[Cat.scala 31:58]
- wire _convvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_conv; // @[VCore.scala 175:44]
- wire _convvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_conv; // @[VCore.scala 176:44]
- wire _convvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_conv; // @[VCore.scala 177:44]
- wire _convvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_conv; // @[VCore.scala 178:44]
- wire [3:0] convvalid = {_convvalid_T,_convvalid_T_1,_convvalid_T_2,_convvalid_T_3}; // @[Cat.scala 31:58]
- wire _convready_T = vconv_io_in_ready & vdec_io_cmdq_3_conv; // @[VCore.scala 180:41]
- wire _convready_T_1 = vconv_io_in_ready & vdec_io_cmdq_2_conv; // @[VCore.scala 181:41]
- wire _convready_T_2 = vconv_io_in_ready & vdec_io_cmdq_1_conv; // @[VCore.scala 182:41]
- wire _convready_T_3 = vconv_io_in_ready & vdec_io_cmdq_0_conv; // @[VCore.scala 183:41]
- wire [3:0] convready = {_convready_T,_convready_T_1,_convready_T_2,_convready_T_3}; // @[Cat.scala 31:58]
- wire _ldstvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_ldst; // @[VCore.scala 198:44]
- wire _ldstvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_ldst; // @[VCore.scala 199:44]
- wire _ldstvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_ldst; // @[VCore.scala 200:44]
- wire _ldstvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_ldst; // @[VCore.scala 201:44]
- wire [3:0] ldstvalid = {_ldstvalid_T,_ldstvalid_T_1,_ldstvalid_T_2,_ldstvalid_T_3}; // @[Cat.scala 31:58]
- wire _ldstready_T = vldst_io_in_ready & vdec_io_cmdq_3_ldst; // @[VCore.scala 203:41]
- wire _ldstready_T_1 = vldst_io_in_ready & vdec_io_cmdq_2_ldst; // @[VCore.scala 204:41]
- wire _ldstready_T_2 = vldst_io_in_ready & vdec_io_cmdq_1_ldst; // @[VCore.scala 205:41]
- wire _ldstready_T_3 = vldst_io_in_ready & vdec_io_cmdq_0_ldst; // @[VCore.scala 206:41]
- wire [3:0] ldstready = {_ldstready_T,_ldstready_T_1,_ldstready_T_2,_ldstready_T_3}; // @[Cat.scala 31:58]
- wire _ldvalid_T = vdec_io_cmdq_3_ld & vdec_io_out_3_valid; // @[VCore.scala 228:37]
- wire _ldvalid_T_1 = vdec_io_cmdq_2_ld & vdec_io_out_2_valid; // @[VCore.scala 229:37]
- wire _ldvalid_T_2 = vdec_io_cmdq_1_ld & vdec_io_out_1_valid; // @[VCore.scala 230:37]
- wire _ldvalid_T_3 = vdec_io_cmdq_0_ld & vdec_io_out_0_valid; // @[VCore.scala 231:37]
- wire [3:0] ldvalid = {_ldvalid_T,_ldvalid_T_1,_ldvalid_T_2,_ldvalid_T_3}; // @[Cat.scala 31:58]
- wire _ldready_T = vdec_io_cmdq_3_ld & vld_io_in_ready; // @[VCore.scala 233:37]
- wire _ldready_T_1 = vdec_io_cmdq_2_ld & vld_io_in_ready; // @[VCore.scala 234:37]
- wire _ldready_T_2 = vdec_io_cmdq_1_ld & vld_io_in_ready; // @[VCore.scala 235:37]
- wire _ldready_T_3 = vdec_io_cmdq_0_ld & vld_io_in_ready; // @[VCore.scala 236:37]
- wire [3:0] ldready = {_ldready_T,_ldready_T_1,_ldready_T_2,_ldready_T_3}; // @[Cat.scala 31:58]
- wire _stvalid_T = vdec_io_out_3_valid & vdec_io_cmdq_3_st; // @[VCore.scala 252:39]
- wire _stvalid_T_1 = vdec_io_out_2_valid & vdec_io_cmdq_2_st; // @[VCore.scala 253:39]
- wire _stvalid_T_2 = vdec_io_out_1_valid & vdec_io_cmdq_1_st; // @[VCore.scala 254:39]
- wire _stvalid_T_3 = vdec_io_out_0_valid & vdec_io_cmdq_0_st; // @[VCore.scala 255:39]
- wire [3:0] stvalid = {_stvalid_T,_stvalid_T_1,_stvalid_T_2,_stvalid_T_3}; // @[Cat.scala 31:58]
- wire _stready_T = vst_io_in_ready & vdec_io_cmdq_3_st; // @[VCore.scala 257:34]
- wire _stready_T_1 = vst_io_in_ready & vdec_io_cmdq_2_st; // @[VCore.scala 258:34]
- wire _stready_T_2 = vst_io_in_ready & vdec_io_cmdq_1_st; // @[VCore.scala 259:34]
- wire _stready_T_3 = vst_io_in_ready & vdec_io_cmdq_0_st; // @[VCore.scala 260:34]
- wire [3:0] stready = {_stready_T,_stready_T_1,_stready_T_2,_stready_T_3}; // @[Cat.scala 31:58]
- wire _vdec_io_out_0_ready_T_6 = aluready[0] | convready[0] | ldstready[0] | ldready[0]; // @[VCore.scala 297:73]
- wire _vdec_io_out_1_ready_T_6 = aluready[1] | convready[1] | ldstready[1] | ldready[1]; // @[VCore.scala 297:73]
- wire _vdec_io_out_2_ready_T_6 = aluready[2] | convready[2] | ldstready[2] | ldready[2]; // @[VCore.scala 297:73]
- wire _vdec_io_out_3_ready_T_6 = aluready[3] | convready[3] | ldstready[3] | ldready[3]; // @[VCore.scala 297:73]
- wire _io_score_mactive_T_1 = vinst_io_nempty | vdec_io_nempty | vld_io_nempty; // @[VCore.scala 303:57]
- VInst vinst ( // @[VInst.scala 25:18]
- .clock(vinst_clock),
- .reset(vinst_reset),
- .io_in_0_valid(vinst_io_in_0_valid),
- .io_in_0_ready(vinst_io_in_0_ready),
- .io_in_0_addr(vinst_io_in_0_addr),
- .io_in_0_inst(vinst_io_in_0_inst),
- .io_in_0_op(vinst_io_in_0_op),
- .io_in_1_valid(vinst_io_in_1_valid),
- .io_in_1_ready(vinst_io_in_1_ready),
- .io_in_1_addr(vinst_io_in_1_addr),
- .io_in_1_inst(vinst_io_in_1_inst),
- .io_in_1_op(vinst_io_in_1_op),
- .io_in_2_valid(vinst_io_in_2_valid),
- .io_in_2_ready(vinst_io_in_2_ready),
- .io_in_2_addr(vinst_io_in_2_addr),
- .io_in_2_inst(vinst_io_in_2_inst),
- .io_in_2_op(vinst_io_in_2_op),
- .io_in_3_valid(vinst_io_in_3_valid),
- .io_in_3_ready(vinst_io_in_3_ready),
- .io_in_3_addr(vinst_io_in_3_addr),
- .io_in_3_inst(vinst_io_in_3_inst),
- .io_in_3_op(vinst_io_in_3_op),
- .io_rs_0_data(vinst_io_rs_0_data),
- .io_rs_1_data(vinst_io_rs_1_data),
- .io_rs_2_data(vinst_io_rs_2_data),
- .io_rs_3_data(vinst_io_rs_3_data),
- .io_rs_4_data(vinst_io_rs_4_data),
- .io_rs_5_data(vinst_io_rs_5_data),
- .io_rs_6_data(vinst_io_rs_6_data),
- .io_rs_7_data(vinst_io_rs_7_data),
- .io_rd_0_valid(vinst_io_rd_0_valid),
- .io_rd_0_addr(vinst_io_rd_0_addr),
- .io_rd_0_data(vinst_io_rd_0_data),
- .io_rd_1_valid(vinst_io_rd_1_valid),
- .io_rd_1_addr(vinst_io_rd_1_addr),
- .io_rd_1_data(vinst_io_rd_1_data),
- .io_rd_2_valid(vinst_io_rd_2_valid),
- .io_rd_2_addr(vinst_io_rd_2_addr),
- .io_rd_2_data(vinst_io_rd_2_data),
- .io_rd_3_valid(vinst_io_rd_3_valid),
- .io_rd_3_addr(vinst_io_rd_3_addr),
- .io_rd_3_data(vinst_io_rd_3_data),
- .io_out_valid(vinst_io_out_valid),
- .io_out_ready(vinst_io_out_ready),
- .io_out_stall(vinst_io_out_stall),
- .io_out_lane_0_valid(vinst_io_out_lane_0_valid),
- .io_out_lane_0_bits_inst(vinst_io_out_lane_0_bits_inst),
- .io_out_lane_0_bits_addr(vinst_io_out_lane_0_bits_addr),
- .io_out_lane_0_bits_data(vinst_io_out_lane_0_bits_data),
- .io_out_lane_1_valid(vinst_io_out_lane_1_valid),
- .io_out_lane_1_bits_inst(vinst_io_out_lane_1_bits_inst),
- .io_out_lane_1_bits_addr(vinst_io_out_lane_1_bits_addr),
- .io_out_lane_1_bits_data(vinst_io_out_lane_1_bits_data),
- .io_out_lane_2_valid(vinst_io_out_lane_2_valid),
- .io_out_lane_2_bits_inst(vinst_io_out_lane_2_bits_inst),
- .io_out_lane_2_bits_addr(vinst_io_out_lane_2_bits_addr),
- .io_out_lane_2_bits_data(vinst_io_out_lane_2_bits_data),
- .io_out_lane_3_valid(vinst_io_out_lane_3_valid),
- .io_out_lane_3_bits_inst(vinst_io_out_lane_3_bits_inst),
- .io_out_lane_3_bits_addr(vinst_io_out_lane_3_bits_addr),
- .io_out_lane_3_bits_data(vinst_io_out_lane_3_bits_data),
- .io_nempty(vinst_io_nempty)
- );
- VDecode vdec ( // @[VDecode.scala 25:18]
- .clock(vdec_clock),
- .reset(vdec_reset),
- .io_in_ready(vdec_io_in_ready),
- .io_in_valid(vdec_io_in_valid),
- .io_in_bits_0_valid(vdec_io_in_bits_0_valid),
- .io_in_bits_0_bits_inst(vdec_io_in_bits_0_bits_inst),
- .io_in_bits_0_bits_addr(vdec_io_in_bits_0_bits_addr),
- .io_in_bits_0_bits_data(vdec_io_in_bits_0_bits_data),
- .io_in_bits_1_valid(vdec_io_in_bits_1_valid),
- .io_in_bits_1_bits_inst(vdec_io_in_bits_1_bits_inst),
- .io_in_bits_1_bits_addr(vdec_io_in_bits_1_bits_addr),
- .io_in_bits_1_bits_data(vdec_io_in_bits_1_bits_data),
- .io_in_bits_2_valid(vdec_io_in_bits_2_valid),
- .io_in_bits_2_bits_inst(vdec_io_in_bits_2_bits_inst),
- .io_in_bits_2_bits_addr(vdec_io_in_bits_2_bits_addr),
- .io_in_bits_2_bits_data(vdec_io_in_bits_2_bits_data),
- .io_in_bits_3_valid(vdec_io_in_bits_3_valid),
- .io_in_bits_3_bits_inst(vdec_io_in_bits_3_bits_inst),
- .io_in_bits_3_bits_addr(vdec_io_in_bits_3_bits_addr),
- .io_in_bits_3_bits_data(vdec_io_in_bits_3_bits_data),
- .io_out_0_ready(vdec_io_out_0_ready),
- .io_out_0_valid(vdec_io_out_0_valid),
- .io_out_0_bits_op(vdec_io_out_0_bits_op),
- .io_out_0_bits_f2(vdec_io_out_0_bits_f2),
- .io_out_0_bits_sz(vdec_io_out_0_bits_sz),
- .io_out_0_bits_m(vdec_io_out_0_bits_m),
- .io_out_0_bits_vd_valid(vdec_io_out_0_bits_vd_valid),
- .io_out_0_bits_vd_addr(vdec_io_out_0_bits_vd_addr),
- .io_out_0_bits_ve_addr(vdec_io_out_0_bits_ve_addr),
- .io_out_0_bits_vf_addr(vdec_io_out_0_bits_vf_addr),
- .io_out_0_bits_vg_addr(vdec_io_out_0_bits_vg_addr),
- .io_out_0_bits_vs_valid(vdec_io_out_0_bits_vs_valid),
- .io_out_0_bits_vs_addr(vdec_io_out_0_bits_vs_addr),
- .io_out_0_bits_vs_tag(vdec_io_out_0_bits_vs_tag),
- .io_out_0_bits_vt_valid(vdec_io_out_0_bits_vt_valid),
- .io_out_0_bits_vt_addr(vdec_io_out_0_bits_vt_addr),
- .io_out_0_bits_vt_tag(vdec_io_out_0_bits_vt_tag),
- .io_out_0_bits_vu_valid(vdec_io_out_0_bits_vu_valid),
- .io_out_0_bits_vu_addr(vdec_io_out_0_bits_vu_addr),
- .io_out_0_bits_vu_tag(vdec_io_out_0_bits_vu_tag),
- .io_out_0_bits_vx_valid(vdec_io_out_0_bits_vx_valid),
- .io_out_0_bits_vx_addr(vdec_io_out_0_bits_vx_addr),
- .io_out_0_bits_vx_tag(vdec_io_out_0_bits_vx_tag),
- .io_out_0_bits_vy_valid(vdec_io_out_0_bits_vy_valid),
- .io_out_0_bits_vy_addr(vdec_io_out_0_bits_vy_addr),
- .io_out_0_bits_vy_tag(vdec_io_out_0_bits_vy_tag),
- .io_out_0_bits_vz_valid(vdec_io_out_0_bits_vz_valid),
- .io_out_0_bits_vz_addr(vdec_io_out_0_bits_vz_addr),
- .io_out_0_bits_vz_tag(vdec_io_out_0_bits_vz_tag),
- .io_out_0_bits_sv_valid(vdec_io_out_0_bits_sv_valid),
- .io_out_0_bits_sv_addr(vdec_io_out_0_bits_sv_addr),
- .io_out_0_bits_sv_data(vdec_io_out_0_bits_sv_data),
- .io_out_0_bits_cmdsync(vdec_io_out_0_bits_cmdsync),
- .io_out_1_ready(vdec_io_out_1_ready),
- .io_out_1_valid(vdec_io_out_1_valid),
- .io_out_1_bits_op(vdec_io_out_1_bits_op),
- .io_out_1_bits_f2(vdec_io_out_1_bits_f2),
- .io_out_1_bits_sz(vdec_io_out_1_bits_sz),
- .io_out_1_bits_m(vdec_io_out_1_bits_m),
- .io_out_1_bits_vd_valid(vdec_io_out_1_bits_vd_valid),
- .io_out_1_bits_vd_addr(vdec_io_out_1_bits_vd_addr),
- .io_out_1_bits_ve_addr(vdec_io_out_1_bits_ve_addr),
- .io_out_1_bits_vf_addr(vdec_io_out_1_bits_vf_addr),
- .io_out_1_bits_vg_addr(vdec_io_out_1_bits_vg_addr),
- .io_out_1_bits_vs_valid(vdec_io_out_1_bits_vs_valid),
- .io_out_1_bits_vs_addr(vdec_io_out_1_bits_vs_addr),
- .io_out_1_bits_vs_tag(vdec_io_out_1_bits_vs_tag),
- .io_out_1_bits_vt_valid(vdec_io_out_1_bits_vt_valid),
- .io_out_1_bits_vt_addr(vdec_io_out_1_bits_vt_addr),
- .io_out_1_bits_vt_tag(vdec_io_out_1_bits_vt_tag),
- .io_out_1_bits_vu_valid(vdec_io_out_1_bits_vu_valid),
- .io_out_1_bits_vu_addr(vdec_io_out_1_bits_vu_addr),
- .io_out_1_bits_vu_tag(vdec_io_out_1_bits_vu_tag),
- .io_out_1_bits_vx_valid(vdec_io_out_1_bits_vx_valid),
- .io_out_1_bits_vx_addr(vdec_io_out_1_bits_vx_addr),
- .io_out_1_bits_vx_tag(vdec_io_out_1_bits_vx_tag),
- .io_out_1_bits_vy_valid(vdec_io_out_1_bits_vy_valid),
- .io_out_1_bits_vy_addr(vdec_io_out_1_bits_vy_addr),
- .io_out_1_bits_vy_tag(vdec_io_out_1_bits_vy_tag),
- .io_out_1_bits_vz_valid(vdec_io_out_1_bits_vz_valid),
- .io_out_1_bits_vz_addr(vdec_io_out_1_bits_vz_addr),
- .io_out_1_bits_vz_tag(vdec_io_out_1_bits_vz_tag),
- .io_out_1_bits_sv_valid(vdec_io_out_1_bits_sv_valid),
- .io_out_1_bits_sv_addr(vdec_io_out_1_bits_sv_addr),
- .io_out_1_bits_sv_data(vdec_io_out_1_bits_sv_data),
- .io_out_1_bits_cmdsync(vdec_io_out_1_bits_cmdsync),
- .io_out_2_ready(vdec_io_out_2_ready),
- .io_out_2_valid(vdec_io_out_2_valid),
- .io_out_2_bits_op(vdec_io_out_2_bits_op),
- .io_out_2_bits_f2(vdec_io_out_2_bits_f2),
- .io_out_2_bits_sz(vdec_io_out_2_bits_sz),
- .io_out_2_bits_m(vdec_io_out_2_bits_m),
- .io_out_2_bits_vd_valid(vdec_io_out_2_bits_vd_valid),
- .io_out_2_bits_vd_addr(vdec_io_out_2_bits_vd_addr),
- .io_out_2_bits_ve_addr(vdec_io_out_2_bits_ve_addr),
- .io_out_2_bits_vf_addr(vdec_io_out_2_bits_vf_addr),
- .io_out_2_bits_vg_addr(vdec_io_out_2_bits_vg_addr),
- .io_out_2_bits_vs_valid(vdec_io_out_2_bits_vs_valid),
- .io_out_2_bits_vs_addr(vdec_io_out_2_bits_vs_addr),
- .io_out_2_bits_vs_tag(vdec_io_out_2_bits_vs_tag),
- .io_out_2_bits_vt_valid(vdec_io_out_2_bits_vt_valid),
- .io_out_2_bits_vt_addr(vdec_io_out_2_bits_vt_addr),
- .io_out_2_bits_vt_tag(vdec_io_out_2_bits_vt_tag),
- .io_out_2_bits_vu_valid(vdec_io_out_2_bits_vu_valid),
- .io_out_2_bits_vu_addr(vdec_io_out_2_bits_vu_addr),
- .io_out_2_bits_vu_tag(vdec_io_out_2_bits_vu_tag),
- .io_out_2_bits_vx_valid(vdec_io_out_2_bits_vx_valid),
- .io_out_2_bits_vx_addr(vdec_io_out_2_bits_vx_addr),
- .io_out_2_bits_vx_tag(vdec_io_out_2_bits_vx_tag),
- .io_out_2_bits_vy_valid(vdec_io_out_2_bits_vy_valid),
- .io_out_2_bits_vy_addr(vdec_io_out_2_bits_vy_addr),
- .io_out_2_bits_vy_tag(vdec_io_out_2_bits_vy_tag),
- .io_out_2_bits_vz_valid(vdec_io_out_2_bits_vz_valid),
- .io_out_2_bits_vz_addr(vdec_io_out_2_bits_vz_addr),
- .io_out_2_bits_vz_tag(vdec_io_out_2_bits_vz_tag),
- .io_out_2_bits_sv_valid(vdec_io_out_2_bits_sv_valid),
- .io_out_2_bits_sv_addr(vdec_io_out_2_bits_sv_addr),
- .io_out_2_bits_sv_data(vdec_io_out_2_bits_sv_data),
- .io_out_2_bits_cmdsync(vdec_io_out_2_bits_cmdsync),
- .io_out_3_ready(vdec_io_out_3_ready),
- .io_out_3_valid(vdec_io_out_3_valid),
- .io_out_3_bits_op(vdec_io_out_3_bits_op),
- .io_out_3_bits_f2(vdec_io_out_3_bits_f2),
- .io_out_3_bits_sz(vdec_io_out_3_bits_sz),
- .io_out_3_bits_m(vdec_io_out_3_bits_m),
- .io_out_3_bits_vd_valid(vdec_io_out_3_bits_vd_valid),
- .io_out_3_bits_vd_addr(vdec_io_out_3_bits_vd_addr),
- .io_out_3_bits_ve_addr(vdec_io_out_3_bits_ve_addr),
- .io_out_3_bits_vf_addr(vdec_io_out_3_bits_vf_addr),
- .io_out_3_bits_vg_addr(vdec_io_out_3_bits_vg_addr),
- .io_out_3_bits_vs_valid(vdec_io_out_3_bits_vs_valid),
- .io_out_3_bits_vs_addr(vdec_io_out_3_bits_vs_addr),
- .io_out_3_bits_vs_tag(vdec_io_out_3_bits_vs_tag),
- .io_out_3_bits_vt_valid(vdec_io_out_3_bits_vt_valid),
- .io_out_3_bits_vt_addr(vdec_io_out_3_bits_vt_addr),
- .io_out_3_bits_vt_tag(vdec_io_out_3_bits_vt_tag),
- .io_out_3_bits_vu_valid(vdec_io_out_3_bits_vu_valid),
- .io_out_3_bits_vu_addr(vdec_io_out_3_bits_vu_addr),
- .io_out_3_bits_vu_tag(vdec_io_out_3_bits_vu_tag),
- .io_out_3_bits_vx_valid(vdec_io_out_3_bits_vx_valid),
- .io_out_3_bits_vx_addr(vdec_io_out_3_bits_vx_addr),
- .io_out_3_bits_vx_tag(vdec_io_out_3_bits_vx_tag),
- .io_out_3_bits_vy_valid(vdec_io_out_3_bits_vy_valid),
- .io_out_3_bits_vy_addr(vdec_io_out_3_bits_vy_addr),
- .io_out_3_bits_vy_tag(vdec_io_out_3_bits_vy_tag),
- .io_out_3_bits_vz_valid(vdec_io_out_3_bits_vz_valid),
- .io_out_3_bits_vz_addr(vdec_io_out_3_bits_vz_addr),
- .io_out_3_bits_vz_tag(vdec_io_out_3_bits_vz_tag),
- .io_out_3_bits_sv_valid(vdec_io_out_3_bits_sv_valid),
- .io_out_3_bits_sv_addr(vdec_io_out_3_bits_sv_addr),
- .io_out_3_bits_sv_data(vdec_io_out_3_bits_sv_data),
- .io_out_3_bits_cmdsync(vdec_io_out_3_bits_cmdsync),
- .io_cmdq_0_alu(vdec_io_cmdq_0_alu),
- .io_cmdq_0_conv(vdec_io_cmdq_0_conv),
- .io_cmdq_0_ldst(vdec_io_cmdq_0_ldst),
- .io_cmdq_0_ld(vdec_io_cmdq_0_ld),
- .io_cmdq_0_st(vdec_io_cmdq_0_st),
- .io_cmdq_1_alu(vdec_io_cmdq_1_alu),
- .io_cmdq_1_conv(vdec_io_cmdq_1_conv),
- .io_cmdq_1_ldst(vdec_io_cmdq_1_ldst),
- .io_cmdq_1_ld(vdec_io_cmdq_1_ld),
- .io_cmdq_1_st(vdec_io_cmdq_1_st),
- .io_cmdq_2_alu(vdec_io_cmdq_2_alu),
- .io_cmdq_2_conv(vdec_io_cmdq_2_conv),
- .io_cmdq_2_ldst(vdec_io_cmdq_2_ldst),
- .io_cmdq_2_ld(vdec_io_cmdq_2_ld),
- .io_cmdq_2_st(vdec_io_cmdq_2_st),
- .io_cmdq_3_alu(vdec_io_cmdq_3_alu),
- .io_cmdq_3_conv(vdec_io_cmdq_3_conv),
- .io_cmdq_3_ldst(vdec_io_cmdq_3_ldst),
- .io_cmdq_3_ld(vdec_io_cmdq_3_ld),
- .io_cmdq_3_st(vdec_io_cmdq_3_st),
- .io_stall(vdec_io_stall),
- .io_active(vdec_io_active),
- .io_vrfsb_set_valid(vdec_io_vrfsb_set_valid),
- .io_vrfsb_set_bits(vdec_io_vrfsb_set_bits),
- .io_vrfsb_data(vdec_io_vrfsb_data),
- .io_undef(vdec_io_undef),
- .io_nempty(vdec_io_nempty)
- );
- VAlu valu ( // @[VAlu.scala 25:18]
- .clock(valu_clock),
- .reset(valu_reset),
- .io_in_ready(valu_io_in_ready),
- .io_in_valid(valu_io_in_valid),
- .io_in_bits_0_valid(valu_io_in_bits_0_valid),
- .io_in_bits_0_bits_op(valu_io_in_bits_0_bits_op),
- .io_in_bits_0_bits_f2(valu_io_in_bits_0_bits_f2),
- .io_in_bits_0_bits_sz(valu_io_in_bits_0_bits_sz),
- .io_in_bits_0_bits_m(valu_io_in_bits_0_bits_m),
- .io_in_bits_0_bits_vd_addr(valu_io_in_bits_0_bits_vd_addr),
- .io_in_bits_0_bits_ve_addr(valu_io_in_bits_0_bits_ve_addr),
- .io_in_bits_0_bits_vf_addr(valu_io_in_bits_0_bits_vf_addr),
- .io_in_bits_0_bits_vg_addr(valu_io_in_bits_0_bits_vg_addr),
- .io_in_bits_0_bits_vs_valid(valu_io_in_bits_0_bits_vs_valid),
- .io_in_bits_0_bits_vs_addr(valu_io_in_bits_0_bits_vs_addr),
- .io_in_bits_0_bits_vs_tag(valu_io_in_bits_0_bits_vs_tag),
- .io_in_bits_0_bits_vt_valid(valu_io_in_bits_0_bits_vt_valid),
- .io_in_bits_0_bits_vt_addr(valu_io_in_bits_0_bits_vt_addr),
- .io_in_bits_0_bits_vt_tag(valu_io_in_bits_0_bits_vt_tag),
- .io_in_bits_0_bits_vu_valid(valu_io_in_bits_0_bits_vu_valid),
- .io_in_bits_0_bits_vu_addr(valu_io_in_bits_0_bits_vu_addr),
- .io_in_bits_0_bits_vu_tag(valu_io_in_bits_0_bits_vu_tag),
- .io_in_bits_0_bits_vx_valid(valu_io_in_bits_0_bits_vx_valid),
- .io_in_bits_0_bits_vx_addr(valu_io_in_bits_0_bits_vx_addr),
- .io_in_bits_0_bits_vx_tag(valu_io_in_bits_0_bits_vx_tag),
- .io_in_bits_0_bits_vy_valid(valu_io_in_bits_0_bits_vy_valid),
- .io_in_bits_0_bits_vy_addr(valu_io_in_bits_0_bits_vy_addr),
- .io_in_bits_0_bits_vy_tag(valu_io_in_bits_0_bits_vy_tag),
- .io_in_bits_0_bits_vz_valid(valu_io_in_bits_0_bits_vz_valid),
- .io_in_bits_0_bits_vz_addr(valu_io_in_bits_0_bits_vz_addr),
- .io_in_bits_0_bits_vz_tag(valu_io_in_bits_0_bits_vz_tag),
- .io_in_bits_0_bits_sv_valid(valu_io_in_bits_0_bits_sv_valid),
- .io_in_bits_0_bits_sv_data(valu_io_in_bits_0_bits_sv_data),
- .io_in_bits_0_bits_cmdsync(valu_io_in_bits_0_bits_cmdsync),
- .io_in_bits_1_valid(valu_io_in_bits_1_valid),
- .io_in_bits_1_bits_op(valu_io_in_bits_1_bits_op),
- .io_in_bits_1_bits_f2(valu_io_in_bits_1_bits_f2),
- .io_in_bits_1_bits_sz(valu_io_in_bits_1_bits_sz),
- .io_in_bits_1_bits_m(valu_io_in_bits_1_bits_m),
- .io_in_bits_1_bits_vd_addr(valu_io_in_bits_1_bits_vd_addr),
- .io_in_bits_1_bits_ve_addr(valu_io_in_bits_1_bits_ve_addr),
- .io_in_bits_1_bits_vf_addr(valu_io_in_bits_1_bits_vf_addr),
- .io_in_bits_1_bits_vg_addr(valu_io_in_bits_1_bits_vg_addr),
- .io_in_bits_1_bits_vs_valid(valu_io_in_bits_1_bits_vs_valid),
- .io_in_bits_1_bits_vs_addr(valu_io_in_bits_1_bits_vs_addr),
- .io_in_bits_1_bits_vs_tag(valu_io_in_bits_1_bits_vs_tag),
- .io_in_bits_1_bits_vt_valid(valu_io_in_bits_1_bits_vt_valid),
- .io_in_bits_1_bits_vt_addr(valu_io_in_bits_1_bits_vt_addr),
- .io_in_bits_1_bits_vt_tag(valu_io_in_bits_1_bits_vt_tag),
- .io_in_bits_1_bits_vu_valid(valu_io_in_bits_1_bits_vu_valid),
- .io_in_bits_1_bits_vu_addr(valu_io_in_bits_1_bits_vu_addr),
- .io_in_bits_1_bits_vu_tag(valu_io_in_bits_1_bits_vu_tag),
- .io_in_bits_1_bits_vx_valid(valu_io_in_bits_1_bits_vx_valid),
- .io_in_bits_1_bits_vx_addr(valu_io_in_bits_1_bits_vx_addr),
- .io_in_bits_1_bits_vx_tag(valu_io_in_bits_1_bits_vx_tag),
- .io_in_bits_1_bits_vy_valid(valu_io_in_bits_1_bits_vy_valid),
- .io_in_bits_1_bits_vy_addr(valu_io_in_bits_1_bits_vy_addr),
- .io_in_bits_1_bits_vy_tag(valu_io_in_bits_1_bits_vy_tag),
- .io_in_bits_1_bits_vz_valid(valu_io_in_bits_1_bits_vz_valid),
- .io_in_bits_1_bits_vz_addr(valu_io_in_bits_1_bits_vz_addr),
- .io_in_bits_1_bits_vz_tag(valu_io_in_bits_1_bits_vz_tag),
- .io_in_bits_1_bits_sv_valid(valu_io_in_bits_1_bits_sv_valid),
- .io_in_bits_1_bits_sv_data(valu_io_in_bits_1_bits_sv_data),
- .io_in_bits_1_bits_cmdsync(valu_io_in_bits_1_bits_cmdsync),
- .io_in_bits_2_valid(valu_io_in_bits_2_valid),
- .io_in_bits_2_bits_op(valu_io_in_bits_2_bits_op),
- .io_in_bits_2_bits_f2(valu_io_in_bits_2_bits_f2),
- .io_in_bits_2_bits_sz(valu_io_in_bits_2_bits_sz),
- .io_in_bits_2_bits_m(valu_io_in_bits_2_bits_m),
- .io_in_bits_2_bits_vd_addr(valu_io_in_bits_2_bits_vd_addr),
- .io_in_bits_2_bits_ve_addr(valu_io_in_bits_2_bits_ve_addr),
- .io_in_bits_2_bits_vf_addr(valu_io_in_bits_2_bits_vf_addr),
- .io_in_bits_2_bits_vg_addr(valu_io_in_bits_2_bits_vg_addr),
- .io_in_bits_2_bits_vs_valid(valu_io_in_bits_2_bits_vs_valid),
- .io_in_bits_2_bits_vs_addr(valu_io_in_bits_2_bits_vs_addr),
- .io_in_bits_2_bits_vs_tag(valu_io_in_bits_2_bits_vs_tag),
- .io_in_bits_2_bits_vt_valid(valu_io_in_bits_2_bits_vt_valid),
- .io_in_bits_2_bits_vt_addr(valu_io_in_bits_2_bits_vt_addr),
- .io_in_bits_2_bits_vt_tag(valu_io_in_bits_2_bits_vt_tag),
- .io_in_bits_2_bits_vu_valid(valu_io_in_bits_2_bits_vu_valid),
- .io_in_bits_2_bits_vu_addr(valu_io_in_bits_2_bits_vu_addr),
- .io_in_bits_2_bits_vu_tag(valu_io_in_bits_2_bits_vu_tag),
- .io_in_bits_2_bits_vx_valid(valu_io_in_bits_2_bits_vx_valid),
- .io_in_bits_2_bits_vx_addr(valu_io_in_bits_2_bits_vx_addr),
- .io_in_bits_2_bits_vx_tag(valu_io_in_bits_2_bits_vx_tag),
- .io_in_bits_2_bits_vy_valid(valu_io_in_bits_2_bits_vy_valid),
- .io_in_bits_2_bits_vy_addr(valu_io_in_bits_2_bits_vy_addr),
- .io_in_bits_2_bits_vy_tag(valu_io_in_bits_2_bits_vy_tag),
- .io_in_bits_2_bits_vz_valid(valu_io_in_bits_2_bits_vz_valid),
- .io_in_bits_2_bits_vz_addr(valu_io_in_bits_2_bits_vz_addr),
- .io_in_bits_2_bits_vz_tag(valu_io_in_bits_2_bits_vz_tag),
- .io_in_bits_2_bits_sv_valid(valu_io_in_bits_2_bits_sv_valid),
- .io_in_bits_2_bits_sv_data(valu_io_in_bits_2_bits_sv_data),
- .io_in_bits_2_bits_cmdsync(valu_io_in_bits_2_bits_cmdsync),
- .io_in_bits_3_valid(valu_io_in_bits_3_valid),
- .io_in_bits_3_bits_op(valu_io_in_bits_3_bits_op),
- .io_in_bits_3_bits_f2(valu_io_in_bits_3_bits_f2),
- .io_in_bits_3_bits_sz(valu_io_in_bits_3_bits_sz),
- .io_in_bits_3_bits_m(valu_io_in_bits_3_bits_m),
- .io_in_bits_3_bits_vd_addr(valu_io_in_bits_3_bits_vd_addr),
- .io_in_bits_3_bits_ve_addr(valu_io_in_bits_3_bits_ve_addr),
- .io_in_bits_3_bits_vf_addr(valu_io_in_bits_3_bits_vf_addr),
- .io_in_bits_3_bits_vg_addr(valu_io_in_bits_3_bits_vg_addr),
- .io_in_bits_3_bits_vs_valid(valu_io_in_bits_3_bits_vs_valid),
- .io_in_bits_3_bits_vs_addr(valu_io_in_bits_3_bits_vs_addr),
- .io_in_bits_3_bits_vs_tag(valu_io_in_bits_3_bits_vs_tag),
- .io_in_bits_3_bits_vt_valid(valu_io_in_bits_3_bits_vt_valid),
- .io_in_bits_3_bits_vt_addr(valu_io_in_bits_3_bits_vt_addr),
- .io_in_bits_3_bits_vt_tag(valu_io_in_bits_3_bits_vt_tag),
- .io_in_bits_3_bits_vu_valid(valu_io_in_bits_3_bits_vu_valid),
- .io_in_bits_3_bits_vu_addr(valu_io_in_bits_3_bits_vu_addr),
- .io_in_bits_3_bits_vu_tag(valu_io_in_bits_3_bits_vu_tag),
- .io_in_bits_3_bits_vx_valid(valu_io_in_bits_3_bits_vx_valid),
- .io_in_bits_3_bits_vx_addr(valu_io_in_bits_3_bits_vx_addr),
- .io_in_bits_3_bits_vx_tag(valu_io_in_bits_3_bits_vx_tag),
- .io_in_bits_3_bits_vy_valid(valu_io_in_bits_3_bits_vy_valid),
- .io_in_bits_3_bits_vy_addr(valu_io_in_bits_3_bits_vy_addr),
- .io_in_bits_3_bits_vy_tag(valu_io_in_bits_3_bits_vy_tag),
- .io_in_bits_3_bits_vz_valid(valu_io_in_bits_3_bits_vz_valid),
- .io_in_bits_3_bits_vz_addr(valu_io_in_bits_3_bits_vz_addr),
- .io_in_bits_3_bits_vz_tag(valu_io_in_bits_3_bits_vz_tag),
- .io_in_bits_3_bits_sv_valid(valu_io_in_bits_3_bits_sv_valid),
- .io_in_bits_3_bits_sv_data(valu_io_in_bits_3_bits_sv_data),
- .io_in_bits_3_bits_cmdsync(valu_io_in_bits_3_bits_cmdsync),
- .io_active(valu_io_active),
- .io_vrfsb(valu_io_vrfsb),
- .io_read_0_valid(valu_io_read_0_valid),
- .io_read_0_addr(valu_io_read_0_addr),
- .io_read_0_data(valu_io_read_0_data),
- .io_read_1_valid(valu_io_read_1_valid),
- .io_read_1_addr(valu_io_read_1_addr),
- .io_read_1_data(valu_io_read_1_data),
- .io_read_2_valid(valu_io_read_2_valid),
- .io_read_2_addr(valu_io_read_2_addr),
- .io_read_2_data(valu_io_read_2_data),
- .io_read_3_valid(valu_io_read_3_valid),
- .io_read_3_addr(valu_io_read_3_addr),
- .io_read_3_data(valu_io_read_3_data),
- .io_read_4_valid(valu_io_read_4_valid),
- .io_read_4_addr(valu_io_read_4_addr),
- .io_read_4_data(valu_io_read_4_data),
- .io_read_5_valid(valu_io_read_5_valid),
- .io_read_5_addr(valu_io_read_5_addr),
- .io_read_5_data(valu_io_read_5_data),
- .io_write_0_valid(valu_io_write_0_valid),
- .io_write_0_addr(valu_io_write_0_addr),
- .io_write_0_data(valu_io_write_0_data),
- .io_write_1_valid(valu_io_write_1_valid),
- .io_write_1_addr(valu_io_write_1_addr),
- .io_write_1_data(valu_io_write_1_data),
- .io_write_2_valid(valu_io_write_2_valid),
- .io_write_2_addr(valu_io_write_2_addr),
- .io_write_2_data(valu_io_write_2_data),
- .io_write_3_valid(valu_io_write_3_valid),
- .io_write_3_addr(valu_io_write_3_addr),
- .io_write_3_data(valu_io_write_3_data),
- .io_whint_0_valid(valu_io_whint_0_valid),
- .io_whint_0_addr(valu_io_whint_0_addr),
- .io_whint_1_valid(valu_io_whint_1_valid),
- .io_whint_1_addr(valu_io_whint_1_addr),
- .io_whint_2_valid(valu_io_whint_2_valid),
- .io_whint_2_addr(valu_io_whint_2_addr),
- .io_whint_3_valid(valu_io_whint_3_valid),
- .io_whint_3_addr(valu_io_whint_3_addr),
- .io_scalar_0_valid(valu_io_scalar_0_valid),
- .io_scalar_0_data(valu_io_scalar_0_data),
- .io_scalar_1_valid(valu_io_scalar_1_valid),
- .io_scalar_1_data(valu_io_scalar_1_data)
- );
- VConvCtrl vconv ( // @[VConvCtrl.scala 25:18]
- .clock(vconv_clock),
- .reset(vconv_reset),
- .io_in_ready(vconv_io_in_ready),
- .io_in_valid(vconv_io_in_valid),
- .io_in_bits_0_valid(vconv_io_in_bits_0_valid),
- .io_in_bits_0_bits_op(vconv_io_in_bits_0_bits_op),
- .io_in_bits_0_bits_m(vconv_io_in_bits_0_bits_m),
- .io_in_bits_0_bits_vs_addr(vconv_io_in_bits_0_bits_vs_addr),
- .io_in_bits_0_bits_vu_addr(vconv_io_in_bits_0_bits_vu_addr),
- .io_in_bits_0_bits_sv_data(vconv_io_in_bits_0_bits_sv_data),
- .io_in_bits_1_valid(vconv_io_in_bits_1_valid),
- .io_in_bits_1_bits_op(vconv_io_in_bits_1_bits_op),
- .io_in_bits_1_bits_m(vconv_io_in_bits_1_bits_m),
- .io_in_bits_1_bits_vs_addr(vconv_io_in_bits_1_bits_vs_addr),
- .io_in_bits_1_bits_vu_addr(vconv_io_in_bits_1_bits_vu_addr),
- .io_in_bits_1_bits_sv_data(vconv_io_in_bits_1_bits_sv_data),
- .io_in_bits_2_valid(vconv_io_in_bits_2_valid),
- .io_in_bits_2_bits_op(vconv_io_in_bits_2_bits_op),
- .io_in_bits_2_bits_m(vconv_io_in_bits_2_bits_m),
- .io_in_bits_2_bits_vs_addr(vconv_io_in_bits_2_bits_vs_addr),
- .io_in_bits_2_bits_vu_addr(vconv_io_in_bits_2_bits_vu_addr),
- .io_in_bits_2_bits_sv_data(vconv_io_in_bits_2_bits_sv_data),
- .io_in_bits_3_valid(vconv_io_in_bits_3_valid),
- .io_in_bits_3_bits_op(vconv_io_in_bits_3_bits_op),
- .io_in_bits_3_bits_m(vconv_io_in_bits_3_bits_m),
- .io_in_bits_3_bits_vs_addr(vconv_io_in_bits_3_bits_vs_addr),
- .io_in_bits_3_bits_vu_addr(vconv_io_in_bits_3_bits_vu_addr),
- .io_in_bits_3_bits_sv_data(vconv_io_in_bits_3_bits_sv_data),
- .io_active(vconv_io_active),
- .io_vrfsb(vconv_io_vrfsb),
- .io_out_valid(vconv_io_out_valid),
- .io_out_ready(vconv_io_out_ready),
- .io_out_op_conv(vconv_io_out_op_conv),
- .io_out_op_init(vconv_io_out_op_init),
- .io_out_op_tran(vconv_io_out_op_tran),
- .io_out_op_wclr(vconv_io_out_op_wclr),
- .io_out_addr1(vconv_io_out_addr1),
- .io_out_addr2(vconv_io_out_addr2),
- .io_out_mode(vconv_io_out_mode),
- .io_out_index(vconv_io_out_index),
- .io_out_abias(vconv_io_out_abias),
- .io_out_bbias(vconv_io_out_bbias),
- .io_out_asign(vconv_io_out_asign),
- .io_out_bsign(vconv_io_out_bsign)
- );
- VLdSt vldst ( // @[VLdSt.scala 25:18]
- .clock(vldst_clock),
- .reset(vldst_reset),
- .io_in_ready(vldst_io_in_ready),
- .io_in_valid(vldst_io_in_valid),
- .io_in_bits_0_valid(vldst_io_in_bits_0_valid),
- .io_in_bits_0_bits_op(vldst_io_in_bits_0_bits_op),
- .io_in_bits_0_bits_f2(vldst_io_in_bits_0_bits_f2),
- .io_in_bits_0_bits_sz(vldst_io_in_bits_0_bits_sz),
- .io_in_bits_0_bits_m(vldst_io_in_bits_0_bits_m),
- .io_in_bits_0_bits_vd_valid(vldst_io_in_bits_0_bits_vd_valid),
- .io_in_bits_0_bits_vd_addr(vldst_io_in_bits_0_bits_vd_addr),
- .io_in_bits_0_bits_vs_valid(vldst_io_in_bits_0_bits_vs_valid),
- .io_in_bits_0_bits_vs_addr(vldst_io_in_bits_0_bits_vs_addr),
- .io_in_bits_0_bits_vs_tag(vldst_io_in_bits_0_bits_vs_tag),
- .io_in_bits_0_bits_sv_addr(vldst_io_in_bits_0_bits_sv_addr),
- .io_in_bits_0_bits_sv_data(vldst_io_in_bits_0_bits_sv_data),
- .io_in_bits_1_valid(vldst_io_in_bits_1_valid),
- .io_in_bits_1_bits_op(vldst_io_in_bits_1_bits_op),
- .io_in_bits_1_bits_f2(vldst_io_in_bits_1_bits_f2),
- .io_in_bits_1_bits_sz(vldst_io_in_bits_1_bits_sz),
- .io_in_bits_1_bits_m(vldst_io_in_bits_1_bits_m),
- .io_in_bits_1_bits_vd_valid(vldst_io_in_bits_1_bits_vd_valid),
- .io_in_bits_1_bits_vd_addr(vldst_io_in_bits_1_bits_vd_addr),
- .io_in_bits_1_bits_vs_valid(vldst_io_in_bits_1_bits_vs_valid),
- .io_in_bits_1_bits_vs_addr(vldst_io_in_bits_1_bits_vs_addr),
- .io_in_bits_1_bits_vs_tag(vldst_io_in_bits_1_bits_vs_tag),
- .io_in_bits_1_bits_sv_addr(vldst_io_in_bits_1_bits_sv_addr),
- .io_in_bits_1_bits_sv_data(vldst_io_in_bits_1_bits_sv_data),
- .io_in_bits_2_valid(vldst_io_in_bits_2_valid),
- .io_in_bits_2_bits_op(vldst_io_in_bits_2_bits_op),
- .io_in_bits_2_bits_f2(vldst_io_in_bits_2_bits_f2),
- .io_in_bits_2_bits_sz(vldst_io_in_bits_2_bits_sz),
- .io_in_bits_2_bits_m(vldst_io_in_bits_2_bits_m),
- .io_in_bits_2_bits_vd_valid(vldst_io_in_bits_2_bits_vd_valid),
- .io_in_bits_2_bits_vd_addr(vldst_io_in_bits_2_bits_vd_addr),
- .io_in_bits_2_bits_vs_valid(vldst_io_in_bits_2_bits_vs_valid),
- .io_in_bits_2_bits_vs_addr(vldst_io_in_bits_2_bits_vs_addr),
- .io_in_bits_2_bits_vs_tag(vldst_io_in_bits_2_bits_vs_tag),
- .io_in_bits_2_bits_sv_addr(vldst_io_in_bits_2_bits_sv_addr),
- .io_in_bits_2_bits_sv_data(vldst_io_in_bits_2_bits_sv_data),
- .io_in_bits_3_valid(vldst_io_in_bits_3_valid),
- .io_in_bits_3_bits_op(vldst_io_in_bits_3_bits_op),
- .io_in_bits_3_bits_f2(vldst_io_in_bits_3_bits_f2),
- .io_in_bits_3_bits_sz(vldst_io_in_bits_3_bits_sz),
- .io_in_bits_3_bits_m(vldst_io_in_bits_3_bits_m),
- .io_in_bits_3_bits_vd_valid(vldst_io_in_bits_3_bits_vd_valid),
- .io_in_bits_3_bits_vd_addr(vldst_io_in_bits_3_bits_vd_addr),
- .io_in_bits_3_bits_vs_valid(vldst_io_in_bits_3_bits_vs_valid),
- .io_in_bits_3_bits_vs_addr(vldst_io_in_bits_3_bits_vs_addr),
- .io_in_bits_3_bits_vs_tag(vldst_io_in_bits_3_bits_vs_tag),
- .io_in_bits_3_bits_sv_addr(vldst_io_in_bits_3_bits_sv_addr),
- .io_in_bits_3_bits_sv_data(vldst_io_in_bits_3_bits_sv_data),
- .io_active(vldst_io_active),
- .io_vrfsb(vldst_io_vrfsb),
- .io_read_valid(vldst_io_read_valid),
- .io_read_ready(vldst_io_read_ready),
- .io_read_addr(vldst_io_read_addr),
- .io_read_data(vldst_io_read_data),
- .io_write_valid(vldst_io_write_valid),
- .io_write_addr(vldst_io_write_addr),
- .io_write_data(vldst_io_write_data),
- .io_dbus_valid(vldst_io_dbus_valid),
- .io_dbus_ready(vldst_io_dbus_ready),
- .io_dbus_write(vldst_io_dbus_write),
- .io_dbus_addr(vldst_io_dbus_addr),
- .io_dbus_adrx(vldst_io_dbus_adrx),
- .io_dbus_size(vldst_io_dbus_size),
- .io_dbus_wdata(vldst_io_dbus_wdata),
- .io_dbus_wmask(vldst_io_dbus_wmask),
- .io_dbus_rdata(vldst_io_dbus_rdata),
- .io_last(vldst_io_last)
- );
- VLd vld ( // @[VLd.scala 25:18]
- .clock(vld_clock),
- .reset(vld_reset),
- .io_in_ready(vld_io_in_ready),
- .io_in_valid(vld_io_in_valid),
- .io_in_bits_0_valid(vld_io_in_bits_0_valid),
- .io_in_bits_0_bits_op(vld_io_in_bits_0_bits_op),
- .io_in_bits_0_bits_f2(vld_io_in_bits_0_bits_f2),
- .io_in_bits_0_bits_sz(vld_io_in_bits_0_bits_sz),
- .io_in_bits_0_bits_m(vld_io_in_bits_0_bits_m),
- .io_in_bits_0_bits_vd_valid(vld_io_in_bits_0_bits_vd_valid),
- .io_in_bits_0_bits_vd_addr(vld_io_in_bits_0_bits_vd_addr),
- .io_in_bits_0_bits_vs_valid(vld_io_in_bits_0_bits_vs_valid),
- .io_in_bits_0_bits_sv_addr(vld_io_in_bits_0_bits_sv_addr),
- .io_in_bits_0_bits_sv_data(vld_io_in_bits_0_bits_sv_data),
- .io_in_bits_1_valid(vld_io_in_bits_1_valid),
- .io_in_bits_1_bits_op(vld_io_in_bits_1_bits_op),
- .io_in_bits_1_bits_f2(vld_io_in_bits_1_bits_f2),
- .io_in_bits_1_bits_sz(vld_io_in_bits_1_bits_sz),
- .io_in_bits_1_bits_m(vld_io_in_bits_1_bits_m),
- .io_in_bits_1_bits_vd_valid(vld_io_in_bits_1_bits_vd_valid),
- .io_in_bits_1_bits_vd_addr(vld_io_in_bits_1_bits_vd_addr),
- .io_in_bits_1_bits_vs_valid(vld_io_in_bits_1_bits_vs_valid),
- .io_in_bits_1_bits_sv_addr(vld_io_in_bits_1_bits_sv_addr),
- .io_in_bits_1_bits_sv_data(vld_io_in_bits_1_bits_sv_data),
- .io_in_bits_2_valid(vld_io_in_bits_2_valid),
- .io_in_bits_2_bits_op(vld_io_in_bits_2_bits_op),
- .io_in_bits_2_bits_f2(vld_io_in_bits_2_bits_f2),
- .io_in_bits_2_bits_sz(vld_io_in_bits_2_bits_sz),
- .io_in_bits_2_bits_m(vld_io_in_bits_2_bits_m),
- .io_in_bits_2_bits_vd_valid(vld_io_in_bits_2_bits_vd_valid),
- .io_in_bits_2_bits_vd_addr(vld_io_in_bits_2_bits_vd_addr),
- .io_in_bits_2_bits_vs_valid(vld_io_in_bits_2_bits_vs_valid),
- .io_in_bits_2_bits_sv_addr(vld_io_in_bits_2_bits_sv_addr),
- .io_in_bits_2_bits_sv_data(vld_io_in_bits_2_bits_sv_data),
- .io_in_bits_3_valid(vld_io_in_bits_3_valid),
- .io_in_bits_3_bits_op(vld_io_in_bits_3_bits_op),
- .io_in_bits_3_bits_f2(vld_io_in_bits_3_bits_f2),
- .io_in_bits_3_bits_sz(vld_io_in_bits_3_bits_sz),
- .io_in_bits_3_bits_m(vld_io_in_bits_3_bits_m),
- .io_in_bits_3_bits_vd_valid(vld_io_in_bits_3_bits_vd_valid),
- .io_in_bits_3_bits_vd_addr(vld_io_in_bits_3_bits_vd_addr),
- .io_in_bits_3_bits_vs_valid(vld_io_in_bits_3_bits_vs_valid),
- .io_in_bits_3_bits_sv_addr(vld_io_in_bits_3_bits_sv_addr),
- .io_in_bits_3_bits_sv_data(vld_io_in_bits_3_bits_sv_data),
- .io_write_valid(vld_io_write_valid),
- .io_write_addr(vld_io_write_addr),
- .io_write_data(vld_io_write_data),
- .io_axi_addr_ready(vld_io_axi_addr_ready),
- .io_axi_addr_valid(vld_io_axi_addr_valid),
- .io_axi_addr_bits_addr(vld_io_axi_addr_bits_addr),
- .io_axi_addr_bits_id(vld_io_axi_addr_bits_id),
- .io_axi_data_ready(vld_io_axi_data_ready),
- .io_axi_data_valid(vld_io_axi_data_valid),
- .io_axi_data_bits_id(vld_io_axi_data_bits_id),
- .io_axi_data_bits_data(vld_io_axi_data_bits_data),
- .io_nempty(vld_io_nempty)
- );
- VSt vst ( // @[VSt.scala 25:18]
- .clock(vst_clock),
- .reset(vst_reset),
- .io_in_ready(vst_io_in_ready),
- .io_in_valid(vst_io_in_valid),
- .io_in_bits_0_valid(vst_io_in_bits_0_valid),
- .io_in_bits_0_bits_op(vst_io_in_bits_0_bits_op),
- .io_in_bits_0_bits_f2(vst_io_in_bits_0_bits_f2),
- .io_in_bits_0_bits_sz(vst_io_in_bits_0_bits_sz),
- .io_in_bits_0_bits_m(vst_io_in_bits_0_bits_m),
- .io_in_bits_0_bits_vs_valid(vst_io_in_bits_0_bits_vs_valid),
- .io_in_bits_0_bits_vs_addr(vst_io_in_bits_0_bits_vs_addr),
- .io_in_bits_0_bits_vs_tag(vst_io_in_bits_0_bits_vs_tag),
- .io_in_bits_0_bits_sv_addr(vst_io_in_bits_0_bits_sv_addr),
- .io_in_bits_0_bits_sv_data(vst_io_in_bits_0_bits_sv_data),
- .io_in_bits_1_valid(vst_io_in_bits_1_valid),
- .io_in_bits_1_bits_op(vst_io_in_bits_1_bits_op),
- .io_in_bits_1_bits_f2(vst_io_in_bits_1_bits_f2),
- .io_in_bits_1_bits_sz(vst_io_in_bits_1_bits_sz),
- .io_in_bits_1_bits_m(vst_io_in_bits_1_bits_m),
- .io_in_bits_1_bits_vs_valid(vst_io_in_bits_1_bits_vs_valid),
- .io_in_bits_1_bits_vs_addr(vst_io_in_bits_1_bits_vs_addr),
- .io_in_bits_1_bits_vs_tag(vst_io_in_bits_1_bits_vs_tag),
- .io_in_bits_1_bits_sv_addr(vst_io_in_bits_1_bits_sv_addr),
- .io_in_bits_1_bits_sv_data(vst_io_in_bits_1_bits_sv_data),
- .io_in_bits_2_valid(vst_io_in_bits_2_valid),
- .io_in_bits_2_bits_op(vst_io_in_bits_2_bits_op),
- .io_in_bits_2_bits_f2(vst_io_in_bits_2_bits_f2),
- .io_in_bits_2_bits_sz(vst_io_in_bits_2_bits_sz),
- .io_in_bits_2_bits_m(vst_io_in_bits_2_bits_m),
- .io_in_bits_2_bits_vs_valid(vst_io_in_bits_2_bits_vs_valid),
- .io_in_bits_2_bits_vs_addr(vst_io_in_bits_2_bits_vs_addr),
- .io_in_bits_2_bits_vs_tag(vst_io_in_bits_2_bits_vs_tag),
- .io_in_bits_2_bits_sv_addr(vst_io_in_bits_2_bits_sv_addr),
- .io_in_bits_2_bits_sv_data(vst_io_in_bits_2_bits_sv_data),
- .io_in_bits_3_valid(vst_io_in_bits_3_valid),
- .io_in_bits_3_bits_op(vst_io_in_bits_3_bits_op),
- .io_in_bits_3_bits_f2(vst_io_in_bits_3_bits_f2),
- .io_in_bits_3_bits_sz(vst_io_in_bits_3_bits_sz),
- .io_in_bits_3_bits_m(vst_io_in_bits_3_bits_m),
- .io_in_bits_3_bits_vs_valid(vst_io_in_bits_3_bits_vs_valid),
- .io_in_bits_3_bits_vs_addr(vst_io_in_bits_3_bits_vs_addr),
- .io_in_bits_3_bits_vs_tag(vst_io_in_bits_3_bits_vs_tag),
- .io_in_bits_3_bits_sv_addr(vst_io_in_bits_3_bits_sv_addr),
- .io_in_bits_3_bits_sv_data(vst_io_in_bits_3_bits_sv_data),
- .io_active(vst_io_active),
- .io_vrfsb(vst_io_vrfsb),
- .io_read_valid(vst_io_read_valid),
- .io_read_ready(vst_io_read_ready),
- .io_read_addr(vst_io_read_addr),
- .io_read_data(vst_io_read_data),
- .io_axi_addr_ready(vst_io_axi_addr_ready),
- .io_axi_addr_valid(vst_io_axi_addr_valid),
- .io_axi_addr_bits_addr(vst_io_axi_addr_bits_addr),
- .io_axi_addr_bits_id(vst_io_axi_addr_bits_id),
- .io_axi_data_ready(vst_io_axi_data_ready),
- .io_axi_data_valid(vst_io_axi_data_valid),
- .io_axi_data_bits_data(vst_io_axi_data_bits_data),
- .io_axi_data_bits_strb(vst_io_axi_data_bits_strb),
- .io_axi_resp_ready(vst_io_axi_resp_ready),
- .io_axi_resp_valid(vst_io_axi_resp_valid),
- .io_nempty(vst_io_nempty)
- );
- VRegfile vrf ( // @[VRegfile.scala 25:18]
- .clock(vrf_clock),
- .reset(vrf_reset),
- .io_read_0_valid(vrf_io_read_0_valid),
- .io_read_0_addr(vrf_io_read_0_addr),
- .io_read_0_data(vrf_io_read_0_data),
- .io_read_1_valid(vrf_io_read_1_valid),
- .io_read_1_addr(vrf_io_read_1_addr),
- .io_read_1_data(vrf_io_read_1_data),
- .io_read_2_valid(vrf_io_read_2_valid),
- .io_read_2_addr(vrf_io_read_2_addr),
- .io_read_2_data(vrf_io_read_2_data),
- .io_read_3_valid(vrf_io_read_3_valid),
- .io_read_3_addr(vrf_io_read_3_addr),
- .io_read_3_data(vrf_io_read_3_data),
- .io_read_4_valid(vrf_io_read_4_valid),
- .io_read_4_addr(vrf_io_read_4_addr),
- .io_read_4_data(vrf_io_read_4_data),
- .io_read_5_valid(vrf_io_read_5_valid),
- .io_read_5_addr(vrf_io_read_5_addr),
- .io_read_5_data(vrf_io_read_5_data),
- .io_read_6_valid(vrf_io_read_6_valid),
- .io_read_6_addr(vrf_io_read_6_addr),
- .io_read_6_data(vrf_io_read_6_data),
- .io_scalar_0_valid(vrf_io_scalar_0_valid),
- .io_scalar_0_data(vrf_io_scalar_0_data),
- .io_scalar_1_valid(vrf_io_scalar_1_valid),
- .io_scalar_1_data(vrf_io_scalar_1_data),
- .io_write_0_valid(vrf_io_write_0_valid),
- .io_write_0_addr(vrf_io_write_0_addr),
- .io_write_0_data(vrf_io_write_0_data),
- .io_write_1_valid(vrf_io_write_1_valid),
- .io_write_1_addr(vrf_io_write_1_addr),
- .io_write_1_data(vrf_io_write_1_data),
- .io_write_2_valid(vrf_io_write_2_valid),
- .io_write_2_addr(vrf_io_write_2_addr),
- .io_write_2_data(vrf_io_write_2_data),
- .io_write_3_valid(vrf_io_write_3_valid),
- .io_write_3_addr(vrf_io_write_3_addr),
- .io_write_3_data(vrf_io_write_3_data),
- .io_write_4_valid(vrf_io_write_4_valid),
- .io_write_4_addr(vrf_io_write_4_addr),
- .io_write_4_data(vrf_io_write_4_data),
- .io_write_5_valid(vrf_io_write_5_valid),
- .io_write_5_addr(vrf_io_write_5_addr),
- .io_write_5_data(vrf_io_write_5_data),
- .io_whint_0_valid(vrf_io_whint_0_valid),
- .io_whint_0_addr(vrf_io_whint_0_addr),
- .io_whint_1_valid(vrf_io_whint_1_valid),
- .io_whint_1_addr(vrf_io_whint_1_addr),
- .io_whint_2_valid(vrf_io_whint_2_valid),
- .io_whint_2_addr(vrf_io_whint_2_addr),
- .io_whint_3_valid(vrf_io_whint_3_valid),
- .io_whint_3_addr(vrf_io_whint_3_addr),
- .io_conv_valid(vrf_io_conv_valid),
- .io_conv_ready(vrf_io_conv_ready),
- .io_conv_op_conv(vrf_io_conv_op_conv),
- .io_conv_op_init(vrf_io_conv_op_init),
- .io_conv_op_tran(vrf_io_conv_op_tran),
- .io_conv_op_wclr(vrf_io_conv_op_wclr),
- .io_conv_addr1(vrf_io_conv_addr1),
- .io_conv_addr2(vrf_io_conv_addr2),
- .io_conv_mode(vrf_io_conv_mode),
- .io_conv_index(vrf_io_conv_index),
- .io_conv_abias(vrf_io_conv_abias),
- .io_conv_bbias(vrf_io_conv_bbias),
- .io_conv_asign(vrf_io_conv_asign),
- .io_conv_bsign(vrf_io_conv_bsign),
- .io_transpose_data(vrf_io_transpose_data),
- .io_vrfsb_set_valid(vrf_io_vrfsb_set_valid),
- .io_vrfsb_set_bits(vrf_io_vrfsb_set_bits),
- .io_vrfsb_data(vrf_io_vrfsb_data)
- );
- assign io_score_vinst_0_ready = vinst_io_in_0_ready; // @[VCore.scala 75:15]
- assign io_score_vinst_1_ready = vinst_io_in_1_ready; // @[VCore.scala 75:15]
- assign io_score_vinst_2_ready = vinst_io_in_2_ready; // @[VCore.scala 75:15]
- assign io_score_vinst_3_ready = vinst_io_in_3_ready; // @[VCore.scala 75:15]
- assign io_score_rd_0_valid = vinst_io_rd_0_valid; // @[VCore.scala 77:15]
- assign io_score_rd_0_addr = vinst_io_rd_0_addr; // @[VCore.scala 77:15]
- assign io_score_rd_0_data = vinst_io_rd_0_data; // @[VCore.scala 77:15]
- assign io_score_rd_1_valid = vinst_io_rd_1_valid; // @[VCore.scala 77:15]
- assign io_score_rd_1_addr = vinst_io_rd_1_addr; // @[VCore.scala 77:15]
- assign io_score_rd_1_data = vinst_io_rd_1_data; // @[VCore.scala 77:15]
- assign io_score_rd_2_valid = vinst_io_rd_2_valid; // @[VCore.scala 77:15]
- assign io_score_rd_2_addr = vinst_io_rd_2_addr; // @[VCore.scala 77:15]
- assign io_score_rd_2_data = vinst_io_rd_2_data; // @[VCore.scala 77:15]
- assign io_score_rd_3_valid = vinst_io_rd_3_valid; // @[VCore.scala 77:15]
- assign io_score_rd_3_addr = vinst_io_rd_3_addr; // @[VCore.scala 77:15]
- assign io_score_rd_3_data = vinst_io_rd_3_data; // @[VCore.scala 77:15]
- assign io_score_mactive = _io_score_mactive_T_1 | vst_io_nempty; // @[VCore.scala 304:37]
- assign io_score_undef = vdec_io_undef; // @[VCore.scala 98:18]
- assign io_dbus_valid = vldst_io_dbus_valid; // @[VCore.scala 220:11]
- assign io_dbus_write = vldst_io_dbus_write; // @[VCore.scala 220:11]
- assign io_dbus_addr = vldst_io_dbus_addr; // @[VCore.scala 220:11]
- assign io_dbus_adrx = vldst_io_dbus_adrx; // @[VCore.scala 220:11]
- assign io_dbus_size = vldst_io_dbus_size; // @[VCore.scala 220:11]
- assign io_dbus_wdata = vldst_io_dbus_wdata; // @[VCore.scala 220:11]
- assign io_dbus_wmask = vldst_io_dbus_wmask; // @[VCore.scala 220:11]
- assign io_last = vldst_io_last; // @[VCore.scala 221:11]
- assign io_ld_addr_valid = vld_io_axi_addr_valid; // @[VCore.scala 245:9]
- assign io_ld_addr_bits_addr = vld_io_axi_addr_bits_addr; // @[VCore.scala 245:9]
- assign io_ld_addr_bits_id = vld_io_axi_addr_bits_id; // @[VCore.scala 245:9]
- assign io_st_addr_valid = vst_io_axi_addr_valid; // @[VCore.scala 269:9]
- assign io_st_addr_bits_addr = vst_io_axi_addr_bits_addr; // @[VCore.scala 269:9]
- assign io_st_addr_bits_id = vst_io_axi_addr_bits_id; // @[VCore.scala 269:9]
- assign io_st_data_valid = vst_io_axi_data_valid; // @[VCore.scala 269:9]
- assign io_st_data_bits_data = vst_io_axi_data_bits_data; // @[VCore.scala 269:9]
- assign io_st_data_bits_strb = vst_io_axi_data_bits_strb; // @[VCore.scala 269:9]
- assign vinst_clock = clock;
- assign vinst_reset = reset;
- assign vinst_io_in_0_valid = io_score_vinst_0_valid; // @[VCore.scala 75:15]
- assign vinst_io_in_0_addr = io_score_vinst_0_addr; // @[VCore.scala 75:15]
- assign vinst_io_in_0_inst = io_score_vinst_0_inst; // @[VCore.scala 75:15]
- assign vinst_io_in_0_op = io_score_vinst_0_op; // @[VCore.scala 75:15]
- assign vinst_io_in_1_valid = io_score_vinst_1_valid; // @[VCore.scala 75:15]
- assign vinst_io_in_1_addr = io_score_vinst_1_addr; // @[VCore.scala 75:15]
- assign vinst_io_in_1_inst = io_score_vinst_1_inst; // @[VCore.scala 75:15]
- assign vinst_io_in_1_op = io_score_vinst_1_op; // @[VCore.scala 75:15]
- assign vinst_io_in_2_valid = io_score_vinst_2_valid; // @[VCore.scala 75:15]
- assign vinst_io_in_2_addr = io_score_vinst_2_addr; // @[VCore.scala 75:15]
- assign vinst_io_in_2_inst = io_score_vinst_2_inst; // @[VCore.scala 75:15]
- assign vinst_io_in_2_op = io_score_vinst_2_op; // @[VCore.scala 75:15]
- assign vinst_io_in_3_valid = io_score_vinst_3_valid; // @[VCore.scala 75:15]
- assign vinst_io_in_3_addr = io_score_vinst_3_addr; // @[VCore.scala 75:15]
- assign vinst_io_in_3_inst = io_score_vinst_3_inst; // @[VCore.scala 75:15]
- assign vinst_io_in_3_op = io_score_vinst_3_op; // @[VCore.scala 75:15]
- assign vinst_io_rs_0_data = io_score_rs_0_data; // @[VCore.scala 76:15]
- assign vinst_io_rs_1_data = io_score_rs_1_data; // @[VCore.scala 76:15]
- assign vinst_io_rs_2_data = io_score_rs_2_data; // @[VCore.scala 76:15]
- assign vinst_io_rs_3_data = io_score_rs_3_data; // @[VCore.scala 76:15]
- assign vinst_io_rs_4_data = io_score_rs_4_data; // @[VCore.scala 76:15]
- assign vinst_io_rs_5_data = io_score_rs_5_data; // @[VCore.scala 76:15]
- assign vinst_io_rs_6_data = io_score_rs_6_data; // @[VCore.scala 76:15]
- assign vinst_io_rs_7_data = io_score_rs_7_data; // @[VCore.scala 76:15]
- assign vinst_io_out_ready = vdec_io_in_ready; // @[VCore.scala 89:22]
- assign vinst_io_out_stall = vdec_io_stall; // @[VCore.scala 92:22]
- assign vdec_clock = clock;
- assign vdec_reset = reset;
- assign vdec_io_in_valid = vinst_io_out_valid; // @[VCore.scala 88:20]
- assign vdec_io_in_bits_0_valid = vinst_io_out_lane_0_valid; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_0_bits_inst = vinst_io_out_lane_0_bits_inst; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_0_bits_addr = vinst_io_out_lane_0_bits_addr; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_0_bits_data = vinst_io_out_lane_0_bits_data; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_1_valid = vinst_io_out_lane_1_valid; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_1_bits_inst = vinst_io_out_lane_1_bits_inst; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_1_bits_addr = vinst_io_out_lane_1_bits_addr; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_1_bits_data = vinst_io_out_lane_1_bits_data; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_2_valid = vinst_io_out_lane_2_valid; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_2_bits_inst = vinst_io_out_lane_2_bits_inst; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_2_bits_addr = vinst_io_out_lane_2_bits_addr; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_2_bits_data = vinst_io_out_lane_2_bits_data; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_3_valid = vinst_io_out_lane_3_valid; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_3_bits_inst = vinst_io_out_lane_3_bits_inst; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_3_bits_addr = vinst_io_out_lane_3_bits_addr; // @[VCore.scala 95:24]
- assign vdec_io_in_bits_3_bits_data = vinst_io_out_lane_3_bits_data; // @[VCore.scala 95:24]
- assign vdec_io_out_0_ready = _vdec_io_out_0_ready_T_6 | stready[0]; // @[VCore.scala 298:40]
- assign vdec_io_out_1_ready = _vdec_io_out_1_ready_T_6 | stready[1]; // @[VCore.scala 298:40]
- assign vdec_io_out_2_ready = _vdec_io_out_2_ready_T_6 | stready[2]; // @[VCore.scala 298:40]
- assign vdec_io_out_3_ready = _vdec_io_out_3_ready_T_6 | stready[3]; // @[VCore.scala 298:40]
- assign vdec_io_active = _vdec_io_active_T_1 | vst_io_active; // @[VCore.scala 86:72]
- assign vdec_io_vrfsb_data = vrf_io_vrfsb_data; // @[VCore.scala 84:17]
- assign valu_clock = clock;
- assign valu_reset = reset;
- assign valu_io_in_valid = aluvalid != 4'h0; // @[VCore.scala 140:32]
- assign valu_io_in_bits_0_valid = aluvalid[0]; // @[VCore.scala 143:41]
- assign valu_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vd_addr = vdec_io_out_0_bits_vd_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_ve_addr = vdec_io_out_0_bits_ve_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vf_addr = vdec_io_out_0_bits_vf_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vg_addr = vdec_io_out_0_bits_vg_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vs_tag = vdec_io_out_0_bits_vs_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vt_valid = vdec_io_out_0_bits_vt_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vt_addr = vdec_io_out_0_bits_vt_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vt_tag = vdec_io_out_0_bits_vt_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vu_valid = vdec_io_out_0_bits_vu_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vu_addr = vdec_io_out_0_bits_vu_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vu_tag = vdec_io_out_0_bits_vu_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vx_valid = vdec_io_out_0_bits_vx_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vx_addr = vdec_io_out_0_bits_vx_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vx_tag = vdec_io_out_0_bits_vx_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vy_valid = vdec_io_out_0_bits_vy_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vy_addr = vdec_io_out_0_bits_vy_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vy_tag = vdec_io_out_0_bits_vy_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vz_valid = vdec_io_out_0_bits_vz_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vz_addr = vdec_io_out_0_bits_vz_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_vz_tag = vdec_io_out_0_bits_vz_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_sv_valid = vdec_io_out_0_bits_sv_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 144:29]
- assign valu_io_in_bits_0_bits_cmdsync = vdec_io_out_0_bits_cmdsync; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_valid = aluvalid[1]; // @[VCore.scala 143:41]
- assign valu_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vd_addr = vdec_io_out_1_bits_vd_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_ve_addr = vdec_io_out_1_bits_ve_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vf_addr = vdec_io_out_1_bits_vf_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vg_addr = vdec_io_out_1_bits_vg_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vs_tag = vdec_io_out_1_bits_vs_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vt_valid = vdec_io_out_1_bits_vt_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vt_addr = vdec_io_out_1_bits_vt_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vt_tag = vdec_io_out_1_bits_vt_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vu_valid = vdec_io_out_1_bits_vu_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vu_addr = vdec_io_out_1_bits_vu_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vu_tag = vdec_io_out_1_bits_vu_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vx_valid = vdec_io_out_1_bits_vx_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vx_addr = vdec_io_out_1_bits_vx_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vx_tag = vdec_io_out_1_bits_vx_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vy_valid = vdec_io_out_1_bits_vy_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vy_addr = vdec_io_out_1_bits_vy_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vy_tag = vdec_io_out_1_bits_vy_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vz_valid = vdec_io_out_1_bits_vz_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vz_addr = vdec_io_out_1_bits_vz_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_vz_tag = vdec_io_out_1_bits_vz_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_sv_valid = vdec_io_out_1_bits_sv_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 144:29]
- assign valu_io_in_bits_1_bits_cmdsync = vdec_io_out_1_bits_cmdsync; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_valid = aluvalid[2]; // @[VCore.scala 143:41]
- assign valu_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vd_addr = vdec_io_out_2_bits_vd_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_ve_addr = vdec_io_out_2_bits_ve_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vf_addr = vdec_io_out_2_bits_vf_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vg_addr = vdec_io_out_2_bits_vg_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vs_tag = vdec_io_out_2_bits_vs_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vt_valid = vdec_io_out_2_bits_vt_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vt_addr = vdec_io_out_2_bits_vt_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vt_tag = vdec_io_out_2_bits_vt_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vu_valid = vdec_io_out_2_bits_vu_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vu_addr = vdec_io_out_2_bits_vu_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vu_tag = vdec_io_out_2_bits_vu_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vx_valid = vdec_io_out_2_bits_vx_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vx_addr = vdec_io_out_2_bits_vx_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vx_tag = vdec_io_out_2_bits_vx_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vy_valid = vdec_io_out_2_bits_vy_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vy_addr = vdec_io_out_2_bits_vy_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vy_tag = vdec_io_out_2_bits_vy_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vz_valid = vdec_io_out_2_bits_vz_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vz_addr = vdec_io_out_2_bits_vz_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_vz_tag = vdec_io_out_2_bits_vz_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_sv_valid = vdec_io_out_2_bits_sv_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 144:29]
- assign valu_io_in_bits_2_bits_cmdsync = vdec_io_out_2_bits_cmdsync; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_valid = aluvalid[3]; // @[VCore.scala 143:41]
- assign valu_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vd_addr = vdec_io_out_3_bits_vd_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_ve_addr = vdec_io_out_3_bits_ve_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vf_addr = vdec_io_out_3_bits_vf_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vg_addr = vdec_io_out_3_bits_vg_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vs_tag = vdec_io_out_3_bits_vs_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vt_valid = vdec_io_out_3_bits_vt_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vt_addr = vdec_io_out_3_bits_vt_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vt_tag = vdec_io_out_3_bits_vt_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vu_valid = vdec_io_out_3_bits_vu_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vu_addr = vdec_io_out_3_bits_vu_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vu_tag = vdec_io_out_3_bits_vu_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vx_valid = vdec_io_out_3_bits_vx_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vx_addr = vdec_io_out_3_bits_vx_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vx_tag = vdec_io_out_3_bits_vx_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vy_valid = vdec_io_out_3_bits_vy_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vy_addr = vdec_io_out_3_bits_vy_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vy_tag = vdec_io_out_3_bits_vy_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vz_valid = vdec_io_out_3_bits_vz_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vz_addr = vdec_io_out_3_bits_vz_addr; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_vz_tag = vdec_io_out_3_bits_vz_tag; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_sv_valid = vdec_io_out_3_bits_sv_valid; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 144:29]
- assign valu_io_in_bits_3_bits_cmdsync = vdec_io_out_3_bits_cmdsync; // @[VCore.scala 144:29]
- assign valu_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 171:17]
- assign valu_io_read_0_data = vrf_io_read_0_data; // @[VCore.scala 154:26]
- assign valu_io_read_1_data = vrf_io_read_1_data; // @[VCore.scala 154:26]
- assign valu_io_read_2_data = vrf_io_read_2_data; // @[VCore.scala 154:26]
- assign valu_io_read_3_data = vrf_io_read_3_data; // @[VCore.scala 154:26]
- assign valu_io_read_4_data = vrf_io_read_4_data; // @[VCore.scala 154:26]
- assign valu_io_read_5_data = vrf_io_read_5_data; // @[VCore.scala 154:26]
- assign vconv_clock = clock;
- assign vconv_reset = reset;
- assign vconv_io_in_valid = convvalid != 4'h0; // @[VCore.scala 185:34]
- assign vconv_io_in_bits_0_valid = convvalid[0]; // @[VCore.scala 188:43]
- assign vconv_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_0_bits_vu_addr = vdec_io_out_0_bits_vu_addr; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_1_valid = convvalid[1]; // @[VCore.scala 188:43]
- assign vconv_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_1_bits_vu_addr = vdec_io_out_1_bits_vu_addr; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_2_valid = convvalid[2]; // @[VCore.scala 188:43]
- assign vconv_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_2_bits_vu_addr = vdec_io_out_2_bits_vu_addr; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_3_valid = convvalid[3]; // @[VCore.scala 188:43]
- assign vconv_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_3_bits_vu_addr = vdec_io_out_3_bits_vu_addr; // @[VCore.scala 189:30]
- assign vconv_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 189:30]
- assign vconv_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 194:18]
- assign vldst_clock = clock;
- assign vldst_reset = reset;
- assign vldst_io_in_valid = ldstvalid != 4'h0; // @[VCore.scala 208:34]
- assign vldst_io_in_bits_0_valid = ldstvalid[0]; // @[VCore.scala 211:43]
- assign vldst_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_0_bits_vd_valid = vdec_io_out_0_bits_vd_valid; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_0_bits_vd_addr = vdec_io_out_0_bits_vd_addr; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_0_bits_vs_tag = vdec_io_out_0_bits_vs_tag; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_1_valid = ldstvalid[1]; // @[VCore.scala 211:43]
- assign vldst_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_1_bits_vd_valid = vdec_io_out_1_bits_vd_valid; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_1_bits_vd_addr = vdec_io_out_1_bits_vd_addr; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_1_bits_vs_tag = vdec_io_out_1_bits_vs_tag; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_2_valid = ldstvalid[2]; // @[VCore.scala 211:43]
- assign vldst_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_2_bits_vd_valid = vdec_io_out_2_bits_vd_valid; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_2_bits_vd_addr = vdec_io_out_2_bits_vd_addr; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_2_bits_vs_tag = vdec_io_out_2_bits_vs_tag; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_3_valid = ldstvalid[3]; // @[VCore.scala 211:43]
- assign vldst_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_3_bits_vd_valid = vdec_io_out_3_bits_vd_valid; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_3_bits_vd_addr = vdec_io_out_3_bits_vd_addr; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_3_bits_vs_tag = vdec_io_out_3_bits_vs_tag; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 212:30]
- assign vldst_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 212:30]
- assign vldst_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 218:18]
- assign vldst_io_read_ready = ~vst_io_read_valid; // @[VCore.scala 215:26]
- assign vldst_io_read_data = vrf_io_read_6_data; // @[VCore.scala 216:22]
- assign vldst_io_dbus_ready = io_dbus_ready; // @[VCore.scala 220:11]
- assign vldst_io_dbus_rdata = io_dbus_rdata; // @[VCore.scala 220:11]
- assign vld_clock = clock;
- assign vld_reset = reset;
- assign vld_io_in_valid = ldvalid != 4'h0; // @[VCore.scala 238:30]
- assign vld_io_in_bits_0_valid = ldvalid[0]; // @[VCore.scala 241:39]
- assign vld_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 242:28]
- assign vld_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 242:28]
- assign vld_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 242:28]
- assign vld_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 242:28]
- assign vld_io_in_bits_0_bits_vd_valid = vdec_io_out_0_bits_vd_valid; // @[VCore.scala 242:28]
- assign vld_io_in_bits_0_bits_vd_addr = vdec_io_out_0_bits_vd_addr; // @[VCore.scala 242:28]
- assign vld_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 242:28]
- assign vld_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 242:28]
- assign vld_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 242:28]
- assign vld_io_in_bits_1_valid = ldvalid[1]; // @[VCore.scala 241:39]
- assign vld_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 242:28]
- assign vld_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 242:28]
- assign vld_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 242:28]
- assign vld_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 242:28]
- assign vld_io_in_bits_1_bits_vd_valid = vdec_io_out_1_bits_vd_valid; // @[VCore.scala 242:28]
- assign vld_io_in_bits_1_bits_vd_addr = vdec_io_out_1_bits_vd_addr; // @[VCore.scala 242:28]
- assign vld_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 242:28]
- assign vld_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 242:28]
- assign vld_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 242:28]
- assign vld_io_in_bits_2_valid = ldvalid[2]; // @[VCore.scala 241:39]
- assign vld_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 242:28]
- assign vld_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 242:28]
- assign vld_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 242:28]
- assign vld_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 242:28]
- assign vld_io_in_bits_2_bits_vd_valid = vdec_io_out_2_bits_vd_valid; // @[VCore.scala 242:28]
- assign vld_io_in_bits_2_bits_vd_addr = vdec_io_out_2_bits_vd_addr; // @[VCore.scala 242:28]
- assign vld_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 242:28]
- assign vld_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 242:28]
- assign vld_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 242:28]
- assign vld_io_in_bits_3_valid = ldvalid[3]; // @[VCore.scala 241:39]
- assign vld_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 242:28]
- assign vld_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 242:28]
- assign vld_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 242:28]
- assign vld_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 242:28]
- assign vld_io_in_bits_3_bits_vd_valid = vdec_io_out_3_bits_vd_valid; // @[VCore.scala 242:28]
- assign vld_io_in_bits_3_bits_vd_addr = vdec_io_out_3_bits_vd_addr; // @[VCore.scala 242:28]
- assign vld_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 242:28]
- assign vld_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 242:28]
- assign vld_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 242:28]
- assign vld_io_axi_addr_ready = io_ld_addr_ready; // @[VCore.scala 245:9]
- assign vld_io_axi_data_valid = io_ld_data_valid; // @[VCore.scala 245:9]
- assign vld_io_axi_data_bits_id = io_ld_data_bits_id; // @[VCore.scala 245:9]
- assign vld_io_axi_data_bits_data = io_ld_data_bits_data; // @[VCore.scala 245:9]
- assign vst_clock = clock;
- assign vst_reset = reset;
- assign vst_io_in_valid = stvalid != 4'h0; // @[VCore.scala 262:30]
- assign vst_io_in_bits_0_valid = stvalid[0]; // @[VCore.scala 265:39]
- assign vst_io_in_bits_0_bits_op = vdec_io_out_0_bits_op; // @[VCore.scala 266:28]
- assign vst_io_in_bits_0_bits_f2 = vdec_io_out_0_bits_f2; // @[VCore.scala 266:28]
- assign vst_io_in_bits_0_bits_sz = vdec_io_out_0_bits_sz; // @[VCore.scala 266:28]
- assign vst_io_in_bits_0_bits_m = vdec_io_out_0_bits_m; // @[VCore.scala 266:28]
- assign vst_io_in_bits_0_bits_vs_valid = vdec_io_out_0_bits_vs_valid; // @[VCore.scala 266:28]
- assign vst_io_in_bits_0_bits_vs_addr = vdec_io_out_0_bits_vs_addr; // @[VCore.scala 266:28]
- assign vst_io_in_bits_0_bits_vs_tag = vdec_io_out_0_bits_vs_tag; // @[VCore.scala 266:28]
- assign vst_io_in_bits_0_bits_sv_addr = vdec_io_out_0_bits_sv_addr; // @[VCore.scala 266:28]
- assign vst_io_in_bits_0_bits_sv_data = vdec_io_out_0_bits_sv_data; // @[VCore.scala 266:28]
- assign vst_io_in_bits_1_valid = stvalid[1]; // @[VCore.scala 265:39]
- assign vst_io_in_bits_1_bits_op = vdec_io_out_1_bits_op; // @[VCore.scala 266:28]
- assign vst_io_in_bits_1_bits_f2 = vdec_io_out_1_bits_f2; // @[VCore.scala 266:28]
- assign vst_io_in_bits_1_bits_sz = vdec_io_out_1_bits_sz; // @[VCore.scala 266:28]
- assign vst_io_in_bits_1_bits_m = vdec_io_out_1_bits_m; // @[VCore.scala 266:28]
- assign vst_io_in_bits_1_bits_vs_valid = vdec_io_out_1_bits_vs_valid; // @[VCore.scala 266:28]
- assign vst_io_in_bits_1_bits_vs_addr = vdec_io_out_1_bits_vs_addr; // @[VCore.scala 266:28]
- assign vst_io_in_bits_1_bits_vs_tag = vdec_io_out_1_bits_vs_tag; // @[VCore.scala 266:28]
- assign vst_io_in_bits_1_bits_sv_addr = vdec_io_out_1_bits_sv_addr; // @[VCore.scala 266:28]
- assign vst_io_in_bits_1_bits_sv_data = vdec_io_out_1_bits_sv_data; // @[VCore.scala 266:28]
- assign vst_io_in_bits_2_valid = stvalid[2]; // @[VCore.scala 265:39]
- assign vst_io_in_bits_2_bits_op = vdec_io_out_2_bits_op; // @[VCore.scala 266:28]
- assign vst_io_in_bits_2_bits_f2 = vdec_io_out_2_bits_f2; // @[VCore.scala 266:28]
- assign vst_io_in_bits_2_bits_sz = vdec_io_out_2_bits_sz; // @[VCore.scala 266:28]
- assign vst_io_in_bits_2_bits_m = vdec_io_out_2_bits_m; // @[VCore.scala 266:28]
- assign vst_io_in_bits_2_bits_vs_valid = vdec_io_out_2_bits_vs_valid; // @[VCore.scala 266:28]
- assign vst_io_in_bits_2_bits_vs_addr = vdec_io_out_2_bits_vs_addr; // @[VCore.scala 266:28]
- assign vst_io_in_bits_2_bits_vs_tag = vdec_io_out_2_bits_vs_tag; // @[VCore.scala 266:28]
- assign vst_io_in_bits_2_bits_sv_addr = vdec_io_out_2_bits_sv_addr; // @[VCore.scala 266:28]
- assign vst_io_in_bits_2_bits_sv_data = vdec_io_out_2_bits_sv_data; // @[VCore.scala 266:28]
- assign vst_io_in_bits_3_valid = stvalid[3]; // @[VCore.scala 265:39]
- assign vst_io_in_bits_3_bits_op = vdec_io_out_3_bits_op; // @[VCore.scala 266:28]
- assign vst_io_in_bits_3_bits_f2 = vdec_io_out_3_bits_f2; // @[VCore.scala 266:28]
- assign vst_io_in_bits_3_bits_sz = vdec_io_out_3_bits_sz; // @[VCore.scala 266:28]
- assign vst_io_in_bits_3_bits_m = vdec_io_out_3_bits_m; // @[VCore.scala 266:28]
- assign vst_io_in_bits_3_bits_vs_valid = vdec_io_out_3_bits_vs_valid; // @[VCore.scala 266:28]
- assign vst_io_in_bits_3_bits_vs_addr = vdec_io_out_3_bits_vs_addr; // @[VCore.scala 266:28]
- assign vst_io_in_bits_3_bits_vs_tag = vdec_io_out_3_bits_vs_tag; // @[VCore.scala 266:28]
- assign vst_io_in_bits_3_bits_sv_addr = vdec_io_out_3_bits_sv_addr; // @[VCore.scala 266:28]
- assign vst_io_in_bits_3_bits_sv_data = vdec_io_out_3_bits_sv_data; // @[VCore.scala 266:28]
- assign vst_io_vrfsb = vrf_io_vrfsb_data; // @[VCore.scala 271:16]
- assign vst_io_read_ready = 1'h1; // @[VCore.scala 273:21]
- assign vst_io_read_data = vrf_io_read_6_data; // @[VCore.scala 274:20]
- assign vst_io_axi_addr_ready = io_st_addr_ready; // @[VCore.scala 269:9]
- assign vst_io_axi_data_ready = io_st_data_ready; // @[VCore.scala 269:9]
- assign vst_io_axi_resp_valid = io_st_resp_valid; // @[VCore.scala 269:9]
- assign vrf_clock = clock;
- assign vrf_reset = reset;
- assign vrf_io_read_0_valid = valu_io_read_0_valid; // @[VCore.scala 148:26]
- assign vrf_io_read_0_addr = valu_io_read_0_addr; // @[VCore.scala 149:25]
- assign vrf_io_read_1_valid = valu_io_read_1_valid; // @[VCore.scala 148:26]
- assign vrf_io_read_1_addr = valu_io_read_1_addr; // @[VCore.scala 149:25]
- assign vrf_io_read_2_valid = valu_io_read_2_valid; // @[VCore.scala 148:26]
- assign vrf_io_read_2_addr = valu_io_read_2_addr; // @[VCore.scala 149:25]
- assign vrf_io_read_3_valid = valu_io_read_3_valid; // @[VCore.scala 148:26]
- assign vrf_io_read_3_addr = valu_io_read_3_addr; // @[VCore.scala 149:25]
- assign vrf_io_read_4_valid = valu_io_read_4_valid; // @[VCore.scala 148:26]
- assign vrf_io_read_4_addr = valu_io_read_4_addr; // @[VCore.scala 149:25]
- assign vrf_io_read_5_valid = valu_io_read_5_valid; // @[VCore.scala 148:26]
- assign vrf_io_read_5_addr = valu_io_read_5_addr; // @[VCore.scala 149:25]
- assign vrf_io_read_6_valid = vst_io_read_valid | vldst_io_read_valid; // @[VCore.scala 288:45]
- assign vrf_io_read_6_addr = vst_io_read_valid ? vst_io_read_addr : vldst_io_read_addr; // @[VCore.scala 289:29]
- assign vrf_io_scalar_0_valid = valu_io_scalar_0_valid; // @[VCore.scala 167:28]
- assign vrf_io_scalar_0_data = valu_io_scalar_0_data; // @[VCore.scala 168:27]
- assign vrf_io_scalar_1_valid = valu_io_scalar_1_valid; // @[VCore.scala 167:28]
- assign vrf_io_scalar_1_data = valu_io_scalar_1_data; // @[VCore.scala 168:27]
- assign vrf_io_write_0_valid = valu_io_write_0_valid; // @[VCore.scala 158:27]
- assign vrf_io_write_0_addr = valu_io_write_0_addr; // @[VCore.scala 159:26]
- assign vrf_io_write_0_data = valu_io_write_0_data; // @[VCore.scala 160:26]
- assign vrf_io_write_1_valid = valu_io_write_1_valid; // @[VCore.scala 158:27]
- assign vrf_io_write_1_addr = valu_io_write_1_addr; // @[VCore.scala 159:26]
- assign vrf_io_write_1_data = valu_io_write_1_data; // @[VCore.scala 160:26]
- assign vrf_io_write_2_valid = valu_io_write_2_valid; // @[VCore.scala 158:27]
- assign vrf_io_write_2_addr = valu_io_write_2_addr; // @[VCore.scala 159:26]
- assign vrf_io_write_2_data = valu_io_write_2_data; // @[VCore.scala 160:26]
- assign vrf_io_write_3_valid = valu_io_write_3_valid; // @[VCore.scala 158:27]
- assign vrf_io_write_3_addr = valu_io_write_3_addr; // @[VCore.scala 159:26]
- assign vrf_io_write_3_data = valu_io_write_3_data; // @[VCore.scala 160:26]
- assign vrf_io_write_4_valid = vldst_io_write_valid; // @[VCore.scala 278:25]
- assign vrf_io_write_4_addr = vldst_io_write_addr; // @[VCore.scala 279:24]
- assign vrf_io_write_4_data = vldst_io_write_data; // @[VCore.scala 280:24]
- assign vrf_io_write_5_valid = vld_io_write_valid; // @[VCore.scala 282:25]
- assign vrf_io_write_5_addr = vld_io_write_addr; // @[VCore.scala 283:24]
- assign vrf_io_write_5_data = vld_io_write_data; // @[VCore.scala 284:24]
- assign vrf_io_whint_0_valid = valu_io_whint_0_valid; // @[VCore.scala 162:27]
- assign vrf_io_whint_0_addr = valu_io_whint_0_addr; // @[VCore.scala 163:26]
- assign vrf_io_whint_1_valid = valu_io_whint_1_valid; // @[VCore.scala 162:27]
- assign vrf_io_whint_1_addr = valu_io_whint_1_addr; // @[VCore.scala 163:26]
- assign vrf_io_whint_2_valid = valu_io_whint_2_valid; // @[VCore.scala 162:27]
- assign vrf_io_whint_2_addr = valu_io_whint_2_addr; // @[VCore.scala 163:26]
- assign vrf_io_whint_3_valid = valu_io_whint_3_valid; // @[VCore.scala 162:27]
- assign vrf_io_whint_3_addr = valu_io_whint_3_addr; // @[VCore.scala 163:26]
- assign vrf_io_conv_valid = vconv_io_out_valid; // @[VCore.scala 192:15]
- assign vrf_io_conv_ready = vconv_io_out_ready; // @[VCore.scala 192:15]
- assign vrf_io_conv_op_conv = vconv_io_out_op_conv; // @[VCore.scala 192:15]
- assign vrf_io_conv_op_init = vconv_io_out_op_init; // @[VCore.scala 192:15]
- assign vrf_io_conv_op_tran = vconv_io_out_op_tran; // @[VCore.scala 192:15]
- assign vrf_io_conv_op_wclr = vconv_io_out_op_wclr; // @[VCore.scala 192:15]
- assign vrf_io_conv_addr1 = vconv_io_out_addr1; // @[VCore.scala 192:15]
- assign vrf_io_conv_addr2 = vconv_io_out_addr2; // @[VCore.scala 192:15]
- assign vrf_io_conv_mode = vconv_io_out_mode; // @[VCore.scala 192:15]
- assign vrf_io_conv_index = vconv_io_out_index; // @[VCore.scala 192:15]
- assign vrf_io_conv_abias = vconv_io_out_abias; // @[VCore.scala 192:15]
- assign vrf_io_conv_bbias = vconv_io_out_bbias; // @[VCore.scala 192:15]
- assign vrf_io_conv_asign = vconv_io_out_asign; // @[VCore.scala 192:15]
- assign vrf_io_conv_bsign = vconv_io_out_bsign; // @[VCore.scala 192:15]
- assign vrf_io_vrfsb_set_valid = vdec_io_vrfsb_set_valid; // @[VCore.scala 84:17]
- assign vrf_io_vrfsb_set_bits = vdec_io_vrfsb_set_bits; // @[VCore.scala 84:17]
- always @(posedge clock) begin
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~_T_7) begin
- $fatal; // @[VCore.scala 79:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~_T_7) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VCore.scala:79 assert(PopCount(Cat(vst.io.read.valid && vst.io.read.ready,\n"); // @[VCore.scala 79:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_9 & ~(~(vdec_io_in_valid & ~vdec_io_in_ready))) begin
- $fatal; // @[VCore.scala 90:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_9 & ~(~(vdec_io_in_valid & ~vdec_io_in_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at VCore.scala:90 assert(!(vdec.io.in.valid && !vdec.io.in.ready))\n"); // @[VCore.scala 90:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
-endmodule
-module DBusMux(
- input io_vldst,
- input io_vlast,
- input io_vcore_valid,
- output io_vcore_ready,
- input io_vcore_write,
- input [31:0] io_vcore_addr,
- input [31:0] io_vcore_adrx,
- input [5:0] io_vcore_size,
- input [255:0] io_vcore_wdata,
- input [31:0] io_vcore_wmask,
- output [255:0] io_vcore_rdata,
- input io_score_valid,
- output io_score_ready,
- input io_score_write,
- input [31:0] io_score_addr,
- input [31:0] io_score_adrx,
- input [5:0] io_score_size,
- input [255:0] io_score_wdata,
- input [31:0] io_score_wmask,
- output [255:0] io_score_rdata,
- output io_dbus_valid,
- input io_dbus_ready,
- output io_dbus_write,
- output [31:0] io_dbus_addr,
- output [31:0] io_dbus_adrx,
- output [5:0] io_dbus_size,
- output [255:0] io_dbus_wdata,
- output [31:0] io_dbus_wmask,
- input [255:0] io_dbus_rdata
-);
- assign io_vcore_ready = io_dbus_ready & io_vldst; // @[DBusMux.scala 49:35]
- assign io_vcore_rdata = io_dbus_rdata; // @[DBusMux.scala 45:18]
- assign io_score_ready = io_dbus_ready & (~io_vldst | io_vcore_valid & io_vlast); // @[DBusMux.scala 48:35]
- assign io_score_rdata = io_dbus_rdata; // @[DBusMux.scala 44:18]
- assign io_dbus_valid = io_vldst ? io_vcore_valid : io_score_valid; // @[DBusMux.scala 36:23]
- assign io_dbus_write = io_vldst ? io_vcore_write : io_score_write; // @[DBusMux.scala 37:23]
- assign io_dbus_addr = io_vldst ? io_vcore_addr : io_score_addr; // @[DBusMux.scala 38:23]
- assign io_dbus_adrx = io_vldst ? io_vcore_adrx : io_score_adrx; // @[DBusMux.scala 39:23]
- assign io_dbus_size = io_vldst ? io_vcore_size : io_score_size; // @[DBusMux.scala 40:23]
- assign io_dbus_wdata = io_vldst ? io_vcore_wdata : io_score_wdata; // @[DBusMux.scala 41:23]
- assign io_dbus_wmask = io_vldst ? io_vcore_wmask : io_score_wmask; // @[DBusMux.scala 42:23]
-endmodule
-module DBus2Axi(
- input clock,
- input reset,
- input io_dbus_valid,
- output io_dbus_ready,
- input io_dbus_write,
- input [31:0] io_dbus_addr,
- input [255:0] io_dbus_wdata,
- input [31:0] io_dbus_wmask,
- output [255:0] io_dbus_rdata,
- input io_axi_write_addr_ready,
- output io_axi_write_addr_valid,
- output [31:0] io_axi_write_addr_bits_addr,
- output io_axi_write_data_valid,
- output [255:0] io_axi_write_data_bits_data,
- output [31:0] io_axi_write_data_bits_strb,
- input io_axi_read_addr_ready,
- output io_axi_read_addr_valid,
- output [31:0] io_axi_read_addr_bits_addr,
- output io_axi_read_data_ready,
- input io_axi_read_data_valid,
- input [255:0] io_axi_read_data_bits_data
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [255:0] _RAND_1;
-`endif // RANDOMIZE_REG_INIT
- reg sraddrActive; // @[DBus2Axi.scala 35:29]
- reg [255:0] sdata; // @[DBus2Axi.scala 36:18]
- wire _T = io_axi_read_data_valid & io_axi_read_data_ready; // @[DBus2Axi.scala 38:32]
- wire _T_2 = ~reset; // @[DBus2Axi.scala 40:11]
- wire _T_3 = ~sraddrActive; // @[DBus2Axi.scala 40:11]
- wire _T_8 = io_axi_read_addr_valid & io_axi_read_addr_ready; // @[DBus2Axi.scala 42:39]
- wire _GEN_0 = io_axi_read_addr_valid & io_axi_read_addr_ready | sraddrActive; // @[DBus2Axi.scala 42:66 43:18 35:29]
- wire _io_dbus_ready_T = io_axi_write_addr_valid & io_axi_write_addr_ready; // @[DBus2Axi.scala 53:48]
- wire _io_dbus_ready_T_1 = io_axi_read_data_valid & sraddrActive; // @[DBus2Axi.scala 54:47]
- wire _GEN_3 = _T & ~reset; // @[DBus2Axi.scala 40:11]
- wire _GEN_11 = ~_T & _T_8 & _T_2; // @[DBus2Axi.scala 44:11]
- assign io_dbus_ready = io_dbus_write ? _io_dbus_ready_T : _io_dbus_ready_T_1; // @[DBus2Axi.scala 52:23]
- assign io_dbus_rdata = sdata; // @[DBus2Axi.scala 55:17]
- assign io_axi_write_addr_valid = io_dbus_valid & io_dbus_write; // @[DBus2Axi.scala 59:44]
- assign io_axi_write_addr_bits_addr = {io_dbus_addr[31:5],5'h0}; // @[Cat.scala 31:58]
- assign io_axi_write_data_valid = io_dbus_valid & io_dbus_write; // @[DBus2Axi.scala 63:44]
- assign io_axi_write_data_bits_data = io_dbus_wdata; // @[DBus2Axi.scala 65:31]
- assign io_axi_write_data_bits_strb = io_dbus_wmask; // @[DBus2Axi.scala 64:31]
- assign io_axi_read_addr_valid = io_dbus_valid & ~io_dbus_write & _T_3; // @[DBus2Axi.scala 69:61]
- assign io_axi_read_addr_bits_addr = {io_dbus_addr[31:5],5'h0}; // @[Cat.scala 31:58]
- assign io_axi_read_data_ready = 1'h1; // @[DBus2Axi.scala 73:26]
- always @(posedge clock) begin
- if (_T) begin // @[DBus2Axi.scala 48:59]
- sdata <= io_axi_read_data_bits_data; // @[DBus2Axi.scala 49:11]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T & ~reset & ~sraddrActive) begin
- $fatal; // @[DBus2Axi.scala 40:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T & ~reset & ~sraddrActive) begin
- $fwrite(32'h80000002,"Assertion failed\n at DBus2Axi.scala:40 assert(sraddrActive)\n"); // @[DBus2Axi.scala 40:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_3 & ~(~io_axi_read_addr_valid)) begin
- $fatal; // @[DBus2Axi.scala 41:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_3 & ~(~io_axi_read_addr_valid)) begin
- $fwrite(32'h80000002,"Assertion failed\n at DBus2Axi.scala:41 assert(!io.axi.read.addr.valid)\n"); // @[DBus2Axi.scala 41:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~_T & _T_8 & _T_2 & ~_T_3) begin
- $fatal; // @[DBus2Axi.scala 44:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~_T & _T_8 & _T_2 & ~_T_3) begin
- $fwrite(32'h80000002,"Assertion failed\n at DBus2Axi.scala:44 assert(!sraddrActive)\n"); // @[DBus2Axi.scala 44:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_11 & ~(~io_axi_read_data_valid)) begin
- $fatal; // @[DBus2Axi.scala 45:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_11 & ~(~io_axi_read_data_valid)) begin
- $fwrite(32'h80000002,"Assertion failed\n at DBus2Axi.scala:45 assert(!io.axi.read.data.valid)\n"); // @[DBus2Axi.scala 45:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[DBus2Axi.scala 38:59]
- sraddrActive <= 1'h0; // @[DBus2Axi.scala 39:18]
- end else if (io_axi_read_data_valid & io_axi_read_data_ready) begin
- sraddrActive <= 1'h0;
- end else begin
- sraddrActive <= _GEN_0;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- sraddrActive = _RAND_0[0:0];
- _RAND_1 = {8{`RANDOM}};
- sdata = _RAND_1[255:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- sraddrActive = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Core(
- input clock,
- input reset,
- input [31:0] io_csr_in_value_0,
- output io_halted,
- output io_fault,
- output io_ibus_valid,
- input io_ibus_ready,
- output [31:0] io_ibus_addr,
- input [255:0] io_ibus_rdata,
- output io_dbus_valid,
- input io_dbus_ready,
- output io_dbus_write,
- output [31:0] io_dbus_addr,
- output [31:0] io_dbus_adrx,
- output [5:0] io_dbus_size,
- output [255:0] io_dbus_wdata,
- output [31:0] io_dbus_wmask,
- input [255:0] io_dbus_rdata,
- input io_axi0_write_addr_ready,
- output io_axi0_write_addr_valid,
- output [31:0] io_axi0_write_addr_bits_addr,
- output [5:0] io_axi0_write_addr_bits_id,
- input io_axi0_write_data_ready,
- output io_axi0_write_data_valid,
- output [255:0] io_axi0_write_data_bits_data,
- output [31:0] io_axi0_write_data_bits_strb,
- input io_axi0_write_resp_valid,
- input io_axi0_read_addr_ready,
- output io_axi0_read_addr_valid,
- output [31:0] io_axi0_read_addr_bits_addr,
- output [5:0] io_axi0_read_addr_bits_id,
- input io_axi0_read_data_valid,
- input [5:0] io_axi0_read_data_bits_id,
- input [255:0] io_axi0_read_data_bits_data,
- input io_axi1_write_addr_ready,
- output io_axi1_write_addr_valid,
- output [31:0] io_axi1_write_addr_bits_addr,
- output io_axi1_write_data_valid,
- output [255:0] io_axi1_write_data_bits_data,
- output [31:0] io_axi1_write_data_bits_strb,
- input io_axi1_read_addr_ready,
- output io_axi1_read_addr_valid,
- output [31:0] io_axi1_read_addr_bits_addr,
- input io_axi1_read_data_valid,
- input [255:0] io_axi1_read_data_bits_data,
- output io_iflush_valid,
- output io_dflush_valid,
- input io_dflush_ready,
- output io_dflush_all,
- output io_slog_valid,
- output [4:0] io_slog_addr,
- output [31:0] io_slog_data
-);
- wire score_clock; // @[SCore.scala 25:18]
- wire score_reset; // @[SCore.scala 25:18]
- wire [31:0] score_io_csr_in_value_0; // @[SCore.scala 25:18]
- wire score_io_halted; // @[SCore.scala 25:18]
- wire score_io_fault; // @[SCore.scala 25:18]
- wire score_io_ibus_valid; // @[SCore.scala 25:18]
- wire score_io_ibus_ready; // @[SCore.scala 25:18]
- wire [31:0] score_io_ibus_addr; // @[SCore.scala 25:18]
- wire [255:0] score_io_ibus_rdata; // @[SCore.scala 25:18]
- wire score_io_dbus_valid; // @[SCore.scala 25:18]
- wire score_io_dbus_ready; // @[SCore.scala 25:18]
- wire score_io_dbus_write; // @[SCore.scala 25:18]
- wire [31:0] score_io_dbus_addr; // @[SCore.scala 25:18]
- wire [31:0] score_io_dbus_adrx; // @[SCore.scala 25:18]
- wire [5:0] score_io_dbus_size; // @[SCore.scala 25:18]
- wire [255:0] score_io_dbus_wdata; // @[SCore.scala 25:18]
- wire [31:0] score_io_dbus_wmask; // @[SCore.scala 25:18]
- wire [255:0] score_io_dbus_rdata; // @[SCore.scala 25:18]
- wire score_io_ubus_valid; // @[SCore.scala 25:18]
- wire score_io_ubus_ready; // @[SCore.scala 25:18]
- wire score_io_ubus_write; // @[SCore.scala 25:18]
- wire [31:0] score_io_ubus_addr; // @[SCore.scala 25:18]
- wire [255:0] score_io_ubus_wdata; // @[SCore.scala 25:18]
- wire [31:0] score_io_ubus_wmask; // @[SCore.scala 25:18]
- wire [255:0] score_io_ubus_rdata; // @[SCore.scala 25:18]
- wire score_io_vldst; // @[SCore.scala 25:18]
- wire score_io_vcore_vinst_0_valid; // @[SCore.scala 25:18]
- wire score_io_vcore_vinst_0_ready; // @[SCore.scala 25:18]
- wire [4:0] score_io_vcore_vinst_0_addr; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_vinst_0_inst; // @[SCore.scala 25:18]
- wire [4:0] score_io_vcore_vinst_0_op; // @[SCore.scala 25:18]
- wire score_io_vcore_vinst_1_valid; // @[SCore.scala 25:18]
- wire score_io_vcore_vinst_1_ready; // @[SCore.scala 25:18]
- wire [4:0] score_io_vcore_vinst_1_addr; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_vinst_1_inst; // @[SCore.scala 25:18]
- wire [4:0] score_io_vcore_vinst_1_op; // @[SCore.scala 25:18]
- wire score_io_vcore_vinst_2_valid; // @[SCore.scala 25:18]
- wire score_io_vcore_vinst_2_ready; // @[SCore.scala 25:18]
- wire [4:0] score_io_vcore_vinst_2_addr; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_vinst_2_inst; // @[SCore.scala 25:18]
- wire [4:0] score_io_vcore_vinst_2_op; // @[SCore.scala 25:18]
- wire score_io_vcore_vinst_3_valid; // @[SCore.scala 25:18]
- wire score_io_vcore_vinst_3_ready; // @[SCore.scala 25:18]
- wire [4:0] score_io_vcore_vinst_3_addr; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_vinst_3_inst; // @[SCore.scala 25:18]
- wire [4:0] score_io_vcore_vinst_3_op; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_rs_0_data; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_rs_1_data; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_rs_2_data; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_rs_3_data; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_rs_4_data; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_rs_5_data; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_rs_6_data; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_rs_7_data; // @[SCore.scala 25:18]
- wire score_io_vcore_rd_0_valid; // @[SCore.scala 25:18]
- wire [4:0] score_io_vcore_rd_0_addr; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_rd_0_data; // @[SCore.scala 25:18]
- wire score_io_vcore_rd_1_valid; // @[SCore.scala 25:18]
- wire [4:0] score_io_vcore_rd_1_addr; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_rd_1_data; // @[SCore.scala 25:18]
- wire score_io_vcore_rd_2_valid; // @[SCore.scala 25:18]
- wire [4:0] score_io_vcore_rd_2_addr; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_rd_2_data; // @[SCore.scala 25:18]
- wire score_io_vcore_rd_3_valid; // @[SCore.scala 25:18]
- wire [4:0] score_io_vcore_rd_3_addr; // @[SCore.scala 25:18]
- wire [31:0] score_io_vcore_rd_3_data; // @[SCore.scala 25:18]
- wire score_io_vcore_mactive; // @[SCore.scala 25:18]
- wire score_io_vcore_undef; // @[SCore.scala 25:18]
- wire score_io_iflush_valid; // @[SCore.scala 25:18]
- wire score_io_dflush_valid; // @[SCore.scala 25:18]
- wire score_io_dflush_ready; // @[SCore.scala 25:18]
- wire score_io_dflush_all; // @[SCore.scala 25:18]
- wire score_io_slog_valid; // @[SCore.scala 25:18]
- wire [4:0] score_io_slog_addr; // @[SCore.scala 25:18]
- wire [31:0] score_io_slog_data; // @[SCore.scala 25:18]
- wire vcore_clock; // @[VCore.scala 25:18]
- wire vcore_reset; // @[VCore.scala 25:18]
- wire vcore_io_score_vinst_0_valid; // @[VCore.scala 25:18]
- wire vcore_io_score_vinst_0_ready; // @[VCore.scala 25:18]
- wire [4:0] vcore_io_score_vinst_0_addr; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_vinst_0_inst; // @[VCore.scala 25:18]
- wire [4:0] vcore_io_score_vinst_0_op; // @[VCore.scala 25:18]
- wire vcore_io_score_vinst_1_valid; // @[VCore.scala 25:18]
- wire vcore_io_score_vinst_1_ready; // @[VCore.scala 25:18]
- wire [4:0] vcore_io_score_vinst_1_addr; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_vinst_1_inst; // @[VCore.scala 25:18]
- wire [4:0] vcore_io_score_vinst_1_op; // @[VCore.scala 25:18]
- wire vcore_io_score_vinst_2_valid; // @[VCore.scala 25:18]
- wire vcore_io_score_vinst_2_ready; // @[VCore.scala 25:18]
- wire [4:0] vcore_io_score_vinst_2_addr; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_vinst_2_inst; // @[VCore.scala 25:18]
- wire [4:0] vcore_io_score_vinst_2_op; // @[VCore.scala 25:18]
- wire vcore_io_score_vinst_3_valid; // @[VCore.scala 25:18]
- wire vcore_io_score_vinst_3_ready; // @[VCore.scala 25:18]
- wire [4:0] vcore_io_score_vinst_3_addr; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_vinst_3_inst; // @[VCore.scala 25:18]
- wire [4:0] vcore_io_score_vinst_3_op; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_rs_0_data; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_rs_1_data; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_rs_2_data; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_rs_3_data; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_rs_4_data; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_rs_5_data; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_rs_6_data; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_rs_7_data; // @[VCore.scala 25:18]
- wire vcore_io_score_rd_0_valid; // @[VCore.scala 25:18]
- wire [4:0] vcore_io_score_rd_0_addr; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_rd_0_data; // @[VCore.scala 25:18]
- wire vcore_io_score_rd_1_valid; // @[VCore.scala 25:18]
- wire [4:0] vcore_io_score_rd_1_addr; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_rd_1_data; // @[VCore.scala 25:18]
- wire vcore_io_score_rd_2_valid; // @[VCore.scala 25:18]
- wire [4:0] vcore_io_score_rd_2_addr; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_rd_2_data; // @[VCore.scala 25:18]
- wire vcore_io_score_rd_3_valid; // @[VCore.scala 25:18]
- wire [4:0] vcore_io_score_rd_3_addr; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_score_rd_3_data; // @[VCore.scala 25:18]
- wire vcore_io_score_mactive; // @[VCore.scala 25:18]
- wire vcore_io_score_undef; // @[VCore.scala 25:18]
- wire vcore_io_dbus_valid; // @[VCore.scala 25:18]
- wire vcore_io_dbus_ready; // @[VCore.scala 25:18]
- wire vcore_io_dbus_write; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_dbus_addr; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_dbus_adrx; // @[VCore.scala 25:18]
- wire [5:0] vcore_io_dbus_size; // @[VCore.scala 25:18]
- wire [255:0] vcore_io_dbus_wdata; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_dbus_wmask; // @[VCore.scala 25:18]
- wire [255:0] vcore_io_dbus_rdata; // @[VCore.scala 25:18]
- wire vcore_io_last; // @[VCore.scala 25:18]
- wire vcore_io_ld_addr_ready; // @[VCore.scala 25:18]
- wire vcore_io_ld_addr_valid; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_ld_addr_bits_addr; // @[VCore.scala 25:18]
- wire [5:0] vcore_io_ld_addr_bits_id; // @[VCore.scala 25:18]
- wire vcore_io_ld_data_valid; // @[VCore.scala 25:18]
- wire [5:0] vcore_io_ld_data_bits_id; // @[VCore.scala 25:18]
- wire [255:0] vcore_io_ld_data_bits_data; // @[VCore.scala 25:18]
- wire vcore_io_st_addr_ready; // @[VCore.scala 25:18]
- wire vcore_io_st_addr_valid; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_st_addr_bits_addr; // @[VCore.scala 25:18]
- wire [5:0] vcore_io_st_addr_bits_id; // @[VCore.scala 25:18]
- wire vcore_io_st_data_ready; // @[VCore.scala 25:18]
- wire vcore_io_st_data_valid; // @[VCore.scala 25:18]
- wire [255:0] vcore_io_st_data_bits_data; // @[VCore.scala 25:18]
- wire [31:0] vcore_io_st_data_bits_strb; // @[VCore.scala 25:18]
- wire vcore_io_st_resp_valid; // @[VCore.scala 25:18]
- wire dbusmux_io_vldst; // @[DBusMux.scala 23:18]
- wire dbusmux_io_vlast; // @[DBusMux.scala 23:18]
- wire dbusmux_io_vcore_valid; // @[DBusMux.scala 23:18]
- wire dbusmux_io_vcore_ready; // @[DBusMux.scala 23:18]
- wire dbusmux_io_vcore_write; // @[DBusMux.scala 23:18]
- wire [31:0] dbusmux_io_vcore_addr; // @[DBusMux.scala 23:18]
- wire [31:0] dbusmux_io_vcore_adrx; // @[DBusMux.scala 23:18]
- wire [5:0] dbusmux_io_vcore_size; // @[DBusMux.scala 23:18]
- wire [255:0] dbusmux_io_vcore_wdata; // @[DBusMux.scala 23:18]
- wire [31:0] dbusmux_io_vcore_wmask; // @[DBusMux.scala 23:18]
- wire [255:0] dbusmux_io_vcore_rdata; // @[DBusMux.scala 23:18]
- wire dbusmux_io_score_valid; // @[DBusMux.scala 23:18]
- wire dbusmux_io_score_ready; // @[DBusMux.scala 23:18]
- wire dbusmux_io_score_write; // @[DBusMux.scala 23:18]
- wire [31:0] dbusmux_io_score_addr; // @[DBusMux.scala 23:18]
- wire [31:0] dbusmux_io_score_adrx; // @[DBusMux.scala 23:18]
- wire [5:0] dbusmux_io_score_size; // @[DBusMux.scala 23:18]
- wire [255:0] dbusmux_io_score_wdata; // @[DBusMux.scala 23:18]
- wire [31:0] dbusmux_io_score_wmask; // @[DBusMux.scala 23:18]
- wire [255:0] dbusmux_io_score_rdata; // @[DBusMux.scala 23:18]
- wire dbusmux_io_dbus_valid; // @[DBusMux.scala 23:18]
- wire dbusmux_io_dbus_ready; // @[DBusMux.scala 23:18]
- wire dbusmux_io_dbus_write; // @[DBusMux.scala 23:18]
- wire [31:0] dbusmux_io_dbus_addr; // @[DBusMux.scala 23:18]
- wire [31:0] dbusmux_io_dbus_adrx; // @[DBusMux.scala 23:18]
- wire [5:0] dbusmux_io_dbus_size; // @[DBusMux.scala 23:18]
- wire [255:0] dbusmux_io_dbus_wdata; // @[DBusMux.scala 23:18]
- wire [31:0] dbusmux_io_dbus_wmask; // @[DBusMux.scala 23:18]
- wire [255:0] dbusmux_io_dbus_rdata; // @[DBusMux.scala 23:18]
- wire dbus2axi_clock; // @[DBus2Axi.scala 23:18]
- wire dbus2axi_reset; // @[DBus2Axi.scala 23:18]
- wire dbus2axi_io_dbus_valid; // @[DBus2Axi.scala 23:18]
- wire dbus2axi_io_dbus_ready; // @[DBus2Axi.scala 23:18]
- wire dbus2axi_io_dbus_write; // @[DBus2Axi.scala 23:18]
- wire [31:0] dbus2axi_io_dbus_addr; // @[DBus2Axi.scala 23:18]
- wire [255:0] dbus2axi_io_dbus_wdata; // @[DBus2Axi.scala 23:18]
- wire [31:0] dbus2axi_io_dbus_wmask; // @[DBus2Axi.scala 23:18]
- wire [255:0] dbus2axi_io_dbus_rdata; // @[DBus2Axi.scala 23:18]
- wire dbus2axi_io_axi_write_addr_ready; // @[DBus2Axi.scala 23:18]
- wire dbus2axi_io_axi_write_addr_valid; // @[DBus2Axi.scala 23:18]
- wire [31:0] dbus2axi_io_axi_write_addr_bits_addr; // @[DBus2Axi.scala 23:18]
- wire dbus2axi_io_axi_write_data_valid; // @[DBus2Axi.scala 23:18]
- wire [255:0] dbus2axi_io_axi_write_data_bits_data; // @[DBus2Axi.scala 23:18]
- wire [31:0] dbus2axi_io_axi_write_data_bits_strb; // @[DBus2Axi.scala 23:18]
- wire dbus2axi_io_axi_read_addr_ready; // @[DBus2Axi.scala 23:18]
- wire dbus2axi_io_axi_read_addr_valid; // @[DBus2Axi.scala 23:18]
- wire [31:0] dbus2axi_io_axi_read_addr_bits_addr; // @[DBus2Axi.scala 23:18]
- wire dbus2axi_io_axi_read_data_ready; // @[DBus2Axi.scala 23:18]
- wire dbus2axi_io_axi_read_data_valid; // @[DBus2Axi.scala 23:18]
- wire [255:0] dbus2axi_io_axi_read_data_bits_data; // @[DBus2Axi.scala 23:18]
- SCore score ( // @[SCore.scala 25:18]
- .clock(score_clock),
- .reset(score_reset),
- .io_csr_in_value_0(score_io_csr_in_value_0),
- .io_halted(score_io_halted),
- .io_fault(score_io_fault),
- .io_ibus_valid(score_io_ibus_valid),
- .io_ibus_ready(score_io_ibus_ready),
- .io_ibus_addr(score_io_ibus_addr),
- .io_ibus_rdata(score_io_ibus_rdata),
- .io_dbus_valid(score_io_dbus_valid),
- .io_dbus_ready(score_io_dbus_ready),
- .io_dbus_write(score_io_dbus_write),
- .io_dbus_addr(score_io_dbus_addr),
- .io_dbus_adrx(score_io_dbus_adrx),
- .io_dbus_size(score_io_dbus_size),
- .io_dbus_wdata(score_io_dbus_wdata),
- .io_dbus_wmask(score_io_dbus_wmask),
- .io_dbus_rdata(score_io_dbus_rdata),
- .io_ubus_valid(score_io_ubus_valid),
- .io_ubus_ready(score_io_ubus_ready),
- .io_ubus_write(score_io_ubus_write),
- .io_ubus_addr(score_io_ubus_addr),
- .io_ubus_wdata(score_io_ubus_wdata),
- .io_ubus_wmask(score_io_ubus_wmask),
- .io_ubus_rdata(score_io_ubus_rdata),
- .io_vldst(score_io_vldst),
- .io_vcore_vinst_0_valid(score_io_vcore_vinst_0_valid),
- .io_vcore_vinst_0_ready(score_io_vcore_vinst_0_ready),
- .io_vcore_vinst_0_addr(score_io_vcore_vinst_0_addr),
- .io_vcore_vinst_0_inst(score_io_vcore_vinst_0_inst),
- .io_vcore_vinst_0_op(score_io_vcore_vinst_0_op),
- .io_vcore_vinst_1_valid(score_io_vcore_vinst_1_valid),
- .io_vcore_vinst_1_ready(score_io_vcore_vinst_1_ready),
- .io_vcore_vinst_1_addr(score_io_vcore_vinst_1_addr),
- .io_vcore_vinst_1_inst(score_io_vcore_vinst_1_inst),
- .io_vcore_vinst_1_op(score_io_vcore_vinst_1_op),
- .io_vcore_vinst_2_valid(score_io_vcore_vinst_2_valid),
- .io_vcore_vinst_2_ready(score_io_vcore_vinst_2_ready),
- .io_vcore_vinst_2_addr(score_io_vcore_vinst_2_addr),
- .io_vcore_vinst_2_inst(score_io_vcore_vinst_2_inst),
- .io_vcore_vinst_2_op(score_io_vcore_vinst_2_op),
- .io_vcore_vinst_3_valid(score_io_vcore_vinst_3_valid),
- .io_vcore_vinst_3_ready(score_io_vcore_vinst_3_ready),
- .io_vcore_vinst_3_addr(score_io_vcore_vinst_3_addr),
- .io_vcore_vinst_3_inst(score_io_vcore_vinst_3_inst),
- .io_vcore_vinst_3_op(score_io_vcore_vinst_3_op),
- .io_vcore_rs_0_data(score_io_vcore_rs_0_data),
- .io_vcore_rs_1_data(score_io_vcore_rs_1_data),
- .io_vcore_rs_2_data(score_io_vcore_rs_2_data),
- .io_vcore_rs_3_data(score_io_vcore_rs_3_data),
- .io_vcore_rs_4_data(score_io_vcore_rs_4_data),
- .io_vcore_rs_5_data(score_io_vcore_rs_5_data),
- .io_vcore_rs_6_data(score_io_vcore_rs_6_data),
- .io_vcore_rs_7_data(score_io_vcore_rs_7_data),
- .io_vcore_rd_0_valid(score_io_vcore_rd_0_valid),
- .io_vcore_rd_0_addr(score_io_vcore_rd_0_addr),
- .io_vcore_rd_0_data(score_io_vcore_rd_0_data),
- .io_vcore_rd_1_valid(score_io_vcore_rd_1_valid),
- .io_vcore_rd_1_addr(score_io_vcore_rd_1_addr),
- .io_vcore_rd_1_data(score_io_vcore_rd_1_data),
- .io_vcore_rd_2_valid(score_io_vcore_rd_2_valid),
- .io_vcore_rd_2_addr(score_io_vcore_rd_2_addr),
- .io_vcore_rd_2_data(score_io_vcore_rd_2_data),
- .io_vcore_rd_3_valid(score_io_vcore_rd_3_valid),
- .io_vcore_rd_3_addr(score_io_vcore_rd_3_addr),
- .io_vcore_rd_3_data(score_io_vcore_rd_3_data),
- .io_vcore_mactive(score_io_vcore_mactive),
- .io_vcore_undef(score_io_vcore_undef),
- .io_iflush_valid(score_io_iflush_valid),
- .io_dflush_valid(score_io_dflush_valid),
- .io_dflush_ready(score_io_dflush_ready),
- .io_dflush_all(score_io_dflush_all),
- .io_slog_valid(score_io_slog_valid),
- .io_slog_addr(score_io_slog_addr),
- .io_slog_data(score_io_slog_data)
- );
- VCore vcore ( // @[VCore.scala 25:18]
- .clock(vcore_clock),
- .reset(vcore_reset),
- .io_score_vinst_0_valid(vcore_io_score_vinst_0_valid),
- .io_score_vinst_0_ready(vcore_io_score_vinst_0_ready),
- .io_score_vinst_0_addr(vcore_io_score_vinst_0_addr),
- .io_score_vinst_0_inst(vcore_io_score_vinst_0_inst),
- .io_score_vinst_0_op(vcore_io_score_vinst_0_op),
- .io_score_vinst_1_valid(vcore_io_score_vinst_1_valid),
- .io_score_vinst_1_ready(vcore_io_score_vinst_1_ready),
- .io_score_vinst_1_addr(vcore_io_score_vinst_1_addr),
- .io_score_vinst_1_inst(vcore_io_score_vinst_1_inst),
- .io_score_vinst_1_op(vcore_io_score_vinst_1_op),
- .io_score_vinst_2_valid(vcore_io_score_vinst_2_valid),
- .io_score_vinst_2_ready(vcore_io_score_vinst_2_ready),
- .io_score_vinst_2_addr(vcore_io_score_vinst_2_addr),
- .io_score_vinst_2_inst(vcore_io_score_vinst_2_inst),
- .io_score_vinst_2_op(vcore_io_score_vinst_2_op),
- .io_score_vinst_3_valid(vcore_io_score_vinst_3_valid),
- .io_score_vinst_3_ready(vcore_io_score_vinst_3_ready),
- .io_score_vinst_3_addr(vcore_io_score_vinst_3_addr),
- .io_score_vinst_3_inst(vcore_io_score_vinst_3_inst),
- .io_score_vinst_3_op(vcore_io_score_vinst_3_op),
- .io_score_rs_0_data(vcore_io_score_rs_0_data),
- .io_score_rs_1_data(vcore_io_score_rs_1_data),
- .io_score_rs_2_data(vcore_io_score_rs_2_data),
- .io_score_rs_3_data(vcore_io_score_rs_3_data),
- .io_score_rs_4_data(vcore_io_score_rs_4_data),
- .io_score_rs_5_data(vcore_io_score_rs_5_data),
- .io_score_rs_6_data(vcore_io_score_rs_6_data),
- .io_score_rs_7_data(vcore_io_score_rs_7_data),
- .io_score_rd_0_valid(vcore_io_score_rd_0_valid),
- .io_score_rd_0_addr(vcore_io_score_rd_0_addr),
- .io_score_rd_0_data(vcore_io_score_rd_0_data),
- .io_score_rd_1_valid(vcore_io_score_rd_1_valid),
- .io_score_rd_1_addr(vcore_io_score_rd_1_addr),
- .io_score_rd_1_data(vcore_io_score_rd_1_data),
- .io_score_rd_2_valid(vcore_io_score_rd_2_valid),
- .io_score_rd_2_addr(vcore_io_score_rd_2_addr),
- .io_score_rd_2_data(vcore_io_score_rd_2_data),
- .io_score_rd_3_valid(vcore_io_score_rd_3_valid),
- .io_score_rd_3_addr(vcore_io_score_rd_3_addr),
- .io_score_rd_3_data(vcore_io_score_rd_3_data),
- .io_score_mactive(vcore_io_score_mactive),
- .io_score_undef(vcore_io_score_undef),
- .io_dbus_valid(vcore_io_dbus_valid),
- .io_dbus_ready(vcore_io_dbus_ready),
- .io_dbus_write(vcore_io_dbus_write),
- .io_dbus_addr(vcore_io_dbus_addr),
- .io_dbus_adrx(vcore_io_dbus_adrx),
- .io_dbus_size(vcore_io_dbus_size),
- .io_dbus_wdata(vcore_io_dbus_wdata),
- .io_dbus_wmask(vcore_io_dbus_wmask),
- .io_dbus_rdata(vcore_io_dbus_rdata),
- .io_last(vcore_io_last),
- .io_ld_addr_ready(vcore_io_ld_addr_ready),
- .io_ld_addr_valid(vcore_io_ld_addr_valid),
- .io_ld_addr_bits_addr(vcore_io_ld_addr_bits_addr),
- .io_ld_addr_bits_id(vcore_io_ld_addr_bits_id),
- .io_ld_data_valid(vcore_io_ld_data_valid),
- .io_ld_data_bits_id(vcore_io_ld_data_bits_id),
- .io_ld_data_bits_data(vcore_io_ld_data_bits_data),
- .io_st_addr_ready(vcore_io_st_addr_ready),
- .io_st_addr_valid(vcore_io_st_addr_valid),
- .io_st_addr_bits_addr(vcore_io_st_addr_bits_addr),
- .io_st_addr_bits_id(vcore_io_st_addr_bits_id),
- .io_st_data_ready(vcore_io_st_data_ready),
- .io_st_data_valid(vcore_io_st_data_valid),
- .io_st_data_bits_data(vcore_io_st_data_bits_data),
- .io_st_data_bits_strb(vcore_io_st_data_bits_strb),
- .io_st_resp_valid(vcore_io_st_resp_valid)
- );
- DBusMux dbusmux ( // @[DBusMux.scala 23:18]
- .io_vldst(dbusmux_io_vldst),
- .io_vlast(dbusmux_io_vlast),
- .io_vcore_valid(dbusmux_io_vcore_valid),
- .io_vcore_ready(dbusmux_io_vcore_ready),
- .io_vcore_write(dbusmux_io_vcore_write),
- .io_vcore_addr(dbusmux_io_vcore_addr),
- .io_vcore_adrx(dbusmux_io_vcore_adrx),
- .io_vcore_size(dbusmux_io_vcore_size),
- .io_vcore_wdata(dbusmux_io_vcore_wdata),
- .io_vcore_wmask(dbusmux_io_vcore_wmask),
- .io_vcore_rdata(dbusmux_io_vcore_rdata),
- .io_score_valid(dbusmux_io_score_valid),
- .io_score_ready(dbusmux_io_score_ready),
- .io_score_write(dbusmux_io_score_write),
- .io_score_addr(dbusmux_io_score_addr),
- .io_score_adrx(dbusmux_io_score_adrx),
- .io_score_size(dbusmux_io_score_size),
- .io_score_wdata(dbusmux_io_score_wdata),
- .io_score_wmask(dbusmux_io_score_wmask),
- .io_score_rdata(dbusmux_io_score_rdata),
- .io_dbus_valid(dbusmux_io_dbus_valid),
- .io_dbus_ready(dbusmux_io_dbus_ready),
- .io_dbus_write(dbusmux_io_dbus_write),
- .io_dbus_addr(dbusmux_io_dbus_addr),
- .io_dbus_adrx(dbusmux_io_dbus_adrx),
- .io_dbus_size(dbusmux_io_dbus_size),
- .io_dbus_wdata(dbusmux_io_dbus_wdata),
- .io_dbus_wmask(dbusmux_io_dbus_wmask),
- .io_dbus_rdata(dbusmux_io_dbus_rdata)
- );
- DBus2Axi dbus2axi ( // @[DBus2Axi.scala 23:18]
- .clock(dbus2axi_clock),
- .reset(dbus2axi_reset),
- .io_dbus_valid(dbus2axi_io_dbus_valid),
- .io_dbus_ready(dbus2axi_io_dbus_ready),
- .io_dbus_write(dbus2axi_io_dbus_write),
- .io_dbus_addr(dbus2axi_io_dbus_addr),
- .io_dbus_wdata(dbus2axi_io_dbus_wdata),
- .io_dbus_wmask(dbus2axi_io_dbus_wmask),
- .io_dbus_rdata(dbus2axi_io_dbus_rdata),
- .io_axi_write_addr_ready(dbus2axi_io_axi_write_addr_ready),
- .io_axi_write_addr_valid(dbus2axi_io_axi_write_addr_valid),
- .io_axi_write_addr_bits_addr(dbus2axi_io_axi_write_addr_bits_addr),
- .io_axi_write_data_valid(dbus2axi_io_axi_write_data_valid),
- .io_axi_write_data_bits_data(dbus2axi_io_axi_write_data_bits_data),
- .io_axi_write_data_bits_strb(dbus2axi_io_axi_write_data_bits_strb),
- .io_axi_read_addr_ready(dbus2axi_io_axi_read_addr_ready),
- .io_axi_read_addr_valid(dbus2axi_io_axi_read_addr_valid),
- .io_axi_read_addr_bits_addr(dbus2axi_io_axi_read_addr_bits_addr),
- .io_axi_read_data_ready(dbus2axi_io_axi_read_data_ready),
- .io_axi_read_data_valid(dbus2axi_io_axi_read_data_valid),
- .io_axi_read_data_bits_data(dbus2axi_io_axi_read_data_bits_data)
- );
- assign io_halted = score_io_halted; // @[Core.scala 53:13]
- assign io_fault = score_io_fault; // @[Core.scala 54:13]
- assign io_ibus_valid = score_io_ibus_valid; // @[Core.scala 52:13]
- assign io_ibus_addr = score_io_ibus_addr; // @[Core.scala 52:13]
- assign io_dbus_valid = dbusmux_io_dbus_valid; // @[Core.scala 72:11]
- assign io_dbus_write = dbusmux_io_dbus_write; // @[Core.scala 72:11]
- assign io_dbus_addr = dbusmux_io_dbus_addr; // @[Core.scala 72:11]
- assign io_dbus_adrx = dbusmux_io_dbus_adrx; // @[Core.scala 72:11]
- assign io_dbus_size = dbusmux_io_dbus_size; // @[Core.scala 72:11]
- assign io_dbus_wdata = dbusmux_io_dbus_wdata; // @[Core.scala 72:11]
- assign io_dbus_wmask = dbusmux_io_dbus_wmask; // @[Core.scala 72:11]
- assign io_axi0_write_addr_valid = vcore_io_st_addr_valid; // @[Core.scala 82:17]
- assign io_axi0_write_addr_bits_addr = vcore_io_st_addr_bits_addr; // @[Core.scala 82:17]
- assign io_axi0_write_addr_bits_id = vcore_io_st_addr_bits_id; // @[Core.scala 82:17]
- assign io_axi0_write_data_valid = vcore_io_st_data_valid; // @[Core.scala 82:17]
- assign io_axi0_write_data_bits_data = vcore_io_st_data_bits_data; // @[Core.scala 82:17]
- assign io_axi0_write_data_bits_strb = vcore_io_st_data_bits_strb; // @[Core.scala 82:17]
- assign io_axi0_read_addr_valid = vcore_io_ld_addr_valid; // @[Core.scala 81:17]
- assign io_axi0_read_addr_bits_addr = vcore_io_ld_addr_bits_addr; // @[Core.scala 81:17]
- assign io_axi0_read_addr_bits_id = vcore_io_ld_addr_bits_id; // @[Core.scala 81:17]
- assign io_axi1_write_addr_valid = dbus2axi_io_axi_write_addr_valid; // @[Core.scala 84:11]
- assign io_axi1_write_addr_bits_addr = dbus2axi_io_axi_write_addr_bits_addr; // @[Core.scala 84:11]
- assign io_axi1_write_data_valid = dbus2axi_io_axi_write_data_valid; // @[Core.scala 84:11]
- assign io_axi1_write_data_bits_data = dbus2axi_io_axi_write_data_bits_data; // @[Core.scala 84:11]
- assign io_axi1_write_data_bits_strb = dbus2axi_io_axi_write_data_bits_strb; // @[Core.scala 84:11]
- assign io_axi1_read_addr_valid = dbus2axi_io_axi_read_addr_valid; // @[Core.scala 84:11]
- assign io_axi1_read_addr_bits_addr = dbus2axi_io_axi_read_addr_bits_addr; // @[Core.scala 84:11]
- assign io_iflush_valid = score_io_iflush_valid; // @[Core.scala 55:13]
- assign io_dflush_valid = score_io_dflush_valid; // @[Core.scala 56:13]
- assign io_dflush_all = score_io_dflush_all; // @[Core.scala 56:13]
- assign io_slog_valid = score_io_slog_valid; // @[Core.scala 57:13]
- assign io_slog_addr = score_io_slog_addr; // @[Core.scala 57:13]
- assign io_slog_data = score_io_slog_data; // @[Core.scala 57:13]
- assign score_clock = clock;
- assign score_reset = reset;
- assign score_io_csr_in_value_0 = io_csr_in_value_0; // @[Core.scala 51:13]
- assign score_io_ibus_ready = io_ibus_ready; // @[Core.scala 52:13]
- assign score_io_ibus_rdata = io_ibus_rdata; // @[Core.scala 52:13]
- assign score_io_dbus_ready = dbusmux_io_score_ready; // @[Core.scala 70:20]
- assign score_io_dbus_rdata = dbusmux_io_score_rdata; // @[Core.scala 70:20]
- assign score_io_ubus_ready = dbus2axi_io_dbus_ready; // @[Core.scala 77:20]
- assign score_io_ubus_rdata = dbus2axi_io_dbus_rdata; // @[Core.scala 77:20]
- assign score_io_vcore_vinst_0_ready = vcore_io_score_vinst_0_ready; // @[Core.scala 62:18]
- assign score_io_vcore_vinst_1_ready = vcore_io_score_vinst_1_ready; // @[Core.scala 62:18]
- assign score_io_vcore_vinst_2_ready = vcore_io_score_vinst_2_ready; // @[Core.scala 62:18]
- assign score_io_vcore_vinst_3_ready = vcore_io_score_vinst_3_ready; // @[Core.scala 62:18]
- assign score_io_vcore_rd_0_valid = vcore_io_score_rd_0_valid; // @[Core.scala 62:18]
- assign score_io_vcore_rd_0_addr = vcore_io_score_rd_0_addr; // @[Core.scala 62:18]
- assign score_io_vcore_rd_0_data = vcore_io_score_rd_0_data; // @[Core.scala 62:18]
- assign score_io_vcore_rd_1_valid = vcore_io_score_rd_1_valid; // @[Core.scala 62:18]
- assign score_io_vcore_rd_1_addr = vcore_io_score_rd_1_addr; // @[Core.scala 62:18]
- assign score_io_vcore_rd_1_data = vcore_io_score_rd_1_data; // @[Core.scala 62:18]
- assign score_io_vcore_rd_2_valid = vcore_io_score_rd_2_valid; // @[Core.scala 62:18]
- assign score_io_vcore_rd_2_addr = vcore_io_score_rd_2_addr; // @[Core.scala 62:18]
- assign score_io_vcore_rd_2_data = vcore_io_score_rd_2_data; // @[Core.scala 62:18]
- assign score_io_vcore_rd_3_valid = vcore_io_score_rd_3_valid; // @[Core.scala 62:18]
- assign score_io_vcore_rd_3_addr = vcore_io_score_rd_3_addr; // @[Core.scala 62:18]
- assign score_io_vcore_rd_3_data = vcore_io_score_rd_3_data; // @[Core.scala 62:18]
- assign score_io_vcore_mactive = vcore_io_score_mactive; // @[Core.scala 62:18]
- assign score_io_vcore_undef = vcore_io_score_undef; // @[Core.scala 62:18]
- assign score_io_dflush_ready = io_dflush_ready; // @[Core.scala 56:13]
- assign vcore_clock = clock;
- assign vcore_reset = reset;
- assign vcore_io_score_vinst_0_valid = score_io_vcore_vinst_0_valid; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_0_addr = score_io_vcore_vinst_0_addr; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_0_inst = score_io_vcore_vinst_0_inst; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_0_op = score_io_vcore_vinst_0_op; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_1_valid = score_io_vcore_vinst_1_valid; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_1_addr = score_io_vcore_vinst_1_addr; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_1_inst = score_io_vcore_vinst_1_inst; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_1_op = score_io_vcore_vinst_1_op; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_2_valid = score_io_vcore_vinst_2_valid; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_2_addr = score_io_vcore_vinst_2_addr; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_2_inst = score_io_vcore_vinst_2_inst; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_2_op = score_io_vcore_vinst_2_op; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_3_valid = score_io_vcore_vinst_3_valid; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_3_addr = score_io_vcore_vinst_3_addr; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_3_inst = score_io_vcore_vinst_3_inst; // @[Core.scala 62:18]
- assign vcore_io_score_vinst_3_op = score_io_vcore_vinst_3_op; // @[Core.scala 62:18]
- assign vcore_io_score_rs_0_data = score_io_vcore_rs_0_data; // @[Core.scala 62:18]
- assign vcore_io_score_rs_1_data = score_io_vcore_rs_1_data; // @[Core.scala 62:18]
- assign vcore_io_score_rs_2_data = score_io_vcore_rs_2_data; // @[Core.scala 62:18]
- assign vcore_io_score_rs_3_data = score_io_vcore_rs_3_data; // @[Core.scala 62:18]
- assign vcore_io_score_rs_4_data = score_io_vcore_rs_4_data; // @[Core.scala 62:18]
- assign vcore_io_score_rs_5_data = score_io_vcore_rs_5_data; // @[Core.scala 62:18]
- assign vcore_io_score_rs_6_data = score_io_vcore_rs_6_data; // @[Core.scala 62:18]
- assign vcore_io_score_rs_7_data = score_io_vcore_rs_7_data; // @[Core.scala 62:18]
- assign vcore_io_dbus_ready = dbusmux_io_vcore_ready; // @[Core.scala 69:20]
- assign vcore_io_dbus_rdata = dbusmux_io_vcore_rdata; // @[Core.scala 69:20]
- assign vcore_io_ld_addr_ready = io_axi0_read_addr_ready; // @[Core.scala 81:17]
- assign vcore_io_ld_data_valid = io_axi0_read_data_valid; // @[Core.scala 81:17]
- assign vcore_io_ld_data_bits_id = io_axi0_read_data_bits_id; // @[Core.scala 81:17]
- assign vcore_io_ld_data_bits_data = io_axi0_read_data_bits_data; // @[Core.scala 81:17]
- assign vcore_io_st_addr_ready = io_axi0_write_addr_ready; // @[Core.scala 82:17]
- assign vcore_io_st_data_ready = io_axi0_write_data_ready; // @[Core.scala 82:17]
- assign vcore_io_st_resp_valid = io_axi0_write_resp_valid; // @[Core.scala 82:17]
- assign dbusmux_io_vldst = score_io_vldst; // @[Core.scala 66:20]
- assign dbusmux_io_vlast = vcore_io_last; // @[Core.scala 67:20]
- assign dbusmux_io_vcore_valid = vcore_io_dbus_valid; // @[Core.scala 69:20]
- assign dbusmux_io_vcore_write = vcore_io_dbus_write; // @[Core.scala 69:20]
- assign dbusmux_io_vcore_addr = vcore_io_dbus_addr; // @[Core.scala 69:20]
- assign dbusmux_io_vcore_adrx = vcore_io_dbus_adrx; // @[Core.scala 69:20]
- assign dbusmux_io_vcore_size = vcore_io_dbus_size; // @[Core.scala 69:20]
- assign dbusmux_io_vcore_wdata = vcore_io_dbus_wdata; // @[Core.scala 69:20]
- assign dbusmux_io_vcore_wmask = vcore_io_dbus_wmask; // @[Core.scala 69:20]
- assign dbusmux_io_score_valid = score_io_dbus_valid; // @[Core.scala 70:20]
- assign dbusmux_io_score_write = score_io_dbus_write; // @[Core.scala 70:20]
- assign dbusmux_io_score_addr = score_io_dbus_addr; // @[Core.scala 70:20]
- assign dbusmux_io_score_adrx = score_io_dbus_adrx; // @[Core.scala 70:20]
- assign dbusmux_io_score_size = score_io_dbus_size; // @[Core.scala 70:20]
- assign dbusmux_io_score_wdata = score_io_dbus_wdata; // @[Core.scala 70:20]
- assign dbusmux_io_score_wmask = score_io_dbus_wmask; // @[Core.scala 70:20]
- assign dbusmux_io_dbus_ready = io_dbus_ready; // @[Core.scala 72:11]
- assign dbusmux_io_dbus_rdata = io_dbus_rdata; // @[Core.scala 72:11]
- assign dbus2axi_clock = clock;
- assign dbus2axi_reset = reset;
- assign dbus2axi_io_dbus_valid = score_io_ubus_valid; // @[Core.scala 77:20]
- assign dbus2axi_io_dbus_write = score_io_ubus_write; // @[Core.scala 77:20]
- assign dbus2axi_io_dbus_addr = score_io_ubus_addr; // @[Core.scala 77:20]
- assign dbus2axi_io_dbus_wdata = score_io_ubus_wdata; // @[Core.scala 77:20]
- assign dbus2axi_io_dbus_wmask = score_io_ubus_wmask; // @[Core.scala 77:20]
- assign dbus2axi_io_axi_write_addr_ready = io_axi1_write_addr_ready; // @[Core.scala 84:11]
- assign dbus2axi_io_axi_read_addr_ready = io_axi1_read_addr_ready; // @[Core.scala 84:11]
- assign dbus2axi_io_axi_read_data_valid = io_axi1_read_data_valid; // @[Core.scala 84:11]
- assign dbus2axi_io_axi_read_data_bits_data = io_axi1_read_data_bits_data; // @[Core.scala 84:11]
-endmodule
-module L1DCacheBank(
- input clock,
- input reset,
- input io_dbus_valid,
- output io_dbus_ready,
- input io_dbus_write,
- input [30:0] io_dbus_addr,
- input [5:0] io_dbus_size,
- input [255:0] io_dbus_wdata,
- input [31:0] io_dbus_wmask,
- output [255:0] io_dbus_rdata,
- input io_axi_write_addr_ready,
- output io_axi_write_addr_valid,
- output [30:0] io_axi_write_addr_bits_addr,
- input io_axi_write_data_ready,
- output io_axi_write_data_valid,
- output [255:0] io_axi_write_data_bits_data,
- output [31:0] io_axi_write_data_bits_strb,
- output io_axi_write_resp_ready,
- input io_axi_write_resp_valid,
- input io_axi_read_addr_ready,
- output io_axi_read_addr_valid,
- output [30:0] io_axi_read_addr_bits_addr,
- output io_axi_read_data_ready,
- input io_axi_read_data_valid,
- input [255:0] io_axi_read_data_bits_data,
- input io_flush_valid,
- output io_flush_ready,
- input io_flush_all,
- input io_volt_sel
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
- reg [31:0] _RAND_34;
- reg [31:0] _RAND_35;
- reg [31:0] _RAND_36;
- reg [31:0] _RAND_37;
- reg [31:0] _RAND_38;
- reg [31:0] _RAND_39;
- reg [31:0] _RAND_40;
- reg [31:0] _RAND_41;
- reg [31:0] _RAND_42;
- reg [31:0] _RAND_43;
- reg [31:0] _RAND_44;
- reg [31:0] _RAND_45;
- reg [31:0] _RAND_46;
- reg [31:0] _RAND_47;
- reg [31:0] _RAND_48;
- reg [31:0] _RAND_49;
- reg [31:0] _RAND_50;
- reg [31:0] _RAND_51;
- reg [31:0] _RAND_52;
- reg [31:0] _RAND_53;
- reg [31:0] _RAND_54;
- reg [31:0] _RAND_55;
- reg [31:0] _RAND_56;
- reg [31:0] _RAND_57;
- reg [31:0] _RAND_58;
- reg [31:0] _RAND_59;
- reg [31:0] _RAND_60;
- reg [31:0] _RAND_61;
- reg [31:0] _RAND_62;
- reg [31:0] _RAND_63;
- reg [31:0] _RAND_64;
- reg [31:0] _RAND_65;
- reg [31:0] _RAND_66;
- reg [31:0] _RAND_67;
- reg [31:0] _RAND_68;
- reg [31:0] _RAND_69;
- reg [31:0] _RAND_70;
- reg [31:0] _RAND_71;
- reg [31:0] _RAND_72;
- reg [31:0] _RAND_73;
- reg [31:0] _RAND_74;
- reg [31:0] _RAND_75;
- reg [31:0] _RAND_76;
- reg [31:0] _RAND_77;
- reg [31:0] _RAND_78;
- reg [31:0] _RAND_79;
- reg [31:0] _RAND_80;
- reg [31:0] _RAND_81;
- reg [31:0] _RAND_82;
- reg [31:0] _RAND_83;
- reg [31:0] _RAND_84;
- reg [31:0] _RAND_85;
- reg [31:0] _RAND_86;
- reg [31:0] _RAND_87;
- reg [31:0] _RAND_88;
- reg [31:0] _RAND_89;
- reg [31:0] _RAND_90;
- reg [31:0] _RAND_91;
- reg [31:0] _RAND_92;
- reg [31:0] _RAND_93;
- reg [31:0] _RAND_94;
- reg [31:0] _RAND_95;
- reg [31:0] _RAND_96;
- reg [31:0] _RAND_97;
- reg [31:0] _RAND_98;
- reg [31:0] _RAND_99;
- reg [31:0] _RAND_100;
- reg [31:0] _RAND_101;
- reg [31:0] _RAND_102;
- reg [31:0] _RAND_103;
- reg [31:0] _RAND_104;
- reg [31:0] _RAND_105;
- reg [31:0] _RAND_106;
- reg [31:0] _RAND_107;
- reg [31:0] _RAND_108;
- reg [31:0] _RAND_109;
- reg [31:0] _RAND_110;
- reg [31:0] _RAND_111;
- reg [31:0] _RAND_112;
- reg [31:0] _RAND_113;
- reg [31:0] _RAND_114;
- reg [31:0] _RAND_115;
- reg [31:0] _RAND_116;
- reg [31:0] _RAND_117;
- reg [31:0] _RAND_118;
- reg [31:0] _RAND_119;
- reg [31:0] _RAND_120;
- reg [31:0] _RAND_121;
- reg [31:0] _RAND_122;
- reg [31:0] _RAND_123;
- reg [31:0] _RAND_124;
- reg [31:0] _RAND_125;
- reg [31:0] _RAND_126;
- reg [31:0] _RAND_127;
- reg [31:0] _RAND_128;
- reg [31:0] _RAND_129;
- reg [31:0] _RAND_130;
- reg [31:0] _RAND_131;
- reg [31:0] _RAND_132;
- reg [31:0] _RAND_133;
- reg [31:0] _RAND_134;
- reg [31:0] _RAND_135;
- reg [31:0] _RAND_136;
- reg [31:0] _RAND_137;
- reg [31:0] _RAND_138;
- reg [31:0] _RAND_139;
- reg [31:0] _RAND_140;
- reg [31:0] _RAND_141;
- reg [31:0] _RAND_142;
- reg [31:0] _RAND_143;
- reg [31:0] _RAND_144;
- reg [31:0] _RAND_145;
- reg [31:0] _RAND_146;
- reg [31:0] _RAND_147;
- reg [31:0] _RAND_148;
- reg [31:0] _RAND_149;
- reg [31:0] _RAND_150;
- reg [31:0] _RAND_151;
- reg [31:0] _RAND_152;
- reg [31:0] _RAND_153;
- reg [31:0] _RAND_154;
- reg [31:0] _RAND_155;
- reg [31:0] _RAND_156;
- reg [31:0] _RAND_157;
- reg [31:0] _RAND_158;
- reg [31:0] _RAND_159;
- reg [31:0] _RAND_160;
- reg [31:0] _RAND_161;
- reg [31:0] _RAND_162;
- reg [31:0] _RAND_163;
- reg [31:0] _RAND_164;
- reg [31:0] _RAND_165;
- reg [31:0] _RAND_166;
- reg [31:0] _RAND_167;
- reg [31:0] _RAND_168;
- reg [31:0] _RAND_169;
- reg [31:0] _RAND_170;
- reg [31:0] _RAND_171;
- reg [31:0] _RAND_172;
- reg [31:0] _RAND_173;
- reg [31:0] _RAND_174;
- reg [31:0] _RAND_175;
- reg [31:0] _RAND_176;
- reg [31:0] _RAND_177;
- reg [31:0] _RAND_178;
- reg [31:0] _RAND_179;
- reg [31:0] _RAND_180;
- reg [31:0] _RAND_181;
- reg [31:0] _RAND_182;
- reg [31:0] _RAND_183;
- reg [31:0] _RAND_184;
- reg [31:0] _RAND_185;
- reg [31:0] _RAND_186;
- reg [31:0] _RAND_187;
- reg [31:0] _RAND_188;
- reg [31:0] _RAND_189;
- reg [31:0] _RAND_190;
- reg [31:0] _RAND_191;
- reg [31:0] _RAND_192;
- reg [31:0] _RAND_193;
- reg [31:0] _RAND_194;
- reg [31:0] _RAND_195;
- reg [31:0] _RAND_196;
- reg [31:0] _RAND_197;
- reg [31:0] _RAND_198;
- reg [31:0] _RAND_199;
- reg [31:0] _RAND_200;
- reg [31:0] _RAND_201;
- reg [31:0] _RAND_202;
- reg [31:0] _RAND_203;
- reg [31:0] _RAND_204;
- reg [31:0] _RAND_205;
- reg [31:0] _RAND_206;
- reg [31:0] _RAND_207;
- reg [31:0] _RAND_208;
- reg [31:0] _RAND_209;
- reg [31:0] _RAND_210;
- reg [31:0] _RAND_211;
- reg [31:0] _RAND_212;
- reg [31:0] _RAND_213;
- reg [31:0] _RAND_214;
- reg [31:0] _RAND_215;
- reg [31:0] _RAND_216;
- reg [31:0] _RAND_217;
- reg [31:0] _RAND_218;
- reg [31:0] _RAND_219;
- reg [31:0] _RAND_220;
- reg [31:0] _RAND_221;
- reg [31:0] _RAND_222;
- reg [31:0] _RAND_223;
- reg [31:0] _RAND_224;
- reg [31:0] _RAND_225;
- reg [31:0] _RAND_226;
- reg [31:0] _RAND_227;
- reg [31:0] _RAND_228;
- reg [31:0] _RAND_229;
- reg [31:0] _RAND_230;
- reg [31:0] _RAND_231;
- reg [31:0] _RAND_232;
- reg [31:0] _RAND_233;
- reg [31:0] _RAND_234;
- reg [31:0] _RAND_235;
- reg [31:0] _RAND_236;
- reg [31:0] _RAND_237;
- reg [31:0] _RAND_238;
- reg [31:0] _RAND_239;
- reg [31:0] _RAND_240;
- reg [31:0] _RAND_241;
- reg [31:0] _RAND_242;
- reg [31:0] _RAND_243;
- reg [31:0] _RAND_244;
- reg [31:0] _RAND_245;
- reg [31:0] _RAND_246;
- reg [31:0] _RAND_247;
- reg [31:0] _RAND_248;
- reg [31:0] _RAND_249;
- reg [31:0] _RAND_250;
- reg [31:0] _RAND_251;
- reg [31:0] _RAND_252;
- reg [31:0] _RAND_253;
- reg [31:0] _RAND_254;
- reg [31:0] _RAND_255;
- reg [31:0] _RAND_256;
- reg [31:0] _RAND_257;
- reg [31:0] _RAND_258;
- reg [31:0] _RAND_259;
- reg [31:0] _RAND_260;
- reg [31:0] _RAND_261;
- reg [31:0] _RAND_262;
- reg [31:0] _RAND_263;
- reg [31:0] _RAND_264;
- reg [31:0] _RAND_265;
- reg [31:0] _RAND_266;
- reg [31:0] _RAND_267;
- reg [31:0] _RAND_268;
- reg [31:0] _RAND_269;
- reg [31:0] _RAND_270;
- reg [31:0] _RAND_271;
- reg [31:0] _RAND_272;
- reg [31:0] _RAND_273;
- reg [31:0] _RAND_274;
- reg [31:0] _RAND_275;
- reg [31:0] _RAND_276;
- reg [31:0] _RAND_277;
- reg [31:0] _RAND_278;
- reg [31:0] _RAND_279;
- reg [31:0] _RAND_280;
- reg [31:0] _RAND_281;
- reg [31:0] _RAND_282;
- reg [31:0] _RAND_283;
- reg [31:0] _RAND_284;
- reg [31:0] _RAND_285;
- reg [31:0] _RAND_286;
- reg [31:0] _RAND_287;
- reg [31:0] _RAND_288;
- reg [31:0] _RAND_289;
- reg [31:0] _RAND_290;
- reg [31:0] _RAND_291;
- reg [31:0] _RAND_292;
- reg [31:0] _RAND_293;
- reg [31:0] _RAND_294;
- reg [31:0] _RAND_295;
- reg [31:0] _RAND_296;
- reg [31:0] _RAND_297;
- reg [31:0] _RAND_298;
- reg [31:0] _RAND_299;
- reg [31:0] _RAND_300;
- reg [31:0] _RAND_301;
- reg [31:0] _RAND_302;
- reg [31:0] _RAND_303;
- reg [31:0] _RAND_304;
- reg [31:0] _RAND_305;
- reg [31:0] _RAND_306;
- reg [31:0] _RAND_307;
- reg [31:0] _RAND_308;
- reg [31:0] _RAND_309;
- reg [31:0] _RAND_310;
- reg [31:0] _RAND_311;
- reg [31:0] _RAND_312;
- reg [31:0] _RAND_313;
- reg [31:0] _RAND_314;
- reg [31:0] _RAND_315;
- reg [31:0] _RAND_316;
- reg [31:0] _RAND_317;
- reg [31:0] _RAND_318;
- reg [31:0] _RAND_319;
- reg [31:0] _RAND_320;
- reg [31:0] _RAND_321;
- reg [31:0] _RAND_322;
- reg [31:0] _RAND_323;
- reg [31:0] _RAND_324;
- reg [31:0] _RAND_325;
- reg [31:0] _RAND_326;
- reg [31:0] _RAND_327;
- reg [31:0] _RAND_328;
- reg [31:0] _RAND_329;
- reg [31:0] _RAND_330;
- reg [31:0] _RAND_331;
- reg [31:0] _RAND_332;
- reg [31:0] _RAND_333;
- reg [31:0] _RAND_334;
- reg [31:0] _RAND_335;
- reg [31:0] _RAND_336;
- reg [31:0] _RAND_337;
- reg [31:0] _RAND_338;
- reg [31:0] _RAND_339;
- reg [31:0] _RAND_340;
- reg [31:0] _RAND_341;
- reg [31:0] _RAND_342;
- reg [31:0] _RAND_343;
- reg [31:0] _RAND_344;
- reg [31:0] _RAND_345;
- reg [31:0] _RAND_346;
- reg [31:0] _RAND_347;
- reg [31:0] _RAND_348;
- reg [31:0] _RAND_349;
- reg [31:0] _RAND_350;
- reg [31:0] _RAND_351;
- reg [31:0] _RAND_352;
- reg [31:0] _RAND_353;
- reg [31:0] _RAND_354;
- reg [31:0] _RAND_355;
- reg [31:0] _RAND_356;
- reg [31:0] _RAND_357;
- reg [31:0] _RAND_358;
- reg [31:0] _RAND_359;
- reg [31:0] _RAND_360;
- reg [31:0] _RAND_361;
- reg [31:0] _RAND_362;
- reg [31:0] _RAND_363;
- reg [31:0] _RAND_364;
- reg [31:0] _RAND_365;
- reg [31:0] _RAND_366;
- reg [31:0] _RAND_367;
- reg [31:0] _RAND_368;
- reg [31:0] _RAND_369;
- reg [31:0] _RAND_370;
- reg [31:0] _RAND_371;
- reg [31:0] _RAND_372;
- reg [31:0] _RAND_373;
- reg [31:0] _RAND_374;
- reg [31:0] _RAND_375;
- reg [31:0] _RAND_376;
- reg [31:0] _RAND_377;
- reg [31:0] _RAND_378;
- reg [31:0] _RAND_379;
- reg [31:0] _RAND_380;
- reg [31:0] _RAND_381;
- reg [31:0] _RAND_382;
- reg [31:0] _RAND_383;
- reg [31:0] _RAND_384;
- reg [31:0] _RAND_385;
- reg [31:0] _RAND_386;
- reg [31:0] _RAND_387;
- reg [31:0] _RAND_388;
- reg [31:0] _RAND_389;
- reg [31:0] _RAND_390;
- reg [31:0] _RAND_391;
- reg [31:0] _RAND_392;
- reg [31:0] _RAND_393;
- reg [31:0] _RAND_394;
- reg [31:0] _RAND_395;
- reg [31:0] _RAND_396;
- reg [31:0] _RAND_397;
- reg [31:0] _RAND_398;
- reg [31:0] _RAND_399;
- reg [31:0] _RAND_400;
- reg [31:0] _RAND_401;
- reg [31:0] _RAND_402;
- reg [31:0] _RAND_403;
- reg [31:0] _RAND_404;
- reg [31:0] _RAND_405;
- reg [31:0] _RAND_406;
- reg [31:0] _RAND_407;
- reg [31:0] _RAND_408;
- reg [31:0] _RAND_409;
- reg [31:0] _RAND_410;
- reg [31:0] _RAND_411;
- reg [31:0] _RAND_412;
- reg [31:0] _RAND_413;
- reg [31:0] _RAND_414;
- reg [31:0] _RAND_415;
- reg [31:0] _RAND_416;
- reg [31:0] _RAND_417;
- reg [31:0] _RAND_418;
- reg [31:0] _RAND_419;
- reg [31:0] _RAND_420;
- reg [31:0] _RAND_421;
- reg [31:0] _RAND_422;
- reg [31:0] _RAND_423;
- reg [31:0] _RAND_424;
- reg [31:0] _RAND_425;
- reg [31:0] _RAND_426;
- reg [31:0] _RAND_427;
- reg [31:0] _RAND_428;
- reg [31:0] _RAND_429;
- reg [31:0] _RAND_430;
- reg [31:0] _RAND_431;
- reg [31:0] _RAND_432;
- reg [31:0] _RAND_433;
- reg [31:0] _RAND_434;
- reg [31:0] _RAND_435;
- reg [31:0] _RAND_436;
- reg [31:0] _RAND_437;
- reg [31:0] _RAND_438;
- reg [31:0] _RAND_439;
- reg [31:0] _RAND_440;
- reg [31:0] _RAND_441;
- reg [31:0] _RAND_442;
- reg [31:0] _RAND_443;
- reg [31:0] _RAND_444;
- reg [31:0] _RAND_445;
- reg [31:0] _RAND_446;
- reg [31:0] _RAND_447;
- reg [31:0] _RAND_448;
- reg [31:0] _RAND_449;
- reg [31:0] _RAND_450;
- reg [31:0] _RAND_451;
- reg [31:0] _RAND_452;
- reg [31:0] _RAND_453;
- reg [31:0] _RAND_454;
- reg [31:0] _RAND_455;
- reg [31:0] _RAND_456;
- reg [31:0] _RAND_457;
- reg [31:0] _RAND_458;
- reg [31:0] _RAND_459;
- reg [31:0] _RAND_460;
- reg [31:0] _RAND_461;
- reg [31:0] _RAND_462;
- reg [31:0] _RAND_463;
- reg [31:0] _RAND_464;
- reg [31:0] _RAND_465;
- reg [31:0] _RAND_466;
- reg [31:0] _RAND_467;
- reg [31:0] _RAND_468;
- reg [31:0] _RAND_469;
- reg [31:0] _RAND_470;
- reg [31:0] _RAND_471;
- reg [31:0] _RAND_472;
- reg [31:0] _RAND_473;
- reg [31:0] _RAND_474;
- reg [31:0] _RAND_475;
- reg [31:0] _RAND_476;
- reg [31:0] _RAND_477;
- reg [31:0] _RAND_478;
- reg [31:0] _RAND_479;
- reg [31:0] _RAND_480;
- reg [31:0] _RAND_481;
- reg [31:0] _RAND_482;
- reg [31:0] _RAND_483;
- reg [31:0] _RAND_484;
- reg [31:0] _RAND_485;
- reg [31:0] _RAND_486;
- reg [31:0] _RAND_487;
- reg [31:0] _RAND_488;
- reg [31:0] _RAND_489;
- reg [31:0] _RAND_490;
- reg [31:0] _RAND_491;
- reg [31:0] _RAND_492;
- reg [31:0] _RAND_493;
- reg [31:0] _RAND_494;
- reg [31:0] _RAND_495;
- reg [31:0] _RAND_496;
- reg [31:0] _RAND_497;
- reg [31:0] _RAND_498;
- reg [31:0] _RAND_499;
- reg [31:0] _RAND_500;
- reg [31:0] _RAND_501;
- reg [31:0] _RAND_502;
- reg [31:0] _RAND_503;
- reg [31:0] _RAND_504;
- reg [31:0] _RAND_505;
- reg [31:0] _RAND_506;
- reg [31:0] _RAND_507;
- reg [31:0] _RAND_508;
- reg [31:0] _RAND_509;
- reg [31:0] _RAND_510;
- reg [31:0] _RAND_511;
- reg [31:0] _RAND_512;
- reg [31:0] _RAND_513;
- reg [31:0] _RAND_514;
- reg [31:0] _RAND_515;
- reg [31:0] _RAND_516;
- reg [31:0] _RAND_517;
- reg [31:0] _RAND_518;
- reg [31:0] _RAND_519;
- reg [31:0] _RAND_520;
- reg [31:0] _RAND_521;
- reg [31:0] _RAND_522;
- reg [31:0] _RAND_523;
- reg [31:0] _RAND_524;
- reg [31:0] _RAND_525;
- reg [31:0] _RAND_526;
- reg [31:0] _RAND_527;
- reg [31:0] _RAND_528;
- reg [31:0] _RAND_529;
- reg [31:0] _RAND_530;
- reg [31:0] _RAND_531;
- reg [31:0] _RAND_532;
- reg [31:0] _RAND_533;
- reg [31:0] _RAND_534;
- reg [31:0] _RAND_535;
- reg [31:0] _RAND_536;
- reg [31:0] _RAND_537;
- reg [31:0] _RAND_538;
- reg [31:0] _RAND_539;
- reg [31:0] _RAND_540;
- reg [31:0] _RAND_541;
- reg [31:0] _RAND_542;
- reg [31:0] _RAND_543;
- reg [31:0] _RAND_544;
- reg [31:0] _RAND_545;
- reg [31:0] _RAND_546;
- reg [31:0] _RAND_547;
- reg [31:0] _RAND_548;
- reg [31:0] _RAND_549;
- reg [31:0] _RAND_550;
- reg [31:0] _RAND_551;
- reg [31:0] _RAND_552;
- reg [31:0] _RAND_553;
- reg [31:0] _RAND_554;
- reg [31:0] _RAND_555;
- reg [31:0] _RAND_556;
- reg [31:0] _RAND_557;
- reg [31:0] _RAND_558;
- reg [31:0] _RAND_559;
- reg [31:0] _RAND_560;
- reg [31:0] _RAND_561;
- reg [31:0] _RAND_562;
- reg [31:0] _RAND_563;
- reg [31:0] _RAND_564;
- reg [31:0] _RAND_565;
- reg [31:0] _RAND_566;
- reg [31:0] _RAND_567;
- reg [31:0] _RAND_568;
- reg [31:0] _RAND_569;
- reg [31:0] _RAND_570;
- reg [31:0] _RAND_571;
- reg [31:0] _RAND_572;
- reg [31:0] _RAND_573;
- reg [31:0] _RAND_574;
- reg [31:0] _RAND_575;
- reg [31:0] _RAND_576;
- reg [31:0] _RAND_577;
- reg [31:0] _RAND_578;
- reg [31:0] _RAND_579;
- reg [31:0] _RAND_580;
- reg [31:0] _RAND_581;
- reg [31:0] _RAND_582;
- reg [31:0] _RAND_583;
- reg [31:0] _RAND_584;
- reg [31:0] _RAND_585;
- reg [31:0] _RAND_586;
- reg [31:0] _RAND_587;
- reg [31:0] _RAND_588;
- reg [31:0] _RAND_589;
- reg [31:0] _RAND_590;
- reg [31:0] _RAND_591;
- reg [31:0] _RAND_592;
- reg [31:0] _RAND_593;
- reg [31:0] _RAND_594;
- reg [31:0] _RAND_595;
- reg [31:0] _RAND_596;
- reg [31:0] _RAND_597;
- reg [31:0] _RAND_598;
- reg [31:0] _RAND_599;
- reg [31:0] _RAND_600;
- reg [31:0] _RAND_601;
- reg [31:0] _RAND_602;
- reg [31:0] _RAND_603;
- reg [31:0] _RAND_604;
- reg [31:0] _RAND_605;
- reg [31:0] _RAND_606;
- reg [31:0] _RAND_607;
- reg [31:0] _RAND_608;
- reg [31:0] _RAND_609;
- reg [31:0] _RAND_610;
- reg [31:0] _RAND_611;
- reg [31:0] _RAND_612;
- reg [31:0] _RAND_613;
- reg [31:0] _RAND_614;
- reg [31:0] _RAND_615;
- reg [31:0] _RAND_616;
- reg [31:0] _RAND_617;
- reg [31:0] _RAND_618;
- reg [31:0] _RAND_619;
- reg [31:0] _RAND_620;
- reg [31:0] _RAND_621;
- reg [31:0] _RAND_622;
- reg [31:0] _RAND_623;
- reg [31:0] _RAND_624;
- reg [31:0] _RAND_625;
- reg [31:0] _RAND_626;
- reg [31:0] _RAND_627;
- reg [31:0] _RAND_628;
- reg [31:0] _RAND_629;
- reg [31:0] _RAND_630;
- reg [31:0] _RAND_631;
- reg [31:0] _RAND_632;
- reg [31:0] _RAND_633;
- reg [31:0] _RAND_634;
- reg [31:0] _RAND_635;
- reg [31:0] _RAND_636;
- reg [31:0] _RAND_637;
- reg [31:0] _RAND_638;
- reg [31:0] _RAND_639;
- reg [31:0] _RAND_640;
- reg [31:0] _RAND_641;
- reg [31:0] _RAND_642;
- reg [31:0] _RAND_643;
- reg [31:0] _RAND_644;
- reg [31:0] _RAND_645;
- reg [31:0] _RAND_646;
- reg [31:0] _RAND_647;
- reg [31:0] _RAND_648;
- reg [31:0] _RAND_649;
- reg [31:0] _RAND_650;
- reg [31:0] _RAND_651;
- reg [31:0] _RAND_652;
- reg [31:0] _RAND_653;
- reg [31:0] _RAND_654;
- reg [31:0] _RAND_655;
- reg [31:0] _RAND_656;
- reg [31:0] _RAND_657;
- reg [31:0] _RAND_658;
- reg [31:0] _RAND_659;
- reg [31:0] _RAND_660;
- reg [31:0] _RAND_661;
- reg [31:0] _RAND_662;
- reg [31:0] _RAND_663;
- reg [31:0] _RAND_664;
- reg [31:0] _RAND_665;
- reg [31:0] _RAND_666;
- reg [31:0] _RAND_667;
- reg [31:0] _RAND_668;
- reg [31:0] _RAND_669;
- reg [31:0] _RAND_670;
- reg [31:0] _RAND_671;
- reg [31:0] _RAND_672;
- reg [31:0] _RAND_673;
- reg [31:0] _RAND_674;
- reg [31:0] _RAND_675;
- reg [31:0] _RAND_676;
- reg [31:0] _RAND_677;
- reg [31:0] _RAND_678;
- reg [31:0] _RAND_679;
- reg [31:0] _RAND_680;
- reg [31:0] _RAND_681;
- reg [31:0] _RAND_682;
- reg [31:0] _RAND_683;
- reg [31:0] _RAND_684;
- reg [31:0] _RAND_685;
- reg [31:0] _RAND_686;
- reg [31:0] _RAND_687;
- reg [31:0] _RAND_688;
- reg [31:0] _RAND_689;
- reg [31:0] _RAND_690;
- reg [31:0] _RAND_691;
- reg [31:0] _RAND_692;
- reg [31:0] _RAND_693;
- reg [31:0] _RAND_694;
- reg [31:0] _RAND_695;
- reg [31:0] _RAND_696;
- reg [31:0] _RAND_697;
- reg [31:0] _RAND_698;
- reg [31:0] _RAND_699;
- reg [31:0] _RAND_700;
- reg [31:0] _RAND_701;
- reg [31:0] _RAND_702;
- reg [31:0] _RAND_703;
- reg [31:0] _RAND_704;
- reg [31:0] _RAND_705;
- reg [31:0] _RAND_706;
- reg [31:0] _RAND_707;
- reg [31:0] _RAND_708;
- reg [31:0] _RAND_709;
- reg [31:0] _RAND_710;
- reg [31:0] _RAND_711;
- reg [31:0] _RAND_712;
- reg [31:0] _RAND_713;
- reg [31:0] _RAND_714;
- reg [31:0] _RAND_715;
- reg [31:0] _RAND_716;
- reg [31:0] _RAND_717;
- reg [31:0] _RAND_718;
- reg [31:0] _RAND_719;
- reg [31:0] _RAND_720;
- reg [31:0] _RAND_721;
- reg [31:0] _RAND_722;
- reg [31:0] _RAND_723;
- reg [31:0] _RAND_724;
- reg [31:0] _RAND_725;
- reg [31:0] _RAND_726;
- reg [31:0] _RAND_727;
- reg [31:0] _RAND_728;
- reg [31:0] _RAND_729;
- reg [31:0] _RAND_730;
- reg [31:0] _RAND_731;
- reg [31:0] _RAND_732;
- reg [31:0] _RAND_733;
- reg [31:0] _RAND_734;
- reg [31:0] _RAND_735;
- reg [31:0] _RAND_736;
- reg [31:0] _RAND_737;
- reg [31:0] _RAND_738;
- reg [31:0] _RAND_739;
- reg [31:0] _RAND_740;
- reg [31:0] _RAND_741;
- reg [31:0] _RAND_742;
- reg [31:0] _RAND_743;
- reg [31:0] _RAND_744;
- reg [31:0] _RAND_745;
- reg [31:0] _RAND_746;
- reg [31:0] _RAND_747;
- reg [31:0] _RAND_748;
- reg [31:0] _RAND_749;
- reg [31:0] _RAND_750;
- reg [31:0] _RAND_751;
- reg [31:0] _RAND_752;
- reg [31:0] _RAND_753;
- reg [31:0] _RAND_754;
- reg [31:0] _RAND_755;
- reg [31:0] _RAND_756;
- reg [31:0] _RAND_757;
- reg [31:0] _RAND_758;
- reg [31:0] _RAND_759;
- reg [31:0] _RAND_760;
- reg [31:0] _RAND_761;
- reg [31:0] _RAND_762;
- reg [31:0] _RAND_763;
- reg [31:0] _RAND_764;
- reg [31:0] _RAND_765;
- reg [31:0] _RAND_766;
- reg [31:0] _RAND_767;
- reg [31:0] _RAND_768;
- reg [31:0] _RAND_769;
- reg [31:0] _RAND_770;
- reg [31:0] _RAND_771;
- reg [31:0] _RAND_772;
- reg [31:0] _RAND_773;
- reg [31:0] _RAND_774;
- reg [31:0] _RAND_775;
- reg [31:0] _RAND_776;
- reg [31:0] _RAND_777;
- reg [31:0] _RAND_778;
- reg [31:0] _RAND_779;
- reg [31:0] _RAND_780;
- reg [31:0] _RAND_781;
- reg [31:0] _RAND_782;
- reg [31:0] _RAND_783;
- reg [31:0] _RAND_784;
- reg [31:0] _RAND_785;
- reg [31:0] _RAND_786;
- reg [31:0] _RAND_787;
- reg [31:0] _RAND_788;
- reg [31:0] _RAND_789;
- reg [31:0] _RAND_790;
- reg [31:0] _RAND_791;
- reg [31:0] _RAND_792;
- reg [31:0] _RAND_793;
- reg [31:0] _RAND_794;
- reg [31:0] _RAND_795;
- reg [31:0] _RAND_796;
- reg [31:0] _RAND_797;
- reg [31:0] _RAND_798;
- reg [31:0] _RAND_799;
- reg [31:0] _RAND_800;
- reg [31:0] _RAND_801;
- reg [31:0] _RAND_802;
- reg [31:0] _RAND_803;
- reg [31:0] _RAND_804;
- reg [31:0] _RAND_805;
- reg [31:0] _RAND_806;
- reg [31:0] _RAND_807;
- reg [31:0] _RAND_808;
- reg [31:0] _RAND_809;
- reg [31:0] _RAND_810;
- reg [31:0] _RAND_811;
- reg [31:0] _RAND_812;
- reg [31:0] _RAND_813;
- reg [31:0] _RAND_814;
- reg [31:0] _RAND_815;
- reg [31:0] _RAND_816;
- reg [31:0] _RAND_817;
- reg [31:0] _RAND_818;
- reg [31:0] _RAND_819;
- reg [31:0] _RAND_820;
- reg [31:0] _RAND_821;
- reg [31:0] _RAND_822;
- reg [31:0] _RAND_823;
- reg [31:0] _RAND_824;
- reg [31:0] _RAND_825;
- reg [31:0] _RAND_826;
- reg [31:0] _RAND_827;
- reg [31:0] _RAND_828;
- reg [31:0] _RAND_829;
- reg [31:0] _RAND_830;
- reg [31:0] _RAND_831;
- reg [31:0] _RAND_832;
- reg [31:0] _RAND_833;
- reg [31:0] _RAND_834;
- reg [31:0] _RAND_835;
- reg [31:0] _RAND_836;
- reg [31:0] _RAND_837;
- reg [31:0] _RAND_838;
- reg [31:0] _RAND_839;
- reg [31:0] _RAND_840;
- reg [31:0] _RAND_841;
- reg [31:0] _RAND_842;
- reg [31:0] _RAND_843;
- reg [31:0] _RAND_844;
- reg [31:0] _RAND_845;
- reg [31:0] _RAND_846;
- reg [31:0] _RAND_847;
- reg [31:0] _RAND_848;
- reg [31:0] _RAND_849;
- reg [31:0] _RAND_850;
- reg [31:0] _RAND_851;
- reg [31:0] _RAND_852;
- reg [31:0] _RAND_853;
- reg [31:0] _RAND_854;
- reg [31:0] _RAND_855;
- reg [31:0] _RAND_856;
- reg [31:0] _RAND_857;
- reg [31:0] _RAND_858;
- reg [31:0] _RAND_859;
- reg [31:0] _RAND_860;
- reg [31:0] _RAND_861;
- reg [31:0] _RAND_862;
- reg [31:0] _RAND_863;
- reg [31:0] _RAND_864;
- reg [31:0] _RAND_865;
- reg [31:0] _RAND_866;
- reg [31:0] _RAND_867;
- reg [31:0] _RAND_868;
- reg [31:0] _RAND_869;
- reg [31:0] _RAND_870;
- reg [31:0] _RAND_871;
- reg [31:0] _RAND_872;
- reg [31:0] _RAND_873;
- reg [31:0] _RAND_874;
- reg [31:0] _RAND_875;
- reg [31:0] _RAND_876;
- reg [31:0] _RAND_877;
- reg [31:0] _RAND_878;
- reg [31:0] _RAND_879;
- reg [31:0] _RAND_880;
- reg [31:0] _RAND_881;
- reg [31:0] _RAND_882;
- reg [31:0] _RAND_883;
- reg [31:0] _RAND_884;
- reg [31:0] _RAND_885;
- reg [31:0] _RAND_886;
- reg [31:0] _RAND_887;
- reg [31:0] _RAND_888;
- reg [31:0] _RAND_889;
- reg [31:0] _RAND_890;
- reg [31:0] _RAND_891;
- reg [31:0] _RAND_892;
- reg [31:0] _RAND_893;
- reg [31:0] _RAND_894;
- reg [31:0] _RAND_895;
- reg [31:0] _RAND_896;
- reg [31:0] _RAND_897;
- reg [31:0] _RAND_898;
- reg [31:0] _RAND_899;
- reg [31:0] _RAND_900;
- reg [31:0] _RAND_901;
- reg [31:0] _RAND_902;
- reg [31:0] _RAND_903;
- reg [31:0] _RAND_904;
- reg [31:0] _RAND_905;
- reg [31:0] _RAND_906;
- reg [31:0] _RAND_907;
- reg [31:0] _RAND_908;
- reg [31:0] _RAND_909;
- reg [31:0] _RAND_910;
- reg [31:0] _RAND_911;
- reg [31:0] _RAND_912;
- reg [31:0] _RAND_913;
- reg [31:0] _RAND_914;
- reg [31:0] _RAND_915;
- reg [31:0] _RAND_916;
- reg [31:0] _RAND_917;
- reg [31:0] _RAND_918;
- reg [31:0] _RAND_919;
- reg [31:0] _RAND_920;
- reg [31:0] _RAND_921;
- reg [31:0] _RAND_922;
- reg [31:0] _RAND_923;
- reg [31:0] _RAND_924;
- reg [31:0] _RAND_925;
- reg [31:0] _RAND_926;
- reg [31:0] _RAND_927;
- reg [31:0] _RAND_928;
- reg [31:0] _RAND_929;
- reg [31:0] _RAND_930;
- reg [31:0] _RAND_931;
- reg [31:0] _RAND_932;
- reg [31:0] _RAND_933;
- reg [31:0] _RAND_934;
- reg [31:0] _RAND_935;
- reg [31:0] _RAND_936;
- reg [31:0] _RAND_937;
- reg [31:0] _RAND_938;
- reg [31:0] _RAND_939;
- reg [31:0] _RAND_940;
- reg [31:0] _RAND_941;
- reg [31:0] _RAND_942;
- reg [31:0] _RAND_943;
- reg [31:0] _RAND_944;
- reg [31:0] _RAND_945;
- reg [31:0] _RAND_946;
- reg [31:0] _RAND_947;
- reg [31:0] _RAND_948;
- reg [31:0] _RAND_949;
- reg [31:0] _RAND_950;
- reg [31:0] _RAND_951;
- reg [31:0] _RAND_952;
- reg [31:0] _RAND_953;
- reg [31:0] _RAND_954;
- reg [31:0] _RAND_955;
- reg [31:0] _RAND_956;
- reg [31:0] _RAND_957;
- reg [31:0] _RAND_958;
- reg [31:0] _RAND_959;
- reg [31:0] _RAND_960;
- reg [31:0] _RAND_961;
- reg [31:0] _RAND_962;
- reg [31:0] _RAND_963;
- reg [31:0] _RAND_964;
- reg [31:0] _RAND_965;
- reg [31:0] _RAND_966;
- reg [31:0] _RAND_967;
- reg [31:0] _RAND_968;
- reg [31:0] _RAND_969;
- reg [31:0] _RAND_970;
- reg [31:0] _RAND_971;
- reg [31:0] _RAND_972;
- reg [31:0] _RAND_973;
- reg [31:0] _RAND_974;
- reg [31:0] _RAND_975;
- reg [31:0] _RAND_976;
- reg [31:0] _RAND_977;
- reg [31:0] _RAND_978;
- reg [31:0] _RAND_979;
- reg [31:0] _RAND_980;
- reg [31:0] _RAND_981;
- reg [31:0] _RAND_982;
- reg [31:0] _RAND_983;
- reg [31:0] _RAND_984;
- reg [31:0] _RAND_985;
- reg [31:0] _RAND_986;
- reg [31:0] _RAND_987;
- reg [31:0] _RAND_988;
- reg [31:0] _RAND_989;
- reg [31:0] _RAND_990;
- reg [31:0] _RAND_991;
- reg [31:0] _RAND_992;
- reg [31:0] _RAND_993;
- reg [31:0] _RAND_994;
- reg [31:0] _RAND_995;
- reg [31:0] _RAND_996;
- reg [31:0] _RAND_997;
- reg [31:0] _RAND_998;
- reg [31:0] _RAND_999;
- reg [31:0] _RAND_1000;
- reg [31:0] _RAND_1001;
- reg [31:0] _RAND_1002;
- reg [31:0] _RAND_1003;
- reg [31:0] _RAND_1004;
- reg [31:0] _RAND_1005;
- reg [31:0] _RAND_1006;
- reg [31:0] _RAND_1007;
- reg [31:0] _RAND_1008;
- reg [31:0] _RAND_1009;
- reg [31:0] _RAND_1010;
- reg [31:0] _RAND_1011;
- reg [31:0] _RAND_1012;
- reg [31:0] _RAND_1013;
- reg [31:0] _RAND_1014;
- reg [31:0] _RAND_1015;
- reg [31:0] _RAND_1016;
- reg [31:0] _RAND_1017;
- reg [31:0] _RAND_1018;
- reg [31:0] _RAND_1019;
- reg [31:0] _RAND_1020;
- reg [31:0] _RAND_1021;
- reg [31:0] _RAND_1022;
- reg [31:0] _RAND_1023;
- reg [31:0] _RAND_1024;
- reg [31:0] _RAND_1025;
- reg [31:0] _RAND_1026;
- reg [31:0] _RAND_1027;
- reg [31:0] _RAND_1028;
- reg [31:0] _RAND_1029;
- reg [31:0] _RAND_1030;
- reg [31:0] _RAND_1031;
- reg [31:0] _RAND_1032;
- reg [31:0] _RAND_1033;
- reg [31:0] _RAND_1034;
- reg [31:0] _RAND_1035;
- reg [31:0] _RAND_1036;
- reg [31:0] _RAND_1037;
- reg [31:0] _RAND_1038;
- reg [31:0] _RAND_1039;
- reg [31:0] _RAND_1040;
- reg [31:0] _RAND_1041;
- reg [31:0] _RAND_1042;
- reg [31:0] _RAND_1043;
- reg [31:0] _RAND_1044;
- reg [31:0] _RAND_1045;
- reg [31:0] _RAND_1046;
- reg [31:0] _RAND_1047;
- reg [31:0] _RAND_1048;
- reg [31:0] _RAND_1049;
- reg [31:0] _RAND_1050;
- reg [31:0] _RAND_1051;
- reg [31:0] _RAND_1052;
- reg [31:0] _RAND_1053;
- reg [31:0] _RAND_1054;
- reg [31:0] _RAND_1055;
- reg [31:0] _RAND_1056;
- reg [31:0] _RAND_1057;
- reg [31:0] _RAND_1058;
- reg [31:0] _RAND_1059;
- reg [31:0] _RAND_1060;
- reg [31:0] _RAND_1061;
- reg [31:0] _RAND_1062;
- reg [31:0] _RAND_1063;
- reg [31:0] _RAND_1064;
- reg [31:0] _RAND_1065;
- reg [31:0] _RAND_1066;
- reg [31:0] _RAND_1067;
- reg [31:0] _RAND_1068;
- reg [31:0] _RAND_1069;
- reg [31:0] _RAND_1070;
- reg [31:0] _RAND_1071;
- reg [31:0] _RAND_1072;
- reg [31:0] _RAND_1073;
- reg [31:0] _RAND_1074;
- reg [31:0] _RAND_1075;
- reg [31:0] _RAND_1076;
- reg [31:0] _RAND_1077;
- reg [31:0] _RAND_1078;
- reg [31:0] _RAND_1079;
- reg [31:0] _RAND_1080;
- reg [31:0] _RAND_1081;
- reg [31:0] _RAND_1082;
- reg [31:0] _RAND_1083;
- reg [31:0] _RAND_1084;
- reg [31:0] _RAND_1085;
- reg [31:0] _RAND_1086;
- reg [31:0] _RAND_1087;
- reg [31:0] _RAND_1088;
- reg [31:0] _RAND_1089;
- reg [31:0] _RAND_1090;
- reg [31:0] _RAND_1091;
- reg [31:0] _RAND_1092;
- reg [31:0] _RAND_1093;
- reg [31:0] _RAND_1094;
- reg [31:0] _RAND_1095;
- reg [31:0] _RAND_1096;
- reg [31:0] _RAND_1097;
- reg [31:0] _RAND_1098;
- reg [31:0] _RAND_1099;
- reg [31:0] _RAND_1100;
- reg [31:0] _RAND_1101;
- reg [31:0] _RAND_1102;
- reg [31:0] _RAND_1103;
- reg [31:0] _RAND_1104;
- reg [31:0] _RAND_1105;
- reg [31:0] _RAND_1106;
- reg [31:0] _RAND_1107;
- reg [31:0] _RAND_1108;
- reg [31:0] _RAND_1109;
- reg [31:0] _RAND_1110;
- reg [31:0] _RAND_1111;
- reg [31:0] _RAND_1112;
- reg [31:0] _RAND_1113;
- reg [31:0] _RAND_1114;
- reg [31:0] _RAND_1115;
- reg [31:0] _RAND_1116;
- reg [31:0] _RAND_1117;
- reg [31:0] _RAND_1118;
- reg [31:0] _RAND_1119;
- reg [31:0] _RAND_1120;
- reg [31:0] _RAND_1121;
- reg [31:0] _RAND_1122;
- reg [31:0] _RAND_1123;
- reg [31:0] _RAND_1124;
- reg [31:0] _RAND_1125;
- reg [31:0] _RAND_1126;
- reg [31:0] _RAND_1127;
- reg [31:0] _RAND_1128;
- reg [31:0] _RAND_1129;
- reg [31:0] _RAND_1130;
- reg [31:0] _RAND_1131;
- reg [31:0] _RAND_1132;
- reg [31:0] _RAND_1133;
- reg [31:0] _RAND_1134;
- reg [31:0] _RAND_1135;
- reg [31:0] _RAND_1136;
- reg [31:0] _RAND_1137;
- reg [31:0] _RAND_1138;
- reg [31:0] _RAND_1139;
- reg [31:0] _RAND_1140;
- reg [31:0] _RAND_1141;
- reg [31:0] _RAND_1142;
- reg [31:0] _RAND_1143;
- reg [31:0] _RAND_1144;
- reg [31:0] _RAND_1145;
- reg [31:0] _RAND_1146;
- reg [31:0] _RAND_1147;
- reg [31:0] _RAND_1148;
- reg [31:0] _RAND_1149;
- reg [31:0] _RAND_1150;
- reg [31:0] _RAND_1151;
- reg [31:0] _RAND_1152;
- reg [31:0] _RAND_1153;
- reg [31:0] _RAND_1154;
- reg [31:0] _RAND_1155;
- reg [31:0] _RAND_1156;
- reg [31:0] _RAND_1157;
- reg [31:0] _RAND_1158;
- reg [31:0] _RAND_1159;
- reg [31:0] _RAND_1160;
- reg [31:0] _RAND_1161;
- reg [31:0] _RAND_1162;
- reg [31:0] _RAND_1163;
- reg [31:0] _RAND_1164;
- reg [31:0] _RAND_1165;
- reg [31:0] _RAND_1166;
- reg [31:0] _RAND_1167;
- reg [31:0] _RAND_1168;
- reg [31:0] _RAND_1169;
- reg [31:0] _RAND_1170;
- reg [31:0] _RAND_1171;
- reg [31:0] _RAND_1172;
- reg [31:0] _RAND_1173;
- reg [31:0] _RAND_1174;
- reg [31:0] _RAND_1175;
- reg [31:0] _RAND_1176;
- reg [31:0] _RAND_1177;
- reg [31:0] _RAND_1178;
- reg [31:0] _RAND_1179;
- reg [31:0] _RAND_1180;
- reg [31:0] _RAND_1181;
- reg [31:0] _RAND_1182;
- reg [31:0] _RAND_1183;
- reg [31:0] _RAND_1184;
- reg [31:0] _RAND_1185;
- reg [31:0] _RAND_1186;
- reg [31:0] _RAND_1187;
- reg [31:0] _RAND_1188;
- reg [31:0] _RAND_1189;
- reg [31:0] _RAND_1190;
- reg [31:0] _RAND_1191;
- reg [31:0] _RAND_1192;
- reg [31:0] _RAND_1193;
- reg [31:0] _RAND_1194;
- reg [31:0] _RAND_1195;
- reg [31:0] _RAND_1196;
- reg [31:0] _RAND_1197;
- reg [31:0] _RAND_1198;
- reg [31:0] _RAND_1199;
- reg [31:0] _RAND_1200;
- reg [31:0] _RAND_1201;
- reg [31:0] _RAND_1202;
- reg [31:0] _RAND_1203;
- reg [31:0] _RAND_1204;
- reg [31:0] _RAND_1205;
- reg [31:0] _RAND_1206;
- reg [31:0] _RAND_1207;
- reg [31:0] _RAND_1208;
- reg [31:0] _RAND_1209;
- reg [31:0] _RAND_1210;
- reg [31:0] _RAND_1211;
- reg [31:0] _RAND_1212;
- reg [31:0] _RAND_1213;
- reg [31:0] _RAND_1214;
- reg [31:0] _RAND_1215;
- reg [31:0] _RAND_1216;
- reg [31:0] _RAND_1217;
- reg [31:0] _RAND_1218;
- reg [31:0] _RAND_1219;
- reg [31:0] _RAND_1220;
- reg [31:0] _RAND_1221;
- reg [31:0] _RAND_1222;
- reg [31:0] _RAND_1223;
- reg [31:0] _RAND_1224;
- reg [31:0] _RAND_1225;
- reg [31:0] _RAND_1226;
- reg [31:0] _RAND_1227;
- reg [31:0] _RAND_1228;
- reg [31:0] _RAND_1229;
- reg [31:0] _RAND_1230;
- reg [31:0] _RAND_1231;
- reg [31:0] _RAND_1232;
- reg [31:0] _RAND_1233;
- reg [31:0] _RAND_1234;
- reg [31:0] _RAND_1235;
- reg [31:0] _RAND_1236;
- reg [31:0] _RAND_1237;
- reg [31:0] _RAND_1238;
- reg [31:0] _RAND_1239;
- reg [31:0] _RAND_1240;
- reg [31:0] _RAND_1241;
- reg [31:0] _RAND_1242;
- reg [31:0] _RAND_1243;
- reg [31:0] _RAND_1244;
- reg [31:0] _RAND_1245;
- reg [31:0] _RAND_1246;
- reg [31:0] _RAND_1247;
- reg [31:0] _RAND_1248;
- reg [31:0] _RAND_1249;
- reg [31:0] _RAND_1250;
- reg [31:0] _RAND_1251;
- reg [31:0] _RAND_1252;
- reg [31:0] _RAND_1253;
- reg [31:0] _RAND_1254;
- reg [31:0] _RAND_1255;
- reg [31:0] _RAND_1256;
- reg [31:0] _RAND_1257;
- reg [31:0] _RAND_1258;
- reg [31:0] _RAND_1259;
- reg [31:0] _RAND_1260;
- reg [31:0] _RAND_1261;
- reg [31:0] _RAND_1262;
- reg [31:0] _RAND_1263;
- reg [31:0] _RAND_1264;
- reg [31:0] _RAND_1265;
- reg [31:0] _RAND_1266;
- reg [31:0] _RAND_1267;
- reg [31:0] _RAND_1268;
- reg [31:0] _RAND_1269;
- reg [31:0] _RAND_1270;
- reg [31:0] _RAND_1271;
- reg [31:0] _RAND_1272;
- reg [31:0] _RAND_1273;
- reg [31:0] _RAND_1274;
- reg [31:0] _RAND_1275;
- reg [31:0] _RAND_1276;
- reg [31:0] _RAND_1277;
- reg [31:0] _RAND_1278;
- reg [31:0] _RAND_1279;
- reg [31:0] _RAND_1280;
- reg [31:0] _RAND_1281;
- reg [31:0] _RAND_1282;
- reg [31:0] _RAND_1283;
- reg [31:0] _RAND_1284;
- reg [31:0] _RAND_1285;
- reg [31:0] _RAND_1286;
- reg [31:0] _RAND_1287;
- reg [31:0] _RAND_1288;
- reg [255:0] _RAND_1289;
- reg [31:0] _RAND_1290;
- reg [31:0] _RAND_1291;
- reg [31:0] _RAND_1292;
- reg [31:0] _RAND_1293;
- reg [31:0] _RAND_1294;
-`endif // RANDOMIZE_REG_INIT
- wire mem_clock; // @[L1DCache.scala 345:19]
- wire mem_valid; // @[L1DCache.scala 345:19]
- wire mem_write; // @[L1DCache.scala 345:19]
- wire [7:0] mem_addr; // @[L1DCache.scala 345:19]
- wire [287:0] mem_wdata; // @[L1DCache.scala 345:19]
- wire [31:0] mem_wmask; // @[L1DCache.scala 345:19]
- wire [287:0] mem_rdata; // @[L1DCache.scala 345:19]
- wire mem_volt_sel; // @[L1DCache.scala 345:19]
- wire [5:0] _chkmask0_T_2 = 6'h20 - io_dbus_size; // @[L1DCache.scala 335:52]
- wire [31:0] chkmask0 = 32'hffffffff >> _chkmask0_T_2; // @[L1DCache.scala 335:37]
- wire [63:0] _chkmask1_T = {chkmask0,chkmask0}; // @[Cat.scala 31:58]
- wire [94:0] _GEN_0 = {{31'd0}, _chkmask1_T}; // @[L1DCache.scala 336:42]
- wire [94:0] chkmask1 = _GEN_0 << io_dbus_addr[4:0]; // @[L1DCache.scala 336:42]
- wire [31:0] chkmask = chkmask1[63:32]; // @[L1DCache.scala 337:25]
- wire _T = io_dbus_valid & io_dbus_write; // @[L1DCache.scala 338:26]
- wire [31:0] _T_2 = ~chkmask; // @[L1DCache.scala 338:64]
- wire [31:0] _T_3 = io_dbus_wmask & _T_2; // @[L1DCache.scala 338:62]
- wire _T_7 = ~reset; // @[L1DCache.scala 338:9]
- reg valid_0; // @[L1DCache.scala 342:22]
- reg valid_1; // @[L1DCache.scala 342:22]
- reg valid_2; // @[L1DCache.scala 342:22]
- reg valid_3; // @[L1DCache.scala 342:22]
- reg valid_4; // @[L1DCache.scala 342:22]
- reg valid_5; // @[L1DCache.scala 342:22]
- reg valid_6; // @[L1DCache.scala 342:22]
- reg valid_7; // @[L1DCache.scala 342:22]
- reg valid_8; // @[L1DCache.scala 342:22]
- reg valid_9; // @[L1DCache.scala 342:22]
- reg valid_10; // @[L1DCache.scala 342:22]
- reg valid_11; // @[L1DCache.scala 342:22]
- reg valid_12; // @[L1DCache.scala 342:22]
- reg valid_13; // @[L1DCache.scala 342:22]
- reg valid_14; // @[L1DCache.scala 342:22]
- reg valid_15; // @[L1DCache.scala 342:22]
- reg valid_16; // @[L1DCache.scala 342:22]
- reg valid_17; // @[L1DCache.scala 342:22]
- reg valid_18; // @[L1DCache.scala 342:22]
- reg valid_19; // @[L1DCache.scala 342:22]
- reg valid_20; // @[L1DCache.scala 342:22]
- reg valid_21; // @[L1DCache.scala 342:22]
- reg valid_22; // @[L1DCache.scala 342:22]
- reg valid_23; // @[L1DCache.scala 342:22]
- reg valid_24; // @[L1DCache.scala 342:22]
- reg valid_25; // @[L1DCache.scala 342:22]
- reg valid_26; // @[L1DCache.scala 342:22]
- reg valid_27; // @[L1DCache.scala 342:22]
- reg valid_28; // @[L1DCache.scala 342:22]
- reg valid_29; // @[L1DCache.scala 342:22]
- reg valid_30; // @[L1DCache.scala 342:22]
- reg valid_31; // @[L1DCache.scala 342:22]
- reg valid_32; // @[L1DCache.scala 342:22]
- reg valid_33; // @[L1DCache.scala 342:22]
- reg valid_34; // @[L1DCache.scala 342:22]
- reg valid_35; // @[L1DCache.scala 342:22]
- reg valid_36; // @[L1DCache.scala 342:22]
- reg valid_37; // @[L1DCache.scala 342:22]
- reg valid_38; // @[L1DCache.scala 342:22]
- reg valid_39; // @[L1DCache.scala 342:22]
- reg valid_40; // @[L1DCache.scala 342:22]
- reg valid_41; // @[L1DCache.scala 342:22]
- reg valid_42; // @[L1DCache.scala 342:22]
- reg valid_43; // @[L1DCache.scala 342:22]
- reg valid_44; // @[L1DCache.scala 342:22]
- reg valid_45; // @[L1DCache.scala 342:22]
- reg valid_46; // @[L1DCache.scala 342:22]
- reg valid_47; // @[L1DCache.scala 342:22]
- reg valid_48; // @[L1DCache.scala 342:22]
- reg valid_49; // @[L1DCache.scala 342:22]
- reg valid_50; // @[L1DCache.scala 342:22]
- reg valid_51; // @[L1DCache.scala 342:22]
- reg valid_52; // @[L1DCache.scala 342:22]
- reg valid_53; // @[L1DCache.scala 342:22]
- reg valid_54; // @[L1DCache.scala 342:22]
- reg valid_55; // @[L1DCache.scala 342:22]
- reg valid_56; // @[L1DCache.scala 342:22]
- reg valid_57; // @[L1DCache.scala 342:22]
- reg valid_58; // @[L1DCache.scala 342:22]
- reg valid_59; // @[L1DCache.scala 342:22]
- reg valid_60; // @[L1DCache.scala 342:22]
- reg valid_61; // @[L1DCache.scala 342:22]
- reg valid_62; // @[L1DCache.scala 342:22]
- reg valid_63; // @[L1DCache.scala 342:22]
- reg valid_64; // @[L1DCache.scala 342:22]
- reg valid_65; // @[L1DCache.scala 342:22]
- reg valid_66; // @[L1DCache.scala 342:22]
- reg valid_67; // @[L1DCache.scala 342:22]
- reg valid_68; // @[L1DCache.scala 342:22]
- reg valid_69; // @[L1DCache.scala 342:22]
- reg valid_70; // @[L1DCache.scala 342:22]
- reg valid_71; // @[L1DCache.scala 342:22]
- reg valid_72; // @[L1DCache.scala 342:22]
- reg valid_73; // @[L1DCache.scala 342:22]
- reg valid_74; // @[L1DCache.scala 342:22]
- reg valid_75; // @[L1DCache.scala 342:22]
- reg valid_76; // @[L1DCache.scala 342:22]
- reg valid_77; // @[L1DCache.scala 342:22]
- reg valid_78; // @[L1DCache.scala 342:22]
- reg valid_79; // @[L1DCache.scala 342:22]
- reg valid_80; // @[L1DCache.scala 342:22]
- reg valid_81; // @[L1DCache.scala 342:22]
- reg valid_82; // @[L1DCache.scala 342:22]
- reg valid_83; // @[L1DCache.scala 342:22]
- reg valid_84; // @[L1DCache.scala 342:22]
- reg valid_85; // @[L1DCache.scala 342:22]
- reg valid_86; // @[L1DCache.scala 342:22]
- reg valid_87; // @[L1DCache.scala 342:22]
- reg valid_88; // @[L1DCache.scala 342:22]
- reg valid_89; // @[L1DCache.scala 342:22]
- reg valid_90; // @[L1DCache.scala 342:22]
- reg valid_91; // @[L1DCache.scala 342:22]
- reg valid_92; // @[L1DCache.scala 342:22]
- reg valid_93; // @[L1DCache.scala 342:22]
- reg valid_94; // @[L1DCache.scala 342:22]
- reg valid_95; // @[L1DCache.scala 342:22]
- reg valid_96; // @[L1DCache.scala 342:22]
- reg valid_97; // @[L1DCache.scala 342:22]
- reg valid_98; // @[L1DCache.scala 342:22]
- reg valid_99; // @[L1DCache.scala 342:22]
- reg valid_100; // @[L1DCache.scala 342:22]
- reg valid_101; // @[L1DCache.scala 342:22]
- reg valid_102; // @[L1DCache.scala 342:22]
- reg valid_103; // @[L1DCache.scala 342:22]
- reg valid_104; // @[L1DCache.scala 342:22]
- reg valid_105; // @[L1DCache.scala 342:22]
- reg valid_106; // @[L1DCache.scala 342:22]
- reg valid_107; // @[L1DCache.scala 342:22]
- reg valid_108; // @[L1DCache.scala 342:22]
- reg valid_109; // @[L1DCache.scala 342:22]
- reg valid_110; // @[L1DCache.scala 342:22]
- reg valid_111; // @[L1DCache.scala 342:22]
- reg valid_112; // @[L1DCache.scala 342:22]
- reg valid_113; // @[L1DCache.scala 342:22]
- reg valid_114; // @[L1DCache.scala 342:22]
- reg valid_115; // @[L1DCache.scala 342:22]
- reg valid_116; // @[L1DCache.scala 342:22]
- reg valid_117; // @[L1DCache.scala 342:22]
- reg valid_118; // @[L1DCache.scala 342:22]
- reg valid_119; // @[L1DCache.scala 342:22]
- reg valid_120; // @[L1DCache.scala 342:22]
- reg valid_121; // @[L1DCache.scala 342:22]
- reg valid_122; // @[L1DCache.scala 342:22]
- reg valid_123; // @[L1DCache.scala 342:22]
- reg valid_124; // @[L1DCache.scala 342:22]
- reg valid_125; // @[L1DCache.scala 342:22]
- reg valid_126; // @[L1DCache.scala 342:22]
- reg valid_127; // @[L1DCache.scala 342:22]
- reg valid_128; // @[L1DCache.scala 342:22]
- reg valid_129; // @[L1DCache.scala 342:22]
- reg valid_130; // @[L1DCache.scala 342:22]
- reg valid_131; // @[L1DCache.scala 342:22]
- reg valid_132; // @[L1DCache.scala 342:22]
- reg valid_133; // @[L1DCache.scala 342:22]
- reg valid_134; // @[L1DCache.scala 342:22]
- reg valid_135; // @[L1DCache.scala 342:22]
- reg valid_136; // @[L1DCache.scala 342:22]
- reg valid_137; // @[L1DCache.scala 342:22]
- reg valid_138; // @[L1DCache.scala 342:22]
- reg valid_139; // @[L1DCache.scala 342:22]
- reg valid_140; // @[L1DCache.scala 342:22]
- reg valid_141; // @[L1DCache.scala 342:22]
- reg valid_142; // @[L1DCache.scala 342:22]
- reg valid_143; // @[L1DCache.scala 342:22]
- reg valid_144; // @[L1DCache.scala 342:22]
- reg valid_145; // @[L1DCache.scala 342:22]
- reg valid_146; // @[L1DCache.scala 342:22]
- reg valid_147; // @[L1DCache.scala 342:22]
- reg valid_148; // @[L1DCache.scala 342:22]
- reg valid_149; // @[L1DCache.scala 342:22]
- reg valid_150; // @[L1DCache.scala 342:22]
- reg valid_151; // @[L1DCache.scala 342:22]
- reg valid_152; // @[L1DCache.scala 342:22]
- reg valid_153; // @[L1DCache.scala 342:22]
- reg valid_154; // @[L1DCache.scala 342:22]
- reg valid_155; // @[L1DCache.scala 342:22]
- reg valid_156; // @[L1DCache.scala 342:22]
- reg valid_157; // @[L1DCache.scala 342:22]
- reg valid_158; // @[L1DCache.scala 342:22]
- reg valid_159; // @[L1DCache.scala 342:22]
- reg valid_160; // @[L1DCache.scala 342:22]
- reg valid_161; // @[L1DCache.scala 342:22]
- reg valid_162; // @[L1DCache.scala 342:22]
- reg valid_163; // @[L1DCache.scala 342:22]
- reg valid_164; // @[L1DCache.scala 342:22]
- reg valid_165; // @[L1DCache.scala 342:22]
- reg valid_166; // @[L1DCache.scala 342:22]
- reg valid_167; // @[L1DCache.scala 342:22]
- reg valid_168; // @[L1DCache.scala 342:22]
- reg valid_169; // @[L1DCache.scala 342:22]
- reg valid_170; // @[L1DCache.scala 342:22]
- reg valid_171; // @[L1DCache.scala 342:22]
- reg valid_172; // @[L1DCache.scala 342:22]
- reg valid_173; // @[L1DCache.scala 342:22]
- reg valid_174; // @[L1DCache.scala 342:22]
- reg valid_175; // @[L1DCache.scala 342:22]
- reg valid_176; // @[L1DCache.scala 342:22]
- reg valid_177; // @[L1DCache.scala 342:22]
- reg valid_178; // @[L1DCache.scala 342:22]
- reg valid_179; // @[L1DCache.scala 342:22]
- reg valid_180; // @[L1DCache.scala 342:22]
- reg valid_181; // @[L1DCache.scala 342:22]
- reg valid_182; // @[L1DCache.scala 342:22]
- reg valid_183; // @[L1DCache.scala 342:22]
- reg valid_184; // @[L1DCache.scala 342:22]
- reg valid_185; // @[L1DCache.scala 342:22]
- reg valid_186; // @[L1DCache.scala 342:22]
- reg valid_187; // @[L1DCache.scala 342:22]
- reg valid_188; // @[L1DCache.scala 342:22]
- reg valid_189; // @[L1DCache.scala 342:22]
- reg valid_190; // @[L1DCache.scala 342:22]
- reg valid_191; // @[L1DCache.scala 342:22]
- reg valid_192; // @[L1DCache.scala 342:22]
- reg valid_193; // @[L1DCache.scala 342:22]
- reg valid_194; // @[L1DCache.scala 342:22]
- reg valid_195; // @[L1DCache.scala 342:22]
- reg valid_196; // @[L1DCache.scala 342:22]
- reg valid_197; // @[L1DCache.scala 342:22]
- reg valid_198; // @[L1DCache.scala 342:22]
- reg valid_199; // @[L1DCache.scala 342:22]
- reg valid_200; // @[L1DCache.scala 342:22]
- reg valid_201; // @[L1DCache.scala 342:22]
- reg valid_202; // @[L1DCache.scala 342:22]
- reg valid_203; // @[L1DCache.scala 342:22]
- reg valid_204; // @[L1DCache.scala 342:22]
- reg valid_205; // @[L1DCache.scala 342:22]
- reg valid_206; // @[L1DCache.scala 342:22]
- reg valid_207; // @[L1DCache.scala 342:22]
- reg valid_208; // @[L1DCache.scala 342:22]
- reg valid_209; // @[L1DCache.scala 342:22]
- reg valid_210; // @[L1DCache.scala 342:22]
- reg valid_211; // @[L1DCache.scala 342:22]
- reg valid_212; // @[L1DCache.scala 342:22]
- reg valid_213; // @[L1DCache.scala 342:22]
- reg valid_214; // @[L1DCache.scala 342:22]
- reg valid_215; // @[L1DCache.scala 342:22]
- reg valid_216; // @[L1DCache.scala 342:22]
- reg valid_217; // @[L1DCache.scala 342:22]
- reg valid_218; // @[L1DCache.scala 342:22]
- reg valid_219; // @[L1DCache.scala 342:22]
- reg valid_220; // @[L1DCache.scala 342:22]
- reg valid_221; // @[L1DCache.scala 342:22]
- reg valid_222; // @[L1DCache.scala 342:22]
- reg valid_223; // @[L1DCache.scala 342:22]
- reg valid_224; // @[L1DCache.scala 342:22]
- reg valid_225; // @[L1DCache.scala 342:22]
- reg valid_226; // @[L1DCache.scala 342:22]
- reg valid_227; // @[L1DCache.scala 342:22]
- reg valid_228; // @[L1DCache.scala 342:22]
- reg valid_229; // @[L1DCache.scala 342:22]
- reg valid_230; // @[L1DCache.scala 342:22]
- reg valid_231; // @[L1DCache.scala 342:22]
- reg valid_232; // @[L1DCache.scala 342:22]
- reg valid_233; // @[L1DCache.scala 342:22]
- reg valid_234; // @[L1DCache.scala 342:22]
- reg valid_235; // @[L1DCache.scala 342:22]
- reg valid_236; // @[L1DCache.scala 342:22]
- reg valid_237; // @[L1DCache.scala 342:22]
- reg valid_238; // @[L1DCache.scala 342:22]
- reg valid_239; // @[L1DCache.scala 342:22]
- reg valid_240; // @[L1DCache.scala 342:22]
- reg valid_241; // @[L1DCache.scala 342:22]
- reg valid_242; // @[L1DCache.scala 342:22]
- reg valid_243; // @[L1DCache.scala 342:22]
- reg valid_244; // @[L1DCache.scala 342:22]
- reg valid_245; // @[L1DCache.scala 342:22]
- reg valid_246; // @[L1DCache.scala 342:22]
- reg valid_247; // @[L1DCache.scala 342:22]
- reg valid_248; // @[L1DCache.scala 342:22]
- reg valid_249; // @[L1DCache.scala 342:22]
- reg valid_250; // @[L1DCache.scala 342:22]
- reg valid_251; // @[L1DCache.scala 342:22]
- reg valid_252; // @[L1DCache.scala 342:22]
- reg valid_253; // @[L1DCache.scala 342:22]
- reg valid_254; // @[L1DCache.scala 342:22]
- reg valid_255; // @[L1DCache.scala 342:22]
- reg dirty_0; // @[L1DCache.scala 343:22]
- reg dirty_1; // @[L1DCache.scala 343:22]
- reg dirty_2; // @[L1DCache.scala 343:22]
- reg dirty_3; // @[L1DCache.scala 343:22]
- reg dirty_4; // @[L1DCache.scala 343:22]
- reg dirty_5; // @[L1DCache.scala 343:22]
- reg dirty_6; // @[L1DCache.scala 343:22]
- reg dirty_7; // @[L1DCache.scala 343:22]
- reg dirty_8; // @[L1DCache.scala 343:22]
- reg dirty_9; // @[L1DCache.scala 343:22]
- reg dirty_10; // @[L1DCache.scala 343:22]
- reg dirty_11; // @[L1DCache.scala 343:22]
- reg dirty_12; // @[L1DCache.scala 343:22]
- reg dirty_13; // @[L1DCache.scala 343:22]
- reg dirty_14; // @[L1DCache.scala 343:22]
- reg dirty_15; // @[L1DCache.scala 343:22]
- reg dirty_16; // @[L1DCache.scala 343:22]
- reg dirty_17; // @[L1DCache.scala 343:22]
- reg dirty_18; // @[L1DCache.scala 343:22]
- reg dirty_19; // @[L1DCache.scala 343:22]
- reg dirty_20; // @[L1DCache.scala 343:22]
- reg dirty_21; // @[L1DCache.scala 343:22]
- reg dirty_22; // @[L1DCache.scala 343:22]
- reg dirty_23; // @[L1DCache.scala 343:22]
- reg dirty_24; // @[L1DCache.scala 343:22]
- reg dirty_25; // @[L1DCache.scala 343:22]
- reg dirty_26; // @[L1DCache.scala 343:22]
- reg dirty_27; // @[L1DCache.scala 343:22]
- reg dirty_28; // @[L1DCache.scala 343:22]
- reg dirty_29; // @[L1DCache.scala 343:22]
- reg dirty_30; // @[L1DCache.scala 343:22]
- reg dirty_31; // @[L1DCache.scala 343:22]
- reg dirty_32; // @[L1DCache.scala 343:22]
- reg dirty_33; // @[L1DCache.scala 343:22]
- reg dirty_34; // @[L1DCache.scala 343:22]
- reg dirty_35; // @[L1DCache.scala 343:22]
- reg dirty_36; // @[L1DCache.scala 343:22]
- reg dirty_37; // @[L1DCache.scala 343:22]
- reg dirty_38; // @[L1DCache.scala 343:22]
- reg dirty_39; // @[L1DCache.scala 343:22]
- reg dirty_40; // @[L1DCache.scala 343:22]
- reg dirty_41; // @[L1DCache.scala 343:22]
- reg dirty_42; // @[L1DCache.scala 343:22]
- reg dirty_43; // @[L1DCache.scala 343:22]
- reg dirty_44; // @[L1DCache.scala 343:22]
- reg dirty_45; // @[L1DCache.scala 343:22]
- reg dirty_46; // @[L1DCache.scala 343:22]
- reg dirty_47; // @[L1DCache.scala 343:22]
- reg dirty_48; // @[L1DCache.scala 343:22]
- reg dirty_49; // @[L1DCache.scala 343:22]
- reg dirty_50; // @[L1DCache.scala 343:22]
- reg dirty_51; // @[L1DCache.scala 343:22]
- reg dirty_52; // @[L1DCache.scala 343:22]
- reg dirty_53; // @[L1DCache.scala 343:22]
- reg dirty_54; // @[L1DCache.scala 343:22]
- reg dirty_55; // @[L1DCache.scala 343:22]
- reg dirty_56; // @[L1DCache.scala 343:22]
- reg dirty_57; // @[L1DCache.scala 343:22]
- reg dirty_58; // @[L1DCache.scala 343:22]
- reg dirty_59; // @[L1DCache.scala 343:22]
- reg dirty_60; // @[L1DCache.scala 343:22]
- reg dirty_61; // @[L1DCache.scala 343:22]
- reg dirty_62; // @[L1DCache.scala 343:22]
- reg dirty_63; // @[L1DCache.scala 343:22]
- reg dirty_64; // @[L1DCache.scala 343:22]
- reg dirty_65; // @[L1DCache.scala 343:22]
- reg dirty_66; // @[L1DCache.scala 343:22]
- reg dirty_67; // @[L1DCache.scala 343:22]
- reg dirty_68; // @[L1DCache.scala 343:22]
- reg dirty_69; // @[L1DCache.scala 343:22]
- reg dirty_70; // @[L1DCache.scala 343:22]
- reg dirty_71; // @[L1DCache.scala 343:22]
- reg dirty_72; // @[L1DCache.scala 343:22]
- reg dirty_73; // @[L1DCache.scala 343:22]
- reg dirty_74; // @[L1DCache.scala 343:22]
- reg dirty_75; // @[L1DCache.scala 343:22]
- reg dirty_76; // @[L1DCache.scala 343:22]
- reg dirty_77; // @[L1DCache.scala 343:22]
- reg dirty_78; // @[L1DCache.scala 343:22]
- reg dirty_79; // @[L1DCache.scala 343:22]
- reg dirty_80; // @[L1DCache.scala 343:22]
- reg dirty_81; // @[L1DCache.scala 343:22]
- reg dirty_82; // @[L1DCache.scala 343:22]
- reg dirty_83; // @[L1DCache.scala 343:22]
- reg dirty_84; // @[L1DCache.scala 343:22]
- reg dirty_85; // @[L1DCache.scala 343:22]
- reg dirty_86; // @[L1DCache.scala 343:22]
- reg dirty_87; // @[L1DCache.scala 343:22]
- reg dirty_88; // @[L1DCache.scala 343:22]
- reg dirty_89; // @[L1DCache.scala 343:22]
- reg dirty_90; // @[L1DCache.scala 343:22]
- reg dirty_91; // @[L1DCache.scala 343:22]
- reg dirty_92; // @[L1DCache.scala 343:22]
- reg dirty_93; // @[L1DCache.scala 343:22]
- reg dirty_94; // @[L1DCache.scala 343:22]
- reg dirty_95; // @[L1DCache.scala 343:22]
- reg dirty_96; // @[L1DCache.scala 343:22]
- reg dirty_97; // @[L1DCache.scala 343:22]
- reg dirty_98; // @[L1DCache.scala 343:22]
- reg dirty_99; // @[L1DCache.scala 343:22]
- reg dirty_100; // @[L1DCache.scala 343:22]
- reg dirty_101; // @[L1DCache.scala 343:22]
- reg dirty_102; // @[L1DCache.scala 343:22]
- reg dirty_103; // @[L1DCache.scala 343:22]
- reg dirty_104; // @[L1DCache.scala 343:22]
- reg dirty_105; // @[L1DCache.scala 343:22]
- reg dirty_106; // @[L1DCache.scala 343:22]
- reg dirty_107; // @[L1DCache.scala 343:22]
- reg dirty_108; // @[L1DCache.scala 343:22]
- reg dirty_109; // @[L1DCache.scala 343:22]
- reg dirty_110; // @[L1DCache.scala 343:22]
- reg dirty_111; // @[L1DCache.scala 343:22]
- reg dirty_112; // @[L1DCache.scala 343:22]
- reg dirty_113; // @[L1DCache.scala 343:22]
- reg dirty_114; // @[L1DCache.scala 343:22]
- reg dirty_115; // @[L1DCache.scala 343:22]
- reg dirty_116; // @[L1DCache.scala 343:22]
- reg dirty_117; // @[L1DCache.scala 343:22]
- reg dirty_118; // @[L1DCache.scala 343:22]
- reg dirty_119; // @[L1DCache.scala 343:22]
- reg dirty_120; // @[L1DCache.scala 343:22]
- reg dirty_121; // @[L1DCache.scala 343:22]
- reg dirty_122; // @[L1DCache.scala 343:22]
- reg dirty_123; // @[L1DCache.scala 343:22]
- reg dirty_124; // @[L1DCache.scala 343:22]
- reg dirty_125; // @[L1DCache.scala 343:22]
- reg dirty_126; // @[L1DCache.scala 343:22]
- reg dirty_127; // @[L1DCache.scala 343:22]
- reg dirty_128; // @[L1DCache.scala 343:22]
- reg dirty_129; // @[L1DCache.scala 343:22]
- reg dirty_130; // @[L1DCache.scala 343:22]
- reg dirty_131; // @[L1DCache.scala 343:22]
- reg dirty_132; // @[L1DCache.scala 343:22]
- reg dirty_133; // @[L1DCache.scala 343:22]
- reg dirty_134; // @[L1DCache.scala 343:22]
- reg dirty_135; // @[L1DCache.scala 343:22]
- reg dirty_136; // @[L1DCache.scala 343:22]
- reg dirty_137; // @[L1DCache.scala 343:22]
- reg dirty_138; // @[L1DCache.scala 343:22]
- reg dirty_139; // @[L1DCache.scala 343:22]
- reg dirty_140; // @[L1DCache.scala 343:22]
- reg dirty_141; // @[L1DCache.scala 343:22]
- reg dirty_142; // @[L1DCache.scala 343:22]
- reg dirty_143; // @[L1DCache.scala 343:22]
- reg dirty_144; // @[L1DCache.scala 343:22]
- reg dirty_145; // @[L1DCache.scala 343:22]
- reg dirty_146; // @[L1DCache.scala 343:22]
- reg dirty_147; // @[L1DCache.scala 343:22]
- reg dirty_148; // @[L1DCache.scala 343:22]
- reg dirty_149; // @[L1DCache.scala 343:22]
- reg dirty_150; // @[L1DCache.scala 343:22]
- reg dirty_151; // @[L1DCache.scala 343:22]
- reg dirty_152; // @[L1DCache.scala 343:22]
- reg dirty_153; // @[L1DCache.scala 343:22]
- reg dirty_154; // @[L1DCache.scala 343:22]
- reg dirty_155; // @[L1DCache.scala 343:22]
- reg dirty_156; // @[L1DCache.scala 343:22]
- reg dirty_157; // @[L1DCache.scala 343:22]
- reg dirty_158; // @[L1DCache.scala 343:22]
- reg dirty_159; // @[L1DCache.scala 343:22]
- reg dirty_160; // @[L1DCache.scala 343:22]
- reg dirty_161; // @[L1DCache.scala 343:22]
- reg dirty_162; // @[L1DCache.scala 343:22]
- reg dirty_163; // @[L1DCache.scala 343:22]
- reg dirty_164; // @[L1DCache.scala 343:22]
- reg dirty_165; // @[L1DCache.scala 343:22]
- reg dirty_166; // @[L1DCache.scala 343:22]
- reg dirty_167; // @[L1DCache.scala 343:22]
- reg dirty_168; // @[L1DCache.scala 343:22]
- reg dirty_169; // @[L1DCache.scala 343:22]
- reg dirty_170; // @[L1DCache.scala 343:22]
- reg dirty_171; // @[L1DCache.scala 343:22]
- reg dirty_172; // @[L1DCache.scala 343:22]
- reg dirty_173; // @[L1DCache.scala 343:22]
- reg dirty_174; // @[L1DCache.scala 343:22]
- reg dirty_175; // @[L1DCache.scala 343:22]
- reg dirty_176; // @[L1DCache.scala 343:22]
- reg dirty_177; // @[L1DCache.scala 343:22]
- reg dirty_178; // @[L1DCache.scala 343:22]
- reg dirty_179; // @[L1DCache.scala 343:22]
- reg dirty_180; // @[L1DCache.scala 343:22]
- reg dirty_181; // @[L1DCache.scala 343:22]
- reg dirty_182; // @[L1DCache.scala 343:22]
- reg dirty_183; // @[L1DCache.scala 343:22]
- reg dirty_184; // @[L1DCache.scala 343:22]
- reg dirty_185; // @[L1DCache.scala 343:22]
- reg dirty_186; // @[L1DCache.scala 343:22]
- reg dirty_187; // @[L1DCache.scala 343:22]
- reg dirty_188; // @[L1DCache.scala 343:22]
- reg dirty_189; // @[L1DCache.scala 343:22]
- reg dirty_190; // @[L1DCache.scala 343:22]
- reg dirty_191; // @[L1DCache.scala 343:22]
- reg dirty_192; // @[L1DCache.scala 343:22]
- reg dirty_193; // @[L1DCache.scala 343:22]
- reg dirty_194; // @[L1DCache.scala 343:22]
- reg dirty_195; // @[L1DCache.scala 343:22]
- reg dirty_196; // @[L1DCache.scala 343:22]
- reg dirty_197; // @[L1DCache.scala 343:22]
- reg dirty_198; // @[L1DCache.scala 343:22]
- reg dirty_199; // @[L1DCache.scala 343:22]
- reg dirty_200; // @[L1DCache.scala 343:22]
- reg dirty_201; // @[L1DCache.scala 343:22]
- reg dirty_202; // @[L1DCache.scala 343:22]
- reg dirty_203; // @[L1DCache.scala 343:22]
- reg dirty_204; // @[L1DCache.scala 343:22]
- reg dirty_205; // @[L1DCache.scala 343:22]
- reg dirty_206; // @[L1DCache.scala 343:22]
- reg dirty_207; // @[L1DCache.scala 343:22]
- reg dirty_208; // @[L1DCache.scala 343:22]
- reg dirty_209; // @[L1DCache.scala 343:22]
- reg dirty_210; // @[L1DCache.scala 343:22]
- reg dirty_211; // @[L1DCache.scala 343:22]
- reg dirty_212; // @[L1DCache.scala 343:22]
- reg dirty_213; // @[L1DCache.scala 343:22]
- reg dirty_214; // @[L1DCache.scala 343:22]
- reg dirty_215; // @[L1DCache.scala 343:22]
- reg dirty_216; // @[L1DCache.scala 343:22]
- reg dirty_217; // @[L1DCache.scala 343:22]
- reg dirty_218; // @[L1DCache.scala 343:22]
- reg dirty_219; // @[L1DCache.scala 343:22]
- reg dirty_220; // @[L1DCache.scala 343:22]
- reg dirty_221; // @[L1DCache.scala 343:22]
- reg dirty_222; // @[L1DCache.scala 343:22]
- reg dirty_223; // @[L1DCache.scala 343:22]
- reg dirty_224; // @[L1DCache.scala 343:22]
- reg dirty_225; // @[L1DCache.scala 343:22]
- reg dirty_226; // @[L1DCache.scala 343:22]
- reg dirty_227; // @[L1DCache.scala 343:22]
- reg dirty_228; // @[L1DCache.scala 343:22]
- reg dirty_229; // @[L1DCache.scala 343:22]
- reg dirty_230; // @[L1DCache.scala 343:22]
- reg dirty_231; // @[L1DCache.scala 343:22]
- reg dirty_232; // @[L1DCache.scala 343:22]
- reg dirty_233; // @[L1DCache.scala 343:22]
- reg dirty_234; // @[L1DCache.scala 343:22]
- reg dirty_235; // @[L1DCache.scala 343:22]
- reg dirty_236; // @[L1DCache.scala 343:22]
- reg dirty_237; // @[L1DCache.scala 343:22]
- reg dirty_238; // @[L1DCache.scala 343:22]
- reg dirty_239; // @[L1DCache.scala 343:22]
- reg dirty_240; // @[L1DCache.scala 343:22]
- reg dirty_241; // @[L1DCache.scala 343:22]
- reg dirty_242; // @[L1DCache.scala 343:22]
- reg dirty_243; // @[L1DCache.scala 343:22]
- reg dirty_244; // @[L1DCache.scala 343:22]
- reg dirty_245; // @[L1DCache.scala 343:22]
- reg dirty_246; // @[L1DCache.scala 343:22]
- reg dirty_247; // @[L1DCache.scala 343:22]
- reg dirty_248; // @[L1DCache.scala 343:22]
- reg dirty_249; // @[L1DCache.scala 343:22]
- reg dirty_250; // @[L1DCache.scala 343:22]
- reg dirty_251; // @[L1DCache.scala 343:22]
- reg dirty_252; // @[L1DCache.scala 343:22]
- reg dirty_253; // @[L1DCache.scala 343:22]
- reg dirty_254; // @[L1DCache.scala 343:22]
- reg dirty_255; // @[L1DCache.scala 343:22]
- reg [31:0] camaddr_0; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_1; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_2; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_3; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_4; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_5; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_6; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_7; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_8; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_9; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_10; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_11; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_12; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_13; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_14; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_15; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_16; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_17; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_18; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_19; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_20; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_21; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_22; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_23; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_24; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_25; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_26; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_27; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_28; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_29; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_30; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_31; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_32; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_33; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_34; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_35; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_36; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_37; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_38; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_39; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_40; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_41; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_42; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_43; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_44; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_45; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_46; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_47; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_48; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_49; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_50; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_51; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_52; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_53; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_54; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_55; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_56; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_57; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_58; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_59; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_60; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_61; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_62; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_63; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_64; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_65; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_66; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_67; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_68; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_69; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_70; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_71; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_72; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_73; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_74; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_75; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_76; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_77; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_78; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_79; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_80; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_81; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_82; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_83; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_84; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_85; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_86; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_87; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_88; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_89; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_90; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_91; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_92; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_93; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_94; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_95; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_96; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_97; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_98; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_99; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_100; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_101; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_102; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_103; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_104; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_105; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_106; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_107; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_108; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_109; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_110; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_111; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_112; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_113; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_114; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_115; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_116; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_117; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_118; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_119; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_120; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_121; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_122; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_123; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_124; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_125; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_126; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_127; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_128; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_129; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_130; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_131; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_132; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_133; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_134; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_135; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_136; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_137; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_138; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_139; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_140; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_141; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_142; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_143; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_144; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_145; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_146; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_147; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_148; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_149; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_150; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_151; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_152; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_153; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_154; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_155; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_156; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_157; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_158; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_159; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_160; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_161; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_162; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_163; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_164; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_165; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_166; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_167; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_168; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_169; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_170; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_171; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_172; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_173; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_174; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_175; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_176; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_177; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_178; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_179; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_180; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_181; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_182; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_183; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_184; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_185; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_186; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_187; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_188; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_189; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_190; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_191; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_192; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_193; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_194; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_195; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_196; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_197; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_198; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_199; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_200; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_201; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_202; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_203; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_204; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_205; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_206; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_207; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_208; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_209; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_210; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_211; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_212; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_213; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_214; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_215; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_216; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_217; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_218; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_219; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_220; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_221; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_222; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_223; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_224; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_225; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_226; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_227; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_228; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_229; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_230; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_231; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_232; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_233; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_234; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_235; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_236; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_237; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_238; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_239; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_240; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_241; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_242; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_243; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_244; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_245; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_246; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_247; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_248; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_249; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_250; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_251; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_252; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_253; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_254; // @[L1DCache.scala 344:20]
- reg [31:0] camaddr_255; // @[L1DCache.scala 344:20]
- reg [1:0] history_0_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_0_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_0_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_0_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_1_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_1_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_1_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_1_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_2_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_2_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_2_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_2_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_3_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_3_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_3_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_3_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_4_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_4_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_4_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_4_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_5_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_5_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_5_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_5_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_6_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_6_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_6_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_6_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_7_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_7_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_7_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_7_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_8_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_8_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_8_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_8_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_9_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_9_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_9_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_9_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_10_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_10_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_10_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_10_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_11_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_11_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_11_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_11_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_12_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_12_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_12_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_12_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_13_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_13_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_13_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_13_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_14_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_14_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_14_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_14_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_15_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_15_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_15_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_15_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_16_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_16_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_16_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_16_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_17_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_17_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_17_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_17_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_18_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_18_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_18_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_18_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_19_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_19_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_19_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_19_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_20_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_20_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_20_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_20_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_21_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_21_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_21_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_21_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_22_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_22_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_22_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_22_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_23_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_23_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_23_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_23_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_24_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_24_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_24_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_24_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_25_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_25_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_25_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_25_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_26_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_26_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_26_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_26_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_27_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_27_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_27_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_27_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_28_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_28_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_28_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_28_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_29_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_29_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_29_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_29_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_30_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_30_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_30_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_30_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_31_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_31_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_31_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_31_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_32_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_32_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_32_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_32_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_33_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_33_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_33_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_33_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_34_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_34_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_34_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_34_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_35_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_35_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_35_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_35_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_36_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_36_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_36_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_36_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_37_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_37_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_37_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_37_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_38_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_38_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_38_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_38_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_39_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_39_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_39_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_39_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_40_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_40_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_40_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_40_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_41_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_41_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_41_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_41_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_42_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_42_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_42_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_42_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_43_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_43_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_43_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_43_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_44_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_44_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_44_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_44_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_45_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_45_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_45_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_45_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_46_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_46_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_46_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_46_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_47_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_47_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_47_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_47_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_48_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_48_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_48_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_48_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_49_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_49_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_49_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_49_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_50_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_50_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_50_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_50_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_51_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_51_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_51_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_51_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_52_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_52_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_52_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_52_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_53_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_53_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_53_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_53_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_54_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_54_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_54_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_54_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_55_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_55_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_55_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_55_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_56_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_56_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_56_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_56_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_57_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_57_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_57_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_57_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_58_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_58_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_58_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_58_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_59_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_59_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_59_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_59_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_60_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_60_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_60_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_60_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_61_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_61_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_61_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_61_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_62_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_62_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_62_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_62_3; // @[L1DCache.scala 347:20]
- reg [1:0] history_63_0; // @[L1DCache.scala 347:20]
- reg [1:0] history_63_1; // @[L1DCache.scala 347:20]
- reg [1:0] history_63_2; // @[L1DCache.scala 347:20]
- reg [1:0] history_63_3; // @[L1DCache.scala 347:20]
- wire setMatch_1 = io_dbus_addr[10:5] == 6'h0; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_127 = setMatch_1 ? camaddr_1 : 32'h0; // @[Library.scala 22:8]
- wire setMatch_5 = io_dbus_addr[10:5] == 6'h1; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_129 = setMatch_5 ? camaddr_5 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_130 = _ca_T_127 | _ca_T_129; // @[L1DCache.scala 360:36]
- wire setMatch_9 = io_dbus_addr[10:5] == 6'h2; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_131 = setMatch_9 ? camaddr_9 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_132 = _ca_T_130 | _ca_T_131; // @[L1DCache.scala 360:36]
- wire setMatch_13 = io_dbus_addr[10:5] == 6'h3; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_133 = setMatch_13 ? camaddr_13 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_134 = _ca_T_132 | _ca_T_133; // @[L1DCache.scala 360:36]
- wire setMatch_17 = io_dbus_addr[10:5] == 6'h4; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_135 = setMatch_17 ? camaddr_17 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_136 = _ca_T_134 | _ca_T_135; // @[L1DCache.scala 360:36]
- wire setMatch_21 = io_dbus_addr[10:5] == 6'h5; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_137 = setMatch_21 ? camaddr_21 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_138 = _ca_T_136 | _ca_T_137; // @[L1DCache.scala 360:36]
- wire setMatch_25 = io_dbus_addr[10:5] == 6'h6; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_139 = setMatch_25 ? camaddr_25 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_140 = _ca_T_138 | _ca_T_139; // @[L1DCache.scala 360:36]
- wire setMatch_29 = io_dbus_addr[10:5] == 6'h7; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_141 = setMatch_29 ? camaddr_29 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_142 = _ca_T_140 | _ca_T_141; // @[L1DCache.scala 360:36]
- wire setMatch_33 = io_dbus_addr[10:5] == 6'h8; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_143 = setMatch_33 ? camaddr_33 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_144 = _ca_T_142 | _ca_T_143; // @[L1DCache.scala 360:36]
- wire setMatch_37 = io_dbus_addr[10:5] == 6'h9; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_145 = setMatch_37 ? camaddr_37 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_146 = _ca_T_144 | _ca_T_145; // @[L1DCache.scala 360:36]
- wire setMatch_41 = io_dbus_addr[10:5] == 6'ha; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_147 = setMatch_41 ? camaddr_41 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_148 = _ca_T_146 | _ca_T_147; // @[L1DCache.scala 360:36]
- wire setMatch_45 = io_dbus_addr[10:5] == 6'hb; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_149 = setMatch_45 ? camaddr_45 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_150 = _ca_T_148 | _ca_T_149; // @[L1DCache.scala 360:36]
- wire setMatch_49 = io_dbus_addr[10:5] == 6'hc; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_151 = setMatch_49 ? camaddr_49 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_152 = _ca_T_150 | _ca_T_151; // @[L1DCache.scala 360:36]
- wire setMatch_53 = io_dbus_addr[10:5] == 6'hd; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_153 = setMatch_53 ? camaddr_53 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_154 = _ca_T_152 | _ca_T_153; // @[L1DCache.scala 360:36]
- wire setMatch_57 = io_dbus_addr[10:5] == 6'he; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_155 = setMatch_57 ? camaddr_57 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_156 = _ca_T_154 | _ca_T_155; // @[L1DCache.scala 360:36]
- wire setMatch_61 = io_dbus_addr[10:5] == 6'hf; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_157 = setMatch_61 ? camaddr_61 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_158 = _ca_T_156 | _ca_T_157; // @[L1DCache.scala 360:36]
- wire setMatch_65 = io_dbus_addr[10:5] == 6'h10; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_159 = setMatch_65 ? camaddr_65 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_160 = _ca_T_158 | _ca_T_159; // @[L1DCache.scala 360:36]
- wire setMatch_69 = io_dbus_addr[10:5] == 6'h11; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_161 = setMatch_69 ? camaddr_69 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_162 = _ca_T_160 | _ca_T_161; // @[L1DCache.scala 360:36]
- wire setMatch_73 = io_dbus_addr[10:5] == 6'h12; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_163 = setMatch_73 ? camaddr_73 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_164 = _ca_T_162 | _ca_T_163; // @[L1DCache.scala 360:36]
- wire setMatch_77 = io_dbus_addr[10:5] == 6'h13; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_165 = setMatch_77 ? camaddr_77 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_166 = _ca_T_164 | _ca_T_165; // @[L1DCache.scala 360:36]
- wire setMatch_81 = io_dbus_addr[10:5] == 6'h14; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_167 = setMatch_81 ? camaddr_81 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_168 = _ca_T_166 | _ca_T_167; // @[L1DCache.scala 360:36]
- wire setMatch_85 = io_dbus_addr[10:5] == 6'h15; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_169 = setMatch_85 ? camaddr_85 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_170 = _ca_T_168 | _ca_T_169; // @[L1DCache.scala 360:36]
- wire setMatch_89 = io_dbus_addr[10:5] == 6'h16; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_171 = setMatch_89 ? camaddr_89 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_172 = _ca_T_170 | _ca_T_171; // @[L1DCache.scala 360:36]
- wire setMatch_93 = io_dbus_addr[10:5] == 6'h17; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_173 = setMatch_93 ? camaddr_93 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_174 = _ca_T_172 | _ca_T_173; // @[L1DCache.scala 360:36]
- wire setMatch_97 = io_dbus_addr[10:5] == 6'h18; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_175 = setMatch_97 ? camaddr_97 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_176 = _ca_T_174 | _ca_T_175; // @[L1DCache.scala 360:36]
- wire setMatch_101 = io_dbus_addr[10:5] == 6'h19; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_177 = setMatch_101 ? camaddr_101 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_178 = _ca_T_176 | _ca_T_177; // @[L1DCache.scala 360:36]
- wire setMatch_105 = io_dbus_addr[10:5] == 6'h1a; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_179 = setMatch_105 ? camaddr_105 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_180 = _ca_T_178 | _ca_T_179; // @[L1DCache.scala 360:36]
- wire setMatch_109 = io_dbus_addr[10:5] == 6'h1b; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_181 = setMatch_109 ? camaddr_109 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_182 = _ca_T_180 | _ca_T_181; // @[L1DCache.scala 360:36]
- wire setMatch_113 = io_dbus_addr[10:5] == 6'h1c; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_183 = setMatch_113 ? camaddr_113 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_184 = _ca_T_182 | _ca_T_183; // @[L1DCache.scala 360:36]
- wire setMatch_117 = io_dbus_addr[10:5] == 6'h1d; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_185 = setMatch_117 ? camaddr_117 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_186 = _ca_T_184 | _ca_T_185; // @[L1DCache.scala 360:36]
- wire setMatch_121 = io_dbus_addr[10:5] == 6'h1e; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_187 = setMatch_121 ? camaddr_121 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_188 = _ca_T_186 | _ca_T_187; // @[L1DCache.scala 360:36]
- wire setMatch_125 = io_dbus_addr[10:5] == 6'h1f; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_189 = setMatch_125 ? camaddr_125 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_190 = _ca_T_188 | _ca_T_189; // @[L1DCache.scala 360:36]
- wire setMatch_129 = io_dbus_addr[10:5] == 6'h20; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_191 = setMatch_129 ? camaddr_129 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_192 = _ca_T_190 | _ca_T_191; // @[L1DCache.scala 360:36]
- wire setMatch_133 = io_dbus_addr[10:5] == 6'h21; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_193 = setMatch_133 ? camaddr_133 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_194 = _ca_T_192 | _ca_T_193; // @[L1DCache.scala 360:36]
- wire setMatch_137 = io_dbus_addr[10:5] == 6'h22; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_195 = setMatch_137 ? camaddr_137 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_196 = _ca_T_194 | _ca_T_195; // @[L1DCache.scala 360:36]
- wire setMatch_141 = io_dbus_addr[10:5] == 6'h23; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_197 = setMatch_141 ? camaddr_141 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_198 = _ca_T_196 | _ca_T_197; // @[L1DCache.scala 360:36]
- wire setMatch_145 = io_dbus_addr[10:5] == 6'h24; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_199 = setMatch_145 ? camaddr_145 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_200 = _ca_T_198 | _ca_T_199; // @[L1DCache.scala 360:36]
- wire setMatch_149 = io_dbus_addr[10:5] == 6'h25; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_201 = setMatch_149 ? camaddr_149 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_202 = _ca_T_200 | _ca_T_201; // @[L1DCache.scala 360:36]
- wire setMatch_153 = io_dbus_addr[10:5] == 6'h26; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_203 = setMatch_153 ? camaddr_153 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_204 = _ca_T_202 | _ca_T_203; // @[L1DCache.scala 360:36]
- wire setMatch_157 = io_dbus_addr[10:5] == 6'h27; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_205 = setMatch_157 ? camaddr_157 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_206 = _ca_T_204 | _ca_T_205; // @[L1DCache.scala 360:36]
- wire setMatch_161 = io_dbus_addr[10:5] == 6'h28; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_207 = setMatch_161 ? camaddr_161 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_208 = _ca_T_206 | _ca_T_207; // @[L1DCache.scala 360:36]
- wire setMatch_165 = io_dbus_addr[10:5] == 6'h29; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_209 = setMatch_165 ? camaddr_165 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_210 = _ca_T_208 | _ca_T_209; // @[L1DCache.scala 360:36]
- wire setMatch_169 = io_dbus_addr[10:5] == 6'h2a; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_211 = setMatch_169 ? camaddr_169 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_212 = _ca_T_210 | _ca_T_211; // @[L1DCache.scala 360:36]
- wire setMatch_173 = io_dbus_addr[10:5] == 6'h2b; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_213 = setMatch_173 ? camaddr_173 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_214 = _ca_T_212 | _ca_T_213; // @[L1DCache.scala 360:36]
- wire setMatch_177 = io_dbus_addr[10:5] == 6'h2c; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_215 = setMatch_177 ? camaddr_177 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_216 = _ca_T_214 | _ca_T_215; // @[L1DCache.scala 360:36]
- wire setMatch_181 = io_dbus_addr[10:5] == 6'h2d; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_217 = setMatch_181 ? camaddr_181 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_218 = _ca_T_216 | _ca_T_217; // @[L1DCache.scala 360:36]
- wire setMatch_185 = io_dbus_addr[10:5] == 6'h2e; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_219 = setMatch_185 ? camaddr_185 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_220 = _ca_T_218 | _ca_T_219; // @[L1DCache.scala 360:36]
- wire setMatch_189 = io_dbus_addr[10:5] == 6'h2f; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_221 = setMatch_189 ? camaddr_189 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_222 = _ca_T_220 | _ca_T_221; // @[L1DCache.scala 360:36]
- wire setMatch_193 = io_dbus_addr[10:5] == 6'h30; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_223 = setMatch_193 ? camaddr_193 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_224 = _ca_T_222 | _ca_T_223; // @[L1DCache.scala 360:36]
- wire setMatch_197 = io_dbus_addr[10:5] == 6'h31; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_225 = setMatch_197 ? camaddr_197 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_226 = _ca_T_224 | _ca_T_225; // @[L1DCache.scala 360:36]
- wire setMatch_201 = io_dbus_addr[10:5] == 6'h32; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_227 = setMatch_201 ? camaddr_201 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_228 = _ca_T_226 | _ca_T_227; // @[L1DCache.scala 360:36]
- wire setMatch_205 = io_dbus_addr[10:5] == 6'h33; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_229 = setMatch_205 ? camaddr_205 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_230 = _ca_T_228 | _ca_T_229; // @[L1DCache.scala 360:36]
- wire setMatch_209 = io_dbus_addr[10:5] == 6'h34; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_231 = setMatch_209 ? camaddr_209 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_232 = _ca_T_230 | _ca_T_231; // @[L1DCache.scala 360:36]
- wire setMatch_213 = io_dbus_addr[10:5] == 6'h35; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_233 = setMatch_213 ? camaddr_213 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_234 = _ca_T_232 | _ca_T_233; // @[L1DCache.scala 360:36]
- wire setMatch_217 = io_dbus_addr[10:5] == 6'h36; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_235 = setMatch_217 ? camaddr_217 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_236 = _ca_T_234 | _ca_T_235; // @[L1DCache.scala 360:36]
- wire setMatch_221 = io_dbus_addr[10:5] == 6'h37; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_237 = setMatch_221 ? camaddr_221 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_238 = _ca_T_236 | _ca_T_237; // @[L1DCache.scala 360:36]
- wire setMatch_225 = io_dbus_addr[10:5] == 6'h38; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_239 = setMatch_225 ? camaddr_225 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_240 = _ca_T_238 | _ca_T_239; // @[L1DCache.scala 360:36]
- wire setMatch_229 = io_dbus_addr[10:5] == 6'h39; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_241 = setMatch_229 ? camaddr_229 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_242 = _ca_T_240 | _ca_T_241; // @[L1DCache.scala 360:36]
- wire setMatch_233 = io_dbus_addr[10:5] == 6'h3a; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_243 = setMatch_233 ? camaddr_233 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_244 = _ca_T_242 | _ca_T_243; // @[L1DCache.scala 360:36]
- wire setMatch_237 = io_dbus_addr[10:5] == 6'h3b; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_245 = setMatch_237 ? camaddr_237 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_246 = _ca_T_244 | _ca_T_245; // @[L1DCache.scala 360:36]
- wire setMatch_241 = io_dbus_addr[10:5] == 6'h3c; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_247 = setMatch_241 ? camaddr_241 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_248 = _ca_T_246 | _ca_T_247; // @[L1DCache.scala 360:36]
- wire setMatch_245 = io_dbus_addr[10:5] == 6'h3d; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_249 = setMatch_245 ? camaddr_245 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_250 = _ca_T_248 | _ca_T_249; // @[L1DCache.scala 360:36]
- wire setMatch_249 = io_dbus_addr[10:5] == 6'h3e; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_251 = setMatch_249 ? camaddr_249 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_252 = _ca_T_250 | _ca_T_251; // @[L1DCache.scala 360:36]
- wire setMatch_253 = io_dbus_addr[10:5] == 6'h3f; // @[L1DCache.scala 373:81]
- wire [31:0] _ca_T_253 = setMatch_253 ? camaddr_253 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] ca_1 = _ca_T_252 | _ca_T_253; // @[L1DCache.scala 360:36]
- wire matchAddr_1 = io_dbus_addr[30:11] == ca_1[30:11]; // @[L1DCache.scala 368:50]
- wire matchSlotB_1 = valid_1 & setMatch_1 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire [31:0] _ca_T = setMatch_1 ? camaddr_0 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_2 = setMatch_5 ? camaddr_4 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_3 = _ca_T | _ca_T_2; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_4 = setMatch_9 ? camaddr_8 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_5 = _ca_T_3 | _ca_T_4; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_6 = setMatch_13 ? camaddr_12 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_7 = _ca_T_5 | _ca_T_6; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_8 = setMatch_17 ? camaddr_16 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_9 = _ca_T_7 | _ca_T_8; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_10 = setMatch_21 ? camaddr_20 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_11 = _ca_T_9 | _ca_T_10; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_12 = setMatch_25 ? camaddr_24 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_13 = _ca_T_11 | _ca_T_12; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_14 = setMatch_29 ? camaddr_28 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_15 = _ca_T_13 | _ca_T_14; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_16 = setMatch_33 ? camaddr_32 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_17 = _ca_T_15 | _ca_T_16; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_18 = setMatch_37 ? camaddr_36 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_19 = _ca_T_17 | _ca_T_18; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_20 = setMatch_41 ? camaddr_40 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_21 = _ca_T_19 | _ca_T_20; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_22 = setMatch_45 ? camaddr_44 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_23 = _ca_T_21 | _ca_T_22; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_24 = setMatch_49 ? camaddr_48 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_25 = _ca_T_23 | _ca_T_24; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_26 = setMatch_53 ? camaddr_52 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_27 = _ca_T_25 | _ca_T_26; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_28 = setMatch_57 ? camaddr_56 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_29 = _ca_T_27 | _ca_T_28; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_30 = setMatch_61 ? camaddr_60 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_31 = _ca_T_29 | _ca_T_30; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_32 = setMatch_65 ? camaddr_64 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_33 = _ca_T_31 | _ca_T_32; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_34 = setMatch_69 ? camaddr_68 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_35 = _ca_T_33 | _ca_T_34; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_36 = setMatch_73 ? camaddr_72 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_37 = _ca_T_35 | _ca_T_36; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_38 = setMatch_77 ? camaddr_76 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_39 = _ca_T_37 | _ca_T_38; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_40 = setMatch_81 ? camaddr_80 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_41 = _ca_T_39 | _ca_T_40; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_42 = setMatch_85 ? camaddr_84 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_43 = _ca_T_41 | _ca_T_42; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_44 = setMatch_89 ? camaddr_88 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_45 = _ca_T_43 | _ca_T_44; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_46 = setMatch_93 ? camaddr_92 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_47 = _ca_T_45 | _ca_T_46; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_48 = setMatch_97 ? camaddr_96 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_49 = _ca_T_47 | _ca_T_48; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_50 = setMatch_101 ? camaddr_100 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_51 = _ca_T_49 | _ca_T_50; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_52 = setMatch_105 ? camaddr_104 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_53 = _ca_T_51 | _ca_T_52; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_54 = setMatch_109 ? camaddr_108 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_55 = _ca_T_53 | _ca_T_54; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_56 = setMatch_113 ? camaddr_112 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_57 = _ca_T_55 | _ca_T_56; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_58 = setMatch_117 ? camaddr_116 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_59 = _ca_T_57 | _ca_T_58; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_60 = setMatch_121 ? camaddr_120 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_61 = _ca_T_59 | _ca_T_60; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_62 = setMatch_125 ? camaddr_124 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_63 = _ca_T_61 | _ca_T_62; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_64 = setMatch_129 ? camaddr_128 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_65 = _ca_T_63 | _ca_T_64; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_66 = setMatch_133 ? camaddr_132 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_67 = _ca_T_65 | _ca_T_66; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_68 = setMatch_137 ? camaddr_136 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_69 = _ca_T_67 | _ca_T_68; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_70 = setMatch_141 ? camaddr_140 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_71 = _ca_T_69 | _ca_T_70; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_72 = setMatch_145 ? camaddr_144 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_73 = _ca_T_71 | _ca_T_72; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_74 = setMatch_149 ? camaddr_148 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_75 = _ca_T_73 | _ca_T_74; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_76 = setMatch_153 ? camaddr_152 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_77 = _ca_T_75 | _ca_T_76; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_78 = setMatch_157 ? camaddr_156 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_79 = _ca_T_77 | _ca_T_78; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_80 = setMatch_161 ? camaddr_160 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_81 = _ca_T_79 | _ca_T_80; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_82 = setMatch_165 ? camaddr_164 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_83 = _ca_T_81 | _ca_T_82; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_84 = setMatch_169 ? camaddr_168 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_85 = _ca_T_83 | _ca_T_84; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_86 = setMatch_173 ? camaddr_172 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_87 = _ca_T_85 | _ca_T_86; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_88 = setMatch_177 ? camaddr_176 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_89 = _ca_T_87 | _ca_T_88; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_90 = setMatch_181 ? camaddr_180 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_91 = _ca_T_89 | _ca_T_90; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_92 = setMatch_185 ? camaddr_184 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_93 = _ca_T_91 | _ca_T_92; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_94 = setMatch_189 ? camaddr_188 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_95 = _ca_T_93 | _ca_T_94; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_96 = setMatch_193 ? camaddr_192 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_97 = _ca_T_95 | _ca_T_96; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_98 = setMatch_197 ? camaddr_196 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_99 = _ca_T_97 | _ca_T_98; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_100 = setMatch_201 ? camaddr_200 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_101 = _ca_T_99 | _ca_T_100; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_102 = setMatch_205 ? camaddr_204 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_103 = _ca_T_101 | _ca_T_102; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_104 = setMatch_209 ? camaddr_208 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_105 = _ca_T_103 | _ca_T_104; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_106 = setMatch_213 ? camaddr_212 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_107 = _ca_T_105 | _ca_T_106; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_108 = setMatch_217 ? camaddr_216 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_109 = _ca_T_107 | _ca_T_108; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_110 = setMatch_221 ? camaddr_220 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_111 = _ca_T_109 | _ca_T_110; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_112 = setMatch_225 ? camaddr_224 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_113 = _ca_T_111 | _ca_T_112; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_114 = setMatch_229 ? camaddr_228 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_115 = _ca_T_113 | _ca_T_114; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_116 = setMatch_233 ? camaddr_232 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_117 = _ca_T_115 | _ca_T_116; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_118 = setMatch_237 ? camaddr_236 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_119 = _ca_T_117 | _ca_T_118; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_120 = setMatch_241 ? camaddr_240 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_121 = _ca_T_119 | _ca_T_120; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_122 = setMatch_245 ? camaddr_244 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_123 = _ca_T_121 | _ca_T_122; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_124 = setMatch_249 ? camaddr_248 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_125 = _ca_T_123 | _ca_T_124; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_126 = setMatch_253 ? camaddr_252 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] ca = _ca_T_125 | _ca_T_126; // @[L1DCache.scala 360:36]
- wire matchAddr_0 = io_dbus_addr[30:11] == ca[30:11]; // @[L1DCache.scala 368:50]
- wire matchSlotB_0 = valid_0 & setMatch_1 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire [31:0] _ca_T_381 = setMatch_1 ? camaddr_3 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_383 = setMatch_5 ? camaddr_7 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_384 = _ca_T_381 | _ca_T_383; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_385 = setMatch_9 ? camaddr_11 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_386 = _ca_T_384 | _ca_T_385; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_387 = setMatch_13 ? camaddr_15 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_388 = _ca_T_386 | _ca_T_387; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_389 = setMatch_17 ? camaddr_19 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_390 = _ca_T_388 | _ca_T_389; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_391 = setMatch_21 ? camaddr_23 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_392 = _ca_T_390 | _ca_T_391; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_393 = setMatch_25 ? camaddr_27 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_394 = _ca_T_392 | _ca_T_393; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_395 = setMatch_29 ? camaddr_31 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_396 = _ca_T_394 | _ca_T_395; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_397 = setMatch_33 ? camaddr_35 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_398 = _ca_T_396 | _ca_T_397; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_399 = setMatch_37 ? camaddr_39 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_400 = _ca_T_398 | _ca_T_399; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_401 = setMatch_41 ? camaddr_43 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_402 = _ca_T_400 | _ca_T_401; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_403 = setMatch_45 ? camaddr_47 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_404 = _ca_T_402 | _ca_T_403; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_405 = setMatch_49 ? camaddr_51 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_406 = _ca_T_404 | _ca_T_405; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_407 = setMatch_53 ? camaddr_55 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_408 = _ca_T_406 | _ca_T_407; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_409 = setMatch_57 ? camaddr_59 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_410 = _ca_T_408 | _ca_T_409; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_411 = setMatch_61 ? camaddr_63 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_412 = _ca_T_410 | _ca_T_411; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_413 = setMatch_65 ? camaddr_67 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_414 = _ca_T_412 | _ca_T_413; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_415 = setMatch_69 ? camaddr_71 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_416 = _ca_T_414 | _ca_T_415; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_417 = setMatch_73 ? camaddr_75 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_418 = _ca_T_416 | _ca_T_417; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_419 = setMatch_77 ? camaddr_79 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_420 = _ca_T_418 | _ca_T_419; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_421 = setMatch_81 ? camaddr_83 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_422 = _ca_T_420 | _ca_T_421; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_423 = setMatch_85 ? camaddr_87 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_424 = _ca_T_422 | _ca_T_423; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_425 = setMatch_89 ? camaddr_91 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_426 = _ca_T_424 | _ca_T_425; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_427 = setMatch_93 ? camaddr_95 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_428 = _ca_T_426 | _ca_T_427; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_429 = setMatch_97 ? camaddr_99 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_430 = _ca_T_428 | _ca_T_429; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_431 = setMatch_101 ? camaddr_103 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_432 = _ca_T_430 | _ca_T_431; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_433 = setMatch_105 ? camaddr_107 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_434 = _ca_T_432 | _ca_T_433; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_435 = setMatch_109 ? camaddr_111 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_436 = _ca_T_434 | _ca_T_435; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_437 = setMatch_113 ? camaddr_115 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_438 = _ca_T_436 | _ca_T_437; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_439 = setMatch_117 ? camaddr_119 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_440 = _ca_T_438 | _ca_T_439; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_441 = setMatch_121 ? camaddr_123 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_442 = _ca_T_440 | _ca_T_441; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_443 = setMatch_125 ? camaddr_127 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_444 = _ca_T_442 | _ca_T_443; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_445 = setMatch_129 ? camaddr_131 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_446 = _ca_T_444 | _ca_T_445; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_447 = setMatch_133 ? camaddr_135 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_448 = _ca_T_446 | _ca_T_447; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_449 = setMatch_137 ? camaddr_139 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_450 = _ca_T_448 | _ca_T_449; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_451 = setMatch_141 ? camaddr_143 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_452 = _ca_T_450 | _ca_T_451; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_453 = setMatch_145 ? camaddr_147 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_454 = _ca_T_452 | _ca_T_453; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_455 = setMatch_149 ? camaddr_151 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_456 = _ca_T_454 | _ca_T_455; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_457 = setMatch_153 ? camaddr_155 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_458 = _ca_T_456 | _ca_T_457; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_459 = setMatch_157 ? camaddr_159 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_460 = _ca_T_458 | _ca_T_459; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_461 = setMatch_161 ? camaddr_163 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_462 = _ca_T_460 | _ca_T_461; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_463 = setMatch_165 ? camaddr_167 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_464 = _ca_T_462 | _ca_T_463; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_465 = setMatch_169 ? camaddr_171 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_466 = _ca_T_464 | _ca_T_465; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_467 = setMatch_173 ? camaddr_175 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_468 = _ca_T_466 | _ca_T_467; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_469 = setMatch_177 ? camaddr_179 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_470 = _ca_T_468 | _ca_T_469; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_471 = setMatch_181 ? camaddr_183 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_472 = _ca_T_470 | _ca_T_471; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_473 = setMatch_185 ? camaddr_187 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_474 = _ca_T_472 | _ca_T_473; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_475 = setMatch_189 ? camaddr_191 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_476 = _ca_T_474 | _ca_T_475; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_477 = setMatch_193 ? camaddr_195 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_478 = _ca_T_476 | _ca_T_477; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_479 = setMatch_197 ? camaddr_199 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_480 = _ca_T_478 | _ca_T_479; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_481 = setMatch_201 ? camaddr_203 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_482 = _ca_T_480 | _ca_T_481; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_483 = setMatch_205 ? camaddr_207 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_484 = _ca_T_482 | _ca_T_483; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_485 = setMatch_209 ? camaddr_211 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_486 = _ca_T_484 | _ca_T_485; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_487 = setMatch_213 ? camaddr_215 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_488 = _ca_T_486 | _ca_T_487; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_489 = setMatch_217 ? camaddr_219 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_490 = _ca_T_488 | _ca_T_489; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_491 = setMatch_221 ? camaddr_223 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_492 = _ca_T_490 | _ca_T_491; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_493 = setMatch_225 ? camaddr_227 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_494 = _ca_T_492 | _ca_T_493; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_495 = setMatch_229 ? camaddr_231 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_496 = _ca_T_494 | _ca_T_495; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_497 = setMatch_233 ? camaddr_235 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_498 = _ca_T_496 | _ca_T_497; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_499 = setMatch_237 ? camaddr_239 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_500 = _ca_T_498 | _ca_T_499; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_501 = setMatch_241 ? camaddr_243 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_502 = _ca_T_500 | _ca_T_501; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_503 = setMatch_245 ? camaddr_247 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_504 = _ca_T_502 | _ca_T_503; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_505 = setMatch_249 ? camaddr_251 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_506 = _ca_T_504 | _ca_T_505; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_507 = setMatch_253 ? camaddr_255 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] ca_3 = _ca_T_506 | _ca_T_507; // @[L1DCache.scala 360:36]
- wire matchAddr_3 = io_dbus_addr[30:11] == ca_3[30:11]; // @[L1DCache.scala 368:50]
- wire matchSlotB_3 = valid_3 & setMatch_1 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire [31:0] _ca_T_254 = setMatch_1 ? camaddr_2 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_256 = setMatch_5 ? camaddr_6 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_257 = _ca_T_254 | _ca_T_256; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_258 = setMatch_9 ? camaddr_10 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_259 = _ca_T_257 | _ca_T_258; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_260 = setMatch_13 ? camaddr_14 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_261 = _ca_T_259 | _ca_T_260; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_262 = setMatch_17 ? camaddr_18 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_263 = _ca_T_261 | _ca_T_262; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_264 = setMatch_21 ? camaddr_22 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_265 = _ca_T_263 | _ca_T_264; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_266 = setMatch_25 ? camaddr_26 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_267 = _ca_T_265 | _ca_T_266; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_268 = setMatch_29 ? camaddr_30 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_269 = _ca_T_267 | _ca_T_268; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_270 = setMatch_33 ? camaddr_34 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_271 = _ca_T_269 | _ca_T_270; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_272 = setMatch_37 ? camaddr_38 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_273 = _ca_T_271 | _ca_T_272; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_274 = setMatch_41 ? camaddr_42 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_275 = _ca_T_273 | _ca_T_274; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_276 = setMatch_45 ? camaddr_46 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_277 = _ca_T_275 | _ca_T_276; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_278 = setMatch_49 ? camaddr_50 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_279 = _ca_T_277 | _ca_T_278; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_280 = setMatch_53 ? camaddr_54 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_281 = _ca_T_279 | _ca_T_280; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_282 = setMatch_57 ? camaddr_58 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_283 = _ca_T_281 | _ca_T_282; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_284 = setMatch_61 ? camaddr_62 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_285 = _ca_T_283 | _ca_T_284; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_286 = setMatch_65 ? camaddr_66 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_287 = _ca_T_285 | _ca_T_286; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_288 = setMatch_69 ? camaddr_70 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_289 = _ca_T_287 | _ca_T_288; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_290 = setMatch_73 ? camaddr_74 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_291 = _ca_T_289 | _ca_T_290; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_292 = setMatch_77 ? camaddr_78 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_293 = _ca_T_291 | _ca_T_292; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_294 = setMatch_81 ? camaddr_82 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_295 = _ca_T_293 | _ca_T_294; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_296 = setMatch_85 ? camaddr_86 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_297 = _ca_T_295 | _ca_T_296; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_298 = setMatch_89 ? camaddr_90 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_299 = _ca_T_297 | _ca_T_298; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_300 = setMatch_93 ? camaddr_94 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_301 = _ca_T_299 | _ca_T_300; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_302 = setMatch_97 ? camaddr_98 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_303 = _ca_T_301 | _ca_T_302; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_304 = setMatch_101 ? camaddr_102 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_305 = _ca_T_303 | _ca_T_304; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_306 = setMatch_105 ? camaddr_106 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_307 = _ca_T_305 | _ca_T_306; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_308 = setMatch_109 ? camaddr_110 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_309 = _ca_T_307 | _ca_T_308; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_310 = setMatch_113 ? camaddr_114 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_311 = _ca_T_309 | _ca_T_310; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_312 = setMatch_117 ? camaddr_118 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_313 = _ca_T_311 | _ca_T_312; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_314 = setMatch_121 ? camaddr_122 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_315 = _ca_T_313 | _ca_T_314; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_316 = setMatch_125 ? camaddr_126 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_317 = _ca_T_315 | _ca_T_316; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_318 = setMatch_129 ? camaddr_130 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_319 = _ca_T_317 | _ca_T_318; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_320 = setMatch_133 ? camaddr_134 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_321 = _ca_T_319 | _ca_T_320; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_322 = setMatch_137 ? camaddr_138 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_323 = _ca_T_321 | _ca_T_322; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_324 = setMatch_141 ? camaddr_142 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_325 = _ca_T_323 | _ca_T_324; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_326 = setMatch_145 ? camaddr_146 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_327 = _ca_T_325 | _ca_T_326; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_328 = setMatch_149 ? camaddr_150 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_329 = _ca_T_327 | _ca_T_328; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_330 = setMatch_153 ? camaddr_154 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_331 = _ca_T_329 | _ca_T_330; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_332 = setMatch_157 ? camaddr_158 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_333 = _ca_T_331 | _ca_T_332; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_334 = setMatch_161 ? camaddr_162 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_335 = _ca_T_333 | _ca_T_334; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_336 = setMatch_165 ? camaddr_166 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_337 = _ca_T_335 | _ca_T_336; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_338 = setMatch_169 ? camaddr_170 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_339 = _ca_T_337 | _ca_T_338; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_340 = setMatch_173 ? camaddr_174 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_341 = _ca_T_339 | _ca_T_340; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_342 = setMatch_177 ? camaddr_178 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_343 = _ca_T_341 | _ca_T_342; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_344 = setMatch_181 ? camaddr_182 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_345 = _ca_T_343 | _ca_T_344; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_346 = setMatch_185 ? camaddr_186 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_347 = _ca_T_345 | _ca_T_346; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_348 = setMatch_189 ? camaddr_190 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_349 = _ca_T_347 | _ca_T_348; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_350 = setMatch_193 ? camaddr_194 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_351 = _ca_T_349 | _ca_T_350; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_352 = setMatch_197 ? camaddr_198 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_353 = _ca_T_351 | _ca_T_352; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_354 = setMatch_201 ? camaddr_202 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_355 = _ca_T_353 | _ca_T_354; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_356 = setMatch_205 ? camaddr_206 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_357 = _ca_T_355 | _ca_T_356; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_358 = setMatch_209 ? camaddr_210 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_359 = _ca_T_357 | _ca_T_358; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_360 = setMatch_213 ? camaddr_214 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_361 = _ca_T_359 | _ca_T_360; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_362 = setMatch_217 ? camaddr_218 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_363 = _ca_T_361 | _ca_T_362; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_364 = setMatch_221 ? camaddr_222 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_365 = _ca_T_363 | _ca_T_364; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_366 = setMatch_225 ? camaddr_226 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_367 = _ca_T_365 | _ca_T_366; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_368 = setMatch_229 ? camaddr_230 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_369 = _ca_T_367 | _ca_T_368; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_370 = setMatch_233 ? camaddr_234 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_371 = _ca_T_369 | _ca_T_370; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_372 = setMatch_237 ? camaddr_238 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_373 = _ca_T_371 | _ca_T_372; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_374 = setMatch_241 ? camaddr_242 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_375 = _ca_T_373 | _ca_T_374; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_376 = setMatch_245 ? camaddr_246 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_377 = _ca_T_375 | _ca_T_376; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_378 = setMatch_249 ? camaddr_250 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_379 = _ca_T_377 | _ca_T_378; // @[L1DCache.scala 360:36]
- wire [31:0] _ca_T_380 = setMatch_253 ? camaddr_254 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] ca_2 = _ca_T_379 | _ca_T_380; // @[L1DCache.scala 360:36]
- wire matchAddr_2 = io_dbus_addr[30:11] == ca_2[30:11]; // @[L1DCache.scala 368:50]
- wire matchSlotB_2 = valid_2 & setMatch_1 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_5 = valid_5 & setMatch_5 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_4 = valid_4 & setMatch_5 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_7 = valid_7 & setMatch_5 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_6 = valid_6 & setMatch_5 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_lo_lo_lo_lo_lo = {matchSlotB_7,matchSlotB_6,matchSlotB_5,matchSlotB_4,matchSlotB_3,matchSlotB_2,
- matchSlotB_1,matchSlotB_0}; // @[L1DCache.scala 353:30]
- wire matchSlotB_9 = valid_9 & setMatch_9 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_8 = valid_8 & setMatch_9 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_11 = valid_11 & setMatch_9 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_10 = valid_10 & setMatch_9 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_13 = valid_13 & setMatch_13 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_12 = valid_12 & setMatch_13 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_15 = valid_15 & setMatch_13 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_14 = valid_14 & setMatch_13 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [15:0] matchSlot_lo_lo_lo_lo = {matchSlotB_15,matchSlotB_14,matchSlotB_13,matchSlotB_12,matchSlotB_11,
- matchSlotB_10,matchSlotB_9,matchSlotB_8,matchSlot_lo_lo_lo_lo_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_17 = valid_17 & setMatch_17 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_16 = valid_16 & setMatch_17 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_19 = valid_19 & setMatch_17 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_18 = valid_18 & setMatch_17 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_21 = valid_21 & setMatch_21 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_20 = valid_20 & setMatch_21 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_23 = valid_23 & setMatch_21 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_22 = valid_22 & setMatch_21 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_lo_lo_lo_hi_lo = {matchSlotB_23,matchSlotB_22,matchSlotB_21,matchSlotB_20,matchSlotB_19,
- matchSlotB_18,matchSlotB_17,matchSlotB_16}; // @[L1DCache.scala 353:30]
- wire matchSlotB_25 = valid_25 & setMatch_25 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_24 = valid_24 & setMatch_25 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_27 = valid_27 & setMatch_25 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_26 = valid_26 & setMatch_25 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_29 = valid_29 & setMatch_29 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_28 = valid_28 & setMatch_29 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_31 = valid_31 & setMatch_29 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_30 = valid_30 & setMatch_29 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [31:0] matchSlot_lo_lo_lo = {matchSlotB_31,matchSlotB_30,matchSlotB_29,matchSlotB_28,matchSlotB_27,matchSlotB_26,
- matchSlotB_25,matchSlotB_24,matchSlot_lo_lo_lo_hi_lo,matchSlot_lo_lo_lo_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_33 = valid_33 & setMatch_33 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_32 = valid_32 & setMatch_33 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_35 = valid_35 & setMatch_33 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_34 = valid_34 & setMatch_33 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_37 = valid_37 & setMatch_37 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_36 = valid_36 & setMatch_37 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_39 = valid_39 & setMatch_37 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_38 = valid_38 & setMatch_37 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_lo_lo_hi_lo_lo = {matchSlotB_39,matchSlotB_38,matchSlotB_37,matchSlotB_36,matchSlotB_35,
- matchSlotB_34,matchSlotB_33,matchSlotB_32}; // @[L1DCache.scala 353:30]
- wire matchSlotB_41 = valid_41 & setMatch_41 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_40 = valid_40 & setMatch_41 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_43 = valid_43 & setMatch_41 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_42 = valid_42 & setMatch_41 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_45 = valid_45 & setMatch_45 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_44 = valid_44 & setMatch_45 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_47 = valid_47 & setMatch_45 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_46 = valid_46 & setMatch_45 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [15:0] matchSlot_lo_lo_hi_lo = {matchSlotB_47,matchSlotB_46,matchSlotB_45,matchSlotB_44,matchSlotB_43,
- matchSlotB_42,matchSlotB_41,matchSlotB_40,matchSlot_lo_lo_hi_lo_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_49 = valid_49 & setMatch_49 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_48 = valid_48 & setMatch_49 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_51 = valid_51 & setMatch_49 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_50 = valid_50 & setMatch_49 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_53 = valid_53 & setMatch_53 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_52 = valid_52 & setMatch_53 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_55 = valid_55 & setMatch_53 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_54 = valid_54 & setMatch_53 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_lo_lo_hi_hi_lo = {matchSlotB_55,matchSlotB_54,matchSlotB_53,matchSlotB_52,matchSlotB_51,
- matchSlotB_50,matchSlotB_49,matchSlotB_48}; // @[L1DCache.scala 353:30]
- wire matchSlotB_57 = valid_57 & setMatch_57 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_56 = valid_56 & setMatch_57 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_59 = valid_59 & setMatch_57 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_58 = valid_58 & setMatch_57 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_61 = valid_61 & setMatch_61 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_60 = valid_60 & setMatch_61 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_63 = valid_63 & setMatch_61 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_62 = valid_62 & setMatch_61 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [31:0] matchSlot_lo_lo_hi = {matchSlotB_63,matchSlotB_62,matchSlotB_61,matchSlotB_60,matchSlotB_59,matchSlotB_58,
- matchSlotB_57,matchSlotB_56,matchSlot_lo_lo_hi_hi_lo,matchSlot_lo_lo_hi_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_65 = valid_65 & setMatch_65 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_64 = valid_64 & setMatch_65 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_67 = valid_67 & setMatch_65 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_66 = valid_66 & setMatch_65 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_69 = valid_69 & setMatch_69 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_68 = valid_68 & setMatch_69 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_71 = valid_71 & setMatch_69 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_70 = valid_70 & setMatch_69 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_lo_hi_lo_lo_lo = {matchSlotB_71,matchSlotB_70,matchSlotB_69,matchSlotB_68,matchSlotB_67,
- matchSlotB_66,matchSlotB_65,matchSlotB_64}; // @[L1DCache.scala 353:30]
- wire matchSlotB_73 = valid_73 & setMatch_73 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_72 = valid_72 & setMatch_73 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_75 = valid_75 & setMatch_73 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_74 = valid_74 & setMatch_73 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_77 = valid_77 & setMatch_77 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_76 = valid_76 & setMatch_77 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_79 = valid_79 & setMatch_77 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_78 = valid_78 & setMatch_77 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [15:0] matchSlot_lo_hi_lo_lo = {matchSlotB_79,matchSlotB_78,matchSlotB_77,matchSlotB_76,matchSlotB_75,
- matchSlotB_74,matchSlotB_73,matchSlotB_72,matchSlot_lo_hi_lo_lo_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_81 = valid_81 & setMatch_81 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_80 = valid_80 & setMatch_81 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_83 = valid_83 & setMatch_81 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_82 = valid_82 & setMatch_81 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_85 = valid_85 & setMatch_85 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_84 = valid_84 & setMatch_85 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_87 = valid_87 & setMatch_85 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_86 = valid_86 & setMatch_85 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_lo_hi_lo_hi_lo = {matchSlotB_87,matchSlotB_86,matchSlotB_85,matchSlotB_84,matchSlotB_83,
- matchSlotB_82,matchSlotB_81,matchSlotB_80}; // @[L1DCache.scala 353:30]
- wire matchSlotB_89 = valid_89 & setMatch_89 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_88 = valid_88 & setMatch_89 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_91 = valid_91 & setMatch_89 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_90 = valid_90 & setMatch_89 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_93 = valid_93 & setMatch_93 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_92 = valid_92 & setMatch_93 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_95 = valid_95 & setMatch_93 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_94 = valid_94 & setMatch_93 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [31:0] matchSlot_lo_hi_lo = {matchSlotB_95,matchSlotB_94,matchSlotB_93,matchSlotB_92,matchSlotB_91,matchSlotB_90,
- matchSlotB_89,matchSlotB_88,matchSlot_lo_hi_lo_hi_lo,matchSlot_lo_hi_lo_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_97 = valid_97 & setMatch_97 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_96 = valid_96 & setMatch_97 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_99 = valid_99 & setMatch_97 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_98 = valid_98 & setMatch_97 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_101 = valid_101 & setMatch_101 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_100 = valid_100 & setMatch_101 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_103 = valid_103 & setMatch_101 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_102 = valid_102 & setMatch_101 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_lo_hi_hi_lo_lo = {matchSlotB_103,matchSlotB_102,matchSlotB_101,matchSlotB_100,matchSlotB_99,
- matchSlotB_98,matchSlotB_97,matchSlotB_96}; // @[L1DCache.scala 353:30]
- wire matchSlotB_105 = valid_105 & setMatch_105 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_104 = valid_104 & setMatch_105 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_107 = valid_107 & setMatch_105 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_106 = valid_106 & setMatch_105 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_109 = valid_109 & setMatch_109 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_108 = valid_108 & setMatch_109 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_111 = valid_111 & setMatch_109 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_110 = valid_110 & setMatch_109 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [15:0] matchSlot_lo_hi_hi_lo = {matchSlotB_111,matchSlotB_110,matchSlotB_109,matchSlotB_108,matchSlotB_107,
- matchSlotB_106,matchSlotB_105,matchSlotB_104,matchSlot_lo_hi_hi_lo_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_113 = valid_113 & setMatch_113 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_112 = valid_112 & setMatch_113 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_115 = valid_115 & setMatch_113 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_114 = valid_114 & setMatch_113 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_117 = valid_117 & setMatch_117 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_116 = valid_116 & setMatch_117 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_119 = valid_119 & setMatch_117 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_118 = valid_118 & setMatch_117 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_lo_hi_hi_hi_lo = {matchSlotB_119,matchSlotB_118,matchSlotB_117,matchSlotB_116,matchSlotB_115,
- matchSlotB_114,matchSlotB_113,matchSlotB_112}; // @[L1DCache.scala 353:30]
- wire matchSlotB_121 = valid_121 & setMatch_121 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_120 = valid_120 & setMatch_121 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_123 = valid_123 & setMatch_121 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_122 = valid_122 & setMatch_121 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_125 = valid_125 & setMatch_125 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_124 = valid_124 & setMatch_125 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_127 = valid_127 & setMatch_125 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_126 = valid_126 & setMatch_125 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [31:0] matchSlot_lo_hi_hi = {matchSlotB_127,matchSlotB_126,matchSlotB_125,matchSlotB_124,matchSlotB_123,
- matchSlotB_122,matchSlotB_121,matchSlotB_120,matchSlot_lo_hi_hi_hi_lo,matchSlot_lo_hi_hi_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_129 = valid_129 & setMatch_129 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_128 = valid_128 & setMatch_129 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_131 = valid_131 & setMatch_129 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_130 = valid_130 & setMatch_129 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_133 = valid_133 & setMatch_133 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_132 = valid_132 & setMatch_133 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_135 = valid_135 & setMatch_133 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_134 = valid_134 & setMatch_133 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_hi_lo_lo_lo_lo = {matchSlotB_135,matchSlotB_134,matchSlotB_133,matchSlotB_132,matchSlotB_131,
- matchSlotB_130,matchSlotB_129,matchSlotB_128}; // @[L1DCache.scala 353:30]
- wire matchSlotB_137 = valid_137 & setMatch_137 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_136 = valid_136 & setMatch_137 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_139 = valid_139 & setMatch_137 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_138 = valid_138 & setMatch_137 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_141 = valid_141 & setMatch_141 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_140 = valid_140 & setMatch_141 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_143 = valid_143 & setMatch_141 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_142 = valid_142 & setMatch_141 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [15:0] matchSlot_hi_lo_lo_lo = {matchSlotB_143,matchSlotB_142,matchSlotB_141,matchSlotB_140,matchSlotB_139,
- matchSlotB_138,matchSlotB_137,matchSlotB_136,matchSlot_hi_lo_lo_lo_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_145 = valid_145 & setMatch_145 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_144 = valid_144 & setMatch_145 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_147 = valid_147 & setMatch_145 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_146 = valid_146 & setMatch_145 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_149 = valid_149 & setMatch_149 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_148 = valid_148 & setMatch_149 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_151 = valid_151 & setMatch_149 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_150 = valid_150 & setMatch_149 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_hi_lo_lo_hi_lo = {matchSlotB_151,matchSlotB_150,matchSlotB_149,matchSlotB_148,matchSlotB_147,
- matchSlotB_146,matchSlotB_145,matchSlotB_144}; // @[L1DCache.scala 353:30]
- wire matchSlotB_153 = valid_153 & setMatch_153 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_152 = valid_152 & setMatch_153 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_155 = valid_155 & setMatch_153 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_154 = valid_154 & setMatch_153 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_157 = valid_157 & setMatch_157 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_156 = valid_156 & setMatch_157 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_159 = valid_159 & setMatch_157 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_158 = valid_158 & setMatch_157 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [31:0] matchSlot_hi_lo_lo = {matchSlotB_159,matchSlotB_158,matchSlotB_157,matchSlotB_156,matchSlotB_155,
- matchSlotB_154,matchSlotB_153,matchSlotB_152,matchSlot_hi_lo_lo_hi_lo,matchSlot_hi_lo_lo_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_161 = valid_161 & setMatch_161 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_160 = valid_160 & setMatch_161 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_163 = valid_163 & setMatch_161 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_162 = valid_162 & setMatch_161 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_165 = valid_165 & setMatch_165 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_164 = valid_164 & setMatch_165 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_167 = valid_167 & setMatch_165 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_166 = valid_166 & setMatch_165 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_hi_lo_hi_lo_lo = {matchSlotB_167,matchSlotB_166,matchSlotB_165,matchSlotB_164,matchSlotB_163,
- matchSlotB_162,matchSlotB_161,matchSlotB_160}; // @[L1DCache.scala 353:30]
- wire matchSlotB_169 = valid_169 & setMatch_169 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_168 = valid_168 & setMatch_169 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_171 = valid_171 & setMatch_169 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_170 = valid_170 & setMatch_169 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_173 = valid_173 & setMatch_173 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_172 = valid_172 & setMatch_173 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_175 = valid_175 & setMatch_173 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_174 = valid_174 & setMatch_173 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [15:0] matchSlot_hi_lo_hi_lo = {matchSlotB_175,matchSlotB_174,matchSlotB_173,matchSlotB_172,matchSlotB_171,
- matchSlotB_170,matchSlotB_169,matchSlotB_168,matchSlot_hi_lo_hi_lo_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_177 = valid_177 & setMatch_177 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_176 = valid_176 & setMatch_177 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_179 = valid_179 & setMatch_177 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_178 = valid_178 & setMatch_177 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_181 = valid_181 & setMatch_181 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_180 = valid_180 & setMatch_181 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_183 = valid_183 & setMatch_181 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_182 = valid_182 & setMatch_181 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_hi_lo_hi_hi_lo = {matchSlotB_183,matchSlotB_182,matchSlotB_181,matchSlotB_180,matchSlotB_179,
- matchSlotB_178,matchSlotB_177,matchSlotB_176}; // @[L1DCache.scala 353:30]
- wire matchSlotB_185 = valid_185 & setMatch_185 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_184 = valid_184 & setMatch_185 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_187 = valid_187 & setMatch_185 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_186 = valid_186 & setMatch_185 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_189 = valid_189 & setMatch_189 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_188 = valid_188 & setMatch_189 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_191 = valid_191 & setMatch_189 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_190 = valid_190 & setMatch_189 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [31:0] matchSlot_hi_lo_hi = {matchSlotB_191,matchSlotB_190,matchSlotB_189,matchSlotB_188,matchSlotB_187,
- matchSlotB_186,matchSlotB_185,matchSlotB_184,matchSlot_hi_lo_hi_hi_lo,matchSlot_hi_lo_hi_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_193 = valid_193 & setMatch_193 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_192 = valid_192 & setMatch_193 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_195 = valid_195 & setMatch_193 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_194 = valid_194 & setMatch_193 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_197 = valid_197 & setMatch_197 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_196 = valid_196 & setMatch_197 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_199 = valid_199 & setMatch_197 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_198 = valid_198 & setMatch_197 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_hi_hi_lo_lo_lo = {matchSlotB_199,matchSlotB_198,matchSlotB_197,matchSlotB_196,matchSlotB_195,
- matchSlotB_194,matchSlotB_193,matchSlotB_192}; // @[L1DCache.scala 353:30]
- wire matchSlotB_201 = valid_201 & setMatch_201 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_200 = valid_200 & setMatch_201 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_203 = valid_203 & setMatch_201 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_202 = valid_202 & setMatch_201 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_205 = valid_205 & setMatch_205 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_204 = valid_204 & setMatch_205 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_207 = valid_207 & setMatch_205 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_206 = valid_206 & setMatch_205 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [15:0] matchSlot_hi_hi_lo_lo = {matchSlotB_207,matchSlotB_206,matchSlotB_205,matchSlotB_204,matchSlotB_203,
- matchSlotB_202,matchSlotB_201,matchSlotB_200,matchSlot_hi_hi_lo_lo_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_209 = valid_209 & setMatch_209 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_208 = valid_208 & setMatch_209 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_211 = valid_211 & setMatch_209 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_210 = valid_210 & setMatch_209 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_213 = valid_213 & setMatch_213 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_212 = valid_212 & setMatch_213 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_215 = valid_215 & setMatch_213 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_214 = valid_214 & setMatch_213 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_hi_hi_lo_hi_lo = {matchSlotB_215,matchSlotB_214,matchSlotB_213,matchSlotB_212,matchSlotB_211,
- matchSlotB_210,matchSlotB_209,matchSlotB_208}; // @[L1DCache.scala 353:30]
- wire matchSlotB_217 = valid_217 & setMatch_217 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_216 = valid_216 & setMatch_217 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_219 = valid_219 & setMatch_217 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_218 = valid_218 & setMatch_217 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_221 = valid_221 & setMatch_221 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_220 = valid_220 & setMatch_221 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_223 = valid_223 & setMatch_221 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_222 = valid_222 & setMatch_221 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [31:0] matchSlot_hi_hi_lo = {matchSlotB_223,matchSlotB_222,matchSlotB_221,matchSlotB_220,matchSlotB_219,
- matchSlotB_218,matchSlotB_217,matchSlotB_216,matchSlot_hi_hi_lo_hi_lo,matchSlot_hi_hi_lo_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_225 = valid_225 & setMatch_225 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_224 = valid_224 & setMatch_225 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_227 = valid_227 & setMatch_225 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_226 = valid_226 & setMatch_225 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_229 = valid_229 & setMatch_229 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_228 = valid_228 & setMatch_229 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_231 = valid_231 & setMatch_229 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_230 = valid_230 & setMatch_229 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_hi_hi_hi_lo_lo = {matchSlotB_231,matchSlotB_230,matchSlotB_229,matchSlotB_228,matchSlotB_227,
- matchSlotB_226,matchSlotB_225,matchSlotB_224}; // @[L1DCache.scala 353:30]
- wire matchSlotB_233 = valid_233 & setMatch_233 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_232 = valid_232 & setMatch_233 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_235 = valid_235 & setMatch_233 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_234 = valid_234 & setMatch_233 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_237 = valid_237 & setMatch_237 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_236 = valid_236 & setMatch_237 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_239 = valid_239 & setMatch_237 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_238 = valid_238 & setMatch_237 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [15:0] matchSlot_hi_hi_hi_lo = {matchSlotB_239,matchSlotB_238,matchSlotB_237,matchSlotB_236,matchSlotB_235,
- matchSlotB_234,matchSlotB_233,matchSlotB_232,matchSlot_hi_hi_hi_lo_lo}; // @[L1DCache.scala 353:30]
- wire matchSlotB_241 = valid_241 & setMatch_241 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_240 = valid_240 & setMatch_241 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_243 = valid_243 & setMatch_241 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_242 = valid_242 & setMatch_241 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_245 = valid_245 & setMatch_245 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_244 = valid_244 & setMatch_245 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_247 = valid_247 & setMatch_245 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_246 = valid_246 & setMatch_245 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [7:0] matchSlot_hi_hi_hi_hi_lo = {matchSlotB_247,matchSlotB_246,matchSlotB_245,matchSlotB_244,matchSlotB_243,
- matchSlotB_242,matchSlotB_241,matchSlotB_240}; // @[L1DCache.scala 353:30]
- wire matchSlotB_249 = valid_249 & setMatch_249 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_248 = valid_248 & setMatch_249 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_251 = valid_251 & setMatch_249 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_250 = valid_250 & setMatch_249 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire matchSlotB_253 = valid_253 & setMatch_253 & matchAddr_1; // @[L1DCache.scala 381:46]
- wire matchSlotB_252 = valid_252 & setMatch_253 & matchAddr_0; // @[L1DCache.scala 381:46]
- wire matchSlotB_255 = valid_255 & setMatch_253 & matchAddr_3; // @[L1DCache.scala 381:46]
- wire matchSlotB_254 = valid_254 & setMatch_253 & matchAddr_2; // @[L1DCache.scala 381:46]
- wire [31:0] matchSlot_hi_hi_hi = {matchSlotB_255,matchSlotB_254,matchSlotB_253,matchSlotB_252,matchSlotB_251,
- matchSlotB_250,matchSlotB_249,matchSlotB_248,matchSlot_hi_hi_hi_hi_lo,matchSlot_hi_hi_hi_lo}; // @[L1DCache.scala 353:30]
- wire [255:0] matchSlot = {matchSlot_hi_hi_hi,matchSlot_hi_hi_lo,matchSlot_hi_lo_hi,matchSlot_hi_lo_lo,
- matchSlot_lo_hi_hi,matchSlot_lo_hi_lo,matchSlot_lo_lo_hi,matchSlot_lo_lo_lo}; // @[L1DCache.scala 353:30]
- wire historyMatch_1 = history_0_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_1 = setMatch_1 & historyMatch_1; // @[L1DCache.scala 384:36]
- wire historyMatch = history_0_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_0 = setMatch_1 & historyMatch; // @[L1DCache.scala 384:36]
- wire historyMatch_3 = history_0_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_3 = setMatch_1 & historyMatch_3; // @[L1DCache.scala 384:36]
- wire historyMatch_2 = history_0_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_2 = setMatch_1 & historyMatch_2; // @[L1DCache.scala 384:36]
- wire historyMatch_5 = history_1_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_5 = setMatch_5 & historyMatch_5; // @[L1DCache.scala 384:36]
- wire historyMatch_4 = history_1_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_4 = setMatch_5 & historyMatch_4; // @[L1DCache.scala 384:36]
- wire historyMatch_7 = history_1_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_7 = setMatch_5 & historyMatch_7; // @[L1DCache.scala 384:36]
- wire historyMatch_6 = history_1_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_6 = setMatch_5 & historyMatch_6; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_lo_lo_lo_lo_lo = {replaceSlotB_7,replaceSlotB_6,replaceSlotB_5,replaceSlotB_4,replaceSlotB_3,
- replaceSlotB_2,replaceSlotB_1,replaceSlotB_0}; // @[L1DCache.scala 355:34]
- wire historyMatch_9 = history_2_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_9 = setMatch_9 & historyMatch_9; // @[L1DCache.scala 384:36]
- wire historyMatch_8 = history_2_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_8 = setMatch_9 & historyMatch_8; // @[L1DCache.scala 384:36]
- wire historyMatch_11 = history_2_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_11 = setMatch_9 & historyMatch_11; // @[L1DCache.scala 384:36]
- wire historyMatch_10 = history_2_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_10 = setMatch_9 & historyMatch_10; // @[L1DCache.scala 384:36]
- wire historyMatch_13 = history_3_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_13 = setMatch_13 & historyMatch_13; // @[L1DCache.scala 384:36]
- wire historyMatch_12 = history_3_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_12 = setMatch_13 & historyMatch_12; // @[L1DCache.scala 384:36]
- wire historyMatch_15 = history_3_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_15 = setMatch_13 & historyMatch_15; // @[L1DCache.scala 384:36]
- wire historyMatch_14 = history_3_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_14 = setMatch_13 & historyMatch_14; // @[L1DCache.scala 384:36]
- wire [15:0] replaceSlot_lo_lo_lo_lo = {replaceSlotB_15,replaceSlotB_14,replaceSlotB_13,replaceSlotB_12,replaceSlotB_11
- ,replaceSlotB_10,replaceSlotB_9,replaceSlotB_8,replaceSlot_lo_lo_lo_lo_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_17 = history_4_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_17 = setMatch_17 & historyMatch_17; // @[L1DCache.scala 384:36]
- wire historyMatch_16 = history_4_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_16 = setMatch_17 & historyMatch_16; // @[L1DCache.scala 384:36]
- wire historyMatch_19 = history_4_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_19 = setMatch_17 & historyMatch_19; // @[L1DCache.scala 384:36]
- wire historyMatch_18 = history_4_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_18 = setMatch_17 & historyMatch_18; // @[L1DCache.scala 384:36]
- wire historyMatch_21 = history_5_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_21 = setMatch_21 & historyMatch_21; // @[L1DCache.scala 384:36]
- wire historyMatch_20 = history_5_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_20 = setMatch_21 & historyMatch_20; // @[L1DCache.scala 384:36]
- wire historyMatch_23 = history_5_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_23 = setMatch_21 & historyMatch_23; // @[L1DCache.scala 384:36]
- wire historyMatch_22 = history_5_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_22 = setMatch_21 & historyMatch_22; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_lo_lo_lo_hi_lo = {replaceSlotB_23,replaceSlotB_22,replaceSlotB_21,replaceSlotB_20,
- replaceSlotB_19,replaceSlotB_18,replaceSlotB_17,replaceSlotB_16}; // @[L1DCache.scala 355:34]
- wire historyMatch_25 = history_6_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_25 = setMatch_25 & historyMatch_25; // @[L1DCache.scala 384:36]
- wire historyMatch_24 = history_6_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_24 = setMatch_25 & historyMatch_24; // @[L1DCache.scala 384:36]
- wire historyMatch_27 = history_6_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_27 = setMatch_25 & historyMatch_27; // @[L1DCache.scala 384:36]
- wire historyMatch_26 = history_6_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_26 = setMatch_25 & historyMatch_26; // @[L1DCache.scala 384:36]
- wire historyMatch_29 = history_7_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_29 = setMatch_29 & historyMatch_29; // @[L1DCache.scala 384:36]
- wire historyMatch_28 = history_7_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_28 = setMatch_29 & historyMatch_28; // @[L1DCache.scala 384:36]
- wire historyMatch_31 = history_7_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_31 = setMatch_29 & historyMatch_31; // @[L1DCache.scala 384:36]
- wire historyMatch_30 = history_7_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_30 = setMatch_29 & historyMatch_30; // @[L1DCache.scala 384:36]
- wire [31:0] replaceSlot_lo_lo_lo = {replaceSlotB_31,replaceSlotB_30,replaceSlotB_29,replaceSlotB_28,replaceSlotB_27,
- replaceSlotB_26,replaceSlotB_25,replaceSlotB_24,replaceSlot_lo_lo_lo_hi_lo,replaceSlot_lo_lo_lo_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_33 = history_8_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_33 = setMatch_33 & historyMatch_33; // @[L1DCache.scala 384:36]
- wire historyMatch_32 = history_8_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_32 = setMatch_33 & historyMatch_32; // @[L1DCache.scala 384:36]
- wire historyMatch_35 = history_8_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_35 = setMatch_33 & historyMatch_35; // @[L1DCache.scala 384:36]
- wire historyMatch_34 = history_8_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_34 = setMatch_33 & historyMatch_34; // @[L1DCache.scala 384:36]
- wire historyMatch_37 = history_9_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_37 = setMatch_37 & historyMatch_37; // @[L1DCache.scala 384:36]
- wire historyMatch_36 = history_9_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_36 = setMatch_37 & historyMatch_36; // @[L1DCache.scala 384:36]
- wire historyMatch_39 = history_9_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_39 = setMatch_37 & historyMatch_39; // @[L1DCache.scala 384:36]
- wire historyMatch_38 = history_9_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_38 = setMatch_37 & historyMatch_38; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_lo_lo_hi_lo_lo = {replaceSlotB_39,replaceSlotB_38,replaceSlotB_37,replaceSlotB_36,
- replaceSlotB_35,replaceSlotB_34,replaceSlotB_33,replaceSlotB_32}; // @[L1DCache.scala 355:34]
- wire historyMatch_41 = history_10_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_41 = setMatch_41 & historyMatch_41; // @[L1DCache.scala 384:36]
- wire historyMatch_40 = history_10_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_40 = setMatch_41 & historyMatch_40; // @[L1DCache.scala 384:36]
- wire historyMatch_43 = history_10_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_43 = setMatch_41 & historyMatch_43; // @[L1DCache.scala 384:36]
- wire historyMatch_42 = history_10_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_42 = setMatch_41 & historyMatch_42; // @[L1DCache.scala 384:36]
- wire historyMatch_45 = history_11_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_45 = setMatch_45 & historyMatch_45; // @[L1DCache.scala 384:36]
- wire historyMatch_44 = history_11_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_44 = setMatch_45 & historyMatch_44; // @[L1DCache.scala 384:36]
- wire historyMatch_47 = history_11_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_47 = setMatch_45 & historyMatch_47; // @[L1DCache.scala 384:36]
- wire historyMatch_46 = history_11_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_46 = setMatch_45 & historyMatch_46; // @[L1DCache.scala 384:36]
- wire [15:0] replaceSlot_lo_lo_hi_lo = {replaceSlotB_47,replaceSlotB_46,replaceSlotB_45,replaceSlotB_44,replaceSlotB_43
- ,replaceSlotB_42,replaceSlotB_41,replaceSlotB_40,replaceSlot_lo_lo_hi_lo_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_49 = history_12_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_49 = setMatch_49 & historyMatch_49; // @[L1DCache.scala 384:36]
- wire historyMatch_48 = history_12_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_48 = setMatch_49 & historyMatch_48; // @[L1DCache.scala 384:36]
- wire historyMatch_51 = history_12_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_51 = setMatch_49 & historyMatch_51; // @[L1DCache.scala 384:36]
- wire historyMatch_50 = history_12_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_50 = setMatch_49 & historyMatch_50; // @[L1DCache.scala 384:36]
- wire historyMatch_53 = history_13_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_53 = setMatch_53 & historyMatch_53; // @[L1DCache.scala 384:36]
- wire historyMatch_52 = history_13_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_52 = setMatch_53 & historyMatch_52; // @[L1DCache.scala 384:36]
- wire historyMatch_55 = history_13_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_55 = setMatch_53 & historyMatch_55; // @[L1DCache.scala 384:36]
- wire historyMatch_54 = history_13_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_54 = setMatch_53 & historyMatch_54; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_lo_lo_hi_hi_lo = {replaceSlotB_55,replaceSlotB_54,replaceSlotB_53,replaceSlotB_52,
- replaceSlotB_51,replaceSlotB_50,replaceSlotB_49,replaceSlotB_48}; // @[L1DCache.scala 355:34]
- wire historyMatch_57 = history_14_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_57 = setMatch_57 & historyMatch_57; // @[L1DCache.scala 384:36]
- wire historyMatch_56 = history_14_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_56 = setMatch_57 & historyMatch_56; // @[L1DCache.scala 384:36]
- wire historyMatch_59 = history_14_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_59 = setMatch_57 & historyMatch_59; // @[L1DCache.scala 384:36]
- wire historyMatch_58 = history_14_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_58 = setMatch_57 & historyMatch_58; // @[L1DCache.scala 384:36]
- wire historyMatch_61 = history_15_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_61 = setMatch_61 & historyMatch_61; // @[L1DCache.scala 384:36]
- wire historyMatch_60 = history_15_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_60 = setMatch_61 & historyMatch_60; // @[L1DCache.scala 384:36]
- wire historyMatch_63 = history_15_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_63 = setMatch_61 & historyMatch_63; // @[L1DCache.scala 384:36]
- wire historyMatch_62 = history_15_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_62 = setMatch_61 & historyMatch_62; // @[L1DCache.scala 384:36]
- wire [31:0] replaceSlot_lo_lo_hi = {replaceSlotB_63,replaceSlotB_62,replaceSlotB_61,replaceSlotB_60,replaceSlotB_59,
- replaceSlotB_58,replaceSlotB_57,replaceSlotB_56,replaceSlot_lo_lo_hi_hi_lo,replaceSlot_lo_lo_hi_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_65 = history_16_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_65 = setMatch_65 & historyMatch_65; // @[L1DCache.scala 384:36]
- wire historyMatch_64 = history_16_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_64 = setMatch_65 & historyMatch_64; // @[L1DCache.scala 384:36]
- wire historyMatch_67 = history_16_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_67 = setMatch_65 & historyMatch_67; // @[L1DCache.scala 384:36]
- wire historyMatch_66 = history_16_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_66 = setMatch_65 & historyMatch_66; // @[L1DCache.scala 384:36]
- wire historyMatch_69 = history_17_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_69 = setMatch_69 & historyMatch_69; // @[L1DCache.scala 384:36]
- wire historyMatch_68 = history_17_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_68 = setMatch_69 & historyMatch_68; // @[L1DCache.scala 384:36]
- wire historyMatch_71 = history_17_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_71 = setMatch_69 & historyMatch_71; // @[L1DCache.scala 384:36]
- wire historyMatch_70 = history_17_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_70 = setMatch_69 & historyMatch_70; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_lo_hi_lo_lo_lo = {replaceSlotB_71,replaceSlotB_70,replaceSlotB_69,replaceSlotB_68,
- replaceSlotB_67,replaceSlotB_66,replaceSlotB_65,replaceSlotB_64}; // @[L1DCache.scala 355:34]
- wire historyMatch_73 = history_18_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_73 = setMatch_73 & historyMatch_73; // @[L1DCache.scala 384:36]
- wire historyMatch_72 = history_18_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_72 = setMatch_73 & historyMatch_72; // @[L1DCache.scala 384:36]
- wire historyMatch_75 = history_18_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_75 = setMatch_73 & historyMatch_75; // @[L1DCache.scala 384:36]
- wire historyMatch_74 = history_18_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_74 = setMatch_73 & historyMatch_74; // @[L1DCache.scala 384:36]
- wire historyMatch_77 = history_19_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_77 = setMatch_77 & historyMatch_77; // @[L1DCache.scala 384:36]
- wire historyMatch_76 = history_19_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_76 = setMatch_77 & historyMatch_76; // @[L1DCache.scala 384:36]
- wire historyMatch_79 = history_19_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_79 = setMatch_77 & historyMatch_79; // @[L1DCache.scala 384:36]
- wire historyMatch_78 = history_19_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_78 = setMatch_77 & historyMatch_78; // @[L1DCache.scala 384:36]
- wire [15:0] replaceSlot_lo_hi_lo_lo = {replaceSlotB_79,replaceSlotB_78,replaceSlotB_77,replaceSlotB_76,replaceSlotB_75
- ,replaceSlotB_74,replaceSlotB_73,replaceSlotB_72,replaceSlot_lo_hi_lo_lo_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_81 = history_20_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_81 = setMatch_81 & historyMatch_81; // @[L1DCache.scala 384:36]
- wire historyMatch_80 = history_20_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_80 = setMatch_81 & historyMatch_80; // @[L1DCache.scala 384:36]
- wire historyMatch_83 = history_20_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_83 = setMatch_81 & historyMatch_83; // @[L1DCache.scala 384:36]
- wire historyMatch_82 = history_20_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_82 = setMatch_81 & historyMatch_82; // @[L1DCache.scala 384:36]
- wire historyMatch_85 = history_21_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_85 = setMatch_85 & historyMatch_85; // @[L1DCache.scala 384:36]
- wire historyMatch_84 = history_21_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_84 = setMatch_85 & historyMatch_84; // @[L1DCache.scala 384:36]
- wire historyMatch_87 = history_21_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_87 = setMatch_85 & historyMatch_87; // @[L1DCache.scala 384:36]
- wire historyMatch_86 = history_21_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_86 = setMatch_85 & historyMatch_86; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_lo_hi_lo_hi_lo = {replaceSlotB_87,replaceSlotB_86,replaceSlotB_85,replaceSlotB_84,
- replaceSlotB_83,replaceSlotB_82,replaceSlotB_81,replaceSlotB_80}; // @[L1DCache.scala 355:34]
- wire historyMatch_89 = history_22_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_89 = setMatch_89 & historyMatch_89; // @[L1DCache.scala 384:36]
- wire historyMatch_88 = history_22_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_88 = setMatch_89 & historyMatch_88; // @[L1DCache.scala 384:36]
- wire historyMatch_91 = history_22_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_91 = setMatch_89 & historyMatch_91; // @[L1DCache.scala 384:36]
- wire historyMatch_90 = history_22_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_90 = setMatch_89 & historyMatch_90; // @[L1DCache.scala 384:36]
- wire historyMatch_93 = history_23_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_93 = setMatch_93 & historyMatch_93; // @[L1DCache.scala 384:36]
- wire historyMatch_92 = history_23_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_92 = setMatch_93 & historyMatch_92; // @[L1DCache.scala 384:36]
- wire historyMatch_95 = history_23_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_95 = setMatch_93 & historyMatch_95; // @[L1DCache.scala 384:36]
- wire historyMatch_94 = history_23_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_94 = setMatch_93 & historyMatch_94; // @[L1DCache.scala 384:36]
- wire [31:0] replaceSlot_lo_hi_lo = {replaceSlotB_95,replaceSlotB_94,replaceSlotB_93,replaceSlotB_92,replaceSlotB_91,
- replaceSlotB_90,replaceSlotB_89,replaceSlotB_88,replaceSlot_lo_hi_lo_hi_lo,replaceSlot_lo_hi_lo_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_97 = history_24_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_97 = setMatch_97 & historyMatch_97; // @[L1DCache.scala 384:36]
- wire historyMatch_96 = history_24_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_96 = setMatch_97 & historyMatch_96; // @[L1DCache.scala 384:36]
- wire historyMatch_99 = history_24_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_99 = setMatch_97 & historyMatch_99; // @[L1DCache.scala 384:36]
- wire historyMatch_98 = history_24_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_98 = setMatch_97 & historyMatch_98; // @[L1DCache.scala 384:36]
- wire historyMatch_101 = history_25_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_101 = setMatch_101 & historyMatch_101; // @[L1DCache.scala 384:36]
- wire historyMatch_100 = history_25_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_100 = setMatch_101 & historyMatch_100; // @[L1DCache.scala 384:36]
- wire historyMatch_103 = history_25_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_103 = setMatch_101 & historyMatch_103; // @[L1DCache.scala 384:36]
- wire historyMatch_102 = history_25_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_102 = setMatch_101 & historyMatch_102; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_lo_hi_hi_lo_lo = {replaceSlotB_103,replaceSlotB_102,replaceSlotB_101,replaceSlotB_100,
- replaceSlotB_99,replaceSlotB_98,replaceSlotB_97,replaceSlotB_96}; // @[L1DCache.scala 355:34]
- wire historyMatch_105 = history_26_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_105 = setMatch_105 & historyMatch_105; // @[L1DCache.scala 384:36]
- wire historyMatch_104 = history_26_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_104 = setMatch_105 & historyMatch_104; // @[L1DCache.scala 384:36]
- wire historyMatch_107 = history_26_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_107 = setMatch_105 & historyMatch_107; // @[L1DCache.scala 384:36]
- wire historyMatch_106 = history_26_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_106 = setMatch_105 & historyMatch_106; // @[L1DCache.scala 384:36]
- wire historyMatch_109 = history_27_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_109 = setMatch_109 & historyMatch_109; // @[L1DCache.scala 384:36]
- wire historyMatch_108 = history_27_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_108 = setMatch_109 & historyMatch_108; // @[L1DCache.scala 384:36]
- wire historyMatch_111 = history_27_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_111 = setMatch_109 & historyMatch_111; // @[L1DCache.scala 384:36]
- wire historyMatch_110 = history_27_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_110 = setMatch_109 & historyMatch_110; // @[L1DCache.scala 384:36]
- wire [15:0] replaceSlot_lo_hi_hi_lo = {replaceSlotB_111,replaceSlotB_110,replaceSlotB_109,replaceSlotB_108,
- replaceSlotB_107,replaceSlotB_106,replaceSlotB_105,replaceSlotB_104,replaceSlot_lo_hi_hi_lo_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_113 = history_28_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_113 = setMatch_113 & historyMatch_113; // @[L1DCache.scala 384:36]
- wire historyMatch_112 = history_28_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_112 = setMatch_113 & historyMatch_112; // @[L1DCache.scala 384:36]
- wire historyMatch_115 = history_28_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_115 = setMatch_113 & historyMatch_115; // @[L1DCache.scala 384:36]
- wire historyMatch_114 = history_28_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_114 = setMatch_113 & historyMatch_114; // @[L1DCache.scala 384:36]
- wire historyMatch_117 = history_29_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_117 = setMatch_117 & historyMatch_117; // @[L1DCache.scala 384:36]
- wire historyMatch_116 = history_29_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_116 = setMatch_117 & historyMatch_116; // @[L1DCache.scala 384:36]
- wire historyMatch_119 = history_29_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_119 = setMatch_117 & historyMatch_119; // @[L1DCache.scala 384:36]
- wire historyMatch_118 = history_29_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_118 = setMatch_117 & historyMatch_118; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_lo_hi_hi_hi_lo = {replaceSlotB_119,replaceSlotB_118,replaceSlotB_117,replaceSlotB_116,
- replaceSlotB_115,replaceSlotB_114,replaceSlotB_113,replaceSlotB_112}; // @[L1DCache.scala 355:34]
- wire historyMatch_121 = history_30_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_121 = setMatch_121 & historyMatch_121; // @[L1DCache.scala 384:36]
- wire historyMatch_120 = history_30_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_120 = setMatch_121 & historyMatch_120; // @[L1DCache.scala 384:36]
- wire historyMatch_123 = history_30_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_123 = setMatch_121 & historyMatch_123; // @[L1DCache.scala 384:36]
- wire historyMatch_122 = history_30_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_122 = setMatch_121 & historyMatch_122; // @[L1DCache.scala 384:36]
- wire historyMatch_125 = history_31_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_125 = setMatch_125 & historyMatch_125; // @[L1DCache.scala 384:36]
- wire historyMatch_124 = history_31_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_124 = setMatch_125 & historyMatch_124; // @[L1DCache.scala 384:36]
- wire historyMatch_127 = history_31_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_127 = setMatch_125 & historyMatch_127; // @[L1DCache.scala 384:36]
- wire historyMatch_126 = history_31_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_126 = setMatch_125 & historyMatch_126; // @[L1DCache.scala 384:36]
- wire [31:0] replaceSlot_lo_hi_hi = {replaceSlotB_127,replaceSlotB_126,replaceSlotB_125,replaceSlotB_124,
- replaceSlotB_123,replaceSlotB_122,replaceSlotB_121,replaceSlotB_120,replaceSlot_lo_hi_hi_hi_lo,
- replaceSlot_lo_hi_hi_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_129 = history_32_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_129 = setMatch_129 & historyMatch_129; // @[L1DCache.scala 384:36]
- wire historyMatch_128 = history_32_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_128 = setMatch_129 & historyMatch_128; // @[L1DCache.scala 384:36]
- wire historyMatch_131 = history_32_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_131 = setMatch_129 & historyMatch_131; // @[L1DCache.scala 384:36]
- wire historyMatch_130 = history_32_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_130 = setMatch_129 & historyMatch_130; // @[L1DCache.scala 384:36]
- wire historyMatch_133 = history_33_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_133 = setMatch_133 & historyMatch_133; // @[L1DCache.scala 384:36]
- wire historyMatch_132 = history_33_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_132 = setMatch_133 & historyMatch_132; // @[L1DCache.scala 384:36]
- wire historyMatch_135 = history_33_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_135 = setMatch_133 & historyMatch_135; // @[L1DCache.scala 384:36]
- wire historyMatch_134 = history_33_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_134 = setMatch_133 & historyMatch_134; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_hi_lo_lo_lo_lo = {replaceSlotB_135,replaceSlotB_134,replaceSlotB_133,replaceSlotB_132,
- replaceSlotB_131,replaceSlotB_130,replaceSlotB_129,replaceSlotB_128}; // @[L1DCache.scala 355:34]
- wire historyMatch_137 = history_34_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_137 = setMatch_137 & historyMatch_137; // @[L1DCache.scala 384:36]
- wire historyMatch_136 = history_34_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_136 = setMatch_137 & historyMatch_136; // @[L1DCache.scala 384:36]
- wire historyMatch_139 = history_34_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_139 = setMatch_137 & historyMatch_139; // @[L1DCache.scala 384:36]
- wire historyMatch_138 = history_34_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_138 = setMatch_137 & historyMatch_138; // @[L1DCache.scala 384:36]
- wire historyMatch_141 = history_35_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_141 = setMatch_141 & historyMatch_141; // @[L1DCache.scala 384:36]
- wire historyMatch_140 = history_35_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_140 = setMatch_141 & historyMatch_140; // @[L1DCache.scala 384:36]
- wire historyMatch_143 = history_35_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_143 = setMatch_141 & historyMatch_143; // @[L1DCache.scala 384:36]
- wire historyMatch_142 = history_35_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_142 = setMatch_141 & historyMatch_142; // @[L1DCache.scala 384:36]
- wire [15:0] replaceSlot_hi_lo_lo_lo = {replaceSlotB_143,replaceSlotB_142,replaceSlotB_141,replaceSlotB_140,
- replaceSlotB_139,replaceSlotB_138,replaceSlotB_137,replaceSlotB_136,replaceSlot_hi_lo_lo_lo_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_145 = history_36_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_145 = setMatch_145 & historyMatch_145; // @[L1DCache.scala 384:36]
- wire historyMatch_144 = history_36_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_144 = setMatch_145 & historyMatch_144; // @[L1DCache.scala 384:36]
- wire historyMatch_147 = history_36_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_147 = setMatch_145 & historyMatch_147; // @[L1DCache.scala 384:36]
- wire historyMatch_146 = history_36_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_146 = setMatch_145 & historyMatch_146; // @[L1DCache.scala 384:36]
- wire historyMatch_149 = history_37_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_149 = setMatch_149 & historyMatch_149; // @[L1DCache.scala 384:36]
- wire historyMatch_148 = history_37_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_148 = setMatch_149 & historyMatch_148; // @[L1DCache.scala 384:36]
- wire historyMatch_151 = history_37_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_151 = setMatch_149 & historyMatch_151; // @[L1DCache.scala 384:36]
- wire historyMatch_150 = history_37_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_150 = setMatch_149 & historyMatch_150; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_hi_lo_lo_hi_lo = {replaceSlotB_151,replaceSlotB_150,replaceSlotB_149,replaceSlotB_148,
- replaceSlotB_147,replaceSlotB_146,replaceSlotB_145,replaceSlotB_144}; // @[L1DCache.scala 355:34]
- wire historyMatch_153 = history_38_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_153 = setMatch_153 & historyMatch_153; // @[L1DCache.scala 384:36]
- wire historyMatch_152 = history_38_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_152 = setMatch_153 & historyMatch_152; // @[L1DCache.scala 384:36]
- wire historyMatch_155 = history_38_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_155 = setMatch_153 & historyMatch_155; // @[L1DCache.scala 384:36]
- wire historyMatch_154 = history_38_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_154 = setMatch_153 & historyMatch_154; // @[L1DCache.scala 384:36]
- wire historyMatch_157 = history_39_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_157 = setMatch_157 & historyMatch_157; // @[L1DCache.scala 384:36]
- wire historyMatch_156 = history_39_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_156 = setMatch_157 & historyMatch_156; // @[L1DCache.scala 384:36]
- wire historyMatch_159 = history_39_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_159 = setMatch_157 & historyMatch_159; // @[L1DCache.scala 384:36]
- wire historyMatch_158 = history_39_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_158 = setMatch_157 & historyMatch_158; // @[L1DCache.scala 384:36]
- wire [31:0] replaceSlot_hi_lo_lo = {replaceSlotB_159,replaceSlotB_158,replaceSlotB_157,replaceSlotB_156,
- replaceSlotB_155,replaceSlotB_154,replaceSlotB_153,replaceSlotB_152,replaceSlot_hi_lo_lo_hi_lo,
- replaceSlot_hi_lo_lo_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_161 = history_40_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_161 = setMatch_161 & historyMatch_161; // @[L1DCache.scala 384:36]
- wire historyMatch_160 = history_40_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_160 = setMatch_161 & historyMatch_160; // @[L1DCache.scala 384:36]
- wire historyMatch_163 = history_40_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_163 = setMatch_161 & historyMatch_163; // @[L1DCache.scala 384:36]
- wire historyMatch_162 = history_40_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_162 = setMatch_161 & historyMatch_162; // @[L1DCache.scala 384:36]
- wire historyMatch_165 = history_41_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_165 = setMatch_165 & historyMatch_165; // @[L1DCache.scala 384:36]
- wire historyMatch_164 = history_41_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_164 = setMatch_165 & historyMatch_164; // @[L1DCache.scala 384:36]
- wire historyMatch_167 = history_41_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_167 = setMatch_165 & historyMatch_167; // @[L1DCache.scala 384:36]
- wire historyMatch_166 = history_41_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_166 = setMatch_165 & historyMatch_166; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_hi_lo_hi_lo_lo = {replaceSlotB_167,replaceSlotB_166,replaceSlotB_165,replaceSlotB_164,
- replaceSlotB_163,replaceSlotB_162,replaceSlotB_161,replaceSlotB_160}; // @[L1DCache.scala 355:34]
- wire historyMatch_169 = history_42_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_169 = setMatch_169 & historyMatch_169; // @[L1DCache.scala 384:36]
- wire historyMatch_168 = history_42_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_168 = setMatch_169 & historyMatch_168; // @[L1DCache.scala 384:36]
- wire historyMatch_171 = history_42_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_171 = setMatch_169 & historyMatch_171; // @[L1DCache.scala 384:36]
- wire historyMatch_170 = history_42_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_170 = setMatch_169 & historyMatch_170; // @[L1DCache.scala 384:36]
- wire historyMatch_173 = history_43_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_173 = setMatch_173 & historyMatch_173; // @[L1DCache.scala 384:36]
- wire historyMatch_172 = history_43_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_172 = setMatch_173 & historyMatch_172; // @[L1DCache.scala 384:36]
- wire historyMatch_175 = history_43_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_175 = setMatch_173 & historyMatch_175; // @[L1DCache.scala 384:36]
- wire historyMatch_174 = history_43_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_174 = setMatch_173 & historyMatch_174; // @[L1DCache.scala 384:36]
- wire [15:0] replaceSlot_hi_lo_hi_lo = {replaceSlotB_175,replaceSlotB_174,replaceSlotB_173,replaceSlotB_172,
- replaceSlotB_171,replaceSlotB_170,replaceSlotB_169,replaceSlotB_168,replaceSlot_hi_lo_hi_lo_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_177 = history_44_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_177 = setMatch_177 & historyMatch_177; // @[L1DCache.scala 384:36]
- wire historyMatch_176 = history_44_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_176 = setMatch_177 & historyMatch_176; // @[L1DCache.scala 384:36]
- wire historyMatch_179 = history_44_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_179 = setMatch_177 & historyMatch_179; // @[L1DCache.scala 384:36]
- wire historyMatch_178 = history_44_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_178 = setMatch_177 & historyMatch_178; // @[L1DCache.scala 384:36]
- wire historyMatch_181 = history_45_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_181 = setMatch_181 & historyMatch_181; // @[L1DCache.scala 384:36]
- wire historyMatch_180 = history_45_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_180 = setMatch_181 & historyMatch_180; // @[L1DCache.scala 384:36]
- wire historyMatch_183 = history_45_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_183 = setMatch_181 & historyMatch_183; // @[L1DCache.scala 384:36]
- wire historyMatch_182 = history_45_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_182 = setMatch_181 & historyMatch_182; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_hi_lo_hi_hi_lo = {replaceSlotB_183,replaceSlotB_182,replaceSlotB_181,replaceSlotB_180,
- replaceSlotB_179,replaceSlotB_178,replaceSlotB_177,replaceSlotB_176}; // @[L1DCache.scala 355:34]
- wire historyMatch_185 = history_46_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_185 = setMatch_185 & historyMatch_185; // @[L1DCache.scala 384:36]
- wire historyMatch_184 = history_46_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_184 = setMatch_185 & historyMatch_184; // @[L1DCache.scala 384:36]
- wire historyMatch_187 = history_46_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_187 = setMatch_185 & historyMatch_187; // @[L1DCache.scala 384:36]
- wire historyMatch_186 = history_46_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_186 = setMatch_185 & historyMatch_186; // @[L1DCache.scala 384:36]
- wire historyMatch_189 = history_47_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_189 = setMatch_189 & historyMatch_189; // @[L1DCache.scala 384:36]
- wire historyMatch_188 = history_47_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_188 = setMatch_189 & historyMatch_188; // @[L1DCache.scala 384:36]
- wire historyMatch_191 = history_47_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_191 = setMatch_189 & historyMatch_191; // @[L1DCache.scala 384:36]
- wire historyMatch_190 = history_47_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_190 = setMatch_189 & historyMatch_190; // @[L1DCache.scala 384:36]
- wire [31:0] replaceSlot_hi_lo_hi = {replaceSlotB_191,replaceSlotB_190,replaceSlotB_189,replaceSlotB_188,
- replaceSlotB_187,replaceSlotB_186,replaceSlotB_185,replaceSlotB_184,replaceSlot_hi_lo_hi_hi_lo,
- replaceSlot_hi_lo_hi_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_193 = history_48_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_193 = setMatch_193 & historyMatch_193; // @[L1DCache.scala 384:36]
- wire historyMatch_192 = history_48_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_192 = setMatch_193 & historyMatch_192; // @[L1DCache.scala 384:36]
- wire historyMatch_195 = history_48_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_195 = setMatch_193 & historyMatch_195; // @[L1DCache.scala 384:36]
- wire historyMatch_194 = history_48_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_194 = setMatch_193 & historyMatch_194; // @[L1DCache.scala 384:36]
- wire historyMatch_197 = history_49_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_197 = setMatch_197 & historyMatch_197; // @[L1DCache.scala 384:36]
- wire historyMatch_196 = history_49_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_196 = setMatch_197 & historyMatch_196; // @[L1DCache.scala 384:36]
- wire historyMatch_199 = history_49_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_199 = setMatch_197 & historyMatch_199; // @[L1DCache.scala 384:36]
- wire historyMatch_198 = history_49_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_198 = setMatch_197 & historyMatch_198; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_hi_hi_lo_lo_lo = {replaceSlotB_199,replaceSlotB_198,replaceSlotB_197,replaceSlotB_196,
- replaceSlotB_195,replaceSlotB_194,replaceSlotB_193,replaceSlotB_192}; // @[L1DCache.scala 355:34]
- wire historyMatch_201 = history_50_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_201 = setMatch_201 & historyMatch_201; // @[L1DCache.scala 384:36]
- wire historyMatch_200 = history_50_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_200 = setMatch_201 & historyMatch_200; // @[L1DCache.scala 384:36]
- wire historyMatch_203 = history_50_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_203 = setMatch_201 & historyMatch_203; // @[L1DCache.scala 384:36]
- wire historyMatch_202 = history_50_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_202 = setMatch_201 & historyMatch_202; // @[L1DCache.scala 384:36]
- wire historyMatch_205 = history_51_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_205 = setMatch_205 & historyMatch_205; // @[L1DCache.scala 384:36]
- wire historyMatch_204 = history_51_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_204 = setMatch_205 & historyMatch_204; // @[L1DCache.scala 384:36]
- wire historyMatch_207 = history_51_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_207 = setMatch_205 & historyMatch_207; // @[L1DCache.scala 384:36]
- wire historyMatch_206 = history_51_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_206 = setMatch_205 & historyMatch_206; // @[L1DCache.scala 384:36]
- wire [15:0] replaceSlot_hi_hi_lo_lo = {replaceSlotB_207,replaceSlotB_206,replaceSlotB_205,replaceSlotB_204,
- replaceSlotB_203,replaceSlotB_202,replaceSlotB_201,replaceSlotB_200,replaceSlot_hi_hi_lo_lo_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_209 = history_52_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_209 = setMatch_209 & historyMatch_209; // @[L1DCache.scala 384:36]
- wire historyMatch_208 = history_52_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_208 = setMatch_209 & historyMatch_208; // @[L1DCache.scala 384:36]
- wire historyMatch_211 = history_52_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_211 = setMatch_209 & historyMatch_211; // @[L1DCache.scala 384:36]
- wire historyMatch_210 = history_52_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_210 = setMatch_209 & historyMatch_210; // @[L1DCache.scala 384:36]
- wire historyMatch_213 = history_53_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_213 = setMatch_213 & historyMatch_213; // @[L1DCache.scala 384:36]
- wire historyMatch_212 = history_53_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_212 = setMatch_213 & historyMatch_212; // @[L1DCache.scala 384:36]
- wire historyMatch_215 = history_53_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_215 = setMatch_213 & historyMatch_215; // @[L1DCache.scala 384:36]
- wire historyMatch_214 = history_53_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_214 = setMatch_213 & historyMatch_214; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_hi_hi_lo_hi_lo = {replaceSlotB_215,replaceSlotB_214,replaceSlotB_213,replaceSlotB_212,
- replaceSlotB_211,replaceSlotB_210,replaceSlotB_209,replaceSlotB_208}; // @[L1DCache.scala 355:34]
- wire historyMatch_217 = history_54_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_217 = setMatch_217 & historyMatch_217; // @[L1DCache.scala 384:36]
- wire historyMatch_216 = history_54_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_216 = setMatch_217 & historyMatch_216; // @[L1DCache.scala 384:36]
- wire historyMatch_219 = history_54_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_219 = setMatch_217 & historyMatch_219; // @[L1DCache.scala 384:36]
- wire historyMatch_218 = history_54_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_218 = setMatch_217 & historyMatch_218; // @[L1DCache.scala 384:36]
- wire historyMatch_221 = history_55_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_221 = setMatch_221 & historyMatch_221; // @[L1DCache.scala 384:36]
- wire historyMatch_220 = history_55_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_220 = setMatch_221 & historyMatch_220; // @[L1DCache.scala 384:36]
- wire historyMatch_223 = history_55_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_223 = setMatch_221 & historyMatch_223; // @[L1DCache.scala 384:36]
- wire historyMatch_222 = history_55_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_222 = setMatch_221 & historyMatch_222; // @[L1DCache.scala 384:36]
- wire [31:0] replaceSlot_hi_hi_lo = {replaceSlotB_223,replaceSlotB_222,replaceSlotB_221,replaceSlotB_220,
- replaceSlotB_219,replaceSlotB_218,replaceSlotB_217,replaceSlotB_216,replaceSlot_hi_hi_lo_hi_lo,
- replaceSlot_hi_hi_lo_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_225 = history_56_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_225 = setMatch_225 & historyMatch_225; // @[L1DCache.scala 384:36]
- wire historyMatch_224 = history_56_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_224 = setMatch_225 & historyMatch_224; // @[L1DCache.scala 384:36]
- wire historyMatch_227 = history_56_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_227 = setMatch_225 & historyMatch_227; // @[L1DCache.scala 384:36]
- wire historyMatch_226 = history_56_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_226 = setMatch_225 & historyMatch_226; // @[L1DCache.scala 384:36]
- wire historyMatch_229 = history_57_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_229 = setMatch_229 & historyMatch_229; // @[L1DCache.scala 384:36]
- wire historyMatch_228 = history_57_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_228 = setMatch_229 & historyMatch_228; // @[L1DCache.scala 384:36]
- wire historyMatch_231 = history_57_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_231 = setMatch_229 & historyMatch_231; // @[L1DCache.scala 384:36]
- wire historyMatch_230 = history_57_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_230 = setMatch_229 & historyMatch_230; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_hi_hi_hi_lo_lo = {replaceSlotB_231,replaceSlotB_230,replaceSlotB_229,replaceSlotB_228,
- replaceSlotB_227,replaceSlotB_226,replaceSlotB_225,replaceSlotB_224}; // @[L1DCache.scala 355:34]
- wire historyMatch_233 = history_58_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_233 = setMatch_233 & historyMatch_233; // @[L1DCache.scala 384:36]
- wire historyMatch_232 = history_58_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_232 = setMatch_233 & historyMatch_232; // @[L1DCache.scala 384:36]
- wire historyMatch_235 = history_58_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_235 = setMatch_233 & historyMatch_235; // @[L1DCache.scala 384:36]
- wire historyMatch_234 = history_58_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_234 = setMatch_233 & historyMatch_234; // @[L1DCache.scala 384:36]
- wire historyMatch_237 = history_59_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_237 = setMatch_237 & historyMatch_237; // @[L1DCache.scala 384:36]
- wire historyMatch_236 = history_59_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_236 = setMatch_237 & historyMatch_236; // @[L1DCache.scala 384:36]
- wire historyMatch_239 = history_59_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_239 = setMatch_237 & historyMatch_239; // @[L1DCache.scala 384:36]
- wire historyMatch_238 = history_59_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_238 = setMatch_237 & historyMatch_238; // @[L1DCache.scala 384:36]
- wire [15:0] replaceSlot_hi_hi_hi_lo = {replaceSlotB_239,replaceSlotB_238,replaceSlotB_237,replaceSlotB_236,
- replaceSlotB_235,replaceSlotB_234,replaceSlotB_233,replaceSlotB_232,replaceSlot_hi_hi_hi_lo_lo}; // @[L1DCache.scala 355:34]
- wire historyMatch_241 = history_60_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_241 = setMatch_241 & historyMatch_241; // @[L1DCache.scala 384:36]
- wire historyMatch_240 = history_60_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_240 = setMatch_241 & historyMatch_240; // @[L1DCache.scala 384:36]
- wire historyMatch_243 = history_60_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_243 = setMatch_241 & historyMatch_243; // @[L1DCache.scala 384:36]
- wire historyMatch_242 = history_60_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_242 = setMatch_241 & historyMatch_242; // @[L1DCache.scala 384:36]
- wire historyMatch_245 = history_61_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_245 = setMatch_245 & historyMatch_245; // @[L1DCache.scala 384:36]
- wire historyMatch_244 = history_61_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_244 = setMatch_245 & historyMatch_244; // @[L1DCache.scala 384:36]
- wire historyMatch_247 = history_61_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_247 = setMatch_245 & historyMatch_247; // @[L1DCache.scala 384:36]
- wire historyMatch_246 = history_61_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_246 = setMatch_245 & historyMatch_246; // @[L1DCache.scala 384:36]
- wire [7:0] replaceSlot_hi_hi_hi_hi_lo = {replaceSlotB_247,replaceSlotB_246,replaceSlotB_245,replaceSlotB_244,
- replaceSlotB_243,replaceSlotB_242,replaceSlotB_241,replaceSlotB_240}; // @[L1DCache.scala 355:34]
- wire historyMatch_249 = history_62_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_249 = setMatch_249 & historyMatch_249; // @[L1DCache.scala 384:36]
- wire historyMatch_248 = history_62_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_248 = setMatch_249 & historyMatch_248; // @[L1DCache.scala 384:36]
- wire historyMatch_251 = history_62_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_251 = setMatch_249 & historyMatch_251; // @[L1DCache.scala 384:36]
- wire historyMatch_250 = history_62_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_250 = setMatch_249 & historyMatch_250; // @[L1DCache.scala 384:36]
- wire historyMatch_253 = history_63_1 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_253 = setMatch_253 & historyMatch_253; // @[L1DCache.scala 384:36]
- wire historyMatch_252 = history_63_0 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_252 = setMatch_253 & historyMatch_252; // @[L1DCache.scala 384:36]
- wire historyMatch_255 = history_63_3 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_255 = setMatch_253 & historyMatch_255; // @[L1DCache.scala 384:36]
- wire historyMatch_254 = history_63_2 == 2'h0; // @[L1DCache.scala 383:44]
- wire replaceSlotB_254 = setMatch_253 & historyMatch_254; // @[L1DCache.scala 384:36]
- wire [31:0] replaceSlot_hi_hi_hi = {replaceSlotB_255,replaceSlotB_254,replaceSlotB_253,replaceSlotB_252,
- replaceSlotB_251,replaceSlotB_250,replaceSlotB_249,replaceSlotB_248,replaceSlot_hi_hi_hi_hi_lo,
- replaceSlot_hi_hi_hi_lo}; // @[L1DCache.scala 355:34]
- wire [255:0] replaceSlot = {replaceSlot_hi_hi_hi,replaceSlot_hi_hi_lo,replaceSlot_hi_lo_hi,replaceSlot_hi_lo_lo,
- replaceSlot_lo_hi_hi,replaceSlot_lo_hi_lo,replaceSlot_lo_lo_hi,replaceSlot_lo_lo_lo}; // @[L1DCache.scala 355:34]
- wire [1:0] _T_265 = matchSlot[0] + matchSlot[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_267 = matchSlot[2] + matchSlot[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_269 = _T_265 + _T_267; // @[Bitwise.scala 48:55]
- wire [1:0] _T_271 = matchSlot[4] + matchSlot[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_273 = matchSlot[6] + matchSlot[7]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_275 = _T_271 + _T_273; // @[Bitwise.scala 48:55]
- wire [3:0] _T_277 = _T_269 + _T_275; // @[Bitwise.scala 48:55]
- wire [1:0] _T_279 = matchSlot[8] + matchSlot[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_281 = matchSlot[10] + matchSlot[11]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_283 = _T_279 + _T_281; // @[Bitwise.scala 48:55]
- wire [1:0] _T_285 = matchSlot[12] + matchSlot[13]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_287 = matchSlot[14] + matchSlot[15]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_289 = _T_285 + _T_287; // @[Bitwise.scala 48:55]
- wire [3:0] _T_291 = _T_283 + _T_289; // @[Bitwise.scala 48:55]
- wire [4:0] _T_293 = _T_277 + _T_291; // @[Bitwise.scala 48:55]
- wire [1:0] _T_295 = matchSlot[16] + matchSlot[17]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_297 = matchSlot[18] + matchSlot[19]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_299 = _T_295 + _T_297; // @[Bitwise.scala 48:55]
- wire [1:0] _T_301 = matchSlot[20] + matchSlot[21]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_303 = matchSlot[22] + matchSlot[23]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_305 = _T_301 + _T_303; // @[Bitwise.scala 48:55]
- wire [3:0] _T_307 = _T_299 + _T_305; // @[Bitwise.scala 48:55]
- wire [1:0] _T_309 = matchSlot[24] + matchSlot[25]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_311 = matchSlot[26] + matchSlot[27]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_313 = _T_309 + _T_311; // @[Bitwise.scala 48:55]
- wire [1:0] _T_315 = matchSlot[28] + matchSlot[29]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_317 = matchSlot[30] + matchSlot[31]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_319 = _T_315 + _T_317; // @[Bitwise.scala 48:55]
- wire [3:0] _T_321 = _T_313 + _T_319; // @[Bitwise.scala 48:55]
- wire [4:0] _T_323 = _T_307 + _T_321; // @[Bitwise.scala 48:55]
- wire [5:0] _T_325 = _T_293 + _T_323; // @[Bitwise.scala 48:55]
- wire [1:0] _T_327 = matchSlot[32] + matchSlot[33]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_329 = matchSlot[34] + matchSlot[35]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_331 = _T_327 + _T_329; // @[Bitwise.scala 48:55]
- wire [1:0] _T_333 = matchSlot[36] + matchSlot[37]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_335 = matchSlot[38] + matchSlot[39]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_337 = _T_333 + _T_335; // @[Bitwise.scala 48:55]
- wire [3:0] _T_339 = _T_331 + _T_337; // @[Bitwise.scala 48:55]
- wire [1:0] _T_341 = matchSlot[40] + matchSlot[41]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_343 = matchSlot[42] + matchSlot[43]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_345 = _T_341 + _T_343; // @[Bitwise.scala 48:55]
- wire [1:0] _T_347 = matchSlot[44] + matchSlot[45]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_349 = matchSlot[46] + matchSlot[47]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_351 = _T_347 + _T_349; // @[Bitwise.scala 48:55]
- wire [3:0] _T_353 = _T_345 + _T_351; // @[Bitwise.scala 48:55]
- wire [4:0] _T_355 = _T_339 + _T_353; // @[Bitwise.scala 48:55]
- wire [1:0] _T_357 = matchSlot[48] + matchSlot[49]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_359 = matchSlot[50] + matchSlot[51]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_361 = _T_357 + _T_359; // @[Bitwise.scala 48:55]
- wire [1:0] _T_363 = matchSlot[52] + matchSlot[53]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_365 = matchSlot[54] + matchSlot[55]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_367 = _T_363 + _T_365; // @[Bitwise.scala 48:55]
- wire [3:0] _T_369 = _T_361 + _T_367; // @[Bitwise.scala 48:55]
- wire [1:0] _T_371 = matchSlot[56] + matchSlot[57]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_373 = matchSlot[58] + matchSlot[59]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_375 = _T_371 + _T_373; // @[Bitwise.scala 48:55]
- wire [1:0] _T_377 = matchSlot[60] + matchSlot[61]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_379 = matchSlot[62] + matchSlot[63]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_381 = _T_377 + _T_379; // @[Bitwise.scala 48:55]
- wire [3:0] _T_383 = _T_375 + _T_381; // @[Bitwise.scala 48:55]
- wire [4:0] _T_385 = _T_369 + _T_383; // @[Bitwise.scala 48:55]
- wire [5:0] _T_387 = _T_355 + _T_385; // @[Bitwise.scala 48:55]
- wire [6:0] _T_389 = _T_325 + _T_387; // @[Bitwise.scala 48:55]
- wire [1:0] _T_391 = matchSlot[64] + matchSlot[65]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_393 = matchSlot[66] + matchSlot[67]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_395 = _T_391 + _T_393; // @[Bitwise.scala 48:55]
- wire [1:0] _T_397 = matchSlot[68] + matchSlot[69]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_399 = matchSlot[70] + matchSlot[71]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_401 = _T_397 + _T_399; // @[Bitwise.scala 48:55]
- wire [3:0] _T_403 = _T_395 + _T_401; // @[Bitwise.scala 48:55]
- wire [1:0] _T_405 = matchSlot[72] + matchSlot[73]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_407 = matchSlot[74] + matchSlot[75]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_409 = _T_405 + _T_407; // @[Bitwise.scala 48:55]
- wire [1:0] _T_411 = matchSlot[76] + matchSlot[77]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_413 = matchSlot[78] + matchSlot[79]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_415 = _T_411 + _T_413; // @[Bitwise.scala 48:55]
- wire [3:0] _T_417 = _T_409 + _T_415; // @[Bitwise.scala 48:55]
- wire [4:0] _T_419 = _T_403 + _T_417; // @[Bitwise.scala 48:55]
- wire [1:0] _T_421 = matchSlot[80] + matchSlot[81]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_423 = matchSlot[82] + matchSlot[83]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_425 = _T_421 + _T_423; // @[Bitwise.scala 48:55]
- wire [1:0] _T_427 = matchSlot[84] + matchSlot[85]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_429 = matchSlot[86] + matchSlot[87]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_431 = _T_427 + _T_429; // @[Bitwise.scala 48:55]
- wire [3:0] _T_433 = _T_425 + _T_431; // @[Bitwise.scala 48:55]
- wire [1:0] _T_435 = matchSlot[88] + matchSlot[89]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_437 = matchSlot[90] + matchSlot[91]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_439 = _T_435 + _T_437; // @[Bitwise.scala 48:55]
- wire [1:0] _T_441 = matchSlot[92] + matchSlot[93]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_443 = matchSlot[94] + matchSlot[95]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_445 = _T_441 + _T_443; // @[Bitwise.scala 48:55]
- wire [3:0] _T_447 = _T_439 + _T_445; // @[Bitwise.scala 48:55]
- wire [4:0] _T_449 = _T_433 + _T_447; // @[Bitwise.scala 48:55]
- wire [5:0] _T_451 = _T_419 + _T_449; // @[Bitwise.scala 48:55]
- wire [1:0] _T_453 = matchSlot[96] + matchSlot[97]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_455 = matchSlot[98] + matchSlot[99]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_457 = _T_453 + _T_455; // @[Bitwise.scala 48:55]
- wire [1:0] _T_459 = matchSlot[100] + matchSlot[101]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_461 = matchSlot[102] + matchSlot[103]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_463 = _T_459 + _T_461; // @[Bitwise.scala 48:55]
- wire [3:0] _T_465 = _T_457 + _T_463; // @[Bitwise.scala 48:55]
- wire [1:0] _T_467 = matchSlot[104] + matchSlot[105]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_469 = matchSlot[106] + matchSlot[107]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_471 = _T_467 + _T_469; // @[Bitwise.scala 48:55]
- wire [1:0] _T_473 = matchSlot[108] + matchSlot[109]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_475 = matchSlot[110] + matchSlot[111]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_477 = _T_473 + _T_475; // @[Bitwise.scala 48:55]
- wire [3:0] _T_479 = _T_471 + _T_477; // @[Bitwise.scala 48:55]
- wire [4:0] _T_481 = _T_465 + _T_479; // @[Bitwise.scala 48:55]
- wire [1:0] _T_483 = matchSlot[112] + matchSlot[113]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_485 = matchSlot[114] + matchSlot[115]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_487 = _T_483 + _T_485; // @[Bitwise.scala 48:55]
- wire [1:0] _T_489 = matchSlot[116] + matchSlot[117]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_491 = matchSlot[118] + matchSlot[119]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_493 = _T_489 + _T_491; // @[Bitwise.scala 48:55]
- wire [3:0] _T_495 = _T_487 + _T_493; // @[Bitwise.scala 48:55]
- wire [1:0] _T_497 = matchSlot[120] + matchSlot[121]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_499 = matchSlot[122] + matchSlot[123]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_501 = _T_497 + _T_499; // @[Bitwise.scala 48:55]
- wire [1:0] _T_503 = matchSlot[124] + matchSlot[125]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_505 = matchSlot[126] + matchSlot[127]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_507 = _T_503 + _T_505; // @[Bitwise.scala 48:55]
- wire [3:0] _T_509 = _T_501 + _T_507; // @[Bitwise.scala 48:55]
- wire [4:0] _T_511 = _T_495 + _T_509; // @[Bitwise.scala 48:55]
- wire [5:0] _T_513 = _T_481 + _T_511; // @[Bitwise.scala 48:55]
- wire [6:0] _T_515 = _T_451 + _T_513; // @[Bitwise.scala 48:55]
- wire [7:0] _T_517 = _T_389 + _T_515; // @[Bitwise.scala 48:55]
- wire [1:0] _T_519 = matchSlot[128] + matchSlot[129]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_521 = matchSlot[130] + matchSlot[131]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_523 = _T_519 + _T_521; // @[Bitwise.scala 48:55]
- wire [1:0] _T_525 = matchSlot[132] + matchSlot[133]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_527 = matchSlot[134] + matchSlot[135]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_529 = _T_525 + _T_527; // @[Bitwise.scala 48:55]
- wire [3:0] _T_531 = _T_523 + _T_529; // @[Bitwise.scala 48:55]
- wire [1:0] _T_533 = matchSlot[136] + matchSlot[137]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_535 = matchSlot[138] + matchSlot[139]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_537 = _T_533 + _T_535; // @[Bitwise.scala 48:55]
- wire [1:0] _T_539 = matchSlot[140] + matchSlot[141]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_541 = matchSlot[142] + matchSlot[143]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_543 = _T_539 + _T_541; // @[Bitwise.scala 48:55]
- wire [3:0] _T_545 = _T_537 + _T_543; // @[Bitwise.scala 48:55]
- wire [4:0] _T_547 = _T_531 + _T_545; // @[Bitwise.scala 48:55]
- wire [1:0] _T_549 = matchSlot[144] + matchSlot[145]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_551 = matchSlot[146] + matchSlot[147]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_553 = _T_549 + _T_551; // @[Bitwise.scala 48:55]
- wire [1:0] _T_555 = matchSlot[148] + matchSlot[149]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_557 = matchSlot[150] + matchSlot[151]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_559 = _T_555 + _T_557; // @[Bitwise.scala 48:55]
- wire [3:0] _T_561 = _T_553 + _T_559; // @[Bitwise.scala 48:55]
- wire [1:0] _T_563 = matchSlot[152] + matchSlot[153]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_565 = matchSlot[154] + matchSlot[155]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_567 = _T_563 + _T_565; // @[Bitwise.scala 48:55]
- wire [1:0] _T_569 = matchSlot[156] + matchSlot[157]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_571 = matchSlot[158] + matchSlot[159]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_573 = _T_569 + _T_571; // @[Bitwise.scala 48:55]
- wire [3:0] _T_575 = _T_567 + _T_573; // @[Bitwise.scala 48:55]
- wire [4:0] _T_577 = _T_561 + _T_575; // @[Bitwise.scala 48:55]
- wire [5:0] _T_579 = _T_547 + _T_577; // @[Bitwise.scala 48:55]
- wire [1:0] _T_581 = matchSlot[160] + matchSlot[161]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_583 = matchSlot[162] + matchSlot[163]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_585 = _T_581 + _T_583; // @[Bitwise.scala 48:55]
- wire [1:0] _T_587 = matchSlot[164] + matchSlot[165]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_589 = matchSlot[166] + matchSlot[167]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_591 = _T_587 + _T_589; // @[Bitwise.scala 48:55]
- wire [3:0] _T_593 = _T_585 + _T_591; // @[Bitwise.scala 48:55]
- wire [1:0] _T_595 = matchSlot[168] + matchSlot[169]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_597 = matchSlot[170] + matchSlot[171]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_599 = _T_595 + _T_597; // @[Bitwise.scala 48:55]
- wire [1:0] _T_601 = matchSlot[172] + matchSlot[173]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_603 = matchSlot[174] + matchSlot[175]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_605 = _T_601 + _T_603; // @[Bitwise.scala 48:55]
- wire [3:0] _T_607 = _T_599 + _T_605; // @[Bitwise.scala 48:55]
- wire [4:0] _T_609 = _T_593 + _T_607; // @[Bitwise.scala 48:55]
- wire [1:0] _T_611 = matchSlot[176] + matchSlot[177]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_613 = matchSlot[178] + matchSlot[179]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_615 = _T_611 + _T_613; // @[Bitwise.scala 48:55]
- wire [1:0] _T_617 = matchSlot[180] + matchSlot[181]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_619 = matchSlot[182] + matchSlot[183]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_621 = _T_617 + _T_619; // @[Bitwise.scala 48:55]
- wire [3:0] _T_623 = _T_615 + _T_621; // @[Bitwise.scala 48:55]
- wire [1:0] _T_625 = matchSlot[184] + matchSlot[185]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_627 = matchSlot[186] + matchSlot[187]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_629 = _T_625 + _T_627; // @[Bitwise.scala 48:55]
- wire [1:0] _T_631 = matchSlot[188] + matchSlot[189]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_633 = matchSlot[190] + matchSlot[191]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_635 = _T_631 + _T_633; // @[Bitwise.scala 48:55]
- wire [3:0] _T_637 = _T_629 + _T_635; // @[Bitwise.scala 48:55]
- wire [4:0] _T_639 = _T_623 + _T_637; // @[Bitwise.scala 48:55]
- wire [5:0] _T_641 = _T_609 + _T_639; // @[Bitwise.scala 48:55]
- wire [6:0] _T_643 = _T_579 + _T_641; // @[Bitwise.scala 48:55]
- wire [1:0] _T_645 = matchSlot[192] + matchSlot[193]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_647 = matchSlot[194] + matchSlot[195]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_649 = _T_645 + _T_647; // @[Bitwise.scala 48:55]
- wire [1:0] _T_651 = matchSlot[196] + matchSlot[197]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_653 = matchSlot[198] + matchSlot[199]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_655 = _T_651 + _T_653; // @[Bitwise.scala 48:55]
- wire [3:0] _T_657 = _T_649 + _T_655; // @[Bitwise.scala 48:55]
- wire [1:0] _T_659 = matchSlot[200] + matchSlot[201]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_661 = matchSlot[202] + matchSlot[203]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_663 = _T_659 + _T_661; // @[Bitwise.scala 48:55]
- wire [1:0] _T_665 = matchSlot[204] + matchSlot[205]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_667 = matchSlot[206] + matchSlot[207]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_669 = _T_665 + _T_667; // @[Bitwise.scala 48:55]
- wire [3:0] _T_671 = _T_663 + _T_669; // @[Bitwise.scala 48:55]
- wire [4:0] _T_673 = _T_657 + _T_671; // @[Bitwise.scala 48:55]
- wire [1:0] _T_675 = matchSlot[208] + matchSlot[209]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_677 = matchSlot[210] + matchSlot[211]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_679 = _T_675 + _T_677; // @[Bitwise.scala 48:55]
- wire [1:0] _T_681 = matchSlot[212] + matchSlot[213]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_683 = matchSlot[214] + matchSlot[215]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_685 = _T_681 + _T_683; // @[Bitwise.scala 48:55]
- wire [3:0] _T_687 = _T_679 + _T_685; // @[Bitwise.scala 48:55]
- wire [1:0] _T_689 = matchSlot[216] + matchSlot[217]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_691 = matchSlot[218] + matchSlot[219]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_693 = _T_689 + _T_691; // @[Bitwise.scala 48:55]
- wire [1:0] _T_695 = matchSlot[220] + matchSlot[221]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_697 = matchSlot[222] + matchSlot[223]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_699 = _T_695 + _T_697; // @[Bitwise.scala 48:55]
- wire [3:0] _T_701 = _T_693 + _T_699; // @[Bitwise.scala 48:55]
- wire [4:0] _T_703 = _T_687 + _T_701; // @[Bitwise.scala 48:55]
- wire [5:0] _T_705 = _T_673 + _T_703; // @[Bitwise.scala 48:55]
- wire [1:0] _T_707 = matchSlot[224] + matchSlot[225]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_709 = matchSlot[226] + matchSlot[227]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_711 = _T_707 + _T_709; // @[Bitwise.scala 48:55]
- wire [1:0] _T_713 = matchSlot[228] + matchSlot[229]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_715 = matchSlot[230] + matchSlot[231]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_717 = _T_713 + _T_715; // @[Bitwise.scala 48:55]
- wire [3:0] _T_719 = _T_711 + _T_717; // @[Bitwise.scala 48:55]
- wire [1:0] _T_721 = matchSlot[232] + matchSlot[233]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_723 = matchSlot[234] + matchSlot[235]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_725 = _T_721 + _T_723; // @[Bitwise.scala 48:55]
- wire [1:0] _T_727 = matchSlot[236] + matchSlot[237]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_729 = matchSlot[238] + matchSlot[239]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_731 = _T_727 + _T_729; // @[Bitwise.scala 48:55]
- wire [3:0] _T_733 = _T_725 + _T_731; // @[Bitwise.scala 48:55]
- wire [4:0] _T_735 = _T_719 + _T_733; // @[Bitwise.scala 48:55]
- wire [1:0] _T_737 = matchSlot[240] + matchSlot[241]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_739 = matchSlot[242] + matchSlot[243]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_741 = _T_737 + _T_739; // @[Bitwise.scala 48:55]
- wire [1:0] _T_743 = matchSlot[244] + matchSlot[245]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_745 = matchSlot[246] + matchSlot[247]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_747 = _T_743 + _T_745; // @[Bitwise.scala 48:55]
- wire [3:0] _T_749 = _T_741 + _T_747; // @[Bitwise.scala 48:55]
- wire [1:0] _T_751 = matchSlot[248] + matchSlot[249]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_753 = matchSlot[250] + matchSlot[251]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_755 = _T_751 + _T_753; // @[Bitwise.scala 48:55]
- wire [1:0] _T_757 = matchSlot[252] + matchSlot[253]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_759 = matchSlot[254] + matchSlot[255]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_761 = _T_757 + _T_759; // @[Bitwise.scala 48:55]
- wire [3:0] _T_763 = _T_755 + _T_761; // @[Bitwise.scala 48:55]
- wire [4:0] _T_765 = _T_749 + _T_763; // @[Bitwise.scala 48:55]
- wire [5:0] _T_767 = _T_735 + _T_765; // @[Bitwise.scala 48:55]
- wire [6:0] _T_769 = _T_705 + _T_767; // @[Bitwise.scala 48:55]
- wire [7:0] _T_771 = _T_643 + _T_769; // @[Bitwise.scala 48:55]
- wire [8:0] _T_773 = _T_517 + _T_771; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1035 = replaceSlot[0] + replaceSlot[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1037 = replaceSlot[2] + replaceSlot[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1039 = _T_1035 + _T_1037; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1041 = replaceSlot[4] + replaceSlot[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1043 = replaceSlot[6] + replaceSlot[7]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1045 = _T_1041 + _T_1043; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1047 = _T_1039 + _T_1045; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1049 = replaceSlot[8] + replaceSlot[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1051 = replaceSlot[10] + replaceSlot[11]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1053 = _T_1049 + _T_1051; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1055 = replaceSlot[12] + replaceSlot[13]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1057 = replaceSlot[14] + replaceSlot[15]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1059 = _T_1055 + _T_1057; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1061 = _T_1053 + _T_1059; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1063 = _T_1047 + _T_1061; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1065 = replaceSlot[16] + replaceSlot[17]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1067 = replaceSlot[18] + replaceSlot[19]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1069 = _T_1065 + _T_1067; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1071 = replaceSlot[20] + replaceSlot[21]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1073 = replaceSlot[22] + replaceSlot[23]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1075 = _T_1071 + _T_1073; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1077 = _T_1069 + _T_1075; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1079 = replaceSlot[24] + replaceSlot[25]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1081 = replaceSlot[26] + replaceSlot[27]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1083 = _T_1079 + _T_1081; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1085 = replaceSlot[28] + replaceSlot[29]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1087 = replaceSlot[30] + replaceSlot[31]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1089 = _T_1085 + _T_1087; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1091 = _T_1083 + _T_1089; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1093 = _T_1077 + _T_1091; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1095 = _T_1063 + _T_1093; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1097 = replaceSlot[32] + replaceSlot[33]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1099 = replaceSlot[34] + replaceSlot[35]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1101 = _T_1097 + _T_1099; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1103 = replaceSlot[36] + replaceSlot[37]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1105 = replaceSlot[38] + replaceSlot[39]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1107 = _T_1103 + _T_1105; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1109 = _T_1101 + _T_1107; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1111 = replaceSlot[40] + replaceSlot[41]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1113 = replaceSlot[42] + replaceSlot[43]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1115 = _T_1111 + _T_1113; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1117 = replaceSlot[44] + replaceSlot[45]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1119 = replaceSlot[46] + replaceSlot[47]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1121 = _T_1117 + _T_1119; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1123 = _T_1115 + _T_1121; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1125 = _T_1109 + _T_1123; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1127 = replaceSlot[48] + replaceSlot[49]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1129 = replaceSlot[50] + replaceSlot[51]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1131 = _T_1127 + _T_1129; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1133 = replaceSlot[52] + replaceSlot[53]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1135 = replaceSlot[54] + replaceSlot[55]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1137 = _T_1133 + _T_1135; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1139 = _T_1131 + _T_1137; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1141 = replaceSlot[56] + replaceSlot[57]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1143 = replaceSlot[58] + replaceSlot[59]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1145 = _T_1141 + _T_1143; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1147 = replaceSlot[60] + replaceSlot[61]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1149 = replaceSlot[62] + replaceSlot[63]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1151 = _T_1147 + _T_1149; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1153 = _T_1145 + _T_1151; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1155 = _T_1139 + _T_1153; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1157 = _T_1125 + _T_1155; // @[Bitwise.scala 48:55]
- wire [6:0] _T_1159 = _T_1095 + _T_1157; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1161 = replaceSlot[64] + replaceSlot[65]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1163 = replaceSlot[66] + replaceSlot[67]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1165 = _T_1161 + _T_1163; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1167 = replaceSlot[68] + replaceSlot[69]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1169 = replaceSlot[70] + replaceSlot[71]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1171 = _T_1167 + _T_1169; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1173 = _T_1165 + _T_1171; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1175 = replaceSlot[72] + replaceSlot[73]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1177 = replaceSlot[74] + replaceSlot[75]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1179 = _T_1175 + _T_1177; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1181 = replaceSlot[76] + replaceSlot[77]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1183 = replaceSlot[78] + replaceSlot[79]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1185 = _T_1181 + _T_1183; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1187 = _T_1179 + _T_1185; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1189 = _T_1173 + _T_1187; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1191 = replaceSlot[80] + replaceSlot[81]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1193 = replaceSlot[82] + replaceSlot[83]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1195 = _T_1191 + _T_1193; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1197 = replaceSlot[84] + replaceSlot[85]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1199 = replaceSlot[86] + replaceSlot[87]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1201 = _T_1197 + _T_1199; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1203 = _T_1195 + _T_1201; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1205 = replaceSlot[88] + replaceSlot[89]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1207 = replaceSlot[90] + replaceSlot[91]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1209 = _T_1205 + _T_1207; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1211 = replaceSlot[92] + replaceSlot[93]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1213 = replaceSlot[94] + replaceSlot[95]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1215 = _T_1211 + _T_1213; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1217 = _T_1209 + _T_1215; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1219 = _T_1203 + _T_1217; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1221 = _T_1189 + _T_1219; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1223 = replaceSlot[96] + replaceSlot[97]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1225 = replaceSlot[98] + replaceSlot[99]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1227 = _T_1223 + _T_1225; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1229 = replaceSlot[100] + replaceSlot[101]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1231 = replaceSlot[102] + replaceSlot[103]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1233 = _T_1229 + _T_1231; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1235 = _T_1227 + _T_1233; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1237 = replaceSlot[104] + replaceSlot[105]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1239 = replaceSlot[106] + replaceSlot[107]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1241 = _T_1237 + _T_1239; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1243 = replaceSlot[108] + replaceSlot[109]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1245 = replaceSlot[110] + replaceSlot[111]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1247 = _T_1243 + _T_1245; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1249 = _T_1241 + _T_1247; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1251 = _T_1235 + _T_1249; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1253 = replaceSlot[112] + replaceSlot[113]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1255 = replaceSlot[114] + replaceSlot[115]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1257 = _T_1253 + _T_1255; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1259 = replaceSlot[116] + replaceSlot[117]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1261 = replaceSlot[118] + replaceSlot[119]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1263 = _T_1259 + _T_1261; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1265 = _T_1257 + _T_1263; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1267 = replaceSlot[120] + replaceSlot[121]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1269 = replaceSlot[122] + replaceSlot[123]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1271 = _T_1267 + _T_1269; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1273 = replaceSlot[124] + replaceSlot[125]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1275 = replaceSlot[126] + replaceSlot[127]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1277 = _T_1273 + _T_1275; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1279 = _T_1271 + _T_1277; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1281 = _T_1265 + _T_1279; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1283 = _T_1251 + _T_1281; // @[Bitwise.scala 48:55]
- wire [6:0] _T_1285 = _T_1221 + _T_1283; // @[Bitwise.scala 48:55]
- wire [7:0] _T_1287 = _T_1159 + _T_1285; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1289 = replaceSlot[128] + replaceSlot[129]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1291 = replaceSlot[130] + replaceSlot[131]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1293 = _T_1289 + _T_1291; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1295 = replaceSlot[132] + replaceSlot[133]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1297 = replaceSlot[134] + replaceSlot[135]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1299 = _T_1295 + _T_1297; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1301 = _T_1293 + _T_1299; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1303 = replaceSlot[136] + replaceSlot[137]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1305 = replaceSlot[138] + replaceSlot[139]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1307 = _T_1303 + _T_1305; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1309 = replaceSlot[140] + replaceSlot[141]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1311 = replaceSlot[142] + replaceSlot[143]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1313 = _T_1309 + _T_1311; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1315 = _T_1307 + _T_1313; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1317 = _T_1301 + _T_1315; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1319 = replaceSlot[144] + replaceSlot[145]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1321 = replaceSlot[146] + replaceSlot[147]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1323 = _T_1319 + _T_1321; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1325 = replaceSlot[148] + replaceSlot[149]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1327 = replaceSlot[150] + replaceSlot[151]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1329 = _T_1325 + _T_1327; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1331 = _T_1323 + _T_1329; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1333 = replaceSlot[152] + replaceSlot[153]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1335 = replaceSlot[154] + replaceSlot[155]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1337 = _T_1333 + _T_1335; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1339 = replaceSlot[156] + replaceSlot[157]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1341 = replaceSlot[158] + replaceSlot[159]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1343 = _T_1339 + _T_1341; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1345 = _T_1337 + _T_1343; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1347 = _T_1331 + _T_1345; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1349 = _T_1317 + _T_1347; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1351 = replaceSlot[160] + replaceSlot[161]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1353 = replaceSlot[162] + replaceSlot[163]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1355 = _T_1351 + _T_1353; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1357 = replaceSlot[164] + replaceSlot[165]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1359 = replaceSlot[166] + replaceSlot[167]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1361 = _T_1357 + _T_1359; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1363 = _T_1355 + _T_1361; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1365 = replaceSlot[168] + replaceSlot[169]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1367 = replaceSlot[170] + replaceSlot[171]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1369 = _T_1365 + _T_1367; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1371 = replaceSlot[172] + replaceSlot[173]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1373 = replaceSlot[174] + replaceSlot[175]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1375 = _T_1371 + _T_1373; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1377 = _T_1369 + _T_1375; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1379 = _T_1363 + _T_1377; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1381 = replaceSlot[176] + replaceSlot[177]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1383 = replaceSlot[178] + replaceSlot[179]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1385 = _T_1381 + _T_1383; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1387 = replaceSlot[180] + replaceSlot[181]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1389 = replaceSlot[182] + replaceSlot[183]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1391 = _T_1387 + _T_1389; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1393 = _T_1385 + _T_1391; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1395 = replaceSlot[184] + replaceSlot[185]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1397 = replaceSlot[186] + replaceSlot[187]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1399 = _T_1395 + _T_1397; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1401 = replaceSlot[188] + replaceSlot[189]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1403 = replaceSlot[190] + replaceSlot[191]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1405 = _T_1401 + _T_1403; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1407 = _T_1399 + _T_1405; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1409 = _T_1393 + _T_1407; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1411 = _T_1379 + _T_1409; // @[Bitwise.scala 48:55]
- wire [6:0] _T_1413 = _T_1349 + _T_1411; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1415 = replaceSlot[192] + replaceSlot[193]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1417 = replaceSlot[194] + replaceSlot[195]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1419 = _T_1415 + _T_1417; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1421 = replaceSlot[196] + replaceSlot[197]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1423 = replaceSlot[198] + replaceSlot[199]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1425 = _T_1421 + _T_1423; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1427 = _T_1419 + _T_1425; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1429 = replaceSlot[200] + replaceSlot[201]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1431 = replaceSlot[202] + replaceSlot[203]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1433 = _T_1429 + _T_1431; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1435 = replaceSlot[204] + replaceSlot[205]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1437 = replaceSlot[206] + replaceSlot[207]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1439 = _T_1435 + _T_1437; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1441 = _T_1433 + _T_1439; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1443 = _T_1427 + _T_1441; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1445 = replaceSlot[208] + replaceSlot[209]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1447 = replaceSlot[210] + replaceSlot[211]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1449 = _T_1445 + _T_1447; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1451 = replaceSlot[212] + replaceSlot[213]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1453 = replaceSlot[214] + replaceSlot[215]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1455 = _T_1451 + _T_1453; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1457 = _T_1449 + _T_1455; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1459 = replaceSlot[216] + replaceSlot[217]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1461 = replaceSlot[218] + replaceSlot[219]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1463 = _T_1459 + _T_1461; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1465 = replaceSlot[220] + replaceSlot[221]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1467 = replaceSlot[222] + replaceSlot[223]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1469 = _T_1465 + _T_1467; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1471 = _T_1463 + _T_1469; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1473 = _T_1457 + _T_1471; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1475 = _T_1443 + _T_1473; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1477 = replaceSlot[224] + replaceSlot[225]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1479 = replaceSlot[226] + replaceSlot[227]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1481 = _T_1477 + _T_1479; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1483 = replaceSlot[228] + replaceSlot[229]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1485 = replaceSlot[230] + replaceSlot[231]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1487 = _T_1483 + _T_1485; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1489 = _T_1481 + _T_1487; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1491 = replaceSlot[232] + replaceSlot[233]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1493 = replaceSlot[234] + replaceSlot[235]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1495 = _T_1491 + _T_1493; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1497 = replaceSlot[236] + replaceSlot[237]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1499 = replaceSlot[238] + replaceSlot[239]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1501 = _T_1497 + _T_1499; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1503 = _T_1495 + _T_1501; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1505 = _T_1489 + _T_1503; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1507 = replaceSlot[240] + replaceSlot[241]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1509 = replaceSlot[242] + replaceSlot[243]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1511 = _T_1507 + _T_1509; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1513 = replaceSlot[244] + replaceSlot[245]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1515 = replaceSlot[246] + replaceSlot[247]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1517 = _T_1513 + _T_1515; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1519 = _T_1511 + _T_1517; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1521 = replaceSlot[248] + replaceSlot[249]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1523 = replaceSlot[250] + replaceSlot[251]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1525 = _T_1521 + _T_1523; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1527 = replaceSlot[252] + replaceSlot[253]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1529 = replaceSlot[254] + replaceSlot[255]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1531 = _T_1527 + _T_1529; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1533 = _T_1525 + _T_1531; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1535 = _T_1519 + _T_1533; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1537 = _T_1505 + _T_1535; // @[Bitwise.scala 48:55]
- wire [6:0] _T_1539 = _T_1475 + _T_1537; // @[Bitwise.scala 48:55]
- wire [7:0] _T_1541 = _T_1413 + _T_1539; // @[Bitwise.scala 48:55]
- wire [8:0] _T_1543 = _T_1287 + _T_1541; // @[Bitwise.scala 48:55]
- wire found = matchSlot != 256'h0; // @[L1DCache.scala 391:25]
- wire [1:0] _replaceNum_2_T_1 = replaceSlot[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] _replaceNum_3_T_1 = replaceSlot[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [2:0] _replaceNum_4_T_1 = replaceSlot[4] ? 3'h4 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _replaceNum_5_T_1 = replaceSlot[5] ? 3'h5 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _replaceNum_6_T_1 = replaceSlot[6] ? 3'h6 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _replaceNum_7_T_1 = replaceSlot[7] ? 3'h7 : 3'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_8_T_1 = replaceSlot[8] ? 4'h8 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_9_T_1 = replaceSlot[9] ? 4'h9 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_10_T_1 = replaceSlot[10] ? 4'ha : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_11_T_1 = replaceSlot[11] ? 4'hb : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_12_T_1 = replaceSlot[12] ? 4'hc : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_13_T_1 = replaceSlot[13] ? 4'hd : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_14_T_1 = replaceSlot[14] ? 4'he : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_15_T_1 = replaceSlot[15] ? 4'hf : 4'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_16_T_1 = replaceSlot[16] ? 5'h10 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_17_T_1 = replaceSlot[17] ? 5'h11 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_18_T_1 = replaceSlot[18] ? 5'h12 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_19_T_1 = replaceSlot[19] ? 5'h13 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_20_T_1 = replaceSlot[20] ? 5'h14 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_21_T_1 = replaceSlot[21] ? 5'h15 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_22_T_1 = replaceSlot[22] ? 5'h16 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_23_T_1 = replaceSlot[23] ? 5'h17 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_24_T_1 = replaceSlot[24] ? 5'h18 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_25_T_1 = replaceSlot[25] ? 5'h19 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_26_T_1 = replaceSlot[26] ? 5'h1a : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_27_T_1 = replaceSlot[27] ? 5'h1b : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_28_T_1 = replaceSlot[28] ? 5'h1c : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_29_T_1 = replaceSlot[29] ? 5'h1d : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_30_T_1 = replaceSlot[30] ? 5'h1e : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_31_T_1 = replaceSlot[31] ? 5'h1f : 5'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_32_T_1 = replaceSlot[32] ? 6'h20 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_33_T_1 = replaceSlot[33] ? 6'h21 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_34_T_1 = replaceSlot[34] ? 6'h22 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_35_T_1 = replaceSlot[35] ? 6'h23 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_36_T_1 = replaceSlot[36] ? 6'h24 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_37_T_1 = replaceSlot[37] ? 6'h25 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_38_T_1 = replaceSlot[38] ? 6'h26 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_39_T_1 = replaceSlot[39] ? 6'h27 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_40_T_1 = replaceSlot[40] ? 6'h28 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_41_T_1 = replaceSlot[41] ? 6'h29 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_42_T_1 = replaceSlot[42] ? 6'h2a : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_43_T_1 = replaceSlot[43] ? 6'h2b : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_44_T_1 = replaceSlot[44] ? 6'h2c : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_45_T_1 = replaceSlot[45] ? 6'h2d : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_46_T_1 = replaceSlot[46] ? 6'h2e : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_47_T_1 = replaceSlot[47] ? 6'h2f : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_48_T_1 = replaceSlot[48] ? 6'h30 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_49_T_1 = replaceSlot[49] ? 6'h31 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_50_T_1 = replaceSlot[50] ? 6'h32 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_51_T_1 = replaceSlot[51] ? 6'h33 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_52_T_1 = replaceSlot[52] ? 6'h34 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_53_T_1 = replaceSlot[53] ? 6'h35 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_54_T_1 = replaceSlot[54] ? 6'h36 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_55_T_1 = replaceSlot[55] ? 6'h37 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_56_T_1 = replaceSlot[56] ? 6'h38 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_57_T_1 = replaceSlot[57] ? 6'h39 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_58_T_1 = replaceSlot[58] ? 6'h3a : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_59_T_1 = replaceSlot[59] ? 6'h3b : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_60_T_1 = replaceSlot[60] ? 6'h3c : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_61_T_1 = replaceSlot[61] ? 6'h3d : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_62_T_1 = replaceSlot[62] ? 6'h3e : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_63_T_1 = replaceSlot[63] ? 6'h3f : 6'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_64_T_1 = replaceSlot[64] ? 7'h40 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_65_T_1 = replaceSlot[65] ? 7'h41 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_66_T_1 = replaceSlot[66] ? 7'h42 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_67_T_1 = replaceSlot[67] ? 7'h43 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_68_T_1 = replaceSlot[68] ? 7'h44 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_69_T_1 = replaceSlot[69] ? 7'h45 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_70_T_1 = replaceSlot[70] ? 7'h46 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_71_T_1 = replaceSlot[71] ? 7'h47 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_72_T_1 = replaceSlot[72] ? 7'h48 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_73_T_1 = replaceSlot[73] ? 7'h49 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_74_T_1 = replaceSlot[74] ? 7'h4a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_75_T_1 = replaceSlot[75] ? 7'h4b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_76_T_1 = replaceSlot[76] ? 7'h4c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_77_T_1 = replaceSlot[77] ? 7'h4d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_78_T_1 = replaceSlot[78] ? 7'h4e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_79_T_1 = replaceSlot[79] ? 7'h4f : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_80_T_1 = replaceSlot[80] ? 7'h50 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_81_T_1 = replaceSlot[81] ? 7'h51 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_82_T_1 = replaceSlot[82] ? 7'h52 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_83_T_1 = replaceSlot[83] ? 7'h53 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_84_T_1 = replaceSlot[84] ? 7'h54 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_85_T_1 = replaceSlot[85] ? 7'h55 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_86_T_1 = replaceSlot[86] ? 7'h56 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_87_T_1 = replaceSlot[87] ? 7'h57 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_88_T_1 = replaceSlot[88] ? 7'h58 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_89_T_1 = replaceSlot[89] ? 7'h59 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_90_T_1 = replaceSlot[90] ? 7'h5a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_91_T_1 = replaceSlot[91] ? 7'h5b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_92_T_1 = replaceSlot[92] ? 7'h5c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_93_T_1 = replaceSlot[93] ? 7'h5d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_94_T_1 = replaceSlot[94] ? 7'h5e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_95_T_1 = replaceSlot[95] ? 7'h5f : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_96_T_1 = replaceSlot[96] ? 7'h60 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_97_T_1 = replaceSlot[97] ? 7'h61 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_98_T_1 = replaceSlot[98] ? 7'h62 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_99_T_1 = replaceSlot[99] ? 7'h63 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_100_T_1 = replaceSlot[100] ? 7'h64 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_101_T_1 = replaceSlot[101] ? 7'h65 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_102_T_1 = replaceSlot[102] ? 7'h66 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_103_T_1 = replaceSlot[103] ? 7'h67 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_104_T_1 = replaceSlot[104] ? 7'h68 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_105_T_1 = replaceSlot[105] ? 7'h69 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_106_T_1 = replaceSlot[106] ? 7'h6a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_107_T_1 = replaceSlot[107] ? 7'h6b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_108_T_1 = replaceSlot[108] ? 7'h6c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_109_T_1 = replaceSlot[109] ? 7'h6d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_110_T_1 = replaceSlot[110] ? 7'h6e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_111_T_1 = replaceSlot[111] ? 7'h6f : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_112_T_1 = replaceSlot[112] ? 7'h70 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_113_T_1 = replaceSlot[113] ? 7'h71 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_114_T_1 = replaceSlot[114] ? 7'h72 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_115_T_1 = replaceSlot[115] ? 7'h73 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_116_T_1 = replaceSlot[116] ? 7'h74 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_117_T_1 = replaceSlot[117] ? 7'h75 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_118_T_1 = replaceSlot[118] ? 7'h76 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_119_T_1 = replaceSlot[119] ? 7'h77 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_120_T_1 = replaceSlot[120] ? 7'h78 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_121_T_1 = replaceSlot[121] ? 7'h79 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_122_T_1 = replaceSlot[122] ? 7'h7a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_123_T_1 = replaceSlot[123] ? 7'h7b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_124_T_1 = replaceSlot[124] ? 7'h7c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_125_T_1 = replaceSlot[125] ? 7'h7d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_126_T_1 = replaceSlot[126] ? 7'h7e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_127_T_1 = replaceSlot[127] ? 7'h7f : 7'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_128 = replaceSlot[128] ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_129 = replaceSlot[129] ? 8'h81 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_130 = replaceSlot[130] ? 8'h82 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_131 = replaceSlot[131] ? 8'h83 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_132 = replaceSlot[132] ? 8'h84 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_133 = replaceSlot[133] ? 8'h85 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_134 = replaceSlot[134] ? 8'h86 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_135 = replaceSlot[135] ? 8'h87 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_136 = replaceSlot[136] ? 8'h88 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_137 = replaceSlot[137] ? 8'h89 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_138 = replaceSlot[138] ? 8'h8a : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_139 = replaceSlot[139] ? 8'h8b : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_140 = replaceSlot[140] ? 8'h8c : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_141 = replaceSlot[141] ? 8'h8d : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_142 = replaceSlot[142] ? 8'h8e : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_143 = replaceSlot[143] ? 8'h8f : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_144 = replaceSlot[144] ? 8'h90 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_145 = replaceSlot[145] ? 8'h91 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_146 = replaceSlot[146] ? 8'h92 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_147 = replaceSlot[147] ? 8'h93 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_148 = replaceSlot[148] ? 8'h94 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_149 = replaceSlot[149] ? 8'h95 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_150 = replaceSlot[150] ? 8'h96 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_151 = replaceSlot[151] ? 8'h97 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_152 = replaceSlot[152] ? 8'h98 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_153 = replaceSlot[153] ? 8'h99 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_154 = replaceSlot[154] ? 8'h9a : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_155 = replaceSlot[155] ? 8'h9b : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_156 = replaceSlot[156] ? 8'h9c : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_157 = replaceSlot[157] ? 8'h9d : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_158 = replaceSlot[158] ? 8'h9e : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_159 = replaceSlot[159] ? 8'h9f : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_160 = replaceSlot[160] ? 8'ha0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_161 = replaceSlot[161] ? 8'ha1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_162 = replaceSlot[162] ? 8'ha2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_163 = replaceSlot[163] ? 8'ha3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_164 = replaceSlot[164] ? 8'ha4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_165 = replaceSlot[165] ? 8'ha5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_166 = replaceSlot[166] ? 8'ha6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_167 = replaceSlot[167] ? 8'ha7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_168 = replaceSlot[168] ? 8'ha8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_169 = replaceSlot[169] ? 8'ha9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_170 = replaceSlot[170] ? 8'haa : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_171 = replaceSlot[171] ? 8'hab : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_172 = replaceSlot[172] ? 8'hac : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_173 = replaceSlot[173] ? 8'had : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_174 = replaceSlot[174] ? 8'hae : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_175 = replaceSlot[175] ? 8'haf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_176 = replaceSlot[176] ? 8'hb0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_177 = replaceSlot[177] ? 8'hb1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_178 = replaceSlot[178] ? 8'hb2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_179 = replaceSlot[179] ? 8'hb3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_180 = replaceSlot[180] ? 8'hb4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_181 = replaceSlot[181] ? 8'hb5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_182 = replaceSlot[182] ? 8'hb6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_183 = replaceSlot[183] ? 8'hb7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_184 = replaceSlot[184] ? 8'hb8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_185 = replaceSlot[185] ? 8'hb9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_186 = replaceSlot[186] ? 8'hba : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_187 = replaceSlot[187] ? 8'hbb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_188 = replaceSlot[188] ? 8'hbc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_189 = replaceSlot[189] ? 8'hbd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_190 = replaceSlot[190] ? 8'hbe : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_191 = replaceSlot[191] ? 8'hbf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_192 = replaceSlot[192] ? 8'hc0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_193 = replaceSlot[193] ? 8'hc1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_194 = replaceSlot[194] ? 8'hc2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_195 = replaceSlot[195] ? 8'hc3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_196 = replaceSlot[196] ? 8'hc4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_197 = replaceSlot[197] ? 8'hc5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_198 = replaceSlot[198] ? 8'hc6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_199 = replaceSlot[199] ? 8'hc7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_200 = replaceSlot[200] ? 8'hc8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_201 = replaceSlot[201] ? 8'hc9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_202 = replaceSlot[202] ? 8'hca : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_203 = replaceSlot[203] ? 8'hcb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_204 = replaceSlot[204] ? 8'hcc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_205 = replaceSlot[205] ? 8'hcd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_206 = replaceSlot[206] ? 8'hce : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_207 = replaceSlot[207] ? 8'hcf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_208 = replaceSlot[208] ? 8'hd0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_209 = replaceSlot[209] ? 8'hd1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_210 = replaceSlot[210] ? 8'hd2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_211 = replaceSlot[211] ? 8'hd3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_212 = replaceSlot[212] ? 8'hd4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_213 = replaceSlot[213] ? 8'hd5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_214 = replaceSlot[214] ? 8'hd6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_215 = replaceSlot[215] ? 8'hd7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_216 = replaceSlot[216] ? 8'hd8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_217 = replaceSlot[217] ? 8'hd9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_218 = replaceSlot[218] ? 8'hda : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_219 = replaceSlot[219] ? 8'hdb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_220 = replaceSlot[220] ? 8'hdc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_221 = replaceSlot[221] ? 8'hdd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_222 = replaceSlot[222] ? 8'hde : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_223 = replaceSlot[223] ? 8'hdf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_224 = replaceSlot[224] ? 8'he0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_225 = replaceSlot[225] ? 8'he1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_226 = replaceSlot[226] ? 8'he2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_227 = replaceSlot[227] ? 8'he3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_228 = replaceSlot[228] ? 8'he4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_229 = replaceSlot[229] ? 8'he5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_230 = replaceSlot[230] ? 8'he6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_231 = replaceSlot[231] ? 8'he7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_232 = replaceSlot[232] ? 8'he8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_233 = replaceSlot[233] ? 8'he9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_234 = replaceSlot[234] ? 8'hea : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_235 = replaceSlot[235] ? 8'heb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_236 = replaceSlot[236] ? 8'hec : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_237 = replaceSlot[237] ? 8'hed : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_238 = replaceSlot[238] ? 8'hee : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_239 = replaceSlot[239] ? 8'hef : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_240 = replaceSlot[240] ? 8'hf0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_241 = replaceSlot[241] ? 8'hf1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_242 = replaceSlot[242] ? 8'hf2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_243 = replaceSlot[243] ? 8'hf3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_244 = replaceSlot[244] ? 8'hf4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_245 = replaceSlot[245] ? 8'hf5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_246 = replaceSlot[246] ? 8'hf6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_247 = replaceSlot[247] ? 8'hf7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_248 = replaceSlot[248] ? 8'hf8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_249 = replaceSlot[249] ? 8'hf9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_250 = replaceSlot[250] ? 8'hfa : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_251 = replaceSlot[251] ? 8'hfb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_252 = replaceSlot[252] ? 8'hfc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_253 = replaceSlot[253] ? 8'hfd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_254 = replaceSlot[254] ? 8'hfe : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_255 = replaceSlot[255] ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_1 = {{7'd0}, replaceSlot[1]}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] replaceNum_2 = {{6'd0}, _replaceNum_2_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_2 = replaceNum_1 | replaceNum_2; // @[Library.scala 76:39]
- wire [7:0] replaceNum_3 = {{6'd0}, _replaceNum_3_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_3 = _replaceId_T_2 | replaceNum_3; // @[Library.scala 76:39]
- wire [7:0] replaceNum_4 = {{5'd0}, _replaceNum_4_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_4 = _replaceId_T_3 | replaceNum_4; // @[Library.scala 76:39]
- wire [7:0] replaceNum_5 = {{5'd0}, _replaceNum_5_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_5 = _replaceId_T_4 | replaceNum_5; // @[Library.scala 76:39]
- wire [7:0] replaceNum_6 = {{5'd0}, _replaceNum_6_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_6 = _replaceId_T_5 | replaceNum_6; // @[Library.scala 76:39]
- wire [7:0] replaceNum_7 = {{5'd0}, _replaceNum_7_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_7 = _replaceId_T_6 | replaceNum_7; // @[Library.scala 76:39]
- wire [7:0] replaceNum_8 = {{4'd0}, _replaceNum_8_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_8 = _replaceId_T_7 | replaceNum_8; // @[Library.scala 76:39]
- wire [7:0] replaceNum_9 = {{4'd0}, _replaceNum_9_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_9 = _replaceId_T_8 | replaceNum_9; // @[Library.scala 76:39]
- wire [7:0] replaceNum_10 = {{4'd0}, _replaceNum_10_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_10 = _replaceId_T_9 | replaceNum_10; // @[Library.scala 76:39]
- wire [7:0] replaceNum_11 = {{4'd0}, _replaceNum_11_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_11 = _replaceId_T_10 | replaceNum_11; // @[Library.scala 76:39]
- wire [7:0] replaceNum_12 = {{4'd0}, _replaceNum_12_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_12 = _replaceId_T_11 | replaceNum_12; // @[Library.scala 76:39]
- wire [7:0] replaceNum_13 = {{4'd0}, _replaceNum_13_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_13 = _replaceId_T_12 | replaceNum_13; // @[Library.scala 76:39]
- wire [7:0] replaceNum_14 = {{4'd0}, _replaceNum_14_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_14 = _replaceId_T_13 | replaceNum_14; // @[Library.scala 76:39]
- wire [7:0] replaceNum_15 = {{4'd0}, _replaceNum_15_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_15 = _replaceId_T_14 | replaceNum_15; // @[Library.scala 76:39]
- wire [7:0] replaceNum_16 = {{3'd0}, _replaceNum_16_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_16 = _replaceId_T_15 | replaceNum_16; // @[Library.scala 76:39]
- wire [7:0] replaceNum_17 = {{3'd0}, _replaceNum_17_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_17 = _replaceId_T_16 | replaceNum_17; // @[Library.scala 76:39]
- wire [7:0] replaceNum_18 = {{3'd0}, _replaceNum_18_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_18 = _replaceId_T_17 | replaceNum_18; // @[Library.scala 76:39]
- wire [7:0] replaceNum_19 = {{3'd0}, _replaceNum_19_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_19 = _replaceId_T_18 | replaceNum_19; // @[Library.scala 76:39]
- wire [7:0] replaceNum_20 = {{3'd0}, _replaceNum_20_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_20 = _replaceId_T_19 | replaceNum_20; // @[Library.scala 76:39]
- wire [7:0] replaceNum_21 = {{3'd0}, _replaceNum_21_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_21 = _replaceId_T_20 | replaceNum_21; // @[Library.scala 76:39]
- wire [7:0] replaceNum_22 = {{3'd0}, _replaceNum_22_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_22 = _replaceId_T_21 | replaceNum_22; // @[Library.scala 76:39]
- wire [7:0] replaceNum_23 = {{3'd0}, _replaceNum_23_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_23 = _replaceId_T_22 | replaceNum_23; // @[Library.scala 76:39]
- wire [7:0] replaceNum_24 = {{3'd0}, _replaceNum_24_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_24 = _replaceId_T_23 | replaceNum_24; // @[Library.scala 76:39]
- wire [7:0] replaceNum_25 = {{3'd0}, _replaceNum_25_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_25 = _replaceId_T_24 | replaceNum_25; // @[Library.scala 76:39]
- wire [7:0] replaceNum_26 = {{3'd0}, _replaceNum_26_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_26 = _replaceId_T_25 | replaceNum_26; // @[Library.scala 76:39]
- wire [7:0] replaceNum_27 = {{3'd0}, _replaceNum_27_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_27 = _replaceId_T_26 | replaceNum_27; // @[Library.scala 76:39]
- wire [7:0] replaceNum_28 = {{3'd0}, _replaceNum_28_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_28 = _replaceId_T_27 | replaceNum_28; // @[Library.scala 76:39]
- wire [7:0] replaceNum_29 = {{3'd0}, _replaceNum_29_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_29 = _replaceId_T_28 | replaceNum_29; // @[Library.scala 76:39]
- wire [7:0] replaceNum_30 = {{3'd0}, _replaceNum_30_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_30 = _replaceId_T_29 | replaceNum_30; // @[Library.scala 76:39]
- wire [7:0] replaceNum_31 = {{3'd0}, _replaceNum_31_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_31 = _replaceId_T_30 | replaceNum_31; // @[Library.scala 76:39]
- wire [7:0] replaceNum_32 = {{2'd0}, _replaceNum_32_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_32 = _replaceId_T_31 | replaceNum_32; // @[Library.scala 76:39]
- wire [7:0] replaceNum_33 = {{2'd0}, _replaceNum_33_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_33 = _replaceId_T_32 | replaceNum_33; // @[Library.scala 76:39]
- wire [7:0] replaceNum_34 = {{2'd0}, _replaceNum_34_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_34 = _replaceId_T_33 | replaceNum_34; // @[Library.scala 76:39]
- wire [7:0] replaceNum_35 = {{2'd0}, _replaceNum_35_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_35 = _replaceId_T_34 | replaceNum_35; // @[Library.scala 76:39]
- wire [7:0] replaceNum_36 = {{2'd0}, _replaceNum_36_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_36 = _replaceId_T_35 | replaceNum_36; // @[Library.scala 76:39]
- wire [7:0] replaceNum_37 = {{2'd0}, _replaceNum_37_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_37 = _replaceId_T_36 | replaceNum_37; // @[Library.scala 76:39]
- wire [7:0] replaceNum_38 = {{2'd0}, _replaceNum_38_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_38 = _replaceId_T_37 | replaceNum_38; // @[Library.scala 76:39]
- wire [7:0] replaceNum_39 = {{2'd0}, _replaceNum_39_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_39 = _replaceId_T_38 | replaceNum_39; // @[Library.scala 76:39]
- wire [7:0] replaceNum_40 = {{2'd0}, _replaceNum_40_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_40 = _replaceId_T_39 | replaceNum_40; // @[Library.scala 76:39]
- wire [7:0] replaceNum_41 = {{2'd0}, _replaceNum_41_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_41 = _replaceId_T_40 | replaceNum_41; // @[Library.scala 76:39]
- wire [7:0] replaceNum_42 = {{2'd0}, _replaceNum_42_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_42 = _replaceId_T_41 | replaceNum_42; // @[Library.scala 76:39]
- wire [7:0] replaceNum_43 = {{2'd0}, _replaceNum_43_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_43 = _replaceId_T_42 | replaceNum_43; // @[Library.scala 76:39]
- wire [7:0] replaceNum_44 = {{2'd0}, _replaceNum_44_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_44 = _replaceId_T_43 | replaceNum_44; // @[Library.scala 76:39]
- wire [7:0] replaceNum_45 = {{2'd0}, _replaceNum_45_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_45 = _replaceId_T_44 | replaceNum_45; // @[Library.scala 76:39]
- wire [7:0] replaceNum_46 = {{2'd0}, _replaceNum_46_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_46 = _replaceId_T_45 | replaceNum_46; // @[Library.scala 76:39]
- wire [7:0] replaceNum_47 = {{2'd0}, _replaceNum_47_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_47 = _replaceId_T_46 | replaceNum_47; // @[Library.scala 76:39]
- wire [7:0] replaceNum_48 = {{2'd0}, _replaceNum_48_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_48 = _replaceId_T_47 | replaceNum_48; // @[Library.scala 76:39]
- wire [7:0] replaceNum_49 = {{2'd0}, _replaceNum_49_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_49 = _replaceId_T_48 | replaceNum_49; // @[Library.scala 76:39]
- wire [7:0] replaceNum_50 = {{2'd0}, _replaceNum_50_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_50 = _replaceId_T_49 | replaceNum_50; // @[Library.scala 76:39]
- wire [7:0] replaceNum_51 = {{2'd0}, _replaceNum_51_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_51 = _replaceId_T_50 | replaceNum_51; // @[Library.scala 76:39]
- wire [7:0] replaceNum_52 = {{2'd0}, _replaceNum_52_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_52 = _replaceId_T_51 | replaceNum_52; // @[Library.scala 76:39]
- wire [7:0] replaceNum_53 = {{2'd0}, _replaceNum_53_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_53 = _replaceId_T_52 | replaceNum_53; // @[Library.scala 76:39]
- wire [7:0] replaceNum_54 = {{2'd0}, _replaceNum_54_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_54 = _replaceId_T_53 | replaceNum_54; // @[Library.scala 76:39]
- wire [7:0] replaceNum_55 = {{2'd0}, _replaceNum_55_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_55 = _replaceId_T_54 | replaceNum_55; // @[Library.scala 76:39]
- wire [7:0] replaceNum_56 = {{2'd0}, _replaceNum_56_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_56 = _replaceId_T_55 | replaceNum_56; // @[Library.scala 76:39]
- wire [7:0] replaceNum_57 = {{2'd0}, _replaceNum_57_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_57 = _replaceId_T_56 | replaceNum_57; // @[Library.scala 76:39]
- wire [7:0] replaceNum_58 = {{2'd0}, _replaceNum_58_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_58 = _replaceId_T_57 | replaceNum_58; // @[Library.scala 76:39]
- wire [7:0] replaceNum_59 = {{2'd0}, _replaceNum_59_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_59 = _replaceId_T_58 | replaceNum_59; // @[Library.scala 76:39]
- wire [7:0] replaceNum_60 = {{2'd0}, _replaceNum_60_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_60 = _replaceId_T_59 | replaceNum_60; // @[Library.scala 76:39]
- wire [7:0] replaceNum_61 = {{2'd0}, _replaceNum_61_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_61 = _replaceId_T_60 | replaceNum_61; // @[Library.scala 76:39]
- wire [7:0] replaceNum_62 = {{2'd0}, _replaceNum_62_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_62 = _replaceId_T_61 | replaceNum_62; // @[Library.scala 76:39]
- wire [7:0] replaceNum_63 = {{2'd0}, _replaceNum_63_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_63 = _replaceId_T_62 | replaceNum_63; // @[Library.scala 76:39]
- wire [7:0] replaceNum_64 = {{1'd0}, _replaceNum_64_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_64 = _replaceId_T_63 | replaceNum_64; // @[Library.scala 76:39]
- wire [7:0] replaceNum_65 = {{1'd0}, _replaceNum_65_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_65 = _replaceId_T_64 | replaceNum_65; // @[Library.scala 76:39]
- wire [7:0] replaceNum_66 = {{1'd0}, _replaceNum_66_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_66 = _replaceId_T_65 | replaceNum_66; // @[Library.scala 76:39]
- wire [7:0] replaceNum_67 = {{1'd0}, _replaceNum_67_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_67 = _replaceId_T_66 | replaceNum_67; // @[Library.scala 76:39]
- wire [7:0] replaceNum_68 = {{1'd0}, _replaceNum_68_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_68 = _replaceId_T_67 | replaceNum_68; // @[Library.scala 76:39]
- wire [7:0] replaceNum_69 = {{1'd0}, _replaceNum_69_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_69 = _replaceId_T_68 | replaceNum_69; // @[Library.scala 76:39]
- wire [7:0] replaceNum_70 = {{1'd0}, _replaceNum_70_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_70 = _replaceId_T_69 | replaceNum_70; // @[Library.scala 76:39]
- wire [7:0] replaceNum_71 = {{1'd0}, _replaceNum_71_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_71 = _replaceId_T_70 | replaceNum_71; // @[Library.scala 76:39]
- wire [7:0] replaceNum_72 = {{1'd0}, _replaceNum_72_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_72 = _replaceId_T_71 | replaceNum_72; // @[Library.scala 76:39]
- wire [7:0] replaceNum_73 = {{1'd0}, _replaceNum_73_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_73 = _replaceId_T_72 | replaceNum_73; // @[Library.scala 76:39]
- wire [7:0] replaceNum_74 = {{1'd0}, _replaceNum_74_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_74 = _replaceId_T_73 | replaceNum_74; // @[Library.scala 76:39]
- wire [7:0] replaceNum_75 = {{1'd0}, _replaceNum_75_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_75 = _replaceId_T_74 | replaceNum_75; // @[Library.scala 76:39]
- wire [7:0] replaceNum_76 = {{1'd0}, _replaceNum_76_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_76 = _replaceId_T_75 | replaceNum_76; // @[Library.scala 76:39]
- wire [7:0] replaceNum_77 = {{1'd0}, _replaceNum_77_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_77 = _replaceId_T_76 | replaceNum_77; // @[Library.scala 76:39]
- wire [7:0] replaceNum_78 = {{1'd0}, _replaceNum_78_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_78 = _replaceId_T_77 | replaceNum_78; // @[Library.scala 76:39]
- wire [7:0] replaceNum_79 = {{1'd0}, _replaceNum_79_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_79 = _replaceId_T_78 | replaceNum_79; // @[Library.scala 76:39]
- wire [7:0] replaceNum_80 = {{1'd0}, _replaceNum_80_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_80 = _replaceId_T_79 | replaceNum_80; // @[Library.scala 76:39]
- wire [7:0] replaceNum_81 = {{1'd0}, _replaceNum_81_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_81 = _replaceId_T_80 | replaceNum_81; // @[Library.scala 76:39]
- wire [7:0] replaceNum_82 = {{1'd0}, _replaceNum_82_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_82 = _replaceId_T_81 | replaceNum_82; // @[Library.scala 76:39]
- wire [7:0] replaceNum_83 = {{1'd0}, _replaceNum_83_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_83 = _replaceId_T_82 | replaceNum_83; // @[Library.scala 76:39]
- wire [7:0] replaceNum_84 = {{1'd0}, _replaceNum_84_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_84 = _replaceId_T_83 | replaceNum_84; // @[Library.scala 76:39]
- wire [7:0] replaceNum_85 = {{1'd0}, _replaceNum_85_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_85 = _replaceId_T_84 | replaceNum_85; // @[Library.scala 76:39]
- wire [7:0] replaceNum_86 = {{1'd0}, _replaceNum_86_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_86 = _replaceId_T_85 | replaceNum_86; // @[Library.scala 76:39]
- wire [7:0] replaceNum_87 = {{1'd0}, _replaceNum_87_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_87 = _replaceId_T_86 | replaceNum_87; // @[Library.scala 76:39]
- wire [7:0] replaceNum_88 = {{1'd0}, _replaceNum_88_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_88 = _replaceId_T_87 | replaceNum_88; // @[Library.scala 76:39]
- wire [7:0] replaceNum_89 = {{1'd0}, _replaceNum_89_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_89 = _replaceId_T_88 | replaceNum_89; // @[Library.scala 76:39]
- wire [7:0] replaceNum_90 = {{1'd0}, _replaceNum_90_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_90 = _replaceId_T_89 | replaceNum_90; // @[Library.scala 76:39]
- wire [7:0] replaceNum_91 = {{1'd0}, _replaceNum_91_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_91 = _replaceId_T_90 | replaceNum_91; // @[Library.scala 76:39]
- wire [7:0] replaceNum_92 = {{1'd0}, _replaceNum_92_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_92 = _replaceId_T_91 | replaceNum_92; // @[Library.scala 76:39]
- wire [7:0] replaceNum_93 = {{1'd0}, _replaceNum_93_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_93 = _replaceId_T_92 | replaceNum_93; // @[Library.scala 76:39]
- wire [7:0] replaceNum_94 = {{1'd0}, _replaceNum_94_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_94 = _replaceId_T_93 | replaceNum_94; // @[Library.scala 76:39]
- wire [7:0] replaceNum_95 = {{1'd0}, _replaceNum_95_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_95 = _replaceId_T_94 | replaceNum_95; // @[Library.scala 76:39]
- wire [7:0] replaceNum_96 = {{1'd0}, _replaceNum_96_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_96 = _replaceId_T_95 | replaceNum_96; // @[Library.scala 76:39]
- wire [7:0] replaceNum_97 = {{1'd0}, _replaceNum_97_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_97 = _replaceId_T_96 | replaceNum_97; // @[Library.scala 76:39]
- wire [7:0] replaceNum_98 = {{1'd0}, _replaceNum_98_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_98 = _replaceId_T_97 | replaceNum_98; // @[Library.scala 76:39]
- wire [7:0] replaceNum_99 = {{1'd0}, _replaceNum_99_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_99 = _replaceId_T_98 | replaceNum_99; // @[Library.scala 76:39]
- wire [7:0] replaceNum_100 = {{1'd0}, _replaceNum_100_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_100 = _replaceId_T_99 | replaceNum_100; // @[Library.scala 76:39]
- wire [7:0] replaceNum_101 = {{1'd0}, _replaceNum_101_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_101 = _replaceId_T_100 | replaceNum_101; // @[Library.scala 76:39]
- wire [7:0] replaceNum_102 = {{1'd0}, _replaceNum_102_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_102 = _replaceId_T_101 | replaceNum_102; // @[Library.scala 76:39]
- wire [7:0] replaceNum_103 = {{1'd0}, _replaceNum_103_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_103 = _replaceId_T_102 | replaceNum_103; // @[Library.scala 76:39]
- wire [7:0] replaceNum_104 = {{1'd0}, _replaceNum_104_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_104 = _replaceId_T_103 | replaceNum_104; // @[Library.scala 76:39]
- wire [7:0] replaceNum_105 = {{1'd0}, _replaceNum_105_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_105 = _replaceId_T_104 | replaceNum_105; // @[Library.scala 76:39]
- wire [7:0] replaceNum_106 = {{1'd0}, _replaceNum_106_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_106 = _replaceId_T_105 | replaceNum_106; // @[Library.scala 76:39]
- wire [7:0] replaceNum_107 = {{1'd0}, _replaceNum_107_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_107 = _replaceId_T_106 | replaceNum_107; // @[Library.scala 76:39]
- wire [7:0] replaceNum_108 = {{1'd0}, _replaceNum_108_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_108 = _replaceId_T_107 | replaceNum_108; // @[Library.scala 76:39]
- wire [7:0] replaceNum_109 = {{1'd0}, _replaceNum_109_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_109 = _replaceId_T_108 | replaceNum_109; // @[Library.scala 76:39]
- wire [7:0] replaceNum_110 = {{1'd0}, _replaceNum_110_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_110 = _replaceId_T_109 | replaceNum_110; // @[Library.scala 76:39]
- wire [7:0] replaceNum_111 = {{1'd0}, _replaceNum_111_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_111 = _replaceId_T_110 | replaceNum_111; // @[Library.scala 76:39]
- wire [7:0] replaceNum_112 = {{1'd0}, _replaceNum_112_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_112 = _replaceId_T_111 | replaceNum_112; // @[Library.scala 76:39]
- wire [7:0] replaceNum_113 = {{1'd0}, _replaceNum_113_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_113 = _replaceId_T_112 | replaceNum_113; // @[Library.scala 76:39]
- wire [7:0] replaceNum_114 = {{1'd0}, _replaceNum_114_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_114 = _replaceId_T_113 | replaceNum_114; // @[Library.scala 76:39]
- wire [7:0] replaceNum_115 = {{1'd0}, _replaceNum_115_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_115 = _replaceId_T_114 | replaceNum_115; // @[Library.scala 76:39]
- wire [7:0] replaceNum_116 = {{1'd0}, _replaceNum_116_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_116 = _replaceId_T_115 | replaceNum_116; // @[Library.scala 76:39]
- wire [7:0] replaceNum_117 = {{1'd0}, _replaceNum_117_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_117 = _replaceId_T_116 | replaceNum_117; // @[Library.scala 76:39]
- wire [7:0] replaceNum_118 = {{1'd0}, _replaceNum_118_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_118 = _replaceId_T_117 | replaceNum_118; // @[Library.scala 76:39]
- wire [7:0] replaceNum_119 = {{1'd0}, _replaceNum_119_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_119 = _replaceId_T_118 | replaceNum_119; // @[Library.scala 76:39]
- wire [7:0] replaceNum_120 = {{1'd0}, _replaceNum_120_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_120 = _replaceId_T_119 | replaceNum_120; // @[Library.scala 76:39]
- wire [7:0] replaceNum_121 = {{1'd0}, _replaceNum_121_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_121 = _replaceId_T_120 | replaceNum_121; // @[Library.scala 76:39]
- wire [7:0] replaceNum_122 = {{1'd0}, _replaceNum_122_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_122 = _replaceId_T_121 | replaceNum_122; // @[Library.scala 76:39]
- wire [7:0] replaceNum_123 = {{1'd0}, _replaceNum_123_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_123 = _replaceId_T_122 | replaceNum_123; // @[Library.scala 76:39]
- wire [7:0] replaceNum_124 = {{1'd0}, _replaceNum_124_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_124 = _replaceId_T_123 | replaceNum_124; // @[Library.scala 76:39]
- wire [7:0] replaceNum_125 = {{1'd0}, _replaceNum_125_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_125 = _replaceId_T_124 | replaceNum_125; // @[Library.scala 76:39]
- wire [7:0] replaceNum_126 = {{1'd0}, _replaceNum_126_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_126 = _replaceId_T_125 | replaceNum_126; // @[Library.scala 76:39]
- wire [7:0] replaceNum_127 = {{1'd0}, _replaceNum_127_T_1}; // @[L1DCache.scala 393:24 395:19]
- wire [7:0] _replaceId_T_127 = _replaceId_T_126 | replaceNum_127; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_128 = _replaceId_T_127 | replaceNum_128; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_129 = _replaceId_T_128 | replaceNum_129; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_130 = _replaceId_T_129 | replaceNum_130; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_131 = _replaceId_T_130 | replaceNum_131; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_132 = _replaceId_T_131 | replaceNum_132; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_133 = _replaceId_T_132 | replaceNum_133; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_134 = _replaceId_T_133 | replaceNum_134; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_135 = _replaceId_T_134 | replaceNum_135; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_136 = _replaceId_T_135 | replaceNum_136; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_137 = _replaceId_T_136 | replaceNum_137; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_138 = _replaceId_T_137 | replaceNum_138; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_139 = _replaceId_T_138 | replaceNum_139; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_140 = _replaceId_T_139 | replaceNum_140; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_141 = _replaceId_T_140 | replaceNum_141; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_142 = _replaceId_T_141 | replaceNum_142; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_143 = _replaceId_T_142 | replaceNum_143; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_144 = _replaceId_T_143 | replaceNum_144; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_145 = _replaceId_T_144 | replaceNum_145; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_146 = _replaceId_T_145 | replaceNum_146; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_147 = _replaceId_T_146 | replaceNum_147; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_148 = _replaceId_T_147 | replaceNum_148; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_149 = _replaceId_T_148 | replaceNum_149; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_150 = _replaceId_T_149 | replaceNum_150; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_151 = _replaceId_T_150 | replaceNum_151; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_152 = _replaceId_T_151 | replaceNum_152; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_153 = _replaceId_T_152 | replaceNum_153; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_154 = _replaceId_T_153 | replaceNum_154; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_155 = _replaceId_T_154 | replaceNum_155; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_156 = _replaceId_T_155 | replaceNum_156; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_157 = _replaceId_T_156 | replaceNum_157; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_158 = _replaceId_T_157 | replaceNum_158; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_159 = _replaceId_T_158 | replaceNum_159; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_160 = _replaceId_T_159 | replaceNum_160; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_161 = _replaceId_T_160 | replaceNum_161; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_162 = _replaceId_T_161 | replaceNum_162; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_163 = _replaceId_T_162 | replaceNum_163; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_164 = _replaceId_T_163 | replaceNum_164; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_165 = _replaceId_T_164 | replaceNum_165; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_166 = _replaceId_T_165 | replaceNum_166; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_167 = _replaceId_T_166 | replaceNum_167; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_168 = _replaceId_T_167 | replaceNum_168; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_169 = _replaceId_T_168 | replaceNum_169; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_170 = _replaceId_T_169 | replaceNum_170; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_171 = _replaceId_T_170 | replaceNum_171; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_172 = _replaceId_T_171 | replaceNum_172; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_173 = _replaceId_T_172 | replaceNum_173; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_174 = _replaceId_T_173 | replaceNum_174; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_175 = _replaceId_T_174 | replaceNum_175; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_176 = _replaceId_T_175 | replaceNum_176; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_177 = _replaceId_T_176 | replaceNum_177; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_178 = _replaceId_T_177 | replaceNum_178; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_179 = _replaceId_T_178 | replaceNum_179; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_180 = _replaceId_T_179 | replaceNum_180; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_181 = _replaceId_T_180 | replaceNum_181; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_182 = _replaceId_T_181 | replaceNum_182; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_183 = _replaceId_T_182 | replaceNum_183; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_184 = _replaceId_T_183 | replaceNum_184; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_185 = _replaceId_T_184 | replaceNum_185; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_186 = _replaceId_T_185 | replaceNum_186; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_187 = _replaceId_T_186 | replaceNum_187; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_188 = _replaceId_T_187 | replaceNum_188; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_189 = _replaceId_T_188 | replaceNum_189; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_190 = _replaceId_T_189 | replaceNum_190; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_191 = _replaceId_T_190 | replaceNum_191; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_192 = _replaceId_T_191 | replaceNum_192; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_193 = _replaceId_T_192 | replaceNum_193; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_194 = _replaceId_T_193 | replaceNum_194; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_195 = _replaceId_T_194 | replaceNum_195; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_196 = _replaceId_T_195 | replaceNum_196; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_197 = _replaceId_T_196 | replaceNum_197; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_198 = _replaceId_T_197 | replaceNum_198; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_199 = _replaceId_T_198 | replaceNum_199; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_200 = _replaceId_T_199 | replaceNum_200; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_201 = _replaceId_T_200 | replaceNum_201; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_202 = _replaceId_T_201 | replaceNum_202; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_203 = _replaceId_T_202 | replaceNum_203; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_204 = _replaceId_T_203 | replaceNum_204; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_205 = _replaceId_T_204 | replaceNum_205; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_206 = _replaceId_T_205 | replaceNum_206; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_207 = _replaceId_T_206 | replaceNum_207; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_208 = _replaceId_T_207 | replaceNum_208; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_209 = _replaceId_T_208 | replaceNum_209; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_210 = _replaceId_T_209 | replaceNum_210; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_211 = _replaceId_T_210 | replaceNum_211; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_212 = _replaceId_T_211 | replaceNum_212; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_213 = _replaceId_T_212 | replaceNum_213; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_214 = _replaceId_T_213 | replaceNum_214; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_215 = _replaceId_T_214 | replaceNum_215; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_216 = _replaceId_T_215 | replaceNum_216; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_217 = _replaceId_T_216 | replaceNum_217; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_218 = _replaceId_T_217 | replaceNum_218; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_219 = _replaceId_T_218 | replaceNum_219; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_220 = _replaceId_T_219 | replaceNum_220; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_221 = _replaceId_T_220 | replaceNum_221; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_222 = _replaceId_T_221 | replaceNum_222; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_223 = _replaceId_T_222 | replaceNum_223; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_224 = _replaceId_T_223 | replaceNum_224; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_225 = _replaceId_T_224 | replaceNum_225; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_226 = _replaceId_T_225 | replaceNum_226; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_227 = _replaceId_T_226 | replaceNum_227; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_228 = _replaceId_T_227 | replaceNum_228; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_229 = _replaceId_T_228 | replaceNum_229; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_230 = _replaceId_T_229 | replaceNum_230; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_231 = _replaceId_T_230 | replaceNum_231; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_232 = _replaceId_T_231 | replaceNum_232; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_233 = _replaceId_T_232 | replaceNum_233; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_234 = _replaceId_T_233 | replaceNum_234; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_235 = _replaceId_T_234 | replaceNum_235; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_236 = _replaceId_T_235 | replaceNum_236; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_237 = _replaceId_T_236 | replaceNum_237; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_238 = _replaceId_T_237 | replaceNum_238; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_239 = _replaceId_T_238 | replaceNum_239; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_240 = _replaceId_T_239 | replaceNum_240; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_241 = _replaceId_T_240 | replaceNum_241; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_242 = _replaceId_T_241 | replaceNum_242; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_243 = _replaceId_T_242 | replaceNum_243; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_244 = _replaceId_T_243 | replaceNum_244; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_245 = _replaceId_T_244 | replaceNum_245; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_246 = _replaceId_T_245 | replaceNum_246; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_247 = _replaceId_T_246 | replaceNum_247; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_248 = _replaceId_T_247 | replaceNum_248; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_249 = _replaceId_T_248 | replaceNum_249; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_250 = _replaceId_T_249 | replaceNum_250; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_251 = _replaceId_T_250 | replaceNum_251; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_252 = _replaceId_T_251 | replaceNum_252; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_253 = _replaceId_T_252 | replaceNum_253; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_254 = _replaceId_T_253 | replaceNum_254; // @[Library.scala 76:39]
- wire [7:0] replaceId = _replaceId_T_254 | replaceNum_255; // @[Library.scala 76:39]
- wire [1:0] _readNum_2_T = matchSlotB_2 ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] _readNum_3_T = matchSlotB_3 ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [2:0] _readNum_4_T = matchSlotB_4 ? 3'h4 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _readNum_5_T = matchSlotB_5 ? 3'h5 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _readNum_6_T = matchSlotB_6 ? 3'h6 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _readNum_7_T = matchSlotB_7 ? 3'h7 : 3'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_8_T = matchSlotB_8 ? 4'h8 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_9_T = matchSlotB_9 ? 4'h9 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_10_T = matchSlotB_10 ? 4'ha : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_11_T = matchSlotB_11 ? 4'hb : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_12_T = matchSlotB_12 ? 4'hc : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_13_T = matchSlotB_13 ? 4'hd : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_14_T = matchSlotB_14 ? 4'he : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_15_T = matchSlotB_15 ? 4'hf : 4'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_16_T = matchSlotB_16 ? 5'h10 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_17_T = matchSlotB_17 ? 5'h11 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_18_T = matchSlotB_18 ? 5'h12 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_19_T = matchSlotB_19 ? 5'h13 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_20_T = matchSlotB_20 ? 5'h14 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_21_T = matchSlotB_21 ? 5'h15 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_22_T = matchSlotB_22 ? 5'h16 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_23_T = matchSlotB_23 ? 5'h17 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_24_T = matchSlotB_24 ? 5'h18 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_25_T = matchSlotB_25 ? 5'h19 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_26_T = matchSlotB_26 ? 5'h1a : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_27_T = matchSlotB_27 ? 5'h1b : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_28_T = matchSlotB_28 ? 5'h1c : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_29_T = matchSlotB_29 ? 5'h1d : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_30_T = matchSlotB_30 ? 5'h1e : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_31_T = matchSlotB_31 ? 5'h1f : 5'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_32_T = matchSlotB_32 ? 6'h20 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_33_T = matchSlotB_33 ? 6'h21 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_34_T = matchSlotB_34 ? 6'h22 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_35_T = matchSlotB_35 ? 6'h23 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_36_T = matchSlotB_36 ? 6'h24 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_37_T = matchSlotB_37 ? 6'h25 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_38_T = matchSlotB_38 ? 6'h26 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_39_T = matchSlotB_39 ? 6'h27 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_40_T = matchSlotB_40 ? 6'h28 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_41_T = matchSlotB_41 ? 6'h29 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_42_T = matchSlotB_42 ? 6'h2a : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_43_T = matchSlotB_43 ? 6'h2b : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_44_T = matchSlotB_44 ? 6'h2c : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_45_T = matchSlotB_45 ? 6'h2d : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_46_T = matchSlotB_46 ? 6'h2e : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_47_T = matchSlotB_47 ? 6'h2f : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_48_T = matchSlotB_48 ? 6'h30 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_49_T = matchSlotB_49 ? 6'h31 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_50_T = matchSlotB_50 ? 6'h32 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_51_T = matchSlotB_51 ? 6'h33 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_52_T = matchSlotB_52 ? 6'h34 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_53_T = matchSlotB_53 ? 6'h35 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_54_T = matchSlotB_54 ? 6'h36 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_55_T = matchSlotB_55 ? 6'h37 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_56_T = matchSlotB_56 ? 6'h38 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_57_T = matchSlotB_57 ? 6'h39 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_58_T = matchSlotB_58 ? 6'h3a : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_59_T = matchSlotB_59 ? 6'h3b : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_60_T = matchSlotB_60 ? 6'h3c : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_61_T = matchSlotB_61 ? 6'h3d : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_62_T = matchSlotB_62 ? 6'h3e : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_63_T = matchSlotB_63 ? 6'h3f : 6'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_64_T = matchSlotB_64 ? 7'h40 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_65_T = matchSlotB_65 ? 7'h41 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_66_T = matchSlotB_66 ? 7'h42 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_67_T = matchSlotB_67 ? 7'h43 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_68_T = matchSlotB_68 ? 7'h44 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_69_T = matchSlotB_69 ? 7'h45 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_70_T = matchSlotB_70 ? 7'h46 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_71_T = matchSlotB_71 ? 7'h47 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_72_T = matchSlotB_72 ? 7'h48 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_73_T = matchSlotB_73 ? 7'h49 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_74_T = matchSlotB_74 ? 7'h4a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_75_T = matchSlotB_75 ? 7'h4b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_76_T = matchSlotB_76 ? 7'h4c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_77_T = matchSlotB_77 ? 7'h4d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_78_T = matchSlotB_78 ? 7'h4e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_79_T = matchSlotB_79 ? 7'h4f : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_80_T = matchSlotB_80 ? 7'h50 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_81_T = matchSlotB_81 ? 7'h51 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_82_T = matchSlotB_82 ? 7'h52 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_83_T = matchSlotB_83 ? 7'h53 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_84_T = matchSlotB_84 ? 7'h54 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_85_T = matchSlotB_85 ? 7'h55 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_86_T = matchSlotB_86 ? 7'h56 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_87_T = matchSlotB_87 ? 7'h57 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_88_T = matchSlotB_88 ? 7'h58 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_89_T = matchSlotB_89 ? 7'h59 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_90_T = matchSlotB_90 ? 7'h5a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_91_T = matchSlotB_91 ? 7'h5b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_92_T = matchSlotB_92 ? 7'h5c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_93_T = matchSlotB_93 ? 7'h5d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_94_T = matchSlotB_94 ? 7'h5e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_95_T = matchSlotB_95 ? 7'h5f : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_96_T = matchSlotB_96 ? 7'h60 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_97_T = matchSlotB_97 ? 7'h61 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_98_T = matchSlotB_98 ? 7'h62 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_99_T = matchSlotB_99 ? 7'h63 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_100_T = matchSlotB_100 ? 7'h64 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_101_T = matchSlotB_101 ? 7'h65 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_102_T = matchSlotB_102 ? 7'h66 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_103_T = matchSlotB_103 ? 7'h67 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_104_T = matchSlotB_104 ? 7'h68 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_105_T = matchSlotB_105 ? 7'h69 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_106_T = matchSlotB_106 ? 7'h6a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_107_T = matchSlotB_107 ? 7'h6b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_108_T = matchSlotB_108 ? 7'h6c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_109_T = matchSlotB_109 ? 7'h6d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_110_T = matchSlotB_110 ? 7'h6e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_111_T = matchSlotB_111 ? 7'h6f : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_112_T = matchSlotB_112 ? 7'h70 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_113_T = matchSlotB_113 ? 7'h71 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_114_T = matchSlotB_114 ? 7'h72 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_115_T = matchSlotB_115 ? 7'h73 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_116_T = matchSlotB_116 ? 7'h74 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_117_T = matchSlotB_117 ? 7'h75 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_118_T = matchSlotB_118 ? 7'h76 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_119_T = matchSlotB_119 ? 7'h77 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_120_T = matchSlotB_120 ? 7'h78 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_121_T = matchSlotB_121 ? 7'h79 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_122_T = matchSlotB_122 ? 7'h7a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_123_T = matchSlotB_123 ? 7'h7b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_124_T = matchSlotB_124 ? 7'h7c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_125_T = matchSlotB_125 ? 7'h7d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_126_T = matchSlotB_126 ? 7'h7e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_127_T = matchSlotB_127 ? 7'h7f : 7'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_128 = matchSlotB_128 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_129 = matchSlotB_129 ? 8'h81 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_130 = matchSlotB_130 ? 8'h82 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_131 = matchSlotB_131 ? 8'h83 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_132 = matchSlotB_132 ? 8'h84 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_133 = matchSlotB_133 ? 8'h85 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_134 = matchSlotB_134 ? 8'h86 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_135 = matchSlotB_135 ? 8'h87 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_136 = matchSlotB_136 ? 8'h88 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_137 = matchSlotB_137 ? 8'h89 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_138 = matchSlotB_138 ? 8'h8a : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_139 = matchSlotB_139 ? 8'h8b : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_140 = matchSlotB_140 ? 8'h8c : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_141 = matchSlotB_141 ? 8'h8d : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_142 = matchSlotB_142 ? 8'h8e : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_143 = matchSlotB_143 ? 8'h8f : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_144 = matchSlotB_144 ? 8'h90 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_145 = matchSlotB_145 ? 8'h91 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_146 = matchSlotB_146 ? 8'h92 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_147 = matchSlotB_147 ? 8'h93 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_148 = matchSlotB_148 ? 8'h94 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_149 = matchSlotB_149 ? 8'h95 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_150 = matchSlotB_150 ? 8'h96 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_151 = matchSlotB_151 ? 8'h97 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_152 = matchSlotB_152 ? 8'h98 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_153 = matchSlotB_153 ? 8'h99 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_154 = matchSlotB_154 ? 8'h9a : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_155 = matchSlotB_155 ? 8'h9b : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_156 = matchSlotB_156 ? 8'h9c : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_157 = matchSlotB_157 ? 8'h9d : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_158 = matchSlotB_158 ? 8'h9e : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_159 = matchSlotB_159 ? 8'h9f : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_160 = matchSlotB_160 ? 8'ha0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_161 = matchSlotB_161 ? 8'ha1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_162 = matchSlotB_162 ? 8'ha2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_163 = matchSlotB_163 ? 8'ha3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_164 = matchSlotB_164 ? 8'ha4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_165 = matchSlotB_165 ? 8'ha5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_166 = matchSlotB_166 ? 8'ha6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_167 = matchSlotB_167 ? 8'ha7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_168 = matchSlotB_168 ? 8'ha8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_169 = matchSlotB_169 ? 8'ha9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_170 = matchSlotB_170 ? 8'haa : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_171 = matchSlotB_171 ? 8'hab : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_172 = matchSlotB_172 ? 8'hac : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_173 = matchSlotB_173 ? 8'had : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_174 = matchSlotB_174 ? 8'hae : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_175 = matchSlotB_175 ? 8'haf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_176 = matchSlotB_176 ? 8'hb0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_177 = matchSlotB_177 ? 8'hb1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_178 = matchSlotB_178 ? 8'hb2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_179 = matchSlotB_179 ? 8'hb3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_180 = matchSlotB_180 ? 8'hb4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_181 = matchSlotB_181 ? 8'hb5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_182 = matchSlotB_182 ? 8'hb6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_183 = matchSlotB_183 ? 8'hb7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_184 = matchSlotB_184 ? 8'hb8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_185 = matchSlotB_185 ? 8'hb9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_186 = matchSlotB_186 ? 8'hba : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_187 = matchSlotB_187 ? 8'hbb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_188 = matchSlotB_188 ? 8'hbc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_189 = matchSlotB_189 ? 8'hbd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_190 = matchSlotB_190 ? 8'hbe : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_191 = matchSlotB_191 ? 8'hbf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_192 = matchSlotB_192 ? 8'hc0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_193 = matchSlotB_193 ? 8'hc1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_194 = matchSlotB_194 ? 8'hc2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_195 = matchSlotB_195 ? 8'hc3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_196 = matchSlotB_196 ? 8'hc4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_197 = matchSlotB_197 ? 8'hc5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_198 = matchSlotB_198 ? 8'hc6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_199 = matchSlotB_199 ? 8'hc7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_200 = matchSlotB_200 ? 8'hc8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_201 = matchSlotB_201 ? 8'hc9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_202 = matchSlotB_202 ? 8'hca : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_203 = matchSlotB_203 ? 8'hcb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_204 = matchSlotB_204 ? 8'hcc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_205 = matchSlotB_205 ? 8'hcd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_206 = matchSlotB_206 ? 8'hce : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_207 = matchSlotB_207 ? 8'hcf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_208 = matchSlotB_208 ? 8'hd0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_209 = matchSlotB_209 ? 8'hd1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_210 = matchSlotB_210 ? 8'hd2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_211 = matchSlotB_211 ? 8'hd3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_212 = matchSlotB_212 ? 8'hd4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_213 = matchSlotB_213 ? 8'hd5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_214 = matchSlotB_214 ? 8'hd6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_215 = matchSlotB_215 ? 8'hd7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_216 = matchSlotB_216 ? 8'hd8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_217 = matchSlotB_217 ? 8'hd9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_218 = matchSlotB_218 ? 8'hda : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_219 = matchSlotB_219 ? 8'hdb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_220 = matchSlotB_220 ? 8'hdc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_221 = matchSlotB_221 ? 8'hdd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_222 = matchSlotB_222 ? 8'hde : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_223 = matchSlotB_223 ? 8'hdf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_224 = matchSlotB_224 ? 8'he0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_225 = matchSlotB_225 ? 8'he1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_226 = matchSlotB_226 ? 8'he2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_227 = matchSlotB_227 ? 8'he3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_228 = matchSlotB_228 ? 8'he4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_229 = matchSlotB_229 ? 8'he5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_230 = matchSlotB_230 ? 8'he6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_231 = matchSlotB_231 ? 8'he7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_232 = matchSlotB_232 ? 8'he8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_233 = matchSlotB_233 ? 8'he9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_234 = matchSlotB_234 ? 8'hea : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_235 = matchSlotB_235 ? 8'heb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_236 = matchSlotB_236 ? 8'hec : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_237 = matchSlotB_237 ? 8'hed : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_238 = matchSlotB_238 ? 8'hee : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_239 = matchSlotB_239 ? 8'hef : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_240 = matchSlotB_240 ? 8'hf0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_241 = matchSlotB_241 ? 8'hf1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_242 = matchSlotB_242 ? 8'hf2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_243 = matchSlotB_243 ? 8'hf3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_244 = matchSlotB_244 ? 8'hf4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_245 = matchSlotB_245 ? 8'hf5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_246 = matchSlotB_246 ? 8'hf6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_247 = matchSlotB_247 ? 8'hf7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_248 = matchSlotB_248 ? 8'hf8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_249 = matchSlotB_249 ? 8'hf9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_250 = matchSlotB_250 ? 8'hfa : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_251 = matchSlotB_251 ? 8'hfb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_252 = matchSlotB_252 ? 8'hfc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_253 = matchSlotB_253 ? 8'hfd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_254 = matchSlotB_254 ? 8'hfe : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_255 = matchSlotB_255 ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_1 = {{7'd0}, matchSlotB_1}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] readNum_2 = {{6'd0}, _readNum_2_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_2 = readNum_1 | readNum_2; // @[Library.scala 76:39]
- wire [7:0] readNum_3 = {{6'd0}, _readNum_3_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_3 = _foundId_T_2 | readNum_3; // @[Library.scala 76:39]
- wire [7:0] readNum_4 = {{5'd0}, _readNum_4_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_4 = _foundId_T_3 | readNum_4; // @[Library.scala 76:39]
- wire [7:0] readNum_5 = {{5'd0}, _readNum_5_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_5 = _foundId_T_4 | readNum_5; // @[Library.scala 76:39]
- wire [7:0] readNum_6 = {{5'd0}, _readNum_6_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_6 = _foundId_T_5 | readNum_6; // @[Library.scala 76:39]
- wire [7:0] readNum_7 = {{5'd0}, _readNum_7_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_7 = _foundId_T_6 | readNum_7; // @[Library.scala 76:39]
- wire [7:0] readNum_8 = {{4'd0}, _readNum_8_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_8 = _foundId_T_7 | readNum_8; // @[Library.scala 76:39]
- wire [7:0] readNum_9 = {{4'd0}, _readNum_9_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_9 = _foundId_T_8 | readNum_9; // @[Library.scala 76:39]
- wire [7:0] readNum_10 = {{4'd0}, _readNum_10_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_10 = _foundId_T_9 | readNum_10; // @[Library.scala 76:39]
- wire [7:0] readNum_11 = {{4'd0}, _readNum_11_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_11 = _foundId_T_10 | readNum_11; // @[Library.scala 76:39]
- wire [7:0] readNum_12 = {{4'd0}, _readNum_12_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_12 = _foundId_T_11 | readNum_12; // @[Library.scala 76:39]
- wire [7:0] readNum_13 = {{4'd0}, _readNum_13_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_13 = _foundId_T_12 | readNum_13; // @[Library.scala 76:39]
- wire [7:0] readNum_14 = {{4'd0}, _readNum_14_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_14 = _foundId_T_13 | readNum_14; // @[Library.scala 76:39]
- wire [7:0] readNum_15 = {{4'd0}, _readNum_15_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_15 = _foundId_T_14 | readNum_15; // @[Library.scala 76:39]
- wire [7:0] readNum_16 = {{3'd0}, _readNum_16_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_16 = _foundId_T_15 | readNum_16; // @[Library.scala 76:39]
- wire [7:0] readNum_17 = {{3'd0}, _readNum_17_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_17 = _foundId_T_16 | readNum_17; // @[Library.scala 76:39]
- wire [7:0] readNum_18 = {{3'd0}, _readNum_18_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_18 = _foundId_T_17 | readNum_18; // @[Library.scala 76:39]
- wire [7:0] readNum_19 = {{3'd0}, _readNum_19_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_19 = _foundId_T_18 | readNum_19; // @[Library.scala 76:39]
- wire [7:0] readNum_20 = {{3'd0}, _readNum_20_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_20 = _foundId_T_19 | readNum_20; // @[Library.scala 76:39]
- wire [7:0] readNum_21 = {{3'd0}, _readNum_21_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_21 = _foundId_T_20 | readNum_21; // @[Library.scala 76:39]
- wire [7:0] readNum_22 = {{3'd0}, _readNum_22_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_22 = _foundId_T_21 | readNum_22; // @[Library.scala 76:39]
- wire [7:0] readNum_23 = {{3'd0}, _readNum_23_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_23 = _foundId_T_22 | readNum_23; // @[Library.scala 76:39]
- wire [7:0] readNum_24 = {{3'd0}, _readNum_24_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_24 = _foundId_T_23 | readNum_24; // @[Library.scala 76:39]
- wire [7:0] readNum_25 = {{3'd0}, _readNum_25_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_25 = _foundId_T_24 | readNum_25; // @[Library.scala 76:39]
- wire [7:0] readNum_26 = {{3'd0}, _readNum_26_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_26 = _foundId_T_25 | readNum_26; // @[Library.scala 76:39]
- wire [7:0] readNum_27 = {{3'd0}, _readNum_27_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_27 = _foundId_T_26 | readNum_27; // @[Library.scala 76:39]
- wire [7:0] readNum_28 = {{3'd0}, _readNum_28_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_28 = _foundId_T_27 | readNum_28; // @[Library.scala 76:39]
- wire [7:0] readNum_29 = {{3'd0}, _readNum_29_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_29 = _foundId_T_28 | readNum_29; // @[Library.scala 76:39]
- wire [7:0] readNum_30 = {{3'd0}, _readNum_30_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_30 = _foundId_T_29 | readNum_30; // @[Library.scala 76:39]
- wire [7:0] readNum_31 = {{3'd0}, _readNum_31_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_31 = _foundId_T_30 | readNum_31; // @[Library.scala 76:39]
- wire [7:0] readNum_32 = {{2'd0}, _readNum_32_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_32 = _foundId_T_31 | readNum_32; // @[Library.scala 76:39]
- wire [7:0] readNum_33 = {{2'd0}, _readNum_33_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_33 = _foundId_T_32 | readNum_33; // @[Library.scala 76:39]
- wire [7:0] readNum_34 = {{2'd0}, _readNum_34_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_34 = _foundId_T_33 | readNum_34; // @[Library.scala 76:39]
- wire [7:0] readNum_35 = {{2'd0}, _readNum_35_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_35 = _foundId_T_34 | readNum_35; // @[Library.scala 76:39]
- wire [7:0] readNum_36 = {{2'd0}, _readNum_36_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_36 = _foundId_T_35 | readNum_36; // @[Library.scala 76:39]
- wire [7:0] readNum_37 = {{2'd0}, _readNum_37_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_37 = _foundId_T_36 | readNum_37; // @[Library.scala 76:39]
- wire [7:0] readNum_38 = {{2'd0}, _readNum_38_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_38 = _foundId_T_37 | readNum_38; // @[Library.scala 76:39]
- wire [7:0] readNum_39 = {{2'd0}, _readNum_39_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_39 = _foundId_T_38 | readNum_39; // @[Library.scala 76:39]
- wire [7:0] readNum_40 = {{2'd0}, _readNum_40_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_40 = _foundId_T_39 | readNum_40; // @[Library.scala 76:39]
- wire [7:0] readNum_41 = {{2'd0}, _readNum_41_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_41 = _foundId_T_40 | readNum_41; // @[Library.scala 76:39]
- wire [7:0] readNum_42 = {{2'd0}, _readNum_42_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_42 = _foundId_T_41 | readNum_42; // @[Library.scala 76:39]
- wire [7:0] readNum_43 = {{2'd0}, _readNum_43_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_43 = _foundId_T_42 | readNum_43; // @[Library.scala 76:39]
- wire [7:0] readNum_44 = {{2'd0}, _readNum_44_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_44 = _foundId_T_43 | readNum_44; // @[Library.scala 76:39]
- wire [7:0] readNum_45 = {{2'd0}, _readNum_45_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_45 = _foundId_T_44 | readNum_45; // @[Library.scala 76:39]
- wire [7:0] readNum_46 = {{2'd0}, _readNum_46_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_46 = _foundId_T_45 | readNum_46; // @[Library.scala 76:39]
- wire [7:0] readNum_47 = {{2'd0}, _readNum_47_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_47 = _foundId_T_46 | readNum_47; // @[Library.scala 76:39]
- wire [7:0] readNum_48 = {{2'd0}, _readNum_48_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_48 = _foundId_T_47 | readNum_48; // @[Library.scala 76:39]
- wire [7:0] readNum_49 = {{2'd0}, _readNum_49_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_49 = _foundId_T_48 | readNum_49; // @[Library.scala 76:39]
- wire [7:0] readNum_50 = {{2'd0}, _readNum_50_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_50 = _foundId_T_49 | readNum_50; // @[Library.scala 76:39]
- wire [7:0] readNum_51 = {{2'd0}, _readNum_51_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_51 = _foundId_T_50 | readNum_51; // @[Library.scala 76:39]
- wire [7:0] readNum_52 = {{2'd0}, _readNum_52_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_52 = _foundId_T_51 | readNum_52; // @[Library.scala 76:39]
- wire [7:0] readNum_53 = {{2'd0}, _readNum_53_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_53 = _foundId_T_52 | readNum_53; // @[Library.scala 76:39]
- wire [7:0] readNum_54 = {{2'd0}, _readNum_54_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_54 = _foundId_T_53 | readNum_54; // @[Library.scala 76:39]
- wire [7:0] readNum_55 = {{2'd0}, _readNum_55_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_55 = _foundId_T_54 | readNum_55; // @[Library.scala 76:39]
- wire [7:0] readNum_56 = {{2'd0}, _readNum_56_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_56 = _foundId_T_55 | readNum_56; // @[Library.scala 76:39]
- wire [7:0] readNum_57 = {{2'd0}, _readNum_57_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_57 = _foundId_T_56 | readNum_57; // @[Library.scala 76:39]
- wire [7:0] readNum_58 = {{2'd0}, _readNum_58_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_58 = _foundId_T_57 | readNum_58; // @[Library.scala 76:39]
- wire [7:0] readNum_59 = {{2'd0}, _readNum_59_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_59 = _foundId_T_58 | readNum_59; // @[Library.scala 76:39]
- wire [7:0] readNum_60 = {{2'd0}, _readNum_60_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_60 = _foundId_T_59 | readNum_60; // @[Library.scala 76:39]
- wire [7:0] readNum_61 = {{2'd0}, _readNum_61_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_61 = _foundId_T_60 | readNum_61; // @[Library.scala 76:39]
- wire [7:0] readNum_62 = {{2'd0}, _readNum_62_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_62 = _foundId_T_61 | readNum_62; // @[Library.scala 76:39]
- wire [7:0] readNum_63 = {{2'd0}, _readNum_63_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_63 = _foundId_T_62 | readNum_63; // @[Library.scala 76:39]
- wire [7:0] readNum_64 = {{1'd0}, _readNum_64_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_64 = _foundId_T_63 | readNum_64; // @[Library.scala 76:39]
- wire [7:0] readNum_65 = {{1'd0}, _readNum_65_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_65 = _foundId_T_64 | readNum_65; // @[Library.scala 76:39]
- wire [7:0] readNum_66 = {{1'd0}, _readNum_66_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_66 = _foundId_T_65 | readNum_66; // @[Library.scala 76:39]
- wire [7:0] readNum_67 = {{1'd0}, _readNum_67_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_67 = _foundId_T_66 | readNum_67; // @[Library.scala 76:39]
- wire [7:0] readNum_68 = {{1'd0}, _readNum_68_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_68 = _foundId_T_67 | readNum_68; // @[Library.scala 76:39]
- wire [7:0] readNum_69 = {{1'd0}, _readNum_69_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_69 = _foundId_T_68 | readNum_69; // @[Library.scala 76:39]
- wire [7:0] readNum_70 = {{1'd0}, _readNum_70_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_70 = _foundId_T_69 | readNum_70; // @[Library.scala 76:39]
- wire [7:0] readNum_71 = {{1'd0}, _readNum_71_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_71 = _foundId_T_70 | readNum_71; // @[Library.scala 76:39]
- wire [7:0] readNum_72 = {{1'd0}, _readNum_72_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_72 = _foundId_T_71 | readNum_72; // @[Library.scala 76:39]
- wire [7:0] readNum_73 = {{1'd0}, _readNum_73_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_73 = _foundId_T_72 | readNum_73; // @[Library.scala 76:39]
- wire [7:0] readNum_74 = {{1'd0}, _readNum_74_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_74 = _foundId_T_73 | readNum_74; // @[Library.scala 76:39]
- wire [7:0] readNum_75 = {{1'd0}, _readNum_75_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_75 = _foundId_T_74 | readNum_75; // @[Library.scala 76:39]
- wire [7:0] readNum_76 = {{1'd0}, _readNum_76_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_76 = _foundId_T_75 | readNum_76; // @[Library.scala 76:39]
- wire [7:0] readNum_77 = {{1'd0}, _readNum_77_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_77 = _foundId_T_76 | readNum_77; // @[Library.scala 76:39]
- wire [7:0] readNum_78 = {{1'd0}, _readNum_78_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_78 = _foundId_T_77 | readNum_78; // @[Library.scala 76:39]
- wire [7:0] readNum_79 = {{1'd0}, _readNum_79_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_79 = _foundId_T_78 | readNum_79; // @[Library.scala 76:39]
- wire [7:0] readNum_80 = {{1'd0}, _readNum_80_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_80 = _foundId_T_79 | readNum_80; // @[Library.scala 76:39]
- wire [7:0] readNum_81 = {{1'd0}, _readNum_81_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_81 = _foundId_T_80 | readNum_81; // @[Library.scala 76:39]
- wire [7:0] readNum_82 = {{1'd0}, _readNum_82_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_82 = _foundId_T_81 | readNum_82; // @[Library.scala 76:39]
- wire [7:0] readNum_83 = {{1'd0}, _readNum_83_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_83 = _foundId_T_82 | readNum_83; // @[Library.scala 76:39]
- wire [7:0] readNum_84 = {{1'd0}, _readNum_84_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_84 = _foundId_T_83 | readNum_84; // @[Library.scala 76:39]
- wire [7:0] readNum_85 = {{1'd0}, _readNum_85_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_85 = _foundId_T_84 | readNum_85; // @[Library.scala 76:39]
- wire [7:0] readNum_86 = {{1'd0}, _readNum_86_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_86 = _foundId_T_85 | readNum_86; // @[Library.scala 76:39]
- wire [7:0] readNum_87 = {{1'd0}, _readNum_87_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_87 = _foundId_T_86 | readNum_87; // @[Library.scala 76:39]
- wire [7:0] readNum_88 = {{1'd0}, _readNum_88_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_88 = _foundId_T_87 | readNum_88; // @[Library.scala 76:39]
- wire [7:0] readNum_89 = {{1'd0}, _readNum_89_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_89 = _foundId_T_88 | readNum_89; // @[Library.scala 76:39]
- wire [7:0] readNum_90 = {{1'd0}, _readNum_90_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_90 = _foundId_T_89 | readNum_90; // @[Library.scala 76:39]
- wire [7:0] readNum_91 = {{1'd0}, _readNum_91_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_91 = _foundId_T_90 | readNum_91; // @[Library.scala 76:39]
- wire [7:0] readNum_92 = {{1'd0}, _readNum_92_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_92 = _foundId_T_91 | readNum_92; // @[Library.scala 76:39]
- wire [7:0] readNum_93 = {{1'd0}, _readNum_93_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_93 = _foundId_T_92 | readNum_93; // @[Library.scala 76:39]
- wire [7:0] readNum_94 = {{1'd0}, _readNum_94_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_94 = _foundId_T_93 | readNum_94; // @[Library.scala 76:39]
- wire [7:0] readNum_95 = {{1'd0}, _readNum_95_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_95 = _foundId_T_94 | readNum_95; // @[Library.scala 76:39]
- wire [7:0] readNum_96 = {{1'd0}, _readNum_96_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_96 = _foundId_T_95 | readNum_96; // @[Library.scala 76:39]
- wire [7:0] readNum_97 = {{1'd0}, _readNum_97_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_97 = _foundId_T_96 | readNum_97; // @[Library.scala 76:39]
- wire [7:0] readNum_98 = {{1'd0}, _readNum_98_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_98 = _foundId_T_97 | readNum_98; // @[Library.scala 76:39]
- wire [7:0] readNum_99 = {{1'd0}, _readNum_99_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_99 = _foundId_T_98 | readNum_99; // @[Library.scala 76:39]
- wire [7:0] readNum_100 = {{1'd0}, _readNum_100_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_100 = _foundId_T_99 | readNum_100; // @[Library.scala 76:39]
- wire [7:0] readNum_101 = {{1'd0}, _readNum_101_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_101 = _foundId_T_100 | readNum_101; // @[Library.scala 76:39]
- wire [7:0] readNum_102 = {{1'd0}, _readNum_102_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_102 = _foundId_T_101 | readNum_102; // @[Library.scala 76:39]
- wire [7:0] readNum_103 = {{1'd0}, _readNum_103_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_103 = _foundId_T_102 | readNum_103; // @[Library.scala 76:39]
- wire [7:0] readNum_104 = {{1'd0}, _readNum_104_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_104 = _foundId_T_103 | readNum_104; // @[Library.scala 76:39]
- wire [7:0] readNum_105 = {{1'd0}, _readNum_105_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_105 = _foundId_T_104 | readNum_105; // @[Library.scala 76:39]
- wire [7:0] readNum_106 = {{1'd0}, _readNum_106_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_106 = _foundId_T_105 | readNum_106; // @[Library.scala 76:39]
- wire [7:0] readNum_107 = {{1'd0}, _readNum_107_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_107 = _foundId_T_106 | readNum_107; // @[Library.scala 76:39]
- wire [7:0] readNum_108 = {{1'd0}, _readNum_108_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_108 = _foundId_T_107 | readNum_108; // @[Library.scala 76:39]
- wire [7:0] readNum_109 = {{1'd0}, _readNum_109_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_109 = _foundId_T_108 | readNum_109; // @[Library.scala 76:39]
- wire [7:0] readNum_110 = {{1'd0}, _readNum_110_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_110 = _foundId_T_109 | readNum_110; // @[Library.scala 76:39]
- wire [7:0] readNum_111 = {{1'd0}, _readNum_111_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_111 = _foundId_T_110 | readNum_111; // @[Library.scala 76:39]
- wire [7:0] readNum_112 = {{1'd0}, _readNum_112_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_112 = _foundId_T_111 | readNum_112; // @[Library.scala 76:39]
- wire [7:0] readNum_113 = {{1'd0}, _readNum_113_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_113 = _foundId_T_112 | readNum_113; // @[Library.scala 76:39]
- wire [7:0] readNum_114 = {{1'd0}, _readNum_114_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_114 = _foundId_T_113 | readNum_114; // @[Library.scala 76:39]
- wire [7:0] readNum_115 = {{1'd0}, _readNum_115_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_115 = _foundId_T_114 | readNum_115; // @[Library.scala 76:39]
- wire [7:0] readNum_116 = {{1'd0}, _readNum_116_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_116 = _foundId_T_115 | readNum_116; // @[Library.scala 76:39]
- wire [7:0] readNum_117 = {{1'd0}, _readNum_117_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_117 = _foundId_T_116 | readNum_117; // @[Library.scala 76:39]
- wire [7:0] readNum_118 = {{1'd0}, _readNum_118_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_118 = _foundId_T_117 | readNum_118; // @[Library.scala 76:39]
- wire [7:0] readNum_119 = {{1'd0}, _readNum_119_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_119 = _foundId_T_118 | readNum_119; // @[Library.scala 76:39]
- wire [7:0] readNum_120 = {{1'd0}, _readNum_120_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_120 = _foundId_T_119 | readNum_120; // @[Library.scala 76:39]
- wire [7:0] readNum_121 = {{1'd0}, _readNum_121_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_121 = _foundId_T_120 | readNum_121; // @[Library.scala 76:39]
- wire [7:0] readNum_122 = {{1'd0}, _readNum_122_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_122 = _foundId_T_121 | readNum_122; // @[Library.scala 76:39]
- wire [7:0] readNum_123 = {{1'd0}, _readNum_123_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_123 = _foundId_T_122 | readNum_123; // @[Library.scala 76:39]
- wire [7:0] readNum_124 = {{1'd0}, _readNum_124_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_124 = _foundId_T_123 | readNum_124; // @[Library.scala 76:39]
- wire [7:0] readNum_125 = {{1'd0}, _readNum_125_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_125 = _foundId_T_124 | readNum_125; // @[Library.scala 76:39]
- wire [7:0] readNum_126 = {{1'd0}, _readNum_126_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_126 = _foundId_T_125 | readNum_126; // @[Library.scala 76:39]
- wire [7:0] readNum_127 = {{1'd0}, _readNum_127_T}; // @[L1DCache.scala 401:21 403:16]
- wire [7:0] _foundId_T_127 = _foundId_T_126 | readNum_127; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_128 = _foundId_T_127 | readNum_128; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_129 = _foundId_T_128 | readNum_129; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_130 = _foundId_T_129 | readNum_130; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_131 = _foundId_T_130 | readNum_131; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_132 = _foundId_T_131 | readNum_132; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_133 = _foundId_T_132 | readNum_133; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_134 = _foundId_T_133 | readNum_134; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_135 = _foundId_T_134 | readNum_135; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_136 = _foundId_T_135 | readNum_136; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_137 = _foundId_T_136 | readNum_137; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_138 = _foundId_T_137 | readNum_138; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_139 = _foundId_T_138 | readNum_139; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_140 = _foundId_T_139 | readNum_140; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_141 = _foundId_T_140 | readNum_141; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_142 = _foundId_T_141 | readNum_142; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_143 = _foundId_T_142 | readNum_143; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_144 = _foundId_T_143 | readNum_144; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_145 = _foundId_T_144 | readNum_145; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_146 = _foundId_T_145 | readNum_146; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_147 = _foundId_T_146 | readNum_147; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_148 = _foundId_T_147 | readNum_148; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_149 = _foundId_T_148 | readNum_149; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_150 = _foundId_T_149 | readNum_150; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_151 = _foundId_T_150 | readNum_151; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_152 = _foundId_T_151 | readNum_152; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_153 = _foundId_T_152 | readNum_153; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_154 = _foundId_T_153 | readNum_154; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_155 = _foundId_T_154 | readNum_155; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_156 = _foundId_T_155 | readNum_156; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_157 = _foundId_T_156 | readNum_157; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_158 = _foundId_T_157 | readNum_158; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_159 = _foundId_T_158 | readNum_159; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_160 = _foundId_T_159 | readNum_160; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_161 = _foundId_T_160 | readNum_161; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_162 = _foundId_T_161 | readNum_162; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_163 = _foundId_T_162 | readNum_163; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_164 = _foundId_T_163 | readNum_164; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_165 = _foundId_T_164 | readNum_165; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_166 = _foundId_T_165 | readNum_166; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_167 = _foundId_T_166 | readNum_167; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_168 = _foundId_T_167 | readNum_168; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_169 = _foundId_T_168 | readNum_169; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_170 = _foundId_T_169 | readNum_170; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_171 = _foundId_T_170 | readNum_171; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_172 = _foundId_T_171 | readNum_172; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_173 = _foundId_T_172 | readNum_173; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_174 = _foundId_T_173 | readNum_174; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_175 = _foundId_T_174 | readNum_175; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_176 = _foundId_T_175 | readNum_176; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_177 = _foundId_T_176 | readNum_177; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_178 = _foundId_T_177 | readNum_178; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_179 = _foundId_T_178 | readNum_179; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_180 = _foundId_T_179 | readNum_180; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_181 = _foundId_T_180 | readNum_181; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_182 = _foundId_T_181 | readNum_182; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_183 = _foundId_T_182 | readNum_183; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_184 = _foundId_T_183 | readNum_184; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_185 = _foundId_T_184 | readNum_185; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_186 = _foundId_T_185 | readNum_186; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_187 = _foundId_T_186 | readNum_187; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_188 = _foundId_T_187 | readNum_188; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_189 = _foundId_T_188 | readNum_189; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_190 = _foundId_T_189 | readNum_190; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_191 = _foundId_T_190 | readNum_191; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_192 = _foundId_T_191 | readNum_192; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_193 = _foundId_T_192 | readNum_193; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_194 = _foundId_T_193 | readNum_194; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_195 = _foundId_T_194 | readNum_195; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_196 = _foundId_T_195 | readNum_196; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_197 = _foundId_T_196 | readNum_197; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_198 = _foundId_T_197 | readNum_198; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_199 = _foundId_T_198 | readNum_199; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_200 = _foundId_T_199 | readNum_200; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_201 = _foundId_T_200 | readNum_201; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_202 = _foundId_T_201 | readNum_202; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_203 = _foundId_T_202 | readNum_203; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_204 = _foundId_T_203 | readNum_204; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_205 = _foundId_T_204 | readNum_205; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_206 = _foundId_T_205 | readNum_206; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_207 = _foundId_T_206 | readNum_207; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_208 = _foundId_T_207 | readNum_208; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_209 = _foundId_T_208 | readNum_209; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_210 = _foundId_T_209 | readNum_210; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_211 = _foundId_T_210 | readNum_211; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_212 = _foundId_T_211 | readNum_212; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_213 = _foundId_T_212 | readNum_213; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_214 = _foundId_T_213 | readNum_214; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_215 = _foundId_T_214 | readNum_215; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_216 = _foundId_T_215 | readNum_216; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_217 = _foundId_T_216 | readNum_217; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_218 = _foundId_T_217 | readNum_218; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_219 = _foundId_T_218 | readNum_219; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_220 = _foundId_T_219 | readNum_220; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_221 = _foundId_T_220 | readNum_221; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_222 = _foundId_T_221 | readNum_222; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_223 = _foundId_T_222 | readNum_223; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_224 = _foundId_T_223 | readNum_224; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_225 = _foundId_T_224 | readNum_225; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_226 = _foundId_T_225 | readNum_226; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_227 = _foundId_T_226 | readNum_227; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_228 = _foundId_T_227 | readNum_228; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_229 = _foundId_T_228 | readNum_229; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_230 = _foundId_T_229 | readNum_230; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_231 = _foundId_T_230 | readNum_231; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_232 = _foundId_T_231 | readNum_232; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_233 = _foundId_T_232 | readNum_233; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_234 = _foundId_T_233 | readNum_234; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_235 = _foundId_T_234 | readNum_235; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_236 = _foundId_T_235 | readNum_236; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_237 = _foundId_T_236 | readNum_237; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_238 = _foundId_T_237 | readNum_238; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_239 = _foundId_T_238 | readNum_239; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_240 = _foundId_T_239 | readNum_240; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_241 = _foundId_T_240 | readNum_241; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_242 = _foundId_T_241 | readNum_242; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_243 = _foundId_T_242 | readNum_243; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_244 = _foundId_T_243 | readNum_244; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_245 = _foundId_T_244 | readNum_245; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_246 = _foundId_T_245 | readNum_246; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_247 = _foundId_T_246 | readNum_247; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_248 = _foundId_T_247 | readNum_248; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_249 = _foundId_T_248 | readNum_249; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_250 = _foundId_T_249 | readNum_250; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_251 = _foundId_T_250 | readNum_251; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_252 = _foundId_T_251 | readNum_252; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_253 = _foundId_T_252 | readNum_253; // @[Library.scala 76:39]
- wire [7:0] _foundId_T_254 = _foundId_T_253 | readNum_254; // @[Library.scala 76:39]
- wire [7:0] foundId = _foundId_T_254 | readNum_255; // @[Library.scala 76:39]
- wire [3:0] matchSet_1 = matchSlot[3:0]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_1553 = matchSet_1[0] + matchSet_1[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1555 = matchSet_1[2] + matchSet_1[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1557 = _T_1553 + _T_1555; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices__2 = matchSet_1[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices__3 = matchSet_1[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices__1 = {{1'd0}, matchSet_1[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_2 = matchIndices__1 | matchIndices__2; // @[Library.scala 76:39]
- wire [1:0] matchIndex = _matchIndex_T_2 | matchIndices__3; // @[Library.scala 76:39]
- wire _T_1563 = io_dbus_valid & io_dbus_ready; // @[L1DCache.scala 420:25]
- wire _T_1566 = io_dbus_valid & io_dbus_ready & setMatch_1; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_1 = 2'h1 == matchIndex ? history_0_1 : history_0_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_2 = 2'h2 == matchIndex ? history_0_2 : _GEN_1; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_3 = 2'h3 == matchIndex ? history_0_3 : _GEN_2; // @[L1DCache.scala 424:{36,36}]
- wire _T_1568 = history_0_0 > _GEN_3; // @[L1DCache.scala 424:36]
- wire [1:0] _history_0_0_T_1 = history_0_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1574 = history_0_1 > _GEN_3; // @[L1DCache.scala 424:36]
- wire [1:0] _history_0_1_T_1 = history_0_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1580 = history_0_2 > _GEN_3; // @[L1DCache.scala 424:36]
- wire [1:0] _history_0_2_T_1 = history_0_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1586 = history_0_3 > _GEN_3; // @[L1DCache.scala 424:36]
- wire [1:0] _history_0_3_T_1 = history_0_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_2 = matchSlot[7:4]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_1595 = matchSet_2[0] + matchSet_2[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1597 = matchSet_2[2] + matchSet_2[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1599 = _T_1595 + _T_1597; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_1_2 = matchSet_2[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_1_3 = matchSet_2[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_1_1 = {{1'd0}, matchSet_2[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_5 = matchIndices_1_1 | matchIndices_1_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_1 = _matchIndex_T_5 | matchIndices_1_3; // @[Library.scala 76:39]
- wire _T_1608 = io_dbus_valid & io_dbus_ready & setMatch_5; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_17 = 2'h1 == matchIndex_1 ? history_1_1 : history_1_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_18 = 2'h2 == matchIndex_1 ? history_1_2 : _GEN_17; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_19 = 2'h3 == matchIndex_1 ? history_1_3 : _GEN_18; // @[L1DCache.scala 424:{36,36}]
- wire _T_1610 = history_1_0 > _GEN_19; // @[L1DCache.scala 424:36]
- wire [1:0] _history_1_0_T_1 = history_1_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1616 = history_1_1 > _GEN_19; // @[L1DCache.scala 424:36]
- wire [1:0] _history_1_1_T_1 = history_1_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1622 = history_1_2 > _GEN_19; // @[L1DCache.scala 424:36]
- wire [1:0] _history_1_2_T_1 = history_1_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1628 = history_1_3 > _GEN_19; // @[L1DCache.scala 424:36]
- wire [1:0] _history_1_3_T_1 = history_1_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_3 = matchSlot[11:8]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_1637 = matchSet_3[0] + matchSet_3[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1639 = matchSet_3[2] + matchSet_3[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1641 = _T_1637 + _T_1639; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_2_2 = matchSet_3[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_2_3 = matchSet_3[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_2_1 = {{1'd0}, matchSet_3[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_8 = matchIndices_2_1 | matchIndices_2_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_2 = _matchIndex_T_8 | matchIndices_2_3; // @[Library.scala 76:39]
- wire _T_1650 = io_dbus_valid & io_dbus_ready & setMatch_9; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_33 = 2'h1 == matchIndex_2 ? history_2_1 : history_2_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_34 = 2'h2 == matchIndex_2 ? history_2_2 : _GEN_33; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_35 = 2'h3 == matchIndex_2 ? history_2_3 : _GEN_34; // @[L1DCache.scala 424:{36,36}]
- wire _T_1652 = history_2_0 > _GEN_35; // @[L1DCache.scala 424:36]
- wire [1:0] _history_2_0_T_1 = history_2_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1658 = history_2_1 > _GEN_35; // @[L1DCache.scala 424:36]
- wire [1:0] _history_2_1_T_1 = history_2_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1664 = history_2_2 > _GEN_35; // @[L1DCache.scala 424:36]
- wire [1:0] _history_2_2_T_1 = history_2_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1670 = history_2_3 > _GEN_35; // @[L1DCache.scala 424:36]
- wire [1:0] _history_2_3_T_1 = history_2_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_4 = matchSlot[15:12]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_1679 = matchSet_4[0] + matchSet_4[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1681 = matchSet_4[2] + matchSet_4[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1683 = _T_1679 + _T_1681; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_3_2 = matchSet_4[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_3_3 = matchSet_4[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_3_1 = {{1'd0}, matchSet_4[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_11 = matchIndices_3_1 | matchIndices_3_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_3 = _matchIndex_T_11 | matchIndices_3_3; // @[Library.scala 76:39]
- wire _T_1692 = io_dbus_valid & io_dbus_ready & setMatch_13; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_49 = 2'h1 == matchIndex_3 ? history_3_1 : history_3_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_50 = 2'h2 == matchIndex_3 ? history_3_2 : _GEN_49; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_51 = 2'h3 == matchIndex_3 ? history_3_3 : _GEN_50; // @[L1DCache.scala 424:{36,36}]
- wire _T_1694 = history_3_0 > _GEN_51; // @[L1DCache.scala 424:36]
- wire [1:0] _history_3_0_T_1 = history_3_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1700 = history_3_1 > _GEN_51; // @[L1DCache.scala 424:36]
- wire [1:0] _history_3_1_T_1 = history_3_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1706 = history_3_2 > _GEN_51; // @[L1DCache.scala 424:36]
- wire [1:0] _history_3_2_T_1 = history_3_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1712 = history_3_3 > _GEN_51; // @[L1DCache.scala 424:36]
- wire [1:0] _history_3_3_T_1 = history_3_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_5 = matchSlot[19:16]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_1721 = matchSet_5[0] + matchSet_5[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1723 = matchSet_5[2] + matchSet_5[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1725 = _T_1721 + _T_1723; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_4_2 = matchSet_5[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_4_3 = matchSet_5[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_4_1 = {{1'd0}, matchSet_5[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_14 = matchIndices_4_1 | matchIndices_4_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_4 = _matchIndex_T_14 | matchIndices_4_3; // @[Library.scala 76:39]
- wire _T_1734 = io_dbus_valid & io_dbus_ready & setMatch_17; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_65 = 2'h1 == matchIndex_4 ? history_4_1 : history_4_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_66 = 2'h2 == matchIndex_4 ? history_4_2 : _GEN_65; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_67 = 2'h3 == matchIndex_4 ? history_4_3 : _GEN_66; // @[L1DCache.scala 424:{36,36}]
- wire _T_1736 = history_4_0 > _GEN_67; // @[L1DCache.scala 424:36]
- wire [1:0] _history_4_0_T_1 = history_4_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1742 = history_4_1 > _GEN_67; // @[L1DCache.scala 424:36]
- wire [1:0] _history_4_1_T_1 = history_4_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1748 = history_4_2 > _GEN_67; // @[L1DCache.scala 424:36]
- wire [1:0] _history_4_2_T_1 = history_4_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1754 = history_4_3 > _GEN_67; // @[L1DCache.scala 424:36]
- wire [1:0] _history_4_3_T_1 = history_4_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_6 = matchSlot[23:20]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_1763 = matchSet_6[0] + matchSet_6[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1765 = matchSet_6[2] + matchSet_6[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1767 = _T_1763 + _T_1765; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_5_2 = matchSet_6[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_5_3 = matchSet_6[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_5_1 = {{1'd0}, matchSet_6[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_17 = matchIndices_5_1 | matchIndices_5_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_5 = _matchIndex_T_17 | matchIndices_5_3; // @[Library.scala 76:39]
- wire _T_1776 = io_dbus_valid & io_dbus_ready & setMatch_21; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_81 = 2'h1 == matchIndex_5 ? history_5_1 : history_5_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_82 = 2'h2 == matchIndex_5 ? history_5_2 : _GEN_81; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_83 = 2'h3 == matchIndex_5 ? history_5_3 : _GEN_82; // @[L1DCache.scala 424:{36,36}]
- wire _T_1778 = history_5_0 > _GEN_83; // @[L1DCache.scala 424:36]
- wire [1:0] _history_5_0_T_1 = history_5_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1784 = history_5_1 > _GEN_83; // @[L1DCache.scala 424:36]
- wire [1:0] _history_5_1_T_1 = history_5_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1790 = history_5_2 > _GEN_83; // @[L1DCache.scala 424:36]
- wire [1:0] _history_5_2_T_1 = history_5_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1796 = history_5_3 > _GEN_83; // @[L1DCache.scala 424:36]
- wire [1:0] _history_5_3_T_1 = history_5_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_7 = matchSlot[27:24]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_1805 = matchSet_7[0] + matchSet_7[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1807 = matchSet_7[2] + matchSet_7[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1809 = _T_1805 + _T_1807; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_6_2 = matchSet_7[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_6_3 = matchSet_7[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_6_1 = {{1'd0}, matchSet_7[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_20 = matchIndices_6_1 | matchIndices_6_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_6 = _matchIndex_T_20 | matchIndices_6_3; // @[Library.scala 76:39]
- wire _T_1818 = io_dbus_valid & io_dbus_ready & setMatch_25; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_97 = 2'h1 == matchIndex_6 ? history_6_1 : history_6_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_98 = 2'h2 == matchIndex_6 ? history_6_2 : _GEN_97; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_99 = 2'h3 == matchIndex_6 ? history_6_3 : _GEN_98; // @[L1DCache.scala 424:{36,36}]
- wire _T_1820 = history_6_0 > _GEN_99; // @[L1DCache.scala 424:36]
- wire [1:0] _history_6_0_T_1 = history_6_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1826 = history_6_1 > _GEN_99; // @[L1DCache.scala 424:36]
- wire [1:0] _history_6_1_T_1 = history_6_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1832 = history_6_2 > _GEN_99; // @[L1DCache.scala 424:36]
- wire [1:0] _history_6_2_T_1 = history_6_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1838 = history_6_3 > _GEN_99; // @[L1DCache.scala 424:36]
- wire [1:0] _history_6_3_T_1 = history_6_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_8 = matchSlot[31:28]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_1847 = matchSet_8[0] + matchSet_8[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1849 = matchSet_8[2] + matchSet_8[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1851 = _T_1847 + _T_1849; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_7_2 = matchSet_8[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_7_3 = matchSet_8[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_7_1 = {{1'd0}, matchSet_8[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_23 = matchIndices_7_1 | matchIndices_7_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_7 = _matchIndex_T_23 | matchIndices_7_3; // @[Library.scala 76:39]
- wire _T_1860 = io_dbus_valid & io_dbus_ready & setMatch_29; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_113 = 2'h1 == matchIndex_7 ? history_7_1 : history_7_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_114 = 2'h2 == matchIndex_7 ? history_7_2 : _GEN_113; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_115 = 2'h3 == matchIndex_7 ? history_7_3 : _GEN_114; // @[L1DCache.scala 424:{36,36}]
- wire _T_1862 = history_7_0 > _GEN_115; // @[L1DCache.scala 424:36]
- wire [1:0] _history_7_0_T_1 = history_7_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1868 = history_7_1 > _GEN_115; // @[L1DCache.scala 424:36]
- wire [1:0] _history_7_1_T_1 = history_7_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1874 = history_7_2 > _GEN_115; // @[L1DCache.scala 424:36]
- wire [1:0] _history_7_2_T_1 = history_7_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1880 = history_7_3 > _GEN_115; // @[L1DCache.scala 424:36]
- wire [1:0] _history_7_3_T_1 = history_7_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_9 = matchSlot[35:32]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_1889 = matchSet_9[0] + matchSet_9[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1891 = matchSet_9[2] + matchSet_9[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1893 = _T_1889 + _T_1891; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_8_2 = matchSet_9[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_8_3 = matchSet_9[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_8_1 = {{1'd0}, matchSet_9[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_26 = matchIndices_8_1 | matchIndices_8_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_8 = _matchIndex_T_26 | matchIndices_8_3; // @[Library.scala 76:39]
- wire _T_1902 = io_dbus_valid & io_dbus_ready & setMatch_33; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_129 = 2'h1 == matchIndex_8 ? history_8_1 : history_8_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_130 = 2'h2 == matchIndex_8 ? history_8_2 : _GEN_129; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_131 = 2'h3 == matchIndex_8 ? history_8_3 : _GEN_130; // @[L1DCache.scala 424:{36,36}]
- wire _T_1904 = history_8_0 > _GEN_131; // @[L1DCache.scala 424:36]
- wire [1:0] _history_8_0_T_1 = history_8_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1910 = history_8_1 > _GEN_131; // @[L1DCache.scala 424:36]
- wire [1:0] _history_8_1_T_1 = history_8_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1916 = history_8_2 > _GEN_131; // @[L1DCache.scala 424:36]
- wire [1:0] _history_8_2_T_1 = history_8_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1922 = history_8_3 > _GEN_131; // @[L1DCache.scala 424:36]
- wire [1:0] _history_8_3_T_1 = history_8_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_10 = matchSlot[39:36]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_1931 = matchSet_10[0] + matchSet_10[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1933 = matchSet_10[2] + matchSet_10[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1935 = _T_1931 + _T_1933; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_9_2 = matchSet_10[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_9_3 = matchSet_10[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_9_1 = {{1'd0}, matchSet_10[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_29 = matchIndices_9_1 | matchIndices_9_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_9 = _matchIndex_T_29 | matchIndices_9_3; // @[Library.scala 76:39]
- wire _T_1944 = io_dbus_valid & io_dbus_ready & setMatch_37; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_145 = 2'h1 == matchIndex_9 ? history_9_1 : history_9_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_146 = 2'h2 == matchIndex_9 ? history_9_2 : _GEN_145; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_147 = 2'h3 == matchIndex_9 ? history_9_3 : _GEN_146; // @[L1DCache.scala 424:{36,36}]
- wire _T_1946 = history_9_0 > _GEN_147; // @[L1DCache.scala 424:36]
- wire [1:0] _history_9_0_T_1 = history_9_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1952 = history_9_1 > _GEN_147; // @[L1DCache.scala 424:36]
- wire [1:0] _history_9_1_T_1 = history_9_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1958 = history_9_2 > _GEN_147; // @[L1DCache.scala 424:36]
- wire [1:0] _history_9_2_T_1 = history_9_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1964 = history_9_3 > _GEN_147; // @[L1DCache.scala 424:36]
- wire [1:0] _history_9_3_T_1 = history_9_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_11 = matchSlot[43:40]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_1973 = matchSet_11[0] + matchSet_11[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1975 = matchSet_11[2] + matchSet_11[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1977 = _T_1973 + _T_1975; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_10_2 = matchSet_11[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_10_3 = matchSet_11[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_10_1 = {{1'd0}, matchSet_11[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_32 = matchIndices_10_1 | matchIndices_10_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_10 = _matchIndex_T_32 | matchIndices_10_3; // @[Library.scala 76:39]
- wire _T_1986 = io_dbus_valid & io_dbus_ready & setMatch_41; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_161 = 2'h1 == matchIndex_10 ? history_10_1 : history_10_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_162 = 2'h2 == matchIndex_10 ? history_10_2 : _GEN_161; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_163 = 2'h3 == matchIndex_10 ? history_10_3 : _GEN_162; // @[L1DCache.scala 424:{36,36}]
- wire _T_1988 = history_10_0 > _GEN_163; // @[L1DCache.scala 424:36]
- wire [1:0] _history_10_0_T_1 = history_10_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_1994 = history_10_1 > _GEN_163; // @[L1DCache.scala 424:36]
- wire [1:0] _history_10_1_T_1 = history_10_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2000 = history_10_2 > _GEN_163; // @[L1DCache.scala 424:36]
- wire [1:0] _history_10_2_T_1 = history_10_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2006 = history_10_3 > _GEN_163; // @[L1DCache.scala 424:36]
- wire [1:0] _history_10_3_T_1 = history_10_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_12 = matchSlot[47:44]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2015 = matchSet_12[0] + matchSet_12[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2017 = matchSet_12[2] + matchSet_12[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2019 = _T_2015 + _T_2017; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_11_2 = matchSet_12[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_11_3 = matchSet_12[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_11_1 = {{1'd0}, matchSet_12[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_35 = matchIndices_11_1 | matchIndices_11_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_11 = _matchIndex_T_35 | matchIndices_11_3; // @[Library.scala 76:39]
- wire _T_2028 = io_dbus_valid & io_dbus_ready & setMatch_45; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_177 = 2'h1 == matchIndex_11 ? history_11_1 : history_11_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_178 = 2'h2 == matchIndex_11 ? history_11_2 : _GEN_177; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_179 = 2'h3 == matchIndex_11 ? history_11_3 : _GEN_178; // @[L1DCache.scala 424:{36,36}]
- wire _T_2030 = history_11_0 > _GEN_179; // @[L1DCache.scala 424:36]
- wire [1:0] _history_11_0_T_1 = history_11_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2036 = history_11_1 > _GEN_179; // @[L1DCache.scala 424:36]
- wire [1:0] _history_11_1_T_1 = history_11_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2042 = history_11_2 > _GEN_179; // @[L1DCache.scala 424:36]
- wire [1:0] _history_11_2_T_1 = history_11_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2048 = history_11_3 > _GEN_179; // @[L1DCache.scala 424:36]
- wire [1:0] _history_11_3_T_1 = history_11_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_13 = matchSlot[51:48]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2057 = matchSet_13[0] + matchSet_13[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2059 = matchSet_13[2] + matchSet_13[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2061 = _T_2057 + _T_2059; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_12_2 = matchSet_13[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_12_3 = matchSet_13[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_12_1 = {{1'd0}, matchSet_13[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_38 = matchIndices_12_1 | matchIndices_12_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_12 = _matchIndex_T_38 | matchIndices_12_3; // @[Library.scala 76:39]
- wire _T_2070 = io_dbus_valid & io_dbus_ready & setMatch_49; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_193 = 2'h1 == matchIndex_12 ? history_12_1 : history_12_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_194 = 2'h2 == matchIndex_12 ? history_12_2 : _GEN_193; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_195 = 2'h3 == matchIndex_12 ? history_12_3 : _GEN_194; // @[L1DCache.scala 424:{36,36}]
- wire _T_2072 = history_12_0 > _GEN_195; // @[L1DCache.scala 424:36]
- wire [1:0] _history_12_0_T_1 = history_12_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2078 = history_12_1 > _GEN_195; // @[L1DCache.scala 424:36]
- wire [1:0] _history_12_1_T_1 = history_12_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2084 = history_12_2 > _GEN_195; // @[L1DCache.scala 424:36]
- wire [1:0] _history_12_2_T_1 = history_12_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2090 = history_12_3 > _GEN_195; // @[L1DCache.scala 424:36]
- wire [1:0] _history_12_3_T_1 = history_12_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_14 = matchSlot[55:52]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2099 = matchSet_14[0] + matchSet_14[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2101 = matchSet_14[2] + matchSet_14[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2103 = _T_2099 + _T_2101; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_13_2 = matchSet_14[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_13_3 = matchSet_14[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_13_1 = {{1'd0}, matchSet_14[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_41 = matchIndices_13_1 | matchIndices_13_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_13 = _matchIndex_T_41 | matchIndices_13_3; // @[Library.scala 76:39]
- wire _T_2112 = io_dbus_valid & io_dbus_ready & setMatch_53; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_209 = 2'h1 == matchIndex_13 ? history_13_1 : history_13_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_210 = 2'h2 == matchIndex_13 ? history_13_2 : _GEN_209; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_211 = 2'h3 == matchIndex_13 ? history_13_3 : _GEN_210; // @[L1DCache.scala 424:{36,36}]
- wire _T_2114 = history_13_0 > _GEN_211; // @[L1DCache.scala 424:36]
- wire [1:0] _history_13_0_T_1 = history_13_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2120 = history_13_1 > _GEN_211; // @[L1DCache.scala 424:36]
- wire [1:0] _history_13_1_T_1 = history_13_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2126 = history_13_2 > _GEN_211; // @[L1DCache.scala 424:36]
- wire [1:0] _history_13_2_T_1 = history_13_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2132 = history_13_3 > _GEN_211; // @[L1DCache.scala 424:36]
- wire [1:0] _history_13_3_T_1 = history_13_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_15 = matchSlot[59:56]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2141 = matchSet_15[0] + matchSet_15[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2143 = matchSet_15[2] + matchSet_15[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2145 = _T_2141 + _T_2143; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_14_2 = matchSet_15[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_14_3 = matchSet_15[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_14_1 = {{1'd0}, matchSet_15[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_44 = matchIndices_14_1 | matchIndices_14_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_14 = _matchIndex_T_44 | matchIndices_14_3; // @[Library.scala 76:39]
- wire _T_2154 = io_dbus_valid & io_dbus_ready & setMatch_57; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_225 = 2'h1 == matchIndex_14 ? history_14_1 : history_14_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_226 = 2'h2 == matchIndex_14 ? history_14_2 : _GEN_225; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_227 = 2'h3 == matchIndex_14 ? history_14_3 : _GEN_226; // @[L1DCache.scala 424:{36,36}]
- wire _T_2156 = history_14_0 > _GEN_227; // @[L1DCache.scala 424:36]
- wire [1:0] _history_14_0_T_1 = history_14_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2162 = history_14_1 > _GEN_227; // @[L1DCache.scala 424:36]
- wire [1:0] _history_14_1_T_1 = history_14_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2168 = history_14_2 > _GEN_227; // @[L1DCache.scala 424:36]
- wire [1:0] _history_14_2_T_1 = history_14_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2174 = history_14_3 > _GEN_227; // @[L1DCache.scala 424:36]
- wire [1:0] _history_14_3_T_1 = history_14_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_16 = matchSlot[63:60]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2183 = matchSet_16[0] + matchSet_16[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2185 = matchSet_16[2] + matchSet_16[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2187 = _T_2183 + _T_2185; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_15_2 = matchSet_16[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_15_3 = matchSet_16[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_15_1 = {{1'd0}, matchSet_16[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_47 = matchIndices_15_1 | matchIndices_15_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_15 = _matchIndex_T_47 | matchIndices_15_3; // @[Library.scala 76:39]
- wire _T_2196 = io_dbus_valid & io_dbus_ready & setMatch_61; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_241 = 2'h1 == matchIndex_15 ? history_15_1 : history_15_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_242 = 2'h2 == matchIndex_15 ? history_15_2 : _GEN_241; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_243 = 2'h3 == matchIndex_15 ? history_15_3 : _GEN_242; // @[L1DCache.scala 424:{36,36}]
- wire _T_2198 = history_15_0 > _GEN_243; // @[L1DCache.scala 424:36]
- wire [1:0] _history_15_0_T_1 = history_15_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2204 = history_15_1 > _GEN_243; // @[L1DCache.scala 424:36]
- wire [1:0] _history_15_1_T_1 = history_15_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2210 = history_15_2 > _GEN_243; // @[L1DCache.scala 424:36]
- wire [1:0] _history_15_2_T_1 = history_15_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2216 = history_15_3 > _GEN_243; // @[L1DCache.scala 424:36]
- wire [1:0] _history_15_3_T_1 = history_15_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_17 = matchSlot[67:64]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2225 = matchSet_17[0] + matchSet_17[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2227 = matchSet_17[2] + matchSet_17[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2229 = _T_2225 + _T_2227; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_16_2 = matchSet_17[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_16_3 = matchSet_17[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_16_1 = {{1'd0}, matchSet_17[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_50 = matchIndices_16_1 | matchIndices_16_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_16 = _matchIndex_T_50 | matchIndices_16_3; // @[Library.scala 76:39]
- wire _T_2238 = io_dbus_valid & io_dbus_ready & setMatch_65; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_257 = 2'h1 == matchIndex_16 ? history_16_1 : history_16_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_258 = 2'h2 == matchIndex_16 ? history_16_2 : _GEN_257; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_259 = 2'h3 == matchIndex_16 ? history_16_3 : _GEN_258; // @[L1DCache.scala 424:{36,36}]
- wire _T_2240 = history_16_0 > _GEN_259; // @[L1DCache.scala 424:36]
- wire [1:0] _history_16_0_T_1 = history_16_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2246 = history_16_1 > _GEN_259; // @[L1DCache.scala 424:36]
- wire [1:0] _history_16_1_T_1 = history_16_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2252 = history_16_2 > _GEN_259; // @[L1DCache.scala 424:36]
- wire [1:0] _history_16_2_T_1 = history_16_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2258 = history_16_3 > _GEN_259; // @[L1DCache.scala 424:36]
- wire [1:0] _history_16_3_T_1 = history_16_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_18 = matchSlot[71:68]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2267 = matchSet_18[0] + matchSet_18[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2269 = matchSet_18[2] + matchSet_18[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2271 = _T_2267 + _T_2269; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_17_2 = matchSet_18[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_17_3 = matchSet_18[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_17_1 = {{1'd0}, matchSet_18[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_53 = matchIndices_17_1 | matchIndices_17_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_17 = _matchIndex_T_53 | matchIndices_17_3; // @[Library.scala 76:39]
- wire _T_2280 = io_dbus_valid & io_dbus_ready & setMatch_69; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_273 = 2'h1 == matchIndex_17 ? history_17_1 : history_17_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_274 = 2'h2 == matchIndex_17 ? history_17_2 : _GEN_273; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_275 = 2'h3 == matchIndex_17 ? history_17_3 : _GEN_274; // @[L1DCache.scala 424:{36,36}]
- wire _T_2282 = history_17_0 > _GEN_275; // @[L1DCache.scala 424:36]
- wire [1:0] _history_17_0_T_1 = history_17_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2288 = history_17_1 > _GEN_275; // @[L1DCache.scala 424:36]
- wire [1:0] _history_17_1_T_1 = history_17_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2294 = history_17_2 > _GEN_275; // @[L1DCache.scala 424:36]
- wire [1:0] _history_17_2_T_1 = history_17_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2300 = history_17_3 > _GEN_275; // @[L1DCache.scala 424:36]
- wire [1:0] _history_17_3_T_1 = history_17_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_19 = matchSlot[75:72]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2309 = matchSet_19[0] + matchSet_19[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2311 = matchSet_19[2] + matchSet_19[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2313 = _T_2309 + _T_2311; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_18_2 = matchSet_19[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_18_3 = matchSet_19[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_18_1 = {{1'd0}, matchSet_19[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_56 = matchIndices_18_1 | matchIndices_18_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_18 = _matchIndex_T_56 | matchIndices_18_3; // @[Library.scala 76:39]
- wire _T_2322 = io_dbus_valid & io_dbus_ready & setMatch_73; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_289 = 2'h1 == matchIndex_18 ? history_18_1 : history_18_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_290 = 2'h2 == matchIndex_18 ? history_18_2 : _GEN_289; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_291 = 2'h3 == matchIndex_18 ? history_18_3 : _GEN_290; // @[L1DCache.scala 424:{36,36}]
- wire _T_2324 = history_18_0 > _GEN_291; // @[L1DCache.scala 424:36]
- wire [1:0] _history_18_0_T_1 = history_18_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2330 = history_18_1 > _GEN_291; // @[L1DCache.scala 424:36]
- wire [1:0] _history_18_1_T_1 = history_18_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2336 = history_18_2 > _GEN_291; // @[L1DCache.scala 424:36]
- wire [1:0] _history_18_2_T_1 = history_18_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2342 = history_18_3 > _GEN_291; // @[L1DCache.scala 424:36]
- wire [1:0] _history_18_3_T_1 = history_18_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_20 = matchSlot[79:76]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2351 = matchSet_20[0] + matchSet_20[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2353 = matchSet_20[2] + matchSet_20[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2355 = _T_2351 + _T_2353; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_19_2 = matchSet_20[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_19_3 = matchSet_20[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_19_1 = {{1'd0}, matchSet_20[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_59 = matchIndices_19_1 | matchIndices_19_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_19 = _matchIndex_T_59 | matchIndices_19_3; // @[Library.scala 76:39]
- wire _T_2364 = io_dbus_valid & io_dbus_ready & setMatch_77; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_305 = 2'h1 == matchIndex_19 ? history_19_1 : history_19_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_306 = 2'h2 == matchIndex_19 ? history_19_2 : _GEN_305; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_307 = 2'h3 == matchIndex_19 ? history_19_3 : _GEN_306; // @[L1DCache.scala 424:{36,36}]
- wire _T_2366 = history_19_0 > _GEN_307; // @[L1DCache.scala 424:36]
- wire [1:0] _history_19_0_T_1 = history_19_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2372 = history_19_1 > _GEN_307; // @[L1DCache.scala 424:36]
- wire [1:0] _history_19_1_T_1 = history_19_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2378 = history_19_2 > _GEN_307; // @[L1DCache.scala 424:36]
- wire [1:0] _history_19_2_T_1 = history_19_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2384 = history_19_3 > _GEN_307; // @[L1DCache.scala 424:36]
- wire [1:0] _history_19_3_T_1 = history_19_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_21 = matchSlot[83:80]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2393 = matchSet_21[0] + matchSet_21[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2395 = matchSet_21[2] + matchSet_21[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2397 = _T_2393 + _T_2395; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_20_2 = matchSet_21[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_20_3 = matchSet_21[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_20_1 = {{1'd0}, matchSet_21[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_62 = matchIndices_20_1 | matchIndices_20_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_20 = _matchIndex_T_62 | matchIndices_20_3; // @[Library.scala 76:39]
- wire _T_2406 = io_dbus_valid & io_dbus_ready & setMatch_81; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_321 = 2'h1 == matchIndex_20 ? history_20_1 : history_20_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_322 = 2'h2 == matchIndex_20 ? history_20_2 : _GEN_321; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_323 = 2'h3 == matchIndex_20 ? history_20_3 : _GEN_322; // @[L1DCache.scala 424:{36,36}]
- wire _T_2408 = history_20_0 > _GEN_323; // @[L1DCache.scala 424:36]
- wire [1:0] _history_20_0_T_1 = history_20_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2414 = history_20_1 > _GEN_323; // @[L1DCache.scala 424:36]
- wire [1:0] _history_20_1_T_1 = history_20_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2420 = history_20_2 > _GEN_323; // @[L1DCache.scala 424:36]
- wire [1:0] _history_20_2_T_1 = history_20_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2426 = history_20_3 > _GEN_323; // @[L1DCache.scala 424:36]
- wire [1:0] _history_20_3_T_1 = history_20_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_22 = matchSlot[87:84]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2435 = matchSet_22[0] + matchSet_22[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2437 = matchSet_22[2] + matchSet_22[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2439 = _T_2435 + _T_2437; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_21_2 = matchSet_22[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_21_3 = matchSet_22[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_21_1 = {{1'd0}, matchSet_22[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_65 = matchIndices_21_1 | matchIndices_21_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_21 = _matchIndex_T_65 | matchIndices_21_3; // @[Library.scala 76:39]
- wire _T_2448 = io_dbus_valid & io_dbus_ready & setMatch_85; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_337 = 2'h1 == matchIndex_21 ? history_21_1 : history_21_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_338 = 2'h2 == matchIndex_21 ? history_21_2 : _GEN_337; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_339 = 2'h3 == matchIndex_21 ? history_21_3 : _GEN_338; // @[L1DCache.scala 424:{36,36}]
- wire _T_2450 = history_21_0 > _GEN_339; // @[L1DCache.scala 424:36]
- wire [1:0] _history_21_0_T_1 = history_21_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2456 = history_21_1 > _GEN_339; // @[L1DCache.scala 424:36]
- wire [1:0] _history_21_1_T_1 = history_21_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2462 = history_21_2 > _GEN_339; // @[L1DCache.scala 424:36]
- wire [1:0] _history_21_2_T_1 = history_21_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2468 = history_21_3 > _GEN_339; // @[L1DCache.scala 424:36]
- wire [1:0] _history_21_3_T_1 = history_21_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_23 = matchSlot[91:88]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2477 = matchSet_23[0] + matchSet_23[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2479 = matchSet_23[2] + matchSet_23[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2481 = _T_2477 + _T_2479; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_22_2 = matchSet_23[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_22_3 = matchSet_23[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_22_1 = {{1'd0}, matchSet_23[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_68 = matchIndices_22_1 | matchIndices_22_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_22 = _matchIndex_T_68 | matchIndices_22_3; // @[Library.scala 76:39]
- wire _T_2490 = io_dbus_valid & io_dbus_ready & setMatch_89; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_353 = 2'h1 == matchIndex_22 ? history_22_1 : history_22_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_354 = 2'h2 == matchIndex_22 ? history_22_2 : _GEN_353; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_355 = 2'h3 == matchIndex_22 ? history_22_3 : _GEN_354; // @[L1DCache.scala 424:{36,36}]
- wire _T_2492 = history_22_0 > _GEN_355; // @[L1DCache.scala 424:36]
- wire [1:0] _history_22_0_T_1 = history_22_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2498 = history_22_1 > _GEN_355; // @[L1DCache.scala 424:36]
- wire [1:0] _history_22_1_T_1 = history_22_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2504 = history_22_2 > _GEN_355; // @[L1DCache.scala 424:36]
- wire [1:0] _history_22_2_T_1 = history_22_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2510 = history_22_3 > _GEN_355; // @[L1DCache.scala 424:36]
- wire [1:0] _history_22_3_T_1 = history_22_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_24 = matchSlot[95:92]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2519 = matchSet_24[0] + matchSet_24[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2521 = matchSet_24[2] + matchSet_24[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2523 = _T_2519 + _T_2521; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_23_2 = matchSet_24[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_23_3 = matchSet_24[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_23_1 = {{1'd0}, matchSet_24[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_71 = matchIndices_23_1 | matchIndices_23_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_23 = _matchIndex_T_71 | matchIndices_23_3; // @[Library.scala 76:39]
- wire _T_2532 = io_dbus_valid & io_dbus_ready & setMatch_93; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_369 = 2'h1 == matchIndex_23 ? history_23_1 : history_23_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_370 = 2'h2 == matchIndex_23 ? history_23_2 : _GEN_369; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_371 = 2'h3 == matchIndex_23 ? history_23_3 : _GEN_370; // @[L1DCache.scala 424:{36,36}]
- wire _T_2534 = history_23_0 > _GEN_371; // @[L1DCache.scala 424:36]
- wire [1:0] _history_23_0_T_1 = history_23_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2540 = history_23_1 > _GEN_371; // @[L1DCache.scala 424:36]
- wire [1:0] _history_23_1_T_1 = history_23_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2546 = history_23_2 > _GEN_371; // @[L1DCache.scala 424:36]
- wire [1:0] _history_23_2_T_1 = history_23_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2552 = history_23_3 > _GEN_371; // @[L1DCache.scala 424:36]
- wire [1:0] _history_23_3_T_1 = history_23_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_25 = matchSlot[99:96]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2561 = matchSet_25[0] + matchSet_25[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2563 = matchSet_25[2] + matchSet_25[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2565 = _T_2561 + _T_2563; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_24_2 = matchSet_25[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_24_3 = matchSet_25[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_24_1 = {{1'd0}, matchSet_25[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_74 = matchIndices_24_1 | matchIndices_24_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_24 = _matchIndex_T_74 | matchIndices_24_3; // @[Library.scala 76:39]
- wire _T_2574 = io_dbus_valid & io_dbus_ready & setMatch_97; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_385 = 2'h1 == matchIndex_24 ? history_24_1 : history_24_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_386 = 2'h2 == matchIndex_24 ? history_24_2 : _GEN_385; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_387 = 2'h3 == matchIndex_24 ? history_24_3 : _GEN_386; // @[L1DCache.scala 424:{36,36}]
- wire _T_2576 = history_24_0 > _GEN_387; // @[L1DCache.scala 424:36]
- wire [1:0] _history_24_0_T_1 = history_24_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2582 = history_24_1 > _GEN_387; // @[L1DCache.scala 424:36]
- wire [1:0] _history_24_1_T_1 = history_24_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2588 = history_24_2 > _GEN_387; // @[L1DCache.scala 424:36]
- wire [1:0] _history_24_2_T_1 = history_24_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2594 = history_24_3 > _GEN_387; // @[L1DCache.scala 424:36]
- wire [1:0] _history_24_3_T_1 = history_24_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_26 = matchSlot[103:100]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2603 = matchSet_26[0] + matchSet_26[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2605 = matchSet_26[2] + matchSet_26[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2607 = _T_2603 + _T_2605; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_25_2 = matchSet_26[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_25_3 = matchSet_26[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_25_1 = {{1'd0}, matchSet_26[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_77 = matchIndices_25_1 | matchIndices_25_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_25 = _matchIndex_T_77 | matchIndices_25_3; // @[Library.scala 76:39]
- wire _T_2616 = io_dbus_valid & io_dbus_ready & setMatch_101; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_401 = 2'h1 == matchIndex_25 ? history_25_1 : history_25_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_402 = 2'h2 == matchIndex_25 ? history_25_2 : _GEN_401; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_403 = 2'h3 == matchIndex_25 ? history_25_3 : _GEN_402; // @[L1DCache.scala 424:{36,36}]
- wire _T_2618 = history_25_0 > _GEN_403; // @[L1DCache.scala 424:36]
- wire [1:0] _history_25_0_T_1 = history_25_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2624 = history_25_1 > _GEN_403; // @[L1DCache.scala 424:36]
- wire [1:0] _history_25_1_T_1 = history_25_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2630 = history_25_2 > _GEN_403; // @[L1DCache.scala 424:36]
- wire [1:0] _history_25_2_T_1 = history_25_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2636 = history_25_3 > _GEN_403; // @[L1DCache.scala 424:36]
- wire [1:0] _history_25_3_T_1 = history_25_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_27 = matchSlot[107:104]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2645 = matchSet_27[0] + matchSet_27[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2647 = matchSet_27[2] + matchSet_27[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2649 = _T_2645 + _T_2647; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_26_2 = matchSet_27[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_26_3 = matchSet_27[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_26_1 = {{1'd0}, matchSet_27[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_80 = matchIndices_26_1 | matchIndices_26_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_26 = _matchIndex_T_80 | matchIndices_26_3; // @[Library.scala 76:39]
- wire _T_2658 = io_dbus_valid & io_dbus_ready & setMatch_105; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_417 = 2'h1 == matchIndex_26 ? history_26_1 : history_26_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_418 = 2'h2 == matchIndex_26 ? history_26_2 : _GEN_417; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_419 = 2'h3 == matchIndex_26 ? history_26_3 : _GEN_418; // @[L1DCache.scala 424:{36,36}]
- wire _T_2660 = history_26_0 > _GEN_419; // @[L1DCache.scala 424:36]
- wire [1:0] _history_26_0_T_1 = history_26_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2666 = history_26_1 > _GEN_419; // @[L1DCache.scala 424:36]
- wire [1:0] _history_26_1_T_1 = history_26_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2672 = history_26_2 > _GEN_419; // @[L1DCache.scala 424:36]
- wire [1:0] _history_26_2_T_1 = history_26_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2678 = history_26_3 > _GEN_419; // @[L1DCache.scala 424:36]
- wire [1:0] _history_26_3_T_1 = history_26_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_28 = matchSlot[111:108]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2687 = matchSet_28[0] + matchSet_28[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2689 = matchSet_28[2] + matchSet_28[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2691 = _T_2687 + _T_2689; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_27_2 = matchSet_28[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_27_3 = matchSet_28[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_27_1 = {{1'd0}, matchSet_28[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_83 = matchIndices_27_1 | matchIndices_27_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_27 = _matchIndex_T_83 | matchIndices_27_3; // @[Library.scala 76:39]
- wire _T_2700 = io_dbus_valid & io_dbus_ready & setMatch_109; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_433 = 2'h1 == matchIndex_27 ? history_27_1 : history_27_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_434 = 2'h2 == matchIndex_27 ? history_27_2 : _GEN_433; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_435 = 2'h3 == matchIndex_27 ? history_27_3 : _GEN_434; // @[L1DCache.scala 424:{36,36}]
- wire _T_2702 = history_27_0 > _GEN_435; // @[L1DCache.scala 424:36]
- wire [1:0] _history_27_0_T_1 = history_27_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2708 = history_27_1 > _GEN_435; // @[L1DCache.scala 424:36]
- wire [1:0] _history_27_1_T_1 = history_27_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2714 = history_27_2 > _GEN_435; // @[L1DCache.scala 424:36]
- wire [1:0] _history_27_2_T_1 = history_27_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2720 = history_27_3 > _GEN_435; // @[L1DCache.scala 424:36]
- wire [1:0] _history_27_3_T_1 = history_27_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_29 = matchSlot[115:112]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2729 = matchSet_29[0] + matchSet_29[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2731 = matchSet_29[2] + matchSet_29[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2733 = _T_2729 + _T_2731; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_28_2 = matchSet_29[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_28_3 = matchSet_29[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_28_1 = {{1'd0}, matchSet_29[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_86 = matchIndices_28_1 | matchIndices_28_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_28 = _matchIndex_T_86 | matchIndices_28_3; // @[Library.scala 76:39]
- wire _T_2742 = io_dbus_valid & io_dbus_ready & setMatch_113; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_449 = 2'h1 == matchIndex_28 ? history_28_1 : history_28_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_450 = 2'h2 == matchIndex_28 ? history_28_2 : _GEN_449; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_451 = 2'h3 == matchIndex_28 ? history_28_3 : _GEN_450; // @[L1DCache.scala 424:{36,36}]
- wire _T_2744 = history_28_0 > _GEN_451; // @[L1DCache.scala 424:36]
- wire [1:0] _history_28_0_T_1 = history_28_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2750 = history_28_1 > _GEN_451; // @[L1DCache.scala 424:36]
- wire [1:0] _history_28_1_T_1 = history_28_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2756 = history_28_2 > _GEN_451; // @[L1DCache.scala 424:36]
- wire [1:0] _history_28_2_T_1 = history_28_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2762 = history_28_3 > _GEN_451; // @[L1DCache.scala 424:36]
- wire [1:0] _history_28_3_T_1 = history_28_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_30 = matchSlot[119:116]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2771 = matchSet_30[0] + matchSet_30[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2773 = matchSet_30[2] + matchSet_30[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2775 = _T_2771 + _T_2773; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_29_2 = matchSet_30[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_29_3 = matchSet_30[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_29_1 = {{1'd0}, matchSet_30[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_89 = matchIndices_29_1 | matchIndices_29_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_29 = _matchIndex_T_89 | matchIndices_29_3; // @[Library.scala 76:39]
- wire _T_2784 = io_dbus_valid & io_dbus_ready & setMatch_117; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_465 = 2'h1 == matchIndex_29 ? history_29_1 : history_29_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_466 = 2'h2 == matchIndex_29 ? history_29_2 : _GEN_465; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_467 = 2'h3 == matchIndex_29 ? history_29_3 : _GEN_466; // @[L1DCache.scala 424:{36,36}]
- wire _T_2786 = history_29_0 > _GEN_467; // @[L1DCache.scala 424:36]
- wire [1:0] _history_29_0_T_1 = history_29_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2792 = history_29_1 > _GEN_467; // @[L1DCache.scala 424:36]
- wire [1:0] _history_29_1_T_1 = history_29_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2798 = history_29_2 > _GEN_467; // @[L1DCache.scala 424:36]
- wire [1:0] _history_29_2_T_1 = history_29_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2804 = history_29_3 > _GEN_467; // @[L1DCache.scala 424:36]
- wire [1:0] _history_29_3_T_1 = history_29_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_31 = matchSlot[123:120]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2813 = matchSet_31[0] + matchSet_31[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2815 = matchSet_31[2] + matchSet_31[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2817 = _T_2813 + _T_2815; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_30_2 = matchSet_31[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_30_3 = matchSet_31[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_30_1 = {{1'd0}, matchSet_31[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_92 = matchIndices_30_1 | matchIndices_30_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_30 = _matchIndex_T_92 | matchIndices_30_3; // @[Library.scala 76:39]
- wire _T_2826 = io_dbus_valid & io_dbus_ready & setMatch_121; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_481 = 2'h1 == matchIndex_30 ? history_30_1 : history_30_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_482 = 2'h2 == matchIndex_30 ? history_30_2 : _GEN_481; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_483 = 2'h3 == matchIndex_30 ? history_30_3 : _GEN_482; // @[L1DCache.scala 424:{36,36}]
- wire _T_2828 = history_30_0 > _GEN_483; // @[L1DCache.scala 424:36]
- wire [1:0] _history_30_0_T_1 = history_30_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2834 = history_30_1 > _GEN_483; // @[L1DCache.scala 424:36]
- wire [1:0] _history_30_1_T_1 = history_30_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2840 = history_30_2 > _GEN_483; // @[L1DCache.scala 424:36]
- wire [1:0] _history_30_2_T_1 = history_30_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2846 = history_30_3 > _GEN_483; // @[L1DCache.scala 424:36]
- wire [1:0] _history_30_3_T_1 = history_30_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_32 = matchSlot[127:124]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2855 = matchSet_32[0] + matchSet_32[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2857 = matchSet_32[2] + matchSet_32[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2859 = _T_2855 + _T_2857; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_31_2 = matchSet_32[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_31_3 = matchSet_32[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_31_1 = {{1'd0}, matchSet_32[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_95 = matchIndices_31_1 | matchIndices_31_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_31 = _matchIndex_T_95 | matchIndices_31_3; // @[Library.scala 76:39]
- wire _T_2868 = io_dbus_valid & io_dbus_ready & setMatch_125; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_497 = 2'h1 == matchIndex_31 ? history_31_1 : history_31_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_498 = 2'h2 == matchIndex_31 ? history_31_2 : _GEN_497; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_499 = 2'h3 == matchIndex_31 ? history_31_3 : _GEN_498; // @[L1DCache.scala 424:{36,36}]
- wire _T_2870 = history_31_0 > _GEN_499; // @[L1DCache.scala 424:36]
- wire [1:0] _history_31_0_T_1 = history_31_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2876 = history_31_1 > _GEN_499; // @[L1DCache.scala 424:36]
- wire [1:0] _history_31_1_T_1 = history_31_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2882 = history_31_2 > _GEN_499; // @[L1DCache.scala 424:36]
- wire [1:0] _history_31_2_T_1 = history_31_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2888 = history_31_3 > _GEN_499; // @[L1DCache.scala 424:36]
- wire [1:0] _history_31_3_T_1 = history_31_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_33 = matchSlot[131:128]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2897 = matchSet_33[0] + matchSet_33[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2899 = matchSet_33[2] + matchSet_33[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2901 = _T_2897 + _T_2899; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_32_2 = matchSet_33[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_32_3 = matchSet_33[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_32_1 = {{1'd0}, matchSet_33[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_98 = matchIndices_32_1 | matchIndices_32_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_32 = _matchIndex_T_98 | matchIndices_32_3; // @[Library.scala 76:39]
- wire _T_2910 = io_dbus_valid & io_dbus_ready & setMatch_129; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_513 = 2'h1 == matchIndex_32 ? history_32_1 : history_32_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_514 = 2'h2 == matchIndex_32 ? history_32_2 : _GEN_513; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_515 = 2'h3 == matchIndex_32 ? history_32_3 : _GEN_514; // @[L1DCache.scala 424:{36,36}]
- wire _T_2912 = history_32_0 > _GEN_515; // @[L1DCache.scala 424:36]
- wire [1:0] _history_32_0_T_1 = history_32_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2918 = history_32_1 > _GEN_515; // @[L1DCache.scala 424:36]
- wire [1:0] _history_32_1_T_1 = history_32_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2924 = history_32_2 > _GEN_515; // @[L1DCache.scala 424:36]
- wire [1:0] _history_32_2_T_1 = history_32_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2930 = history_32_3 > _GEN_515; // @[L1DCache.scala 424:36]
- wire [1:0] _history_32_3_T_1 = history_32_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_34 = matchSlot[135:132]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2939 = matchSet_34[0] + matchSet_34[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2941 = matchSet_34[2] + matchSet_34[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2943 = _T_2939 + _T_2941; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_33_2 = matchSet_34[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_33_3 = matchSet_34[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_33_1 = {{1'd0}, matchSet_34[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_101 = matchIndices_33_1 | matchIndices_33_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_33 = _matchIndex_T_101 | matchIndices_33_3; // @[Library.scala 76:39]
- wire _T_2952 = io_dbus_valid & io_dbus_ready & setMatch_133; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_529 = 2'h1 == matchIndex_33 ? history_33_1 : history_33_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_530 = 2'h2 == matchIndex_33 ? history_33_2 : _GEN_529; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_531 = 2'h3 == matchIndex_33 ? history_33_3 : _GEN_530; // @[L1DCache.scala 424:{36,36}]
- wire _T_2954 = history_33_0 > _GEN_531; // @[L1DCache.scala 424:36]
- wire [1:0] _history_33_0_T_1 = history_33_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2960 = history_33_1 > _GEN_531; // @[L1DCache.scala 424:36]
- wire [1:0] _history_33_1_T_1 = history_33_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2966 = history_33_2 > _GEN_531; // @[L1DCache.scala 424:36]
- wire [1:0] _history_33_2_T_1 = history_33_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_2972 = history_33_3 > _GEN_531; // @[L1DCache.scala 424:36]
- wire [1:0] _history_33_3_T_1 = history_33_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_35 = matchSlot[139:136]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_2981 = matchSet_35[0] + matchSet_35[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2983 = matchSet_35[2] + matchSet_35[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2985 = _T_2981 + _T_2983; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_34_2 = matchSet_35[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_34_3 = matchSet_35[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_34_1 = {{1'd0}, matchSet_35[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_104 = matchIndices_34_1 | matchIndices_34_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_34 = _matchIndex_T_104 | matchIndices_34_3; // @[Library.scala 76:39]
- wire _T_2994 = io_dbus_valid & io_dbus_ready & setMatch_137; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_545 = 2'h1 == matchIndex_34 ? history_34_1 : history_34_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_546 = 2'h2 == matchIndex_34 ? history_34_2 : _GEN_545; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_547 = 2'h3 == matchIndex_34 ? history_34_3 : _GEN_546; // @[L1DCache.scala 424:{36,36}]
- wire _T_2996 = history_34_0 > _GEN_547; // @[L1DCache.scala 424:36]
- wire [1:0] _history_34_0_T_1 = history_34_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3002 = history_34_1 > _GEN_547; // @[L1DCache.scala 424:36]
- wire [1:0] _history_34_1_T_1 = history_34_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3008 = history_34_2 > _GEN_547; // @[L1DCache.scala 424:36]
- wire [1:0] _history_34_2_T_1 = history_34_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3014 = history_34_3 > _GEN_547; // @[L1DCache.scala 424:36]
- wire [1:0] _history_34_3_T_1 = history_34_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_36 = matchSlot[143:140]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3023 = matchSet_36[0] + matchSet_36[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3025 = matchSet_36[2] + matchSet_36[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3027 = _T_3023 + _T_3025; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_35_2 = matchSet_36[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_35_3 = matchSet_36[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_35_1 = {{1'd0}, matchSet_36[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_107 = matchIndices_35_1 | matchIndices_35_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_35 = _matchIndex_T_107 | matchIndices_35_3; // @[Library.scala 76:39]
- wire _T_3036 = io_dbus_valid & io_dbus_ready & setMatch_141; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_561 = 2'h1 == matchIndex_35 ? history_35_1 : history_35_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_562 = 2'h2 == matchIndex_35 ? history_35_2 : _GEN_561; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_563 = 2'h3 == matchIndex_35 ? history_35_3 : _GEN_562; // @[L1DCache.scala 424:{36,36}]
- wire _T_3038 = history_35_0 > _GEN_563; // @[L1DCache.scala 424:36]
- wire [1:0] _history_35_0_T_1 = history_35_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3044 = history_35_1 > _GEN_563; // @[L1DCache.scala 424:36]
- wire [1:0] _history_35_1_T_1 = history_35_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3050 = history_35_2 > _GEN_563; // @[L1DCache.scala 424:36]
- wire [1:0] _history_35_2_T_1 = history_35_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3056 = history_35_3 > _GEN_563; // @[L1DCache.scala 424:36]
- wire [1:0] _history_35_3_T_1 = history_35_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_37 = matchSlot[147:144]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3065 = matchSet_37[0] + matchSet_37[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3067 = matchSet_37[2] + matchSet_37[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3069 = _T_3065 + _T_3067; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_36_2 = matchSet_37[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_36_3 = matchSet_37[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_36_1 = {{1'd0}, matchSet_37[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_110 = matchIndices_36_1 | matchIndices_36_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_36 = _matchIndex_T_110 | matchIndices_36_3; // @[Library.scala 76:39]
- wire _T_3078 = io_dbus_valid & io_dbus_ready & setMatch_145; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_577 = 2'h1 == matchIndex_36 ? history_36_1 : history_36_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_578 = 2'h2 == matchIndex_36 ? history_36_2 : _GEN_577; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_579 = 2'h3 == matchIndex_36 ? history_36_3 : _GEN_578; // @[L1DCache.scala 424:{36,36}]
- wire _T_3080 = history_36_0 > _GEN_579; // @[L1DCache.scala 424:36]
- wire [1:0] _history_36_0_T_1 = history_36_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3086 = history_36_1 > _GEN_579; // @[L1DCache.scala 424:36]
- wire [1:0] _history_36_1_T_1 = history_36_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3092 = history_36_2 > _GEN_579; // @[L1DCache.scala 424:36]
- wire [1:0] _history_36_2_T_1 = history_36_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3098 = history_36_3 > _GEN_579; // @[L1DCache.scala 424:36]
- wire [1:0] _history_36_3_T_1 = history_36_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_38 = matchSlot[151:148]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3107 = matchSet_38[0] + matchSet_38[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3109 = matchSet_38[2] + matchSet_38[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3111 = _T_3107 + _T_3109; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_37_2 = matchSet_38[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_37_3 = matchSet_38[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_37_1 = {{1'd0}, matchSet_38[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_113 = matchIndices_37_1 | matchIndices_37_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_37 = _matchIndex_T_113 | matchIndices_37_3; // @[Library.scala 76:39]
- wire _T_3120 = io_dbus_valid & io_dbus_ready & setMatch_149; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_593 = 2'h1 == matchIndex_37 ? history_37_1 : history_37_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_594 = 2'h2 == matchIndex_37 ? history_37_2 : _GEN_593; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_595 = 2'h3 == matchIndex_37 ? history_37_3 : _GEN_594; // @[L1DCache.scala 424:{36,36}]
- wire _T_3122 = history_37_0 > _GEN_595; // @[L1DCache.scala 424:36]
- wire [1:0] _history_37_0_T_1 = history_37_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3128 = history_37_1 > _GEN_595; // @[L1DCache.scala 424:36]
- wire [1:0] _history_37_1_T_1 = history_37_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3134 = history_37_2 > _GEN_595; // @[L1DCache.scala 424:36]
- wire [1:0] _history_37_2_T_1 = history_37_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3140 = history_37_3 > _GEN_595; // @[L1DCache.scala 424:36]
- wire [1:0] _history_37_3_T_1 = history_37_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_39 = matchSlot[155:152]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3149 = matchSet_39[0] + matchSet_39[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3151 = matchSet_39[2] + matchSet_39[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3153 = _T_3149 + _T_3151; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_38_2 = matchSet_39[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_38_3 = matchSet_39[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_38_1 = {{1'd0}, matchSet_39[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_116 = matchIndices_38_1 | matchIndices_38_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_38 = _matchIndex_T_116 | matchIndices_38_3; // @[Library.scala 76:39]
- wire _T_3162 = io_dbus_valid & io_dbus_ready & setMatch_153; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_609 = 2'h1 == matchIndex_38 ? history_38_1 : history_38_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_610 = 2'h2 == matchIndex_38 ? history_38_2 : _GEN_609; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_611 = 2'h3 == matchIndex_38 ? history_38_3 : _GEN_610; // @[L1DCache.scala 424:{36,36}]
- wire _T_3164 = history_38_0 > _GEN_611; // @[L1DCache.scala 424:36]
- wire [1:0] _history_38_0_T_1 = history_38_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3170 = history_38_1 > _GEN_611; // @[L1DCache.scala 424:36]
- wire [1:0] _history_38_1_T_1 = history_38_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3176 = history_38_2 > _GEN_611; // @[L1DCache.scala 424:36]
- wire [1:0] _history_38_2_T_1 = history_38_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3182 = history_38_3 > _GEN_611; // @[L1DCache.scala 424:36]
- wire [1:0] _history_38_3_T_1 = history_38_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_40 = matchSlot[159:156]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3191 = matchSet_40[0] + matchSet_40[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3193 = matchSet_40[2] + matchSet_40[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3195 = _T_3191 + _T_3193; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_39_2 = matchSet_40[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_39_3 = matchSet_40[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_39_1 = {{1'd0}, matchSet_40[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_119 = matchIndices_39_1 | matchIndices_39_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_39 = _matchIndex_T_119 | matchIndices_39_3; // @[Library.scala 76:39]
- wire _T_3204 = io_dbus_valid & io_dbus_ready & setMatch_157; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_625 = 2'h1 == matchIndex_39 ? history_39_1 : history_39_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_626 = 2'h2 == matchIndex_39 ? history_39_2 : _GEN_625; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_627 = 2'h3 == matchIndex_39 ? history_39_3 : _GEN_626; // @[L1DCache.scala 424:{36,36}]
- wire _T_3206 = history_39_0 > _GEN_627; // @[L1DCache.scala 424:36]
- wire [1:0] _history_39_0_T_1 = history_39_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3212 = history_39_1 > _GEN_627; // @[L1DCache.scala 424:36]
- wire [1:0] _history_39_1_T_1 = history_39_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3218 = history_39_2 > _GEN_627; // @[L1DCache.scala 424:36]
- wire [1:0] _history_39_2_T_1 = history_39_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3224 = history_39_3 > _GEN_627; // @[L1DCache.scala 424:36]
- wire [1:0] _history_39_3_T_1 = history_39_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_41 = matchSlot[163:160]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3233 = matchSet_41[0] + matchSet_41[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3235 = matchSet_41[2] + matchSet_41[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3237 = _T_3233 + _T_3235; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_40_2 = matchSet_41[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_40_3 = matchSet_41[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_40_1 = {{1'd0}, matchSet_41[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_122 = matchIndices_40_1 | matchIndices_40_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_40 = _matchIndex_T_122 | matchIndices_40_3; // @[Library.scala 76:39]
- wire _T_3246 = io_dbus_valid & io_dbus_ready & setMatch_161; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_641 = 2'h1 == matchIndex_40 ? history_40_1 : history_40_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_642 = 2'h2 == matchIndex_40 ? history_40_2 : _GEN_641; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_643 = 2'h3 == matchIndex_40 ? history_40_3 : _GEN_642; // @[L1DCache.scala 424:{36,36}]
- wire _T_3248 = history_40_0 > _GEN_643; // @[L1DCache.scala 424:36]
- wire [1:0] _history_40_0_T_1 = history_40_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3254 = history_40_1 > _GEN_643; // @[L1DCache.scala 424:36]
- wire [1:0] _history_40_1_T_1 = history_40_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3260 = history_40_2 > _GEN_643; // @[L1DCache.scala 424:36]
- wire [1:0] _history_40_2_T_1 = history_40_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3266 = history_40_3 > _GEN_643; // @[L1DCache.scala 424:36]
- wire [1:0] _history_40_3_T_1 = history_40_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_42 = matchSlot[167:164]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3275 = matchSet_42[0] + matchSet_42[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3277 = matchSet_42[2] + matchSet_42[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3279 = _T_3275 + _T_3277; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_41_2 = matchSet_42[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_41_3 = matchSet_42[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_41_1 = {{1'd0}, matchSet_42[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_125 = matchIndices_41_1 | matchIndices_41_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_41 = _matchIndex_T_125 | matchIndices_41_3; // @[Library.scala 76:39]
- wire _T_3288 = io_dbus_valid & io_dbus_ready & setMatch_165; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_657 = 2'h1 == matchIndex_41 ? history_41_1 : history_41_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_658 = 2'h2 == matchIndex_41 ? history_41_2 : _GEN_657; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_659 = 2'h3 == matchIndex_41 ? history_41_3 : _GEN_658; // @[L1DCache.scala 424:{36,36}]
- wire _T_3290 = history_41_0 > _GEN_659; // @[L1DCache.scala 424:36]
- wire [1:0] _history_41_0_T_1 = history_41_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3296 = history_41_1 > _GEN_659; // @[L1DCache.scala 424:36]
- wire [1:0] _history_41_1_T_1 = history_41_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3302 = history_41_2 > _GEN_659; // @[L1DCache.scala 424:36]
- wire [1:0] _history_41_2_T_1 = history_41_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3308 = history_41_3 > _GEN_659; // @[L1DCache.scala 424:36]
- wire [1:0] _history_41_3_T_1 = history_41_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_43 = matchSlot[171:168]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3317 = matchSet_43[0] + matchSet_43[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3319 = matchSet_43[2] + matchSet_43[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3321 = _T_3317 + _T_3319; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_42_2 = matchSet_43[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_42_3 = matchSet_43[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_42_1 = {{1'd0}, matchSet_43[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_128 = matchIndices_42_1 | matchIndices_42_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_42 = _matchIndex_T_128 | matchIndices_42_3; // @[Library.scala 76:39]
- wire _T_3330 = io_dbus_valid & io_dbus_ready & setMatch_169; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_673 = 2'h1 == matchIndex_42 ? history_42_1 : history_42_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_674 = 2'h2 == matchIndex_42 ? history_42_2 : _GEN_673; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_675 = 2'h3 == matchIndex_42 ? history_42_3 : _GEN_674; // @[L1DCache.scala 424:{36,36}]
- wire _T_3332 = history_42_0 > _GEN_675; // @[L1DCache.scala 424:36]
- wire [1:0] _history_42_0_T_1 = history_42_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3338 = history_42_1 > _GEN_675; // @[L1DCache.scala 424:36]
- wire [1:0] _history_42_1_T_1 = history_42_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3344 = history_42_2 > _GEN_675; // @[L1DCache.scala 424:36]
- wire [1:0] _history_42_2_T_1 = history_42_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3350 = history_42_3 > _GEN_675; // @[L1DCache.scala 424:36]
- wire [1:0] _history_42_3_T_1 = history_42_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_44 = matchSlot[175:172]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3359 = matchSet_44[0] + matchSet_44[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3361 = matchSet_44[2] + matchSet_44[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3363 = _T_3359 + _T_3361; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_43_2 = matchSet_44[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_43_3 = matchSet_44[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_43_1 = {{1'd0}, matchSet_44[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_131 = matchIndices_43_1 | matchIndices_43_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_43 = _matchIndex_T_131 | matchIndices_43_3; // @[Library.scala 76:39]
- wire _T_3372 = io_dbus_valid & io_dbus_ready & setMatch_173; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_689 = 2'h1 == matchIndex_43 ? history_43_1 : history_43_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_690 = 2'h2 == matchIndex_43 ? history_43_2 : _GEN_689; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_691 = 2'h3 == matchIndex_43 ? history_43_3 : _GEN_690; // @[L1DCache.scala 424:{36,36}]
- wire _T_3374 = history_43_0 > _GEN_691; // @[L1DCache.scala 424:36]
- wire [1:0] _history_43_0_T_1 = history_43_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3380 = history_43_1 > _GEN_691; // @[L1DCache.scala 424:36]
- wire [1:0] _history_43_1_T_1 = history_43_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3386 = history_43_2 > _GEN_691; // @[L1DCache.scala 424:36]
- wire [1:0] _history_43_2_T_1 = history_43_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3392 = history_43_3 > _GEN_691; // @[L1DCache.scala 424:36]
- wire [1:0] _history_43_3_T_1 = history_43_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_45 = matchSlot[179:176]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3401 = matchSet_45[0] + matchSet_45[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3403 = matchSet_45[2] + matchSet_45[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3405 = _T_3401 + _T_3403; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_44_2 = matchSet_45[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_44_3 = matchSet_45[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_44_1 = {{1'd0}, matchSet_45[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_134 = matchIndices_44_1 | matchIndices_44_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_44 = _matchIndex_T_134 | matchIndices_44_3; // @[Library.scala 76:39]
- wire _T_3414 = io_dbus_valid & io_dbus_ready & setMatch_177; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_705 = 2'h1 == matchIndex_44 ? history_44_1 : history_44_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_706 = 2'h2 == matchIndex_44 ? history_44_2 : _GEN_705; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_707 = 2'h3 == matchIndex_44 ? history_44_3 : _GEN_706; // @[L1DCache.scala 424:{36,36}]
- wire _T_3416 = history_44_0 > _GEN_707; // @[L1DCache.scala 424:36]
- wire [1:0] _history_44_0_T_1 = history_44_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3422 = history_44_1 > _GEN_707; // @[L1DCache.scala 424:36]
- wire [1:0] _history_44_1_T_1 = history_44_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3428 = history_44_2 > _GEN_707; // @[L1DCache.scala 424:36]
- wire [1:0] _history_44_2_T_1 = history_44_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3434 = history_44_3 > _GEN_707; // @[L1DCache.scala 424:36]
- wire [1:0] _history_44_3_T_1 = history_44_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_46 = matchSlot[183:180]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3443 = matchSet_46[0] + matchSet_46[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3445 = matchSet_46[2] + matchSet_46[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3447 = _T_3443 + _T_3445; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_45_2 = matchSet_46[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_45_3 = matchSet_46[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_45_1 = {{1'd0}, matchSet_46[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_137 = matchIndices_45_1 | matchIndices_45_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_45 = _matchIndex_T_137 | matchIndices_45_3; // @[Library.scala 76:39]
- wire _T_3456 = io_dbus_valid & io_dbus_ready & setMatch_181; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_721 = 2'h1 == matchIndex_45 ? history_45_1 : history_45_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_722 = 2'h2 == matchIndex_45 ? history_45_2 : _GEN_721; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_723 = 2'h3 == matchIndex_45 ? history_45_3 : _GEN_722; // @[L1DCache.scala 424:{36,36}]
- wire _T_3458 = history_45_0 > _GEN_723; // @[L1DCache.scala 424:36]
- wire [1:0] _history_45_0_T_1 = history_45_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3464 = history_45_1 > _GEN_723; // @[L1DCache.scala 424:36]
- wire [1:0] _history_45_1_T_1 = history_45_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3470 = history_45_2 > _GEN_723; // @[L1DCache.scala 424:36]
- wire [1:0] _history_45_2_T_1 = history_45_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3476 = history_45_3 > _GEN_723; // @[L1DCache.scala 424:36]
- wire [1:0] _history_45_3_T_1 = history_45_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_47 = matchSlot[187:184]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3485 = matchSet_47[0] + matchSet_47[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3487 = matchSet_47[2] + matchSet_47[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3489 = _T_3485 + _T_3487; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_46_2 = matchSet_47[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_46_3 = matchSet_47[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_46_1 = {{1'd0}, matchSet_47[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_140 = matchIndices_46_1 | matchIndices_46_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_46 = _matchIndex_T_140 | matchIndices_46_3; // @[Library.scala 76:39]
- wire _T_3498 = io_dbus_valid & io_dbus_ready & setMatch_185; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_737 = 2'h1 == matchIndex_46 ? history_46_1 : history_46_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_738 = 2'h2 == matchIndex_46 ? history_46_2 : _GEN_737; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_739 = 2'h3 == matchIndex_46 ? history_46_3 : _GEN_738; // @[L1DCache.scala 424:{36,36}]
- wire _T_3500 = history_46_0 > _GEN_739; // @[L1DCache.scala 424:36]
- wire [1:0] _history_46_0_T_1 = history_46_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3506 = history_46_1 > _GEN_739; // @[L1DCache.scala 424:36]
- wire [1:0] _history_46_1_T_1 = history_46_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3512 = history_46_2 > _GEN_739; // @[L1DCache.scala 424:36]
- wire [1:0] _history_46_2_T_1 = history_46_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3518 = history_46_3 > _GEN_739; // @[L1DCache.scala 424:36]
- wire [1:0] _history_46_3_T_1 = history_46_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_48 = matchSlot[191:188]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3527 = matchSet_48[0] + matchSet_48[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3529 = matchSet_48[2] + matchSet_48[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3531 = _T_3527 + _T_3529; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_47_2 = matchSet_48[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_47_3 = matchSet_48[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_47_1 = {{1'd0}, matchSet_48[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_143 = matchIndices_47_1 | matchIndices_47_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_47 = _matchIndex_T_143 | matchIndices_47_3; // @[Library.scala 76:39]
- wire _T_3540 = io_dbus_valid & io_dbus_ready & setMatch_189; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_753 = 2'h1 == matchIndex_47 ? history_47_1 : history_47_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_754 = 2'h2 == matchIndex_47 ? history_47_2 : _GEN_753; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_755 = 2'h3 == matchIndex_47 ? history_47_3 : _GEN_754; // @[L1DCache.scala 424:{36,36}]
- wire _T_3542 = history_47_0 > _GEN_755; // @[L1DCache.scala 424:36]
- wire [1:0] _history_47_0_T_1 = history_47_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3548 = history_47_1 > _GEN_755; // @[L1DCache.scala 424:36]
- wire [1:0] _history_47_1_T_1 = history_47_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3554 = history_47_2 > _GEN_755; // @[L1DCache.scala 424:36]
- wire [1:0] _history_47_2_T_1 = history_47_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3560 = history_47_3 > _GEN_755; // @[L1DCache.scala 424:36]
- wire [1:0] _history_47_3_T_1 = history_47_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_49 = matchSlot[195:192]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3569 = matchSet_49[0] + matchSet_49[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3571 = matchSet_49[2] + matchSet_49[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3573 = _T_3569 + _T_3571; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_48_2 = matchSet_49[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_48_3 = matchSet_49[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_48_1 = {{1'd0}, matchSet_49[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_146 = matchIndices_48_1 | matchIndices_48_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_48 = _matchIndex_T_146 | matchIndices_48_3; // @[Library.scala 76:39]
- wire _T_3582 = io_dbus_valid & io_dbus_ready & setMatch_193; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_769 = 2'h1 == matchIndex_48 ? history_48_1 : history_48_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_770 = 2'h2 == matchIndex_48 ? history_48_2 : _GEN_769; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_771 = 2'h3 == matchIndex_48 ? history_48_3 : _GEN_770; // @[L1DCache.scala 424:{36,36}]
- wire _T_3584 = history_48_0 > _GEN_771; // @[L1DCache.scala 424:36]
- wire [1:0] _history_48_0_T_1 = history_48_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3590 = history_48_1 > _GEN_771; // @[L1DCache.scala 424:36]
- wire [1:0] _history_48_1_T_1 = history_48_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3596 = history_48_2 > _GEN_771; // @[L1DCache.scala 424:36]
- wire [1:0] _history_48_2_T_1 = history_48_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3602 = history_48_3 > _GEN_771; // @[L1DCache.scala 424:36]
- wire [1:0] _history_48_3_T_1 = history_48_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_50 = matchSlot[199:196]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3611 = matchSet_50[0] + matchSet_50[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3613 = matchSet_50[2] + matchSet_50[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3615 = _T_3611 + _T_3613; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_49_2 = matchSet_50[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_49_3 = matchSet_50[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_49_1 = {{1'd0}, matchSet_50[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_149 = matchIndices_49_1 | matchIndices_49_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_49 = _matchIndex_T_149 | matchIndices_49_3; // @[Library.scala 76:39]
- wire _T_3624 = io_dbus_valid & io_dbus_ready & setMatch_197; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_785 = 2'h1 == matchIndex_49 ? history_49_1 : history_49_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_786 = 2'h2 == matchIndex_49 ? history_49_2 : _GEN_785; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_787 = 2'h3 == matchIndex_49 ? history_49_3 : _GEN_786; // @[L1DCache.scala 424:{36,36}]
- wire _T_3626 = history_49_0 > _GEN_787; // @[L1DCache.scala 424:36]
- wire [1:0] _history_49_0_T_1 = history_49_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3632 = history_49_1 > _GEN_787; // @[L1DCache.scala 424:36]
- wire [1:0] _history_49_1_T_1 = history_49_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3638 = history_49_2 > _GEN_787; // @[L1DCache.scala 424:36]
- wire [1:0] _history_49_2_T_1 = history_49_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3644 = history_49_3 > _GEN_787; // @[L1DCache.scala 424:36]
- wire [1:0] _history_49_3_T_1 = history_49_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_51 = matchSlot[203:200]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3653 = matchSet_51[0] + matchSet_51[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3655 = matchSet_51[2] + matchSet_51[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3657 = _T_3653 + _T_3655; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_50_2 = matchSet_51[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_50_3 = matchSet_51[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_50_1 = {{1'd0}, matchSet_51[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_152 = matchIndices_50_1 | matchIndices_50_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_50 = _matchIndex_T_152 | matchIndices_50_3; // @[Library.scala 76:39]
- wire _T_3666 = io_dbus_valid & io_dbus_ready & setMatch_201; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_801 = 2'h1 == matchIndex_50 ? history_50_1 : history_50_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_802 = 2'h2 == matchIndex_50 ? history_50_2 : _GEN_801; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_803 = 2'h3 == matchIndex_50 ? history_50_3 : _GEN_802; // @[L1DCache.scala 424:{36,36}]
- wire _T_3668 = history_50_0 > _GEN_803; // @[L1DCache.scala 424:36]
- wire [1:0] _history_50_0_T_1 = history_50_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3674 = history_50_1 > _GEN_803; // @[L1DCache.scala 424:36]
- wire [1:0] _history_50_1_T_1 = history_50_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3680 = history_50_2 > _GEN_803; // @[L1DCache.scala 424:36]
- wire [1:0] _history_50_2_T_1 = history_50_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3686 = history_50_3 > _GEN_803; // @[L1DCache.scala 424:36]
- wire [1:0] _history_50_3_T_1 = history_50_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_52 = matchSlot[207:204]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3695 = matchSet_52[0] + matchSet_52[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3697 = matchSet_52[2] + matchSet_52[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3699 = _T_3695 + _T_3697; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_51_2 = matchSet_52[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_51_3 = matchSet_52[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_51_1 = {{1'd0}, matchSet_52[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_155 = matchIndices_51_1 | matchIndices_51_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_51 = _matchIndex_T_155 | matchIndices_51_3; // @[Library.scala 76:39]
- wire _T_3708 = io_dbus_valid & io_dbus_ready & setMatch_205; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_817 = 2'h1 == matchIndex_51 ? history_51_1 : history_51_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_818 = 2'h2 == matchIndex_51 ? history_51_2 : _GEN_817; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_819 = 2'h3 == matchIndex_51 ? history_51_3 : _GEN_818; // @[L1DCache.scala 424:{36,36}]
- wire _T_3710 = history_51_0 > _GEN_819; // @[L1DCache.scala 424:36]
- wire [1:0] _history_51_0_T_1 = history_51_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3716 = history_51_1 > _GEN_819; // @[L1DCache.scala 424:36]
- wire [1:0] _history_51_1_T_1 = history_51_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3722 = history_51_2 > _GEN_819; // @[L1DCache.scala 424:36]
- wire [1:0] _history_51_2_T_1 = history_51_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3728 = history_51_3 > _GEN_819; // @[L1DCache.scala 424:36]
- wire [1:0] _history_51_3_T_1 = history_51_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_53 = matchSlot[211:208]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3737 = matchSet_53[0] + matchSet_53[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3739 = matchSet_53[2] + matchSet_53[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3741 = _T_3737 + _T_3739; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_52_2 = matchSet_53[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_52_3 = matchSet_53[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_52_1 = {{1'd0}, matchSet_53[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_158 = matchIndices_52_1 | matchIndices_52_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_52 = _matchIndex_T_158 | matchIndices_52_3; // @[Library.scala 76:39]
- wire _T_3750 = io_dbus_valid & io_dbus_ready & setMatch_209; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_833 = 2'h1 == matchIndex_52 ? history_52_1 : history_52_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_834 = 2'h2 == matchIndex_52 ? history_52_2 : _GEN_833; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_835 = 2'h3 == matchIndex_52 ? history_52_3 : _GEN_834; // @[L1DCache.scala 424:{36,36}]
- wire _T_3752 = history_52_0 > _GEN_835; // @[L1DCache.scala 424:36]
- wire [1:0] _history_52_0_T_1 = history_52_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3758 = history_52_1 > _GEN_835; // @[L1DCache.scala 424:36]
- wire [1:0] _history_52_1_T_1 = history_52_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3764 = history_52_2 > _GEN_835; // @[L1DCache.scala 424:36]
- wire [1:0] _history_52_2_T_1 = history_52_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3770 = history_52_3 > _GEN_835; // @[L1DCache.scala 424:36]
- wire [1:0] _history_52_3_T_1 = history_52_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_54 = matchSlot[215:212]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3779 = matchSet_54[0] + matchSet_54[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3781 = matchSet_54[2] + matchSet_54[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3783 = _T_3779 + _T_3781; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_53_2 = matchSet_54[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_53_3 = matchSet_54[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_53_1 = {{1'd0}, matchSet_54[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_161 = matchIndices_53_1 | matchIndices_53_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_53 = _matchIndex_T_161 | matchIndices_53_3; // @[Library.scala 76:39]
- wire _T_3792 = io_dbus_valid & io_dbus_ready & setMatch_213; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_849 = 2'h1 == matchIndex_53 ? history_53_1 : history_53_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_850 = 2'h2 == matchIndex_53 ? history_53_2 : _GEN_849; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_851 = 2'h3 == matchIndex_53 ? history_53_3 : _GEN_850; // @[L1DCache.scala 424:{36,36}]
- wire _T_3794 = history_53_0 > _GEN_851; // @[L1DCache.scala 424:36]
- wire [1:0] _history_53_0_T_1 = history_53_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3800 = history_53_1 > _GEN_851; // @[L1DCache.scala 424:36]
- wire [1:0] _history_53_1_T_1 = history_53_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3806 = history_53_2 > _GEN_851; // @[L1DCache.scala 424:36]
- wire [1:0] _history_53_2_T_1 = history_53_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3812 = history_53_3 > _GEN_851; // @[L1DCache.scala 424:36]
- wire [1:0] _history_53_3_T_1 = history_53_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_55 = matchSlot[219:216]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3821 = matchSet_55[0] + matchSet_55[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3823 = matchSet_55[2] + matchSet_55[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3825 = _T_3821 + _T_3823; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_54_2 = matchSet_55[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_54_3 = matchSet_55[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_54_1 = {{1'd0}, matchSet_55[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_164 = matchIndices_54_1 | matchIndices_54_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_54 = _matchIndex_T_164 | matchIndices_54_3; // @[Library.scala 76:39]
- wire _T_3834 = io_dbus_valid & io_dbus_ready & setMatch_217; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_865 = 2'h1 == matchIndex_54 ? history_54_1 : history_54_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_866 = 2'h2 == matchIndex_54 ? history_54_2 : _GEN_865; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_867 = 2'h3 == matchIndex_54 ? history_54_3 : _GEN_866; // @[L1DCache.scala 424:{36,36}]
- wire _T_3836 = history_54_0 > _GEN_867; // @[L1DCache.scala 424:36]
- wire [1:0] _history_54_0_T_1 = history_54_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3842 = history_54_1 > _GEN_867; // @[L1DCache.scala 424:36]
- wire [1:0] _history_54_1_T_1 = history_54_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3848 = history_54_2 > _GEN_867; // @[L1DCache.scala 424:36]
- wire [1:0] _history_54_2_T_1 = history_54_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3854 = history_54_3 > _GEN_867; // @[L1DCache.scala 424:36]
- wire [1:0] _history_54_3_T_1 = history_54_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_56 = matchSlot[223:220]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3863 = matchSet_56[0] + matchSet_56[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3865 = matchSet_56[2] + matchSet_56[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3867 = _T_3863 + _T_3865; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_55_2 = matchSet_56[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_55_3 = matchSet_56[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_55_1 = {{1'd0}, matchSet_56[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_167 = matchIndices_55_1 | matchIndices_55_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_55 = _matchIndex_T_167 | matchIndices_55_3; // @[Library.scala 76:39]
- wire _T_3876 = io_dbus_valid & io_dbus_ready & setMatch_221; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_881 = 2'h1 == matchIndex_55 ? history_55_1 : history_55_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_882 = 2'h2 == matchIndex_55 ? history_55_2 : _GEN_881; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_883 = 2'h3 == matchIndex_55 ? history_55_3 : _GEN_882; // @[L1DCache.scala 424:{36,36}]
- wire _T_3878 = history_55_0 > _GEN_883; // @[L1DCache.scala 424:36]
- wire [1:0] _history_55_0_T_1 = history_55_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3884 = history_55_1 > _GEN_883; // @[L1DCache.scala 424:36]
- wire [1:0] _history_55_1_T_1 = history_55_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3890 = history_55_2 > _GEN_883; // @[L1DCache.scala 424:36]
- wire [1:0] _history_55_2_T_1 = history_55_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3896 = history_55_3 > _GEN_883; // @[L1DCache.scala 424:36]
- wire [1:0] _history_55_3_T_1 = history_55_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_57 = matchSlot[227:224]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3905 = matchSet_57[0] + matchSet_57[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3907 = matchSet_57[2] + matchSet_57[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3909 = _T_3905 + _T_3907; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_56_2 = matchSet_57[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_56_3 = matchSet_57[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_56_1 = {{1'd0}, matchSet_57[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_170 = matchIndices_56_1 | matchIndices_56_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_56 = _matchIndex_T_170 | matchIndices_56_3; // @[Library.scala 76:39]
- wire _T_3918 = io_dbus_valid & io_dbus_ready & setMatch_225; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_897 = 2'h1 == matchIndex_56 ? history_56_1 : history_56_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_898 = 2'h2 == matchIndex_56 ? history_56_2 : _GEN_897; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_899 = 2'h3 == matchIndex_56 ? history_56_3 : _GEN_898; // @[L1DCache.scala 424:{36,36}]
- wire _T_3920 = history_56_0 > _GEN_899; // @[L1DCache.scala 424:36]
- wire [1:0] _history_56_0_T_1 = history_56_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3926 = history_56_1 > _GEN_899; // @[L1DCache.scala 424:36]
- wire [1:0] _history_56_1_T_1 = history_56_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3932 = history_56_2 > _GEN_899; // @[L1DCache.scala 424:36]
- wire [1:0] _history_56_2_T_1 = history_56_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3938 = history_56_3 > _GEN_899; // @[L1DCache.scala 424:36]
- wire [1:0] _history_56_3_T_1 = history_56_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_58 = matchSlot[231:228]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3947 = matchSet_58[0] + matchSet_58[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3949 = matchSet_58[2] + matchSet_58[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3951 = _T_3947 + _T_3949; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_57_2 = matchSet_58[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_57_3 = matchSet_58[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_57_1 = {{1'd0}, matchSet_58[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_173 = matchIndices_57_1 | matchIndices_57_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_57 = _matchIndex_T_173 | matchIndices_57_3; // @[Library.scala 76:39]
- wire _T_3960 = io_dbus_valid & io_dbus_ready & setMatch_229; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_913 = 2'h1 == matchIndex_57 ? history_57_1 : history_57_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_914 = 2'h2 == matchIndex_57 ? history_57_2 : _GEN_913; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_915 = 2'h3 == matchIndex_57 ? history_57_3 : _GEN_914; // @[L1DCache.scala 424:{36,36}]
- wire _T_3962 = history_57_0 > _GEN_915; // @[L1DCache.scala 424:36]
- wire [1:0] _history_57_0_T_1 = history_57_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3968 = history_57_1 > _GEN_915; // @[L1DCache.scala 424:36]
- wire [1:0] _history_57_1_T_1 = history_57_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3974 = history_57_2 > _GEN_915; // @[L1DCache.scala 424:36]
- wire [1:0] _history_57_2_T_1 = history_57_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_3980 = history_57_3 > _GEN_915; // @[L1DCache.scala 424:36]
- wire [1:0] _history_57_3_T_1 = history_57_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_59 = matchSlot[235:232]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_3989 = matchSet_59[0] + matchSet_59[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3991 = matchSet_59[2] + matchSet_59[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3993 = _T_3989 + _T_3991; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_58_2 = matchSet_59[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_58_3 = matchSet_59[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_58_1 = {{1'd0}, matchSet_59[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_176 = matchIndices_58_1 | matchIndices_58_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_58 = _matchIndex_T_176 | matchIndices_58_3; // @[Library.scala 76:39]
- wire _T_4002 = io_dbus_valid & io_dbus_ready & setMatch_233; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_929 = 2'h1 == matchIndex_58 ? history_58_1 : history_58_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_930 = 2'h2 == matchIndex_58 ? history_58_2 : _GEN_929; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_931 = 2'h3 == matchIndex_58 ? history_58_3 : _GEN_930; // @[L1DCache.scala 424:{36,36}]
- wire _T_4004 = history_58_0 > _GEN_931; // @[L1DCache.scala 424:36]
- wire [1:0] _history_58_0_T_1 = history_58_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4010 = history_58_1 > _GEN_931; // @[L1DCache.scala 424:36]
- wire [1:0] _history_58_1_T_1 = history_58_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4016 = history_58_2 > _GEN_931; // @[L1DCache.scala 424:36]
- wire [1:0] _history_58_2_T_1 = history_58_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4022 = history_58_3 > _GEN_931; // @[L1DCache.scala 424:36]
- wire [1:0] _history_58_3_T_1 = history_58_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_60 = matchSlot[239:236]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_4031 = matchSet_60[0] + matchSet_60[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_4033 = matchSet_60[2] + matchSet_60[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_4035 = _T_4031 + _T_4033; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_59_2 = matchSet_60[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_59_3 = matchSet_60[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_59_1 = {{1'd0}, matchSet_60[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_179 = matchIndices_59_1 | matchIndices_59_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_59 = _matchIndex_T_179 | matchIndices_59_3; // @[Library.scala 76:39]
- wire _T_4044 = io_dbus_valid & io_dbus_ready & setMatch_237; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_945 = 2'h1 == matchIndex_59 ? history_59_1 : history_59_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_946 = 2'h2 == matchIndex_59 ? history_59_2 : _GEN_945; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_947 = 2'h3 == matchIndex_59 ? history_59_3 : _GEN_946; // @[L1DCache.scala 424:{36,36}]
- wire _T_4046 = history_59_0 > _GEN_947; // @[L1DCache.scala 424:36]
- wire [1:0] _history_59_0_T_1 = history_59_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4052 = history_59_1 > _GEN_947; // @[L1DCache.scala 424:36]
- wire [1:0] _history_59_1_T_1 = history_59_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4058 = history_59_2 > _GEN_947; // @[L1DCache.scala 424:36]
- wire [1:0] _history_59_2_T_1 = history_59_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4064 = history_59_3 > _GEN_947; // @[L1DCache.scala 424:36]
- wire [1:0] _history_59_3_T_1 = history_59_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_61 = matchSlot[243:240]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_4073 = matchSet_61[0] + matchSet_61[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_4075 = matchSet_61[2] + matchSet_61[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_4077 = _T_4073 + _T_4075; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_60_2 = matchSet_61[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_60_3 = matchSet_61[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_60_1 = {{1'd0}, matchSet_61[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_182 = matchIndices_60_1 | matchIndices_60_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_60 = _matchIndex_T_182 | matchIndices_60_3; // @[Library.scala 76:39]
- wire _T_4086 = io_dbus_valid & io_dbus_ready & setMatch_241; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_961 = 2'h1 == matchIndex_60 ? history_60_1 : history_60_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_962 = 2'h2 == matchIndex_60 ? history_60_2 : _GEN_961; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_963 = 2'h3 == matchIndex_60 ? history_60_3 : _GEN_962; // @[L1DCache.scala 424:{36,36}]
- wire _T_4088 = history_60_0 > _GEN_963; // @[L1DCache.scala 424:36]
- wire [1:0] _history_60_0_T_1 = history_60_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4094 = history_60_1 > _GEN_963; // @[L1DCache.scala 424:36]
- wire [1:0] _history_60_1_T_1 = history_60_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4100 = history_60_2 > _GEN_963; // @[L1DCache.scala 424:36]
- wire [1:0] _history_60_2_T_1 = history_60_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4106 = history_60_3 > _GEN_963; // @[L1DCache.scala 424:36]
- wire [1:0] _history_60_3_T_1 = history_60_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_62 = matchSlot[247:244]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_4115 = matchSet_62[0] + matchSet_62[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_4117 = matchSet_62[2] + matchSet_62[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_4119 = _T_4115 + _T_4117; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_61_2 = matchSet_62[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_61_3 = matchSet_62[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_61_1 = {{1'd0}, matchSet_62[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_185 = matchIndices_61_1 | matchIndices_61_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_61 = _matchIndex_T_185 | matchIndices_61_3; // @[Library.scala 76:39]
- wire _T_4128 = io_dbus_valid & io_dbus_ready & setMatch_245; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_977 = 2'h1 == matchIndex_61 ? history_61_1 : history_61_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_978 = 2'h2 == matchIndex_61 ? history_61_2 : _GEN_977; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_979 = 2'h3 == matchIndex_61 ? history_61_3 : _GEN_978; // @[L1DCache.scala 424:{36,36}]
- wire _T_4130 = history_61_0 > _GEN_979; // @[L1DCache.scala 424:36]
- wire [1:0] _history_61_0_T_1 = history_61_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4136 = history_61_1 > _GEN_979; // @[L1DCache.scala 424:36]
- wire [1:0] _history_61_1_T_1 = history_61_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4142 = history_61_2 > _GEN_979; // @[L1DCache.scala 424:36]
- wire [1:0] _history_61_2_T_1 = history_61_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4148 = history_61_3 > _GEN_979; // @[L1DCache.scala 424:36]
- wire [1:0] _history_61_3_T_1 = history_61_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_63 = matchSlot[251:248]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_4157 = matchSet_63[0] + matchSet_63[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_4159 = matchSet_63[2] + matchSet_63[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_4161 = _T_4157 + _T_4159; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_62_2 = matchSet_63[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_62_3 = matchSet_63[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_62_1 = {{1'd0}, matchSet_63[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_188 = matchIndices_62_1 | matchIndices_62_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_62 = _matchIndex_T_188 | matchIndices_62_3; // @[Library.scala 76:39]
- wire _T_4170 = io_dbus_valid & io_dbus_ready & setMatch_249; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_993 = 2'h1 == matchIndex_62 ? history_62_1 : history_62_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_994 = 2'h2 == matchIndex_62 ? history_62_2 : _GEN_993; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_995 = 2'h3 == matchIndex_62 ? history_62_3 : _GEN_994; // @[L1DCache.scala 424:{36,36}]
- wire _T_4172 = history_62_0 > _GEN_995; // @[L1DCache.scala 424:36]
- wire [1:0] _history_62_0_T_1 = history_62_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4178 = history_62_1 > _GEN_995; // @[L1DCache.scala 424:36]
- wire [1:0] _history_62_1_T_1 = history_62_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4184 = history_62_2 > _GEN_995; // @[L1DCache.scala 424:36]
- wire [1:0] _history_62_2_T_1 = history_62_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4190 = history_62_3 > _GEN_995; // @[L1DCache.scala 424:36]
- wire [1:0] _history_62_3_T_1 = history_62_3 - 2'h1; // @[L1DCache.scala 425:42]
- wire [3:0] matchSet_64 = matchSlot[255:252]; // @[L1DCache.scala 409:29]
- wire [1:0] _T_4199 = matchSet_64[0] + matchSet_64[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_4201 = matchSet_64[2] + matchSet_64[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_4203 = _T_4199 + _T_4201; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_63_2 = matchSet_64[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_63_3 = matchSet_64[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_63_1 = {{1'd0}, matchSet_64[1]}; // @[L1DCache.scala 411:28 413:23]
- wire [1:0] _matchIndex_T_191 = matchIndices_63_1 | matchIndices_63_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_63 = _matchIndex_T_191 | matchIndices_63_3; // @[Library.scala 76:39]
- wire _T_4212 = io_dbus_valid & io_dbus_ready & setMatch_253; // @[L1DCache.scala 420:42]
- wire [1:0] _GEN_1009 = 2'h1 == matchIndex_63 ? history_63_1 : history_63_0; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_1010 = 2'h2 == matchIndex_63 ? history_63_2 : _GEN_1009; // @[L1DCache.scala 424:{36,36}]
- wire [1:0] _GEN_1011 = 2'h3 == matchIndex_63 ? history_63_3 : _GEN_1010; // @[L1DCache.scala 424:{36,36}]
- wire _T_4214 = history_63_0 > _GEN_1011; // @[L1DCache.scala 424:36]
- wire [1:0] _history_63_0_T_1 = history_63_0 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4220 = history_63_1 > _GEN_1011; // @[L1DCache.scala 424:36]
- wire [1:0] _history_63_1_T_1 = history_63_1 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4226 = history_63_2 > _GEN_1011; // @[L1DCache.scala 424:36]
- wire [1:0] _history_63_2_T_1 = history_63_2 - 2'h1; // @[L1DCache.scala 425:42]
- wire _T_4232 = history_63_3 > _GEN_1011; // @[L1DCache.scala 424:36]
- wire [1:0] _history_63_3_T_1 = history_63_3 - 2'h1; // @[L1DCache.scala 425:42]
- reg [2:0] fstate; // @[L1DCache.scala 462:23]
- reg flush_0; // @[L1DCache.scala 463:22]
- reg flush_1; // @[L1DCache.scala 463:22]
- reg flush_2; // @[L1DCache.scala 463:22]
- reg flush_3; // @[L1DCache.scala 463:22]
- reg flush_4; // @[L1DCache.scala 463:22]
- reg flush_5; // @[L1DCache.scala 463:22]
- reg flush_6; // @[L1DCache.scala 463:22]
- reg flush_7; // @[L1DCache.scala 463:22]
- reg flush_8; // @[L1DCache.scala 463:22]
- reg flush_9; // @[L1DCache.scala 463:22]
- reg flush_10; // @[L1DCache.scala 463:22]
- reg flush_11; // @[L1DCache.scala 463:22]
- reg flush_12; // @[L1DCache.scala 463:22]
- reg flush_13; // @[L1DCache.scala 463:22]
- reg flush_14; // @[L1DCache.scala 463:22]
- reg flush_15; // @[L1DCache.scala 463:22]
- reg flush_16; // @[L1DCache.scala 463:22]
- reg flush_17; // @[L1DCache.scala 463:22]
- reg flush_18; // @[L1DCache.scala 463:22]
- reg flush_19; // @[L1DCache.scala 463:22]
- reg flush_20; // @[L1DCache.scala 463:22]
- reg flush_21; // @[L1DCache.scala 463:22]
- reg flush_22; // @[L1DCache.scala 463:22]
- reg flush_23; // @[L1DCache.scala 463:22]
- reg flush_24; // @[L1DCache.scala 463:22]
- reg flush_25; // @[L1DCache.scala 463:22]
- reg flush_26; // @[L1DCache.scala 463:22]
- reg flush_27; // @[L1DCache.scala 463:22]
- reg flush_28; // @[L1DCache.scala 463:22]
- reg flush_29; // @[L1DCache.scala 463:22]
- reg flush_30; // @[L1DCache.scala 463:22]
- reg flush_31; // @[L1DCache.scala 463:22]
- reg flush_32; // @[L1DCache.scala 463:22]
- reg flush_33; // @[L1DCache.scala 463:22]
- reg flush_34; // @[L1DCache.scala 463:22]
- reg flush_35; // @[L1DCache.scala 463:22]
- reg flush_36; // @[L1DCache.scala 463:22]
- reg flush_37; // @[L1DCache.scala 463:22]
- reg flush_38; // @[L1DCache.scala 463:22]
- reg flush_39; // @[L1DCache.scala 463:22]
- reg flush_40; // @[L1DCache.scala 463:22]
- reg flush_41; // @[L1DCache.scala 463:22]
- reg flush_42; // @[L1DCache.scala 463:22]
- reg flush_43; // @[L1DCache.scala 463:22]
- reg flush_44; // @[L1DCache.scala 463:22]
- reg flush_45; // @[L1DCache.scala 463:22]
- reg flush_46; // @[L1DCache.scala 463:22]
- reg flush_47; // @[L1DCache.scala 463:22]
- reg flush_48; // @[L1DCache.scala 463:22]
- reg flush_49; // @[L1DCache.scala 463:22]
- reg flush_50; // @[L1DCache.scala 463:22]
- reg flush_51; // @[L1DCache.scala 463:22]
- reg flush_52; // @[L1DCache.scala 463:22]
- reg flush_53; // @[L1DCache.scala 463:22]
- reg flush_54; // @[L1DCache.scala 463:22]
- reg flush_55; // @[L1DCache.scala 463:22]
- reg flush_56; // @[L1DCache.scala 463:22]
- reg flush_57; // @[L1DCache.scala 463:22]
- reg flush_58; // @[L1DCache.scala 463:22]
- reg flush_59; // @[L1DCache.scala 463:22]
- reg flush_60; // @[L1DCache.scala 463:22]
- reg flush_61; // @[L1DCache.scala 463:22]
- reg flush_62; // @[L1DCache.scala 463:22]
- reg flush_63; // @[L1DCache.scala 463:22]
- reg flush_64; // @[L1DCache.scala 463:22]
- reg flush_65; // @[L1DCache.scala 463:22]
- reg flush_66; // @[L1DCache.scala 463:22]
- reg flush_67; // @[L1DCache.scala 463:22]
- reg flush_68; // @[L1DCache.scala 463:22]
- reg flush_69; // @[L1DCache.scala 463:22]
- reg flush_70; // @[L1DCache.scala 463:22]
- reg flush_71; // @[L1DCache.scala 463:22]
- reg flush_72; // @[L1DCache.scala 463:22]
- reg flush_73; // @[L1DCache.scala 463:22]
- reg flush_74; // @[L1DCache.scala 463:22]
- reg flush_75; // @[L1DCache.scala 463:22]
- reg flush_76; // @[L1DCache.scala 463:22]
- reg flush_77; // @[L1DCache.scala 463:22]
- reg flush_78; // @[L1DCache.scala 463:22]
- reg flush_79; // @[L1DCache.scala 463:22]
- reg flush_80; // @[L1DCache.scala 463:22]
- reg flush_81; // @[L1DCache.scala 463:22]
- reg flush_82; // @[L1DCache.scala 463:22]
- reg flush_83; // @[L1DCache.scala 463:22]
- reg flush_84; // @[L1DCache.scala 463:22]
- reg flush_85; // @[L1DCache.scala 463:22]
- reg flush_86; // @[L1DCache.scala 463:22]
- reg flush_87; // @[L1DCache.scala 463:22]
- reg flush_88; // @[L1DCache.scala 463:22]
- reg flush_89; // @[L1DCache.scala 463:22]
- reg flush_90; // @[L1DCache.scala 463:22]
- reg flush_91; // @[L1DCache.scala 463:22]
- reg flush_92; // @[L1DCache.scala 463:22]
- reg flush_93; // @[L1DCache.scala 463:22]
- reg flush_94; // @[L1DCache.scala 463:22]
- reg flush_95; // @[L1DCache.scala 463:22]
- reg flush_96; // @[L1DCache.scala 463:22]
- reg flush_97; // @[L1DCache.scala 463:22]
- reg flush_98; // @[L1DCache.scala 463:22]
- reg flush_99; // @[L1DCache.scala 463:22]
- reg flush_100; // @[L1DCache.scala 463:22]
- reg flush_101; // @[L1DCache.scala 463:22]
- reg flush_102; // @[L1DCache.scala 463:22]
- reg flush_103; // @[L1DCache.scala 463:22]
- reg flush_104; // @[L1DCache.scala 463:22]
- reg flush_105; // @[L1DCache.scala 463:22]
- reg flush_106; // @[L1DCache.scala 463:22]
- reg flush_107; // @[L1DCache.scala 463:22]
- reg flush_108; // @[L1DCache.scala 463:22]
- reg flush_109; // @[L1DCache.scala 463:22]
- reg flush_110; // @[L1DCache.scala 463:22]
- reg flush_111; // @[L1DCache.scala 463:22]
- reg flush_112; // @[L1DCache.scala 463:22]
- reg flush_113; // @[L1DCache.scala 463:22]
- reg flush_114; // @[L1DCache.scala 463:22]
- reg flush_115; // @[L1DCache.scala 463:22]
- reg flush_116; // @[L1DCache.scala 463:22]
- reg flush_117; // @[L1DCache.scala 463:22]
- reg flush_118; // @[L1DCache.scala 463:22]
- reg flush_119; // @[L1DCache.scala 463:22]
- reg flush_120; // @[L1DCache.scala 463:22]
- reg flush_121; // @[L1DCache.scala 463:22]
- reg flush_122; // @[L1DCache.scala 463:22]
- reg flush_123; // @[L1DCache.scala 463:22]
- reg flush_124; // @[L1DCache.scala 463:22]
- reg flush_125; // @[L1DCache.scala 463:22]
- reg flush_126; // @[L1DCache.scala 463:22]
- reg flush_127; // @[L1DCache.scala 463:22]
- reg flush_128; // @[L1DCache.scala 463:22]
- reg flush_129; // @[L1DCache.scala 463:22]
- reg flush_130; // @[L1DCache.scala 463:22]
- reg flush_131; // @[L1DCache.scala 463:22]
- reg flush_132; // @[L1DCache.scala 463:22]
- reg flush_133; // @[L1DCache.scala 463:22]
- reg flush_134; // @[L1DCache.scala 463:22]
- reg flush_135; // @[L1DCache.scala 463:22]
- reg flush_136; // @[L1DCache.scala 463:22]
- reg flush_137; // @[L1DCache.scala 463:22]
- reg flush_138; // @[L1DCache.scala 463:22]
- reg flush_139; // @[L1DCache.scala 463:22]
- reg flush_140; // @[L1DCache.scala 463:22]
- reg flush_141; // @[L1DCache.scala 463:22]
- reg flush_142; // @[L1DCache.scala 463:22]
- reg flush_143; // @[L1DCache.scala 463:22]
- reg flush_144; // @[L1DCache.scala 463:22]
- reg flush_145; // @[L1DCache.scala 463:22]
- reg flush_146; // @[L1DCache.scala 463:22]
- reg flush_147; // @[L1DCache.scala 463:22]
- reg flush_148; // @[L1DCache.scala 463:22]
- reg flush_149; // @[L1DCache.scala 463:22]
- reg flush_150; // @[L1DCache.scala 463:22]
- reg flush_151; // @[L1DCache.scala 463:22]
- reg flush_152; // @[L1DCache.scala 463:22]
- reg flush_153; // @[L1DCache.scala 463:22]
- reg flush_154; // @[L1DCache.scala 463:22]
- reg flush_155; // @[L1DCache.scala 463:22]
- reg flush_156; // @[L1DCache.scala 463:22]
- reg flush_157; // @[L1DCache.scala 463:22]
- reg flush_158; // @[L1DCache.scala 463:22]
- reg flush_159; // @[L1DCache.scala 463:22]
- reg flush_160; // @[L1DCache.scala 463:22]
- reg flush_161; // @[L1DCache.scala 463:22]
- reg flush_162; // @[L1DCache.scala 463:22]
- reg flush_163; // @[L1DCache.scala 463:22]
- reg flush_164; // @[L1DCache.scala 463:22]
- reg flush_165; // @[L1DCache.scala 463:22]
- reg flush_166; // @[L1DCache.scala 463:22]
- reg flush_167; // @[L1DCache.scala 463:22]
- reg flush_168; // @[L1DCache.scala 463:22]
- reg flush_169; // @[L1DCache.scala 463:22]
- reg flush_170; // @[L1DCache.scala 463:22]
- reg flush_171; // @[L1DCache.scala 463:22]
- reg flush_172; // @[L1DCache.scala 463:22]
- reg flush_173; // @[L1DCache.scala 463:22]
- reg flush_174; // @[L1DCache.scala 463:22]
- reg flush_175; // @[L1DCache.scala 463:22]
- reg flush_176; // @[L1DCache.scala 463:22]
- reg flush_177; // @[L1DCache.scala 463:22]
- reg flush_178; // @[L1DCache.scala 463:22]
- reg flush_179; // @[L1DCache.scala 463:22]
- reg flush_180; // @[L1DCache.scala 463:22]
- reg flush_181; // @[L1DCache.scala 463:22]
- reg flush_182; // @[L1DCache.scala 463:22]
- reg flush_183; // @[L1DCache.scala 463:22]
- reg flush_184; // @[L1DCache.scala 463:22]
- reg flush_185; // @[L1DCache.scala 463:22]
- reg flush_186; // @[L1DCache.scala 463:22]
- reg flush_187; // @[L1DCache.scala 463:22]
- reg flush_188; // @[L1DCache.scala 463:22]
- reg flush_189; // @[L1DCache.scala 463:22]
- reg flush_190; // @[L1DCache.scala 463:22]
- reg flush_191; // @[L1DCache.scala 463:22]
- reg flush_192; // @[L1DCache.scala 463:22]
- reg flush_193; // @[L1DCache.scala 463:22]
- reg flush_194; // @[L1DCache.scala 463:22]
- reg flush_195; // @[L1DCache.scala 463:22]
- reg flush_196; // @[L1DCache.scala 463:22]
- reg flush_197; // @[L1DCache.scala 463:22]
- reg flush_198; // @[L1DCache.scala 463:22]
- reg flush_199; // @[L1DCache.scala 463:22]
- reg flush_200; // @[L1DCache.scala 463:22]
- reg flush_201; // @[L1DCache.scala 463:22]
- reg flush_202; // @[L1DCache.scala 463:22]
- reg flush_203; // @[L1DCache.scala 463:22]
- reg flush_204; // @[L1DCache.scala 463:22]
- reg flush_205; // @[L1DCache.scala 463:22]
- reg flush_206; // @[L1DCache.scala 463:22]
- reg flush_207; // @[L1DCache.scala 463:22]
- reg flush_208; // @[L1DCache.scala 463:22]
- reg flush_209; // @[L1DCache.scala 463:22]
- reg flush_210; // @[L1DCache.scala 463:22]
- reg flush_211; // @[L1DCache.scala 463:22]
- reg flush_212; // @[L1DCache.scala 463:22]
- reg flush_213; // @[L1DCache.scala 463:22]
- reg flush_214; // @[L1DCache.scala 463:22]
- reg flush_215; // @[L1DCache.scala 463:22]
- reg flush_216; // @[L1DCache.scala 463:22]
- reg flush_217; // @[L1DCache.scala 463:22]
- reg flush_218; // @[L1DCache.scala 463:22]
- reg flush_219; // @[L1DCache.scala 463:22]
- reg flush_220; // @[L1DCache.scala 463:22]
- reg flush_221; // @[L1DCache.scala 463:22]
- reg flush_222; // @[L1DCache.scala 463:22]
- reg flush_223; // @[L1DCache.scala 463:22]
- reg flush_224; // @[L1DCache.scala 463:22]
- reg flush_225; // @[L1DCache.scala 463:22]
- reg flush_226; // @[L1DCache.scala 463:22]
- reg flush_227; // @[L1DCache.scala 463:22]
- reg flush_228; // @[L1DCache.scala 463:22]
- reg flush_229; // @[L1DCache.scala 463:22]
- reg flush_230; // @[L1DCache.scala 463:22]
- reg flush_231; // @[L1DCache.scala 463:22]
- reg flush_232; // @[L1DCache.scala 463:22]
- reg flush_233; // @[L1DCache.scala 463:22]
- reg flush_234; // @[L1DCache.scala 463:22]
- reg flush_235; // @[L1DCache.scala 463:22]
- reg flush_236; // @[L1DCache.scala 463:22]
- reg flush_237; // @[L1DCache.scala 463:22]
- reg flush_238; // @[L1DCache.scala 463:22]
- reg flush_239; // @[L1DCache.scala 463:22]
- reg flush_240; // @[L1DCache.scala 463:22]
- reg flush_241; // @[L1DCache.scala 463:22]
- reg flush_242; // @[L1DCache.scala 463:22]
- reg flush_243; // @[L1DCache.scala 463:22]
- reg flush_244; // @[L1DCache.scala 463:22]
- reg flush_245; // @[L1DCache.scala 463:22]
- reg flush_246; // @[L1DCache.scala 463:22]
- reg flush_247; // @[L1DCache.scala 463:22]
- reg flush_248; // @[L1DCache.scala 463:22]
- reg flush_249; // @[L1DCache.scala 463:22]
- reg flush_250; // @[L1DCache.scala 463:22]
- reg flush_251; // @[L1DCache.scala 463:22]
- reg flush_252; // @[L1DCache.scala 463:22]
- reg flush_253; // @[L1DCache.scala 463:22]
- reg flush_254; // @[L1DCache.scala 463:22]
- reg flush_255; // @[L1DCache.scala 463:22]
- reg ractive; // @[L1DCache.scala 467:24]
- reg wactive; // @[L1DCache.scala 468:24]
- wire active = ractive | wactive; // @[L1DCache.scala 469:24]
- reg axiraddrvalid; // @[L1DCache.scala 473:30]
- reg axirdataready; // @[L1DCache.scala 474:30]
- reg axiwrite; // @[L1DCache.scala 476:27]
- reg memwdataEn; // @[L1DCache.scala 477:27]
- reg axiwaddrvalid; // @[L1DCache.scala 478:30]
- reg axiwdatavalid; // @[L1DCache.scala 479:30]
- reg [255:0] axiwdatabuf; // @[L1DCache.scala 480:24]
- reg [31:0] axiwstrbbuf; // @[L1DCache.scala 481:24]
- reg [31:0] axiraddr; // @[L1DCache.scala 483:21]
- reg [31:0] axiwaddr; // @[L1DCache.scala 484:21]
- reg [7:0] replaceIdReg; // @[L1DCache.scala 486:25]
- wire [30:0] alignedAddr = {io_dbus_addr[30:5],5'h0}; // @[Cat.scala 31:58]
- wire _T_4247 = io_dbus_valid & ~io_dbus_ready & ~active; // @[L1DCache.scala 490:41]
- wire _GEN_1281 = 8'h1 == replaceId ? dirty_1 : dirty_0; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1282 = 8'h2 == replaceId ? dirty_2 : _GEN_1281; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1283 = 8'h3 == replaceId ? dirty_3 : _GEN_1282; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1284 = 8'h4 == replaceId ? dirty_4 : _GEN_1283; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1285 = 8'h5 == replaceId ? dirty_5 : _GEN_1284; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1286 = 8'h6 == replaceId ? dirty_6 : _GEN_1285; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1287 = 8'h7 == replaceId ? dirty_7 : _GEN_1286; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1288 = 8'h8 == replaceId ? dirty_8 : _GEN_1287; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1289 = 8'h9 == replaceId ? dirty_9 : _GEN_1288; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1290 = 8'ha == replaceId ? dirty_10 : _GEN_1289; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1291 = 8'hb == replaceId ? dirty_11 : _GEN_1290; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1292 = 8'hc == replaceId ? dirty_12 : _GEN_1291; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1293 = 8'hd == replaceId ? dirty_13 : _GEN_1292; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1294 = 8'he == replaceId ? dirty_14 : _GEN_1293; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1295 = 8'hf == replaceId ? dirty_15 : _GEN_1294; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1296 = 8'h10 == replaceId ? dirty_16 : _GEN_1295; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1297 = 8'h11 == replaceId ? dirty_17 : _GEN_1296; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1298 = 8'h12 == replaceId ? dirty_18 : _GEN_1297; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1299 = 8'h13 == replaceId ? dirty_19 : _GEN_1298; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1300 = 8'h14 == replaceId ? dirty_20 : _GEN_1299; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1301 = 8'h15 == replaceId ? dirty_21 : _GEN_1300; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1302 = 8'h16 == replaceId ? dirty_22 : _GEN_1301; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1303 = 8'h17 == replaceId ? dirty_23 : _GEN_1302; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1304 = 8'h18 == replaceId ? dirty_24 : _GEN_1303; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1305 = 8'h19 == replaceId ? dirty_25 : _GEN_1304; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1306 = 8'h1a == replaceId ? dirty_26 : _GEN_1305; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1307 = 8'h1b == replaceId ? dirty_27 : _GEN_1306; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1308 = 8'h1c == replaceId ? dirty_28 : _GEN_1307; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1309 = 8'h1d == replaceId ? dirty_29 : _GEN_1308; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1310 = 8'h1e == replaceId ? dirty_30 : _GEN_1309; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1311 = 8'h1f == replaceId ? dirty_31 : _GEN_1310; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1312 = 8'h20 == replaceId ? dirty_32 : _GEN_1311; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1313 = 8'h21 == replaceId ? dirty_33 : _GEN_1312; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1314 = 8'h22 == replaceId ? dirty_34 : _GEN_1313; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1315 = 8'h23 == replaceId ? dirty_35 : _GEN_1314; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1316 = 8'h24 == replaceId ? dirty_36 : _GEN_1315; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1317 = 8'h25 == replaceId ? dirty_37 : _GEN_1316; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1318 = 8'h26 == replaceId ? dirty_38 : _GEN_1317; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1319 = 8'h27 == replaceId ? dirty_39 : _GEN_1318; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1320 = 8'h28 == replaceId ? dirty_40 : _GEN_1319; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1321 = 8'h29 == replaceId ? dirty_41 : _GEN_1320; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1322 = 8'h2a == replaceId ? dirty_42 : _GEN_1321; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1323 = 8'h2b == replaceId ? dirty_43 : _GEN_1322; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1324 = 8'h2c == replaceId ? dirty_44 : _GEN_1323; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1325 = 8'h2d == replaceId ? dirty_45 : _GEN_1324; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1326 = 8'h2e == replaceId ? dirty_46 : _GEN_1325; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1327 = 8'h2f == replaceId ? dirty_47 : _GEN_1326; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1328 = 8'h30 == replaceId ? dirty_48 : _GEN_1327; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1329 = 8'h31 == replaceId ? dirty_49 : _GEN_1328; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1330 = 8'h32 == replaceId ? dirty_50 : _GEN_1329; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1331 = 8'h33 == replaceId ? dirty_51 : _GEN_1330; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1332 = 8'h34 == replaceId ? dirty_52 : _GEN_1331; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1333 = 8'h35 == replaceId ? dirty_53 : _GEN_1332; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1334 = 8'h36 == replaceId ? dirty_54 : _GEN_1333; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1335 = 8'h37 == replaceId ? dirty_55 : _GEN_1334; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1336 = 8'h38 == replaceId ? dirty_56 : _GEN_1335; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1337 = 8'h39 == replaceId ? dirty_57 : _GEN_1336; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1338 = 8'h3a == replaceId ? dirty_58 : _GEN_1337; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1339 = 8'h3b == replaceId ? dirty_59 : _GEN_1338; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1340 = 8'h3c == replaceId ? dirty_60 : _GEN_1339; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1341 = 8'h3d == replaceId ? dirty_61 : _GEN_1340; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1342 = 8'h3e == replaceId ? dirty_62 : _GEN_1341; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1343 = 8'h3f == replaceId ? dirty_63 : _GEN_1342; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1344 = 8'h40 == replaceId ? dirty_64 : _GEN_1343; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1345 = 8'h41 == replaceId ? dirty_65 : _GEN_1344; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1346 = 8'h42 == replaceId ? dirty_66 : _GEN_1345; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1347 = 8'h43 == replaceId ? dirty_67 : _GEN_1346; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1348 = 8'h44 == replaceId ? dirty_68 : _GEN_1347; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1349 = 8'h45 == replaceId ? dirty_69 : _GEN_1348; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1350 = 8'h46 == replaceId ? dirty_70 : _GEN_1349; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1351 = 8'h47 == replaceId ? dirty_71 : _GEN_1350; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1352 = 8'h48 == replaceId ? dirty_72 : _GEN_1351; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1353 = 8'h49 == replaceId ? dirty_73 : _GEN_1352; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1354 = 8'h4a == replaceId ? dirty_74 : _GEN_1353; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1355 = 8'h4b == replaceId ? dirty_75 : _GEN_1354; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1356 = 8'h4c == replaceId ? dirty_76 : _GEN_1355; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1357 = 8'h4d == replaceId ? dirty_77 : _GEN_1356; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1358 = 8'h4e == replaceId ? dirty_78 : _GEN_1357; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1359 = 8'h4f == replaceId ? dirty_79 : _GEN_1358; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1360 = 8'h50 == replaceId ? dirty_80 : _GEN_1359; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1361 = 8'h51 == replaceId ? dirty_81 : _GEN_1360; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1362 = 8'h52 == replaceId ? dirty_82 : _GEN_1361; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1363 = 8'h53 == replaceId ? dirty_83 : _GEN_1362; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1364 = 8'h54 == replaceId ? dirty_84 : _GEN_1363; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1365 = 8'h55 == replaceId ? dirty_85 : _GEN_1364; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1366 = 8'h56 == replaceId ? dirty_86 : _GEN_1365; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1367 = 8'h57 == replaceId ? dirty_87 : _GEN_1366; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1368 = 8'h58 == replaceId ? dirty_88 : _GEN_1367; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1369 = 8'h59 == replaceId ? dirty_89 : _GEN_1368; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1370 = 8'h5a == replaceId ? dirty_90 : _GEN_1369; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1371 = 8'h5b == replaceId ? dirty_91 : _GEN_1370; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1372 = 8'h5c == replaceId ? dirty_92 : _GEN_1371; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1373 = 8'h5d == replaceId ? dirty_93 : _GEN_1372; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1374 = 8'h5e == replaceId ? dirty_94 : _GEN_1373; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1375 = 8'h5f == replaceId ? dirty_95 : _GEN_1374; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1376 = 8'h60 == replaceId ? dirty_96 : _GEN_1375; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1377 = 8'h61 == replaceId ? dirty_97 : _GEN_1376; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1378 = 8'h62 == replaceId ? dirty_98 : _GEN_1377; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1379 = 8'h63 == replaceId ? dirty_99 : _GEN_1378; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1380 = 8'h64 == replaceId ? dirty_100 : _GEN_1379; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1381 = 8'h65 == replaceId ? dirty_101 : _GEN_1380; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1382 = 8'h66 == replaceId ? dirty_102 : _GEN_1381; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1383 = 8'h67 == replaceId ? dirty_103 : _GEN_1382; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1384 = 8'h68 == replaceId ? dirty_104 : _GEN_1383; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1385 = 8'h69 == replaceId ? dirty_105 : _GEN_1384; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1386 = 8'h6a == replaceId ? dirty_106 : _GEN_1385; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1387 = 8'h6b == replaceId ? dirty_107 : _GEN_1386; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1388 = 8'h6c == replaceId ? dirty_108 : _GEN_1387; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1389 = 8'h6d == replaceId ? dirty_109 : _GEN_1388; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1390 = 8'h6e == replaceId ? dirty_110 : _GEN_1389; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1391 = 8'h6f == replaceId ? dirty_111 : _GEN_1390; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1392 = 8'h70 == replaceId ? dirty_112 : _GEN_1391; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1393 = 8'h71 == replaceId ? dirty_113 : _GEN_1392; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1394 = 8'h72 == replaceId ? dirty_114 : _GEN_1393; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1395 = 8'h73 == replaceId ? dirty_115 : _GEN_1394; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1396 = 8'h74 == replaceId ? dirty_116 : _GEN_1395; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1397 = 8'h75 == replaceId ? dirty_117 : _GEN_1396; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1398 = 8'h76 == replaceId ? dirty_118 : _GEN_1397; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1399 = 8'h77 == replaceId ? dirty_119 : _GEN_1398; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1400 = 8'h78 == replaceId ? dirty_120 : _GEN_1399; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1401 = 8'h79 == replaceId ? dirty_121 : _GEN_1400; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1402 = 8'h7a == replaceId ? dirty_122 : _GEN_1401; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1403 = 8'h7b == replaceId ? dirty_123 : _GEN_1402; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1404 = 8'h7c == replaceId ? dirty_124 : _GEN_1403; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1405 = 8'h7d == replaceId ? dirty_125 : _GEN_1404; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1406 = 8'h7e == replaceId ? dirty_126 : _GEN_1405; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1407 = 8'h7f == replaceId ? dirty_127 : _GEN_1406; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1408 = 8'h80 == replaceId ? dirty_128 : _GEN_1407; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1409 = 8'h81 == replaceId ? dirty_129 : _GEN_1408; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1410 = 8'h82 == replaceId ? dirty_130 : _GEN_1409; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1411 = 8'h83 == replaceId ? dirty_131 : _GEN_1410; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1412 = 8'h84 == replaceId ? dirty_132 : _GEN_1411; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1413 = 8'h85 == replaceId ? dirty_133 : _GEN_1412; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1414 = 8'h86 == replaceId ? dirty_134 : _GEN_1413; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1415 = 8'h87 == replaceId ? dirty_135 : _GEN_1414; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1416 = 8'h88 == replaceId ? dirty_136 : _GEN_1415; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1417 = 8'h89 == replaceId ? dirty_137 : _GEN_1416; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1418 = 8'h8a == replaceId ? dirty_138 : _GEN_1417; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1419 = 8'h8b == replaceId ? dirty_139 : _GEN_1418; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1420 = 8'h8c == replaceId ? dirty_140 : _GEN_1419; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1421 = 8'h8d == replaceId ? dirty_141 : _GEN_1420; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1422 = 8'h8e == replaceId ? dirty_142 : _GEN_1421; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1423 = 8'h8f == replaceId ? dirty_143 : _GEN_1422; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1424 = 8'h90 == replaceId ? dirty_144 : _GEN_1423; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1425 = 8'h91 == replaceId ? dirty_145 : _GEN_1424; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1426 = 8'h92 == replaceId ? dirty_146 : _GEN_1425; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1427 = 8'h93 == replaceId ? dirty_147 : _GEN_1426; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1428 = 8'h94 == replaceId ? dirty_148 : _GEN_1427; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1429 = 8'h95 == replaceId ? dirty_149 : _GEN_1428; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1430 = 8'h96 == replaceId ? dirty_150 : _GEN_1429; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1431 = 8'h97 == replaceId ? dirty_151 : _GEN_1430; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1432 = 8'h98 == replaceId ? dirty_152 : _GEN_1431; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1433 = 8'h99 == replaceId ? dirty_153 : _GEN_1432; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1434 = 8'h9a == replaceId ? dirty_154 : _GEN_1433; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1435 = 8'h9b == replaceId ? dirty_155 : _GEN_1434; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1436 = 8'h9c == replaceId ? dirty_156 : _GEN_1435; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1437 = 8'h9d == replaceId ? dirty_157 : _GEN_1436; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1438 = 8'h9e == replaceId ? dirty_158 : _GEN_1437; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1439 = 8'h9f == replaceId ? dirty_159 : _GEN_1438; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1440 = 8'ha0 == replaceId ? dirty_160 : _GEN_1439; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1441 = 8'ha1 == replaceId ? dirty_161 : _GEN_1440; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1442 = 8'ha2 == replaceId ? dirty_162 : _GEN_1441; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1443 = 8'ha3 == replaceId ? dirty_163 : _GEN_1442; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1444 = 8'ha4 == replaceId ? dirty_164 : _GEN_1443; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1445 = 8'ha5 == replaceId ? dirty_165 : _GEN_1444; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1446 = 8'ha6 == replaceId ? dirty_166 : _GEN_1445; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1447 = 8'ha7 == replaceId ? dirty_167 : _GEN_1446; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1448 = 8'ha8 == replaceId ? dirty_168 : _GEN_1447; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1449 = 8'ha9 == replaceId ? dirty_169 : _GEN_1448; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1450 = 8'haa == replaceId ? dirty_170 : _GEN_1449; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1451 = 8'hab == replaceId ? dirty_171 : _GEN_1450; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1452 = 8'hac == replaceId ? dirty_172 : _GEN_1451; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1453 = 8'had == replaceId ? dirty_173 : _GEN_1452; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1454 = 8'hae == replaceId ? dirty_174 : _GEN_1453; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1455 = 8'haf == replaceId ? dirty_175 : _GEN_1454; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1456 = 8'hb0 == replaceId ? dirty_176 : _GEN_1455; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1457 = 8'hb1 == replaceId ? dirty_177 : _GEN_1456; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1458 = 8'hb2 == replaceId ? dirty_178 : _GEN_1457; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1459 = 8'hb3 == replaceId ? dirty_179 : _GEN_1458; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1460 = 8'hb4 == replaceId ? dirty_180 : _GEN_1459; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1461 = 8'hb5 == replaceId ? dirty_181 : _GEN_1460; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1462 = 8'hb6 == replaceId ? dirty_182 : _GEN_1461; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1463 = 8'hb7 == replaceId ? dirty_183 : _GEN_1462; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1464 = 8'hb8 == replaceId ? dirty_184 : _GEN_1463; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1465 = 8'hb9 == replaceId ? dirty_185 : _GEN_1464; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1466 = 8'hba == replaceId ? dirty_186 : _GEN_1465; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1467 = 8'hbb == replaceId ? dirty_187 : _GEN_1466; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1468 = 8'hbc == replaceId ? dirty_188 : _GEN_1467; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1469 = 8'hbd == replaceId ? dirty_189 : _GEN_1468; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1470 = 8'hbe == replaceId ? dirty_190 : _GEN_1469; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1471 = 8'hbf == replaceId ? dirty_191 : _GEN_1470; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1472 = 8'hc0 == replaceId ? dirty_192 : _GEN_1471; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1473 = 8'hc1 == replaceId ? dirty_193 : _GEN_1472; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1474 = 8'hc2 == replaceId ? dirty_194 : _GEN_1473; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1475 = 8'hc3 == replaceId ? dirty_195 : _GEN_1474; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1476 = 8'hc4 == replaceId ? dirty_196 : _GEN_1475; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1477 = 8'hc5 == replaceId ? dirty_197 : _GEN_1476; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1478 = 8'hc6 == replaceId ? dirty_198 : _GEN_1477; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1479 = 8'hc7 == replaceId ? dirty_199 : _GEN_1478; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1480 = 8'hc8 == replaceId ? dirty_200 : _GEN_1479; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1481 = 8'hc9 == replaceId ? dirty_201 : _GEN_1480; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1482 = 8'hca == replaceId ? dirty_202 : _GEN_1481; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1483 = 8'hcb == replaceId ? dirty_203 : _GEN_1482; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1484 = 8'hcc == replaceId ? dirty_204 : _GEN_1483; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1485 = 8'hcd == replaceId ? dirty_205 : _GEN_1484; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1486 = 8'hce == replaceId ? dirty_206 : _GEN_1485; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1487 = 8'hcf == replaceId ? dirty_207 : _GEN_1486; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1488 = 8'hd0 == replaceId ? dirty_208 : _GEN_1487; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1489 = 8'hd1 == replaceId ? dirty_209 : _GEN_1488; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1490 = 8'hd2 == replaceId ? dirty_210 : _GEN_1489; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1491 = 8'hd3 == replaceId ? dirty_211 : _GEN_1490; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1492 = 8'hd4 == replaceId ? dirty_212 : _GEN_1491; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1493 = 8'hd5 == replaceId ? dirty_213 : _GEN_1492; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1494 = 8'hd6 == replaceId ? dirty_214 : _GEN_1493; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1495 = 8'hd7 == replaceId ? dirty_215 : _GEN_1494; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1496 = 8'hd8 == replaceId ? dirty_216 : _GEN_1495; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1497 = 8'hd9 == replaceId ? dirty_217 : _GEN_1496; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1498 = 8'hda == replaceId ? dirty_218 : _GEN_1497; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1499 = 8'hdb == replaceId ? dirty_219 : _GEN_1498; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1500 = 8'hdc == replaceId ? dirty_220 : _GEN_1499; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1501 = 8'hdd == replaceId ? dirty_221 : _GEN_1500; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1502 = 8'hde == replaceId ? dirty_222 : _GEN_1501; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1503 = 8'hdf == replaceId ? dirty_223 : _GEN_1502; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1504 = 8'he0 == replaceId ? dirty_224 : _GEN_1503; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1505 = 8'he1 == replaceId ? dirty_225 : _GEN_1504; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1506 = 8'he2 == replaceId ? dirty_226 : _GEN_1505; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1507 = 8'he3 == replaceId ? dirty_227 : _GEN_1506; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1508 = 8'he4 == replaceId ? dirty_228 : _GEN_1507; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1509 = 8'he5 == replaceId ? dirty_229 : _GEN_1508; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1510 = 8'he6 == replaceId ? dirty_230 : _GEN_1509; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1511 = 8'he7 == replaceId ? dirty_231 : _GEN_1510; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1512 = 8'he8 == replaceId ? dirty_232 : _GEN_1511; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1513 = 8'he9 == replaceId ? dirty_233 : _GEN_1512; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1514 = 8'hea == replaceId ? dirty_234 : _GEN_1513; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1515 = 8'heb == replaceId ? dirty_235 : _GEN_1514; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1516 = 8'hec == replaceId ? dirty_236 : _GEN_1515; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1517 = 8'hed == replaceId ? dirty_237 : _GEN_1516; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1518 = 8'hee == replaceId ? dirty_238 : _GEN_1517; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1519 = 8'hef == replaceId ? dirty_239 : _GEN_1518; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1520 = 8'hf0 == replaceId ? dirty_240 : _GEN_1519; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1521 = 8'hf1 == replaceId ? dirty_241 : _GEN_1520; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1522 = 8'hf2 == replaceId ? dirty_242 : _GEN_1521; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1523 = 8'hf3 == replaceId ? dirty_243 : _GEN_1522; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1524 = 8'hf4 == replaceId ? dirty_244 : _GEN_1523; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1525 = 8'hf5 == replaceId ? dirty_245 : _GEN_1524; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1526 = 8'hf6 == replaceId ? dirty_246 : _GEN_1525; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1527 = 8'hf7 == replaceId ? dirty_247 : _GEN_1526; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1528 = 8'hf8 == replaceId ? dirty_248 : _GEN_1527; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1529 = 8'hf9 == replaceId ? dirty_249 : _GEN_1528; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1530 = 8'hfa == replaceId ? dirty_250 : _GEN_1529; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1531 = 8'hfb == replaceId ? dirty_251 : _GEN_1530; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1532 = 8'hfc == replaceId ? dirty_252 : _GEN_1531; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1533 = 8'hfd == replaceId ? dirty_253 : _GEN_1532; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1534 = 8'hfe == replaceId ? dirty_254 : _GEN_1533; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1535 = 8'hff == replaceId ? dirty_255 : _GEN_1534; // @[L1DCache.scala 492:{13,13}]
- wire _GEN_1537 = 8'h1 == replaceId ? valid_1 : valid_0; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1538 = 8'h2 == replaceId ? valid_2 : _GEN_1537; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1539 = 8'h3 == replaceId ? valid_3 : _GEN_1538; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1540 = 8'h4 == replaceId ? valid_4 : _GEN_1539; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1541 = 8'h5 == replaceId ? valid_5 : _GEN_1540; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1542 = 8'h6 == replaceId ? valid_6 : _GEN_1541; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1543 = 8'h7 == replaceId ? valid_7 : _GEN_1542; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1544 = 8'h8 == replaceId ? valid_8 : _GEN_1543; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1545 = 8'h9 == replaceId ? valid_9 : _GEN_1544; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1546 = 8'ha == replaceId ? valid_10 : _GEN_1545; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1547 = 8'hb == replaceId ? valid_11 : _GEN_1546; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1548 = 8'hc == replaceId ? valid_12 : _GEN_1547; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1549 = 8'hd == replaceId ? valid_13 : _GEN_1548; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1550 = 8'he == replaceId ? valid_14 : _GEN_1549; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1551 = 8'hf == replaceId ? valid_15 : _GEN_1550; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1552 = 8'h10 == replaceId ? valid_16 : _GEN_1551; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1553 = 8'h11 == replaceId ? valid_17 : _GEN_1552; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1554 = 8'h12 == replaceId ? valid_18 : _GEN_1553; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1555 = 8'h13 == replaceId ? valid_19 : _GEN_1554; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1556 = 8'h14 == replaceId ? valid_20 : _GEN_1555; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1557 = 8'h15 == replaceId ? valid_21 : _GEN_1556; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1558 = 8'h16 == replaceId ? valid_22 : _GEN_1557; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1559 = 8'h17 == replaceId ? valid_23 : _GEN_1558; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1560 = 8'h18 == replaceId ? valid_24 : _GEN_1559; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1561 = 8'h19 == replaceId ? valid_25 : _GEN_1560; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1562 = 8'h1a == replaceId ? valid_26 : _GEN_1561; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1563 = 8'h1b == replaceId ? valid_27 : _GEN_1562; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1564 = 8'h1c == replaceId ? valid_28 : _GEN_1563; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1565 = 8'h1d == replaceId ? valid_29 : _GEN_1564; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1566 = 8'h1e == replaceId ? valid_30 : _GEN_1565; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1567 = 8'h1f == replaceId ? valid_31 : _GEN_1566; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1568 = 8'h20 == replaceId ? valid_32 : _GEN_1567; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1569 = 8'h21 == replaceId ? valid_33 : _GEN_1568; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1570 = 8'h22 == replaceId ? valid_34 : _GEN_1569; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1571 = 8'h23 == replaceId ? valid_35 : _GEN_1570; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1572 = 8'h24 == replaceId ? valid_36 : _GEN_1571; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1573 = 8'h25 == replaceId ? valid_37 : _GEN_1572; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1574 = 8'h26 == replaceId ? valid_38 : _GEN_1573; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1575 = 8'h27 == replaceId ? valid_39 : _GEN_1574; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1576 = 8'h28 == replaceId ? valid_40 : _GEN_1575; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1577 = 8'h29 == replaceId ? valid_41 : _GEN_1576; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1578 = 8'h2a == replaceId ? valid_42 : _GEN_1577; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1579 = 8'h2b == replaceId ? valid_43 : _GEN_1578; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1580 = 8'h2c == replaceId ? valid_44 : _GEN_1579; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1581 = 8'h2d == replaceId ? valid_45 : _GEN_1580; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1582 = 8'h2e == replaceId ? valid_46 : _GEN_1581; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1583 = 8'h2f == replaceId ? valid_47 : _GEN_1582; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1584 = 8'h30 == replaceId ? valid_48 : _GEN_1583; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1585 = 8'h31 == replaceId ? valid_49 : _GEN_1584; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1586 = 8'h32 == replaceId ? valid_50 : _GEN_1585; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1587 = 8'h33 == replaceId ? valid_51 : _GEN_1586; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1588 = 8'h34 == replaceId ? valid_52 : _GEN_1587; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1589 = 8'h35 == replaceId ? valid_53 : _GEN_1588; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1590 = 8'h36 == replaceId ? valid_54 : _GEN_1589; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1591 = 8'h37 == replaceId ? valid_55 : _GEN_1590; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1592 = 8'h38 == replaceId ? valid_56 : _GEN_1591; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1593 = 8'h39 == replaceId ? valid_57 : _GEN_1592; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1594 = 8'h3a == replaceId ? valid_58 : _GEN_1593; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1595 = 8'h3b == replaceId ? valid_59 : _GEN_1594; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1596 = 8'h3c == replaceId ? valid_60 : _GEN_1595; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1597 = 8'h3d == replaceId ? valid_61 : _GEN_1596; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1598 = 8'h3e == replaceId ? valid_62 : _GEN_1597; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1599 = 8'h3f == replaceId ? valid_63 : _GEN_1598; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1600 = 8'h40 == replaceId ? valid_64 : _GEN_1599; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1601 = 8'h41 == replaceId ? valid_65 : _GEN_1600; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1602 = 8'h42 == replaceId ? valid_66 : _GEN_1601; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1603 = 8'h43 == replaceId ? valid_67 : _GEN_1602; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1604 = 8'h44 == replaceId ? valid_68 : _GEN_1603; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1605 = 8'h45 == replaceId ? valid_69 : _GEN_1604; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1606 = 8'h46 == replaceId ? valid_70 : _GEN_1605; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1607 = 8'h47 == replaceId ? valid_71 : _GEN_1606; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1608 = 8'h48 == replaceId ? valid_72 : _GEN_1607; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1609 = 8'h49 == replaceId ? valid_73 : _GEN_1608; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1610 = 8'h4a == replaceId ? valid_74 : _GEN_1609; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1611 = 8'h4b == replaceId ? valid_75 : _GEN_1610; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1612 = 8'h4c == replaceId ? valid_76 : _GEN_1611; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1613 = 8'h4d == replaceId ? valid_77 : _GEN_1612; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1614 = 8'h4e == replaceId ? valid_78 : _GEN_1613; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1615 = 8'h4f == replaceId ? valid_79 : _GEN_1614; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1616 = 8'h50 == replaceId ? valid_80 : _GEN_1615; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1617 = 8'h51 == replaceId ? valid_81 : _GEN_1616; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1618 = 8'h52 == replaceId ? valid_82 : _GEN_1617; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1619 = 8'h53 == replaceId ? valid_83 : _GEN_1618; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1620 = 8'h54 == replaceId ? valid_84 : _GEN_1619; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1621 = 8'h55 == replaceId ? valid_85 : _GEN_1620; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1622 = 8'h56 == replaceId ? valid_86 : _GEN_1621; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1623 = 8'h57 == replaceId ? valid_87 : _GEN_1622; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1624 = 8'h58 == replaceId ? valid_88 : _GEN_1623; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1625 = 8'h59 == replaceId ? valid_89 : _GEN_1624; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1626 = 8'h5a == replaceId ? valid_90 : _GEN_1625; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1627 = 8'h5b == replaceId ? valid_91 : _GEN_1626; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1628 = 8'h5c == replaceId ? valid_92 : _GEN_1627; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1629 = 8'h5d == replaceId ? valid_93 : _GEN_1628; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1630 = 8'h5e == replaceId ? valid_94 : _GEN_1629; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1631 = 8'h5f == replaceId ? valid_95 : _GEN_1630; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1632 = 8'h60 == replaceId ? valid_96 : _GEN_1631; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1633 = 8'h61 == replaceId ? valid_97 : _GEN_1632; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1634 = 8'h62 == replaceId ? valid_98 : _GEN_1633; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1635 = 8'h63 == replaceId ? valid_99 : _GEN_1634; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1636 = 8'h64 == replaceId ? valid_100 : _GEN_1635; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1637 = 8'h65 == replaceId ? valid_101 : _GEN_1636; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1638 = 8'h66 == replaceId ? valid_102 : _GEN_1637; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1639 = 8'h67 == replaceId ? valid_103 : _GEN_1638; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1640 = 8'h68 == replaceId ? valid_104 : _GEN_1639; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1641 = 8'h69 == replaceId ? valid_105 : _GEN_1640; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1642 = 8'h6a == replaceId ? valid_106 : _GEN_1641; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1643 = 8'h6b == replaceId ? valid_107 : _GEN_1642; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1644 = 8'h6c == replaceId ? valid_108 : _GEN_1643; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1645 = 8'h6d == replaceId ? valid_109 : _GEN_1644; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1646 = 8'h6e == replaceId ? valid_110 : _GEN_1645; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1647 = 8'h6f == replaceId ? valid_111 : _GEN_1646; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1648 = 8'h70 == replaceId ? valid_112 : _GEN_1647; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1649 = 8'h71 == replaceId ? valid_113 : _GEN_1648; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1650 = 8'h72 == replaceId ? valid_114 : _GEN_1649; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1651 = 8'h73 == replaceId ? valid_115 : _GEN_1650; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1652 = 8'h74 == replaceId ? valid_116 : _GEN_1651; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1653 = 8'h75 == replaceId ? valid_117 : _GEN_1652; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1654 = 8'h76 == replaceId ? valid_118 : _GEN_1653; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1655 = 8'h77 == replaceId ? valid_119 : _GEN_1654; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1656 = 8'h78 == replaceId ? valid_120 : _GEN_1655; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1657 = 8'h79 == replaceId ? valid_121 : _GEN_1656; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1658 = 8'h7a == replaceId ? valid_122 : _GEN_1657; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1659 = 8'h7b == replaceId ? valid_123 : _GEN_1658; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1660 = 8'h7c == replaceId ? valid_124 : _GEN_1659; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1661 = 8'h7d == replaceId ? valid_125 : _GEN_1660; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1662 = 8'h7e == replaceId ? valid_126 : _GEN_1661; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1663 = 8'h7f == replaceId ? valid_127 : _GEN_1662; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1664 = 8'h80 == replaceId ? valid_128 : _GEN_1663; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1665 = 8'h81 == replaceId ? valid_129 : _GEN_1664; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1666 = 8'h82 == replaceId ? valid_130 : _GEN_1665; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1667 = 8'h83 == replaceId ? valid_131 : _GEN_1666; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1668 = 8'h84 == replaceId ? valid_132 : _GEN_1667; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1669 = 8'h85 == replaceId ? valid_133 : _GEN_1668; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1670 = 8'h86 == replaceId ? valid_134 : _GEN_1669; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1671 = 8'h87 == replaceId ? valid_135 : _GEN_1670; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1672 = 8'h88 == replaceId ? valid_136 : _GEN_1671; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1673 = 8'h89 == replaceId ? valid_137 : _GEN_1672; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1674 = 8'h8a == replaceId ? valid_138 : _GEN_1673; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1675 = 8'h8b == replaceId ? valid_139 : _GEN_1674; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1676 = 8'h8c == replaceId ? valid_140 : _GEN_1675; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1677 = 8'h8d == replaceId ? valid_141 : _GEN_1676; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1678 = 8'h8e == replaceId ? valid_142 : _GEN_1677; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1679 = 8'h8f == replaceId ? valid_143 : _GEN_1678; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1680 = 8'h90 == replaceId ? valid_144 : _GEN_1679; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1681 = 8'h91 == replaceId ? valid_145 : _GEN_1680; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1682 = 8'h92 == replaceId ? valid_146 : _GEN_1681; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1683 = 8'h93 == replaceId ? valid_147 : _GEN_1682; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1684 = 8'h94 == replaceId ? valid_148 : _GEN_1683; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1685 = 8'h95 == replaceId ? valid_149 : _GEN_1684; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1686 = 8'h96 == replaceId ? valid_150 : _GEN_1685; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1687 = 8'h97 == replaceId ? valid_151 : _GEN_1686; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1688 = 8'h98 == replaceId ? valid_152 : _GEN_1687; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1689 = 8'h99 == replaceId ? valid_153 : _GEN_1688; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1690 = 8'h9a == replaceId ? valid_154 : _GEN_1689; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1691 = 8'h9b == replaceId ? valid_155 : _GEN_1690; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1692 = 8'h9c == replaceId ? valid_156 : _GEN_1691; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1693 = 8'h9d == replaceId ? valid_157 : _GEN_1692; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1694 = 8'h9e == replaceId ? valid_158 : _GEN_1693; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1695 = 8'h9f == replaceId ? valid_159 : _GEN_1694; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1696 = 8'ha0 == replaceId ? valid_160 : _GEN_1695; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1697 = 8'ha1 == replaceId ? valid_161 : _GEN_1696; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1698 = 8'ha2 == replaceId ? valid_162 : _GEN_1697; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1699 = 8'ha3 == replaceId ? valid_163 : _GEN_1698; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1700 = 8'ha4 == replaceId ? valid_164 : _GEN_1699; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1701 = 8'ha5 == replaceId ? valid_165 : _GEN_1700; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1702 = 8'ha6 == replaceId ? valid_166 : _GEN_1701; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1703 = 8'ha7 == replaceId ? valid_167 : _GEN_1702; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1704 = 8'ha8 == replaceId ? valid_168 : _GEN_1703; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1705 = 8'ha9 == replaceId ? valid_169 : _GEN_1704; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1706 = 8'haa == replaceId ? valid_170 : _GEN_1705; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1707 = 8'hab == replaceId ? valid_171 : _GEN_1706; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1708 = 8'hac == replaceId ? valid_172 : _GEN_1707; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1709 = 8'had == replaceId ? valid_173 : _GEN_1708; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1710 = 8'hae == replaceId ? valid_174 : _GEN_1709; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1711 = 8'haf == replaceId ? valid_175 : _GEN_1710; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1712 = 8'hb0 == replaceId ? valid_176 : _GEN_1711; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1713 = 8'hb1 == replaceId ? valid_177 : _GEN_1712; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1714 = 8'hb2 == replaceId ? valid_178 : _GEN_1713; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1715 = 8'hb3 == replaceId ? valid_179 : _GEN_1714; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1716 = 8'hb4 == replaceId ? valid_180 : _GEN_1715; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1717 = 8'hb5 == replaceId ? valid_181 : _GEN_1716; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1718 = 8'hb6 == replaceId ? valid_182 : _GEN_1717; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1719 = 8'hb7 == replaceId ? valid_183 : _GEN_1718; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1720 = 8'hb8 == replaceId ? valid_184 : _GEN_1719; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1721 = 8'hb9 == replaceId ? valid_185 : _GEN_1720; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1722 = 8'hba == replaceId ? valid_186 : _GEN_1721; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1723 = 8'hbb == replaceId ? valid_187 : _GEN_1722; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1724 = 8'hbc == replaceId ? valid_188 : _GEN_1723; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1725 = 8'hbd == replaceId ? valid_189 : _GEN_1724; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1726 = 8'hbe == replaceId ? valid_190 : _GEN_1725; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1727 = 8'hbf == replaceId ? valid_191 : _GEN_1726; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1728 = 8'hc0 == replaceId ? valid_192 : _GEN_1727; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1729 = 8'hc1 == replaceId ? valid_193 : _GEN_1728; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1730 = 8'hc2 == replaceId ? valid_194 : _GEN_1729; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1731 = 8'hc3 == replaceId ? valid_195 : _GEN_1730; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1732 = 8'hc4 == replaceId ? valid_196 : _GEN_1731; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1733 = 8'hc5 == replaceId ? valid_197 : _GEN_1732; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1734 = 8'hc6 == replaceId ? valid_198 : _GEN_1733; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1735 = 8'hc7 == replaceId ? valid_199 : _GEN_1734; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1736 = 8'hc8 == replaceId ? valid_200 : _GEN_1735; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1737 = 8'hc9 == replaceId ? valid_201 : _GEN_1736; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1738 = 8'hca == replaceId ? valid_202 : _GEN_1737; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1739 = 8'hcb == replaceId ? valid_203 : _GEN_1738; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1740 = 8'hcc == replaceId ? valid_204 : _GEN_1739; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1741 = 8'hcd == replaceId ? valid_205 : _GEN_1740; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1742 = 8'hce == replaceId ? valid_206 : _GEN_1741; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1743 = 8'hcf == replaceId ? valid_207 : _GEN_1742; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1744 = 8'hd0 == replaceId ? valid_208 : _GEN_1743; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1745 = 8'hd1 == replaceId ? valid_209 : _GEN_1744; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1746 = 8'hd2 == replaceId ? valid_210 : _GEN_1745; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1747 = 8'hd3 == replaceId ? valid_211 : _GEN_1746; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1748 = 8'hd4 == replaceId ? valid_212 : _GEN_1747; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1749 = 8'hd5 == replaceId ? valid_213 : _GEN_1748; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1750 = 8'hd6 == replaceId ? valid_214 : _GEN_1749; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1751 = 8'hd7 == replaceId ? valid_215 : _GEN_1750; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1752 = 8'hd8 == replaceId ? valid_216 : _GEN_1751; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1753 = 8'hd9 == replaceId ? valid_217 : _GEN_1752; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1754 = 8'hda == replaceId ? valid_218 : _GEN_1753; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1755 = 8'hdb == replaceId ? valid_219 : _GEN_1754; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1756 = 8'hdc == replaceId ? valid_220 : _GEN_1755; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1757 = 8'hdd == replaceId ? valid_221 : _GEN_1756; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1758 = 8'hde == replaceId ? valid_222 : _GEN_1757; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1759 = 8'hdf == replaceId ? valid_223 : _GEN_1758; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1760 = 8'he0 == replaceId ? valid_224 : _GEN_1759; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1761 = 8'he1 == replaceId ? valid_225 : _GEN_1760; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1762 = 8'he2 == replaceId ? valid_226 : _GEN_1761; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1763 = 8'he3 == replaceId ? valid_227 : _GEN_1762; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1764 = 8'he4 == replaceId ? valid_228 : _GEN_1763; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1765 = 8'he5 == replaceId ? valid_229 : _GEN_1764; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1766 = 8'he6 == replaceId ? valid_230 : _GEN_1765; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1767 = 8'he7 == replaceId ? valid_231 : _GEN_1766; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1768 = 8'he8 == replaceId ? valid_232 : _GEN_1767; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1769 = 8'he9 == replaceId ? valid_233 : _GEN_1768; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1770 = 8'hea == replaceId ? valid_234 : _GEN_1769; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1771 = 8'heb == replaceId ? valid_235 : _GEN_1770; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1772 = 8'hec == replaceId ? valid_236 : _GEN_1771; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1773 = 8'hed == replaceId ? valid_237 : _GEN_1772; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1774 = 8'hee == replaceId ? valid_238 : _GEN_1773; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1775 = 8'hef == replaceId ? valid_239 : _GEN_1774; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1776 = 8'hf0 == replaceId ? valid_240 : _GEN_1775; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1777 = 8'hf1 == replaceId ? valid_241 : _GEN_1776; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1778 = 8'hf2 == replaceId ? valid_242 : _GEN_1777; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1779 = 8'hf3 == replaceId ? valid_243 : _GEN_1778; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1780 = 8'hf4 == replaceId ? valid_244 : _GEN_1779; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1781 = 8'hf5 == replaceId ? valid_245 : _GEN_1780; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1782 = 8'hf6 == replaceId ? valid_246 : _GEN_1781; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1783 = 8'hf7 == replaceId ? valid_247 : _GEN_1782; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1784 = 8'hf8 == replaceId ? valid_248 : _GEN_1783; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1785 = 8'hf9 == replaceId ? valid_249 : _GEN_1784; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1786 = 8'hfa == replaceId ? valid_250 : _GEN_1785; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1787 = 8'hfb == replaceId ? valid_251 : _GEN_1786; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1788 = 8'hfc == replaceId ? valid_252 : _GEN_1787; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1789 = 8'hfd == replaceId ? valid_253 : _GEN_1788; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1790 = 8'hfe == replaceId ? valid_254 : _GEN_1789; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1791 = 8'hff == replaceId ? valid_255 : _GEN_1790; // @[L1DCache.scala 493:{34,34}]
- wire _GEN_1792 = 8'h0 == replaceId ? 1'h0 : valid_0; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1793 = 8'h1 == replaceId ? 1'h0 : valid_1; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1794 = 8'h2 == replaceId ? 1'h0 : valid_2; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1795 = 8'h3 == replaceId ? 1'h0 : valid_3; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1796 = 8'h4 == replaceId ? 1'h0 : valid_4; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1797 = 8'h5 == replaceId ? 1'h0 : valid_5; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1798 = 8'h6 == replaceId ? 1'h0 : valid_6; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1799 = 8'h7 == replaceId ? 1'h0 : valid_7; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1800 = 8'h8 == replaceId ? 1'h0 : valid_8; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1801 = 8'h9 == replaceId ? 1'h0 : valid_9; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1802 = 8'ha == replaceId ? 1'h0 : valid_10; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1803 = 8'hb == replaceId ? 1'h0 : valid_11; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1804 = 8'hc == replaceId ? 1'h0 : valid_12; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1805 = 8'hd == replaceId ? 1'h0 : valid_13; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1806 = 8'he == replaceId ? 1'h0 : valid_14; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1807 = 8'hf == replaceId ? 1'h0 : valid_15; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1808 = 8'h10 == replaceId ? 1'h0 : valid_16; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1809 = 8'h11 == replaceId ? 1'h0 : valid_17; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1810 = 8'h12 == replaceId ? 1'h0 : valid_18; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1811 = 8'h13 == replaceId ? 1'h0 : valid_19; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1812 = 8'h14 == replaceId ? 1'h0 : valid_20; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1813 = 8'h15 == replaceId ? 1'h0 : valid_21; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1814 = 8'h16 == replaceId ? 1'h0 : valid_22; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1815 = 8'h17 == replaceId ? 1'h0 : valid_23; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1816 = 8'h18 == replaceId ? 1'h0 : valid_24; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1817 = 8'h19 == replaceId ? 1'h0 : valid_25; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1818 = 8'h1a == replaceId ? 1'h0 : valid_26; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1819 = 8'h1b == replaceId ? 1'h0 : valid_27; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1820 = 8'h1c == replaceId ? 1'h0 : valid_28; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1821 = 8'h1d == replaceId ? 1'h0 : valid_29; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1822 = 8'h1e == replaceId ? 1'h0 : valid_30; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1823 = 8'h1f == replaceId ? 1'h0 : valid_31; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1824 = 8'h20 == replaceId ? 1'h0 : valid_32; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1825 = 8'h21 == replaceId ? 1'h0 : valid_33; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1826 = 8'h22 == replaceId ? 1'h0 : valid_34; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1827 = 8'h23 == replaceId ? 1'h0 : valid_35; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1828 = 8'h24 == replaceId ? 1'h0 : valid_36; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1829 = 8'h25 == replaceId ? 1'h0 : valid_37; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1830 = 8'h26 == replaceId ? 1'h0 : valid_38; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1831 = 8'h27 == replaceId ? 1'h0 : valid_39; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1832 = 8'h28 == replaceId ? 1'h0 : valid_40; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1833 = 8'h29 == replaceId ? 1'h0 : valid_41; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1834 = 8'h2a == replaceId ? 1'h0 : valid_42; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1835 = 8'h2b == replaceId ? 1'h0 : valid_43; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1836 = 8'h2c == replaceId ? 1'h0 : valid_44; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1837 = 8'h2d == replaceId ? 1'h0 : valid_45; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1838 = 8'h2e == replaceId ? 1'h0 : valid_46; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1839 = 8'h2f == replaceId ? 1'h0 : valid_47; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1840 = 8'h30 == replaceId ? 1'h0 : valid_48; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1841 = 8'h31 == replaceId ? 1'h0 : valid_49; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1842 = 8'h32 == replaceId ? 1'h0 : valid_50; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1843 = 8'h33 == replaceId ? 1'h0 : valid_51; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1844 = 8'h34 == replaceId ? 1'h0 : valid_52; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1845 = 8'h35 == replaceId ? 1'h0 : valid_53; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1846 = 8'h36 == replaceId ? 1'h0 : valid_54; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1847 = 8'h37 == replaceId ? 1'h0 : valid_55; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1848 = 8'h38 == replaceId ? 1'h0 : valid_56; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1849 = 8'h39 == replaceId ? 1'h0 : valid_57; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1850 = 8'h3a == replaceId ? 1'h0 : valid_58; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1851 = 8'h3b == replaceId ? 1'h0 : valid_59; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1852 = 8'h3c == replaceId ? 1'h0 : valid_60; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1853 = 8'h3d == replaceId ? 1'h0 : valid_61; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1854 = 8'h3e == replaceId ? 1'h0 : valid_62; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1855 = 8'h3f == replaceId ? 1'h0 : valid_63; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1856 = 8'h40 == replaceId ? 1'h0 : valid_64; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1857 = 8'h41 == replaceId ? 1'h0 : valid_65; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1858 = 8'h42 == replaceId ? 1'h0 : valid_66; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1859 = 8'h43 == replaceId ? 1'h0 : valid_67; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1860 = 8'h44 == replaceId ? 1'h0 : valid_68; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1861 = 8'h45 == replaceId ? 1'h0 : valid_69; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1862 = 8'h46 == replaceId ? 1'h0 : valid_70; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1863 = 8'h47 == replaceId ? 1'h0 : valid_71; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1864 = 8'h48 == replaceId ? 1'h0 : valid_72; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1865 = 8'h49 == replaceId ? 1'h0 : valid_73; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1866 = 8'h4a == replaceId ? 1'h0 : valid_74; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1867 = 8'h4b == replaceId ? 1'h0 : valid_75; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1868 = 8'h4c == replaceId ? 1'h0 : valid_76; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1869 = 8'h4d == replaceId ? 1'h0 : valid_77; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1870 = 8'h4e == replaceId ? 1'h0 : valid_78; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1871 = 8'h4f == replaceId ? 1'h0 : valid_79; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1872 = 8'h50 == replaceId ? 1'h0 : valid_80; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1873 = 8'h51 == replaceId ? 1'h0 : valid_81; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1874 = 8'h52 == replaceId ? 1'h0 : valid_82; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1875 = 8'h53 == replaceId ? 1'h0 : valid_83; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1876 = 8'h54 == replaceId ? 1'h0 : valid_84; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1877 = 8'h55 == replaceId ? 1'h0 : valid_85; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1878 = 8'h56 == replaceId ? 1'h0 : valid_86; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1879 = 8'h57 == replaceId ? 1'h0 : valid_87; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1880 = 8'h58 == replaceId ? 1'h0 : valid_88; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1881 = 8'h59 == replaceId ? 1'h0 : valid_89; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1882 = 8'h5a == replaceId ? 1'h0 : valid_90; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1883 = 8'h5b == replaceId ? 1'h0 : valid_91; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1884 = 8'h5c == replaceId ? 1'h0 : valid_92; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1885 = 8'h5d == replaceId ? 1'h0 : valid_93; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1886 = 8'h5e == replaceId ? 1'h0 : valid_94; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1887 = 8'h5f == replaceId ? 1'h0 : valid_95; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1888 = 8'h60 == replaceId ? 1'h0 : valid_96; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1889 = 8'h61 == replaceId ? 1'h0 : valid_97; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1890 = 8'h62 == replaceId ? 1'h0 : valid_98; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1891 = 8'h63 == replaceId ? 1'h0 : valid_99; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1892 = 8'h64 == replaceId ? 1'h0 : valid_100; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1893 = 8'h65 == replaceId ? 1'h0 : valid_101; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1894 = 8'h66 == replaceId ? 1'h0 : valid_102; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1895 = 8'h67 == replaceId ? 1'h0 : valid_103; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1896 = 8'h68 == replaceId ? 1'h0 : valid_104; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1897 = 8'h69 == replaceId ? 1'h0 : valid_105; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1898 = 8'h6a == replaceId ? 1'h0 : valid_106; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1899 = 8'h6b == replaceId ? 1'h0 : valid_107; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1900 = 8'h6c == replaceId ? 1'h0 : valid_108; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1901 = 8'h6d == replaceId ? 1'h0 : valid_109; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1902 = 8'h6e == replaceId ? 1'h0 : valid_110; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1903 = 8'h6f == replaceId ? 1'h0 : valid_111; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1904 = 8'h70 == replaceId ? 1'h0 : valid_112; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1905 = 8'h71 == replaceId ? 1'h0 : valid_113; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1906 = 8'h72 == replaceId ? 1'h0 : valid_114; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1907 = 8'h73 == replaceId ? 1'h0 : valid_115; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1908 = 8'h74 == replaceId ? 1'h0 : valid_116; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1909 = 8'h75 == replaceId ? 1'h0 : valid_117; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1910 = 8'h76 == replaceId ? 1'h0 : valid_118; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1911 = 8'h77 == replaceId ? 1'h0 : valid_119; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1912 = 8'h78 == replaceId ? 1'h0 : valid_120; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1913 = 8'h79 == replaceId ? 1'h0 : valid_121; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1914 = 8'h7a == replaceId ? 1'h0 : valid_122; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1915 = 8'h7b == replaceId ? 1'h0 : valid_123; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1916 = 8'h7c == replaceId ? 1'h0 : valid_124; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1917 = 8'h7d == replaceId ? 1'h0 : valid_125; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1918 = 8'h7e == replaceId ? 1'h0 : valid_126; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1919 = 8'h7f == replaceId ? 1'h0 : valid_127; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1920 = 8'h80 == replaceId ? 1'h0 : valid_128; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1921 = 8'h81 == replaceId ? 1'h0 : valid_129; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1922 = 8'h82 == replaceId ? 1'h0 : valid_130; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1923 = 8'h83 == replaceId ? 1'h0 : valid_131; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1924 = 8'h84 == replaceId ? 1'h0 : valid_132; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1925 = 8'h85 == replaceId ? 1'h0 : valid_133; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1926 = 8'h86 == replaceId ? 1'h0 : valid_134; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1927 = 8'h87 == replaceId ? 1'h0 : valid_135; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1928 = 8'h88 == replaceId ? 1'h0 : valid_136; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1929 = 8'h89 == replaceId ? 1'h0 : valid_137; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1930 = 8'h8a == replaceId ? 1'h0 : valid_138; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1931 = 8'h8b == replaceId ? 1'h0 : valid_139; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1932 = 8'h8c == replaceId ? 1'h0 : valid_140; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1933 = 8'h8d == replaceId ? 1'h0 : valid_141; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1934 = 8'h8e == replaceId ? 1'h0 : valid_142; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1935 = 8'h8f == replaceId ? 1'h0 : valid_143; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1936 = 8'h90 == replaceId ? 1'h0 : valid_144; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1937 = 8'h91 == replaceId ? 1'h0 : valid_145; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1938 = 8'h92 == replaceId ? 1'h0 : valid_146; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1939 = 8'h93 == replaceId ? 1'h0 : valid_147; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1940 = 8'h94 == replaceId ? 1'h0 : valid_148; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1941 = 8'h95 == replaceId ? 1'h0 : valid_149; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1942 = 8'h96 == replaceId ? 1'h0 : valid_150; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1943 = 8'h97 == replaceId ? 1'h0 : valid_151; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1944 = 8'h98 == replaceId ? 1'h0 : valid_152; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1945 = 8'h99 == replaceId ? 1'h0 : valid_153; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1946 = 8'h9a == replaceId ? 1'h0 : valid_154; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1947 = 8'h9b == replaceId ? 1'h0 : valid_155; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1948 = 8'h9c == replaceId ? 1'h0 : valid_156; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1949 = 8'h9d == replaceId ? 1'h0 : valid_157; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1950 = 8'h9e == replaceId ? 1'h0 : valid_158; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1951 = 8'h9f == replaceId ? 1'h0 : valid_159; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1952 = 8'ha0 == replaceId ? 1'h0 : valid_160; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1953 = 8'ha1 == replaceId ? 1'h0 : valid_161; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1954 = 8'ha2 == replaceId ? 1'h0 : valid_162; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1955 = 8'ha3 == replaceId ? 1'h0 : valid_163; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1956 = 8'ha4 == replaceId ? 1'h0 : valid_164; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1957 = 8'ha5 == replaceId ? 1'h0 : valid_165; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1958 = 8'ha6 == replaceId ? 1'h0 : valid_166; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1959 = 8'ha7 == replaceId ? 1'h0 : valid_167; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1960 = 8'ha8 == replaceId ? 1'h0 : valid_168; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1961 = 8'ha9 == replaceId ? 1'h0 : valid_169; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1962 = 8'haa == replaceId ? 1'h0 : valid_170; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1963 = 8'hab == replaceId ? 1'h0 : valid_171; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1964 = 8'hac == replaceId ? 1'h0 : valid_172; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1965 = 8'had == replaceId ? 1'h0 : valid_173; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1966 = 8'hae == replaceId ? 1'h0 : valid_174; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1967 = 8'haf == replaceId ? 1'h0 : valid_175; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1968 = 8'hb0 == replaceId ? 1'h0 : valid_176; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1969 = 8'hb1 == replaceId ? 1'h0 : valid_177; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1970 = 8'hb2 == replaceId ? 1'h0 : valid_178; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1971 = 8'hb3 == replaceId ? 1'h0 : valid_179; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1972 = 8'hb4 == replaceId ? 1'h0 : valid_180; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1973 = 8'hb5 == replaceId ? 1'h0 : valid_181; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1974 = 8'hb6 == replaceId ? 1'h0 : valid_182; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1975 = 8'hb7 == replaceId ? 1'h0 : valid_183; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1976 = 8'hb8 == replaceId ? 1'h0 : valid_184; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1977 = 8'hb9 == replaceId ? 1'h0 : valid_185; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1978 = 8'hba == replaceId ? 1'h0 : valid_186; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1979 = 8'hbb == replaceId ? 1'h0 : valid_187; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1980 = 8'hbc == replaceId ? 1'h0 : valid_188; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1981 = 8'hbd == replaceId ? 1'h0 : valid_189; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1982 = 8'hbe == replaceId ? 1'h0 : valid_190; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1983 = 8'hbf == replaceId ? 1'h0 : valid_191; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1984 = 8'hc0 == replaceId ? 1'h0 : valid_192; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1985 = 8'hc1 == replaceId ? 1'h0 : valid_193; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1986 = 8'hc2 == replaceId ? 1'h0 : valid_194; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1987 = 8'hc3 == replaceId ? 1'h0 : valid_195; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1988 = 8'hc4 == replaceId ? 1'h0 : valid_196; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1989 = 8'hc5 == replaceId ? 1'h0 : valid_197; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1990 = 8'hc6 == replaceId ? 1'h0 : valid_198; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1991 = 8'hc7 == replaceId ? 1'h0 : valid_199; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1992 = 8'hc8 == replaceId ? 1'h0 : valid_200; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1993 = 8'hc9 == replaceId ? 1'h0 : valid_201; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1994 = 8'hca == replaceId ? 1'h0 : valid_202; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1995 = 8'hcb == replaceId ? 1'h0 : valid_203; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1996 = 8'hcc == replaceId ? 1'h0 : valid_204; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1997 = 8'hcd == replaceId ? 1'h0 : valid_205; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1998 = 8'hce == replaceId ? 1'h0 : valid_206; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_1999 = 8'hcf == replaceId ? 1'h0 : valid_207; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2000 = 8'hd0 == replaceId ? 1'h0 : valid_208; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2001 = 8'hd1 == replaceId ? 1'h0 : valid_209; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2002 = 8'hd2 == replaceId ? 1'h0 : valid_210; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2003 = 8'hd3 == replaceId ? 1'h0 : valid_211; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2004 = 8'hd4 == replaceId ? 1'h0 : valid_212; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2005 = 8'hd5 == replaceId ? 1'h0 : valid_213; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2006 = 8'hd6 == replaceId ? 1'h0 : valid_214; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2007 = 8'hd7 == replaceId ? 1'h0 : valid_215; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2008 = 8'hd8 == replaceId ? 1'h0 : valid_216; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2009 = 8'hd9 == replaceId ? 1'h0 : valid_217; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2010 = 8'hda == replaceId ? 1'h0 : valid_218; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2011 = 8'hdb == replaceId ? 1'h0 : valid_219; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2012 = 8'hdc == replaceId ? 1'h0 : valid_220; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2013 = 8'hdd == replaceId ? 1'h0 : valid_221; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2014 = 8'hde == replaceId ? 1'h0 : valid_222; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2015 = 8'hdf == replaceId ? 1'h0 : valid_223; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2016 = 8'he0 == replaceId ? 1'h0 : valid_224; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2017 = 8'he1 == replaceId ? 1'h0 : valid_225; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2018 = 8'he2 == replaceId ? 1'h0 : valid_226; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2019 = 8'he3 == replaceId ? 1'h0 : valid_227; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2020 = 8'he4 == replaceId ? 1'h0 : valid_228; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2021 = 8'he5 == replaceId ? 1'h0 : valid_229; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2022 = 8'he6 == replaceId ? 1'h0 : valid_230; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2023 = 8'he7 == replaceId ? 1'h0 : valid_231; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2024 = 8'he8 == replaceId ? 1'h0 : valid_232; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2025 = 8'he9 == replaceId ? 1'h0 : valid_233; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2026 = 8'hea == replaceId ? 1'h0 : valid_234; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2027 = 8'heb == replaceId ? 1'h0 : valid_235; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2028 = 8'hec == replaceId ? 1'h0 : valid_236; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2029 = 8'hed == replaceId ? 1'h0 : valid_237; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2030 = 8'hee == replaceId ? 1'h0 : valid_238; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2031 = 8'hef == replaceId ? 1'h0 : valid_239; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2032 = 8'hf0 == replaceId ? 1'h0 : valid_240; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2033 = 8'hf1 == replaceId ? 1'h0 : valid_241; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2034 = 8'hf2 == replaceId ? 1'h0 : valid_242; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2035 = 8'hf3 == replaceId ? 1'h0 : valid_243; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2036 = 8'hf4 == replaceId ? 1'h0 : valid_244; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2037 = 8'hf5 == replaceId ? 1'h0 : valid_245; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2038 = 8'hf6 == replaceId ? 1'h0 : valid_246; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2039 = 8'hf7 == replaceId ? 1'h0 : valid_247; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2040 = 8'hf8 == replaceId ? 1'h0 : valid_248; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2041 = 8'hf9 == replaceId ? 1'h0 : valid_249; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2042 = 8'hfa == replaceId ? 1'h0 : valid_250; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2043 = 8'hfb == replaceId ? 1'h0 : valid_251; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2044 = 8'hfc == replaceId ? 1'h0 : valid_252; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2045 = 8'hfd == replaceId ? 1'h0 : valid_253; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2046 = 8'hfe == replaceId ? 1'h0 : valid_254; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2047 = 8'hff == replaceId ? 1'h0 : valid_255; // @[L1DCache.scala 342:22 496:{22,22}]
- wire _GEN_2048 = 8'h0 == replaceId ? 1'h0 : dirty_0; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2049 = 8'h1 == replaceId ? 1'h0 : dirty_1; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2050 = 8'h2 == replaceId ? 1'h0 : dirty_2; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2051 = 8'h3 == replaceId ? 1'h0 : dirty_3; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2052 = 8'h4 == replaceId ? 1'h0 : dirty_4; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2053 = 8'h5 == replaceId ? 1'h0 : dirty_5; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2054 = 8'h6 == replaceId ? 1'h0 : dirty_6; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2055 = 8'h7 == replaceId ? 1'h0 : dirty_7; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2056 = 8'h8 == replaceId ? 1'h0 : dirty_8; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2057 = 8'h9 == replaceId ? 1'h0 : dirty_9; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2058 = 8'ha == replaceId ? 1'h0 : dirty_10; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2059 = 8'hb == replaceId ? 1'h0 : dirty_11; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2060 = 8'hc == replaceId ? 1'h0 : dirty_12; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2061 = 8'hd == replaceId ? 1'h0 : dirty_13; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2062 = 8'he == replaceId ? 1'h0 : dirty_14; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2063 = 8'hf == replaceId ? 1'h0 : dirty_15; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2064 = 8'h10 == replaceId ? 1'h0 : dirty_16; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2065 = 8'h11 == replaceId ? 1'h0 : dirty_17; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2066 = 8'h12 == replaceId ? 1'h0 : dirty_18; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2067 = 8'h13 == replaceId ? 1'h0 : dirty_19; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2068 = 8'h14 == replaceId ? 1'h0 : dirty_20; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2069 = 8'h15 == replaceId ? 1'h0 : dirty_21; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2070 = 8'h16 == replaceId ? 1'h0 : dirty_22; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2071 = 8'h17 == replaceId ? 1'h0 : dirty_23; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2072 = 8'h18 == replaceId ? 1'h0 : dirty_24; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2073 = 8'h19 == replaceId ? 1'h0 : dirty_25; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2074 = 8'h1a == replaceId ? 1'h0 : dirty_26; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2075 = 8'h1b == replaceId ? 1'h0 : dirty_27; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2076 = 8'h1c == replaceId ? 1'h0 : dirty_28; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2077 = 8'h1d == replaceId ? 1'h0 : dirty_29; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2078 = 8'h1e == replaceId ? 1'h0 : dirty_30; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2079 = 8'h1f == replaceId ? 1'h0 : dirty_31; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2080 = 8'h20 == replaceId ? 1'h0 : dirty_32; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2081 = 8'h21 == replaceId ? 1'h0 : dirty_33; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2082 = 8'h22 == replaceId ? 1'h0 : dirty_34; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2083 = 8'h23 == replaceId ? 1'h0 : dirty_35; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2084 = 8'h24 == replaceId ? 1'h0 : dirty_36; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2085 = 8'h25 == replaceId ? 1'h0 : dirty_37; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2086 = 8'h26 == replaceId ? 1'h0 : dirty_38; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2087 = 8'h27 == replaceId ? 1'h0 : dirty_39; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2088 = 8'h28 == replaceId ? 1'h0 : dirty_40; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2089 = 8'h29 == replaceId ? 1'h0 : dirty_41; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2090 = 8'h2a == replaceId ? 1'h0 : dirty_42; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2091 = 8'h2b == replaceId ? 1'h0 : dirty_43; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2092 = 8'h2c == replaceId ? 1'h0 : dirty_44; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2093 = 8'h2d == replaceId ? 1'h0 : dirty_45; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2094 = 8'h2e == replaceId ? 1'h0 : dirty_46; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2095 = 8'h2f == replaceId ? 1'h0 : dirty_47; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2096 = 8'h30 == replaceId ? 1'h0 : dirty_48; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2097 = 8'h31 == replaceId ? 1'h0 : dirty_49; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2098 = 8'h32 == replaceId ? 1'h0 : dirty_50; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2099 = 8'h33 == replaceId ? 1'h0 : dirty_51; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2100 = 8'h34 == replaceId ? 1'h0 : dirty_52; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2101 = 8'h35 == replaceId ? 1'h0 : dirty_53; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2102 = 8'h36 == replaceId ? 1'h0 : dirty_54; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2103 = 8'h37 == replaceId ? 1'h0 : dirty_55; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2104 = 8'h38 == replaceId ? 1'h0 : dirty_56; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2105 = 8'h39 == replaceId ? 1'h0 : dirty_57; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2106 = 8'h3a == replaceId ? 1'h0 : dirty_58; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2107 = 8'h3b == replaceId ? 1'h0 : dirty_59; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2108 = 8'h3c == replaceId ? 1'h0 : dirty_60; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2109 = 8'h3d == replaceId ? 1'h0 : dirty_61; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2110 = 8'h3e == replaceId ? 1'h0 : dirty_62; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2111 = 8'h3f == replaceId ? 1'h0 : dirty_63; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2112 = 8'h40 == replaceId ? 1'h0 : dirty_64; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2113 = 8'h41 == replaceId ? 1'h0 : dirty_65; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2114 = 8'h42 == replaceId ? 1'h0 : dirty_66; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2115 = 8'h43 == replaceId ? 1'h0 : dirty_67; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2116 = 8'h44 == replaceId ? 1'h0 : dirty_68; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2117 = 8'h45 == replaceId ? 1'h0 : dirty_69; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2118 = 8'h46 == replaceId ? 1'h0 : dirty_70; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2119 = 8'h47 == replaceId ? 1'h0 : dirty_71; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2120 = 8'h48 == replaceId ? 1'h0 : dirty_72; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2121 = 8'h49 == replaceId ? 1'h0 : dirty_73; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2122 = 8'h4a == replaceId ? 1'h0 : dirty_74; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2123 = 8'h4b == replaceId ? 1'h0 : dirty_75; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2124 = 8'h4c == replaceId ? 1'h0 : dirty_76; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2125 = 8'h4d == replaceId ? 1'h0 : dirty_77; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2126 = 8'h4e == replaceId ? 1'h0 : dirty_78; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2127 = 8'h4f == replaceId ? 1'h0 : dirty_79; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2128 = 8'h50 == replaceId ? 1'h0 : dirty_80; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2129 = 8'h51 == replaceId ? 1'h0 : dirty_81; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2130 = 8'h52 == replaceId ? 1'h0 : dirty_82; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2131 = 8'h53 == replaceId ? 1'h0 : dirty_83; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2132 = 8'h54 == replaceId ? 1'h0 : dirty_84; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2133 = 8'h55 == replaceId ? 1'h0 : dirty_85; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2134 = 8'h56 == replaceId ? 1'h0 : dirty_86; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2135 = 8'h57 == replaceId ? 1'h0 : dirty_87; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2136 = 8'h58 == replaceId ? 1'h0 : dirty_88; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2137 = 8'h59 == replaceId ? 1'h0 : dirty_89; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2138 = 8'h5a == replaceId ? 1'h0 : dirty_90; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2139 = 8'h5b == replaceId ? 1'h0 : dirty_91; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2140 = 8'h5c == replaceId ? 1'h0 : dirty_92; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2141 = 8'h5d == replaceId ? 1'h0 : dirty_93; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2142 = 8'h5e == replaceId ? 1'h0 : dirty_94; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2143 = 8'h5f == replaceId ? 1'h0 : dirty_95; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2144 = 8'h60 == replaceId ? 1'h0 : dirty_96; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2145 = 8'h61 == replaceId ? 1'h0 : dirty_97; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2146 = 8'h62 == replaceId ? 1'h0 : dirty_98; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2147 = 8'h63 == replaceId ? 1'h0 : dirty_99; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2148 = 8'h64 == replaceId ? 1'h0 : dirty_100; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2149 = 8'h65 == replaceId ? 1'h0 : dirty_101; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2150 = 8'h66 == replaceId ? 1'h0 : dirty_102; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2151 = 8'h67 == replaceId ? 1'h0 : dirty_103; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2152 = 8'h68 == replaceId ? 1'h0 : dirty_104; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2153 = 8'h69 == replaceId ? 1'h0 : dirty_105; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2154 = 8'h6a == replaceId ? 1'h0 : dirty_106; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2155 = 8'h6b == replaceId ? 1'h0 : dirty_107; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2156 = 8'h6c == replaceId ? 1'h0 : dirty_108; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2157 = 8'h6d == replaceId ? 1'h0 : dirty_109; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2158 = 8'h6e == replaceId ? 1'h0 : dirty_110; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2159 = 8'h6f == replaceId ? 1'h0 : dirty_111; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2160 = 8'h70 == replaceId ? 1'h0 : dirty_112; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2161 = 8'h71 == replaceId ? 1'h0 : dirty_113; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2162 = 8'h72 == replaceId ? 1'h0 : dirty_114; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2163 = 8'h73 == replaceId ? 1'h0 : dirty_115; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2164 = 8'h74 == replaceId ? 1'h0 : dirty_116; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2165 = 8'h75 == replaceId ? 1'h0 : dirty_117; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2166 = 8'h76 == replaceId ? 1'h0 : dirty_118; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2167 = 8'h77 == replaceId ? 1'h0 : dirty_119; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2168 = 8'h78 == replaceId ? 1'h0 : dirty_120; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2169 = 8'h79 == replaceId ? 1'h0 : dirty_121; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2170 = 8'h7a == replaceId ? 1'h0 : dirty_122; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2171 = 8'h7b == replaceId ? 1'h0 : dirty_123; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2172 = 8'h7c == replaceId ? 1'h0 : dirty_124; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2173 = 8'h7d == replaceId ? 1'h0 : dirty_125; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2174 = 8'h7e == replaceId ? 1'h0 : dirty_126; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2175 = 8'h7f == replaceId ? 1'h0 : dirty_127; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2176 = 8'h80 == replaceId ? 1'h0 : dirty_128; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2177 = 8'h81 == replaceId ? 1'h0 : dirty_129; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2178 = 8'h82 == replaceId ? 1'h0 : dirty_130; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2179 = 8'h83 == replaceId ? 1'h0 : dirty_131; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2180 = 8'h84 == replaceId ? 1'h0 : dirty_132; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2181 = 8'h85 == replaceId ? 1'h0 : dirty_133; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2182 = 8'h86 == replaceId ? 1'h0 : dirty_134; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2183 = 8'h87 == replaceId ? 1'h0 : dirty_135; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2184 = 8'h88 == replaceId ? 1'h0 : dirty_136; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2185 = 8'h89 == replaceId ? 1'h0 : dirty_137; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2186 = 8'h8a == replaceId ? 1'h0 : dirty_138; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2187 = 8'h8b == replaceId ? 1'h0 : dirty_139; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2188 = 8'h8c == replaceId ? 1'h0 : dirty_140; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2189 = 8'h8d == replaceId ? 1'h0 : dirty_141; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2190 = 8'h8e == replaceId ? 1'h0 : dirty_142; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2191 = 8'h8f == replaceId ? 1'h0 : dirty_143; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2192 = 8'h90 == replaceId ? 1'h0 : dirty_144; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2193 = 8'h91 == replaceId ? 1'h0 : dirty_145; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2194 = 8'h92 == replaceId ? 1'h0 : dirty_146; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2195 = 8'h93 == replaceId ? 1'h0 : dirty_147; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2196 = 8'h94 == replaceId ? 1'h0 : dirty_148; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2197 = 8'h95 == replaceId ? 1'h0 : dirty_149; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2198 = 8'h96 == replaceId ? 1'h0 : dirty_150; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2199 = 8'h97 == replaceId ? 1'h0 : dirty_151; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2200 = 8'h98 == replaceId ? 1'h0 : dirty_152; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2201 = 8'h99 == replaceId ? 1'h0 : dirty_153; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2202 = 8'h9a == replaceId ? 1'h0 : dirty_154; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2203 = 8'h9b == replaceId ? 1'h0 : dirty_155; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2204 = 8'h9c == replaceId ? 1'h0 : dirty_156; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2205 = 8'h9d == replaceId ? 1'h0 : dirty_157; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2206 = 8'h9e == replaceId ? 1'h0 : dirty_158; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2207 = 8'h9f == replaceId ? 1'h0 : dirty_159; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2208 = 8'ha0 == replaceId ? 1'h0 : dirty_160; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2209 = 8'ha1 == replaceId ? 1'h0 : dirty_161; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2210 = 8'ha2 == replaceId ? 1'h0 : dirty_162; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2211 = 8'ha3 == replaceId ? 1'h0 : dirty_163; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2212 = 8'ha4 == replaceId ? 1'h0 : dirty_164; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2213 = 8'ha5 == replaceId ? 1'h0 : dirty_165; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2214 = 8'ha6 == replaceId ? 1'h0 : dirty_166; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2215 = 8'ha7 == replaceId ? 1'h0 : dirty_167; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2216 = 8'ha8 == replaceId ? 1'h0 : dirty_168; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2217 = 8'ha9 == replaceId ? 1'h0 : dirty_169; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2218 = 8'haa == replaceId ? 1'h0 : dirty_170; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2219 = 8'hab == replaceId ? 1'h0 : dirty_171; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2220 = 8'hac == replaceId ? 1'h0 : dirty_172; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2221 = 8'had == replaceId ? 1'h0 : dirty_173; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2222 = 8'hae == replaceId ? 1'h0 : dirty_174; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2223 = 8'haf == replaceId ? 1'h0 : dirty_175; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2224 = 8'hb0 == replaceId ? 1'h0 : dirty_176; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2225 = 8'hb1 == replaceId ? 1'h0 : dirty_177; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2226 = 8'hb2 == replaceId ? 1'h0 : dirty_178; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2227 = 8'hb3 == replaceId ? 1'h0 : dirty_179; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2228 = 8'hb4 == replaceId ? 1'h0 : dirty_180; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2229 = 8'hb5 == replaceId ? 1'h0 : dirty_181; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2230 = 8'hb6 == replaceId ? 1'h0 : dirty_182; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2231 = 8'hb7 == replaceId ? 1'h0 : dirty_183; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2232 = 8'hb8 == replaceId ? 1'h0 : dirty_184; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2233 = 8'hb9 == replaceId ? 1'h0 : dirty_185; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2234 = 8'hba == replaceId ? 1'h0 : dirty_186; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2235 = 8'hbb == replaceId ? 1'h0 : dirty_187; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2236 = 8'hbc == replaceId ? 1'h0 : dirty_188; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2237 = 8'hbd == replaceId ? 1'h0 : dirty_189; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2238 = 8'hbe == replaceId ? 1'h0 : dirty_190; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2239 = 8'hbf == replaceId ? 1'h0 : dirty_191; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2240 = 8'hc0 == replaceId ? 1'h0 : dirty_192; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2241 = 8'hc1 == replaceId ? 1'h0 : dirty_193; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2242 = 8'hc2 == replaceId ? 1'h0 : dirty_194; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2243 = 8'hc3 == replaceId ? 1'h0 : dirty_195; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2244 = 8'hc4 == replaceId ? 1'h0 : dirty_196; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2245 = 8'hc5 == replaceId ? 1'h0 : dirty_197; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2246 = 8'hc6 == replaceId ? 1'h0 : dirty_198; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2247 = 8'hc7 == replaceId ? 1'h0 : dirty_199; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2248 = 8'hc8 == replaceId ? 1'h0 : dirty_200; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2249 = 8'hc9 == replaceId ? 1'h0 : dirty_201; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2250 = 8'hca == replaceId ? 1'h0 : dirty_202; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2251 = 8'hcb == replaceId ? 1'h0 : dirty_203; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2252 = 8'hcc == replaceId ? 1'h0 : dirty_204; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2253 = 8'hcd == replaceId ? 1'h0 : dirty_205; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2254 = 8'hce == replaceId ? 1'h0 : dirty_206; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2255 = 8'hcf == replaceId ? 1'h0 : dirty_207; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2256 = 8'hd0 == replaceId ? 1'h0 : dirty_208; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2257 = 8'hd1 == replaceId ? 1'h0 : dirty_209; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2258 = 8'hd2 == replaceId ? 1'h0 : dirty_210; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2259 = 8'hd3 == replaceId ? 1'h0 : dirty_211; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2260 = 8'hd4 == replaceId ? 1'h0 : dirty_212; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2261 = 8'hd5 == replaceId ? 1'h0 : dirty_213; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2262 = 8'hd6 == replaceId ? 1'h0 : dirty_214; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2263 = 8'hd7 == replaceId ? 1'h0 : dirty_215; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2264 = 8'hd8 == replaceId ? 1'h0 : dirty_216; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2265 = 8'hd9 == replaceId ? 1'h0 : dirty_217; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2266 = 8'hda == replaceId ? 1'h0 : dirty_218; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2267 = 8'hdb == replaceId ? 1'h0 : dirty_219; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2268 = 8'hdc == replaceId ? 1'h0 : dirty_220; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2269 = 8'hdd == replaceId ? 1'h0 : dirty_221; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2270 = 8'hde == replaceId ? 1'h0 : dirty_222; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2271 = 8'hdf == replaceId ? 1'h0 : dirty_223; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2272 = 8'he0 == replaceId ? 1'h0 : dirty_224; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2273 = 8'he1 == replaceId ? 1'h0 : dirty_225; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2274 = 8'he2 == replaceId ? 1'h0 : dirty_226; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2275 = 8'he3 == replaceId ? 1'h0 : dirty_227; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2276 = 8'he4 == replaceId ? 1'h0 : dirty_228; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2277 = 8'he5 == replaceId ? 1'h0 : dirty_229; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2278 = 8'he6 == replaceId ? 1'h0 : dirty_230; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2279 = 8'he7 == replaceId ? 1'h0 : dirty_231; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2280 = 8'he8 == replaceId ? 1'h0 : dirty_232; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2281 = 8'he9 == replaceId ? 1'h0 : dirty_233; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2282 = 8'hea == replaceId ? 1'h0 : dirty_234; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2283 = 8'heb == replaceId ? 1'h0 : dirty_235; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2284 = 8'hec == replaceId ? 1'h0 : dirty_236; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2285 = 8'hed == replaceId ? 1'h0 : dirty_237; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2286 = 8'hee == replaceId ? 1'h0 : dirty_238; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2287 = 8'hef == replaceId ? 1'h0 : dirty_239; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2288 = 8'hf0 == replaceId ? 1'h0 : dirty_240; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2289 = 8'hf1 == replaceId ? 1'h0 : dirty_241; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2290 = 8'hf2 == replaceId ? 1'h0 : dirty_242; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2291 = 8'hf3 == replaceId ? 1'h0 : dirty_243; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2292 = 8'hf4 == replaceId ? 1'h0 : dirty_244; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2293 = 8'hf5 == replaceId ? 1'h0 : dirty_245; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2294 = 8'hf6 == replaceId ? 1'h0 : dirty_246; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2295 = 8'hf7 == replaceId ? 1'h0 : dirty_247; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2296 = 8'hf8 == replaceId ? 1'h0 : dirty_248; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2297 = 8'hf9 == replaceId ? 1'h0 : dirty_249; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2298 = 8'hfa == replaceId ? 1'h0 : dirty_250; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2299 = 8'hfb == replaceId ? 1'h0 : dirty_251; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2300 = 8'hfc == replaceId ? 1'h0 : dirty_252; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2301 = 8'hfd == replaceId ? 1'h0 : dirty_253; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2302 = 8'hfe == replaceId ? 1'h0 : dirty_254; // @[L1DCache.scala 343:22 497:{22,22}]
- wire _GEN_2303 = 8'hff == replaceId ? 1'h0 : dirty_255; // @[L1DCache.scala 343:22 497:{22,22}]
- wire [31:0] _camaddr_replaceId = {{1'd0}, alignedAddr}; // @[L1DCache.scala 499:{24,24}]
- wire [31:0] _GEN_2561 = 8'h1 == replaceId ? camaddr_1 : camaddr_0; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2562 = 8'h2 == replaceId ? camaddr_2 : _GEN_2561; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2563 = 8'h3 == replaceId ? camaddr_3 : _GEN_2562; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2564 = 8'h4 == replaceId ? camaddr_4 : _GEN_2563; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2565 = 8'h5 == replaceId ? camaddr_5 : _GEN_2564; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2566 = 8'h6 == replaceId ? camaddr_6 : _GEN_2565; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2567 = 8'h7 == replaceId ? camaddr_7 : _GEN_2566; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2568 = 8'h8 == replaceId ? camaddr_8 : _GEN_2567; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2569 = 8'h9 == replaceId ? camaddr_9 : _GEN_2568; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2570 = 8'ha == replaceId ? camaddr_10 : _GEN_2569; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2571 = 8'hb == replaceId ? camaddr_11 : _GEN_2570; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2572 = 8'hc == replaceId ? camaddr_12 : _GEN_2571; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2573 = 8'hd == replaceId ? camaddr_13 : _GEN_2572; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2574 = 8'he == replaceId ? camaddr_14 : _GEN_2573; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2575 = 8'hf == replaceId ? camaddr_15 : _GEN_2574; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2576 = 8'h10 == replaceId ? camaddr_16 : _GEN_2575; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2577 = 8'h11 == replaceId ? camaddr_17 : _GEN_2576; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2578 = 8'h12 == replaceId ? camaddr_18 : _GEN_2577; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2579 = 8'h13 == replaceId ? camaddr_19 : _GEN_2578; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2580 = 8'h14 == replaceId ? camaddr_20 : _GEN_2579; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2581 = 8'h15 == replaceId ? camaddr_21 : _GEN_2580; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2582 = 8'h16 == replaceId ? camaddr_22 : _GEN_2581; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2583 = 8'h17 == replaceId ? camaddr_23 : _GEN_2582; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2584 = 8'h18 == replaceId ? camaddr_24 : _GEN_2583; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2585 = 8'h19 == replaceId ? camaddr_25 : _GEN_2584; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2586 = 8'h1a == replaceId ? camaddr_26 : _GEN_2585; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2587 = 8'h1b == replaceId ? camaddr_27 : _GEN_2586; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2588 = 8'h1c == replaceId ? camaddr_28 : _GEN_2587; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2589 = 8'h1d == replaceId ? camaddr_29 : _GEN_2588; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2590 = 8'h1e == replaceId ? camaddr_30 : _GEN_2589; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2591 = 8'h1f == replaceId ? camaddr_31 : _GEN_2590; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2592 = 8'h20 == replaceId ? camaddr_32 : _GEN_2591; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2593 = 8'h21 == replaceId ? camaddr_33 : _GEN_2592; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2594 = 8'h22 == replaceId ? camaddr_34 : _GEN_2593; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2595 = 8'h23 == replaceId ? camaddr_35 : _GEN_2594; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2596 = 8'h24 == replaceId ? camaddr_36 : _GEN_2595; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2597 = 8'h25 == replaceId ? camaddr_37 : _GEN_2596; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2598 = 8'h26 == replaceId ? camaddr_38 : _GEN_2597; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2599 = 8'h27 == replaceId ? camaddr_39 : _GEN_2598; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2600 = 8'h28 == replaceId ? camaddr_40 : _GEN_2599; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2601 = 8'h29 == replaceId ? camaddr_41 : _GEN_2600; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2602 = 8'h2a == replaceId ? camaddr_42 : _GEN_2601; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2603 = 8'h2b == replaceId ? camaddr_43 : _GEN_2602; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2604 = 8'h2c == replaceId ? camaddr_44 : _GEN_2603; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2605 = 8'h2d == replaceId ? camaddr_45 : _GEN_2604; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2606 = 8'h2e == replaceId ? camaddr_46 : _GEN_2605; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2607 = 8'h2f == replaceId ? camaddr_47 : _GEN_2606; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2608 = 8'h30 == replaceId ? camaddr_48 : _GEN_2607; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2609 = 8'h31 == replaceId ? camaddr_49 : _GEN_2608; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2610 = 8'h32 == replaceId ? camaddr_50 : _GEN_2609; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2611 = 8'h33 == replaceId ? camaddr_51 : _GEN_2610; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2612 = 8'h34 == replaceId ? camaddr_52 : _GEN_2611; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2613 = 8'h35 == replaceId ? camaddr_53 : _GEN_2612; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2614 = 8'h36 == replaceId ? camaddr_54 : _GEN_2613; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2615 = 8'h37 == replaceId ? camaddr_55 : _GEN_2614; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2616 = 8'h38 == replaceId ? camaddr_56 : _GEN_2615; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2617 = 8'h39 == replaceId ? camaddr_57 : _GEN_2616; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2618 = 8'h3a == replaceId ? camaddr_58 : _GEN_2617; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2619 = 8'h3b == replaceId ? camaddr_59 : _GEN_2618; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2620 = 8'h3c == replaceId ? camaddr_60 : _GEN_2619; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2621 = 8'h3d == replaceId ? camaddr_61 : _GEN_2620; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2622 = 8'h3e == replaceId ? camaddr_62 : _GEN_2621; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2623 = 8'h3f == replaceId ? camaddr_63 : _GEN_2622; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2624 = 8'h40 == replaceId ? camaddr_64 : _GEN_2623; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2625 = 8'h41 == replaceId ? camaddr_65 : _GEN_2624; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2626 = 8'h42 == replaceId ? camaddr_66 : _GEN_2625; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2627 = 8'h43 == replaceId ? camaddr_67 : _GEN_2626; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2628 = 8'h44 == replaceId ? camaddr_68 : _GEN_2627; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2629 = 8'h45 == replaceId ? camaddr_69 : _GEN_2628; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2630 = 8'h46 == replaceId ? camaddr_70 : _GEN_2629; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2631 = 8'h47 == replaceId ? camaddr_71 : _GEN_2630; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2632 = 8'h48 == replaceId ? camaddr_72 : _GEN_2631; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2633 = 8'h49 == replaceId ? camaddr_73 : _GEN_2632; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2634 = 8'h4a == replaceId ? camaddr_74 : _GEN_2633; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2635 = 8'h4b == replaceId ? camaddr_75 : _GEN_2634; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2636 = 8'h4c == replaceId ? camaddr_76 : _GEN_2635; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2637 = 8'h4d == replaceId ? camaddr_77 : _GEN_2636; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2638 = 8'h4e == replaceId ? camaddr_78 : _GEN_2637; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2639 = 8'h4f == replaceId ? camaddr_79 : _GEN_2638; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2640 = 8'h50 == replaceId ? camaddr_80 : _GEN_2639; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2641 = 8'h51 == replaceId ? camaddr_81 : _GEN_2640; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2642 = 8'h52 == replaceId ? camaddr_82 : _GEN_2641; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2643 = 8'h53 == replaceId ? camaddr_83 : _GEN_2642; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2644 = 8'h54 == replaceId ? camaddr_84 : _GEN_2643; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2645 = 8'h55 == replaceId ? camaddr_85 : _GEN_2644; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2646 = 8'h56 == replaceId ? camaddr_86 : _GEN_2645; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2647 = 8'h57 == replaceId ? camaddr_87 : _GEN_2646; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2648 = 8'h58 == replaceId ? camaddr_88 : _GEN_2647; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2649 = 8'h59 == replaceId ? camaddr_89 : _GEN_2648; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2650 = 8'h5a == replaceId ? camaddr_90 : _GEN_2649; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2651 = 8'h5b == replaceId ? camaddr_91 : _GEN_2650; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2652 = 8'h5c == replaceId ? camaddr_92 : _GEN_2651; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2653 = 8'h5d == replaceId ? camaddr_93 : _GEN_2652; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2654 = 8'h5e == replaceId ? camaddr_94 : _GEN_2653; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2655 = 8'h5f == replaceId ? camaddr_95 : _GEN_2654; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2656 = 8'h60 == replaceId ? camaddr_96 : _GEN_2655; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2657 = 8'h61 == replaceId ? camaddr_97 : _GEN_2656; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2658 = 8'h62 == replaceId ? camaddr_98 : _GEN_2657; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2659 = 8'h63 == replaceId ? camaddr_99 : _GEN_2658; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2660 = 8'h64 == replaceId ? camaddr_100 : _GEN_2659; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2661 = 8'h65 == replaceId ? camaddr_101 : _GEN_2660; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2662 = 8'h66 == replaceId ? camaddr_102 : _GEN_2661; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2663 = 8'h67 == replaceId ? camaddr_103 : _GEN_2662; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2664 = 8'h68 == replaceId ? camaddr_104 : _GEN_2663; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2665 = 8'h69 == replaceId ? camaddr_105 : _GEN_2664; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2666 = 8'h6a == replaceId ? camaddr_106 : _GEN_2665; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2667 = 8'h6b == replaceId ? camaddr_107 : _GEN_2666; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2668 = 8'h6c == replaceId ? camaddr_108 : _GEN_2667; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2669 = 8'h6d == replaceId ? camaddr_109 : _GEN_2668; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2670 = 8'h6e == replaceId ? camaddr_110 : _GEN_2669; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2671 = 8'h6f == replaceId ? camaddr_111 : _GEN_2670; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2672 = 8'h70 == replaceId ? camaddr_112 : _GEN_2671; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2673 = 8'h71 == replaceId ? camaddr_113 : _GEN_2672; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2674 = 8'h72 == replaceId ? camaddr_114 : _GEN_2673; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2675 = 8'h73 == replaceId ? camaddr_115 : _GEN_2674; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2676 = 8'h74 == replaceId ? camaddr_116 : _GEN_2675; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2677 = 8'h75 == replaceId ? camaddr_117 : _GEN_2676; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2678 = 8'h76 == replaceId ? camaddr_118 : _GEN_2677; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2679 = 8'h77 == replaceId ? camaddr_119 : _GEN_2678; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2680 = 8'h78 == replaceId ? camaddr_120 : _GEN_2679; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2681 = 8'h79 == replaceId ? camaddr_121 : _GEN_2680; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2682 = 8'h7a == replaceId ? camaddr_122 : _GEN_2681; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2683 = 8'h7b == replaceId ? camaddr_123 : _GEN_2682; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2684 = 8'h7c == replaceId ? camaddr_124 : _GEN_2683; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2685 = 8'h7d == replaceId ? camaddr_125 : _GEN_2684; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2686 = 8'h7e == replaceId ? camaddr_126 : _GEN_2685; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2687 = 8'h7f == replaceId ? camaddr_127 : _GEN_2686; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2688 = 8'h80 == replaceId ? camaddr_128 : _GEN_2687; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2689 = 8'h81 == replaceId ? camaddr_129 : _GEN_2688; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2690 = 8'h82 == replaceId ? camaddr_130 : _GEN_2689; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2691 = 8'h83 == replaceId ? camaddr_131 : _GEN_2690; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2692 = 8'h84 == replaceId ? camaddr_132 : _GEN_2691; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2693 = 8'h85 == replaceId ? camaddr_133 : _GEN_2692; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2694 = 8'h86 == replaceId ? camaddr_134 : _GEN_2693; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2695 = 8'h87 == replaceId ? camaddr_135 : _GEN_2694; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2696 = 8'h88 == replaceId ? camaddr_136 : _GEN_2695; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2697 = 8'h89 == replaceId ? camaddr_137 : _GEN_2696; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2698 = 8'h8a == replaceId ? camaddr_138 : _GEN_2697; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2699 = 8'h8b == replaceId ? camaddr_139 : _GEN_2698; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2700 = 8'h8c == replaceId ? camaddr_140 : _GEN_2699; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2701 = 8'h8d == replaceId ? camaddr_141 : _GEN_2700; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2702 = 8'h8e == replaceId ? camaddr_142 : _GEN_2701; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2703 = 8'h8f == replaceId ? camaddr_143 : _GEN_2702; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2704 = 8'h90 == replaceId ? camaddr_144 : _GEN_2703; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2705 = 8'h91 == replaceId ? camaddr_145 : _GEN_2704; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2706 = 8'h92 == replaceId ? camaddr_146 : _GEN_2705; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2707 = 8'h93 == replaceId ? camaddr_147 : _GEN_2706; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2708 = 8'h94 == replaceId ? camaddr_148 : _GEN_2707; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2709 = 8'h95 == replaceId ? camaddr_149 : _GEN_2708; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2710 = 8'h96 == replaceId ? camaddr_150 : _GEN_2709; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2711 = 8'h97 == replaceId ? camaddr_151 : _GEN_2710; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2712 = 8'h98 == replaceId ? camaddr_152 : _GEN_2711; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2713 = 8'h99 == replaceId ? camaddr_153 : _GEN_2712; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2714 = 8'h9a == replaceId ? camaddr_154 : _GEN_2713; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2715 = 8'h9b == replaceId ? camaddr_155 : _GEN_2714; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2716 = 8'h9c == replaceId ? camaddr_156 : _GEN_2715; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2717 = 8'h9d == replaceId ? camaddr_157 : _GEN_2716; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2718 = 8'h9e == replaceId ? camaddr_158 : _GEN_2717; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2719 = 8'h9f == replaceId ? camaddr_159 : _GEN_2718; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2720 = 8'ha0 == replaceId ? camaddr_160 : _GEN_2719; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2721 = 8'ha1 == replaceId ? camaddr_161 : _GEN_2720; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2722 = 8'ha2 == replaceId ? camaddr_162 : _GEN_2721; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2723 = 8'ha3 == replaceId ? camaddr_163 : _GEN_2722; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2724 = 8'ha4 == replaceId ? camaddr_164 : _GEN_2723; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2725 = 8'ha5 == replaceId ? camaddr_165 : _GEN_2724; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2726 = 8'ha6 == replaceId ? camaddr_166 : _GEN_2725; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2727 = 8'ha7 == replaceId ? camaddr_167 : _GEN_2726; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2728 = 8'ha8 == replaceId ? camaddr_168 : _GEN_2727; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2729 = 8'ha9 == replaceId ? camaddr_169 : _GEN_2728; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2730 = 8'haa == replaceId ? camaddr_170 : _GEN_2729; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2731 = 8'hab == replaceId ? camaddr_171 : _GEN_2730; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2732 = 8'hac == replaceId ? camaddr_172 : _GEN_2731; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2733 = 8'had == replaceId ? camaddr_173 : _GEN_2732; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2734 = 8'hae == replaceId ? camaddr_174 : _GEN_2733; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2735 = 8'haf == replaceId ? camaddr_175 : _GEN_2734; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2736 = 8'hb0 == replaceId ? camaddr_176 : _GEN_2735; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2737 = 8'hb1 == replaceId ? camaddr_177 : _GEN_2736; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2738 = 8'hb2 == replaceId ? camaddr_178 : _GEN_2737; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2739 = 8'hb3 == replaceId ? camaddr_179 : _GEN_2738; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2740 = 8'hb4 == replaceId ? camaddr_180 : _GEN_2739; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2741 = 8'hb5 == replaceId ? camaddr_181 : _GEN_2740; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2742 = 8'hb6 == replaceId ? camaddr_182 : _GEN_2741; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2743 = 8'hb7 == replaceId ? camaddr_183 : _GEN_2742; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2744 = 8'hb8 == replaceId ? camaddr_184 : _GEN_2743; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2745 = 8'hb9 == replaceId ? camaddr_185 : _GEN_2744; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2746 = 8'hba == replaceId ? camaddr_186 : _GEN_2745; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2747 = 8'hbb == replaceId ? camaddr_187 : _GEN_2746; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2748 = 8'hbc == replaceId ? camaddr_188 : _GEN_2747; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2749 = 8'hbd == replaceId ? camaddr_189 : _GEN_2748; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2750 = 8'hbe == replaceId ? camaddr_190 : _GEN_2749; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2751 = 8'hbf == replaceId ? camaddr_191 : _GEN_2750; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2752 = 8'hc0 == replaceId ? camaddr_192 : _GEN_2751; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2753 = 8'hc1 == replaceId ? camaddr_193 : _GEN_2752; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2754 = 8'hc2 == replaceId ? camaddr_194 : _GEN_2753; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2755 = 8'hc3 == replaceId ? camaddr_195 : _GEN_2754; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2756 = 8'hc4 == replaceId ? camaddr_196 : _GEN_2755; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2757 = 8'hc5 == replaceId ? camaddr_197 : _GEN_2756; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2758 = 8'hc6 == replaceId ? camaddr_198 : _GEN_2757; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2759 = 8'hc7 == replaceId ? camaddr_199 : _GEN_2758; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2760 = 8'hc8 == replaceId ? camaddr_200 : _GEN_2759; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2761 = 8'hc9 == replaceId ? camaddr_201 : _GEN_2760; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2762 = 8'hca == replaceId ? camaddr_202 : _GEN_2761; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2763 = 8'hcb == replaceId ? camaddr_203 : _GEN_2762; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2764 = 8'hcc == replaceId ? camaddr_204 : _GEN_2763; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2765 = 8'hcd == replaceId ? camaddr_205 : _GEN_2764; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2766 = 8'hce == replaceId ? camaddr_206 : _GEN_2765; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2767 = 8'hcf == replaceId ? camaddr_207 : _GEN_2766; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2768 = 8'hd0 == replaceId ? camaddr_208 : _GEN_2767; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2769 = 8'hd1 == replaceId ? camaddr_209 : _GEN_2768; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2770 = 8'hd2 == replaceId ? camaddr_210 : _GEN_2769; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2771 = 8'hd3 == replaceId ? camaddr_211 : _GEN_2770; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2772 = 8'hd4 == replaceId ? camaddr_212 : _GEN_2771; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2773 = 8'hd5 == replaceId ? camaddr_213 : _GEN_2772; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2774 = 8'hd6 == replaceId ? camaddr_214 : _GEN_2773; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2775 = 8'hd7 == replaceId ? camaddr_215 : _GEN_2774; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2776 = 8'hd8 == replaceId ? camaddr_216 : _GEN_2775; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2777 = 8'hd9 == replaceId ? camaddr_217 : _GEN_2776; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2778 = 8'hda == replaceId ? camaddr_218 : _GEN_2777; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2779 = 8'hdb == replaceId ? camaddr_219 : _GEN_2778; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2780 = 8'hdc == replaceId ? camaddr_220 : _GEN_2779; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2781 = 8'hdd == replaceId ? camaddr_221 : _GEN_2780; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2782 = 8'hde == replaceId ? camaddr_222 : _GEN_2781; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2783 = 8'hdf == replaceId ? camaddr_223 : _GEN_2782; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2784 = 8'he0 == replaceId ? camaddr_224 : _GEN_2783; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2785 = 8'he1 == replaceId ? camaddr_225 : _GEN_2784; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2786 = 8'he2 == replaceId ? camaddr_226 : _GEN_2785; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2787 = 8'he3 == replaceId ? camaddr_227 : _GEN_2786; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2788 = 8'he4 == replaceId ? camaddr_228 : _GEN_2787; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2789 = 8'he5 == replaceId ? camaddr_229 : _GEN_2788; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2790 = 8'he6 == replaceId ? camaddr_230 : _GEN_2789; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2791 = 8'he7 == replaceId ? camaddr_231 : _GEN_2790; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2792 = 8'he8 == replaceId ? camaddr_232 : _GEN_2791; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2793 = 8'he9 == replaceId ? camaddr_233 : _GEN_2792; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2794 = 8'hea == replaceId ? camaddr_234 : _GEN_2793; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2795 = 8'heb == replaceId ? camaddr_235 : _GEN_2794; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2796 = 8'hec == replaceId ? camaddr_236 : _GEN_2795; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2797 = 8'hed == replaceId ? camaddr_237 : _GEN_2796; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2798 = 8'hee == replaceId ? camaddr_238 : _GEN_2797; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2799 = 8'hef == replaceId ? camaddr_239 : _GEN_2798; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2800 = 8'hf0 == replaceId ? camaddr_240 : _GEN_2799; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2801 = 8'hf1 == replaceId ? camaddr_241 : _GEN_2800; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2802 = 8'hf2 == replaceId ? camaddr_242 : _GEN_2801; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2803 = 8'hf3 == replaceId ? camaddr_243 : _GEN_2802; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2804 = 8'hf4 == replaceId ? camaddr_244 : _GEN_2803; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2805 = 8'hf5 == replaceId ? camaddr_245 : _GEN_2804; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2806 = 8'hf6 == replaceId ? camaddr_246 : _GEN_2805; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2807 = 8'hf7 == replaceId ? camaddr_247 : _GEN_2806; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2808 = 8'hf8 == replaceId ? camaddr_248 : _GEN_2807; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2809 = 8'hf9 == replaceId ? camaddr_249 : _GEN_2808; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2810 = 8'hfa == replaceId ? camaddr_250 : _GEN_2809; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2811 = 8'hfb == replaceId ? camaddr_251 : _GEN_2810; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2812 = 8'hfc == replaceId ? camaddr_252 : _GEN_2811; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2813 = 8'hfd == replaceId ? camaddr_253 : _GEN_2812; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2814 = 8'hfe == replaceId ? camaddr_254 : _GEN_2813; // @[L1DCache.scala 501:{14,14}]
- wire [31:0] _GEN_2815 = 8'hff == replaceId ? camaddr_255 : _GEN_2814; // @[L1DCache.scala 501:{14,14}]
- wire _GEN_2816 = io_dbus_valid & ~io_dbus_ready & ~active | ractive; // @[L1DCache.scala 490:53 491:13 467:24]
- wire _GEN_2818 = io_dbus_valid & ~io_dbus_ready & ~active | axiraddrvalid; // @[L1DCache.scala 490:53 494:19 473:30]
- wire _GEN_2819 = io_dbus_valid & ~io_dbus_ready & ~active | axirdataready; // @[L1DCache.scala 490:53 495:19 474:30]
- wire _GEN_2820 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1792 : valid_0; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2821 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1793 : valid_1; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2822 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1794 : valid_2; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2823 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1795 : valid_3; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2824 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1796 : valid_4; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2825 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1797 : valid_5; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2826 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1798 : valid_6; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2827 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1799 : valid_7; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2828 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1800 : valid_8; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2829 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1801 : valid_9; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2830 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1802 : valid_10; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2831 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1803 : valid_11; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2832 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1804 : valid_12; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2833 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1805 : valid_13; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2834 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1806 : valid_14; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2835 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1807 : valid_15; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2836 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1808 : valid_16; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2837 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1809 : valid_17; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2838 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1810 : valid_18; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2839 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1811 : valid_19; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2840 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1812 : valid_20; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2841 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1813 : valid_21; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2842 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1814 : valid_22; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2843 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1815 : valid_23; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2844 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1816 : valid_24; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2845 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1817 : valid_25; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2846 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1818 : valid_26; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2847 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1819 : valid_27; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2848 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1820 : valid_28; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2849 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1821 : valid_29; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2850 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1822 : valid_30; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2851 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1823 : valid_31; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2852 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1824 : valid_32; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2853 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1825 : valid_33; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2854 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1826 : valid_34; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2855 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1827 : valid_35; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2856 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1828 : valid_36; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2857 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1829 : valid_37; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2858 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1830 : valid_38; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2859 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1831 : valid_39; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2860 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1832 : valid_40; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2861 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1833 : valid_41; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2862 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1834 : valid_42; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2863 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1835 : valid_43; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2864 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1836 : valid_44; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2865 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1837 : valid_45; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2866 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1838 : valid_46; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2867 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1839 : valid_47; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2868 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1840 : valid_48; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2869 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1841 : valid_49; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2870 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1842 : valid_50; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2871 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1843 : valid_51; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2872 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1844 : valid_52; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2873 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1845 : valid_53; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2874 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1846 : valid_54; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2875 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1847 : valid_55; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2876 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1848 : valid_56; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2877 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1849 : valid_57; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2878 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1850 : valid_58; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2879 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1851 : valid_59; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2880 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1852 : valid_60; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2881 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1853 : valid_61; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2882 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1854 : valid_62; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2883 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1855 : valid_63; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2884 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1856 : valid_64; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2885 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1857 : valid_65; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2886 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1858 : valid_66; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2887 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1859 : valid_67; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2888 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1860 : valid_68; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2889 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1861 : valid_69; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2890 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1862 : valid_70; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2891 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1863 : valid_71; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2892 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1864 : valid_72; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2893 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1865 : valid_73; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2894 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1866 : valid_74; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2895 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1867 : valid_75; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2896 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1868 : valid_76; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2897 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1869 : valid_77; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2898 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1870 : valid_78; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2899 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1871 : valid_79; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2900 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1872 : valid_80; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2901 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1873 : valid_81; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2902 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1874 : valid_82; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2903 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1875 : valid_83; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2904 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1876 : valid_84; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2905 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1877 : valid_85; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2906 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1878 : valid_86; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2907 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1879 : valid_87; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2908 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1880 : valid_88; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2909 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1881 : valid_89; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2910 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1882 : valid_90; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2911 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1883 : valid_91; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2912 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1884 : valid_92; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2913 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1885 : valid_93; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2914 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1886 : valid_94; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2915 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1887 : valid_95; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2916 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1888 : valid_96; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2917 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1889 : valid_97; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2918 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1890 : valid_98; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2919 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1891 : valid_99; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2920 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1892 : valid_100; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2921 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1893 : valid_101; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2922 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1894 : valid_102; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2923 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1895 : valid_103; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2924 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1896 : valid_104; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2925 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1897 : valid_105; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2926 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1898 : valid_106; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2927 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1899 : valid_107; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2928 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1900 : valid_108; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2929 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1901 : valid_109; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2930 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1902 : valid_110; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2931 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1903 : valid_111; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2932 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1904 : valid_112; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2933 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1905 : valid_113; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2934 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1906 : valid_114; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2935 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1907 : valid_115; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2936 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1908 : valid_116; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2937 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1909 : valid_117; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2938 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1910 : valid_118; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2939 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1911 : valid_119; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2940 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1912 : valid_120; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2941 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1913 : valid_121; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2942 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1914 : valid_122; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2943 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1915 : valid_123; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2944 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1916 : valid_124; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2945 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1917 : valid_125; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2946 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1918 : valid_126; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2947 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1919 : valid_127; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2948 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1920 : valid_128; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2949 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1921 : valid_129; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2950 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1922 : valid_130; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2951 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1923 : valid_131; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2952 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1924 : valid_132; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2953 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1925 : valid_133; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2954 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1926 : valid_134; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2955 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1927 : valid_135; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2956 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1928 : valid_136; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2957 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1929 : valid_137; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2958 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1930 : valid_138; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2959 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1931 : valid_139; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2960 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1932 : valid_140; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2961 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1933 : valid_141; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2962 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1934 : valid_142; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2963 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1935 : valid_143; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2964 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1936 : valid_144; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2965 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1937 : valid_145; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2966 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1938 : valid_146; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2967 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1939 : valid_147; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2968 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1940 : valid_148; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2969 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1941 : valid_149; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2970 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1942 : valid_150; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2971 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1943 : valid_151; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2972 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1944 : valid_152; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2973 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1945 : valid_153; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2974 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1946 : valid_154; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2975 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1947 : valid_155; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2976 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1948 : valid_156; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2977 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1949 : valid_157; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2978 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1950 : valid_158; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2979 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1951 : valid_159; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2980 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1952 : valid_160; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2981 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1953 : valid_161; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2982 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1954 : valid_162; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2983 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1955 : valid_163; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2984 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1956 : valid_164; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2985 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1957 : valid_165; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2986 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1958 : valid_166; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2987 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1959 : valid_167; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2988 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1960 : valid_168; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2989 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1961 : valid_169; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2990 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1962 : valid_170; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2991 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1963 : valid_171; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2992 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1964 : valid_172; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2993 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1965 : valid_173; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2994 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1966 : valid_174; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2995 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1967 : valid_175; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2996 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1968 : valid_176; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2997 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1969 : valid_177; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2998 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1970 : valid_178; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_2999 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1971 : valid_179; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3000 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1972 : valid_180; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3001 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1973 : valid_181; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3002 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1974 : valid_182; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3003 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1975 : valid_183; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3004 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1976 : valid_184; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3005 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1977 : valid_185; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3006 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1978 : valid_186; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3007 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1979 : valid_187; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3008 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1980 : valid_188; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3009 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1981 : valid_189; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3010 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1982 : valid_190; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3011 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1983 : valid_191; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3012 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1984 : valid_192; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3013 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1985 : valid_193; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3014 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1986 : valid_194; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3015 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1987 : valid_195; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3016 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1988 : valid_196; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3017 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1989 : valid_197; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3018 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1990 : valid_198; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3019 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1991 : valid_199; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3020 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1992 : valid_200; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3021 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1993 : valid_201; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3022 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1994 : valid_202; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3023 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1995 : valid_203; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3024 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1996 : valid_204; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3025 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1997 : valid_205; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3026 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1998 : valid_206; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3027 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_1999 : valid_207; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3028 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2000 : valid_208; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3029 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2001 : valid_209; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3030 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2002 : valid_210; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3031 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2003 : valid_211; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3032 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2004 : valid_212; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3033 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2005 : valid_213; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3034 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2006 : valid_214; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3035 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2007 : valid_215; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3036 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2008 : valid_216; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3037 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2009 : valid_217; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3038 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2010 : valid_218; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3039 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2011 : valid_219; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3040 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2012 : valid_220; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3041 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2013 : valid_221; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3042 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2014 : valid_222; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3043 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2015 : valid_223; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3044 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2016 : valid_224; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3045 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2017 : valid_225; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3046 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2018 : valid_226; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3047 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2019 : valid_227; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3048 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2020 : valid_228; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3049 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2021 : valid_229; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3050 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2022 : valid_230; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3051 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2023 : valid_231; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3052 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2024 : valid_232; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3053 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2025 : valid_233; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3054 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2026 : valid_234; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3055 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2027 : valid_235; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3056 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2028 : valid_236; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3057 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2029 : valid_237; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3058 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2030 : valid_238; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3059 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2031 : valid_239; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3060 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2032 : valid_240; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3061 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2033 : valid_241; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3062 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2034 : valid_242; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3063 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2035 : valid_243; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3064 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2036 : valid_244; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3065 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2037 : valid_245; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3066 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2038 : valid_246; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3067 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2039 : valid_247; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3068 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2040 : valid_248; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3069 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2041 : valid_249; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3070 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2042 : valid_250; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3071 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2043 : valid_251; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3072 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2044 : valid_252; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3073 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2045 : valid_253; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3074 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2046 : valid_254; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3075 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2047 : valid_255; // @[L1DCache.scala 342:22 490:53]
- wire _GEN_3076 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2048 : dirty_0; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3077 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2049 : dirty_1; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3078 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2050 : dirty_2; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3079 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2051 : dirty_3; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3080 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2052 : dirty_4; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3081 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2053 : dirty_5; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3082 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2054 : dirty_6; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3083 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2055 : dirty_7; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3084 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2056 : dirty_8; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3085 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2057 : dirty_9; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3086 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2058 : dirty_10; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3087 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2059 : dirty_11; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3088 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2060 : dirty_12; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3089 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2061 : dirty_13; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3090 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2062 : dirty_14; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3091 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2063 : dirty_15; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3092 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2064 : dirty_16; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3093 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2065 : dirty_17; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3094 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2066 : dirty_18; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3095 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2067 : dirty_19; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3096 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2068 : dirty_20; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3097 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2069 : dirty_21; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3098 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2070 : dirty_22; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3099 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2071 : dirty_23; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3100 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2072 : dirty_24; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3101 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2073 : dirty_25; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3102 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2074 : dirty_26; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3103 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2075 : dirty_27; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3104 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2076 : dirty_28; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3105 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2077 : dirty_29; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3106 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2078 : dirty_30; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3107 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2079 : dirty_31; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3108 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2080 : dirty_32; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3109 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2081 : dirty_33; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3110 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2082 : dirty_34; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3111 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2083 : dirty_35; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3112 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2084 : dirty_36; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3113 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2085 : dirty_37; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3114 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2086 : dirty_38; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3115 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2087 : dirty_39; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3116 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2088 : dirty_40; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3117 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2089 : dirty_41; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3118 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2090 : dirty_42; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3119 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2091 : dirty_43; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3120 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2092 : dirty_44; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3121 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2093 : dirty_45; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3122 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2094 : dirty_46; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3123 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2095 : dirty_47; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3124 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2096 : dirty_48; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3125 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2097 : dirty_49; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3126 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2098 : dirty_50; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3127 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2099 : dirty_51; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3128 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2100 : dirty_52; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3129 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2101 : dirty_53; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3130 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2102 : dirty_54; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3131 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2103 : dirty_55; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3132 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2104 : dirty_56; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3133 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2105 : dirty_57; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3134 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2106 : dirty_58; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3135 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2107 : dirty_59; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3136 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2108 : dirty_60; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3137 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2109 : dirty_61; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3138 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2110 : dirty_62; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3139 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2111 : dirty_63; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3140 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2112 : dirty_64; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3141 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2113 : dirty_65; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3142 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2114 : dirty_66; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3143 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2115 : dirty_67; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3144 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2116 : dirty_68; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3145 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2117 : dirty_69; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3146 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2118 : dirty_70; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3147 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2119 : dirty_71; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3148 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2120 : dirty_72; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3149 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2121 : dirty_73; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3150 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2122 : dirty_74; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3151 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2123 : dirty_75; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3152 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2124 : dirty_76; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3153 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2125 : dirty_77; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3154 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2126 : dirty_78; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3155 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2127 : dirty_79; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3156 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2128 : dirty_80; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3157 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2129 : dirty_81; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3158 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2130 : dirty_82; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3159 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2131 : dirty_83; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3160 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2132 : dirty_84; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3161 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2133 : dirty_85; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3162 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2134 : dirty_86; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3163 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2135 : dirty_87; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3164 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2136 : dirty_88; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3165 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2137 : dirty_89; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3166 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2138 : dirty_90; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3167 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2139 : dirty_91; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3168 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2140 : dirty_92; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3169 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2141 : dirty_93; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3170 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2142 : dirty_94; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3171 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2143 : dirty_95; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3172 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2144 : dirty_96; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3173 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2145 : dirty_97; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3174 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2146 : dirty_98; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3175 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2147 : dirty_99; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3176 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2148 : dirty_100; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3177 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2149 : dirty_101; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3178 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2150 : dirty_102; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3179 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2151 : dirty_103; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3180 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2152 : dirty_104; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3181 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2153 : dirty_105; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3182 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2154 : dirty_106; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3183 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2155 : dirty_107; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3184 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2156 : dirty_108; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3185 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2157 : dirty_109; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3186 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2158 : dirty_110; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3187 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2159 : dirty_111; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3188 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2160 : dirty_112; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3189 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2161 : dirty_113; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3190 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2162 : dirty_114; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3191 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2163 : dirty_115; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3192 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2164 : dirty_116; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3193 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2165 : dirty_117; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3194 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2166 : dirty_118; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3195 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2167 : dirty_119; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3196 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2168 : dirty_120; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3197 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2169 : dirty_121; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3198 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2170 : dirty_122; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3199 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2171 : dirty_123; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3200 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2172 : dirty_124; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3201 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2173 : dirty_125; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3202 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2174 : dirty_126; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3203 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2175 : dirty_127; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3204 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2176 : dirty_128; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3205 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2177 : dirty_129; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3206 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2178 : dirty_130; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3207 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2179 : dirty_131; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3208 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2180 : dirty_132; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3209 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2181 : dirty_133; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3210 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2182 : dirty_134; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3211 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2183 : dirty_135; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3212 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2184 : dirty_136; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3213 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2185 : dirty_137; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3214 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2186 : dirty_138; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3215 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2187 : dirty_139; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3216 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2188 : dirty_140; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3217 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2189 : dirty_141; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3218 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2190 : dirty_142; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3219 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2191 : dirty_143; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3220 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2192 : dirty_144; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3221 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2193 : dirty_145; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3222 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2194 : dirty_146; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3223 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2195 : dirty_147; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3224 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2196 : dirty_148; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3225 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2197 : dirty_149; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3226 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2198 : dirty_150; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3227 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2199 : dirty_151; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3228 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2200 : dirty_152; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3229 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2201 : dirty_153; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3230 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2202 : dirty_154; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3231 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2203 : dirty_155; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3232 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2204 : dirty_156; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3233 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2205 : dirty_157; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3234 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2206 : dirty_158; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3235 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2207 : dirty_159; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3236 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2208 : dirty_160; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3237 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2209 : dirty_161; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3238 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2210 : dirty_162; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3239 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2211 : dirty_163; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3240 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2212 : dirty_164; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3241 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2213 : dirty_165; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3242 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2214 : dirty_166; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3243 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2215 : dirty_167; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3244 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2216 : dirty_168; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3245 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2217 : dirty_169; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3246 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2218 : dirty_170; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3247 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2219 : dirty_171; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3248 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2220 : dirty_172; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3249 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2221 : dirty_173; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3250 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2222 : dirty_174; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3251 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2223 : dirty_175; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3252 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2224 : dirty_176; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3253 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2225 : dirty_177; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3254 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2226 : dirty_178; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3255 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2227 : dirty_179; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3256 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2228 : dirty_180; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3257 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2229 : dirty_181; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3258 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2230 : dirty_182; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3259 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2231 : dirty_183; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3260 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2232 : dirty_184; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3261 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2233 : dirty_185; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3262 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2234 : dirty_186; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3263 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2235 : dirty_187; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3264 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2236 : dirty_188; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3265 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2237 : dirty_189; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3266 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2238 : dirty_190; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3267 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2239 : dirty_191; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3268 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2240 : dirty_192; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3269 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2241 : dirty_193; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3270 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2242 : dirty_194; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3271 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2243 : dirty_195; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3272 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2244 : dirty_196; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3273 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2245 : dirty_197; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3274 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2246 : dirty_198; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3275 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2247 : dirty_199; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3276 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2248 : dirty_200; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3277 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2249 : dirty_201; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3278 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2250 : dirty_202; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3279 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2251 : dirty_203; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3280 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2252 : dirty_204; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3281 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2253 : dirty_205; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3282 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2254 : dirty_206; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3283 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2255 : dirty_207; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3284 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2256 : dirty_208; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3285 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2257 : dirty_209; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3286 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2258 : dirty_210; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3287 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2259 : dirty_211; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3288 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2260 : dirty_212; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3289 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2261 : dirty_213; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3290 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2262 : dirty_214; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3291 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2263 : dirty_215; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3292 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2264 : dirty_216; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3293 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2265 : dirty_217; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3294 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2266 : dirty_218; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3295 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2267 : dirty_219; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3296 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2268 : dirty_220; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3297 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2269 : dirty_221; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3298 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2270 : dirty_222; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3299 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2271 : dirty_223; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3300 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2272 : dirty_224; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3301 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2273 : dirty_225; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3302 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2274 : dirty_226; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3303 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2275 : dirty_227; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3304 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2276 : dirty_228; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3305 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2277 : dirty_229; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3306 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2278 : dirty_230; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3307 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2279 : dirty_231; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3308 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2280 : dirty_232; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3309 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2281 : dirty_233; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3310 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2282 : dirty_234; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3311 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2283 : dirty_235; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3312 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2284 : dirty_236; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3313 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2285 : dirty_237; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3314 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2286 : dirty_238; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3315 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2287 : dirty_239; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3316 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2288 : dirty_240; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3317 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2289 : dirty_241; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3318 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2290 : dirty_242; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3319 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2291 : dirty_243; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3320 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2292 : dirty_244; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3321 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2293 : dirty_245; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3322 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2294 : dirty_246; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3323 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2295 : dirty_247; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3324 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2296 : dirty_248; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3325 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2297 : dirty_249; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3326 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2298 : dirty_250; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3327 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2299 : dirty_251; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3328 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2300 : dirty_252; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3329 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2301 : dirty_253; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3330 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2302 : dirty_254; // @[L1DCache.scala 343:22 490:53]
- wire _GEN_3331 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2303 : dirty_255; // @[L1DCache.scala 343:22 490:53]
- wire [7:0] _GEN_3332 = io_dbus_valid & ~io_dbus_ready & ~active ? replaceId : replaceIdReg; // @[L1DCache.scala 490:53 498:18 486:25]
- wire [31:0] _GEN_3590 = io_dbus_valid & ~io_dbus_ready & ~active ? _GEN_2815 : axiwaddr; // @[L1DCache.scala 490:53 501:14 484:21]
- wire _T_4255 = _T_1563 & io_dbus_write; // @[L1DCache.scala 508:40]
- wire _GEN_3591 = 8'h0 == foundId | _GEN_3076; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3592 = 8'h1 == foundId | _GEN_3077; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3593 = 8'h2 == foundId | _GEN_3078; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3594 = 8'h3 == foundId | _GEN_3079; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3595 = 8'h4 == foundId | _GEN_3080; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3596 = 8'h5 == foundId | _GEN_3081; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3597 = 8'h6 == foundId | _GEN_3082; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3598 = 8'h7 == foundId | _GEN_3083; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3599 = 8'h8 == foundId | _GEN_3084; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3600 = 8'h9 == foundId | _GEN_3085; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3601 = 8'ha == foundId | _GEN_3086; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3602 = 8'hb == foundId | _GEN_3087; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3603 = 8'hc == foundId | _GEN_3088; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3604 = 8'hd == foundId | _GEN_3089; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3605 = 8'he == foundId | _GEN_3090; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3606 = 8'hf == foundId | _GEN_3091; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3607 = 8'h10 == foundId | _GEN_3092; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3608 = 8'h11 == foundId | _GEN_3093; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3609 = 8'h12 == foundId | _GEN_3094; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3610 = 8'h13 == foundId | _GEN_3095; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3611 = 8'h14 == foundId | _GEN_3096; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3612 = 8'h15 == foundId | _GEN_3097; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3613 = 8'h16 == foundId | _GEN_3098; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3614 = 8'h17 == foundId | _GEN_3099; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3615 = 8'h18 == foundId | _GEN_3100; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3616 = 8'h19 == foundId | _GEN_3101; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3617 = 8'h1a == foundId | _GEN_3102; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3618 = 8'h1b == foundId | _GEN_3103; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3619 = 8'h1c == foundId | _GEN_3104; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3620 = 8'h1d == foundId | _GEN_3105; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3621 = 8'h1e == foundId | _GEN_3106; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3622 = 8'h1f == foundId | _GEN_3107; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3623 = 8'h20 == foundId | _GEN_3108; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3624 = 8'h21 == foundId | _GEN_3109; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3625 = 8'h22 == foundId | _GEN_3110; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3626 = 8'h23 == foundId | _GEN_3111; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3627 = 8'h24 == foundId | _GEN_3112; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3628 = 8'h25 == foundId | _GEN_3113; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3629 = 8'h26 == foundId | _GEN_3114; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3630 = 8'h27 == foundId | _GEN_3115; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3631 = 8'h28 == foundId | _GEN_3116; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3632 = 8'h29 == foundId | _GEN_3117; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3633 = 8'h2a == foundId | _GEN_3118; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3634 = 8'h2b == foundId | _GEN_3119; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3635 = 8'h2c == foundId | _GEN_3120; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3636 = 8'h2d == foundId | _GEN_3121; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3637 = 8'h2e == foundId | _GEN_3122; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3638 = 8'h2f == foundId | _GEN_3123; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3639 = 8'h30 == foundId | _GEN_3124; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3640 = 8'h31 == foundId | _GEN_3125; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3641 = 8'h32 == foundId | _GEN_3126; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3642 = 8'h33 == foundId | _GEN_3127; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3643 = 8'h34 == foundId | _GEN_3128; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3644 = 8'h35 == foundId | _GEN_3129; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3645 = 8'h36 == foundId | _GEN_3130; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3646 = 8'h37 == foundId | _GEN_3131; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3647 = 8'h38 == foundId | _GEN_3132; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3648 = 8'h39 == foundId | _GEN_3133; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3649 = 8'h3a == foundId | _GEN_3134; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3650 = 8'h3b == foundId | _GEN_3135; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3651 = 8'h3c == foundId | _GEN_3136; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3652 = 8'h3d == foundId | _GEN_3137; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3653 = 8'h3e == foundId | _GEN_3138; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3654 = 8'h3f == foundId | _GEN_3139; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3655 = 8'h40 == foundId | _GEN_3140; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3656 = 8'h41 == foundId | _GEN_3141; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3657 = 8'h42 == foundId | _GEN_3142; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3658 = 8'h43 == foundId | _GEN_3143; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3659 = 8'h44 == foundId | _GEN_3144; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3660 = 8'h45 == foundId | _GEN_3145; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3661 = 8'h46 == foundId | _GEN_3146; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3662 = 8'h47 == foundId | _GEN_3147; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3663 = 8'h48 == foundId | _GEN_3148; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3664 = 8'h49 == foundId | _GEN_3149; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3665 = 8'h4a == foundId | _GEN_3150; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3666 = 8'h4b == foundId | _GEN_3151; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3667 = 8'h4c == foundId | _GEN_3152; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3668 = 8'h4d == foundId | _GEN_3153; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3669 = 8'h4e == foundId | _GEN_3154; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3670 = 8'h4f == foundId | _GEN_3155; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3671 = 8'h50 == foundId | _GEN_3156; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3672 = 8'h51 == foundId | _GEN_3157; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3673 = 8'h52 == foundId | _GEN_3158; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3674 = 8'h53 == foundId | _GEN_3159; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3675 = 8'h54 == foundId | _GEN_3160; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3676 = 8'h55 == foundId | _GEN_3161; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3677 = 8'h56 == foundId | _GEN_3162; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3678 = 8'h57 == foundId | _GEN_3163; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3679 = 8'h58 == foundId | _GEN_3164; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3680 = 8'h59 == foundId | _GEN_3165; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3681 = 8'h5a == foundId | _GEN_3166; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3682 = 8'h5b == foundId | _GEN_3167; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3683 = 8'h5c == foundId | _GEN_3168; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3684 = 8'h5d == foundId | _GEN_3169; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3685 = 8'h5e == foundId | _GEN_3170; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3686 = 8'h5f == foundId | _GEN_3171; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3687 = 8'h60 == foundId | _GEN_3172; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3688 = 8'h61 == foundId | _GEN_3173; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3689 = 8'h62 == foundId | _GEN_3174; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3690 = 8'h63 == foundId | _GEN_3175; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3691 = 8'h64 == foundId | _GEN_3176; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3692 = 8'h65 == foundId | _GEN_3177; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3693 = 8'h66 == foundId | _GEN_3178; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3694 = 8'h67 == foundId | _GEN_3179; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3695 = 8'h68 == foundId | _GEN_3180; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3696 = 8'h69 == foundId | _GEN_3181; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3697 = 8'h6a == foundId | _GEN_3182; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3698 = 8'h6b == foundId | _GEN_3183; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3699 = 8'h6c == foundId | _GEN_3184; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3700 = 8'h6d == foundId | _GEN_3185; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3701 = 8'h6e == foundId | _GEN_3186; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3702 = 8'h6f == foundId | _GEN_3187; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3703 = 8'h70 == foundId | _GEN_3188; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3704 = 8'h71 == foundId | _GEN_3189; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3705 = 8'h72 == foundId | _GEN_3190; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3706 = 8'h73 == foundId | _GEN_3191; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3707 = 8'h74 == foundId | _GEN_3192; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3708 = 8'h75 == foundId | _GEN_3193; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3709 = 8'h76 == foundId | _GEN_3194; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3710 = 8'h77 == foundId | _GEN_3195; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3711 = 8'h78 == foundId | _GEN_3196; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3712 = 8'h79 == foundId | _GEN_3197; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3713 = 8'h7a == foundId | _GEN_3198; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3714 = 8'h7b == foundId | _GEN_3199; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3715 = 8'h7c == foundId | _GEN_3200; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3716 = 8'h7d == foundId | _GEN_3201; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3717 = 8'h7e == foundId | _GEN_3202; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3718 = 8'h7f == foundId | _GEN_3203; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3719 = 8'h80 == foundId | _GEN_3204; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3720 = 8'h81 == foundId | _GEN_3205; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3721 = 8'h82 == foundId | _GEN_3206; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3722 = 8'h83 == foundId | _GEN_3207; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3723 = 8'h84 == foundId | _GEN_3208; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3724 = 8'h85 == foundId | _GEN_3209; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3725 = 8'h86 == foundId | _GEN_3210; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3726 = 8'h87 == foundId | _GEN_3211; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3727 = 8'h88 == foundId | _GEN_3212; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3728 = 8'h89 == foundId | _GEN_3213; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3729 = 8'h8a == foundId | _GEN_3214; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3730 = 8'h8b == foundId | _GEN_3215; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3731 = 8'h8c == foundId | _GEN_3216; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3732 = 8'h8d == foundId | _GEN_3217; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3733 = 8'h8e == foundId | _GEN_3218; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3734 = 8'h8f == foundId | _GEN_3219; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3735 = 8'h90 == foundId | _GEN_3220; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3736 = 8'h91 == foundId | _GEN_3221; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3737 = 8'h92 == foundId | _GEN_3222; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3738 = 8'h93 == foundId | _GEN_3223; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3739 = 8'h94 == foundId | _GEN_3224; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3740 = 8'h95 == foundId | _GEN_3225; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3741 = 8'h96 == foundId | _GEN_3226; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3742 = 8'h97 == foundId | _GEN_3227; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3743 = 8'h98 == foundId | _GEN_3228; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3744 = 8'h99 == foundId | _GEN_3229; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3745 = 8'h9a == foundId | _GEN_3230; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3746 = 8'h9b == foundId | _GEN_3231; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3747 = 8'h9c == foundId | _GEN_3232; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3748 = 8'h9d == foundId | _GEN_3233; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3749 = 8'h9e == foundId | _GEN_3234; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3750 = 8'h9f == foundId | _GEN_3235; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3751 = 8'ha0 == foundId | _GEN_3236; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3752 = 8'ha1 == foundId | _GEN_3237; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3753 = 8'ha2 == foundId | _GEN_3238; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3754 = 8'ha3 == foundId | _GEN_3239; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3755 = 8'ha4 == foundId | _GEN_3240; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3756 = 8'ha5 == foundId | _GEN_3241; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3757 = 8'ha6 == foundId | _GEN_3242; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3758 = 8'ha7 == foundId | _GEN_3243; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3759 = 8'ha8 == foundId | _GEN_3244; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3760 = 8'ha9 == foundId | _GEN_3245; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3761 = 8'haa == foundId | _GEN_3246; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3762 = 8'hab == foundId | _GEN_3247; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3763 = 8'hac == foundId | _GEN_3248; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3764 = 8'had == foundId | _GEN_3249; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3765 = 8'hae == foundId | _GEN_3250; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3766 = 8'haf == foundId | _GEN_3251; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3767 = 8'hb0 == foundId | _GEN_3252; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3768 = 8'hb1 == foundId | _GEN_3253; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3769 = 8'hb2 == foundId | _GEN_3254; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3770 = 8'hb3 == foundId | _GEN_3255; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3771 = 8'hb4 == foundId | _GEN_3256; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3772 = 8'hb5 == foundId | _GEN_3257; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3773 = 8'hb6 == foundId | _GEN_3258; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3774 = 8'hb7 == foundId | _GEN_3259; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3775 = 8'hb8 == foundId | _GEN_3260; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3776 = 8'hb9 == foundId | _GEN_3261; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3777 = 8'hba == foundId | _GEN_3262; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3778 = 8'hbb == foundId | _GEN_3263; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3779 = 8'hbc == foundId | _GEN_3264; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3780 = 8'hbd == foundId | _GEN_3265; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3781 = 8'hbe == foundId | _GEN_3266; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3782 = 8'hbf == foundId | _GEN_3267; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3783 = 8'hc0 == foundId | _GEN_3268; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3784 = 8'hc1 == foundId | _GEN_3269; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3785 = 8'hc2 == foundId | _GEN_3270; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3786 = 8'hc3 == foundId | _GEN_3271; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3787 = 8'hc4 == foundId | _GEN_3272; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3788 = 8'hc5 == foundId | _GEN_3273; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3789 = 8'hc6 == foundId | _GEN_3274; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3790 = 8'hc7 == foundId | _GEN_3275; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3791 = 8'hc8 == foundId | _GEN_3276; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3792 = 8'hc9 == foundId | _GEN_3277; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3793 = 8'hca == foundId | _GEN_3278; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3794 = 8'hcb == foundId | _GEN_3279; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3795 = 8'hcc == foundId | _GEN_3280; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3796 = 8'hcd == foundId | _GEN_3281; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3797 = 8'hce == foundId | _GEN_3282; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3798 = 8'hcf == foundId | _GEN_3283; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3799 = 8'hd0 == foundId | _GEN_3284; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3800 = 8'hd1 == foundId | _GEN_3285; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3801 = 8'hd2 == foundId | _GEN_3286; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3802 = 8'hd3 == foundId | _GEN_3287; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3803 = 8'hd4 == foundId | _GEN_3288; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3804 = 8'hd5 == foundId | _GEN_3289; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3805 = 8'hd6 == foundId | _GEN_3290; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3806 = 8'hd7 == foundId | _GEN_3291; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3807 = 8'hd8 == foundId | _GEN_3292; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3808 = 8'hd9 == foundId | _GEN_3293; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3809 = 8'hda == foundId | _GEN_3294; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3810 = 8'hdb == foundId | _GEN_3295; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3811 = 8'hdc == foundId | _GEN_3296; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3812 = 8'hdd == foundId | _GEN_3297; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3813 = 8'hde == foundId | _GEN_3298; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3814 = 8'hdf == foundId | _GEN_3299; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3815 = 8'he0 == foundId | _GEN_3300; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3816 = 8'he1 == foundId | _GEN_3301; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3817 = 8'he2 == foundId | _GEN_3302; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3818 = 8'he3 == foundId | _GEN_3303; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3819 = 8'he4 == foundId | _GEN_3304; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3820 = 8'he5 == foundId | _GEN_3305; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3821 = 8'he6 == foundId | _GEN_3306; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3822 = 8'he7 == foundId | _GEN_3307; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3823 = 8'he8 == foundId | _GEN_3308; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3824 = 8'he9 == foundId | _GEN_3309; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3825 = 8'hea == foundId | _GEN_3310; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3826 = 8'heb == foundId | _GEN_3311; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3827 = 8'hec == foundId | _GEN_3312; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3828 = 8'hed == foundId | _GEN_3313; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3829 = 8'hee == foundId | _GEN_3314; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3830 = 8'hef == foundId | _GEN_3315; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3831 = 8'hf0 == foundId | _GEN_3316; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3832 = 8'hf1 == foundId | _GEN_3317; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3833 = 8'hf2 == foundId | _GEN_3318; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3834 = 8'hf3 == foundId | _GEN_3319; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3835 = 8'hf4 == foundId | _GEN_3320; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3836 = 8'hf5 == foundId | _GEN_3321; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3837 = 8'hf6 == foundId | _GEN_3322; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3838 = 8'hf7 == foundId | _GEN_3323; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3839 = 8'hf8 == foundId | _GEN_3324; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3840 = 8'hf9 == foundId | _GEN_3325; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3841 = 8'hfa == foundId | _GEN_3326; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3842 = 8'hfb == foundId | _GEN_3327; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3843 = 8'hfc == foundId | _GEN_3328; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3844 = 8'hfd == foundId | _GEN_3329; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3845 = 8'hfe == foundId | _GEN_3330; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3846 = 8'hff == foundId | _GEN_3331; // @[L1DCache.scala 509:{20,20}]
- wire _GEN_3847 = _T_1563 & io_dbus_write ? _GEN_3591 : _GEN_3076; // @[L1DCache.scala 508:58]
- wire _GEN_3848 = _T_1563 & io_dbus_write ? _GEN_3592 : _GEN_3077; // @[L1DCache.scala 508:58]
- wire _GEN_3849 = _T_1563 & io_dbus_write ? _GEN_3593 : _GEN_3078; // @[L1DCache.scala 508:58]
- wire _GEN_3850 = _T_1563 & io_dbus_write ? _GEN_3594 : _GEN_3079; // @[L1DCache.scala 508:58]
- wire _GEN_3851 = _T_1563 & io_dbus_write ? _GEN_3595 : _GEN_3080; // @[L1DCache.scala 508:58]
- wire _GEN_3852 = _T_1563 & io_dbus_write ? _GEN_3596 : _GEN_3081; // @[L1DCache.scala 508:58]
- wire _GEN_3853 = _T_1563 & io_dbus_write ? _GEN_3597 : _GEN_3082; // @[L1DCache.scala 508:58]
- wire _GEN_3854 = _T_1563 & io_dbus_write ? _GEN_3598 : _GEN_3083; // @[L1DCache.scala 508:58]
- wire _GEN_3855 = _T_1563 & io_dbus_write ? _GEN_3599 : _GEN_3084; // @[L1DCache.scala 508:58]
- wire _GEN_3856 = _T_1563 & io_dbus_write ? _GEN_3600 : _GEN_3085; // @[L1DCache.scala 508:58]
- wire _GEN_3857 = _T_1563 & io_dbus_write ? _GEN_3601 : _GEN_3086; // @[L1DCache.scala 508:58]
- wire _GEN_3858 = _T_1563 & io_dbus_write ? _GEN_3602 : _GEN_3087; // @[L1DCache.scala 508:58]
- wire _GEN_3859 = _T_1563 & io_dbus_write ? _GEN_3603 : _GEN_3088; // @[L1DCache.scala 508:58]
- wire _GEN_3860 = _T_1563 & io_dbus_write ? _GEN_3604 : _GEN_3089; // @[L1DCache.scala 508:58]
- wire _GEN_3861 = _T_1563 & io_dbus_write ? _GEN_3605 : _GEN_3090; // @[L1DCache.scala 508:58]
- wire _GEN_3862 = _T_1563 & io_dbus_write ? _GEN_3606 : _GEN_3091; // @[L1DCache.scala 508:58]
- wire _GEN_3863 = _T_1563 & io_dbus_write ? _GEN_3607 : _GEN_3092; // @[L1DCache.scala 508:58]
- wire _GEN_3864 = _T_1563 & io_dbus_write ? _GEN_3608 : _GEN_3093; // @[L1DCache.scala 508:58]
- wire _GEN_3865 = _T_1563 & io_dbus_write ? _GEN_3609 : _GEN_3094; // @[L1DCache.scala 508:58]
- wire _GEN_3866 = _T_1563 & io_dbus_write ? _GEN_3610 : _GEN_3095; // @[L1DCache.scala 508:58]
- wire _GEN_3867 = _T_1563 & io_dbus_write ? _GEN_3611 : _GEN_3096; // @[L1DCache.scala 508:58]
- wire _GEN_3868 = _T_1563 & io_dbus_write ? _GEN_3612 : _GEN_3097; // @[L1DCache.scala 508:58]
- wire _GEN_3869 = _T_1563 & io_dbus_write ? _GEN_3613 : _GEN_3098; // @[L1DCache.scala 508:58]
- wire _GEN_3870 = _T_1563 & io_dbus_write ? _GEN_3614 : _GEN_3099; // @[L1DCache.scala 508:58]
- wire _GEN_3871 = _T_1563 & io_dbus_write ? _GEN_3615 : _GEN_3100; // @[L1DCache.scala 508:58]
- wire _GEN_3872 = _T_1563 & io_dbus_write ? _GEN_3616 : _GEN_3101; // @[L1DCache.scala 508:58]
- wire _GEN_3873 = _T_1563 & io_dbus_write ? _GEN_3617 : _GEN_3102; // @[L1DCache.scala 508:58]
- wire _GEN_3874 = _T_1563 & io_dbus_write ? _GEN_3618 : _GEN_3103; // @[L1DCache.scala 508:58]
- wire _GEN_3875 = _T_1563 & io_dbus_write ? _GEN_3619 : _GEN_3104; // @[L1DCache.scala 508:58]
- wire _GEN_3876 = _T_1563 & io_dbus_write ? _GEN_3620 : _GEN_3105; // @[L1DCache.scala 508:58]
- wire _GEN_3877 = _T_1563 & io_dbus_write ? _GEN_3621 : _GEN_3106; // @[L1DCache.scala 508:58]
- wire _GEN_3878 = _T_1563 & io_dbus_write ? _GEN_3622 : _GEN_3107; // @[L1DCache.scala 508:58]
- wire _GEN_3879 = _T_1563 & io_dbus_write ? _GEN_3623 : _GEN_3108; // @[L1DCache.scala 508:58]
- wire _GEN_3880 = _T_1563 & io_dbus_write ? _GEN_3624 : _GEN_3109; // @[L1DCache.scala 508:58]
- wire _GEN_3881 = _T_1563 & io_dbus_write ? _GEN_3625 : _GEN_3110; // @[L1DCache.scala 508:58]
- wire _GEN_3882 = _T_1563 & io_dbus_write ? _GEN_3626 : _GEN_3111; // @[L1DCache.scala 508:58]
- wire _GEN_3883 = _T_1563 & io_dbus_write ? _GEN_3627 : _GEN_3112; // @[L1DCache.scala 508:58]
- wire _GEN_3884 = _T_1563 & io_dbus_write ? _GEN_3628 : _GEN_3113; // @[L1DCache.scala 508:58]
- wire _GEN_3885 = _T_1563 & io_dbus_write ? _GEN_3629 : _GEN_3114; // @[L1DCache.scala 508:58]
- wire _GEN_3886 = _T_1563 & io_dbus_write ? _GEN_3630 : _GEN_3115; // @[L1DCache.scala 508:58]
- wire _GEN_3887 = _T_1563 & io_dbus_write ? _GEN_3631 : _GEN_3116; // @[L1DCache.scala 508:58]
- wire _GEN_3888 = _T_1563 & io_dbus_write ? _GEN_3632 : _GEN_3117; // @[L1DCache.scala 508:58]
- wire _GEN_3889 = _T_1563 & io_dbus_write ? _GEN_3633 : _GEN_3118; // @[L1DCache.scala 508:58]
- wire _GEN_3890 = _T_1563 & io_dbus_write ? _GEN_3634 : _GEN_3119; // @[L1DCache.scala 508:58]
- wire _GEN_3891 = _T_1563 & io_dbus_write ? _GEN_3635 : _GEN_3120; // @[L1DCache.scala 508:58]
- wire _GEN_3892 = _T_1563 & io_dbus_write ? _GEN_3636 : _GEN_3121; // @[L1DCache.scala 508:58]
- wire _GEN_3893 = _T_1563 & io_dbus_write ? _GEN_3637 : _GEN_3122; // @[L1DCache.scala 508:58]
- wire _GEN_3894 = _T_1563 & io_dbus_write ? _GEN_3638 : _GEN_3123; // @[L1DCache.scala 508:58]
- wire _GEN_3895 = _T_1563 & io_dbus_write ? _GEN_3639 : _GEN_3124; // @[L1DCache.scala 508:58]
- wire _GEN_3896 = _T_1563 & io_dbus_write ? _GEN_3640 : _GEN_3125; // @[L1DCache.scala 508:58]
- wire _GEN_3897 = _T_1563 & io_dbus_write ? _GEN_3641 : _GEN_3126; // @[L1DCache.scala 508:58]
- wire _GEN_3898 = _T_1563 & io_dbus_write ? _GEN_3642 : _GEN_3127; // @[L1DCache.scala 508:58]
- wire _GEN_3899 = _T_1563 & io_dbus_write ? _GEN_3643 : _GEN_3128; // @[L1DCache.scala 508:58]
- wire _GEN_3900 = _T_1563 & io_dbus_write ? _GEN_3644 : _GEN_3129; // @[L1DCache.scala 508:58]
- wire _GEN_3901 = _T_1563 & io_dbus_write ? _GEN_3645 : _GEN_3130; // @[L1DCache.scala 508:58]
- wire _GEN_3902 = _T_1563 & io_dbus_write ? _GEN_3646 : _GEN_3131; // @[L1DCache.scala 508:58]
- wire _GEN_3903 = _T_1563 & io_dbus_write ? _GEN_3647 : _GEN_3132; // @[L1DCache.scala 508:58]
- wire _GEN_3904 = _T_1563 & io_dbus_write ? _GEN_3648 : _GEN_3133; // @[L1DCache.scala 508:58]
- wire _GEN_3905 = _T_1563 & io_dbus_write ? _GEN_3649 : _GEN_3134; // @[L1DCache.scala 508:58]
- wire _GEN_3906 = _T_1563 & io_dbus_write ? _GEN_3650 : _GEN_3135; // @[L1DCache.scala 508:58]
- wire _GEN_3907 = _T_1563 & io_dbus_write ? _GEN_3651 : _GEN_3136; // @[L1DCache.scala 508:58]
- wire _GEN_3908 = _T_1563 & io_dbus_write ? _GEN_3652 : _GEN_3137; // @[L1DCache.scala 508:58]
- wire _GEN_3909 = _T_1563 & io_dbus_write ? _GEN_3653 : _GEN_3138; // @[L1DCache.scala 508:58]
- wire _GEN_3910 = _T_1563 & io_dbus_write ? _GEN_3654 : _GEN_3139; // @[L1DCache.scala 508:58]
- wire _GEN_3911 = _T_1563 & io_dbus_write ? _GEN_3655 : _GEN_3140; // @[L1DCache.scala 508:58]
- wire _GEN_3912 = _T_1563 & io_dbus_write ? _GEN_3656 : _GEN_3141; // @[L1DCache.scala 508:58]
- wire _GEN_3913 = _T_1563 & io_dbus_write ? _GEN_3657 : _GEN_3142; // @[L1DCache.scala 508:58]
- wire _GEN_3914 = _T_1563 & io_dbus_write ? _GEN_3658 : _GEN_3143; // @[L1DCache.scala 508:58]
- wire _GEN_3915 = _T_1563 & io_dbus_write ? _GEN_3659 : _GEN_3144; // @[L1DCache.scala 508:58]
- wire _GEN_3916 = _T_1563 & io_dbus_write ? _GEN_3660 : _GEN_3145; // @[L1DCache.scala 508:58]
- wire _GEN_3917 = _T_1563 & io_dbus_write ? _GEN_3661 : _GEN_3146; // @[L1DCache.scala 508:58]
- wire _GEN_3918 = _T_1563 & io_dbus_write ? _GEN_3662 : _GEN_3147; // @[L1DCache.scala 508:58]
- wire _GEN_3919 = _T_1563 & io_dbus_write ? _GEN_3663 : _GEN_3148; // @[L1DCache.scala 508:58]
- wire _GEN_3920 = _T_1563 & io_dbus_write ? _GEN_3664 : _GEN_3149; // @[L1DCache.scala 508:58]
- wire _GEN_3921 = _T_1563 & io_dbus_write ? _GEN_3665 : _GEN_3150; // @[L1DCache.scala 508:58]
- wire _GEN_3922 = _T_1563 & io_dbus_write ? _GEN_3666 : _GEN_3151; // @[L1DCache.scala 508:58]
- wire _GEN_3923 = _T_1563 & io_dbus_write ? _GEN_3667 : _GEN_3152; // @[L1DCache.scala 508:58]
- wire _GEN_3924 = _T_1563 & io_dbus_write ? _GEN_3668 : _GEN_3153; // @[L1DCache.scala 508:58]
- wire _GEN_3925 = _T_1563 & io_dbus_write ? _GEN_3669 : _GEN_3154; // @[L1DCache.scala 508:58]
- wire _GEN_3926 = _T_1563 & io_dbus_write ? _GEN_3670 : _GEN_3155; // @[L1DCache.scala 508:58]
- wire _GEN_3927 = _T_1563 & io_dbus_write ? _GEN_3671 : _GEN_3156; // @[L1DCache.scala 508:58]
- wire _GEN_3928 = _T_1563 & io_dbus_write ? _GEN_3672 : _GEN_3157; // @[L1DCache.scala 508:58]
- wire _GEN_3929 = _T_1563 & io_dbus_write ? _GEN_3673 : _GEN_3158; // @[L1DCache.scala 508:58]
- wire _GEN_3930 = _T_1563 & io_dbus_write ? _GEN_3674 : _GEN_3159; // @[L1DCache.scala 508:58]
- wire _GEN_3931 = _T_1563 & io_dbus_write ? _GEN_3675 : _GEN_3160; // @[L1DCache.scala 508:58]
- wire _GEN_3932 = _T_1563 & io_dbus_write ? _GEN_3676 : _GEN_3161; // @[L1DCache.scala 508:58]
- wire _GEN_3933 = _T_1563 & io_dbus_write ? _GEN_3677 : _GEN_3162; // @[L1DCache.scala 508:58]
- wire _GEN_3934 = _T_1563 & io_dbus_write ? _GEN_3678 : _GEN_3163; // @[L1DCache.scala 508:58]
- wire _GEN_3935 = _T_1563 & io_dbus_write ? _GEN_3679 : _GEN_3164; // @[L1DCache.scala 508:58]
- wire _GEN_3936 = _T_1563 & io_dbus_write ? _GEN_3680 : _GEN_3165; // @[L1DCache.scala 508:58]
- wire _GEN_3937 = _T_1563 & io_dbus_write ? _GEN_3681 : _GEN_3166; // @[L1DCache.scala 508:58]
- wire _GEN_3938 = _T_1563 & io_dbus_write ? _GEN_3682 : _GEN_3167; // @[L1DCache.scala 508:58]
- wire _GEN_3939 = _T_1563 & io_dbus_write ? _GEN_3683 : _GEN_3168; // @[L1DCache.scala 508:58]
- wire _GEN_3940 = _T_1563 & io_dbus_write ? _GEN_3684 : _GEN_3169; // @[L1DCache.scala 508:58]
- wire _GEN_3941 = _T_1563 & io_dbus_write ? _GEN_3685 : _GEN_3170; // @[L1DCache.scala 508:58]
- wire _GEN_3942 = _T_1563 & io_dbus_write ? _GEN_3686 : _GEN_3171; // @[L1DCache.scala 508:58]
- wire _GEN_3943 = _T_1563 & io_dbus_write ? _GEN_3687 : _GEN_3172; // @[L1DCache.scala 508:58]
- wire _GEN_3944 = _T_1563 & io_dbus_write ? _GEN_3688 : _GEN_3173; // @[L1DCache.scala 508:58]
- wire _GEN_3945 = _T_1563 & io_dbus_write ? _GEN_3689 : _GEN_3174; // @[L1DCache.scala 508:58]
- wire _GEN_3946 = _T_1563 & io_dbus_write ? _GEN_3690 : _GEN_3175; // @[L1DCache.scala 508:58]
- wire _GEN_3947 = _T_1563 & io_dbus_write ? _GEN_3691 : _GEN_3176; // @[L1DCache.scala 508:58]
- wire _GEN_3948 = _T_1563 & io_dbus_write ? _GEN_3692 : _GEN_3177; // @[L1DCache.scala 508:58]
- wire _GEN_3949 = _T_1563 & io_dbus_write ? _GEN_3693 : _GEN_3178; // @[L1DCache.scala 508:58]
- wire _GEN_3950 = _T_1563 & io_dbus_write ? _GEN_3694 : _GEN_3179; // @[L1DCache.scala 508:58]
- wire _GEN_3951 = _T_1563 & io_dbus_write ? _GEN_3695 : _GEN_3180; // @[L1DCache.scala 508:58]
- wire _GEN_3952 = _T_1563 & io_dbus_write ? _GEN_3696 : _GEN_3181; // @[L1DCache.scala 508:58]
- wire _GEN_3953 = _T_1563 & io_dbus_write ? _GEN_3697 : _GEN_3182; // @[L1DCache.scala 508:58]
- wire _GEN_3954 = _T_1563 & io_dbus_write ? _GEN_3698 : _GEN_3183; // @[L1DCache.scala 508:58]
- wire _GEN_3955 = _T_1563 & io_dbus_write ? _GEN_3699 : _GEN_3184; // @[L1DCache.scala 508:58]
- wire _GEN_3956 = _T_1563 & io_dbus_write ? _GEN_3700 : _GEN_3185; // @[L1DCache.scala 508:58]
- wire _GEN_3957 = _T_1563 & io_dbus_write ? _GEN_3701 : _GEN_3186; // @[L1DCache.scala 508:58]
- wire _GEN_3958 = _T_1563 & io_dbus_write ? _GEN_3702 : _GEN_3187; // @[L1DCache.scala 508:58]
- wire _GEN_3959 = _T_1563 & io_dbus_write ? _GEN_3703 : _GEN_3188; // @[L1DCache.scala 508:58]
- wire _GEN_3960 = _T_1563 & io_dbus_write ? _GEN_3704 : _GEN_3189; // @[L1DCache.scala 508:58]
- wire _GEN_3961 = _T_1563 & io_dbus_write ? _GEN_3705 : _GEN_3190; // @[L1DCache.scala 508:58]
- wire _GEN_3962 = _T_1563 & io_dbus_write ? _GEN_3706 : _GEN_3191; // @[L1DCache.scala 508:58]
- wire _GEN_3963 = _T_1563 & io_dbus_write ? _GEN_3707 : _GEN_3192; // @[L1DCache.scala 508:58]
- wire _GEN_3964 = _T_1563 & io_dbus_write ? _GEN_3708 : _GEN_3193; // @[L1DCache.scala 508:58]
- wire _GEN_3965 = _T_1563 & io_dbus_write ? _GEN_3709 : _GEN_3194; // @[L1DCache.scala 508:58]
- wire _GEN_3966 = _T_1563 & io_dbus_write ? _GEN_3710 : _GEN_3195; // @[L1DCache.scala 508:58]
- wire _GEN_3967 = _T_1563 & io_dbus_write ? _GEN_3711 : _GEN_3196; // @[L1DCache.scala 508:58]
- wire _GEN_3968 = _T_1563 & io_dbus_write ? _GEN_3712 : _GEN_3197; // @[L1DCache.scala 508:58]
- wire _GEN_3969 = _T_1563 & io_dbus_write ? _GEN_3713 : _GEN_3198; // @[L1DCache.scala 508:58]
- wire _GEN_3970 = _T_1563 & io_dbus_write ? _GEN_3714 : _GEN_3199; // @[L1DCache.scala 508:58]
- wire _GEN_3971 = _T_1563 & io_dbus_write ? _GEN_3715 : _GEN_3200; // @[L1DCache.scala 508:58]
- wire _GEN_3972 = _T_1563 & io_dbus_write ? _GEN_3716 : _GEN_3201; // @[L1DCache.scala 508:58]
- wire _GEN_3973 = _T_1563 & io_dbus_write ? _GEN_3717 : _GEN_3202; // @[L1DCache.scala 508:58]
- wire _GEN_3974 = _T_1563 & io_dbus_write ? _GEN_3718 : _GEN_3203; // @[L1DCache.scala 508:58]
- wire _GEN_3975 = _T_1563 & io_dbus_write ? _GEN_3719 : _GEN_3204; // @[L1DCache.scala 508:58]
- wire _GEN_3976 = _T_1563 & io_dbus_write ? _GEN_3720 : _GEN_3205; // @[L1DCache.scala 508:58]
- wire _GEN_3977 = _T_1563 & io_dbus_write ? _GEN_3721 : _GEN_3206; // @[L1DCache.scala 508:58]
- wire _GEN_3978 = _T_1563 & io_dbus_write ? _GEN_3722 : _GEN_3207; // @[L1DCache.scala 508:58]
- wire _GEN_3979 = _T_1563 & io_dbus_write ? _GEN_3723 : _GEN_3208; // @[L1DCache.scala 508:58]
- wire _GEN_3980 = _T_1563 & io_dbus_write ? _GEN_3724 : _GEN_3209; // @[L1DCache.scala 508:58]
- wire _GEN_3981 = _T_1563 & io_dbus_write ? _GEN_3725 : _GEN_3210; // @[L1DCache.scala 508:58]
- wire _GEN_3982 = _T_1563 & io_dbus_write ? _GEN_3726 : _GEN_3211; // @[L1DCache.scala 508:58]
- wire _GEN_3983 = _T_1563 & io_dbus_write ? _GEN_3727 : _GEN_3212; // @[L1DCache.scala 508:58]
- wire _GEN_3984 = _T_1563 & io_dbus_write ? _GEN_3728 : _GEN_3213; // @[L1DCache.scala 508:58]
- wire _GEN_3985 = _T_1563 & io_dbus_write ? _GEN_3729 : _GEN_3214; // @[L1DCache.scala 508:58]
- wire _GEN_3986 = _T_1563 & io_dbus_write ? _GEN_3730 : _GEN_3215; // @[L1DCache.scala 508:58]
- wire _GEN_3987 = _T_1563 & io_dbus_write ? _GEN_3731 : _GEN_3216; // @[L1DCache.scala 508:58]
- wire _GEN_3988 = _T_1563 & io_dbus_write ? _GEN_3732 : _GEN_3217; // @[L1DCache.scala 508:58]
- wire _GEN_3989 = _T_1563 & io_dbus_write ? _GEN_3733 : _GEN_3218; // @[L1DCache.scala 508:58]
- wire _GEN_3990 = _T_1563 & io_dbus_write ? _GEN_3734 : _GEN_3219; // @[L1DCache.scala 508:58]
- wire _GEN_3991 = _T_1563 & io_dbus_write ? _GEN_3735 : _GEN_3220; // @[L1DCache.scala 508:58]
- wire _GEN_3992 = _T_1563 & io_dbus_write ? _GEN_3736 : _GEN_3221; // @[L1DCache.scala 508:58]
- wire _GEN_3993 = _T_1563 & io_dbus_write ? _GEN_3737 : _GEN_3222; // @[L1DCache.scala 508:58]
- wire _GEN_3994 = _T_1563 & io_dbus_write ? _GEN_3738 : _GEN_3223; // @[L1DCache.scala 508:58]
- wire _GEN_3995 = _T_1563 & io_dbus_write ? _GEN_3739 : _GEN_3224; // @[L1DCache.scala 508:58]
- wire _GEN_3996 = _T_1563 & io_dbus_write ? _GEN_3740 : _GEN_3225; // @[L1DCache.scala 508:58]
- wire _GEN_3997 = _T_1563 & io_dbus_write ? _GEN_3741 : _GEN_3226; // @[L1DCache.scala 508:58]
- wire _GEN_3998 = _T_1563 & io_dbus_write ? _GEN_3742 : _GEN_3227; // @[L1DCache.scala 508:58]
- wire _GEN_3999 = _T_1563 & io_dbus_write ? _GEN_3743 : _GEN_3228; // @[L1DCache.scala 508:58]
- wire _GEN_4000 = _T_1563 & io_dbus_write ? _GEN_3744 : _GEN_3229; // @[L1DCache.scala 508:58]
- wire _GEN_4001 = _T_1563 & io_dbus_write ? _GEN_3745 : _GEN_3230; // @[L1DCache.scala 508:58]
- wire _GEN_4002 = _T_1563 & io_dbus_write ? _GEN_3746 : _GEN_3231; // @[L1DCache.scala 508:58]
- wire _GEN_4003 = _T_1563 & io_dbus_write ? _GEN_3747 : _GEN_3232; // @[L1DCache.scala 508:58]
- wire _GEN_4004 = _T_1563 & io_dbus_write ? _GEN_3748 : _GEN_3233; // @[L1DCache.scala 508:58]
- wire _GEN_4005 = _T_1563 & io_dbus_write ? _GEN_3749 : _GEN_3234; // @[L1DCache.scala 508:58]
- wire _GEN_4006 = _T_1563 & io_dbus_write ? _GEN_3750 : _GEN_3235; // @[L1DCache.scala 508:58]
- wire _GEN_4007 = _T_1563 & io_dbus_write ? _GEN_3751 : _GEN_3236; // @[L1DCache.scala 508:58]
- wire _GEN_4008 = _T_1563 & io_dbus_write ? _GEN_3752 : _GEN_3237; // @[L1DCache.scala 508:58]
- wire _GEN_4009 = _T_1563 & io_dbus_write ? _GEN_3753 : _GEN_3238; // @[L1DCache.scala 508:58]
- wire _GEN_4010 = _T_1563 & io_dbus_write ? _GEN_3754 : _GEN_3239; // @[L1DCache.scala 508:58]
- wire _GEN_4011 = _T_1563 & io_dbus_write ? _GEN_3755 : _GEN_3240; // @[L1DCache.scala 508:58]
- wire _GEN_4012 = _T_1563 & io_dbus_write ? _GEN_3756 : _GEN_3241; // @[L1DCache.scala 508:58]
- wire _GEN_4013 = _T_1563 & io_dbus_write ? _GEN_3757 : _GEN_3242; // @[L1DCache.scala 508:58]
- wire _GEN_4014 = _T_1563 & io_dbus_write ? _GEN_3758 : _GEN_3243; // @[L1DCache.scala 508:58]
- wire _GEN_4015 = _T_1563 & io_dbus_write ? _GEN_3759 : _GEN_3244; // @[L1DCache.scala 508:58]
- wire _GEN_4016 = _T_1563 & io_dbus_write ? _GEN_3760 : _GEN_3245; // @[L1DCache.scala 508:58]
- wire _GEN_4017 = _T_1563 & io_dbus_write ? _GEN_3761 : _GEN_3246; // @[L1DCache.scala 508:58]
- wire _GEN_4018 = _T_1563 & io_dbus_write ? _GEN_3762 : _GEN_3247; // @[L1DCache.scala 508:58]
- wire _GEN_4019 = _T_1563 & io_dbus_write ? _GEN_3763 : _GEN_3248; // @[L1DCache.scala 508:58]
- wire _GEN_4020 = _T_1563 & io_dbus_write ? _GEN_3764 : _GEN_3249; // @[L1DCache.scala 508:58]
- wire _GEN_4021 = _T_1563 & io_dbus_write ? _GEN_3765 : _GEN_3250; // @[L1DCache.scala 508:58]
- wire _GEN_4022 = _T_1563 & io_dbus_write ? _GEN_3766 : _GEN_3251; // @[L1DCache.scala 508:58]
- wire _GEN_4023 = _T_1563 & io_dbus_write ? _GEN_3767 : _GEN_3252; // @[L1DCache.scala 508:58]
- wire _GEN_4024 = _T_1563 & io_dbus_write ? _GEN_3768 : _GEN_3253; // @[L1DCache.scala 508:58]
- wire _GEN_4025 = _T_1563 & io_dbus_write ? _GEN_3769 : _GEN_3254; // @[L1DCache.scala 508:58]
- wire _GEN_4026 = _T_1563 & io_dbus_write ? _GEN_3770 : _GEN_3255; // @[L1DCache.scala 508:58]
- wire _GEN_4027 = _T_1563 & io_dbus_write ? _GEN_3771 : _GEN_3256; // @[L1DCache.scala 508:58]
- wire _GEN_4028 = _T_1563 & io_dbus_write ? _GEN_3772 : _GEN_3257; // @[L1DCache.scala 508:58]
- wire _GEN_4029 = _T_1563 & io_dbus_write ? _GEN_3773 : _GEN_3258; // @[L1DCache.scala 508:58]
- wire _GEN_4030 = _T_1563 & io_dbus_write ? _GEN_3774 : _GEN_3259; // @[L1DCache.scala 508:58]
- wire _GEN_4031 = _T_1563 & io_dbus_write ? _GEN_3775 : _GEN_3260; // @[L1DCache.scala 508:58]
- wire _GEN_4032 = _T_1563 & io_dbus_write ? _GEN_3776 : _GEN_3261; // @[L1DCache.scala 508:58]
- wire _GEN_4033 = _T_1563 & io_dbus_write ? _GEN_3777 : _GEN_3262; // @[L1DCache.scala 508:58]
- wire _GEN_4034 = _T_1563 & io_dbus_write ? _GEN_3778 : _GEN_3263; // @[L1DCache.scala 508:58]
- wire _GEN_4035 = _T_1563 & io_dbus_write ? _GEN_3779 : _GEN_3264; // @[L1DCache.scala 508:58]
- wire _GEN_4036 = _T_1563 & io_dbus_write ? _GEN_3780 : _GEN_3265; // @[L1DCache.scala 508:58]
- wire _GEN_4037 = _T_1563 & io_dbus_write ? _GEN_3781 : _GEN_3266; // @[L1DCache.scala 508:58]
- wire _GEN_4038 = _T_1563 & io_dbus_write ? _GEN_3782 : _GEN_3267; // @[L1DCache.scala 508:58]
- wire _GEN_4039 = _T_1563 & io_dbus_write ? _GEN_3783 : _GEN_3268; // @[L1DCache.scala 508:58]
- wire _GEN_4040 = _T_1563 & io_dbus_write ? _GEN_3784 : _GEN_3269; // @[L1DCache.scala 508:58]
- wire _GEN_4041 = _T_1563 & io_dbus_write ? _GEN_3785 : _GEN_3270; // @[L1DCache.scala 508:58]
- wire _GEN_4042 = _T_1563 & io_dbus_write ? _GEN_3786 : _GEN_3271; // @[L1DCache.scala 508:58]
- wire _GEN_4043 = _T_1563 & io_dbus_write ? _GEN_3787 : _GEN_3272; // @[L1DCache.scala 508:58]
- wire _GEN_4044 = _T_1563 & io_dbus_write ? _GEN_3788 : _GEN_3273; // @[L1DCache.scala 508:58]
- wire _GEN_4045 = _T_1563 & io_dbus_write ? _GEN_3789 : _GEN_3274; // @[L1DCache.scala 508:58]
- wire _GEN_4046 = _T_1563 & io_dbus_write ? _GEN_3790 : _GEN_3275; // @[L1DCache.scala 508:58]
- wire _GEN_4047 = _T_1563 & io_dbus_write ? _GEN_3791 : _GEN_3276; // @[L1DCache.scala 508:58]
- wire _GEN_4048 = _T_1563 & io_dbus_write ? _GEN_3792 : _GEN_3277; // @[L1DCache.scala 508:58]
- wire _GEN_4049 = _T_1563 & io_dbus_write ? _GEN_3793 : _GEN_3278; // @[L1DCache.scala 508:58]
- wire _GEN_4050 = _T_1563 & io_dbus_write ? _GEN_3794 : _GEN_3279; // @[L1DCache.scala 508:58]
- wire _GEN_4051 = _T_1563 & io_dbus_write ? _GEN_3795 : _GEN_3280; // @[L1DCache.scala 508:58]
- wire _GEN_4052 = _T_1563 & io_dbus_write ? _GEN_3796 : _GEN_3281; // @[L1DCache.scala 508:58]
- wire _GEN_4053 = _T_1563 & io_dbus_write ? _GEN_3797 : _GEN_3282; // @[L1DCache.scala 508:58]
- wire _GEN_4054 = _T_1563 & io_dbus_write ? _GEN_3798 : _GEN_3283; // @[L1DCache.scala 508:58]
- wire _GEN_4055 = _T_1563 & io_dbus_write ? _GEN_3799 : _GEN_3284; // @[L1DCache.scala 508:58]
- wire _GEN_4056 = _T_1563 & io_dbus_write ? _GEN_3800 : _GEN_3285; // @[L1DCache.scala 508:58]
- wire _GEN_4057 = _T_1563 & io_dbus_write ? _GEN_3801 : _GEN_3286; // @[L1DCache.scala 508:58]
- wire _GEN_4058 = _T_1563 & io_dbus_write ? _GEN_3802 : _GEN_3287; // @[L1DCache.scala 508:58]
- wire _GEN_4059 = _T_1563 & io_dbus_write ? _GEN_3803 : _GEN_3288; // @[L1DCache.scala 508:58]
- wire _GEN_4060 = _T_1563 & io_dbus_write ? _GEN_3804 : _GEN_3289; // @[L1DCache.scala 508:58]
- wire _GEN_4061 = _T_1563 & io_dbus_write ? _GEN_3805 : _GEN_3290; // @[L1DCache.scala 508:58]
- wire _GEN_4062 = _T_1563 & io_dbus_write ? _GEN_3806 : _GEN_3291; // @[L1DCache.scala 508:58]
- wire _GEN_4063 = _T_1563 & io_dbus_write ? _GEN_3807 : _GEN_3292; // @[L1DCache.scala 508:58]
- wire _GEN_4064 = _T_1563 & io_dbus_write ? _GEN_3808 : _GEN_3293; // @[L1DCache.scala 508:58]
- wire _GEN_4065 = _T_1563 & io_dbus_write ? _GEN_3809 : _GEN_3294; // @[L1DCache.scala 508:58]
- wire _GEN_4066 = _T_1563 & io_dbus_write ? _GEN_3810 : _GEN_3295; // @[L1DCache.scala 508:58]
- wire _GEN_4067 = _T_1563 & io_dbus_write ? _GEN_3811 : _GEN_3296; // @[L1DCache.scala 508:58]
- wire _GEN_4068 = _T_1563 & io_dbus_write ? _GEN_3812 : _GEN_3297; // @[L1DCache.scala 508:58]
- wire _GEN_4069 = _T_1563 & io_dbus_write ? _GEN_3813 : _GEN_3298; // @[L1DCache.scala 508:58]
- wire _GEN_4070 = _T_1563 & io_dbus_write ? _GEN_3814 : _GEN_3299; // @[L1DCache.scala 508:58]
- wire _GEN_4071 = _T_1563 & io_dbus_write ? _GEN_3815 : _GEN_3300; // @[L1DCache.scala 508:58]
- wire _GEN_4072 = _T_1563 & io_dbus_write ? _GEN_3816 : _GEN_3301; // @[L1DCache.scala 508:58]
- wire _GEN_4073 = _T_1563 & io_dbus_write ? _GEN_3817 : _GEN_3302; // @[L1DCache.scala 508:58]
- wire _GEN_4074 = _T_1563 & io_dbus_write ? _GEN_3818 : _GEN_3303; // @[L1DCache.scala 508:58]
- wire _GEN_4075 = _T_1563 & io_dbus_write ? _GEN_3819 : _GEN_3304; // @[L1DCache.scala 508:58]
- wire _GEN_4076 = _T_1563 & io_dbus_write ? _GEN_3820 : _GEN_3305; // @[L1DCache.scala 508:58]
- wire _GEN_4077 = _T_1563 & io_dbus_write ? _GEN_3821 : _GEN_3306; // @[L1DCache.scala 508:58]
- wire _GEN_4078 = _T_1563 & io_dbus_write ? _GEN_3822 : _GEN_3307; // @[L1DCache.scala 508:58]
- wire _GEN_4079 = _T_1563 & io_dbus_write ? _GEN_3823 : _GEN_3308; // @[L1DCache.scala 508:58]
- wire _GEN_4080 = _T_1563 & io_dbus_write ? _GEN_3824 : _GEN_3309; // @[L1DCache.scala 508:58]
- wire _GEN_4081 = _T_1563 & io_dbus_write ? _GEN_3825 : _GEN_3310; // @[L1DCache.scala 508:58]
- wire _GEN_4082 = _T_1563 & io_dbus_write ? _GEN_3826 : _GEN_3311; // @[L1DCache.scala 508:58]
- wire _GEN_4083 = _T_1563 & io_dbus_write ? _GEN_3827 : _GEN_3312; // @[L1DCache.scala 508:58]
- wire _GEN_4084 = _T_1563 & io_dbus_write ? _GEN_3828 : _GEN_3313; // @[L1DCache.scala 508:58]
- wire _GEN_4085 = _T_1563 & io_dbus_write ? _GEN_3829 : _GEN_3314; // @[L1DCache.scala 508:58]
- wire _GEN_4086 = _T_1563 & io_dbus_write ? _GEN_3830 : _GEN_3315; // @[L1DCache.scala 508:58]
- wire _GEN_4087 = _T_1563 & io_dbus_write ? _GEN_3831 : _GEN_3316; // @[L1DCache.scala 508:58]
- wire _GEN_4088 = _T_1563 & io_dbus_write ? _GEN_3832 : _GEN_3317; // @[L1DCache.scala 508:58]
- wire _GEN_4089 = _T_1563 & io_dbus_write ? _GEN_3833 : _GEN_3318; // @[L1DCache.scala 508:58]
- wire _GEN_4090 = _T_1563 & io_dbus_write ? _GEN_3834 : _GEN_3319; // @[L1DCache.scala 508:58]
- wire _GEN_4091 = _T_1563 & io_dbus_write ? _GEN_3835 : _GEN_3320; // @[L1DCache.scala 508:58]
- wire _GEN_4092 = _T_1563 & io_dbus_write ? _GEN_3836 : _GEN_3321; // @[L1DCache.scala 508:58]
- wire _GEN_4093 = _T_1563 & io_dbus_write ? _GEN_3837 : _GEN_3322; // @[L1DCache.scala 508:58]
- wire _GEN_4094 = _T_1563 & io_dbus_write ? _GEN_3838 : _GEN_3323; // @[L1DCache.scala 508:58]
- wire _GEN_4095 = _T_1563 & io_dbus_write ? _GEN_3839 : _GEN_3324; // @[L1DCache.scala 508:58]
- wire _GEN_4096 = _T_1563 & io_dbus_write ? _GEN_3840 : _GEN_3325; // @[L1DCache.scala 508:58]
- wire _GEN_4097 = _T_1563 & io_dbus_write ? _GEN_3841 : _GEN_3326; // @[L1DCache.scala 508:58]
- wire _GEN_4098 = _T_1563 & io_dbus_write ? _GEN_3842 : _GEN_3327; // @[L1DCache.scala 508:58]
- wire _GEN_4099 = _T_1563 & io_dbus_write ? _GEN_3843 : _GEN_3328; // @[L1DCache.scala 508:58]
- wire _GEN_4100 = _T_1563 & io_dbus_write ? _GEN_3844 : _GEN_3329; // @[L1DCache.scala 508:58]
- wire _GEN_4101 = _T_1563 & io_dbus_write ? _GEN_3845 : _GEN_3330; // @[L1DCache.scala 508:58]
- wire _GEN_4102 = _T_1563 & io_dbus_write ? _GEN_3846 : _GEN_3331; // @[L1DCache.scala 508:58]
- wire _T_4257 = io_axi_read_data_valid & io_axi_read_data_ready; // @[L1DCache.scala 516:32]
- wire _GEN_4104 = 8'h0 == replaceIdReg | _GEN_2820; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4105 = 8'h1 == replaceIdReg | _GEN_2821; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4106 = 8'h2 == replaceIdReg | _GEN_2822; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4107 = 8'h3 == replaceIdReg | _GEN_2823; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4108 = 8'h4 == replaceIdReg | _GEN_2824; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4109 = 8'h5 == replaceIdReg | _GEN_2825; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4110 = 8'h6 == replaceIdReg | _GEN_2826; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4111 = 8'h7 == replaceIdReg | _GEN_2827; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4112 = 8'h8 == replaceIdReg | _GEN_2828; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4113 = 8'h9 == replaceIdReg | _GEN_2829; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4114 = 8'ha == replaceIdReg | _GEN_2830; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4115 = 8'hb == replaceIdReg | _GEN_2831; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4116 = 8'hc == replaceIdReg | _GEN_2832; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4117 = 8'hd == replaceIdReg | _GEN_2833; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4118 = 8'he == replaceIdReg | _GEN_2834; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4119 = 8'hf == replaceIdReg | _GEN_2835; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4120 = 8'h10 == replaceIdReg | _GEN_2836; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4121 = 8'h11 == replaceIdReg | _GEN_2837; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4122 = 8'h12 == replaceIdReg | _GEN_2838; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4123 = 8'h13 == replaceIdReg | _GEN_2839; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4124 = 8'h14 == replaceIdReg | _GEN_2840; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4125 = 8'h15 == replaceIdReg | _GEN_2841; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4126 = 8'h16 == replaceIdReg | _GEN_2842; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4127 = 8'h17 == replaceIdReg | _GEN_2843; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4128 = 8'h18 == replaceIdReg | _GEN_2844; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4129 = 8'h19 == replaceIdReg | _GEN_2845; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4130 = 8'h1a == replaceIdReg | _GEN_2846; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4131 = 8'h1b == replaceIdReg | _GEN_2847; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4132 = 8'h1c == replaceIdReg | _GEN_2848; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4133 = 8'h1d == replaceIdReg | _GEN_2849; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4134 = 8'h1e == replaceIdReg | _GEN_2850; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4135 = 8'h1f == replaceIdReg | _GEN_2851; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4136 = 8'h20 == replaceIdReg | _GEN_2852; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4137 = 8'h21 == replaceIdReg | _GEN_2853; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4138 = 8'h22 == replaceIdReg | _GEN_2854; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4139 = 8'h23 == replaceIdReg | _GEN_2855; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4140 = 8'h24 == replaceIdReg | _GEN_2856; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4141 = 8'h25 == replaceIdReg | _GEN_2857; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4142 = 8'h26 == replaceIdReg | _GEN_2858; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4143 = 8'h27 == replaceIdReg | _GEN_2859; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4144 = 8'h28 == replaceIdReg | _GEN_2860; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4145 = 8'h29 == replaceIdReg | _GEN_2861; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4146 = 8'h2a == replaceIdReg | _GEN_2862; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4147 = 8'h2b == replaceIdReg | _GEN_2863; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4148 = 8'h2c == replaceIdReg | _GEN_2864; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4149 = 8'h2d == replaceIdReg | _GEN_2865; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4150 = 8'h2e == replaceIdReg | _GEN_2866; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4151 = 8'h2f == replaceIdReg | _GEN_2867; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4152 = 8'h30 == replaceIdReg | _GEN_2868; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4153 = 8'h31 == replaceIdReg | _GEN_2869; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4154 = 8'h32 == replaceIdReg | _GEN_2870; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4155 = 8'h33 == replaceIdReg | _GEN_2871; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4156 = 8'h34 == replaceIdReg | _GEN_2872; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4157 = 8'h35 == replaceIdReg | _GEN_2873; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4158 = 8'h36 == replaceIdReg | _GEN_2874; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4159 = 8'h37 == replaceIdReg | _GEN_2875; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4160 = 8'h38 == replaceIdReg | _GEN_2876; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4161 = 8'h39 == replaceIdReg | _GEN_2877; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4162 = 8'h3a == replaceIdReg | _GEN_2878; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4163 = 8'h3b == replaceIdReg | _GEN_2879; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4164 = 8'h3c == replaceIdReg | _GEN_2880; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4165 = 8'h3d == replaceIdReg | _GEN_2881; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4166 = 8'h3e == replaceIdReg | _GEN_2882; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4167 = 8'h3f == replaceIdReg | _GEN_2883; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4168 = 8'h40 == replaceIdReg | _GEN_2884; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4169 = 8'h41 == replaceIdReg | _GEN_2885; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4170 = 8'h42 == replaceIdReg | _GEN_2886; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4171 = 8'h43 == replaceIdReg | _GEN_2887; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4172 = 8'h44 == replaceIdReg | _GEN_2888; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4173 = 8'h45 == replaceIdReg | _GEN_2889; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4174 = 8'h46 == replaceIdReg | _GEN_2890; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4175 = 8'h47 == replaceIdReg | _GEN_2891; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4176 = 8'h48 == replaceIdReg | _GEN_2892; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4177 = 8'h49 == replaceIdReg | _GEN_2893; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4178 = 8'h4a == replaceIdReg | _GEN_2894; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4179 = 8'h4b == replaceIdReg | _GEN_2895; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4180 = 8'h4c == replaceIdReg | _GEN_2896; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4181 = 8'h4d == replaceIdReg | _GEN_2897; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4182 = 8'h4e == replaceIdReg | _GEN_2898; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4183 = 8'h4f == replaceIdReg | _GEN_2899; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4184 = 8'h50 == replaceIdReg | _GEN_2900; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4185 = 8'h51 == replaceIdReg | _GEN_2901; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4186 = 8'h52 == replaceIdReg | _GEN_2902; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4187 = 8'h53 == replaceIdReg | _GEN_2903; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4188 = 8'h54 == replaceIdReg | _GEN_2904; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4189 = 8'h55 == replaceIdReg | _GEN_2905; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4190 = 8'h56 == replaceIdReg | _GEN_2906; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4191 = 8'h57 == replaceIdReg | _GEN_2907; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4192 = 8'h58 == replaceIdReg | _GEN_2908; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4193 = 8'h59 == replaceIdReg | _GEN_2909; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4194 = 8'h5a == replaceIdReg | _GEN_2910; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4195 = 8'h5b == replaceIdReg | _GEN_2911; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4196 = 8'h5c == replaceIdReg | _GEN_2912; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4197 = 8'h5d == replaceIdReg | _GEN_2913; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4198 = 8'h5e == replaceIdReg | _GEN_2914; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4199 = 8'h5f == replaceIdReg | _GEN_2915; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4200 = 8'h60 == replaceIdReg | _GEN_2916; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4201 = 8'h61 == replaceIdReg | _GEN_2917; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4202 = 8'h62 == replaceIdReg | _GEN_2918; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4203 = 8'h63 == replaceIdReg | _GEN_2919; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4204 = 8'h64 == replaceIdReg | _GEN_2920; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4205 = 8'h65 == replaceIdReg | _GEN_2921; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4206 = 8'h66 == replaceIdReg | _GEN_2922; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4207 = 8'h67 == replaceIdReg | _GEN_2923; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4208 = 8'h68 == replaceIdReg | _GEN_2924; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4209 = 8'h69 == replaceIdReg | _GEN_2925; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4210 = 8'h6a == replaceIdReg | _GEN_2926; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4211 = 8'h6b == replaceIdReg | _GEN_2927; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4212 = 8'h6c == replaceIdReg | _GEN_2928; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4213 = 8'h6d == replaceIdReg | _GEN_2929; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4214 = 8'h6e == replaceIdReg | _GEN_2930; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4215 = 8'h6f == replaceIdReg | _GEN_2931; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4216 = 8'h70 == replaceIdReg | _GEN_2932; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4217 = 8'h71 == replaceIdReg | _GEN_2933; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4218 = 8'h72 == replaceIdReg | _GEN_2934; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4219 = 8'h73 == replaceIdReg | _GEN_2935; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4220 = 8'h74 == replaceIdReg | _GEN_2936; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4221 = 8'h75 == replaceIdReg | _GEN_2937; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4222 = 8'h76 == replaceIdReg | _GEN_2938; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4223 = 8'h77 == replaceIdReg | _GEN_2939; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4224 = 8'h78 == replaceIdReg | _GEN_2940; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4225 = 8'h79 == replaceIdReg | _GEN_2941; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4226 = 8'h7a == replaceIdReg | _GEN_2942; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4227 = 8'h7b == replaceIdReg | _GEN_2943; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4228 = 8'h7c == replaceIdReg | _GEN_2944; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4229 = 8'h7d == replaceIdReg | _GEN_2945; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4230 = 8'h7e == replaceIdReg | _GEN_2946; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4231 = 8'h7f == replaceIdReg | _GEN_2947; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4232 = 8'h80 == replaceIdReg | _GEN_2948; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4233 = 8'h81 == replaceIdReg | _GEN_2949; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4234 = 8'h82 == replaceIdReg | _GEN_2950; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4235 = 8'h83 == replaceIdReg | _GEN_2951; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4236 = 8'h84 == replaceIdReg | _GEN_2952; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4237 = 8'h85 == replaceIdReg | _GEN_2953; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4238 = 8'h86 == replaceIdReg | _GEN_2954; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4239 = 8'h87 == replaceIdReg | _GEN_2955; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4240 = 8'h88 == replaceIdReg | _GEN_2956; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4241 = 8'h89 == replaceIdReg | _GEN_2957; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4242 = 8'h8a == replaceIdReg | _GEN_2958; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4243 = 8'h8b == replaceIdReg | _GEN_2959; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4244 = 8'h8c == replaceIdReg | _GEN_2960; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4245 = 8'h8d == replaceIdReg | _GEN_2961; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4246 = 8'h8e == replaceIdReg | _GEN_2962; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4247 = 8'h8f == replaceIdReg | _GEN_2963; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4248 = 8'h90 == replaceIdReg | _GEN_2964; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4249 = 8'h91 == replaceIdReg | _GEN_2965; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4250 = 8'h92 == replaceIdReg | _GEN_2966; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4251 = 8'h93 == replaceIdReg | _GEN_2967; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4252 = 8'h94 == replaceIdReg | _GEN_2968; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4253 = 8'h95 == replaceIdReg | _GEN_2969; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4254 = 8'h96 == replaceIdReg | _GEN_2970; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4255 = 8'h97 == replaceIdReg | _GEN_2971; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4256 = 8'h98 == replaceIdReg | _GEN_2972; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4257 = 8'h99 == replaceIdReg | _GEN_2973; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4258 = 8'h9a == replaceIdReg | _GEN_2974; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4259 = 8'h9b == replaceIdReg | _GEN_2975; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4260 = 8'h9c == replaceIdReg | _GEN_2976; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4261 = 8'h9d == replaceIdReg | _GEN_2977; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4262 = 8'h9e == replaceIdReg | _GEN_2978; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4263 = 8'h9f == replaceIdReg | _GEN_2979; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4264 = 8'ha0 == replaceIdReg | _GEN_2980; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4265 = 8'ha1 == replaceIdReg | _GEN_2981; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4266 = 8'ha2 == replaceIdReg | _GEN_2982; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4267 = 8'ha3 == replaceIdReg | _GEN_2983; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4268 = 8'ha4 == replaceIdReg | _GEN_2984; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4269 = 8'ha5 == replaceIdReg | _GEN_2985; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4270 = 8'ha6 == replaceIdReg | _GEN_2986; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4271 = 8'ha7 == replaceIdReg | _GEN_2987; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4272 = 8'ha8 == replaceIdReg | _GEN_2988; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4273 = 8'ha9 == replaceIdReg | _GEN_2989; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4274 = 8'haa == replaceIdReg | _GEN_2990; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4275 = 8'hab == replaceIdReg | _GEN_2991; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4276 = 8'hac == replaceIdReg | _GEN_2992; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4277 = 8'had == replaceIdReg | _GEN_2993; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4278 = 8'hae == replaceIdReg | _GEN_2994; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4279 = 8'haf == replaceIdReg | _GEN_2995; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4280 = 8'hb0 == replaceIdReg | _GEN_2996; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4281 = 8'hb1 == replaceIdReg | _GEN_2997; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4282 = 8'hb2 == replaceIdReg | _GEN_2998; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4283 = 8'hb3 == replaceIdReg | _GEN_2999; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4284 = 8'hb4 == replaceIdReg | _GEN_3000; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4285 = 8'hb5 == replaceIdReg | _GEN_3001; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4286 = 8'hb6 == replaceIdReg | _GEN_3002; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4287 = 8'hb7 == replaceIdReg | _GEN_3003; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4288 = 8'hb8 == replaceIdReg | _GEN_3004; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4289 = 8'hb9 == replaceIdReg | _GEN_3005; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4290 = 8'hba == replaceIdReg | _GEN_3006; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4291 = 8'hbb == replaceIdReg | _GEN_3007; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4292 = 8'hbc == replaceIdReg | _GEN_3008; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4293 = 8'hbd == replaceIdReg | _GEN_3009; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4294 = 8'hbe == replaceIdReg | _GEN_3010; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4295 = 8'hbf == replaceIdReg | _GEN_3011; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4296 = 8'hc0 == replaceIdReg | _GEN_3012; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4297 = 8'hc1 == replaceIdReg | _GEN_3013; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4298 = 8'hc2 == replaceIdReg | _GEN_3014; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4299 = 8'hc3 == replaceIdReg | _GEN_3015; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4300 = 8'hc4 == replaceIdReg | _GEN_3016; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4301 = 8'hc5 == replaceIdReg | _GEN_3017; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4302 = 8'hc6 == replaceIdReg | _GEN_3018; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4303 = 8'hc7 == replaceIdReg | _GEN_3019; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4304 = 8'hc8 == replaceIdReg | _GEN_3020; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4305 = 8'hc9 == replaceIdReg | _GEN_3021; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4306 = 8'hca == replaceIdReg | _GEN_3022; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4307 = 8'hcb == replaceIdReg | _GEN_3023; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4308 = 8'hcc == replaceIdReg | _GEN_3024; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4309 = 8'hcd == replaceIdReg | _GEN_3025; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4310 = 8'hce == replaceIdReg | _GEN_3026; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4311 = 8'hcf == replaceIdReg | _GEN_3027; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4312 = 8'hd0 == replaceIdReg | _GEN_3028; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4313 = 8'hd1 == replaceIdReg | _GEN_3029; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4314 = 8'hd2 == replaceIdReg | _GEN_3030; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4315 = 8'hd3 == replaceIdReg | _GEN_3031; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4316 = 8'hd4 == replaceIdReg | _GEN_3032; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4317 = 8'hd5 == replaceIdReg | _GEN_3033; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4318 = 8'hd6 == replaceIdReg | _GEN_3034; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4319 = 8'hd7 == replaceIdReg | _GEN_3035; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4320 = 8'hd8 == replaceIdReg | _GEN_3036; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4321 = 8'hd9 == replaceIdReg | _GEN_3037; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4322 = 8'hda == replaceIdReg | _GEN_3038; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4323 = 8'hdb == replaceIdReg | _GEN_3039; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4324 = 8'hdc == replaceIdReg | _GEN_3040; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4325 = 8'hdd == replaceIdReg | _GEN_3041; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4326 = 8'hde == replaceIdReg | _GEN_3042; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4327 = 8'hdf == replaceIdReg | _GEN_3043; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4328 = 8'he0 == replaceIdReg | _GEN_3044; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4329 = 8'he1 == replaceIdReg | _GEN_3045; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4330 = 8'he2 == replaceIdReg | _GEN_3046; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4331 = 8'he3 == replaceIdReg | _GEN_3047; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4332 = 8'he4 == replaceIdReg | _GEN_3048; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4333 = 8'he5 == replaceIdReg | _GEN_3049; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4334 = 8'he6 == replaceIdReg | _GEN_3050; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4335 = 8'he7 == replaceIdReg | _GEN_3051; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4336 = 8'he8 == replaceIdReg | _GEN_3052; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4337 = 8'he9 == replaceIdReg | _GEN_3053; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4338 = 8'hea == replaceIdReg | _GEN_3054; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4339 = 8'heb == replaceIdReg | _GEN_3055; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4340 = 8'hec == replaceIdReg | _GEN_3056; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4341 = 8'hed == replaceIdReg | _GEN_3057; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4342 = 8'hee == replaceIdReg | _GEN_3058; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4343 = 8'hef == replaceIdReg | _GEN_3059; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4344 = 8'hf0 == replaceIdReg | _GEN_3060; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4345 = 8'hf1 == replaceIdReg | _GEN_3061; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4346 = 8'hf2 == replaceIdReg | _GEN_3062; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4347 = 8'hf3 == replaceIdReg | _GEN_3063; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4348 = 8'hf4 == replaceIdReg | _GEN_3064; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4349 = 8'hf5 == replaceIdReg | _GEN_3065; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4350 = 8'hf6 == replaceIdReg | _GEN_3066; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4351 = 8'hf7 == replaceIdReg | _GEN_3067; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4352 = 8'hf8 == replaceIdReg | _GEN_3068; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4353 = 8'hf9 == replaceIdReg | _GEN_3069; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4354 = 8'hfa == replaceIdReg | _GEN_3070; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4355 = 8'hfb == replaceIdReg | _GEN_3071; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4356 = 8'hfc == replaceIdReg | _GEN_3072; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4357 = 8'hfd == replaceIdReg | _GEN_3073; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4358 = 8'hfe == replaceIdReg | _GEN_3074; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4359 = 8'hff == replaceIdReg | _GEN_3075; // @[L1DCache.scala 517:{25,25}]
- wire _GEN_4360 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4104 : _GEN_2820; // @[L1DCache.scala 516:59]
- wire _GEN_4361 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4105 : _GEN_2821; // @[L1DCache.scala 516:59]
- wire _GEN_4362 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4106 : _GEN_2822; // @[L1DCache.scala 516:59]
- wire _GEN_4363 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4107 : _GEN_2823; // @[L1DCache.scala 516:59]
- wire _GEN_4364 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4108 : _GEN_2824; // @[L1DCache.scala 516:59]
- wire _GEN_4365 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4109 : _GEN_2825; // @[L1DCache.scala 516:59]
- wire _GEN_4366 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4110 : _GEN_2826; // @[L1DCache.scala 516:59]
- wire _GEN_4367 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4111 : _GEN_2827; // @[L1DCache.scala 516:59]
- wire _GEN_4368 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4112 : _GEN_2828; // @[L1DCache.scala 516:59]
- wire _GEN_4369 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4113 : _GEN_2829; // @[L1DCache.scala 516:59]
- wire _GEN_4370 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4114 : _GEN_2830; // @[L1DCache.scala 516:59]
- wire _GEN_4371 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4115 : _GEN_2831; // @[L1DCache.scala 516:59]
- wire _GEN_4372 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4116 : _GEN_2832; // @[L1DCache.scala 516:59]
- wire _GEN_4373 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4117 : _GEN_2833; // @[L1DCache.scala 516:59]
- wire _GEN_4374 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4118 : _GEN_2834; // @[L1DCache.scala 516:59]
- wire _GEN_4375 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4119 : _GEN_2835; // @[L1DCache.scala 516:59]
- wire _GEN_4376 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4120 : _GEN_2836; // @[L1DCache.scala 516:59]
- wire _GEN_4377 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4121 : _GEN_2837; // @[L1DCache.scala 516:59]
- wire _GEN_4378 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4122 : _GEN_2838; // @[L1DCache.scala 516:59]
- wire _GEN_4379 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4123 : _GEN_2839; // @[L1DCache.scala 516:59]
- wire _GEN_4380 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4124 : _GEN_2840; // @[L1DCache.scala 516:59]
- wire _GEN_4381 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4125 : _GEN_2841; // @[L1DCache.scala 516:59]
- wire _GEN_4382 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4126 : _GEN_2842; // @[L1DCache.scala 516:59]
- wire _GEN_4383 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4127 : _GEN_2843; // @[L1DCache.scala 516:59]
- wire _GEN_4384 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4128 : _GEN_2844; // @[L1DCache.scala 516:59]
- wire _GEN_4385 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4129 : _GEN_2845; // @[L1DCache.scala 516:59]
- wire _GEN_4386 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4130 : _GEN_2846; // @[L1DCache.scala 516:59]
- wire _GEN_4387 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4131 : _GEN_2847; // @[L1DCache.scala 516:59]
- wire _GEN_4388 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4132 : _GEN_2848; // @[L1DCache.scala 516:59]
- wire _GEN_4389 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4133 : _GEN_2849; // @[L1DCache.scala 516:59]
- wire _GEN_4390 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4134 : _GEN_2850; // @[L1DCache.scala 516:59]
- wire _GEN_4391 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4135 : _GEN_2851; // @[L1DCache.scala 516:59]
- wire _GEN_4392 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4136 : _GEN_2852; // @[L1DCache.scala 516:59]
- wire _GEN_4393 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4137 : _GEN_2853; // @[L1DCache.scala 516:59]
- wire _GEN_4394 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4138 : _GEN_2854; // @[L1DCache.scala 516:59]
- wire _GEN_4395 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4139 : _GEN_2855; // @[L1DCache.scala 516:59]
- wire _GEN_4396 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4140 : _GEN_2856; // @[L1DCache.scala 516:59]
- wire _GEN_4397 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4141 : _GEN_2857; // @[L1DCache.scala 516:59]
- wire _GEN_4398 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4142 : _GEN_2858; // @[L1DCache.scala 516:59]
- wire _GEN_4399 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4143 : _GEN_2859; // @[L1DCache.scala 516:59]
- wire _GEN_4400 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4144 : _GEN_2860; // @[L1DCache.scala 516:59]
- wire _GEN_4401 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4145 : _GEN_2861; // @[L1DCache.scala 516:59]
- wire _GEN_4402 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4146 : _GEN_2862; // @[L1DCache.scala 516:59]
- wire _GEN_4403 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4147 : _GEN_2863; // @[L1DCache.scala 516:59]
- wire _GEN_4404 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4148 : _GEN_2864; // @[L1DCache.scala 516:59]
- wire _GEN_4405 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4149 : _GEN_2865; // @[L1DCache.scala 516:59]
- wire _GEN_4406 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4150 : _GEN_2866; // @[L1DCache.scala 516:59]
- wire _GEN_4407 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4151 : _GEN_2867; // @[L1DCache.scala 516:59]
- wire _GEN_4408 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4152 : _GEN_2868; // @[L1DCache.scala 516:59]
- wire _GEN_4409 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4153 : _GEN_2869; // @[L1DCache.scala 516:59]
- wire _GEN_4410 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4154 : _GEN_2870; // @[L1DCache.scala 516:59]
- wire _GEN_4411 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4155 : _GEN_2871; // @[L1DCache.scala 516:59]
- wire _GEN_4412 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4156 : _GEN_2872; // @[L1DCache.scala 516:59]
- wire _GEN_4413 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4157 : _GEN_2873; // @[L1DCache.scala 516:59]
- wire _GEN_4414 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4158 : _GEN_2874; // @[L1DCache.scala 516:59]
- wire _GEN_4415 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4159 : _GEN_2875; // @[L1DCache.scala 516:59]
- wire _GEN_4416 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4160 : _GEN_2876; // @[L1DCache.scala 516:59]
- wire _GEN_4417 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4161 : _GEN_2877; // @[L1DCache.scala 516:59]
- wire _GEN_4418 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4162 : _GEN_2878; // @[L1DCache.scala 516:59]
- wire _GEN_4419 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4163 : _GEN_2879; // @[L1DCache.scala 516:59]
- wire _GEN_4420 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4164 : _GEN_2880; // @[L1DCache.scala 516:59]
- wire _GEN_4421 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4165 : _GEN_2881; // @[L1DCache.scala 516:59]
- wire _GEN_4422 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4166 : _GEN_2882; // @[L1DCache.scala 516:59]
- wire _GEN_4423 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4167 : _GEN_2883; // @[L1DCache.scala 516:59]
- wire _GEN_4424 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4168 : _GEN_2884; // @[L1DCache.scala 516:59]
- wire _GEN_4425 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4169 : _GEN_2885; // @[L1DCache.scala 516:59]
- wire _GEN_4426 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4170 : _GEN_2886; // @[L1DCache.scala 516:59]
- wire _GEN_4427 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4171 : _GEN_2887; // @[L1DCache.scala 516:59]
- wire _GEN_4428 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4172 : _GEN_2888; // @[L1DCache.scala 516:59]
- wire _GEN_4429 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4173 : _GEN_2889; // @[L1DCache.scala 516:59]
- wire _GEN_4430 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4174 : _GEN_2890; // @[L1DCache.scala 516:59]
- wire _GEN_4431 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4175 : _GEN_2891; // @[L1DCache.scala 516:59]
- wire _GEN_4432 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4176 : _GEN_2892; // @[L1DCache.scala 516:59]
- wire _GEN_4433 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4177 : _GEN_2893; // @[L1DCache.scala 516:59]
- wire _GEN_4434 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4178 : _GEN_2894; // @[L1DCache.scala 516:59]
- wire _GEN_4435 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4179 : _GEN_2895; // @[L1DCache.scala 516:59]
- wire _GEN_4436 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4180 : _GEN_2896; // @[L1DCache.scala 516:59]
- wire _GEN_4437 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4181 : _GEN_2897; // @[L1DCache.scala 516:59]
- wire _GEN_4438 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4182 : _GEN_2898; // @[L1DCache.scala 516:59]
- wire _GEN_4439 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4183 : _GEN_2899; // @[L1DCache.scala 516:59]
- wire _GEN_4440 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4184 : _GEN_2900; // @[L1DCache.scala 516:59]
- wire _GEN_4441 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4185 : _GEN_2901; // @[L1DCache.scala 516:59]
- wire _GEN_4442 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4186 : _GEN_2902; // @[L1DCache.scala 516:59]
- wire _GEN_4443 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4187 : _GEN_2903; // @[L1DCache.scala 516:59]
- wire _GEN_4444 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4188 : _GEN_2904; // @[L1DCache.scala 516:59]
- wire _GEN_4445 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4189 : _GEN_2905; // @[L1DCache.scala 516:59]
- wire _GEN_4446 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4190 : _GEN_2906; // @[L1DCache.scala 516:59]
- wire _GEN_4447 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4191 : _GEN_2907; // @[L1DCache.scala 516:59]
- wire _GEN_4448 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4192 : _GEN_2908; // @[L1DCache.scala 516:59]
- wire _GEN_4449 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4193 : _GEN_2909; // @[L1DCache.scala 516:59]
- wire _GEN_4450 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4194 : _GEN_2910; // @[L1DCache.scala 516:59]
- wire _GEN_4451 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4195 : _GEN_2911; // @[L1DCache.scala 516:59]
- wire _GEN_4452 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4196 : _GEN_2912; // @[L1DCache.scala 516:59]
- wire _GEN_4453 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4197 : _GEN_2913; // @[L1DCache.scala 516:59]
- wire _GEN_4454 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4198 : _GEN_2914; // @[L1DCache.scala 516:59]
- wire _GEN_4455 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4199 : _GEN_2915; // @[L1DCache.scala 516:59]
- wire _GEN_4456 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4200 : _GEN_2916; // @[L1DCache.scala 516:59]
- wire _GEN_4457 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4201 : _GEN_2917; // @[L1DCache.scala 516:59]
- wire _GEN_4458 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4202 : _GEN_2918; // @[L1DCache.scala 516:59]
- wire _GEN_4459 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4203 : _GEN_2919; // @[L1DCache.scala 516:59]
- wire _GEN_4460 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4204 : _GEN_2920; // @[L1DCache.scala 516:59]
- wire _GEN_4461 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4205 : _GEN_2921; // @[L1DCache.scala 516:59]
- wire _GEN_4462 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4206 : _GEN_2922; // @[L1DCache.scala 516:59]
- wire _GEN_4463 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4207 : _GEN_2923; // @[L1DCache.scala 516:59]
- wire _GEN_4464 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4208 : _GEN_2924; // @[L1DCache.scala 516:59]
- wire _GEN_4465 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4209 : _GEN_2925; // @[L1DCache.scala 516:59]
- wire _GEN_4466 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4210 : _GEN_2926; // @[L1DCache.scala 516:59]
- wire _GEN_4467 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4211 : _GEN_2927; // @[L1DCache.scala 516:59]
- wire _GEN_4468 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4212 : _GEN_2928; // @[L1DCache.scala 516:59]
- wire _GEN_4469 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4213 : _GEN_2929; // @[L1DCache.scala 516:59]
- wire _GEN_4470 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4214 : _GEN_2930; // @[L1DCache.scala 516:59]
- wire _GEN_4471 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4215 : _GEN_2931; // @[L1DCache.scala 516:59]
- wire _GEN_4472 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4216 : _GEN_2932; // @[L1DCache.scala 516:59]
- wire _GEN_4473 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4217 : _GEN_2933; // @[L1DCache.scala 516:59]
- wire _GEN_4474 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4218 : _GEN_2934; // @[L1DCache.scala 516:59]
- wire _GEN_4475 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4219 : _GEN_2935; // @[L1DCache.scala 516:59]
- wire _GEN_4476 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4220 : _GEN_2936; // @[L1DCache.scala 516:59]
- wire _GEN_4477 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4221 : _GEN_2937; // @[L1DCache.scala 516:59]
- wire _GEN_4478 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4222 : _GEN_2938; // @[L1DCache.scala 516:59]
- wire _GEN_4479 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4223 : _GEN_2939; // @[L1DCache.scala 516:59]
- wire _GEN_4480 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4224 : _GEN_2940; // @[L1DCache.scala 516:59]
- wire _GEN_4481 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4225 : _GEN_2941; // @[L1DCache.scala 516:59]
- wire _GEN_4482 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4226 : _GEN_2942; // @[L1DCache.scala 516:59]
- wire _GEN_4483 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4227 : _GEN_2943; // @[L1DCache.scala 516:59]
- wire _GEN_4484 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4228 : _GEN_2944; // @[L1DCache.scala 516:59]
- wire _GEN_4485 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4229 : _GEN_2945; // @[L1DCache.scala 516:59]
- wire _GEN_4486 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4230 : _GEN_2946; // @[L1DCache.scala 516:59]
- wire _GEN_4487 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4231 : _GEN_2947; // @[L1DCache.scala 516:59]
- wire _GEN_4488 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4232 : _GEN_2948; // @[L1DCache.scala 516:59]
- wire _GEN_4489 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4233 : _GEN_2949; // @[L1DCache.scala 516:59]
- wire _GEN_4490 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4234 : _GEN_2950; // @[L1DCache.scala 516:59]
- wire _GEN_4491 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4235 : _GEN_2951; // @[L1DCache.scala 516:59]
- wire _GEN_4492 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4236 : _GEN_2952; // @[L1DCache.scala 516:59]
- wire _GEN_4493 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4237 : _GEN_2953; // @[L1DCache.scala 516:59]
- wire _GEN_4494 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4238 : _GEN_2954; // @[L1DCache.scala 516:59]
- wire _GEN_4495 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4239 : _GEN_2955; // @[L1DCache.scala 516:59]
- wire _GEN_4496 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4240 : _GEN_2956; // @[L1DCache.scala 516:59]
- wire _GEN_4497 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4241 : _GEN_2957; // @[L1DCache.scala 516:59]
- wire _GEN_4498 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4242 : _GEN_2958; // @[L1DCache.scala 516:59]
- wire _GEN_4499 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4243 : _GEN_2959; // @[L1DCache.scala 516:59]
- wire _GEN_4500 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4244 : _GEN_2960; // @[L1DCache.scala 516:59]
- wire _GEN_4501 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4245 : _GEN_2961; // @[L1DCache.scala 516:59]
- wire _GEN_4502 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4246 : _GEN_2962; // @[L1DCache.scala 516:59]
- wire _GEN_4503 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4247 : _GEN_2963; // @[L1DCache.scala 516:59]
- wire _GEN_4504 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4248 : _GEN_2964; // @[L1DCache.scala 516:59]
- wire _GEN_4505 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4249 : _GEN_2965; // @[L1DCache.scala 516:59]
- wire _GEN_4506 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4250 : _GEN_2966; // @[L1DCache.scala 516:59]
- wire _GEN_4507 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4251 : _GEN_2967; // @[L1DCache.scala 516:59]
- wire _GEN_4508 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4252 : _GEN_2968; // @[L1DCache.scala 516:59]
- wire _GEN_4509 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4253 : _GEN_2969; // @[L1DCache.scala 516:59]
- wire _GEN_4510 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4254 : _GEN_2970; // @[L1DCache.scala 516:59]
- wire _GEN_4511 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4255 : _GEN_2971; // @[L1DCache.scala 516:59]
- wire _GEN_4512 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4256 : _GEN_2972; // @[L1DCache.scala 516:59]
- wire _GEN_4513 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4257 : _GEN_2973; // @[L1DCache.scala 516:59]
- wire _GEN_4514 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4258 : _GEN_2974; // @[L1DCache.scala 516:59]
- wire _GEN_4515 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4259 : _GEN_2975; // @[L1DCache.scala 516:59]
- wire _GEN_4516 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4260 : _GEN_2976; // @[L1DCache.scala 516:59]
- wire _GEN_4517 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4261 : _GEN_2977; // @[L1DCache.scala 516:59]
- wire _GEN_4518 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4262 : _GEN_2978; // @[L1DCache.scala 516:59]
- wire _GEN_4519 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4263 : _GEN_2979; // @[L1DCache.scala 516:59]
- wire _GEN_4520 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4264 : _GEN_2980; // @[L1DCache.scala 516:59]
- wire _GEN_4521 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4265 : _GEN_2981; // @[L1DCache.scala 516:59]
- wire _GEN_4522 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4266 : _GEN_2982; // @[L1DCache.scala 516:59]
- wire _GEN_4523 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4267 : _GEN_2983; // @[L1DCache.scala 516:59]
- wire _GEN_4524 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4268 : _GEN_2984; // @[L1DCache.scala 516:59]
- wire _GEN_4525 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4269 : _GEN_2985; // @[L1DCache.scala 516:59]
- wire _GEN_4526 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4270 : _GEN_2986; // @[L1DCache.scala 516:59]
- wire _GEN_4527 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4271 : _GEN_2987; // @[L1DCache.scala 516:59]
- wire _GEN_4528 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4272 : _GEN_2988; // @[L1DCache.scala 516:59]
- wire _GEN_4529 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4273 : _GEN_2989; // @[L1DCache.scala 516:59]
- wire _GEN_4530 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4274 : _GEN_2990; // @[L1DCache.scala 516:59]
- wire _GEN_4531 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4275 : _GEN_2991; // @[L1DCache.scala 516:59]
- wire _GEN_4532 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4276 : _GEN_2992; // @[L1DCache.scala 516:59]
- wire _GEN_4533 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4277 : _GEN_2993; // @[L1DCache.scala 516:59]
- wire _GEN_4534 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4278 : _GEN_2994; // @[L1DCache.scala 516:59]
- wire _GEN_4535 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4279 : _GEN_2995; // @[L1DCache.scala 516:59]
- wire _GEN_4536 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4280 : _GEN_2996; // @[L1DCache.scala 516:59]
- wire _GEN_4537 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4281 : _GEN_2997; // @[L1DCache.scala 516:59]
- wire _GEN_4538 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4282 : _GEN_2998; // @[L1DCache.scala 516:59]
- wire _GEN_4539 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4283 : _GEN_2999; // @[L1DCache.scala 516:59]
- wire _GEN_4540 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4284 : _GEN_3000; // @[L1DCache.scala 516:59]
- wire _GEN_4541 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4285 : _GEN_3001; // @[L1DCache.scala 516:59]
- wire _GEN_4542 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4286 : _GEN_3002; // @[L1DCache.scala 516:59]
- wire _GEN_4543 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4287 : _GEN_3003; // @[L1DCache.scala 516:59]
- wire _GEN_4544 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4288 : _GEN_3004; // @[L1DCache.scala 516:59]
- wire _GEN_4545 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4289 : _GEN_3005; // @[L1DCache.scala 516:59]
- wire _GEN_4546 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4290 : _GEN_3006; // @[L1DCache.scala 516:59]
- wire _GEN_4547 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4291 : _GEN_3007; // @[L1DCache.scala 516:59]
- wire _GEN_4548 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4292 : _GEN_3008; // @[L1DCache.scala 516:59]
- wire _GEN_4549 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4293 : _GEN_3009; // @[L1DCache.scala 516:59]
- wire _GEN_4550 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4294 : _GEN_3010; // @[L1DCache.scala 516:59]
- wire _GEN_4551 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4295 : _GEN_3011; // @[L1DCache.scala 516:59]
- wire _GEN_4552 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4296 : _GEN_3012; // @[L1DCache.scala 516:59]
- wire _GEN_4553 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4297 : _GEN_3013; // @[L1DCache.scala 516:59]
- wire _GEN_4554 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4298 : _GEN_3014; // @[L1DCache.scala 516:59]
- wire _GEN_4555 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4299 : _GEN_3015; // @[L1DCache.scala 516:59]
- wire _GEN_4556 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4300 : _GEN_3016; // @[L1DCache.scala 516:59]
- wire _GEN_4557 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4301 : _GEN_3017; // @[L1DCache.scala 516:59]
- wire _GEN_4558 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4302 : _GEN_3018; // @[L1DCache.scala 516:59]
- wire _GEN_4559 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4303 : _GEN_3019; // @[L1DCache.scala 516:59]
- wire _GEN_4560 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4304 : _GEN_3020; // @[L1DCache.scala 516:59]
- wire _GEN_4561 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4305 : _GEN_3021; // @[L1DCache.scala 516:59]
- wire _GEN_4562 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4306 : _GEN_3022; // @[L1DCache.scala 516:59]
- wire _GEN_4563 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4307 : _GEN_3023; // @[L1DCache.scala 516:59]
- wire _GEN_4564 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4308 : _GEN_3024; // @[L1DCache.scala 516:59]
- wire _GEN_4565 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4309 : _GEN_3025; // @[L1DCache.scala 516:59]
- wire _GEN_4566 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4310 : _GEN_3026; // @[L1DCache.scala 516:59]
- wire _GEN_4567 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4311 : _GEN_3027; // @[L1DCache.scala 516:59]
- wire _GEN_4568 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4312 : _GEN_3028; // @[L1DCache.scala 516:59]
- wire _GEN_4569 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4313 : _GEN_3029; // @[L1DCache.scala 516:59]
- wire _GEN_4570 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4314 : _GEN_3030; // @[L1DCache.scala 516:59]
- wire _GEN_4571 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4315 : _GEN_3031; // @[L1DCache.scala 516:59]
- wire _GEN_4572 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4316 : _GEN_3032; // @[L1DCache.scala 516:59]
- wire _GEN_4573 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4317 : _GEN_3033; // @[L1DCache.scala 516:59]
- wire _GEN_4574 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4318 : _GEN_3034; // @[L1DCache.scala 516:59]
- wire _GEN_4575 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4319 : _GEN_3035; // @[L1DCache.scala 516:59]
- wire _GEN_4576 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4320 : _GEN_3036; // @[L1DCache.scala 516:59]
- wire _GEN_4577 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4321 : _GEN_3037; // @[L1DCache.scala 516:59]
- wire _GEN_4578 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4322 : _GEN_3038; // @[L1DCache.scala 516:59]
- wire _GEN_4579 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4323 : _GEN_3039; // @[L1DCache.scala 516:59]
- wire _GEN_4580 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4324 : _GEN_3040; // @[L1DCache.scala 516:59]
- wire _GEN_4581 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4325 : _GEN_3041; // @[L1DCache.scala 516:59]
- wire _GEN_4582 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4326 : _GEN_3042; // @[L1DCache.scala 516:59]
- wire _GEN_4583 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4327 : _GEN_3043; // @[L1DCache.scala 516:59]
- wire _GEN_4584 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4328 : _GEN_3044; // @[L1DCache.scala 516:59]
- wire _GEN_4585 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4329 : _GEN_3045; // @[L1DCache.scala 516:59]
- wire _GEN_4586 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4330 : _GEN_3046; // @[L1DCache.scala 516:59]
- wire _GEN_4587 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4331 : _GEN_3047; // @[L1DCache.scala 516:59]
- wire _GEN_4588 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4332 : _GEN_3048; // @[L1DCache.scala 516:59]
- wire _GEN_4589 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4333 : _GEN_3049; // @[L1DCache.scala 516:59]
- wire _GEN_4590 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4334 : _GEN_3050; // @[L1DCache.scala 516:59]
- wire _GEN_4591 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4335 : _GEN_3051; // @[L1DCache.scala 516:59]
- wire _GEN_4592 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4336 : _GEN_3052; // @[L1DCache.scala 516:59]
- wire _GEN_4593 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4337 : _GEN_3053; // @[L1DCache.scala 516:59]
- wire _GEN_4594 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4338 : _GEN_3054; // @[L1DCache.scala 516:59]
- wire _GEN_4595 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4339 : _GEN_3055; // @[L1DCache.scala 516:59]
- wire _GEN_4596 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4340 : _GEN_3056; // @[L1DCache.scala 516:59]
- wire _GEN_4597 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4341 : _GEN_3057; // @[L1DCache.scala 516:59]
- wire _GEN_4598 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4342 : _GEN_3058; // @[L1DCache.scala 516:59]
- wire _GEN_4599 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4343 : _GEN_3059; // @[L1DCache.scala 516:59]
- wire _GEN_4600 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4344 : _GEN_3060; // @[L1DCache.scala 516:59]
- wire _GEN_4601 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4345 : _GEN_3061; // @[L1DCache.scala 516:59]
- wire _GEN_4602 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4346 : _GEN_3062; // @[L1DCache.scala 516:59]
- wire _GEN_4603 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4347 : _GEN_3063; // @[L1DCache.scala 516:59]
- wire _GEN_4604 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4348 : _GEN_3064; // @[L1DCache.scala 516:59]
- wire _GEN_4605 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4349 : _GEN_3065; // @[L1DCache.scala 516:59]
- wire _GEN_4606 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4350 : _GEN_3066; // @[L1DCache.scala 516:59]
- wire _GEN_4607 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4351 : _GEN_3067; // @[L1DCache.scala 516:59]
- wire _GEN_4608 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4352 : _GEN_3068; // @[L1DCache.scala 516:59]
- wire _GEN_4609 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4353 : _GEN_3069; // @[L1DCache.scala 516:59]
- wire _GEN_4610 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4354 : _GEN_3070; // @[L1DCache.scala 516:59]
- wire _GEN_4611 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4355 : _GEN_3071; // @[L1DCache.scala 516:59]
- wire _GEN_4612 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4356 : _GEN_3072; // @[L1DCache.scala 516:59]
- wire _GEN_4613 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4357 : _GEN_3073; // @[L1DCache.scala 516:59]
- wire _GEN_4614 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4358 : _GEN_3074; // @[L1DCache.scala 516:59]
- wire _GEN_4615 = io_axi_read_data_valid & io_axi_read_data_ready ? _GEN_4359 : _GEN_3075; // @[L1DCache.scala 516:59]
- wire [7:0] axiwdatabuf_data_0 = mem_rdata[7:0]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_1 = mem_rdata[16:9]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_2 = mem_rdata[25:18]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_3 = mem_rdata[34:27]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_4 = mem_rdata[43:36]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_5 = mem_rdata[52:45]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_6 = mem_rdata[61:54]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_7 = mem_rdata[70:63]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_8 = mem_rdata[79:72]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_9 = mem_rdata[88:81]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_10 = mem_rdata[97:90]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_11 = mem_rdata[106:99]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_12 = mem_rdata[115:108]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_13 = mem_rdata[124:117]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_14 = mem_rdata[133:126]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_15 = mem_rdata[142:135]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_16 = mem_rdata[151:144]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_17 = mem_rdata[160:153]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_18 = mem_rdata[169:162]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_19 = mem_rdata[178:171]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_20 = mem_rdata[187:180]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_21 = mem_rdata[196:189]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_22 = mem_rdata[205:198]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_23 = mem_rdata[214:207]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_24 = mem_rdata[223:216]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_25 = mem_rdata[232:225]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_26 = mem_rdata[241:234]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_27 = mem_rdata[250:243]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_28 = mem_rdata[259:252]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_29 = mem_rdata[268:261]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_30 = mem_rdata[277:270]; // @[L1DCache.scala 296:19]
- wire [7:0] axiwdatabuf_data_31 = mem_rdata[286:279]; // @[L1DCache.scala 296:19]
- wire [63:0] axiwdatabuf_lo_lo = {axiwdatabuf_data_7,axiwdatabuf_data_6,axiwdatabuf_data_5,axiwdatabuf_data_4,
- axiwdatabuf_data_3,axiwdatabuf_data_2,axiwdatabuf_data_1,axiwdatabuf_data_0}; // @[L1DCache.scala 298:10]
- wire [127:0] axiwdatabuf_lo = {axiwdatabuf_data_15,axiwdatabuf_data_14,axiwdatabuf_data_13,axiwdatabuf_data_12,
- axiwdatabuf_data_11,axiwdatabuf_data_10,axiwdatabuf_data_9,axiwdatabuf_data_8,axiwdatabuf_lo_lo}; // @[L1DCache.scala 298:10]
- wire [63:0] axiwdatabuf_hi_lo = {axiwdatabuf_data_23,axiwdatabuf_data_22,axiwdatabuf_data_21,axiwdatabuf_data_20,
- axiwdatabuf_data_19,axiwdatabuf_data_18,axiwdatabuf_data_17,axiwdatabuf_data_16}; // @[L1DCache.scala 298:10]
- wire [127:0] axiwdatabuf_hi = {axiwdatabuf_data_31,axiwdatabuf_data_30,axiwdatabuf_data_29,axiwdatabuf_data_28,
- axiwdatabuf_data_27,axiwdatabuf_data_26,axiwdatabuf_data_25,axiwdatabuf_data_24,axiwdatabuf_hi_lo}; // @[L1DCache.scala 298:10]
- wire [255:0] _axiwdatabuf_T = {axiwdatabuf_data_31,axiwdatabuf_data_30,axiwdatabuf_data_29,axiwdatabuf_data_28,
- axiwdatabuf_data_27,axiwdatabuf_data_26,axiwdatabuf_data_25,axiwdatabuf_data_24,axiwdatabuf_hi_lo,axiwdatabuf_lo}; // @[L1DCache.scala 298:10]
- wire axiwstrbbuf_data_0 = mem_rdata[8]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_1 = mem_rdata[17]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_2 = mem_rdata[26]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_3 = mem_rdata[35]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_4 = mem_rdata[44]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_5 = mem_rdata[53]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_6 = mem_rdata[62]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_7 = mem_rdata[71]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_8 = mem_rdata[80]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_9 = mem_rdata[89]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_10 = mem_rdata[98]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_11 = mem_rdata[107]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_12 = mem_rdata[116]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_13 = mem_rdata[125]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_14 = mem_rdata[134]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_15 = mem_rdata[143]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_16 = mem_rdata[152]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_17 = mem_rdata[161]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_18 = mem_rdata[170]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_19 = mem_rdata[179]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_20 = mem_rdata[188]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_21 = mem_rdata[197]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_22 = mem_rdata[206]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_23 = mem_rdata[215]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_24 = mem_rdata[224]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_25 = mem_rdata[233]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_26 = mem_rdata[242]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_27 = mem_rdata[251]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_28 = mem_rdata[260]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_29 = mem_rdata[269]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_30 = mem_rdata[278]; // @[L1DCache.scala 305:23]
- wire axiwstrbbuf_data_31 = mem_rdata[287]; // @[L1DCache.scala 305:23]
- wire [7:0] axiwstrbbuf_lo_lo = {axiwstrbbuf_data_7,axiwstrbbuf_data_6,axiwstrbbuf_data_5,axiwstrbbuf_data_4,
- axiwstrbbuf_data_3,axiwstrbbuf_data_2,axiwstrbbuf_data_1,axiwstrbbuf_data_0}; // @[L1DCache.scala 307:10]
- wire [15:0] axiwstrbbuf_lo = {axiwstrbbuf_data_15,axiwstrbbuf_data_14,axiwstrbbuf_data_13,axiwstrbbuf_data_12,
- axiwstrbbuf_data_11,axiwstrbbuf_data_10,axiwstrbbuf_data_9,axiwstrbbuf_data_8,axiwstrbbuf_lo_lo}; // @[L1DCache.scala 307:10]
- wire [7:0] axiwstrbbuf_hi_lo = {axiwstrbbuf_data_23,axiwstrbbuf_data_22,axiwstrbbuf_data_21,axiwstrbbuf_data_20,
- axiwstrbbuf_data_19,axiwstrbbuf_data_18,axiwstrbbuf_data_17,axiwstrbbuf_data_16}; // @[L1DCache.scala 307:10]
- wire [31:0] _axiwstrbbuf_T = {axiwstrbbuf_data_31,axiwstrbbuf_data_30,axiwstrbbuf_data_29,axiwstrbbuf_data_28,
- axiwstrbbuf_data_27,axiwstrbbuf_data_26,axiwstrbbuf_data_25,axiwstrbbuf_data_24,axiwstrbbuf_hi_lo,axiwstrbbuf_lo}; // @[L1DCache.scala 307:10]
- wire _GEN_4620 = memwdataEn | axiwaddrvalid; // @[L1DCache.scala 522:21 526:19 478:30]
- wire _GEN_4621 = memwdataEn | axiwdatavalid; // @[L1DCache.scala 522:21 527:19 479:30]
- wire _T_4258 = io_axi_write_addr_valid & io_axi_write_addr_ready; // @[L1DCache.scala 530:33]
- wire _T_4259 = io_axi_write_data_valid & io_axi_write_data_ready; // @[L1DCache.scala 534:33]
- wire _T_4260 = io_axi_write_resp_valid & io_axi_write_resp_ready; // @[L1DCache.scala 538:33]
- wire _T_4267 = ~ractive; // @[L1DCache.scala 558:38]
- reg [8:0] wrespcnt; // @[L1DCache.scala 564:25]
- wire [8:0] _wrespcnt_T_1 = wrespcnt + 9'h1; // @[L1DCache.scala 569:26]
- wire [8:0] _wrespcnt_T_3 = wrespcnt - 9'h1; // @[L1DCache.scala 571:26]
- wire [7:0] flushId_lo_lo_lo_lo_lo = {flush_7,flush_6,flush_5,flush_4,flush_3,flush_2,flush_1,flush_0}; // @[L1DCache.scala 576:27]
- wire [15:0] flushId_lo_lo_lo_lo = {flush_15,flush_14,flush_13,flush_12,flush_11,flush_10,flush_9,flush_8,
- flushId_lo_lo_lo_lo_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_lo_lo_lo_hi_lo = {flush_23,flush_22,flush_21,flush_20,flush_19,flush_18,flush_17,flush_16}; // @[L1DCache.scala 576:27]
- wire [31:0] flushId_lo_lo_lo = {flush_31,flush_30,flush_29,flush_28,flush_27,flush_26,flush_25,flush_24,
- flushId_lo_lo_lo_hi_lo,flushId_lo_lo_lo_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_lo_lo_hi_lo_lo = {flush_39,flush_38,flush_37,flush_36,flush_35,flush_34,flush_33,flush_32}; // @[L1DCache.scala 576:27]
- wire [15:0] flushId_lo_lo_hi_lo = {flush_47,flush_46,flush_45,flush_44,flush_43,flush_42,flush_41,flush_40,
- flushId_lo_lo_hi_lo_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_lo_lo_hi_hi_lo = {flush_55,flush_54,flush_53,flush_52,flush_51,flush_50,flush_49,flush_48}; // @[L1DCache.scala 576:27]
- wire [31:0] flushId_lo_lo_hi = {flush_63,flush_62,flush_61,flush_60,flush_59,flush_58,flush_57,flush_56,
- flushId_lo_lo_hi_hi_lo,flushId_lo_lo_hi_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_lo_hi_lo_lo_lo = {flush_71,flush_70,flush_69,flush_68,flush_67,flush_66,flush_65,flush_64}; // @[L1DCache.scala 576:27]
- wire [15:0] flushId_lo_hi_lo_lo = {flush_79,flush_78,flush_77,flush_76,flush_75,flush_74,flush_73,flush_72,
- flushId_lo_hi_lo_lo_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_lo_hi_lo_hi_lo = {flush_87,flush_86,flush_85,flush_84,flush_83,flush_82,flush_81,flush_80}; // @[L1DCache.scala 576:27]
- wire [31:0] flushId_lo_hi_lo = {flush_95,flush_94,flush_93,flush_92,flush_91,flush_90,flush_89,flush_88,
- flushId_lo_hi_lo_hi_lo,flushId_lo_hi_lo_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_lo_hi_hi_lo_lo = {flush_103,flush_102,flush_101,flush_100,flush_99,flush_98,flush_97,flush_96}; // @[L1DCache.scala 576:27]
- wire [15:0] flushId_lo_hi_hi_lo = {flush_111,flush_110,flush_109,flush_108,flush_107,flush_106,flush_105,flush_104,
- flushId_lo_hi_hi_lo_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_lo_hi_hi_hi_lo = {flush_119,flush_118,flush_117,flush_116,flush_115,flush_114,flush_113,flush_112}; // @[L1DCache.scala 576:27]
- wire [31:0] flushId_lo_hi_hi = {flush_127,flush_126,flush_125,flush_124,flush_123,flush_122,flush_121,flush_120,
- flushId_lo_hi_hi_hi_lo,flushId_lo_hi_hi_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_hi_lo_lo_lo_lo = {flush_135,flush_134,flush_133,flush_132,flush_131,flush_130,flush_129,flush_128}; // @[L1DCache.scala 576:27]
- wire [15:0] flushId_hi_lo_lo_lo = {flush_143,flush_142,flush_141,flush_140,flush_139,flush_138,flush_137,flush_136,
- flushId_hi_lo_lo_lo_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_hi_lo_lo_hi_lo = {flush_151,flush_150,flush_149,flush_148,flush_147,flush_146,flush_145,flush_144}; // @[L1DCache.scala 576:27]
- wire [31:0] flushId_hi_lo_lo = {flush_159,flush_158,flush_157,flush_156,flush_155,flush_154,flush_153,flush_152,
- flushId_hi_lo_lo_hi_lo,flushId_hi_lo_lo_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_hi_lo_hi_lo_lo = {flush_167,flush_166,flush_165,flush_164,flush_163,flush_162,flush_161,flush_160}; // @[L1DCache.scala 576:27]
- wire [15:0] flushId_hi_lo_hi_lo = {flush_175,flush_174,flush_173,flush_172,flush_171,flush_170,flush_169,flush_168,
- flushId_hi_lo_hi_lo_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_hi_lo_hi_hi_lo = {flush_183,flush_182,flush_181,flush_180,flush_179,flush_178,flush_177,flush_176}; // @[L1DCache.scala 576:27]
- wire [31:0] flushId_hi_lo_hi = {flush_191,flush_190,flush_189,flush_188,flush_187,flush_186,flush_185,flush_184,
- flushId_hi_lo_hi_hi_lo,flushId_hi_lo_hi_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_hi_hi_lo_lo_lo = {flush_199,flush_198,flush_197,flush_196,flush_195,flush_194,flush_193,flush_192}; // @[L1DCache.scala 576:27]
- wire [15:0] flushId_hi_hi_lo_lo = {flush_207,flush_206,flush_205,flush_204,flush_203,flush_202,flush_201,flush_200,
- flushId_hi_hi_lo_lo_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_hi_hi_lo_hi_lo = {flush_215,flush_214,flush_213,flush_212,flush_211,flush_210,flush_209,flush_208}; // @[L1DCache.scala 576:27]
- wire [31:0] flushId_hi_hi_lo = {flush_223,flush_222,flush_221,flush_220,flush_219,flush_218,flush_217,flush_216,
- flushId_hi_hi_lo_hi_lo,flushId_hi_hi_lo_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_hi_hi_hi_lo_lo = {flush_231,flush_230,flush_229,flush_228,flush_227,flush_226,flush_225,flush_224}; // @[L1DCache.scala 576:27]
- wire [15:0] flushId_hi_hi_hi_lo = {flush_239,flush_238,flush_237,flush_236,flush_235,flush_234,flush_233,flush_232,
- flushId_hi_hi_hi_lo_lo}; // @[L1DCache.scala 576:27]
- wire [7:0] flushId_hi_hi_hi_hi_lo = {flush_247,flush_246,flush_245,flush_244,flush_243,flush_242,flush_241,flush_240}; // @[L1DCache.scala 576:27]
- wire [31:0] flushId_hi_hi_hi = {flush_255,flush_254,flush_253,flush_252,flush_251,flush_250,flush_249,flush_248,
- flushId_hi_hi_hi_hi_lo,flushId_hi_hi_hi_lo}; // @[L1DCache.scala 576:27]
- wire [255:0] _flushId_T = {flushId_hi_hi_hi,flushId_hi_hi_lo,flushId_hi_lo_hi,flushId_hi_lo_lo,flushId_lo_hi_hi,
- flushId_lo_hi_lo,flushId_lo_lo_hi,flushId_lo_lo_lo}; // @[L1DCache.scala 576:27]
- wire [256:0] _flushId_T_1 = {1'h1,flushId_hi_hi_hi,flushId_hi_hi_lo,flushId_hi_lo_hi,flushId_hi_lo_lo,flushId_lo_hi_hi
- ,flushId_lo_hi_lo,flushId_lo_lo_hi,flushId_lo_lo_lo}; // @[Cat.scala 31:58]
- wire [8:0] _flushId_T_259 = _flushId_T_1[255] ? 9'hff : 9'h100; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_260 = _flushId_T_1[254] ? 9'hfe : _flushId_T_259; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_261 = _flushId_T_1[253] ? 9'hfd : _flushId_T_260; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_262 = _flushId_T_1[252] ? 9'hfc : _flushId_T_261; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_263 = _flushId_T_1[251] ? 9'hfb : _flushId_T_262; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_264 = _flushId_T_1[250] ? 9'hfa : _flushId_T_263; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_265 = _flushId_T_1[249] ? 9'hf9 : _flushId_T_264; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_266 = _flushId_T_1[248] ? 9'hf8 : _flushId_T_265; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_267 = _flushId_T_1[247] ? 9'hf7 : _flushId_T_266; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_268 = _flushId_T_1[246] ? 9'hf6 : _flushId_T_267; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_269 = _flushId_T_1[245] ? 9'hf5 : _flushId_T_268; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_270 = _flushId_T_1[244] ? 9'hf4 : _flushId_T_269; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_271 = _flushId_T_1[243] ? 9'hf3 : _flushId_T_270; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_272 = _flushId_T_1[242] ? 9'hf2 : _flushId_T_271; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_273 = _flushId_T_1[241] ? 9'hf1 : _flushId_T_272; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_274 = _flushId_T_1[240] ? 9'hf0 : _flushId_T_273; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_275 = _flushId_T_1[239] ? 9'hef : _flushId_T_274; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_276 = _flushId_T_1[238] ? 9'hee : _flushId_T_275; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_277 = _flushId_T_1[237] ? 9'hed : _flushId_T_276; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_278 = _flushId_T_1[236] ? 9'hec : _flushId_T_277; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_279 = _flushId_T_1[235] ? 9'heb : _flushId_T_278; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_280 = _flushId_T_1[234] ? 9'hea : _flushId_T_279; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_281 = _flushId_T_1[233] ? 9'he9 : _flushId_T_280; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_282 = _flushId_T_1[232] ? 9'he8 : _flushId_T_281; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_283 = _flushId_T_1[231] ? 9'he7 : _flushId_T_282; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_284 = _flushId_T_1[230] ? 9'he6 : _flushId_T_283; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_285 = _flushId_T_1[229] ? 9'he5 : _flushId_T_284; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_286 = _flushId_T_1[228] ? 9'he4 : _flushId_T_285; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_287 = _flushId_T_1[227] ? 9'he3 : _flushId_T_286; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_288 = _flushId_T_1[226] ? 9'he2 : _flushId_T_287; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_289 = _flushId_T_1[225] ? 9'he1 : _flushId_T_288; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_290 = _flushId_T_1[224] ? 9'he0 : _flushId_T_289; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_291 = _flushId_T_1[223] ? 9'hdf : _flushId_T_290; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_292 = _flushId_T_1[222] ? 9'hde : _flushId_T_291; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_293 = _flushId_T_1[221] ? 9'hdd : _flushId_T_292; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_294 = _flushId_T_1[220] ? 9'hdc : _flushId_T_293; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_295 = _flushId_T_1[219] ? 9'hdb : _flushId_T_294; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_296 = _flushId_T_1[218] ? 9'hda : _flushId_T_295; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_297 = _flushId_T_1[217] ? 9'hd9 : _flushId_T_296; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_298 = _flushId_T_1[216] ? 9'hd8 : _flushId_T_297; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_299 = _flushId_T_1[215] ? 9'hd7 : _flushId_T_298; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_300 = _flushId_T_1[214] ? 9'hd6 : _flushId_T_299; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_301 = _flushId_T_1[213] ? 9'hd5 : _flushId_T_300; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_302 = _flushId_T_1[212] ? 9'hd4 : _flushId_T_301; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_303 = _flushId_T_1[211] ? 9'hd3 : _flushId_T_302; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_304 = _flushId_T_1[210] ? 9'hd2 : _flushId_T_303; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_305 = _flushId_T_1[209] ? 9'hd1 : _flushId_T_304; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_306 = _flushId_T_1[208] ? 9'hd0 : _flushId_T_305; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_307 = _flushId_T_1[207] ? 9'hcf : _flushId_T_306; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_308 = _flushId_T_1[206] ? 9'hce : _flushId_T_307; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_309 = _flushId_T_1[205] ? 9'hcd : _flushId_T_308; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_310 = _flushId_T_1[204] ? 9'hcc : _flushId_T_309; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_311 = _flushId_T_1[203] ? 9'hcb : _flushId_T_310; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_312 = _flushId_T_1[202] ? 9'hca : _flushId_T_311; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_313 = _flushId_T_1[201] ? 9'hc9 : _flushId_T_312; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_314 = _flushId_T_1[200] ? 9'hc8 : _flushId_T_313; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_315 = _flushId_T_1[199] ? 9'hc7 : _flushId_T_314; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_316 = _flushId_T_1[198] ? 9'hc6 : _flushId_T_315; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_317 = _flushId_T_1[197] ? 9'hc5 : _flushId_T_316; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_318 = _flushId_T_1[196] ? 9'hc4 : _flushId_T_317; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_319 = _flushId_T_1[195] ? 9'hc3 : _flushId_T_318; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_320 = _flushId_T_1[194] ? 9'hc2 : _flushId_T_319; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_321 = _flushId_T_1[193] ? 9'hc1 : _flushId_T_320; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_322 = _flushId_T_1[192] ? 9'hc0 : _flushId_T_321; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_323 = _flushId_T_1[191] ? 9'hbf : _flushId_T_322; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_324 = _flushId_T_1[190] ? 9'hbe : _flushId_T_323; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_325 = _flushId_T_1[189] ? 9'hbd : _flushId_T_324; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_326 = _flushId_T_1[188] ? 9'hbc : _flushId_T_325; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_327 = _flushId_T_1[187] ? 9'hbb : _flushId_T_326; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_328 = _flushId_T_1[186] ? 9'hba : _flushId_T_327; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_329 = _flushId_T_1[185] ? 9'hb9 : _flushId_T_328; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_330 = _flushId_T_1[184] ? 9'hb8 : _flushId_T_329; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_331 = _flushId_T_1[183] ? 9'hb7 : _flushId_T_330; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_332 = _flushId_T_1[182] ? 9'hb6 : _flushId_T_331; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_333 = _flushId_T_1[181] ? 9'hb5 : _flushId_T_332; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_334 = _flushId_T_1[180] ? 9'hb4 : _flushId_T_333; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_335 = _flushId_T_1[179] ? 9'hb3 : _flushId_T_334; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_336 = _flushId_T_1[178] ? 9'hb2 : _flushId_T_335; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_337 = _flushId_T_1[177] ? 9'hb1 : _flushId_T_336; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_338 = _flushId_T_1[176] ? 9'hb0 : _flushId_T_337; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_339 = _flushId_T_1[175] ? 9'haf : _flushId_T_338; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_340 = _flushId_T_1[174] ? 9'hae : _flushId_T_339; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_341 = _flushId_T_1[173] ? 9'had : _flushId_T_340; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_342 = _flushId_T_1[172] ? 9'hac : _flushId_T_341; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_343 = _flushId_T_1[171] ? 9'hab : _flushId_T_342; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_344 = _flushId_T_1[170] ? 9'haa : _flushId_T_343; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_345 = _flushId_T_1[169] ? 9'ha9 : _flushId_T_344; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_346 = _flushId_T_1[168] ? 9'ha8 : _flushId_T_345; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_347 = _flushId_T_1[167] ? 9'ha7 : _flushId_T_346; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_348 = _flushId_T_1[166] ? 9'ha6 : _flushId_T_347; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_349 = _flushId_T_1[165] ? 9'ha5 : _flushId_T_348; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_350 = _flushId_T_1[164] ? 9'ha4 : _flushId_T_349; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_351 = _flushId_T_1[163] ? 9'ha3 : _flushId_T_350; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_352 = _flushId_T_1[162] ? 9'ha2 : _flushId_T_351; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_353 = _flushId_T_1[161] ? 9'ha1 : _flushId_T_352; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_354 = _flushId_T_1[160] ? 9'ha0 : _flushId_T_353; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_355 = _flushId_T_1[159] ? 9'h9f : _flushId_T_354; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_356 = _flushId_T_1[158] ? 9'h9e : _flushId_T_355; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_357 = _flushId_T_1[157] ? 9'h9d : _flushId_T_356; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_358 = _flushId_T_1[156] ? 9'h9c : _flushId_T_357; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_359 = _flushId_T_1[155] ? 9'h9b : _flushId_T_358; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_360 = _flushId_T_1[154] ? 9'h9a : _flushId_T_359; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_361 = _flushId_T_1[153] ? 9'h99 : _flushId_T_360; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_362 = _flushId_T_1[152] ? 9'h98 : _flushId_T_361; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_363 = _flushId_T_1[151] ? 9'h97 : _flushId_T_362; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_364 = _flushId_T_1[150] ? 9'h96 : _flushId_T_363; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_365 = _flushId_T_1[149] ? 9'h95 : _flushId_T_364; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_366 = _flushId_T_1[148] ? 9'h94 : _flushId_T_365; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_367 = _flushId_T_1[147] ? 9'h93 : _flushId_T_366; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_368 = _flushId_T_1[146] ? 9'h92 : _flushId_T_367; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_369 = _flushId_T_1[145] ? 9'h91 : _flushId_T_368; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_370 = _flushId_T_1[144] ? 9'h90 : _flushId_T_369; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_371 = _flushId_T_1[143] ? 9'h8f : _flushId_T_370; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_372 = _flushId_T_1[142] ? 9'h8e : _flushId_T_371; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_373 = _flushId_T_1[141] ? 9'h8d : _flushId_T_372; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_374 = _flushId_T_1[140] ? 9'h8c : _flushId_T_373; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_375 = _flushId_T_1[139] ? 9'h8b : _flushId_T_374; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_376 = _flushId_T_1[138] ? 9'h8a : _flushId_T_375; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_377 = _flushId_T_1[137] ? 9'h89 : _flushId_T_376; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_378 = _flushId_T_1[136] ? 9'h88 : _flushId_T_377; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_379 = _flushId_T_1[135] ? 9'h87 : _flushId_T_378; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_380 = _flushId_T_1[134] ? 9'h86 : _flushId_T_379; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_381 = _flushId_T_1[133] ? 9'h85 : _flushId_T_380; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_382 = _flushId_T_1[132] ? 9'h84 : _flushId_T_381; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_383 = _flushId_T_1[131] ? 9'h83 : _flushId_T_382; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_384 = _flushId_T_1[130] ? 9'h82 : _flushId_T_383; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_385 = _flushId_T_1[129] ? 9'h81 : _flushId_T_384; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_386 = _flushId_T_1[128] ? 9'h80 : _flushId_T_385; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_387 = _flushId_T_1[127] ? 9'h7f : _flushId_T_386; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_388 = _flushId_T_1[126] ? 9'h7e : _flushId_T_387; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_389 = _flushId_T_1[125] ? 9'h7d : _flushId_T_388; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_390 = _flushId_T_1[124] ? 9'h7c : _flushId_T_389; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_391 = _flushId_T_1[123] ? 9'h7b : _flushId_T_390; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_392 = _flushId_T_1[122] ? 9'h7a : _flushId_T_391; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_393 = _flushId_T_1[121] ? 9'h79 : _flushId_T_392; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_394 = _flushId_T_1[120] ? 9'h78 : _flushId_T_393; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_395 = _flushId_T_1[119] ? 9'h77 : _flushId_T_394; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_396 = _flushId_T_1[118] ? 9'h76 : _flushId_T_395; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_397 = _flushId_T_1[117] ? 9'h75 : _flushId_T_396; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_398 = _flushId_T_1[116] ? 9'h74 : _flushId_T_397; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_399 = _flushId_T_1[115] ? 9'h73 : _flushId_T_398; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_400 = _flushId_T_1[114] ? 9'h72 : _flushId_T_399; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_401 = _flushId_T_1[113] ? 9'h71 : _flushId_T_400; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_402 = _flushId_T_1[112] ? 9'h70 : _flushId_T_401; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_403 = _flushId_T_1[111] ? 9'h6f : _flushId_T_402; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_404 = _flushId_T_1[110] ? 9'h6e : _flushId_T_403; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_405 = _flushId_T_1[109] ? 9'h6d : _flushId_T_404; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_406 = _flushId_T_1[108] ? 9'h6c : _flushId_T_405; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_407 = _flushId_T_1[107] ? 9'h6b : _flushId_T_406; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_408 = _flushId_T_1[106] ? 9'h6a : _flushId_T_407; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_409 = _flushId_T_1[105] ? 9'h69 : _flushId_T_408; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_410 = _flushId_T_1[104] ? 9'h68 : _flushId_T_409; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_411 = _flushId_T_1[103] ? 9'h67 : _flushId_T_410; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_412 = _flushId_T_1[102] ? 9'h66 : _flushId_T_411; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_413 = _flushId_T_1[101] ? 9'h65 : _flushId_T_412; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_414 = _flushId_T_1[100] ? 9'h64 : _flushId_T_413; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_415 = _flushId_T_1[99] ? 9'h63 : _flushId_T_414; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_416 = _flushId_T_1[98] ? 9'h62 : _flushId_T_415; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_417 = _flushId_T_1[97] ? 9'h61 : _flushId_T_416; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_418 = _flushId_T_1[96] ? 9'h60 : _flushId_T_417; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_419 = _flushId_T_1[95] ? 9'h5f : _flushId_T_418; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_420 = _flushId_T_1[94] ? 9'h5e : _flushId_T_419; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_421 = _flushId_T_1[93] ? 9'h5d : _flushId_T_420; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_422 = _flushId_T_1[92] ? 9'h5c : _flushId_T_421; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_423 = _flushId_T_1[91] ? 9'h5b : _flushId_T_422; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_424 = _flushId_T_1[90] ? 9'h5a : _flushId_T_423; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_425 = _flushId_T_1[89] ? 9'h59 : _flushId_T_424; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_426 = _flushId_T_1[88] ? 9'h58 : _flushId_T_425; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_427 = _flushId_T_1[87] ? 9'h57 : _flushId_T_426; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_428 = _flushId_T_1[86] ? 9'h56 : _flushId_T_427; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_429 = _flushId_T_1[85] ? 9'h55 : _flushId_T_428; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_430 = _flushId_T_1[84] ? 9'h54 : _flushId_T_429; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_431 = _flushId_T_1[83] ? 9'h53 : _flushId_T_430; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_432 = _flushId_T_1[82] ? 9'h52 : _flushId_T_431; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_433 = _flushId_T_1[81] ? 9'h51 : _flushId_T_432; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_434 = _flushId_T_1[80] ? 9'h50 : _flushId_T_433; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_435 = _flushId_T_1[79] ? 9'h4f : _flushId_T_434; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_436 = _flushId_T_1[78] ? 9'h4e : _flushId_T_435; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_437 = _flushId_T_1[77] ? 9'h4d : _flushId_T_436; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_438 = _flushId_T_1[76] ? 9'h4c : _flushId_T_437; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_439 = _flushId_T_1[75] ? 9'h4b : _flushId_T_438; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_440 = _flushId_T_1[74] ? 9'h4a : _flushId_T_439; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_441 = _flushId_T_1[73] ? 9'h49 : _flushId_T_440; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_442 = _flushId_T_1[72] ? 9'h48 : _flushId_T_441; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_443 = _flushId_T_1[71] ? 9'h47 : _flushId_T_442; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_444 = _flushId_T_1[70] ? 9'h46 : _flushId_T_443; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_445 = _flushId_T_1[69] ? 9'h45 : _flushId_T_444; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_446 = _flushId_T_1[68] ? 9'h44 : _flushId_T_445; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_447 = _flushId_T_1[67] ? 9'h43 : _flushId_T_446; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_448 = _flushId_T_1[66] ? 9'h42 : _flushId_T_447; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_449 = _flushId_T_1[65] ? 9'h41 : _flushId_T_448; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_450 = _flushId_T_1[64] ? 9'h40 : _flushId_T_449; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_451 = _flushId_T_1[63] ? 9'h3f : _flushId_T_450; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_452 = _flushId_T_1[62] ? 9'h3e : _flushId_T_451; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_453 = _flushId_T_1[61] ? 9'h3d : _flushId_T_452; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_454 = _flushId_T_1[60] ? 9'h3c : _flushId_T_453; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_455 = _flushId_T_1[59] ? 9'h3b : _flushId_T_454; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_456 = _flushId_T_1[58] ? 9'h3a : _flushId_T_455; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_457 = _flushId_T_1[57] ? 9'h39 : _flushId_T_456; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_458 = _flushId_T_1[56] ? 9'h38 : _flushId_T_457; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_459 = _flushId_T_1[55] ? 9'h37 : _flushId_T_458; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_460 = _flushId_T_1[54] ? 9'h36 : _flushId_T_459; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_461 = _flushId_T_1[53] ? 9'h35 : _flushId_T_460; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_462 = _flushId_T_1[52] ? 9'h34 : _flushId_T_461; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_463 = _flushId_T_1[51] ? 9'h33 : _flushId_T_462; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_464 = _flushId_T_1[50] ? 9'h32 : _flushId_T_463; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_465 = _flushId_T_1[49] ? 9'h31 : _flushId_T_464; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_466 = _flushId_T_1[48] ? 9'h30 : _flushId_T_465; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_467 = _flushId_T_1[47] ? 9'h2f : _flushId_T_466; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_468 = _flushId_T_1[46] ? 9'h2e : _flushId_T_467; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_469 = _flushId_T_1[45] ? 9'h2d : _flushId_T_468; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_470 = _flushId_T_1[44] ? 9'h2c : _flushId_T_469; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_471 = _flushId_T_1[43] ? 9'h2b : _flushId_T_470; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_472 = _flushId_T_1[42] ? 9'h2a : _flushId_T_471; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_473 = _flushId_T_1[41] ? 9'h29 : _flushId_T_472; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_474 = _flushId_T_1[40] ? 9'h28 : _flushId_T_473; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_475 = _flushId_T_1[39] ? 9'h27 : _flushId_T_474; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_476 = _flushId_T_1[38] ? 9'h26 : _flushId_T_475; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_477 = _flushId_T_1[37] ? 9'h25 : _flushId_T_476; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_478 = _flushId_T_1[36] ? 9'h24 : _flushId_T_477; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_479 = _flushId_T_1[35] ? 9'h23 : _flushId_T_478; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_480 = _flushId_T_1[34] ? 9'h22 : _flushId_T_479; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_481 = _flushId_T_1[33] ? 9'h21 : _flushId_T_480; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_482 = _flushId_T_1[32] ? 9'h20 : _flushId_T_481; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_483 = _flushId_T_1[31] ? 9'h1f : _flushId_T_482; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_484 = _flushId_T_1[30] ? 9'h1e : _flushId_T_483; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_485 = _flushId_T_1[29] ? 9'h1d : _flushId_T_484; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_486 = _flushId_T_1[28] ? 9'h1c : _flushId_T_485; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_487 = _flushId_T_1[27] ? 9'h1b : _flushId_T_486; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_488 = _flushId_T_1[26] ? 9'h1a : _flushId_T_487; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_489 = _flushId_T_1[25] ? 9'h19 : _flushId_T_488; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_490 = _flushId_T_1[24] ? 9'h18 : _flushId_T_489; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_491 = _flushId_T_1[23] ? 9'h17 : _flushId_T_490; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_492 = _flushId_T_1[22] ? 9'h16 : _flushId_T_491; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_493 = _flushId_T_1[21] ? 9'h15 : _flushId_T_492; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_494 = _flushId_T_1[20] ? 9'h14 : _flushId_T_493; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_495 = _flushId_T_1[19] ? 9'h13 : _flushId_T_494; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_496 = _flushId_T_1[18] ? 9'h12 : _flushId_T_495; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_497 = _flushId_T_1[17] ? 9'h11 : _flushId_T_496; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_498 = _flushId_T_1[16] ? 9'h10 : _flushId_T_497; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_499 = _flushId_T_1[15] ? 9'hf : _flushId_T_498; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_500 = _flushId_T_1[14] ? 9'he : _flushId_T_499; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_501 = _flushId_T_1[13] ? 9'hd : _flushId_T_500; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_502 = _flushId_T_1[12] ? 9'hc : _flushId_T_501; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_503 = _flushId_T_1[11] ? 9'hb : _flushId_T_502; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_504 = _flushId_T_1[10] ? 9'ha : _flushId_T_503; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_505 = _flushId_T_1[9] ? 9'h9 : _flushId_T_504; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_506 = _flushId_T_1[8] ? 9'h8 : _flushId_T_505; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_507 = _flushId_T_1[7] ? 9'h7 : _flushId_T_506; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_508 = _flushId_T_1[6] ? 9'h6 : _flushId_T_507; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_509 = _flushId_T_1[5] ? 9'h5 : _flushId_T_508; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_510 = _flushId_T_1[4] ? 9'h4 : _flushId_T_509; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_511 = _flushId_T_1[3] ? 9'h3 : _flushId_T_510; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_512 = _flushId_T_1[2] ? 9'h2 : _flushId_T_511; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_513 = _flushId_T_1[1] ? 9'h1 : _flushId_T_512; // @[Mux.scala 47:70]
- wire [8:0] _flushId_T_514 = _flushId_T_1[0] ? 9'h0 : _flushId_T_513; // @[Mux.scala 47:70]
- wire [7:0] flushId = _flushId_T_514[7:0]; // @[L1DCache.scala 576:34]
- wire _T_4291 = ~dirty_0; // @[L1DCache.scala 579:26]
- wire _T_4297 = ~dirty_1; // @[L1DCache.scala 579:26]
- wire _T_4303 = ~dirty_2; // @[L1DCache.scala 579:26]
- wire _T_4309 = ~dirty_3; // @[L1DCache.scala 579:26]
- wire _T_4315 = ~dirty_4; // @[L1DCache.scala 579:26]
- wire _T_4321 = ~dirty_5; // @[L1DCache.scala 579:26]
- wire _T_4327 = ~dirty_6; // @[L1DCache.scala 579:26]
- wire _T_4333 = ~dirty_7; // @[L1DCache.scala 579:26]
- wire _T_4339 = ~dirty_8; // @[L1DCache.scala 579:26]
- wire _T_4345 = ~dirty_9; // @[L1DCache.scala 579:26]
- wire _T_4351 = ~dirty_10; // @[L1DCache.scala 579:26]
- wire _T_4357 = ~dirty_11; // @[L1DCache.scala 579:26]
- wire _T_4363 = ~dirty_12; // @[L1DCache.scala 579:26]
- wire _T_4369 = ~dirty_13; // @[L1DCache.scala 579:26]
- wire _T_4375 = ~dirty_14; // @[L1DCache.scala 579:26]
- wire _T_4381 = ~dirty_15; // @[L1DCache.scala 579:26]
- wire _T_4387 = ~dirty_16; // @[L1DCache.scala 579:26]
- wire _T_4393 = ~dirty_17; // @[L1DCache.scala 579:26]
- wire _T_4399 = ~dirty_18; // @[L1DCache.scala 579:26]
- wire _T_4405 = ~dirty_19; // @[L1DCache.scala 579:26]
- wire _T_4411 = ~dirty_20; // @[L1DCache.scala 579:26]
- wire _T_4417 = ~dirty_21; // @[L1DCache.scala 579:26]
- wire _T_4423 = ~dirty_22; // @[L1DCache.scala 579:26]
- wire _T_4429 = ~dirty_23; // @[L1DCache.scala 579:26]
- wire _T_4435 = ~dirty_24; // @[L1DCache.scala 579:26]
- wire _T_4441 = ~dirty_25; // @[L1DCache.scala 579:26]
- wire _T_4447 = ~dirty_26; // @[L1DCache.scala 579:26]
- wire _T_4453 = ~dirty_27; // @[L1DCache.scala 579:26]
- wire _T_4459 = ~dirty_28; // @[L1DCache.scala 579:26]
- wire _T_4465 = ~dirty_29; // @[L1DCache.scala 579:26]
- wire _T_4471 = ~dirty_30; // @[L1DCache.scala 579:26]
- wire _T_4477 = ~dirty_31; // @[L1DCache.scala 579:26]
- wire _T_4483 = ~dirty_32; // @[L1DCache.scala 579:26]
- wire _T_4489 = ~dirty_33; // @[L1DCache.scala 579:26]
- wire _T_4495 = ~dirty_34; // @[L1DCache.scala 579:26]
- wire _T_4501 = ~dirty_35; // @[L1DCache.scala 579:26]
- wire _T_4507 = ~dirty_36; // @[L1DCache.scala 579:26]
- wire _T_4513 = ~dirty_37; // @[L1DCache.scala 579:26]
- wire _T_4519 = ~dirty_38; // @[L1DCache.scala 579:26]
- wire _T_4525 = ~dirty_39; // @[L1DCache.scala 579:26]
- wire _T_4531 = ~dirty_40; // @[L1DCache.scala 579:26]
- wire _T_4537 = ~dirty_41; // @[L1DCache.scala 579:26]
- wire _T_4543 = ~dirty_42; // @[L1DCache.scala 579:26]
- wire _T_4549 = ~dirty_43; // @[L1DCache.scala 579:26]
- wire _T_4555 = ~dirty_44; // @[L1DCache.scala 579:26]
- wire _T_4561 = ~dirty_45; // @[L1DCache.scala 579:26]
- wire _T_4567 = ~dirty_46; // @[L1DCache.scala 579:26]
- wire _T_4573 = ~dirty_47; // @[L1DCache.scala 579:26]
- wire _T_4579 = ~dirty_48; // @[L1DCache.scala 579:26]
- wire _T_4585 = ~dirty_49; // @[L1DCache.scala 579:26]
- wire _T_4591 = ~dirty_50; // @[L1DCache.scala 579:26]
- wire _T_4597 = ~dirty_51; // @[L1DCache.scala 579:26]
- wire _T_4603 = ~dirty_52; // @[L1DCache.scala 579:26]
- wire _T_4609 = ~dirty_53; // @[L1DCache.scala 579:26]
- wire _T_4615 = ~dirty_54; // @[L1DCache.scala 579:26]
- wire _T_4621 = ~dirty_55; // @[L1DCache.scala 579:26]
- wire _T_4627 = ~dirty_56; // @[L1DCache.scala 579:26]
- wire _T_4633 = ~dirty_57; // @[L1DCache.scala 579:26]
- wire _T_4639 = ~dirty_58; // @[L1DCache.scala 579:26]
- wire _T_4645 = ~dirty_59; // @[L1DCache.scala 579:26]
- wire _T_4651 = ~dirty_60; // @[L1DCache.scala 579:26]
- wire _T_4657 = ~dirty_61; // @[L1DCache.scala 579:26]
- wire _T_4663 = ~dirty_62; // @[L1DCache.scala 579:26]
- wire _T_4669 = ~dirty_63; // @[L1DCache.scala 579:26]
- wire _T_4675 = ~dirty_64; // @[L1DCache.scala 579:26]
- wire _T_4681 = ~dirty_65; // @[L1DCache.scala 579:26]
- wire _T_4687 = ~dirty_66; // @[L1DCache.scala 579:26]
- wire _T_4693 = ~dirty_67; // @[L1DCache.scala 579:26]
- wire _T_4699 = ~dirty_68; // @[L1DCache.scala 579:26]
- wire _T_4705 = ~dirty_69; // @[L1DCache.scala 579:26]
- wire _T_4711 = ~dirty_70; // @[L1DCache.scala 579:26]
- wire _T_4717 = ~dirty_71; // @[L1DCache.scala 579:26]
- wire _T_4723 = ~dirty_72; // @[L1DCache.scala 579:26]
- wire _T_4729 = ~dirty_73; // @[L1DCache.scala 579:26]
- wire _T_4735 = ~dirty_74; // @[L1DCache.scala 579:26]
- wire _T_4741 = ~dirty_75; // @[L1DCache.scala 579:26]
- wire _T_4747 = ~dirty_76; // @[L1DCache.scala 579:26]
- wire _T_4753 = ~dirty_77; // @[L1DCache.scala 579:26]
- wire _T_4759 = ~dirty_78; // @[L1DCache.scala 579:26]
- wire _T_4765 = ~dirty_79; // @[L1DCache.scala 579:26]
- wire _T_4771 = ~dirty_80; // @[L1DCache.scala 579:26]
- wire _T_4777 = ~dirty_81; // @[L1DCache.scala 579:26]
- wire _T_4783 = ~dirty_82; // @[L1DCache.scala 579:26]
- wire _T_4789 = ~dirty_83; // @[L1DCache.scala 579:26]
- wire _T_4795 = ~dirty_84; // @[L1DCache.scala 579:26]
- wire _T_4801 = ~dirty_85; // @[L1DCache.scala 579:26]
- wire _T_4807 = ~dirty_86; // @[L1DCache.scala 579:26]
- wire _T_4813 = ~dirty_87; // @[L1DCache.scala 579:26]
- wire _T_4819 = ~dirty_88; // @[L1DCache.scala 579:26]
- wire _T_4825 = ~dirty_89; // @[L1DCache.scala 579:26]
- wire _T_4831 = ~dirty_90; // @[L1DCache.scala 579:26]
- wire _T_4837 = ~dirty_91; // @[L1DCache.scala 579:26]
- wire _T_4843 = ~dirty_92; // @[L1DCache.scala 579:26]
- wire _T_4849 = ~dirty_93; // @[L1DCache.scala 579:26]
- wire _T_4855 = ~dirty_94; // @[L1DCache.scala 579:26]
- wire _T_4861 = ~dirty_95; // @[L1DCache.scala 579:26]
- wire _T_4867 = ~dirty_96; // @[L1DCache.scala 579:26]
- wire _T_4873 = ~dirty_97; // @[L1DCache.scala 579:26]
- wire _T_4879 = ~dirty_98; // @[L1DCache.scala 579:26]
- wire _T_4885 = ~dirty_99; // @[L1DCache.scala 579:26]
- wire _T_4891 = ~dirty_100; // @[L1DCache.scala 579:26]
- wire _T_4897 = ~dirty_101; // @[L1DCache.scala 579:26]
- wire _T_4903 = ~dirty_102; // @[L1DCache.scala 579:26]
- wire _T_4909 = ~dirty_103; // @[L1DCache.scala 579:26]
- wire _T_4915 = ~dirty_104; // @[L1DCache.scala 579:26]
- wire _T_4921 = ~dirty_105; // @[L1DCache.scala 579:26]
- wire _T_4927 = ~dirty_106; // @[L1DCache.scala 579:26]
- wire _T_4933 = ~dirty_107; // @[L1DCache.scala 579:26]
- wire _T_4939 = ~dirty_108; // @[L1DCache.scala 579:26]
- wire _T_4945 = ~dirty_109; // @[L1DCache.scala 579:26]
- wire _T_4951 = ~dirty_110; // @[L1DCache.scala 579:26]
- wire _T_4957 = ~dirty_111; // @[L1DCache.scala 579:26]
- wire _T_4963 = ~dirty_112; // @[L1DCache.scala 579:26]
- wire _T_4969 = ~dirty_113; // @[L1DCache.scala 579:26]
- wire _T_4975 = ~dirty_114; // @[L1DCache.scala 579:26]
- wire _T_4981 = ~dirty_115; // @[L1DCache.scala 579:26]
- wire _T_4987 = ~dirty_116; // @[L1DCache.scala 579:26]
- wire _T_4993 = ~dirty_117; // @[L1DCache.scala 579:26]
- wire _T_4999 = ~dirty_118; // @[L1DCache.scala 579:26]
- wire _T_5005 = ~dirty_119; // @[L1DCache.scala 579:26]
- wire _T_5011 = ~dirty_120; // @[L1DCache.scala 579:26]
- wire _T_5017 = ~dirty_121; // @[L1DCache.scala 579:26]
- wire _T_5023 = ~dirty_122; // @[L1DCache.scala 579:26]
- wire _T_5029 = ~dirty_123; // @[L1DCache.scala 579:26]
- wire _T_5035 = ~dirty_124; // @[L1DCache.scala 579:26]
- wire _T_5041 = ~dirty_125; // @[L1DCache.scala 579:26]
- wire _T_5047 = ~dirty_126; // @[L1DCache.scala 579:26]
- wire _T_5053 = ~dirty_127; // @[L1DCache.scala 579:26]
- wire _T_5059 = ~dirty_128; // @[L1DCache.scala 579:26]
- wire _T_5065 = ~dirty_129; // @[L1DCache.scala 579:26]
- wire _T_5071 = ~dirty_130; // @[L1DCache.scala 579:26]
- wire _T_5077 = ~dirty_131; // @[L1DCache.scala 579:26]
- wire _T_5083 = ~dirty_132; // @[L1DCache.scala 579:26]
- wire _T_5089 = ~dirty_133; // @[L1DCache.scala 579:26]
- wire _T_5095 = ~dirty_134; // @[L1DCache.scala 579:26]
- wire _T_5101 = ~dirty_135; // @[L1DCache.scala 579:26]
- wire _T_5107 = ~dirty_136; // @[L1DCache.scala 579:26]
- wire _T_5113 = ~dirty_137; // @[L1DCache.scala 579:26]
- wire _T_5119 = ~dirty_138; // @[L1DCache.scala 579:26]
- wire _T_5125 = ~dirty_139; // @[L1DCache.scala 579:26]
- wire _T_5131 = ~dirty_140; // @[L1DCache.scala 579:26]
- wire _T_5137 = ~dirty_141; // @[L1DCache.scala 579:26]
- wire _T_5143 = ~dirty_142; // @[L1DCache.scala 579:26]
- wire _T_5149 = ~dirty_143; // @[L1DCache.scala 579:26]
- wire _T_5155 = ~dirty_144; // @[L1DCache.scala 579:26]
- wire _T_5161 = ~dirty_145; // @[L1DCache.scala 579:26]
- wire _T_5167 = ~dirty_146; // @[L1DCache.scala 579:26]
- wire _T_5173 = ~dirty_147; // @[L1DCache.scala 579:26]
- wire _T_5179 = ~dirty_148; // @[L1DCache.scala 579:26]
- wire _T_5185 = ~dirty_149; // @[L1DCache.scala 579:26]
- wire _T_5191 = ~dirty_150; // @[L1DCache.scala 579:26]
- wire _T_5197 = ~dirty_151; // @[L1DCache.scala 579:26]
- wire _T_5203 = ~dirty_152; // @[L1DCache.scala 579:26]
- wire _T_5209 = ~dirty_153; // @[L1DCache.scala 579:26]
- wire _T_5215 = ~dirty_154; // @[L1DCache.scala 579:26]
- wire _T_5221 = ~dirty_155; // @[L1DCache.scala 579:26]
- wire _T_5227 = ~dirty_156; // @[L1DCache.scala 579:26]
- wire _T_5233 = ~dirty_157; // @[L1DCache.scala 579:26]
- wire _T_5239 = ~dirty_158; // @[L1DCache.scala 579:26]
- wire _T_5245 = ~dirty_159; // @[L1DCache.scala 579:26]
- wire _T_5251 = ~dirty_160; // @[L1DCache.scala 579:26]
- wire _T_5257 = ~dirty_161; // @[L1DCache.scala 579:26]
- wire _T_5263 = ~dirty_162; // @[L1DCache.scala 579:26]
- wire _T_5269 = ~dirty_163; // @[L1DCache.scala 579:26]
- wire _T_5275 = ~dirty_164; // @[L1DCache.scala 579:26]
- wire _T_5281 = ~dirty_165; // @[L1DCache.scala 579:26]
- wire _T_5287 = ~dirty_166; // @[L1DCache.scala 579:26]
- wire _T_5293 = ~dirty_167; // @[L1DCache.scala 579:26]
- wire _T_5299 = ~dirty_168; // @[L1DCache.scala 579:26]
- wire _T_5305 = ~dirty_169; // @[L1DCache.scala 579:26]
- wire _T_5311 = ~dirty_170; // @[L1DCache.scala 579:26]
- wire _T_5317 = ~dirty_171; // @[L1DCache.scala 579:26]
- wire _T_5323 = ~dirty_172; // @[L1DCache.scala 579:26]
- wire _T_5329 = ~dirty_173; // @[L1DCache.scala 579:26]
- wire _T_5335 = ~dirty_174; // @[L1DCache.scala 579:26]
- wire _T_5341 = ~dirty_175; // @[L1DCache.scala 579:26]
- wire _T_5347 = ~dirty_176; // @[L1DCache.scala 579:26]
- wire _T_5353 = ~dirty_177; // @[L1DCache.scala 579:26]
- wire _T_5359 = ~dirty_178; // @[L1DCache.scala 579:26]
- wire _T_5365 = ~dirty_179; // @[L1DCache.scala 579:26]
- wire _T_5371 = ~dirty_180; // @[L1DCache.scala 579:26]
- wire _T_5377 = ~dirty_181; // @[L1DCache.scala 579:26]
- wire _T_5383 = ~dirty_182; // @[L1DCache.scala 579:26]
- wire _T_5389 = ~dirty_183; // @[L1DCache.scala 579:26]
- wire _T_5395 = ~dirty_184; // @[L1DCache.scala 579:26]
- wire _T_5401 = ~dirty_185; // @[L1DCache.scala 579:26]
- wire _T_5407 = ~dirty_186; // @[L1DCache.scala 579:26]
- wire _T_5413 = ~dirty_187; // @[L1DCache.scala 579:26]
- wire _T_5419 = ~dirty_188; // @[L1DCache.scala 579:26]
- wire _T_5425 = ~dirty_189; // @[L1DCache.scala 579:26]
- wire _T_5431 = ~dirty_190; // @[L1DCache.scala 579:26]
- wire _T_5437 = ~dirty_191; // @[L1DCache.scala 579:26]
- wire _T_5443 = ~dirty_192; // @[L1DCache.scala 579:26]
- wire _T_5449 = ~dirty_193; // @[L1DCache.scala 579:26]
- wire _T_5455 = ~dirty_194; // @[L1DCache.scala 579:26]
- wire _T_5461 = ~dirty_195; // @[L1DCache.scala 579:26]
- wire _T_5467 = ~dirty_196; // @[L1DCache.scala 579:26]
- wire _T_5473 = ~dirty_197; // @[L1DCache.scala 579:26]
- wire _T_5479 = ~dirty_198; // @[L1DCache.scala 579:26]
- wire _T_5485 = ~dirty_199; // @[L1DCache.scala 579:26]
- wire _T_5491 = ~dirty_200; // @[L1DCache.scala 579:26]
- wire _T_5497 = ~dirty_201; // @[L1DCache.scala 579:26]
- wire _T_5503 = ~dirty_202; // @[L1DCache.scala 579:26]
- wire _T_5509 = ~dirty_203; // @[L1DCache.scala 579:26]
- wire _T_5515 = ~dirty_204; // @[L1DCache.scala 579:26]
- wire _T_5521 = ~dirty_205; // @[L1DCache.scala 579:26]
- wire _T_5527 = ~dirty_206; // @[L1DCache.scala 579:26]
- wire _T_5533 = ~dirty_207; // @[L1DCache.scala 579:26]
- wire _T_5539 = ~dirty_208; // @[L1DCache.scala 579:26]
- wire _T_5545 = ~dirty_209; // @[L1DCache.scala 579:26]
- wire _T_5551 = ~dirty_210; // @[L1DCache.scala 579:26]
- wire _T_5557 = ~dirty_211; // @[L1DCache.scala 579:26]
- wire _T_5563 = ~dirty_212; // @[L1DCache.scala 579:26]
- wire _T_5569 = ~dirty_213; // @[L1DCache.scala 579:26]
- wire _T_5575 = ~dirty_214; // @[L1DCache.scala 579:26]
- wire _T_5581 = ~dirty_215; // @[L1DCache.scala 579:26]
- wire _T_5587 = ~dirty_216; // @[L1DCache.scala 579:26]
- wire _T_5593 = ~dirty_217; // @[L1DCache.scala 579:26]
- wire _T_5599 = ~dirty_218; // @[L1DCache.scala 579:26]
- wire _T_5605 = ~dirty_219; // @[L1DCache.scala 579:26]
- wire _T_5611 = ~dirty_220; // @[L1DCache.scala 579:26]
- wire _T_5617 = ~dirty_221; // @[L1DCache.scala 579:26]
- wire _T_5623 = ~dirty_222; // @[L1DCache.scala 579:26]
- wire _T_5629 = ~dirty_223; // @[L1DCache.scala 579:26]
- wire _T_5635 = ~dirty_224; // @[L1DCache.scala 579:26]
- wire _T_5641 = ~dirty_225; // @[L1DCache.scala 579:26]
- wire _T_5647 = ~dirty_226; // @[L1DCache.scala 579:26]
- wire _T_5653 = ~dirty_227; // @[L1DCache.scala 579:26]
- wire _T_5659 = ~dirty_228; // @[L1DCache.scala 579:26]
- wire _T_5665 = ~dirty_229; // @[L1DCache.scala 579:26]
- wire _T_5671 = ~dirty_230; // @[L1DCache.scala 579:26]
- wire _T_5677 = ~dirty_231; // @[L1DCache.scala 579:26]
- wire _T_5683 = ~dirty_232; // @[L1DCache.scala 579:26]
- wire _T_5689 = ~dirty_233; // @[L1DCache.scala 579:26]
- wire _T_5695 = ~dirty_234; // @[L1DCache.scala 579:26]
- wire _T_5701 = ~dirty_235; // @[L1DCache.scala 579:26]
- wire _T_5707 = ~dirty_236; // @[L1DCache.scala 579:26]
- wire _T_5713 = ~dirty_237; // @[L1DCache.scala 579:26]
- wire _T_5719 = ~dirty_238; // @[L1DCache.scala 579:26]
- wire _T_5725 = ~dirty_239; // @[L1DCache.scala 579:26]
- wire _T_5731 = ~dirty_240; // @[L1DCache.scala 579:26]
- wire _T_5737 = ~dirty_241; // @[L1DCache.scala 579:26]
- wire _T_5743 = ~dirty_242; // @[L1DCache.scala 579:26]
- wire _T_5749 = ~dirty_243; // @[L1DCache.scala 579:26]
- wire _T_5755 = ~dirty_244; // @[L1DCache.scala 579:26]
- wire _T_5761 = ~dirty_245; // @[L1DCache.scala 579:26]
- wire _T_5767 = ~dirty_246; // @[L1DCache.scala 579:26]
- wire _T_5773 = ~dirty_247; // @[L1DCache.scala 579:26]
- wire _T_5779 = ~dirty_248; // @[L1DCache.scala 579:26]
- wire _T_5785 = ~dirty_249; // @[L1DCache.scala 579:26]
- wire _T_5791 = ~dirty_250; // @[L1DCache.scala 579:26]
- wire _T_5797 = ~dirty_251; // @[L1DCache.scala 579:26]
- wire _T_5803 = ~dirty_252; // @[L1DCache.scala 579:26]
- wire _T_5809 = ~dirty_253; // @[L1DCache.scala 579:26]
- wire _T_5815 = ~dirty_254; // @[L1DCache.scala 579:26]
- wire _T_5821 = ~dirty_255; // @[L1DCache.scala 579:26]
- wire _T_5829 = 3'h0 == fstate; // @[L1DCache.scala 582:18]
- wire _T_5830 = ~axiwaddrvalid; // @[L1DCache.scala 584:31]
- wire _T_5832 = ~axiwdatavalid; // @[L1DCache.scala 584:49]
- wire _T_5840 = 3'h1 == fstate; // @[L1DCache.scala 582:18]
- wire _GEN_4886 = 8'h1 == replaceIdReg ? dirty_1 : dirty_0; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4887 = 8'h2 == replaceIdReg ? dirty_2 : _GEN_4886; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4888 = 8'h3 == replaceIdReg ? dirty_3 : _GEN_4887; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4889 = 8'h4 == replaceIdReg ? dirty_4 : _GEN_4888; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4890 = 8'h5 == replaceIdReg ? dirty_5 : _GEN_4889; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4891 = 8'h6 == replaceIdReg ? dirty_6 : _GEN_4890; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4892 = 8'h7 == replaceIdReg ? dirty_7 : _GEN_4891; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4893 = 8'h8 == replaceIdReg ? dirty_8 : _GEN_4892; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4894 = 8'h9 == replaceIdReg ? dirty_9 : _GEN_4893; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4895 = 8'ha == replaceIdReg ? dirty_10 : _GEN_4894; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4896 = 8'hb == replaceIdReg ? dirty_11 : _GEN_4895; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4897 = 8'hc == replaceIdReg ? dirty_12 : _GEN_4896; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4898 = 8'hd == replaceIdReg ? dirty_13 : _GEN_4897; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4899 = 8'he == replaceIdReg ? dirty_14 : _GEN_4898; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4900 = 8'hf == replaceIdReg ? dirty_15 : _GEN_4899; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4901 = 8'h10 == replaceIdReg ? dirty_16 : _GEN_4900; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4902 = 8'h11 == replaceIdReg ? dirty_17 : _GEN_4901; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4903 = 8'h12 == replaceIdReg ? dirty_18 : _GEN_4902; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4904 = 8'h13 == replaceIdReg ? dirty_19 : _GEN_4903; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4905 = 8'h14 == replaceIdReg ? dirty_20 : _GEN_4904; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4906 = 8'h15 == replaceIdReg ? dirty_21 : _GEN_4905; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4907 = 8'h16 == replaceIdReg ? dirty_22 : _GEN_4906; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4908 = 8'h17 == replaceIdReg ? dirty_23 : _GEN_4907; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4909 = 8'h18 == replaceIdReg ? dirty_24 : _GEN_4908; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4910 = 8'h19 == replaceIdReg ? dirty_25 : _GEN_4909; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4911 = 8'h1a == replaceIdReg ? dirty_26 : _GEN_4910; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4912 = 8'h1b == replaceIdReg ? dirty_27 : _GEN_4911; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4913 = 8'h1c == replaceIdReg ? dirty_28 : _GEN_4912; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4914 = 8'h1d == replaceIdReg ? dirty_29 : _GEN_4913; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4915 = 8'h1e == replaceIdReg ? dirty_30 : _GEN_4914; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4916 = 8'h1f == replaceIdReg ? dirty_31 : _GEN_4915; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4917 = 8'h20 == replaceIdReg ? dirty_32 : _GEN_4916; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4918 = 8'h21 == replaceIdReg ? dirty_33 : _GEN_4917; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4919 = 8'h22 == replaceIdReg ? dirty_34 : _GEN_4918; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4920 = 8'h23 == replaceIdReg ? dirty_35 : _GEN_4919; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4921 = 8'h24 == replaceIdReg ? dirty_36 : _GEN_4920; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4922 = 8'h25 == replaceIdReg ? dirty_37 : _GEN_4921; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4923 = 8'h26 == replaceIdReg ? dirty_38 : _GEN_4922; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4924 = 8'h27 == replaceIdReg ? dirty_39 : _GEN_4923; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4925 = 8'h28 == replaceIdReg ? dirty_40 : _GEN_4924; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4926 = 8'h29 == replaceIdReg ? dirty_41 : _GEN_4925; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4927 = 8'h2a == replaceIdReg ? dirty_42 : _GEN_4926; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4928 = 8'h2b == replaceIdReg ? dirty_43 : _GEN_4927; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4929 = 8'h2c == replaceIdReg ? dirty_44 : _GEN_4928; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4930 = 8'h2d == replaceIdReg ? dirty_45 : _GEN_4929; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4931 = 8'h2e == replaceIdReg ? dirty_46 : _GEN_4930; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4932 = 8'h2f == replaceIdReg ? dirty_47 : _GEN_4931; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4933 = 8'h30 == replaceIdReg ? dirty_48 : _GEN_4932; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4934 = 8'h31 == replaceIdReg ? dirty_49 : _GEN_4933; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4935 = 8'h32 == replaceIdReg ? dirty_50 : _GEN_4934; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4936 = 8'h33 == replaceIdReg ? dirty_51 : _GEN_4935; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4937 = 8'h34 == replaceIdReg ? dirty_52 : _GEN_4936; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4938 = 8'h35 == replaceIdReg ? dirty_53 : _GEN_4937; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4939 = 8'h36 == replaceIdReg ? dirty_54 : _GEN_4938; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4940 = 8'h37 == replaceIdReg ? dirty_55 : _GEN_4939; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4941 = 8'h38 == replaceIdReg ? dirty_56 : _GEN_4940; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4942 = 8'h39 == replaceIdReg ? dirty_57 : _GEN_4941; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4943 = 8'h3a == replaceIdReg ? dirty_58 : _GEN_4942; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4944 = 8'h3b == replaceIdReg ? dirty_59 : _GEN_4943; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4945 = 8'h3c == replaceIdReg ? dirty_60 : _GEN_4944; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4946 = 8'h3d == replaceIdReg ? dirty_61 : _GEN_4945; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4947 = 8'h3e == replaceIdReg ? dirty_62 : _GEN_4946; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4948 = 8'h3f == replaceIdReg ? dirty_63 : _GEN_4947; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4949 = 8'h40 == replaceIdReg ? dirty_64 : _GEN_4948; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4950 = 8'h41 == replaceIdReg ? dirty_65 : _GEN_4949; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4951 = 8'h42 == replaceIdReg ? dirty_66 : _GEN_4950; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4952 = 8'h43 == replaceIdReg ? dirty_67 : _GEN_4951; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4953 = 8'h44 == replaceIdReg ? dirty_68 : _GEN_4952; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4954 = 8'h45 == replaceIdReg ? dirty_69 : _GEN_4953; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4955 = 8'h46 == replaceIdReg ? dirty_70 : _GEN_4954; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4956 = 8'h47 == replaceIdReg ? dirty_71 : _GEN_4955; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4957 = 8'h48 == replaceIdReg ? dirty_72 : _GEN_4956; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4958 = 8'h49 == replaceIdReg ? dirty_73 : _GEN_4957; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4959 = 8'h4a == replaceIdReg ? dirty_74 : _GEN_4958; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4960 = 8'h4b == replaceIdReg ? dirty_75 : _GEN_4959; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4961 = 8'h4c == replaceIdReg ? dirty_76 : _GEN_4960; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4962 = 8'h4d == replaceIdReg ? dirty_77 : _GEN_4961; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4963 = 8'h4e == replaceIdReg ? dirty_78 : _GEN_4962; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4964 = 8'h4f == replaceIdReg ? dirty_79 : _GEN_4963; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4965 = 8'h50 == replaceIdReg ? dirty_80 : _GEN_4964; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4966 = 8'h51 == replaceIdReg ? dirty_81 : _GEN_4965; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4967 = 8'h52 == replaceIdReg ? dirty_82 : _GEN_4966; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4968 = 8'h53 == replaceIdReg ? dirty_83 : _GEN_4967; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4969 = 8'h54 == replaceIdReg ? dirty_84 : _GEN_4968; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4970 = 8'h55 == replaceIdReg ? dirty_85 : _GEN_4969; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4971 = 8'h56 == replaceIdReg ? dirty_86 : _GEN_4970; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4972 = 8'h57 == replaceIdReg ? dirty_87 : _GEN_4971; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4973 = 8'h58 == replaceIdReg ? dirty_88 : _GEN_4972; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4974 = 8'h59 == replaceIdReg ? dirty_89 : _GEN_4973; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4975 = 8'h5a == replaceIdReg ? dirty_90 : _GEN_4974; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4976 = 8'h5b == replaceIdReg ? dirty_91 : _GEN_4975; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4977 = 8'h5c == replaceIdReg ? dirty_92 : _GEN_4976; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4978 = 8'h5d == replaceIdReg ? dirty_93 : _GEN_4977; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4979 = 8'h5e == replaceIdReg ? dirty_94 : _GEN_4978; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4980 = 8'h5f == replaceIdReg ? dirty_95 : _GEN_4979; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4981 = 8'h60 == replaceIdReg ? dirty_96 : _GEN_4980; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4982 = 8'h61 == replaceIdReg ? dirty_97 : _GEN_4981; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4983 = 8'h62 == replaceIdReg ? dirty_98 : _GEN_4982; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4984 = 8'h63 == replaceIdReg ? dirty_99 : _GEN_4983; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4985 = 8'h64 == replaceIdReg ? dirty_100 : _GEN_4984; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4986 = 8'h65 == replaceIdReg ? dirty_101 : _GEN_4985; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4987 = 8'h66 == replaceIdReg ? dirty_102 : _GEN_4986; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4988 = 8'h67 == replaceIdReg ? dirty_103 : _GEN_4987; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4989 = 8'h68 == replaceIdReg ? dirty_104 : _GEN_4988; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4990 = 8'h69 == replaceIdReg ? dirty_105 : _GEN_4989; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4991 = 8'h6a == replaceIdReg ? dirty_106 : _GEN_4990; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4992 = 8'h6b == replaceIdReg ? dirty_107 : _GEN_4991; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4993 = 8'h6c == replaceIdReg ? dirty_108 : _GEN_4992; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4994 = 8'h6d == replaceIdReg ? dirty_109 : _GEN_4993; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4995 = 8'h6e == replaceIdReg ? dirty_110 : _GEN_4994; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4996 = 8'h6f == replaceIdReg ? dirty_111 : _GEN_4995; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4997 = 8'h70 == replaceIdReg ? dirty_112 : _GEN_4996; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4998 = 8'h71 == replaceIdReg ? dirty_113 : _GEN_4997; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_4999 = 8'h72 == replaceIdReg ? dirty_114 : _GEN_4998; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5000 = 8'h73 == replaceIdReg ? dirty_115 : _GEN_4999; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5001 = 8'h74 == replaceIdReg ? dirty_116 : _GEN_5000; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5002 = 8'h75 == replaceIdReg ? dirty_117 : _GEN_5001; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5003 = 8'h76 == replaceIdReg ? dirty_118 : _GEN_5002; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5004 = 8'h77 == replaceIdReg ? dirty_119 : _GEN_5003; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5005 = 8'h78 == replaceIdReg ? dirty_120 : _GEN_5004; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5006 = 8'h79 == replaceIdReg ? dirty_121 : _GEN_5005; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5007 = 8'h7a == replaceIdReg ? dirty_122 : _GEN_5006; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5008 = 8'h7b == replaceIdReg ? dirty_123 : _GEN_5007; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5009 = 8'h7c == replaceIdReg ? dirty_124 : _GEN_5008; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5010 = 8'h7d == replaceIdReg ? dirty_125 : _GEN_5009; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5011 = 8'h7e == replaceIdReg ? dirty_126 : _GEN_5010; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5012 = 8'h7f == replaceIdReg ? dirty_127 : _GEN_5011; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5013 = 8'h80 == replaceIdReg ? dirty_128 : _GEN_5012; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5014 = 8'h81 == replaceIdReg ? dirty_129 : _GEN_5013; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5015 = 8'h82 == replaceIdReg ? dirty_130 : _GEN_5014; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5016 = 8'h83 == replaceIdReg ? dirty_131 : _GEN_5015; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5017 = 8'h84 == replaceIdReg ? dirty_132 : _GEN_5016; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5018 = 8'h85 == replaceIdReg ? dirty_133 : _GEN_5017; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5019 = 8'h86 == replaceIdReg ? dirty_134 : _GEN_5018; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5020 = 8'h87 == replaceIdReg ? dirty_135 : _GEN_5019; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5021 = 8'h88 == replaceIdReg ? dirty_136 : _GEN_5020; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5022 = 8'h89 == replaceIdReg ? dirty_137 : _GEN_5021; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5023 = 8'h8a == replaceIdReg ? dirty_138 : _GEN_5022; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5024 = 8'h8b == replaceIdReg ? dirty_139 : _GEN_5023; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5025 = 8'h8c == replaceIdReg ? dirty_140 : _GEN_5024; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5026 = 8'h8d == replaceIdReg ? dirty_141 : _GEN_5025; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5027 = 8'h8e == replaceIdReg ? dirty_142 : _GEN_5026; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5028 = 8'h8f == replaceIdReg ? dirty_143 : _GEN_5027; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5029 = 8'h90 == replaceIdReg ? dirty_144 : _GEN_5028; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5030 = 8'h91 == replaceIdReg ? dirty_145 : _GEN_5029; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5031 = 8'h92 == replaceIdReg ? dirty_146 : _GEN_5030; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5032 = 8'h93 == replaceIdReg ? dirty_147 : _GEN_5031; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5033 = 8'h94 == replaceIdReg ? dirty_148 : _GEN_5032; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5034 = 8'h95 == replaceIdReg ? dirty_149 : _GEN_5033; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5035 = 8'h96 == replaceIdReg ? dirty_150 : _GEN_5034; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5036 = 8'h97 == replaceIdReg ? dirty_151 : _GEN_5035; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5037 = 8'h98 == replaceIdReg ? dirty_152 : _GEN_5036; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5038 = 8'h99 == replaceIdReg ? dirty_153 : _GEN_5037; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5039 = 8'h9a == replaceIdReg ? dirty_154 : _GEN_5038; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5040 = 8'h9b == replaceIdReg ? dirty_155 : _GEN_5039; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5041 = 8'h9c == replaceIdReg ? dirty_156 : _GEN_5040; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5042 = 8'h9d == replaceIdReg ? dirty_157 : _GEN_5041; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5043 = 8'h9e == replaceIdReg ? dirty_158 : _GEN_5042; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5044 = 8'h9f == replaceIdReg ? dirty_159 : _GEN_5043; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5045 = 8'ha0 == replaceIdReg ? dirty_160 : _GEN_5044; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5046 = 8'ha1 == replaceIdReg ? dirty_161 : _GEN_5045; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5047 = 8'ha2 == replaceIdReg ? dirty_162 : _GEN_5046; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5048 = 8'ha3 == replaceIdReg ? dirty_163 : _GEN_5047; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5049 = 8'ha4 == replaceIdReg ? dirty_164 : _GEN_5048; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5050 = 8'ha5 == replaceIdReg ? dirty_165 : _GEN_5049; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5051 = 8'ha6 == replaceIdReg ? dirty_166 : _GEN_5050; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5052 = 8'ha7 == replaceIdReg ? dirty_167 : _GEN_5051; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5053 = 8'ha8 == replaceIdReg ? dirty_168 : _GEN_5052; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5054 = 8'ha9 == replaceIdReg ? dirty_169 : _GEN_5053; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5055 = 8'haa == replaceIdReg ? dirty_170 : _GEN_5054; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5056 = 8'hab == replaceIdReg ? dirty_171 : _GEN_5055; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5057 = 8'hac == replaceIdReg ? dirty_172 : _GEN_5056; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5058 = 8'had == replaceIdReg ? dirty_173 : _GEN_5057; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5059 = 8'hae == replaceIdReg ? dirty_174 : _GEN_5058; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5060 = 8'haf == replaceIdReg ? dirty_175 : _GEN_5059; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5061 = 8'hb0 == replaceIdReg ? dirty_176 : _GEN_5060; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5062 = 8'hb1 == replaceIdReg ? dirty_177 : _GEN_5061; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5063 = 8'hb2 == replaceIdReg ? dirty_178 : _GEN_5062; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5064 = 8'hb3 == replaceIdReg ? dirty_179 : _GEN_5063; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5065 = 8'hb4 == replaceIdReg ? dirty_180 : _GEN_5064; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5066 = 8'hb5 == replaceIdReg ? dirty_181 : _GEN_5065; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5067 = 8'hb6 == replaceIdReg ? dirty_182 : _GEN_5066; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5068 = 8'hb7 == replaceIdReg ? dirty_183 : _GEN_5067; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5069 = 8'hb8 == replaceIdReg ? dirty_184 : _GEN_5068; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5070 = 8'hb9 == replaceIdReg ? dirty_185 : _GEN_5069; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5071 = 8'hba == replaceIdReg ? dirty_186 : _GEN_5070; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5072 = 8'hbb == replaceIdReg ? dirty_187 : _GEN_5071; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5073 = 8'hbc == replaceIdReg ? dirty_188 : _GEN_5072; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5074 = 8'hbd == replaceIdReg ? dirty_189 : _GEN_5073; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5075 = 8'hbe == replaceIdReg ? dirty_190 : _GEN_5074; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5076 = 8'hbf == replaceIdReg ? dirty_191 : _GEN_5075; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5077 = 8'hc0 == replaceIdReg ? dirty_192 : _GEN_5076; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5078 = 8'hc1 == replaceIdReg ? dirty_193 : _GEN_5077; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5079 = 8'hc2 == replaceIdReg ? dirty_194 : _GEN_5078; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5080 = 8'hc3 == replaceIdReg ? dirty_195 : _GEN_5079; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5081 = 8'hc4 == replaceIdReg ? dirty_196 : _GEN_5080; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5082 = 8'hc5 == replaceIdReg ? dirty_197 : _GEN_5081; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5083 = 8'hc6 == replaceIdReg ? dirty_198 : _GEN_5082; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5084 = 8'hc7 == replaceIdReg ? dirty_199 : _GEN_5083; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5085 = 8'hc8 == replaceIdReg ? dirty_200 : _GEN_5084; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5086 = 8'hc9 == replaceIdReg ? dirty_201 : _GEN_5085; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5087 = 8'hca == replaceIdReg ? dirty_202 : _GEN_5086; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5088 = 8'hcb == replaceIdReg ? dirty_203 : _GEN_5087; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5089 = 8'hcc == replaceIdReg ? dirty_204 : _GEN_5088; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5090 = 8'hcd == replaceIdReg ? dirty_205 : _GEN_5089; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5091 = 8'hce == replaceIdReg ? dirty_206 : _GEN_5090; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5092 = 8'hcf == replaceIdReg ? dirty_207 : _GEN_5091; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5093 = 8'hd0 == replaceIdReg ? dirty_208 : _GEN_5092; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5094 = 8'hd1 == replaceIdReg ? dirty_209 : _GEN_5093; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5095 = 8'hd2 == replaceIdReg ? dirty_210 : _GEN_5094; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5096 = 8'hd3 == replaceIdReg ? dirty_211 : _GEN_5095; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5097 = 8'hd4 == replaceIdReg ? dirty_212 : _GEN_5096; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5098 = 8'hd5 == replaceIdReg ? dirty_213 : _GEN_5097; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5099 = 8'hd6 == replaceIdReg ? dirty_214 : _GEN_5098; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5100 = 8'hd7 == replaceIdReg ? dirty_215 : _GEN_5099; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5101 = 8'hd8 == replaceIdReg ? dirty_216 : _GEN_5100; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5102 = 8'hd9 == replaceIdReg ? dirty_217 : _GEN_5101; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5103 = 8'hda == replaceIdReg ? dirty_218 : _GEN_5102; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5104 = 8'hdb == replaceIdReg ? dirty_219 : _GEN_5103; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5105 = 8'hdc == replaceIdReg ? dirty_220 : _GEN_5104; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5106 = 8'hdd == replaceIdReg ? dirty_221 : _GEN_5105; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5107 = 8'hde == replaceIdReg ? dirty_222 : _GEN_5106; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5108 = 8'hdf == replaceIdReg ? dirty_223 : _GEN_5107; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5109 = 8'he0 == replaceIdReg ? dirty_224 : _GEN_5108; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5110 = 8'he1 == replaceIdReg ? dirty_225 : _GEN_5109; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5111 = 8'he2 == replaceIdReg ? dirty_226 : _GEN_5110; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5112 = 8'he3 == replaceIdReg ? dirty_227 : _GEN_5111; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5113 = 8'he4 == replaceIdReg ? dirty_228 : _GEN_5112; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5114 = 8'he5 == replaceIdReg ? dirty_229 : _GEN_5113; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5115 = 8'he6 == replaceIdReg ? dirty_230 : _GEN_5114; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5116 = 8'he7 == replaceIdReg ? dirty_231 : _GEN_5115; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5117 = 8'he8 == replaceIdReg ? dirty_232 : _GEN_5116; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5118 = 8'he9 == replaceIdReg ? dirty_233 : _GEN_5117; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5119 = 8'hea == replaceIdReg ? dirty_234 : _GEN_5118; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5120 = 8'heb == replaceIdReg ? dirty_235 : _GEN_5119; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5121 = 8'hec == replaceIdReg ? dirty_236 : _GEN_5120; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5122 = 8'hed == replaceIdReg ? dirty_237 : _GEN_5121; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5123 = 8'hee == replaceIdReg ? dirty_238 : _GEN_5122; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5124 = 8'hef == replaceIdReg ? dirty_239 : _GEN_5123; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5125 = 8'hf0 == replaceIdReg ? dirty_240 : _GEN_5124; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5126 = 8'hf1 == replaceIdReg ? dirty_241 : _GEN_5125; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5127 = 8'hf2 == replaceIdReg ? dirty_242 : _GEN_5126; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5128 = 8'hf3 == replaceIdReg ? dirty_243 : _GEN_5127; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5129 = 8'hf4 == replaceIdReg ? dirty_244 : _GEN_5128; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5130 = 8'hf5 == replaceIdReg ? dirty_245 : _GEN_5129; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5131 = 8'hf6 == replaceIdReg ? dirty_246 : _GEN_5130; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5132 = 8'hf7 == replaceIdReg ? dirty_247 : _GEN_5131; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5133 = 8'hf8 == replaceIdReg ? dirty_248 : _GEN_5132; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5134 = 8'hf9 == replaceIdReg ? dirty_249 : _GEN_5133; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5135 = 8'hfa == replaceIdReg ? dirty_250 : _GEN_5134; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5136 = 8'hfb == replaceIdReg ? dirty_251 : _GEN_5135; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5137 = 8'hfc == replaceIdReg ? dirty_252 : _GEN_5136; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5138 = 8'hfd == replaceIdReg ? dirty_253 : _GEN_5137; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5139 = 8'hfe == replaceIdReg ? dirty_254 : _GEN_5138; // @[L1DCache.scala 592:{27,27}]
- wire _GEN_5140 = 8'hff == replaceIdReg ? dirty_255 : _GEN_5139; // @[L1DCache.scala 592:{27,27}]
- wire _T_5843 = 3'h2 == fstate; // @[L1DCache.scala 582:18]
- wire _T_5848 = 3'h3 == fstate; // @[L1DCache.scala 582:18]
- wire _T_5851 = ~axiwrite; // @[L1DCache.scala 611:13]
- wire [31:0] _GEN_5400 = 8'h1 == replaceIdReg ? camaddr_1 : camaddr_0; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5401 = 8'h2 == replaceIdReg ? camaddr_2 : _GEN_5400; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5402 = 8'h3 == replaceIdReg ? camaddr_3 : _GEN_5401; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5403 = 8'h4 == replaceIdReg ? camaddr_4 : _GEN_5402; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5404 = 8'h5 == replaceIdReg ? camaddr_5 : _GEN_5403; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5405 = 8'h6 == replaceIdReg ? camaddr_6 : _GEN_5404; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5406 = 8'h7 == replaceIdReg ? camaddr_7 : _GEN_5405; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5407 = 8'h8 == replaceIdReg ? camaddr_8 : _GEN_5406; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5408 = 8'h9 == replaceIdReg ? camaddr_9 : _GEN_5407; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5409 = 8'ha == replaceIdReg ? camaddr_10 : _GEN_5408; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5410 = 8'hb == replaceIdReg ? camaddr_11 : _GEN_5409; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5411 = 8'hc == replaceIdReg ? camaddr_12 : _GEN_5410; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5412 = 8'hd == replaceIdReg ? camaddr_13 : _GEN_5411; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5413 = 8'he == replaceIdReg ? camaddr_14 : _GEN_5412; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5414 = 8'hf == replaceIdReg ? camaddr_15 : _GEN_5413; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5415 = 8'h10 == replaceIdReg ? camaddr_16 : _GEN_5414; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5416 = 8'h11 == replaceIdReg ? camaddr_17 : _GEN_5415; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5417 = 8'h12 == replaceIdReg ? camaddr_18 : _GEN_5416; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5418 = 8'h13 == replaceIdReg ? camaddr_19 : _GEN_5417; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5419 = 8'h14 == replaceIdReg ? camaddr_20 : _GEN_5418; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5420 = 8'h15 == replaceIdReg ? camaddr_21 : _GEN_5419; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5421 = 8'h16 == replaceIdReg ? camaddr_22 : _GEN_5420; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5422 = 8'h17 == replaceIdReg ? camaddr_23 : _GEN_5421; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5423 = 8'h18 == replaceIdReg ? camaddr_24 : _GEN_5422; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5424 = 8'h19 == replaceIdReg ? camaddr_25 : _GEN_5423; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5425 = 8'h1a == replaceIdReg ? camaddr_26 : _GEN_5424; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5426 = 8'h1b == replaceIdReg ? camaddr_27 : _GEN_5425; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5427 = 8'h1c == replaceIdReg ? camaddr_28 : _GEN_5426; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5428 = 8'h1d == replaceIdReg ? camaddr_29 : _GEN_5427; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5429 = 8'h1e == replaceIdReg ? camaddr_30 : _GEN_5428; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5430 = 8'h1f == replaceIdReg ? camaddr_31 : _GEN_5429; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5431 = 8'h20 == replaceIdReg ? camaddr_32 : _GEN_5430; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5432 = 8'h21 == replaceIdReg ? camaddr_33 : _GEN_5431; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5433 = 8'h22 == replaceIdReg ? camaddr_34 : _GEN_5432; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5434 = 8'h23 == replaceIdReg ? camaddr_35 : _GEN_5433; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5435 = 8'h24 == replaceIdReg ? camaddr_36 : _GEN_5434; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5436 = 8'h25 == replaceIdReg ? camaddr_37 : _GEN_5435; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5437 = 8'h26 == replaceIdReg ? camaddr_38 : _GEN_5436; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5438 = 8'h27 == replaceIdReg ? camaddr_39 : _GEN_5437; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5439 = 8'h28 == replaceIdReg ? camaddr_40 : _GEN_5438; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5440 = 8'h29 == replaceIdReg ? camaddr_41 : _GEN_5439; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5441 = 8'h2a == replaceIdReg ? camaddr_42 : _GEN_5440; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5442 = 8'h2b == replaceIdReg ? camaddr_43 : _GEN_5441; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5443 = 8'h2c == replaceIdReg ? camaddr_44 : _GEN_5442; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5444 = 8'h2d == replaceIdReg ? camaddr_45 : _GEN_5443; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5445 = 8'h2e == replaceIdReg ? camaddr_46 : _GEN_5444; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5446 = 8'h2f == replaceIdReg ? camaddr_47 : _GEN_5445; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5447 = 8'h30 == replaceIdReg ? camaddr_48 : _GEN_5446; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5448 = 8'h31 == replaceIdReg ? camaddr_49 : _GEN_5447; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5449 = 8'h32 == replaceIdReg ? camaddr_50 : _GEN_5448; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5450 = 8'h33 == replaceIdReg ? camaddr_51 : _GEN_5449; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5451 = 8'h34 == replaceIdReg ? camaddr_52 : _GEN_5450; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5452 = 8'h35 == replaceIdReg ? camaddr_53 : _GEN_5451; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5453 = 8'h36 == replaceIdReg ? camaddr_54 : _GEN_5452; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5454 = 8'h37 == replaceIdReg ? camaddr_55 : _GEN_5453; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5455 = 8'h38 == replaceIdReg ? camaddr_56 : _GEN_5454; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5456 = 8'h39 == replaceIdReg ? camaddr_57 : _GEN_5455; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5457 = 8'h3a == replaceIdReg ? camaddr_58 : _GEN_5456; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5458 = 8'h3b == replaceIdReg ? camaddr_59 : _GEN_5457; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5459 = 8'h3c == replaceIdReg ? camaddr_60 : _GEN_5458; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5460 = 8'h3d == replaceIdReg ? camaddr_61 : _GEN_5459; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5461 = 8'h3e == replaceIdReg ? camaddr_62 : _GEN_5460; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5462 = 8'h3f == replaceIdReg ? camaddr_63 : _GEN_5461; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5463 = 8'h40 == replaceIdReg ? camaddr_64 : _GEN_5462; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5464 = 8'h41 == replaceIdReg ? camaddr_65 : _GEN_5463; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5465 = 8'h42 == replaceIdReg ? camaddr_66 : _GEN_5464; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5466 = 8'h43 == replaceIdReg ? camaddr_67 : _GEN_5465; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5467 = 8'h44 == replaceIdReg ? camaddr_68 : _GEN_5466; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5468 = 8'h45 == replaceIdReg ? camaddr_69 : _GEN_5467; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5469 = 8'h46 == replaceIdReg ? camaddr_70 : _GEN_5468; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5470 = 8'h47 == replaceIdReg ? camaddr_71 : _GEN_5469; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5471 = 8'h48 == replaceIdReg ? camaddr_72 : _GEN_5470; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5472 = 8'h49 == replaceIdReg ? camaddr_73 : _GEN_5471; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5473 = 8'h4a == replaceIdReg ? camaddr_74 : _GEN_5472; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5474 = 8'h4b == replaceIdReg ? camaddr_75 : _GEN_5473; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5475 = 8'h4c == replaceIdReg ? camaddr_76 : _GEN_5474; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5476 = 8'h4d == replaceIdReg ? camaddr_77 : _GEN_5475; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5477 = 8'h4e == replaceIdReg ? camaddr_78 : _GEN_5476; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5478 = 8'h4f == replaceIdReg ? camaddr_79 : _GEN_5477; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5479 = 8'h50 == replaceIdReg ? camaddr_80 : _GEN_5478; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5480 = 8'h51 == replaceIdReg ? camaddr_81 : _GEN_5479; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5481 = 8'h52 == replaceIdReg ? camaddr_82 : _GEN_5480; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5482 = 8'h53 == replaceIdReg ? camaddr_83 : _GEN_5481; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5483 = 8'h54 == replaceIdReg ? camaddr_84 : _GEN_5482; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5484 = 8'h55 == replaceIdReg ? camaddr_85 : _GEN_5483; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5485 = 8'h56 == replaceIdReg ? camaddr_86 : _GEN_5484; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5486 = 8'h57 == replaceIdReg ? camaddr_87 : _GEN_5485; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5487 = 8'h58 == replaceIdReg ? camaddr_88 : _GEN_5486; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5488 = 8'h59 == replaceIdReg ? camaddr_89 : _GEN_5487; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5489 = 8'h5a == replaceIdReg ? camaddr_90 : _GEN_5488; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5490 = 8'h5b == replaceIdReg ? camaddr_91 : _GEN_5489; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5491 = 8'h5c == replaceIdReg ? camaddr_92 : _GEN_5490; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5492 = 8'h5d == replaceIdReg ? camaddr_93 : _GEN_5491; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5493 = 8'h5e == replaceIdReg ? camaddr_94 : _GEN_5492; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5494 = 8'h5f == replaceIdReg ? camaddr_95 : _GEN_5493; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5495 = 8'h60 == replaceIdReg ? camaddr_96 : _GEN_5494; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5496 = 8'h61 == replaceIdReg ? camaddr_97 : _GEN_5495; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5497 = 8'h62 == replaceIdReg ? camaddr_98 : _GEN_5496; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5498 = 8'h63 == replaceIdReg ? camaddr_99 : _GEN_5497; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5499 = 8'h64 == replaceIdReg ? camaddr_100 : _GEN_5498; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5500 = 8'h65 == replaceIdReg ? camaddr_101 : _GEN_5499; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5501 = 8'h66 == replaceIdReg ? camaddr_102 : _GEN_5500; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5502 = 8'h67 == replaceIdReg ? camaddr_103 : _GEN_5501; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5503 = 8'h68 == replaceIdReg ? camaddr_104 : _GEN_5502; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5504 = 8'h69 == replaceIdReg ? camaddr_105 : _GEN_5503; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5505 = 8'h6a == replaceIdReg ? camaddr_106 : _GEN_5504; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5506 = 8'h6b == replaceIdReg ? camaddr_107 : _GEN_5505; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5507 = 8'h6c == replaceIdReg ? camaddr_108 : _GEN_5506; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5508 = 8'h6d == replaceIdReg ? camaddr_109 : _GEN_5507; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5509 = 8'h6e == replaceIdReg ? camaddr_110 : _GEN_5508; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5510 = 8'h6f == replaceIdReg ? camaddr_111 : _GEN_5509; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5511 = 8'h70 == replaceIdReg ? camaddr_112 : _GEN_5510; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5512 = 8'h71 == replaceIdReg ? camaddr_113 : _GEN_5511; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5513 = 8'h72 == replaceIdReg ? camaddr_114 : _GEN_5512; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5514 = 8'h73 == replaceIdReg ? camaddr_115 : _GEN_5513; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5515 = 8'h74 == replaceIdReg ? camaddr_116 : _GEN_5514; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5516 = 8'h75 == replaceIdReg ? camaddr_117 : _GEN_5515; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5517 = 8'h76 == replaceIdReg ? camaddr_118 : _GEN_5516; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5518 = 8'h77 == replaceIdReg ? camaddr_119 : _GEN_5517; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5519 = 8'h78 == replaceIdReg ? camaddr_120 : _GEN_5518; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5520 = 8'h79 == replaceIdReg ? camaddr_121 : _GEN_5519; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5521 = 8'h7a == replaceIdReg ? camaddr_122 : _GEN_5520; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5522 = 8'h7b == replaceIdReg ? camaddr_123 : _GEN_5521; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5523 = 8'h7c == replaceIdReg ? camaddr_124 : _GEN_5522; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5524 = 8'h7d == replaceIdReg ? camaddr_125 : _GEN_5523; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5525 = 8'h7e == replaceIdReg ? camaddr_126 : _GEN_5524; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5526 = 8'h7f == replaceIdReg ? camaddr_127 : _GEN_5525; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5527 = 8'h80 == replaceIdReg ? camaddr_128 : _GEN_5526; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5528 = 8'h81 == replaceIdReg ? camaddr_129 : _GEN_5527; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5529 = 8'h82 == replaceIdReg ? camaddr_130 : _GEN_5528; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5530 = 8'h83 == replaceIdReg ? camaddr_131 : _GEN_5529; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5531 = 8'h84 == replaceIdReg ? camaddr_132 : _GEN_5530; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5532 = 8'h85 == replaceIdReg ? camaddr_133 : _GEN_5531; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5533 = 8'h86 == replaceIdReg ? camaddr_134 : _GEN_5532; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5534 = 8'h87 == replaceIdReg ? camaddr_135 : _GEN_5533; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5535 = 8'h88 == replaceIdReg ? camaddr_136 : _GEN_5534; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5536 = 8'h89 == replaceIdReg ? camaddr_137 : _GEN_5535; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5537 = 8'h8a == replaceIdReg ? camaddr_138 : _GEN_5536; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5538 = 8'h8b == replaceIdReg ? camaddr_139 : _GEN_5537; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5539 = 8'h8c == replaceIdReg ? camaddr_140 : _GEN_5538; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5540 = 8'h8d == replaceIdReg ? camaddr_141 : _GEN_5539; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5541 = 8'h8e == replaceIdReg ? camaddr_142 : _GEN_5540; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5542 = 8'h8f == replaceIdReg ? camaddr_143 : _GEN_5541; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5543 = 8'h90 == replaceIdReg ? camaddr_144 : _GEN_5542; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5544 = 8'h91 == replaceIdReg ? camaddr_145 : _GEN_5543; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5545 = 8'h92 == replaceIdReg ? camaddr_146 : _GEN_5544; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5546 = 8'h93 == replaceIdReg ? camaddr_147 : _GEN_5545; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5547 = 8'h94 == replaceIdReg ? camaddr_148 : _GEN_5546; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5548 = 8'h95 == replaceIdReg ? camaddr_149 : _GEN_5547; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5549 = 8'h96 == replaceIdReg ? camaddr_150 : _GEN_5548; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5550 = 8'h97 == replaceIdReg ? camaddr_151 : _GEN_5549; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5551 = 8'h98 == replaceIdReg ? camaddr_152 : _GEN_5550; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5552 = 8'h99 == replaceIdReg ? camaddr_153 : _GEN_5551; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5553 = 8'h9a == replaceIdReg ? camaddr_154 : _GEN_5552; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5554 = 8'h9b == replaceIdReg ? camaddr_155 : _GEN_5553; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5555 = 8'h9c == replaceIdReg ? camaddr_156 : _GEN_5554; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5556 = 8'h9d == replaceIdReg ? camaddr_157 : _GEN_5555; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5557 = 8'h9e == replaceIdReg ? camaddr_158 : _GEN_5556; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5558 = 8'h9f == replaceIdReg ? camaddr_159 : _GEN_5557; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5559 = 8'ha0 == replaceIdReg ? camaddr_160 : _GEN_5558; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5560 = 8'ha1 == replaceIdReg ? camaddr_161 : _GEN_5559; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5561 = 8'ha2 == replaceIdReg ? camaddr_162 : _GEN_5560; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5562 = 8'ha3 == replaceIdReg ? camaddr_163 : _GEN_5561; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5563 = 8'ha4 == replaceIdReg ? camaddr_164 : _GEN_5562; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5564 = 8'ha5 == replaceIdReg ? camaddr_165 : _GEN_5563; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5565 = 8'ha6 == replaceIdReg ? camaddr_166 : _GEN_5564; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5566 = 8'ha7 == replaceIdReg ? camaddr_167 : _GEN_5565; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5567 = 8'ha8 == replaceIdReg ? camaddr_168 : _GEN_5566; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5568 = 8'ha9 == replaceIdReg ? camaddr_169 : _GEN_5567; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5569 = 8'haa == replaceIdReg ? camaddr_170 : _GEN_5568; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5570 = 8'hab == replaceIdReg ? camaddr_171 : _GEN_5569; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5571 = 8'hac == replaceIdReg ? camaddr_172 : _GEN_5570; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5572 = 8'had == replaceIdReg ? camaddr_173 : _GEN_5571; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5573 = 8'hae == replaceIdReg ? camaddr_174 : _GEN_5572; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5574 = 8'haf == replaceIdReg ? camaddr_175 : _GEN_5573; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5575 = 8'hb0 == replaceIdReg ? camaddr_176 : _GEN_5574; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5576 = 8'hb1 == replaceIdReg ? camaddr_177 : _GEN_5575; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5577 = 8'hb2 == replaceIdReg ? camaddr_178 : _GEN_5576; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5578 = 8'hb3 == replaceIdReg ? camaddr_179 : _GEN_5577; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5579 = 8'hb4 == replaceIdReg ? camaddr_180 : _GEN_5578; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5580 = 8'hb5 == replaceIdReg ? camaddr_181 : _GEN_5579; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5581 = 8'hb6 == replaceIdReg ? camaddr_182 : _GEN_5580; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5582 = 8'hb7 == replaceIdReg ? camaddr_183 : _GEN_5581; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5583 = 8'hb8 == replaceIdReg ? camaddr_184 : _GEN_5582; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5584 = 8'hb9 == replaceIdReg ? camaddr_185 : _GEN_5583; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5585 = 8'hba == replaceIdReg ? camaddr_186 : _GEN_5584; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5586 = 8'hbb == replaceIdReg ? camaddr_187 : _GEN_5585; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5587 = 8'hbc == replaceIdReg ? camaddr_188 : _GEN_5586; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5588 = 8'hbd == replaceIdReg ? camaddr_189 : _GEN_5587; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5589 = 8'hbe == replaceIdReg ? camaddr_190 : _GEN_5588; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5590 = 8'hbf == replaceIdReg ? camaddr_191 : _GEN_5589; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5591 = 8'hc0 == replaceIdReg ? camaddr_192 : _GEN_5590; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5592 = 8'hc1 == replaceIdReg ? camaddr_193 : _GEN_5591; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5593 = 8'hc2 == replaceIdReg ? camaddr_194 : _GEN_5592; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5594 = 8'hc3 == replaceIdReg ? camaddr_195 : _GEN_5593; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5595 = 8'hc4 == replaceIdReg ? camaddr_196 : _GEN_5594; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5596 = 8'hc5 == replaceIdReg ? camaddr_197 : _GEN_5595; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5597 = 8'hc6 == replaceIdReg ? camaddr_198 : _GEN_5596; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5598 = 8'hc7 == replaceIdReg ? camaddr_199 : _GEN_5597; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5599 = 8'hc8 == replaceIdReg ? camaddr_200 : _GEN_5598; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5600 = 8'hc9 == replaceIdReg ? camaddr_201 : _GEN_5599; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5601 = 8'hca == replaceIdReg ? camaddr_202 : _GEN_5600; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5602 = 8'hcb == replaceIdReg ? camaddr_203 : _GEN_5601; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5603 = 8'hcc == replaceIdReg ? camaddr_204 : _GEN_5602; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5604 = 8'hcd == replaceIdReg ? camaddr_205 : _GEN_5603; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5605 = 8'hce == replaceIdReg ? camaddr_206 : _GEN_5604; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5606 = 8'hcf == replaceIdReg ? camaddr_207 : _GEN_5605; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5607 = 8'hd0 == replaceIdReg ? camaddr_208 : _GEN_5606; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5608 = 8'hd1 == replaceIdReg ? camaddr_209 : _GEN_5607; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5609 = 8'hd2 == replaceIdReg ? camaddr_210 : _GEN_5608; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5610 = 8'hd3 == replaceIdReg ? camaddr_211 : _GEN_5609; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5611 = 8'hd4 == replaceIdReg ? camaddr_212 : _GEN_5610; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5612 = 8'hd5 == replaceIdReg ? camaddr_213 : _GEN_5611; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5613 = 8'hd6 == replaceIdReg ? camaddr_214 : _GEN_5612; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5614 = 8'hd7 == replaceIdReg ? camaddr_215 : _GEN_5613; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5615 = 8'hd8 == replaceIdReg ? camaddr_216 : _GEN_5614; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5616 = 8'hd9 == replaceIdReg ? camaddr_217 : _GEN_5615; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5617 = 8'hda == replaceIdReg ? camaddr_218 : _GEN_5616; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5618 = 8'hdb == replaceIdReg ? camaddr_219 : _GEN_5617; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5619 = 8'hdc == replaceIdReg ? camaddr_220 : _GEN_5618; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5620 = 8'hdd == replaceIdReg ? camaddr_221 : _GEN_5619; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5621 = 8'hde == replaceIdReg ? camaddr_222 : _GEN_5620; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5622 = 8'hdf == replaceIdReg ? camaddr_223 : _GEN_5621; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5623 = 8'he0 == replaceIdReg ? camaddr_224 : _GEN_5622; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5624 = 8'he1 == replaceIdReg ? camaddr_225 : _GEN_5623; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5625 = 8'he2 == replaceIdReg ? camaddr_226 : _GEN_5624; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5626 = 8'he3 == replaceIdReg ? camaddr_227 : _GEN_5625; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5627 = 8'he4 == replaceIdReg ? camaddr_228 : _GEN_5626; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5628 = 8'he5 == replaceIdReg ? camaddr_229 : _GEN_5627; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5629 = 8'he6 == replaceIdReg ? camaddr_230 : _GEN_5628; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5630 = 8'he7 == replaceIdReg ? camaddr_231 : _GEN_5629; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5631 = 8'he8 == replaceIdReg ? camaddr_232 : _GEN_5630; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5632 = 8'he9 == replaceIdReg ? camaddr_233 : _GEN_5631; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5633 = 8'hea == replaceIdReg ? camaddr_234 : _GEN_5632; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5634 = 8'heb == replaceIdReg ? camaddr_235 : _GEN_5633; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5635 = 8'hec == replaceIdReg ? camaddr_236 : _GEN_5634; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5636 = 8'hed == replaceIdReg ? camaddr_237 : _GEN_5635; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5637 = 8'hee == replaceIdReg ? camaddr_238 : _GEN_5636; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5638 = 8'hef == replaceIdReg ? camaddr_239 : _GEN_5637; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5639 = 8'hf0 == replaceIdReg ? camaddr_240 : _GEN_5638; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5640 = 8'hf1 == replaceIdReg ? camaddr_241 : _GEN_5639; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5641 = 8'hf2 == replaceIdReg ? camaddr_242 : _GEN_5640; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5642 = 8'hf3 == replaceIdReg ? camaddr_243 : _GEN_5641; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5643 = 8'hf4 == replaceIdReg ? camaddr_244 : _GEN_5642; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5644 = 8'hf5 == replaceIdReg ? camaddr_245 : _GEN_5643; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5645 = 8'hf6 == replaceIdReg ? camaddr_246 : _GEN_5644; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5646 = 8'hf7 == replaceIdReg ? camaddr_247 : _GEN_5645; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5647 = 8'hf8 == replaceIdReg ? camaddr_248 : _GEN_5646; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5648 = 8'hf9 == replaceIdReg ? camaddr_249 : _GEN_5647; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5649 = 8'hfa == replaceIdReg ? camaddr_250 : _GEN_5648; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5650 = 8'hfb == replaceIdReg ? camaddr_251 : _GEN_5649; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5651 = 8'hfc == replaceIdReg ? camaddr_252 : _GEN_5650; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5652 = 8'hfd == replaceIdReg ? camaddr_253 : _GEN_5651; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5653 = 8'hfe == replaceIdReg ? camaddr_254 : _GEN_5652; // @[L1DCache.scala 613:{16,16}]
- wire [31:0] _GEN_5654 = 8'hff == replaceIdReg ? camaddr_255 : _GEN_5653; // @[L1DCache.scala 613:{16,16}]
- wire _GEN_5655 = 8'h0 == replaceIdReg ? 1'h0 : flush_0; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5656 = 8'h1 == replaceIdReg ? 1'h0 : flush_1; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5657 = 8'h2 == replaceIdReg ? 1'h0 : flush_2; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5658 = 8'h3 == replaceIdReg ? 1'h0 : flush_3; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5659 = 8'h4 == replaceIdReg ? 1'h0 : flush_4; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5660 = 8'h5 == replaceIdReg ? 1'h0 : flush_5; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5661 = 8'h6 == replaceIdReg ? 1'h0 : flush_6; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5662 = 8'h7 == replaceIdReg ? 1'h0 : flush_7; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5663 = 8'h8 == replaceIdReg ? 1'h0 : flush_8; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5664 = 8'h9 == replaceIdReg ? 1'h0 : flush_9; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5665 = 8'ha == replaceIdReg ? 1'h0 : flush_10; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5666 = 8'hb == replaceIdReg ? 1'h0 : flush_11; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5667 = 8'hc == replaceIdReg ? 1'h0 : flush_12; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5668 = 8'hd == replaceIdReg ? 1'h0 : flush_13; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5669 = 8'he == replaceIdReg ? 1'h0 : flush_14; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5670 = 8'hf == replaceIdReg ? 1'h0 : flush_15; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5671 = 8'h10 == replaceIdReg ? 1'h0 : flush_16; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5672 = 8'h11 == replaceIdReg ? 1'h0 : flush_17; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5673 = 8'h12 == replaceIdReg ? 1'h0 : flush_18; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5674 = 8'h13 == replaceIdReg ? 1'h0 : flush_19; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5675 = 8'h14 == replaceIdReg ? 1'h0 : flush_20; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5676 = 8'h15 == replaceIdReg ? 1'h0 : flush_21; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5677 = 8'h16 == replaceIdReg ? 1'h0 : flush_22; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5678 = 8'h17 == replaceIdReg ? 1'h0 : flush_23; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5679 = 8'h18 == replaceIdReg ? 1'h0 : flush_24; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5680 = 8'h19 == replaceIdReg ? 1'h0 : flush_25; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5681 = 8'h1a == replaceIdReg ? 1'h0 : flush_26; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5682 = 8'h1b == replaceIdReg ? 1'h0 : flush_27; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5683 = 8'h1c == replaceIdReg ? 1'h0 : flush_28; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5684 = 8'h1d == replaceIdReg ? 1'h0 : flush_29; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5685 = 8'h1e == replaceIdReg ? 1'h0 : flush_30; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5686 = 8'h1f == replaceIdReg ? 1'h0 : flush_31; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5687 = 8'h20 == replaceIdReg ? 1'h0 : flush_32; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5688 = 8'h21 == replaceIdReg ? 1'h0 : flush_33; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5689 = 8'h22 == replaceIdReg ? 1'h0 : flush_34; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5690 = 8'h23 == replaceIdReg ? 1'h0 : flush_35; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5691 = 8'h24 == replaceIdReg ? 1'h0 : flush_36; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5692 = 8'h25 == replaceIdReg ? 1'h0 : flush_37; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5693 = 8'h26 == replaceIdReg ? 1'h0 : flush_38; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5694 = 8'h27 == replaceIdReg ? 1'h0 : flush_39; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5695 = 8'h28 == replaceIdReg ? 1'h0 : flush_40; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5696 = 8'h29 == replaceIdReg ? 1'h0 : flush_41; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5697 = 8'h2a == replaceIdReg ? 1'h0 : flush_42; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5698 = 8'h2b == replaceIdReg ? 1'h0 : flush_43; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5699 = 8'h2c == replaceIdReg ? 1'h0 : flush_44; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5700 = 8'h2d == replaceIdReg ? 1'h0 : flush_45; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5701 = 8'h2e == replaceIdReg ? 1'h0 : flush_46; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5702 = 8'h2f == replaceIdReg ? 1'h0 : flush_47; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5703 = 8'h30 == replaceIdReg ? 1'h0 : flush_48; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5704 = 8'h31 == replaceIdReg ? 1'h0 : flush_49; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5705 = 8'h32 == replaceIdReg ? 1'h0 : flush_50; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5706 = 8'h33 == replaceIdReg ? 1'h0 : flush_51; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5707 = 8'h34 == replaceIdReg ? 1'h0 : flush_52; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5708 = 8'h35 == replaceIdReg ? 1'h0 : flush_53; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5709 = 8'h36 == replaceIdReg ? 1'h0 : flush_54; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5710 = 8'h37 == replaceIdReg ? 1'h0 : flush_55; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5711 = 8'h38 == replaceIdReg ? 1'h0 : flush_56; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5712 = 8'h39 == replaceIdReg ? 1'h0 : flush_57; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5713 = 8'h3a == replaceIdReg ? 1'h0 : flush_58; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5714 = 8'h3b == replaceIdReg ? 1'h0 : flush_59; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5715 = 8'h3c == replaceIdReg ? 1'h0 : flush_60; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5716 = 8'h3d == replaceIdReg ? 1'h0 : flush_61; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5717 = 8'h3e == replaceIdReg ? 1'h0 : flush_62; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5718 = 8'h3f == replaceIdReg ? 1'h0 : flush_63; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5719 = 8'h40 == replaceIdReg ? 1'h0 : flush_64; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5720 = 8'h41 == replaceIdReg ? 1'h0 : flush_65; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5721 = 8'h42 == replaceIdReg ? 1'h0 : flush_66; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5722 = 8'h43 == replaceIdReg ? 1'h0 : flush_67; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5723 = 8'h44 == replaceIdReg ? 1'h0 : flush_68; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5724 = 8'h45 == replaceIdReg ? 1'h0 : flush_69; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5725 = 8'h46 == replaceIdReg ? 1'h0 : flush_70; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5726 = 8'h47 == replaceIdReg ? 1'h0 : flush_71; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5727 = 8'h48 == replaceIdReg ? 1'h0 : flush_72; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5728 = 8'h49 == replaceIdReg ? 1'h0 : flush_73; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5729 = 8'h4a == replaceIdReg ? 1'h0 : flush_74; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5730 = 8'h4b == replaceIdReg ? 1'h0 : flush_75; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5731 = 8'h4c == replaceIdReg ? 1'h0 : flush_76; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5732 = 8'h4d == replaceIdReg ? 1'h0 : flush_77; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5733 = 8'h4e == replaceIdReg ? 1'h0 : flush_78; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5734 = 8'h4f == replaceIdReg ? 1'h0 : flush_79; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5735 = 8'h50 == replaceIdReg ? 1'h0 : flush_80; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5736 = 8'h51 == replaceIdReg ? 1'h0 : flush_81; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5737 = 8'h52 == replaceIdReg ? 1'h0 : flush_82; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5738 = 8'h53 == replaceIdReg ? 1'h0 : flush_83; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5739 = 8'h54 == replaceIdReg ? 1'h0 : flush_84; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5740 = 8'h55 == replaceIdReg ? 1'h0 : flush_85; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5741 = 8'h56 == replaceIdReg ? 1'h0 : flush_86; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5742 = 8'h57 == replaceIdReg ? 1'h0 : flush_87; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5743 = 8'h58 == replaceIdReg ? 1'h0 : flush_88; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5744 = 8'h59 == replaceIdReg ? 1'h0 : flush_89; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5745 = 8'h5a == replaceIdReg ? 1'h0 : flush_90; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5746 = 8'h5b == replaceIdReg ? 1'h0 : flush_91; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5747 = 8'h5c == replaceIdReg ? 1'h0 : flush_92; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5748 = 8'h5d == replaceIdReg ? 1'h0 : flush_93; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5749 = 8'h5e == replaceIdReg ? 1'h0 : flush_94; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5750 = 8'h5f == replaceIdReg ? 1'h0 : flush_95; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5751 = 8'h60 == replaceIdReg ? 1'h0 : flush_96; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5752 = 8'h61 == replaceIdReg ? 1'h0 : flush_97; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5753 = 8'h62 == replaceIdReg ? 1'h0 : flush_98; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5754 = 8'h63 == replaceIdReg ? 1'h0 : flush_99; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5755 = 8'h64 == replaceIdReg ? 1'h0 : flush_100; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5756 = 8'h65 == replaceIdReg ? 1'h0 : flush_101; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5757 = 8'h66 == replaceIdReg ? 1'h0 : flush_102; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5758 = 8'h67 == replaceIdReg ? 1'h0 : flush_103; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5759 = 8'h68 == replaceIdReg ? 1'h0 : flush_104; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5760 = 8'h69 == replaceIdReg ? 1'h0 : flush_105; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5761 = 8'h6a == replaceIdReg ? 1'h0 : flush_106; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5762 = 8'h6b == replaceIdReg ? 1'h0 : flush_107; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5763 = 8'h6c == replaceIdReg ? 1'h0 : flush_108; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5764 = 8'h6d == replaceIdReg ? 1'h0 : flush_109; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5765 = 8'h6e == replaceIdReg ? 1'h0 : flush_110; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5766 = 8'h6f == replaceIdReg ? 1'h0 : flush_111; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5767 = 8'h70 == replaceIdReg ? 1'h0 : flush_112; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5768 = 8'h71 == replaceIdReg ? 1'h0 : flush_113; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5769 = 8'h72 == replaceIdReg ? 1'h0 : flush_114; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5770 = 8'h73 == replaceIdReg ? 1'h0 : flush_115; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5771 = 8'h74 == replaceIdReg ? 1'h0 : flush_116; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5772 = 8'h75 == replaceIdReg ? 1'h0 : flush_117; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5773 = 8'h76 == replaceIdReg ? 1'h0 : flush_118; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5774 = 8'h77 == replaceIdReg ? 1'h0 : flush_119; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5775 = 8'h78 == replaceIdReg ? 1'h0 : flush_120; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5776 = 8'h79 == replaceIdReg ? 1'h0 : flush_121; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5777 = 8'h7a == replaceIdReg ? 1'h0 : flush_122; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5778 = 8'h7b == replaceIdReg ? 1'h0 : flush_123; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5779 = 8'h7c == replaceIdReg ? 1'h0 : flush_124; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5780 = 8'h7d == replaceIdReg ? 1'h0 : flush_125; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5781 = 8'h7e == replaceIdReg ? 1'h0 : flush_126; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5782 = 8'h7f == replaceIdReg ? 1'h0 : flush_127; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5783 = 8'h80 == replaceIdReg ? 1'h0 : flush_128; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5784 = 8'h81 == replaceIdReg ? 1'h0 : flush_129; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5785 = 8'h82 == replaceIdReg ? 1'h0 : flush_130; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5786 = 8'h83 == replaceIdReg ? 1'h0 : flush_131; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5787 = 8'h84 == replaceIdReg ? 1'h0 : flush_132; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5788 = 8'h85 == replaceIdReg ? 1'h0 : flush_133; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5789 = 8'h86 == replaceIdReg ? 1'h0 : flush_134; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5790 = 8'h87 == replaceIdReg ? 1'h0 : flush_135; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5791 = 8'h88 == replaceIdReg ? 1'h0 : flush_136; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5792 = 8'h89 == replaceIdReg ? 1'h0 : flush_137; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5793 = 8'h8a == replaceIdReg ? 1'h0 : flush_138; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5794 = 8'h8b == replaceIdReg ? 1'h0 : flush_139; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5795 = 8'h8c == replaceIdReg ? 1'h0 : flush_140; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5796 = 8'h8d == replaceIdReg ? 1'h0 : flush_141; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5797 = 8'h8e == replaceIdReg ? 1'h0 : flush_142; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5798 = 8'h8f == replaceIdReg ? 1'h0 : flush_143; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5799 = 8'h90 == replaceIdReg ? 1'h0 : flush_144; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5800 = 8'h91 == replaceIdReg ? 1'h0 : flush_145; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5801 = 8'h92 == replaceIdReg ? 1'h0 : flush_146; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5802 = 8'h93 == replaceIdReg ? 1'h0 : flush_147; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5803 = 8'h94 == replaceIdReg ? 1'h0 : flush_148; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5804 = 8'h95 == replaceIdReg ? 1'h0 : flush_149; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5805 = 8'h96 == replaceIdReg ? 1'h0 : flush_150; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5806 = 8'h97 == replaceIdReg ? 1'h0 : flush_151; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5807 = 8'h98 == replaceIdReg ? 1'h0 : flush_152; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5808 = 8'h99 == replaceIdReg ? 1'h0 : flush_153; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5809 = 8'h9a == replaceIdReg ? 1'h0 : flush_154; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5810 = 8'h9b == replaceIdReg ? 1'h0 : flush_155; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5811 = 8'h9c == replaceIdReg ? 1'h0 : flush_156; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5812 = 8'h9d == replaceIdReg ? 1'h0 : flush_157; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5813 = 8'h9e == replaceIdReg ? 1'h0 : flush_158; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5814 = 8'h9f == replaceIdReg ? 1'h0 : flush_159; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5815 = 8'ha0 == replaceIdReg ? 1'h0 : flush_160; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5816 = 8'ha1 == replaceIdReg ? 1'h0 : flush_161; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5817 = 8'ha2 == replaceIdReg ? 1'h0 : flush_162; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5818 = 8'ha3 == replaceIdReg ? 1'h0 : flush_163; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5819 = 8'ha4 == replaceIdReg ? 1'h0 : flush_164; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5820 = 8'ha5 == replaceIdReg ? 1'h0 : flush_165; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5821 = 8'ha6 == replaceIdReg ? 1'h0 : flush_166; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5822 = 8'ha7 == replaceIdReg ? 1'h0 : flush_167; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5823 = 8'ha8 == replaceIdReg ? 1'h0 : flush_168; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5824 = 8'ha9 == replaceIdReg ? 1'h0 : flush_169; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5825 = 8'haa == replaceIdReg ? 1'h0 : flush_170; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5826 = 8'hab == replaceIdReg ? 1'h0 : flush_171; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5827 = 8'hac == replaceIdReg ? 1'h0 : flush_172; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5828 = 8'had == replaceIdReg ? 1'h0 : flush_173; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5829 = 8'hae == replaceIdReg ? 1'h0 : flush_174; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5830 = 8'haf == replaceIdReg ? 1'h0 : flush_175; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5831 = 8'hb0 == replaceIdReg ? 1'h0 : flush_176; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5832 = 8'hb1 == replaceIdReg ? 1'h0 : flush_177; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5833 = 8'hb2 == replaceIdReg ? 1'h0 : flush_178; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5834 = 8'hb3 == replaceIdReg ? 1'h0 : flush_179; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5835 = 8'hb4 == replaceIdReg ? 1'h0 : flush_180; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5836 = 8'hb5 == replaceIdReg ? 1'h0 : flush_181; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5837 = 8'hb6 == replaceIdReg ? 1'h0 : flush_182; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5838 = 8'hb7 == replaceIdReg ? 1'h0 : flush_183; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5839 = 8'hb8 == replaceIdReg ? 1'h0 : flush_184; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5840 = 8'hb9 == replaceIdReg ? 1'h0 : flush_185; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5841 = 8'hba == replaceIdReg ? 1'h0 : flush_186; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5842 = 8'hbb == replaceIdReg ? 1'h0 : flush_187; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5843 = 8'hbc == replaceIdReg ? 1'h0 : flush_188; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5844 = 8'hbd == replaceIdReg ? 1'h0 : flush_189; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5845 = 8'hbe == replaceIdReg ? 1'h0 : flush_190; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5846 = 8'hbf == replaceIdReg ? 1'h0 : flush_191; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5847 = 8'hc0 == replaceIdReg ? 1'h0 : flush_192; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5848 = 8'hc1 == replaceIdReg ? 1'h0 : flush_193; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5849 = 8'hc2 == replaceIdReg ? 1'h0 : flush_194; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5850 = 8'hc3 == replaceIdReg ? 1'h0 : flush_195; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5851 = 8'hc4 == replaceIdReg ? 1'h0 : flush_196; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5852 = 8'hc5 == replaceIdReg ? 1'h0 : flush_197; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5853 = 8'hc6 == replaceIdReg ? 1'h0 : flush_198; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5854 = 8'hc7 == replaceIdReg ? 1'h0 : flush_199; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5855 = 8'hc8 == replaceIdReg ? 1'h0 : flush_200; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5856 = 8'hc9 == replaceIdReg ? 1'h0 : flush_201; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5857 = 8'hca == replaceIdReg ? 1'h0 : flush_202; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5858 = 8'hcb == replaceIdReg ? 1'h0 : flush_203; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5859 = 8'hcc == replaceIdReg ? 1'h0 : flush_204; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5860 = 8'hcd == replaceIdReg ? 1'h0 : flush_205; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5861 = 8'hce == replaceIdReg ? 1'h0 : flush_206; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5862 = 8'hcf == replaceIdReg ? 1'h0 : flush_207; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5863 = 8'hd0 == replaceIdReg ? 1'h0 : flush_208; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5864 = 8'hd1 == replaceIdReg ? 1'h0 : flush_209; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5865 = 8'hd2 == replaceIdReg ? 1'h0 : flush_210; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5866 = 8'hd3 == replaceIdReg ? 1'h0 : flush_211; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5867 = 8'hd4 == replaceIdReg ? 1'h0 : flush_212; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5868 = 8'hd5 == replaceIdReg ? 1'h0 : flush_213; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5869 = 8'hd6 == replaceIdReg ? 1'h0 : flush_214; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5870 = 8'hd7 == replaceIdReg ? 1'h0 : flush_215; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5871 = 8'hd8 == replaceIdReg ? 1'h0 : flush_216; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5872 = 8'hd9 == replaceIdReg ? 1'h0 : flush_217; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5873 = 8'hda == replaceIdReg ? 1'h0 : flush_218; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5874 = 8'hdb == replaceIdReg ? 1'h0 : flush_219; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5875 = 8'hdc == replaceIdReg ? 1'h0 : flush_220; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5876 = 8'hdd == replaceIdReg ? 1'h0 : flush_221; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5877 = 8'hde == replaceIdReg ? 1'h0 : flush_222; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5878 = 8'hdf == replaceIdReg ? 1'h0 : flush_223; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5879 = 8'he0 == replaceIdReg ? 1'h0 : flush_224; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5880 = 8'he1 == replaceIdReg ? 1'h0 : flush_225; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5881 = 8'he2 == replaceIdReg ? 1'h0 : flush_226; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5882 = 8'he3 == replaceIdReg ? 1'h0 : flush_227; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5883 = 8'he4 == replaceIdReg ? 1'h0 : flush_228; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5884 = 8'he5 == replaceIdReg ? 1'h0 : flush_229; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5885 = 8'he6 == replaceIdReg ? 1'h0 : flush_230; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5886 = 8'he7 == replaceIdReg ? 1'h0 : flush_231; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5887 = 8'he8 == replaceIdReg ? 1'h0 : flush_232; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5888 = 8'he9 == replaceIdReg ? 1'h0 : flush_233; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5889 = 8'hea == replaceIdReg ? 1'h0 : flush_234; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5890 = 8'heb == replaceIdReg ? 1'h0 : flush_235; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5891 = 8'hec == replaceIdReg ? 1'h0 : flush_236; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5892 = 8'hed == replaceIdReg ? 1'h0 : flush_237; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5893 = 8'hee == replaceIdReg ? 1'h0 : flush_238; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5894 = 8'hef == replaceIdReg ? 1'h0 : flush_239; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5895 = 8'hf0 == replaceIdReg ? 1'h0 : flush_240; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5896 = 8'hf1 == replaceIdReg ? 1'h0 : flush_241; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5897 = 8'hf2 == replaceIdReg ? 1'h0 : flush_242; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5898 = 8'hf3 == replaceIdReg ? 1'h0 : flush_243; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5899 = 8'hf4 == replaceIdReg ? 1'h0 : flush_244; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5900 = 8'hf5 == replaceIdReg ? 1'h0 : flush_245; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5901 = 8'hf6 == replaceIdReg ? 1'h0 : flush_246; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5902 = 8'hf7 == replaceIdReg ? 1'h0 : flush_247; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5903 = 8'hf8 == replaceIdReg ? 1'h0 : flush_248; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5904 = 8'hf9 == replaceIdReg ? 1'h0 : flush_249; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5905 = 8'hfa == replaceIdReg ? 1'h0 : flush_250; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5906 = 8'hfb == replaceIdReg ? 1'h0 : flush_251; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5907 = 8'hfc == replaceIdReg ? 1'h0 : flush_252; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5908 = 8'hfd == replaceIdReg ? 1'h0 : flush_253; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5909 = 8'hfe == replaceIdReg ? 1'h0 : flush_254; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5910 = 8'hff == replaceIdReg ? 1'h0 : flush_255; // @[L1DCache.scala 463:22 614:{27,27}]
- wire _GEN_5911 = 8'h0 == replaceIdReg ? 1'h0 : _GEN_3847; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5912 = 8'h1 == replaceIdReg ? 1'h0 : _GEN_3848; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5913 = 8'h2 == replaceIdReg ? 1'h0 : _GEN_3849; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5914 = 8'h3 == replaceIdReg ? 1'h0 : _GEN_3850; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5915 = 8'h4 == replaceIdReg ? 1'h0 : _GEN_3851; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5916 = 8'h5 == replaceIdReg ? 1'h0 : _GEN_3852; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5917 = 8'h6 == replaceIdReg ? 1'h0 : _GEN_3853; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5918 = 8'h7 == replaceIdReg ? 1'h0 : _GEN_3854; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5919 = 8'h8 == replaceIdReg ? 1'h0 : _GEN_3855; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5920 = 8'h9 == replaceIdReg ? 1'h0 : _GEN_3856; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5921 = 8'ha == replaceIdReg ? 1'h0 : _GEN_3857; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5922 = 8'hb == replaceIdReg ? 1'h0 : _GEN_3858; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5923 = 8'hc == replaceIdReg ? 1'h0 : _GEN_3859; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5924 = 8'hd == replaceIdReg ? 1'h0 : _GEN_3860; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5925 = 8'he == replaceIdReg ? 1'h0 : _GEN_3861; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5926 = 8'hf == replaceIdReg ? 1'h0 : _GEN_3862; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5927 = 8'h10 == replaceIdReg ? 1'h0 : _GEN_3863; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5928 = 8'h11 == replaceIdReg ? 1'h0 : _GEN_3864; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5929 = 8'h12 == replaceIdReg ? 1'h0 : _GEN_3865; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5930 = 8'h13 == replaceIdReg ? 1'h0 : _GEN_3866; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5931 = 8'h14 == replaceIdReg ? 1'h0 : _GEN_3867; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5932 = 8'h15 == replaceIdReg ? 1'h0 : _GEN_3868; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5933 = 8'h16 == replaceIdReg ? 1'h0 : _GEN_3869; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5934 = 8'h17 == replaceIdReg ? 1'h0 : _GEN_3870; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5935 = 8'h18 == replaceIdReg ? 1'h0 : _GEN_3871; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5936 = 8'h19 == replaceIdReg ? 1'h0 : _GEN_3872; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5937 = 8'h1a == replaceIdReg ? 1'h0 : _GEN_3873; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5938 = 8'h1b == replaceIdReg ? 1'h0 : _GEN_3874; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5939 = 8'h1c == replaceIdReg ? 1'h0 : _GEN_3875; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5940 = 8'h1d == replaceIdReg ? 1'h0 : _GEN_3876; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5941 = 8'h1e == replaceIdReg ? 1'h0 : _GEN_3877; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5942 = 8'h1f == replaceIdReg ? 1'h0 : _GEN_3878; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5943 = 8'h20 == replaceIdReg ? 1'h0 : _GEN_3879; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5944 = 8'h21 == replaceIdReg ? 1'h0 : _GEN_3880; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5945 = 8'h22 == replaceIdReg ? 1'h0 : _GEN_3881; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5946 = 8'h23 == replaceIdReg ? 1'h0 : _GEN_3882; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5947 = 8'h24 == replaceIdReg ? 1'h0 : _GEN_3883; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5948 = 8'h25 == replaceIdReg ? 1'h0 : _GEN_3884; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5949 = 8'h26 == replaceIdReg ? 1'h0 : _GEN_3885; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5950 = 8'h27 == replaceIdReg ? 1'h0 : _GEN_3886; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5951 = 8'h28 == replaceIdReg ? 1'h0 : _GEN_3887; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5952 = 8'h29 == replaceIdReg ? 1'h0 : _GEN_3888; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5953 = 8'h2a == replaceIdReg ? 1'h0 : _GEN_3889; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5954 = 8'h2b == replaceIdReg ? 1'h0 : _GEN_3890; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5955 = 8'h2c == replaceIdReg ? 1'h0 : _GEN_3891; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5956 = 8'h2d == replaceIdReg ? 1'h0 : _GEN_3892; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5957 = 8'h2e == replaceIdReg ? 1'h0 : _GEN_3893; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5958 = 8'h2f == replaceIdReg ? 1'h0 : _GEN_3894; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5959 = 8'h30 == replaceIdReg ? 1'h0 : _GEN_3895; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5960 = 8'h31 == replaceIdReg ? 1'h0 : _GEN_3896; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5961 = 8'h32 == replaceIdReg ? 1'h0 : _GEN_3897; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5962 = 8'h33 == replaceIdReg ? 1'h0 : _GEN_3898; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5963 = 8'h34 == replaceIdReg ? 1'h0 : _GEN_3899; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5964 = 8'h35 == replaceIdReg ? 1'h0 : _GEN_3900; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5965 = 8'h36 == replaceIdReg ? 1'h0 : _GEN_3901; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5966 = 8'h37 == replaceIdReg ? 1'h0 : _GEN_3902; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5967 = 8'h38 == replaceIdReg ? 1'h0 : _GEN_3903; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5968 = 8'h39 == replaceIdReg ? 1'h0 : _GEN_3904; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5969 = 8'h3a == replaceIdReg ? 1'h0 : _GEN_3905; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5970 = 8'h3b == replaceIdReg ? 1'h0 : _GEN_3906; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5971 = 8'h3c == replaceIdReg ? 1'h0 : _GEN_3907; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5972 = 8'h3d == replaceIdReg ? 1'h0 : _GEN_3908; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5973 = 8'h3e == replaceIdReg ? 1'h0 : _GEN_3909; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5974 = 8'h3f == replaceIdReg ? 1'h0 : _GEN_3910; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5975 = 8'h40 == replaceIdReg ? 1'h0 : _GEN_3911; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5976 = 8'h41 == replaceIdReg ? 1'h0 : _GEN_3912; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5977 = 8'h42 == replaceIdReg ? 1'h0 : _GEN_3913; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5978 = 8'h43 == replaceIdReg ? 1'h0 : _GEN_3914; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5979 = 8'h44 == replaceIdReg ? 1'h0 : _GEN_3915; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5980 = 8'h45 == replaceIdReg ? 1'h0 : _GEN_3916; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5981 = 8'h46 == replaceIdReg ? 1'h0 : _GEN_3917; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5982 = 8'h47 == replaceIdReg ? 1'h0 : _GEN_3918; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5983 = 8'h48 == replaceIdReg ? 1'h0 : _GEN_3919; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5984 = 8'h49 == replaceIdReg ? 1'h0 : _GEN_3920; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5985 = 8'h4a == replaceIdReg ? 1'h0 : _GEN_3921; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5986 = 8'h4b == replaceIdReg ? 1'h0 : _GEN_3922; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5987 = 8'h4c == replaceIdReg ? 1'h0 : _GEN_3923; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5988 = 8'h4d == replaceIdReg ? 1'h0 : _GEN_3924; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5989 = 8'h4e == replaceIdReg ? 1'h0 : _GEN_3925; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5990 = 8'h4f == replaceIdReg ? 1'h0 : _GEN_3926; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5991 = 8'h50 == replaceIdReg ? 1'h0 : _GEN_3927; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5992 = 8'h51 == replaceIdReg ? 1'h0 : _GEN_3928; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5993 = 8'h52 == replaceIdReg ? 1'h0 : _GEN_3929; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5994 = 8'h53 == replaceIdReg ? 1'h0 : _GEN_3930; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5995 = 8'h54 == replaceIdReg ? 1'h0 : _GEN_3931; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5996 = 8'h55 == replaceIdReg ? 1'h0 : _GEN_3932; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5997 = 8'h56 == replaceIdReg ? 1'h0 : _GEN_3933; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5998 = 8'h57 == replaceIdReg ? 1'h0 : _GEN_3934; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_5999 = 8'h58 == replaceIdReg ? 1'h0 : _GEN_3935; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6000 = 8'h59 == replaceIdReg ? 1'h0 : _GEN_3936; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6001 = 8'h5a == replaceIdReg ? 1'h0 : _GEN_3937; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6002 = 8'h5b == replaceIdReg ? 1'h0 : _GEN_3938; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6003 = 8'h5c == replaceIdReg ? 1'h0 : _GEN_3939; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6004 = 8'h5d == replaceIdReg ? 1'h0 : _GEN_3940; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6005 = 8'h5e == replaceIdReg ? 1'h0 : _GEN_3941; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6006 = 8'h5f == replaceIdReg ? 1'h0 : _GEN_3942; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6007 = 8'h60 == replaceIdReg ? 1'h0 : _GEN_3943; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6008 = 8'h61 == replaceIdReg ? 1'h0 : _GEN_3944; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6009 = 8'h62 == replaceIdReg ? 1'h0 : _GEN_3945; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6010 = 8'h63 == replaceIdReg ? 1'h0 : _GEN_3946; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6011 = 8'h64 == replaceIdReg ? 1'h0 : _GEN_3947; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6012 = 8'h65 == replaceIdReg ? 1'h0 : _GEN_3948; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6013 = 8'h66 == replaceIdReg ? 1'h0 : _GEN_3949; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6014 = 8'h67 == replaceIdReg ? 1'h0 : _GEN_3950; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6015 = 8'h68 == replaceIdReg ? 1'h0 : _GEN_3951; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6016 = 8'h69 == replaceIdReg ? 1'h0 : _GEN_3952; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6017 = 8'h6a == replaceIdReg ? 1'h0 : _GEN_3953; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6018 = 8'h6b == replaceIdReg ? 1'h0 : _GEN_3954; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6019 = 8'h6c == replaceIdReg ? 1'h0 : _GEN_3955; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6020 = 8'h6d == replaceIdReg ? 1'h0 : _GEN_3956; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6021 = 8'h6e == replaceIdReg ? 1'h0 : _GEN_3957; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6022 = 8'h6f == replaceIdReg ? 1'h0 : _GEN_3958; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6023 = 8'h70 == replaceIdReg ? 1'h0 : _GEN_3959; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6024 = 8'h71 == replaceIdReg ? 1'h0 : _GEN_3960; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6025 = 8'h72 == replaceIdReg ? 1'h0 : _GEN_3961; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6026 = 8'h73 == replaceIdReg ? 1'h0 : _GEN_3962; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6027 = 8'h74 == replaceIdReg ? 1'h0 : _GEN_3963; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6028 = 8'h75 == replaceIdReg ? 1'h0 : _GEN_3964; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6029 = 8'h76 == replaceIdReg ? 1'h0 : _GEN_3965; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6030 = 8'h77 == replaceIdReg ? 1'h0 : _GEN_3966; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6031 = 8'h78 == replaceIdReg ? 1'h0 : _GEN_3967; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6032 = 8'h79 == replaceIdReg ? 1'h0 : _GEN_3968; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6033 = 8'h7a == replaceIdReg ? 1'h0 : _GEN_3969; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6034 = 8'h7b == replaceIdReg ? 1'h0 : _GEN_3970; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6035 = 8'h7c == replaceIdReg ? 1'h0 : _GEN_3971; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6036 = 8'h7d == replaceIdReg ? 1'h0 : _GEN_3972; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6037 = 8'h7e == replaceIdReg ? 1'h0 : _GEN_3973; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6038 = 8'h7f == replaceIdReg ? 1'h0 : _GEN_3974; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6039 = 8'h80 == replaceIdReg ? 1'h0 : _GEN_3975; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6040 = 8'h81 == replaceIdReg ? 1'h0 : _GEN_3976; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6041 = 8'h82 == replaceIdReg ? 1'h0 : _GEN_3977; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6042 = 8'h83 == replaceIdReg ? 1'h0 : _GEN_3978; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6043 = 8'h84 == replaceIdReg ? 1'h0 : _GEN_3979; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6044 = 8'h85 == replaceIdReg ? 1'h0 : _GEN_3980; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6045 = 8'h86 == replaceIdReg ? 1'h0 : _GEN_3981; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6046 = 8'h87 == replaceIdReg ? 1'h0 : _GEN_3982; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6047 = 8'h88 == replaceIdReg ? 1'h0 : _GEN_3983; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6048 = 8'h89 == replaceIdReg ? 1'h0 : _GEN_3984; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6049 = 8'h8a == replaceIdReg ? 1'h0 : _GEN_3985; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6050 = 8'h8b == replaceIdReg ? 1'h0 : _GEN_3986; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6051 = 8'h8c == replaceIdReg ? 1'h0 : _GEN_3987; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6052 = 8'h8d == replaceIdReg ? 1'h0 : _GEN_3988; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6053 = 8'h8e == replaceIdReg ? 1'h0 : _GEN_3989; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6054 = 8'h8f == replaceIdReg ? 1'h0 : _GEN_3990; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6055 = 8'h90 == replaceIdReg ? 1'h0 : _GEN_3991; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6056 = 8'h91 == replaceIdReg ? 1'h0 : _GEN_3992; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6057 = 8'h92 == replaceIdReg ? 1'h0 : _GEN_3993; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6058 = 8'h93 == replaceIdReg ? 1'h0 : _GEN_3994; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6059 = 8'h94 == replaceIdReg ? 1'h0 : _GEN_3995; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6060 = 8'h95 == replaceIdReg ? 1'h0 : _GEN_3996; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6061 = 8'h96 == replaceIdReg ? 1'h0 : _GEN_3997; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6062 = 8'h97 == replaceIdReg ? 1'h0 : _GEN_3998; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6063 = 8'h98 == replaceIdReg ? 1'h0 : _GEN_3999; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6064 = 8'h99 == replaceIdReg ? 1'h0 : _GEN_4000; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6065 = 8'h9a == replaceIdReg ? 1'h0 : _GEN_4001; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6066 = 8'h9b == replaceIdReg ? 1'h0 : _GEN_4002; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6067 = 8'h9c == replaceIdReg ? 1'h0 : _GEN_4003; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6068 = 8'h9d == replaceIdReg ? 1'h0 : _GEN_4004; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6069 = 8'h9e == replaceIdReg ? 1'h0 : _GEN_4005; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6070 = 8'h9f == replaceIdReg ? 1'h0 : _GEN_4006; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6071 = 8'ha0 == replaceIdReg ? 1'h0 : _GEN_4007; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6072 = 8'ha1 == replaceIdReg ? 1'h0 : _GEN_4008; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6073 = 8'ha2 == replaceIdReg ? 1'h0 : _GEN_4009; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6074 = 8'ha3 == replaceIdReg ? 1'h0 : _GEN_4010; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6075 = 8'ha4 == replaceIdReg ? 1'h0 : _GEN_4011; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6076 = 8'ha5 == replaceIdReg ? 1'h0 : _GEN_4012; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6077 = 8'ha6 == replaceIdReg ? 1'h0 : _GEN_4013; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6078 = 8'ha7 == replaceIdReg ? 1'h0 : _GEN_4014; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6079 = 8'ha8 == replaceIdReg ? 1'h0 : _GEN_4015; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6080 = 8'ha9 == replaceIdReg ? 1'h0 : _GEN_4016; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6081 = 8'haa == replaceIdReg ? 1'h0 : _GEN_4017; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6082 = 8'hab == replaceIdReg ? 1'h0 : _GEN_4018; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6083 = 8'hac == replaceIdReg ? 1'h0 : _GEN_4019; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6084 = 8'had == replaceIdReg ? 1'h0 : _GEN_4020; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6085 = 8'hae == replaceIdReg ? 1'h0 : _GEN_4021; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6086 = 8'haf == replaceIdReg ? 1'h0 : _GEN_4022; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6087 = 8'hb0 == replaceIdReg ? 1'h0 : _GEN_4023; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6088 = 8'hb1 == replaceIdReg ? 1'h0 : _GEN_4024; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6089 = 8'hb2 == replaceIdReg ? 1'h0 : _GEN_4025; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6090 = 8'hb3 == replaceIdReg ? 1'h0 : _GEN_4026; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6091 = 8'hb4 == replaceIdReg ? 1'h0 : _GEN_4027; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6092 = 8'hb5 == replaceIdReg ? 1'h0 : _GEN_4028; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6093 = 8'hb6 == replaceIdReg ? 1'h0 : _GEN_4029; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6094 = 8'hb7 == replaceIdReg ? 1'h0 : _GEN_4030; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6095 = 8'hb8 == replaceIdReg ? 1'h0 : _GEN_4031; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6096 = 8'hb9 == replaceIdReg ? 1'h0 : _GEN_4032; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6097 = 8'hba == replaceIdReg ? 1'h0 : _GEN_4033; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6098 = 8'hbb == replaceIdReg ? 1'h0 : _GEN_4034; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6099 = 8'hbc == replaceIdReg ? 1'h0 : _GEN_4035; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6100 = 8'hbd == replaceIdReg ? 1'h0 : _GEN_4036; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6101 = 8'hbe == replaceIdReg ? 1'h0 : _GEN_4037; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6102 = 8'hbf == replaceIdReg ? 1'h0 : _GEN_4038; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6103 = 8'hc0 == replaceIdReg ? 1'h0 : _GEN_4039; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6104 = 8'hc1 == replaceIdReg ? 1'h0 : _GEN_4040; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6105 = 8'hc2 == replaceIdReg ? 1'h0 : _GEN_4041; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6106 = 8'hc3 == replaceIdReg ? 1'h0 : _GEN_4042; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6107 = 8'hc4 == replaceIdReg ? 1'h0 : _GEN_4043; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6108 = 8'hc5 == replaceIdReg ? 1'h0 : _GEN_4044; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6109 = 8'hc6 == replaceIdReg ? 1'h0 : _GEN_4045; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6110 = 8'hc7 == replaceIdReg ? 1'h0 : _GEN_4046; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6111 = 8'hc8 == replaceIdReg ? 1'h0 : _GEN_4047; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6112 = 8'hc9 == replaceIdReg ? 1'h0 : _GEN_4048; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6113 = 8'hca == replaceIdReg ? 1'h0 : _GEN_4049; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6114 = 8'hcb == replaceIdReg ? 1'h0 : _GEN_4050; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6115 = 8'hcc == replaceIdReg ? 1'h0 : _GEN_4051; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6116 = 8'hcd == replaceIdReg ? 1'h0 : _GEN_4052; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6117 = 8'hce == replaceIdReg ? 1'h0 : _GEN_4053; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6118 = 8'hcf == replaceIdReg ? 1'h0 : _GEN_4054; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6119 = 8'hd0 == replaceIdReg ? 1'h0 : _GEN_4055; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6120 = 8'hd1 == replaceIdReg ? 1'h0 : _GEN_4056; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6121 = 8'hd2 == replaceIdReg ? 1'h0 : _GEN_4057; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6122 = 8'hd3 == replaceIdReg ? 1'h0 : _GEN_4058; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6123 = 8'hd4 == replaceIdReg ? 1'h0 : _GEN_4059; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6124 = 8'hd5 == replaceIdReg ? 1'h0 : _GEN_4060; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6125 = 8'hd6 == replaceIdReg ? 1'h0 : _GEN_4061; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6126 = 8'hd7 == replaceIdReg ? 1'h0 : _GEN_4062; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6127 = 8'hd8 == replaceIdReg ? 1'h0 : _GEN_4063; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6128 = 8'hd9 == replaceIdReg ? 1'h0 : _GEN_4064; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6129 = 8'hda == replaceIdReg ? 1'h0 : _GEN_4065; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6130 = 8'hdb == replaceIdReg ? 1'h0 : _GEN_4066; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6131 = 8'hdc == replaceIdReg ? 1'h0 : _GEN_4067; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6132 = 8'hdd == replaceIdReg ? 1'h0 : _GEN_4068; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6133 = 8'hde == replaceIdReg ? 1'h0 : _GEN_4069; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6134 = 8'hdf == replaceIdReg ? 1'h0 : _GEN_4070; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6135 = 8'he0 == replaceIdReg ? 1'h0 : _GEN_4071; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6136 = 8'he1 == replaceIdReg ? 1'h0 : _GEN_4072; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6137 = 8'he2 == replaceIdReg ? 1'h0 : _GEN_4073; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6138 = 8'he3 == replaceIdReg ? 1'h0 : _GEN_4074; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6139 = 8'he4 == replaceIdReg ? 1'h0 : _GEN_4075; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6140 = 8'he5 == replaceIdReg ? 1'h0 : _GEN_4076; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6141 = 8'he6 == replaceIdReg ? 1'h0 : _GEN_4077; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6142 = 8'he7 == replaceIdReg ? 1'h0 : _GEN_4078; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6143 = 8'he8 == replaceIdReg ? 1'h0 : _GEN_4079; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6144 = 8'he9 == replaceIdReg ? 1'h0 : _GEN_4080; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6145 = 8'hea == replaceIdReg ? 1'h0 : _GEN_4081; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6146 = 8'heb == replaceIdReg ? 1'h0 : _GEN_4082; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6147 = 8'hec == replaceIdReg ? 1'h0 : _GEN_4083; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6148 = 8'hed == replaceIdReg ? 1'h0 : _GEN_4084; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6149 = 8'hee == replaceIdReg ? 1'h0 : _GEN_4085; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6150 = 8'hef == replaceIdReg ? 1'h0 : _GEN_4086; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6151 = 8'hf0 == replaceIdReg ? 1'h0 : _GEN_4087; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6152 = 8'hf1 == replaceIdReg ? 1'h0 : _GEN_4088; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6153 = 8'hf2 == replaceIdReg ? 1'h0 : _GEN_4089; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6154 = 8'hf3 == replaceIdReg ? 1'h0 : _GEN_4090; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6155 = 8'hf4 == replaceIdReg ? 1'h0 : _GEN_4091; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6156 = 8'hf5 == replaceIdReg ? 1'h0 : _GEN_4092; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6157 = 8'hf6 == replaceIdReg ? 1'h0 : _GEN_4093; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6158 = 8'hf7 == replaceIdReg ? 1'h0 : _GEN_4094; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6159 = 8'hf8 == replaceIdReg ? 1'h0 : _GEN_4095; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6160 = 8'hf9 == replaceIdReg ? 1'h0 : _GEN_4096; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6161 = 8'hfa == replaceIdReg ? 1'h0 : _GEN_4097; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6162 = 8'hfb == replaceIdReg ? 1'h0 : _GEN_4098; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6163 = 8'hfc == replaceIdReg ? 1'h0 : _GEN_4099; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6164 = 8'hfd == replaceIdReg ? 1'h0 : _GEN_4100; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6165 = 8'hfe == replaceIdReg ? 1'h0 : _GEN_4101; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6166 = 8'hff == replaceIdReg ? 1'h0 : _GEN_4102; // @[L1DCache.scala 615:{27,27}]
- wire _GEN_6167 = 8'h0 == replaceIdReg ? 1'h0 : _GEN_4360; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6168 = 8'h1 == replaceIdReg ? 1'h0 : _GEN_4361; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6169 = 8'h2 == replaceIdReg ? 1'h0 : _GEN_4362; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6170 = 8'h3 == replaceIdReg ? 1'h0 : _GEN_4363; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6171 = 8'h4 == replaceIdReg ? 1'h0 : _GEN_4364; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6172 = 8'h5 == replaceIdReg ? 1'h0 : _GEN_4365; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6173 = 8'h6 == replaceIdReg ? 1'h0 : _GEN_4366; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6174 = 8'h7 == replaceIdReg ? 1'h0 : _GEN_4367; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6175 = 8'h8 == replaceIdReg ? 1'h0 : _GEN_4368; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6176 = 8'h9 == replaceIdReg ? 1'h0 : _GEN_4369; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6177 = 8'ha == replaceIdReg ? 1'h0 : _GEN_4370; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6178 = 8'hb == replaceIdReg ? 1'h0 : _GEN_4371; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6179 = 8'hc == replaceIdReg ? 1'h0 : _GEN_4372; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6180 = 8'hd == replaceIdReg ? 1'h0 : _GEN_4373; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6181 = 8'he == replaceIdReg ? 1'h0 : _GEN_4374; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6182 = 8'hf == replaceIdReg ? 1'h0 : _GEN_4375; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6183 = 8'h10 == replaceIdReg ? 1'h0 : _GEN_4376; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6184 = 8'h11 == replaceIdReg ? 1'h0 : _GEN_4377; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6185 = 8'h12 == replaceIdReg ? 1'h0 : _GEN_4378; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6186 = 8'h13 == replaceIdReg ? 1'h0 : _GEN_4379; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6187 = 8'h14 == replaceIdReg ? 1'h0 : _GEN_4380; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6188 = 8'h15 == replaceIdReg ? 1'h0 : _GEN_4381; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6189 = 8'h16 == replaceIdReg ? 1'h0 : _GEN_4382; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6190 = 8'h17 == replaceIdReg ? 1'h0 : _GEN_4383; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6191 = 8'h18 == replaceIdReg ? 1'h0 : _GEN_4384; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6192 = 8'h19 == replaceIdReg ? 1'h0 : _GEN_4385; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6193 = 8'h1a == replaceIdReg ? 1'h0 : _GEN_4386; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6194 = 8'h1b == replaceIdReg ? 1'h0 : _GEN_4387; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6195 = 8'h1c == replaceIdReg ? 1'h0 : _GEN_4388; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6196 = 8'h1d == replaceIdReg ? 1'h0 : _GEN_4389; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6197 = 8'h1e == replaceIdReg ? 1'h0 : _GEN_4390; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6198 = 8'h1f == replaceIdReg ? 1'h0 : _GEN_4391; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6199 = 8'h20 == replaceIdReg ? 1'h0 : _GEN_4392; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6200 = 8'h21 == replaceIdReg ? 1'h0 : _GEN_4393; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6201 = 8'h22 == replaceIdReg ? 1'h0 : _GEN_4394; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6202 = 8'h23 == replaceIdReg ? 1'h0 : _GEN_4395; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6203 = 8'h24 == replaceIdReg ? 1'h0 : _GEN_4396; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6204 = 8'h25 == replaceIdReg ? 1'h0 : _GEN_4397; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6205 = 8'h26 == replaceIdReg ? 1'h0 : _GEN_4398; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6206 = 8'h27 == replaceIdReg ? 1'h0 : _GEN_4399; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6207 = 8'h28 == replaceIdReg ? 1'h0 : _GEN_4400; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6208 = 8'h29 == replaceIdReg ? 1'h0 : _GEN_4401; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6209 = 8'h2a == replaceIdReg ? 1'h0 : _GEN_4402; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6210 = 8'h2b == replaceIdReg ? 1'h0 : _GEN_4403; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6211 = 8'h2c == replaceIdReg ? 1'h0 : _GEN_4404; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6212 = 8'h2d == replaceIdReg ? 1'h0 : _GEN_4405; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6213 = 8'h2e == replaceIdReg ? 1'h0 : _GEN_4406; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6214 = 8'h2f == replaceIdReg ? 1'h0 : _GEN_4407; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6215 = 8'h30 == replaceIdReg ? 1'h0 : _GEN_4408; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6216 = 8'h31 == replaceIdReg ? 1'h0 : _GEN_4409; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6217 = 8'h32 == replaceIdReg ? 1'h0 : _GEN_4410; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6218 = 8'h33 == replaceIdReg ? 1'h0 : _GEN_4411; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6219 = 8'h34 == replaceIdReg ? 1'h0 : _GEN_4412; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6220 = 8'h35 == replaceIdReg ? 1'h0 : _GEN_4413; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6221 = 8'h36 == replaceIdReg ? 1'h0 : _GEN_4414; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6222 = 8'h37 == replaceIdReg ? 1'h0 : _GEN_4415; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6223 = 8'h38 == replaceIdReg ? 1'h0 : _GEN_4416; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6224 = 8'h39 == replaceIdReg ? 1'h0 : _GEN_4417; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6225 = 8'h3a == replaceIdReg ? 1'h0 : _GEN_4418; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6226 = 8'h3b == replaceIdReg ? 1'h0 : _GEN_4419; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6227 = 8'h3c == replaceIdReg ? 1'h0 : _GEN_4420; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6228 = 8'h3d == replaceIdReg ? 1'h0 : _GEN_4421; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6229 = 8'h3e == replaceIdReg ? 1'h0 : _GEN_4422; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6230 = 8'h3f == replaceIdReg ? 1'h0 : _GEN_4423; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6231 = 8'h40 == replaceIdReg ? 1'h0 : _GEN_4424; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6232 = 8'h41 == replaceIdReg ? 1'h0 : _GEN_4425; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6233 = 8'h42 == replaceIdReg ? 1'h0 : _GEN_4426; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6234 = 8'h43 == replaceIdReg ? 1'h0 : _GEN_4427; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6235 = 8'h44 == replaceIdReg ? 1'h0 : _GEN_4428; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6236 = 8'h45 == replaceIdReg ? 1'h0 : _GEN_4429; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6237 = 8'h46 == replaceIdReg ? 1'h0 : _GEN_4430; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6238 = 8'h47 == replaceIdReg ? 1'h0 : _GEN_4431; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6239 = 8'h48 == replaceIdReg ? 1'h0 : _GEN_4432; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6240 = 8'h49 == replaceIdReg ? 1'h0 : _GEN_4433; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6241 = 8'h4a == replaceIdReg ? 1'h0 : _GEN_4434; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6242 = 8'h4b == replaceIdReg ? 1'h0 : _GEN_4435; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6243 = 8'h4c == replaceIdReg ? 1'h0 : _GEN_4436; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6244 = 8'h4d == replaceIdReg ? 1'h0 : _GEN_4437; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6245 = 8'h4e == replaceIdReg ? 1'h0 : _GEN_4438; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6246 = 8'h4f == replaceIdReg ? 1'h0 : _GEN_4439; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6247 = 8'h50 == replaceIdReg ? 1'h0 : _GEN_4440; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6248 = 8'h51 == replaceIdReg ? 1'h0 : _GEN_4441; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6249 = 8'h52 == replaceIdReg ? 1'h0 : _GEN_4442; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6250 = 8'h53 == replaceIdReg ? 1'h0 : _GEN_4443; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6251 = 8'h54 == replaceIdReg ? 1'h0 : _GEN_4444; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6252 = 8'h55 == replaceIdReg ? 1'h0 : _GEN_4445; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6253 = 8'h56 == replaceIdReg ? 1'h0 : _GEN_4446; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6254 = 8'h57 == replaceIdReg ? 1'h0 : _GEN_4447; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6255 = 8'h58 == replaceIdReg ? 1'h0 : _GEN_4448; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6256 = 8'h59 == replaceIdReg ? 1'h0 : _GEN_4449; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6257 = 8'h5a == replaceIdReg ? 1'h0 : _GEN_4450; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6258 = 8'h5b == replaceIdReg ? 1'h0 : _GEN_4451; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6259 = 8'h5c == replaceIdReg ? 1'h0 : _GEN_4452; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6260 = 8'h5d == replaceIdReg ? 1'h0 : _GEN_4453; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6261 = 8'h5e == replaceIdReg ? 1'h0 : _GEN_4454; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6262 = 8'h5f == replaceIdReg ? 1'h0 : _GEN_4455; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6263 = 8'h60 == replaceIdReg ? 1'h0 : _GEN_4456; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6264 = 8'h61 == replaceIdReg ? 1'h0 : _GEN_4457; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6265 = 8'h62 == replaceIdReg ? 1'h0 : _GEN_4458; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6266 = 8'h63 == replaceIdReg ? 1'h0 : _GEN_4459; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6267 = 8'h64 == replaceIdReg ? 1'h0 : _GEN_4460; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6268 = 8'h65 == replaceIdReg ? 1'h0 : _GEN_4461; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6269 = 8'h66 == replaceIdReg ? 1'h0 : _GEN_4462; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6270 = 8'h67 == replaceIdReg ? 1'h0 : _GEN_4463; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6271 = 8'h68 == replaceIdReg ? 1'h0 : _GEN_4464; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6272 = 8'h69 == replaceIdReg ? 1'h0 : _GEN_4465; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6273 = 8'h6a == replaceIdReg ? 1'h0 : _GEN_4466; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6274 = 8'h6b == replaceIdReg ? 1'h0 : _GEN_4467; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6275 = 8'h6c == replaceIdReg ? 1'h0 : _GEN_4468; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6276 = 8'h6d == replaceIdReg ? 1'h0 : _GEN_4469; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6277 = 8'h6e == replaceIdReg ? 1'h0 : _GEN_4470; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6278 = 8'h6f == replaceIdReg ? 1'h0 : _GEN_4471; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6279 = 8'h70 == replaceIdReg ? 1'h0 : _GEN_4472; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6280 = 8'h71 == replaceIdReg ? 1'h0 : _GEN_4473; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6281 = 8'h72 == replaceIdReg ? 1'h0 : _GEN_4474; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6282 = 8'h73 == replaceIdReg ? 1'h0 : _GEN_4475; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6283 = 8'h74 == replaceIdReg ? 1'h0 : _GEN_4476; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6284 = 8'h75 == replaceIdReg ? 1'h0 : _GEN_4477; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6285 = 8'h76 == replaceIdReg ? 1'h0 : _GEN_4478; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6286 = 8'h77 == replaceIdReg ? 1'h0 : _GEN_4479; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6287 = 8'h78 == replaceIdReg ? 1'h0 : _GEN_4480; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6288 = 8'h79 == replaceIdReg ? 1'h0 : _GEN_4481; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6289 = 8'h7a == replaceIdReg ? 1'h0 : _GEN_4482; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6290 = 8'h7b == replaceIdReg ? 1'h0 : _GEN_4483; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6291 = 8'h7c == replaceIdReg ? 1'h0 : _GEN_4484; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6292 = 8'h7d == replaceIdReg ? 1'h0 : _GEN_4485; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6293 = 8'h7e == replaceIdReg ? 1'h0 : _GEN_4486; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6294 = 8'h7f == replaceIdReg ? 1'h0 : _GEN_4487; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6295 = 8'h80 == replaceIdReg ? 1'h0 : _GEN_4488; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6296 = 8'h81 == replaceIdReg ? 1'h0 : _GEN_4489; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6297 = 8'h82 == replaceIdReg ? 1'h0 : _GEN_4490; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6298 = 8'h83 == replaceIdReg ? 1'h0 : _GEN_4491; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6299 = 8'h84 == replaceIdReg ? 1'h0 : _GEN_4492; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6300 = 8'h85 == replaceIdReg ? 1'h0 : _GEN_4493; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6301 = 8'h86 == replaceIdReg ? 1'h0 : _GEN_4494; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6302 = 8'h87 == replaceIdReg ? 1'h0 : _GEN_4495; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6303 = 8'h88 == replaceIdReg ? 1'h0 : _GEN_4496; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6304 = 8'h89 == replaceIdReg ? 1'h0 : _GEN_4497; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6305 = 8'h8a == replaceIdReg ? 1'h0 : _GEN_4498; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6306 = 8'h8b == replaceIdReg ? 1'h0 : _GEN_4499; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6307 = 8'h8c == replaceIdReg ? 1'h0 : _GEN_4500; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6308 = 8'h8d == replaceIdReg ? 1'h0 : _GEN_4501; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6309 = 8'h8e == replaceIdReg ? 1'h0 : _GEN_4502; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6310 = 8'h8f == replaceIdReg ? 1'h0 : _GEN_4503; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6311 = 8'h90 == replaceIdReg ? 1'h0 : _GEN_4504; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6312 = 8'h91 == replaceIdReg ? 1'h0 : _GEN_4505; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6313 = 8'h92 == replaceIdReg ? 1'h0 : _GEN_4506; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6314 = 8'h93 == replaceIdReg ? 1'h0 : _GEN_4507; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6315 = 8'h94 == replaceIdReg ? 1'h0 : _GEN_4508; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6316 = 8'h95 == replaceIdReg ? 1'h0 : _GEN_4509; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6317 = 8'h96 == replaceIdReg ? 1'h0 : _GEN_4510; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6318 = 8'h97 == replaceIdReg ? 1'h0 : _GEN_4511; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6319 = 8'h98 == replaceIdReg ? 1'h0 : _GEN_4512; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6320 = 8'h99 == replaceIdReg ? 1'h0 : _GEN_4513; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6321 = 8'h9a == replaceIdReg ? 1'h0 : _GEN_4514; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6322 = 8'h9b == replaceIdReg ? 1'h0 : _GEN_4515; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6323 = 8'h9c == replaceIdReg ? 1'h0 : _GEN_4516; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6324 = 8'h9d == replaceIdReg ? 1'h0 : _GEN_4517; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6325 = 8'h9e == replaceIdReg ? 1'h0 : _GEN_4518; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6326 = 8'h9f == replaceIdReg ? 1'h0 : _GEN_4519; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6327 = 8'ha0 == replaceIdReg ? 1'h0 : _GEN_4520; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6328 = 8'ha1 == replaceIdReg ? 1'h0 : _GEN_4521; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6329 = 8'ha2 == replaceIdReg ? 1'h0 : _GEN_4522; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6330 = 8'ha3 == replaceIdReg ? 1'h0 : _GEN_4523; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6331 = 8'ha4 == replaceIdReg ? 1'h0 : _GEN_4524; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6332 = 8'ha5 == replaceIdReg ? 1'h0 : _GEN_4525; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6333 = 8'ha6 == replaceIdReg ? 1'h0 : _GEN_4526; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6334 = 8'ha7 == replaceIdReg ? 1'h0 : _GEN_4527; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6335 = 8'ha8 == replaceIdReg ? 1'h0 : _GEN_4528; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6336 = 8'ha9 == replaceIdReg ? 1'h0 : _GEN_4529; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6337 = 8'haa == replaceIdReg ? 1'h0 : _GEN_4530; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6338 = 8'hab == replaceIdReg ? 1'h0 : _GEN_4531; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6339 = 8'hac == replaceIdReg ? 1'h0 : _GEN_4532; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6340 = 8'had == replaceIdReg ? 1'h0 : _GEN_4533; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6341 = 8'hae == replaceIdReg ? 1'h0 : _GEN_4534; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6342 = 8'haf == replaceIdReg ? 1'h0 : _GEN_4535; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6343 = 8'hb0 == replaceIdReg ? 1'h0 : _GEN_4536; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6344 = 8'hb1 == replaceIdReg ? 1'h0 : _GEN_4537; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6345 = 8'hb2 == replaceIdReg ? 1'h0 : _GEN_4538; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6346 = 8'hb3 == replaceIdReg ? 1'h0 : _GEN_4539; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6347 = 8'hb4 == replaceIdReg ? 1'h0 : _GEN_4540; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6348 = 8'hb5 == replaceIdReg ? 1'h0 : _GEN_4541; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6349 = 8'hb6 == replaceIdReg ? 1'h0 : _GEN_4542; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6350 = 8'hb7 == replaceIdReg ? 1'h0 : _GEN_4543; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6351 = 8'hb8 == replaceIdReg ? 1'h0 : _GEN_4544; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6352 = 8'hb9 == replaceIdReg ? 1'h0 : _GEN_4545; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6353 = 8'hba == replaceIdReg ? 1'h0 : _GEN_4546; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6354 = 8'hbb == replaceIdReg ? 1'h0 : _GEN_4547; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6355 = 8'hbc == replaceIdReg ? 1'h0 : _GEN_4548; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6356 = 8'hbd == replaceIdReg ? 1'h0 : _GEN_4549; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6357 = 8'hbe == replaceIdReg ? 1'h0 : _GEN_4550; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6358 = 8'hbf == replaceIdReg ? 1'h0 : _GEN_4551; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6359 = 8'hc0 == replaceIdReg ? 1'h0 : _GEN_4552; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6360 = 8'hc1 == replaceIdReg ? 1'h0 : _GEN_4553; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6361 = 8'hc2 == replaceIdReg ? 1'h0 : _GEN_4554; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6362 = 8'hc3 == replaceIdReg ? 1'h0 : _GEN_4555; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6363 = 8'hc4 == replaceIdReg ? 1'h0 : _GEN_4556; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6364 = 8'hc5 == replaceIdReg ? 1'h0 : _GEN_4557; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6365 = 8'hc6 == replaceIdReg ? 1'h0 : _GEN_4558; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6366 = 8'hc7 == replaceIdReg ? 1'h0 : _GEN_4559; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6367 = 8'hc8 == replaceIdReg ? 1'h0 : _GEN_4560; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6368 = 8'hc9 == replaceIdReg ? 1'h0 : _GEN_4561; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6369 = 8'hca == replaceIdReg ? 1'h0 : _GEN_4562; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6370 = 8'hcb == replaceIdReg ? 1'h0 : _GEN_4563; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6371 = 8'hcc == replaceIdReg ? 1'h0 : _GEN_4564; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6372 = 8'hcd == replaceIdReg ? 1'h0 : _GEN_4565; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6373 = 8'hce == replaceIdReg ? 1'h0 : _GEN_4566; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6374 = 8'hcf == replaceIdReg ? 1'h0 : _GEN_4567; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6375 = 8'hd0 == replaceIdReg ? 1'h0 : _GEN_4568; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6376 = 8'hd1 == replaceIdReg ? 1'h0 : _GEN_4569; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6377 = 8'hd2 == replaceIdReg ? 1'h0 : _GEN_4570; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6378 = 8'hd3 == replaceIdReg ? 1'h0 : _GEN_4571; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6379 = 8'hd4 == replaceIdReg ? 1'h0 : _GEN_4572; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6380 = 8'hd5 == replaceIdReg ? 1'h0 : _GEN_4573; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6381 = 8'hd6 == replaceIdReg ? 1'h0 : _GEN_4574; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6382 = 8'hd7 == replaceIdReg ? 1'h0 : _GEN_4575; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6383 = 8'hd8 == replaceIdReg ? 1'h0 : _GEN_4576; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6384 = 8'hd9 == replaceIdReg ? 1'h0 : _GEN_4577; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6385 = 8'hda == replaceIdReg ? 1'h0 : _GEN_4578; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6386 = 8'hdb == replaceIdReg ? 1'h0 : _GEN_4579; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6387 = 8'hdc == replaceIdReg ? 1'h0 : _GEN_4580; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6388 = 8'hdd == replaceIdReg ? 1'h0 : _GEN_4581; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6389 = 8'hde == replaceIdReg ? 1'h0 : _GEN_4582; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6390 = 8'hdf == replaceIdReg ? 1'h0 : _GEN_4583; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6391 = 8'he0 == replaceIdReg ? 1'h0 : _GEN_4584; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6392 = 8'he1 == replaceIdReg ? 1'h0 : _GEN_4585; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6393 = 8'he2 == replaceIdReg ? 1'h0 : _GEN_4586; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6394 = 8'he3 == replaceIdReg ? 1'h0 : _GEN_4587; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6395 = 8'he4 == replaceIdReg ? 1'h0 : _GEN_4588; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6396 = 8'he5 == replaceIdReg ? 1'h0 : _GEN_4589; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6397 = 8'he6 == replaceIdReg ? 1'h0 : _GEN_4590; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6398 = 8'he7 == replaceIdReg ? 1'h0 : _GEN_4591; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6399 = 8'he8 == replaceIdReg ? 1'h0 : _GEN_4592; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6400 = 8'he9 == replaceIdReg ? 1'h0 : _GEN_4593; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6401 = 8'hea == replaceIdReg ? 1'h0 : _GEN_4594; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6402 = 8'heb == replaceIdReg ? 1'h0 : _GEN_4595; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6403 = 8'hec == replaceIdReg ? 1'h0 : _GEN_4596; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6404 = 8'hed == replaceIdReg ? 1'h0 : _GEN_4597; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6405 = 8'hee == replaceIdReg ? 1'h0 : _GEN_4598; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6406 = 8'hef == replaceIdReg ? 1'h0 : _GEN_4599; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6407 = 8'hf0 == replaceIdReg ? 1'h0 : _GEN_4600; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6408 = 8'hf1 == replaceIdReg ? 1'h0 : _GEN_4601; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6409 = 8'hf2 == replaceIdReg ? 1'h0 : _GEN_4602; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6410 = 8'hf3 == replaceIdReg ? 1'h0 : _GEN_4603; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6411 = 8'hf4 == replaceIdReg ? 1'h0 : _GEN_4604; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6412 = 8'hf5 == replaceIdReg ? 1'h0 : _GEN_4605; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6413 = 8'hf6 == replaceIdReg ? 1'h0 : _GEN_4606; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6414 = 8'hf7 == replaceIdReg ? 1'h0 : _GEN_4607; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6415 = 8'hf8 == replaceIdReg ? 1'h0 : _GEN_4608; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6416 = 8'hf9 == replaceIdReg ? 1'h0 : _GEN_4609; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6417 = 8'hfa == replaceIdReg ? 1'h0 : _GEN_4610; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6418 = 8'hfb == replaceIdReg ? 1'h0 : _GEN_4611; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6419 = 8'hfc == replaceIdReg ? 1'h0 : _GEN_4612; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6420 = 8'hfd == replaceIdReg ? 1'h0 : _GEN_4613; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6421 = 8'hfe == replaceIdReg ? 1'h0 : _GEN_4614; // @[L1DCache.scala 617:{29,29}]
- wire _GEN_6422 = 8'hff == replaceIdReg ? 1'h0 : _GEN_4615; // @[L1DCache.scala 617:{29,29}]
- wire _T_5854 = 3'h4 == fstate; // @[L1DCache.scala 582:18]
- wire _T_5860 = 3'h5 == fstate; // @[L1DCache.scala 582:18]
- wire _T_5866 = _T_5832 | _T_4259; // @[L1DCache.scala 628:29]
- wire _T_5867 = (_T_5830 | _T_4258) & _T_5866; // @[L1DCache.scala 627:84]
- wire [2:0] _GEN_6679 = _T_5867 ? 3'h2 : fstate; // @[L1DCache.scala 628:85 629:16 462:23]
- wire _T_5870 = 3'h6 == fstate; // @[L1DCache.scala 582:18]
- wire [2:0] _GEN_6680 = wrespcnt == 9'h0 ? 3'h7 : fstate; // @[L1DCache.scala 634:31 635:16 462:23]
- wire _T_5874 = 3'h7 == fstate; // @[L1DCache.scala 582:18]
- wire [2:0] _GEN_6681 = io_flush_ready & ~io_flush_valid ? 3'h0 : fstate; // @[L1DCache.scala 641:48 642:16 462:23]
- wire _GEN_6682 = io_flush_all ? 1'h0 : _GEN_4360; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6683 = io_flush_all ? 1'h0 : _GEN_4361; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6684 = io_flush_all ? 1'h0 : _GEN_4362; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6685 = io_flush_all ? 1'h0 : _GEN_4363; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6686 = io_flush_all ? 1'h0 : _GEN_4364; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6687 = io_flush_all ? 1'h0 : _GEN_4365; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6688 = io_flush_all ? 1'h0 : _GEN_4366; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6689 = io_flush_all ? 1'h0 : _GEN_4367; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6690 = io_flush_all ? 1'h0 : _GEN_4368; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6691 = io_flush_all ? 1'h0 : _GEN_4369; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6692 = io_flush_all ? 1'h0 : _GEN_4370; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6693 = io_flush_all ? 1'h0 : _GEN_4371; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6694 = io_flush_all ? 1'h0 : _GEN_4372; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6695 = io_flush_all ? 1'h0 : _GEN_4373; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6696 = io_flush_all ? 1'h0 : _GEN_4374; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6697 = io_flush_all ? 1'h0 : _GEN_4375; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6698 = io_flush_all ? 1'h0 : _GEN_4376; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6699 = io_flush_all ? 1'h0 : _GEN_4377; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6700 = io_flush_all ? 1'h0 : _GEN_4378; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6701 = io_flush_all ? 1'h0 : _GEN_4379; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6702 = io_flush_all ? 1'h0 : _GEN_4380; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6703 = io_flush_all ? 1'h0 : _GEN_4381; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6704 = io_flush_all ? 1'h0 : _GEN_4382; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6705 = io_flush_all ? 1'h0 : _GEN_4383; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6706 = io_flush_all ? 1'h0 : _GEN_4384; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6707 = io_flush_all ? 1'h0 : _GEN_4385; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6708 = io_flush_all ? 1'h0 : _GEN_4386; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6709 = io_flush_all ? 1'h0 : _GEN_4387; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6710 = io_flush_all ? 1'h0 : _GEN_4388; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6711 = io_flush_all ? 1'h0 : _GEN_4389; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6712 = io_flush_all ? 1'h0 : _GEN_4390; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6713 = io_flush_all ? 1'h0 : _GEN_4391; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6714 = io_flush_all ? 1'h0 : _GEN_4392; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6715 = io_flush_all ? 1'h0 : _GEN_4393; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6716 = io_flush_all ? 1'h0 : _GEN_4394; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6717 = io_flush_all ? 1'h0 : _GEN_4395; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6718 = io_flush_all ? 1'h0 : _GEN_4396; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6719 = io_flush_all ? 1'h0 : _GEN_4397; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6720 = io_flush_all ? 1'h0 : _GEN_4398; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6721 = io_flush_all ? 1'h0 : _GEN_4399; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6722 = io_flush_all ? 1'h0 : _GEN_4400; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6723 = io_flush_all ? 1'h0 : _GEN_4401; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6724 = io_flush_all ? 1'h0 : _GEN_4402; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6725 = io_flush_all ? 1'h0 : _GEN_4403; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6726 = io_flush_all ? 1'h0 : _GEN_4404; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6727 = io_flush_all ? 1'h0 : _GEN_4405; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6728 = io_flush_all ? 1'h0 : _GEN_4406; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6729 = io_flush_all ? 1'h0 : _GEN_4407; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6730 = io_flush_all ? 1'h0 : _GEN_4408; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6731 = io_flush_all ? 1'h0 : _GEN_4409; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6732 = io_flush_all ? 1'h0 : _GEN_4410; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6733 = io_flush_all ? 1'h0 : _GEN_4411; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6734 = io_flush_all ? 1'h0 : _GEN_4412; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6735 = io_flush_all ? 1'h0 : _GEN_4413; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6736 = io_flush_all ? 1'h0 : _GEN_4414; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6737 = io_flush_all ? 1'h0 : _GEN_4415; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6738 = io_flush_all ? 1'h0 : _GEN_4416; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6739 = io_flush_all ? 1'h0 : _GEN_4417; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6740 = io_flush_all ? 1'h0 : _GEN_4418; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6741 = io_flush_all ? 1'h0 : _GEN_4419; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6742 = io_flush_all ? 1'h0 : _GEN_4420; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6743 = io_flush_all ? 1'h0 : _GEN_4421; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6744 = io_flush_all ? 1'h0 : _GEN_4422; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6745 = io_flush_all ? 1'h0 : _GEN_4423; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6746 = io_flush_all ? 1'h0 : _GEN_4424; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6747 = io_flush_all ? 1'h0 : _GEN_4425; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6748 = io_flush_all ? 1'h0 : _GEN_4426; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6749 = io_flush_all ? 1'h0 : _GEN_4427; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6750 = io_flush_all ? 1'h0 : _GEN_4428; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6751 = io_flush_all ? 1'h0 : _GEN_4429; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6752 = io_flush_all ? 1'h0 : _GEN_4430; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6753 = io_flush_all ? 1'h0 : _GEN_4431; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6754 = io_flush_all ? 1'h0 : _GEN_4432; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6755 = io_flush_all ? 1'h0 : _GEN_4433; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6756 = io_flush_all ? 1'h0 : _GEN_4434; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6757 = io_flush_all ? 1'h0 : _GEN_4435; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6758 = io_flush_all ? 1'h0 : _GEN_4436; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6759 = io_flush_all ? 1'h0 : _GEN_4437; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6760 = io_flush_all ? 1'h0 : _GEN_4438; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6761 = io_flush_all ? 1'h0 : _GEN_4439; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6762 = io_flush_all ? 1'h0 : _GEN_4440; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6763 = io_flush_all ? 1'h0 : _GEN_4441; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6764 = io_flush_all ? 1'h0 : _GEN_4442; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6765 = io_flush_all ? 1'h0 : _GEN_4443; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6766 = io_flush_all ? 1'h0 : _GEN_4444; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6767 = io_flush_all ? 1'h0 : _GEN_4445; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6768 = io_flush_all ? 1'h0 : _GEN_4446; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6769 = io_flush_all ? 1'h0 : _GEN_4447; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6770 = io_flush_all ? 1'h0 : _GEN_4448; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6771 = io_flush_all ? 1'h0 : _GEN_4449; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6772 = io_flush_all ? 1'h0 : _GEN_4450; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6773 = io_flush_all ? 1'h0 : _GEN_4451; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6774 = io_flush_all ? 1'h0 : _GEN_4452; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6775 = io_flush_all ? 1'h0 : _GEN_4453; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6776 = io_flush_all ? 1'h0 : _GEN_4454; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6777 = io_flush_all ? 1'h0 : _GEN_4455; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6778 = io_flush_all ? 1'h0 : _GEN_4456; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6779 = io_flush_all ? 1'h0 : _GEN_4457; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6780 = io_flush_all ? 1'h0 : _GEN_4458; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6781 = io_flush_all ? 1'h0 : _GEN_4459; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6782 = io_flush_all ? 1'h0 : _GEN_4460; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6783 = io_flush_all ? 1'h0 : _GEN_4461; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6784 = io_flush_all ? 1'h0 : _GEN_4462; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6785 = io_flush_all ? 1'h0 : _GEN_4463; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6786 = io_flush_all ? 1'h0 : _GEN_4464; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6787 = io_flush_all ? 1'h0 : _GEN_4465; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6788 = io_flush_all ? 1'h0 : _GEN_4466; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6789 = io_flush_all ? 1'h0 : _GEN_4467; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6790 = io_flush_all ? 1'h0 : _GEN_4468; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6791 = io_flush_all ? 1'h0 : _GEN_4469; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6792 = io_flush_all ? 1'h0 : _GEN_4470; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6793 = io_flush_all ? 1'h0 : _GEN_4471; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6794 = io_flush_all ? 1'h0 : _GEN_4472; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6795 = io_flush_all ? 1'h0 : _GEN_4473; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6796 = io_flush_all ? 1'h0 : _GEN_4474; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6797 = io_flush_all ? 1'h0 : _GEN_4475; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6798 = io_flush_all ? 1'h0 : _GEN_4476; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6799 = io_flush_all ? 1'h0 : _GEN_4477; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6800 = io_flush_all ? 1'h0 : _GEN_4478; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6801 = io_flush_all ? 1'h0 : _GEN_4479; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6802 = io_flush_all ? 1'h0 : _GEN_4480; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6803 = io_flush_all ? 1'h0 : _GEN_4481; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6804 = io_flush_all ? 1'h0 : _GEN_4482; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6805 = io_flush_all ? 1'h0 : _GEN_4483; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6806 = io_flush_all ? 1'h0 : _GEN_4484; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6807 = io_flush_all ? 1'h0 : _GEN_4485; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6808 = io_flush_all ? 1'h0 : _GEN_4486; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6809 = io_flush_all ? 1'h0 : _GEN_4487; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6810 = io_flush_all ? 1'h0 : _GEN_4488; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6811 = io_flush_all ? 1'h0 : _GEN_4489; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6812 = io_flush_all ? 1'h0 : _GEN_4490; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6813 = io_flush_all ? 1'h0 : _GEN_4491; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6814 = io_flush_all ? 1'h0 : _GEN_4492; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6815 = io_flush_all ? 1'h0 : _GEN_4493; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6816 = io_flush_all ? 1'h0 : _GEN_4494; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6817 = io_flush_all ? 1'h0 : _GEN_4495; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6818 = io_flush_all ? 1'h0 : _GEN_4496; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6819 = io_flush_all ? 1'h0 : _GEN_4497; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6820 = io_flush_all ? 1'h0 : _GEN_4498; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6821 = io_flush_all ? 1'h0 : _GEN_4499; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6822 = io_flush_all ? 1'h0 : _GEN_4500; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6823 = io_flush_all ? 1'h0 : _GEN_4501; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6824 = io_flush_all ? 1'h0 : _GEN_4502; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6825 = io_flush_all ? 1'h0 : _GEN_4503; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6826 = io_flush_all ? 1'h0 : _GEN_4504; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6827 = io_flush_all ? 1'h0 : _GEN_4505; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6828 = io_flush_all ? 1'h0 : _GEN_4506; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6829 = io_flush_all ? 1'h0 : _GEN_4507; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6830 = io_flush_all ? 1'h0 : _GEN_4508; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6831 = io_flush_all ? 1'h0 : _GEN_4509; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6832 = io_flush_all ? 1'h0 : _GEN_4510; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6833 = io_flush_all ? 1'h0 : _GEN_4511; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6834 = io_flush_all ? 1'h0 : _GEN_4512; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6835 = io_flush_all ? 1'h0 : _GEN_4513; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6836 = io_flush_all ? 1'h0 : _GEN_4514; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6837 = io_flush_all ? 1'h0 : _GEN_4515; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6838 = io_flush_all ? 1'h0 : _GEN_4516; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6839 = io_flush_all ? 1'h0 : _GEN_4517; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6840 = io_flush_all ? 1'h0 : _GEN_4518; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6841 = io_flush_all ? 1'h0 : _GEN_4519; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6842 = io_flush_all ? 1'h0 : _GEN_4520; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6843 = io_flush_all ? 1'h0 : _GEN_4521; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6844 = io_flush_all ? 1'h0 : _GEN_4522; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6845 = io_flush_all ? 1'h0 : _GEN_4523; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6846 = io_flush_all ? 1'h0 : _GEN_4524; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6847 = io_flush_all ? 1'h0 : _GEN_4525; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6848 = io_flush_all ? 1'h0 : _GEN_4526; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6849 = io_flush_all ? 1'h0 : _GEN_4527; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6850 = io_flush_all ? 1'h0 : _GEN_4528; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6851 = io_flush_all ? 1'h0 : _GEN_4529; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6852 = io_flush_all ? 1'h0 : _GEN_4530; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6853 = io_flush_all ? 1'h0 : _GEN_4531; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6854 = io_flush_all ? 1'h0 : _GEN_4532; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6855 = io_flush_all ? 1'h0 : _GEN_4533; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6856 = io_flush_all ? 1'h0 : _GEN_4534; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6857 = io_flush_all ? 1'h0 : _GEN_4535; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6858 = io_flush_all ? 1'h0 : _GEN_4536; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6859 = io_flush_all ? 1'h0 : _GEN_4537; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6860 = io_flush_all ? 1'h0 : _GEN_4538; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6861 = io_flush_all ? 1'h0 : _GEN_4539; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6862 = io_flush_all ? 1'h0 : _GEN_4540; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6863 = io_flush_all ? 1'h0 : _GEN_4541; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6864 = io_flush_all ? 1'h0 : _GEN_4542; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6865 = io_flush_all ? 1'h0 : _GEN_4543; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6866 = io_flush_all ? 1'h0 : _GEN_4544; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6867 = io_flush_all ? 1'h0 : _GEN_4545; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6868 = io_flush_all ? 1'h0 : _GEN_4546; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6869 = io_flush_all ? 1'h0 : _GEN_4547; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6870 = io_flush_all ? 1'h0 : _GEN_4548; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6871 = io_flush_all ? 1'h0 : _GEN_4549; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6872 = io_flush_all ? 1'h0 : _GEN_4550; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6873 = io_flush_all ? 1'h0 : _GEN_4551; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6874 = io_flush_all ? 1'h0 : _GEN_4552; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6875 = io_flush_all ? 1'h0 : _GEN_4553; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6876 = io_flush_all ? 1'h0 : _GEN_4554; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6877 = io_flush_all ? 1'h0 : _GEN_4555; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6878 = io_flush_all ? 1'h0 : _GEN_4556; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6879 = io_flush_all ? 1'h0 : _GEN_4557; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6880 = io_flush_all ? 1'h0 : _GEN_4558; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6881 = io_flush_all ? 1'h0 : _GEN_4559; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6882 = io_flush_all ? 1'h0 : _GEN_4560; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6883 = io_flush_all ? 1'h0 : _GEN_4561; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6884 = io_flush_all ? 1'h0 : _GEN_4562; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6885 = io_flush_all ? 1'h0 : _GEN_4563; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6886 = io_flush_all ? 1'h0 : _GEN_4564; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6887 = io_flush_all ? 1'h0 : _GEN_4565; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6888 = io_flush_all ? 1'h0 : _GEN_4566; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6889 = io_flush_all ? 1'h0 : _GEN_4567; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6890 = io_flush_all ? 1'h0 : _GEN_4568; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6891 = io_flush_all ? 1'h0 : _GEN_4569; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6892 = io_flush_all ? 1'h0 : _GEN_4570; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6893 = io_flush_all ? 1'h0 : _GEN_4571; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6894 = io_flush_all ? 1'h0 : _GEN_4572; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6895 = io_flush_all ? 1'h0 : _GEN_4573; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6896 = io_flush_all ? 1'h0 : _GEN_4574; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6897 = io_flush_all ? 1'h0 : _GEN_4575; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6898 = io_flush_all ? 1'h0 : _GEN_4576; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6899 = io_flush_all ? 1'h0 : _GEN_4577; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6900 = io_flush_all ? 1'h0 : _GEN_4578; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6901 = io_flush_all ? 1'h0 : _GEN_4579; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6902 = io_flush_all ? 1'h0 : _GEN_4580; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6903 = io_flush_all ? 1'h0 : _GEN_4581; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6904 = io_flush_all ? 1'h0 : _GEN_4582; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6905 = io_flush_all ? 1'h0 : _GEN_4583; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6906 = io_flush_all ? 1'h0 : _GEN_4584; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6907 = io_flush_all ? 1'h0 : _GEN_4585; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6908 = io_flush_all ? 1'h0 : _GEN_4586; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6909 = io_flush_all ? 1'h0 : _GEN_4587; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6910 = io_flush_all ? 1'h0 : _GEN_4588; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6911 = io_flush_all ? 1'h0 : _GEN_4589; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6912 = io_flush_all ? 1'h0 : _GEN_4590; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6913 = io_flush_all ? 1'h0 : _GEN_4591; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6914 = io_flush_all ? 1'h0 : _GEN_4592; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6915 = io_flush_all ? 1'h0 : _GEN_4593; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6916 = io_flush_all ? 1'h0 : _GEN_4594; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6917 = io_flush_all ? 1'h0 : _GEN_4595; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6918 = io_flush_all ? 1'h0 : _GEN_4596; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6919 = io_flush_all ? 1'h0 : _GEN_4597; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6920 = io_flush_all ? 1'h0 : _GEN_4598; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6921 = io_flush_all ? 1'h0 : _GEN_4599; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6922 = io_flush_all ? 1'h0 : _GEN_4600; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6923 = io_flush_all ? 1'h0 : _GEN_4601; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6924 = io_flush_all ? 1'h0 : _GEN_4602; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6925 = io_flush_all ? 1'h0 : _GEN_4603; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6926 = io_flush_all ? 1'h0 : _GEN_4604; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6927 = io_flush_all ? 1'h0 : _GEN_4605; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6928 = io_flush_all ? 1'h0 : _GEN_4606; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6929 = io_flush_all ? 1'h0 : _GEN_4607; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6930 = io_flush_all ? 1'h0 : _GEN_4608; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6931 = io_flush_all ? 1'h0 : _GEN_4609; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6932 = io_flush_all ? 1'h0 : _GEN_4610; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6933 = io_flush_all ? 1'h0 : _GEN_4611; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6934 = io_flush_all ? 1'h0 : _GEN_4612; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6935 = io_flush_all ? 1'h0 : _GEN_4613; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6936 = io_flush_all ? 1'h0 : _GEN_4614; // @[L1DCache.scala 645:29 647:22]
- wire _GEN_6937 = io_flush_all ? 1'h0 : _GEN_4615; // @[L1DCache.scala 645:29 647:22]
- wire [2:0] _GEN_7194 = 3'h7 == fstate ? _GEN_6681 : fstate; // @[L1DCache.scala 582:18 462:23]
- wire _GEN_7195 = 3'h7 == fstate ? _GEN_6682 : _GEN_4360; // @[L1DCache.scala 582:18]
- wire _GEN_7196 = 3'h7 == fstate ? _GEN_6683 : _GEN_4361; // @[L1DCache.scala 582:18]
- wire _GEN_7197 = 3'h7 == fstate ? _GEN_6684 : _GEN_4362; // @[L1DCache.scala 582:18]
- wire _GEN_7198 = 3'h7 == fstate ? _GEN_6685 : _GEN_4363; // @[L1DCache.scala 582:18]
- wire _GEN_7199 = 3'h7 == fstate ? _GEN_6686 : _GEN_4364; // @[L1DCache.scala 582:18]
- wire _GEN_7200 = 3'h7 == fstate ? _GEN_6687 : _GEN_4365; // @[L1DCache.scala 582:18]
- wire _GEN_7201 = 3'h7 == fstate ? _GEN_6688 : _GEN_4366; // @[L1DCache.scala 582:18]
- wire _GEN_7202 = 3'h7 == fstate ? _GEN_6689 : _GEN_4367; // @[L1DCache.scala 582:18]
- wire _GEN_7203 = 3'h7 == fstate ? _GEN_6690 : _GEN_4368; // @[L1DCache.scala 582:18]
- wire _GEN_7204 = 3'h7 == fstate ? _GEN_6691 : _GEN_4369; // @[L1DCache.scala 582:18]
- wire _GEN_7205 = 3'h7 == fstate ? _GEN_6692 : _GEN_4370; // @[L1DCache.scala 582:18]
- wire _GEN_7206 = 3'h7 == fstate ? _GEN_6693 : _GEN_4371; // @[L1DCache.scala 582:18]
- wire _GEN_7207 = 3'h7 == fstate ? _GEN_6694 : _GEN_4372; // @[L1DCache.scala 582:18]
- wire _GEN_7208 = 3'h7 == fstate ? _GEN_6695 : _GEN_4373; // @[L1DCache.scala 582:18]
- wire _GEN_7209 = 3'h7 == fstate ? _GEN_6696 : _GEN_4374; // @[L1DCache.scala 582:18]
- wire _GEN_7210 = 3'h7 == fstate ? _GEN_6697 : _GEN_4375; // @[L1DCache.scala 582:18]
- wire _GEN_7211 = 3'h7 == fstate ? _GEN_6698 : _GEN_4376; // @[L1DCache.scala 582:18]
- wire _GEN_7212 = 3'h7 == fstate ? _GEN_6699 : _GEN_4377; // @[L1DCache.scala 582:18]
- wire _GEN_7213 = 3'h7 == fstate ? _GEN_6700 : _GEN_4378; // @[L1DCache.scala 582:18]
- wire _GEN_7214 = 3'h7 == fstate ? _GEN_6701 : _GEN_4379; // @[L1DCache.scala 582:18]
- wire _GEN_7215 = 3'h7 == fstate ? _GEN_6702 : _GEN_4380; // @[L1DCache.scala 582:18]
- wire _GEN_7216 = 3'h7 == fstate ? _GEN_6703 : _GEN_4381; // @[L1DCache.scala 582:18]
- wire _GEN_7217 = 3'h7 == fstate ? _GEN_6704 : _GEN_4382; // @[L1DCache.scala 582:18]
- wire _GEN_7218 = 3'h7 == fstate ? _GEN_6705 : _GEN_4383; // @[L1DCache.scala 582:18]
- wire _GEN_7219 = 3'h7 == fstate ? _GEN_6706 : _GEN_4384; // @[L1DCache.scala 582:18]
- wire _GEN_7220 = 3'h7 == fstate ? _GEN_6707 : _GEN_4385; // @[L1DCache.scala 582:18]
- wire _GEN_7221 = 3'h7 == fstate ? _GEN_6708 : _GEN_4386; // @[L1DCache.scala 582:18]
- wire _GEN_7222 = 3'h7 == fstate ? _GEN_6709 : _GEN_4387; // @[L1DCache.scala 582:18]
- wire _GEN_7223 = 3'h7 == fstate ? _GEN_6710 : _GEN_4388; // @[L1DCache.scala 582:18]
- wire _GEN_7224 = 3'h7 == fstate ? _GEN_6711 : _GEN_4389; // @[L1DCache.scala 582:18]
- wire _GEN_7225 = 3'h7 == fstate ? _GEN_6712 : _GEN_4390; // @[L1DCache.scala 582:18]
- wire _GEN_7226 = 3'h7 == fstate ? _GEN_6713 : _GEN_4391; // @[L1DCache.scala 582:18]
- wire _GEN_7227 = 3'h7 == fstate ? _GEN_6714 : _GEN_4392; // @[L1DCache.scala 582:18]
- wire _GEN_7228 = 3'h7 == fstate ? _GEN_6715 : _GEN_4393; // @[L1DCache.scala 582:18]
- wire _GEN_7229 = 3'h7 == fstate ? _GEN_6716 : _GEN_4394; // @[L1DCache.scala 582:18]
- wire _GEN_7230 = 3'h7 == fstate ? _GEN_6717 : _GEN_4395; // @[L1DCache.scala 582:18]
- wire _GEN_7231 = 3'h7 == fstate ? _GEN_6718 : _GEN_4396; // @[L1DCache.scala 582:18]
- wire _GEN_7232 = 3'h7 == fstate ? _GEN_6719 : _GEN_4397; // @[L1DCache.scala 582:18]
- wire _GEN_7233 = 3'h7 == fstate ? _GEN_6720 : _GEN_4398; // @[L1DCache.scala 582:18]
- wire _GEN_7234 = 3'h7 == fstate ? _GEN_6721 : _GEN_4399; // @[L1DCache.scala 582:18]
- wire _GEN_7235 = 3'h7 == fstate ? _GEN_6722 : _GEN_4400; // @[L1DCache.scala 582:18]
- wire _GEN_7236 = 3'h7 == fstate ? _GEN_6723 : _GEN_4401; // @[L1DCache.scala 582:18]
- wire _GEN_7237 = 3'h7 == fstate ? _GEN_6724 : _GEN_4402; // @[L1DCache.scala 582:18]
- wire _GEN_7238 = 3'h7 == fstate ? _GEN_6725 : _GEN_4403; // @[L1DCache.scala 582:18]
- wire _GEN_7239 = 3'h7 == fstate ? _GEN_6726 : _GEN_4404; // @[L1DCache.scala 582:18]
- wire _GEN_7240 = 3'h7 == fstate ? _GEN_6727 : _GEN_4405; // @[L1DCache.scala 582:18]
- wire _GEN_7241 = 3'h7 == fstate ? _GEN_6728 : _GEN_4406; // @[L1DCache.scala 582:18]
- wire _GEN_7242 = 3'h7 == fstate ? _GEN_6729 : _GEN_4407; // @[L1DCache.scala 582:18]
- wire _GEN_7243 = 3'h7 == fstate ? _GEN_6730 : _GEN_4408; // @[L1DCache.scala 582:18]
- wire _GEN_7244 = 3'h7 == fstate ? _GEN_6731 : _GEN_4409; // @[L1DCache.scala 582:18]
- wire _GEN_7245 = 3'h7 == fstate ? _GEN_6732 : _GEN_4410; // @[L1DCache.scala 582:18]
- wire _GEN_7246 = 3'h7 == fstate ? _GEN_6733 : _GEN_4411; // @[L1DCache.scala 582:18]
- wire _GEN_7247 = 3'h7 == fstate ? _GEN_6734 : _GEN_4412; // @[L1DCache.scala 582:18]
- wire _GEN_7248 = 3'h7 == fstate ? _GEN_6735 : _GEN_4413; // @[L1DCache.scala 582:18]
- wire _GEN_7249 = 3'h7 == fstate ? _GEN_6736 : _GEN_4414; // @[L1DCache.scala 582:18]
- wire _GEN_7250 = 3'h7 == fstate ? _GEN_6737 : _GEN_4415; // @[L1DCache.scala 582:18]
- wire _GEN_7251 = 3'h7 == fstate ? _GEN_6738 : _GEN_4416; // @[L1DCache.scala 582:18]
- wire _GEN_7252 = 3'h7 == fstate ? _GEN_6739 : _GEN_4417; // @[L1DCache.scala 582:18]
- wire _GEN_7253 = 3'h7 == fstate ? _GEN_6740 : _GEN_4418; // @[L1DCache.scala 582:18]
- wire _GEN_7254 = 3'h7 == fstate ? _GEN_6741 : _GEN_4419; // @[L1DCache.scala 582:18]
- wire _GEN_7255 = 3'h7 == fstate ? _GEN_6742 : _GEN_4420; // @[L1DCache.scala 582:18]
- wire _GEN_7256 = 3'h7 == fstate ? _GEN_6743 : _GEN_4421; // @[L1DCache.scala 582:18]
- wire _GEN_7257 = 3'h7 == fstate ? _GEN_6744 : _GEN_4422; // @[L1DCache.scala 582:18]
- wire _GEN_7258 = 3'h7 == fstate ? _GEN_6745 : _GEN_4423; // @[L1DCache.scala 582:18]
- wire _GEN_7259 = 3'h7 == fstate ? _GEN_6746 : _GEN_4424; // @[L1DCache.scala 582:18]
- wire _GEN_7260 = 3'h7 == fstate ? _GEN_6747 : _GEN_4425; // @[L1DCache.scala 582:18]
- wire _GEN_7261 = 3'h7 == fstate ? _GEN_6748 : _GEN_4426; // @[L1DCache.scala 582:18]
- wire _GEN_7262 = 3'h7 == fstate ? _GEN_6749 : _GEN_4427; // @[L1DCache.scala 582:18]
- wire _GEN_7263 = 3'h7 == fstate ? _GEN_6750 : _GEN_4428; // @[L1DCache.scala 582:18]
- wire _GEN_7264 = 3'h7 == fstate ? _GEN_6751 : _GEN_4429; // @[L1DCache.scala 582:18]
- wire _GEN_7265 = 3'h7 == fstate ? _GEN_6752 : _GEN_4430; // @[L1DCache.scala 582:18]
- wire _GEN_7266 = 3'h7 == fstate ? _GEN_6753 : _GEN_4431; // @[L1DCache.scala 582:18]
- wire _GEN_7267 = 3'h7 == fstate ? _GEN_6754 : _GEN_4432; // @[L1DCache.scala 582:18]
- wire _GEN_7268 = 3'h7 == fstate ? _GEN_6755 : _GEN_4433; // @[L1DCache.scala 582:18]
- wire _GEN_7269 = 3'h7 == fstate ? _GEN_6756 : _GEN_4434; // @[L1DCache.scala 582:18]
- wire _GEN_7270 = 3'h7 == fstate ? _GEN_6757 : _GEN_4435; // @[L1DCache.scala 582:18]
- wire _GEN_7271 = 3'h7 == fstate ? _GEN_6758 : _GEN_4436; // @[L1DCache.scala 582:18]
- wire _GEN_7272 = 3'h7 == fstate ? _GEN_6759 : _GEN_4437; // @[L1DCache.scala 582:18]
- wire _GEN_7273 = 3'h7 == fstate ? _GEN_6760 : _GEN_4438; // @[L1DCache.scala 582:18]
- wire _GEN_7274 = 3'h7 == fstate ? _GEN_6761 : _GEN_4439; // @[L1DCache.scala 582:18]
- wire _GEN_7275 = 3'h7 == fstate ? _GEN_6762 : _GEN_4440; // @[L1DCache.scala 582:18]
- wire _GEN_7276 = 3'h7 == fstate ? _GEN_6763 : _GEN_4441; // @[L1DCache.scala 582:18]
- wire _GEN_7277 = 3'h7 == fstate ? _GEN_6764 : _GEN_4442; // @[L1DCache.scala 582:18]
- wire _GEN_7278 = 3'h7 == fstate ? _GEN_6765 : _GEN_4443; // @[L1DCache.scala 582:18]
- wire _GEN_7279 = 3'h7 == fstate ? _GEN_6766 : _GEN_4444; // @[L1DCache.scala 582:18]
- wire _GEN_7280 = 3'h7 == fstate ? _GEN_6767 : _GEN_4445; // @[L1DCache.scala 582:18]
- wire _GEN_7281 = 3'h7 == fstate ? _GEN_6768 : _GEN_4446; // @[L1DCache.scala 582:18]
- wire _GEN_7282 = 3'h7 == fstate ? _GEN_6769 : _GEN_4447; // @[L1DCache.scala 582:18]
- wire _GEN_7283 = 3'h7 == fstate ? _GEN_6770 : _GEN_4448; // @[L1DCache.scala 582:18]
- wire _GEN_7284 = 3'h7 == fstate ? _GEN_6771 : _GEN_4449; // @[L1DCache.scala 582:18]
- wire _GEN_7285 = 3'h7 == fstate ? _GEN_6772 : _GEN_4450; // @[L1DCache.scala 582:18]
- wire _GEN_7286 = 3'h7 == fstate ? _GEN_6773 : _GEN_4451; // @[L1DCache.scala 582:18]
- wire _GEN_7287 = 3'h7 == fstate ? _GEN_6774 : _GEN_4452; // @[L1DCache.scala 582:18]
- wire _GEN_7288 = 3'h7 == fstate ? _GEN_6775 : _GEN_4453; // @[L1DCache.scala 582:18]
- wire _GEN_7289 = 3'h7 == fstate ? _GEN_6776 : _GEN_4454; // @[L1DCache.scala 582:18]
- wire _GEN_7290 = 3'h7 == fstate ? _GEN_6777 : _GEN_4455; // @[L1DCache.scala 582:18]
- wire _GEN_7291 = 3'h7 == fstate ? _GEN_6778 : _GEN_4456; // @[L1DCache.scala 582:18]
- wire _GEN_7292 = 3'h7 == fstate ? _GEN_6779 : _GEN_4457; // @[L1DCache.scala 582:18]
- wire _GEN_7293 = 3'h7 == fstate ? _GEN_6780 : _GEN_4458; // @[L1DCache.scala 582:18]
- wire _GEN_7294 = 3'h7 == fstate ? _GEN_6781 : _GEN_4459; // @[L1DCache.scala 582:18]
- wire _GEN_7295 = 3'h7 == fstate ? _GEN_6782 : _GEN_4460; // @[L1DCache.scala 582:18]
- wire _GEN_7296 = 3'h7 == fstate ? _GEN_6783 : _GEN_4461; // @[L1DCache.scala 582:18]
- wire _GEN_7297 = 3'h7 == fstate ? _GEN_6784 : _GEN_4462; // @[L1DCache.scala 582:18]
- wire _GEN_7298 = 3'h7 == fstate ? _GEN_6785 : _GEN_4463; // @[L1DCache.scala 582:18]
- wire _GEN_7299 = 3'h7 == fstate ? _GEN_6786 : _GEN_4464; // @[L1DCache.scala 582:18]
- wire _GEN_7300 = 3'h7 == fstate ? _GEN_6787 : _GEN_4465; // @[L1DCache.scala 582:18]
- wire _GEN_7301 = 3'h7 == fstate ? _GEN_6788 : _GEN_4466; // @[L1DCache.scala 582:18]
- wire _GEN_7302 = 3'h7 == fstate ? _GEN_6789 : _GEN_4467; // @[L1DCache.scala 582:18]
- wire _GEN_7303 = 3'h7 == fstate ? _GEN_6790 : _GEN_4468; // @[L1DCache.scala 582:18]
- wire _GEN_7304 = 3'h7 == fstate ? _GEN_6791 : _GEN_4469; // @[L1DCache.scala 582:18]
- wire _GEN_7305 = 3'h7 == fstate ? _GEN_6792 : _GEN_4470; // @[L1DCache.scala 582:18]
- wire _GEN_7306 = 3'h7 == fstate ? _GEN_6793 : _GEN_4471; // @[L1DCache.scala 582:18]
- wire _GEN_7307 = 3'h7 == fstate ? _GEN_6794 : _GEN_4472; // @[L1DCache.scala 582:18]
- wire _GEN_7308 = 3'h7 == fstate ? _GEN_6795 : _GEN_4473; // @[L1DCache.scala 582:18]
- wire _GEN_7309 = 3'h7 == fstate ? _GEN_6796 : _GEN_4474; // @[L1DCache.scala 582:18]
- wire _GEN_7310 = 3'h7 == fstate ? _GEN_6797 : _GEN_4475; // @[L1DCache.scala 582:18]
- wire _GEN_7311 = 3'h7 == fstate ? _GEN_6798 : _GEN_4476; // @[L1DCache.scala 582:18]
- wire _GEN_7312 = 3'h7 == fstate ? _GEN_6799 : _GEN_4477; // @[L1DCache.scala 582:18]
- wire _GEN_7313 = 3'h7 == fstate ? _GEN_6800 : _GEN_4478; // @[L1DCache.scala 582:18]
- wire _GEN_7314 = 3'h7 == fstate ? _GEN_6801 : _GEN_4479; // @[L1DCache.scala 582:18]
- wire _GEN_7315 = 3'h7 == fstate ? _GEN_6802 : _GEN_4480; // @[L1DCache.scala 582:18]
- wire _GEN_7316 = 3'h7 == fstate ? _GEN_6803 : _GEN_4481; // @[L1DCache.scala 582:18]
- wire _GEN_7317 = 3'h7 == fstate ? _GEN_6804 : _GEN_4482; // @[L1DCache.scala 582:18]
- wire _GEN_7318 = 3'h7 == fstate ? _GEN_6805 : _GEN_4483; // @[L1DCache.scala 582:18]
- wire _GEN_7319 = 3'h7 == fstate ? _GEN_6806 : _GEN_4484; // @[L1DCache.scala 582:18]
- wire _GEN_7320 = 3'h7 == fstate ? _GEN_6807 : _GEN_4485; // @[L1DCache.scala 582:18]
- wire _GEN_7321 = 3'h7 == fstate ? _GEN_6808 : _GEN_4486; // @[L1DCache.scala 582:18]
- wire _GEN_7322 = 3'h7 == fstate ? _GEN_6809 : _GEN_4487; // @[L1DCache.scala 582:18]
- wire _GEN_7323 = 3'h7 == fstate ? _GEN_6810 : _GEN_4488; // @[L1DCache.scala 582:18]
- wire _GEN_7324 = 3'h7 == fstate ? _GEN_6811 : _GEN_4489; // @[L1DCache.scala 582:18]
- wire _GEN_7325 = 3'h7 == fstate ? _GEN_6812 : _GEN_4490; // @[L1DCache.scala 582:18]
- wire _GEN_7326 = 3'h7 == fstate ? _GEN_6813 : _GEN_4491; // @[L1DCache.scala 582:18]
- wire _GEN_7327 = 3'h7 == fstate ? _GEN_6814 : _GEN_4492; // @[L1DCache.scala 582:18]
- wire _GEN_7328 = 3'h7 == fstate ? _GEN_6815 : _GEN_4493; // @[L1DCache.scala 582:18]
- wire _GEN_7329 = 3'h7 == fstate ? _GEN_6816 : _GEN_4494; // @[L1DCache.scala 582:18]
- wire _GEN_7330 = 3'h7 == fstate ? _GEN_6817 : _GEN_4495; // @[L1DCache.scala 582:18]
- wire _GEN_7331 = 3'h7 == fstate ? _GEN_6818 : _GEN_4496; // @[L1DCache.scala 582:18]
- wire _GEN_7332 = 3'h7 == fstate ? _GEN_6819 : _GEN_4497; // @[L1DCache.scala 582:18]
- wire _GEN_7333 = 3'h7 == fstate ? _GEN_6820 : _GEN_4498; // @[L1DCache.scala 582:18]
- wire _GEN_7334 = 3'h7 == fstate ? _GEN_6821 : _GEN_4499; // @[L1DCache.scala 582:18]
- wire _GEN_7335 = 3'h7 == fstate ? _GEN_6822 : _GEN_4500; // @[L1DCache.scala 582:18]
- wire _GEN_7336 = 3'h7 == fstate ? _GEN_6823 : _GEN_4501; // @[L1DCache.scala 582:18]
- wire _GEN_7337 = 3'h7 == fstate ? _GEN_6824 : _GEN_4502; // @[L1DCache.scala 582:18]
- wire _GEN_7338 = 3'h7 == fstate ? _GEN_6825 : _GEN_4503; // @[L1DCache.scala 582:18]
- wire _GEN_7339 = 3'h7 == fstate ? _GEN_6826 : _GEN_4504; // @[L1DCache.scala 582:18]
- wire _GEN_7340 = 3'h7 == fstate ? _GEN_6827 : _GEN_4505; // @[L1DCache.scala 582:18]
- wire _GEN_7341 = 3'h7 == fstate ? _GEN_6828 : _GEN_4506; // @[L1DCache.scala 582:18]
- wire _GEN_7342 = 3'h7 == fstate ? _GEN_6829 : _GEN_4507; // @[L1DCache.scala 582:18]
- wire _GEN_7343 = 3'h7 == fstate ? _GEN_6830 : _GEN_4508; // @[L1DCache.scala 582:18]
- wire _GEN_7344 = 3'h7 == fstate ? _GEN_6831 : _GEN_4509; // @[L1DCache.scala 582:18]
- wire _GEN_7345 = 3'h7 == fstate ? _GEN_6832 : _GEN_4510; // @[L1DCache.scala 582:18]
- wire _GEN_7346 = 3'h7 == fstate ? _GEN_6833 : _GEN_4511; // @[L1DCache.scala 582:18]
- wire _GEN_7347 = 3'h7 == fstate ? _GEN_6834 : _GEN_4512; // @[L1DCache.scala 582:18]
- wire _GEN_7348 = 3'h7 == fstate ? _GEN_6835 : _GEN_4513; // @[L1DCache.scala 582:18]
- wire _GEN_7349 = 3'h7 == fstate ? _GEN_6836 : _GEN_4514; // @[L1DCache.scala 582:18]
- wire _GEN_7350 = 3'h7 == fstate ? _GEN_6837 : _GEN_4515; // @[L1DCache.scala 582:18]
- wire _GEN_7351 = 3'h7 == fstate ? _GEN_6838 : _GEN_4516; // @[L1DCache.scala 582:18]
- wire _GEN_7352 = 3'h7 == fstate ? _GEN_6839 : _GEN_4517; // @[L1DCache.scala 582:18]
- wire _GEN_7353 = 3'h7 == fstate ? _GEN_6840 : _GEN_4518; // @[L1DCache.scala 582:18]
- wire _GEN_7354 = 3'h7 == fstate ? _GEN_6841 : _GEN_4519; // @[L1DCache.scala 582:18]
- wire _GEN_7355 = 3'h7 == fstate ? _GEN_6842 : _GEN_4520; // @[L1DCache.scala 582:18]
- wire _GEN_7356 = 3'h7 == fstate ? _GEN_6843 : _GEN_4521; // @[L1DCache.scala 582:18]
- wire _GEN_7357 = 3'h7 == fstate ? _GEN_6844 : _GEN_4522; // @[L1DCache.scala 582:18]
- wire _GEN_7358 = 3'h7 == fstate ? _GEN_6845 : _GEN_4523; // @[L1DCache.scala 582:18]
- wire _GEN_7359 = 3'h7 == fstate ? _GEN_6846 : _GEN_4524; // @[L1DCache.scala 582:18]
- wire _GEN_7360 = 3'h7 == fstate ? _GEN_6847 : _GEN_4525; // @[L1DCache.scala 582:18]
- wire _GEN_7361 = 3'h7 == fstate ? _GEN_6848 : _GEN_4526; // @[L1DCache.scala 582:18]
- wire _GEN_7362 = 3'h7 == fstate ? _GEN_6849 : _GEN_4527; // @[L1DCache.scala 582:18]
- wire _GEN_7363 = 3'h7 == fstate ? _GEN_6850 : _GEN_4528; // @[L1DCache.scala 582:18]
- wire _GEN_7364 = 3'h7 == fstate ? _GEN_6851 : _GEN_4529; // @[L1DCache.scala 582:18]
- wire _GEN_7365 = 3'h7 == fstate ? _GEN_6852 : _GEN_4530; // @[L1DCache.scala 582:18]
- wire _GEN_7366 = 3'h7 == fstate ? _GEN_6853 : _GEN_4531; // @[L1DCache.scala 582:18]
- wire _GEN_7367 = 3'h7 == fstate ? _GEN_6854 : _GEN_4532; // @[L1DCache.scala 582:18]
- wire _GEN_7368 = 3'h7 == fstate ? _GEN_6855 : _GEN_4533; // @[L1DCache.scala 582:18]
- wire _GEN_7369 = 3'h7 == fstate ? _GEN_6856 : _GEN_4534; // @[L1DCache.scala 582:18]
- wire _GEN_7370 = 3'h7 == fstate ? _GEN_6857 : _GEN_4535; // @[L1DCache.scala 582:18]
- wire _GEN_7371 = 3'h7 == fstate ? _GEN_6858 : _GEN_4536; // @[L1DCache.scala 582:18]
- wire _GEN_7372 = 3'h7 == fstate ? _GEN_6859 : _GEN_4537; // @[L1DCache.scala 582:18]
- wire _GEN_7373 = 3'h7 == fstate ? _GEN_6860 : _GEN_4538; // @[L1DCache.scala 582:18]
- wire _GEN_7374 = 3'h7 == fstate ? _GEN_6861 : _GEN_4539; // @[L1DCache.scala 582:18]
- wire _GEN_7375 = 3'h7 == fstate ? _GEN_6862 : _GEN_4540; // @[L1DCache.scala 582:18]
- wire _GEN_7376 = 3'h7 == fstate ? _GEN_6863 : _GEN_4541; // @[L1DCache.scala 582:18]
- wire _GEN_7377 = 3'h7 == fstate ? _GEN_6864 : _GEN_4542; // @[L1DCache.scala 582:18]
- wire _GEN_7378 = 3'h7 == fstate ? _GEN_6865 : _GEN_4543; // @[L1DCache.scala 582:18]
- wire _GEN_7379 = 3'h7 == fstate ? _GEN_6866 : _GEN_4544; // @[L1DCache.scala 582:18]
- wire _GEN_7380 = 3'h7 == fstate ? _GEN_6867 : _GEN_4545; // @[L1DCache.scala 582:18]
- wire _GEN_7381 = 3'h7 == fstate ? _GEN_6868 : _GEN_4546; // @[L1DCache.scala 582:18]
- wire _GEN_7382 = 3'h7 == fstate ? _GEN_6869 : _GEN_4547; // @[L1DCache.scala 582:18]
- wire _GEN_7383 = 3'h7 == fstate ? _GEN_6870 : _GEN_4548; // @[L1DCache.scala 582:18]
- wire _GEN_7384 = 3'h7 == fstate ? _GEN_6871 : _GEN_4549; // @[L1DCache.scala 582:18]
- wire _GEN_7385 = 3'h7 == fstate ? _GEN_6872 : _GEN_4550; // @[L1DCache.scala 582:18]
- wire _GEN_7386 = 3'h7 == fstate ? _GEN_6873 : _GEN_4551; // @[L1DCache.scala 582:18]
- wire _GEN_7387 = 3'h7 == fstate ? _GEN_6874 : _GEN_4552; // @[L1DCache.scala 582:18]
- wire _GEN_7388 = 3'h7 == fstate ? _GEN_6875 : _GEN_4553; // @[L1DCache.scala 582:18]
- wire _GEN_7389 = 3'h7 == fstate ? _GEN_6876 : _GEN_4554; // @[L1DCache.scala 582:18]
- wire _GEN_7390 = 3'h7 == fstate ? _GEN_6877 : _GEN_4555; // @[L1DCache.scala 582:18]
- wire _GEN_7391 = 3'h7 == fstate ? _GEN_6878 : _GEN_4556; // @[L1DCache.scala 582:18]
- wire _GEN_7392 = 3'h7 == fstate ? _GEN_6879 : _GEN_4557; // @[L1DCache.scala 582:18]
- wire _GEN_7393 = 3'h7 == fstate ? _GEN_6880 : _GEN_4558; // @[L1DCache.scala 582:18]
- wire _GEN_7394 = 3'h7 == fstate ? _GEN_6881 : _GEN_4559; // @[L1DCache.scala 582:18]
- wire _GEN_7395 = 3'h7 == fstate ? _GEN_6882 : _GEN_4560; // @[L1DCache.scala 582:18]
- wire _GEN_7396 = 3'h7 == fstate ? _GEN_6883 : _GEN_4561; // @[L1DCache.scala 582:18]
- wire _GEN_7397 = 3'h7 == fstate ? _GEN_6884 : _GEN_4562; // @[L1DCache.scala 582:18]
- wire _GEN_7398 = 3'h7 == fstate ? _GEN_6885 : _GEN_4563; // @[L1DCache.scala 582:18]
- wire _GEN_7399 = 3'h7 == fstate ? _GEN_6886 : _GEN_4564; // @[L1DCache.scala 582:18]
- wire _GEN_7400 = 3'h7 == fstate ? _GEN_6887 : _GEN_4565; // @[L1DCache.scala 582:18]
- wire _GEN_7401 = 3'h7 == fstate ? _GEN_6888 : _GEN_4566; // @[L1DCache.scala 582:18]
- wire _GEN_7402 = 3'h7 == fstate ? _GEN_6889 : _GEN_4567; // @[L1DCache.scala 582:18]
- wire _GEN_7403 = 3'h7 == fstate ? _GEN_6890 : _GEN_4568; // @[L1DCache.scala 582:18]
- wire _GEN_7404 = 3'h7 == fstate ? _GEN_6891 : _GEN_4569; // @[L1DCache.scala 582:18]
- wire _GEN_7405 = 3'h7 == fstate ? _GEN_6892 : _GEN_4570; // @[L1DCache.scala 582:18]
- wire _GEN_7406 = 3'h7 == fstate ? _GEN_6893 : _GEN_4571; // @[L1DCache.scala 582:18]
- wire _GEN_7407 = 3'h7 == fstate ? _GEN_6894 : _GEN_4572; // @[L1DCache.scala 582:18]
- wire _GEN_7408 = 3'h7 == fstate ? _GEN_6895 : _GEN_4573; // @[L1DCache.scala 582:18]
- wire _GEN_7409 = 3'h7 == fstate ? _GEN_6896 : _GEN_4574; // @[L1DCache.scala 582:18]
- wire _GEN_7410 = 3'h7 == fstate ? _GEN_6897 : _GEN_4575; // @[L1DCache.scala 582:18]
- wire _GEN_7411 = 3'h7 == fstate ? _GEN_6898 : _GEN_4576; // @[L1DCache.scala 582:18]
- wire _GEN_7412 = 3'h7 == fstate ? _GEN_6899 : _GEN_4577; // @[L1DCache.scala 582:18]
- wire _GEN_7413 = 3'h7 == fstate ? _GEN_6900 : _GEN_4578; // @[L1DCache.scala 582:18]
- wire _GEN_7414 = 3'h7 == fstate ? _GEN_6901 : _GEN_4579; // @[L1DCache.scala 582:18]
- wire _GEN_7415 = 3'h7 == fstate ? _GEN_6902 : _GEN_4580; // @[L1DCache.scala 582:18]
- wire _GEN_7416 = 3'h7 == fstate ? _GEN_6903 : _GEN_4581; // @[L1DCache.scala 582:18]
- wire _GEN_7417 = 3'h7 == fstate ? _GEN_6904 : _GEN_4582; // @[L1DCache.scala 582:18]
- wire _GEN_7418 = 3'h7 == fstate ? _GEN_6905 : _GEN_4583; // @[L1DCache.scala 582:18]
- wire _GEN_7419 = 3'h7 == fstate ? _GEN_6906 : _GEN_4584; // @[L1DCache.scala 582:18]
- wire _GEN_7420 = 3'h7 == fstate ? _GEN_6907 : _GEN_4585; // @[L1DCache.scala 582:18]
- wire _GEN_7421 = 3'h7 == fstate ? _GEN_6908 : _GEN_4586; // @[L1DCache.scala 582:18]
- wire _GEN_7422 = 3'h7 == fstate ? _GEN_6909 : _GEN_4587; // @[L1DCache.scala 582:18]
- wire _GEN_7423 = 3'h7 == fstate ? _GEN_6910 : _GEN_4588; // @[L1DCache.scala 582:18]
- wire _GEN_7424 = 3'h7 == fstate ? _GEN_6911 : _GEN_4589; // @[L1DCache.scala 582:18]
- wire _GEN_7425 = 3'h7 == fstate ? _GEN_6912 : _GEN_4590; // @[L1DCache.scala 582:18]
- wire _GEN_7426 = 3'h7 == fstate ? _GEN_6913 : _GEN_4591; // @[L1DCache.scala 582:18]
- wire _GEN_7427 = 3'h7 == fstate ? _GEN_6914 : _GEN_4592; // @[L1DCache.scala 582:18]
- wire _GEN_7428 = 3'h7 == fstate ? _GEN_6915 : _GEN_4593; // @[L1DCache.scala 582:18]
- wire _GEN_7429 = 3'h7 == fstate ? _GEN_6916 : _GEN_4594; // @[L1DCache.scala 582:18]
- wire _GEN_7430 = 3'h7 == fstate ? _GEN_6917 : _GEN_4595; // @[L1DCache.scala 582:18]
- wire _GEN_7431 = 3'h7 == fstate ? _GEN_6918 : _GEN_4596; // @[L1DCache.scala 582:18]
- wire _GEN_7432 = 3'h7 == fstate ? _GEN_6919 : _GEN_4597; // @[L1DCache.scala 582:18]
- wire _GEN_7433 = 3'h7 == fstate ? _GEN_6920 : _GEN_4598; // @[L1DCache.scala 582:18]
- wire _GEN_7434 = 3'h7 == fstate ? _GEN_6921 : _GEN_4599; // @[L1DCache.scala 582:18]
- wire _GEN_7435 = 3'h7 == fstate ? _GEN_6922 : _GEN_4600; // @[L1DCache.scala 582:18]
- wire _GEN_7436 = 3'h7 == fstate ? _GEN_6923 : _GEN_4601; // @[L1DCache.scala 582:18]
- wire _GEN_7437 = 3'h7 == fstate ? _GEN_6924 : _GEN_4602; // @[L1DCache.scala 582:18]
- wire _GEN_7438 = 3'h7 == fstate ? _GEN_6925 : _GEN_4603; // @[L1DCache.scala 582:18]
- wire _GEN_7439 = 3'h7 == fstate ? _GEN_6926 : _GEN_4604; // @[L1DCache.scala 582:18]
- wire _GEN_7440 = 3'h7 == fstate ? _GEN_6927 : _GEN_4605; // @[L1DCache.scala 582:18]
- wire _GEN_7441 = 3'h7 == fstate ? _GEN_6928 : _GEN_4606; // @[L1DCache.scala 582:18]
- wire _GEN_7442 = 3'h7 == fstate ? _GEN_6929 : _GEN_4607; // @[L1DCache.scala 582:18]
- wire _GEN_7443 = 3'h7 == fstate ? _GEN_6930 : _GEN_4608; // @[L1DCache.scala 582:18]
- wire _GEN_7444 = 3'h7 == fstate ? _GEN_6931 : _GEN_4609; // @[L1DCache.scala 582:18]
- wire _GEN_7445 = 3'h7 == fstate ? _GEN_6932 : _GEN_4610; // @[L1DCache.scala 582:18]
- wire _GEN_7446 = 3'h7 == fstate ? _GEN_6933 : _GEN_4611; // @[L1DCache.scala 582:18]
- wire _GEN_7447 = 3'h7 == fstate ? _GEN_6934 : _GEN_4612; // @[L1DCache.scala 582:18]
- wire _GEN_7448 = 3'h7 == fstate ? _GEN_6935 : _GEN_4613; // @[L1DCache.scala 582:18]
- wire _GEN_7449 = 3'h7 == fstate ? _GEN_6936 : _GEN_4614; // @[L1DCache.scala 582:18]
- wire _GEN_7450 = 3'h7 == fstate ? _GEN_6937 : _GEN_4615; // @[L1DCache.scala 582:18]
- wire [2:0] _GEN_7451 = 3'h6 == fstate ? _GEN_6680 : _GEN_7194; // @[L1DCache.scala 582:18]
- wire _GEN_7452 = 3'h6 == fstate ? _GEN_4360 : _GEN_7195; // @[L1DCache.scala 582:18]
- wire _GEN_7453 = 3'h6 == fstate ? _GEN_4361 : _GEN_7196; // @[L1DCache.scala 582:18]
- wire _GEN_7454 = 3'h6 == fstate ? _GEN_4362 : _GEN_7197; // @[L1DCache.scala 582:18]
- wire _GEN_7455 = 3'h6 == fstate ? _GEN_4363 : _GEN_7198; // @[L1DCache.scala 582:18]
- wire _GEN_7456 = 3'h6 == fstate ? _GEN_4364 : _GEN_7199; // @[L1DCache.scala 582:18]
- wire _GEN_7457 = 3'h6 == fstate ? _GEN_4365 : _GEN_7200; // @[L1DCache.scala 582:18]
- wire _GEN_7458 = 3'h6 == fstate ? _GEN_4366 : _GEN_7201; // @[L1DCache.scala 582:18]
- wire _GEN_7459 = 3'h6 == fstate ? _GEN_4367 : _GEN_7202; // @[L1DCache.scala 582:18]
- wire _GEN_7460 = 3'h6 == fstate ? _GEN_4368 : _GEN_7203; // @[L1DCache.scala 582:18]
- wire _GEN_7461 = 3'h6 == fstate ? _GEN_4369 : _GEN_7204; // @[L1DCache.scala 582:18]
- wire _GEN_7462 = 3'h6 == fstate ? _GEN_4370 : _GEN_7205; // @[L1DCache.scala 582:18]
- wire _GEN_7463 = 3'h6 == fstate ? _GEN_4371 : _GEN_7206; // @[L1DCache.scala 582:18]
- wire _GEN_7464 = 3'h6 == fstate ? _GEN_4372 : _GEN_7207; // @[L1DCache.scala 582:18]
- wire _GEN_7465 = 3'h6 == fstate ? _GEN_4373 : _GEN_7208; // @[L1DCache.scala 582:18]
- wire _GEN_7466 = 3'h6 == fstate ? _GEN_4374 : _GEN_7209; // @[L1DCache.scala 582:18]
- wire _GEN_7467 = 3'h6 == fstate ? _GEN_4375 : _GEN_7210; // @[L1DCache.scala 582:18]
- wire _GEN_7468 = 3'h6 == fstate ? _GEN_4376 : _GEN_7211; // @[L1DCache.scala 582:18]
- wire _GEN_7469 = 3'h6 == fstate ? _GEN_4377 : _GEN_7212; // @[L1DCache.scala 582:18]
- wire _GEN_7470 = 3'h6 == fstate ? _GEN_4378 : _GEN_7213; // @[L1DCache.scala 582:18]
- wire _GEN_7471 = 3'h6 == fstate ? _GEN_4379 : _GEN_7214; // @[L1DCache.scala 582:18]
- wire _GEN_7472 = 3'h6 == fstate ? _GEN_4380 : _GEN_7215; // @[L1DCache.scala 582:18]
- wire _GEN_7473 = 3'h6 == fstate ? _GEN_4381 : _GEN_7216; // @[L1DCache.scala 582:18]
- wire _GEN_7474 = 3'h6 == fstate ? _GEN_4382 : _GEN_7217; // @[L1DCache.scala 582:18]
- wire _GEN_7475 = 3'h6 == fstate ? _GEN_4383 : _GEN_7218; // @[L1DCache.scala 582:18]
- wire _GEN_7476 = 3'h6 == fstate ? _GEN_4384 : _GEN_7219; // @[L1DCache.scala 582:18]
- wire _GEN_7477 = 3'h6 == fstate ? _GEN_4385 : _GEN_7220; // @[L1DCache.scala 582:18]
- wire _GEN_7478 = 3'h6 == fstate ? _GEN_4386 : _GEN_7221; // @[L1DCache.scala 582:18]
- wire _GEN_7479 = 3'h6 == fstate ? _GEN_4387 : _GEN_7222; // @[L1DCache.scala 582:18]
- wire _GEN_7480 = 3'h6 == fstate ? _GEN_4388 : _GEN_7223; // @[L1DCache.scala 582:18]
- wire _GEN_7481 = 3'h6 == fstate ? _GEN_4389 : _GEN_7224; // @[L1DCache.scala 582:18]
- wire _GEN_7482 = 3'h6 == fstate ? _GEN_4390 : _GEN_7225; // @[L1DCache.scala 582:18]
- wire _GEN_7483 = 3'h6 == fstate ? _GEN_4391 : _GEN_7226; // @[L1DCache.scala 582:18]
- wire _GEN_7484 = 3'h6 == fstate ? _GEN_4392 : _GEN_7227; // @[L1DCache.scala 582:18]
- wire _GEN_7485 = 3'h6 == fstate ? _GEN_4393 : _GEN_7228; // @[L1DCache.scala 582:18]
- wire _GEN_7486 = 3'h6 == fstate ? _GEN_4394 : _GEN_7229; // @[L1DCache.scala 582:18]
- wire _GEN_7487 = 3'h6 == fstate ? _GEN_4395 : _GEN_7230; // @[L1DCache.scala 582:18]
- wire _GEN_7488 = 3'h6 == fstate ? _GEN_4396 : _GEN_7231; // @[L1DCache.scala 582:18]
- wire _GEN_7489 = 3'h6 == fstate ? _GEN_4397 : _GEN_7232; // @[L1DCache.scala 582:18]
- wire _GEN_7490 = 3'h6 == fstate ? _GEN_4398 : _GEN_7233; // @[L1DCache.scala 582:18]
- wire _GEN_7491 = 3'h6 == fstate ? _GEN_4399 : _GEN_7234; // @[L1DCache.scala 582:18]
- wire _GEN_7492 = 3'h6 == fstate ? _GEN_4400 : _GEN_7235; // @[L1DCache.scala 582:18]
- wire _GEN_7493 = 3'h6 == fstate ? _GEN_4401 : _GEN_7236; // @[L1DCache.scala 582:18]
- wire _GEN_7494 = 3'h6 == fstate ? _GEN_4402 : _GEN_7237; // @[L1DCache.scala 582:18]
- wire _GEN_7495 = 3'h6 == fstate ? _GEN_4403 : _GEN_7238; // @[L1DCache.scala 582:18]
- wire _GEN_7496 = 3'h6 == fstate ? _GEN_4404 : _GEN_7239; // @[L1DCache.scala 582:18]
- wire _GEN_7497 = 3'h6 == fstate ? _GEN_4405 : _GEN_7240; // @[L1DCache.scala 582:18]
- wire _GEN_7498 = 3'h6 == fstate ? _GEN_4406 : _GEN_7241; // @[L1DCache.scala 582:18]
- wire _GEN_7499 = 3'h6 == fstate ? _GEN_4407 : _GEN_7242; // @[L1DCache.scala 582:18]
- wire _GEN_7500 = 3'h6 == fstate ? _GEN_4408 : _GEN_7243; // @[L1DCache.scala 582:18]
- wire _GEN_7501 = 3'h6 == fstate ? _GEN_4409 : _GEN_7244; // @[L1DCache.scala 582:18]
- wire _GEN_7502 = 3'h6 == fstate ? _GEN_4410 : _GEN_7245; // @[L1DCache.scala 582:18]
- wire _GEN_7503 = 3'h6 == fstate ? _GEN_4411 : _GEN_7246; // @[L1DCache.scala 582:18]
- wire _GEN_7504 = 3'h6 == fstate ? _GEN_4412 : _GEN_7247; // @[L1DCache.scala 582:18]
- wire _GEN_7505 = 3'h6 == fstate ? _GEN_4413 : _GEN_7248; // @[L1DCache.scala 582:18]
- wire _GEN_7506 = 3'h6 == fstate ? _GEN_4414 : _GEN_7249; // @[L1DCache.scala 582:18]
- wire _GEN_7507 = 3'h6 == fstate ? _GEN_4415 : _GEN_7250; // @[L1DCache.scala 582:18]
- wire _GEN_7508 = 3'h6 == fstate ? _GEN_4416 : _GEN_7251; // @[L1DCache.scala 582:18]
- wire _GEN_7509 = 3'h6 == fstate ? _GEN_4417 : _GEN_7252; // @[L1DCache.scala 582:18]
- wire _GEN_7510 = 3'h6 == fstate ? _GEN_4418 : _GEN_7253; // @[L1DCache.scala 582:18]
- wire _GEN_7511 = 3'h6 == fstate ? _GEN_4419 : _GEN_7254; // @[L1DCache.scala 582:18]
- wire _GEN_7512 = 3'h6 == fstate ? _GEN_4420 : _GEN_7255; // @[L1DCache.scala 582:18]
- wire _GEN_7513 = 3'h6 == fstate ? _GEN_4421 : _GEN_7256; // @[L1DCache.scala 582:18]
- wire _GEN_7514 = 3'h6 == fstate ? _GEN_4422 : _GEN_7257; // @[L1DCache.scala 582:18]
- wire _GEN_7515 = 3'h6 == fstate ? _GEN_4423 : _GEN_7258; // @[L1DCache.scala 582:18]
- wire _GEN_7516 = 3'h6 == fstate ? _GEN_4424 : _GEN_7259; // @[L1DCache.scala 582:18]
- wire _GEN_7517 = 3'h6 == fstate ? _GEN_4425 : _GEN_7260; // @[L1DCache.scala 582:18]
- wire _GEN_7518 = 3'h6 == fstate ? _GEN_4426 : _GEN_7261; // @[L1DCache.scala 582:18]
- wire _GEN_7519 = 3'h6 == fstate ? _GEN_4427 : _GEN_7262; // @[L1DCache.scala 582:18]
- wire _GEN_7520 = 3'h6 == fstate ? _GEN_4428 : _GEN_7263; // @[L1DCache.scala 582:18]
- wire _GEN_7521 = 3'h6 == fstate ? _GEN_4429 : _GEN_7264; // @[L1DCache.scala 582:18]
- wire _GEN_7522 = 3'h6 == fstate ? _GEN_4430 : _GEN_7265; // @[L1DCache.scala 582:18]
- wire _GEN_7523 = 3'h6 == fstate ? _GEN_4431 : _GEN_7266; // @[L1DCache.scala 582:18]
- wire _GEN_7524 = 3'h6 == fstate ? _GEN_4432 : _GEN_7267; // @[L1DCache.scala 582:18]
- wire _GEN_7525 = 3'h6 == fstate ? _GEN_4433 : _GEN_7268; // @[L1DCache.scala 582:18]
- wire _GEN_7526 = 3'h6 == fstate ? _GEN_4434 : _GEN_7269; // @[L1DCache.scala 582:18]
- wire _GEN_7527 = 3'h6 == fstate ? _GEN_4435 : _GEN_7270; // @[L1DCache.scala 582:18]
- wire _GEN_7528 = 3'h6 == fstate ? _GEN_4436 : _GEN_7271; // @[L1DCache.scala 582:18]
- wire _GEN_7529 = 3'h6 == fstate ? _GEN_4437 : _GEN_7272; // @[L1DCache.scala 582:18]
- wire _GEN_7530 = 3'h6 == fstate ? _GEN_4438 : _GEN_7273; // @[L1DCache.scala 582:18]
- wire _GEN_7531 = 3'h6 == fstate ? _GEN_4439 : _GEN_7274; // @[L1DCache.scala 582:18]
- wire _GEN_7532 = 3'h6 == fstate ? _GEN_4440 : _GEN_7275; // @[L1DCache.scala 582:18]
- wire _GEN_7533 = 3'h6 == fstate ? _GEN_4441 : _GEN_7276; // @[L1DCache.scala 582:18]
- wire _GEN_7534 = 3'h6 == fstate ? _GEN_4442 : _GEN_7277; // @[L1DCache.scala 582:18]
- wire _GEN_7535 = 3'h6 == fstate ? _GEN_4443 : _GEN_7278; // @[L1DCache.scala 582:18]
- wire _GEN_7536 = 3'h6 == fstate ? _GEN_4444 : _GEN_7279; // @[L1DCache.scala 582:18]
- wire _GEN_7537 = 3'h6 == fstate ? _GEN_4445 : _GEN_7280; // @[L1DCache.scala 582:18]
- wire _GEN_7538 = 3'h6 == fstate ? _GEN_4446 : _GEN_7281; // @[L1DCache.scala 582:18]
- wire _GEN_7539 = 3'h6 == fstate ? _GEN_4447 : _GEN_7282; // @[L1DCache.scala 582:18]
- wire _GEN_7540 = 3'h6 == fstate ? _GEN_4448 : _GEN_7283; // @[L1DCache.scala 582:18]
- wire _GEN_7541 = 3'h6 == fstate ? _GEN_4449 : _GEN_7284; // @[L1DCache.scala 582:18]
- wire _GEN_7542 = 3'h6 == fstate ? _GEN_4450 : _GEN_7285; // @[L1DCache.scala 582:18]
- wire _GEN_7543 = 3'h6 == fstate ? _GEN_4451 : _GEN_7286; // @[L1DCache.scala 582:18]
- wire _GEN_7544 = 3'h6 == fstate ? _GEN_4452 : _GEN_7287; // @[L1DCache.scala 582:18]
- wire _GEN_7545 = 3'h6 == fstate ? _GEN_4453 : _GEN_7288; // @[L1DCache.scala 582:18]
- wire _GEN_7546 = 3'h6 == fstate ? _GEN_4454 : _GEN_7289; // @[L1DCache.scala 582:18]
- wire _GEN_7547 = 3'h6 == fstate ? _GEN_4455 : _GEN_7290; // @[L1DCache.scala 582:18]
- wire _GEN_7548 = 3'h6 == fstate ? _GEN_4456 : _GEN_7291; // @[L1DCache.scala 582:18]
- wire _GEN_7549 = 3'h6 == fstate ? _GEN_4457 : _GEN_7292; // @[L1DCache.scala 582:18]
- wire _GEN_7550 = 3'h6 == fstate ? _GEN_4458 : _GEN_7293; // @[L1DCache.scala 582:18]
- wire _GEN_7551 = 3'h6 == fstate ? _GEN_4459 : _GEN_7294; // @[L1DCache.scala 582:18]
- wire _GEN_7552 = 3'h6 == fstate ? _GEN_4460 : _GEN_7295; // @[L1DCache.scala 582:18]
- wire _GEN_7553 = 3'h6 == fstate ? _GEN_4461 : _GEN_7296; // @[L1DCache.scala 582:18]
- wire _GEN_7554 = 3'h6 == fstate ? _GEN_4462 : _GEN_7297; // @[L1DCache.scala 582:18]
- wire _GEN_7555 = 3'h6 == fstate ? _GEN_4463 : _GEN_7298; // @[L1DCache.scala 582:18]
- wire _GEN_7556 = 3'h6 == fstate ? _GEN_4464 : _GEN_7299; // @[L1DCache.scala 582:18]
- wire _GEN_7557 = 3'h6 == fstate ? _GEN_4465 : _GEN_7300; // @[L1DCache.scala 582:18]
- wire _GEN_7558 = 3'h6 == fstate ? _GEN_4466 : _GEN_7301; // @[L1DCache.scala 582:18]
- wire _GEN_7559 = 3'h6 == fstate ? _GEN_4467 : _GEN_7302; // @[L1DCache.scala 582:18]
- wire _GEN_7560 = 3'h6 == fstate ? _GEN_4468 : _GEN_7303; // @[L1DCache.scala 582:18]
- wire _GEN_7561 = 3'h6 == fstate ? _GEN_4469 : _GEN_7304; // @[L1DCache.scala 582:18]
- wire _GEN_7562 = 3'h6 == fstate ? _GEN_4470 : _GEN_7305; // @[L1DCache.scala 582:18]
- wire _GEN_7563 = 3'h6 == fstate ? _GEN_4471 : _GEN_7306; // @[L1DCache.scala 582:18]
- wire _GEN_7564 = 3'h6 == fstate ? _GEN_4472 : _GEN_7307; // @[L1DCache.scala 582:18]
- wire _GEN_7565 = 3'h6 == fstate ? _GEN_4473 : _GEN_7308; // @[L1DCache.scala 582:18]
- wire _GEN_7566 = 3'h6 == fstate ? _GEN_4474 : _GEN_7309; // @[L1DCache.scala 582:18]
- wire _GEN_7567 = 3'h6 == fstate ? _GEN_4475 : _GEN_7310; // @[L1DCache.scala 582:18]
- wire _GEN_7568 = 3'h6 == fstate ? _GEN_4476 : _GEN_7311; // @[L1DCache.scala 582:18]
- wire _GEN_7569 = 3'h6 == fstate ? _GEN_4477 : _GEN_7312; // @[L1DCache.scala 582:18]
- wire _GEN_7570 = 3'h6 == fstate ? _GEN_4478 : _GEN_7313; // @[L1DCache.scala 582:18]
- wire _GEN_7571 = 3'h6 == fstate ? _GEN_4479 : _GEN_7314; // @[L1DCache.scala 582:18]
- wire _GEN_7572 = 3'h6 == fstate ? _GEN_4480 : _GEN_7315; // @[L1DCache.scala 582:18]
- wire _GEN_7573 = 3'h6 == fstate ? _GEN_4481 : _GEN_7316; // @[L1DCache.scala 582:18]
- wire _GEN_7574 = 3'h6 == fstate ? _GEN_4482 : _GEN_7317; // @[L1DCache.scala 582:18]
- wire _GEN_7575 = 3'h6 == fstate ? _GEN_4483 : _GEN_7318; // @[L1DCache.scala 582:18]
- wire _GEN_7576 = 3'h6 == fstate ? _GEN_4484 : _GEN_7319; // @[L1DCache.scala 582:18]
- wire _GEN_7577 = 3'h6 == fstate ? _GEN_4485 : _GEN_7320; // @[L1DCache.scala 582:18]
- wire _GEN_7578 = 3'h6 == fstate ? _GEN_4486 : _GEN_7321; // @[L1DCache.scala 582:18]
- wire _GEN_7579 = 3'h6 == fstate ? _GEN_4487 : _GEN_7322; // @[L1DCache.scala 582:18]
- wire _GEN_7580 = 3'h6 == fstate ? _GEN_4488 : _GEN_7323; // @[L1DCache.scala 582:18]
- wire _GEN_7581 = 3'h6 == fstate ? _GEN_4489 : _GEN_7324; // @[L1DCache.scala 582:18]
- wire _GEN_7582 = 3'h6 == fstate ? _GEN_4490 : _GEN_7325; // @[L1DCache.scala 582:18]
- wire _GEN_7583 = 3'h6 == fstate ? _GEN_4491 : _GEN_7326; // @[L1DCache.scala 582:18]
- wire _GEN_7584 = 3'h6 == fstate ? _GEN_4492 : _GEN_7327; // @[L1DCache.scala 582:18]
- wire _GEN_7585 = 3'h6 == fstate ? _GEN_4493 : _GEN_7328; // @[L1DCache.scala 582:18]
- wire _GEN_7586 = 3'h6 == fstate ? _GEN_4494 : _GEN_7329; // @[L1DCache.scala 582:18]
- wire _GEN_7587 = 3'h6 == fstate ? _GEN_4495 : _GEN_7330; // @[L1DCache.scala 582:18]
- wire _GEN_7588 = 3'h6 == fstate ? _GEN_4496 : _GEN_7331; // @[L1DCache.scala 582:18]
- wire _GEN_7589 = 3'h6 == fstate ? _GEN_4497 : _GEN_7332; // @[L1DCache.scala 582:18]
- wire _GEN_7590 = 3'h6 == fstate ? _GEN_4498 : _GEN_7333; // @[L1DCache.scala 582:18]
- wire _GEN_7591 = 3'h6 == fstate ? _GEN_4499 : _GEN_7334; // @[L1DCache.scala 582:18]
- wire _GEN_7592 = 3'h6 == fstate ? _GEN_4500 : _GEN_7335; // @[L1DCache.scala 582:18]
- wire _GEN_7593 = 3'h6 == fstate ? _GEN_4501 : _GEN_7336; // @[L1DCache.scala 582:18]
- wire _GEN_7594 = 3'h6 == fstate ? _GEN_4502 : _GEN_7337; // @[L1DCache.scala 582:18]
- wire _GEN_7595 = 3'h6 == fstate ? _GEN_4503 : _GEN_7338; // @[L1DCache.scala 582:18]
- wire _GEN_7596 = 3'h6 == fstate ? _GEN_4504 : _GEN_7339; // @[L1DCache.scala 582:18]
- wire _GEN_7597 = 3'h6 == fstate ? _GEN_4505 : _GEN_7340; // @[L1DCache.scala 582:18]
- wire _GEN_7598 = 3'h6 == fstate ? _GEN_4506 : _GEN_7341; // @[L1DCache.scala 582:18]
- wire _GEN_7599 = 3'h6 == fstate ? _GEN_4507 : _GEN_7342; // @[L1DCache.scala 582:18]
- wire _GEN_7600 = 3'h6 == fstate ? _GEN_4508 : _GEN_7343; // @[L1DCache.scala 582:18]
- wire _GEN_7601 = 3'h6 == fstate ? _GEN_4509 : _GEN_7344; // @[L1DCache.scala 582:18]
- wire _GEN_7602 = 3'h6 == fstate ? _GEN_4510 : _GEN_7345; // @[L1DCache.scala 582:18]
- wire _GEN_7603 = 3'h6 == fstate ? _GEN_4511 : _GEN_7346; // @[L1DCache.scala 582:18]
- wire _GEN_7604 = 3'h6 == fstate ? _GEN_4512 : _GEN_7347; // @[L1DCache.scala 582:18]
- wire _GEN_7605 = 3'h6 == fstate ? _GEN_4513 : _GEN_7348; // @[L1DCache.scala 582:18]
- wire _GEN_7606 = 3'h6 == fstate ? _GEN_4514 : _GEN_7349; // @[L1DCache.scala 582:18]
- wire _GEN_7607 = 3'h6 == fstate ? _GEN_4515 : _GEN_7350; // @[L1DCache.scala 582:18]
- wire _GEN_7608 = 3'h6 == fstate ? _GEN_4516 : _GEN_7351; // @[L1DCache.scala 582:18]
- wire _GEN_7609 = 3'h6 == fstate ? _GEN_4517 : _GEN_7352; // @[L1DCache.scala 582:18]
- wire _GEN_7610 = 3'h6 == fstate ? _GEN_4518 : _GEN_7353; // @[L1DCache.scala 582:18]
- wire _GEN_7611 = 3'h6 == fstate ? _GEN_4519 : _GEN_7354; // @[L1DCache.scala 582:18]
- wire _GEN_7612 = 3'h6 == fstate ? _GEN_4520 : _GEN_7355; // @[L1DCache.scala 582:18]
- wire _GEN_7613 = 3'h6 == fstate ? _GEN_4521 : _GEN_7356; // @[L1DCache.scala 582:18]
- wire _GEN_7614 = 3'h6 == fstate ? _GEN_4522 : _GEN_7357; // @[L1DCache.scala 582:18]
- wire _GEN_7615 = 3'h6 == fstate ? _GEN_4523 : _GEN_7358; // @[L1DCache.scala 582:18]
- wire _GEN_7616 = 3'h6 == fstate ? _GEN_4524 : _GEN_7359; // @[L1DCache.scala 582:18]
- wire _GEN_7617 = 3'h6 == fstate ? _GEN_4525 : _GEN_7360; // @[L1DCache.scala 582:18]
- wire _GEN_7618 = 3'h6 == fstate ? _GEN_4526 : _GEN_7361; // @[L1DCache.scala 582:18]
- wire _GEN_7619 = 3'h6 == fstate ? _GEN_4527 : _GEN_7362; // @[L1DCache.scala 582:18]
- wire _GEN_7620 = 3'h6 == fstate ? _GEN_4528 : _GEN_7363; // @[L1DCache.scala 582:18]
- wire _GEN_7621 = 3'h6 == fstate ? _GEN_4529 : _GEN_7364; // @[L1DCache.scala 582:18]
- wire _GEN_7622 = 3'h6 == fstate ? _GEN_4530 : _GEN_7365; // @[L1DCache.scala 582:18]
- wire _GEN_7623 = 3'h6 == fstate ? _GEN_4531 : _GEN_7366; // @[L1DCache.scala 582:18]
- wire _GEN_7624 = 3'h6 == fstate ? _GEN_4532 : _GEN_7367; // @[L1DCache.scala 582:18]
- wire _GEN_7625 = 3'h6 == fstate ? _GEN_4533 : _GEN_7368; // @[L1DCache.scala 582:18]
- wire _GEN_7626 = 3'h6 == fstate ? _GEN_4534 : _GEN_7369; // @[L1DCache.scala 582:18]
- wire _GEN_7627 = 3'h6 == fstate ? _GEN_4535 : _GEN_7370; // @[L1DCache.scala 582:18]
- wire _GEN_7628 = 3'h6 == fstate ? _GEN_4536 : _GEN_7371; // @[L1DCache.scala 582:18]
- wire _GEN_7629 = 3'h6 == fstate ? _GEN_4537 : _GEN_7372; // @[L1DCache.scala 582:18]
- wire _GEN_7630 = 3'h6 == fstate ? _GEN_4538 : _GEN_7373; // @[L1DCache.scala 582:18]
- wire _GEN_7631 = 3'h6 == fstate ? _GEN_4539 : _GEN_7374; // @[L1DCache.scala 582:18]
- wire _GEN_7632 = 3'h6 == fstate ? _GEN_4540 : _GEN_7375; // @[L1DCache.scala 582:18]
- wire _GEN_7633 = 3'h6 == fstate ? _GEN_4541 : _GEN_7376; // @[L1DCache.scala 582:18]
- wire _GEN_7634 = 3'h6 == fstate ? _GEN_4542 : _GEN_7377; // @[L1DCache.scala 582:18]
- wire _GEN_7635 = 3'h6 == fstate ? _GEN_4543 : _GEN_7378; // @[L1DCache.scala 582:18]
- wire _GEN_7636 = 3'h6 == fstate ? _GEN_4544 : _GEN_7379; // @[L1DCache.scala 582:18]
- wire _GEN_7637 = 3'h6 == fstate ? _GEN_4545 : _GEN_7380; // @[L1DCache.scala 582:18]
- wire _GEN_7638 = 3'h6 == fstate ? _GEN_4546 : _GEN_7381; // @[L1DCache.scala 582:18]
- wire _GEN_7639 = 3'h6 == fstate ? _GEN_4547 : _GEN_7382; // @[L1DCache.scala 582:18]
- wire _GEN_7640 = 3'h6 == fstate ? _GEN_4548 : _GEN_7383; // @[L1DCache.scala 582:18]
- wire _GEN_7641 = 3'h6 == fstate ? _GEN_4549 : _GEN_7384; // @[L1DCache.scala 582:18]
- wire _GEN_7642 = 3'h6 == fstate ? _GEN_4550 : _GEN_7385; // @[L1DCache.scala 582:18]
- wire _GEN_7643 = 3'h6 == fstate ? _GEN_4551 : _GEN_7386; // @[L1DCache.scala 582:18]
- wire _GEN_7644 = 3'h6 == fstate ? _GEN_4552 : _GEN_7387; // @[L1DCache.scala 582:18]
- wire _GEN_7645 = 3'h6 == fstate ? _GEN_4553 : _GEN_7388; // @[L1DCache.scala 582:18]
- wire _GEN_7646 = 3'h6 == fstate ? _GEN_4554 : _GEN_7389; // @[L1DCache.scala 582:18]
- wire _GEN_7647 = 3'h6 == fstate ? _GEN_4555 : _GEN_7390; // @[L1DCache.scala 582:18]
- wire _GEN_7648 = 3'h6 == fstate ? _GEN_4556 : _GEN_7391; // @[L1DCache.scala 582:18]
- wire _GEN_7649 = 3'h6 == fstate ? _GEN_4557 : _GEN_7392; // @[L1DCache.scala 582:18]
- wire _GEN_7650 = 3'h6 == fstate ? _GEN_4558 : _GEN_7393; // @[L1DCache.scala 582:18]
- wire _GEN_7651 = 3'h6 == fstate ? _GEN_4559 : _GEN_7394; // @[L1DCache.scala 582:18]
- wire _GEN_7652 = 3'h6 == fstate ? _GEN_4560 : _GEN_7395; // @[L1DCache.scala 582:18]
- wire _GEN_7653 = 3'h6 == fstate ? _GEN_4561 : _GEN_7396; // @[L1DCache.scala 582:18]
- wire _GEN_7654 = 3'h6 == fstate ? _GEN_4562 : _GEN_7397; // @[L1DCache.scala 582:18]
- wire _GEN_7655 = 3'h6 == fstate ? _GEN_4563 : _GEN_7398; // @[L1DCache.scala 582:18]
- wire _GEN_7656 = 3'h6 == fstate ? _GEN_4564 : _GEN_7399; // @[L1DCache.scala 582:18]
- wire _GEN_7657 = 3'h6 == fstate ? _GEN_4565 : _GEN_7400; // @[L1DCache.scala 582:18]
- wire _GEN_7658 = 3'h6 == fstate ? _GEN_4566 : _GEN_7401; // @[L1DCache.scala 582:18]
- wire _GEN_7659 = 3'h6 == fstate ? _GEN_4567 : _GEN_7402; // @[L1DCache.scala 582:18]
- wire _GEN_7660 = 3'h6 == fstate ? _GEN_4568 : _GEN_7403; // @[L1DCache.scala 582:18]
- wire _GEN_7661 = 3'h6 == fstate ? _GEN_4569 : _GEN_7404; // @[L1DCache.scala 582:18]
- wire _GEN_7662 = 3'h6 == fstate ? _GEN_4570 : _GEN_7405; // @[L1DCache.scala 582:18]
- wire _GEN_7663 = 3'h6 == fstate ? _GEN_4571 : _GEN_7406; // @[L1DCache.scala 582:18]
- wire _GEN_7664 = 3'h6 == fstate ? _GEN_4572 : _GEN_7407; // @[L1DCache.scala 582:18]
- wire _GEN_7665 = 3'h6 == fstate ? _GEN_4573 : _GEN_7408; // @[L1DCache.scala 582:18]
- wire _GEN_7666 = 3'h6 == fstate ? _GEN_4574 : _GEN_7409; // @[L1DCache.scala 582:18]
- wire _GEN_7667 = 3'h6 == fstate ? _GEN_4575 : _GEN_7410; // @[L1DCache.scala 582:18]
- wire _GEN_7668 = 3'h6 == fstate ? _GEN_4576 : _GEN_7411; // @[L1DCache.scala 582:18]
- wire _GEN_7669 = 3'h6 == fstate ? _GEN_4577 : _GEN_7412; // @[L1DCache.scala 582:18]
- wire _GEN_7670 = 3'h6 == fstate ? _GEN_4578 : _GEN_7413; // @[L1DCache.scala 582:18]
- wire _GEN_7671 = 3'h6 == fstate ? _GEN_4579 : _GEN_7414; // @[L1DCache.scala 582:18]
- wire _GEN_7672 = 3'h6 == fstate ? _GEN_4580 : _GEN_7415; // @[L1DCache.scala 582:18]
- wire _GEN_7673 = 3'h6 == fstate ? _GEN_4581 : _GEN_7416; // @[L1DCache.scala 582:18]
- wire _GEN_7674 = 3'h6 == fstate ? _GEN_4582 : _GEN_7417; // @[L1DCache.scala 582:18]
- wire _GEN_7675 = 3'h6 == fstate ? _GEN_4583 : _GEN_7418; // @[L1DCache.scala 582:18]
- wire _GEN_7676 = 3'h6 == fstate ? _GEN_4584 : _GEN_7419; // @[L1DCache.scala 582:18]
- wire _GEN_7677 = 3'h6 == fstate ? _GEN_4585 : _GEN_7420; // @[L1DCache.scala 582:18]
- wire _GEN_7678 = 3'h6 == fstate ? _GEN_4586 : _GEN_7421; // @[L1DCache.scala 582:18]
- wire _GEN_7679 = 3'h6 == fstate ? _GEN_4587 : _GEN_7422; // @[L1DCache.scala 582:18]
- wire _GEN_7680 = 3'h6 == fstate ? _GEN_4588 : _GEN_7423; // @[L1DCache.scala 582:18]
- wire _GEN_7681 = 3'h6 == fstate ? _GEN_4589 : _GEN_7424; // @[L1DCache.scala 582:18]
- wire _GEN_7682 = 3'h6 == fstate ? _GEN_4590 : _GEN_7425; // @[L1DCache.scala 582:18]
- wire _GEN_7683 = 3'h6 == fstate ? _GEN_4591 : _GEN_7426; // @[L1DCache.scala 582:18]
- wire _GEN_7684 = 3'h6 == fstate ? _GEN_4592 : _GEN_7427; // @[L1DCache.scala 582:18]
- wire _GEN_7685 = 3'h6 == fstate ? _GEN_4593 : _GEN_7428; // @[L1DCache.scala 582:18]
- wire _GEN_7686 = 3'h6 == fstate ? _GEN_4594 : _GEN_7429; // @[L1DCache.scala 582:18]
- wire _GEN_7687 = 3'h6 == fstate ? _GEN_4595 : _GEN_7430; // @[L1DCache.scala 582:18]
- wire _GEN_7688 = 3'h6 == fstate ? _GEN_4596 : _GEN_7431; // @[L1DCache.scala 582:18]
- wire _GEN_7689 = 3'h6 == fstate ? _GEN_4597 : _GEN_7432; // @[L1DCache.scala 582:18]
- wire _GEN_7690 = 3'h6 == fstate ? _GEN_4598 : _GEN_7433; // @[L1DCache.scala 582:18]
- wire _GEN_7691 = 3'h6 == fstate ? _GEN_4599 : _GEN_7434; // @[L1DCache.scala 582:18]
- wire _GEN_7692 = 3'h6 == fstate ? _GEN_4600 : _GEN_7435; // @[L1DCache.scala 582:18]
- wire _GEN_7693 = 3'h6 == fstate ? _GEN_4601 : _GEN_7436; // @[L1DCache.scala 582:18]
- wire _GEN_7694 = 3'h6 == fstate ? _GEN_4602 : _GEN_7437; // @[L1DCache.scala 582:18]
- wire _GEN_7695 = 3'h6 == fstate ? _GEN_4603 : _GEN_7438; // @[L1DCache.scala 582:18]
- wire _GEN_7696 = 3'h6 == fstate ? _GEN_4604 : _GEN_7439; // @[L1DCache.scala 582:18]
- wire _GEN_7697 = 3'h6 == fstate ? _GEN_4605 : _GEN_7440; // @[L1DCache.scala 582:18]
- wire _GEN_7698 = 3'h6 == fstate ? _GEN_4606 : _GEN_7441; // @[L1DCache.scala 582:18]
- wire _GEN_7699 = 3'h6 == fstate ? _GEN_4607 : _GEN_7442; // @[L1DCache.scala 582:18]
- wire _GEN_7700 = 3'h6 == fstate ? _GEN_4608 : _GEN_7443; // @[L1DCache.scala 582:18]
- wire _GEN_7701 = 3'h6 == fstate ? _GEN_4609 : _GEN_7444; // @[L1DCache.scala 582:18]
- wire _GEN_7702 = 3'h6 == fstate ? _GEN_4610 : _GEN_7445; // @[L1DCache.scala 582:18]
- wire _GEN_7703 = 3'h6 == fstate ? _GEN_4611 : _GEN_7446; // @[L1DCache.scala 582:18]
- wire _GEN_7704 = 3'h6 == fstate ? _GEN_4612 : _GEN_7447; // @[L1DCache.scala 582:18]
- wire _GEN_7705 = 3'h6 == fstate ? _GEN_4613 : _GEN_7448; // @[L1DCache.scala 582:18]
- wire _GEN_7706 = 3'h6 == fstate ? _GEN_4614 : _GEN_7449; // @[L1DCache.scala 582:18]
- wire _GEN_7707 = 3'h6 == fstate ? _GEN_4615 : _GEN_7450; // @[L1DCache.scala 582:18]
- wire [2:0] _GEN_7708 = 3'h5 == fstate ? _GEN_6679 : _GEN_7451; // @[L1DCache.scala 582:18]
- wire _GEN_7709 = 3'h5 == fstate ? _GEN_4360 : _GEN_7452; // @[L1DCache.scala 582:18]
- wire _GEN_7710 = 3'h5 == fstate ? _GEN_4361 : _GEN_7453; // @[L1DCache.scala 582:18]
- wire _GEN_7711 = 3'h5 == fstate ? _GEN_4362 : _GEN_7454; // @[L1DCache.scala 582:18]
- wire _GEN_7712 = 3'h5 == fstate ? _GEN_4363 : _GEN_7455; // @[L1DCache.scala 582:18]
- wire _GEN_7713 = 3'h5 == fstate ? _GEN_4364 : _GEN_7456; // @[L1DCache.scala 582:18]
- wire _GEN_7714 = 3'h5 == fstate ? _GEN_4365 : _GEN_7457; // @[L1DCache.scala 582:18]
- wire _GEN_7715 = 3'h5 == fstate ? _GEN_4366 : _GEN_7458; // @[L1DCache.scala 582:18]
- wire _GEN_7716 = 3'h5 == fstate ? _GEN_4367 : _GEN_7459; // @[L1DCache.scala 582:18]
- wire _GEN_7717 = 3'h5 == fstate ? _GEN_4368 : _GEN_7460; // @[L1DCache.scala 582:18]
- wire _GEN_7718 = 3'h5 == fstate ? _GEN_4369 : _GEN_7461; // @[L1DCache.scala 582:18]
- wire _GEN_7719 = 3'h5 == fstate ? _GEN_4370 : _GEN_7462; // @[L1DCache.scala 582:18]
- wire _GEN_7720 = 3'h5 == fstate ? _GEN_4371 : _GEN_7463; // @[L1DCache.scala 582:18]
- wire _GEN_7721 = 3'h5 == fstate ? _GEN_4372 : _GEN_7464; // @[L1DCache.scala 582:18]
- wire _GEN_7722 = 3'h5 == fstate ? _GEN_4373 : _GEN_7465; // @[L1DCache.scala 582:18]
- wire _GEN_7723 = 3'h5 == fstate ? _GEN_4374 : _GEN_7466; // @[L1DCache.scala 582:18]
- wire _GEN_7724 = 3'h5 == fstate ? _GEN_4375 : _GEN_7467; // @[L1DCache.scala 582:18]
- wire _GEN_7725 = 3'h5 == fstate ? _GEN_4376 : _GEN_7468; // @[L1DCache.scala 582:18]
- wire _GEN_7726 = 3'h5 == fstate ? _GEN_4377 : _GEN_7469; // @[L1DCache.scala 582:18]
- wire _GEN_7727 = 3'h5 == fstate ? _GEN_4378 : _GEN_7470; // @[L1DCache.scala 582:18]
- wire _GEN_7728 = 3'h5 == fstate ? _GEN_4379 : _GEN_7471; // @[L1DCache.scala 582:18]
- wire _GEN_7729 = 3'h5 == fstate ? _GEN_4380 : _GEN_7472; // @[L1DCache.scala 582:18]
- wire _GEN_7730 = 3'h5 == fstate ? _GEN_4381 : _GEN_7473; // @[L1DCache.scala 582:18]
- wire _GEN_7731 = 3'h5 == fstate ? _GEN_4382 : _GEN_7474; // @[L1DCache.scala 582:18]
- wire _GEN_7732 = 3'h5 == fstate ? _GEN_4383 : _GEN_7475; // @[L1DCache.scala 582:18]
- wire _GEN_7733 = 3'h5 == fstate ? _GEN_4384 : _GEN_7476; // @[L1DCache.scala 582:18]
- wire _GEN_7734 = 3'h5 == fstate ? _GEN_4385 : _GEN_7477; // @[L1DCache.scala 582:18]
- wire _GEN_7735 = 3'h5 == fstate ? _GEN_4386 : _GEN_7478; // @[L1DCache.scala 582:18]
- wire _GEN_7736 = 3'h5 == fstate ? _GEN_4387 : _GEN_7479; // @[L1DCache.scala 582:18]
- wire _GEN_7737 = 3'h5 == fstate ? _GEN_4388 : _GEN_7480; // @[L1DCache.scala 582:18]
- wire _GEN_7738 = 3'h5 == fstate ? _GEN_4389 : _GEN_7481; // @[L1DCache.scala 582:18]
- wire _GEN_7739 = 3'h5 == fstate ? _GEN_4390 : _GEN_7482; // @[L1DCache.scala 582:18]
- wire _GEN_7740 = 3'h5 == fstate ? _GEN_4391 : _GEN_7483; // @[L1DCache.scala 582:18]
- wire _GEN_7741 = 3'h5 == fstate ? _GEN_4392 : _GEN_7484; // @[L1DCache.scala 582:18]
- wire _GEN_7742 = 3'h5 == fstate ? _GEN_4393 : _GEN_7485; // @[L1DCache.scala 582:18]
- wire _GEN_7743 = 3'h5 == fstate ? _GEN_4394 : _GEN_7486; // @[L1DCache.scala 582:18]
- wire _GEN_7744 = 3'h5 == fstate ? _GEN_4395 : _GEN_7487; // @[L1DCache.scala 582:18]
- wire _GEN_7745 = 3'h5 == fstate ? _GEN_4396 : _GEN_7488; // @[L1DCache.scala 582:18]
- wire _GEN_7746 = 3'h5 == fstate ? _GEN_4397 : _GEN_7489; // @[L1DCache.scala 582:18]
- wire _GEN_7747 = 3'h5 == fstate ? _GEN_4398 : _GEN_7490; // @[L1DCache.scala 582:18]
- wire _GEN_7748 = 3'h5 == fstate ? _GEN_4399 : _GEN_7491; // @[L1DCache.scala 582:18]
- wire _GEN_7749 = 3'h5 == fstate ? _GEN_4400 : _GEN_7492; // @[L1DCache.scala 582:18]
- wire _GEN_7750 = 3'h5 == fstate ? _GEN_4401 : _GEN_7493; // @[L1DCache.scala 582:18]
- wire _GEN_7751 = 3'h5 == fstate ? _GEN_4402 : _GEN_7494; // @[L1DCache.scala 582:18]
- wire _GEN_7752 = 3'h5 == fstate ? _GEN_4403 : _GEN_7495; // @[L1DCache.scala 582:18]
- wire _GEN_7753 = 3'h5 == fstate ? _GEN_4404 : _GEN_7496; // @[L1DCache.scala 582:18]
- wire _GEN_7754 = 3'h5 == fstate ? _GEN_4405 : _GEN_7497; // @[L1DCache.scala 582:18]
- wire _GEN_7755 = 3'h5 == fstate ? _GEN_4406 : _GEN_7498; // @[L1DCache.scala 582:18]
- wire _GEN_7756 = 3'h5 == fstate ? _GEN_4407 : _GEN_7499; // @[L1DCache.scala 582:18]
- wire _GEN_7757 = 3'h5 == fstate ? _GEN_4408 : _GEN_7500; // @[L1DCache.scala 582:18]
- wire _GEN_7758 = 3'h5 == fstate ? _GEN_4409 : _GEN_7501; // @[L1DCache.scala 582:18]
- wire _GEN_7759 = 3'h5 == fstate ? _GEN_4410 : _GEN_7502; // @[L1DCache.scala 582:18]
- wire _GEN_7760 = 3'h5 == fstate ? _GEN_4411 : _GEN_7503; // @[L1DCache.scala 582:18]
- wire _GEN_7761 = 3'h5 == fstate ? _GEN_4412 : _GEN_7504; // @[L1DCache.scala 582:18]
- wire _GEN_7762 = 3'h5 == fstate ? _GEN_4413 : _GEN_7505; // @[L1DCache.scala 582:18]
- wire _GEN_7763 = 3'h5 == fstate ? _GEN_4414 : _GEN_7506; // @[L1DCache.scala 582:18]
- wire _GEN_7764 = 3'h5 == fstate ? _GEN_4415 : _GEN_7507; // @[L1DCache.scala 582:18]
- wire _GEN_7765 = 3'h5 == fstate ? _GEN_4416 : _GEN_7508; // @[L1DCache.scala 582:18]
- wire _GEN_7766 = 3'h5 == fstate ? _GEN_4417 : _GEN_7509; // @[L1DCache.scala 582:18]
- wire _GEN_7767 = 3'h5 == fstate ? _GEN_4418 : _GEN_7510; // @[L1DCache.scala 582:18]
- wire _GEN_7768 = 3'h5 == fstate ? _GEN_4419 : _GEN_7511; // @[L1DCache.scala 582:18]
- wire _GEN_7769 = 3'h5 == fstate ? _GEN_4420 : _GEN_7512; // @[L1DCache.scala 582:18]
- wire _GEN_7770 = 3'h5 == fstate ? _GEN_4421 : _GEN_7513; // @[L1DCache.scala 582:18]
- wire _GEN_7771 = 3'h5 == fstate ? _GEN_4422 : _GEN_7514; // @[L1DCache.scala 582:18]
- wire _GEN_7772 = 3'h5 == fstate ? _GEN_4423 : _GEN_7515; // @[L1DCache.scala 582:18]
- wire _GEN_7773 = 3'h5 == fstate ? _GEN_4424 : _GEN_7516; // @[L1DCache.scala 582:18]
- wire _GEN_7774 = 3'h5 == fstate ? _GEN_4425 : _GEN_7517; // @[L1DCache.scala 582:18]
- wire _GEN_7775 = 3'h5 == fstate ? _GEN_4426 : _GEN_7518; // @[L1DCache.scala 582:18]
- wire _GEN_7776 = 3'h5 == fstate ? _GEN_4427 : _GEN_7519; // @[L1DCache.scala 582:18]
- wire _GEN_7777 = 3'h5 == fstate ? _GEN_4428 : _GEN_7520; // @[L1DCache.scala 582:18]
- wire _GEN_7778 = 3'h5 == fstate ? _GEN_4429 : _GEN_7521; // @[L1DCache.scala 582:18]
- wire _GEN_7779 = 3'h5 == fstate ? _GEN_4430 : _GEN_7522; // @[L1DCache.scala 582:18]
- wire _GEN_7780 = 3'h5 == fstate ? _GEN_4431 : _GEN_7523; // @[L1DCache.scala 582:18]
- wire _GEN_7781 = 3'h5 == fstate ? _GEN_4432 : _GEN_7524; // @[L1DCache.scala 582:18]
- wire _GEN_7782 = 3'h5 == fstate ? _GEN_4433 : _GEN_7525; // @[L1DCache.scala 582:18]
- wire _GEN_7783 = 3'h5 == fstate ? _GEN_4434 : _GEN_7526; // @[L1DCache.scala 582:18]
- wire _GEN_7784 = 3'h5 == fstate ? _GEN_4435 : _GEN_7527; // @[L1DCache.scala 582:18]
- wire _GEN_7785 = 3'h5 == fstate ? _GEN_4436 : _GEN_7528; // @[L1DCache.scala 582:18]
- wire _GEN_7786 = 3'h5 == fstate ? _GEN_4437 : _GEN_7529; // @[L1DCache.scala 582:18]
- wire _GEN_7787 = 3'h5 == fstate ? _GEN_4438 : _GEN_7530; // @[L1DCache.scala 582:18]
- wire _GEN_7788 = 3'h5 == fstate ? _GEN_4439 : _GEN_7531; // @[L1DCache.scala 582:18]
- wire _GEN_7789 = 3'h5 == fstate ? _GEN_4440 : _GEN_7532; // @[L1DCache.scala 582:18]
- wire _GEN_7790 = 3'h5 == fstate ? _GEN_4441 : _GEN_7533; // @[L1DCache.scala 582:18]
- wire _GEN_7791 = 3'h5 == fstate ? _GEN_4442 : _GEN_7534; // @[L1DCache.scala 582:18]
- wire _GEN_7792 = 3'h5 == fstate ? _GEN_4443 : _GEN_7535; // @[L1DCache.scala 582:18]
- wire _GEN_7793 = 3'h5 == fstate ? _GEN_4444 : _GEN_7536; // @[L1DCache.scala 582:18]
- wire _GEN_7794 = 3'h5 == fstate ? _GEN_4445 : _GEN_7537; // @[L1DCache.scala 582:18]
- wire _GEN_7795 = 3'h5 == fstate ? _GEN_4446 : _GEN_7538; // @[L1DCache.scala 582:18]
- wire _GEN_7796 = 3'h5 == fstate ? _GEN_4447 : _GEN_7539; // @[L1DCache.scala 582:18]
- wire _GEN_7797 = 3'h5 == fstate ? _GEN_4448 : _GEN_7540; // @[L1DCache.scala 582:18]
- wire _GEN_7798 = 3'h5 == fstate ? _GEN_4449 : _GEN_7541; // @[L1DCache.scala 582:18]
- wire _GEN_7799 = 3'h5 == fstate ? _GEN_4450 : _GEN_7542; // @[L1DCache.scala 582:18]
- wire _GEN_7800 = 3'h5 == fstate ? _GEN_4451 : _GEN_7543; // @[L1DCache.scala 582:18]
- wire _GEN_7801 = 3'h5 == fstate ? _GEN_4452 : _GEN_7544; // @[L1DCache.scala 582:18]
- wire _GEN_7802 = 3'h5 == fstate ? _GEN_4453 : _GEN_7545; // @[L1DCache.scala 582:18]
- wire _GEN_7803 = 3'h5 == fstate ? _GEN_4454 : _GEN_7546; // @[L1DCache.scala 582:18]
- wire _GEN_7804 = 3'h5 == fstate ? _GEN_4455 : _GEN_7547; // @[L1DCache.scala 582:18]
- wire _GEN_7805 = 3'h5 == fstate ? _GEN_4456 : _GEN_7548; // @[L1DCache.scala 582:18]
- wire _GEN_7806 = 3'h5 == fstate ? _GEN_4457 : _GEN_7549; // @[L1DCache.scala 582:18]
- wire _GEN_7807 = 3'h5 == fstate ? _GEN_4458 : _GEN_7550; // @[L1DCache.scala 582:18]
- wire _GEN_7808 = 3'h5 == fstate ? _GEN_4459 : _GEN_7551; // @[L1DCache.scala 582:18]
- wire _GEN_7809 = 3'h5 == fstate ? _GEN_4460 : _GEN_7552; // @[L1DCache.scala 582:18]
- wire _GEN_7810 = 3'h5 == fstate ? _GEN_4461 : _GEN_7553; // @[L1DCache.scala 582:18]
- wire _GEN_7811 = 3'h5 == fstate ? _GEN_4462 : _GEN_7554; // @[L1DCache.scala 582:18]
- wire _GEN_7812 = 3'h5 == fstate ? _GEN_4463 : _GEN_7555; // @[L1DCache.scala 582:18]
- wire _GEN_7813 = 3'h5 == fstate ? _GEN_4464 : _GEN_7556; // @[L1DCache.scala 582:18]
- wire _GEN_7814 = 3'h5 == fstate ? _GEN_4465 : _GEN_7557; // @[L1DCache.scala 582:18]
- wire _GEN_7815 = 3'h5 == fstate ? _GEN_4466 : _GEN_7558; // @[L1DCache.scala 582:18]
- wire _GEN_7816 = 3'h5 == fstate ? _GEN_4467 : _GEN_7559; // @[L1DCache.scala 582:18]
- wire _GEN_7817 = 3'h5 == fstate ? _GEN_4468 : _GEN_7560; // @[L1DCache.scala 582:18]
- wire _GEN_7818 = 3'h5 == fstate ? _GEN_4469 : _GEN_7561; // @[L1DCache.scala 582:18]
- wire _GEN_7819 = 3'h5 == fstate ? _GEN_4470 : _GEN_7562; // @[L1DCache.scala 582:18]
- wire _GEN_7820 = 3'h5 == fstate ? _GEN_4471 : _GEN_7563; // @[L1DCache.scala 582:18]
- wire _GEN_7821 = 3'h5 == fstate ? _GEN_4472 : _GEN_7564; // @[L1DCache.scala 582:18]
- wire _GEN_7822 = 3'h5 == fstate ? _GEN_4473 : _GEN_7565; // @[L1DCache.scala 582:18]
- wire _GEN_7823 = 3'h5 == fstate ? _GEN_4474 : _GEN_7566; // @[L1DCache.scala 582:18]
- wire _GEN_7824 = 3'h5 == fstate ? _GEN_4475 : _GEN_7567; // @[L1DCache.scala 582:18]
- wire _GEN_7825 = 3'h5 == fstate ? _GEN_4476 : _GEN_7568; // @[L1DCache.scala 582:18]
- wire _GEN_7826 = 3'h5 == fstate ? _GEN_4477 : _GEN_7569; // @[L1DCache.scala 582:18]
- wire _GEN_7827 = 3'h5 == fstate ? _GEN_4478 : _GEN_7570; // @[L1DCache.scala 582:18]
- wire _GEN_7828 = 3'h5 == fstate ? _GEN_4479 : _GEN_7571; // @[L1DCache.scala 582:18]
- wire _GEN_7829 = 3'h5 == fstate ? _GEN_4480 : _GEN_7572; // @[L1DCache.scala 582:18]
- wire _GEN_7830 = 3'h5 == fstate ? _GEN_4481 : _GEN_7573; // @[L1DCache.scala 582:18]
- wire _GEN_7831 = 3'h5 == fstate ? _GEN_4482 : _GEN_7574; // @[L1DCache.scala 582:18]
- wire _GEN_7832 = 3'h5 == fstate ? _GEN_4483 : _GEN_7575; // @[L1DCache.scala 582:18]
- wire _GEN_7833 = 3'h5 == fstate ? _GEN_4484 : _GEN_7576; // @[L1DCache.scala 582:18]
- wire _GEN_7834 = 3'h5 == fstate ? _GEN_4485 : _GEN_7577; // @[L1DCache.scala 582:18]
- wire _GEN_7835 = 3'h5 == fstate ? _GEN_4486 : _GEN_7578; // @[L1DCache.scala 582:18]
- wire _GEN_7836 = 3'h5 == fstate ? _GEN_4487 : _GEN_7579; // @[L1DCache.scala 582:18]
- wire _GEN_7837 = 3'h5 == fstate ? _GEN_4488 : _GEN_7580; // @[L1DCache.scala 582:18]
- wire _GEN_7838 = 3'h5 == fstate ? _GEN_4489 : _GEN_7581; // @[L1DCache.scala 582:18]
- wire _GEN_7839 = 3'h5 == fstate ? _GEN_4490 : _GEN_7582; // @[L1DCache.scala 582:18]
- wire _GEN_7840 = 3'h5 == fstate ? _GEN_4491 : _GEN_7583; // @[L1DCache.scala 582:18]
- wire _GEN_7841 = 3'h5 == fstate ? _GEN_4492 : _GEN_7584; // @[L1DCache.scala 582:18]
- wire _GEN_7842 = 3'h5 == fstate ? _GEN_4493 : _GEN_7585; // @[L1DCache.scala 582:18]
- wire _GEN_7843 = 3'h5 == fstate ? _GEN_4494 : _GEN_7586; // @[L1DCache.scala 582:18]
- wire _GEN_7844 = 3'h5 == fstate ? _GEN_4495 : _GEN_7587; // @[L1DCache.scala 582:18]
- wire _GEN_7845 = 3'h5 == fstate ? _GEN_4496 : _GEN_7588; // @[L1DCache.scala 582:18]
- wire _GEN_7846 = 3'h5 == fstate ? _GEN_4497 : _GEN_7589; // @[L1DCache.scala 582:18]
- wire _GEN_7847 = 3'h5 == fstate ? _GEN_4498 : _GEN_7590; // @[L1DCache.scala 582:18]
- wire _GEN_7848 = 3'h5 == fstate ? _GEN_4499 : _GEN_7591; // @[L1DCache.scala 582:18]
- wire _GEN_7849 = 3'h5 == fstate ? _GEN_4500 : _GEN_7592; // @[L1DCache.scala 582:18]
- wire _GEN_7850 = 3'h5 == fstate ? _GEN_4501 : _GEN_7593; // @[L1DCache.scala 582:18]
- wire _GEN_7851 = 3'h5 == fstate ? _GEN_4502 : _GEN_7594; // @[L1DCache.scala 582:18]
- wire _GEN_7852 = 3'h5 == fstate ? _GEN_4503 : _GEN_7595; // @[L1DCache.scala 582:18]
- wire _GEN_7853 = 3'h5 == fstate ? _GEN_4504 : _GEN_7596; // @[L1DCache.scala 582:18]
- wire _GEN_7854 = 3'h5 == fstate ? _GEN_4505 : _GEN_7597; // @[L1DCache.scala 582:18]
- wire _GEN_7855 = 3'h5 == fstate ? _GEN_4506 : _GEN_7598; // @[L1DCache.scala 582:18]
- wire _GEN_7856 = 3'h5 == fstate ? _GEN_4507 : _GEN_7599; // @[L1DCache.scala 582:18]
- wire _GEN_7857 = 3'h5 == fstate ? _GEN_4508 : _GEN_7600; // @[L1DCache.scala 582:18]
- wire _GEN_7858 = 3'h5 == fstate ? _GEN_4509 : _GEN_7601; // @[L1DCache.scala 582:18]
- wire _GEN_7859 = 3'h5 == fstate ? _GEN_4510 : _GEN_7602; // @[L1DCache.scala 582:18]
- wire _GEN_7860 = 3'h5 == fstate ? _GEN_4511 : _GEN_7603; // @[L1DCache.scala 582:18]
- wire _GEN_7861 = 3'h5 == fstate ? _GEN_4512 : _GEN_7604; // @[L1DCache.scala 582:18]
- wire _GEN_7862 = 3'h5 == fstate ? _GEN_4513 : _GEN_7605; // @[L1DCache.scala 582:18]
- wire _GEN_7863 = 3'h5 == fstate ? _GEN_4514 : _GEN_7606; // @[L1DCache.scala 582:18]
- wire _GEN_7864 = 3'h5 == fstate ? _GEN_4515 : _GEN_7607; // @[L1DCache.scala 582:18]
- wire _GEN_7865 = 3'h5 == fstate ? _GEN_4516 : _GEN_7608; // @[L1DCache.scala 582:18]
- wire _GEN_7866 = 3'h5 == fstate ? _GEN_4517 : _GEN_7609; // @[L1DCache.scala 582:18]
- wire _GEN_7867 = 3'h5 == fstate ? _GEN_4518 : _GEN_7610; // @[L1DCache.scala 582:18]
- wire _GEN_7868 = 3'h5 == fstate ? _GEN_4519 : _GEN_7611; // @[L1DCache.scala 582:18]
- wire _GEN_7869 = 3'h5 == fstate ? _GEN_4520 : _GEN_7612; // @[L1DCache.scala 582:18]
- wire _GEN_7870 = 3'h5 == fstate ? _GEN_4521 : _GEN_7613; // @[L1DCache.scala 582:18]
- wire _GEN_7871 = 3'h5 == fstate ? _GEN_4522 : _GEN_7614; // @[L1DCache.scala 582:18]
- wire _GEN_7872 = 3'h5 == fstate ? _GEN_4523 : _GEN_7615; // @[L1DCache.scala 582:18]
- wire _GEN_7873 = 3'h5 == fstate ? _GEN_4524 : _GEN_7616; // @[L1DCache.scala 582:18]
- wire _GEN_7874 = 3'h5 == fstate ? _GEN_4525 : _GEN_7617; // @[L1DCache.scala 582:18]
- wire _GEN_7875 = 3'h5 == fstate ? _GEN_4526 : _GEN_7618; // @[L1DCache.scala 582:18]
- wire _GEN_7876 = 3'h5 == fstate ? _GEN_4527 : _GEN_7619; // @[L1DCache.scala 582:18]
- wire _GEN_7877 = 3'h5 == fstate ? _GEN_4528 : _GEN_7620; // @[L1DCache.scala 582:18]
- wire _GEN_7878 = 3'h5 == fstate ? _GEN_4529 : _GEN_7621; // @[L1DCache.scala 582:18]
- wire _GEN_7879 = 3'h5 == fstate ? _GEN_4530 : _GEN_7622; // @[L1DCache.scala 582:18]
- wire _GEN_7880 = 3'h5 == fstate ? _GEN_4531 : _GEN_7623; // @[L1DCache.scala 582:18]
- wire _GEN_7881 = 3'h5 == fstate ? _GEN_4532 : _GEN_7624; // @[L1DCache.scala 582:18]
- wire _GEN_7882 = 3'h5 == fstate ? _GEN_4533 : _GEN_7625; // @[L1DCache.scala 582:18]
- wire _GEN_7883 = 3'h5 == fstate ? _GEN_4534 : _GEN_7626; // @[L1DCache.scala 582:18]
- wire _GEN_7884 = 3'h5 == fstate ? _GEN_4535 : _GEN_7627; // @[L1DCache.scala 582:18]
- wire _GEN_7885 = 3'h5 == fstate ? _GEN_4536 : _GEN_7628; // @[L1DCache.scala 582:18]
- wire _GEN_7886 = 3'h5 == fstate ? _GEN_4537 : _GEN_7629; // @[L1DCache.scala 582:18]
- wire _GEN_7887 = 3'h5 == fstate ? _GEN_4538 : _GEN_7630; // @[L1DCache.scala 582:18]
- wire _GEN_7888 = 3'h5 == fstate ? _GEN_4539 : _GEN_7631; // @[L1DCache.scala 582:18]
- wire _GEN_7889 = 3'h5 == fstate ? _GEN_4540 : _GEN_7632; // @[L1DCache.scala 582:18]
- wire _GEN_7890 = 3'h5 == fstate ? _GEN_4541 : _GEN_7633; // @[L1DCache.scala 582:18]
- wire _GEN_7891 = 3'h5 == fstate ? _GEN_4542 : _GEN_7634; // @[L1DCache.scala 582:18]
- wire _GEN_7892 = 3'h5 == fstate ? _GEN_4543 : _GEN_7635; // @[L1DCache.scala 582:18]
- wire _GEN_7893 = 3'h5 == fstate ? _GEN_4544 : _GEN_7636; // @[L1DCache.scala 582:18]
- wire _GEN_7894 = 3'h5 == fstate ? _GEN_4545 : _GEN_7637; // @[L1DCache.scala 582:18]
- wire _GEN_7895 = 3'h5 == fstate ? _GEN_4546 : _GEN_7638; // @[L1DCache.scala 582:18]
- wire _GEN_7896 = 3'h5 == fstate ? _GEN_4547 : _GEN_7639; // @[L1DCache.scala 582:18]
- wire _GEN_7897 = 3'h5 == fstate ? _GEN_4548 : _GEN_7640; // @[L1DCache.scala 582:18]
- wire _GEN_7898 = 3'h5 == fstate ? _GEN_4549 : _GEN_7641; // @[L1DCache.scala 582:18]
- wire _GEN_7899 = 3'h5 == fstate ? _GEN_4550 : _GEN_7642; // @[L1DCache.scala 582:18]
- wire _GEN_7900 = 3'h5 == fstate ? _GEN_4551 : _GEN_7643; // @[L1DCache.scala 582:18]
- wire _GEN_7901 = 3'h5 == fstate ? _GEN_4552 : _GEN_7644; // @[L1DCache.scala 582:18]
- wire _GEN_7902 = 3'h5 == fstate ? _GEN_4553 : _GEN_7645; // @[L1DCache.scala 582:18]
- wire _GEN_7903 = 3'h5 == fstate ? _GEN_4554 : _GEN_7646; // @[L1DCache.scala 582:18]
- wire _GEN_7904 = 3'h5 == fstate ? _GEN_4555 : _GEN_7647; // @[L1DCache.scala 582:18]
- wire _GEN_7905 = 3'h5 == fstate ? _GEN_4556 : _GEN_7648; // @[L1DCache.scala 582:18]
- wire _GEN_7906 = 3'h5 == fstate ? _GEN_4557 : _GEN_7649; // @[L1DCache.scala 582:18]
- wire _GEN_7907 = 3'h5 == fstate ? _GEN_4558 : _GEN_7650; // @[L1DCache.scala 582:18]
- wire _GEN_7908 = 3'h5 == fstate ? _GEN_4559 : _GEN_7651; // @[L1DCache.scala 582:18]
- wire _GEN_7909 = 3'h5 == fstate ? _GEN_4560 : _GEN_7652; // @[L1DCache.scala 582:18]
- wire _GEN_7910 = 3'h5 == fstate ? _GEN_4561 : _GEN_7653; // @[L1DCache.scala 582:18]
- wire _GEN_7911 = 3'h5 == fstate ? _GEN_4562 : _GEN_7654; // @[L1DCache.scala 582:18]
- wire _GEN_7912 = 3'h5 == fstate ? _GEN_4563 : _GEN_7655; // @[L1DCache.scala 582:18]
- wire _GEN_7913 = 3'h5 == fstate ? _GEN_4564 : _GEN_7656; // @[L1DCache.scala 582:18]
- wire _GEN_7914 = 3'h5 == fstate ? _GEN_4565 : _GEN_7657; // @[L1DCache.scala 582:18]
- wire _GEN_7915 = 3'h5 == fstate ? _GEN_4566 : _GEN_7658; // @[L1DCache.scala 582:18]
- wire _GEN_7916 = 3'h5 == fstate ? _GEN_4567 : _GEN_7659; // @[L1DCache.scala 582:18]
- wire _GEN_7917 = 3'h5 == fstate ? _GEN_4568 : _GEN_7660; // @[L1DCache.scala 582:18]
- wire _GEN_7918 = 3'h5 == fstate ? _GEN_4569 : _GEN_7661; // @[L1DCache.scala 582:18]
- wire _GEN_7919 = 3'h5 == fstate ? _GEN_4570 : _GEN_7662; // @[L1DCache.scala 582:18]
- wire _GEN_7920 = 3'h5 == fstate ? _GEN_4571 : _GEN_7663; // @[L1DCache.scala 582:18]
- wire _GEN_7921 = 3'h5 == fstate ? _GEN_4572 : _GEN_7664; // @[L1DCache.scala 582:18]
- wire _GEN_7922 = 3'h5 == fstate ? _GEN_4573 : _GEN_7665; // @[L1DCache.scala 582:18]
- wire _GEN_7923 = 3'h5 == fstate ? _GEN_4574 : _GEN_7666; // @[L1DCache.scala 582:18]
- wire _GEN_7924 = 3'h5 == fstate ? _GEN_4575 : _GEN_7667; // @[L1DCache.scala 582:18]
- wire _GEN_7925 = 3'h5 == fstate ? _GEN_4576 : _GEN_7668; // @[L1DCache.scala 582:18]
- wire _GEN_7926 = 3'h5 == fstate ? _GEN_4577 : _GEN_7669; // @[L1DCache.scala 582:18]
- wire _GEN_7927 = 3'h5 == fstate ? _GEN_4578 : _GEN_7670; // @[L1DCache.scala 582:18]
- wire _GEN_7928 = 3'h5 == fstate ? _GEN_4579 : _GEN_7671; // @[L1DCache.scala 582:18]
- wire _GEN_7929 = 3'h5 == fstate ? _GEN_4580 : _GEN_7672; // @[L1DCache.scala 582:18]
- wire _GEN_7930 = 3'h5 == fstate ? _GEN_4581 : _GEN_7673; // @[L1DCache.scala 582:18]
- wire _GEN_7931 = 3'h5 == fstate ? _GEN_4582 : _GEN_7674; // @[L1DCache.scala 582:18]
- wire _GEN_7932 = 3'h5 == fstate ? _GEN_4583 : _GEN_7675; // @[L1DCache.scala 582:18]
- wire _GEN_7933 = 3'h5 == fstate ? _GEN_4584 : _GEN_7676; // @[L1DCache.scala 582:18]
- wire _GEN_7934 = 3'h5 == fstate ? _GEN_4585 : _GEN_7677; // @[L1DCache.scala 582:18]
- wire _GEN_7935 = 3'h5 == fstate ? _GEN_4586 : _GEN_7678; // @[L1DCache.scala 582:18]
- wire _GEN_7936 = 3'h5 == fstate ? _GEN_4587 : _GEN_7679; // @[L1DCache.scala 582:18]
- wire _GEN_7937 = 3'h5 == fstate ? _GEN_4588 : _GEN_7680; // @[L1DCache.scala 582:18]
- wire _GEN_7938 = 3'h5 == fstate ? _GEN_4589 : _GEN_7681; // @[L1DCache.scala 582:18]
- wire _GEN_7939 = 3'h5 == fstate ? _GEN_4590 : _GEN_7682; // @[L1DCache.scala 582:18]
- wire _GEN_7940 = 3'h5 == fstate ? _GEN_4591 : _GEN_7683; // @[L1DCache.scala 582:18]
- wire _GEN_7941 = 3'h5 == fstate ? _GEN_4592 : _GEN_7684; // @[L1DCache.scala 582:18]
- wire _GEN_7942 = 3'h5 == fstate ? _GEN_4593 : _GEN_7685; // @[L1DCache.scala 582:18]
- wire _GEN_7943 = 3'h5 == fstate ? _GEN_4594 : _GEN_7686; // @[L1DCache.scala 582:18]
- wire _GEN_7944 = 3'h5 == fstate ? _GEN_4595 : _GEN_7687; // @[L1DCache.scala 582:18]
- wire _GEN_7945 = 3'h5 == fstate ? _GEN_4596 : _GEN_7688; // @[L1DCache.scala 582:18]
- wire _GEN_7946 = 3'h5 == fstate ? _GEN_4597 : _GEN_7689; // @[L1DCache.scala 582:18]
- wire _GEN_7947 = 3'h5 == fstate ? _GEN_4598 : _GEN_7690; // @[L1DCache.scala 582:18]
- wire _GEN_7948 = 3'h5 == fstate ? _GEN_4599 : _GEN_7691; // @[L1DCache.scala 582:18]
- wire _GEN_7949 = 3'h5 == fstate ? _GEN_4600 : _GEN_7692; // @[L1DCache.scala 582:18]
- wire _GEN_7950 = 3'h5 == fstate ? _GEN_4601 : _GEN_7693; // @[L1DCache.scala 582:18]
- wire _GEN_7951 = 3'h5 == fstate ? _GEN_4602 : _GEN_7694; // @[L1DCache.scala 582:18]
- wire _GEN_7952 = 3'h5 == fstate ? _GEN_4603 : _GEN_7695; // @[L1DCache.scala 582:18]
- wire _GEN_7953 = 3'h5 == fstate ? _GEN_4604 : _GEN_7696; // @[L1DCache.scala 582:18]
- wire _GEN_7954 = 3'h5 == fstate ? _GEN_4605 : _GEN_7697; // @[L1DCache.scala 582:18]
- wire _GEN_7955 = 3'h5 == fstate ? _GEN_4606 : _GEN_7698; // @[L1DCache.scala 582:18]
- wire _GEN_7956 = 3'h5 == fstate ? _GEN_4607 : _GEN_7699; // @[L1DCache.scala 582:18]
- wire _GEN_7957 = 3'h5 == fstate ? _GEN_4608 : _GEN_7700; // @[L1DCache.scala 582:18]
- wire _GEN_7958 = 3'h5 == fstate ? _GEN_4609 : _GEN_7701; // @[L1DCache.scala 582:18]
- wire _GEN_7959 = 3'h5 == fstate ? _GEN_4610 : _GEN_7702; // @[L1DCache.scala 582:18]
- wire _GEN_7960 = 3'h5 == fstate ? _GEN_4611 : _GEN_7703; // @[L1DCache.scala 582:18]
- wire _GEN_7961 = 3'h5 == fstate ? _GEN_4612 : _GEN_7704; // @[L1DCache.scala 582:18]
- wire _GEN_7962 = 3'h5 == fstate ? _GEN_4613 : _GEN_7705; // @[L1DCache.scala 582:18]
- wire _GEN_7963 = 3'h5 == fstate ? _GEN_4614 : _GEN_7706; // @[L1DCache.scala 582:18]
- wire _GEN_7964 = 3'h5 == fstate ? _GEN_4615 : _GEN_7707; // @[L1DCache.scala 582:18]
- wire [2:0] _GEN_7965 = 3'h4 == fstate ? 3'h5 : _GEN_7708; // @[L1DCache.scala 582:18 623:14]
- wire _GEN_7966 = 3'h4 == fstate ? _GEN_4360 : _GEN_7709; // @[L1DCache.scala 582:18]
- wire _GEN_7967 = 3'h4 == fstate ? _GEN_4361 : _GEN_7710; // @[L1DCache.scala 582:18]
- wire _GEN_7968 = 3'h4 == fstate ? _GEN_4362 : _GEN_7711; // @[L1DCache.scala 582:18]
- wire _GEN_7969 = 3'h4 == fstate ? _GEN_4363 : _GEN_7712; // @[L1DCache.scala 582:18]
- wire _GEN_7970 = 3'h4 == fstate ? _GEN_4364 : _GEN_7713; // @[L1DCache.scala 582:18]
- wire _GEN_7971 = 3'h4 == fstate ? _GEN_4365 : _GEN_7714; // @[L1DCache.scala 582:18]
- wire _GEN_7972 = 3'h4 == fstate ? _GEN_4366 : _GEN_7715; // @[L1DCache.scala 582:18]
- wire _GEN_7973 = 3'h4 == fstate ? _GEN_4367 : _GEN_7716; // @[L1DCache.scala 582:18]
- wire _GEN_7974 = 3'h4 == fstate ? _GEN_4368 : _GEN_7717; // @[L1DCache.scala 582:18]
- wire _GEN_7975 = 3'h4 == fstate ? _GEN_4369 : _GEN_7718; // @[L1DCache.scala 582:18]
- wire _GEN_7976 = 3'h4 == fstate ? _GEN_4370 : _GEN_7719; // @[L1DCache.scala 582:18]
- wire _GEN_7977 = 3'h4 == fstate ? _GEN_4371 : _GEN_7720; // @[L1DCache.scala 582:18]
- wire _GEN_7978 = 3'h4 == fstate ? _GEN_4372 : _GEN_7721; // @[L1DCache.scala 582:18]
- wire _GEN_7979 = 3'h4 == fstate ? _GEN_4373 : _GEN_7722; // @[L1DCache.scala 582:18]
- wire _GEN_7980 = 3'h4 == fstate ? _GEN_4374 : _GEN_7723; // @[L1DCache.scala 582:18]
- wire _GEN_7981 = 3'h4 == fstate ? _GEN_4375 : _GEN_7724; // @[L1DCache.scala 582:18]
- wire _GEN_7982 = 3'h4 == fstate ? _GEN_4376 : _GEN_7725; // @[L1DCache.scala 582:18]
- wire _GEN_7983 = 3'h4 == fstate ? _GEN_4377 : _GEN_7726; // @[L1DCache.scala 582:18]
- wire _GEN_7984 = 3'h4 == fstate ? _GEN_4378 : _GEN_7727; // @[L1DCache.scala 582:18]
- wire _GEN_7985 = 3'h4 == fstate ? _GEN_4379 : _GEN_7728; // @[L1DCache.scala 582:18]
- wire _GEN_7986 = 3'h4 == fstate ? _GEN_4380 : _GEN_7729; // @[L1DCache.scala 582:18]
- wire _GEN_7987 = 3'h4 == fstate ? _GEN_4381 : _GEN_7730; // @[L1DCache.scala 582:18]
- wire _GEN_7988 = 3'h4 == fstate ? _GEN_4382 : _GEN_7731; // @[L1DCache.scala 582:18]
- wire _GEN_7989 = 3'h4 == fstate ? _GEN_4383 : _GEN_7732; // @[L1DCache.scala 582:18]
- wire _GEN_7990 = 3'h4 == fstate ? _GEN_4384 : _GEN_7733; // @[L1DCache.scala 582:18]
- wire _GEN_7991 = 3'h4 == fstate ? _GEN_4385 : _GEN_7734; // @[L1DCache.scala 582:18]
- wire _GEN_7992 = 3'h4 == fstate ? _GEN_4386 : _GEN_7735; // @[L1DCache.scala 582:18]
- wire _GEN_7993 = 3'h4 == fstate ? _GEN_4387 : _GEN_7736; // @[L1DCache.scala 582:18]
- wire _GEN_7994 = 3'h4 == fstate ? _GEN_4388 : _GEN_7737; // @[L1DCache.scala 582:18]
- wire _GEN_7995 = 3'h4 == fstate ? _GEN_4389 : _GEN_7738; // @[L1DCache.scala 582:18]
- wire _GEN_7996 = 3'h4 == fstate ? _GEN_4390 : _GEN_7739; // @[L1DCache.scala 582:18]
- wire _GEN_7997 = 3'h4 == fstate ? _GEN_4391 : _GEN_7740; // @[L1DCache.scala 582:18]
- wire _GEN_7998 = 3'h4 == fstate ? _GEN_4392 : _GEN_7741; // @[L1DCache.scala 582:18]
- wire _GEN_7999 = 3'h4 == fstate ? _GEN_4393 : _GEN_7742; // @[L1DCache.scala 582:18]
- wire _GEN_8000 = 3'h4 == fstate ? _GEN_4394 : _GEN_7743; // @[L1DCache.scala 582:18]
- wire _GEN_8001 = 3'h4 == fstate ? _GEN_4395 : _GEN_7744; // @[L1DCache.scala 582:18]
- wire _GEN_8002 = 3'h4 == fstate ? _GEN_4396 : _GEN_7745; // @[L1DCache.scala 582:18]
- wire _GEN_8003 = 3'h4 == fstate ? _GEN_4397 : _GEN_7746; // @[L1DCache.scala 582:18]
- wire _GEN_8004 = 3'h4 == fstate ? _GEN_4398 : _GEN_7747; // @[L1DCache.scala 582:18]
- wire _GEN_8005 = 3'h4 == fstate ? _GEN_4399 : _GEN_7748; // @[L1DCache.scala 582:18]
- wire _GEN_8006 = 3'h4 == fstate ? _GEN_4400 : _GEN_7749; // @[L1DCache.scala 582:18]
- wire _GEN_8007 = 3'h4 == fstate ? _GEN_4401 : _GEN_7750; // @[L1DCache.scala 582:18]
- wire _GEN_8008 = 3'h4 == fstate ? _GEN_4402 : _GEN_7751; // @[L1DCache.scala 582:18]
- wire _GEN_8009 = 3'h4 == fstate ? _GEN_4403 : _GEN_7752; // @[L1DCache.scala 582:18]
- wire _GEN_8010 = 3'h4 == fstate ? _GEN_4404 : _GEN_7753; // @[L1DCache.scala 582:18]
- wire _GEN_8011 = 3'h4 == fstate ? _GEN_4405 : _GEN_7754; // @[L1DCache.scala 582:18]
- wire _GEN_8012 = 3'h4 == fstate ? _GEN_4406 : _GEN_7755; // @[L1DCache.scala 582:18]
- wire _GEN_8013 = 3'h4 == fstate ? _GEN_4407 : _GEN_7756; // @[L1DCache.scala 582:18]
- wire _GEN_8014 = 3'h4 == fstate ? _GEN_4408 : _GEN_7757; // @[L1DCache.scala 582:18]
- wire _GEN_8015 = 3'h4 == fstate ? _GEN_4409 : _GEN_7758; // @[L1DCache.scala 582:18]
- wire _GEN_8016 = 3'h4 == fstate ? _GEN_4410 : _GEN_7759; // @[L1DCache.scala 582:18]
- wire _GEN_8017 = 3'h4 == fstate ? _GEN_4411 : _GEN_7760; // @[L1DCache.scala 582:18]
- wire _GEN_8018 = 3'h4 == fstate ? _GEN_4412 : _GEN_7761; // @[L1DCache.scala 582:18]
- wire _GEN_8019 = 3'h4 == fstate ? _GEN_4413 : _GEN_7762; // @[L1DCache.scala 582:18]
- wire _GEN_8020 = 3'h4 == fstate ? _GEN_4414 : _GEN_7763; // @[L1DCache.scala 582:18]
- wire _GEN_8021 = 3'h4 == fstate ? _GEN_4415 : _GEN_7764; // @[L1DCache.scala 582:18]
- wire _GEN_8022 = 3'h4 == fstate ? _GEN_4416 : _GEN_7765; // @[L1DCache.scala 582:18]
- wire _GEN_8023 = 3'h4 == fstate ? _GEN_4417 : _GEN_7766; // @[L1DCache.scala 582:18]
- wire _GEN_8024 = 3'h4 == fstate ? _GEN_4418 : _GEN_7767; // @[L1DCache.scala 582:18]
- wire _GEN_8025 = 3'h4 == fstate ? _GEN_4419 : _GEN_7768; // @[L1DCache.scala 582:18]
- wire _GEN_8026 = 3'h4 == fstate ? _GEN_4420 : _GEN_7769; // @[L1DCache.scala 582:18]
- wire _GEN_8027 = 3'h4 == fstate ? _GEN_4421 : _GEN_7770; // @[L1DCache.scala 582:18]
- wire _GEN_8028 = 3'h4 == fstate ? _GEN_4422 : _GEN_7771; // @[L1DCache.scala 582:18]
- wire _GEN_8029 = 3'h4 == fstate ? _GEN_4423 : _GEN_7772; // @[L1DCache.scala 582:18]
- wire _GEN_8030 = 3'h4 == fstate ? _GEN_4424 : _GEN_7773; // @[L1DCache.scala 582:18]
- wire _GEN_8031 = 3'h4 == fstate ? _GEN_4425 : _GEN_7774; // @[L1DCache.scala 582:18]
- wire _GEN_8032 = 3'h4 == fstate ? _GEN_4426 : _GEN_7775; // @[L1DCache.scala 582:18]
- wire _GEN_8033 = 3'h4 == fstate ? _GEN_4427 : _GEN_7776; // @[L1DCache.scala 582:18]
- wire _GEN_8034 = 3'h4 == fstate ? _GEN_4428 : _GEN_7777; // @[L1DCache.scala 582:18]
- wire _GEN_8035 = 3'h4 == fstate ? _GEN_4429 : _GEN_7778; // @[L1DCache.scala 582:18]
- wire _GEN_8036 = 3'h4 == fstate ? _GEN_4430 : _GEN_7779; // @[L1DCache.scala 582:18]
- wire _GEN_8037 = 3'h4 == fstate ? _GEN_4431 : _GEN_7780; // @[L1DCache.scala 582:18]
- wire _GEN_8038 = 3'h4 == fstate ? _GEN_4432 : _GEN_7781; // @[L1DCache.scala 582:18]
- wire _GEN_8039 = 3'h4 == fstate ? _GEN_4433 : _GEN_7782; // @[L1DCache.scala 582:18]
- wire _GEN_8040 = 3'h4 == fstate ? _GEN_4434 : _GEN_7783; // @[L1DCache.scala 582:18]
- wire _GEN_8041 = 3'h4 == fstate ? _GEN_4435 : _GEN_7784; // @[L1DCache.scala 582:18]
- wire _GEN_8042 = 3'h4 == fstate ? _GEN_4436 : _GEN_7785; // @[L1DCache.scala 582:18]
- wire _GEN_8043 = 3'h4 == fstate ? _GEN_4437 : _GEN_7786; // @[L1DCache.scala 582:18]
- wire _GEN_8044 = 3'h4 == fstate ? _GEN_4438 : _GEN_7787; // @[L1DCache.scala 582:18]
- wire _GEN_8045 = 3'h4 == fstate ? _GEN_4439 : _GEN_7788; // @[L1DCache.scala 582:18]
- wire _GEN_8046 = 3'h4 == fstate ? _GEN_4440 : _GEN_7789; // @[L1DCache.scala 582:18]
- wire _GEN_8047 = 3'h4 == fstate ? _GEN_4441 : _GEN_7790; // @[L1DCache.scala 582:18]
- wire _GEN_8048 = 3'h4 == fstate ? _GEN_4442 : _GEN_7791; // @[L1DCache.scala 582:18]
- wire _GEN_8049 = 3'h4 == fstate ? _GEN_4443 : _GEN_7792; // @[L1DCache.scala 582:18]
- wire _GEN_8050 = 3'h4 == fstate ? _GEN_4444 : _GEN_7793; // @[L1DCache.scala 582:18]
- wire _GEN_8051 = 3'h4 == fstate ? _GEN_4445 : _GEN_7794; // @[L1DCache.scala 582:18]
- wire _GEN_8052 = 3'h4 == fstate ? _GEN_4446 : _GEN_7795; // @[L1DCache.scala 582:18]
- wire _GEN_8053 = 3'h4 == fstate ? _GEN_4447 : _GEN_7796; // @[L1DCache.scala 582:18]
- wire _GEN_8054 = 3'h4 == fstate ? _GEN_4448 : _GEN_7797; // @[L1DCache.scala 582:18]
- wire _GEN_8055 = 3'h4 == fstate ? _GEN_4449 : _GEN_7798; // @[L1DCache.scala 582:18]
- wire _GEN_8056 = 3'h4 == fstate ? _GEN_4450 : _GEN_7799; // @[L1DCache.scala 582:18]
- wire _GEN_8057 = 3'h4 == fstate ? _GEN_4451 : _GEN_7800; // @[L1DCache.scala 582:18]
- wire _GEN_8058 = 3'h4 == fstate ? _GEN_4452 : _GEN_7801; // @[L1DCache.scala 582:18]
- wire _GEN_8059 = 3'h4 == fstate ? _GEN_4453 : _GEN_7802; // @[L1DCache.scala 582:18]
- wire _GEN_8060 = 3'h4 == fstate ? _GEN_4454 : _GEN_7803; // @[L1DCache.scala 582:18]
- wire _GEN_8061 = 3'h4 == fstate ? _GEN_4455 : _GEN_7804; // @[L1DCache.scala 582:18]
- wire _GEN_8062 = 3'h4 == fstate ? _GEN_4456 : _GEN_7805; // @[L1DCache.scala 582:18]
- wire _GEN_8063 = 3'h4 == fstate ? _GEN_4457 : _GEN_7806; // @[L1DCache.scala 582:18]
- wire _GEN_8064 = 3'h4 == fstate ? _GEN_4458 : _GEN_7807; // @[L1DCache.scala 582:18]
- wire _GEN_8065 = 3'h4 == fstate ? _GEN_4459 : _GEN_7808; // @[L1DCache.scala 582:18]
- wire _GEN_8066 = 3'h4 == fstate ? _GEN_4460 : _GEN_7809; // @[L1DCache.scala 582:18]
- wire _GEN_8067 = 3'h4 == fstate ? _GEN_4461 : _GEN_7810; // @[L1DCache.scala 582:18]
- wire _GEN_8068 = 3'h4 == fstate ? _GEN_4462 : _GEN_7811; // @[L1DCache.scala 582:18]
- wire _GEN_8069 = 3'h4 == fstate ? _GEN_4463 : _GEN_7812; // @[L1DCache.scala 582:18]
- wire _GEN_8070 = 3'h4 == fstate ? _GEN_4464 : _GEN_7813; // @[L1DCache.scala 582:18]
- wire _GEN_8071 = 3'h4 == fstate ? _GEN_4465 : _GEN_7814; // @[L1DCache.scala 582:18]
- wire _GEN_8072 = 3'h4 == fstate ? _GEN_4466 : _GEN_7815; // @[L1DCache.scala 582:18]
- wire _GEN_8073 = 3'h4 == fstate ? _GEN_4467 : _GEN_7816; // @[L1DCache.scala 582:18]
- wire _GEN_8074 = 3'h4 == fstate ? _GEN_4468 : _GEN_7817; // @[L1DCache.scala 582:18]
- wire _GEN_8075 = 3'h4 == fstate ? _GEN_4469 : _GEN_7818; // @[L1DCache.scala 582:18]
- wire _GEN_8076 = 3'h4 == fstate ? _GEN_4470 : _GEN_7819; // @[L1DCache.scala 582:18]
- wire _GEN_8077 = 3'h4 == fstate ? _GEN_4471 : _GEN_7820; // @[L1DCache.scala 582:18]
- wire _GEN_8078 = 3'h4 == fstate ? _GEN_4472 : _GEN_7821; // @[L1DCache.scala 582:18]
- wire _GEN_8079 = 3'h4 == fstate ? _GEN_4473 : _GEN_7822; // @[L1DCache.scala 582:18]
- wire _GEN_8080 = 3'h4 == fstate ? _GEN_4474 : _GEN_7823; // @[L1DCache.scala 582:18]
- wire _GEN_8081 = 3'h4 == fstate ? _GEN_4475 : _GEN_7824; // @[L1DCache.scala 582:18]
- wire _GEN_8082 = 3'h4 == fstate ? _GEN_4476 : _GEN_7825; // @[L1DCache.scala 582:18]
- wire _GEN_8083 = 3'h4 == fstate ? _GEN_4477 : _GEN_7826; // @[L1DCache.scala 582:18]
- wire _GEN_8084 = 3'h4 == fstate ? _GEN_4478 : _GEN_7827; // @[L1DCache.scala 582:18]
- wire _GEN_8085 = 3'h4 == fstate ? _GEN_4479 : _GEN_7828; // @[L1DCache.scala 582:18]
- wire _GEN_8086 = 3'h4 == fstate ? _GEN_4480 : _GEN_7829; // @[L1DCache.scala 582:18]
- wire _GEN_8087 = 3'h4 == fstate ? _GEN_4481 : _GEN_7830; // @[L1DCache.scala 582:18]
- wire _GEN_8088 = 3'h4 == fstate ? _GEN_4482 : _GEN_7831; // @[L1DCache.scala 582:18]
- wire _GEN_8089 = 3'h4 == fstate ? _GEN_4483 : _GEN_7832; // @[L1DCache.scala 582:18]
- wire _GEN_8090 = 3'h4 == fstate ? _GEN_4484 : _GEN_7833; // @[L1DCache.scala 582:18]
- wire _GEN_8091 = 3'h4 == fstate ? _GEN_4485 : _GEN_7834; // @[L1DCache.scala 582:18]
- wire _GEN_8092 = 3'h4 == fstate ? _GEN_4486 : _GEN_7835; // @[L1DCache.scala 582:18]
- wire _GEN_8093 = 3'h4 == fstate ? _GEN_4487 : _GEN_7836; // @[L1DCache.scala 582:18]
- wire _GEN_8094 = 3'h4 == fstate ? _GEN_4488 : _GEN_7837; // @[L1DCache.scala 582:18]
- wire _GEN_8095 = 3'h4 == fstate ? _GEN_4489 : _GEN_7838; // @[L1DCache.scala 582:18]
- wire _GEN_8096 = 3'h4 == fstate ? _GEN_4490 : _GEN_7839; // @[L1DCache.scala 582:18]
- wire _GEN_8097 = 3'h4 == fstate ? _GEN_4491 : _GEN_7840; // @[L1DCache.scala 582:18]
- wire _GEN_8098 = 3'h4 == fstate ? _GEN_4492 : _GEN_7841; // @[L1DCache.scala 582:18]
- wire _GEN_8099 = 3'h4 == fstate ? _GEN_4493 : _GEN_7842; // @[L1DCache.scala 582:18]
- wire _GEN_8100 = 3'h4 == fstate ? _GEN_4494 : _GEN_7843; // @[L1DCache.scala 582:18]
- wire _GEN_8101 = 3'h4 == fstate ? _GEN_4495 : _GEN_7844; // @[L1DCache.scala 582:18]
- wire _GEN_8102 = 3'h4 == fstate ? _GEN_4496 : _GEN_7845; // @[L1DCache.scala 582:18]
- wire _GEN_8103 = 3'h4 == fstate ? _GEN_4497 : _GEN_7846; // @[L1DCache.scala 582:18]
- wire _GEN_8104 = 3'h4 == fstate ? _GEN_4498 : _GEN_7847; // @[L1DCache.scala 582:18]
- wire _GEN_8105 = 3'h4 == fstate ? _GEN_4499 : _GEN_7848; // @[L1DCache.scala 582:18]
- wire _GEN_8106 = 3'h4 == fstate ? _GEN_4500 : _GEN_7849; // @[L1DCache.scala 582:18]
- wire _GEN_8107 = 3'h4 == fstate ? _GEN_4501 : _GEN_7850; // @[L1DCache.scala 582:18]
- wire _GEN_8108 = 3'h4 == fstate ? _GEN_4502 : _GEN_7851; // @[L1DCache.scala 582:18]
- wire _GEN_8109 = 3'h4 == fstate ? _GEN_4503 : _GEN_7852; // @[L1DCache.scala 582:18]
- wire _GEN_8110 = 3'h4 == fstate ? _GEN_4504 : _GEN_7853; // @[L1DCache.scala 582:18]
- wire _GEN_8111 = 3'h4 == fstate ? _GEN_4505 : _GEN_7854; // @[L1DCache.scala 582:18]
- wire _GEN_8112 = 3'h4 == fstate ? _GEN_4506 : _GEN_7855; // @[L1DCache.scala 582:18]
- wire _GEN_8113 = 3'h4 == fstate ? _GEN_4507 : _GEN_7856; // @[L1DCache.scala 582:18]
- wire _GEN_8114 = 3'h4 == fstate ? _GEN_4508 : _GEN_7857; // @[L1DCache.scala 582:18]
- wire _GEN_8115 = 3'h4 == fstate ? _GEN_4509 : _GEN_7858; // @[L1DCache.scala 582:18]
- wire _GEN_8116 = 3'h4 == fstate ? _GEN_4510 : _GEN_7859; // @[L1DCache.scala 582:18]
- wire _GEN_8117 = 3'h4 == fstate ? _GEN_4511 : _GEN_7860; // @[L1DCache.scala 582:18]
- wire _GEN_8118 = 3'h4 == fstate ? _GEN_4512 : _GEN_7861; // @[L1DCache.scala 582:18]
- wire _GEN_8119 = 3'h4 == fstate ? _GEN_4513 : _GEN_7862; // @[L1DCache.scala 582:18]
- wire _GEN_8120 = 3'h4 == fstate ? _GEN_4514 : _GEN_7863; // @[L1DCache.scala 582:18]
- wire _GEN_8121 = 3'h4 == fstate ? _GEN_4515 : _GEN_7864; // @[L1DCache.scala 582:18]
- wire _GEN_8122 = 3'h4 == fstate ? _GEN_4516 : _GEN_7865; // @[L1DCache.scala 582:18]
- wire _GEN_8123 = 3'h4 == fstate ? _GEN_4517 : _GEN_7866; // @[L1DCache.scala 582:18]
- wire _GEN_8124 = 3'h4 == fstate ? _GEN_4518 : _GEN_7867; // @[L1DCache.scala 582:18]
- wire _GEN_8125 = 3'h4 == fstate ? _GEN_4519 : _GEN_7868; // @[L1DCache.scala 582:18]
- wire _GEN_8126 = 3'h4 == fstate ? _GEN_4520 : _GEN_7869; // @[L1DCache.scala 582:18]
- wire _GEN_8127 = 3'h4 == fstate ? _GEN_4521 : _GEN_7870; // @[L1DCache.scala 582:18]
- wire _GEN_8128 = 3'h4 == fstate ? _GEN_4522 : _GEN_7871; // @[L1DCache.scala 582:18]
- wire _GEN_8129 = 3'h4 == fstate ? _GEN_4523 : _GEN_7872; // @[L1DCache.scala 582:18]
- wire _GEN_8130 = 3'h4 == fstate ? _GEN_4524 : _GEN_7873; // @[L1DCache.scala 582:18]
- wire _GEN_8131 = 3'h4 == fstate ? _GEN_4525 : _GEN_7874; // @[L1DCache.scala 582:18]
- wire _GEN_8132 = 3'h4 == fstate ? _GEN_4526 : _GEN_7875; // @[L1DCache.scala 582:18]
- wire _GEN_8133 = 3'h4 == fstate ? _GEN_4527 : _GEN_7876; // @[L1DCache.scala 582:18]
- wire _GEN_8134 = 3'h4 == fstate ? _GEN_4528 : _GEN_7877; // @[L1DCache.scala 582:18]
- wire _GEN_8135 = 3'h4 == fstate ? _GEN_4529 : _GEN_7878; // @[L1DCache.scala 582:18]
- wire _GEN_8136 = 3'h4 == fstate ? _GEN_4530 : _GEN_7879; // @[L1DCache.scala 582:18]
- wire _GEN_8137 = 3'h4 == fstate ? _GEN_4531 : _GEN_7880; // @[L1DCache.scala 582:18]
- wire _GEN_8138 = 3'h4 == fstate ? _GEN_4532 : _GEN_7881; // @[L1DCache.scala 582:18]
- wire _GEN_8139 = 3'h4 == fstate ? _GEN_4533 : _GEN_7882; // @[L1DCache.scala 582:18]
- wire _GEN_8140 = 3'h4 == fstate ? _GEN_4534 : _GEN_7883; // @[L1DCache.scala 582:18]
- wire _GEN_8141 = 3'h4 == fstate ? _GEN_4535 : _GEN_7884; // @[L1DCache.scala 582:18]
- wire _GEN_8142 = 3'h4 == fstate ? _GEN_4536 : _GEN_7885; // @[L1DCache.scala 582:18]
- wire _GEN_8143 = 3'h4 == fstate ? _GEN_4537 : _GEN_7886; // @[L1DCache.scala 582:18]
- wire _GEN_8144 = 3'h4 == fstate ? _GEN_4538 : _GEN_7887; // @[L1DCache.scala 582:18]
- wire _GEN_8145 = 3'h4 == fstate ? _GEN_4539 : _GEN_7888; // @[L1DCache.scala 582:18]
- wire _GEN_8146 = 3'h4 == fstate ? _GEN_4540 : _GEN_7889; // @[L1DCache.scala 582:18]
- wire _GEN_8147 = 3'h4 == fstate ? _GEN_4541 : _GEN_7890; // @[L1DCache.scala 582:18]
- wire _GEN_8148 = 3'h4 == fstate ? _GEN_4542 : _GEN_7891; // @[L1DCache.scala 582:18]
- wire _GEN_8149 = 3'h4 == fstate ? _GEN_4543 : _GEN_7892; // @[L1DCache.scala 582:18]
- wire _GEN_8150 = 3'h4 == fstate ? _GEN_4544 : _GEN_7893; // @[L1DCache.scala 582:18]
- wire _GEN_8151 = 3'h4 == fstate ? _GEN_4545 : _GEN_7894; // @[L1DCache.scala 582:18]
- wire _GEN_8152 = 3'h4 == fstate ? _GEN_4546 : _GEN_7895; // @[L1DCache.scala 582:18]
- wire _GEN_8153 = 3'h4 == fstate ? _GEN_4547 : _GEN_7896; // @[L1DCache.scala 582:18]
- wire _GEN_8154 = 3'h4 == fstate ? _GEN_4548 : _GEN_7897; // @[L1DCache.scala 582:18]
- wire _GEN_8155 = 3'h4 == fstate ? _GEN_4549 : _GEN_7898; // @[L1DCache.scala 582:18]
- wire _GEN_8156 = 3'h4 == fstate ? _GEN_4550 : _GEN_7899; // @[L1DCache.scala 582:18]
- wire _GEN_8157 = 3'h4 == fstate ? _GEN_4551 : _GEN_7900; // @[L1DCache.scala 582:18]
- wire _GEN_8158 = 3'h4 == fstate ? _GEN_4552 : _GEN_7901; // @[L1DCache.scala 582:18]
- wire _GEN_8159 = 3'h4 == fstate ? _GEN_4553 : _GEN_7902; // @[L1DCache.scala 582:18]
- wire _GEN_8160 = 3'h4 == fstate ? _GEN_4554 : _GEN_7903; // @[L1DCache.scala 582:18]
- wire _GEN_8161 = 3'h4 == fstate ? _GEN_4555 : _GEN_7904; // @[L1DCache.scala 582:18]
- wire _GEN_8162 = 3'h4 == fstate ? _GEN_4556 : _GEN_7905; // @[L1DCache.scala 582:18]
- wire _GEN_8163 = 3'h4 == fstate ? _GEN_4557 : _GEN_7906; // @[L1DCache.scala 582:18]
- wire _GEN_8164 = 3'h4 == fstate ? _GEN_4558 : _GEN_7907; // @[L1DCache.scala 582:18]
- wire _GEN_8165 = 3'h4 == fstate ? _GEN_4559 : _GEN_7908; // @[L1DCache.scala 582:18]
- wire _GEN_8166 = 3'h4 == fstate ? _GEN_4560 : _GEN_7909; // @[L1DCache.scala 582:18]
- wire _GEN_8167 = 3'h4 == fstate ? _GEN_4561 : _GEN_7910; // @[L1DCache.scala 582:18]
- wire _GEN_8168 = 3'h4 == fstate ? _GEN_4562 : _GEN_7911; // @[L1DCache.scala 582:18]
- wire _GEN_8169 = 3'h4 == fstate ? _GEN_4563 : _GEN_7912; // @[L1DCache.scala 582:18]
- wire _GEN_8170 = 3'h4 == fstate ? _GEN_4564 : _GEN_7913; // @[L1DCache.scala 582:18]
- wire _GEN_8171 = 3'h4 == fstate ? _GEN_4565 : _GEN_7914; // @[L1DCache.scala 582:18]
- wire _GEN_8172 = 3'h4 == fstate ? _GEN_4566 : _GEN_7915; // @[L1DCache.scala 582:18]
- wire _GEN_8173 = 3'h4 == fstate ? _GEN_4567 : _GEN_7916; // @[L1DCache.scala 582:18]
- wire _GEN_8174 = 3'h4 == fstate ? _GEN_4568 : _GEN_7917; // @[L1DCache.scala 582:18]
- wire _GEN_8175 = 3'h4 == fstate ? _GEN_4569 : _GEN_7918; // @[L1DCache.scala 582:18]
- wire _GEN_8176 = 3'h4 == fstate ? _GEN_4570 : _GEN_7919; // @[L1DCache.scala 582:18]
- wire _GEN_8177 = 3'h4 == fstate ? _GEN_4571 : _GEN_7920; // @[L1DCache.scala 582:18]
- wire _GEN_8178 = 3'h4 == fstate ? _GEN_4572 : _GEN_7921; // @[L1DCache.scala 582:18]
- wire _GEN_8179 = 3'h4 == fstate ? _GEN_4573 : _GEN_7922; // @[L1DCache.scala 582:18]
- wire _GEN_8180 = 3'h4 == fstate ? _GEN_4574 : _GEN_7923; // @[L1DCache.scala 582:18]
- wire _GEN_8181 = 3'h4 == fstate ? _GEN_4575 : _GEN_7924; // @[L1DCache.scala 582:18]
- wire _GEN_8182 = 3'h4 == fstate ? _GEN_4576 : _GEN_7925; // @[L1DCache.scala 582:18]
- wire _GEN_8183 = 3'h4 == fstate ? _GEN_4577 : _GEN_7926; // @[L1DCache.scala 582:18]
- wire _GEN_8184 = 3'h4 == fstate ? _GEN_4578 : _GEN_7927; // @[L1DCache.scala 582:18]
- wire _GEN_8185 = 3'h4 == fstate ? _GEN_4579 : _GEN_7928; // @[L1DCache.scala 582:18]
- wire _GEN_8186 = 3'h4 == fstate ? _GEN_4580 : _GEN_7929; // @[L1DCache.scala 582:18]
- wire _GEN_8187 = 3'h4 == fstate ? _GEN_4581 : _GEN_7930; // @[L1DCache.scala 582:18]
- wire _GEN_8188 = 3'h4 == fstate ? _GEN_4582 : _GEN_7931; // @[L1DCache.scala 582:18]
- wire _GEN_8189 = 3'h4 == fstate ? _GEN_4583 : _GEN_7932; // @[L1DCache.scala 582:18]
- wire _GEN_8190 = 3'h4 == fstate ? _GEN_4584 : _GEN_7933; // @[L1DCache.scala 582:18]
- wire _GEN_8191 = 3'h4 == fstate ? _GEN_4585 : _GEN_7934; // @[L1DCache.scala 582:18]
- wire _GEN_8192 = 3'h4 == fstate ? _GEN_4586 : _GEN_7935; // @[L1DCache.scala 582:18]
- wire _GEN_8193 = 3'h4 == fstate ? _GEN_4587 : _GEN_7936; // @[L1DCache.scala 582:18]
- wire _GEN_8194 = 3'h4 == fstate ? _GEN_4588 : _GEN_7937; // @[L1DCache.scala 582:18]
- wire _GEN_8195 = 3'h4 == fstate ? _GEN_4589 : _GEN_7938; // @[L1DCache.scala 582:18]
- wire _GEN_8196 = 3'h4 == fstate ? _GEN_4590 : _GEN_7939; // @[L1DCache.scala 582:18]
- wire _GEN_8197 = 3'h4 == fstate ? _GEN_4591 : _GEN_7940; // @[L1DCache.scala 582:18]
- wire _GEN_8198 = 3'h4 == fstate ? _GEN_4592 : _GEN_7941; // @[L1DCache.scala 582:18]
- wire _GEN_8199 = 3'h4 == fstate ? _GEN_4593 : _GEN_7942; // @[L1DCache.scala 582:18]
- wire _GEN_8200 = 3'h4 == fstate ? _GEN_4594 : _GEN_7943; // @[L1DCache.scala 582:18]
- wire _GEN_8201 = 3'h4 == fstate ? _GEN_4595 : _GEN_7944; // @[L1DCache.scala 582:18]
- wire _GEN_8202 = 3'h4 == fstate ? _GEN_4596 : _GEN_7945; // @[L1DCache.scala 582:18]
- wire _GEN_8203 = 3'h4 == fstate ? _GEN_4597 : _GEN_7946; // @[L1DCache.scala 582:18]
- wire _GEN_8204 = 3'h4 == fstate ? _GEN_4598 : _GEN_7947; // @[L1DCache.scala 582:18]
- wire _GEN_8205 = 3'h4 == fstate ? _GEN_4599 : _GEN_7948; // @[L1DCache.scala 582:18]
- wire _GEN_8206 = 3'h4 == fstate ? _GEN_4600 : _GEN_7949; // @[L1DCache.scala 582:18]
- wire _GEN_8207 = 3'h4 == fstate ? _GEN_4601 : _GEN_7950; // @[L1DCache.scala 582:18]
- wire _GEN_8208 = 3'h4 == fstate ? _GEN_4602 : _GEN_7951; // @[L1DCache.scala 582:18]
- wire _GEN_8209 = 3'h4 == fstate ? _GEN_4603 : _GEN_7952; // @[L1DCache.scala 582:18]
- wire _GEN_8210 = 3'h4 == fstate ? _GEN_4604 : _GEN_7953; // @[L1DCache.scala 582:18]
- wire _GEN_8211 = 3'h4 == fstate ? _GEN_4605 : _GEN_7954; // @[L1DCache.scala 582:18]
- wire _GEN_8212 = 3'h4 == fstate ? _GEN_4606 : _GEN_7955; // @[L1DCache.scala 582:18]
- wire _GEN_8213 = 3'h4 == fstate ? _GEN_4607 : _GEN_7956; // @[L1DCache.scala 582:18]
- wire _GEN_8214 = 3'h4 == fstate ? _GEN_4608 : _GEN_7957; // @[L1DCache.scala 582:18]
- wire _GEN_8215 = 3'h4 == fstate ? _GEN_4609 : _GEN_7958; // @[L1DCache.scala 582:18]
- wire _GEN_8216 = 3'h4 == fstate ? _GEN_4610 : _GEN_7959; // @[L1DCache.scala 582:18]
- wire _GEN_8217 = 3'h4 == fstate ? _GEN_4611 : _GEN_7960; // @[L1DCache.scala 582:18]
- wire _GEN_8218 = 3'h4 == fstate ? _GEN_4612 : _GEN_7961; // @[L1DCache.scala 582:18]
- wire _GEN_8219 = 3'h4 == fstate ? _GEN_4613 : _GEN_7962; // @[L1DCache.scala 582:18]
- wire _GEN_8220 = 3'h4 == fstate ? _GEN_4614 : _GEN_7963; // @[L1DCache.scala 582:18]
- wire _GEN_8221 = 3'h4 == fstate ? _GEN_4615 : _GEN_7964; // @[L1DCache.scala 582:18]
- wire busread = io_dbus_valid & ~io_dbus_write & _T_4267; // @[L1DCache.scala 671:50]
- wire [35:0] mem_io_wdata_lo_lo_lo = {1'h0,io_axi_read_data_bits_data[31:24],1'h0,io_axi_read_data_bits_data[23:16],1'h0
- ,io_axi_read_data_bits_data[15:8],1'h0,io_axi_read_data_bits_data[7:0]}; // @[L1DCache.scala 289:10]
- wire [71:0] mem_io_wdata_lo_lo = {1'h0,io_axi_read_data_bits_data[63:56],1'h0,io_axi_read_data_bits_data[55:48],1'h0,
- io_axi_read_data_bits_data[47:40],1'h0,io_axi_read_data_bits_data[39:32],mem_io_wdata_lo_lo_lo}; // @[L1DCache.scala 289:10]
- wire [35:0] mem_io_wdata_lo_hi_lo = {1'h0,io_axi_read_data_bits_data[95:88],1'h0,io_axi_read_data_bits_data[87:80],1'h0
- ,io_axi_read_data_bits_data[79:72],1'h0,io_axi_read_data_bits_data[71:64]}; // @[L1DCache.scala 289:10]
- wire [143:0] mem_io_wdata_lo = {1'h0,io_axi_read_data_bits_data[127:120],1'h0,io_axi_read_data_bits_data[119:112],1'h0
- ,io_axi_read_data_bits_data[111:104],1'h0,io_axi_read_data_bits_data[103:96],mem_io_wdata_lo_hi_lo,
- mem_io_wdata_lo_lo}; // @[L1DCache.scala 289:10]
- wire [35:0] mem_io_wdata_hi_lo_lo = {1'h0,io_axi_read_data_bits_data[159:152],1'h0,io_axi_read_data_bits_data[151:144]
- ,1'h0,io_axi_read_data_bits_data[143:136],1'h0,io_axi_read_data_bits_data[135:128]}; // @[L1DCache.scala 289:10]
- wire [71:0] mem_io_wdata_hi_lo = {1'h0,io_axi_read_data_bits_data[191:184],1'h0,io_axi_read_data_bits_data[183:176],1'h0
- ,io_axi_read_data_bits_data[175:168],1'h0,io_axi_read_data_bits_data[167:160],mem_io_wdata_hi_lo_lo}; // @[L1DCache.scala 289:10]
- wire [35:0] mem_io_wdata_hi_hi_lo = {1'h0,io_axi_read_data_bits_data[223:216],1'h0,io_axi_read_data_bits_data[215:208]
- ,1'h0,io_axi_read_data_bits_data[207:200],1'h0,io_axi_read_data_bits_data[199:192]}; // @[L1DCache.scala 289:10]
- wire [143:0] mem_io_wdata_hi = {1'h0,io_axi_read_data_bits_data[255:248],1'h0,io_axi_read_data_bits_data[247:240],1'h0
- ,io_axi_read_data_bits_data[239:232],1'h0,io_axi_read_data_bits_data[231:224],mem_io_wdata_hi_hi_lo,
- mem_io_wdata_hi_lo}; // @[L1DCache.scala 289:10]
- wire [287:0] _mem_io_wdata_T = {mem_io_wdata_hi,mem_io_wdata_lo}; // @[L1DCache.scala 289:10]
- wire [35:0] mem_io_wdata_lo_lo_lo_1 = {1'h1,io_dbus_wdata[31:24],1'h1,io_dbus_wdata[23:16],1'h1,io_dbus_wdata[15:8],1'h1
- ,io_dbus_wdata[7:0]}; // @[L1DCache.scala 289:10]
- wire [71:0] mem_io_wdata_lo_lo_1 = {1'h1,io_dbus_wdata[63:56],1'h1,io_dbus_wdata[55:48],1'h1,io_dbus_wdata[47:40],1'h1
- ,io_dbus_wdata[39:32],mem_io_wdata_lo_lo_lo_1}; // @[L1DCache.scala 289:10]
- wire [35:0] mem_io_wdata_lo_hi_lo_1 = {1'h1,io_dbus_wdata[95:88],1'h1,io_dbus_wdata[87:80],1'h1,io_dbus_wdata[79:72],1'h1
- ,io_dbus_wdata[71:64]}; // @[L1DCache.scala 289:10]
- wire [143:0] mem_io_wdata_lo_1 = {1'h1,io_dbus_wdata[127:120],1'h1,io_dbus_wdata[119:112],1'h1,io_dbus_wdata[111:104],1'h1
- ,io_dbus_wdata[103:96],mem_io_wdata_lo_hi_lo_1,mem_io_wdata_lo_lo_1}; // @[L1DCache.scala 289:10]
- wire [35:0] mem_io_wdata_hi_lo_lo_1 = {1'h1,io_dbus_wdata[159:152],1'h1,io_dbus_wdata[151:144],1'h1,io_dbus_wdata[143:
- 136],1'h1,io_dbus_wdata[135:128]}; // @[L1DCache.scala 289:10]
- wire [71:0] mem_io_wdata_hi_lo_1 = {1'h1,io_dbus_wdata[191:184],1'h1,io_dbus_wdata[183:176],1'h1,io_dbus_wdata[175:168
- ],1'h1,io_dbus_wdata[167:160],mem_io_wdata_hi_lo_lo_1}; // @[L1DCache.scala 289:10]
- wire [35:0] mem_io_wdata_hi_hi_lo_1 = {1'h1,io_dbus_wdata[223:216],1'h1,io_dbus_wdata[215:208],1'h1,io_dbus_wdata[207:
- 200],1'h1,io_dbus_wdata[199:192]}; // @[L1DCache.scala 289:10]
- wire [143:0] mem_io_wdata_hi_1 = {1'h1,io_dbus_wdata[255:248],1'h1,io_dbus_wdata[247:240],1'h1,io_dbus_wdata[239:232],1'h1
- ,io_dbus_wdata[231:224],mem_io_wdata_hi_hi_lo_1,mem_io_wdata_hi_lo_1}; // @[L1DCache.scala 289:10]
- wire [287:0] _mem_io_wdata_T_2 = {mem_io_wdata_hi_1,mem_io_wdata_lo_1}; // @[L1DCache.scala 289:10]
- wire [1:0] _T_7936 = busread + _T_4255; // @[L1DCache.scala 688:27]
- wire [1:0] _GEN_11820 = {{1'd0}, _T_4257}; // @[L1DCache.scala 688:39]
- wire [2:0] _T_7937 = _T_7936 + _GEN_11820; // @[L1DCache.scala 688:39]
- wire [1:0] _T_7941 = _T_7937[1] + _T_7937[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_11821 = {{1'd0}, _T_7937[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_7943 = _GEN_11821 + _T_7941; // @[Bitwise.scala 48:55]
- wire _GEN_14461 = ~_T_5829 & ~_T_5840 & ~_T_5843; // @[L1DCache.scala 611:13]
- wire _GEN_14478 = _GEN_14461 & ~_T_5848; // @[L1DCache.scala 622:13]
- wire _GEN_14506 = _GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7; // @[L1DCache.scala 648:19]
- Sram_1rwm_256x288 mem ( // @[L1DCache.scala 345:19]
- .clock(mem_clock),
- .valid(mem_valid),
- .write(mem_write),
- .addr(mem_addr),
- .wdata(mem_wdata),
- .wmask(mem_wmask),
- .rdata(mem_rdata),
- .volt_sel(mem_volt_sel)
- );
- assign io_dbus_ready = found & _T_4267; // @[L1DCache.scala 662:26]
- assign io_dbus_rdata = {axiwdatabuf_hi,axiwdatabuf_lo}; // @[L1DCache.scala 298:10]
- assign io_axi_write_addr_valid = axiwaddrvalid; // @[L1DCache.scala 548:31]
- assign io_axi_write_addr_bits_addr = axiwaddr[30:0]; // @[L1DCache.scala 550:31]
- assign io_axi_write_data_valid = axiwdatavalid; // @[L1DCache.scala 554:31]
- assign io_axi_write_data_bits_data = axiwdatabuf; // @[L1DCache.scala 555:31]
- assign io_axi_write_data_bits_strb = axiwstrbbuf; // @[L1DCache.scala 556:31]
- assign io_axi_write_resp_ready = 1'h1; // @[L1DCache.scala 552:31]
- assign io_axi_read_addr_valid = axiraddrvalid; // @[L1DCache.scala 542:26]
- assign io_axi_read_addr_bits_addr = axiraddr[30:0]; // @[L1DCache.scala 543:30]
- assign io_axi_read_data_ready = axirdataready; // @[L1DCache.scala 545:26]
- assign io_flush_ready = fstate == 3'h7; // @[L1DCache.scala 656:28]
- assign mem_clock = clock; // @[L1DCache.scala 678:19]
- assign mem_valid = busread | _T_4255 | _T_4257 | axiwrite; // @[L1DCache.scala 679:53]
- assign mem_write = axirdataready & _T_5851 | _T & _T_4267; // @[L1DCache.scala 680:40]
- assign mem_addr = axirdataready | axiwrite ? replaceIdReg : foundId; // @[L1DCache.scala 681:25]
- assign mem_wdata = axirdataready ? _mem_io_wdata_T : _mem_io_wdata_T_2; // @[L1DCache.scala 683:25]
- assign mem_wmask = axirdataready ? 32'hffffffff : io_dbus_wmask; // @[L1DCache.scala 682:25]
- assign mem_volt_sel = io_volt_sel; // @[L1DCache.scala 685:19]
- always @(posedge clock) begin
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h0 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_0 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h1 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_1 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h2 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_2 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h3 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_3 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h4 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_4 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h5 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_5 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h6 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_6 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h7 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_7 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h8 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_8 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h9 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_9 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'ha == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_10 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hb == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_11 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hc == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_12 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hd == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_13 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'he == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_14 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hf == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_15 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h10 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_16 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h11 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_17 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h12 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_18 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h13 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_19 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h14 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_20 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h15 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_21 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h16 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_22 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h17 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_23 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h18 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_24 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h19 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_25 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h1a == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_26 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h1b == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_27 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h1c == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_28 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h1d == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_29 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h1e == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_30 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h1f == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_31 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h20 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_32 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h21 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_33 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h22 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_34 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h23 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_35 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h24 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_36 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h25 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_37 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h26 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_38 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h27 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_39 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h28 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_40 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h29 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_41 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h2a == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_42 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h2b == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_43 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h2c == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_44 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h2d == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_45 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h2e == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_46 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h2f == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_47 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h30 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_48 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h31 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_49 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h32 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_50 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h33 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_51 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h34 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_52 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h35 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_53 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h36 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_54 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h37 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_55 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h38 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_56 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h39 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_57 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h3a == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_58 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h3b == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_59 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h3c == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_60 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h3d == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_61 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h3e == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_62 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h3f == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_63 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h40 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_64 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h41 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_65 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h42 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_66 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h43 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_67 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h44 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_68 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h45 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_69 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h46 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_70 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h47 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_71 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h48 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_72 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h49 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_73 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h4a == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_74 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h4b == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_75 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h4c == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_76 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h4d == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_77 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h4e == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_78 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h4f == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_79 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h50 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_80 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h51 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_81 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h52 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_82 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h53 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_83 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h54 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_84 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h55 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_85 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h56 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_86 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h57 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_87 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h58 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_88 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h59 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_89 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h5a == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_90 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h5b == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_91 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h5c == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_92 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h5d == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_93 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h5e == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_94 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h5f == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_95 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h60 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_96 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h61 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_97 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h62 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_98 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h63 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_99 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h64 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_100 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h65 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_101 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h66 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_102 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h67 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_103 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h68 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_104 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h69 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_105 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h6a == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_106 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h6b == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_107 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h6c == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_108 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h6d == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_109 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h6e == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_110 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h6f == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_111 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h70 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_112 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h71 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_113 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h72 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_114 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h73 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_115 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h74 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_116 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h75 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_117 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h76 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_118 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h77 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_119 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h78 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_120 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h79 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_121 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h7a == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_122 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h7b == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_123 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h7c == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_124 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h7d == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_125 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h7e == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_126 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h7f == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_127 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h80 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_128 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h81 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_129 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h82 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_130 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h83 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_131 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h84 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_132 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h85 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_133 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h86 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_134 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h87 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_135 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h88 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_136 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h89 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_137 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h8a == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_138 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h8b == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_139 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h8c == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_140 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h8d == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_141 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h8e == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_142 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h8f == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_143 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h90 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_144 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h91 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_145 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h92 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_146 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h93 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_147 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h94 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_148 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h95 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_149 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h96 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_150 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h97 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_151 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h98 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_152 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h99 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_153 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h9a == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_154 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h9b == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_155 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h9c == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_156 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h9d == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_157 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h9e == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_158 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'h9f == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_159 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'ha0 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_160 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'ha1 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_161 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'ha2 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_162 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'ha3 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_163 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'ha4 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_164 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'ha5 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_165 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'ha6 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_166 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'ha7 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_167 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'ha8 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_168 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'ha9 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_169 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'haa == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_170 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hab == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_171 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hac == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_172 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'had == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_173 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hae == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_174 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'haf == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_175 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hb0 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_176 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hb1 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_177 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hb2 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_178 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hb3 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_179 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hb4 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_180 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hb5 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_181 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hb6 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_182 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hb7 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_183 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hb8 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_184 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hb9 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_185 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hba == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_186 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hbb == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_187 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hbc == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_188 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hbd == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_189 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hbe == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_190 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hbf == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_191 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hc0 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_192 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hc1 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_193 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hc2 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_194 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hc3 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_195 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hc4 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_196 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hc5 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_197 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hc6 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_198 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hc7 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_199 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hc8 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_200 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hc9 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_201 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hca == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_202 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hcb == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_203 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hcc == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_204 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hcd == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_205 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hce == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_206 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hcf == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_207 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hd0 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_208 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hd1 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_209 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hd2 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_210 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hd3 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_211 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hd4 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_212 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hd5 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_213 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hd6 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_214 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hd7 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_215 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hd8 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_216 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hd9 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_217 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hda == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_218 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hdb == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_219 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hdc == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_220 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hdd == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_221 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hde == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_222 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hdf == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_223 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'he0 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_224 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'he1 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_225 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'he2 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_226 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'he3 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_227 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'he4 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_228 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'he5 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_229 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'he6 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_230 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'he7 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_231 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'he8 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_232 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'he9 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_233 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hea == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_234 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'heb == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_235 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hec == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_236 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hed == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_237 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hee == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_238 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hef == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_239 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hf0 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_240 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hf1 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_241 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hf2 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_242 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hf3 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_243 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hf4 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_244 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hf5 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_245 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hf6 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_246 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hf7 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_247 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hf8 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_248 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hf9 == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_249 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hfa == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_250 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hfb == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_251 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hfc == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_252 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hfd == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_253 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hfe == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_254 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- if (8'hff == replaceId) begin // @[L1DCache.scala 499:24]
- camaddr_255 <= _camaddr_replaceId; // @[L1DCache.scala 499:24]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_0_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_1) begin // @[L1DCache.scala 420:117]
- if (matchSet_1[0]) begin // @[L1DCache.scala 422:28]
- history_0_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_0_0 > _GEN_3) begin // @[L1DCache.scala 424:50]
- history_0_0 <= _history_0_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_0_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_1) begin // @[L1DCache.scala 420:117]
- if (matchSet_1[1]) begin // @[L1DCache.scala 422:28]
- history_0_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_0_1 > _GEN_3) begin // @[L1DCache.scala 424:50]
- history_0_1 <= _history_0_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_0_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_1) begin // @[L1DCache.scala 420:117]
- if (matchSet_1[2]) begin // @[L1DCache.scala 422:28]
- history_0_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_0_2 > _GEN_3) begin // @[L1DCache.scala 424:50]
- history_0_2 <= _history_0_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_0_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_1) begin // @[L1DCache.scala 420:117]
- if (matchSet_1[3]) begin // @[L1DCache.scala 422:28]
- history_0_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_0_3 > _GEN_3) begin // @[L1DCache.scala 424:50]
- history_0_3 <= _history_0_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_1_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_5) begin // @[L1DCache.scala 420:117]
- if (matchSet_2[0]) begin // @[L1DCache.scala 422:28]
- history_1_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_1_0 > _GEN_19) begin // @[L1DCache.scala 424:50]
- history_1_0 <= _history_1_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_1_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_5) begin // @[L1DCache.scala 420:117]
- if (matchSet_2[1]) begin // @[L1DCache.scala 422:28]
- history_1_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_1_1 > _GEN_19) begin // @[L1DCache.scala 424:50]
- history_1_1 <= _history_1_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_1_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_5) begin // @[L1DCache.scala 420:117]
- if (matchSet_2[2]) begin // @[L1DCache.scala 422:28]
- history_1_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_1_2 > _GEN_19) begin // @[L1DCache.scala 424:50]
- history_1_2 <= _history_1_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_1_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_5) begin // @[L1DCache.scala 420:117]
- if (matchSet_2[3]) begin // @[L1DCache.scala 422:28]
- history_1_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_1_3 > _GEN_19) begin // @[L1DCache.scala 424:50]
- history_1_3 <= _history_1_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_2_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_9) begin // @[L1DCache.scala 420:117]
- if (matchSet_3[0]) begin // @[L1DCache.scala 422:28]
- history_2_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_2_0 > _GEN_35) begin // @[L1DCache.scala 424:50]
- history_2_0 <= _history_2_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_2_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_9) begin // @[L1DCache.scala 420:117]
- if (matchSet_3[1]) begin // @[L1DCache.scala 422:28]
- history_2_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_2_1 > _GEN_35) begin // @[L1DCache.scala 424:50]
- history_2_1 <= _history_2_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_2_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_9) begin // @[L1DCache.scala 420:117]
- if (matchSet_3[2]) begin // @[L1DCache.scala 422:28]
- history_2_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_2_2 > _GEN_35) begin // @[L1DCache.scala 424:50]
- history_2_2 <= _history_2_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_2_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_9) begin // @[L1DCache.scala 420:117]
- if (matchSet_3[3]) begin // @[L1DCache.scala 422:28]
- history_2_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_2_3 > _GEN_35) begin // @[L1DCache.scala 424:50]
- history_2_3 <= _history_2_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_3_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_13) begin // @[L1DCache.scala 420:117]
- if (matchSet_4[0]) begin // @[L1DCache.scala 422:28]
- history_3_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_3_0 > _GEN_51) begin // @[L1DCache.scala 424:50]
- history_3_0 <= _history_3_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_3_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_13) begin // @[L1DCache.scala 420:117]
- if (matchSet_4[1]) begin // @[L1DCache.scala 422:28]
- history_3_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_3_1 > _GEN_51) begin // @[L1DCache.scala 424:50]
- history_3_1 <= _history_3_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_3_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_13) begin // @[L1DCache.scala 420:117]
- if (matchSet_4[2]) begin // @[L1DCache.scala 422:28]
- history_3_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_3_2 > _GEN_51) begin // @[L1DCache.scala 424:50]
- history_3_2 <= _history_3_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_3_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_13) begin // @[L1DCache.scala 420:117]
- if (matchSet_4[3]) begin // @[L1DCache.scala 422:28]
- history_3_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_3_3 > _GEN_51) begin // @[L1DCache.scala 424:50]
- history_3_3 <= _history_3_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_4_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_17) begin // @[L1DCache.scala 420:117]
- if (matchSet_5[0]) begin // @[L1DCache.scala 422:28]
- history_4_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_4_0 > _GEN_67) begin // @[L1DCache.scala 424:50]
- history_4_0 <= _history_4_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_4_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_17) begin // @[L1DCache.scala 420:117]
- if (matchSet_5[1]) begin // @[L1DCache.scala 422:28]
- history_4_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_4_1 > _GEN_67) begin // @[L1DCache.scala 424:50]
- history_4_1 <= _history_4_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_4_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_17) begin // @[L1DCache.scala 420:117]
- if (matchSet_5[2]) begin // @[L1DCache.scala 422:28]
- history_4_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_4_2 > _GEN_67) begin // @[L1DCache.scala 424:50]
- history_4_2 <= _history_4_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_4_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_17) begin // @[L1DCache.scala 420:117]
- if (matchSet_5[3]) begin // @[L1DCache.scala 422:28]
- history_4_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_4_3 > _GEN_67) begin // @[L1DCache.scala 424:50]
- history_4_3 <= _history_4_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_5_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_21) begin // @[L1DCache.scala 420:117]
- if (matchSet_6[0]) begin // @[L1DCache.scala 422:28]
- history_5_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_5_0 > _GEN_83) begin // @[L1DCache.scala 424:50]
- history_5_0 <= _history_5_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_5_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_21) begin // @[L1DCache.scala 420:117]
- if (matchSet_6[1]) begin // @[L1DCache.scala 422:28]
- history_5_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_5_1 > _GEN_83) begin // @[L1DCache.scala 424:50]
- history_5_1 <= _history_5_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_5_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_21) begin // @[L1DCache.scala 420:117]
- if (matchSet_6[2]) begin // @[L1DCache.scala 422:28]
- history_5_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_5_2 > _GEN_83) begin // @[L1DCache.scala 424:50]
- history_5_2 <= _history_5_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_5_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_21) begin // @[L1DCache.scala 420:117]
- if (matchSet_6[3]) begin // @[L1DCache.scala 422:28]
- history_5_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_5_3 > _GEN_83) begin // @[L1DCache.scala 424:50]
- history_5_3 <= _history_5_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_6_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_25) begin // @[L1DCache.scala 420:117]
- if (matchSet_7[0]) begin // @[L1DCache.scala 422:28]
- history_6_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_6_0 > _GEN_99) begin // @[L1DCache.scala 424:50]
- history_6_0 <= _history_6_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_6_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_25) begin // @[L1DCache.scala 420:117]
- if (matchSet_7[1]) begin // @[L1DCache.scala 422:28]
- history_6_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_6_1 > _GEN_99) begin // @[L1DCache.scala 424:50]
- history_6_1 <= _history_6_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_6_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_25) begin // @[L1DCache.scala 420:117]
- if (matchSet_7[2]) begin // @[L1DCache.scala 422:28]
- history_6_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_6_2 > _GEN_99) begin // @[L1DCache.scala 424:50]
- history_6_2 <= _history_6_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_6_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_25) begin // @[L1DCache.scala 420:117]
- if (matchSet_7[3]) begin // @[L1DCache.scala 422:28]
- history_6_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_6_3 > _GEN_99) begin // @[L1DCache.scala 424:50]
- history_6_3 <= _history_6_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_7_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_29) begin // @[L1DCache.scala 420:117]
- if (matchSet_8[0]) begin // @[L1DCache.scala 422:28]
- history_7_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_7_0 > _GEN_115) begin // @[L1DCache.scala 424:50]
- history_7_0 <= _history_7_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_7_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_29) begin // @[L1DCache.scala 420:117]
- if (matchSet_8[1]) begin // @[L1DCache.scala 422:28]
- history_7_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_7_1 > _GEN_115) begin // @[L1DCache.scala 424:50]
- history_7_1 <= _history_7_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_7_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_29) begin // @[L1DCache.scala 420:117]
- if (matchSet_8[2]) begin // @[L1DCache.scala 422:28]
- history_7_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_7_2 > _GEN_115) begin // @[L1DCache.scala 424:50]
- history_7_2 <= _history_7_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_7_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_29) begin // @[L1DCache.scala 420:117]
- if (matchSet_8[3]) begin // @[L1DCache.scala 422:28]
- history_7_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_7_3 > _GEN_115) begin // @[L1DCache.scala 424:50]
- history_7_3 <= _history_7_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_8_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_33) begin // @[L1DCache.scala 420:117]
- if (matchSet_9[0]) begin // @[L1DCache.scala 422:28]
- history_8_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_8_0 > _GEN_131) begin // @[L1DCache.scala 424:50]
- history_8_0 <= _history_8_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_8_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_33) begin // @[L1DCache.scala 420:117]
- if (matchSet_9[1]) begin // @[L1DCache.scala 422:28]
- history_8_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_8_1 > _GEN_131) begin // @[L1DCache.scala 424:50]
- history_8_1 <= _history_8_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_8_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_33) begin // @[L1DCache.scala 420:117]
- if (matchSet_9[2]) begin // @[L1DCache.scala 422:28]
- history_8_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_8_2 > _GEN_131) begin // @[L1DCache.scala 424:50]
- history_8_2 <= _history_8_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_8_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_33) begin // @[L1DCache.scala 420:117]
- if (matchSet_9[3]) begin // @[L1DCache.scala 422:28]
- history_8_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_8_3 > _GEN_131) begin // @[L1DCache.scala 424:50]
- history_8_3 <= _history_8_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_9_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_37) begin // @[L1DCache.scala 420:117]
- if (matchSet_10[0]) begin // @[L1DCache.scala 422:28]
- history_9_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_9_0 > _GEN_147) begin // @[L1DCache.scala 424:50]
- history_9_0 <= _history_9_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_9_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_37) begin // @[L1DCache.scala 420:117]
- if (matchSet_10[1]) begin // @[L1DCache.scala 422:28]
- history_9_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_9_1 > _GEN_147) begin // @[L1DCache.scala 424:50]
- history_9_1 <= _history_9_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_9_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_37) begin // @[L1DCache.scala 420:117]
- if (matchSet_10[2]) begin // @[L1DCache.scala 422:28]
- history_9_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_9_2 > _GEN_147) begin // @[L1DCache.scala 424:50]
- history_9_2 <= _history_9_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_9_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_37) begin // @[L1DCache.scala 420:117]
- if (matchSet_10[3]) begin // @[L1DCache.scala 422:28]
- history_9_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_9_3 > _GEN_147) begin // @[L1DCache.scala 424:50]
- history_9_3 <= _history_9_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_10_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_41) begin // @[L1DCache.scala 420:117]
- if (matchSet_11[0]) begin // @[L1DCache.scala 422:28]
- history_10_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_10_0 > _GEN_163) begin // @[L1DCache.scala 424:50]
- history_10_0 <= _history_10_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_10_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_41) begin // @[L1DCache.scala 420:117]
- if (matchSet_11[1]) begin // @[L1DCache.scala 422:28]
- history_10_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_10_1 > _GEN_163) begin // @[L1DCache.scala 424:50]
- history_10_1 <= _history_10_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_10_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_41) begin // @[L1DCache.scala 420:117]
- if (matchSet_11[2]) begin // @[L1DCache.scala 422:28]
- history_10_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_10_2 > _GEN_163) begin // @[L1DCache.scala 424:50]
- history_10_2 <= _history_10_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_10_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_41) begin // @[L1DCache.scala 420:117]
- if (matchSet_11[3]) begin // @[L1DCache.scala 422:28]
- history_10_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_10_3 > _GEN_163) begin // @[L1DCache.scala 424:50]
- history_10_3 <= _history_10_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_11_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_45) begin // @[L1DCache.scala 420:117]
- if (matchSet_12[0]) begin // @[L1DCache.scala 422:28]
- history_11_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_11_0 > _GEN_179) begin // @[L1DCache.scala 424:50]
- history_11_0 <= _history_11_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_11_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_45) begin // @[L1DCache.scala 420:117]
- if (matchSet_12[1]) begin // @[L1DCache.scala 422:28]
- history_11_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_11_1 > _GEN_179) begin // @[L1DCache.scala 424:50]
- history_11_1 <= _history_11_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_11_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_45) begin // @[L1DCache.scala 420:117]
- if (matchSet_12[2]) begin // @[L1DCache.scala 422:28]
- history_11_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_11_2 > _GEN_179) begin // @[L1DCache.scala 424:50]
- history_11_2 <= _history_11_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_11_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_45) begin // @[L1DCache.scala 420:117]
- if (matchSet_12[3]) begin // @[L1DCache.scala 422:28]
- history_11_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_11_3 > _GEN_179) begin // @[L1DCache.scala 424:50]
- history_11_3 <= _history_11_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_12_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_49) begin // @[L1DCache.scala 420:117]
- if (matchSet_13[0]) begin // @[L1DCache.scala 422:28]
- history_12_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_12_0 > _GEN_195) begin // @[L1DCache.scala 424:50]
- history_12_0 <= _history_12_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_12_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_49) begin // @[L1DCache.scala 420:117]
- if (matchSet_13[1]) begin // @[L1DCache.scala 422:28]
- history_12_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_12_1 > _GEN_195) begin // @[L1DCache.scala 424:50]
- history_12_1 <= _history_12_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_12_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_49) begin // @[L1DCache.scala 420:117]
- if (matchSet_13[2]) begin // @[L1DCache.scala 422:28]
- history_12_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_12_2 > _GEN_195) begin // @[L1DCache.scala 424:50]
- history_12_2 <= _history_12_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_12_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_49) begin // @[L1DCache.scala 420:117]
- if (matchSet_13[3]) begin // @[L1DCache.scala 422:28]
- history_12_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_12_3 > _GEN_195) begin // @[L1DCache.scala 424:50]
- history_12_3 <= _history_12_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_13_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_53) begin // @[L1DCache.scala 420:117]
- if (matchSet_14[0]) begin // @[L1DCache.scala 422:28]
- history_13_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_13_0 > _GEN_211) begin // @[L1DCache.scala 424:50]
- history_13_0 <= _history_13_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_13_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_53) begin // @[L1DCache.scala 420:117]
- if (matchSet_14[1]) begin // @[L1DCache.scala 422:28]
- history_13_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_13_1 > _GEN_211) begin // @[L1DCache.scala 424:50]
- history_13_1 <= _history_13_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_13_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_53) begin // @[L1DCache.scala 420:117]
- if (matchSet_14[2]) begin // @[L1DCache.scala 422:28]
- history_13_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_13_2 > _GEN_211) begin // @[L1DCache.scala 424:50]
- history_13_2 <= _history_13_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_13_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_53) begin // @[L1DCache.scala 420:117]
- if (matchSet_14[3]) begin // @[L1DCache.scala 422:28]
- history_13_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_13_3 > _GEN_211) begin // @[L1DCache.scala 424:50]
- history_13_3 <= _history_13_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_14_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_57) begin // @[L1DCache.scala 420:117]
- if (matchSet_15[0]) begin // @[L1DCache.scala 422:28]
- history_14_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_14_0 > _GEN_227) begin // @[L1DCache.scala 424:50]
- history_14_0 <= _history_14_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_14_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_57) begin // @[L1DCache.scala 420:117]
- if (matchSet_15[1]) begin // @[L1DCache.scala 422:28]
- history_14_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_14_1 > _GEN_227) begin // @[L1DCache.scala 424:50]
- history_14_1 <= _history_14_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_14_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_57) begin // @[L1DCache.scala 420:117]
- if (matchSet_15[2]) begin // @[L1DCache.scala 422:28]
- history_14_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_14_2 > _GEN_227) begin // @[L1DCache.scala 424:50]
- history_14_2 <= _history_14_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_14_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_57) begin // @[L1DCache.scala 420:117]
- if (matchSet_15[3]) begin // @[L1DCache.scala 422:28]
- history_14_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_14_3 > _GEN_227) begin // @[L1DCache.scala 424:50]
- history_14_3 <= _history_14_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_15_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_61) begin // @[L1DCache.scala 420:117]
- if (matchSet_16[0]) begin // @[L1DCache.scala 422:28]
- history_15_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_15_0 > _GEN_243) begin // @[L1DCache.scala 424:50]
- history_15_0 <= _history_15_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_15_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_61) begin // @[L1DCache.scala 420:117]
- if (matchSet_16[1]) begin // @[L1DCache.scala 422:28]
- history_15_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_15_1 > _GEN_243) begin // @[L1DCache.scala 424:50]
- history_15_1 <= _history_15_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_15_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_61) begin // @[L1DCache.scala 420:117]
- if (matchSet_16[2]) begin // @[L1DCache.scala 422:28]
- history_15_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_15_2 > _GEN_243) begin // @[L1DCache.scala 424:50]
- history_15_2 <= _history_15_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_15_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_61) begin // @[L1DCache.scala 420:117]
- if (matchSet_16[3]) begin // @[L1DCache.scala 422:28]
- history_15_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_15_3 > _GEN_243) begin // @[L1DCache.scala 424:50]
- history_15_3 <= _history_15_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_16_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_65) begin // @[L1DCache.scala 420:117]
- if (matchSet_17[0]) begin // @[L1DCache.scala 422:28]
- history_16_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_16_0 > _GEN_259) begin // @[L1DCache.scala 424:50]
- history_16_0 <= _history_16_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_16_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_65) begin // @[L1DCache.scala 420:117]
- if (matchSet_17[1]) begin // @[L1DCache.scala 422:28]
- history_16_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_16_1 > _GEN_259) begin // @[L1DCache.scala 424:50]
- history_16_1 <= _history_16_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_16_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_65) begin // @[L1DCache.scala 420:117]
- if (matchSet_17[2]) begin // @[L1DCache.scala 422:28]
- history_16_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_16_2 > _GEN_259) begin // @[L1DCache.scala 424:50]
- history_16_2 <= _history_16_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_16_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_65) begin // @[L1DCache.scala 420:117]
- if (matchSet_17[3]) begin // @[L1DCache.scala 422:28]
- history_16_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_16_3 > _GEN_259) begin // @[L1DCache.scala 424:50]
- history_16_3 <= _history_16_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_17_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_69) begin // @[L1DCache.scala 420:117]
- if (matchSet_18[0]) begin // @[L1DCache.scala 422:28]
- history_17_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_17_0 > _GEN_275) begin // @[L1DCache.scala 424:50]
- history_17_0 <= _history_17_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_17_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_69) begin // @[L1DCache.scala 420:117]
- if (matchSet_18[1]) begin // @[L1DCache.scala 422:28]
- history_17_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_17_1 > _GEN_275) begin // @[L1DCache.scala 424:50]
- history_17_1 <= _history_17_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_17_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_69) begin // @[L1DCache.scala 420:117]
- if (matchSet_18[2]) begin // @[L1DCache.scala 422:28]
- history_17_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_17_2 > _GEN_275) begin // @[L1DCache.scala 424:50]
- history_17_2 <= _history_17_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_17_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_69) begin // @[L1DCache.scala 420:117]
- if (matchSet_18[3]) begin // @[L1DCache.scala 422:28]
- history_17_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_17_3 > _GEN_275) begin // @[L1DCache.scala 424:50]
- history_17_3 <= _history_17_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_18_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_73) begin // @[L1DCache.scala 420:117]
- if (matchSet_19[0]) begin // @[L1DCache.scala 422:28]
- history_18_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_18_0 > _GEN_291) begin // @[L1DCache.scala 424:50]
- history_18_0 <= _history_18_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_18_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_73) begin // @[L1DCache.scala 420:117]
- if (matchSet_19[1]) begin // @[L1DCache.scala 422:28]
- history_18_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_18_1 > _GEN_291) begin // @[L1DCache.scala 424:50]
- history_18_1 <= _history_18_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_18_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_73) begin // @[L1DCache.scala 420:117]
- if (matchSet_19[2]) begin // @[L1DCache.scala 422:28]
- history_18_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_18_2 > _GEN_291) begin // @[L1DCache.scala 424:50]
- history_18_2 <= _history_18_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_18_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_73) begin // @[L1DCache.scala 420:117]
- if (matchSet_19[3]) begin // @[L1DCache.scala 422:28]
- history_18_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_18_3 > _GEN_291) begin // @[L1DCache.scala 424:50]
- history_18_3 <= _history_18_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_19_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_77) begin // @[L1DCache.scala 420:117]
- if (matchSet_20[0]) begin // @[L1DCache.scala 422:28]
- history_19_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_19_0 > _GEN_307) begin // @[L1DCache.scala 424:50]
- history_19_0 <= _history_19_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_19_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_77) begin // @[L1DCache.scala 420:117]
- if (matchSet_20[1]) begin // @[L1DCache.scala 422:28]
- history_19_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_19_1 > _GEN_307) begin // @[L1DCache.scala 424:50]
- history_19_1 <= _history_19_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_19_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_77) begin // @[L1DCache.scala 420:117]
- if (matchSet_20[2]) begin // @[L1DCache.scala 422:28]
- history_19_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_19_2 > _GEN_307) begin // @[L1DCache.scala 424:50]
- history_19_2 <= _history_19_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_19_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_77) begin // @[L1DCache.scala 420:117]
- if (matchSet_20[3]) begin // @[L1DCache.scala 422:28]
- history_19_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_19_3 > _GEN_307) begin // @[L1DCache.scala 424:50]
- history_19_3 <= _history_19_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_20_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_81) begin // @[L1DCache.scala 420:117]
- if (matchSet_21[0]) begin // @[L1DCache.scala 422:28]
- history_20_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_20_0 > _GEN_323) begin // @[L1DCache.scala 424:50]
- history_20_0 <= _history_20_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_20_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_81) begin // @[L1DCache.scala 420:117]
- if (matchSet_21[1]) begin // @[L1DCache.scala 422:28]
- history_20_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_20_1 > _GEN_323) begin // @[L1DCache.scala 424:50]
- history_20_1 <= _history_20_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_20_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_81) begin // @[L1DCache.scala 420:117]
- if (matchSet_21[2]) begin // @[L1DCache.scala 422:28]
- history_20_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_20_2 > _GEN_323) begin // @[L1DCache.scala 424:50]
- history_20_2 <= _history_20_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_20_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_81) begin // @[L1DCache.scala 420:117]
- if (matchSet_21[3]) begin // @[L1DCache.scala 422:28]
- history_20_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_20_3 > _GEN_323) begin // @[L1DCache.scala 424:50]
- history_20_3 <= _history_20_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_21_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_85) begin // @[L1DCache.scala 420:117]
- if (matchSet_22[0]) begin // @[L1DCache.scala 422:28]
- history_21_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_21_0 > _GEN_339) begin // @[L1DCache.scala 424:50]
- history_21_0 <= _history_21_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_21_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_85) begin // @[L1DCache.scala 420:117]
- if (matchSet_22[1]) begin // @[L1DCache.scala 422:28]
- history_21_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_21_1 > _GEN_339) begin // @[L1DCache.scala 424:50]
- history_21_1 <= _history_21_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_21_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_85) begin // @[L1DCache.scala 420:117]
- if (matchSet_22[2]) begin // @[L1DCache.scala 422:28]
- history_21_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_21_2 > _GEN_339) begin // @[L1DCache.scala 424:50]
- history_21_2 <= _history_21_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_21_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_85) begin // @[L1DCache.scala 420:117]
- if (matchSet_22[3]) begin // @[L1DCache.scala 422:28]
- history_21_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_21_3 > _GEN_339) begin // @[L1DCache.scala 424:50]
- history_21_3 <= _history_21_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_22_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_89) begin // @[L1DCache.scala 420:117]
- if (matchSet_23[0]) begin // @[L1DCache.scala 422:28]
- history_22_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_22_0 > _GEN_355) begin // @[L1DCache.scala 424:50]
- history_22_0 <= _history_22_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_22_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_89) begin // @[L1DCache.scala 420:117]
- if (matchSet_23[1]) begin // @[L1DCache.scala 422:28]
- history_22_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_22_1 > _GEN_355) begin // @[L1DCache.scala 424:50]
- history_22_1 <= _history_22_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_22_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_89) begin // @[L1DCache.scala 420:117]
- if (matchSet_23[2]) begin // @[L1DCache.scala 422:28]
- history_22_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_22_2 > _GEN_355) begin // @[L1DCache.scala 424:50]
- history_22_2 <= _history_22_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_22_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_89) begin // @[L1DCache.scala 420:117]
- if (matchSet_23[3]) begin // @[L1DCache.scala 422:28]
- history_22_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_22_3 > _GEN_355) begin // @[L1DCache.scala 424:50]
- history_22_3 <= _history_22_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_23_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_93) begin // @[L1DCache.scala 420:117]
- if (matchSet_24[0]) begin // @[L1DCache.scala 422:28]
- history_23_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_23_0 > _GEN_371) begin // @[L1DCache.scala 424:50]
- history_23_0 <= _history_23_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_23_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_93) begin // @[L1DCache.scala 420:117]
- if (matchSet_24[1]) begin // @[L1DCache.scala 422:28]
- history_23_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_23_1 > _GEN_371) begin // @[L1DCache.scala 424:50]
- history_23_1 <= _history_23_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_23_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_93) begin // @[L1DCache.scala 420:117]
- if (matchSet_24[2]) begin // @[L1DCache.scala 422:28]
- history_23_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_23_2 > _GEN_371) begin // @[L1DCache.scala 424:50]
- history_23_2 <= _history_23_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_23_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_93) begin // @[L1DCache.scala 420:117]
- if (matchSet_24[3]) begin // @[L1DCache.scala 422:28]
- history_23_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_23_3 > _GEN_371) begin // @[L1DCache.scala 424:50]
- history_23_3 <= _history_23_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_24_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_97) begin // @[L1DCache.scala 420:117]
- if (matchSet_25[0]) begin // @[L1DCache.scala 422:28]
- history_24_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_24_0 > _GEN_387) begin // @[L1DCache.scala 424:50]
- history_24_0 <= _history_24_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_24_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_97) begin // @[L1DCache.scala 420:117]
- if (matchSet_25[1]) begin // @[L1DCache.scala 422:28]
- history_24_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_24_1 > _GEN_387) begin // @[L1DCache.scala 424:50]
- history_24_1 <= _history_24_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_24_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_97) begin // @[L1DCache.scala 420:117]
- if (matchSet_25[2]) begin // @[L1DCache.scala 422:28]
- history_24_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_24_2 > _GEN_387) begin // @[L1DCache.scala 424:50]
- history_24_2 <= _history_24_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_24_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_97) begin // @[L1DCache.scala 420:117]
- if (matchSet_25[3]) begin // @[L1DCache.scala 422:28]
- history_24_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_24_3 > _GEN_387) begin // @[L1DCache.scala 424:50]
- history_24_3 <= _history_24_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_25_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_101) begin // @[L1DCache.scala 420:117]
- if (matchSet_26[0]) begin // @[L1DCache.scala 422:28]
- history_25_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_25_0 > _GEN_403) begin // @[L1DCache.scala 424:50]
- history_25_0 <= _history_25_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_25_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_101) begin // @[L1DCache.scala 420:117]
- if (matchSet_26[1]) begin // @[L1DCache.scala 422:28]
- history_25_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_25_1 > _GEN_403) begin // @[L1DCache.scala 424:50]
- history_25_1 <= _history_25_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_25_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_101) begin // @[L1DCache.scala 420:117]
- if (matchSet_26[2]) begin // @[L1DCache.scala 422:28]
- history_25_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_25_2 > _GEN_403) begin // @[L1DCache.scala 424:50]
- history_25_2 <= _history_25_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_25_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_101) begin // @[L1DCache.scala 420:117]
- if (matchSet_26[3]) begin // @[L1DCache.scala 422:28]
- history_25_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_25_3 > _GEN_403) begin // @[L1DCache.scala 424:50]
- history_25_3 <= _history_25_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_26_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_105) begin // @[L1DCache.scala 420:117]
- if (matchSet_27[0]) begin // @[L1DCache.scala 422:28]
- history_26_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_26_0 > _GEN_419) begin // @[L1DCache.scala 424:50]
- history_26_0 <= _history_26_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_26_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_105) begin // @[L1DCache.scala 420:117]
- if (matchSet_27[1]) begin // @[L1DCache.scala 422:28]
- history_26_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_26_1 > _GEN_419) begin // @[L1DCache.scala 424:50]
- history_26_1 <= _history_26_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_26_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_105) begin // @[L1DCache.scala 420:117]
- if (matchSet_27[2]) begin // @[L1DCache.scala 422:28]
- history_26_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_26_2 > _GEN_419) begin // @[L1DCache.scala 424:50]
- history_26_2 <= _history_26_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_26_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_105) begin // @[L1DCache.scala 420:117]
- if (matchSet_27[3]) begin // @[L1DCache.scala 422:28]
- history_26_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_26_3 > _GEN_419) begin // @[L1DCache.scala 424:50]
- history_26_3 <= _history_26_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_27_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_109) begin // @[L1DCache.scala 420:117]
- if (matchSet_28[0]) begin // @[L1DCache.scala 422:28]
- history_27_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_27_0 > _GEN_435) begin // @[L1DCache.scala 424:50]
- history_27_0 <= _history_27_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_27_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_109) begin // @[L1DCache.scala 420:117]
- if (matchSet_28[1]) begin // @[L1DCache.scala 422:28]
- history_27_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_27_1 > _GEN_435) begin // @[L1DCache.scala 424:50]
- history_27_1 <= _history_27_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_27_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_109) begin // @[L1DCache.scala 420:117]
- if (matchSet_28[2]) begin // @[L1DCache.scala 422:28]
- history_27_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_27_2 > _GEN_435) begin // @[L1DCache.scala 424:50]
- history_27_2 <= _history_27_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_27_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_109) begin // @[L1DCache.scala 420:117]
- if (matchSet_28[3]) begin // @[L1DCache.scala 422:28]
- history_27_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_27_3 > _GEN_435) begin // @[L1DCache.scala 424:50]
- history_27_3 <= _history_27_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_28_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_113) begin // @[L1DCache.scala 420:117]
- if (matchSet_29[0]) begin // @[L1DCache.scala 422:28]
- history_28_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_28_0 > _GEN_451) begin // @[L1DCache.scala 424:50]
- history_28_0 <= _history_28_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_28_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_113) begin // @[L1DCache.scala 420:117]
- if (matchSet_29[1]) begin // @[L1DCache.scala 422:28]
- history_28_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_28_1 > _GEN_451) begin // @[L1DCache.scala 424:50]
- history_28_1 <= _history_28_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_28_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_113) begin // @[L1DCache.scala 420:117]
- if (matchSet_29[2]) begin // @[L1DCache.scala 422:28]
- history_28_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_28_2 > _GEN_451) begin // @[L1DCache.scala 424:50]
- history_28_2 <= _history_28_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_28_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_113) begin // @[L1DCache.scala 420:117]
- if (matchSet_29[3]) begin // @[L1DCache.scala 422:28]
- history_28_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_28_3 > _GEN_451) begin // @[L1DCache.scala 424:50]
- history_28_3 <= _history_28_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_29_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_117) begin // @[L1DCache.scala 420:117]
- if (matchSet_30[0]) begin // @[L1DCache.scala 422:28]
- history_29_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_29_0 > _GEN_467) begin // @[L1DCache.scala 424:50]
- history_29_0 <= _history_29_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_29_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_117) begin // @[L1DCache.scala 420:117]
- if (matchSet_30[1]) begin // @[L1DCache.scala 422:28]
- history_29_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_29_1 > _GEN_467) begin // @[L1DCache.scala 424:50]
- history_29_1 <= _history_29_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_29_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_117) begin // @[L1DCache.scala 420:117]
- if (matchSet_30[2]) begin // @[L1DCache.scala 422:28]
- history_29_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_29_2 > _GEN_467) begin // @[L1DCache.scala 424:50]
- history_29_2 <= _history_29_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_29_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_117) begin // @[L1DCache.scala 420:117]
- if (matchSet_30[3]) begin // @[L1DCache.scala 422:28]
- history_29_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_29_3 > _GEN_467) begin // @[L1DCache.scala 424:50]
- history_29_3 <= _history_29_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_30_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_121) begin // @[L1DCache.scala 420:117]
- if (matchSet_31[0]) begin // @[L1DCache.scala 422:28]
- history_30_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_30_0 > _GEN_483) begin // @[L1DCache.scala 424:50]
- history_30_0 <= _history_30_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_30_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_121) begin // @[L1DCache.scala 420:117]
- if (matchSet_31[1]) begin // @[L1DCache.scala 422:28]
- history_30_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_30_1 > _GEN_483) begin // @[L1DCache.scala 424:50]
- history_30_1 <= _history_30_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_30_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_121) begin // @[L1DCache.scala 420:117]
- if (matchSet_31[2]) begin // @[L1DCache.scala 422:28]
- history_30_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_30_2 > _GEN_483) begin // @[L1DCache.scala 424:50]
- history_30_2 <= _history_30_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_30_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_121) begin // @[L1DCache.scala 420:117]
- if (matchSet_31[3]) begin // @[L1DCache.scala 422:28]
- history_30_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_30_3 > _GEN_483) begin // @[L1DCache.scala 424:50]
- history_30_3 <= _history_30_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_31_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_125) begin // @[L1DCache.scala 420:117]
- if (matchSet_32[0]) begin // @[L1DCache.scala 422:28]
- history_31_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_31_0 > _GEN_499) begin // @[L1DCache.scala 424:50]
- history_31_0 <= _history_31_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_31_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_125) begin // @[L1DCache.scala 420:117]
- if (matchSet_32[1]) begin // @[L1DCache.scala 422:28]
- history_31_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_31_1 > _GEN_499) begin // @[L1DCache.scala 424:50]
- history_31_1 <= _history_31_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_31_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_125) begin // @[L1DCache.scala 420:117]
- if (matchSet_32[2]) begin // @[L1DCache.scala 422:28]
- history_31_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_31_2 > _GEN_499) begin // @[L1DCache.scala 424:50]
- history_31_2 <= _history_31_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_31_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_125) begin // @[L1DCache.scala 420:117]
- if (matchSet_32[3]) begin // @[L1DCache.scala 422:28]
- history_31_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_31_3 > _GEN_499) begin // @[L1DCache.scala 424:50]
- history_31_3 <= _history_31_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_32_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_129) begin // @[L1DCache.scala 420:117]
- if (matchSet_33[0]) begin // @[L1DCache.scala 422:28]
- history_32_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_32_0 > _GEN_515) begin // @[L1DCache.scala 424:50]
- history_32_0 <= _history_32_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_32_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_129) begin // @[L1DCache.scala 420:117]
- if (matchSet_33[1]) begin // @[L1DCache.scala 422:28]
- history_32_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_32_1 > _GEN_515) begin // @[L1DCache.scala 424:50]
- history_32_1 <= _history_32_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_32_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_129) begin // @[L1DCache.scala 420:117]
- if (matchSet_33[2]) begin // @[L1DCache.scala 422:28]
- history_32_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_32_2 > _GEN_515) begin // @[L1DCache.scala 424:50]
- history_32_2 <= _history_32_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_32_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_129) begin // @[L1DCache.scala 420:117]
- if (matchSet_33[3]) begin // @[L1DCache.scala 422:28]
- history_32_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_32_3 > _GEN_515) begin // @[L1DCache.scala 424:50]
- history_32_3 <= _history_32_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_33_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_133) begin // @[L1DCache.scala 420:117]
- if (matchSet_34[0]) begin // @[L1DCache.scala 422:28]
- history_33_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_33_0 > _GEN_531) begin // @[L1DCache.scala 424:50]
- history_33_0 <= _history_33_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_33_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_133) begin // @[L1DCache.scala 420:117]
- if (matchSet_34[1]) begin // @[L1DCache.scala 422:28]
- history_33_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_33_1 > _GEN_531) begin // @[L1DCache.scala 424:50]
- history_33_1 <= _history_33_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_33_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_133) begin // @[L1DCache.scala 420:117]
- if (matchSet_34[2]) begin // @[L1DCache.scala 422:28]
- history_33_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_33_2 > _GEN_531) begin // @[L1DCache.scala 424:50]
- history_33_2 <= _history_33_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_33_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_133) begin // @[L1DCache.scala 420:117]
- if (matchSet_34[3]) begin // @[L1DCache.scala 422:28]
- history_33_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_33_3 > _GEN_531) begin // @[L1DCache.scala 424:50]
- history_33_3 <= _history_33_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_34_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_137) begin // @[L1DCache.scala 420:117]
- if (matchSet_35[0]) begin // @[L1DCache.scala 422:28]
- history_34_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_34_0 > _GEN_547) begin // @[L1DCache.scala 424:50]
- history_34_0 <= _history_34_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_34_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_137) begin // @[L1DCache.scala 420:117]
- if (matchSet_35[1]) begin // @[L1DCache.scala 422:28]
- history_34_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_34_1 > _GEN_547) begin // @[L1DCache.scala 424:50]
- history_34_1 <= _history_34_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_34_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_137) begin // @[L1DCache.scala 420:117]
- if (matchSet_35[2]) begin // @[L1DCache.scala 422:28]
- history_34_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_34_2 > _GEN_547) begin // @[L1DCache.scala 424:50]
- history_34_2 <= _history_34_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_34_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_137) begin // @[L1DCache.scala 420:117]
- if (matchSet_35[3]) begin // @[L1DCache.scala 422:28]
- history_34_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_34_3 > _GEN_547) begin // @[L1DCache.scala 424:50]
- history_34_3 <= _history_34_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_35_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_141) begin // @[L1DCache.scala 420:117]
- if (matchSet_36[0]) begin // @[L1DCache.scala 422:28]
- history_35_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_35_0 > _GEN_563) begin // @[L1DCache.scala 424:50]
- history_35_0 <= _history_35_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_35_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_141) begin // @[L1DCache.scala 420:117]
- if (matchSet_36[1]) begin // @[L1DCache.scala 422:28]
- history_35_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_35_1 > _GEN_563) begin // @[L1DCache.scala 424:50]
- history_35_1 <= _history_35_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_35_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_141) begin // @[L1DCache.scala 420:117]
- if (matchSet_36[2]) begin // @[L1DCache.scala 422:28]
- history_35_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_35_2 > _GEN_563) begin // @[L1DCache.scala 424:50]
- history_35_2 <= _history_35_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_35_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_141) begin // @[L1DCache.scala 420:117]
- if (matchSet_36[3]) begin // @[L1DCache.scala 422:28]
- history_35_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_35_3 > _GEN_563) begin // @[L1DCache.scala 424:50]
- history_35_3 <= _history_35_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_36_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_145) begin // @[L1DCache.scala 420:117]
- if (matchSet_37[0]) begin // @[L1DCache.scala 422:28]
- history_36_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_36_0 > _GEN_579) begin // @[L1DCache.scala 424:50]
- history_36_0 <= _history_36_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_36_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_145) begin // @[L1DCache.scala 420:117]
- if (matchSet_37[1]) begin // @[L1DCache.scala 422:28]
- history_36_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_36_1 > _GEN_579) begin // @[L1DCache.scala 424:50]
- history_36_1 <= _history_36_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_36_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_145) begin // @[L1DCache.scala 420:117]
- if (matchSet_37[2]) begin // @[L1DCache.scala 422:28]
- history_36_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_36_2 > _GEN_579) begin // @[L1DCache.scala 424:50]
- history_36_2 <= _history_36_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_36_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_145) begin // @[L1DCache.scala 420:117]
- if (matchSet_37[3]) begin // @[L1DCache.scala 422:28]
- history_36_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_36_3 > _GEN_579) begin // @[L1DCache.scala 424:50]
- history_36_3 <= _history_36_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_37_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_149) begin // @[L1DCache.scala 420:117]
- if (matchSet_38[0]) begin // @[L1DCache.scala 422:28]
- history_37_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_37_0 > _GEN_595) begin // @[L1DCache.scala 424:50]
- history_37_0 <= _history_37_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_37_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_149) begin // @[L1DCache.scala 420:117]
- if (matchSet_38[1]) begin // @[L1DCache.scala 422:28]
- history_37_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_37_1 > _GEN_595) begin // @[L1DCache.scala 424:50]
- history_37_1 <= _history_37_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_37_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_149) begin // @[L1DCache.scala 420:117]
- if (matchSet_38[2]) begin // @[L1DCache.scala 422:28]
- history_37_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_37_2 > _GEN_595) begin // @[L1DCache.scala 424:50]
- history_37_2 <= _history_37_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_37_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_149) begin // @[L1DCache.scala 420:117]
- if (matchSet_38[3]) begin // @[L1DCache.scala 422:28]
- history_37_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_37_3 > _GEN_595) begin // @[L1DCache.scala 424:50]
- history_37_3 <= _history_37_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_38_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_153) begin // @[L1DCache.scala 420:117]
- if (matchSet_39[0]) begin // @[L1DCache.scala 422:28]
- history_38_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_38_0 > _GEN_611) begin // @[L1DCache.scala 424:50]
- history_38_0 <= _history_38_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_38_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_153) begin // @[L1DCache.scala 420:117]
- if (matchSet_39[1]) begin // @[L1DCache.scala 422:28]
- history_38_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_38_1 > _GEN_611) begin // @[L1DCache.scala 424:50]
- history_38_1 <= _history_38_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_38_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_153) begin // @[L1DCache.scala 420:117]
- if (matchSet_39[2]) begin // @[L1DCache.scala 422:28]
- history_38_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_38_2 > _GEN_611) begin // @[L1DCache.scala 424:50]
- history_38_2 <= _history_38_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_38_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_153) begin // @[L1DCache.scala 420:117]
- if (matchSet_39[3]) begin // @[L1DCache.scala 422:28]
- history_38_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_38_3 > _GEN_611) begin // @[L1DCache.scala 424:50]
- history_38_3 <= _history_38_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_39_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_157) begin // @[L1DCache.scala 420:117]
- if (matchSet_40[0]) begin // @[L1DCache.scala 422:28]
- history_39_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_39_0 > _GEN_627) begin // @[L1DCache.scala 424:50]
- history_39_0 <= _history_39_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_39_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_157) begin // @[L1DCache.scala 420:117]
- if (matchSet_40[1]) begin // @[L1DCache.scala 422:28]
- history_39_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_39_1 > _GEN_627) begin // @[L1DCache.scala 424:50]
- history_39_1 <= _history_39_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_39_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_157) begin // @[L1DCache.scala 420:117]
- if (matchSet_40[2]) begin // @[L1DCache.scala 422:28]
- history_39_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_39_2 > _GEN_627) begin // @[L1DCache.scala 424:50]
- history_39_2 <= _history_39_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_39_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_157) begin // @[L1DCache.scala 420:117]
- if (matchSet_40[3]) begin // @[L1DCache.scala 422:28]
- history_39_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_39_3 > _GEN_627) begin // @[L1DCache.scala 424:50]
- history_39_3 <= _history_39_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_40_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_161) begin // @[L1DCache.scala 420:117]
- if (matchSet_41[0]) begin // @[L1DCache.scala 422:28]
- history_40_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_40_0 > _GEN_643) begin // @[L1DCache.scala 424:50]
- history_40_0 <= _history_40_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_40_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_161) begin // @[L1DCache.scala 420:117]
- if (matchSet_41[1]) begin // @[L1DCache.scala 422:28]
- history_40_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_40_1 > _GEN_643) begin // @[L1DCache.scala 424:50]
- history_40_1 <= _history_40_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_40_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_161) begin // @[L1DCache.scala 420:117]
- if (matchSet_41[2]) begin // @[L1DCache.scala 422:28]
- history_40_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_40_2 > _GEN_643) begin // @[L1DCache.scala 424:50]
- history_40_2 <= _history_40_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_40_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_161) begin // @[L1DCache.scala 420:117]
- if (matchSet_41[3]) begin // @[L1DCache.scala 422:28]
- history_40_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_40_3 > _GEN_643) begin // @[L1DCache.scala 424:50]
- history_40_3 <= _history_40_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_41_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_165) begin // @[L1DCache.scala 420:117]
- if (matchSet_42[0]) begin // @[L1DCache.scala 422:28]
- history_41_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_41_0 > _GEN_659) begin // @[L1DCache.scala 424:50]
- history_41_0 <= _history_41_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_41_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_165) begin // @[L1DCache.scala 420:117]
- if (matchSet_42[1]) begin // @[L1DCache.scala 422:28]
- history_41_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_41_1 > _GEN_659) begin // @[L1DCache.scala 424:50]
- history_41_1 <= _history_41_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_41_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_165) begin // @[L1DCache.scala 420:117]
- if (matchSet_42[2]) begin // @[L1DCache.scala 422:28]
- history_41_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_41_2 > _GEN_659) begin // @[L1DCache.scala 424:50]
- history_41_2 <= _history_41_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_41_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_165) begin // @[L1DCache.scala 420:117]
- if (matchSet_42[3]) begin // @[L1DCache.scala 422:28]
- history_41_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_41_3 > _GEN_659) begin // @[L1DCache.scala 424:50]
- history_41_3 <= _history_41_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_42_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_169) begin // @[L1DCache.scala 420:117]
- if (matchSet_43[0]) begin // @[L1DCache.scala 422:28]
- history_42_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_42_0 > _GEN_675) begin // @[L1DCache.scala 424:50]
- history_42_0 <= _history_42_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_42_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_169) begin // @[L1DCache.scala 420:117]
- if (matchSet_43[1]) begin // @[L1DCache.scala 422:28]
- history_42_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_42_1 > _GEN_675) begin // @[L1DCache.scala 424:50]
- history_42_1 <= _history_42_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_42_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_169) begin // @[L1DCache.scala 420:117]
- if (matchSet_43[2]) begin // @[L1DCache.scala 422:28]
- history_42_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_42_2 > _GEN_675) begin // @[L1DCache.scala 424:50]
- history_42_2 <= _history_42_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_42_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_169) begin // @[L1DCache.scala 420:117]
- if (matchSet_43[3]) begin // @[L1DCache.scala 422:28]
- history_42_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_42_3 > _GEN_675) begin // @[L1DCache.scala 424:50]
- history_42_3 <= _history_42_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_43_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_173) begin // @[L1DCache.scala 420:117]
- if (matchSet_44[0]) begin // @[L1DCache.scala 422:28]
- history_43_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_43_0 > _GEN_691) begin // @[L1DCache.scala 424:50]
- history_43_0 <= _history_43_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_43_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_173) begin // @[L1DCache.scala 420:117]
- if (matchSet_44[1]) begin // @[L1DCache.scala 422:28]
- history_43_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_43_1 > _GEN_691) begin // @[L1DCache.scala 424:50]
- history_43_1 <= _history_43_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_43_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_173) begin // @[L1DCache.scala 420:117]
- if (matchSet_44[2]) begin // @[L1DCache.scala 422:28]
- history_43_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_43_2 > _GEN_691) begin // @[L1DCache.scala 424:50]
- history_43_2 <= _history_43_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_43_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_173) begin // @[L1DCache.scala 420:117]
- if (matchSet_44[3]) begin // @[L1DCache.scala 422:28]
- history_43_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_43_3 > _GEN_691) begin // @[L1DCache.scala 424:50]
- history_43_3 <= _history_43_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_44_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_177) begin // @[L1DCache.scala 420:117]
- if (matchSet_45[0]) begin // @[L1DCache.scala 422:28]
- history_44_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_44_0 > _GEN_707) begin // @[L1DCache.scala 424:50]
- history_44_0 <= _history_44_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_44_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_177) begin // @[L1DCache.scala 420:117]
- if (matchSet_45[1]) begin // @[L1DCache.scala 422:28]
- history_44_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_44_1 > _GEN_707) begin // @[L1DCache.scala 424:50]
- history_44_1 <= _history_44_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_44_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_177) begin // @[L1DCache.scala 420:117]
- if (matchSet_45[2]) begin // @[L1DCache.scala 422:28]
- history_44_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_44_2 > _GEN_707) begin // @[L1DCache.scala 424:50]
- history_44_2 <= _history_44_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_44_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_177) begin // @[L1DCache.scala 420:117]
- if (matchSet_45[3]) begin // @[L1DCache.scala 422:28]
- history_44_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_44_3 > _GEN_707) begin // @[L1DCache.scala 424:50]
- history_44_3 <= _history_44_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_45_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_181) begin // @[L1DCache.scala 420:117]
- if (matchSet_46[0]) begin // @[L1DCache.scala 422:28]
- history_45_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_45_0 > _GEN_723) begin // @[L1DCache.scala 424:50]
- history_45_0 <= _history_45_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_45_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_181) begin // @[L1DCache.scala 420:117]
- if (matchSet_46[1]) begin // @[L1DCache.scala 422:28]
- history_45_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_45_1 > _GEN_723) begin // @[L1DCache.scala 424:50]
- history_45_1 <= _history_45_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_45_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_181) begin // @[L1DCache.scala 420:117]
- if (matchSet_46[2]) begin // @[L1DCache.scala 422:28]
- history_45_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_45_2 > _GEN_723) begin // @[L1DCache.scala 424:50]
- history_45_2 <= _history_45_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_45_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_181) begin // @[L1DCache.scala 420:117]
- if (matchSet_46[3]) begin // @[L1DCache.scala 422:28]
- history_45_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_45_3 > _GEN_723) begin // @[L1DCache.scala 424:50]
- history_45_3 <= _history_45_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_46_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_185) begin // @[L1DCache.scala 420:117]
- if (matchSet_47[0]) begin // @[L1DCache.scala 422:28]
- history_46_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_46_0 > _GEN_739) begin // @[L1DCache.scala 424:50]
- history_46_0 <= _history_46_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_46_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_185) begin // @[L1DCache.scala 420:117]
- if (matchSet_47[1]) begin // @[L1DCache.scala 422:28]
- history_46_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_46_1 > _GEN_739) begin // @[L1DCache.scala 424:50]
- history_46_1 <= _history_46_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_46_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_185) begin // @[L1DCache.scala 420:117]
- if (matchSet_47[2]) begin // @[L1DCache.scala 422:28]
- history_46_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_46_2 > _GEN_739) begin // @[L1DCache.scala 424:50]
- history_46_2 <= _history_46_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_46_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_185) begin // @[L1DCache.scala 420:117]
- if (matchSet_47[3]) begin // @[L1DCache.scala 422:28]
- history_46_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_46_3 > _GEN_739) begin // @[L1DCache.scala 424:50]
- history_46_3 <= _history_46_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_47_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_189) begin // @[L1DCache.scala 420:117]
- if (matchSet_48[0]) begin // @[L1DCache.scala 422:28]
- history_47_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_47_0 > _GEN_755) begin // @[L1DCache.scala 424:50]
- history_47_0 <= _history_47_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_47_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_189) begin // @[L1DCache.scala 420:117]
- if (matchSet_48[1]) begin // @[L1DCache.scala 422:28]
- history_47_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_47_1 > _GEN_755) begin // @[L1DCache.scala 424:50]
- history_47_1 <= _history_47_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_47_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_189) begin // @[L1DCache.scala 420:117]
- if (matchSet_48[2]) begin // @[L1DCache.scala 422:28]
- history_47_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_47_2 > _GEN_755) begin // @[L1DCache.scala 424:50]
- history_47_2 <= _history_47_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_47_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_189) begin // @[L1DCache.scala 420:117]
- if (matchSet_48[3]) begin // @[L1DCache.scala 422:28]
- history_47_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_47_3 > _GEN_755) begin // @[L1DCache.scala 424:50]
- history_47_3 <= _history_47_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_48_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_193) begin // @[L1DCache.scala 420:117]
- if (matchSet_49[0]) begin // @[L1DCache.scala 422:28]
- history_48_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_48_0 > _GEN_771) begin // @[L1DCache.scala 424:50]
- history_48_0 <= _history_48_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_48_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_193) begin // @[L1DCache.scala 420:117]
- if (matchSet_49[1]) begin // @[L1DCache.scala 422:28]
- history_48_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_48_1 > _GEN_771) begin // @[L1DCache.scala 424:50]
- history_48_1 <= _history_48_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_48_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_193) begin // @[L1DCache.scala 420:117]
- if (matchSet_49[2]) begin // @[L1DCache.scala 422:28]
- history_48_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_48_2 > _GEN_771) begin // @[L1DCache.scala 424:50]
- history_48_2 <= _history_48_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_48_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_193) begin // @[L1DCache.scala 420:117]
- if (matchSet_49[3]) begin // @[L1DCache.scala 422:28]
- history_48_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_48_3 > _GEN_771) begin // @[L1DCache.scala 424:50]
- history_48_3 <= _history_48_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_49_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_197) begin // @[L1DCache.scala 420:117]
- if (matchSet_50[0]) begin // @[L1DCache.scala 422:28]
- history_49_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_49_0 > _GEN_787) begin // @[L1DCache.scala 424:50]
- history_49_0 <= _history_49_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_49_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_197) begin // @[L1DCache.scala 420:117]
- if (matchSet_50[1]) begin // @[L1DCache.scala 422:28]
- history_49_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_49_1 > _GEN_787) begin // @[L1DCache.scala 424:50]
- history_49_1 <= _history_49_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_49_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_197) begin // @[L1DCache.scala 420:117]
- if (matchSet_50[2]) begin // @[L1DCache.scala 422:28]
- history_49_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_49_2 > _GEN_787) begin // @[L1DCache.scala 424:50]
- history_49_2 <= _history_49_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_49_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_197) begin // @[L1DCache.scala 420:117]
- if (matchSet_50[3]) begin // @[L1DCache.scala 422:28]
- history_49_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_49_3 > _GEN_787) begin // @[L1DCache.scala 424:50]
- history_49_3 <= _history_49_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_50_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_201) begin // @[L1DCache.scala 420:117]
- if (matchSet_51[0]) begin // @[L1DCache.scala 422:28]
- history_50_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_50_0 > _GEN_803) begin // @[L1DCache.scala 424:50]
- history_50_0 <= _history_50_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_50_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_201) begin // @[L1DCache.scala 420:117]
- if (matchSet_51[1]) begin // @[L1DCache.scala 422:28]
- history_50_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_50_1 > _GEN_803) begin // @[L1DCache.scala 424:50]
- history_50_1 <= _history_50_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_50_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_201) begin // @[L1DCache.scala 420:117]
- if (matchSet_51[2]) begin // @[L1DCache.scala 422:28]
- history_50_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_50_2 > _GEN_803) begin // @[L1DCache.scala 424:50]
- history_50_2 <= _history_50_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_50_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_201) begin // @[L1DCache.scala 420:117]
- if (matchSet_51[3]) begin // @[L1DCache.scala 422:28]
- history_50_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_50_3 > _GEN_803) begin // @[L1DCache.scala 424:50]
- history_50_3 <= _history_50_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_51_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_205) begin // @[L1DCache.scala 420:117]
- if (matchSet_52[0]) begin // @[L1DCache.scala 422:28]
- history_51_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_51_0 > _GEN_819) begin // @[L1DCache.scala 424:50]
- history_51_0 <= _history_51_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_51_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_205) begin // @[L1DCache.scala 420:117]
- if (matchSet_52[1]) begin // @[L1DCache.scala 422:28]
- history_51_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_51_1 > _GEN_819) begin // @[L1DCache.scala 424:50]
- history_51_1 <= _history_51_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_51_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_205) begin // @[L1DCache.scala 420:117]
- if (matchSet_52[2]) begin // @[L1DCache.scala 422:28]
- history_51_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_51_2 > _GEN_819) begin // @[L1DCache.scala 424:50]
- history_51_2 <= _history_51_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_51_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_205) begin // @[L1DCache.scala 420:117]
- if (matchSet_52[3]) begin // @[L1DCache.scala 422:28]
- history_51_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_51_3 > _GEN_819) begin // @[L1DCache.scala 424:50]
- history_51_3 <= _history_51_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_52_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_209) begin // @[L1DCache.scala 420:117]
- if (matchSet_53[0]) begin // @[L1DCache.scala 422:28]
- history_52_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_52_0 > _GEN_835) begin // @[L1DCache.scala 424:50]
- history_52_0 <= _history_52_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_52_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_209) begin // @[L1DCache.scala 420:117]
- if (matchSet_53[1]) begin // @[L1DCache.scala 422:28]
- history_52_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_52_1 > _GEN_835) begin // @[L1DCache.scala 424:50]
- history_52_1 <= _history_52_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_52_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_209) begin // @[L1DCache.scala 420:117]
- if (matchSet_53[2]) begin // @[L1DCache.scala 422:28]
- history_52_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_52_2 > _GEN_835) begin // @[L1DCache.scala 424:50]
- history_52_2 <= _history_52_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_52_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_209) begin // @[L1DCache.scala 420:117]
- if (matchSet_53[3]) begin // @[L1DCache.scala 422:28]
- history_52_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_52_3 > _GEN_835) begin // @[L1DCache.scala 424:50]
- history_52_3 <= _history_52_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_53_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_213) begin // @[L1DCache.scala 420:117]
- if (matchSet_54[0]) begin // @[L1DCache.scala 422:28]
- history_53_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_53_0 > _GEN_851) begin // @[L1DCache.scala 424:50]
- history_53_0 <= _history_53_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_53_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_213) begin // @[L1DCache.scala 420:117]
- if (matchSet_54[1]) begin // @[L1DCache.scala 422:28]
- history_53_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_53_1 > _GEN_851) begin // @[L1DCache.scala 424:50]
- history_53_1 <= _history_53_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_53_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_213) begin // @[L1DCache.scala 420:117]
- if (matchSet_54[2]) begin // @[L1DCache.scala 422:28]
- history_53_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_53_2 > _GEN_851) begin // @[L1DCache.scala 424:50]
- history_53_2 <= _history_53_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_53_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_213) begin // @[L1DCache.scala 420:117]
- if (matchSet_54[3]) begin // @[L1DCache.scala 422:28]
- history_53_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_53_3 > _GEN_851) begin // @[L1DCache.scala 424:50]
- history_53_3 <= _history_53_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_54_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_217) begin // @[L1DCache.scala 420:117]
- if (matchSet_55[0]) begin // @[L1DCache.scala 422:28]
- history_54_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_54_0 > _GEN_867) begin // @[L1DCache.scala 424:50]
- history_54_0 <= _history_54_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_54_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_217) begin // @[L1DCache.scala 420:117]
- if (matchSet_55[1]) begin // @[L1DCache.scala 422:28]
- history_54_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_54_1 > _GEN_867) begin // @[L1DCache.scala 424:50]
- history_54_1 <= _history_54_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_54_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_217) begin // @[L1DCache.scala 420:117]
- if (matchSet_55[2]) begin // @[L1DCache.scala 422:28]
- history_54_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_54_2 > _GEN_867) begin // @[L1DCache.scala 424:50]
- history_54_2 <= _history_54_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_54_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_217) begin // @[L1DCache.scala 420:117]
- if (matchSet_55[3]) begin // @[L1DCache.scala 422:28]
- history_54_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_54_3 > _GEN_867) begin // @[L1DCache.scala 424:50]
- history_54_3 <= _history_54_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_55_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_221) begin // @[L1DCache.scala 420:117]
- if (matchSet_56[0]) begin // @[L1DCache.scala 422:28]
- history_55_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_55_0 > _GEN_883) begin // @[L1DCache.scala 424:50]
- history_55_0 <= _history_55_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_55_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_221) begin // @[L1DCache.scala 420:117]
- if (matchSet_56[1]) begin // @[L1DCache.scala 422:28]
- history_55_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_55_1 > _GEN_883) begin // @[L1DCache.scala 424:50]
- history_55_1 <= _history_55_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_55_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_221) begin // @[L1DCache.scala 420:117]
- if (matchSet_56[2]) begin // @[L1DCache.scala 422:28]
- history_55_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_55_2 > _GEN_883) begin // @[L1DCache.scala 424:50]
- history_55_2 <= _history_55_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_55_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_221) begin // @[L1DCache.scala 420:117]
- if (matchSet_56[3]) begin // @[L1DCache.scala 422:28]
- history_55_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_55_3 > _GEN_883) begin // @[L1DCache.scala 424:50]
- history_55_3 <= _history_55_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_56_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_225) begin // @[L1DCache.scala 420:117]
- if (matchSet_57[0]) begin // @[L1DCache.scala 422:28]
- history_56_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_56_0 > _GEN_899) begin // @[L1DCache.scala 424:50]
- history_56_0 <= _history_56_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_56_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_225) begin // @[L1DCache.scala 420:117]
- if (matchSet_57[1]) begin // @[L1DCache.scala 422:28]
- history_56_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_56_1 > _GEN_899) begin // @[L1DCache.scala 424:50]
- history_56_1 <= _history_56_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_56_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_225) begin // @[L1DCache.scala 420:117]
- if (matchSet_57[2]) begin // @[L1DCache.scala 422:28]
- history_56_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_56_2 > _GEN_899) begin // @[L1DCache.scala 424:50]
- history_56_2 <= _history_56_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_56_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_225) begin // @[L1DCache.scala 420:117]
- if (matchSet_57[3]) begin // @[L1DCache.scala 422:28]
- history_56_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_56_3 > _GEN_899) begin // @[L1DCache.scala 424:50]
- history_56_3 <= _history_56_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_57_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_229) begin // @[L1DCache.scala 420:117]
- if (matchSet_58[0]) begin // @[L1DCache.scala 422:28]
- history_57_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_57_0 > _GEN_915) begin // @[L1DCache.scala 424:50]
- history_57_0 <= _history_57_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_57_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_229) begin // @[L1DCache.scala 420:117]
- if (matchSet_58[1]) begin // @[L1DCache.scala 422:28]
- history_57_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_57_1 > _GEN_915) begin // @[L1DCache.scala 424:50]
- history_57_1 <= _history_57_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_57_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_229) begin // @[L1DCache.scala 420:117]
- if (matchSet_58[2]) begin // @[L1DCache.scala 422:28]
- history_57_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_57_2 > _GEN_915) begin // @[L1DCache.scala 424:50]
- history_57_2 <= _history_57_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_57_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_229) begin // @[L1DCache.scala 420:117]
- if (matchSet_58[3]) begin // @[L1DCache.scala 422:28]
- history_57_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_57_3 > _GEN_915) begin // @[L1DCache.scala 424:50]
- history_57_3 <= _history_57_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_58_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_233) begin // @[L1DCache.scala 420:117]
- if (matchSet_59[0]) begin // @[L1DCache.scala 422:28]
- history_58_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_58_0 > _GEN_931) begin // @[L1DCache.scala 424:50]
- history_58_0 <= _history_58_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_58_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_233) begin // @[L1DCache.scala 420:117]
- if (matchSet_59[1]) begin // @[L1DCache.scala 422:28]
- history_58_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_58_1 > _GEN_931) begin // @[L1DCache.scala 424:50]
- history_58_1 <= _history_58_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_58_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_233) begin // @[L1DCache.scala 420:117]
- if (matchSet_59[2]) begin // @[L1DCache.scala 422:28]
- history_58_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_58_2 > _GEN_931) begin // @[L1DCache.scala 424:50]
- history_58_2 <= _history_58_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_58_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_233) begin // @[L1DCache.scala 420:117]
- if (matchSet_59[3]) begin // @[L1DCache.scala 422:28]
- history_58_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_58_3 > _GEN_931) begin // @[L1DCache.scala 424:50]
- history_58_3 <= _history_58_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_59_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_237) begin // @[L1DCache.scala 420:117]
- if (matchSet_60[0]) begin // @[L1DCache.scala 422:28]
- history_59_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_59_0 > _GEN_947) begin // @[L1DCache.scala 424:50]
- history_59_0 <= _history_59_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_59_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_237) begin // @[L1DCache.scala 420:117]
- if (matchSet_60[1]) begin // @[L1DCache.scala 422:28]
- history_59_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_59_1 > _GEN_947) begin // @[L1DCache.scala 424:50]
- history_59_1 <= _history_59_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_59_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_237) begin // @[L1DCache.scala 420:117]
- if (matchSet_60[2]) begin // @[L1DCache.scala 422:28]
- history_59_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_59_2 > _GEN_947) begin // @[L1DCache.scala 424:50]
- history_59_2 <= _history_59_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_59_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_237) begin // @[L1DCache.scala 420:117]
- if (matchSet_60[3]) begin // @[L1DCache.scala 422:28]
- history_59_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_59_3 > _GEN_947) begin // @[L1DCache.scala 424:50]
- history_59_3 <= _history_59_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_60_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_241) begin // @[L1DCache.scala 420:117]
- if (matchSet_61[0]) begin // @[L1DCache.scala 422:28]
- history_60_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_60_0 > _GEN_963) begin // @[L1DCache.scala 424:50]
- history_60_0 <= _history_60_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_60_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_241) begin // @[L1DCache.scala 420:117]
- if (matchSet_61[1]) begin // @[L1DCache.scala 422:28]
- history_60_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_60_1 > _GEN_963) begin // @[L1DCache.scala 424:50]
- history_60_1 <= _history_60_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_60_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_241) begin // @[L1DCache.scala 420:117]
- if (matchSet_61[2]) begin // @[L1DCache.scala 422:28]
- history_60_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_60_2 > _GEN_963) begin // @[L1DCache.scala 424:50]
- history_60_2 <= _history_60_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_60_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_241) begin // @[L1DCache.scala 420:117]
- if (matchSet_61[3]) begin // @[L1DCache.scala 422:28]
- history_60_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_60_3 > _GEN_963) begin // @[L1DCache.scala 424:50]
- history_60_3 <= _history_60_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_61_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_245) begin // @[L1DCache.scala 420:117]
- if (matchSet_62[0]) begin // @[L1DCache.scala 422:28]
- history_61_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_61_0 > _GEN_979) begin // @[L1DCache.scala 424:50]
- history_61_0 <= _history_61_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_61_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_245) begin // @[L1DCache.scala 420:117]
- if (matchSet_62[1]) begin // @[L1DCache.scala 422:28]
- history_61_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_61_1 > _GEN_979) begin // @[L1DCache.scala 424:50]
- history_61_1 <= _history_61_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_61_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_245) begin // @[L1DCache.scala 420:117]
- if (matchSet_62[2]) begin // @[L1DCache.scala 422:28]
- history_61_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_61_2 > _GEN_979) begin // @[L1DCache.scala 424:50]
- history_61_2 <= _history_61_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_61_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_245) begin // @[L1DCache.scala 420:117]
- if (matchSet_62[3]) begin // @[L1DCache.scala 422:28]
- history_61_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_61_3 > _GEN_979) begin // @[L1DCache.scala 424:50]
- history_61_3 <= _history_61_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_62_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_249) begin // @[L1DCache.scala 420:117]
- if (matchSet_63[0]) begin // @[L1DCache.scala 422:28]
- history_62_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_62_0 > _GEN_995) begin // @[L1DCache.scala 424:50]
- history_62_0 <= _history_62_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_62_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_249) begin // @[L1DCache.scala 420:117]
- if (matchSet_63[1]) begin // @[L1DCache.scala 422:28]
- history_62_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_62_1 > _GEN_995) begin // @[L1DCache.scala 424:50]
- history_62_1 <= _history_62_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_62_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_249) begin // @[L1DCache.scala 420:117]
- if (matchSet_63[2]) begin // @[L1DCache.scala 422:28]
- history_62_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_62_2 > _GEN_995) begin // @[L1DCache.scala 424:50]
- history_62_2 <= _history_62_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_62_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_249) begin // @[L1DCache.scala 420:117]
- if (matchSet_63[3]) begin // @[L1DCache.scala 422:28]
- history_62_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_62_3 > _GEN_995) begin // @[L1DCache.scala 424:50]
- history_62_3 <= _history_62_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_63_0 <= 2'h0; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_253) begin // @[L1DCache.scala 420:117]
- if (matchSet_64[0]) begin // @[L1DCache.scala 422:28]
- history_63_0 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_63_0 > _GEN_1011) begin // @[L1DCache.scala 424:50]
- history_63_0 <= _history_63_0_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_63_1 <= 2'h1; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_253) begin // @[L1DCache.scala 420:117]
- if (matchSet_64[1]) begin // @[L1DCache.scala 422:28]
- history_63_1 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_63_1 > _GEN_1011) begin // @[L1DCache.scala 424:50]
- history_63_1 <= _history_63_1_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_63_2 <= 2'h2; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_253) begin // @[L1DCache.scala 420:117]
- if (matchSet_64[2]) begin // @[L1DCache.scala 422:28]
- history_63_2 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_63_2 > _GEN_1011) begin // @[L1DCache.scala 424:50]
- history_63_2 <= _history_63_2_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (reset) begin // @[L1DCache.scala 435:23]
- history_63_3 <= 2'h3; // @[L1DCache.scala 438:23]
- end else if (io_dbus_valid & io_dbus_ready & setMatch_253) begin // @[L1DCache.scala 420:117]
- if (matchSet_64[3]) begin // @[L1DCache.scala 422:28]
- history_63_3 <= 2'h3; // @[L1DCache.scala 423:25]
- end else if (history_63_3 > _GEN_1011) begin // @[L1DCache.scala 424:50]
- history_63_3 <= _history_63_3_T_1; // @[L1DCache.scala 425:25]
- end
- end
- if (memwdataEn) begin // @[L1DCache.scala 522:21]
- axiwdatabuf <= _axiwdatabuf_T; // @[L1DCache.scala 524:17]
- end
- if (memwdataEn) begin // @[L1DCache.scala 522:21]
- axiwstrbbuf <= _axiwstrbbuf_T; // @[L1DCache.scala 525:17]
- end
- if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 490:53]
- axiraddr <= {{1'd0}, alignedAddr}; // @[L1DCache.scala 500:14]
- end
- if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- axiwaddr <= _GEN_3590;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- axiwaddr <= _GEN_3590;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- axiwaddr <= _GEN_3590;
- end else if (3'h3 == fstate) begin // @[L1DCache.scala 582:18]
- axiwaddr <= _GEN_5654; // @[L1DCache.scala 613:16]
- end else begin
- axiwaddr <= _GEN_3590;
- end
- if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_valid & ~axiwaddrvalid & ~axiwdatavalid & ~axiraddrvalid & ~axirdataready) begin // @[L1DCache.scala 584:101]
- replaceIdReg <= foundId; // @[L1DCache.scala 586:22]
- end else begin
- replaceIdReg <= _GEN_3332;
- end
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- replaceIdReg <= _GEN_3332;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- replaceIdReg <= flushId; // @[L1DCache.scala 607:20]
- end else begin
- replaceIdReg <= _GEN_3332;
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(~(io_dbus_valid & io_dbus_write) | _T_3 == 32'h0)) begin
- $fatal; // @[L1DCache.scala 338:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(~(io_dbus_valid & io_dbus_write) | _T_3 == 32'h0)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:338 assert(!(io.dbus.valid && io.dbus.write) || (io.dbus.wmask & ~chkmask) === 0.U)\n"
- ); // @[L1DCache.scala 338:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_773 <= 9'h1)) begin
- $fatal; // @[L1DCache.scala 388:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_773 <= 9'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:388 assert(PopCount(matchSlot) <= 1.U)\n"); // @[L1DCache.scala 388:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_1543 <= 9'h1)) begin
- $fatal; // @[L1DCache.scala 389:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_1543 <= 9'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:389 assert(PopCount(replaceSlot) <= 1.U)\n"); // @[L1DCache.scala 389:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_1557 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_1557 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1566 & ~matchSet_1[0] & _T_1568 & _T_7 & ~(history_0_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1566 & ~matchSet_1[0] & _T_1568 & _T_7 & ~(history_0_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1566 & ~matchSet_1[1] & _T_1574 & _T_7 & ~(history_0_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1566 & ~matchSet_1[1] & _T_1574 & _T_7 & ~(history_0_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1566 & ~matchSet_1[2] & _T_1580 & _T_7 & ~(history_0_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1566 & ~matchSet_1[2] & _T_1580 & _T_7 & ~(history_0_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1566 & ~matchSet_1[3] & _T_1586 & _T_7 & ~(history_0_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1566 & ~matchSet_1[3] & _T_1586 & _T_7 & ~(history_0_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_1599 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_1599 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1608 & ~matchSet_2[0] & _T_1610 & _T_7 & ~(history_1_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1608 & ~matchSet_2[0] & _T_1610 & _T_7 & ~(history_1_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1608 & ~matchSet_2[1] & _T_1616 & _T_7 & ~(history_1_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1608 & ~matchSet_2[1] & _T_1616 & _T_7 & ~(history_1_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1608 & ~matchSet_2[2] & _T_1622 & _T_7 & ~(history_1_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1608 & ~matchSet_2[2] & _T_1622 & _T_7 & ~(history_1_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1608 & ~matchSet_2[3] & _T_1628 & _T_7 & ~(history_1_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1608 & ~matchSet_2[3] & _T_1628 & _T_7 & ~(history_1_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_1641 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_1641 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1650 & ~matchSet_3[0] & _T_1652 & _T_7 & ~(history_2_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1650 & ~matchSet_3[0] & _T_1652 & _T_7 & ~(history_2_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1650 & ~matchSet_3[1] & _T_1658 & _T_7 & ~(history_2_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1650 & ~matchSet_3[1] & _T_1658 & _T_7 & ~(history_2_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1650 & ~matchSet_3[2] & _T_1664 & _T_7 & ~(history_2_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1650 & ~matchSet_3[2] & _T_1664 & _T_7 & ~(history_2_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1650 & ~matchSet_3[3] & _T_1670 & _T_7 & ~(history_2_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1650 & ~matchSet_3[3] & _T_1670 & _T_7 & ~(history_2_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_1683 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_1683 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1692 & ~matchSet_4[0] & _T_1694 & _T_7 & ~(history_3_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1692 & ~matchSet_4[0] & _T_1694 & _T_7 & ~(history_3_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1692 & ~matchSet_4[1] & _T_1700 & _T_7 & ~(history_3_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1692 & ~matchSet_4[1] & _T_1700 & _T_7 & ~(history_3_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1692 & ~matchSet_4[2] & _T_1706 & _T_7 & ~(history_3_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1692 & ~matchSet_4[2] & _T_1706 & _T_7 & ~(history_3_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1692 & ~matchSet_4[3] & _T_1712 & _T_7 & ~(history_3_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1692 & ~matchSet_4[3] & _T_1712 & _T_7 & ~(history_3_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_1725 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_1725 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1734 & ~matchSet_5[0] & _T_1736 & _T_7 & ~(history_4_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1734 & ~matchSet_5[0] & _T_1736 & _T_7 & ~(history_4_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1734 & ~matchSet_5[1] & _T_1742 & _T_7 & ~(history_4_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1734 & ~matchSet_5[1] & _T_1742 & _T_7 & ~(history_4_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1734 & ~matchSet_5[2] & _T_1748 & _T_7 & ~(history_4_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1734 & ~matchSet_5[2] & _T_1748 & _T_7 & ~(history_4_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1734 & ~matchSet_5[3] & _T_1754 & _T_7 & ~(history_4_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1734 & ~matchSet_5[3] & _T_1754 & _T_7 & ~(history_4_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_1767 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_1767 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1776 & ~matchSet_6[0] & _T_1778 & _T_7 & ~(history_5_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1776 & ~matchSet_6[0] & _T_1778 & _T_7 & ~(history_5_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1776 & ~matchSet_6[1] & _T_1784 & _T_7 & ~(history_5_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1776 & ~matchSet_6[1] & _T_1784 & _T_7 & ~(history_5_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1776 & ~matchSet_6[2] & _T_1790 & _T_7 & ~(history_5_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1776 & ~matchSet_6[2] & _T_1790 & _T_7 & ~(history_5_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1776 & ~matchSet_6[3] & _T_1796 & _T_7 & ~(history_5_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1776 & ~matchSet_6[3] & _T_1796 & _T_7 & ~(history_5_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_1809 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_1809 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1818 & ~matchSet_7[0] & _T_1820 & _T_7 & ~(history_6_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1818 & ~matchSet_7[0] & _T_1820 & _T_7 & ~(history_6_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1818 & ~matchSet_7[1] & _T_1826 & _T_7 & ~(history_6_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1818 & ~matchSet_7[1] & _T_1826 & _T_7 & ~(history_6_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1818 & ~matchSet_7[2] & _T_1832 & _T_7 & ~(history_6_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1818 & ~matchSet_7[2] & _T_1832 & _T_7 & ~(history_6_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1818 & ~matchSet_7[3] & _T_1838 & _T_7 & ~(history_6_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1818 & ~matchSet_7[3] & _T_1838 & _T_7 & ~(history_6_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_1851 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_1851 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1860 & ~matchSet_8[0] & _T_1862 & _T_7 & ~(history_7_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1860 & ~matchSet_8[0] & _T_1862 & _T_7 & ~(history_7_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1860 & ~matchSet_8[1] & _T_1868 & _T_7 & ~(history_7_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1860 & ~matchSet_8[1] & _T_1868 & _T_7 & ~(history_7_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1860 & ~matchSet_8[2] & _T_1874 & _T_7 & ~(history_7_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1860 & ~matchSet_8[2] & _T_1874 & _T_7 & ~(history_7_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1860 & ~matchSet_8[3] & _T_1880 & _T_7 & ~(history_7_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1860 & ~matchSet_8[3] & _T_1880 & _T_7 & ~(history_7_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_1893 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_1893 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1902 & ~matchSet_9[0] & _T_1904 & _T_7 & ~(history_8_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1902 & ~matchSet_9[0] & _T_1904 & _T_7 & ~(history_8_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1902 & ~matchSet_9[1] & _T_1910 & _T_7 & ~(history_8_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1902 & ~matchSet_9[1] & _T_1910 & _T_7 & ~(history_8_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1902 & ~matchSet_9[2] & _T_1916 & _T_7 & ~(history_8_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1902 & ~matchSet_9[2] & _T_1916 & _T_7 & ~(history_8_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1902 & ~matchSet_9[3] & _T_1922 & _T_7 & ~(history_8_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1902 & ~matchSet_9[3] & _T_1922 & _T_7 & ~(history_8_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_1935 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_1935 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1944 & ~matchSet_10[0] & _T_1946 & _T_7 & ~(history_9_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1944 & ~matchSet_10[0] & _T_1946 & _T_7 & ~(history_9_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1944 & ~matchSet_10[1] & _T_1952 & _T_7 & ~(history_9_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1944 & ~matchSet_10[1] & _T_1952 & _T_7 & ~(history_9_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1944 & ~matchSet_10[2] & _T_1958 & _T_7 & ~(history_9_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1944 & ~matchSet_10[2] & _T_1958 & _T_7 & ~(history_9_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1944 & ~matchSet_10[3] & _T_1964 & _T_7 & ~(history_9_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1944 & ~matchSet_10[3] & _T_1964 & _T_7 & ~(history_9_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_1977 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_1977 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1986 & ~matchSet_11[0] & _T_1988 & _T_7 & ~(history_10_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1986 & ~matchSet_11[0] & _T_1988 & _T_7 & ~(history_10_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1986 & ~matchSet_11[1] & _T_1994 & _T_7 & ~(history_10_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1986 & ~matchSet_11[1] & _T_1994 & _T_7 & ~(history_10_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1986 & ~matchSet_11[2] & _T_2000 & _T_7 & ~(history_10_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1986 & ~matchSet_11[2] & _T_2000 & _T_7 & ~(history_10_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1986 & ~matchSet_11[3] & _T_2006 & _T_7 & ~(history_10_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1986 & ~matchSet_11[3] & _T_2006 & _T_7 & ~(history_10_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2019 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2019 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2028 & ~matchSet_12[0] & _T_2030 & _T_7 & ~(history_11_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2028 & ~matchSet_12[0] & _T_2030 & _T_7 & ~(history_11_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2028 & ~matchSet_12[1] & _T_2036 & _T_7 & ~(history_11_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2028 & ~matchSet_12[1] & _T_2036 & _T_7 & ~(history_11_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2028 & ~matchSet_12[2] & _T_2042 & _T_7 & ~(history_11_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2028 & ~matchSet_12[2] & _T_2042 & _T_7 & ~(history_11_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2028 & ~matchSet_12[3] & _T_2048 & _T_7 & ~(history_11_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2028 & ~matchSet_12[3] & _T_2048 & _T_7 & ~(history_11_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2061 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2061 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2070 & ~matchSet_13[0] & _T_2072 & _T_7 & ~(history_12_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2070 & ~matchSet_13[0] & _T_2072 & _T_7 & ~(history_12_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2070 & ~matchSet_13[1] & _T_2078 & _T_7 & ~(history_12_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2070 & ~matchSet_13[1] & _T_2078 & _T_7 & ~(history_12_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2070 & ~matchSet_13[2] & _T_2084 & _T_7 & ~(history_12_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2070 & ~matchSet_13[2] & _T_2084 & _T_7 & ~(history_12_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2070 & ~matchSet_13[3] & _T_2090 & _T_7 & ~(history_12_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2070 & ~matchSet_13[3] & _T_2090 & _T_7 & ~(history_12_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2103 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2103 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2112 & ~matchSet_14[0] & _T_2114 & _T_7 & ~(history_13_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2112 & ~matchSet_14[0] & _T_2114 & _T_7 & ~(history_13_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2112 & ~matchSet_14[1] & _T_2120 & _T_7 & ~(history_13_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2112 & ~matchSet_14[1] & _T_2120 & _T_7 & ~(history_13_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2112 & ~matchSet_14[2] & _T_2126 & _T_7 & ~(history_13_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2112 & ~matchSet_14[2] & _T_2126 & _T_7 & ~(history_13_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2112 & ~matchSet_14[3] & _T_2132 & _T_7 & ~(history_13_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2112 & ~matchSet_14[3] & _T_2132 & _T_7 & ~(history_13_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2145 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2145 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2154 & ~matchSet_15[0] & _T_2156 & _T_7 & ~(history_14_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2154 & ~matchSet_15[0] & _T_2156 & _T_7 & ~(history_14_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2154 & ~matchSet_15[1] & _T_2162 & _T_7 & ~(history_14_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2154 & ~matchSet_15[1] & _T_2162 & _T_7 & ~(history_14_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2154 & ~matchSet_15[2] & _T_2168 & _T_7 & ~(history_14_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2154 & ~matchSet_15[2] & _T_2168 & _T_7 & ~(history_14_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2154 & ~matchSet_15[3] & _T_2174 & _T_7 & ~(history_14_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2154 & ~matchSet_15[3] & _T_2174 & _T_7 & ~(history_14_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2187 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2187 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2196 & ~matchSet_16[0] & _T_2198 & _T_7 & ~(history_15_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2196 & ~matchSet_16[0] & _T_2198 & _T_7 & ~(history_15_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2196 & ~matchSet_16[1] & _T_2204 & _T_7 & ~(history_15_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2196 & ~matchSet_16[1] & _T_2204 & _T_7 & ~(history_15_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2196 & ~matchSet_16[2] & _T_2210 & _T_7 & ~(history_15_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2196 & ~matchSet_16[2] & _T_2210 & _T_7 & ~(history_15_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2196 & ~matchSet_16[3] & _T_2216 & _T_7 & ~(history_15_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2196 & ~matchSet_16[3] & _T_2216 & _T_7 & ~(history_15_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2229 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2229 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2238 & ~matchSet_17[0] & _T_2240 & _T_7 & ~(history_16_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2238 & ~matchSet_17[0] & _T_2240 & _T_7 & ~(history_16_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2238 & ~matchSet_17[1] & _T_2246 & _T_7 & ~(history_16_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2238 & ~matchSet_17[1] & _T_2246 & _T_7 & ~(history_16_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2238 & ~matchSet_17[2] & _T_2252 & _T_7 & ~(history_16_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2238 & ~matchSet_17[2] & _T_2252 & _T_7 & ~(history_16_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2238 & ~matchSet_17[3] & _T_2258 & _T_7 & ~(history_16_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2238 & ~matchSet_17[3] & _T_2258 & _T_7 & ~(history_16_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2271 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2271 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2280 & ~matchSet_18[0] & _T_2282 & _T_7 & ~(history_17_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2280 & ~matchSet_18[0] & _T_2282 & _T_7 & ~(history_17_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2280 & ~matchSet_18[1] & _T_2288 & _T_7 & ~(history_17_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2280 & ~matchSet_18[1] & _T_2288 & _T_7 & ~(history_17_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2280 & ~matchSet_18[2] & _T_2294 & _T_7 & ~(history_17_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2280 & ~matchSet_18[2] & _T_2294 & _T_7 & ~(history_17_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2280 & ~matchSet_18[3] & _T_2300 & _T_7 & ~(history_17_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2280 & ~matchSet_18[3] & _T_2300 & _T_7 & ~(history_17_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2313 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2313 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2322 & ~matchSet_19[0] & _T_2324 & _T_7 & ~(history_18_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2322 & ~matchSet_19[0] & _T_2324 & _T_7 & ~(history_18_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2322 & ~matchSet_19[1] & _T_2330 & _T_7 & ~(history_18_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2322 & ~matchSet_19[1] & _T_2330 & _T_7 & ~(history_18_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2322 & ~matchSet_19[2] & _T_2336 & _T_7 & ~(history_18_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2322 & ~matchSet_19[2] & _T_2336 & _T_7 & ~(history_18_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2322 & ~matchSet_19[3] & _T_2342 & _T_7 & ~(history_18_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2322 & ~matchSet_19[3] & _T_2342 & _T_7 & ~(history_18_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2355 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2355 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2364 & ~matchSet_20[0] & _T_2366 & _T_7 & ~(history_19_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2364 & ~matchSet_20[0] & _T_2366 & _T_7 & ~(history_19_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2364 & ~matchSet_20[1] & _T_2372 & _T_7 & ~(history_19_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2364 & ~matchSet_20[1] & _T_2372 & _T_7 & ~(history_19_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2364 & ~matchSet_20[2] & _T_2378 & _T_7 & ~(history_19_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2364 & ~matchSet_20[2] & _T_2378 & _T_7 & ~(history_19_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2364 & ~matchSet_20[3] & _T_2384 & _T_7 & ~(history_19_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2364 & ~matchSet_20[3] & _T_2384 & _T_7 & ~(history_19_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2397 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2397 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2406 & ~matchSet_21[0] & _T_2408 & _T_7 & ~(history_20_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2406 & ~matchSet_21[0] & _T_2408 & _T_7 & ~(history_20_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2406 & ~matchSet_21[1] & _T_2414 & _T_7 & ~(history_20_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2406 & ~matchSet_21[1] & _T_2414 & _T_7 & ~(history_20_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2406 & ~matchSet_21[2] & _T_2420 & _T_7 & ~(history_20_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2406 & ~matchSet_21[2] & _T_2420 & _T_7 & ~(history_20_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2406 & ~matchSet_21[3] & _T_2426 & _T_7 & ~(history_20_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2406 & ~matchSet_21[3] & _T_2426 & _T_7 & ~(history_20_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2439 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2439 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2448 & ~matchSet_22[0] & _T_2450 & _T_7 & ~(history_21_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2448 & ~matchSet_22[0] & _T_2450 & _T_7 & ~(history_21_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2448 & ~matchSet_22[1] & _T_2456 & _T_7 & ~(history_21_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2448 & ~matchSet_22[1] & _T_2456 & _T_7 & ~(history_21_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2448 & ~matchSet_22[2] & _T_2462 & _T_7 & ~(history_21_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2448 & ~matchSet_22[2] & _T_2462 & _T_7 & ~(history_21_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2448 & ~matchSet_22[3] & _T_2468 & _T_7 & ~(history_21_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2448 & ~matchSet_22[3] & _T_2468 & _T_7 & ~(history_21_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2481 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2481 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2490 & ~matchSet_23[0] & _T_2492 & _T_7 & ~(history_22_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2490 & ~matchSet_23[0] & _T_2492 & _T_7 & ~(history_22_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2490 & ~matchSet_23[1] & _T_2498 & _T_7 & ~(history_22_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2490 & ~matchSet_23[1] & _T_2498 & _T_7 & ~(history_22_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2490 & ~matchSet_23[2] & _T_2504 & _T_7 & ~(history_22_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2490 & ~matchSet_23[2] & _T_2504 & _T_7 & ~(history_22_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2490 & ~matchSet_23[3] & _T_2510 & _T_7 & ~(history_22_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2490 & ~matchSet_23[3] & _T_2510 & _T_7 & ~(history_22_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2523 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2523 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2532 & ~matchSet_24[0] & _T_2534 & _T_7 & ~(history_23_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2532 & ~matchSet_24[0] & _T_2534 & _T_7 & ~(history_23_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2532 & ~matchSet_24[1] & _T_2540 & _T_7 & ~(history_23_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2532 & ~matchSet_24[1] & _T_2540 & _T_7 & ~(history_23_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2532 & ~matchSet_24[2] & _T_2546 & _T_7 & ~(history_23_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2532 & ~matchSet_24[2] & _T_2546 & _T_7 & ~(history_23_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2532 & ~matchSet_24[3] & _T_2552 & _T_7 & ~(history_23_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2532 & ~matchSet_24[3] & _T_2552 & _T_7 & ~(history_23_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2565 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2565 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2574 & ~matchSet_25[0] & _T_2576 & _T_7 & ~(history_24_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2574 & ~matchSet_25[0] & _T_2576 & _T_7 & ~(history_24_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2574 & ~matchSet_25[1] & _T_2582 & _T_7 & ~(history_24_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2574 & ~matchSet_25[1] & _T_2582 & _T_7 & ~(history_24_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2574 & ~matchSet_25[2] & _T_2588 & _T_7 & ~(history_24_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2574 & ~matchSet_25[2] & _T_2588 & _T_7 & ~(history_24_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2574 & ~matchSet_25[3] & _T_2594 & _T_7 & ~(history_24_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2574 & ~matchSet_25[3] & _T_2594 & _T_7 & ~(history_24_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2607 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2607 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2616 & ~matchSet_26[0] & _T_2618 & _T_7 & ~(history_25_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2616 & ~matchSet_26[0] & _T_2618 & _T_7 & ~(history_25_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2616 & ~matchSet_26[1] & _T_2624 & _T_7 & ~(history_25_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2616 & ~matchSet_26[1] & _T_2624 & _T_7 & ~(history_25_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2616 & ~matchSet_26[2] & _T_2630 & _T_7 & ~(history_25_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2616 & ~matchSet_26[2] & _T_2630 & _T_7 & ~(history_25_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2616 & ~matchSet_26[3] & _T_2636 & _T_7 & ~(history_25_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2616 & ~matchSet_26[3] & _T_2636 & _T_7 & ~(history_25_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2649 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2649 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2658 & ~matchSet_27[0] & _T_2660 & _T_7 & ~(history_26_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2658 & ~matchSet_27[0] & _T_2660 & _T_7 & ~(history_26_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2658 & ~matchSet_27[1] & _T_2666 & _T_7 & ~(history_26_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2658 & ~matchSet_27[1] & _T_2666 & _T_7 & ~(history_26_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2658 & ~matchSet_27[2] & _T_2672 & _T_7 & ~(history_26_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2658 & ~matchSet_27[2] & _T_2672 & _T_7 & ~(history_26_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2658 & ~matchSet_27[3] & _T_2678 & _T_7 & ~(history_26_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2658 & ~matchSet_27[3] & _T_2678 & _T_7 & ~(history_26_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2691 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2691 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2700 & ~matchSet_28[0] & _T_2702 & _T_7 & ~(history_27_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2700 & ~matchSet_28[0] & _T_2702 & _T_7 & ~(history_27_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2700 & ~matchSet_28[1] & _T_2708 & _T_7 & ~(history_27_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2700 & ~matchSet_28[1] & _T_2708 & _T_7 & ~(history_27_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2700 & ~matchSet_28[2] & _T_2714 & _T_7 & ~(history_27_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2700 & ~matchSet_28[2] & _T_2714 & _T_7 & ~(history_27_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2700 & ~matchSet_28[3] & _T_2720 & _T_7 & ~(history_27_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2700 & ~matchSet_28[3] & _T_2720 & _T_7 & ~(history_27_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2733 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2733 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2742 & ~matchSet_29[0] & _T_2744 & _T_7 & ~(history_28_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2742 & ~matchSet_29[0] & _T_2744 & _T_7 & ~(history_28_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2742 & ~matchSet_29[1] & _T_2750 & _T_7 & ~(history_28_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2742 & ~matchSet_29[1] & _T_2750 & _T_7 & ~(history_28_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2742 & ~matchSet_29[2] & _T_2756 & _T_7 & ~(history_28_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2742 & ~matchSet_29[2] & _T_2756 & _T_7 & ~(history_28_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2742 & ~matchSet_29[3] & _T_2762 & _T_7 & ~(history_28_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2742 & ~matchSet_29[3] & _T_2762 & _T_7 & ~(history_28_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2775 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2775 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2784 & ~matchSet_30[0] & _T_2786 & _T_7 & ~(history_29_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2784 & ~matchSet_30[0] & _T_2786 & _T_7 & ~(history_29_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2784 & ~matchSet_30[1] & _T_2792 & _T_7 & ~(history_29_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2784 & ~matchSet_30[1] & _T_2792 & _T_7 & ~(history_29_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2784 & ~matchSet_30[2] & _T_2798 & _T_7 & ~(history_29_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2784 & ~matchSet_30[2] & _T_2798 & _T_7 & ~(history_29_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2784 & ~matchSet_30[3] & _T_2804 & _T_7 & ~(history_29_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2784 & ~matchSet_30[3] & _T_2804 & _T_7 & ~(history_29_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2817 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2817 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2826 & ~matchSet_31[0] & _T_2828 & _T_7 & ~(history_30_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2826 & ~matchSet_31[0] & _T_2828 & _T_7 & ~(history_30_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2826 & ~matchSet_31[1] & _T_2834 & _T_7 & ~(history_30_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2826 & ~matchSet_31[1] & _T_2834 & _T_7 & ~(history_30_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2826 & ~matchSet_31[2] & _T_2840 & _T_7 & ~(history_30_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2826 & ~matchSet_31[2] & _T_2840 & _T_7 & ~(history_30_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2826 & ~matchSet_31[3] & _T_2846 & _T_7 & ~(history_30_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2826 & ~matchSet_31[3] & _T_2846 & _T_7 & ~(history_30_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2859 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2859 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2868 & ~matchSet_32[0] & _T_2870 & _T_7 & ~(history_31_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2868 & ~matchSet_32[0] & _T_2870 & _T_7 & ~(history_31_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2868 & ~matchSet_32[1] & _T_2876 & _T_7 & ~(history_31_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2868 & ~matchSet_32[1] & _T_2876 & _T_7 & ~(history_31_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2868 & ~matchSet_32[2] & _T_2882 & _T_7 & ~(history_31_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2868 & ~matchSet_32[2] & _T_2882 & _T_7 & ~(history_31_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2868 & ~matchSet_32[3] & _T_2888 & _T_7 & ~(history_31_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2868 & ~matchSet_32[3] & _T_2888 & _T_7 & ~(history_31_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2901 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2901 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2910 & ~matchSet_33[0] & _T_2912 & _T_7 & ~(history_32_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2910 & ~matchSet_33[0] & _T_2912 & _T_7 & ~(history_32_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2910 & ~matchSet_33[1] & _T_2918 & _T_7 & ~(history_32_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2910 & ~matchSet_33[1] & _T_2918 & _T_7 & ~(history_32_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2910 & ~matchSet_33[2] & _T_2924 & _T_7 & ~(history_32_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2910 & ~matchSet_33[2] & _T_2924 & _T_7 & ~(history_32_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2910 & ~matchSet_33[3] & _T_2930 & _T_7 & ~(history_32_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2910 & ~matchSet_33[3] & _T_2930 & _T_7 & ~(history_32_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2943 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2943 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2952 & ~matchSet_34[0] & _T_2954 & _T_7 & ~(history_33_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2952 & ~matchSet_34[0] & _T_2954 & _T_7 & ~(history_33_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2952 & ~matchSet_34[1] & _T_2960 & _T_7 & ~(history_33_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2952 & ~matchSet_34[1] & _T_2960 & _T_7 & ~(history_33_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2952 & ~matchSet_34[2] & _T_2966 & _T_7 & ~(history_33_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2952 & ~matchSet_34[2] & _T_2966 & _T_7 & ~(history_33_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2952 & ~matchSet_34[3] & _T_2972 & _T_7 & ~(history_33_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2952 & ~matchSet_34[3] & _T_2972 & _T_7 & ~(history_33_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_2985 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_2985 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2994 & ~matchSet_35[0] & _T_2996 & _T_7 & ~(history_34_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2994 & ~matchSet_35[0] & _T_2996 & _T_7 & ~(history_34_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2994 & ~matchSet_35[1] & _T_3002 & _T_7 & ~(history_34_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2994 & ~matchSet_35[1] & _T_3002 & _T_7 & ~(history_34_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2994 & ~matchSet_35[2] & _T_3008 & _T_7 & ~(history_34_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2994 & ~matchSet_35[2] & _T_3008 & _T_7 & ~(history_34_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2994 & ~matchSet_35[3] & _T_3014 & _T_7 & ~(history_34_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2994 & ~matchSet_35[3] & _T_3014 & _T_7 & ~(history_34_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3027 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3027 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3036 & ~matchSet_36[0] & _T_3038 & _T_7 & ~(history_35_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3036 & ~matchSet_36[0] & _T_3038 & _T_7 & ~(history_35_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3036 & ~matchSet_36[1] & _T_3044 & _T_7 & ~(history_35_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3036 & ~matchSet_36[1] & _T_3044 & _T_7 & ~(history_35_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3036 & ~matchSet_36[2] & _T_3050 & _T_7 & ~(history_35_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3036 & ~matchSet_36[2] & _T_3050 & _T_7 & ~(history_35_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3036 & ~matchSet_36[3] & _T_3056 & _T_7 & ~(history_35_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3036 & ~matchSet_36[3] & _T_3056 & _T_7 & ~(history_35_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3069 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3069 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3078 & ~matchSet_37[0] & _T_3080 & _T_7 & ~(history_36_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3078 & ~matchSet_37[0] & _T_3080 & _T_7 & ~(history_36_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3078 & ~matchSet_37[1] & _T_3086 & _T_7 & ~(history_36_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3078 & ~matchSet_37[1] & _T_3086 & _T_7 & ~(history_36_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3078 & ~matchSet_37[2] & _T_3092 & _T_7 & ~(history_36_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3078 & ~matchSet_37[2] & _T_3092 & _T_7 & ~(history_36_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3078 & ~matchSet_37[3] & _T_3098 & _T_7 & ~(history_36_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3078 & ~matchSet_37[3] & _T_3098 & _T_7 & ~(history_36_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3111 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3111 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3120 & ~matchSet_38[0] & _T_3122 & _T_7 & ~(history_37_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3120 & ~matchSet_38[0] & _T_3122 & _T_7 & ~(history_37_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3120 & ~matchSet_38[1] & _T_3128 & _T_7 & ~(history_37_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3120 & ~matchSet_38[1] & _T_3128 & _T_7 & ~(history_37_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3120 & ~matchSet_38[2] & _T_3134 & _T_7 & ~(history_37_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3120 & ~matchSet_38[2] & _T_3134 & _T_7 & ~(history_37_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3120 & ~matchSet_38[3] & _T_3140 & _T_7 & ~(history_37_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3120 & ~matchSet_38[3] & _T_3140 & _T_7 & ~(history_37_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3153 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3153 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3162 & ~matchSet_39[0] & _T_3164 & _T_7 & ~(history_38_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3162 & ~matchSet_39[0] & _T_3164 & _T_7 & ~(history_38_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3162 & ~matchSet_39[1] & _T_3170 & _T_7 & ~(history_38_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3162 & ~matchSet_39[1] & _T_3170 & _T_7 & ~(history_38_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3162 & ~matchSet_39[2] & _T_3176 & _T_7 & ~(history_38_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3162 & ~matchSet_39[2] & _T_3176 & _T_7 & ~(history_38_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3162 & ~matchSet_39[3] & _T_3182 & _T_7 & ~(history_38_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3162 & ~matchSet_39[3] & _T_3182 & _T_7 & ~(history_38_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3195 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3195 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3204 & ~matchSet_40[0] & _T_3206 & _T_7 & ~(history_39_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3204 & ~matchSet_40[0] & _T_3206 & _T_7 & ~(history_39_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3204 & ~matchSet_40[1] & _T_3212 & _T_7 & ~(history_39_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3204 & ~matchSet_40[1] & _T_3212 & _T_7 & ~(history_39_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3204 & ~matchSet_40[2] & _T_3218 & _T_7 & ~(history_39_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3204 & ~matchSet_40[2] & _T_3218 & _T_7 & ~(history_39_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3204 & ~matchSet_40[3] & _T_3224 & _T_7 & ~(history_39_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3204 & ~matchSet_40[3] & _T_3224 & _T_7 & ~(history_39_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3237 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3237 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3246 & ~matchSet_41[0] & _T_3248 & _T_7 & ~(history_40_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3246 & ~matchSet_41[0] & _T_3248 & _T_7 & ~(history_40_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3246 & ~matchSet_41[1] & _T_3254 & _T_7 & ~(history_40_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3246 & ~matchSet_41[1] & _T_3254 & _T_7 & ~(history_40_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3246 & ~matchSet_41[2] & _T_3260 & _T_7 & ~(history_40_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3246 & ~matchSet_41[2] & _T_3260 & _T_7 & ~(history_40_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3246 & ~matchSet_41[3] & _T_3266 & _T_7 & ~(history_40_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3246 & ~matchSet_41[3] & _T_3266 & _T_7 & ~(history_40_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3279 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3279 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3288 & ~matchSet_42[0] & _T_3290 & _T_7 & ~(history_41_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3288 & ~matchSet_42[0] & _T_3290 & _T_7 & ~(history_41_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3288 & ~matchSet_42[1] & _T_3296 & _T_7 & ~(history_41_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3288 & ~matchSet_42[1] & _T_3296 & _T_7 & ~(history_41_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3288 & ~matchSet_42[2] & _T_3302 & _T_7 & ~(history_41_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3288 & ~matchSet_42[2] & _T_3302 & _T_7 & ~(history_41_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3288 & ~matchSet_42[3] & _T_3308 & _T_7 & ~(history_41_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3288 & ~matchSet_42[3] & _T_3308 & _T_7 & ~(history_41_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3321 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3321 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3330 & ~matchSet_43[0] & _T_3332 & _T_7 & ~(history_42_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3330 & ~matchSet_43[0] & _T_3332 & _T_7 & ~(history_42_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3330 & ~matchSet_43[1] & _T_3338 & _T_7 & ~(history_42_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3330 & ~matchSet_43[1] & _T_3338 & _T_7 & ~(history_42_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3330 & ~matchSet_43[2] & _T_3344 & _T_7 & ~(history_42_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3330 & ~matchSet_43[2] & _T_3344 & _T_7 & ~(history_42_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3330 & ~matchSet_43[3] & _T_3350 & _T_7 & ~(history_42_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3330 & ~matchSet_43[3] & _T_3350 & _T_7 & ~(history_42_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3363 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3363 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3372 & ~matchSet_44[0] & _T_3374 & _T_7 & ~(history_43_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3372 & ~matchSet_44[0] & _T_3374 & _T_7 & ~(history_43_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3372 & ~matchSet_44[1] & _T_3380 & _T_7 & ~(history_43_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3372 & ~matchSet_44[1] & _T_3380 & _T_7 & ~(history_43_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3372 & ~matchSet_44[2] & _T_3386 & _T_7 & ~(history_43_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3372 & ~matchSet_44[2] & _T_3386 & _T_7 & ~(history_43_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3372 & ~matchSet_44[3] & _T_3392 & _T_7 & ~(history_43_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3372 & ~matchSet_44[3] & _T_3392 & _T_7 & ~(history_43_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3405 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3405 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3414 & ~matchSet_45[0] & _T_3416 & _T_7 & ~(history_44_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3414 & ~matchSet_45[0] & _T_3416 & _T_7 & ~(history_44_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3414 & ~matchSet_45[1] & _T_3422 & _T_7 & ~(history_44_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3414 & ~matchSet_45[1] & _T_3422 & _T_7 & ~(history_44_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3414 & ~matchSet_45[2] & _T_3428 & _T_7 & ~(history_44_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3414 & ~matchSet_45[2] & _T_3428 & _T_7 & ~(history_44_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3414 & ~matchSet_45[3] & _T_3434 & _T_7 & ~(history_44_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3414 & ~matchSet_45[3] & _T_3434 & _T_7 & ~(history_44_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3447 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3447 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3456 & ~matchSet_46[0] & _T_3458 & _T_7 & ~(history_45_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3456 & ~matchSet_46[0] & _T_3458 & _T_7 & ~(history_45_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3456 & ~matchSet_46[1] & _T_3464 & _T_7 & ~(history_45_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3456 & ~matchSet_46[1] & _T_3464 & _T_7 & ~(history_45_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3456 & ~matchSet_46[2] & _T_3470 & _T_7 & ~(history_45_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3456 & ~matchSet_46[2] & _T_3470 & _T_7 & ~(history_45_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3456 & ~matchSet_46[3] & _T_3476 & _T_7 & ~(history_45_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3456 & ~matchSet_46[3] & _T_3476 & _T_7 & ~(history_45_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3489 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3489 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3498 & ~matchSet_47[0] & _T_3500 & _T_7 & ~(history_46_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3498 & ~matchSet_47[0] & _T_3500 & _T_7 & ~(history_46_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3498 & ~matchSet_47[1] & _T_3506 & _T_7 & ~(history_46_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3498 & ~matchSet_47[1] & _T_3506 & _T_7 & ~(history_46_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3498 & ~matchSet_47[2] & _T_3512 & _T_7 & ~(history_46_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3498 & ~matchSet_47[2] & _T_3512 & _T_7 & ~(history_46_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3498 & ~matchSet_47[3] & _T_3518 & _T_7 & ~(history_46_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3498 & ~matchSet_47[3] & _T_3518 & _T_7 & ~(history_46_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3531 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3531 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3540 & ~matchSet_48[0] & _T_3542 & _T_7 & ~(history_47_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3540 & ~matchSet_48[0] & _T_3542 & _T_7 & ~(history_47_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3540 & ~matchSet_48[1] & _T_3548 & _T_7 & ~(history_47_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3540 & ~matchSet_48[1] & _T_3548 & _T_7 & ~(history_47_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3540 & ~matchSet_48[2] & _T_3554 & _T_7 & ~(history_47_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3540 & ~matchSet_48[2] & _T_3554 & _T_7 & ~(history_47_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3540 & ~matchSet_48[3] & _T_3560 & _T_7 & ~(history_47_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3540 & ~matchSet_48[3] & _T_3560 & _T_7 & ~(history_47_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3573 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3573 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3582 & ~matchSet_49[0] & _T_3584 & _T_7 & ~(history_48_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3582 & ~matchSet_49[0] & _T_3584 & _T_7 & ~(history_48_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3582 & ~matchSet_49[1] & _T_3590 & _T_7 & ~(history_48_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3582 & ~matchSet_49[1] & _T_3590 & _T_7 & ~(history_48_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3582 & ~matchSet_49[2] & _T_3596 & _T_7 & ~(history_48_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3582 & ~matchSet_49[2] & _T_3596 & _T_7 & ~(history_48_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3582 & ~matchSet_49[3] & _T_3602 & _T_7 & ~(history_48_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3582 & ~matchSet_49[3] & _T_3602 & _T_7 & ~(history_48_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3615 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3615 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3624 & ~matchSet_50[0] & _T_3626 & _T_7 & ~(history_49_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3624 & ~matchSet_50[0] & _T_3626 & _T_7 & ~(history_49_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3624 & ~matchSet_50[1] & _T_3632 & _T_7 & ~(history_49_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3624 & ~matchSet_50[1] & _T_3632 & _T_7 & ~(history_49_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3624 & ~matchSet_50[2] & _T_3638 & _T_7 & ~(history_49_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3624 & ~matchSet_50[2] & _T_3638 & _T_7 & ~(history_49_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3624 & ~matchSet_50[3] & _T_3644 & _T_7 & ~(history_49_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3624 & ~matchSet_50[3] & _T_3644 & _T_7 & ~(history_49_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3657 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3657 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3666 & ~matchSet_51[0] & _T_3668 & _T_7 & ~(history_50_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3666 & ~matchSet_51[0] & _T_3668 & _T_7 & ~(history_50_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3666 & ~matchSet_51[1] & _T_3674 & _T_7 & ~(history_50_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3666 & ~matchSet_51[1] & _T_3674 & _T_7 & ~(history_50_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3666 & ~matchSet_51[2] & _T_3680 & _T_7 & ~(history_50_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3666 & ~matchSet_51[2] & _T_3680 & _T_7 & ~(history_50_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3666 & ~matchSet_51[3] & _T_3686 & _T_7 & ~(history_50_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3666 & ~matchSet_51[3] & _T_3686 & _T_7 & ~(history_50_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3699 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3699 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3708 & ~matchSet_52[0] & _T_3710 & _T_7 & ~(history_51_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3708 & ~matchSet_52[0] & _T_3710 & _T_7 & ~(history_51_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3708 & ~matchSet_52[1] & _T_3716 & _T_7 & ~(history_51_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3708 & ~matchSet_52[1] & _T_3716 & _T_7 & ~(history_51_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3708 & ~matchSet_52[2] & _T_3722 & _T_7 & ~(history_51_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3708 & ~matchSet_52[2] & _T_3722 & _T_7 & ~(history_51_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3708 & ~matchSet_52[3] & _T_3728 & _T_7 & ~(history_51_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3708 & ~matchSet_52[3] & _T_3728 & _T_7 & ~(history_51_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3741 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3741 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3750 & ~matchSet_53[0] & _T_3752 & _T_7 & ~(history_52_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3750 & ~matchSet_53[0] & _T_3752 & _T_7 & ~(history_52_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3750 & ~matchSet_53[1] & _T_3758 & _T_7 & ~(history_52_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3750 & ~matchSet_53[1] & _T_3758 & _T_7 & ~(history_52_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3750 & ~matchSet_53[2] & _T_3764 & _T_7 & ~(history_52_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3750 & ~matchSet_53[2] & _T_3764 & _T_7 & ~(history_52_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3750 & ~matchSet_53[3] & _T_3770 & _T_7 & ~(history_52_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3750 & ~matchSet_53[3] & _T_3770 & _T_7 & ~(history_52_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3783 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3783 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3792 & ~matchSet_54[0] & _T_3794 & _T_7 & ~(history_53_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3792 & ~matchSet_54[0] & _T_3794 & _T_7 & ~(history_53_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3792 & ~matchSet_54[1] & _T_3800 & _T_7 & ~(history_53_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3792 & ~matchSet_54[1] & _T_3800 & _T_7 & ~(history_53_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3792 & ~matchSet_54[2] & _T_3806 & _T_7 & ~(history_53_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3792 & ~matchSet_54[2] & _T_3806 & _T_7 & ~(history_53_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3792 & ~matchSet_54[3] & _T_3812 & _T_7 & ~(history_53_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3792 & ~matchSet_54[3] & _T_3812 & _T_7 & ~(history_53_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3825 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3825 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3834 & ~matchSet_55[0] & _T_3836 & _T_7 & ~(history_54_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3834 & ~matchSet_55[0] & _T_3836 & _T_7 & ~(history_54_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3834 & ~matchSet_55[1] & _T_3842 & _T_7 & ~(history_54_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3834 & ~matchSet_55[1] & _T_3842 & _T_7 & ~(history_54_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3834 & ~matchSet_55[2] & _T_3848 & _T_7 & ~(history_54_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3834 & ~matchSet_55[2] & _T_3848 & _T_7 & ~(history_54_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3834 & ~matchSet_55[3] & _T_3854 & _T_7 & ~(history_54_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3834 & ~matchSet_55[3] & _T_3854 & _T_7 & ~(history_54_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3867 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3867 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3876 & ~matchSet_56[0] & _T_3878 & _T_7 & ~(history_55_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3876 & ~matchSet_56[0] & _T_3878 & _T_7 & ~(history_55_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3876 & ~matchSet_56[1] & _T_3884 & _T_7 & ~(history_55_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3876 & ~matchSet_56[1] & _T_3884 & _T_7 & ~(history_55_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3876 & ~matchSet_56[2] & _T_3890 & _T_7 & ~(history_55_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3876 & ~matchSet_56[2] & _T_3890 & _T_7 & ~(history_55_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3876 & ~matchSet_56[3] & _T_3896 & _T_7 & ~(history_55_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3876 & ~matchSet_56[3] & _T_3896 & _T_7 & ~(history_55_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3909 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3909 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3918 & ~matchSet_57[0] & _T_3920 & _T_7 & ~(history_56_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3918 & ~matchSet_57[0] & _T_3920 & _T_7 & ~(history_56_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3918 & ~matchSet_57[1] & _T_3926 & _T_7 & ~(history_56_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3918 & ~matchSet_57[1] & _T_3926 & _T_7 & ~(history_56_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3918 & ~matchSet_57[2] & _T_3932 & _T_7 & ~(history_56_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3918 & ~matchSet_57[2] & _T_3932 & _T_7 & ~(history_56_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3918 & ~matchSet_57[3] & _T_3938 & _T_7 & ~(history_56_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3918 & ~matchSet_57[3] & _T_3938 & _T_7 & ~(history_56_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3951 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3951 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3960 & ~matchSet_58[0] & _T_3962 & _T_7 & ~(history_57_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3960 & ~matchSet_58[0] & _T_3962 & _T_7 & ~(history_57_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3960 & ~matchSet_58[1] & _T_3968 & _T_7 & ~(history_57_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3960 & ~matchSet_58[1] & _T_3968 & _T_7 & ~(history_57_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3960 & ~matchSet_58[2] & _T_3974 & _T_7 & ~(history_57_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3960 & ~matchSet_58[2] & _T_3974 & _T_7 & ~(history_57_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3960 & ~matchSet_58[3] & _T_3980 & _T_7 & ~(history_57_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3960 & ~matchSet_58[3] & _T_3980 & _T_7 & ~(history_57_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_3993 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_3993 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4002 & ~matchSet_59[0] & _T_4004 & _T_7 & ~(history_58_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4002 & ~matchSet_59[0] & _T_4004 & _T_7 & ~(history_58_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4002 & ~matchSet_59[1] & _T_4010 & _T_7 & ~(history_58_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4002 & ~matchSet_59[1] & _T_4010 & _T_7 & ~(history_58_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4002 & ~matchSet_59[2] & _T_4016 & _T_7 & ~(history_58_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4002 & ~matchSet_59[2] & _T_4016 & _T_7 & ~(history_58_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4002 & ~matchSet_59[3] & _T_4022 & _T_7 & ~(history_58_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4002 & ~matchSet_59[3] & _T_4022 & _T_7 & ~(history_58_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_4035 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_4035 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4044 & ~matchSet_60[0] & _T_4046 & _T_7 & ~(history_59_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4044 & ~matchSet_60[0] & _T_4046 & _T_7 & ~(history_59_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4044 & ~matchSet_60[1] & _T_4052 & _T_7 & ~(history_59_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4044 & ~matchSet_60[1] & _T_4052 & _T_7 & ~(history_59_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4044 & ~matchSet_60[2] & _T_4058 & _T_7 & ~(history_59_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4044 & ~matchSet_60[2] & _T_4058 & _T_7 & ~(history_59_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4044 & ~matchSet_60[3] & _T_4064 & _T_7 & ~(history_59_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4044 & ~matchSet_60[3] & _T_4064 & _T_7 & ~(history_59_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_4077 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_4077 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4086 & ~matchSet_61[0] & _T_4088 & _T_7 & ~(history_60_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4086 & ~matchSet_61[0] & _T_4088 & _T_7 & ~(history_60_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4086 & ~matchSet_61[1] & _T_4094 & _T_7 & ~(history_60_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4086 & ~matchSet_61[1] & _T_4094 & _T_7 & ~(history_60_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4086 & ~matchSet_61[2] & _T_4100 & _T_7 & ~(history_60_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4086 & ~matchSet_61[2] & _T_4100 & _T_7 & ~(history_60_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4086 & ~matchSet_61[3] & _T_4106 & _T_7 & ~(history_60_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4086 & ~matchSet_61[3] & _T_4106 & _T_7 & ~(history_60_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_4119 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_4119 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4128 & ~matchSet_62[0] & _T_4130 & _T_7 & ~(history_61_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4128 & ~matchSet_62[0] & _T_4130 & _T_7 & ~(history_61_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4128 & ~matchSet_62[1] & _T_4136 & _T_7 & ~(history_61_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4128 & ~matchSet_62[1] & _T_4136 & _T_7 & ~(history_61_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4128 & ~matchSet_62[2] & _T_4142 & _T_7 & ~(history_61_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4128 & ~matchSet_62[2] & _T_4142 & _T_7 & ~(history_61_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4128 & ~matchSet_62[3] & _T_4148 & _T_7 & ~(history_61_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4128 & ~matchSet_62[3] & _T_4148 & _T_7 & ~(history_61_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_4161 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_4161 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4170 & ~matchSet_63[0] & _T_4172 & _T_7 & ~(history_62_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4170 & ~matchSet_63[0] & _T_4172 & _T_7 & ~(history_62_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4170 & ~matchSet_63[1] & _T_4178 & _T_7 & ~(history_62_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4170 & ~matchSet_63[1] & _T_4178 & _T_7 & ~(history_62_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4170 & ~matchSet_63[2] & _T_4184 & _T_7 & ~(history_62_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4170 & ~matchSet_63[2] & _T_4184 & _T_7 & ~(history_62_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4170 & ~matchSet_63[3] & _T_4190 & _T_7 & ~(history_62_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4170 & ~matchSet_63[3] & _T_4190 & _T_7 & ~(history_62_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_4203 <= 3'h1)) begin
- $fatal; // @[L1DCache.scala 410:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_4203 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:410 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1DCache.scala 410:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4212 & ~matchSet_64[0] & _T_4214 & _T_7 & ~(history_63_0 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4212 & ~matchSet_64[0] & _T_4214 & _T_7 & ~(history_63_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4212 & ~matchSet_64[1] & _T_4220 & _T_7 & ~(history_63_1 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4212 & ~matchSet_64[1] & _T_4220 & _T_7 & ~(history_63_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4212 & ~matchSet_64[2] & _T_4226 & _T_7 & ~(history_63_2 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4212 & ~matchSet_64[2] & _T_4226 & _T_7 & ~(history_63_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4212 & ~matchSet_64[3] & _T_4232 & _T_7 & ~(history_63_3 > 2'h0)) begin
- $fatal; // @[L1DCache.scala 426:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4212 & ~matchSet_64[3] & _T_4232 & _T_7 & ~(history_63_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:426 assert(history(i)(j) > 0.U)\n"); // @[L1DCache.scala 426:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(ractive & fstate != 3'h0))) begin
- $fatal; // @[L1DCache.scala 471:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(ractive & fstate != 3'h0))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:471 assert(!(ractive && fstate =/= FlushState.sNone))\n"); // @[L1DCache.scala 471:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4247 & _T_7 & ~(~(_GEN_1535 & ~_GEN_1791))) begin
- $fatal; // @[L1DCache.scala 493:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4247 & _T_7 & ~(~(_GEN_1535 & ~_GEN_1791))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:493 assert(!(dirty(replaceId) && !valid(replaceId)))\n"); // @[L1DCache.scala 493:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(io_axi_read_data_valid & ~io_axi_read_data_ready))) begin
- $fatal; // @[L1DCache.scala 546:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(io_axi_read_data_valid & ~io_axi_read_data_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:546 assert(!(io.axi.read.data.valid && !io.axi.read.data.ready))\n"
- ); // @[L1DCache.scala 546:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(io_axi_read_addr_valid & ~ractive))) begin
- $fatal; // @[L1DCache.scala 558:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(io_axi_read_addr_valid & ~ractive))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:558 assert(!(io.axi.read.addr.valid && !ractive))\n"); // @[L1DCache.scala 558:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(io_axi_read_data_ready & _T_4267))) begin
- $fatal; // @[L1DCache.scala 559:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(io_axi_read_data_ready & _T_4267))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:559 assert(!(io.axi.read.data.ready && !ractive))\n"); // @[L1DCache.scala 559:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(io_axi_write_addr_valid & ~wactive & fstate == 3'h0))) begin
- $fatal; // @[L1DCache.scala 560:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(io_axi_write_addr_valid & ~wactive & fstate == 3'h0))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:560 assert(!(io.axi.write.addr.valid && !wactive && fstate === FlushState.sNone))\n"
- ); // @[L1DCache.scala 560:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_0 & ~dirty_0))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_0 & ~dirty_0))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_1 & ~dirty_1))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_1 & ~dirty_1))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_2 & ~dirty_2))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_2 & ~dirty_2))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_3 & ~dirty_3))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_3 & ~dirty_3))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_4 & ~dirty_4))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_4 & ~dirty_4))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_5 & ~dirty_5))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_5 & ~dirty_5))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_6 & ~dirty_6))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_6 & ~dirty_6))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_7 & ~dirty_7))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_7 & ~dirty_7))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_8 & ~dirty_8))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_8 & ~dirty_8))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_9 & ~dirty_9))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_9 & ~dirty_9))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_10 & ~dirty_10))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_10 & ~dirty_10))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_11 & ~dirty_11))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_11 & ~dirty_11))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_12 & ~dirty_12))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_12 & ~dirty_12))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_13 & ~dirty_13))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_13 & ~dirty_13))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_14 & ~dirty_14))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_14 & ~dirty_14))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_15 & ~dirty_15))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_15 & ~dirty_15))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_16 & ~dirty_16))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_16 & ~dirty_16))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_17 & ~dirty_17))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_17 & ~dirty_17))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_18 & ~dirty_18))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_18 & ~dirty_18))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_19 & ~dirty_19))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_19 & ~dirty_19))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_20 & ~dirty_20))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_20 & ~dirty_20))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_21 & ~dirty_21))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_21 & ~dirty_21))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_22 & ~dirty_22))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_22 & ~dirty_22))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_23 & ~dirty_23))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_23 & ~dirty_23))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_24 & ~dirty_24))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_24 & ~dirty_24))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_25 & ~dirty_25))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_25 & ~dirty_25))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_26 & ~dirty_26))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_26 & ~dirty_26))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_27 & ~dirty_27))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_27 & ~dirty_27))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_28 & ~dirty_28))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_28 & ~dirty_28))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_29 & ~dirty_29))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_29 & ~dirty_29))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_30 & ~dirty_30))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_30 & ~dirty_30))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_31 & ~dirty_31))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_31 & ~dirty_31))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_32 & ~dirty_32))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_32 & ~dirty_32))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_33 & ~dirty_33))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_33 & ~dirty_33))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_34 & ~dirty_34))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_34 & ~dirty_34))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_35 & ~dirty_35))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_35 & ~dirty_35))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_36 & ~dirty_36))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_36 & ~dirty_36))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_37 & ~dirty_37))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_37 & ~dirty_37))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_38 & ~dirty_38))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_38 & ~dirty_38))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_39 & ~dirty_39))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_39 & ~dirty_39))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_40 & ~dirty_40))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_40 & ~dirty_40))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_41 & ~dirty_41))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_41 & ~dirty_41))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_42 & ~dirty_42))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_42 & ~dirty_42))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_43 & ~dirty_43))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_43 & ~dirty_43))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_44 & ~dirty_44))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_44 & ~dirty_44))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_45 & ~dirty_45))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_45 & ~dirty_45))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_46 & ~dirty_46))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_46 & ~dirty_46))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_47 & ~dirty_47))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_47 & ~dirty_47))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_48 & ~dirty_48))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_48 & ~dirty_48))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_49 & ~dirty_49))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_49 & ~dirty_49))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_50 & ~dirty_50))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_50 & ~dirty_50))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_51 & ~dirty_51))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_51 & ~dirty_51))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_52 & ~dirty_52))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_52 & ~dirty_52))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_53 & ~dirty_53))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_53 & ~dirty_53))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_54 & ~dirty_54))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_54 & ~dirty_54))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_55 & ~dirty_55))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_55 & ~dirty_55))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_56 & ~dirty_56))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_56 & ~dirty_56))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_57 & ~dirty_57))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_57 & ~dirty_57))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_58 & ~dirty_58))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_58 & ~dirty_58))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_59 & ~dirty_59))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_59 & ~dirty_59))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_60 & ~dirty_60))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_60 & ~dirty_60))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_61 & ~dirty_61))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_61 & ~dirty_61))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_62 & ~dirty_62))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_62 & ~dirty_62))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_63 & ~dirty_63))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_63 & ~dirty_63))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_64 & ~dirty_64))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_64 & ~dirty_64))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_65 & ~dirty_65))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_65 & ~dirty_65))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_66 & ~dirty_66))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_66 & ~dirty_66))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_67 & ~dirty_67))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_67 & ~dirty_67))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_68 & ~dirty_68))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_68 & ~dirty_68))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_69 & ~dirty_69))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_69 & ~dirty_69))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_70 & ~dirty_70))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_70 & ~dirty_70))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_71 & ~dirty_71))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_71 & ~dirty_71))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_72 & ~dirty_72))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_72 & ~dirty_72))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_73 & ~dirty_73))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_73 & ~dirty_73))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_74 & ~dirty_74))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_74 & ~dirty_74))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_75 & ~dirty_75))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_75 & ~dirty_75))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_76 & ~dirty_76))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_76 & ~dirty_76))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_77 & ~dirty_77))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_77 & ~dirty_77))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_78 & ~dirty_78))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_78 & ~dirty_78))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_79 & ~dirty_79))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_79 & ~dirty_79))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_80 & ~dirty_80))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_80 & ~dirty_80))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_81 & ~dirty_81))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_81 & ~dirty_81))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_82 & ~dirty_82))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_82 & ~dirty_82))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_83 & ~dirty_83))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_83 & ~dirty_83))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_84 & ~dirty_84))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_84 & ~dirty_84))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_85 & ~dirty_85))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_85 & ~dirty_85))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_86 & ~dirty_86))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_86 & ~dirty_86))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_87 & ~dirty_87))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_87 & ~dirty_87))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_88 & ~dirty_88))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_88 & ~dirty_88))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_89 & ~dirty_89))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_89 & ~dirty_89))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_90 & ~dirty_90))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_90 & ~dirty_90))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_91 & ~dirty_91))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_91 & ~dirty_91))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_92 & ~dirty_92))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_92 & ~dirty_92))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_93 & ~dirty_93))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_93 & ~dirty_93))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_94 & ~dirty_94))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_94 & ~dirty_94))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_95 & ~dirty_95))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_95 & ~dirty_95))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_96 & ~dirty_96))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_96 & ~dirty_96))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_97 & ~dirty_97))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_97 & ~dirty_97))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_98 & ~dirty_98))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_98 & ~dirty_98))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_99 & ~dirty_99))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_99 & ~dirty_99))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_100 & ~dirty_100))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_100 & ~dirty_100))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_101 & ~dirty_101))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_101 & ~dirty_101))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_102 & ~dirty_102))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_102 & ~dirty_102))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_103 & ~dirty_103))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_103 & ~dirty_103))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_104 & ~dirty_104))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_104 & ~dirty_104))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_105 & ~dirty_105))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_105 & ~dirty_105))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_106 & ~dirty_106))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_106 & ~dirty_106))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_107 & ~dirty_107))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_107 & ~dirty_107))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_108 & ~dirty_108))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_108 & ~dirty_108))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_109 & ~dirty_109))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_109 & ~dirty_109))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_110 & ~dirty_110))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_110 & ~dirty_110))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_111 & ~dirty_111))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_111 & ~dirty_111))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_112 & ~dirty_112))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_112 & ~dirty_112))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_113 & ~dirty_113))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_113 & ~dirty_113))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_114 & ~dirty_114))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_114 & ~dirty_114))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_115 & ~dirty_115))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_115 & ~dirty_115))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_116 & ~dirty_116))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_116 & ~dirty_116))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_117 & ~dirty_117))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_117 & ~dirty_117))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_118 & ~dirty_118))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_118 & ~dirty_118))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_119 & ~dirty_119))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_119 & ~dirty_119))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_120 & ~dirty_120))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_120 & ~dirty_120))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_121 & ~dirty_121))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_121 & ~dirty_121))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_122 & ~dirty_122))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_122 & ~dirty_122))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_123 & ~dirty_123))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_123 & ~dirty_123))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_124 & ~dirty_124))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_124 & ~dirty_124))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_125 & ~dirty_125))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_125 & ~dirty_125))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_126 & ~dirty_126))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_126 & ~dirty_126))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_127 & ~dirty_127))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_127 & ~dirty_127))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_128 & ~dirty_128))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_128 & ~dirty_128))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_129 & ~dirty_129))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_129 & ~dirty_129))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_130 & ~dirty_130))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_130 & ~dirty_130))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_131 & ~dirty_131))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_131 & ~dirty_131))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_132 & ~dirty_132))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_132 & ~dirty_132))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_133 & ~dirty_133))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_133 & ~dirty_133))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_134 & ~dirty_134))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_134 & ~dirty_134))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_135 & ~dirty_135))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_135 & ~dirty_135))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_136 & ~dirty_136))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_136 & ~dirty_136))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_137 & ~dirty_137))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_137 & ~dirty_137))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_138 & ~dirty_138))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_138 & ~dirty_138))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_139 & ~dirty_139))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_139 & ~dirty_139))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_140 & ~dirty_140))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_140 & ~dirty_140))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_141 & ~dirty_141))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_141 & ~dirty_141))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_142 & ~dirty_142))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_142 & ~dirty_142))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_143 & ~dirty_143))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_143 & ~dirty_143))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_144 & ~dirty_144))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_144 & ~dirty_144))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_145 & ~dirty_145))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_145 & ~dirty_145))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_146 & ~dirty_146))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_146 & ~dirty_146))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_147 & ~dirty_147))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_147 & ~dirty_147))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_148 & ~dirty_148))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_148 & ~dirty_148))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_149 & ~dirty_149))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_149 & ~dirty_149))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_150 & ~dirty_150))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_150 & ~dirty_150))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_151 & ~dirty_151))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_151 & ~dirty_151))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_152 & ~dirty_152))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_152 & ~dirty_152))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_153 & ~dirty_153))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_153 & ~dirty_153))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_154 & ~dirty_154))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_154 & ~dirty_154))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_155 & ~dirty_155))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_155 & ~dirty_155))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_156 & ~dirty_156))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_156 & ~dirty_156))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_157 & ~dirty_157))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_157 & ~dirty_157))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_158 & ~dirty_158))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_158 & ~dirty_158))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_159 & ~dirty_159))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_159 & ~dirty_159))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_160 & ~dirty_160))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_160 & ~dirty_160))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_161 & ~dirty_161))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_161 & ~dirty_161))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_162 & ~dirty_162))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_162 & ~dirty_162))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_163 & ~dirty_163))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_163 & ~dirty_163))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_164 & ~dirty_164))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_164 & ~dirty_164))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_165 & ~dirty_165))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_165 & ~dirty_165))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_166 & ~dirty_166))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_166 & ~dirty_166))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_167 & ~dirty_167))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_167 & ~dirty_167))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_168 & ~dirty_168))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_168 & ~dirty_168))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_169 & ~dirty_169))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_169 & ~dirty_169))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_170 & ~dirty_170))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_170 & ~dirty_170))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_171 & ~dirty_171))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_171 & ~dirty_171))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_172 & ~dirty_172))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_172 & ~dirty_172))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_173 & ~dirty_173))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_173 & ~dirty_173))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_174 & ~dirty_174))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_174 & ~dirty_174))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_175 & ~dirty_175))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_175 & ~dirty_175))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_176 & ~dirty_176))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_176 & ~dirty_176))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_177 & ~dirty_177))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_177 & ~dirty_177))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_178 & ~dirty_178))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_178 & ~dirty_178))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_179 & ~dirty_179))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_179 & ~dirty_179))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_180 & ~dirty_180))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_180 & ~dirty_180))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_181 & ~dirty_181))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_181 & ~dirty_181))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_182 & ~dirty_182))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_182 & ~dirty_182))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_183 & ~dirty_183))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_183 & ~dirty_183))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_184 & ~dirty_184))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_184 & ~dirty_184))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_185 & ~dirty_185))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_185 & ~dirty_185))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_186 & ~dirty_186))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_186 & ~dirty_186))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_187 & ~dirty_187))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_187 & ~dirty_187))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_188 & ~dirty_188))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_188 & ~dirty_188))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_189 & ~dirty_189))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_189 & ~dirty_189))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_190 & ~dirty_190))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_190 & ~dirty_190))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_191 & ~dirty_191))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_191 & ~dirty_191))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_192 & ~dirty_192))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_192 & ~dirty_192))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_193 & ~dirty_193))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_193 & ~dirty_193))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_194 & ~dirty_194))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_194 & ~dirty_194))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_195 & ~dirty_195))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_195 & ~dirty_195))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_196 & ~dirty_196))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_196 & ~dirty_196))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_197 & ~dirty_197))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_197 & ~dirty_197))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_198 & ~dirty_198))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_198 & ~dirty_198))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_199 & ~dirty_199))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_199 & ~dirty_199))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_200 & ~dirty_200))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_200 & ~dirty_200))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_201 & ~dirty_201))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_201 & ~dirty_201))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_202 & ~dirty_202))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_202 & ~dirty_202))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_203 & ~dirty_203))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_203 & ~dirty_203))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_204 & ~dirty_204))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_204 & ~dirty_204))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_205 & ~dirty_205))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_205 & ~dirty_205))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_206 & ~dirty_206))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_206 & ~dirty_206))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_207 & ~dirty_207))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_207 & ~dirty_207))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_208 & ~dirty_208))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_208 & ~dirty_208))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_209 & ~dirty_209))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_209 & ~dirty_209))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_210 & ~dirty_210))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_210 & ~dirty_210))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_211 & ~dirty_211))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_211 & ~dirty_211))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_212 & ~dirty_212))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_212 & ~dirty_212))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_213 & ~dirty_213))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_213 & ~dirty_213))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_214 & ~dirty_214))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_214 & ~dirty_214))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_215 & ~dirty_215))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_215 & ~dirty_215))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_216 & ~dirty_216))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_216 & ~dirty_216))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_217 & ~dirty_217))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_217 & ~dirty_217))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_218 & ~dirty_218))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_218 & ~dirty_218))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_219 & ~dirty_219))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_219 & ~dirty_219))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_220 & ~dirty_220))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_220 & ~dirty_220))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_221 & ~dirty_221))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_221 & ~dirty_221))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_222 & ~dirty_222))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_222 & ~dirty_222))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_223 & ~dirty_223))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_223 & ~dirty_223))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_224 & ~dirty_224))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_224 & ~dirty_224))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_225 & ~dirty_225))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_225 & ~dirty_225))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_226 & ~dirty_226))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_226 & ~dirty_226))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_227 & ~dirty_227))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_227 & ~dirty_227))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_228 & ~dirty_228))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_228 & ~dirty_228))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_229 & ~dirty_229))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_229 & ~dirty_229))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_230 & ~dirty_230))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_230 & ~dirty_230))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_231 & ~dirty_231))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_231 & ~dirty_231))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_232 & ~dirty_232))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_232 & ~dirty_232))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_233 & ~dirty_233))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_233 & ~dirty_233))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_234 & ~dirty_234))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_234 & ~dirty_234))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_235 & ~dirty_235))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_235 & ~dirty_235))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_236 & ~dirty_236))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_236 & ~dirty_236))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_237 & ~dirty_237))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_237 & ~dirty_237))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_238 & ~dirty_238))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_238 & ~dirty_238))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_239 & ~dirty_239))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_239 & ~dirty_239))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_240 & ~dirty_240))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_240 & ~dirty_240))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_241 & ~dirty_241))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_241 & ~dirty_241))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_242 & ~dirty_242))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_242 & ~dirty_242))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_243 & ~dirty_243))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_243 & ~dirty_243))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_244 & ~dirty_244))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_244 & ~dirty_244))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_245 & ~dirty_245))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_245 & ~dirty_245))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_246 & ~dirty_246))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_246 & ~dirty_246))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_247 & ~dirty_247))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_247 & ~dirty_247))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_248 & ~dirty_248))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_248 & ~dirty_248))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_249 & ~dirty_249))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_249 & ~dirty_249))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_250 & ~dirty_250))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_250 & ~dirty_250))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_251 & ~dirty_251))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_251 & ~dirty_251))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_252 & ~dirty_252))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_252 & ~dirty_252))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_253 & ~dirty_253))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_253 & ~dirty_253))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_254 & ~dirty_254))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_254 & ~dirty_254))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(flush_255 & ~dirty_255))) begin
- $fatal; // @[L1DCache.scala 579:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(flush_255 & ~dirty_255))) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:579 assert(!(flush(i) && !dirty(i)))\n"); // @[L1DCache.scala 579:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~_T_5829 & ~_T_5840 & ~_T_5843 & _T_5848 & _T_7 & ~axiwrite) begin
- $fatal; // @[L1DCache.scala 611:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~_T_5829 & ~_T_5840 & ~_T_5843 & _T_5848 & _T_7 & ~axiwrite) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:611 assert(memwaddrEn)\n"); // @[L1DCache.scala 611:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14461 & ~_T_5848 & _T_5854 & _T_7 & ~memwdataEn) begin
- $fatal; // @[L1DCache.scala 622:13]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14461 & ~_T_5848 & _T_5854 & _T_7 & ~memwdataEn) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:622 assert(memwdataEn)\n"); // @[L1DCache.scala 622:13]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4291) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4291) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_0)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4297) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4297) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_1)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4303) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4303) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_2)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_2)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4309) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4309) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_3)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_3)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4315) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4315) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_4)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_4)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4321) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4321) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_5)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_5)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4327) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4327) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_6)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_6)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4333) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4333) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_7)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_7)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4339) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4339) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_8)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_8)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4345) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4345) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_9)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_9)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4351) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4351) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_10)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_10)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4357) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4357) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_11)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_11)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4363) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4363) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_12)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_12)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4369) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4369) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_13)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_13)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4375) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4375) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_14)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_14)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4381) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4381) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_15)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_15)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4387) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4387) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_16)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_16)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4393) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4393) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_17)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_17)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4399) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4399) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_18)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_18)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4405) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4405) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_19)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_19)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4411) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4411) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_20)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_20)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4417) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4417) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_21)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_21)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4423) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4423) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_22)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_22)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4429) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4429) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_23)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_23)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4435) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4435) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_24)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_24)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4441) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4441) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_25)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_25)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4447) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4447) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_26)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_26)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4453) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4453) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_27)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_27)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4459) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4459) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_28)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_28)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4465) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4465) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_29)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_29)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4471) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4471) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_30)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_30)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4477) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4477) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_31)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_31)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4483) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4483) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_32)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_32)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4489) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4489) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_33)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_33)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4495) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4495) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_34)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_34)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4501) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4501) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_35)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_35)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4507) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4507) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_36)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_36)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4513) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4513) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_37)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_37)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4519) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4519) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_38)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_38)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4525) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4525) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_39)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_39)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4531) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4531) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_40)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_40)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4537) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4537) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_41)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_41)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4543) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4543) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_42)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_42)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4549) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4549) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_43)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_43)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4555) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4555) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_44)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_44)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4561) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4561) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_45)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_45)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4567) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4567) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_46)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_46)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4573) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4573) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_47)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_47)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4579) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4579) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_48)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_48)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4585) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4585) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_49)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_49)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4591) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4591) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_50)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_50)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4597) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4597) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_51)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_51)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4603) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4603) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_52)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_52)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4609) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4609) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_53)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_53)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4615) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4615) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_54)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_54)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4621) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4621) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_55)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_55)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4627) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4627) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_56)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_56)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4633) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4633) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_57)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_57)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4639) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4639) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_58)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_58)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4645) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4645) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_59)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_59)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4651) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4651) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_60)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_60)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4657) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4657) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_61)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_61)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4663) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4663) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_62)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_62)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4669) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4669) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_63)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_63)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4675) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4675) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_64)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_64)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4681) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4681) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_65)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_65)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4687) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4687) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_66)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_66)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4693) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4693) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_67)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_67)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4699) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4699) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_68)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_68)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4705) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4705) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_69)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_69)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4711) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4711) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_70)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_70)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4717) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4717) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_71)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_71)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4723) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4723) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_72)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_72)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4729) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4729) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_73)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_73)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4735) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4735) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_74)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_74)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4741) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4741) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_75)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_75)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4747) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4747) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_76)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_76)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4753) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4753) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_77)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_77)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4759) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4759) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_78)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_78)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4765) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4765) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_79)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_79)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4771) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4771) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_80)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_80)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4777) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4777) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_81)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_81)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4783) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4783) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_82)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_82)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4789) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4789) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_83)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_83)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4795) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4795) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_84)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_84)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4801) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4801) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_85)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_85)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4807) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4807) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_86)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_86)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4813) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4813) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_87)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_87)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4819) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4819) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_88)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_88)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4825) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4825) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_89)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_89)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4831) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4831) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_90)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_90)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4837) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4837) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_91)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_91)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4843) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4843) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_92)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_92)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4849) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4849) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_93)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_93)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4855) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4855) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_94)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_94)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4861) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4861) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_95)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_95)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4867) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4867) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_96)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_96)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4873) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4873) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_97)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_97)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4879) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4879) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_98)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_98)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4885) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4885) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_99)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_99)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4891) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4891) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_100)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_100)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4897) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4897) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_101)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_101)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4903) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4903) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_102)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_102)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4909) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4909) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_103)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_103)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4915) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4915) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_104)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_104)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4921) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4921) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_105)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_105)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4927) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4927) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_106)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_106)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4933) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4933) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_107)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_107)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4939) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4939) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_108)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_108)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4945) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4945) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_109)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_109)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4951) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4951) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_110)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_110)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4957) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4957) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_111)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_111)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4963) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4963) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_112)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_112)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4969) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4969) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_113)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_113)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4975) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4975) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_114)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_114)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4981) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4981) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_115)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_115)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4987) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4987) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_116)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_116)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4993) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4993) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_117)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_117)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4999) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_4999) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_118)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_118)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5005) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5005) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_119)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_119)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5011) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5011) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_120)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_120)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5017) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5017) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_121)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_121)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5023) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5023) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_122)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_122)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5029) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5029) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_123)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_123)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5035) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5035) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_124)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_124)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5041) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5041) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_125)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_125)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5047) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5047) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_126)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_126)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5053) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5053) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_127)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_127)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5059) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5059) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_128)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_128)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5065) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5065) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_129)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_129)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5071) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5071) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_130)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_130)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5077) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5077) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_131)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_131)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5083) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5083) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_132)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_132)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5089) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5089) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_133)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_133)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5095) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5095) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_134)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_134)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5101) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5101) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_135)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_135)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5107) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5107) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_136)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_136)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5113) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5113) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_137)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_137)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5119) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5119) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_138)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_138)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5125) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5125) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_139)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_139)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5131) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5131) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_140)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_140)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5137) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5137) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_141)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_141)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5143) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5143) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_142)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_142)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5149) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5149) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_143)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_143)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5155) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5155) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_144)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_144)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5161) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5161) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_145)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_145)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5167) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5167) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_146)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_146)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5173) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5173) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_147)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_147)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5179) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5179) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_148)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_148)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5185) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5185) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_149)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_149)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5191) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5191) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_150)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_150)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5197) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5197) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_151)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_151)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5203) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5203) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_152)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_152)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5209) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5209) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_153)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_153)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5215) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5215) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_154)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_154)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5221) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5221) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_155)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_155)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5227) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5227) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_156)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_156)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5233) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5233) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_157)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_157)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5239) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5239) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_158)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_158)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5245) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5245) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_159)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_159)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5251) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5251) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_160)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_160)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5257) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5257) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_161)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_161)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5263) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5263) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_162)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_162)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5269) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5269) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_163)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_163)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5275) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5275) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_164)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_164)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5281) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5281) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_165)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_165)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5287) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5287) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_166)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_166)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5293) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5293) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_167)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_167)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5299) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5299) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_168)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_168)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5305) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5305) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_169)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_169)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5311) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5311) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_170)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_170)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5317) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5317) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_171)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_171)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5323) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5323) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_172)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_172)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5329) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5329) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_173)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_173)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5335) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5335) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_174)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_174)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5341) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5341) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_175)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_175)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5347) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5347) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_176)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_176)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5353) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5353) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_177)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_177)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5359) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5359) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_178)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_178)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5365) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5365) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_179)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_179)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5371) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5371) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_180)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_180)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5377) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5377) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_181)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_181)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5383) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5383) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_182)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_182)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5389) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5389) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_183)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_183)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5395) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5395) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_184)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_184)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5401) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5401) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_185)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_185)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5407) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5407) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_186)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_186)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5413) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5413) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_187)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_187)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5419) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5419) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_188)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_188)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5425) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5425) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_189)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_189)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5431) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5431) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_190)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_190)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5437) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5437) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_191)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_191)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5443) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5443) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_192)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_192)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5449) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5449) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_193)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_193)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5455) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5455) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_194)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_194)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5461) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5461) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_195)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_195)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5467) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5467) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_196)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_196)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5473) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5473) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_197)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_197)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5479) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5479) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_198)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_198)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5485) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5485) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_199)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_199)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5491) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5491) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_200)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_200)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5497) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5497) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_201)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_201)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5503) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5503) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_202)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_202)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5509) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5509) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_203)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_203)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5515) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5515) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_204)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_204)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5521) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5521) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_205)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_205)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5527) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5527) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_206)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_206)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5533) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5533) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_207)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_207)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5539) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5539) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_208)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_208)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5545) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5545) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_209)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_209)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5551) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5551) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_210)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_210)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5557) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5557) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_211)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_211)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5563) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5563) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_212)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_212)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5569) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5569) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_213)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_213)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5575) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5575) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_214)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_214)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5581) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5581) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_215)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_215)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5587) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5587) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_216)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_216)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5593) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5593) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_217)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_217)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5599) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5599) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_218)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_218)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5605) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5605) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_219)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_219)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5611) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5611) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_220)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_220)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5617) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5617) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_221)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_221)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5623) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5623) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_222)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_222)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5629) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5629) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_223)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_223)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5635) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5635) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_224)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_224)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5641) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5641) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_225)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_225)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5647) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5647) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_226)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_226)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5653) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5653) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_227)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_227)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5659) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5659) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_228)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_228)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5665) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5665) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_229)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_229)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5671) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5671) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_230)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_230)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5677) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5677) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_231)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_231)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5683) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5683) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_232)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_232)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5689) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5689) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_233)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_233)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5695) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5695) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_234)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_234)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5701) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5701) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_235)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_235)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5707) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5707) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_236)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_236)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5713) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5713) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_237)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_237)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5719) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5719) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_238)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_238)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5725) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5725) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_239)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_239)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5731) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5731) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_240)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_240)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5737) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5737) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_241)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_241)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5743) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5743) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_242)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_242)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5749) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5749) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_243)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_243)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5755) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5755) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_244)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_244)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5761) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5761) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_245)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_245)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5767) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5767) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_246)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_246)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5773) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5773) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_247)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_247)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5779) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5779) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_248)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_248)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5785) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5785) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_249)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_249)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5791) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5791) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_250)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_250)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5797) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5797) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_251)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_251)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5803) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5803) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_252)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_252)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5809) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5809) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_253)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_253)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5815) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5815) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_254)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_254)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5821) begin
- $fatal; // @[L1DCache.scala 648:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14478 & ~_T_5854 & ~_T_5860 & ~_T_5870 & _T_5874 & io_flush_all & _T_7 & ~_T_5821) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:648 assert(!dirty(i))\n"); // @[L1DCache.scala 648:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_255)) begin
- $fatal; // @[L1DCache.scala 649:19]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_GEN_14506 & ~(~flush_255)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:649 assert(!flush(i))\n"); // @[L1DCache.scala 649:19]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(io_flush_valid & io_dbus_valid))) begin
- $fatal; // @[L1DCache.scala 658:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(io_flush_valid & io_dbus_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:658 assert(!(io.flush.valid && io.dbus.valid))\n"); // @[L1DCache.scala 658:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(~(io_dbus_valid & io_dbus_size == 6'h0))) begin
- $fatal; // @[L1DCache.scala 664:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(~(io_dbus_valid & io_dbus_size == 6'h0))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:664 assert(!(io.dbus.valid && io.dbus.size === 0.U))\n"); // @[L1DCache.scala 664:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_7 & ~(_T_7943[1:0] <= 2'h1)) begin
- $fatal; // @[L1DCache.scala 688:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_7 & ~(_T_7943[1:0] <= 2'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:688 assert(PopCount(busread +& buswrite +& axiread) <= 1.U)\n"); // @[L1DCache.scala 688:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_0 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_0 <= _GEN_4360;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_0 <= _GEN_4360;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_0 <= _GEN_4360;
- end else if (3'h3 == fstate) begin
- valid_0 <= _GEN_6167;
- end else begin
- valid_0 <= _GEN_7966;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_1 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_1 <= _GEN_4361;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_1 <= _GEN_4361;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_1 <= _GEN_4361;
- end else if (3'h3 == fstate) begin
- valid_1 <= _GEN_6168;
- end else begin
- valid_1 <= _GEN_7967;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_2 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_2 <= _GEN_4362;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_2 <= _GEN_4362;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_2 <= _GEN_4362;
- end else if (3'h3 == fstate) begin
- valid_2 <= _GEN_6169;
- end else begin
- valid_2 <= _GEN_7968;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_3 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_3 <= _GEN_4363;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_3 <= _GEN_4363;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_3 <= _GEN_4363;
- end else if (3'h3 == fstate) begin
- valid_3 <= _GEN_6170;
- end else begin
- valid_3 <= _GEN_7969;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_4 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_4 <= _GEN_4364;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_4 <= _GEN_4364;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_4 <= _GEN_4364;
- end else if (3'h3 == fstate) begin
- valid_4 <= _GEN_6171;
- end else begin
- valid_4 <= _GEN_7970;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_5 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_5 <= _GEN_4365;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_5 <= _GEN_4365;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_5 <= _GEN_4365;
- end else if (3'h3 == fstate) begin
- valid_5 <= _GEN_6172;
- end else begin
- valid_5 <= _GEN_7971;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_6 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_6 <= _GEN_4366;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_6 <= _GEN_4366;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_6 <= _GEN_4366;
- end else if (3'h3 == fstate) begin
- valid_6 <= _GEN_6173;
- end else begin
- valid_6 <= _GEN_7972;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_7 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_7 <= _GEN_4367;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_7 <= _GEN_4367;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_7 <= _GEN_4367;
- end else if (3'h3 == fstate) begin
- valid_7 <= _GEN_6174;
- end else begin
- valid_7 <= _GEN_7973;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_8 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_8 <= _GEN_4368;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_8 <= _GEN_4368;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_8 <= _GEN_4368;
- end else if (3'h3 == fstate) begin
- valid_8 <= _GEN_6175;
- end else begin
- valid_8 <= _GEN_7974;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_9 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_9 <= _GEN_4369;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_9 <= _GEN_4369;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_9 <= _GEN_4369;
- end else if (3'h3 == fstate) begin
- valid_9 <= _GEN_6176;
- end else begin
- valid_9 <= _GEN_7975;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_10 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_10 <= _GEN_4370;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_10 <= _GEN_4370;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_10 <= _GEN_4370;
- end else if (3'h3 == fstate) begin
- valid_10 <= _GEN_6177;
- end else begin
- valid_10 <= _GEN_7976;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_11 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_11 <= _GEN_4371;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_11 <= _GEN_4371;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_11 <= _GEN_4371;
- end else if (3'h3 == fstate) begin
- valid_11 <= _GEN_6178;
- end else begin
- valid_11 <= _GEN_7977;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_12 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_12 <= _GEN_4372;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_12 <= _GEN_4372;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_12 <= _GEN_4372;
- end else if (3'h3 == fstate) begin
- valid_12 <= _GEN_6179;
- end else begin
- valid_12 <= _GEN_7978;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_13 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_13 <= _GEN_4373;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_13 <= _GEN_4373;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_13 <= _GEN_4373;
- end else if (3'h3 == fstate) begin
- valid_13 <= _GEN_6180;
- end else begin
- valid_13 <= _GEN_7979;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_14 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_14 <= _GEN_4374;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_14 <= _GEN_4374;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_14 <= _GEN_4374;
- end else if (3'h3 == fstate) begin
- valid_14 <= _GEN_6181;
- end else begin
- valid_14 <= _GEN_7980;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_15 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_15 <= _GEN_4375;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_15 <= _GEN_4375;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_15 <= _GEN_4375;
- end else if (3'h3 == fstate) begin
- valid_15 <= _GEN_6182;
- end else begin
- valid_15 <= _GEN_7981;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_16 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_16 <= _GEN_4376;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_16 <= _GEN_4376;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_16 <= _GEN_4376;
- end else if (3'h3 == fstate) begin
- valid_16 <= _GEN_6183;
- end else begin
- valid_16 <= _GEN_7982;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_17 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_17 <= _GEN_4377;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_17 <= _GEN_4377;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_17 <= _GEN_4377;
- end else if (3'h3 == fstate) begin
- valid_17 <= _GEN_6184;
- end else begin
- valid_17 <= _GEN_7983;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_18 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_18 <= _GEN_4378;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_18 <= _GEN_4378;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_18 <= _GEN_4378;
- end else if (3'h3 == fstate) begin
- valid_18 <= _GEN_6185;
- end else begin
- valid_18 <= _GEN_7984;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_19 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_19 <= _GEN_4379;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_19 <= _GEN_4379;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_19 <= _GEN_4379;
- end else if (3'h3 == fstate) begin
- valid_19 <= _GEN_6186;
- end else begin
- valid_19 <= _GEN_7985;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_20 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_20 <= _GEN_4380;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_20 <= _GEN_4380;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_20 <= _GEN_4380;
- end else if (3'h3 == fstate) begin
- valid_20 <= _GEN_6187;
- end else begin
- valid_20 <= _GEN_7986;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_21 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_21 <= _GEN_4381;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_21 <= _GEN_4381;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_21 <= _GEN_4381;
- end else if (3'h3 == fstate) begin
- valid_21 <= _GEN_6188;
- end else begin
- valid_21 <= _GEN_7987;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_22 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_22 <= _GEN_4382;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_22 <= _GEN_4382;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_22 <= _GEN_4382;
- end else if (3'h3 == fstate) begin
- valid_22 <= _GEN_6189;
- end else begin
- valid_22 <= _GEN_7988;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_23 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_23 <= _GEN_4383;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_23 <= _GEN_4383;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_23 <= _GEN_4383;
- end else if (3'h3 == fstate) begin
- valid_23 <= _GEN_6190;
- end else begin
- valid_23 <= _GEN_7989;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_24 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_24 <= _GEN_4384;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_24 <= _GEN_4384;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_24 <= _GEN_4384;
- end else if (3'h3 == fstate) begin
- valid_24 <= _GEN_6191;
- end else begin
- valid_24 <= _GEN_7990;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_25 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_25 <= _GEN_4385;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_25 <= _GEN_4385;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_25 <= _GEN_4385;
- end else if (3'h3 == fstate) begin
- valid_25 <= _GEN_6192;
- end else begin
- valid_25 <= _GEN_7991;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_26 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_26 <= _GEN_4386;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_26 <= _GEN_4386;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_26 <= _GEN_4386;
- end else if (3'h3 == fstate) begin
- valid_26 <= _GEN_6193;
- end else begin
- valid_26 <= _GEN_7992;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_27 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_27 <= _GEN_4387;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_27 <= _GEN_4387;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_27 <= _GEN_4387;
- end else if (3'h3 == fstate) begin
- valid_27 <= _GEN_6194;
- end else begin
- valid_27 <= _GEN_7993;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_28 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_28 <= _GEN_4388;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_28 <= _GEN_4388;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_28 <= _GEN_4388;
- end else if (3'h3 == fstate) begin
- valid_28 <= _GEN_6195;
- end else begin
- valid_28 <= _GEN_7994;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_29 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_29 <= _GEN_4389;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_29 <= _GEN_4389;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_29 <= _GEN_4389;
- end else if (3'h3 == fstate) begin
- valid_29 <= _GEN_6196;
- end else begin
- valid_29 <= _GEN_7995;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_30 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_30 <= _GEN_4390;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_30 <= _GEN_4390;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_30 <= _GEN_4390;
- end else if (3'h3 == fstate) begin
- valid_30 <= _GEN_6197;
- end else begin
- valid_30 <= _GEN_7996;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_31 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_31 <= _GEN_4391;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_31 <= _GEN_4391;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_31 <= _GEN_4391;
- end else if (3'h3 == fstate) begin
- valid_31 <= _GEN_6198;
- end else begin
- valid_31 <= _GEN_7997;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_32 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_32 <= _GEN_4392;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_32 <= _GEN_4392;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_32 <= _GEN_4392;
- end else if (3'h3 == fstate) begin
- valid_32 <= _GEN_6199;
- end else begin
- valid_32 <= _GEN_7998;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_33 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_33 <= _GEN_4393;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_33 <= _GEN_4393;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_33 <= _GEN_4393;
- end else if (3'h3 == fstate) begin
- valid_33 <= _GEN_6200;
- end else begin
- valid_33 <= _GEN_7999;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_34 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_34 <= _GEN_4394;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_34 <= _GEN_4394;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_34 <= _GEN_4394;
- end else if (3'h3 == fstate) begin
- valid_34 <= _GEN_6201;
- end else begin
- valid_34 <= _GEN_8000;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_35 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_35 <= _GEN_4395;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_35 <= _GEN_4395;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_35 <= _GEN_4395;
- end else if (3'h3 == fstate) begin
- valid_35 <= _GEN_6202;
- end else begin
- valid_35 <= _GEN_8001;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_36 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_36 <= _GEN_4396;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_36 <= _GEN_4396;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_36 <= _GEN_4396;
- end else if (3'h3 == fstate) begin
- valid_36 <= _GEN_6203;
- end else begin
- valid_36 <= _GEN_8002;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_37 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_37 <= _GEN_4397;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_37 <= _GEN_4397;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_37 <= _GEN_4397;
- end else if (3'h3 == fstate) begin
- valid_37 <= _GEN_6204;
- end else begin
- valid_37 <= _GEN_8003;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_38 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_38 <= _GEN_4398;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_38 <= _GEN_4398;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_38 <= _GEN_4398;
- end else if (3'h3 == fstate) begin
- valid_38 <= _GEN_6205;
- end else begin
- valid_38 <= _GEN_8004;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_39 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_39 <= _GEN_4399;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_39 <= _GEN_4399;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_39 <= _GEN_4399;
- end else if (3'h3 == fstate) begin
- valid_39 <= _GEN_6206;
- end else begin
- valid_39 <= _GEN_8005;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_40 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_40 <= _GEN_4400;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_40 <= _GEN_4400;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_40 <= _GEN_4400;
- end else if (3'h3 == fstate) begin
- valid_40 <= _GEN_6207;
- end else begin
- valid_40 <= _GEN_8006;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_41 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_41 <= _GEN_4401;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_41 <= _GEN_4401;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_41 <= _GEN_4401;
- end else if (3'h3 == fstate) begin
- valid_41 <= _GEN_6208;
- end else begin
- valid_41 <= _GEN_8007;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_42 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_42 <= _GEN_4402;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_42 <= _GEN_4402;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_42 <= _GEN_4402;
- end else if (3'h3 == fstate) begin
- valid_42 <= _GEN_6209;
- end else begin
- valid_42 <= _GEN_8008;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_43 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_43 <= _GEN_4403;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_43 <= _GEN_4403;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_43 <= _GEN_4403;
- end else if (3'h3 == fstate) begin
- valid_43 <= _GEN_6210;
- end else begin
- valid_43 <= _GEN_8009;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_44 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_44 <= _GEN_4404;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_44 <= _GEN_4404;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_44 <= _GEN_4404;
- end else if (3'h3 == fstate) begin
- valid_44 <= _GEN_6211;
- end else begin
- valid_44 <= _GEN_8010;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_45 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_45 <= _GEN_4405;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_45 <= _GEN_4405;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_45 <= _GEN_4405;
- end else if (3'h3 == fstate) begin
- valid_45 <= _GEN_6212;
- end else begin
- valid_45 <= _GEN_8011;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_46 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_46 <= _GEN_4406;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_46 <= _GEN_4406;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_46 <= _GEN_4406;
- end else if (3'h3 == fstate) begin
- valid_46 <= _GEN_6213;
- end else begin
- valid_46 <= _GEN_8012;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_47 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_47 <= _GEN_4407;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_47 <= _GEN_4407;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_47 <= _GEN_4407;
- end else if (3'h3 == fstate) begin
- valid_47 <= _GEN_6214;
- end else begin
- valid_47 <= _GEN_8013;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_48 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_48 <= _GEN_4408;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_48 <= _GEN_4408;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_48 <= _GEN_4408;
- end else if (3'h3 == fstate) begin
- valid_48 <= _GEN_6215;
- end else begin
- valid_48 <= _GEN_8014;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_49 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_49 <= _GEN_4409;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_49 <= _GEN_4409;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_49 <= _GEN_4409;
- end else if (3'h3 == fstate) begin
- valid_49 <= _GEN_6216;
- end else begin
- valid_49 <= _GEN_8015;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_50 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_50 <= _GEN_4410;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_50 <= _GEN_4410;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_50 <= _GEN_4410;
- end else if (3'h3 == fstate) begin
- valid_50 <= _GEN_6217;
- end else begin
- valid_50 <= _GEN_8016;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_51 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_51 <= _GEN_4411;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_51 <= _GEN_4411;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_51 <= _GEN_4411;
- end else if (3'h3 == fstate) begin
- valid_51 <= _GEN_6218;
- end else begin
- valid_51 <= _GEN_8017;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_52 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_52 <= _GEN_4412;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_52 <= _GEN_4412;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_52 <= _GEN_4412;
- end else if (3'h3 == fstate) begin
- valid_52 <= _GEN_6219;
- end else begin
- valid_52 <= _GEN_8018;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_53 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_53 <= _GEN_4413;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_53 <= _GEN_4413;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_53 <= _GEN_4413;
- end else if (3'h3 == fstate) begin
- valid_53 <= _GEN_6220;
- end else begin
- valid_53 <= _GEN_8019;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_54 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_54 <= _GEN_4414;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_54 <= _GEN_4414;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_54 <= _GEN_4414;
- end else if (3'h3 == fstate) begin
- valid_54 <= _GEN_6221;
- end else begin
- valid_54 <= _GEN_8020;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_55 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_55 <= _GEN_4415;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_55 <= _GEN_4415;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_55 <= _GEN_4415;
- end else if (3'h3 == fstate) begin
- valid_55 <= _GEN_6222;
- end else begin
- valid_55 <= _GEN_8021;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_56 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_56 <= _GEN_4416;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_56 <= _GEN_4416;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_56 <= _GEN_4416;
- end else if (3'h3 == fstate) begin
- valid_56 <= _GEN_6223;
- end else begin
- valid_56 <= _GEN_8022;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_57 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_57 <= _GEN_4417;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_57 <= _GEN_4417;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_57 <= _GEN_4417;
- end else if (3'h3 == fstate) begin
- valid_57 <= _GEN_6224;
- end else begin
- valid_57 <= _GEN_8023;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_58 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_58 <= _GEN_4418;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_58 <= _GEN_4418;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_58 <= _GEN_4418;
- end else if (3'h3 == fstate) begin
- valid_58 <= _GEN_6225;
- end else begin
- valid_58 <= _GEN_8024;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_59 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_59 <= _GEN_4419;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_59 <= _GEN_4419;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_59 <= _GEN_4419;
- end else if (3'h3 == fstate) begin
- valid_59 <= _GEN_6226;
- end else begin
- valid_59 <= _GEN_8025;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_60 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_60 <= _GEN_4420;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_60 <= _GEN_4420;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_60 <= _GEN_4420;
- end else if (3'h3 == fstate) begin
- valid_60 <= _GEN_6227;
- end else begin
- valid_60 <= _GEN_8026;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_61 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_61 <= _GEN_4421;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_61 <= _GEN_4421;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_61 <= _GEN_4421;
- end else if (3'h3 == fstate) begin
- valid_61 <= _GEN_6228;
- end else begin
- valid_61 <= _GEN_8027;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_62 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_62 <= _GEN_4422;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_62 <= _GEN_4422;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_62 <= _GEN_4422;
- end else if (3'h3 == fstate) begin
- valid_62 <= _GEN_6229;
- end else begin
- valid_62 <= _GEN_8028;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_63 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_63 <= _GEN_4423;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_63 <= _GEN_4423;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_63 <= _GEN_4423;
- end else if (3'h3 == fstate) begin
- valid_63 <= _GEN_6230;
- end else begin
- valid_63 <= _GEN_8029;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_64 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_64 <= _GEN_4424;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_64 <= _GEN_4424;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_64 <= _GEN_4424;
- end else if (3'h3 == fstate) begin
- valid_64 <= _GEN_6231;
- end else begin
- valid_64 <= _GEN_8030;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_65 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_65 <= _GEN_4425;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_65 <= _GEN_4425;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_65 <= _GEN_4425;
- end else if (3'h3 == fstate) begin
- valid_65 <= _GEN_6232;
- end else begin
- valid_65 <= _GEN_8031;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_66 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_66 <= _GEN_4426;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_66 <= _GEN_4426;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_66 <= _GEN_4426;
- end else if (3'h3 == fstate) begin
- valid_66 <= _GEN_6233;
- end else begin
- valid_66 <= _GEN_8032;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_67 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_67 <= _GEN_4427;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_67 <= _GEN_4427;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_67 <= _GEN_4427;
- end else if (3'h3 == fstate) begin
- valid_67 <= _GEN_6234;
- end else begin
- valid_67 <= _GEN_8033;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_68 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_68 <= _GEN_4428;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_68 <= _GEN_4428;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_68 <= _GEN_4428;
- end else if (3'h3 == fstate) begin
- valid_68 <= _GEN_6235;
- end else begin
- valid_68 <= _GEN_8034;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_69 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_69 <= _GEN_4429;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_69 <= _GEN_4429;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_69 <= _GEN_4429;
- end else if (3'h3 == fstate) begin
- valid_69 <= _GEN_6236;
- end else begin
- valid_69 <= _GEN_8035;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_70 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_70 <= _GEN_4430;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_70 <= _GEN_4430;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_70 <= _GEN_4430;
- end else if (3'h3 == fstate) begin
- valid_70 <= _GEN_6237;
- end else begin
- valid_70 <= _GEN_8036;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_71 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_71 <= _GEN_4431;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_71 <= _GEN_4431;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_71 <= _GEN_4431;
- end else if (3'h3 == fstate) begin
- valid_71 <= _GEN_6238;
- end else begin
- valid_71 <= _GEN_8037;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_72 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_72 <= _GEN_4432;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_72 <= _GEN_4432;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_72 <= _GEN_4432;
- end else if (3'h3 == fstate) begin
- valid_72 <= _GEN_6239;
- end else begin
- valid_72 <= _GEN_8038;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_73 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_73 <= _GEN_4433;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_73 <= _GEN_4433;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_73 <= _GEN_4433;
- end else if (3'h3 == fstate) begin
- valid_73 <= _GEN_6240;
- end else begin
- valid_73 <= _GEN_8039;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_74 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_74 <= _GEN_4434;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_74 <= _GEN_4434;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_74 <= _GEN_4434;
- end else if (3'h3 == fstate) begin
- valid_74 <= _GEN_6241;
- end else begin
- valid_74 <= _GEN_8040;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_75 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_75 <= _GEN_4435;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_75 <= _GEN_4435;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_75 <= _GEN_4435;
- end else if (3'h3 == fstate) begin
- valid_75 <= _GEN_6242;
- end else begin
- valid_75 <= _GEN_8041;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_76 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_76 <= _GEN_4436;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_76 <= _GEN_4436;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_76 <= _GEN_4436;
- end else if (3'h3 == fstate) begin
- valid_76 <= _GEN_6243;
- end else begin
- valid_76 <= _GEN_8042;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_77 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_77 <= _GEN_4437;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_77 <= _GEN_4437;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_77 <= _GEN_4437;
- end else if (3'h3 == fstate) begin
- valid_77 <= _GEN_6244;
- end else begin
- valid_77 <= _GEN_8043;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_78 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_78 <= _GEN_4438;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_78 <= _GEN_4438;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_78 <= _GEN_4438;
- end else if (3'h3 == fstate) begin
- valid_78 <= _GEN_6245;
- end else begin
- valid_78 <= _GEN_8044;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_79 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_79 <= _GEN_4439;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_79 <= _GEN_4439;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_79 <= _GEN_4439;
- end else if (3'h3 == fstate) begin
- valid_79 <= _GEN_6246;
- end else begin
- valid_79 <= _GEN_8045;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_80 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_80 <= _GEN_4440;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_80 <= _GEN_4440;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_80 <= _GEN_4440;
- end else if (3'h3 == fstate) begin
- valid_80 <= _GEN_6247;
- end else begin
- valid_80 <= _GEN_8046;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_81 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_81 <= _GEN_4441;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_81 <= _GEN_4441;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_81 <= _GEN_4441;
- end else if (3'h3 == fstate) begin
- valid_81 <= _GEN_6248;
- end else begin
- valid_81 <= _GEN_8047;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_82 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_82 <= _GEN_4442;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_82 <= _GEN_4442;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_82 <= _GEN_4442;
- end else if (3'h3 == fstate) begin
- valid_82 <= _GEN_6249;
- end else begin
- valid_82 <= _GEN_8048;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_83 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_83 <= _GEN_4443;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_83 <= _GEN_4443;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_83 <= _GEN_4443;
- end else if (3'h3 == fstate) begin
- valid_83 <= _GEN_6250;
- end else begin
- valid_83 <= _GEN_8049;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_84 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_84 <= _GEN_4444;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_84 <= _GEN_4444;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_84 <= _GEN_4444;
- end else if (3'h3 == fstate) begin
- valid_84 <= _GEN_6251;
- end else begin
- valid_84 <= _GEN_8050;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_85 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_85 <= _GEN_4445;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_85 <= _GEN_4445;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_85 <= _GEN_4445;
- end else if (3'h3 == fstate) begin
- valid_85 <= _GEN_6252;
- end else begin
- valid_85 <= _GEN_8051;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_86 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_86 <= _GEN_4446;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_86 <= _GEN_4446;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_86 <= _GEN_4446;
- end else if (3'h3 == fstate) begin
- valid_86 <= _GEN_6253;
- end else begin
- valid_86 <= _GEN_8052;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_87 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_87 <= _GEN_4447;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_87 <= _GEN_4447;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_87 <= _GEN_4447;
- end else if (3'h3 == fstate) begin
- valid_87 <= _GEN_6254;
- end else begin
- valid_87 <= _GEN_8053;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_88 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_88 <= _GEN_4448;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_88 <= _GEN_4448;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_88 <= _GEN_4448;
- end else if (3'h3 == fstate) begin
- valid_88 <= _GEN_6255;
- end else begin
- valid_88 <= _GEN_8054;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_89 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_89 <= _GEN_4449;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_89 <= _GEN_4449;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_89 <= _GEN_4449;
- end else if (3'h3 == fstate) begin
- valid_89 <= _GEN_6256;
- end else begin
- valid_89 <= _GEN_8055;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_90 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_90 <= _GEN_4450;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_90 <= _GEN_4450;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_90 <= _GEN_4450;
- end else if (3'h3 == fstate) begin
- valid_90 <= _GEN_6257;
- end else begin
- valid_90 <= _GEN_8056;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_91 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_91 <= _GEN_4451;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_91 <= _GEN_4451;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_91 <= _GEN_4451;
- end else if (3'h3 == fstate) begin
- valid_91 <= _GEN_6258;
- end else begin
- valid_91 <= _GEN_8057;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_92 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_92 <= _GEN_4452;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_92 <= _GEN_4452;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_92 <= _GEN_4452;
- end else if (3'h3 == fstate) begin
- valid_92 <= _GEN_6259;
- end else begin
- valid_92 <= _GEN_8058;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_93 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_93 <= _GEN_4453;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_93 <= _GEN_4453;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_93 <= _GEN_4453;
- end else if (3'h3 == fstate) begin
- valid_93 <= _GEN_6260;
- end else begin
- valid_93 <= _GEN_8059;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_94 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_94 <= _GEN_4454;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_94 <= _GEN_4454;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_94 <= _GEN_4454;
- end else if (3'h3 == fstate) begin
- valid_94 <= _GEN_6261;
- end else begin
- valid_94 <= _GEN_8060;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_95 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_95 <= _GEN_4455;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_95 <= _GEN_4455;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_95 <= _GEN_4455;
- end else if (3'h3 == fstate) begin
- valid_95 <= _GEN_6262;
- end else begin
- valid_95 <= _GEN_8061;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_96 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_96 <= _GEN_4456;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_96 <= _GEN_4456;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_96 <= _GEN_4456;
- end else if (3'h3 == fstate) begin
- valid_96 <= _GEN_6263;
- end else begin
- valid_96 <= _GEN_8062;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_97 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_97 <= _GEN_4457;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_97 <= _GEN_4457;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_97 <= _GEN_4457;
- end else if (3'h3 == fstate) begin
- valid_97 <= _GEN_6264;
- end else begin
- valid_97 <= _GEN_8063;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_98 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_98 <= _GEN_4458;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_98 <= _GEN_4458;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_98 <= _GEN_4458;
- end else if (3'h3 == fstate) begin
- valid_98 <= _GEN_6265;
- end else begin
- valid_98 <= _GEN_8064;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_99 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_99 <= _GEN_4459;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_99 <= _GEN_4459;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_99 <= _GEN_4459;
- end else if (3'h3 == fstate) begin
- valid_99 <= _GEN_6266;
- end else begin
- valid_99 <= _GEN_8065;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_100 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_100 <= _GEN_4460;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_100 <= _GEN_4460;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_100 <= _GEN_4460;
- end else if (3'h3 == fstate) begin
- valid_100 <= _GEN_6267;
- end else begin
- valid_100 <= _GEN_8066;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_101 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_101 <= _GEN_4461;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_101 <= _GEN_4461;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_101 <= _GEN_4461;
- end else if (3'h3 == fstate) begin
- valid_101 <= _GEN_6268;
- end else begin
- valid_101 <= _GEN_8067;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_102 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_102 <= _GEN_4462;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_102 <= _GEN_4462;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_102 <= _GEN_4462;
- end else if (3'h3 == fstate) begin
- valid_102 <= _GEN_6269;
- end else begin
- valid_102 <= _GEN_8068;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_103 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_103 <= _GEN_4463;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_103 <= _GEN_4463;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_103 <= _GEN_4463;
- end else if (3'h3 == fstate) begin
- valid_103 <= _GEN_6270;
- end else begin
- valid_103 <= _GEN_8069;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_104 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_104 <= _GEN_4464;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_104 <= _GEN_4464;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_104 <= _GEN_4464;
- end else if (3'h3 == fstate) begin
- valid_104 <= _GEN_6271;
- end else begin
- valid_104 <= _GEN_8070;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_105 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_105 <= _GEN_4465;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_105 <= _GEN_4465;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_105 <= _GEN_4465;
- end else if (3'h3 == fstate) begin
- valid_105 <= _GEN_6272;
- end else begin
- valid_105 <= _GEN_8071;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_106 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_106 <= _GEN_4466;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_106 <= _GEN_4466;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_106 <= _GEN_4466;
- end else if (3'h3 == fstate) begin
- valid_106 <= _GEN_6273;
- end else begin
- valid_106 <= _GEN_8072;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_107 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_107 <= _GEN_4467;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_107 <= _GEN_4467;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_107 <= _GEN_4467;
- end else if (3'h3 == fstate) begin
- valid_107 <= _GEN_6274;
- end else begin
- valid_107 <= _GEN_8073;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_108 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_108 <= _GEN_4468;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_108 <= _GEN_4468;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_108 <= _GEN_4468;
- end else if (3'h3 == fstate) begin
- valid_108 <= _GEN_6275;
- end else begin
- valid_108 <= _GEN_8074;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_109 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_109 <= _GEN_4469;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_109 <= _GEN_4469;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_109 <= _GEN_4469;
- end else if (3'h3 == fstate) begin
- valid_109 <= _GEN_6276;
- end else begin
- valid_109 <= _GEN_8075;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_110 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_110 <= _GEN_4470;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_110 <= _GEN_4470;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_110 <= _GEN_4470;
- end else if (3'h3 == fstate) begin
- valid_110 <= _GEN_6277;
- end else begin
- valid_110 <= _GEN_8076;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_111 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_111 <= _GEN_4471;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_111 <= _GEN_4471;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_111 <= _GEN_4471;
- end else if (3'h3 == fstate) begin
- valid_111 <= _GEN_6278;
- end else begin
- valid_111 <= _GEN_8077;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_112 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_112 <= _GEN_4472;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_112 <= _GEN_4472;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_112 <= _GEN_4472;
- end else if (3'h3 == fstate) begin
- valid_112 <= _GEN_6279;
- end else begin
- valid_112 <= _GEN_8078;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_113 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_113 <= _GEN_4473;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_113 <= _GEN_4473;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_113 <= _GEN_4473;
- end else if (3'h3 == fstate) begin
- valid_113 <= _GEN_6280;
- end else begin
- valid_113 <= _GEN_8079;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_114 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_114 <= _GEN_4474;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_114 <= _GEN_4474;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_114 <= _GEN_4474;
- end else if (3'h3 == fstate) begin
- valid_114 <= _GEN_6281;
- end else begin
- valid_114 <= _GEN_8080;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_115 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_115 <= _GEN_4475;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_115 <= _GEN_4475;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_115 <= _GEN_4475;
- end else if (3'h3 == fstate) begin
- valid_115 <= _GEN_6282;
- end else begin
- valid_115 <= _GEN_8081;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_116 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_116 <= _GEN_4476;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_116 <= _GEN_4476;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_116 <= _GEN_4476;
- end else if (3'h3 == fstate) begin
- valid_116 <= _GEN_6283;
- end else begin
- valid_116 <= _GEN_8082;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_117 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_117 <= _GEN_4477;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_117 <= _GEN_4477;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_117 <= _GEN_4477;
- end else if (3'h3 == fstate) begin
- valid_117 <= _GEN_6284;
- end else begin
- valid_117 <= _GEN_8083;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_118 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_118 <= _GEN_4478;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_118 <= _GEN_4478;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_118 <= _GEN_4478;
- end else if (3'h3 == fstate) begin
- valid_118 <= _GEN_6285;
- end else begin
- valid_118 <= _GEN_8084;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_119 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_119 <= _GEN_4479;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_119 <= _GEN_4479;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_119 <= _GEN_4479;
- end else if (3'h3 == fstate) begin
- valid_119 <= _GEN_6286;
- end else begin
- valid_119 <= _GEN_8085;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_120 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_120 <= _GEN_4480;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_120 <= _GEN_4480;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_120 <= _GEN_4480;
- end else if (3'h3 == fstate) begin
- valid_120 <= _GEN_6287;
- end else begin
- valid_120 <= _GEN_8086;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_121 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_121 <= _GEN_4481;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_121 <= _GEN_4481;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_121 <= _GEN_4481;
- end else if (3'h3 == fstate) begin
- valid_121 <= _GEN_6288;
- end else begin
- valid_121 <= _GEN_8087;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_122 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_122 <= _GEN_4482;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_122 <= _GEN_4482;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_122 <= _GEN_4482;
- end else if (3'h3 == fstate) begin
- valid_122 <= _GEN_6289;
- end else begin
- valid_122 <= _GEN_8088;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_123 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_123 <= _GEN_4483;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_123 <= _GEN_4483;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_123 <= _GEN_4483;
- end else if (3'h3 == fstate) begin
- valid_123 <= _GEN_6290;
- end else begin
- valid_123 <= _GEN_8089;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_124 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_124 <= _GEN_4484;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_124 <= _GEN_4484;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_124 <= _GEN_4484;
- end else if (3'h3 == fstate) begin
- valid_124 <= _GEN_6291;
- end else begin
- valid_124 <= _GEN_8090;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_125 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_125 <= _GEN_4485;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_125 <= _GEN_4485;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_125 <= _GEN_4485;
- end else if (3'h3 == fstate) begin
- valid_125 <= _GEN_6292;
- end else begin
- valid_125 <= _GEN_8091;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_126 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_126 <= _GEN_4486;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_126 <= _GEN_4486;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_126 <= _GEN_4486;
- end else if (3'h3 == fstate) begin
- valid_126 <= _GEN_6293;
- end else begin
- valid_126 <= _GEN_8092;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_127 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_127 <= _GEN_4487;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_127 <= _GEN_4487;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_127 <= _GEN_4487;
- end else if (3'h3 == fstate) begin
- valid_127 <= _GEN_6294;
- end else begin
- valid_127 <= _GEN_8093;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_128 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_128 <= _GEN_4488;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_128 <= _GEN_4488;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_128 <= _GEN_4488;
- end else if (3'h3 == fstate) begin
- valid_128 <= _GEN_6295;
- end else begin
- valid_128 <= _GEN_8094;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_129 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_129 <= _GEN_4489;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_129 <= _GEN_4489;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_129 <= _GEN_4489;
- end else if (3'h3 == fstate) begin
- valid_129 <= _GEN_6296;
- end else begin
- valid_129 <= _GEN_8095;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_130 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_130 <= _GEN_4490;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_130 <= _GEN_4490;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_130 <= _GEN_4490;
- end else if (3'h3 == fstate) begin
- valid_130 <= _GEN_6297;
- end else begin
- valid_130 <= _GEN_8096;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_131 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_131 <= _GEN_4491;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_131 <= _GEN_4491;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_131 <= _GEN_4491;
- end else if (3'h3 == fstate) begin
- valid_131 <= _GEN_6298;
- end else begin
- valid_131 <= _GEN_8097;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_132 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_132 <= _GEN_4492;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_132 <= _GEN_4492;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_132 <= _GEN_4492;
- end else if (3'h3 == fstate) begin
- valid_132 <= _GEN_6299;
- end else begin
- valid_132 <= _GEN_8098;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_133 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_133 <= _GEN_4493;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_133 <= _GEN_4493;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_133 <= _GEN_4493;
- end else if (3'h3 == fstate) begin
- valid_133 <= _GEN_6300;
- end else begin
- valid_133 <= _GEN_8099;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_134 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_134 <= _GEN_4494;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_134 <= _GEN_4494;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_134 <= _GEN_4494;
- end else if (3'h3 == fstate) begin
- valid_134 <= _GEN_6301;
- end else begin
- valid_134 <= _GEN_8100;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_135 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_135 <= _GEN_4495;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_135 <= _GEN_4495;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_135 <= _GEN_4495;
- end else if (3'h3 == fstate) begin
- valid_135 <= _GEN_6302;
- end else begin
- valid_135 <= _GEN_8101;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_136 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_136 <= _GEN_4496;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_136 <= _GEN_4496;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_136 <= _GEN_4496;
- end else if (3'h3 == fstate) begin
- valid_136 <= _GEN_6303;
- end else begin
- valid_136 <= _GEN_8102;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_137 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_137 <= _GEN_4497;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_137 <= _GEN_4497;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_137 <= _GEN_4497;
- end else if (3'h3 == fstate) begin
- valid_137 <= _GEN_6304;
- end else begin
- valid_137 <= _GEN_8103;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_138 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_138 <= _GEN_4498;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_138 <= _GEN_4498;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_138 <= _GEN_4498;
- end else if (3'h3 == fstate) begin
- valid_138 <= _GEN_6305;
- end else begin
- valid_138 <= _GEN_8104;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_139 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_139 <= _GEN_4499;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_139 <= _GEN_4499;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_139 <= _GEN_4499;
- end else if (3'h3 == fstate) begin
- valid_139 <= _GEN_6306;
- end else begin
- valid_139 <= _GEN_8105;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_140 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_140 <= _GEN_4500;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_140 <= _GEN_4500;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_140 <= _GEN_4500;
- end else if (3'h3 == fstate) begin
- valid_140 <= _GEN_6307;
- end else begin
- valid_140 <= _GEN_8106;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_141 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_141 <= _GEN_4501;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_141 <= _GEN_4501;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_141 <= _GEN_4501;
- end else if (3'h3 == fstate) begin
- valid_141 <= _GEN_6308;
- end else begin
- valid_141 <= _GEN_8107;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_142 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_142 <= _GEN_4502;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_142 <= _GEN_4502;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_142 <= _GEN_4502;
- end else if (3'h3 == fstate) begin
- valid_142 <= _GEN_6309;
- end else begin
- valid_142 <= _GEN_8108;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_143 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_143 <= _GEN_4503;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_143 <= _GEN_4503;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_143 <= _GEN_4503;
- end else if (3'h3 == fstate) begin
- valid_143 <= _GEN_6310;
- end else begin
- valid_143 <= _GEN_8109;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_144 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_144 <= _GEN_4504;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_144 <= _GEN_4504;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_144 <= _GEN_4504;
- end else if (3'h3 == fstate) begin
- valid_144 <= _GEN_6311;
- end else begin
- valid_144 <= _GEN_8110;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_145 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_145 <= _GEN_4505;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_145 <= _GEN_4505;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_145 <= _GEN_4505;
- end else if (3'h3 == fstate) begin
- valid_145 <= _GEN_6312;
- end else begin
- valid_145 <= _GEN_8111;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_146 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_146 <= _GEN_4506;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_146 <= _GEN_4506;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_146 <= _GEN_4506;
- end else if (3'h3 == fstate) begin
- valid_146 <= _GEN_6313;
- end else begin
- valid_146 <= _GEN_8112;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_147 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_147 <= _GEN_4507;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_147 <= _GEN_4507;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_147 <= _GEN_4507;
- end else if (3'h3 == fstate) begin
- valid_147 <= _GEN_6314;
- end else begin
- valid_147 <= _GEN_8113;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_148 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_148 <= _GEN_4508;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_148 <= _GEN_4508;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_148 <= _GEN_4508;
- end else if (3'h3 == fstate) begin
- valid_148 <= _GEN_6315;
- end else begin
- valid_148 <= _GEN_8114;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_149 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_149 <= _GEN_4509;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_149 <= _GEN_4509;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_149 <= _GEN_4509;
- end else if (3'h3 == fstate) begin
- valid_149 <= _GEN_6316;
- end else begin
- valid_149 <= _GEN_8115;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_150 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_150 <= _GEN_4510;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_150 <= _GEN_4510;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_150 <= _GEN_4510;
- end else if (3'h3 == fstate) begin
- valid_150 <= _GEN_6317;
- end else begin
- valid_150 <= _GEN_8116;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_151 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_151 <= _GEN_4511;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_151 <= _GEN_4511;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_151 <= _GEN_4511;
- end else if (3'h3 == fstate) begin
- valid_151 <= _GEN_6318;
- end else begin
- valid_151 <= _GEN_8117;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_152 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_152 <= _GEN_4512;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_152 <= _GEN_4512;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_152 <= _GEN_4512;
- end else if (3'h3 == fstate) begin
- valid_152 <= _GEN_6319;
- end else begin
- valid_152 <= _GEN_8118;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_153 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_153 <= _GEN_4513;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_153 <= _GEN_4513;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_153 <= _GEN_4513;
- end else if (3'h3 == fstate) begin
- valid_153 <= _GEN_6320;
- end else begin
- valid_153 <= _GEN_8119;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_154 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_154 <= _GEN_4514;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_154 <= _GEN_4514;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_154 <= _GEN_4514;
- end else if (3'h3 == fstate) begin
- valid_154 <= _GEN_6321;
- end else begin
- valid_154 <= _GEN_8120;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_155 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_155 <= _GEN_4515;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_155 <= _GEN_4515;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_155 <= _GEN_4515;
- end else if (3'h3 == fstate) begin
- valid_155 <= _GEN_6322;
- end else begin
- valid_155 <= _GEN_8121;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_156 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_156 <= _GEN_4516;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_156 <= _GEN_4516;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_156 <= _GEN_4516;
- end else if (3'h3 == fstate) begin
- valid_156 <= _GEN_6323;
- end else begin
- valid_156 <= _GEN_8122;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_157 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_157 <= _GEN_4517;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_157 <= _GEN_4517;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_157 <= _GEN_4517;
- end else if (3'h3 == fstate) begin
- valid_157 <= _GEN_6324;
- end else begin
- valid_157 <= _GEN_8123;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_158 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_158 <= _GEN_4518;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_158 <= _GEN_4518;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_158 <= _GEN_4518;
- end else if (3'h3 == fstate) begin
- valid_158 <= _GEN_6325;
- end else begin
- valid_158 <= _GEN_8124;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_159 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_159 <= _GEN_4519;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_159 <= _GEN_4519;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_159 <= _GEN_4519;
- end else if (3'h3 == fstate) begin
- valid_159 <= _GEN_6326;
- end else begin
- valid_159 <= _GEN_8125;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_160 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_160 <= _GEN_4520;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_160 <= _GEN_4520;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_160 <= _GEN_4520;
- end else if (3'h3 == fstate) begin
- valid_160 <= _GEN_6327;
- end else begin
- valid_160 <= _GEN_8126;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_161 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_161 <= _GEN_4521;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_161 <= _GEN_4521;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_161 <= _GEN_4521;
- end else if (3'h3 == fstate) begin
- valid_161 <= _GEN_6328;
- end else begin
- valid_161 <= _GEN_8127;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_162 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_162 <= _GEN_4522;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_162 <= _GEN_4522;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_162 <= _GEN_4522;
- end else if (3'h3 == fstate) begin
- valid_162 <= _GEN_6329;
- end else begin
- valid_162 <= _GEN_8128;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_163 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_163 <= _GEN_4523;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_163 <= _GEN_4523;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_163 <= _GEN_4523;
- end else if (3'h3 == fstate) begin
- valid_163 <= _GEN_6330;
- end else begin
- valid_163 <= _GEN_8129;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_164 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_164 <= _GEN_4524;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_164 <= _GEN_4524;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_164 <= _GEN_4524;
- end else if (3'h3 == fstate) begin
- valid_164 <= _GEN_6331;
- end else begin
- valid_164 <= _GEN_8130;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_165 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_165 <= _GEN_4525;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_165 <= _GEN_4525;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_165 <= _GEN_4525;
- end else if (3'h3 == fstate) begin
- valid_165 <= _GEN_6332;
- end else begin
- valid_165 <= _GEN_8131;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_166 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_166 <= _GEN_4526;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_166 <= _GEN_4526;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_166 <= _GEN_4526;
- end else if (3'h3 == fstate) begin
- valid_166 <= _GEN_6333;
- end else begin
- valid_166 <= _GEN_8132;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_167 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_167 <= _GEN_4527;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_167 <= _GEN_4527;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_167 <= _GEN_4527;
- end else if (3'h3 == fstate) begin
- valid_167 <= _GEN_6334;
- end else begin
- valid_167 <= _GEN_8133;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_168 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_168 <= _GEN_4528;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_168 <= _GEN_4528;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_168 <= _GEN_4528;
- end else if (3'h3 == fstate) begin
- valid_168 <= _GEN_6335;
- end else begin
- valid_168 <= _GEN_8134;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_169 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_169 <= _GEN_4529;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_169 <= _GEN_4529;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_169 <= _GEN_4529;
- end else if (3'h3 == fstate) begin
- valid_169 <= _GEN_6336;
- end else begin
- valid_169 <= _GEN_8135;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_170 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_170 <= _GEN_4530;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_170 <= _GEN_4530;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_170 <= _GEN_4530;
- end else if (3'h3 == fstate) begin
- valid_170 <= _GEN_6337;
- end else begin
- valid_170 <= _GEN_8136;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_171 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_171 <= _GEN_4531;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_171 <= _GEN_4531;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_171 <= _GEN_4531;
- end else if (3'h3 == fstate) begin
- valid_171 <= _GEN_6338;
- end else begin
- valid_171 <= _GEN_8137;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_172 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_172 <= _GEN_4532;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_172 <= _GEN_4532;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_172 <= _GEN_4532;
- end else if (3'h3 == fstate) begin
- valid_172 <= _GEN_6339;
- end else begin
- valid_172 <= _GEN_8138;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_173 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_173 <= _GEN_4533;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_173 <= _GEN_4533;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_173 <= _GEN_4533;
- end else if (3'h3 == fstate) begin
- valid_173 <= _GEN_6340;
- end else begin
- valid_173 <= _GEN_8139;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_174 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_174 <= _GEN_4534;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_174 <= _GEN_4534;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_174 <= _GEN_4534;
- end else if (3'h3 == fstate) begin
- valid_174 <= _GEN_6341;
- end else begin
- valid_174 <= _GEN_8140;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_175 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_175 <= _GEN_4535;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_175 <= _GEN_4535;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_175 <= _GEN_4535;
- end else if (3'h3 == fstate) begin
- valid_175 <= _GEN_6342;
- end else begin
- valid_175 <= _GEN_8141;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_176 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_176 <= _GEN_4536;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_176 <= _GEN_4536;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_176 <= _GEN_4536;
- end else if (3'h3 == fstate) begin
- valid_176 <= _GEN_6343;
- end else begin
- valid_176 <= _GEN_8142;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_177 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_177 <= _GEN_4537;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_177 <= _GEN_4537;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_177 <= _GEN_4537;
- end else if (3'h3 == fstate) begin
- valid_177 <= _GEN_6344;
- end else begin
- valid_177 <= _GEN_8143;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_178 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_178 <= _GEN_4538;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_178 <= _GEN_4538;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_178 <= _GEN_4538;
- end else if (3'h3 == fstate) begin
- valid_178 <= _GEN_6345;
- end else begin
- valid_178 <= _GEN_8144;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_179 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_179 <= _GEN_4539;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_179 <= _GEN_4539;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_179 <= _GEN_4539;
- end else if (3'h3 == fstate) begin
- valid_179 <= _GEN_6346;
- end else begin
- valid_179 <= _GEN_8145;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_180 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_180 <= _GEN_4540;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_180 <= _GEN_4540;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_180 <= _GEN_4540;
- end else if (3'h3 == fstate) begin
- valid_180 <= _GEN_6347;
- end else begin
- valid_180 <= _GEN_8146;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_181 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_181 <= _GEN_4541;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_181 <= _GEN_4541;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_181 <= _GEN_4541;
- end else if (3'h3 == fstate) begin
- valid_181 <= _GEN_6348;
- end else begin
- valid_181 <= _GEN_8147;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_182 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_182 <= _GEN_4542;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_182 <= _GEN_4542;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_182 <= _GEN_4542;
- end else if (3'h3 == fstate) begin
- valid_182 <= _GEN_6349;
- end else begin
- valid_182 <= _GEN_8148;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_183 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_183 <= _GEN_4543;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_183 <= _GEN_4543;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_183 <= _GEN_4543;
- end else if (3'h3 == fstate) begin
- valid_183 <= _GEN_6350;
- end else begin
- valid_183 <= _GEN_8149;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_184 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_184 <= _GEN_4544;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_184 <= _GEN_4544;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_184 <= _GEN_4544;
- end else if (3'h3 == fstate) begin
- valid_184 <= _GEN_6351;
- end else begin
- valid_184 <= _GEN_8150;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_185 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_185 <= _GEN_4545;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_185 <= _GEN_4545;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_185 <= _GEN_4545;
- end else if (3'h3 == fstate) begin
- valid_185 <= _GEN_6352;
- end else begin
- valid_185 <= _GEN_8151;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_186 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_186 <= _GEN_4546;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_186 <= _GEN_4546;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_186 <= _GEN_4546;
- end else if (3'h3 == fstate) begin
- valid_186 <= _GEN_6353;
- end else begin
- valid_186 <= _GEN_8152;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_187 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_187 <= _GEN_4547;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_187 <= _GEN_4547;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_187 <= _GEN_4547;
- end else if (3'h3 == fstate) begin
- valid_187 <= _GEN_6354;
- end else begin
- valid_187 <= _GEN_8153;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_188 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_188 <= _GEN_4548;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_188 <= _GEN_4548;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_188 <= _GEN_4548;
- end else if (3'h3 == fstate) begin
- valid_188 <= _GEN_6355;
- end else begin
- valid_188 <= _GEN_8154;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_189 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_189 <= _GEN_4549;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_189 <= _GEN_4549;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_189 <= _GEN_4549;
- end else if (3'h3 == fstate) begin
- valid_189 <= _GEN_6356;
- end else begin
- valid_189 <= _GEN_8155;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_190 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_190 <= _GEN_4550;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_190 <= _GEN_4550;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_190 <= _GEN_4550;
- end else if (3'h3 == fstate) begin
- valid_190 <= _GEN_6357;
- end else begin
- valid_190 <= _GEN_8156;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_191 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_191 <= _GEN_4551;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_191 <= _GEN_4551;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_191 <= _GEN_4551;
- end else if (3'h3 == fstate) begin
- valid_191 <= _GEN_6358;
- end else begin
- valid_191 <= _GEN_8157;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_192 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_192 <= _GEN_4552;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_192 <= _GEN_4552;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_192 <= _GEN_4552;
- end else if (3'h3 == fstate) begin
- valid_192 <= _GEN_6359;
- end else begin
- valid_192 <= _GEN_8158;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_193 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_193 <= _GEN_4553;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_193 <= _GEN_4553;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_193 <= _GEN_4553;
- end else if (3'h3 == fstate) begin
- valid_193 <= _GEN_6360;
- end else begin
- valid_193 <= _GEN_8159;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_194 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_194 <= _GEN_4554;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_194 <= _GEN_4554;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_194 <= _GEN_4554;
- end else if (3'h3 == fstate) begin
- valid_194 <= _GEN_6361;
- end else begin
- valid_194 <= _GEN_8160;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_195 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_195 <= _GEN_4555;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_195 <= _GEN_4555;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_195 <= _GEN_4555;
- end else if (3'h3 == fstate) begin
- valid_195 <= _GEN_6362;
- end else begin
- valid_195 <= _GEN_8161;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_196 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_196 <= _GEN_4556;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_196 <= _GEN_4556;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_196 <= _GEN_4556;
- end else if (3'h3 == fstate) begin
- valid_196 <= _GEN_6363;
- end else begin
- valid_196 <= _GEN_8162;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_197 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_197 <= _GEN_4557;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_197 <= _GEN_4557;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_197 <= _GEN_4557;
- end else if (3'h3 == fstate) begin
- valid_197 <= _GEN_6364;
- end else begin
- valid_197 <= _GEN_8163;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_198 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_198 <= _GEN_4558;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_198 <= _GEN_4558;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_198 <= _GEN_4558;
- end else if (3'h3 == fstate) begin
- valid_198 <= _GEN_6365;
- end else begin
- valid_198 <= _GEN_8164;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_199 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_199 <= _GEN_4559;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_199 <= _GEN_4559;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_199 <= _GEN_4559;
- end else if (3'h3 == fstate) begin
- valid_199 <= _GEN_6366;
- end else begin
- valid_199 <= _GEN_8165;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_200 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_200 <= _GEN_4560;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_200 <= _GEN_4560;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_200 <= _GEN_4560;
- end else if (3'h3 == fstate) begin
- valid_200 <= _GEN_6367;
- end else begin
- valid_200 <= _GEN_8166;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_201 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_201 <= _GEN_4561;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_201 <= _GEN_4561;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_201 <= _GEN_4561;
- end else if (3'h3 == fstate) begin
- valid_201 <= _GEN_6368;
- end else begin
- valid_201 <= _GEN_8167;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_202 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_202 <= _GEN_4562;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_202 <= _GEN_4562;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_202 <= _GEN_4562;
- end else if (3'h3 == fstate) begin
- valid_202 <= _GEN_6369;
- end else begin
- valid_202 <= _GEN_8168;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_203 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_203 <= _GEN_4563;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_203 <= _GEN_4563;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_203 <= _GEN_4563;
- end else if (3'h3 == fstate) begin
- valid_203 <= _GEN_6370;
- end else begin
- valid_203 <= _GEN_8169;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_204 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_204 <= _GEN_4564;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_204 <= _GEN_4564;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_204 <= _GEN_4564;
- end else if (3'h3 == fstate) begin
- valid_204 <= _GEN_6371;
- end else begin
- valid_204 <= _GEN_8170;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_205 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_205 <= _GEN_4565;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_205 <= _GEN_4565;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_205 <= _GEN_4565;
- end else if (3'h3 == fstate) begin
- valid_205 <= _GEN_6372;
- end else begin
- valid_205 <= _GEN_8171;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_206 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_206 <= _GEN_4566;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_206 <= _GEN_4566;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_206 <= _GEN_4566;
- end else if (3'h3 == fstate) begin
- valid_206 <= _GEN_6373;
- end else begin
- valid_206 <= _GEN_8172;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_207 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_207 <= _GEN_4567;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_207 <= _GEN_4567;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_207 <= _GEN_4567;
- end else if (3'h3 == fstate) begin
- valid_207 <= _GEN_6374;
- end else begin
- valid_207 <= _GEN_8173;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_208 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_208 <= _GEN_4568;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_208 <= _GEN_4568;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_208 <= _GEN_4568;
- end else if (3'h3 == fstate) begin
- valid_208 <= _GEN_6375;
- end else begin
- valid_208 <= _GEN_8174;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_209 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_209 <= _GEN_4569;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_209 <= _GEN_4569;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_209 <= _GEN_4569;
- end else if (3'h3 == fstate) begin
- valid_209 <= _GEN_6376;
- end else begin
- valid_209 <= _GEN_8175;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_210 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_210 <= _GEN_4570;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_210 <= _GEN_4570;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_210 <= _GEN_4570;
- end else if (3'h3 == fstate) begin
- valid_210 <= _GEN_6377;
- end else begin
- valid_210 <= _GEN_8176;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_211 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_211 <= _GEN_4571;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_211 <= _GEN_4571;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_211 <= _GEN_4571;
- end else if (3'h3 == fstate) begin
- valid_211 <= _GEN_6378;
- end else begin
- valid_211 <= _GEN_8177;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_212 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_212 <= _GEN_4572;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_212 <= _GEN_4572;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_212 <= _GEN_4572;
- end else if (3'h3 == fstate) begin
- valid_212 <= _GEN_6379;
- end else begin
- valid_212 <= _GEN_8178;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_213 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_213 <= _GEN_4573;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_213 <= _GEN_4573;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_213 <= _GEN_4573;
- end else if (3'h3 == fstate) begin
- valid_213 <= _GEN_6380;
- end else begin
- valid_213 <= _GEN_8179;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_214 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_214 <= _GEN_4574;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_214 <= _GEN_4574;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_214 <= _GEN_4574;
- end else if (3'h3 == fstate) begin
- valid_214 <= _GEN_6381;
- end else begin
- valid_214 <= _GEN_8180;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_215 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_215 <= _GEN_4575;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_215 <= _GEN_4575;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_215 <= _GEN_4575;
- end else if (3'h3 == fstate) begin
- valid_215 <= _GEN_6382;
- end else begin
- valid_215 <= _GEN_8181;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_216 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_216 <= _GEN_4576;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_216 <= _GEN_4576;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_216 <= _GEN_4576;
- end else if (3'h3 == fstate) begin
- valid_216 <= _GEN_6383;
- end else begin
- valid_216 <= _GEN_8182;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_217 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_217 <= _GEN_4577;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_217 <= _GEN_4577;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_217 <= _GEN_4577;
- end else if (3'h3 == fstate) begin
- valid_217 <= _GEN_6384;
- end else begin
- valid_217 <= _GEN_8183;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_218 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_218 <= _GEN_4578;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_218 <= _GEN_4578;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_218 <= _GEN_4578;
- end else if (3'h3 == fstate) begin
- valid_218 <= _GEN_6385;
- end else begin
- valid_218 <= _GEN_8184;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_219 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_219 <= _GEN_4579;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_219 <= _GEN_4579;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_219 <= _GEN_4579;
- end else if (3'h3 == fstate) begin
- valid_219 <= _GEN_6386;
- end else begin
- valid_219 <= _GEN_8185;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_220 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_220 <= _GEN_4580;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_220 <= _GEN_4580;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_220 <= _GEN_4580;
- end else if (3'h3 == fstate) begin
- valid_220 <= _GEN_6387;
- end else begin
- valid_220 <= _GEN_8186;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_221 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_221 <= _GEN_4581;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_221 <= _GEN_4581;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_221 <= _GEN_4581;
- end else if (3'h3 == fstate) begin
- valid_221 <= _GEN_6388;
- end else begin
- valid_221 <= _GEN_8187;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_222 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_222 <= _GEN_4582;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_222 <= _GEN_4582;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_222 <= _GEN_4582;
- end else if (3'h3 == fstate) begin
- valid_222 <= _GEN_6389;
- end else begin
- valid_222 <= _GEN_8188;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_223 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_223 <= _GEN_4583;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_223 <= _GEN_4583;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_223 <= _GEN_4583;
- end else if (3'h3 == fstate) begin
- valid_223 <= _GEN_6390;
- end else begin
- valid_223 <= _GEN_8189;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_224 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_224 <= _GEN_4584;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_224 <= _GEN_4584;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_224 <= _GEN_4584;
- end else if (3'h3 == fstate) begin
- valid_224 <= _GEN_6391;
- end else begin
- valid_224 <= _GEN_8190;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_225 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_225 <= _GEN_4585;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_225 <= _GEN_4585;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_225 <= _GEN_4585;
- end else if (3'h3 == fstate) begin
- valid_225 <= _GEN_6392;
- end else begin
- valid_225 <= _GEN_8191;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_226 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_226 <= _GEN_4586;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_226 <= _GEN_4586;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_226 <= _GEN_4586;
- end else if (3'h3 == fstate) begin
- valid_226 <= _GEN_6393;
- end else begin
- valid_226 <= _GEN_8192;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_227 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_227 <= _GEN_4587;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_227 <= _GEN_4587;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_227 <= _GEN_4587;
- end else if (3'h3 == fstate) begin
- valid_227 <= _GEN_6394;
- end else begin
- valid_227 <= _GEN_8193;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_228 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_228 <= _GEN_4588;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_228 <= _GEN_4588;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_228 <= _GEN_4588;
- end else if (3'h3 == fstate) begin
- valid_228 <= _GEN_6395;
- end else begin
- valid_228 <= _GEN_8194;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_229 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_229 <= _GEN_4589;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_229 <= _GEN_4589;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_229 <= _GEN_4589;
- end else if (3'h3 == fstate) begin
- valid_229 <= _GEN_6396;
- end else begin
- valid_229 <= _GEN_8195;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_230 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_230 <= _GEN_4590;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_230 <= _GEN_4590;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_230 <= _GEN_4590;
- end else if (3'h3 == fstate) begin
- valid_230 <= _GEN_6397;
- end else begin
- valid_230 <= _GEN_8196;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_231 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_231 <= _GEN_4591;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_231 <= _GEN_4591;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_231 <= _GEN_4591;
- end else if (3'h3 == fstate) begin
- valid_231 <= _GEN_6398;
- end else begin
- valid_231 <= _GEN_8197;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_232 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_232 <= _GEN_4592;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_232 <= _GEN_4592;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_232 <= _GEN_4592;
- end else if (3'h3 == fstate) begin
- valid_232 <= _GEN_6399;
- end else begin
- valid_232 <= _GEN_8198;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_233 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_233 <= _GEN_4593;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_233 <= _GEN_4593;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_233 <= _GEN_4593;
- end else if (3'h3 == fstate) begin
- valid_233 <= _GEN_6400;
- end else begin
- valid_233 <= _GEN_8199;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_234 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_234 <= _GEN_4594;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_234 <= _GEN_4594;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_234 <= _GEN_4594;
- end else if (3'h3 == fstate) begin
- valid_234 <= _GEN_6401;
- end else begin
- valid_234 <= _GEN_8200;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_235 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_235 <= _GEN_4595;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_235 <= _GEN_4595;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_235 <= _GEN_4595;
- end else if (3'h3 == fstate) begin
- valid_235 <= _GEN_6402;
- end else begin
- valid_235 <= _GEN_8201;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_236 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_236 <= _GEN_4596;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_236 <= _GEN_4596;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_236 <= _GEN_4596;
- end else if (3'h3 == fstate) begin
- valid_236 <= _GEN_6403;
- end else begin
- valid_236 <= _GEN_8202;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_237 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_237 <= _GEN_4597;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_237 <= _GEN_4597;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_237 <= _GEN_4597;
- end else if (3'h3 == fstate) begin
- valid_237 <= _GEN_6404;
- end else begin
- valid_237 <= _GEN_8203;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_238 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_238 <= _GEN_4598;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_238 <= _GEN_4598;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_238 <= _GEN_4598;
- end else if (3'h3 == fstate) begin
- valid_238 <= _GEN_6405;
- end else begin
- valid_238 <= _GEN_8204;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_239 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_239 <= _GEN_4599;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_239 <= _GEN_4599;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_239 <= _GEN_4599;
- end else if (3'h3 == fstate) begin
- valid_239 <= _GEN_6406;
- end else begin
- valid_239 <= _GEN_8205;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_240 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_240 <= _GEN_4600;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_240 <= _GEN_4600;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_240 <= _GEN_4600;
- end else if (3'h3 == fstate) begin
- valid_240 <= _GEN_6407;
- end else begin
- valid_240 <= _GEN_8206;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_241 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_241 <= _GEN_4601;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_241 <= _GEN_4601;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_241 <= _GEN_4601;
- end else if (3'h3 == fstate) begin
- valid_241 <= _GEN_6408;
- end else begin
- valid_241 <= _GEN_8207;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_242 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_242 <= _GEN_4602;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_242 <= _GEN_4602;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_242 <= _GEN_4602;
- end else if (3'h3 == fstate) begin
- valid_242 <= _GEN_6409;
- end else begin
- valid_242 <= _GEN_8208;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_243 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_243 <= _GEN_4603;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_243 <= _GEN_4603;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_243 <= _GEN_4603;
- end else if (3'h3 == fstate) begin
- valid_243 <= _GEN_6410;
- end else begin
- valid_243 <= _GEN_8209;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_244 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_244 <= _GEN_4604;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_244 <= _GEN_4604;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_244 <= _GEN_4604;
- end else if (3'h3 == fstate) begin
- valid_244 <= _GEN_6411;
- end else begin
- valid_244 <= _GEN_8210;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_245 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_245 <= _GEN_4605;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_245 <= _GEN_4605;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_245 <= _GEN_4605;
- end else if (3'h3 == fstate) begin
- valid_245 <= _GEN_6412;
- end else begin
- valid_245 <= _GEN_8211;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_246 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_246 <= _GEN_4606;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_246 <= _GEN_4606;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_246 <= _GEN_4606;
- end else if (3'h3 == fstate) begin
- valid_246 <= _GEN_6413;
- end else begin
- valid_246 <= _GEN_8212;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_247 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_247 <= _GEN_4607;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_247 <= _GEN_4607;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_247 <= _GEN_4607;
- end else if (3'h3 == fstate) begin
- valid_247 <= _GEN_6414;
- end else begin
- valid_247 <= _GEN_8213;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_248 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_248 <= _GEN_4608;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_248 <= _GEN_4608;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_248 <= _GEN_4608;
- end else if (3'h3 == fstate) begin
- valid_248 <= _GEN_6415;
- end else begin
- valid_248 <= _GEN_8214;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_249 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_249 <= _GEN_4609;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_249 <= _GEN_4609;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_249 <= _GEN_4609;
- end else if (3'h3 == fstate) begin
- valid_249 <= _GEN_6416;
- end else begin
- valid_249 <= _GEN_8215;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_250 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_250 <= _GEN_4610;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_250 <= _GEN_4610;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_250 <= _GEN_4610;
- end else if (3'h3 == fstate) begin
- valid_250 <= _GEN_6417;
- end else begin
- valid_250 <= _GEN_8216;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_251 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_251 <= _GEN_4611;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_251 <= _GEN_4611;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_251 <= _GEN_4611;
- end else if (3'h3 == fstate) begin
- valid_251 <= _GEN_6418;
- end else begin
- valid_251 <= _GEN_8217;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_252 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_252 <= _GEN_4612;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_252 <= _GEN_4612;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_252 <= _GEN_4612;
- end else if (3'h3 == fstate) begin
- valid_252 <= _GEN_6419;
- end else begin
- valid_252 <= _GEN_8218;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_253 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_253 <= _GEN_4613;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_253 <= _GEN_4613;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_253 <= _GEN_4613;
- end else if (3'h3 == fstate) begin
- valid_253 <= _GEN_6420;
- end else begin
- valid_253 <= _GEN_8219;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_254 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_254 <= _GEN_4614;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_254 <= _GEN_4614;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_254 <= _GEN_4614;
- end else if (3'h3 == fstate) begin
- valid_254 <= _GEN_6421;
- end else begin
- valid_254 <= _GEN_8220;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- valid_255 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- valid_255 <= _GEN_4615;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- valid_255 <= _GEN_4615;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- valid_255 <= _GEN_4615;
- end else if (3'h3 == fstate) begin
- valid_255 <= _GEN_6422;
- end else begin
- valid_255 <= _GEN_8221;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_0 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_0 <= _GEN_3847;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_0 <= _GEN_3847;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_0 <= _GEN_3847;
- end else if (3'h3 == fstate) begin
- dirty_0 <= _GEN_5911;
- end else begin
- dirty_0 <= _GEN_3847;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_1 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_1 <= _GEN_3848;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_1 <= _GEN_3848;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_1 <= _GEN_3848;
- end else if (3'h3 == fstate) begin
- dirty_1 <= _GEN_5912;
- end else begin
- dirty_1 <= _GEN_3848;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_2 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_2 <= _GEN_3849;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_2 <= _GEN_3849;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_2 <= _GEN_3849;
- end else if (3'h3 == fstate) begin
- dirty_2 <= _GEN_5913;
- end else begin
- dirty_2 <= _GEN_3849;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_3 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_3 <= _GEN_3850;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_3 <= _GEN_3850;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_3 <= _GEN_3850;
- end else if (3'h3 == fstate) begin
- dirty_3 <= _GEN_5914;
- end else begin
- dirty_3 <= _GEN_3850;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_4 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_4 <= _GEN_3851;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_4 <= _GEN_3851;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_4 <= _GEN_3851;
- end else if (3'h3 == fstate) begin
- dirty_4 <= _GEN_5915;
- end else begin
- dirty_4 <= _GEN_3851;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_5 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_5 <= _GEN_3852;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_5 <= _GEN_3852;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_5 <= _GEN_3852;
- end else if (3'h3 == fstate) begin
- dirty_5 <= _GEN_5916;
- end else begin
- dirty_5 <= _GEN_3852;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_6 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_6 <= _GEN_3853;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_6 <= _GEN_3853;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_6 <= _GEN_3853;
- end else if (3'h3 == fstate) begin
- dirty_6 <= _GEN_5917;
- end else begin
- dirty_6 <= _GEN_3853;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_7 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_7 <= _GEN_3854;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_7 <= _GEN_3854;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_7 <= _GEN_3854;
- end else if (3'h3 == fstate) begin
- dirty_7 <= _GEN_5918;
- end else begin
- dirty_7 <= _GEN_3854;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_8 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_8 <= _GEN_3855;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_8 <= _GEN_3855;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_8 <= _GEN_3855;
- end else if (3'h3 == fstate) begin
- dirty_8 <= _GEN_5919;
- end else begin
- dirty_8 <= _GEN_3855;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_9 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_9 <= _GEN_3856;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_9 <= _GEN_3856;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_9 <= _GEN_3856;
- end else if (3'h3 == fstate) begin
- dirty_9 <= _GEN_5920;
- end else begin
- dirty_9 <= _GEN_3856;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_10 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_10 <= _GEN_3857;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_10 <= _GEN_3857;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_10 <= _GEN_3857;
- end else if (3'h3 == fstate) begin
- dirty_10 <= _GEN_5921;
- end else begin
- dirty_10 <= _GEN_3857;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_11 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_11 <= _GEN_3858;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_11 <= _GEN_3858;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_11 <= _GEN_3858;
- end else if (3'h3 == fstate) begin
- dirty_11 <= _GEN_5922;
- end else begin
- dirty_11 <= _GEN_3858;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_12 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_12 <= _GEN_3859;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_12 <= _GEN_3859;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_12 <= _GEN_3859;
- end else if (3'h3 == fstate) begin
- dirty_12 <= _GEN_5923;
- end else begin
- dirty_12 <= _GEN_3859;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_13 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_13 <= _GEN_3860;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_13 <= _GEN_3860;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_13 <= _GEN_3860;
- end else if (3'h3 == fstate) begin
- dirty_13 <= _GEN_5924;
- end else begin
- dirty_13 <= _GEN_3860;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_14 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_14 <= _GEN_3861;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_14 <= _GEN_3861;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_14 <= _GEN_3861;
- end else if (3'h3 == fstate) begin
- dirty_14 <= _GEN_5925;
- end else begin
- dirty_14 <= _GEN_3861;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_15 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_15 <= _GEN_3862;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_15 <= _GEN_3862;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_15 <= _GEN_3862;
- end else if (3'h3 == fstate) begin
- dirty_15 <= _GEN_5926;
- end else begin
- dirty_15 <= _GEN_3862;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_16 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_16 <= _GEN_3863;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_16 <= _GEN_3863;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_16 <= _GEN_3863;
- end else if (3'h3 == fstate) begin
- dirty_16 <= _GEN_5927;
- end else begin
- dirty_16 <= _GEN_3863;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_17 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_17 <= _GEN_3864;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_17 <= _GEN_3864;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_17 <= _GEN_3864;
- end else if (3'h3 == fstate) begin
- dirty_17 <= _GEN_5928;
- end else begin
- dirty_17 <= _GEN_3864;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_18 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_18 <= _GEN_3865;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_18 <= _GEN_3865;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_18 <= _GEN_3865;
- end else if (3'h3 == fstate) begin
- dirty_18 <= _GEN_5929;
- end else begin
- dirty_18 <= _GEN_3865;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_19 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_19 <= _GEN_3866;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_19 <= _GEN_3866;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_19 <= _GEN_3866;
- end else if (3'h3 == fstate) begin
- dirty_19 <= _GEN_5930;
- end else begin
- dirty_19 <= _GEN_3866;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_20 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_20 <= _GEN_3867;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_20 <= _GEN_3867;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_20 <= _GEN_3867;
- end else if (3'h3 == fstate) begin
- dirty_20 <= _GEN_5931;
- end else begin
- dirty_20 <= _GEN_3867;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_21 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_21 <= _GEN_3868;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_21 <= _GEN_3868;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_21 <= _GEN_3868;
- end else if (3'h3 == fstate) begin
- dirty_21 <= _GEN_5932;
- end else begin
- dirty_21 <= _GEN_3868;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_22 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_22 <= _GEN_3869;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_22 <= _GEN_3869;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_22 <= _GEN_3869;
- end else if (3'h3 == fstate) begin
- dirty_22 <= _GEN_5933;
- end else begin
- dirty_22 <= _GEN_3869;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_23 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_23 <= _GEN_3870;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_23 <= _GEN_3870;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_23 <= _GEN_3870;
- end else if (3'h3 == fstate) begin
- dirty_23 <= _GEN_5934;
- end else begin
- dirty_23 <= _GEN_3870;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_24 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_24 <= _GEN_3871;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_24 <= _GEN_3871;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_24 <= _GEN_3871;
- end else if (3'h3 == fstate) begin
- dirty_24 <= _GEN_5935;
- end else begin
- dirty_24 <= _GEN_3871;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_25 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_25 <= _GEN_3872;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_25 <= _GEN_3872;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_25 <= _GEN_3872;
- end else if (3'h3 == fstate) begin
- dirty_25 <= _GEN_5936;
- end else begin
- dirty_25 <= _GEN_3872;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_26 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_26 <= _GEN_3873;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_26 <= _GEN_3873;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_26 <= _GEN_3873;
- end else if (3'h3 == fstate) begin
- dirty_26 <= _GEN_5937;
- end else begin
- dirty_26 <= _GEN_3873;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_27 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_27 <= _GEN_3874;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_27 <= _GEN_3874;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_27 <= _GEN_3874;
- end else if (3'h3 == fstate) begin
- dirty_27 <= _GEN_5938;
- end else begin
- dirty_27 <= _GEN_3874;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_28 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_28 <= _GEN_3875;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_28 <= _GEN_3875;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_28 <= _GEN_3875;
- end else if (3'h3 == fstate) begin
- dirty_28 <= _GEN_5939;
- end else begin
- dirty_28 <= _GEN_3875;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_29 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_29 <= _GEN_3876;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_29 <= _GEN_3876;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_29 <= _GEN_3876;
- end else if (3'h3 == fstate) begin
- dirty_29 <= _GEN_5940;
- end else begin
- dirty_29 <= _GEN_3876;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_30 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_30 <= _GEN_3877;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_30 <= _GEN_3877;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_30 <= _GEN_3877;
- end else if (3'h3 == fstate) begin
- dirty_30 <= _GEN_5941;
- end else begin
- dirty_30 <= _GEN_3877;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_31 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_31 <= _GEN_3878;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_31 <= _GEN_3878;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_31 <= _GEN_3878;
- end else if (3'h3 == fstate) begin
- dirty_31 <= _GEN_5942;
- end else begin
- dirty_31 <= _GEN_3878;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_32 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_32 <= _GEN_3879;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_32 <= _GEN_3879;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_32 <= _GEN_3879;
- end else if (3'h3 == fstate) begin
- dirty_32 <= _GEN_5943;
- end else begin
- dirty_32 <= _GEN_3879;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_33 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_33 <= _GEN_3880;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_33 <= _GEN_3880;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_33 <= _GEN_3880;
- end else if (3'h3 == fstate) begin
- dirty_33 <= _GEN_5944;
- end else begin
- dirty_33 <= _GEN_3880;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_34 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_34 <= _GEN_3881;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_34 <= _GEN_3881;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_34 <= _GEN_3881;
- end else if (3'h3 == fstate) begin
- dirty_34 <= _GEN_5945;
- end else begin
- dirty_34 <= _GEN_3881;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_35 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_35 <= _GEN_3882;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_35 <= _GEN_3882;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_35 <= _GEN_3882;
- end else if (3'h3 == fstate) begin
- dirty_35 <= _GEN_5946;
- end else begin
- dirty_35 <= _GEN_3882;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_36 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_36 <= _GEN_3883;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_36 <= _GEN_3883;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_36 <= _GEN_3883;
- end else if (3'h3 == fstate) begin
- dirty_36 <= _GEN_5947;
- end else begin
- dirty_36 <= _GEN_3883;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_37 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_37 <= _GEN_3884;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_37 <= _GEN_3884;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_37 <= _GEN_3884;
- end else if (3'h3 == fstate) begin
- dirty_37 <= _GEN_5948;
- end else begin
- dirty_37 <= _GEN_3884;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_38 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_38 <= _GEN_3885;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_38 <= _GEN_3885;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_38 <= _GEN_3885;
- end else if (3'h3 == fstate) begin
- dirty_38 <= _GEN_5949;
- end else begin
- dirty_38 <= _GEN_3885;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_39 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_39 <= _GEN_3886;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_39 <= _GEN_3886;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_39 <= _GEN_3886;
- end else if (3'h3 == fstate) begin
- dirty_39 <= _GEN_5950;
- end else begin
- dirty_39 <= _GEN_3886;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_40 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_40 <= _GEN_3887;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_40 <= _GEN_3887;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_40 <= _GEN_3887;
- end else if (3'h3 == fstate) begin
- dirty_40 <= _GEN_5951;
- end else begin
- dirty_40 <= _GEN_3887;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_41 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_41 <= _GEN_3888;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_41 <= _GEN_3888;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_41 <= _GEN_3888;
- end else if (3'h3 == fstate) begin
- dirty_41 <= _GEN_5952;
- end else begin
- dirty_41 <= _GEN_3888;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_42 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_42 <= _GEN_3889;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_42 <= _GEN_3889;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_42 <= _GEN_3889;
- end else if (3'h3 == fstate) begin
- dirty_42 <= _GEN_5953;
- end else begin
- dirty_42 <= _GEN_3889;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_43 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_43 <= _GEN_3890;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_43 <= _GEN_3890;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_43 <= _GEN_3890;
- end else if (3'h3 == fstate) begin
- dirty_43 <= _GEN_5954;
- end else begin
- dirty_43 <= _GEN_3890;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_44 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_44 <= _GEN_3891;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_44 <= _GEN_3891;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_44 <= _GEN_3891;
- end else if (3'h3 == fstate) begin
- dirty_44 <= _GEN_5955;
- end else begin
- dirty_44 <= _GEN_3891;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_45 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_45 <= _GEN_3892;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_45 <= _GEN_3892;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_45 <= _GEN_3892;
- end else if (3'h3 == fstate) begin
- dirty_45 <= _GEN_5956;
- end else begin
- dirty_45 <= _GEN_3892;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_46 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_46 <= _GEN_3893;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_46 <= _GEN_3893;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_46 <= _GEN_3893;
- end else if (3'h3 == fstate) begin
- dirty_46 <= _GEN_5957;
- end else begin
- dirty_46 <= _GEN_3893;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_47 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_47 <= _GEN_3894;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_47 <= _GEN_3894;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_47 <= _GEN_3894;
- end else if (3'h3 == fstate) begin
- dirty_47 <= _GEN_5958;
- end else begin
- dirty_47 <= _GEN_3894;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_48 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_48 <= _GEN_3895;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_48 <= _GEN_3895;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_48 <= _GEN_3895;
- end else if (3'h3 == fstate) begin
- dirty_48 <= _GEN_5959;
- end else begin
- dirty_48 <= _GEN_3895;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_49 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_49 <= _GEN_3896;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_49 <= _GEN_3896;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_49 <= _GEN_3896;
- end else if (3'h3 == fstate) begin
- dirty_49 <= _GEN_5960;
- end else begin
- dirty_49 <= _GEN_3896;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_50 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_50 <= _GEN_3897;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_50 <= _GEN_3897;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_50 <= _GEN_3897;
- end else if (3'h3 == fstate) begin
- dirty_50 <= _GEN_5961;
- end else begin
- dirty_50 <= _GEN_3897;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_51 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_51 <= _GEN_3898;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_51 <= _GEN_3898;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_51 <= _GEN_3898;
- end else if (3'h3 == fstate) begin
- dirty_51 <= _GEN_5962;
- end else begin
- dirty_51 <= _GEN_3898;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_52 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_52 <= _GEN_3899;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_52 <= _GEN_3899;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_52 <= _GEN_3899;
- end else if (3'h3 == fstate) begin
- dirty_52 <= _GEN_5963;
- end else begin
- dirty_52 <= _GEN_3899;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_53 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_53 <= _GEN_3900;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_53 <= _GEN_3900;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_53 <= _GEN_3900;
- end else if (3'h3 == fstate) begin
- dirty_53 <= _GEN_5964;
- end else begin
- dirty_53 <= _GEN_3900;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_54 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_54 <= _GEN_3901;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_54 <= _GEN_3901;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_54 <= _GEN_3901;
- end else if (3'h3 == fstate) begin
- dirty_54 <= _GEN_5965;
- end else begin
- dirty_54 <= _GEN_3901;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_55 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_55 <= _GEN_3902;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_55 <= _GEN_3902;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_55 <= _GEN_3902;
- end else if (3'h3 == fstate) begin
- dirty_55 <= _GEN_5966;
- end else begin
- dirty_55 <= _GEN_3902;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_56 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_56 <= _GEN_3903;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_56 <= _GEN_3903;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_56 <= _GEN_3903;
- end else if (3'h3 == fstate) begin
- dirty_56 <= _GEN_5967;
- end else begin
- dirty_56 <= _GEN_3903;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_57 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_57 <= _GEN_3904;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_57 <= _GEN_3904;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_57 <= _GEN_3904;
- end else if (3'h3 == fstate) begin
- dirty_57 <= _GEN_5968;
- end else begin
- dirty_57 <= _GEN_3904;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_58 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_58 <= _GEN_3905;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_58 <= _GEN_3905;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_58 <= _GEN_3905;
- end else if (3'h3 == fstate) begin
- dirty_58 <= _GEN_5969;
- end else begin
- dirty_58 <= _GEN_3905;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_59 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_59 <= _GEN_3906;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_59 <= _GEN_3906;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_59 <= _GEN_3906;
- end else if (3'h3 == fstate) begin
- dirty_59 <= _GEN_5970;
- end else begin
- dirty_59 <= _GEN_3906;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_60 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_60 <= _GEN_3907;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_60 <= _GEN_3907;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_60 <= _GEN_3907;
- end else if (3'h3 == fstate) begin
- dirty_60 <= _GEN_5971;
- end else begin
- dirty_60 <= _GEN_3907;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_61 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_61 <= _GEN_3908;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_61 <= _GEN_3908;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_61 <= _GEN_3908;
- end else if (3'h3 == fstate) begin
- dirty_61 <= _GEN_5972;
- end else begin
- dirty_61 <= _GEN_3908;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_62 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_62 <= _GEN_3909;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_62 <= _GEN_3909;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_62 <= _GEN_3909;
- end else if (3'h3 == fstate) begin
- dirty_62 <= _GEN_5973;
- end else begin
- dirty_62 <= _GEN_3909;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_63 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_63 <= _GEN_3910;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_63 <= _GEN_3910;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_63 <= _GEN_3910;
- end else if (3'h3 == fstate) begin
- dirty_63 <= _GEN_5974;
- end else begin
- dirty_63 <= _GEN_3910;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_64 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_64 <= _GEN_3911;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_64 <= _GEN_3911;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_64 <= _GEN_3911;
- end else if (3'h3 == fstate) begin
- dirty_64 <= _GEN_5975;
- end else begin
- dirty_64 <= _GEN_3911;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_65 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_65 <= _GEN_3912;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_65 <= _GEN_3912;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_65 <= _GEN_3912;
- end else if (3'h3 == fstate) begin
- dirty_65 <= _GEN_5976;
- end else begin
- dirty_65 <= _GEN_3912;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_66 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_66 <= _GEN_3913;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_66 <= _GEN_3913;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_66 <= _GEN_3913;
- end else if (3'h3 == fstate) begin
- dirty_66 <= _GEN_5977;
- end else begin
- dirty_66 <= _GEN_3913;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_67 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_67 <= _GEN_3914;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_67 <= _GEN_3914;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_67 <= _GEN_3914;
- end else if (3'h3 == fstate) begin
- dirty_67 <= _GEN_5978;
- end else begin
- dirty_67 <= _GEN_3914;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_68 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_68 <= _GEN_3915;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_68 <= _GEN_3915;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_68 <= _GEN_3915;
- end else if (3'h3 == fstate) begin
- dirty_68 <= _GEN_5979;
- end else begin
- dirty_68 <= _GEN_3915;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_69 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_69 <= _GEN_3916;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_69 <= _GEN_3916;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_69 <= _GEN_3916;
- end else if (3'h3 == fstate) begin
- dirty_69 <= _GEN_5980;
- end else begin
- dirty_69 <= _GEN_3916;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_70 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_70 <= _GEN_3917;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_70 <= _GEN_3917;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_70 <= _GEN_3917;
- end else if (3'h3 == fstate) begin
- dirty_70 <= _GEN_5981;
- end else begin
- dirty_70 <= _GEN_3917;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_71 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_71 <= _GEN_3918;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_71 <= _GEN_3918;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_71 <= _GEN_3918;
- end else if (3'h3 == fstate) begin
- dirty_71 <= _GEN_5982;
- end else begin
- dirty_71 <= _GEN_3918;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_72 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_72 <= _GEN_3919;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_72 <= _GEN_3919;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_72 <= _GEN_3919;
- end else if (3'h3 == fstate) begin
- dirty_72 <= _GEN_5983;
- end else begin
- dirty_72 <= _GEN_3919;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_73 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_73 <= _GEN_3920;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_73 <= _GEN_3920;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_73 <= _GEN_3920;
- end else if (3'h3 == fstate) begin
- dirty_73 <= _GEN_5984;
- end else begin
- dirty_73 <= _GEN_3920;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_74 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_74 <= _GEN_3921;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_74 <= _GEN_3921;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_74 <= _GEN_3921;
- end else if (3'h3 == fstate) begin
- dirty_74 <= _GEN_5985;
- end else begin
- dirty_74 <= _GEN_3921;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_75 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_75 <= _GEN_3922;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_75 <= _GEN_3922;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_75 <= _GEN_3922;
- end else if (3'h3 == fstate) begin
- dirty_75 <= _GEN_5986;
- end else begin
- dirty_75 <= _GEN_3922;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_76 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_76 <= _GEN_3923;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_76 <= _GEN_3923;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_76 <= _GEN_3923;
- end else if (3'h3 == fstate) begin
- dirty_76 <= _GEN_5987;
- end else begin
- dirty_76 <= _GEN_3923;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_77 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_77 <= _GEN_3924;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_77 <= _GEN_3924;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_77 <= _GEN_3924;
- end else if (3'h3 == fstate) begin
- dirty_77 <= _GEN_5988;
- end else begin
- dirty_77 <= _GEN_3924;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_78 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_78 <= _GEN_3925;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_78 <= _GEN_3925;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_78 <= _GEN_3925;
- end else if (3'h3 == fstate) begin
- dirty_78 <= _GEN_5989;
- end else begin
- dirty_78 <= _GEN_3925;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_79 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_79 <= _GEN_3926;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_79 <= _GEN_3926;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_79 <= _GEN_3926;
- end else if (3'h3 == fstate) begin
- dirty_79 <= _GEN_5990;
- end else begin
- dirty_79 <= _GEN_3926;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_80 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_80 <= _GEN_3927;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_80 <= _GEN_3927;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_80 <= _GEN_3927;
- end else if (3'h3 == fstate) begin
- dirty_80 <= _GEN_5991;
- end else begin
- dirty_80 <= _GEN_3927;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_81 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_81 <= _GEN_3928;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_81 <= _GEN_3928;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_81 <= _GEN_3928;
- end else if (3'h3 == fstate) begin
- dirty_81 <= _GEN_5992;
- end else begin
- dirty_81 <= _GEN_3928;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_82 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_82 <= _GEN_3929;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_82 <= _GEN_3929;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_82 <= _GEN_3929;
- end else if (3'h3 == fstate) begin
- dirty_82 <= _GEN_5993;
- end else begin
- dirty_82 <= _GEN_3929;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_83 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_83 <= _GEN_3930;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_83 <= _GEN_3930;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_83 <= _GEN_3930;
- end else if (3'h3 == fstate) begin
- dirty_83 <= _GEN_5994;
- end else begin
- dirty_83 <= _GEN_3930;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_84 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_84 <= _GEN_3931;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_84 <= _GEN_3931;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_84 <= _GEN_3931;
- end else if (3'h3 == fstate) begin
- dirty_84 <= _GEN_5995;
- end else begin
- dirty_84 <= _GEN_3931;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_85 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_85 <= _GEN_3932;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_85 <= _GEN_3932;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_85 <= _GEN_3932;
- end else if (3'h3 == fstate) begin
- dirty_85 <= _GEN_5996;
- end else begin
- dirty_85 <= _GEN_3932;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_86 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_86 <= _GEN_3933;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_86 <= _GEN_3933;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_86 <= _GEN_3933;
- end else if (3'h3 == fstate) begin
- dirty_86 <= _GEN_5997;
- end else begin
- dirty_86 <= _GEN_3933;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_87 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_87 <= _GEN_3934;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_87 <= _GEN_3934;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_87 <= _GEN_3934;
- end else if (3'h3 == fstate) begin
- dirty_87 <= _GEN_5998;
- end else begin
- dirty_87 <= _GEN_3934;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_88 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_88 <= _GEN_3935;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_88 <= _GEN_3935;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_88 <= _GEN_3935;
- end else if (3'h3 == fstate) begin
- dirty_88 <= _GEN_5999;
- end else begin
- dirty_88 <= _GEN_3935;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_89 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_89 <= _GEN_3936;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_89 <= _GEN_3936;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_89 <= _GEN_3936;
- end else if (3'h3 == fstate) begin
- dirty_89 <= _GEN_6000;
- end else begin
- dirty_89 <= _GEN_3936;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_90 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_90 <= _GEN_3937;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_90 <= _GEN_3937;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_90 <= _GEN_3937;
- end else if (3'h3 == fstate) begin
- dirty_90 <= _GEN_6001;
- end else begin
- dirty_90 <= _GEN_3937;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_91 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_91 <= _GEN_3938;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_91 <= _GEN_3938;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_91 <= _GEN_3938;
- end else if (3'h3 == fstate) begin
- dirty_91 <= _GEN_6002;
- end else begin
- dirty_91 <= _GEN_3938;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_92 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_92 <= _GEN_3939;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_92 <= _GEN_3939;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_92 <= _GEN_3939;
- end else if (3'h3 == fstate) begin
- dirty_92 <= _GEN_6003;
- end else begin
- dirty_92 <= _GEN_3939;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_93 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_93 <= _GEN_3940;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_93 <= _GEN_3940;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_93 <= _GEN_3940;
- end else if (3'h3 == fstate) begin
- dirty_93 <= _GEN_6004;
- end else begin
- dirty_93 <= _GEN_3940;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_94 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_94 <= _GEN_3941;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_94 <= _GEN_3941;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_94 <= _GEN_3941;
- end else if (3'h3 == fstate) begin
- dirty_94 <= _GEN_6005;
- end else begin
- dirty_94 <= _GEN_3941;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_95 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_95 <= _GEN_3942;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_95 <= _GEN_3942;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_95 <= _GEN_3942;
- end else if (3'h3 == fstate) begin
- dirty_95 <= _GEN_6006;
- end else begin
- dirty_95 <= _GEN_3942;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_96 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_96 <= _GEN_3943;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_96 <= _GEN_3943;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_96 <= _GEN_3943;
- end else if (3'h3 == fstate) begin
- dirty_96 <= _GEN_6007;
- end else begin
- dirty_96 <= _GEN_3943;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_97 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_97 <= _GEN_3944;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_97 <= _GEN_3944;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_97 <= _GEN_3944;
- end else if (3'h3 == fstate) begin
- dirty_97 <= _GEN_6008;
- end else begin
- dirty_97 <= _GEN_3944;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_98 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_98 <= _GEN_3945;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_98 <= _GEN_3945;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_98 <= _GEN_3945;
- end else if (3'h3 == fstate) begin
- dirty_98 <= _GEN_6009;
- end else begin
- dirty_98 <= _GEN_3945;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_99 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_99 <= _GEN_3946;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_99 <= _GEN_3946;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_99 <= _GEN_3946;
- end else if (3'h3 == fstate) begin
- dirty_99 <= _GEN_6010;
- end else begin
- dirty_99 <= _GEN_3946;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_100 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_100 <= _GEN_3947;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_100 <= _GEN_3947;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_100 <= _GEN_3947;
- end else if (3'h3 == fstate) begin
- dirty_100 <= _GEN_6011;
- end else begin
- dirty_100 <= _GEN_3947;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_101 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_101 <= _GEN_3948;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_101 <= _GEN_3948;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_101 <= _GEN_3948;
- end else if (3'h3 == fstate) begin
- dirty_101 <= _GEN_6012;
- end else begin
- dirty_101 <= _GEN_3948;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_102 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_102 <= _GEN_3949;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_102 <= _GEN_3949;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_102 <= _GEN_3949;
- end else if (3'h3 == fstate) begin
- dirty_102 <= _GEN_6013;
- end else begin
- dirty_102 <= _GEN_3949;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_103 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_103 <= _GEN_3950;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_103 <= _GEN_3950;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_103 <= _GEN_3950;
- end else if (3'h3 == fstate) begin
- dirty_103 <= _GEN_6014;
- end else begin
- dirty_103 <= _GEN_3950;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_104 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_104 <= _GEN_3951;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_104 <= _GEN_3951;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_104 <= _GEN_3951;
- end else if (3'h3 == fstate) begin
- dirty_104 <= _GEN_6015;
- end else begin
- dirty_104 <= _GEN_3951;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_105 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_105 <= _GEN_3952;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_105 <= _GEN_3952;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_105 <= _GEN_3952;
- end else if (3'h3 == fstate) begin
- dirty_105 <= _GEN_6016;
- end else begin
- dirty_105 <= _GEN_3952;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_106 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_106 <= _GEN_3953;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_106 <= _GEN_3953;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_106 <= _GEN_3953;
- end else if (3'h3 == fstate) begin
- dirty_106 <= _GEN_6017;
- end else begin
- dirty_106 <= _GEN_3953;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_107 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_107 <= _GEN_3954;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_107 <= _GEN_3954;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_107 <= _GEN_3954;
- end else if (3'h3 == fstate) begin
- dirty_107 <= _GEN_6018;
- end else begin
- dirty_107 <= _GEN_3954;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_108 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_108 <= _GEN_3955;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_108 <= _GEN_3955;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_108 <= _GEN_3955;
- end else if (3'h3 == fstate) begin
- dirty_108 <= _GEN_6019;
- end else begin
- dirty_108 <= _GEN_3955;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_109 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_109 <= _GEN_3956;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_109 <= _GEN_3956;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_109 <= _GEN_3956;
- end else if (3'h3 == fstate) begin
- dirty_109 <= _GEN_6020;
- end else begin
- dirty_109 <= _GEN_3956;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_110 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_110 <= _GEN_3957;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_110 <= _GEN_3957;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_110 <= _GEN_3957;
- end else if (3'h3 == fstate) begin
- dirty_110 <= _GEN_6021;
- end else begin
- dirty_110 <= _GEN_3957;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_111 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_111 <= _GEN_3958;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_111 <= _GEN_3958;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_111 <= _GEN_3958;
- end else if (3'h3 == fstate) begin
- dirty_111 <= _GEN_6022;
- end else begin
- dirty_111 <= _GEN_3958;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_112 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_112 <= _GEN_3959;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_112 <= _GEN_3959;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_112 <= _GEN_3959;
- end else if (3'h3 == fstate) begin
- dirty_112 <= _GEN_6023;
- end else begin
- dirty_112 <= _GEN_3959;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_113 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_113 <= _GEN_3960;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_113 <= _GEN_3960;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_113 <= _GEN_3960;
- end else if (3'h3 == fstate) begin
- dirty_113 <= _GEN_6024;
- end else begin
- dirty_113 <= _GEN_3960;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_114 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_114 <= _GEN_3961;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_114 <= _GEN_3961;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_114 <= _GEN_3961;
- end else if (3'h3 == fstate) begin
- dirty_114 <= _GEN_6025;
- end else begin
- dirty_114 <= _GEN_3961;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_115 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_115 <= _GEN_3962;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_115 <= _GEN_3962;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_115 <= _GEN_3962;
- end else if (3'h3 == fstate) begin
- dirty_115 <= _GEN_6026;
- end else begin
- dirty_115 <= _GEN_3962;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_116 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_116 <= _GEN_3963;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_116 <= _GEN_3963;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_116 <= _GEN_3963;
- end else if (3'h3 == fstate) begin
- dirty_116 <= _GEN_6027;
- end else begin
- dirty_116 <= _GEN_3963;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_117 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_117 <= _GEN_3964;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_117 <= _GEN_3964;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_117 <= _GEN_3964;
- end else if (3'h3 == fstate) begin
- dirty_117 <= _GEN_6028;
- end else begin
- dirty_117 <= _GEN_3964;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_118 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_118 <= _GEN_3965;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_118 <= _GEN_3965;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_118 <= _GEN_3965;
- end else if (3'h3 == fstate) begin
- dirty_118 <= _GEN_6029;
- end else begin
- dirty_118 <= _GEN_3965;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_119 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_119 <= _GEN_3966;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_119 <= _GEN_3966;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_119 <= _GEN_3966;
- end else if (3'h3 == fstate) begin
- dirty_119 <= _GEN_6030;
- end else begin
- dirty_119 <= _GEN_3966;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_120 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_120 <= _GEN_3967;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_120 <= _GEN_3967;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_120 <= _GEN_3967;
- end else if (3'h3 == fstate) begin
- dirty_120 <= _GEN_6031;
- end else begin
- dirty_120 <= _GEN_3967;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_121 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_121 <= _GEN_3968;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_121 <= _GEN_3968;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_121 <= _GEN_3968;
- end else if (3'h3 == fstate) begin
- dirty_121 <= _GEN_6032;
- end else begin
- dirty_121 <= _GEN_3968;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_122 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_122 <= _GEN_3969;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_122 <= _GEN_3969;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_122 <= _GEN_3969;
- end else if (3'h3 == fstate) begin
- dirty_122 <= _GEN_6033;
- end else begin
- dirty_122 <= _GEN_3969;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_123 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_123 <= _GEN_3970;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_123 <= _GEN_3970;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_123 <= _GEN_3970;
- end else if (3'h3 == fstate) begin
- dirty_123 <= _GEN_6034;
- end else begin
- dirty_123 <= _GEN_3970;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_124 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_124 <= _GEN_3971;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_124 <= _GEN_3971;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_124 <= _GEN_3971;
- end else if (3'h3 == fstate) begin
- dirty_124 <= _GEN_6035;
- end else begin
- dirty_124 <= _GEN_3971;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_125 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_125 <= _GEN_3972;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_125 <= _GEN_3972;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_125 <= _GEN_3972;
- end else if (3'h3 == fstate) begin
- dirty_125 <= _GEN_6036;
- end else begin
- dirty_125 <= _GEN_3972;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_126 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_126 <= _GEN_3973;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_126 <= _GEN_3973;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_126 <= _GEN_3973;
- end else if (3'h3 == fstate) begin
- dirty_126 <= _GEN_6037;
- end else begin
- dirty_126 <= _GEN_3973;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_127 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_127 <= _GEN_3974;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_127 <= _GEN_3974;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_127 <= _GEN_3974;
- end else if (3'h3 == fstate) begin
- dirty_127 <= _GEN_6038;
- end else begin
- dirty_127 <= _GEN_3974;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_128 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_128 <= _GEN_3975;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_128 <= _GEN_3975;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_128 <= _GEN_3975;
- end else if (3'h3 == fstate) begin
- dirty_128 <= _GEN_6039;
- end else begin
- dirty_128 <= _GEN_3975;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_129 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_129 <= _GEN_3976;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_129 <= _GEN_3976;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_129 <= _GEN_3976;
- end else if (3'h3 == fstate) begin
- dirty_129 <= _GEN_6040;
- end else begin
- dirty_129 <= _GEN_3976;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_130 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_130 <= _GEN_3977;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_130 <= _GEN_3977;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_130 <= _GEN_3977;
- end else if (3'h3 == fstate) begin
- dirty_130 <= _GEN_6041;
- end else begin
- dirty_130 <= _GEN_3977;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_131 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_131 <= _GEN_3978;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_131 <= _GEN_3978;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_131 <= _GEN_3978;
- end else if (3'h3 == fstate) begin
- dirty_131 <= _GEN_6042;
- end else begin
- dirty_131 <= _GEN_3978;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_132 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_132 <= _GEN_3979;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_132 <= _GEN_3979;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_132 <= _GEN_3979;
- end else if (3'h3 == fstate) begin
- dirty_132 <= _GEN_6043;
- end else begin
- dirty_132 <= _GEN_3979;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_133 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_133 <= _GEN_3980;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_133 <= _GEN_3980;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_133 <= _GEN_3980;
- end else if (3'h3 == fstate) begin
- dirty_133 <= _GEN_6044;
- end else begin
- dirty_133 <= _GEN_3980;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_134 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_134 <= _GEN_3981;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_134 <= _GEN_3981;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_134 <= _GEN_3981;
- end else if (3'h3 == fstate) begin
- dirty_134 <= _GEN_6045;
- end else begin
- dirty_134 <= _GEN_3981;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_135 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_135 <= _GEN_3982;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_135 <= _GEN_3982;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_135 <= _GEN_3982;
- end else if (3'h3 == fstate) begin
- dirty_135 <= _GEN_6046;
- end else begin
- dirty_135 <= _GEN_3982;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_136 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_136 <= _GEN_3983;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_136 <= _GEN_3983;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_136 <= _GEN_3983;
- end else if (3'h3 == fstate) begin
- dirty_136 <= _GEN_6047;
- end else begin
- dirty_136 <= _GEN_3983;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_137 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_137 <= _GEN_3984;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_137 <= _GEN_3984;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_137 <= _GEN_3984;
- end else if (3'h3 == fstate) begin
- dirty_137 <= _GEN_6048;
- end else begin
- dirty_137 <= _GEN_3984;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_138 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_138 <= _GEN_3985;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_138 <= _GEN_3985;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_138 <= _GEN_3985;
- end else if (3'h3 == fstate) begin
- dirty_138 <= _GEN_6049;
- end else begin
- dirty_138 <= _GEN_3985;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_139 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_139 <= _GEN_3986;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_139 <= _GEN_3986;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_139 <= _GEN_3986;
- end else if (3'h3 == fstate) begin
- dirty_139 <= _GEN_6050;
- end else begin
- dirty_139 <= _GEN_3986;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_140 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_140 <= _GEN_3987;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_140 <= _GEN_3987;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_140 <= _GEN_3987;
- end else if (3'h3 == fstate) begin
- dirty_140 <= _GEN_6051;
- end else begin
- dirty_140 <= _GEN_3987;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_141 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_141 <= _GEN_3988;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_141 <= _GEN_3988;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_141 <= _GEN_3988;
- end else if (3'h3 == fstate) begin
- dirty_141 <= _GEN_6052;
- end else begin
- dirty_141 <= _GEN_3988;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_142 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_142 <= _GEN_3989;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_142 <= _GEN_3989;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_142 <= _GEN_3989;
- end else if (3'h3 == fstate) begin
- dirty_142 <= _GEN_6053;
- end else begin
- dirty_142 <= _GEN_3989;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_143 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_143 <= _GEN_3990;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_143 <= _GEN_3990;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_143 <= _GEN_3990;
- end else if (3'h3 == fstate) begin
- dirty_143 <= _GEN_6054;
- end else begin
- dirty_143 <= _GEN_3990;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_144 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_144 <= _GEN_3991;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_144 <= _GEN_3991;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_144 <= _GEN_3991;
- end else if (3'h3 == fstate) begin
- dirty_144 <= _GEN_6055;
- end else begin
- dirty_144 <= _GEN_3991;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_145 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_145 <= _GEN_3992;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_145 <= _GEN_3992;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_145 <= _GEN_3992;
- end else if (3'h3 == fstate) begin
- dirty_145 <= _GEN_6056;
- end else begin
- dirty_145 <= _GEN_3992;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_146 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_146 <= _GEN_3993;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_146 <= _GEN_3993;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_146 <= _GEN_3993;
- end else if (3'h3 == fstate) begin
- dirty_146 <= _GEN_6057;
- end else begin
- dirty_146 <= _GEN_3993;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_147 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_147 <= _GEN_3994;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_147 <= _GEN_3994;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_147 <= _GEN_3994;
- end else if (3'h3 == fstate) begin
- dirty_147 <= _GEN_6058;
- end else begin
- dirty_147 <= _GEN_3994;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_148 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_148 <= _GEN_3995;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_148 <= _GEN_3995;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_148 <= _GEN_3995;
- end else if (3'h3 == fstate) begin
- dirty_148 <= _GEN_6059;
- end else begin
- dirty_148 <= _GEN_3995;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_149 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_149 <= _GEN_3996;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_149 <= _GEN_3996;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_149 <= _GEN_3996;
- end else if (3'h3 == fstate) begin
- dirty_149 <= _GEN_6060;
- end else begin
- dirty_149 <= _GEN_3996;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_150 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_150 <= _GEN_3997;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_150 <= _GEN_3997;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_150 <= _GEN_3997;
- end else if (3'h3 == fstate) begin
- dirty_150 <= _GEN_6061;
- end else begin
- dirty_150 <= _GEN_3997;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_151 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_151 <= _GEN_3998;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_151 <= _GEN_3998;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_151 <= _GEN_3998;
- end else if (3'h3 == fstate) begin
- dirty_151 <= _GEN_6062;
- end else begin
- dirty_151 <= _GEN_3998;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_152 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_152 <= _GEN_3999;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_152 <= _GEN_3999;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_152 <= _GEN_3999;
- end else if (3'h3 == fstate) begin
- dirty_152 <= _GEN_6063;
- end else begin
- dirty_152 <= _GEN_3999;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_153 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_153 <= _GEN_4000;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_153 <= _GEN_4000;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_153 <= _GEN_4000;
- end else if (3'h3 == fstate) begin
- dirty_153 <= _GEN_6064;
- end else begin
- dirty_153 <= _GEN_4000;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_154 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_154 <= _GEN_4001;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_154 <= _GEN_4001;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_154 <= _GEN_4001;
- end else if (3'h3 == fstate) begin
- dirty_154 <= _GEN_6065;
- end else begin
- dirty_154 <= _GEN_4001;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_155 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_155 <= _GEN_4002;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_155 <= _GEN_4002;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_155 <= _GEN_4002;
- end else if (3'h3 == fstate) begin
- dirty_155 <= _GEN_6066;
- end else begin
- dirty_155 <= _GEN_4002;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_156 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_156 <= _GEN_4003;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_156 <= _GEN_4003;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_156 <= _GEN_4003;
- end else if (3'h3 == fstate) begin
- dirty_156 <= _GEN_6067;
- end else begin
- dirty_156 <= _GEN_4003;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_157 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_157 <= _GEN_4004;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_157 <= _GEN_4004;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_157 <= _GEN_4004;
- end else if (3'h3 == fstate) begin
- dirty_157 <= _GEN_6068;
- end else begin
- dirty_157 <= _GEN_4004;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_158 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_158 <= _GEN_4005;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_158 <= _GEN_4005;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_158 <= _GEN_4005;
- end else if (3'h3 == fstate) begin
- dirty_158 <= _GEN_6069;
- end else begin
- dirty_158 <= _GEN_4005;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_159 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_159 <= _GEN_4006;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_159 <= _GEN_4006;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_159 <= _GEN_4006;
- end else if (3'h3 == fstate) begin
- dirty_159 <= _GEN_6070;
- end else begin
- dirty_159 <= _GEN_4006;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_160 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_160 <= _GEN_4007;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_160 <= _GEN_4007;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_160 <= _GEN_4007;
- end else if (3'h3 == fstate) begin
- dirty_160 <= _GEN_6071;
- end else begin
- dirty_160 <= _GEN_4007;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_161 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_161 <= _GEN_4008;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_161 <= _GEN_4008;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_161 <= _GEN_4008;
- end else if (3'h3 == fstate) begin
- dirty_161 <= _GEN_6072;
- end else begin
- dirty_161 <= _GEN_4008;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_162 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_162 <= _GEN_4009;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_162 <= _GEN_4009;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_162 <= _GEN_4009;
- end else if (3'h3 == fstate) begin
- dirty_162 <= _GEN_6073;
- end else begin
- dirty_162 <= _GEN_4009;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_163 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_163 <= _GEN_4010;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_163 <= _GEN_4010;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_163 <= _GEN_4010;
- end else if (3'h3 == fstate) begin
- dirty_163 <= _GEN_6074;
- end else begin
- dirty_163 <= _GEN_4010;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_164 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_164 <= _GEN_4011;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_164 <= _GEN_4011;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_164 <= _GEN_4011;
- end else if (3'h3 == fstate) begin
- dirty_164 <= _GEN_6075;
- end else begin
- dirty_164 <= _GEN_4011;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_165 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_165 <= _GEN_4012;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_165 <= _GEN_4012;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_165 <= _GEN_4012;
- end else if (3'h3 == fstate) begin
- dirty_165 <= _GEN_6076;
- end else begin
- dirty_165 <= _GEN_4012;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_166 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_166 <= _GEN_4013;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_166 <= _GEN_4013;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_166 <= _GEN_4013;
- end else if (3'h3 == fstate) begin
- dirty_166 <= _GEN_6077;
- end else begin
- dirty_166 <= _GEN_4013;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_167 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_167 <= _GEN_4014;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_167 <= _GEN_4014;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_167 <= _GEN_4014;
- end else if (3'h3 == fstate) begin
- dirty_167 <= _GEN_6078;
- end else begin
- dirty_167 <= _GEN_4014;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_168 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_168 <= _GEN_4015;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_168 <= _GEN_4015;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_168 <= _GEN_4015;
- end else if (3'h3 == fstate) begin
- dirty_168 <= _GEN_6079;
- end else begin
- dirty_168 <= _GEN_4015;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_169 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_169 <= _GEN_4016;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_169 <= _GEN_4016;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_169 <= _GEN_4016;
- end else if (3'h3 == fstate) begin
- dirty_169 <= _GEN_6080;
- end else begin
- dirty_169 <= _GEN_4016;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_170 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_170 <= _GEN_4017;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_170 <= _GEN_4017;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_170 <= _GEN_4017;
- end else if (3'h3 == fstate) begin
- dirty_170 <= _GEN_6081;
- end else begin
- dirty_170 <= _GEN_4017;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_171 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_171 <= _GEN_4018;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_171 <= _GEN_4018;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_171 <= _GEN_4018;
- end else if (3'h3 == fstate) begin
- dirty_171 <= _GEN_6082;
- end else begin
- dirty_171 <= _GEN_4018;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_172 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_172 <= _GEN_4019;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_172 <= _GEN_4019;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_172 <= _GEN_4019;
- end else if (3'h3 == fstate) begin
- dirty_172 <= _GEN_6083;
- end else begin
- dirty_172 <= _GEN_4019;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_173 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_173 <= _GEN_4020;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_173 <= _GEN_4020;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_173 <= _GEN_4020;
- end else if (3'h3 == fstate) begin
- dirty_173 <= _GEN_6084;
- end else begin
- dirty_173 <= _GEN_4020;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_174 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_174 <= _GEN_4021;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_174 <= _GEN_4021;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_174 <= _GEN_4021;
- end else if (3'h3 == fstate) begin
- dirty_174 <= _GEN_6085;
- end else begin
- dirty_174 <= _GEN_4021;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_175 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_175 <= _GEN_4022;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_175 <= _GEN_4022;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_175 <= _GEN_4022;
- end else if (3'h3 == fstate) begin
- dirty_175 <= _GEN_6086;
- end else begin
- dirty_175 <= _GEN_4022;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_176 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_176 <= _GEN_4023;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_176 <= _GEN_4023;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_176 <= _GEN_4023;
- end else if (3'h3 == fstate) begin
- dirty_176 <= _GEN_6087;
- end else begin
- dirty_176 <= _GEN_4023;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_177 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_177 <= _GEN_4024;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_177 <= _GEN_4024;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_177 <= _GEN_4024;
- end else if (3'h3 == fstate) begin
- dirty_177 <= _GEN_6088;
- end else begin
- dirty_177 <= _GEN_4024;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_178 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_178 <= _GEN_4025;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_178 <= _GEN_4025;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_178 <= _GEN_4025;
- end else if (3'h3 == fstate) begin
- dirty_178 <= _GEN_6089;
- end else begin
- dirty_178 <= _GEN_4025;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_179 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_179 <= _GEN_4026;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_179 <= _GEN_4026;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_179 <= _GEN_4026;
- end else if (3'h3 == fstate) begin
- dirty_179 <= _GEN_6090;
- end else begin
- dirty_179 <= _GEN_4026;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_180 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_180 <= _GEN_4027;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_180 <= _GEN_4027;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_180 <= _GEN_4027;
- end else if (3'h3 == fstate) begin
- dirty_180 <= _GEN_6091;
- end else begin
- dirty_180 <= _GEN_4027;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_181 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_181 <= _GEN_4028;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_181 <= _GEN_4028;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_181 <= _GEN_4028;
- end else if (3'h3 == fstate) begin
- dirty_181 <= _GEN_6092;
- end else begin
- dirty_181 <= _GEN_4028;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_182 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_182 <= _GEN_4029;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_182 <= _GEN_4029;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_182 <= _GEN_4029;
- end else if (3'h3 == fstate) begin
- dirty_182 <= _GEN_6093;
- end else begin
- dirty_182 <= _GEN_4029;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_183 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_183 <= _GEN_4030;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_183 <= _GEN_4030;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_183 <= _GEN_4030;
- end else if (3'h3 == fstate) begin
- dirty_183 <= _GEN_6094;
- end else begin
- dirty_183 <= _GEN_4030;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_184 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_184 <= _GEN_4031;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_184 <= _GEN_4031;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_184 <= _GEN_4031;
- end else if (3'h3 == fstate) begin
- dirty_184 <= _GEN_6095;
- end else begin
- dirty_184 <= _GEN_4031;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_185 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_185 <= _GEN_4032;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_185 <= _GEN_4032;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_185 <= _GEN_4032;
- end else if (3'h3 == fstate) begin
- dirty_185 <= _GEN_6096;
- end else begin
- dirty_185 <= _GEN_4032;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_186 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_186 <= _GEN_4033;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_186 <= _GEN_4033;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_186 <= _GEN_4033;
- end else if (3'h3 == fstate) begin
- dirty_186 <= _GEN_6097;
- end else begin
- dirty_186 <= _GEN_4033;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_187 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_187 <= _GEN_4034;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_187 <= _GEN_4034;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_187 <= _GEN_4034;
- end else if (3'h3 == fstate) begin
- dirty_187 <= _GEN_6098;
- end else begin
- dirty_187 <= _GEN_4034;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_188 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_188 <= _GEN_4035;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_188 <= _GEN_4035;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_188 <= _GEN_4035;
- end else if (3'h3 == fstate) begin
- dirty_188 <= _GEN_6099;
- end else begin
- dirty_188 <= _GEN_4035;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_189 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_189 <= _GEN_4036;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_189 <= _GEN_4036;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_189 <= _GEN_4036;
- end else if (3'h3 == fstate) begin
- dirty_189 <= _GEN_6100;
- end else begin
- dirty_189 <= _GEN_4036;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_190 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_190 <= _GEN_4037;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_190 <= _GEN_4037;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_190 <= _GEN_4037;
- end else if (3'h3 == fstate) begin
- dirty_190 <= _GEN_6101;
- end else begin
- dirty_190 <= _GEN_4037;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_191 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_191 <= _GEN_4038;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_191 <= _GEN_4038;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_191 <= _GEN_4038;
- end else if (3'h3 == fstate) begin
- dirty_191 <= _GEN_6102;
- end else begin
- dirty_191 <= _GEN_4038;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_192 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_192 <= _GEN_4039;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_192 <= _GEN_4039;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_192 <= _GEN_4039;
- end else if (3'h3 == fstate) begin
- dirty_192 <= _GEN_6103;
- end else begin
- dirty_192 <= _GEN_4039;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_193 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_193 <= _GEN_4040;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_193 <= _GEN_4040;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_193 <= _GEN_4040;
- end else if (3'h3 == fstate) begin
- dirty_193 <= _GEN_6104;
- end else begin
- dirty_193 <= _GEN_4040;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_194 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_194 <= _GEN_4041;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_194 <= _GEN_4041;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_194 <= _GEN_4041;
- end else if (3'h3 == fstate) begin
- dirty_194 <= _GEN_6105;
- end else begin
- dirty_194 <= _GEN_4041;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_195 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_195 <= _GEN_4042;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_195 <= _GEN_4042;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_195 <= _GEN_4042;
- end else if (3'h3 == fstate) begin
- dirty_195 <= _GEN_6106;
- end else begin
- dirty_195 <= _GEN_4042;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_196 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_196 <= _GEN_4043;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_196 <= _GEN_4043;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_196 <= _GEN_4043;
- end else if (3'h3 == fstate) begin
- dirty_196 <= _GEN_6107;
- end else begin
- dirty_196 <= _GEN_4043;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_197 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_197 <= _GEN_4044;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_197 <= _GEN_4044;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_197 <= _GEN_4044;
- end else if (3'h3 == fstate) begin
- dirty_197 <= _GEN_6108;
- end else begin
- dirty_197 <= _GEN_4044;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_198 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_198 <= _GEN_4045;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_198 <= _GEN_4045;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_198 <= _GEN_4045;
- end else if (3'h3 == fstate) begin
- dirty_198 <= _GEN_6109;
- end else begin
- dirty_198 <= _GEN_4045;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_199 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_199 <= _GEN_4046;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_199 <= _GEN_4046;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_199 <= _GEN_4046;
- end else if (3'h3 == fstate) begin
- dirty_199 <= _GEN_6110;
- end else begin
- dirty_199 <= _GEN_4046;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_200 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_200 <= _GEN_4047;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_200 <= _GEN_4047;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_200 <= _GEN_4047;
- end else if (3'h3 == fstate) begin
- dirty_200 <= _GEN_6111;
- end else begin
- dirty_200 <= _GEN_4047;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_201 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_201 <= _GEN_4048;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_201 <= _GEN_4048;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_201 <= _GEN_4048;
- end else if (3'h3 == fstate) begin
- dirty_201 <= _GEN_6112;
- end else begin
- dirty_201 <= _GEN_4048;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_202 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_202 <= _GEN_4049;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_202 <= _GEN_4049;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_202 <= _GEN_4049;
- end else if (3'h3 == fstate) begin
- dirty_202 <= _GEN_6113;
- end else begin
- dirty_202 <= _GEN_4049;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_203 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_203 <= _GEN_4050;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_203 <= _GEN_4050;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_203 <= _GEN_4050;
- end else if (3'h3 == fstate) begin
- dirty_203 <= _GEN_6114;
- end else begin
- dirty_203 <= _GEN_4050;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_204 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_204 <= _GEN_4051;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_204 <= _GEN_4051;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_204 <= _GEN_4051;
- end else if (3'h3 == fstate) begin
- dirty_204 <= _GEN_6115;
- end else begin
- dirty_204 <= _GEN_4051;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_205 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_205 <= _GEN_4052;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_205 <= _GEN_4052;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_205 <= _GEN_4052;
- end else if (3'h3 == fstate) begin
- dirty_205 <= _GEN_6116;
- end else begin
- dirty_205 <= _GEN_4052;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_206 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_206 <= _GEN_4053;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_206 <= _GEN_4053;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_206 <= _GEN_4053;
- end else if (3'h3 == fstate) begin
- dirty_206 <= _GEN_6117;
- end else begin
- dirty_206 <= _GEN_4053;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_207 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_207 <= _GEN_4054;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_207 <= _GEN_4054;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_207 <= _GEN_4054;
- end else if (3'h3 == fstate) begin
- dirty_207 <= _GEN_6118;
- end else begin
- dirty_207 <= _GEN_4054;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_208 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_208 <= _GEN_4055;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_208 <= _GEN_4055;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_208 <= _GEN_4055;
- end else if (3'h3 == fstate) begin
- dirty_208 <= _GEN_6119;
- end else begin
- dirty_208 <= _GEN_4055;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_209 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_209 <= _GEN_4056;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_209 <= _GEN_4056;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_209 <= _GEN_4056;
- end else if (3'h3 == fstate) begin
- dirty_209 <= _GEN_6120;
- end else begin
- dirty_209 <= _GEN_4056;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_210 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_210 <= _GEN_4057;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_210 <= _GEN_4057;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_210 <= _GEN_4057;
- end else if (3'h3 == fstate) begin
- dirty_210 <= _GEN_6121;
- end else begin
- dirty_210 <= _GEN_4057;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_211 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_211 <= _GEN_4058;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_211 <= _GEN_4058;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_211 <= _GEN_4058;
- end else if (3'h3 == fstate) begin
- dirty_211 <= _GEN_6122;
- end else begin
- dirty_211 <= _GEN_4058;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_212 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_212 <= _GEN_4059;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_212 <= _GEN_4059;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_212 <= _GEN_4059;
- end else if (3'h3 == fstate) begin
- dirty_212 <= _GEN_6123;
- end else begin
- dirty_212 <= _GEN_4059;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_213 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_213 <= _GEN_4060;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_213 <= _GEN_4060;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_213 <= _GEN_4060;
- end else if (3'h3 == fstate) begin
- dirty_213 <= _GEN_6124;
- end else begin
- dirty_213 <= _GEN_4060;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_214 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_214 <= _GEN_4061;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_214 <= _GEN_4061;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_214 <= _GEN_4061;
- end else if (3'h3 == fstate) begin
- dirty_214 <= _GEN_6125;
- end else begin
- dirty_214 <= _GEN_4061;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_215 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_215 <= _GEN_4062;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_215 <= _GEN_4062;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_215 <= _GEN_4062;
- end else if (3'h3 == fstate) begin
- dirty_215 <= _GEN_6126;
- end else begin
- dirty_215 <= _GEN_4062;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_216 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_216 <= _GEN_4063;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_216 <= _GEN_4063;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_216 <= _GEN_4063;
- end else if (3'h3 == fstate) begin
- dirty_216 <= _GEN_6127;
- end else begin
- dirty_216 <= _GEN_4063;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_217 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_217 <= _GEN_4064;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_217 <= _GEN_4064;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_217 <= _GEN_4064;
- end else if (3'h3 == fstate) begin
- dirty_217 <= _GEN_6128;
- end else begin
- dirty_217 <= _GEN_4064;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_218 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_218 <= _GEN_4065;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_218 <= _GEN_4065;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_218 <= _GEN_4065;
- end else if (3'h3 == fstate) begin
- dirty_218 <= _GEN_6129;
- end else begin
- dirty_218 <= _GEN_4065;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_219 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_219 <= _GEN_4066;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_219 <= _GEN_4066;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_219 <= _GEN_4066;
- end else if (3'h3 == fstate) begin
- dirty_219 <= _GEN_6130;
- end else begin
- dirty_219 <= _GEN_4066;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_220 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_220 <= _GEN_4067;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_220 <= _GEN_4067;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_220 <= _GEN_4067;
- end else if (3'h3 == fstate) begin
- dirty_220 <= _GEN_6131;
- end else begin
- dirty_220 <= _GEN_4067;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_221 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_221 <= _GEN_4068;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_221 <= _GEN_4068;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_221 <= _GEN_4068;
- end else if (3'h3 == fstate) begin
- dirty_221 <= _GEN_6132;
- end else begin
- dirty_221 <= _GEN_4068;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_222 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_222 <= _GEN_4069;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_222 <= _GEN_4069;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_222 <= _GEN_4069;
- end else if (3'h3 == fstate) begin
- dirty_222 <= _GEN_6133;
- end else begin
- dirty_222 <= _GEN_4069;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_223 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_223 <= _GEN_4070;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_223 <= _GEN_4070;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_223 <= _GEN_4070;
- end else if (3'h3 == fstate) begin
- dirty_223 <= _GEN_6134;
- end else begin
- dirty_223 <= _GEN_4070;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_224 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_224 <= _GEN_4071;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_224 <= _GEN_4071;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_224 <= _GEN_4071;
- end else if (3'h3 == fstate) begin
- dirty_224 <= _GEN_6135;
- end else begin
- dirty_224 <= _GEN_4071;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_225 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_225 <= _GEN_4072;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_225 <= _GEN_4072;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_225 <= _GEN_4072;
- end else if (3'h3 == fstate) begin
- dirty_225 <= _GEN_6136;
- end else begin
- dirty_225 <= _GEN_4072;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_226 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_226 <= _GEN_4073;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_226 <= _GEN_4073;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_226 <= _GEN_4073;
- end else if (3'h3 == fstate) begin
- dirty_226 <= _GEN_6137;
- end else begin
- dirty_226 <= _GEN_4073;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_227 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_227 <= _GEN_4074;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_227 <= _GEN_4074;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_227 <= _GEN_4074;
- end else if (3'h3 == fstate) begin
- dirty_227 <= _GEN_6138;
- end else begin
- dirty_227 <= _GEN_4074;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_228 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_228 <= _GEN_4075;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_228 <= _GEN_4075;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_228 <= _GEN_4075;
- end else if (3'h3 == fstate) begin
- dirty_228 <= _GEN_6139;
- end else begin
- dirty_228 <= _GEN_4075;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_229 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_229 <= _GEN_4076;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_229 <= _GEN_4076;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_229 <= _GEN_4076;
- end else if (3'h3 == fstate) begin
- dirty_229 <= _GEN_6140;
- end else begin
- dirty_229 <= _GEN_4076;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_230 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_230 <= _GEN_4077;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_230 <= _GEN_4077;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_230 <= _GEN_4077;
- end else if (3'h3 == fstate) begin
- dirty_230 <= _GEN_6141;
- end else begin
- dirty_230 <= _GEN_4077;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_231 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_231 <= _GEN_4078;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_231 <= _GEN_4078;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_231 <= _GEN_4078;
- end else if (3'h3 == fstate) begin
- dirty_231 <= _GEN_6142;
- end else begin
- dirty_231 <= _GEN_4078;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_232 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_232 <= _GEN_4079;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_232 <= _GEN_4079;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_232 <= _GEN_4079;
- end else if (3'h3 == fstate) begin
- dirty_232 <= _GEN_6143;
- end else begin
- dirty_232 <= _GEN_4079;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_233 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_233 <= _GEN_4080;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_233 <= _GEN_4080;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_233 <= _GEN_4080;
- end else if (3'h3 == fstate) begin
- dirty_233 <= _GEN_6144;
- end else begin
- dirty_233 <= _GEN_4080;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_234 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_234 <= _GEN_4081;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_234 <= _GEN_4081;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_234 <= _GEN_4081;
- end else if (3'h3 == fstate) begin
- dirty_234 <= _GEN_6145;
- end else begin
- dirty_234 <= _GEN_4081;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_235 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_235 <= _GEN_4082;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_235 <= _GEN_4082;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_235 <= _GEN_4082;
- end else if (3'h3 == fstate) begin
- dirty_235 <= _GEN_6146;
- end else begin
- dirty_235 <= _GEN_4082;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_236 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_236 <= _GEN_4083;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_236 <= _GEN_4083;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_236 <= _GEN_4083;
- end else if (3'h3 == fstate) begin
- dirty_236 <= _GEN_6147;
- end else begin
- dirty_236 <= _GEN_4083;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_237 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_237 <= _GEN_4084;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_237 <= _GEN_4084;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_237 <= _GEN_4084;
- end else if (3'h3 == fstate) begin
- dirty_237 <= _GEN_6148;
- end else begin
- dirty_237 <= _GEN_4084;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_238 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_238 <= _GEN_4085;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_238 <= _GEN_4085;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_238 <= _GEN_4085;
- end else if (3'h3 == fstate) begin
- dirty_238 <= _GEN_6149;
- end else begin
- dirty_238 <= _GEN_4085;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_239 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_239 <= _GEN_4086;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_239 <= _GEN_4086;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_239 <= _GEN_4086;
- end else if (3'h3 == fstate) begin
- dirty_239 <= _GEN_6150;
- end else begin
- dirty_239 <= _GEN_4086;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_240 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_240 <= _GEN_4087;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_240 <= _GEN_4087;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_240 <= _GEN_4087;
- end else if (3'h3 == fstate) begin
- dirty_240 <= _GEN_6151;
- end else begin
- dirty_240 <= _GEN_4087;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_241 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_241 <= _GEN_4088;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_241 <= _GEN_4088;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_241 <= _GEN_4088;
- end else if (3'h3 == fstate) begin
- dirty_241 <= _GEN_6152;
- end else begin
- dirty_241 <= _GEN_4088;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_242 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_242 <= _GEN_4089;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_242 <= _GEN_4089;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_242 <= _GEN_4089;
- end else if (3'h3 == fstate) begin
- dirty_242 <= _GEN_6153;
- end else begin
- dirty_242 <= _GEN_4089;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_243 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_243 <= _GEN_4090;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_243 <= _GEN_4090;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_243 <= _GEN_4090;
- end else if (3'h3 == fstate) begin
- dirty_243 <= _GEN_6154;
- end else begin
- dirty_243 <= _GEN_4090;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_244 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_244 <= _GEN_4091;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_244 <= _GEN_4091;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_244 <= _GEN_4091;
- end else if (3'h3 == fstate) begin
- dirty_244 <= _GEN_6155;
- end else begin
- dirty_244 <= _GEN_4091;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_245 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_245 <= _GEN_4092;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_245 <= _GEN_4092;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_245 <= _GEN_4092;
- end else if (3'h3 == fstate) begin
- dirty_245 <= _GEN_6156;
- end else begin
- dirty_245 <= _GEN_4092;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_246 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_246 <= _GEN_4093;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_246 <= _GEN_4093;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_246 <= _GEN_4093;
- end else if (3'h3 == fstate) begin
- dirty_246 <= _GEN_6157;
- end else begin
- dirty_246 <= _GEN_4093;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_247 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_247 <= _GEN_4094;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_247 <= _GEN_4094;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_247 <= _GEN_4094;
- end else if (3'h3 == fstate) begin
- dirty_247 <= _GEN_6158;
- end else begin
- dirty_247 <= _GEN_4094;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_248 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_248 <= _GEN_4095;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_248 <= _GEN_4095;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_248 <= _GEN_4095;
- end else if (3'h3 == fstate) begin
- dirty_248 <= _GEN_6159;
- end else begin
- dirty_248 <= _GEN_4095;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_249 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_249 <= _GEN_4096;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_249 <= _GEN_4096;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_249 <= _GEN_4096;
- end else if (3'h3 == fstate) begin
- dirty_249 <= _GEN_6160;
- end else begin
- dirty_249 <= _GEN_4096;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_250 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_250 <= _GEN_4097;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_250 <= _GEN_4097;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_250 <= _GEN_4097;
- end else if (3'h3 == fstate) begin
- dirty_250 <= _GEN_6161;
- end else begin
- dirty_250 <= _GEN_4097;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_251 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_251 <= _GEN_4098;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_251 <= _GEN_4098;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_251 <= _GEN_4098;
- end else if (3'h3 == fstate) begin
- dirty_251 <= _GEN_6162;
- end else begin
- dirty_251 <= _GEN_4098;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_252 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_252 <= _GEN_4099;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_252 <= _GEN_4099;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_252 <= _GEN_4099;
- end else if (3'h3 == fstate) begin
- dirty_252 <= _GEN_6163;
- end else begin
- dirty_252 <= _GEN_4099;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_253 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_253 <= _GEN_4100;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_253 <= _GEN_4100;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_253 <= _GEN_4100;
- end else if (3'h3 == fstate) begin
- dirty_253 <= _GEN_6164;
- end else begin
- dirty_253 <= _GEN_4100;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_254 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_254 <= _GEN_4101;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_254 <= _GEN_4101;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_254 <= _GEN_4101;
- end else if (3'h3 == fstate) begin
- dirty_254 <= _GEN_6165;
- end else begin
- dirty_254 <= _GEN_4101;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- dirty_255 <= 1'h0;
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_255 <= _GEN_4102;
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_255 <= _GEN_4102;
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- dirty_255 <= _GEN_4102;
- end else if (3'h3 == fstate) begin
- dirty_255 <= _GEN_6166;
- end else begin
- dirty_255 <= _GEN_4102;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- fstate <= 3'h0; // @[L1DCache.scala 584:101 585:16 462:23]
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_valid & ~axiwaddrvalid & ~axiwdatavalid & ~axiraddrvalid & ~axirdataready) begin // @[L1DCache.scala 591:14]
- fstate <= 3'h1;
- end
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- fstate <= 3'h2; // @[L1DCache.scala 601:35 602:16 604:16]
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 582:18]
- if (_flushId_T == 256'h0) begin // @[L1DCache.scala 612:14]
- fstate <= 3'h6;
- end else begin
- fstate <= 3'h3;
- end
- end else if (3'h3 == fstate) begin
- fstate <= 3'h4;
- end else begin
- fstate <= _GEN_7965;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_0 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_0 <= dirty_0;
- end else if (8'h0 == replaceIdReg) begin
- flush_0 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_0 <= _GEN_5655;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_1 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_1 <= dirty_1;
- end else if (8'h1 == replaceIdReg) begin
- flush_1 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_1 <= _GEN_5656;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_2 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_2 <= dirty_2;
- end else if (8'h2 == replaceIdReg) begin
- flush_2 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_2 <= _GEN_5657;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_3 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_3 <= dirty_3;
- end else if (8'h3 == replaceIdReg) begin
- flush_3 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_3 <= _GEN_5658;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_4 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_4 <= dirty_4;
- end else if (8'h4 == replaceIdReg) begin
- flush_4 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_4 <= _GEN_5659;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_5 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_5 <= dirty_5;
- end else if (8'h5 == replaceIdReg) begin
- flush_5 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_5 <= _GEN_5660;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_6 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_6 <= dirty_6;
- end else if (8'h6 == replaceIdReg) begin
- flush_6 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_6 <= _GEN_5661;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_7 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_7 <= dirty_7;
- end else if (8'h7 == replaceIdReg) begin
- flush_7 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_7 <= _GEN_5662;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_8 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_8 <= dirty_8;
- end else if (8'h8 == replaceIdReg) begin
- flush_8 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_8 <= _GEN_5663;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_9 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_9 <= dirty_9;
- end else if (8'h9 == replaceIdReg) begin
- flush_9 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_9 <= _GEN_5664;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_10 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_10 <= dirty_10;
- end else if (8'ha == replaceIdReg) begin
- flush_10 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_10 <= _GEN_5665;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_11 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_11 <= dirty_11;
- end else if (8'hb == replaceIdReg) begin
- flush_11 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_11 <= _GEN_5666;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_12 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_12 <= dirty_12;
- end else if (8'hc == replaceIdReg) begin
- flush_12 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_12 <= _GEN_5667;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_13 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_13 <= dirty_13;
- end else if (8'hd == replaceIdReg) begin
- flush_13 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_13 <= _GEN_5668;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_14 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_14 <= dirty_14;
- end else if (8'he == replaceIdReg) begin
- flush_14 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_14 <= _GEN_5669;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_15 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_15 <= dirty_15;
- end else if (8'hf == replaceIdReg) begin
- flush_15 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_15 <= _GEN_5670;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_16 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_16 <= dirty_16;
- end else if (8'h10 == replaceIdReg) begin
- flush_16 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_16 <= _GEN_5671;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_17 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_17 <= dirty_17;
- end else if (8'h11 == replaceIdReg) begin
- flush_17 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_17 <= _GEN_5672;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_18 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_18 <= dirty_18;
- end else if (8'h12 == replaceIdReg) begin
- flush_18 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_18 <= _GEN_5673;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_19 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_19 <= dirty_19;
- end else if (8'h13 == replaceIdReg) begin
- flush_19 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_19 <= _GEN_5674;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_20 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_20 <= dirty_20;
- end else if (8'h14 == replaceIdReg) begin
- flush_20 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_20 <= _GEN_5675;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_21 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_21 <= dirty_21;
- end else if (8'h15 == replaceIdReg) begin
- flush_21 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_21 <= _GEN_5676;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_22 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_22 <= dirty_22;
- end else if (8'h16 == replaceIdReg) begin
- flush_22 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_22 <= _GEN_5677;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_23 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_23 <= dirty_23;
- end else if (8'h17 == replaceIdReg) begin
- flush_23 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_23 <= _GEN_5678;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_24 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_24 <= dirty_24;
- end else if (8'h18 == replaceIdReg) begin
- flush_24 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_24 <= _GEN_5679;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_25 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_25 <= dirty_25;
- end else if (8'h19 == replaceIdReg) begin
- flush_25 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_25 <= _GEN_5680;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_26 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_26 <= dirty_26;
- end else if (8'h1a == replaceIdReg) begin
- flush_26 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_26 <= _GEN_5681;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_27 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_27 <= dirty_27;
- end else if (8'h1b == replaceIdReg) begin
- flush_27 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_27 <= _GEN_5682;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_28 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_28 <= dirty_28;
- end else if (8'h1c == replaceIdReg) begin
- flush_28 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_28 <= _GEN_5683;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_29 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_29 <= dirty_29;
- end else if (8'h1d == replaceIdReg) begin
- flush_29 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_29 <= _GEN_5684;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_30 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_30 <= dirty_30;
- end else if (8'h1e == replaceIdReg) begin
- flush_30 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_30 <= _GEN_5685;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_31 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_31 <= dirty_31;
- end else if (8'h1f == replaceIdReg) begin
- flush_31 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_31 <= _GEN_5686;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_32 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_32 <= dirty_32;
- end else if (8'h20 == replaceIdReg) begin
- flush_32 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_32 <= _GEN_5687;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_33 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_33 <= dirty_33;
- end else if (8'h21 == replaceIdReg) begin
- flush_33 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_33 <= _GEN_5688;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_34 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_34 <= dirty_34;
- end else if (8'h22 == replaceIdReg) begin
- flush_34 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_34 <= _GEN_5689;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_35 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_35 <= dirty_35;
- end else if (8'h23 == replaceIdReg) begin
- flush_35 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_35 <= _GEN_5690;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_36 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_36 <= dirty_36;
- end else if (8'h24 == replaceIdReg) begin
- flush_36 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_36 <= _GEN_5691;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_37 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_37 <= dirty_37;
- end else if (8'h25 == replaceIdReg) begin
- flush_37 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_37 <= _GEN_5692;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_38 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_38 <= dirty_38;
- end else if (8'h26 == replaceIdReg) begin
- flush_38 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_38 <= _GEN_5693;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_39 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_39 <= dirty_39;
- end else if (8'h27 == replaceIdReg) begin
- flush_39 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_39 <= _GEN_5694;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_40 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_40 <= dirty_40;
- end else if (8'h28 == replaceIdReg) begin
- flush_40 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_40 <= _GEN_5695;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_41 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_41 <= dirty_41;
- end else if (8'h29 == replaceIdReg) begin
- flush_41 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_41 <= _GEN_5696;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_42 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_42 <= dirty_42;
- end else if (8'h2a == replaceIdReg) begin
- flush_42 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_42 <= _GEN_5697;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_43 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_43 <= dirty_43;
- end else if (8'h2b == replaceIdReg) begin
- flush_43 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_43 <= _GEN_5698;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_44 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_44 <= dirty_44;
- end else if (8'h2c == replaceIdReg) begin
- flush_44 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_44 <= _GEN_5699;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_45 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_45 <= dirty_45;
- end else if (8'h2d == replaceIdReg) begin
- flush_45 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_45 <= _GEN_5700;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_46 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_46 <= dirty_46;
- end else if (8'h2e == replaceIdReg) begin
- flush_46 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_46 <= _GEN_5701;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_47 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_47 <= dirty_47;
- end else if (8'h2f == replaceIdReg) begin
- flush_47 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_47 <= _GEN_5702;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_48 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_48 <= dirty_48;
- end else if (8'h30 == replaceIdReg) begin
- flush_48 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_48 <= _GEN_5703;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_49 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_49 <= dirty_49;
- end else if (8'h31 == replaceIdReg) begin
- flush_49 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_49 <= _GEN_5704;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_50 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_50 <= dirty_50;
- end else if (8'h32 == replaceIdReg) begin
- flush_50 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_50 <= _GEN_5705;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_51 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_51 <= dirty_51;
- end else if (8'h33 == replaceIdReg) begin
- flush_51 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_51 <= _GEN_5706;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_52 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_52 <= dirty_52;
- end else if (8'h34 == replaceIdReg) begin
- flush_52 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_52 <= _GEN_5707;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_53 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_53 <= dirty_53;
- end else if (8'h35 == replaceIdReg) begin
- flush_53 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_53 <= _GEN_5708;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_54 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_54 <= dirty_54;
- end else if (8'h36 == replaceIdReg) begin
- flush_54 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_54 <= _GEN_5709;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_55 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_55 <= dirty_55;
- end else if (8'h37 == replaceIdReg) begin
- flush_55 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_55 <= _GEN_5710;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_56 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_56 <= dirty_56;
- end else if (8'h38 == replaceIdReg) begin
- flush_56 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_56 <= _GEN_5711;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_57 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_57 <= dirty_57;
- end else if (8'h39 == replaceIdReg) begin
- flush_57 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_57 <= _GEN_5712;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_58 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_58 <= dirty_58;
- end else if (8'h3a == replaceIdReg) begin
- flush_58 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_58 <= _GEN_5713;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_59 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_59 <= dirty_59;
- end else if (8'h3b == replaceIdReg) begin
- flush_59 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_59 <= _GEN_5714;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_60 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_60 <= dirty_60;
- end else if (8'h3c == replaceIdReg) begin
- flush_60 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_60 <= _GEN_5715;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_61 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_61 <= dirty_61;
- end else if (8'h3d == replaceIdReg) begin
- flush_61 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_61 <= _GEN_5716;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_62 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_62 <= dirty_62;
- end else if (8'h3e == replaceIdReg) begin
- flush_62 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_62 <= _GEN_5717;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_63 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_63 <= dirty_63;
- end else if (8'h3f == replaceIdReg) begin
- flush_63 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_63 <= _GEN_5718;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_64 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_64 <= dirty_64;
- end else if (8'h40 == replaceIdReg) begin
- flush_64 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_64 <= _GEN_5719;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_65 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_65 <= dirty_65;
- end else if (8'h41 == replaceIdReg) begin
- flush_65 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_65 <= _GEN_5720;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_66 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_66 <= dirty_66;
- end else if (8'h42 == replaceIdReg) begin
- flush_66 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_66 <= _GEN_5721;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_67 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_67 <= dirty_67;
- end else if (8'h43 == replaceIdReg) begin
- flush_67 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_67 <= _GEN_5722;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_68 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_68 <= dirty_68;
- end else if (8'h44 == replaceIdReg) begin
- flush_68 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_68 <= _GEN_5723;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_69 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_69 <= dirty_69;
- end else if (8'h45 == replaceIdReg) begin
- flush_69 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_69 <= _GEN_5724;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_70 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_70 <= dirty_70;
- end else if (8'h46 == replaceIdReg) begin
- flush_70 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_70 <= _GEN_5725;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_71 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_71 <= dirty_71;
- end else if (8'h47 == replaceIdReg) begin
- flush_71 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_71 <= _GEN_5726;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_72 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_72 <= dirty_72;
- end else if (8'h48 == replaceIdReg) begin
- flush_72 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_72 <= _GEN_5727;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_73 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_73 <= dirty_73;
- end else if (8'h49 == replaceIdReg) begin
- flush_73 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_73 <= _GEN_5728;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_74 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_74 <= dirty_74;
- end else if (8'h4a == replaceIdReg) begin
- flush_74 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_74 <= _GEN_5729;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_75 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_75 <= dirty_75;
- end else if (8'h4b == replaceIdReg) begin
- flush_75 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_75 <= _GEN_5730;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_76 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_76 <= dirty_76;
- end else if (8'h4c == replaceIdReg) begin
- flush_76 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_76 <= _GEN_5731;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_77 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_77 <= dirty_77;
- end else if (8'h4d == replaceIdReg) begin
- flush_77 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_77 <= _GEN_5732;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_78 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_78 <= dirty_78;
- end else if (8'h4e == replaceIdReg) begin
- flush_78 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_78 <= _GEN_5733;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_79 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_79 <= dirty_79;
- end else if (8'h4f == replaceIdReg) begin
- flush_79 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_79 <= _GEN_5734;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_80 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_80 <= dirty_80;
- end else if (8'h50 == replaceIdReg) begin
- flush_80 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_80 <= _GEN_5735;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_81 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_81 <= dirty_81;
- end else if (8'h51 == replaceIdReg) begin
- flush_81 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_81 <= _GEN_5736;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_82 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_82 <= dirty_82;
- end else if (8'h52 == replaceIdReg) begin
- flush_82 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_82 <= _GEN_5737;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_83 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_83 <= dirty_83;
- end else if (8'h53 == replaceIdReg) begin
- flush_83 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_83 <= _GEN_5738;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_84 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_84 <= dirty_84;
- end else if (8'h54 == replaceIdReg) begin
- flush_84 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_84 <= _GEN_5739;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_85 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_85 <= dirty_85;
- end else if (8'h55 == replaceIdReg) begin
- flush_85 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_85 <= _GEN_5740;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_86 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_86 <= dirty_86;
- end else if (8'h56 == replaceIdReg) begin
- flush_86 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_86 <= _GEN_5741;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_87 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_87 <= dirty_87;
- end else if (8'h57 == replaceIdReg) begin
- flush_87 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_87 <= _GEN_5742;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_88 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_88 <= dirty_88;
- end else if (8'h58 == replaceIdReg) begin
- flush_88 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_88 <= _GEN_5743;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_89 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_89 <= dirty_89;
- end else if (8'h59 == replaceIdReg) begin
- flush_89 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_89 <= _GEN_5744;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_90 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_90 <= dirty_90;
- end else if (8'h5a == replaceIdReg) begin
- flush_90 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_90 <= _GEN_5745;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_91 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_91 <= dirty_91;
- end else if (8'h5b == replaceIdReg) begin
- flush_91 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_91 <= _GEN_5746;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_92 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_92 <= dirty_92;
- end else if (8'h5c == replaceIdReg) begin
- flush_92 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_92 <= _GEN_5747;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_93 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_93 <= dirty_93;
- end else if (8'h5d == replaceIdReg) begin
- flush_93 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_93 <= _GEN_5748;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_94 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_94 <= dirty_94;
- end else if (8'h5e == replaceIdReg) begin
- flush_94 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_94 <= _GEN_5749;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_95 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_95 <= dirty_95;
- end else if (8'h5f == replaceIdReg) begin
- flush_95 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_95 <= _GEN_5750;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_96 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_96 <= dirty_96;
- end else if (8'h60 == replaceIdReg) begin
- flush_96 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_96 <= _GEN_5751;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_97 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_97 <= dirty_97;
- end else if (8'h61 == replaceIdReg) begin
- flush_97 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_97 <= _GEN_5752;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_98 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_98 <= dirty_98;
- end else if (8'h62 == replaceIdReg) begin
- flush_98 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_98 <= _GEN_5753;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_99 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_99 <= dirty_99;
- end else if (8'h63 == replaceIdReg) begin
- flush_99 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_99 <= _GEN_5754;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_100 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_100 <= dirty_100;
- end else if (8'h64 == replaceIdReg) begin
- flush_100 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_100 <= _GEN_5755;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_101 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_101 <= dirty_101;
- end else if (8'h65 == replaceIdReg) begin
- flush_101 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_101 <= _GEN_5756;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_102 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_102 <= dirty_102;
- end else if (8'h66 == replaceIdReg) begin
- flush_102 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_102 <= _GEN_5757;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_103 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_103 <= dirty_103;
- end else if (8'h67 == replaceIdReg) begin
- flush_103 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_103 <= _GEN_5758;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_104 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_104 <= dirty_104;
- end else if (8'h68 == replaceIdReg) begin
- flush_104 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_104 <= _GEN_5759;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_105 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_105 <= dirty_105;
- end else if (8'h69 == replaceIdReg) begin
- flush_105 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_105 <= _GEN_5760;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_106 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_106 <= dirty_106;
- end else if (8'h6a == replaceIdReg) begin
- flush_106 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_106 <= _GEN_5761;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_107 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_107 <= dirty_107;
- end else if (8'h6b == replaceIdReg) begin
- flush_107 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_107 <= _GEN_5762;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_108 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_108 <= dirty_108;
- end else if (8'h6c == replaceIdReg) begin
- flush_108 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_108 <= _GEN_5763;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_109 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_109 <= dirty_109;
- end else if (8'h6d == replaceIdReg) begin
- flush_109 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_109 <= _GEN_5764;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_110 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_110 <= dirty_110;
- end else if (8'h6e == replaceIdReg) begin
- flush_110 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_110 <= _GEN_5765;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_111 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_111 <= dirty_111;
- end else if (8'h6f == replaceIdReg) begin
- flush_111 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_111 <= _GEN_5766;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_112 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_112 <= dirty_112;
- end else if (8'h70 == replaceIdReg) begin
- flush_112 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_112 <= _GEN_5767;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_113 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_113 <= dirty_113;
- end else if (8'h71 == replaceIdReg) begin
- flush_113 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_113 <= _GEN_5768;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_114 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_114 <= dirty_114;
- end else if (8'h72 == replaceIdReg) begin
- flush_114 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_114 <= _GEN_5769;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_115 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_115 <= dirty_115;
- end else if (8'h73 == replaceIdReg) begin
- flush_115 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_115 <= _GEN_5770;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_116 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_116 <= dirty_116;
- end else if (8'h74 == replaceIdReg) begin
- flush_116 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_116 <= _GEN_5771;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_117 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_117 <= dirty_117;
- end else if (8'h75 == replaceIdReg) begin
- flush_117 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_117 <= _GEN_5772;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_118 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_118 <= dirty_118;
- end else if (8'h76 == replaceIdReg) begin
- flush_118 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_118 <= _GEN_5773;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_119 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_119 <= dirty_119;
- end else if (8'h77 == replaceIdReg) begin
- flush_119 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_119 <= _GEN_5774;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_120 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_120 <= dirty_120;
- end else if (8'h78 == replaceIdReg) begin
- flush_120 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_120 <= _GEN_5775;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_121 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_121 <= dirty_121;
- end else if (8'h79 == replaceIdReg) begin
- flush_121 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_121 <= _GEN_5776;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_122 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_122 <= dirty_122;
- end else if (8'h7a == replaceIdReg) begin
- flush_122 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_122 <= _GEN_5777;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_123 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_123 <= dirty_123;
- end else if (8'h7b == replaceIdReg) begin
- flush_123 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_123 <= _GEN_5778;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_124 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_124 <= dirty_124;
- end else if (8'h7c == replaceIdReg) begin
- flush_124 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_124 <= _GEN_5779;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_125 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_125 <= dirty_125;
- end else if (8'h7d == replaceIdReg) begin
- flush_125 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_125 <= _GEN_5780;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_126 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_126 <= dirty_126;
- end else if (8'h7e == replaceIdReg) begin
- flush_126 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_126 <= _GEN_5781;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_127 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_127 <= dirty_127;
- end else if (8'h7f == replaceIdReg) begin
- flush_127 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_127 <= _GEN_5782;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_128 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_128 <= dirty_128;
- end else if (8'h80 == replaceIdReg) begin
- flush_128 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_128 <= _GEN_5783;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_129 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_129 <= dirty_129;
- end else if (8'h81 == replaceIdReg) begin
- flush_129 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_129 <= _GEN_5784;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_130 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_130 <= dirty_130;
- end else if (8'h82 == replaceIdReg) begin
- flush_130 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_130 <= _GEN_5785;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_131 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_131 <= dirty_131;
- end else if (8'h83 == replaceIdReg) begin
- flush_131 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_131 <= _GEN_5786;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_132 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_132 <= dirty_132;
- end else if (8'h84 == replaceIdReg) begin
- flush_132 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_132 <= _GEN_5787;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_133 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_133 <= dirty_133;
- end else if (8'h85 == replaceIdReg) begin
- flush_133 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_133 <= _GEN_5788;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_134 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_134 <= dirty_134;
- end else if (8'h86 == replaceIdReg) begin
- flush_134 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_134 <= _GEN_5789;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_135 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_135 <= dirty_135;
- end else if (8'h87 == replaceIdReg) begin
- flush_135 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_135 <= _GEN_5790;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_136 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_136 <= dirty_136;
- end else if (8'h88 == replaceIdReg) begin
- flush_136 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_136 <= _GEN_5791;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_137 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_137 <= dirty_137;
- end else if (8'h89 == replaceIdReg) begin
- flush_137 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_137 <= _GEN_5792;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_138 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_138 <= dirty_138;
- end else if (8'h8a == replaceIdReg) begin
- flush_138 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_138 <= _GEN_5793;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_139 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_139 <= dirty_139;
- end else if (8'h8b == replaceIdReg) begin
- flush_139 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_139 <= _GEN_5794;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_140 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_140 <= dirty_140;
- end else if (8'h8c == replaceIdReg) begin
- flush_140 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_140 <= _GEN_5795;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_141 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_141 <= dirty_141;
- end else if (8'h8d == replaceIdReg) begin
- flush_141 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_141 <= _GEN_5796;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_142 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_142 <= dirty_142;
- end else if (8'h8e == replaceIdReg) begin
- flush_142 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_142 <= _GEN_5797;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_143 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_143 <= dirty_143;
- end else if (8'h8f == replaceIdReg) begin
- flush_143 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_143 <= _GEN_5798;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_144 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_144 <= dirty_144;
- end else if (8'h90 == replaceIdReg) begin
- flush_144 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_144 <= _GEN_5799;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_145 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_145 <= dirty_145;
- end else if (8'h91 == replaceIdReg) begin
- flush_145 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_145 <= _GEN_5800;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_146 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_146 <= dirty_146;
- end else if (8'h92 == replaceIdReg) begin
- flush_146 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_146 <= _GEN_5801;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_147 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_147 <= dirty_147;
- end else if (8'h93 == replaceIdReg) begin
- flush_147 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_147 <= _GEN_5802;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_148 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_148 <= dirty_148;
- end else if (8'h94 == replaceIdReg) begin
- flush_148 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_148 <= _GEN_5803;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_149 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_149 <= dirty_149;
- end else if (8'h95 == replaceIdReg) begin
- flush_149 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_149 <= _GEN_5804;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_150 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_150 <= dirty_150;
- end else if (8'h96 == replaceIdReg) begin
- flush_150 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_150 <= _GEN_5805;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_151 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_151 <= dirty_151;
- end else if (8'h97 == replaceIdReg) begin
- flush_151 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_151 <= _GEN_5806;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_152 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_152 <= dirty_152;
- end else if (8'h98 == replaceIdReg) begin
- flush_152 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_152 <= _GEN_5807;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_153 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_153 <= dirty_153;
- end else if (8'h99 == replaceIdReg) begin
- flush_153 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_153 <= _GEN_5808;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_154 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_154 <= dirty_154;
- end else if (8'h9a == replaceIdReg) begin
- flush_154 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_154 <= _GEN_5809;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_155 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_155 <= dirty_155;
- end else if (8'h9b == replaceIdReg) begin
- flush_155 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_155 <= _GEN_5810;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_156 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_156 <= dirty_156;
- end else if (8'h9c == replaceIdReg) begin
- flush_156 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_156 <= _GEN_5811;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_157 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_157 <= dirty_157;
- end else if (8'h9d == replaceIdReg) begin
- flush_157 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_157 <= _GEN_5812;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_158 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_158 <= dirty_158;
- end else if (8'h9e == replaceIdReg) begin
- flush_158 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_158 <= _GEN_5813;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_159 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_159 <= dirty_159;
- end else if (8'h9f == replaceIdReg) begin
- flush_159 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_159 <= _GEN_5814;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_160 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_160 <= dirty_160;
- end else if (8'ha0 == replaceIdReg) begin
- flush_160 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_160 <= _GEN_5815;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_161 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_161 <= dirty_161;
- end else if (8'ha1 == replaceIdReg) begin
- flush_161 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_161 <= _GEN_5816;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_162 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_162 <= dirty_162;
- end else if (8'ha2 == replaceIdReg) begin
- flush_162 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_162 <= _GEN_5817;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_163 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_163 <= dirty_163;
- end else if (8'ha3 == replaceIdReg) begin
- flush_163 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_163 <= _GEN_5818;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_164 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_164 <= dirty_164;
- end else if (8'ha4 == replaceIdReg) begin
- flush_164 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_164 <= _GEN_5819;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_165 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_165 <= dirty_165;
- end else if (8'ha5 == replaceIdReg) begin
- flush_165 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_165 <= _GEN_5820;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_166 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_166 <= dirty_166;
- end else if (8'ha6 == replaceIdReg) begin
- flush_166 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_166 <= _GEN_5821;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_167 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_167 <= dirty_167;
- end else if (8'ha7 == replaceIdReg) begin
- flush_167 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_167 <= _GEN_5822;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_168 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_168 <= dirty_168;
- end else if (8'ha8 == replaceIdReg) begin
- flush_168 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_168 <= _GEN_5823;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_169 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_169 <= dirty_169;
- end else if (8'ha9 == replaceIdReg) begin
- flush_169 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_169 <= _GEN_5824;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_170 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_170 <= dirty_170;
- end else if (8'haa == replaceIdReg) begin
- flush_170 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_170 <= _GEN_5825;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_171 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_171 <= dirty_171;
- end else if (8'hab == replaceIdReg) begin
- flush_171 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_171 <= _GEN_5826;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_172 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_172 <= dirty_172;
- end else if (8'hac == replaceIdReg) begin
- flush_172 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_172 <= _GEN_5827;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_173 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_173 <= dirty_173;
- end else if (8'had == replaceIdReg) begin
- flush_173 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_173 <= _GEN_5828;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_174 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_174 <= dirty_174;
- end else if (8'hae == replaceIdReg) begin
- flush_174 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_174 <= _GEN_5829;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_175 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_175 <= dirty_175;
- end else if (8'haf == replaceIdReg) begin
- flush_175 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_175 <= _GEN_5830;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_176 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_176 <= dirty_176;
- end else if (8'hb0 == replaceIdReg) begin
- flush_176 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_176 <= _GEN_5831;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_177 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_177 <= dirty_177;
- end else if (8'hb1 == replaceIdReg) begin
- flush_177 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_177 <= _GEN_5832;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_178 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_178 <= dirty_178;
- end else if (8'hb2 == replaceIdReg) begin
- flush_178 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_178 <= _GEN_5833;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_179 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_179 <= dirty_179;
- end else if (8'hb3 == replaceIdReg) begin
- flush_179 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_179 <= _GEN_5834;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_180 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_180 <= dirty_180;
- end else if (8'hb4 == replaceIdReg) begin
- flush_180 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_180 <= _GEN_5835;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_181 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_181 <= dirty_181;
- end else if (8'hb5 == replaceIdReg) begin
- flush_181 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_181 <= _GEN_5836;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_182 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_182 <= dirty_182;
- end else if (8'hb6 == replaceIdReg) begin
- flush_182 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_182 <= _GEN_5837;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_183 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_183 <= dirty_183;
- end else if (8'hb7 == replaceIdReg) begin
- flush_183 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_183 <= _GEN_5838;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_184 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_184 <= dirty_184;
- end else if (8'hb8 == replaceIdReg) begin
- flush_184 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_184 <= _GEN_5839;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_185 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_185 <= dirty_185;
- end else if (8'hb9 == replaceIdReg) begin
- flush_185 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_185 <= _GEN_5840;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_186 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_186 <= dirty_186;
- end else if (8'hba == replaceIdReg) begin
- flush_186 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_186 <= _GEN_5841;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_187 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_187 <= dirty_187;
- end else if (8'hbb == replaceIdReg) begin
- flush_187 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_187 <= _GEN_5842;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_188 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_188 <= dirty_188;
- end else if (8'hbc == replaceIdReg) begin
- flush_188 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_188 <= _GEN_5843;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_189 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_189 <= dirty_189;
- end else if (8'hbd == replaceIdReg) begin
- flush_189 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_189 <= _GEN_5844;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_190 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_190 <= dirty_190;
- end else if (8'hbe == replaceIdReg) begin
- flush_190 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_190 <= _GEN_5845;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_191 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_191 <= dirty_191;
- end else if (8'hbf == replaceIdReg) begin
- flush_191 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_191 <= _GEN_5846;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_192 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_192 <= dirty_192;
- end else if (8'hc0 == replaceIdReg) begin
- flush_192 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_192 <= _GEN_5847;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_193 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_193 <= dirty_193;
- end else if (8'hc1 == replaceIdReg) begin
- flush_193 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_193 <= _GEN_5848;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_194 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_194 <= dirty_194;
- end else if (8'hc2 == replaceIdReg) begin
- flush_194 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_194 <= _GEN_5849;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_195 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_195 <= dirty_195;
- end else if (8'hc3 == replaceIdReg) begin
- flush_195 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_195 <= _GEN_5850;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_196 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_196 <= dirty_196;
- end else if (8'hc4 == replaceIdReg) begin
- flush_196 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_196 <= _GEN_5851;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_197 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_197 <= dirty_197;
- end else if (8'hc5 == replaceIdReg) begin
- flush_197 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_197 <= _GEN_5852;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_198 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_198 <= dirty_198;
- end else if (8'hc6 == replaceIdReg) begin
- flush_198 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_198 <= _GEN_5853;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_199 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_199 <= dirty_199;
- end else if (8'hc7 == replaceIdReg) begin
- flush_199 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_199 <= _GEN_5854;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_200 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_200 <= dirty_200;
- end else if (8'hc8 == replaceIdReg) begin
- flush_200 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_200 <= _GEN_5855;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_201 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_201 <= dirty_201;
- end else if (8'hc9 == replaceIdReg) begin
- flush_201 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_201 <= _GEN_5856;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_202 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_202 <= dirty_202;
- end else if (8'hca == replaceIdReg) begin
- flush_202 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_202 <= _GEN_5857;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_203 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_203 <= dirty_203;
- end else if (8'hcb == replaceIdReg) begin
- flush_203 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_203 <= _GEN_5858;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_204 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_204 <= dirty_204;
- end else if (8'hcc == replaceIdReg) begin
- flush_204 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_204 <= _GEN_5859;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_205 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_205 <= dirty_205;
- end else if (8'hcd == replaceIdReg) begin
- flush_205 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_205 <= _GEN_5860;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_206 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_206 <= dirty_206;
- end else if (8'hce == replaceIdReg) begin
- flush_206 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_206 <= _GEN_5861;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_207 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_207 <= dirty_207;
- end else if (8'hcf == replaceIdReg) begin
- flush_207 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_207 <= _GEN_5862;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_208 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_208 <= dirty_208;
- end else if (8'hd0 == replaceIdReg) begin
- flush_208 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_208 <= _GEN_5863;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_209 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_209 <= dirty_209;
- end else if (8'hd1 == replaceIdReg) begin
- flush_209 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_209 <= _GEN_5864;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_210 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_210 <= dirty_210;
- end else if (8'hd2 == replaceIdReg) begin
- flush_210 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_210 <= _GEN_5865;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_211 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_211 <= dirty_211;
- end else if (8'hd3 == replaceIdReg) begin
- flush_211 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_211 <= _GEN_5866;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_212 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_212 <= dirty_212;
- end else if (8'hd4 == replaceIdReg) begin
- flush_212 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_212 <= _GEN_5867;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_213 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_213 <= dirty_213;
- end else if (8'hd5 == replaceIdReg) begin
- flush_213 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_213 <= _GEN_5868;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_214 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_214 <= dirty_214;
- end else if (8'hd6 == replaceIdReg) begin
- flush_214 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_214 <= _GEN_5869;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_215 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_215 <= dirty_215;
- end else if (8'hd7 == replaceIdReg) begin
- flush_215 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_215 <= _GEN_5870;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_216 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_216 <= dirty_216;
- end else if (8'hd8 == replaceIdReg) begin
- flush_216 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_216 <= _GEN_5871;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_217 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_217 <= dirty_217;
- end else if (8'hd9 == replaceIdReg) begin
- flush_217 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_217 <= _GEN_5872;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_218 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_218 <= dirty_218;
- end else if (8'hda == replaceIdReg) begin
- flush_218 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_218 <= _GEN_5873;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_219 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_219 <= dirty_219;
- end else if (8'hdb == replaceIdReg) begin
- flush_219 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_219 <= _GEN_5874;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_220 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_220 <= dirty_220;
- end else if (8'hdc == replaceIdReg) begin
- flush_220 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_220 <= _GEN_5875;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_221 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_221 <= dirty_221;
- end else if (8'hdd == replaceIdReg) begin
- flush_221 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_221 <= _GEN_5876;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_222 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_222 <= dirty_222;
- end else if (8'hde == replaceIdReg) begin
- flush_222 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_222 <= _GEN_5877;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_223 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_223 <= dirty_223;
- end else if (8'hdf == replaceIdReg) begin
- flush_223 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_223 <= _GEN_5878;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_224 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_224 <= dirty_224;
- end else if (8'he0 == replaceIdReg) begin
- flush_224 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_224 <= _GEN_5879;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_225 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_225 <= dirty_225;
- end else if (8'he1 == replaceIdReg) begin
- flush_225 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_225 <= _GEN_5880;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_226 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_226 <= dirty_226;
- end else if (8'he2 == replaceIdReg) begin
- flush_226 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_226 <= _GEN_5881;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_227 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_227 <= dirty_227;
- end else if (8'he3 == replaceIdReg) begin
- flush_227 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_227 <= _GEN_5882;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_228 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_228 <= dirty_228;
- end else if (8'he4 == replaceIdReg) begin
- flush_228 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_228 <= _GEN_5883;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_229 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_229 <= dirty_229;
- end else if (8'he5 == replaceIdReg) begin
- flush_229 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_229 <= _GEN_5884;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_230 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_230 <= dirty_230;
- end else if (8'he6 == replaceIdReg) begin
- flush_230 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_230 <= _GEN_5885;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_231 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_231 <= dirty_231;
- end else if (8'he7 == replaceIdReg) begin
- flush_231 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_231 <= _GEN_5886;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_232 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_232 <= dirty_232;
- end else if (8'he8 == replaceIdReg) begin
- flush_232 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_232 <= _GEN_5887;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_233 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_233 <= dirty_233;
- end else if (8'he9 == replaceIdReg) begin
- flush_233 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_233 <= _GEN_5888;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_234 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_234 <= dirty_234;
- end else if (8'hea == replaceIdReg) begin
- flush_234 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_234 <= _GEN_5889;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_235 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_235 <= dirty_235;
- end else if (8'heb == replaceIdReg) begin
- flush_235 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_235 <= _GEN_5890;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_236 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_236 <= dirty_236;
- end else if (8'hec == replaceIdReg) begin
- flush_236 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_236 <= _GEN_5891;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_237 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_237 <= dirty_237;
- end else if (8'hed == replaceIdReg) begin
- flush_237 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_237 <= _GEN_5892;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_238 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_238 <= dirty_238;
- end else if (8'hee == replaceIdReg) begin
- flush_238 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_238 <= _GEN_5893;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_239 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_239 <= dirty_239;
- end else if (8'hef == replaceIdReg) begin
- flush_239 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_239 <= _GEN_5894;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_240 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_240 <= dirty_240;
- end else if (8'hf0 == replaceIdReg) begin
- flush_240 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_240 <= _GEN_5895;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_241 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_241 <= dirty_241;
- end else if (8'hf1 == replaceIdReg) begin
- flush_241 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_241 <= _GEN_5896;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_242 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_242 <= dirty_242;
- end else if (8'hf2 == replaceIdReg) begin
- flush_242 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_242 <= _GEN_5897;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_243 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_243 <= dirty_243;
- end else if (8'hf3 == replaceIdReg) begin
- flush_243 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_243 <= _GEN_5898;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_244 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_244 <= dirty_244;
- end else if (8'hf4 == replaceIdReg) begin
- flush_244 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_244 <= _GEN_5899;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_245 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_245 <= dirty_245;
- end else if (8'hf5 == replaceIdReg) begin
- flush_245 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_245 <= _GEN_5900;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_246 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_246 <= dirty_246;
- end else if (8'hf6 == replaceIdReg) begin
- flush_246 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_246 <= _GEN_5901;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_247 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_247 <= dirty_247;
- end else if (8'hf7 == replaceIdReg) begin
- flush_247 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_247 <= _GEN_5902;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_248 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_248 <= dirty_248;
- end else if (8'hf8 == replaceIdReg) begin
- flush_248 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_248 <= _GEN_5903;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_249 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_249 <= dirty_249;
- end else if (8'hf9 == replaceIdReg) begin
- flush_249 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_249 <= _GEN_5904;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_250 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_250 <= dirty_250;
- end else if (8'hfa == replaceIdReg) begin
- flush_250 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_250 <= _GEN_5905;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_251 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_251 <= dirty_251;
- end else if (8'hfb == replaceIdReg) begin
- flush_251 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_251 <= _GEN_5906;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_252 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_252 <= dirty_252;
- end else if (8'hfc == replaceIdReg) begin
- flush_252 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_252 <= _GEN_5907;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_253 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_253 <= dirty_253;
- end else if (8'hfd == replaceIdReg) begin
- flush_253 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_253 <= _GEN_5908;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_254 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_254 <= dirty_254;
- end else if (8'hfe == replaceIdReg) begin
- flush_254 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_254 <= _GEN_5909;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- flush_255 <= 1'h0; // @[L1DCache.scala 463:22]
- end else if (!(3'h0 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- if (io_flush_all) begin // @[L1DCache.scala 463:22]
- flush_255 <= dirty_255;
- end else if (8'hff == replaceIdReg) begin
- flush_255 <= _GEN_5140;
- end
- end else if (!(3'h2 == fstate)) begin // @[L1DCache.scala 582:18]
- if (3'h3 == fstate) begin // @[L1DCache.scala 463:22]
- flush_255 <= _GEN_5910;
- end
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 516:59]
- ractive <= 1'h0; // @[L1DCache.scala 519:13]
- end else if (io_axi_read_data_valid & io_axi_read_data_ready) begin
- ractive <= 1'h0;
- end else begin
- ractive <= _GEN_2816;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 538:61]
- wactive <= 1'h0; // @[L1DCache.scala 539:13]
- end else if (io_axi_write_resp_valid & io_axi_write_resp_ready) begin // @[L1DCache.scala 490:53]
- wactive <= 1'h0; // @[L1DCache.scala 492:{13,13,13,13}]
- end else if (io_dbus_valid & ~io_dbus_ready & ~active) begin // @[L1DCache.scala 468:24]
- if (8'hff == replaceId) begin
- wactive <= dirty_255;
- end else if (8'hfe == replaceId) begin
- wactive <= dirty_254;
- end else begin
- wactive <= _GEN_1533;
- end
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 512:59]
- axiraddrvalid <= 1'h0; // @[L1DCache.scala 513:19]
- end else if (io_axi_read_addr_valid & io_axi_read_addr_ready) begin
- axiraddrvalid <= 1'h0;
- end else begin
- axiraddrvalid <= _GEN_2818;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 516:59]
- axirdataready <= 1'h0; // @[L1DCache.scala 518:19]
- end else if (io_axi_read_data_valid & io_axi_read_data_ready) begin
- axirdataready <= 1'h0;
- end else begin
- axirdataready <= _GEN_2819;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 582:18]
- axiwrite <= 1'h0; // @[L1DCache.scala 505:14]
- end else if (3'h0 == fstate) begin // @[L1DCache.scala 582:18]
- axiwrite <= _T_4247 & _GEN_1535; // @[L1DCache.scala 505:14]
- end else if (3'h1 == fstate) begin // @[L1DCache.scala 582:18]
- axiwrite <= _T_4247 & _GEN_1535; // @[L1DCache.scala 505:14 601:35 605:20]
- end else if (3'h2 == fstate) begin // @[L1DCache.scala 505:14]
- if (_flushId_T == 256'h0) begin
- axiwrite <= _T_4247 & _GEN_1535;
- end else begin
- axiwrite <= 1'h1;
- end
- end else begin
- axiwrite <= _T_4247 & _GEN_1535;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 477:27]
- memwdataEn <= 1'h0; // @[L1DCache.scala 477:27]
- end else begin
- memwdataEn <= axiwrite; // @[L1DCache.scala 506:14]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 530:61]
- axiwaddrvalid <= 1'h0; // @[L1DCache.scala 531:19]
- end else if (io_axi_write_addr_valid & io_axi_write_addr_ready) begin
- axiwaddrvalid <= 1'h0;
- end else begin
- axiwaddrvalid <= _GEN_4620;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 534:61]
- axiwdatavalid <= 1'h0; // @[L1DCache.scala 535:19]
- end else if (io_axi_write_data_valid & io_axi_write_data_ready) begin
- axiwdatavalid <= 1'h0;
- end else begin
- axiwdatavalid <= _GEN_4621;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 568:32]
- wrespcnt <= 9'h0; // @[L1DCache.scala 569:14]
- end else if (_T_4258 & ~_T_4260) begin // @[L1DCache.scala 570:39]
- wrespcnt <= _wrespcnt_T_1; // @[L1DCache.scala 571:14]
- end else if (~_T_4258 & _T_4260) begin // @[L1DCache.scala 564:25]
- wrespcnt <= _wrespcnt_T_3;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- valid_0 = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- valid_1 = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- valid_2 = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- valid_3 = _RAND_3[0:0];
- _RAND_4 = {1{`RANDOM}};
- valid_4 = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- valid_5 = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- valid_6 = _RAND_6[0:0];
- _RAND_7 = {1{`RANDOM}};
- valid_7 = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- valid_8 = _RAND_8[0:0];
- _RAND_9 = {1{`RANDOM}};
- valid_9 = _RAND_9[0:0];
- _RAND_10 = {1{`RANDOM}};
- valid_10 = _RAND_10[0:0];
- _RAND_11 = {1{`RANDOM}};
- valid_11 = _RAND_11[0:0];
- _RAND_12 = {1{`RANDOM}};
- valid_12 = _RAND_12[0:0];
- _RAND_13 = {1{`RANDOM}};
- valid_13 = _RAND_13[0:0];
- _RAND_14 = {1{`RANDOM}};
- valid_14 = _RAND_14[0:0];
- _RAND_15 = {1{`RANDOM}};
- valid_15 = _RAND_15[0:0];
- _RAND_16 = {1{`RANDOM}};
- valid_16 = _RAND_16[0:0];
- _RAND_17 = {1{`RANDOM}};
- valid_17 = _RAND_17[0:0];
- _RAND_18 = {1{`RANDOM}};
- valid_18 = _RAND_18[0:0];
- _RAND_19 = {1{`RANDOM}};
- valid_19 = _RAND_19[0:0];
- _RAND_20 = {1{`RANDOM}};
- valid_20 = _RAND_20[0:0];
- _RAND_21 = {1{`RANDOM}};
- valid_21 = _RAND_21[0:0];
- _RAND_22 = {1{`RANDOM}};
- valid_22 = _RAND_22[0:0];
- _RAND_23 = {1{`RANDOM}};
- valid_23 = _RAND_23[0:0];
- _RAND_24 = {1{`RANDOM}};
- valid_24 = _RAND_24[0:0];
- _RAND_25 = {1{`RANDOM}};
- valid_25 = _RAND_25[0:0];
- _RAND_26 = {1{`RANDOM}};
- valid_26 = _RAND_26[0:0];
- _RAND_27 = {1{`RANDOM}};
- valid_27 = _RAND_27[0:0];
- _RAND_28 = {1{`RANDOM}};
- valid_28 = _RAND_28[0:0];
- _RAND_29 = {1{`RANDOM}};
- valid_29 = _RAND_29[0:0];
- _RAND_30 = {1{`RANDOM}};
- valid_30 = _RAND_30[0:0];
- _RAND_31 = {1{`RANDOM}};
- valid_31 = _RAND_31[0:0];
- _RAND_32 = {1{`RANDOM}};
- valid_32 = _RAND_32[0:0];
- _RAND_33 = {1{`RANDOM}};
- valid_33 = _RAND_33[0:0];
- _RAND_34 = {1{`RANDOM}};
- valid_34 = _RAND_34[0:0];
- _RAND_35 = {1{`RANDOM}};
- valid_35 = _RAND_35[0:0];
- _RAND_36 = {1{`RANDOM}};
- valid_36 = _RAND_36[0:0];
- _RAND_37 = {1{`RANDOM}};
- valid_37 = _RAND_37[0:0];
- _RAND_38 = {1{`RANDOM}};
- valid_38 = _RAND_38[0:0];
- _RAND_39 = {1{`RANDOM}};
- valid_39 = _RAND_39[0:0];
- _RAND_40 = {1{`RANDOM}};
- valid_40 = _RAND_40[0:0];
- _RAND_41 = {1{`RANDOM}};
- valid_41 = _RAND_41[0:0];
- _RAND_42 = {1{`RANDOM}};
- valid_42 = _RAND_42[0:0];
- _RAND_43 = {1{`RANDOM}};
- valid_43 = _RAND_43[0:0];
- _RAND_44 = {1{`RANDOM}};
- valid_44 = _RAND_44[0:0];
- _RAND_45 = {1{`RANDOM}};
- valid_45 = _RAND_45[0:0];
- _RAND_46 = {1{`RANDOM}};
- valid_46 = _RAND_46[0:0];
- _RAND_47 = {1{`RANDOM}};
- valid_47 = _RAND_47[0:0];
- _RAND_48 = {1{`RANDOM}};
- valid_48 = _RAND_48[0:0];
- _RAND_49 = {1{`RANDOM}};
- valid_49 = _RAND_49[0:0];
- _RAND_50 = {1{`RANDOM}};
- valid_50 = _RAND_50[0:0];
- _RAND_51 = {1{`RANDOM}};
- valid_51 = _RAND_51[0:0];
- _RAND_52 = {1{`RANDOM}};
- valid_52 = _RAND_52[0:0];
- _RAND_53 = {1{`RANDOM}};
- valid_53 = _RAND_53[0:0];
- _RAND_54 = {1{`RANDOM}};
- valid_54 = _RAND_54[0:0];
- _RAND_55 = {1{`RANDOM}};
- valid_55 = _RAND_55[0:0];
- _RAND_56 = {1{`RANDOM}};
- valid_56 = _RAND_56[0:0];
- _RAND_57 = {1{`RANDOM}};
- valid_57 = _RAND_57[0:0];
- _RAND_58 = {1{`RANDOM}};
- valid_58 = _RAND_58[0:0];
- _RAND_59 = {1{`RANDOM}};
- valid_59 = _RAND_59[0:0];
- _RAND_60 = {1{`RANDOM}};
- valid_60 = _RAND_60[0:0];
- _RAND_61 = {1{`RANDOM}};
- valid_61 = _RAND_61[0:0];
- _RAND_62 = {1{`RANDOM}};
- valid_62 = _RAND_62[0:0];
- _RAND_63 = {1{`RANDOM}};
- valid_63 = _RAND_63[0:0];
- _RAND_64 = {1{`RANDOM}};
- valid_64 = _RAND_64[0:0];
- _RAND_65 = {1{`RANDOM}};
- valid_65 = _RAND_65[0:0];
- _RAND_66 = {1{`RANDOM}};
- valid_66 = _RAND_66[0:0];
- _RAND_67 = {1{`RANDOM}};
- valid_67 = _RAND_67[0:0];
- _RAND_68 = {1{`RANDOM}};
- valid_68 = _RAND_68[0:0];
- _RAND_69 = {1{`RANDOM}};
- valid_69 = _RAND_69[0:0];
- _RAND_70 = {1{`RANDOM}};
- valid_70 = _RAND_70[0:0];
- _RAND_71 = {1{`RANDOM}};
- valid_71 = _RAND_71[0:0];
- _RAND_72 = {1{`RANDOM}};
- valid_72 = _RAND_72[0:0];
- _RAND_73 = {1{`RANDOM}};
- valid_73 = _RAND_73[0:0];
- _RAND_74 = {1{`RANDOM}};
- valid_74 = _RAND_74[0:0];
- _RAND_75 = {1{`RANDOM}};
- valid_75 = _RAND_75[0:0];
- _RAND_76 = {1{`RANDOM}};
- valid_76 = _RAND_76[0:0];
- _RAND_77 = {1{`RANDOM}};
- valid_77 = _RAND_77[0:0];
- _RAND_78 = {1{`RANDOM}};
- valid_78 = _RAND_78[0:0];
- _RAND_79 = {1{`RANDOM}};
- valid_79 = _RAND_79[0:0];
- _RAND_80 = {1{`RANDOM}};
- valid_80 = _RAND_80[0:0];
- _RAND_81 = {1{`RANDOM}};
- valid_81 = _RAND_81[0:0];
- _RAND_82 = {1{`RANDOM}};
- valid_82 = _RAND_82[0:0];
- _RAND_83 = {1{`RANDOM}};
- valid_83 = _RAND_83[0:0];
- _RAND_84 = {1{`RANDOM}};
- valid_84 = _RAND_84[0:0];
- _RAND_85 = {1{`RANDOM}};
- valid_85 = _RAND_85[0:0];
- _RAND_86 = {1{`RANDOM}};
- valid_86 = _RAND_86[0:0];
- _RAND_87 = {1{`RANDOM}};
- valid_87 = _RAND_87[0:0];
- _RAND_88 = {1{`RANDOM}};
- valid_88 = _RAND_88[0:0];
- _RAND_89 = {1{`RANDOM}};
- valid_89 = _RAND_89[0:0];
- _RAND_90 = {1{`RANDOM}};
- valid_90 = _RAND_90[0:0];
- _RAND_91 = {1{`RANDOM}};
- valid_91 = _RAND_91[0:0];
- _RAND_92 = {1{`RANDOM}};
- valid_92 = _RAND_92[0:0];
- _RAND_93 = {1{`RANDOM}};
- valid_93 = _RAND_93[0:0];
- _RAND_94 = {1{`RANDOM}};
- valid_94 = _RAND_94[0:0];
- _RAND_95 = {1{`RANDOM}};
- valid_95 = _RAND_95[0:0];
- _RAND_96 = {1{`RANDOM}};
- valid_96 = _RAND_96[0:0];
- _RAND_97 = {1{`RANDOM}};
- valid_97 = _RAND_97[0:0];
- _RAND_98 = {1{`RANDOM}};
- valid_98 = _RAND_98[0:0];
- _RAND_99 = {1{`RANDOM}};
- valid_99 = _RAND_99[0:0];
- _RAND_100 = {1{`RANDOM}};
- valid_100 = _RAND_100[0:0];
- _RAND_101 = {1{`RANDOM}};
- valid_101 = _RAND_101[0:0];
- _RAND_102 = {1{`RANDOM}};
- valid_102 = _RAND_102[0:0];
- _RAND_103 = {1{`RANDOM}};
- valid_103 = _RAND_103[0:0];
- _RAND_104 = {1{`RANDOM}};
- valid_104 = _RAND_104[0:0];
- _RAND_105 = {1{`RANDOM}};
- valid_105 = _RAND_105[0:0];
- _RAND_106 = {1{`RANDOM}};
- valid_106 = _RAND_106[0:0];
- _RAND_107 = {1{`RANDOM}};
- valid_107 = _RAND_107[0:0];
- _RAND_108 = {1{`RANDOM}};
- valid_108 = _RAND_108[0:0];
- _RAND_109 = {1{`RANDOM}};
- valid_109 = _RAND_109[0:0];
- _RAND_110 = {1{`RANDOM}};
- valid_110 = _RAND_110[0:0];
- _RAND_111 = {1{`RANDOM}};
- valid_111 = _RAND_111[0:0];
- _RAND_112 = {1{`RANDOM}};
- valid_112 = _RAND_112[0:0];
- _RAND_113 = {1{`RANDOM}};
- valid_113 = _RAND_113[0:0];
- _RAND_114 = {1{`RANDOM}};
- valid_114 = _RAND_114[0:0];
- _RAND_115 = {1{`RANDOM}};
- valid_115 = _RAND_115[0:0];
- _RAND_116 = {1{`RANDOM}};
- valid_116 = _RAND_116[0:0];
- _RAND_117 = {1{`RANDOM}};
- valid_117 = _RAND_117[0:0];
- _RAND_118 = {1{`RANDOM}};
- valid_118 = _RAND_118[0:0];
- _RAND_119 = {1{`RANDOM}};
- valid_119 = _RAND_119[0:0];
- _RAND_120 = {1{`RANDOM}};
- valid_120 = _RAND_120[0:0];
- _RAND_121 = {1{`RANDOM}};
- valid_121 = _RAND_121[0:0];
- _RAND_122 = {1{`RANDOM}};
- valid_122 = _RAND_122[0:0];
- _RAND_123 = {1{`RANDOM}};
- valid_123 = _RAND_123[0:0];
- _RAND_124 = {1{`RANDOM}};
- valid_124 = _RAND_124[0:0];
- _RAND_125 = {1{`RANDOM}};
- valid_125 = _RAND_125[0:0];
- _RAND_126 = {1{`RANDOM}};
- valid_126 = _RAND_126[0:0];
- _RAND_127 = {1{`RANDOM}};
- valid_127 = _RAND_127[0:0];
- _RAND_128 = {1{`RANDOM}};
- valid_128 = _RAND_128[0:0];
- _RAND_129 = {1{`RANDOM}};
- valid_129 = _RAND_129[0:0];
- _RAND_130 = {1{`RANDOM}};
- valid_130 = _RAND_130[0:0];
- _RAND_131 = {1{`RANDOM}};
- valid_131 = _RAND_131[0:0];
- _RAND_132 = {1{`RANDOM}};
- valid_132 = _RAND_132[0:0];
- _RAND_133 = {1{`RANDOM}};
- valid_133 = _RAND_133[0:0];
- _RAND_134 = {1{`RANDOM}};
- valid_134 = _RAND_134[0:0];
- _RAND_135 = {1{`RANDOM}};
- valid_135 = _RAND_135[0:0];
- _RAND_136 = {1{`RANDOM}};
- valid_136 = _RAND_136[0:0];
- _RAND_137 = {1{`RANDOM}};
- valid_137 = _RAND_137[0:0];
- _RAND_138 = {1{`RANDOM}};
- valid_138 = _RAND_138[0:0];
- _RAND_139 = {1{`RANDOM}};
- valid_139 = _RAND_139[0:0];
- _RAND_140 = {1{`RANDOM}};
- valid_140 = _RAND_140[0:0];
- _RAND_141 = {1{`RANDOM}};
- valid_141 = _RAND_141[0:0];
- _RAND_142 = {1{`RANDOM}};
- valid_142 = _RAND_142[0:0];
- _RAND_143 = {1{`RANDOM}};
- valid_143 = _RAND_143[0:0];
- _RAND_144 = {1{`RANDOM}};
- valid_144 = _RAND_144[0:0];
- _RAND_145 = {1{`RANDOM}};
- valid_145 = _RAND_145[0:0];
- _RAND_146 = {1{`RANDOM}};
- valid_146 = _RAND_146[0:0];
- _RAND_147 = {1{`RANDOM}};
- valid_147 = _RAND_147[0:0];
- _RAND_148 = {1{`RANDOM}};
- valid_148 = _RAND_148[0:0];
- _RAND_149 = {1{`RANDOM}};
- valid_149 = _RAND_149[0:0];
- _RAND_150 = {1{`RANDOM}};
- valid_150 = _RAND_150[0:0];
- _RAND_151 = {1{`RANDOM}};
- valid_151 = _RAND_151[0:0];
- _RAND_152 = {1{`RANDOM}};
- valid_152 = _RAND_152[0:0];
- _RAND_153 = {1{`RANDOM}};
- valid_153 = _RAND_153[0:0];
- _RAND_154 = {1{`RANDOM}};
- valid_154 = _RAND_154[0:0];
- _RAND_155 = {1{`RANDOM}};
- valid_155 = _RAND_155[0:0];
- _RAND_156 = {1{`RANDOM}};
- valid_156 = _RAND_156[0:0];
- _RAND_157 = {1{`RANDOM}};
- valid_157 = _RAND_157[0:0];
- _RAND_158 = {1{`RANDOM}};
- valid_158 = _RAND_158[0:0];
- _RAND_159 = {1{`RANDOM}};
- valid_159 = _RAND_159[0:0];
- _RAND_160 = {1{`RANDOM}};
- valid_160 = _RAND_160[0:0];
- _RAND_161 = {1{`RANDOM}};
- valid_161 = _RAND_161[0:0];
- _RAND_162 = {1{`RANDOM}};
- valid_162 = _RAND_162[0:0];
- _RAND_163 = {1{`RANDOM}};
- valid_163 = _RAND_163[0:0];
- _RAND_164 = {1{`RANDOM}};
- valid_164 = _RAND_164[0:0];
- _RAND_165 = {1{`RANDOM}};
- valid_165 = _RAND_165[0:0];
- _RAND_166 = {1{`RANDOM}};
- valid_166 = _RAND_166[0:0];
- _RAND_167 = {1{`RANDOM}};
- valid_167 = _RAND_167[0:0];
- _RAND_168 = {1{`RANDOM}};
- valid_168 = _RAND_168[0:0];
- _RAND_169 = {1{`RANDOM}};
- valid_169 = _RAND_169[0:0];
- _RAND_170 = {1{`RANDOM}};
- valid_170 = _RAND_170[0:0];
- _RAND_171 = {1{`RANDOM}};
- valid_171 = _RAND_171[0:0];
- _RAND_172 = {1{`RANDOM}};
- valid_172 = _RAND_172[0:0];
- _RAND_173 = {1{`RANDOM}};
- valid_173 = _RAND_173[0:0];
- _RAND_174 = {1{`RANDOM}};
- valid_174 = _RAND_174[0:0];
- _RAND_175 = {1{`RANDOM}};
- valid_175 = _RAND_175[0:0];
- _RAND_176 = {1{`RANDOM}};
- valid_176 = _RAND_176[0:0];
- _RAND_177 = {1{`RANDOM}};
- valid_177 = _RAND_177[0:0];
- _RAND_178 = {1{`RANDOM}};
- valid_178 = _RAND_178[0:0];
- _RAND_179 = {1{`RANDOM}};
- valid_179 = _RAND_179[0:0];
- _RAND_180 = {1{`RANDOM}};
- valid_180 = _RAND_180[0:0];
- _RAND_181 = {1{`RANDOM}};
- valid_181 = _RAND_181[0:0];
- _RAND_182 = {1{`RANDOM}};
- valid_182 = _RAND_182[0:0];
- _RAND_183 = {1{`RANDOM}};
- valid_183 = _RAND_183[0:0];
- _RAND_184 = {1{`RANDOM}};
- valid_184 = _RAND_184[0:0];
- _RAND_185 = {1{`RANDOM}};
- valid_185 = _RAND_185[0:0];
- _RAND_186 = {1{`RANDOM}};
- valid_186 = _RAND_186[0:0];
- _RAND_187 = {1{`RANDOM}};
- valid_187 = _RAND_187[0:0];
- _RAND_188 = {1{`RANDOM}};
- valid_188 = _RAND_188[0:0];
- _RAND_189 = {1{`RANDOM}};
- valid_189 = _RAND_189[0:0];
- _RAND_190 = {1{`RANDOM}};
- valid_190 = _RAND_190[0:0];
- _RAND_191 = {1{`RANDOM}};
- valid_191 = _RAND_191[0:0];
- _RAND_192 = {1{`RANDOM}};
- valid_192 = _RAND_192[0:0];
- _RAND_193 = {1{`RANDOM}};
- valid_193 = _RAND_193[0:0];
- _RAND_194 = {1{`RANDOM}};
- valid_194 = _RAND_194[0:0];
- _RAND_195 = {1{`RANDOM}};
- valid_195 = _RAND_195[0:0];
- _RAND_196 = {1{`RANDOM}};
- valid_196 = _RAND_196[0:0];
- _RAND_197 = {1{`RANDOM}};
- valid_197 = _RAND_197[0:0];
- _RAND_198 = {1{`RANDOM}};
- valid_198 = _RAND_198[0:0];
- _RAND_199 = {1{`RANDOM}};
- valid_199 = _RAND_199[0:0];
- _RAND_200 = {1{`RANDOM}};
- valid_200 = _RAND_200[0:0];
- _RAND_201 = {1{`RANDOM}};
- valid_201 = _RAND_201[0:0];
- _RAND_202 = {1{`RANDOM}};
- valid_202 = _RAND_202[0:0];
- _RAND_203 = {1{`RANDOM}};
- valid_203 = _RAND_203[0:0];
- _RAND_204 = {1{`RANDOM}};
- valid_204 = _RAND_204[0:0];
- _RAND_205 = {1{`RANDOM}};
- valid_205 = _RAND_205[0:0];
- _RAND_206 = {1{`RANDOM}};
- valid_206 = _RAND_206[0:0];
- _RAND_207 = {1{`RANDOM}};
- valid_207 = _RAND_207[0:0];
- _RAND_208 = {1{`RANDOM}};
- valid_208 = _RAND_208[0:0];
- _RAND_209 = {1{`RANDOM}};
- valid_209 = _RAND_209[0:0];
- _RAND_210 = {1{`RANDOM}};
- valid_210 = _RAND_210[0:0];
- _RAND_211 = {1{`RANDOM}};
- valid_211 = _RAND_211[0:0];
- _RAND_212 = {1{`RANDOM}};
- valid_212 = _RAND_212[0:0];
- _RAND_213 = {1{`RANDOM}};
- valid_213 = _RAND_213[0:0];
- _RAND_214 = {1{`RANDOM}};
- valid_214 = _RAND_214[0:0];
- _RAND_215 = {1{`RANDOM}};
- valid_215 = _RAND_215[0:0];
- _RAND_216 = {1{`RANDOM}};
- valid_216 = _RAND_216[0:0];
- _RAND_217 = {1{`RANDOM}};
- valid_217 = _RAND_217[0:0];
- _RAND_218 = {1{`RANDOM}};
- valid_218 = _RAND_218[0:0];
- _RAND_219 = {1{`RANDOM}};
- valid_219 = _RAND_219[0:0];
- _RAND_220 = {1{`RANDOM}};
- valid_220 = _RAND_220[0:0];
- _RAND_221 = {1{`RANDOM}};
- valid_221 = _RAND_221[0:0];
- _RAND_222 = {1{`RANDOM}};
- valid_222 = _RAND_222[0:0];
- _RAND_223 = {1{`RANDOM}};
- valid_223 = _RAND_223[0:0];
- _RAND_224 = {1{`RANDOM}};
- valid_224 = _RAND_224[0:0];
- _RAND_225 = {1{`RANDOM}};
- valid_225 = _RAND_225[0:0];
- _RAND_226 = {1{`RANDOM}};
- valid_226 = _RAND_226[0:0];
- _RAND_227 = {1{`RANDOM}};
- valid_227 = _RAND_227[0:0];
- _RAND_228 = {1{`RANDOM}};
- valid_228 = _RAND_228[0:0];
- _RAND_229 = {1{`RANDOM}};
- valid_229 = _RAND_229[0:0];
- _RAND_230 = {1{`RANDOM}};
- valid_230 = _RAND_230[0:0];
- _RAND_231 = {1{`RANDOM}};
- valid_231 = _RAND_231[0:0];
- _RAND_232 = {1{`RANDOM}};
- valid_232 = _RAND_232[0:0];
- _RAND_233 = {1{`RANDOM}};
- valid_233 = _RAND_233[0:0];
- _RAND_234 = {1{`RANDOM}};
- valid_234 = _RAND_234[0:0];
- _RAND_235 = {1{`RANDOM}};
- valid_235 = _RAND_235[0:0];
- _RAND_236 = {1{`RANDOM}};
- valid_236 = _RAND_236[0:0];
- _RAND_237 = {1{`RANDOM}};
- valid_237 = _RAND_237[0:0];
- _RAND_238 = {1{`RANDOM}};
- valid_238 = _RAND_238[0:0];
- _RAND_239 = {1{`RANDOM}};
- valid_239 = _RAND_239[0:0];
- _RAND_240 = {1{`RANDOM}};
- valid_240 = _RAND_240[0:0];
- _RAND_241 = {1{`RANDOM}};
- valid_241 = _RAND_241[0:0];
- _RAND_242 = {1{`RANDOM}};
- valid_242 = _RAND_242[0:0];
- _RAND_243 = {1{`RANDOM}};
- valid_243 = _RAND_243[0:0];
- _RAND_244 = {1{`RANDOM}};
- valid_244 = _RAND_244[0:0];
- _RAND_245 = {1{`RANDOM}};
- valid_245 = _RAND_245[0:0];
- _RAND_246 = {1{`RANDOM}};
- valid_246 = _RAND_246[0:0];
- _RAND_247 = {1{`RANDOM}};
- valid_247 = _RAND_247[0:0];
- _RAND_248 = {1{`RANDOM}};
- valid_248 = _RAND_248[0:0];
- _RAND_249 = {1{`RANDOM}};
- valid_249 = _RAND_249[0:0];
- _RAND_250 = {1{`RANDOM}};
- valid_250 = _RAND_250[0:0];
- _RAND_251 = {1{`RANDOM}};
- valid_251 = _RAND_251[0:0];
- _RAND_252 = {1{`RANDOM}};
- valid_252 = _RAND_252[0:0];
- _RAND_253 = {1{`RANDOM}};
- valid_253 = _RAND_253[0:0];
- _RAND_254 = {1{`RANDOM}};
- valid_254 = _RAND_254[0:0];
- _RAND_255 = {1{`RANDOM}};
- valid_255 = _RAND_255[0:0];
- _RAND_256 = {1{`RANDOM}};
- dirty_0 = _RAND_256[0:0];
- _RAND_257 = {1{`RANDOM}};
- dirty_1 = _RAND_257[0:0];
- _RAND_258 = {1{`RANDOM}};
- dirty_2 = _RAND_258[0:0];
- _RAND_259 = {1{`RANDOM}};
- dirty_3 = _RAND_259[0:0];
- _RAND_260 = {1{`RANDOM}};
- dirty_4 = _RAND_260[0:0];
- _RAND_261 = {1{`RANDOM}};
- dirty_5 = _RAND_261[0:0];
- _RAND_262 = {1{`RANDOM}};
- dirty_6 = _RAND_262[0:0];
- _RAND_263 = {1{`RANDOM}};
- dirty_7 = _RAND_263[0:0];
- _RAND_264 = {1{`RANDOM}};
- dirty_8 = _RAND_264[0:0];
- _RAND_265 = {1{`RANDOM}};
- dirty_9 = _RAND_265[0:0];
- _RAND_266 = {1{`RANDOM}};
- dirty_10 = _RAND_266[0:0];
- _RAND_267 = {1{`RANDOM}};
- dirty_11 = _RAND_267[0:0];
- _RAND_268 = {1{`RANDOM}};
- dirty_12 = _RAND_268[0:0];
- _RAND_269 = {1{`RANDOM}};
- dirty_13 = _RAND_269[0:0];
- _RAND_270 = {1{`RANDOM}};
- dirty_14 = _RAND_270[0:0];
- _RAND_271 = {1{`RANDOM}};
- dirty_15 = _RAND_271[0:0];
- _RAND_272 = {1{`RANDOM}};
- dirty_16 = _RAND_272[0:0];
- _RAND_273 = {1{`RANDOM}};
- dirty_17 = _RAND_273[0:0];
- _RAND_274 = {1{`RANDOM}};
- dirty_18 = _RAND_274[0:0];
- _RAND_275 = {1{`RANDOM}};
- dirty_19 = _RAND_275[0:0];
- _RAND_276 = {1{`RANDOM}};
- dirty_20 = _RAND_276[0:0];
- _RAND_277 = {1{`RANDOM}};
- dirty_21 = _RAND_277[0:0];
- _RAND_278 = {1{`RANDOM}};
- dirty_22 = _RAND_278[0:0];
- _RAND_279 = {1{`RANDOM}};
- dirty_23 = _RAND_279[0:0];
- _RAND_280 = {1{`RANDOM}};
- dirty_24 = _RAND_280[0:0];
- _RAND_281 = {1{`RANDOM}};
- dirty_25 = _RAND_281[0:0];
- _RAND_282 = {1{`RANDOM}};
- dirty_26 = _RAND_282[0:0];
- _RAND_283 = {1{`RANDOM}};
- dirty_27 = _RAND_283[0:0];
- _RAND_284 = {1{`RANDOM}};
- dirty_28 = _RAND_284[0:0];
- _RAND_285 = {1{`RANDOM}};
- dirty_29 = _RAND_285[0:0];
- _RAND_286 = {1{`RANDOM}};
- dirty_30 = _RAND_286[0:0];
- _RAND_287 = {1{`RANDOM}};
- dirty_31 = _RAND_287[0:0];
- _RAND_288 = {1{`RANDOM}};
- dirty_32 = _RAND_288[0:0];
- _RAND_289 = {1{`RANDOM}};
- dirty_33 = _RAND_289[0:0];
- _RAND_290 = {1{`RANDOM}};
- dirty_34 = _RAND_290[0:0];
- _RAND_291 = {1{`RANDOM}};
- dirty_35 = _RAND_291[0:0];
- _RAND_292 = {1{`RANDOM}};
- dirty_36 = _RAND_292[0:0];
- _RAND_293 = {1{`RANDOM}};
- dirty_37 = _RAND_293[0:0];
- _RAND_294 = {1{`RANDOM}};
- dirty_38 = _RAND_294[0:0];
- _RAND_295 = {1{`RANDOM}};
- dirty_39 = _RAND_295[0:0];
- _RAND_296 = {1{`RANDOM}};
- dirty_40 = _RAND_296[0:0];
- _RAND_297 = {1{`RANDOM}};
- dirty_41 = _RAND_297[0:0];
- _RAND_298 = {1{`RANDOM}};
- dirty_42 = _RAND_298[0:0];
- _RAND_299 = {1{`RANDOM}};
- dirty_43 = _RAND_299[0:0];
- _RAND_300 = {1{`RANDOM}};
- dirty_44 = _RAND_300[0:0];
- _RAND_301 = {1{`RANDOM}};
- dirty_45 = _RAND_301[0:0];
- _RAND_302 = {1{`RANDOM}};
- dirty_46 = _RAND_302[0:0];
- _RAND_303 = {1{`RANDOM}};
- dirty_47 = _RAND_303[0:0];
- _RAND_304 = {1{`RANDOM}};
- dirty_48 = _RAND_304[0:0];
- _RAND_305 = {1{`RANDOM}};
- dirty_49 = _RAND_305[0:0];
- _RAND_306 = {1{`RANDOM}};
- dirty_50 = _RAND_306[0:0];
- _RAND_307 = {1{`RANDOM}};
- dirty_51 = _RAND_307[0:0];
- _RAND_308 = {1{`RANDOM}};
- dirty_52 = _RAND_308[0:0];
- _RAND_309 = {1{`RANDOM}};
- dirty_53 = _RAND_309[0:0];
- _RAND_310 = {1{`RANDOM}};
- dirty_54 = _RAND_310[0:0];
- _RAND_311 = {1{`RANDOM}};
- dirty_55 = _RAND_311[0:0];
- _RAND_312 = {1{`RANDOM}};
- dirty_56 = _RAND_312[0:0];
- _RAND_313 = {1{`RANDOM}};
- dirty_57 = _RAND_313[0:0];
- _RAND_314 = {1{`RANDOM}};
- dirty_58 = _RAND_314[0:0];
- _RAND_315 = {1{`RANDOM}};
- dirty_59 = _RAND_315[0:0];
- _RAND_316 = {1{`RANDOM}};
- dirty_60 = _RAND_316[0:0];
- _RAND_317 = {1{`RANDOM}};
- dirty_61 = _RAND_317[0:0];
- _RAND_318 = {1{`RANDOM}};
- dirty_62 = _RAND_318[0:0];
- _RAND_319 = {1{`RANDOM}};
- dirty_63 = _RAND_319[0:0];
- _RAND_320 = {1{`RANDOM}};
- dirty_64 = _RAND_320[0:0];
- _RAND_321 = {1{`RANDOM}};
- dirty_65 = _RAND_321[0:0];
- _RAND_322 = {1{`RANDOM}};
- dirty_66 = _RAND_322[0:0];
- _RAND_323 = {1{`RANDOM}};
- dirty_67 = _RAND_323[0:0];
- _RAND_324 = {1{`RANDOM}};
- dirty_68 = _RAND_324[0:0];
- _RAND_325 = {1{`RANDOM}};
- dirty_69 = _RAND_325[0:0];
- _RAND_326 = {1{`RANDOM}};
- dirty_70 = _RAND_326[0:0];
- _RAND_327 = {1{`RANDOM}};
- dirty_71 = _RAND_327[0:0];
- _RAND_328 = {1{`RANDOM}};
- dirty_72 = _RAND_328[0:0];
- _RAND_329 = {1{`RANDOM}};
- dirty_73 = _RAND_329[0:0];
- _RAND_330 = {1{`RANDOM}};
- dirty_74 = _RAND_330[0:0];
- _RAND_331 = {1{`RANDOM}};
- dirty_75 = _RAND_331[0:0];
- _RAND_332 = {1{`RANDOM}};
- dirty_76 = _RAND_332[0:0];
- _RAND_333 = {1{`RANDOM}};
- dirty_77 = _RAND_333[0:0];
- _RAND_334 = {1{`RANDOM}};
- dirty_78 = _RAND_334[0:0];
- _RAND_335 = {1{`RANDOM}};
- dirty_79 = _RAND_335[0:0];
- _RAND_336 = {1{`RANDOM}};
- dirty_80 = _RAND_336[0:0];
- _RAND_337 = {1{`RANDOM}};
- dirty_81 = _RAND_337[0:0];
- _RAND_338 = {1{`RANDOM}};
- dirty_82 = _RAND_338[0:0];
- _RAND_339 = {1{`RANDOM}};
- dirty_83 = _RAND_339[0:0];
- _RAND_340 = {1{`RANDOM}};
- dirty_84 = _RAND_340[0:0];
- _RAND_341 = {1{`RANDOM}};
- dirty_85 = _RAND_341[0:0];
- _RAND_342 = {1{`RANDOM}};
- dirty_86 = _RAND_342[0:0];
- _RAND_343 = {1{`RANDOM}};
- dirty_87 = _RAND_343[0:0];
- _RAND_344 = {1{`RANDOM}};
- dirty_88 = _RAND_344[0:0];
- _RAND_345 = {1{`RANDOM}};
- dirty_89 = _RAND_345[0:0];
- _RAND_346 = {1{`RANDOM}};
- dirty_90 = _RAND_346[0:0];
- _RAND_347 = {1{`RANDOM}};
- dirty_91 = _RAND_347[0:0];
- _RAND_348 = {1{`RANDOM}};
- dirty_92 = _RAND_348[0:0];
- _RAND_349 = {1{`RANDOM}};
- dirty_93 = _RAND_349[0:0];
- _RAND_350 = {1{`RANDOM}};
- dirty_94 = _RAND_350[0:0];
- _RAND_351 = {1{`RANDOM}};
- dirty_95 = _RAND_351[0:0];
- _RAND_352 = {1{`RANDOM}};
- dirty_96 = _RAND_352[0:0];
- _RAND_353 = {1{`RANDOM}};
- dirty_97 = _RAND_353[0:0];
- _RAND_354 = {1{`RANDOM}};
- dirty_98 = _RAND_354[0:0];
- _RAND_355 = {1{`RANDOM}};
- dirty_99 = _RAND_355[0:0];
- _RAND_356 = {1{`RANDOM}};
- dirty_100 = _RAND_356[0:0];
- _RAND_357 = {1{`RANDOM}};
- dirty_101 = _RAND_357[0:0];
- _RAND_358 = {1{`RANDOM}};
- dirty_102 = _RAND_358[0:0];
- _RAND_359 = {1{`RANDOM}};
- dirty_103 = _RAND_359[0:0];
- _RAND_360 = {1{`RANDOM}};
- dirty_104 = _RAND_360[0:0];
- _RAND_361 = {1{`RANDOM}};
- dirty_105 = _RAND_361[0:0];
- _RAND_362 = {1{`RANDOM}};
- dirty_106 = _RAND_362[0:0];
- _RAND_363 = {1{`RANDOM}};
- dirty_107 = _RAND_363[0:0];
- _RAND_364 = {1{`RANDOM}};
- dirty_108 = _RAND_364[0:0];
- _RAND_365 = {1{`RANDOM}};
- dirty_109 = _RAND_365[0:0];
- _RAND_366 = {1{`RANDOM}};
- dirty_110 = _RAND_366[0:0];
- _RAND_367 = {1{`RANDOM}};
- dirty_111 = _RAND_367[0:0];
- _RAND_368 = {1{`RANDOM}};
- dirty_112 = _RAND_368[0:0];
- _RAND_369 = {1{`RANDOM}};
- dirty_113 = _RAND_369[0:0];
- _RAND_370 = {1{`RANDOM}};
- dirty_114 = _RAND_370[0:0];
- _RAND_371 = {1{`RANDOM}};
- dirty_115 = _RAND_371[0:0];
- _RAND_372 = {1{`RANDOM}};
- dirty_116 = _RAND_372[0:0];
- _RAND_373 = {1{`RANDOM}};
- dirty_117 = _RAND_373[0:0];
- _RAND_374 = {1{`RANDOM}};
- dirty_118 = _RAND_374[0:0];
- _RAND_375 = {1{`RANDOM}};
- dirty_119 = _RAND_375[0:0];
- _RAND_376 = {1{`RANDOM}};
- dirty_120 = _RAND_376[0:0];
- _RAND_377 = {1{`RANDOM}};
- dirty_121 = _RAND_377[0:0];
- _RAND_378 = {1{`RANDOM}};
- dirty_122 = _RAND_378[0:0];
- _RAND_379 = {1{`RANDOM}};
- dirty_123 = _RAND_379[0:0];
- _RAND_380 = {1{`RANDOM}};
- dirty_124 = _RAND_380[0:0];
- _RAND_381 = {1{`RANDOM}};
- dirty_125 = _RAND_381[0:0];
- _RAND_382 = {1{`RANDOM}};
- dirty_126 = _RAND_382[0:0];
- _RAND_383 = {1{`RANDOM}};
- dirty_127 = _RAND_383[0:0];
- _RAND_384 = {1{`RANDOM}};
- dirty_128 = _RAND_384[0:0];
- _RAND_385 = {1{`RANDOM}};
- dirty_129 = _RAND_385[0:0];
- _RAND_386 = {1{`RANDOM}};
- dirty_130 = _RAND_386[0:0];
- _RAND_387 = {1{`RANDOM}};
- dirty_131 = _RAND_387[0:0];
- _RAND_388 = {1{`RANDOM}};
- dirty_132 = _RAND_388[0:0];
- _RAND_389 = {1{`RANDOM}};
- dirty_133 = _RAND_389[0:0];
- _RAND_390 = {1{`RANDOM}};
- dirty_134 = _RAND_390[0:0];
- _RAND_391 = {1{`RANDOM}};
- dirty_135 = _RAND_391[0:0];
- _RAND_392 = {1{`RANDOM}};
- dirty_136 = _RAND_392[0:0];
- _RAND_393 = {1{`RANDOM}};
- dirty_137 = _RAND_393[0:0];
- _RAND_394 = {1{`RANDOM}};
- dirty_138 = _RAND_394[0:0];
- _RAND_395 = {1{`RANDOM}};
- dirty_139 = _RAND_395[0:0];
- _RAND_396 = {1{`RANDOM}};
- dirty_140 = _RAND_396[0:0];
- _RAND_397 = {1{`RANDOM}};
- dirty_141 = _RAND_397[0:0];
- _RAND_398 = {1{`RANDOM}};
- dirty_142 = _RAND_398[0:0];
- _RAND_399 = {1{`RANDOM}};
- dirty_143 = _RAND_399[0:0];
- _RAND_400 = {1{`RANDOM}};
- dirty_144 = _RAND_400[0:0];
- _RAND_401 = {1{`RANDOM}};
- dirty_145 = _RAND_401[0:0];
- _RAND_402 = {1{`RANDOM}};
- dirty_146 = _RAND_402[0:0];
- _RAND_403 = {1{`RANDOM}};
- dirty_147 = _RAND_403[0:0];
- _RAND_404 = {1{`RANDOM}};
- dirty_148 = _RAND_404[0:0];
- _RAND_405 = {1{`RANDOM}};
- dirty_149 = _RAND_405[0:0];
- _RAND_406 = {1{`RANDOM}};
- dirty_150 = _RAND_406[0:0];
- _RAND_407 = {1{`RANDOM}};
- dirty_151 = _RAND_407[0:0];
- _RAND_408 = {1{`RANDOM}};
- dirty_152 = _RAND_408[0:0];
- _RAND_409 = {1{`RANDOM}};
- dirty_153 = _RAND_409[0:0];
- _RAND_410 = {1{`RANDOM}};
- dirty_154 = _RAND_410[0:0];
- _RAND_411 = {1{`RANDOM}};
- dirty_155 = _RAND_411[0:0];
- _RAND_412 = {1{`RANDOM}};
- dirty_156 = _RAND_412[0:0];
- _RAND_413 = {1{`RANDOM}};
- dirty_157 = _RAND_413[0:0];
- _RAND_414 = {1{`RANDOM}};
- dirty_158 = _RAND_414[0:0];
- _RAND_415 = {1{`RANDOM}};
- dirty_159 = _RAND_415[0:0];
- _RAND_416 = {1{`RANDOM}};
- dirty_160 = _RAND_416[0:0];
- _RAND_417 = {1{`RANDOM}};
- dirty_161 = _RAND_417[0:0];
- _RAND_418 = {1{`RANDOM}};
- dirty_162 = _RAND_418[0:0];
- _RAND_419 = {1{`RANDOM}};
- dirty_163 = _RAND_419[0:0];
- _RAND_420 = {1{`RANDOM}};
- dirty_164 = _RAND_420[0:0];
- _RAND_421 = {1{`RANDOM}};
- dirty_165 = _RAND_421[0:0];
- _RAND_422 = {1{`RANDOM}};
- dirty_166 = _RAND_422[0:0];
- _RAND_423 = {1{`RANDOM}};
- dirty_167 = _RAND_423[0:0];
- _RAND_424 = {1{`RANDOM}};
- dirty_168 = _RAND_424[0:0];
- _RAND_425 = {1{`RANDOM}};
- dirty_169 = _RAND_425[0:0];
- _RAND_426 = {1{`RANDOM}};
- dirty_170 = _RAND_426[0:0];
- _RAND_427 = {1{`RANDOM}};
- dirty_171 = _RAND_427[0:0];
- _RAND_428 = {1{`RANDOM}};
- dirty_172 = _RAND_428[0:0];
- _RAND_429 = {1{`RANDOM}};
- dirty_173 = _RAND_429[0:0];
- _RAND_430 = {1{`RANDOM}};
- dirty_174 = _RAND_430[0:0];
- _RAND_431 = {1{`RANDOM}};
- dirty_175 = _RAND_431[0:0];
- _RAND_432 = {1{`RANDOM}};
- dirty_176 = _RAND_432[0:0];
- _RAND_433 = {1{`RANDOM}};
- dirty_177 = _RAND_433[0:0];
- _RAND_434 = {1{`RANDOM}};
- dirty_178 = _RAND_434[0:0];
- _RAND_435 = {1{`RANDOM}};
- dirty_179 = _RAND_435[0:0];
- _RAND_436 = {1{`RANDOM}};
- dirty_180 = _RAND_436[0:0];
- _RAND_437 = {1{`RANDOM}};
- dirty_181 = _RAND_437[0:0];
- _RAND_438 = {1{`RANDOM}};
- dirty_182 = _RAND_438[0:0];
- _RAND_439 = {1{`RANDOM}};
- dirty_183 = _RAND_439[0:0];
- _RAND_440 = {1{`RANDOM}};
- dirty_184 = _RAND_440[0:0];
- _RAND_441 = {1{`RANDOM}};
- dirty_185 = _RAND_441[0:0];
- _RAND_442 = {1{`RANDOM}};
- dirty_186 = _RAND_442[0:0];
- _RAND_443 = {1{`RANDOM}};
- dirty_187 = _RAND_443[0:0];
- _RAND_444 = {1{`RANDOM}};
- dirty_188 = _RAND_444[0:0];
- _RAND_445 = {1{`RANDOM}};
- dirty_189 = _RAND_445[0:0];
- _RAND_446 = {1{`RANDOM}};
- dirty_190 = _RAND_446[0:0];
- _RAND_447 = {1{`RANDOM}};
- dirty_191 = _RAND_447[0:0];
- _RAND_448 = {1{`RANDOM}};
- dirty_192 = _RAND_448[0:0];
- _RAND_449 = {1{`RANDOM}};
- dirty_193 = _RAND_449[0:0];
- _RAND_450 = {1{`RANDOM}};
- dirty_194 = _RAND_450[0:0];
- _RAND_451 = {1{`RANDOM}};
- dirty_195 = _RAND_451[0:0];
- _RAND_452 = {1{`RANDOM}};
- dirty_196 = _RAND_452[0:0];
- _RAND_453 = {1{`RANDOM}};
- dirty_197 = _RAND_453[0:0];
- _RAND_454 = {1{`RANDOM}};
- dirty_198 = _RAND_454[0:0];
- _RAND_455 = {1{`RANDOM}};
- dirty_199 = _RAND_455[0:0];
- _RAND_456 = {1{`RANDOM}};
- dirty_200 = _RAND_456[0:0];
- _RAND_457 = {1{`RANDOM}};
- dirty_201 = _RAND_457[0:0];
- _RAND_458 = {1{`RANDOM}};
- dirty_202 = _RAND_458[0:0];
- _RAND_459 = {1{`RANDOM}};
- dirty_203 = _RAND_459[0:0];
- _RAND_460 = {1{`RANDOM}};
- dirty_204 = _RAND_460[0:0];
- _RAND_461 = {1{`RANDOM}};
- dirty_205 = _RAND_461[0:0];
- _RAND_462 = {1{`RANDOM}};
- dirty_206 = _RAND_462[0:0];
- _RAND_463 = {1{`RANDOM}};
- dirty_207 = _RAND_463[0:0];
- _RAND_464 = {1{`RANDOM}};
- dirty_208 = _RAND_464[0:0];
- _RAND_465 = {1{`RANDOM}};
- dirty_209 = _RAND_465[0:0];
- _RAND_466 = {1{`RANDOM}};
- dirty_210 = _RAND_466[0:0];
- _RAND_467 = {1{`RANDOM}};
- dirty_211 = _RAND_467[0:0];
- _RAND_468 = {1{`RANDOM}};
- dirty_212 = _RAND_468[0:0];
- _RAND_469 = {1{`RANDOM}};
- dirty_213 = _RAND_469[0:0];
- _RAND_470 = {1{`RANDOM}};
- dirty_214 = _RAND_470[0:0];
- _RAND_471 = {1{`RANDOM}};
- dirty_215 = _RAND_471[0:0];
- _RAND_472 = {1{`RANDOM}};
- dirty_216 = _RAND_472[0:0];
- _RAND_473 = {1{`RANDOM}};
- dirty_217 = _RAND_473[0:0];
- _RAND_474 = {1{`RANDOM}};
- dirty_218 = _RAND_474[0:0];
- _RAND_475 = {1{`RANDOM}};
- dirty_219 = _RAND_475[0:0];
- _RAND_476 = {1{`RANDOM}};
- dirty_220 = _RAND_476[0:0];
- _RAND_477 = {1{`RANDOM}};
- dirty_221 = _RAND_477[0:0];
- _RAND_478 = {1{`RANDOM}};
- dirty_222 = _RAND_478[0:0];
- _RAND_479 = {1{`RANDOM}};
- dirty_223 = _RAND_479[0:0];
- _RAND_480 = {1{`RANDOM}};
- dirty_224 = _RAND_480[0:0];
- _RAND_481 = {1{`RANDOM}};
- dirty_225 = _RAND_481[0:0];
- _RAND_482 = {1{`RANDOM}};
- dirty_226 = _RAND_482[0:0];
- _RAND_483 = {1{`RANDOM}};
- dirty_227 = _RAND_483[0:0];
- _RAND_484 = {1{`RANDOM}};
- dirty_228 = _RAND_484[0:0];
- _RAND_485 = {1{`RANDOM}};
- dirty_229 = _RAND_485[0:0];
- _RAND_486 = {1{`RANDOM}};
- dirty_230 = _RAND_486[0:0];
- _RAND_487 = {1{`RANDOM}};
- dirty_231 = _RAND_487[0:0];
- _RAND_488 = {1{`RANDOM}};
- dirty_232 = _RAND_488[0:0];
- _RAND_489 = {1{`RANDOM}};
- dirty_233 = _RAND_489[0:0];
- _RAND_490 = {1{`RANDOM}};
- dirty_234 = _RAND_490[0:0];
- _RAND_491 = {1{`RANDOM}};
- dirty_235 = _RAND_491[0:0];
- _RAND_492 = {1{`RANDOM}};
- dirty_236 = _RAND_492[0:0];
- _RAND_493 = {1{`RANDOM}};
- dirty_237 = _RAND_493[0:0];
- _RAND_494 = {1{`RANDOM}};
- dirty_238 = _RAND_494[0:0];
- _RAND_495 = {1{`RANDOM}};
- dirty_239 = _RAND_495[0:0];
- _RAND_496 = {1{`RANDOM}};
- dirty_240 = _RAND_496[0:0];
- _RAND_497 = {1{`RANDOM}};
- dirty_241 = _RAND_497[0:0];
- _RAND_498 = {1{`RANDOM}};
- dirty_242 = _RAND_498[0:0];
- _RAND_499 = {1{`RANDOM}};
- dirty_243 = _RAND_499[0:0];
- _RAND_500 = {1{`RANDOM}};
- dirty_244 = _RAND_500[0:0];
- _RAND_501 = {1{`RANDOM}};
- dirty_245 = _RAND_501[0:0];
- _RAND_502 = {1{`RANDOM}};
- dirty_246 = _RAND_502[0:0];
- _RAND_503 = {1{`RANDOM}};
- dirty_247 = _RAND_503[0:0];
- _RAND_504 = {1{`RANDOM}};
- dirty_248 = _RAND_504[0:0];
- _RAND_505 = {1{`RANDOM}};
- dirty_249 = _RAND_505[0:0];
- _RAND_506 = {1{`RANDOM}};
- dirty_250 = _RAND_506[0:0];
- _RAND_507 = {1{`RANDOM}};
- dirty_251 = _RAND_507[0:0];
- _RAND_508 = {1{`RANDOM}};
- dirty_252 = _RAND_508[0:0];
- _RAND_509 = {1{`RANDOM}};
- dirty_253 = _RAND_509[0:0];
- _RAND_510 = {1{`RANDOM}};
- dirty_254 = _RAND_510[0:0];
- _RAND_511 = {1{`RANDOM}};
- dirty_255 = _RAND_511[0:0];
- _RAND_512 = {1{`RANDOM}};
- camaddr_0 = _RAND_512[31:0];
- _RAND_513 = {1{`RANDOM}};
- camaddr_1 = _RAND_513[31:0];
- _RAND_514 = {1{`RANDOM}};
- camaddr_2 = _RAND_514[31:0];
- _RAND_515 = {1{`RANDOM}};
- camaddr_3 = _RAND_515[31:0];
- _RAND_516 = {1{`RANDOM}};
- camaddr_4 = _RAND_516[31:0];
- _RAND_517 = {1{`RANDOM}};
- camaddr_5 = _RAND_517[31:0];
- _RAND_518 = {1{`RANDOM}};
- camaddr_6 = _RAND_518[31:0];
- _RAND_519 = {1{`RANDOM}};
- camaddr_7 = _RAND_519[31:0];
- _RAND_520 = {1{`RANDOM}};
- camaddr_8 = _RAND_520[31:0];
- _RAND_521 = {1{`RANDOM}};
- camaddr_9 = _RAND_521[31:0];
- _RAND_522 = {1{`RANDOM}};
- camaddr_10 = _RAND_522[31:0];
- _RAND_523 = {1{`RANDOM}};
- camaddr_11 = _RAND_523[31:0];
- _RAND_524 = {1{`RANDOM}};
- camaddr_12 = _RAND_524[31:0];
- _RAND_525 = {1{`RANDOM}};
- camaddr_13 = _RAND_525[31:0];
- _RAND_526 = {1{`RANDOM}};
- camaddr_14 = _RAND_526[31:0];
- _RAND_527 = {1{`RANDOM}};
- camaddr_15 = _RAND_527[31:0];
- _RAND_528 = {1{`RANDOM}};
- camaddr_16 = _RAND_528[31:0];
- _RAND_529 = {1{`RANDOM}};
- camaddr_17 = _RAND_529[31:0];
- _RAND_530 = {1{`RANDOM}};
- camaddr_18 = _RAND_530[31:0];
- _RAND_531 = {1{`RANDOM}};
- camaddr_19 = _RAND_531[31:0];
- _RAND_532 = {1{`RANDOM}};
- camaddr_20 = _RAND_532[31:0];
- _RAND_533 = {1{`RANDOM}};
- camaddr_21 = _RAND_533[31:0];
- _RAND_534 = {1{`RANDOM}};
- camaddr_22 = _RAND_534[31:0];
- _RAND_535 = {1{`RANDOM}};
- camaddr_23 = _RAND_535[31:0];
- _RAND_536 = {1{`RANDOM}};
- camaddr_24 = _RAND_536[31:0];
- _RAND_537 = {1{`RANDOM}};
- camaddr_25 = _RAND_537[31:0];
- _RAND_538 = {1{`RANDOM}};
- camaddr_26 = _RAND_538[31:0];
- _RAND_539 = {1{`RANDOM}};
- camaddr_27 = _RAND_539[31:0];
- _RAND_540 = {1{`RANDOM}};
- camaddr_28 = _RAND_540[31:0];
- _RAND_541 = {1{`RANDOM}};
- camaddr_29 = _RAND_541[31:0];
- _RAND_542 = {1{`RANDOM}};
- camaddr_30 = _RAND_542[31:0];
- _RAND_543 = {1{`RANDOM}};
- camaddr_31 = _RAND_543[31:0];
- _RAND_544 = {1{`RANDOM}};
- camaddr_32 = _RAND_544[31:0];
- _RAND_545 = {1{`RANDOM}};
- camaddr_33 = _RAND_545[31:0];
- _RAND_546 = {1{`RANDOM}};
- camaddr_34 = _RAND_546[31:0];
- _RAND_547 = {1{`RANDOM}};
- camaddr_35 = _RAND_547[31:0];
- _RAND_548 = {1{`RANDOM}};
- camaddr_36 = _RAND_548[31:0];
- _RAND_549 = {1{`RANDOM}};
- camaddr_37 = _RAND_549[31:0];
- _RAND_550 = {1{`RANDOM}};
- camaddr_38 = _RAND_550[31:0];
- _RAND_551 = {1{`RANDOM}};
- camaddr_39 = _RAND_551[31:0];
- _RAND_552 = {1{`RANDOM}};
- camaddr_40 = _RAND_552[31:0];
- _RAND_553 = {1{`RANDOM}};
- camaddr_41 = _RAND_553[31:0];
- _RAND_554 = {1{`RANDOM}};
- camaddr_42 = _RAND_554[31:0];
- _RAND_555 = {1{`RANDOM}};
- camaddr_43 = _RAND_555[31:0];
- _RAND_556 = {1{`RANDOM}};
- camaddr_44 = _RAND_556[31:0];
- _RAND_557 = {1{`RANDOM}};
- camaddr_45 = _RAND_557[31:0];
- _RAND_558 = {1{`RANDOM}};
- camaddr_46 = _RAND_558[31:0];
- _RAND_559 = {1{`RANDOM}};
- camaddr_47 = _RAND_559[31:0];
- _RAND_560 = {1{`RANDOM}};
- camaddr_48 = _RAND_560[31:0];
- _RAND_561 = {1{`RANDOM}};
- camaddr_49 = _RAND_561[31:0];
- _RAND_562 = {1{`RANDOM}};
- camaddr_50 = _RAND_562[31:0];
- _RAND_563 = {1{`RANDOM}};
- camaddr_51 = _RAND_563[31:0];
- _RAND_564 = {1{`RANDOM}};
- camaddr_52 = _RAND_564[31:0];
- _RAND_565 = {1{`RANDOM}};
- camaddr_53 = _RAND_565[31:0];
- _RAND_566 = {1{`RANDOM}};
- camaddr_54 = _RAND_566[31:0];
- _RAND_567 = {1{`RANDOM}};
- camaddr_55 = _RAND_567[31:0];
- _RAND_568 = {1{`RANDOM}};
- camaddr_56 = _RAND_568[31:0];
- _RAND_569 = {1{`RANDOM}};
- camaddr_57 = _RAND_569[31:0];
- _RAND_570 = {1{`RANDOM}};
- camaddr_58 = _RAND_570[31:0];
- _RAND_571 = {1{`RANDOM}};
- camaddr_59 = _RAND_571[31:0];
- _RAND_572 = {1{`RANDOM}};
- camaddr_60 = _RAND_572[31:0];
- _RAND_573 = {1{`RANDOM}};
- camaddr_61 = _RAND_573[31:0];
- _RAND_574 = {1{`RANDOM}};
- camaddr_62 = _RAND_574[31:0];
- _RAND_575 = {1{`RANDOM}};
- camaddr_63 = _RAND_575[31:0];
- _RAND_576 = {1{`RANDOM}};
- camaddr_64 = _RAND_576[31:0];
- _RAND_577 = {1{`RANDOM}};
- camaddr_65 = _RAND_577[31:0];
- _RAND_578 = {1{`RANDOM}};
- camaddr_66 = _RAND_578[31:0];
- _RAND_579 = {1{`RANDOM}};
- camaddr_67 = _RAND_579[31:0];
- _RAND_580 = {1{`RANDOM}};
- camaddr_68 = _RAND_580[31:0];
- _RAND_581 = {1{`RANDOM}};
- camaddr_69 = _RAND_581[31:0];
- _RAND_582 = {1{`RANDOM}};
- camaddr_70 = _RAND_582[31:0];
- _RAND_583 = {1{`RANDOM}};
- camaddr_71 = _RAND_583[31:0];
- _RAND_584 = {1{`RANDOM}};
- camaddr_72 = _RAND_584[31:0];
- _RAND_585 = {1{`RANDOM}};
- camaddr_73 = _RAND_585[31:0];
- _RAND_586 = {1{`RANDOM}};
- camaddr_74 = _RAND_586[31:0];
- _RAND_587 = {1{`RANDOM}};
- camaddr_75 = _RAND_587[31:0];
- _RAND_588 = {1{`RANDOM}};
- camaddr_76 = _RAND_588[31:0];
- _RAND_589 = {1{`RANDOM}};
- camaddr_77 = _RAND_589[31:0];
- _RAND_590 = {1{`RANDOM}};
- camaddr_78 = _RAND_590[31:0];
- _RAND_591 = {1{`RANDOM}};
- camaddr_79 = _RAND_591[31:0];
- _RAND_592 = {1{`RANDOM}};
- camaddr_80 = _RAND_592[31:0];
- _RAND_593 = {1{`RANDOM}};
- camaddr_81 = _RAND_593[31:0];
- _RAND_594 = {1{`RANDOM}};
- camaddr_82 = _RAND_594[31:0];
- _RAND_595 = {1{`RANDOM}};
- camaddr_83 = _RAND_595[31:0];
- _RAND_596 = {1{`RANDOM}};
- camaddr_84 = _RAND_596[31:0];
- _RAND_597 = {1{`RANDOM}};
- camaddr_85 = _RAND_597[31:0];
- _RAND_598 = {1{`RANDOM}};
- camaddr_86 = _RAND_598[31:0];
- _RAND_599 = {1{`RANDOM}};
- camaddr_87 = _RAND_599[31:0];
- _RAND_600 = {1{`RANDOM}};
- camaddr_88 = _RAND_600[31:0];
- _RAND_601 = {1{`RANDOM}};
- camaddr_89 = _RAND_601[31:0];
- _RAND_602 = {1{`RANDOM}};
- camaddr_90 = _RAND_602[31:0];
- _RAND_603 = {1{`RANDOM}};
- camaddr_91 = _RAND_603[31:0];
- _RAND_604 = {1{`RANDOM}};
- camaddr_92 = _RAND_604[31:0];
- _RAND_605 = {1{`RANDOM}};
- camaddr_93 = _RAND_605[31:0];
- _RAND_606 = {1{`RANDOM}};
- camaddr_94 = _RAND_606[31:0];
- _RAND_607 = {1{`RANDOM}};
- camaddr_95 = _RAND_607[31:0];
- _RAND_608 = {1{`RANDOM}};
- camaddr_96 = _RAND_608[31:0];
- _RAND_609 = {1{`RANDOM}};
- camaddr_97 = _RAND_609[31:0];
- _RAND_610 = {1{`RANDOM}};
- camaddr_98 = _RAND_610[31:0];
- _RAND_611 = {1{`RANDOM}};
- camaddr_99 = _RAND_611[31:0];
- _RAND_612 = {1{`RANDOM}};
- camaddr_100 = _RAND_612[31:0];
- _RAND_613 = {1{`RANDOM}};
- camaddr_101 = _RAND_613[31:0];
- _RAND_614 = {1{`RANDOM}};
- camaddr_102 = _RAND_614[31:0];
- _RAND_615 = {1{`RANDOM}};
- camaddr_103 = _RAND_615[31:0];
- _RAND_616 = {1{`RANDOM}};
- camaddr_104 = _RAND_616[31:0];
- _RAND_617 = {1{`RANDOM}};
- camaddr_105 = _RAND_617[31:0];
- _RAND_618 = {1{`RANDOM}};
- camaddr_106 = _RAND_618[31:0];
- _RAND_619 = {1{`RANDOM}};
- camaddr_107 = _RAND_619[31:0];
- _RAND_620 = {1{`RANDOM}};
- camaddr_108 = _RAND_620[31:0];
- _RAND_621 = {1{`RANDOM}};
- camaddr_109 = _RAND_621[31:0];
- _RAND_622 = {1{`RANDOM}};
- camaddr_110 = _RAND_622[31:0];
- _RAND_623 = {1{`RANDOM}};
- camaddr_111 = _RAND_623[31:0];
- _RAND_624 = {1{`RANDOM}};
- camaddr_112 = _RAND_624[31:0];
- _RAND_625 = {1{`RANDOM}};
- camaddr_113 = _RAND_625[31:0];
- _RAND_626 = {1{`RANDOM}};
- camaddr_114 = _RAND_626[31:0];
- _RAND_627 = {1{`RANDOM}};
- camaddr_115 = _RAND_627[31:0];
- _RAND_628 = {1{`RANDOM}};
- camaddr_116 = _RAND_628[31:0];
- _RAND_629 = {1{`RANDOM}};
- camaddr_117 = _RAND_629[31:0];
- _RAND_630 = {1{`RANDOM}};
- camaddr_118 = _RAND_630[31:0];
- _RAND_631 = {1{`RANDOM}};
- camaddr_119 = _RAND_631[31:0];
- _RAND_632 = {1{`RANDOM}};
- camaddr_120 = _RAND_632[31:0];
- _RAND_633 = {1{`RANDOM}};
- camaddr_121 = _RAND_633[31:0];
- _RAND_634 = {1{`RANDOM}};
- camaddr_122 = _RAND_634[31:0];
- _RAND_635 = {1{`RANDOM}};
- camaddr_123 = _RAND_635[31:0];
- _RAND_636 = {1{`RANDOM}};
- camaddr_124 = _RAND_636[31:0];
- _RAND_637 = {1{`RANDOM}};
- camaddr_125 = _RAND_637[31:0];
- _RAND_638 = {1{`RANDOM}};
- camaddr_126 = _RAND_638[31:0];
- _RAND_639 = {1{`RANDOM}};
- camaddr_127 = _RAND_639[31:0];
- _RAND_640 = {1{`RANDOM}};
- camaddr_128 = _RAND_640[31:0];
- _RAND_641 = {1{`RANDOM}};
- camaddr_129 = _RAND_641[31:0];
- _RAND_642 = {1{`RANDOM}};
- camaddr_130 = _RAND_642[31:0];
- _RAND_643 = {1{`RANDOM}};
- camaddr_131 = _RAND_643[31:0];
- _RAND_644 = {1{`RANDOM}};
- camaddr_132 = _RAND_644[31:0];
- _RAND_645 = {1{`RANDOM}};
- camaddr_133 = _RAND_645[31:0];
- _RAND_646 = {1{`RANDOM}};
- camaddr_134 = _RAND_646[31:0];
- _RAND_647 = {1{`RANDOM}};
- camaddr_135 = _RAND_647[31:0];
- _RAND_648 = {1{`RANDOM}};
- camaddr_136 = _RAND_648[31:0];
- _RAND_649 = {1{`RANDOM}};
- camaddr_137 = _RAND_649[31:0];
- _RAND_650 = {1{`RANDOM}};
- camaddr_138 = _RAND_650[31:0];
- _RAND_651 = {1{`RANDOM}};
- camaddr_139 = _RAND_651[31:0];
- _RAND_652 = {1{`RANDOM}};
- camaddr_140 = _RAND_652[31:0];
- _RAND_653 = {1{`RANDOM}};
- camaddr_141 = _RAND_653[31:0];
- _RAND_654 = {1{`RANDOM}};
- camaddr_142 = _RAND_654[31:0];
- _RAND_655 = {1{`RANDOM}};
- camaddr_143 = _RAND_655[31:0];
- _RAND_656 = {1{`RANDOM}};
- camaddr_144 = _RAND_656[31:0];
- _RAND_657 = {1{`RANDOM}};
- camaddr_145 = _RAND_657[31:0];
- _RAND_658 = {1{`RANDOM}};
- camaddr_146 = _RAND_658[31:0];
- _RAND_659 = {1{`RANDOM}};
- camaddr_147 = _RAND_659[31:0];
- _RAND_660 = {1{`RANDOM}};
- camaddr_148 = _RAND_660[31:0];
- _RAND_661 = {1{`RANDOM}};
- camaddr_149 = _RAND_661[31:0];
- _RAND_662 = {1{`RANDOM}};
- camaddr_150 = _RAND_662[31:0];
- _RAND_663 = {1{`RANDOM}};
- camaddr_151 = _RAND_663[31:0];
- _RAND_664 = {1{`RANDOM}};
- camaddr_152 = _RAND_664[31:0];
- _RAND_665 = {1{`RANDOM}};
- camaddr_153 = _RAND_665[31:0];
- _RAND_666 = {1{`RANDOM}};
- camaddr_154 = _RAND_666[31:0];
- _RAND_667 = {1{`RANDOM}};
- camaddr_155 = _RAND_667[31:0];
- _RAND_668 = {1{`RANDOM}};
- camaddr_156 = _RAND_668[31:0];
- _RAND_669 = {1{`RANDOM}};
- camaddr_157 = _RAND_669[31:0];
- _RAND_670 = {1{`RANDOM}};
- camaddr_158 = _RAND_670[31:0];
- _RAND_671 = {1{`RANDOM}};
- camaddr_159 = _RAND_671[31:0];
- _RAND_672 = {1{`RANDOM}};
- camaddr_160 = _RAND_672[31:0];
- _RAND_673 = {1{`RANDOM}};
- camaddr_161 = _RAND_673[31:0];
- _RAND_674 = {1{`RANDOM}};
- camaddr_162 = _RAND_674[31:0];
- _RAND_675 = {1{`RANDOM}};
- camaddr_163 = _RAND_675[31:0];
- _RAND_676 = {1{`RANDOM}};
- camaddr_164 = _RAND_676[31:0];
- _RAND_677 = {1{`RANDOM}};
- camaddr_165 = _RAND_677[31:0];
- _RAND_678 = {1{`RANDOM}};
- camaddr_166 = _RAND_678[31:0];
- _RAND_679 = {1{`RANDOM}};
- camaddr_167 = _RAND_679[31:0];
- _RAND_680 = {1{`RANDOM}};
- camaddr_168 = _RAND_680[31:0];
- _RAND_681 = {1{`RANDOM}};
- camaddr_169 = _RAND_681[31:0];
- _RAND_682 = {1{`RANDOM}};
- camaddr_170 = _RAND_682[31:0];
- _RAND_683 = {1{`RANDOM}};
- camaddr_171 = _RAND_683[31:0];
- _RAND_684 = {1{`RANDOM}};
- camaddr_172 = _RAND_684[31:0];
- _RAND_685 = {1{`RANDOM}};
- camaddr_173 = _RAND_685[31:0];
- _RAND_686 = {1{`RANDOM}};
- camaddr_174 = _RAND_686[31:0];
- _RAND_687 = {1{`RANDOM}};
- camaddr_175 = _RAND_687[31:0];
- _RAND_688 = {1{`RANDOM}};
- camaddr_176 = _RAND_688[31:0];
- _RAND_689 = {1{`RANDOM}};
- camaddr_177 = _RAND_689[31:0];
- _RAND_690 = {1{`RANDOM}};
- camaddr_178 = _RAND_690[31:0];
- _RAND_691 = {1{`RANDOM}};
- camaddr_179 = _RAND_691[31:0];
- _RAND_692 = {1{`RANDOM}};
- camaddr_180 = _RAND_692[31:0];
- _RAND_693 = {1{`RANDOM}};
- camaddr_181 = _RAND_693[31:0];
- _RAND_694 = {1{`RANDOM}};
- camaddr_182 = _RAND_694[31:0];
- _RAND_695 = {1{`RANDOM}};
- camaddr_183 = _RAND_695[31:0];
- _RAND_696 = {1{`RANDOM}};
- camaddr_184 = _RAND_696[31:0];
- _RAND_697 = {1{`RANDOM}};
- camaddr_185 = _RAND_697[31:0];
- _RAND_698 = {1{`RANDOM}};
- camaddr_186 = _RAND_698[31:0];
- _RAND_699 = {1{`RANDOM}};
- camaddr_187 = _RAND_699[31:0];
- _RAND_700 = {1{`RANDOM}};
- camaddr_188 = _RAND_700[31:0];
- _RAND_701 = {1{`RANDOM}};
- camaddr_189 = _RAND_701[31:0];
- _RAND_702 = {1{`RANDOM}};
- camaddr_190 = _RAND_702[31:0];
- _RAND_703 = {1{`RANDOM}};
- camaddr_191 = _RAND_703[31:0];
- _RAND_704 = {1{`RANDOM}};
- camaddr_192 = _RAND_704[31:0];
- _RAND_705 = {1{`RANDOM}};
- camaddr_193 = _RAND_705[31:0];
- _RAND_706 = {1{`RANDOM}};
- camaddr_194 = _RAND_706[31:0];
- _RAND_707 = {1{`RANDOM}};
- camaddr_195 = _RAND_707[31:0];
- _RAND_708 = {1{`RANDOM}};
- camaddr_196 = _RAND_708[31:0];
- _RAND_709 = {1{`RANDOM}};
- camaddr_197 = _RAND_709[31:0];
- _RAND_710 = {1{`RANDOM}};
- camaddr_198 = _RAND_710[31:0];
- _RAND_711 = {1{`RANDOM}};
- camaddr_199 = _RAND_711[31:0];
- _RAND_712 = {1{`RANDOM}};
- camaddr_200 = _RAND_712[31:0];
- _RAND_713 = {1{`RANDOM}};
- camaddr_201 = _RAND_713[31:0];
- _RAND_714 = {1{`RANDOM}};
- camaddr_202 = _RAND_714[31:0];
- _RAND_715 = {1{`RANDOM}};
- camaddr_203 = _RAND_715[31:0];
- _RAND_716 = {1{`RANDOM}};
- camaddr_204 = _RAND_716[31:0];
- _RAND_717 = {1{`RANDOM}};
- camaddr_205 = _RAND_717[31:0];
- _RAND_718 = {1{`RANDOM}};
- camaddr_206 = _RAND_718[31:0];
- _RAND_719 = {1{`RANDOM}};
- camaddr_207 = _RAND_719[31:0];
- _RAND_720 = {1{`RANDOM}};
- camaddr_208 = _RAND_720[31:0];
- _RAND_721 = {1{`RANDOM}};
- camaddr_209 = _RAND_721[31:0];
- _RAND_722 = {1{`RANDOM}};
- camaddr_210 = _RAND_722[31:0];
- _RAND_723 = {1{`RANDOM}};
- camaddr_211 = _RAND_723[31:0];
- _RAND_724 = {1{`RANDOM}};
- camaddr_212 = _RAND_724[31:0];
- _RAND_725 = {1{`RANDOM}};
- camaddr_213 = _RAND_725[31:0];
- _RAND_726 = {1{`RANDOM}};
- camaddr_214 = _RAND_726[31:0];
- _RAND_727 = {1{`RANDOM}};
- camaddr_215 = _RAND_727[31:0];
- _RAND_728 = {1{`RANDOM}};
- camaddr_216 = _RAND_728[31:0];
- _RAND_729 = {1{`RANDOM}};
- camaddr_217 = _RAND_729[31:0];
- _RAND_730 = {1{`RANDOM}};
- camaddr_218 = _RAND_730[31:0];
- _RAND_731 = {1{`RANDOM}};
- camaddr_219 = _RAND_731[31:0];
- _RAND_732 = {1{`RANDOM}};
- camaddr_220 = _RAND_732[31:0];
- _RAND_733 = {1{`RANDOM}};
- camaddr_221 = _RAND_733[31:0];
- _RAND_734 = {1{`RANDOM}};
- camaddr_222 = _RAND_734[31:0];
- _RAND_735 = {1{`RANDOM}};
- camaddr_223 = _RAND_735[31:0];
- _RAND_736 = {1{`RANDOM}};
- camaddr_224 = _RAND_736[31:0];
- _RAND_737 = {1{`RANDOM}};
- camaddr_225 = _RAND_737[31:0];
- _RAND_738 = {1{`RANDOM}};
- camaddr_226 = _RAND_738[31:0];
- _RAND_739 = {1{`RANDOM}};
- camaddr_227 = _RAND_739[31:0];
- _RAND_740 = {1{`RANDOM}};
- camaddr_228 = _RAND_740[31:0];
- _RAND_741 = {1{`RANDOM}};
- camaddr_229 = _RAND_741[31:0];
- _RAND_742 = {1{`RANDOM}};
- camaddr_230 = _RAND_742[31:0];
- _RAND_743 = {1{`RANDOM}};
- camaddr_231 = _RAND_743[31:0];
- _RAND_744 = {1{`RANDOM}};
- camaddr_232 = _RAND_744[31:0];
- _RAND_745 = {1{`RANDOM}};
- camaddr_233 = _RAND_745[31:0];
- _RAND_746 = {1{`RANDOM}};
- camaddr_234 = _RAND_746[31:0];
- _RAND_747 = {1{`RANDOM}};
- camaddr_235 = _RAND_747[31:0];
- _RAND_748 = {1{`RANDOM}};
- camaddr_236 = _RAND_748[31:0];
- _RAND_749 = {1{`RANDOM}};
- camaddr_237 = _RAND_749[31:0];
- _RAND_750 = {1{`RANDOM}};
- camaddr_238 = _RAND_750[31:0];
- _RAND_751 = {1{`RANDOM}};
- camaddr_239 = _RAND_751[31:0];
- _RAND_752 = {1{`RANDOM}};
- camaddr_240 = _RAND_752[31:0];
- _RAND_753 = {1{`RANDOM}};
- camaddr_241 = _RAND_753[31:0];
- _RAND_754 = {1{`RANDOM}};
- camaddr_242 = _RAND_754[31:0];
- _RAND_755 = {1{`RANDOM}};
- camaddr_243 = _RAND_755[31:0];
- _RAND_756 = {1{`RANDOM}};
- camaddr_244 = _RAND_756[31:0];
- _RAND_757 = {1{`RANDOM}};
- camaddr_245 = _RAND_757[31:0];
- _RAND_758 = {1{`RANDOM}};
- camaddr_246 = _RAND_758[31:0];
- _RAND_759 = {1{`RANDOM}};
- camaddr_247 = _RAND_759[31:0];
- _RAND_760 = {1{`RANDOM}};
- camaddr_248 = _RAND_760[31:0];
- _RAND_761 = {1{`RANDOM}};
- camaddr_249 = _RAND_761[31:0];
- _RAND_762 = {1{`RANDOM}};
- camaddr_250 = _RAND_762[31:0];
- _RAND_763 = {1{`RANDOM}};
- camaddr_251 = _RAND_763[31:0];
- _RAND_764 = {1{`RANDOM}};
- camaddr_252 = _RAND_764[31:0];
- _RAND_765 = {1{`RANDOM}};
- camaddr_253 = _RAND_765[31:0];
- _RAND_766 = {1{`RANDOM}};
- camaddr_254 = _RAND_766[31:0];
- _RAND_767 = {1{`RANDOM}};
- camaddr_255 = _RAND_767[31:0];
- _RAND_768 = {1{`RANDOM}};
- history_0_0 = _RAND_768[1:0];
- _RAND_769 = {1{`RANDOM}};
- history_0_1 = _RAND_769[1:0];
- _RAND_770 = {1{`RANDOM}};
- history_0_2 = _RAND_770[1:0];
- _RAND_771 = {1{`RANDOM}};
- history_0_3 = _RAND_771[1:0];
- _RAND_772 = {1{`RANDOM}};
- history_1_0 = _RAND_772[1:0];
- _RAND_773 = {1{`RANDOM}};
- history_1_1 = _RAND_773[1:0];
- _RAND_774 = {1{`RANDOM}};
- history_1_2 = _RAND_774[1:0];
- _RAND_775 = {1{`RANDOM}};
- history_1_3 = _RAND_775[1:0];
- _RAND_776 = {1{`RANDOM}};
- history_2_0 = _RAND_776[1:0];
- _RAND_777 = {1{`RANDOM}};
- history_2_1 = _RAND_777[1:0];
- _RAND_778 = {1{`RANDOM}};
- history_2_2 = _RAND_778[1:0];
- _RAND_779 = {1{`RANDOM}};
- history_2_3 = _RAND_779[1:0];
- _RAND_780 = {1{`RANDOM}};
- history_3_0 = _RAND_780[1:0];
- _RAND_781 = {1{`RANDOM}};
- history_3_1 = _RAND_781[1:0];
- _RAND_782 = {1{`RANDOM}};
- history_3_2 = _RAND_782[1:0];
- _RAND_783 = {1{`RANDOM}};
- history_3_3 = _RAND_783[1:0];
- _RAND_784 = {1{`RANDOM}};
- history_4_0 = _RAND_784[1:0];
- _RAND_785 = {1{`RANDOM}};
- history_4_1 = _RAND_785[1:0];
- _RAND_786 = {1{`RANDOM}};
- history_4_2 = _RAND_786[1:0];
- _RAND_787 = {1{`RANDOM}};
- history_4_3 = _RAND_787[1:0];
- _RAND_788 = {1{`RANDOM}};
- history_5_0 = _RAND_788[1:0];
- _RAND_789 = {1{`RANDOM}};
- history_5_1 = _RAND_789[1:0];
- _RAND_790 = {1{`RANDOM}};
- history_5_2 = _RAND_790[1:0];
- _RAND_791 = {1{`RANDOM}};
- history_5_3 = _RAND_791[1:0];
- _RAND_792 = {1{`RANDOM}};
- history_6_0 = _RAND_792[1:0];
- _RAND_793 = {1{`RANDOM}};
- history_6_1 = _RAND_793[1:0];
- _RAND_794 = {1{`RANDOM}};
- history_6_2 = _RAND_794[1:0];
- _RAND_795 = {1{`RANDOM}};
- history_6_3 = _RAND_795[1:0];
- _RAND_796 = {1{`RANDOM}};
- history_7_0 = _RAND_796[1:0];
- _RAND_797 = {1{`RANDOM}};
- history_7_1 = _RAND_797[1:0];
- _RAND_798 = {1{`RANDOM}};
- history_7_2 = _RAND_798[1:0];
- _RAND_799 = {1{`RANDOM}};
- history_7_3 = _RAND_799[1:0];
- _RAND_800 = {1{`RANDOM}};
- history_8_0 = _RAND_800[1:0];
- _RAND_801 = {1{`RANDOM}};
- history_8_1 = _RAND_801[1:0];
- _RAND_802 = {1{`RANDOM}};
- history_8_2 = _RAND_802[1:0];
- _RAND_803 = {1{`RANDOM}};
- history_8_3 = _RAND_803[1:0];
- _RAND_804 = {1{`RANDOM}};
- history_9_0 = _RAND_804[1:0];
- _RAND_805 = {1{`RANDOM}};
- history_9_1 = _RAND_805[1:0];
- _RAND_806 = {1{`RANDOM}};
- history_9_2 = _RAND_806[1:0];
- _RAND_807 = {1{`RANDOM}};
- history_9_3 = _RAND_807[1:0];
- _RAND_808 = {1{`RANDOM}};
- history_10_0 = _RAND_808[1:0];
- _RAND_809 = {1{`RANDOM}};
- history_10_1 = _RAND_809[1:0];
- _RAND_810 = {1{`RANDOM}};
- history_10_2 = _RAND_810[1:0];
- _RAND_811 = {1{`RANDOM}};
- history_10_3 = _RAND_811[1:0];
- _RAND_812 = {1{`RANDOM}};
- history_11_0 = _RAND_812[1:0];
- _RAND_813 = {1{`RANDOM}};
- history_11_1 = _RAND_813[1:0];
- _RAND_814 = {1{`RANDOM}};
- history_11_2 = _RAND_814[1:0];
- _RAND_815 = {1{`RANDOM}};
- history_11_3 = _RAND_815[1:0];
- _RAND_816 = {1{`RANDOM}};
- history_12_0 = _RAND_816[1:0];
- _RAND_817 = {1{`RANDOM}};
- history_12_1 = _RAND_817[1:0];
- _RAND_818 = {1{`RANDOM}};
- history_12_2 = _RAND_818[1:0];
- _RAND_819 = {1{`RANDOM}};
- history_12_3 = _RAND_819[1:0];
- _RAND_820 = {1{`RANDOM}};
- history_13_0 = _RAND_820[1:0];
- _RAND_821 = {1{`RANDOM}};
- history_13_1 = _RAND_821[1:0];
- _RAND_822 = {1{`RANDOM}};
- history_13_2 = _RAND_822[1:0];
- _RAND_823 = {1{`RANDOM}};
- history_13_3 = _RAND_823[1:0];
- _RAND_824 = {1{`RANDOM}};
- history_14_0 = _RAND_824[1:0];
- _RAND_825 = {1{`RANDOM}};
- history_14_1 = _RAND_825[1:0];
- _RAND_826 = {1{`RANDOM}};
- history_14_2 = _RAND_826[1:0];
- _RAND_827 = {1{`RANDOM}};
- history_14_3 = _RAND_827[1:0];
- _RAND_828 = {1{`RANDOM}};
- history_15_0 = _RAND_828[1:0];
- _RAND_829 = {1{`RANDOM}};
- history_15_1 = _RAND_829[1:0];
- _RAND_830 = {1{`RANDOM}};
- history_15_2 = _RAND_830[1:0];
- _RAND_831 = {1{`RANDOM}};
- history_15_3 = _RAND_831[1:0];
- _RAND_832 = {1{`RANDOM}};
- history_16_0 = _RAND_832[1:0];
- _RAND_833 = {1{`RANDOM}};
- history_16_1 = _RAND_833[1:0];
- _RAND_834 = {1{`RANDOM}};
- history_16_2 = _RAND_834[1:0];
- _RAND_835 = {1{`RANDOM}};
- history_16_3 = _RAND_835[1:0];
- _RAND_836 = {1{`RANDOM}};
- history_17_0 = _RAND_836[1:0];
- _RAND_837 = {1{`RANDOM}};
- history_17_1 = _RAND_837[1:0];
- _RAND_838 = {1{`RANDOM}};
- history_17_2 = _RAND_838[1:0];
- _RAND_839 = {1{`RANDOM}};
- history_17_3 = _RAND_839[1:0];
- _RAND_840 = {1{`RANDOM}};
- history_18_0 = _RAND_840[1:0];
- _RAND_841 = {1{`RANDOM}};
- history_18_1 = _RAND_841[1:0];
- _RAND_842 = {1{`RANDOM}};
- history_18_2 = _RAND_842[1:0];
- _RAND_843 = {1{`RANDOM}};
- history_18_3 = _RAND_843[1:0];
- _RAND_844 = {1{`RANDOM}};
- history_19_0 = _RAND_844[1:0];
- _RAND_845 = {1{`RANDOM}};
- history_19_1 = _RAND_845[1:0];
- _RAND_846 = {1{`RANDOM}};
- history_19_2 = _RAND_846[1:0];
- _RAND_847 = {1{`RANDOM}};
- history_19_3 = _RAND_847[1:0];
- _RAND_848 = {1{`RANDOM}};
- history_20_0 = _RAND_848[1:0];
- _RAND_849 = {1{`RANDOM}};
- history_20_1 = _RAND_849[1:0];
- _RAND_850 = {1{`RANDOM}};
- history_20_2 = _RAND_850[1:0];
- _RAND_851 = {1{`RANDOM}};
- history_20_3 = _RAND_851[1:0];
- _RAND_852 = {1{`RANDOM}};
- history_21_0 = _RAND_852[1:0];
- _RAND_853 = {1{`RANDOM}};
- history_21_1 = _RAND_853[1:0];
- _RAND_854 = {1{`RANDOM}};
- history_21_2 = _RAND_854[1:0];
- _RAND_855 = {1{`RANDOM}};
- history_21_3 = _RAND_855[1:0];
- _RAND_856 = {1{`RANDOM}};
- history_22_0 = _RAND_856[1:0];
- _RAND_857 = {1{`RANDOM}};
- history_22_1 = _RAND_857[1:0];
- _RAND_858 = {1{`RANDOM}};
- history_22_2 = _RAND_858[1:0];
- _RAND_859 = {1{`RANDOM}};
- history_22_3 = _RAND_859[1:0];
- _RAND_860 = {1{`RANDOM}};
- history_23_0 = _RAND_860[1:0];
- _RAND_861 = {1{`RANDOM}};
- history_23_1 = _RAND_861[1:0];
- _RAND_862 = {1{`RANDOM}};
- history_23_2 = _RAND_862[1:0];
- _RAND_863 = {1{`RANDOM}};
- history_23_3 = _RAND_863[1:0];
- _RAND_864 = {1{`RANDOM}};
- history_24_0 = _RAND_864[1:0];
- _RAND_865 = {1{`RANDOM}};
- history_24_1 = _RAND_865[1:0];
- _RAND_866 = {1{`RANDOM}};
- history_24_2 = _RAND_866[1:0];
- _RAND_867 = {1{`RANDOM}};
- history_24_3 = _RAND_867[1:0];
- _RAND_868 = {1{`RANDOM}};
- history_25_0 = _RAND_868[1:0];
- _RAND_869 = {1{`RANDOM}};
- history_25_1 = _RAND_869[1:0];
- _RAND_870 = {1{`RANDOM}};
- history_25_2 = _RAND_870[1:0];
- _RAND_871 = {1{`RANDOM}};
- history_25_3 = _RAND_871[1:0];
- _RAND_872 = {1{`RANDOM}};
- history_26_0 = _RAND_872[1:0];
- _RAND_873 = {1{`RANDOM}};
- history_26_1 = _RAND_873[1:0];
- _RAND_874 = {1{`RANDOM}};
- history_26_2 = _RAND_874[1:0];
- _RAND_875 = {1{`RANDOM}};
- history_26_3 = _RAND_875[1:0];
- _RAND_876 = {1{`RANDOM}};
- history_27_0 = _RAND_876[1:0];
- _RAND_877 = {1{`RANDOM}};
- history_27_1 = _RAND_877[1:0];
- _RAND_878 = {1{`RANDOM}};
- history_27_2 = _RAND_878[1:0];
- _RAND_879 = {1{`RANDOM}};
- history_27_3 = _RAND_879[1:0];
- _RAND_880 = {1{`RANDOM}};
- history_28_0 = _RAND_880[1:0];
- _RAND_881 = {1{`RANDOM}};
- history_28_1 = _RAND_881[1:0];
- _RAND_882 = {1{`RANDOM}};
- history_28_2 = _RAND_882[1:0];
- _RAND_883 = {1{`RANDOM}};
- history_28_3 = _RAND_883[1:0];
- _RAND_884 = {1{`RANDOM}};
- history_29_0 = _RAND_884[1:0];
- _RAND_885 = {1{`RANDOM}};
- history_29_1 = _RAND_885[1:0];
- _RAND_886 = {1{`RANDOM}};
- history_29_2 = _RAND_886[1:0];
- _RAND_887 = {1{`RANDOM}};
- history_29_3 = _RAND_887[1:0];
- _RAND_888 = {1{`RANDOM}};
- history_30_0 = _RAND_888[1:0];
- _RAND_889 = {1{`RANDOM}};
- history_30_1 = _RAND_889[1:0];
- _RAND_890 = {1{`RANDOM}};
- history_30_2 = _RAND_890[1:0];
- _RAND_891 = {1{`RANDOM}};
- history_30_3 = _RAND_891[1:0];
- _RAND_892 = {1{`RANDOM}};
- history_31_0 = _RAND_892[1:0];
- _RAND_893 = {1{`RANDOM}};
- history_31_1 = _RAND_893[1:0];
- _RAND_894 = {1{`RANDOM}};
- history_31_2 = _RAND_894[1:0];
- _RAND_895 = {1{`RANDOM}};
- history_31_3 = _RAND_895[1:0];
- _RAND_896 = {1{`RANDOM}};
- history_32_0 = _RAND_896[1:0];
- _RAND_897 = {1{`RANDOM}};
- history_32_1 = _RAND_897[1:0];
- _RAND_898 = {1{`RANDOM}};
- history_32_2 = _RAND_898[1:0];
- _RAND_899 = {1{`RANDOM}};
- history_32_3 = _RAND_899[1:0];
- _RAND_900 = {1{`RANDOM}};
- history_33_0 = _RAND_900[1:0];
- _RAND_901 = {1{`RANDOM}};
- history_33_1 = _RAND_901[1:0];
- _RAND_902 = {1{`RANDOM}};
- history_33_2 = _RAND_902[1:0];
- _RAND_903 = {1{`RANDOM}};
- history_33_3 = _RAND_903[1:0];
- _RAND_904 = {1{`RANDOM}};
- history_34_0 = _RAND_904[1:0];
- _RAND_905 = {1{`RANDOM}};
- history_34_1 = _RAND_905[1:0];
- _RAND_906 = {1{`RANDOM}};
- history_34_2 = _RAND_906[1:0];
- _RAND_907 = {1{`RANDOM}};
- history_34_3 = _RAND_907[1:0];
- _RAND_908 = {1{`RANDOM}};
- history_35_0 = _RAND_908[1:0];
- _RAND_909 = {1{`RANDOM}};
- history_35_1 = _RAND_909[1:0];
- _RAND_910 = {1{`RANDOM}};
- history_35_2 = _RAND_910[1:0];
- _RAND_911 = {1{`RANDOM}};
- history_35_3 = _RAND_911[1:0];
- _RAND_912 = {1{`RANDOM}};
- history_36_0 = _RAND_912[1:0];
- _RAND_913 = {1{`RANDOM}};
- history_36_1 = _RAND_913[1:0];
- _RAND_914 = {1{`RANDOM}};
- history_36_2 = _RAND_914[1:0];
- _RAND_915 = {1{`RANDOM}};
- history_36_3 = _RAND_915[1:0];
- _RAND_916 = {1{`RANDOM}};
- history_37_0 = _RAND_916[1:0];
- _RAND_917 = {1{`RANDOM}};
- history_37_1 = _RAND_917[1:0];
- _RAND_918 = {1{`RANDOM}};
- history_37_2 = _RAND_918[1:0];
- _RAND_919 = {1{`RANDOM}};
- history_37_3 = _RAND_919[1:0];
- _RAND_920 = {1{`RANDOM}};
- history_38_0 = _RAND_920[1:0];
- _RAND_921 = {1{`RANDOM}};
- history_38_1 = _RAND_921[1:0];
- _RAND_922 = {1{`RANDOM}};
- history_38_2 = _RAND_922[1:0];
- _RAND_923 = {1{`RANDOM}};
- history_38_3 = _RAND_923[1:0];
- _RAND_924 = {1{`RANDOM}};
- history_39_0 = _RAND_924[1:0];
- _RAND_925 = {1{`RANDOM}};
- history_39_1 = _RAND_925[1:0];
- _RAND_926 = {1{`RANDOM}};
- history_39_2 = _RAND_926[1:0];
- _RAND_927 = {1{`RANDOM}};
- history_39_3 = _RAND_927[1:0];
- _RAND_928 = {1{`RANDOM}};
- history_40_0 = _RAND_928[1:0];
- _RAND_929 = {1{`RANDOM}};
- history_40_1 = _RAND_929[1:0];
- _RAND_930 = {1{`RANDOM}};
- history_40_2 = _RAND_930[1:0];
- _RAND_931 = {1{`RANDOM}};
- history_40_3 = _RAND_931[1:0];
- _RAND_932 = {1{`RANDOM}};
- history_41_0 = _RAND_932[1:0];
- _RAND_933 = {1{`RANDOM}};
- history_41_1 = _RAND_933[1:0];
- _RAND_934 = {1{`RANDOM}};
- history_41_2 = _RAND_934[1:0];
- _RAND_935 = {1{`RANDOM}};
- history_41_3 = _RAND_935[1:0];
- _RAND_936 = {1{`RANDOM}};
- history_42_0 = _RAND_936[1:0];
- _RAND_937 = {1{`RANDOM}};
- history_42_1 = _RAND_937[1:0];
- _RAND_938 = {1{`RANDOM}};
- history_42_2 = _RAND_938[1:0];
- _RAND_939 = {1{`RANDOM}};
- history_42_3 = _RAND_939[1:0];
- _RAND_940 = {1{`RANDOM}};
- history_43_0 = _RAND_940[1:0];
- _RAND_941 = {1{`RANDOM}};
- history_43_1 = _RAND_941[1:0];
- _RAND_942 = {1{`RANDOM}};
- history_43_2 = _RAND_942[1:0];
- _RAND_943 = {1{`RANDOM}};
- history_43_3 = _RAND_943[1:0];
- _RAND_944 = {1{`RANDOM}};
- history_44_0 = _RAND_944[1:0];
- _RAND_945 = {1{`RANDOM}};
- history_44_1 = _RAND_945[1:0];
- _RAND_946 = {1{`RANDOM}};
- history_44_2 = _RAND_946[1:0];
- _RAND_947 = {1{`RANDOM}};
- history_44_3 = _RAND_947[1:0];
- _RAND_948 = {1{`RANDOM}};
- history_45_0 = _RAND_948[1:0];
- _RAND_949 = {1{`RANDOM}};
- history_45_1 = _RAND_949[1:0];
- _RAND_950 = {1{`RANDOM}};
- history_45_2 = _RAND_950[1:0];
- _RAND_951 = {1{`RANDOM}};
- history_45_3 = _RAND_951[1:0];
- _RAND_952 = {1{`RANDOM}};
- history_46_0 = _RAND_952[1:0];
- _RAND_953 = {1{`RANDOM}};
- history_46_1 = _RAND_953[1:0];
- _RAND_954 = {1{`RANDOM}};
- history_46_2 = _RAND_954[1:0];
- _RAND_955 = {1{`RANDOM}};
- history_46_3 = _RAND_955[1:0];
- _RAND_956 = {1{`RANDOM}};
- history_47_0 = _RAND_956[1:0];
- _RAND_957 = {1{`RANDOM}};
- history_47_1 = _RAND_957[1:0];
- _RAND_958 = {1{`RANDOM}};
- history_47_2 = _RAND_958[1:0];
- _RAND_959 = {1{`RANDOM}};
- history_47_3 = _RAND_959[1:0];
- _RAND_960 = {1{`RANDOM}};
- history_48_0 = _RAND_960[1:0];
- _RAND_961 = {1{`RANDOM}};
- history_48_1 = _RAND_961[1:0];
- _RAND_962 = {1{`RANDOM}};
- history_48_2 = _RAND_962[1:0];
- _RAND_963 = {1{`RANDOM}};
- history_48_3 = _RAND_963[1:0];
- _RAND_964 = {1{`RANDOM}};
- history_49_0 = _RAND_964[1:0];
- _RAND_965 = {1{`RANDOM}};
- history_49_1 = _RAND_965[1:0];
- _RAND_966 = {1{`RANDOM}};
- history_49_2 = _RAND_966[1:0];
- _RAND_967 = {1{`RANDOM}};
- history_49_3 = _RAND_967[1:0];
- _RAND_968 = {1{`RANDOM}};
- history_50_0 = _RAND_968[1:0];
- _RAND_969 = {1{`RANDOM}};
- history_50_1 = _RAND_969[1:0];
- _RAND_970 = {1{`RANDOM}};
- history_50_2 = _RAND_970[1:0];
- _RAND_971 = {1{`RANDOM}};
- history_50_3 = _RAND_971[1:0];
- _RAND_972 = {1{`RANDOM}};
- history_51_0 = _RAND_972[1:0];
- _RAND_973 = {1{`RANDOM}};
- history_51_1 = _RAND_973[1:0];
- _RAND_974 = {1{`RANDOM}};
- history_51_2 = _RAND_974[1:0];
- _RAND_975 = {1{`RANDOM}};
- history_51_3 = _RAND_975[1:0];
- _RAND_976 = {1{`RANDOM}};
- history_52_0 = _RAND_976[1:0];
- _RAND_977 = {1{`RANDOM}};
- history_52_1 = _RAND_977[1:0];
- _RAND_978 = {1{`RANDOM}};
- history_52_2 = _RAND_978[1:0];
- _RAND_979 = {1{`RANDOM}};
- history_52_3 = _RAND_979[1:0];
- _RAND_980 = {1{`RANDOM}};
- history_53_0 = _RAND_980[1:0];
- _RAND_981 = {1{`RANDOM}};
- history_53_1 = _RAND_981[1:0];
- _RAND_982 = {1{`RANDOM}};
- history_53_2 = _RAND_982[1:0];
- _RAND_983 = {1{`RANDOM}};
- history_53_3 = _RAND_983[1:0];
- _RAND_984 = {1{`RANDOM}};
- history_54_0 = _RAND_984[1:0];
- _RAND_985 = {1{`RANDOM}};
- history_54_1 = _RAND_985[1:0];
- _RAND_986 = {1{`RANDOM}};
- history_54_2 = _RAND_986[1:0];
- _RAND_987 = {1{`RANDOM}};
- history_54_3 = _RAND_987[1:0];
- _RAND_988 = {1{`RANDOM}};
- history_55_0 = _RAND_988[1:0];
- _RAND_989 = {1{`RANDOM}};
- history_55_1 = _RAND_989[1:0];
- _RAND_990 = {1{`RANDOM}};
- history_55_2 = _RAND_990[1:0];
- _RAND_991 = {1{`RANDOM}};
- history_55_3 = _RAND_991[1:0];
- _RAND_992 = {1{`RANDOM}};
- history_56_0 = _RAND_992[1:0];
- _RAND_993 = {1{`RANDOM}};
- history_56_1 = _RAND_993[1:0];
- _RAND_994 = {1{`RANDOM}};
- history_56_2 = _RAND_994[1:0];
- _RAND_995 = {1{`RANDOM}};
- history_56_3 = _RAND_995[1:0];
- _RAND_996 = {1{`RANDOM}};
- history_57_0 = _RAND_996[1:0];
- _RAND_997 = {1{`RANDOM}};
- history_57_1 = _RAND_997[1:0];
- _RAND_998 = {1{`RANDOM}};
- history_57_2 = _RAND_998[1:0];
- _RAND_999 = {1{`RANDOM}};
- history_57_3 = _RAND_999[1:0];
- _RAND_1000 = {1{`RANDOM}};
- history_58_0 = _RAND_1000[1:0];
- _RAND_1001 = {1{`RANDOM}};
- history_58_1 = _RAND_1001[1:0];
- _RAND_1002 = {1{`RANDOM}};
- history_58_2 = _RAND_1002[1:0];
- _RAND_1003 = {1{`RANDOM}};
- history_58_3 = _RAND_1003[1:0];
- _RAND_1004 = {1{`RANDOM}};
- history_59_0 = _RAND_1004[1:0];
- _RAND_1005 = {1{`RANDOM}};
- history_59_1 = _RAND_1005[1:0];
- _RAND_1006 = {1{`RANDOM}};
- history_59_2 = _RAND_1006[1:0];
- _RAND_1007 = {1{`RANDOM}};
- history_59_3 = _RAND_1007[1:0];
- _RAND_1008 = {1{`RANDOM}};
- history_60_0 = _RAND_1008[1:0];
- _RAND_1009 = {1{`RANDOM}};
- history_60_1 = _RAND_1009[1:0];
- _RAND_1010 = {1{`RANDOM}};
- history_60_2 = _RAND_1010[1:0];
- _RAND_1011 = {1{`RANDOM}};
- history_60_3 = _RAND_1011[1:0];
- _RAND_1012 = {1{`RANDOM}};
- history_61_0 = _RAND_1012[1:0];
- _RAND_1013 = {1{`RANDOM}};
- history_61_1 = _RAND_1013[1:0];
- _RAND_1014 = {1{`RANDOM}};
- history_61_2 = _RAND_1014[1:0];
- _RAND_1015 = {1{`RANDOM}};
- history_61_3 = _RAND_1015[1:0];
- _RAND_1016 = {1{`RANDOM}};
- history_62_0 = _RAND_1016[1:0];
- _RAND_1017 = {1{`RANDOM}};
- history_62_1 = _RAND_1017[1:0];
- _RAND_1018 = {1{`RANDOM}};
- history_62_2 = _RAND_1018[1:0];
- _RAND_1019 = {1{`RANDOM}};
- history_62_3 = _RAND_1019[1:0];
- _RAND_1020 = {1{`RANDOM}};
- history_63_0 = _RAND_1020[1:0];
- _RAND_1021 = {1{`RANDOM}};
- history_63_1 = _RAND_1021[1:0];
- _RAND_1022 = {1{`RANDOM}};
- history_63_2 = _RAND_1022[1:0];
- _RAND_1023 = {1{`RANDOM}};
- history_63_3 = _RAND_1023[1:0];
- _RAND_1024 = {1{`RANDOM}};
- fstate = _RAND_1024[2:0];
- _RAND_1025 = {1{`RANDOM}};
- flush_0 = _RAND_1025[0:0];
- _RAND_1026 = {1{`RANDOM}};
- flush_1 = _RAND_1026[0:0];
- _RAND_1027 = {1{`RANDOM}};
- flush_2 = _RAND_1027[0:0];
- _RAND_1028 = {1{`RANDOM}};
- flush_3 = _RAND_1028[0:0];
- _RAND_1029 = {1{`RANDOM}};
- flush_4 = _RAND_1029[0:0];
- _RAND_1030 = {1{`RANDOM}};
- flush_5 = _RAND_1030[0:0];
- _RAND_1031 = {1{`RANDOM}};
- flush_6 = _RAND_1031[0:0];
- _RAND_1032 = {1{`RANDOM}};
- flush_7 = _RAND_1032[0:0];
- _RAND_1033 = {1{`RANDOM}};
- flush_8 = _RAND_1033[0:0];
- _RAND_1034 = {1{`RANDOM}};
- flush_9 = _RAND_1034[0:0];
- _RAND_1035 = {1{`RANDOM}};
- flush_10 = _RAND_1035[0:0];
- _RAND_1036 = {1{`RANDOM}};
- flush_11 = _RAND_1036[0:0];
- _RAND_1037 = {1{`RANDOM}};
- flush_12 = _RAND_1037[0:0];
- _RAND_1038 = {1{`RANDOM}};
- flush_13 = _RAND_1038[0:0];
- _RAND_1039 = {1{`RANDOM}};
- flush_14 = _RAND_1039[0:0];
- _RAND_1040 = {1{`RANDOM}};
- flush_15 = _RAND_1040[0:0];
- _RAND_1041 = {1{`RANDOM}};
- flush_16 = _RAND_1041[0:0];
- _RAND_1042 = {1{`RANDOM}};
- flush_17 = _RAND_1042[0:0];
- _RAND_1043 = {1{`RANDOM}};
- flush_18 = _RAND_1043[0:0];
- _RAND_1044 = {1{`RANDOM}};
- flush_19 = _RAND_1044[0:0];
- _RAND_1045 = {1{`RANDOM}};
- flush_20 = _RAND_1045[0:0];
- _RAND_1046 = {1{`RANDOM}};
- flush_21 = _RAND_1046[0:0];
- _RAND_1047 = {1{`RANDOM}};
- flush_22 = _RAND_1047[0:0];
- _RAND_1048 = {1{`RANDOM}};
- flush_23 = _RAND_1048[0:0];
- _RAND_1049 = {1{`RANDOM}};
- flush_24 = _RAND_1049[0:0];
- _RAND_1050 = {1{`RANDOM}};
- flush_25 = _RAND_1050[0:0];
- _RAND_1051 = {1{`RANDOM}};
- flush_26 = _RAND_1051[0:0];
- _RAND_1052 = {1{`RANDOM}};
- flush_27 = _RAND_1052[0:0];
- _RAND_1053 = {1{`RANDOM}};
- flush_28 = _RAND_1053[0:0];
- _RAND_1054 = {1{`RANDOM}};
- flush_29 = _RAND_1054[0:0];
- _RAND_1055 = {1{`RANDOM}};
- flush_30 = _RAND_1055[0:0];
- _RAND_1056 = {1{`RANDOM}};
- flush_31 = _RAND_1056[0:0];
- _RAND_1057 = {1{`RANDOM}};
- flush_32 = _RAND_1057[0:0];
- _RAND_1058 = {1{`RANDOM}};
- flush_33 = _RAND_1058[0:0];
- _RAND_1059 = {1{`RANDOM}};
- flush_34 = _RAND_1059[0:0];
- _RAND_1060 = {1{`RANDOM}};
- flush_35 = _RAND_1060[0:0];
- _RAND_1061 = {1{`RANDOM}};
- flush_36 = _RAND_1061[0:0];
- _RAND_1062 = {1{`RANDOM}};
- flush_37 = _RAND_1062[0:0];
- _RAND_1063 = {1{`RANDOM}};
- flush_38 = _RAND_1063[0:0];
- _RAND_1064 = {1{`RANDOM}};
- flush_39 = _RAND_1064[0:0];
- _RAND_1065 = {1{`RANDOM}};
- flush_40 = _RAND_1065[0:0];
- _RAND_1066 = {1{`RANDOM}};
- flush_41 = _RAND_1066[0:0];
- _RAND_1067 = {1{`RANDOM}};
- flush_42 = _RAND_1067[0:0];
- _RAND_1068 = {1{`RANDOM}};
- flush_43 = _RAND_1068[0:0];
- _RAND_1069 = {1{`RANDOM}};
- flush_44 = _RAND_1069[0:0];
- _RAND_1070 = {1{`RANDOM}};
- flush_45 = _RAND_1070[0:0];
- _RAND_1071 = {1{`RANDOM}};
- flush_46 = _RAND_1071[0:0];
- _RAND_1072 = {1{`RANDOM}};
- flush_47 = _RAND_1072[0:0];
- _RAND_1073 = {1{`RANDOM}};
- flush_48 = _RAND_1073[0:0];
- _RAND_1074 = {1{`RANDOM}};
- flush_49 = _RAND_1074[0:0];
- _RAND_1075 = {1{`RANDOM}};
- flush_50 = _RAND_1075[0:0];
- _RAND_1076 = {1{`RANDOM}};
- flush_51 = _RAND_1076[0:0];
- _RAND_1077 = {1{`RANDOM}};
- flush_52 = _RAND_1077[0:0];
- _RAND_1078 = {1{`RANDOM}};
- flush_53 = _RAND_1078[0:0];
- _RAND_1079 = {1{`RANDOM}};
- flush_54 = _RAND_1079[0:0];
- _RAND_1080 = {1{`RANDOM}};
- flush_55 = _RAND_1080[0:0];
- _RAND_1081 = {1{`RANDOM}};
- flush_56 = _RAND_1081[0:0];
- _RAND_1082 = {1{`RANDOM}};
- flush_57 = _RAND_1082[0:0];
- _RAND_1083 = {1{`RANDOM}};
- flush_58 = _RAND_1083[0:0];
- _RAND_1084 = {1{`RANDOM}};
- flush_59 = _RAND_1084[0:0];
- _RAND_1085 = {1{`RANDOM}};
- flush_60 = _RAND_1085[0:0];
- _RAND_1086 = {1{`RANDOM}};
- flush_61 = _RAND_1086[0:0];
- _RAND_1087 = {1{`RANDOM}};
- flush_62 = _RAND_1087[0:0];
- _RAND_1088 = {1{`RANDOM}};
- flush_63 = _RAND_1088[0:0];
- _RAND_1089 = {1{`RANDOM}};
- flush_64 = _RAND_1089[0:0];
- _RAND_1090 = {1{`RANDOM}};
- flush_65 = _RAND_1090[0:0];
- _RAND_1091 = {1{`RANDOM}};
- flush_66 = _RAND_1091[0:0];
- _RAND_1092 = {1{`RANDOM}};
- flush_67 = _RAND_1092[0:0];
- _RAND_1093 = {1{`RANDOM}};
- flush_68 = _RAND_1093[0:0];
- _RAND_1094 = {1{`RANDOM}};
- flush_69 = _RAND_1094[0:0];
- _RAND_1095 = {1{`RANDOM}};
- flush_70 = _RAND_1095[0:0];
- _RAND_1096 = {1{`RANDOM}};
- flush_71 = _RAND_1096[0:0];
- _RAND_1097 = {1{`RANDOM}};
- flush_72 = _RAND_1097[0:0];
- _RAND_1098 = {1{`RANDOM}};
- flush_73 = _RAND_1098[0:0];
- _RAND_1099 = {1{`RANDOM}};
- flush_74 = _RAND_1099[0:0];
- _RAND_1100 = {1{`RANDOM}};
- flush_75 = _RAND_1100[0:0];
- _RAND_1101 = {1{`RANDOM}};
- flush_76 = _RAND_1101[0:0];
- _RAND_1102 = {1{`RANDOM}};
- flush_77 = _RAND_1102[0:0];
- _RAND_1103 = {1{`RANDOM}};
- flush_78 = _RAND_1103[0:0];
- _RAND_1104 = {1{`RANDOM}};
- flush_79 = _RAND_1104[0:0];
- _RAND_1105 = {1{`RANDOM}};
- flush_80 = _RAND_1105[0:0];
- _RAND_1106 = {1{`RANDOM}};
- flush_81 = _RAND_1106[0:0];
- _RAND_1107 = {1{`RANDOM}};
- flush_82 = _RAND_1107[0:0];
- _RAND_1108 = {1{`RANDOM}};
- flush_83 = _RAND_1108[0:0];
- _RAND_1109 = {1{`RANDOM}};
- flush_84 = _RAND_1109[0:0];
- _RAND_1110 = {1{`RANDOM}};
- flush_85 = _RAND_1110[0:0];
- _RAND_1111 = {1{`RANDOM}};
- flush_86 = _RAND_1111[0:0];
- _RAND_1112 = {1{`RANDOM}};
- flush_87 = _RAND_1112[0:0];
- _RAND_1113 = {1{`RANDOM}};
- flush_88 = _RAND_1113[0:0];
- _RAND_1114 = {1{`RANDOM}};
- flush_89 = _RAND_1114[0:0];
- _RAND_1115 = {1{`RANDOM}};
- flush_90 = _RAND_1115[0:0];
- _RAND_1116 = {1{`RANDOM}};
- flush_91 = _RAND_1116[0:0];
- _RAND_1117 = {1{`RANDOM}};
- flush_92 = _RAND_1117[0:0];
- _RAND_1118 = {1{`RANDOM}};
- flush_93 = _RAND_1118[0:0];
- _RAND_1119 = {1{`RANDOM}};
- flush_94 = _RAND_1119[0:0];
- _RAND_1120 = {1{`RANDOM}};
- flush_95 = _RAND_1120[0:0];
- _RAND_1121 = {1{`RANDOM}};
- flush_96 = _RAND_1121[0:0];
- _RAND_1122 = {1{`RANDOM}};
- flush_97 = _RAND_1122[0:0];
- _RAND_1123 = {1{`RANDOM}};
- flush_98 = _RAND_1123[0:0];
- _RAND_1124 = {1{`RANDOM}};
- flush_99 = _RAND_1124[0:0];
- _RAND_1125 = {1{`RANDOM}};
- flush_100 = _RAND_1125[0:0];
- _RAND_1126 = {1{`RANDOM}};
- flush_101 = _RAND_1126[0:0];
- _RAND_1127 = {1{`RANDOM}};
- flush_102 = _RAND_1127[0:0];
- _RAND_1128 = {1{`RANDOM}};
- flush_103 = _RAND_1128[0:0];
- _RAND_1129 = {1{`RANDOM}};
- flush_104 = _RAND_1129[0:0];
- _RAND_1130 = {1{`RANDOM}};
- flush_105 = _RAND_1130[0:0];
- _RAND_1131 = {1{`RANDOM}};
- flush_106 = _RAND_1131[0:0];
- _RAND_1132 = {1{`RANDOM}};
- flush_107 = _RAND_1132[0:0];
- _RAND_1133 = {1{`RANDOM}};
- flush_108 = _RAND_1133[0:0];
- _RAND_1134 = {1{`RANDOM}};
- flush_109 = _RAND_1134[0:0];
- _RAND_1135 = {1{`RANDOM}};
- flush_110 = _RAND_1135[0:0];
- _RAND_1136 = {1{`RANDOM}};
- flush_111 = _RAND_1136[0:0];
- _RAND_1137 = {1{`RANDOM}};
- flush_112 = _RAND_1137[0:0];
- _RAND_1138 = {1{`RANDOM}};
- flush_113 = _RAND_1138[0:0];
- _RAND_1139 = {1{`RANDOM}};
- flush_114 = _RAND_1139[0:0];
- _RAND_1140 = {1{`RANDOM}};
- flush_115 = _RAND_1140[0:0];
- _RAND_1141 = {1{`RANDOM}};
- flush_116 = _RAND_1141[0:0];
- _RAND_1142 = {1{`RANDOM}};
- flush_117 = _RAND_1142[0:0];
- _RAND_1143 = {1{`RANDOM}};
- flush_118 = _RAND_1143[0:0];
- _RAND_1144 = {1{`RANDOM}};
- flush_119 = _RAND_1144[0:0];
- _RAND_1145 = {1{`RANDOM}};
- flush_120 = _RAND_1145[0:0];
- _RAND_1146 = {1{`RANDOM}};
- flush_121 = _RAND_1146[0:0];
- _RAND_1147 = {1{`RANDOM}};
- flush_122 = _RAND_1147[0:0];
- _RAND_1148 = {1{`RANDOM}};
- flush_123 = _RAND_1148[0:0];
- _RAND_1149 = {1{`RANDOM}};
- flush_124 = _RAND_1149[0:0];
- _RAND_1150 = {1{`RANDOM}};
- flush_125 = _RAND_1150[0:0];
- _RAND_1151 = {1{`RANDOM}};
- flush_126 = _RAND_1151[0:0];
- _RAND_1152 = {1{`RANDOM}};
- flush_127 = _RAND_1152[0:0];
- _RAND_1153 = {1{`RANDOM}};
- flush_128 = _RAND_1153[0:0];
- _RAND_1154 = {1{`RANDOM}};
- flush_129 = _RAND_1154[0:0];
- _RAND_1155 = {1{`RANDOM}};
- flush_130 = _RAND_1155[0:0];
- _RAND_1156 = {1{`RANDOM}};
- flush_131 = _RAND_1156[0:0];
- _RAND_1157 = {1{`RANDOM}};
- flush_132 = _RAND_1157[0:0];
- _RAND_1158 = {1{`RANDOM}};
- flush_133 = _RAND_1158[0:0];
- _RAND_1159 = {1{`RANDOM}};
- flush_134 = _RAND_1159[0:0];
- _RAND_1160 = {1{`RANDOM}};
- flush_135 = _RAND_1160[0:0];
- _RAND_1161 = {1{`RANDOM}};
- flush_136 = _RAND_1161[0:0];
- _RAND_1162 = {1{`RANDOM}};
- flush_137 = _RAND_1162[0:0];
- _RAND_1163 = {1{`RANDOM}};
- flush_138 = _RAND_1163[0:0];
- _RAND_1164 = {1{`RANDOM}};
- flush_139 = _RAND_1164[0:0];
- _RAND_1165 = {1{`RANDOM}};
- flush_140 = _RAND_1165[0:0];
- _RAND_1166 = {1{`RANDOM}};
- flush_141 = _RAND_1166[0:0];
- _RAND_1167 = {1{`RANDOM}};
- flush_142 = _RAND_1167[0:0];
- _RAND_1168 = {1{`RANDOM}};
- flush_143 = _RAND_1168[0:0];
- _RAND_1169 = {1{`RANDOM}};
- flush_144 = _RAND_1169[0:0];
- _RAND_1170 = {1{`RANDOM}};
- flush_145 = _RAND_1170[0:0];
- _RAND_1171 = {1{`RANDOM}};
- flush_146 = _RAND_1171[0:0];
- _RAND_1172 = {1{`RANDOM}};
- flush_147 = _RAND_1172[0:0];
- _RAND_1173 = {1{`RANDOM}};
- flush_148 = _RAND_1173[0:0];
- _RAND_1174 = {1{`RANDOM}};
- flush_149 = _RAND_1174[0:0];
- _RAND_1175 = {1{`RANDOM}};
- flush_150 = _RAND_1175[0:0];
- _RAND_1176 = {1{`RANDOM}};
- flush_151 = _RAND_1176[0:0];
- _RAND_1177 = {1{`RANDOM}};
- flush_152 = _RAND_1177[0:0];
- _RAND_1178 = {1{`RANDOM}};
- flush_153 = _RAND_1178[0:0];
- _RAND_1179 = {1{`RANDOM}};
- flush_154 = _RAND_1179[0:0];
- _RAND_1180 = {1{`RANDOM}};
- flush_155 = _RAND_1180[0:0];
- _RAND_1181 = {1{`RANDOM}};
- flush_156 = _RAND_1181[0:0];
- _RAND_1182 = {1{`RANDOM}};
- flush_157 = _RAND_1182[0:0];
- _RAND_1183 = {1{`RANDOM}};
- flush_158 = _RAND_1183[0:0];
- _RAND_1184 = {1{`RANDOM}};
- flush_159 = _RAND_1184[0:0];
- _RAND_1185 = {1{`RANDOM}};
- flush_160 = _RAND_1185[0:0];
- _RAND_1186 = {1{`RANDOM}};
- flush_161 = _RAND_1186[0:0];
- _RAND_1187 = {1{`RANDOM}};
- flush_162 = _RAND_1187[0:0];
- _RAND_1188 = {1{`RANDOM}};
- flush_163 = _RAND_1188[0:0];
- _RAND_1189 = {1{`RANDOM}};
- flush_164 = _RAND_1189[0:0];
- _RAND_1190 = {1{`RANDOM}};
- flush_165 = _RAND_1190[0:0];
- _RAND_1191 = {1{`RANDOM}};
- flush_166 = _RAND_1191[0:0];
- _RAND_1192 = {1{`RANDOM}};
- flush_167 = _RAND_1192[0:0];
- _RAND_1193 = {1{`RANDOM}};
- flush_168 = _RAND_1193[0:0];
- _RAND_1194 = {1{`RANDOM}};
- flush_169 = _RAND_1194[0:0];
- _RAND_1195 = {1{`RANDOM}};
- flush_170 = _RAND_1195[0:0];
- _RAND_1196 = {1{`RANDOM}};
- flush_171 = _RAND_1196[0:0];
- _RAND_1197 = {1{`RANDOM}};
- flush_172 = _RAND_1197[0:0];
- _RAND_1198 = {1{`RANDOM}};
- flush_173 = _RAND_1198[0:0];
- _RAND_1199 = {1{`RANDOM}};
- flush_174 = _RAND_1199[0:0];
- _RAND_1200 = {1{`RANDOM}};
- flush_175 = _RAND_1200[0:0];
- _RAND_1201 = {1{`RANDOM}};
- flush_176 = _RAND_1201[0:0];
- _RAND_1202 = {1{`RANDOM}};
- flush_177 = _RAND_1202[0:0];
- _RAND_1203 = {1{`RANDOM}};
- flush_178 = _RAND_1203[0:0];
- _RAND_1204 = {1{`RANDOM}};
- flush_179 = _RAND_1204[0:0];
- _RAND_1205 = {1{`RANDOM}};
- flush_180 = _RAND_1205[0:0];
- _RAND_1206 = {1{`RANDOM}};
- flush_181 = _RAND_1206[0:0];
- _RAND_1207 = {1{`RANDOM}};
- flush_182 = _RAND_1207[0:0];
- _RAND_1208 = {1{`RANDOM}};
- flush_183 = _RAND_1208[0:0];
- _RAND_1209 = {1{`RANDOM}};
- flush_184 = _RAND_1209[0:0];
- _RAND_1210 = {1{`RANDOM}};
- flush_185 = _RAND_1210[0:0];
- _RAND_1211 = {1{`RANDOM}};
- flush_186 = _RAND_1211[0:0];
- _RAND_1212 = {1{`RANDOM}};
- flush_187 = _RAND_1212[0:0];
- _RAND_1213 = {1{`RANDOM}};
- flush_188 = _RAND_1213[0:0];
- _RAND_1214 = {1{`RANDOM}};
- flush_189 = _RAND_1214[0:0];
- _RAND_1215 = {1{`RANDOM}};
- flush_190 = _RAND_1215[0:0];
- _RAND_1216 = {1{`RANDOM}};
- flush_191 = _RAND_1216[0:0];
- _RAND_1217 = {1{`RANDOM}};
- flush_192 = _RAND_1217[0:0];
- _RAND_1218 = {1{`RANDOM}};
- flush_193 = _RAND_1218[0:0];
- _RAND_1219 = {1{`RANDOM}};
- flush_194 = _RAND_1219[0:0];
- _RAND_1220 = {1{`RANDOM}};
- flush_195 = _RAND_1220[0:0];
- _RAND_1221 = {1{`RANDOM}};
- flush_196 = _RAND_1221[0:0];
- _RAND_1222 = {1{`RANDOM}};
- flush_197 = _RAND_1222[0:0];
- _RAND_1223 = {1{`RANDOM}};
- flush_198 = _RAND_1223[0:0];
- _RAND_1224 = {1{`RANDOM}};
- flush_199 = _RAND_1224[0:0];
- _RAND_1225 = {1{`RANDOM}};
- flush_200 = _RAND_1225[0:0];
- _RAND_1226 = {1{`RANDOM}};
- flush_201 = _RAND_1226[0:0];
- _RAND_1227 = {1{`RANDOM}};
- flush_202 = _RAND_1227[0:0];
- _RAND_1228 = {1{`RANDOM}};
- flush_203 = _RAND_1228[0:0];
- _RAND_1229 = {1{`RANDOM}};
- flush_204 = _RAND_1229[0:0];
- _RAND_1230 = {1{`RANDOM}};
- flush_205 = _RAND_1230[0:0];
- _RAND_1231 = {1{`RANDOM}};
- flush_206 = _RAND_1231[0:0];
- _RAND_1232 = {1{`RANDOM}};
- flush_207 = _RAND_1232[0:0];
- _RAND_1233 = {1{`RANDOM}};
- flush_208 = _RAND_1233[0:0];
- _RAND_1234 = {1{`RANDOM}};
- flush_209 = _RAND_1234[0:0];
- _RAND_1235 = {1{`RANDOM}};
- flush_210 = _RAND_1235[0:0];
- _RAND_1236 = {1{`RANDOM}};
- flush_211 = _RAND_1236[0:0];
- _RAND_1237 = {1{`RANDOM}};
- flush_212 = _RAND_1237[0:0];
- _RAND_1238 = {1{`RANDOM}};
- flush_213 = _RAND_1238[0:0];
- _RAND_1239 = {1{`RANDOM}};
- flush_214 = _RAND_1239[0:0];
- _RAND_1240 = {1{`RANDOM}};
- flush_215 = _RAND_1240[0:0];
- _RAND_1241 = {1{`RANDOM}};
- flush_216 = _RAND_1241[0:0];
- _RAND_1242 = {1{`RANDOM}};
- flush_217 = _RAND_1242[0:0];
- _RAND_1243 = {1{`RANDOM}};
- flush_218 = _RAND_1243[0:0];
- _RAND_1244 = {1{`RANDOM}};
- flush_219 = _RAND_1244[0:0];
- _RAND_1245 = {1{`RANDOM}};
- flush_220 = _RAND_1245[0:0];
- _RAND_1246 = {1{`RANDOM}};
- flush_221 = _RAND_1246[0:0];
- _RAND_1247 = {1{`RANDOM}};
- flush_222 = _RAND_1247[0:0];
- _RAND_1248 = {1{`RANDOM}};
- flush_223 = _RAND_1248[0:0];
- _RAND_1249 = {1{`RANDOM}};
- flush_224 = _RAND_1249[0:0];
- _RAND_1250 = {1{`RANDOM}};
- flush_225 = _RAND_1250[0:0];
- _RAND_1251 = {1{`RANDOM}};
- flush_226 = _RAND_1251[0:0];
- _RAND_1252 = {1{`RANDOM}};
- flush_227 = _RAND_1252[0:0];
- _RAND_1253 = {1{`RANDOM}};
- flush_228 = _RAND_1253[0:0];
- _RAND_1254 = {1{`RANDOM}};
- flush_229 = _RAND_1254[0:0];
- _RAND_1255 = {1{`RANDOM}};
- flush_230 = _RAND_1255[0:0];
- _RAND_1256 = {1{`RANDOM}};
- flush_231 = _RAND_1256[0:0];
- _RAND_1257 = {1{`RANDOM}};
- flush_232 = _RAND_1257[0:0];
- _RAND_1258 = {1{`RANDOM}};
- flush_233 = _RAND_1258[0:0];
- _RAND_1259 = {1{`RANDOM}};
- flush_234 = _RAND_1259[0:0];
- _RAND_1260 = {1{`RANDOM}};
- flush_235 = _RAND_1260[0:0];
- _RAND_1261 = {1{`RANDOM}};
- flush_236 = _RAND_1261[0:0];
- _RAND_1262 = {1{`RANDOM}};
- flush_237 = _RAND_1262[0:0];
- _RAND_1263 = {1{`RANDOM}};
- flush_238 = _RAND_1263[0:0];
- _RAND_1264 = {1{`RANDOM}};
- flush_239 = _RAND_1264[0:0];
- _RAND_1265 = {1{`RANDOM}};
- flush_240 = _RAND_1265[0:0];
- _RAND_1266 = {1{`RANDOM}};
- flush_241 = _RAND_1266[0:0];
- _RAND_1267 = {1{`RANDOM}};
- flush_242 = _RAND_1267[0:0];
- _RAND_1268 = {1{`RANDOM}};
- flush_243 = _RAND_1268[0:0];
- _RAND_1269 = {1{`RANDOM}};
- flush_244 = _RAND_1269[0:0];
- _RAND_1270 = {1{`RANDOM}};
- flush_245 = _RAND_1270[0:0];
- _RAND_1271 = {1{`RANDOM}};
- flush_246 = _RAND_1271[0:0];
- _RAND_1272 = {1{`RANDOM}};
- flush_247 = _RAND_1272[0:0];
- _RAND_1273 = {1{`RANDOM}};
- flush_248 = _RAND_1273[0:0];
- _RAND_1274 = {1{`RANDOM}};
- flush_249 = _RAND_1274[0:0];
- _RAND_1275 = {1{`RANDOM}};
- flush_250 = _RAND_1275[0:0];
- _RAND_1276 = {1{`RANDOM}};
- flush_251 = _RAND_1276[0:0];
- _RAND_1277 = {1{`RANDOM}};
- flush_252 = _RAND_1277[0:0];
- _RAND_1278 = {1{`RANDOM}};
- flush_253 = _RAND_1278[0:0];
- _RAND_1279 = {1{`RANDOM}};
- flush_254 = _RAND_1279[0:0];
- _RAND_1280 = {1{`RANDOM}};
- flush_255 = _RAND_1280[0:0];
- _RAND_1281 = {1{`RANDOM}};
- ractive = _RAND_1281[0:0];
- _RAND_1282 = {1{`RANDOM}};
- wactive = _RAND_1282[0:0];
- _RAND_1283 = {1{`RANDOM}};
- axiraddrvalid = _RAND_1283[0:0];
- _RAND_1284 = {1{`RANDOM}};
- axirdataready = _RAND_1284[0:0];
- _RAND_1285 = {1{`RANDOM}};
- axiwrite = _RAND_1285[0:0];
- _RAND_1286 = {1{`RANDOM}};
- memwdataEn = _RAND_1286[0:0];
- _RAND_1287 = {1{`RANDOM}};
- axiwaddrvalid = _RAND_1287[0:0];
- _RAND_1288 = {1{`RANDOM}};
- axiwdatavalid = _RAND_1288[0:0];
- _RAND_1289 = {8{`RANDOM}};
- axiwdatabuf = _RAND_1289[255:0];
- _RAND_1290 = {1{`RANDOM}};
- axiwstrbbuf = _RAND_1290[31:0];
- _RAND_1291 = {1{`RANDOM}};
- axiraddr = _RAND_1291[31:0];
- _RAND_1292 = {1{`RANDOM}};
- axiwaddr = _RAND_1292[31:0];
- _RAND_1293 = {1{`RANDOM}};
- replaceIdReg = _RAND_1293[7:0];
- _RAND_1294 = {1{`RANDOM}};
- wrespcnt = _RAND_1294[8:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- valid_0 = 1'h0;
- end
- if (reset) begin
- valid_1 = 1'h0;
- end
- if (reset) begin
- valid_2 = 1'h0;
- end
- if (reset) begin
- valid_3 = 1'h0;
- end
- if (reset) begin
- valid_4 = 1'h0;
- end
- if (reset) begin
- valid_5 = 1'h0;
- end
- if (reset) begin
- valid_6 = 1'h0;
- end
- if (reset) begin
- valid_7 = 1'h0;
- end
- if (reset) begin
- valid_8 = 1'h0;
- end
- if (reset) begin
- valid_9 = 1'h0;
- end
- if (reset) begin
- valid_10 = 1'h0;
- end
- if (reset) begin
- valid_11 = 1'h0;
- end
- if (reset) begin
- valid_12 = 1'h0;
- end
- if (reset) begin
- valid_13 = 1'h0;
- end
- if (reset) begin
- valid_14 = 1'h0;
- end
- if (reset) begin
- valid_15 = 1'h0;
- end
- if (reset) begin
- valid_16 = 1'h0;
- end
- if (reset) begin
- valid_17 = 1'h0;
- end
- if (reset) begin
- valid_18 = 1'h0;
- end
- if (reset) begin
- valid_19 = 1'h0;
- end
- if (reset) begin
- valid_20 = 1'h0;
- end
- if (reset) begin
- valid_21 = 1'h0;
- end
- if (reset) begin
- valid_22 = 1'h0;
- end
- if (reset) begin
- valid_23 = 1'h0;
- end
- if (reset) begin
- valid_24 = 1'h0;
- end
- if (reset) begin
- valid_25 = 1'h0;
- end
- if (reset) begin
- valid_26 = 1'h0;
- end
- if (reset) begin
- valid_27 = 1'h0;
- end
- if (reset) begin
- valid_28 = 1'h0;
- end
- if (reset) begin
- valid_29 = 1'h0;
- end
- if (reset) begin
- valid_30 = 1'h0;
- end
- if (reset) begin
- valid_31 = 1'h0;
- end
- if (reset) begin
- valid_32 = 1'h0;
- end
- if (reset) begin
- valid_33 = 1'h0;
- end
- if (reset) begin
- valid_34 = 1'h0;
- end
- if (reset) begin
- valid_35 = 1'h0;
- end
- if (reset) begin
- valid_36 = 1'h0;
- end
- if (reset) begin
- valid_37 = 1'h0;
- end
- if (reset) begin
- valid_38 = 1'h0;
- end
- if (reset) begin
- valid_39 = 1'h0;
- end
- if (reset) begin
- valid_40 = 1'h0;
- end
- if (reset) begin
- valid_41 = 1'h0;
- end
- if (reset) begin
- valid_42 = 1'h0;
- end
- if (reset) begin
- valid_43 = 1'h0;
- end
- if (reset) begin
- valid_44 = 1'h0;
- end
- if (reset) begin
- valid_45 = 1'h0;
- end
- if (reset) begin
- valid_46 = 1'h0;
- end
- if (reset) begin
- valid_47 = 1'h0;
- end
- if (reset) begin
- valid_48 = 1'h0;
- end
- if (reset) begin
- valid_49 = 1'h0;
- end
- if (reset) begin
- valid_50 = 1'h0;
- end
- if (reset) begin
- valid_51 = 1'h0;
- end
- if (reset) begin
- valid_52 = 1'h0;
- end
- if (reset) begin
- valid_53 = 1'h0;
- end
- if (reset) begin
- valid_54 = 1'h0;
- end
- if (reset) begin
- valid_55 = 1'h0;
- end
- if (reset) begin
- valid_56 = 1'h0;
- end
- if (reset) begin
- valid_57 = 1'h0;
- end
- if (reset) begin
- valid_58 = 1'h0;
- end
- if (reset) begin
- valid_59 = 1'h0;
- end
- if (reset) begin
- valid_60 = 1'h0;
- end
- if (reset) begin
- valid_61 = 1'h0;
- end
- if (reset) begin
- valid_62 = 1'h0;
- end
- if (reset) begin
- valid_63 = 1'h0;
- end
- if (reset) begin
- valid_64 = 1'h0;
- end
- if (reset) begin
- valid_65 = 1'h0;
- end
- if (reset) begin
- valid_66 = 1'h0;
- end
- if (reset) begin
- valid_67 = 1'h0;
- end
- if (reset) begin
- valid_68 = 1'h0;
- end
- if (reset) begin
- valid_69 = 1'h0;
- end
- if (reset) begin
- valid_70 = 1'h0;
- end
- if (reset) begin
- valid_71 = 1'h0;
- end
- if (reset) begin
- valid_72 = 1'h0;
- end
- if (reset) begin
- valid_73 = 1'h0;
- end
- if (reset) begin
- valid_74 = 1'h0;
- end
- if (reset) begin
- valid_75 = 1'h0;
- end
- if (reset) begin
- valid_76 = 1'h0;
- end
- if (reset) begin
- valid_77 = 1'h0;
- end
- if (reset) begin
- valid_78 = 1'h0;
- end
- if (reset) begin
- valid_79 = 1'h0;
- end
- if (reset) begin
- valid_80 = 1'h0;
- end
- if (reset) begin
- valid_81 = 1'h0;
- end
- if (reset) begin
- valid_82 = 1'h0;
- end
- if (reset) begin
- valid_83 = 1'h0;
- end
- if (reset) begin
- valid_84 = 1'h0;
- end
- if (reset) begin
- valid_85 = 1'h0;
- end
- if (reset) begin
- valid_86 = 1'h0;
- end
- if (reset) begin
- valid_87 = 1'h0;
- end
- if (reset) begin
- valid_88 = 1'h0;
- end
- if (reset) begin
- valid_89 = 1'h0;
- end
- if (reset) begin
- valid_90 = 1'h0;
- end
- if (reset) begin
- valid_91 = 1'h0;
- end
- if (reset) begin
- valid_92 = 1'h0;
- end
- if (reset) begin
- valid_93 = 1'h0;
- end
- if (reset) begin
- valid_94 = 1'h0;
- end
- if (reset) begin
- valid_95 = 1'h0;
- end
- if (reset) begin
- valid_96 = 1'h0;
- end
- if (reset) begin
- valid_97 = 1'h0;
- end
- if (reset) begin
- valid_98 = 1'h0;
- end
- if (reset) begin
- valid_99 = 1'h0;
- end
- if (reset) begin
- valid_100 = 1'h0;
- end
- if (reset) begin
- valid_101 = 1'h0;
- end
- if (reset) begin
- valid_102 = 1'h0;
- end
- if (reset) begin
- valid_103 = 1'h0;
- end
- if (reset) begin
- valid_104 = 1'h0;
- end
- if (reset) begin
- valid_105 = 1'h0;
- end
- if (reset) begin
- valid_106 = 1'h0;
- end
- if (reset) begin
- valid_107 = 1'h0;
- end
- if (reset) begin
- valid_108 = 1'h0;
- end
- if (reset) begin
- valid_109 = 1'h0;
- end
- if (reset) begin
- valid_110 = 1'h0;
- end
- if (reset) begin
- valid_111 = 1'h0;
- end
- if (reset) begin
- valid_112 = 1'h0;
- end
- if (reset) begin
- valid_113 = 1'h0;
- end
- if (reset) begin
- valid_114 = 1'h0;
- end
- if (reset) begin
- valid_115 = 1'h0;
- end
- if (reset) begin
- valid_116 = 1'h0;
- end
- if (reset) begin
- valid_117 = 1'h0;
- end
- if (reset) begin
- valid_118 = 1'h0;
- end
- if (reset) begin
- valid_119 = 1'h0;
- end
- if (reset) begin
- valid_120 = 1'h0;
- end
- if (reset) begin
- valid_121 = 1'h0;
- end
- if (reset) begin
- valid_122 = 1'h0;
- end
- if (reset) begin
- valid_123 = 1'h0;
- end
- if (reset) begin
- valid_124 = 1'h0;
- end
- if (reset) begin
- valid_125 = 1'h0;
- end
- if (reset) begin
- valid_126 = 1'h0;
- end
- if (reset) begin
- valid_127 = 1'h0;
- end
- if (reset) begin
- valid_128 = 1'h0;
- end
- if (reset) begin
- valid_129 = 1'h0;
- end
- if (reset) begin
- valid_130 = 1'h0;
- end
- if (reset) begin
- valid_131 = 1'h0;
- end
- if (reset) begin
- valid_132 = 1'h0;
- end
- if (reset) begin
- valid_133 = 1'h0;
- end
- if (reset) begin
- valid_134 = 1'h0;
- end
- if (reset) begin
- valid_135 = 1'h0;
- end
- if (reset) begin
- valid_136 = 1'h0;
- end
- if (reset) begin
- valid_137 = 1'h0;
- end
- if (reset) begin
- valid_138 = 1'h0;
- end
- if (reset) begin
- valid_139 = 1'h0;
- end
- if (reset) begin
- valid_140 = 1'h0;
- end
- if (reset) begin
- valid_141 = 1'h0;
- end
- if (reset) begin
- valid_142 = 1'h0;
- end
- if (reset) begin
- valid_143 = 1'h0;
- end
- if (reset) begin
- valid_144 = 1'h0;
- end
- if (reset) begin
- valid_145 = 1'h0;
- end
- if (reset) begin
- valid_146 = 1'h0;
- end
- if (reset) begin
- valid_147 = 1'h0;
- end
- if (reset) begin
- valid_148 = 1'h0;
- end
- if (reset) begin
- valid_149 = 1'h0;
- end
- if (reset) begin
- valid_150 = 1'h0;
- end
- if (reset) begin
- valid_151 = 1'h0;
- end
- if (reset) begin
- valid_152 = 1'h0;
- end
- if (reset) begin
- valid_153 = 1'h0;
- end
- if (reset) begin
- valid_154 = 1'h0;
- end
- if (reset) begin
- valid_155 = 1'h0;
- end
- if (reset) begin
- valid_156 = 1'h0;
- end
- if (reset) begin
- valid_157 = 1'h0;
- end
- if (reset) begin
- valid_158 = 1'h0;
- end
- if (reset) begin
- valid_159 = 1'h0;
- end
- if (reset) begin
- valid_160 = 1'h0;
- end
- if (reset) begin
- valid_161 = 1'h0;
- end
- if (reset) begin
- valid_162 = 1'h0;
- end
- if (reset) begin
- valid_163 = 1'h0;
- end
- if (reset) begin
- valid_164 = 1'h0;
- end
- if (reset) begin
- valid_165 = 1'h0;
- end
- if (reset) begin
- valid_166 = 1'h0;
- end
- if (reset) begin
- valid_167 = 1'h0;
- end
- if (reset) begin
- valid_168 = 1'h0;
- end
- if (reset) begin
- valid_169 = 1'h0;
- end
- if (reset) begin
- valid_170 = 1'h0;
- end
- if (reset) begin
- valid_171 = 1'h0;
- end
- if (reset) begin
- valid_172 = 1'h0;
- end
- if (reset) begin
- valid_173 = 1'h0;
- end
- if (reset) begin
- valid_174 = 1'h0;
- end
- if (reset) begin
- valid_175 = 1'h0;
- end
- if (reset) begin
- valid_176 = 1'h0;
- end
- if (reset) begin
- valid_177 = 1'h0;
- end
- if (reset) begin
- valid_178 = 1'h0;
- end
- if (reset) begin
- valid_179 = 1'h0;
- end
- if (reset) begin
- valid_180 = 1'h0;
- end
- if (reset) begin
- valid_181 = 1'h0;
- end
- if (reset) begin
- valid_182 = 1'h0;
- end
- if (reset) begin
- valid_183 = 1'h0;
- end
- if (reset) begin
- valid_184 = 1'h0;
- end
- if (reset) begin
- valid_185 = 1'h0;
- end
- if (reset) begin
- valid_186 = 1'h0;
- end
- if (reset) begin
- valid_187 = 1'h0;
- end
- if (reset) begin
- valid_188 = 1'h0;
- end
- if (reset) begin
- valid_189 = 1'h0;
- end
- if (reset) begin
- valid_190 = 1'h0;
- end
- if (reset) begin
- valid_191 = 1'h0;
- end
- if (reset) begin
- valid_192 = 1'h0;
- end
- if (reset) begin
- valid_193 = 1'h0;
- end
- if (reset) begin
- valid_194 = 1'h0;
- end
- if (reset) begin
- valid_195 = 1'h0;
- end
- if (reset) begin
- valid_196 = 1'h0;
- end
- if (reset) begin
- valid_197 = 1'h0;
- end
- if (reset) begin
- valid_198 = 1'h0;
- end
- if (reset) begin
- valid_199 = 1'h0;
- end
- if (reset) begin
- valid_200 = 1'h0;
- end
- if (reset) begin
- valid_201 = 1'h0;
- end
- if (reset) begin
- valid_202 = 1'h0;
- end
- if (reset) begin
- valid_203 = 1'h0;
- end
- if (reset) begin
- valid_204 = 1'h0;
- end
- if (reset) begin
- valid_205 = 1'h0;
- end
- if (reset) begin
- valid_206 = 1'h0;
- end
- if (reset) begin
- valid_207 = 1'h0;
- end
- if (reset) begin
- valid_208 = 1'h0;
- end
- if (reset) begin
- valid_209 = 1'h0;
- end
- if (reset) begin
- valid_210 = 1'h0;
- end
- if (reset) begin
- valid_211 = 1'h0;
- end
- if (reset) begin
- valid_212 = 1'h0;
- end
- if (reset) begin
- valid_213 = 1'h0;
- end
- if (reset) begin
- valid_214 = 1'h0;
- end
- if (reset) begin
- valid_215 = 1'h0;
- end
- if (reset) begin
- valid_216 = 1'h0;
- end
- if (reset) begin
- valid_217 = 1'h0;
- end
- if (reset) begin
- valid_218 = 1'h0;
- end
- if (reset) begin
- valid_219 = 1'h0;
- end
- if (reset) begin
- valid_220 = 1'h0;
- end
- if (reset) begin
- valid_221 = 1'h0;
- end
- if (reset) begin
- valid_222 = 1'h0;
- end
- if (reset) begin
- valid_223 = 1'h0;
- end
- if (reset) begin
- valid_224 = 1'h0;
- end
- if (reset) begin
- valid_225 = 1'h0;
- end
- if (reset) begin
- valid_226 = 1'h0;
- end
- if (reset) begin
- valid_227 = 1'h0;
- end
- if (reset) begin
- valid_228 = 1'h0;
- end
- if (reset) begin
- valid_229 = 1'h0;
- end
- if (reset) begin
- valid_230 = 1'h0;
- end
- if (reset) begin
- valid_231 = 1'h0;
- end
- if (reset) begin
- valid_232 = 1'h0;
- end
- if (reset) begin
- valid_233 = 1'h0;
- end
- if (reset) begin
- valid_234 = 1'h0;
- end
- if (reset) begin
- valid_235 = 1'h0;
- end
- if (reset) begin
- valid_236 = 1'h0;
- end
- if (reset) begin
- valid_237 = 1'h0;
- end
- if (reset) begin
- valid_238 = 1'h0;
- end
- if (reset) begin
- valid_239 = 1'h0;
- end
- if (reset) begin
- valid_240 = 1'h0;
- end
- if (reset) begin
- valid_241 = 1'h0;
- end
- if (reset) begin
- valid_242 = 1'h0;
- end
- if (reset) begin
- valid_243 = 1'h0;
- end
- if (reset) begin
- valid_244 = 1'h0;
- end
- if (reset) begin
- valid_245 = 1'h0;
- end
- if (reset) begin
- valid_246 = 1'h0;
- end
- if (reset) begin
- valid_247 = 1'h0;
- end
- if (reset) begin
- valid_248 = 1'h0;
- end
- if (reset) begin
- valid_249 = 1'h0;
- end
- if (reset) begin
- valid_250 = 1'h0;
- end
- if (reset) begin
- valid_251 = 1'h0;
- end
- if (reset) begin
- valid_252 = 1'h0;
- end
- if (reset) begin
- valid_253 = 1'h0;
- end
- if (reset) begin
- valid_254 = 1'h0;
- end
- if (reset) begin
- valid_255 = 1'h0;
- end
- if (reset) begin
- dirty_0 = 1'h0;
- end
- if (reset) begin
- dirty_1 = 1'h0;
- end
- if (reset) begin
- dirty_2 = 1'h0;
- end
- if (reset) begin
- dirty_3 = 1'h0;
- end
- if (reset) begin
- dirty_4 = 1'h0;
- end
- if (reset) begin
- dirty_5 = 1'h0;
- end
- if (reset) begin
- dirty_6 = 1'h0;
- end
- if (reset) begin
- dirty_7 = 1'h0;
- end
- if (reset) begin
- dirty_8 = 1'h0;
- end
- if (reset) begin
- dirty_9 = 1'h0;
- end
- if (reset) begin
- dirty_10 = 1'h0;
- end
- if (reset) begin
- dirty_11 = 1'h0;
- end
- if (reset) begin
- dirty_12 = 1'h0;
- end
- if (reset) begin
- dirty_13 = 1'h0;
- end
- if (reset) begin
- dirty_14 = 1'h0;
- end
- if (reset) begin
- dirty_15 = 1'h0;
- end
- if (reset) begin
- dirty_16 = 1'h0;
- end
- if (reset) begin
- dirty_17 = 1'h0;
- end
- if (reset) begin
- dirty_18 = 1'h0;
- end
- if (reset) begin
- dirty_19 = 1'h0;
- end
- if (reset) begin
- dirty_20 = 1'h0;
- end
- if (reset) begin
- dirty_21 = 1'h0;
- end
- if (reset) begin
- dirty_22 = 1'h0;
- end
- if (reset) begin
- dirty_23 = 1'h0;
- end
- if (reset) begin
- dirty_24 = 1'h0;
- end
- if (reset) begin
- dirty_25 = 1'h0;
- end
- if (reset) begin
- dirty_26 = 1'h0;
- end
- if (reset) begin
- dirty_27 = 1'h0;
- end
- if (reset) begin
- dirty_28 = 1'h0;
- end
- if (reset) begin
- dirty_29 = 1'h0;
- end
- if (reset) begin
- dirty_30 = 1'h0;
- end
- if (reset) begin
- dirty_31 = 1'h0;
- end
- if (reset) begin
- dirty_32 = 1'h0;
- end
- if (reset) begin
- dirty_33 = 1'h0;
- end
- if (reset) begin
- dirty_34 = 1'h0;
- end
- if (reset) begin
- dirty_35 = 1'h0;
- end
- if (reset) begin
- dirty_36 = 1'h0;
- end
- if (reset) begin
- dirty_37 = 1'h0;
- end
- if (reset) begin
- dirty_38 = 1'h0;
- end
- if (reset) begin
- dirty_39 = 1'h0;
- end
- if (reset) begin
- dirty_40 = 1'h0;
- end
- if (reset) begin
- dirty_41 = 1'h0;
- end
- if (reset) begin
- dirty_42 = 1'h0;
- end
- if (reset) begin
- dirty_43 = 1'h0;
- end
- if (reset) begin
- dirty_44 = 1'h0;
- end
- if (reset) begin
- dirty_45 = 1'h0;
- end
- if (reset) begin
- dirty_46 = 1'h0;
- end
- if (reset) begin
- dirty_47 = 1'h0;
- end
- if (reset) begin
- dirty_48 = 1'h0;
- end
- if (reset) begin
- dirty_49 = 1'h0;
- end
- if (reset) begin
- dirty_50 = 1'h0;
- end
- if (reset) begin
- dirty_51 = 1'h0;
- end
- if (reset) begin
- dirty_52 = 1'h0;
- end
- if (reset) begin
- dirty_53 = 1'h0;
- end
- if (reset) begin
- dirty_54 = 1'h0;
- end
- if (reset) begin
- dirty_55 = 1'h0;
- end
- if (reset) begin
- dirty_56 = 1'h0;
- end
- if (reset) begin
- dirty_57 = 1'h0;
- end
- if (reset) begin
- dirty_58 = 1'h0;
- end
- if (reset) begin
- dirty_59 = 1'h0;
- end
- if (reset) begin
- dirty_60 = 1'h0;
- end
- if (reset) begin
- dirty_61 = 1'h0;
- end
- if (reset) begin
- dirty_62 = 1'h0;
- end
- if (reset) begin
- dirty_63 = 1'h0;
- end
- if (reset) begin
- dirty_64 = 1'h0;
- end
- if (reset) begin
- dirty_65 = 1'h0;
- end
- if (reset) begin
- dirty_66 = 1'h0;
- end
- if (reset) begin
- dirty_67 = 1'h0;
- end
- if (reset) begin
- dirty_68 = 1'h0;
- end
- if (reset) begin
- dirty_69 = 1'h0;
- end
- if (reset) begin
- dirty_70 = 1'h0;
- end
- if (reset) begin
- dirty_71 = 1'h0;
- end
- if (reset) begin
- dirty_72 = 1'h0;
- end
- if (reset) begin
- dirty_73 = 1'h0;
- end
- if (reset) begin
- dirty_74 = 1'h0;
- end
- if (reset) begin
- dirty_75 = 1'h0;
- end
- if (reset) begin
- dirty_76 = 1'h0;
- end
- if (reset) begin
- dirty_77 = 1'h0;
- end
- if (reset) begin
- dirty_78 = 1'h0;
- end
- if (reset) begin
- dirty_79 = 1'h0;
- end
- if (reset) begin
- dirty_80 = 1'h0;
- end
- if (reset) begin
- dirty_81 = 1'h0;
- end
- if (reset) begin
- dirty_82 = 1'h0;
- end
- if (reset) begin
- dirty_83 = 1'h0;
- end
- if (reset) begin
- dirty_84 = 1'h0;
- end
- if (reset) begin
- dirty_85 = 1'h0;
- end
- if (reset) begin
- dirty_86 = 1'h0;
- end
- if (reset) begin
- dirty_87 = 1'h0;
- end
- if (reset) begin
- dirty_88 = 1'h0;
- end
- if (reset) begin
- dirty_89 = 1'h0;
- end
- if (reset) begin
- dirty_90 = 1'h0;
- end
- if (reset) begin
- dirty_91 = 1'h0;
- end
- if (reset) begin
- dirty_92 = 1'h0;
- end
- if (reset) begin
- dirty_93 = 1'h0;
- end
- if (reset) begin
- dirty_94 = 1'h0;
- end
- if (reset) begin
- dirty_95 = 1'h0;
- end
- if (reset) begin
- dirty_96 = 1'h0;
- end
- if (reset) begin
- dirty_97 = 1'h0;
- end
- if (reset) begin
- dirty_98 = 1'h0;
- end
- if (reset) begin
- dirty_99 = 1'h0;
- end
- if (reset) begin
- dirty_100 = 1'h0;
- end
- if (reset) begin
- dirty_101 = 1'h0;
- end
- if (reset) begin
- dirty_102 = 1'h0;
- end
- if (reset) begin
- dirty_103 = 1'h0;
- end
- if (reset) begin
- dirty_104 = 1'h0;
- end
- if (reset) begin
- dirty_105 = 1'h0;
- end
- if (reset) begin
- dirty_106 = 1'h0;
- end
- if (reset) begin
- dirty_107 = 1'h0;
- end
- if (reset) begin
- dirty_108 = 1'h0;
- end
- if (reset) begin
- dirty_109 = 1'h0;
- end
- if (reset) begin
- dirty_110 = 1'h0;
- end
- if (reset) begin
- dirty_111 = 1'h0;
- end
- if (reset) begin
- dirty_112 = 1'h0;
- end
- if (reset) begin
- dirty_113 = 1'h0;
- end
- if (reset) begin
- dirty_114 = 1'h0;
- end
- if (reset) begin
- dirty_115 = 1'h0;
- end
- if (reset) begin
- dirty_116 = 1'h0;
- end
- if (reset) begin
- dirty_117 = 1'h0;
- end
- if (reset) begin
- dirty_118 = 1'h0;
- end
- if (reset) begin
- dirty_119 = 1'h0;
- end
- if (reset) begin
- dirty_120 = 1'h0;
- end
- if (reset) begin
- dirty_121 = 1'h0;
- end
- if (reset) begin
- dirty_122 = 1'h0;
- end
- if (reset) begin
- dirty_123 = 1'h0;
- end
- if (reset) begin
- dirty_124 = 1'h0;
- end
- if (reset) begin
- dirty_125 = 1'h0;
- end
- if (reset) begin
- dirty_126 = 1'h0;
- end
- if (reset) begin
- dirty_127 = 1'h0;
- end
- if (reset) begin
- dirty_128 = 1'h0;
- end
- if (reset) begin
- dirty_129 = 1'h0;
- end
- if (reset) begin
- dirty_130 = 1'h0;
- end
- if (reset) begin
- dirty_131 = 1'h0;
- end
- if (reset) begin
- dirty_132 = 1'h0;
- end
- if (reset) begin
- dirty_133 = 1'h0;
- end
- if (reset) begin
- dirty_134 = 1'h0;
- end
- if (reset) begin
- dirty_135 = 1'h0;
- end
- if (reset) begin
- dirty_136 = 1'h0;
- end
- if (reset) begin
- dirty_137 = 1'h0;
- end
- if (reset) begin
- dirty_138 = 1'h0;
- end
- if (reset) begin
- dirty_139 = 1'h0;
- end
- if (reset) begin
- dirty_140 = 1'h0;
- end
- if (reset) begin
- dirty_141 = 1'h0;
- end
- if (reset) begin
- dirty_142 = 1'h0;
- end
- if (reset) begin
- dirty_143 = 1'h0;
- end
- if (reset) begin
- dirty_144 = 1'h0;
- end
- if (reset) begin
- dirty_145 = 1'h0;
- end
- if (reset) begin
- dirty_146 = 1'h0;
- end
- if (reset) begin
- dirty_147 = 1'h0;
- end
- if (reset) begin
- dirty_148 = 1'h0;
- end
- if (reset) begin
- dirty_149 = 1'h0;
- end
- if (reset) begin
- dirty_150 = 1'h0;
- end
- if (reset) begin
- dirty_151 = 1'h0;
- end
- if (reset) begin
- dirty_152 = 1'h0;
- end
- if (reset) begin
- dirty_153 = 1'h0;
- end
- if (reset) begin
- dirty_154 = 1'h0;
- end
- if (reset) begin
- dirty_155 = 1'h0;
- end
- if (reset) begin
- dirty_156 = 1'h0;
- end
- if (reset) begin
- dirty_157 = 1'h0;
- end
- if (reset) begin
- dirty_158 = 1'h0;
- end
- if (reset) begin
- dirty_159 = 1'h0;
- end
- if (reset) begin
- dirty_160 = 1'h0;
- end
- if (reset) begin
- dirty_161 = 1'h0;
- end
- if (reset) begin
- dirty_162 = 1'h0;
- end
- if (reset) begin
- dirty_163 = 1'h0;
- end
- if (reset) begin
- dirty_164 = 1'h0;
- end
- if (reset) begin
- dirty_165 = 1'h0;
- end
- if (reset) begin
- dirty_166 = 1'h0;
- end
- if (reset) begin
- dirty_167 = 1'h0;
- end
- if (reset) begin
- dirty_168 = 1'h0;
- end
- if (reset) begin
- dirty_169 = 1'h0;
- end
- if (reset) begin
- dirty_170 = 1'h0;
- end
- if (reset) begin
- dirty_171 = 1'h0;
- end
- if (reset) begin
- dirty_172 = 1'h0;
- end
- if (reset) begin
- dirty_173 = 1'h0;
- end
- if (reset) begin
- dirty_174 = 1'h0;
- end
- if (reset) begin
- dirty_175 = 1'h0;
- end
- if (reset) begin
- dirty_176 = 1'h0;
- end
- if (reset) begin
- dirty_177 = 1'h0;
- end
- if (reset) begin
- dirty_178 = 1'h0;
- end
- if (reset) begin
- dirty_179 = 1'h0;
- end
- if (reset) begin
- dirty_180 = 1'h0;
- end
- if (reset) begin
- dirty_181 = 1'h0;
- end
- if (reset) begin
- dirty_182 = 1'h0;
- end
- if (reset) begin
- dirty_183 = 1'h0;
- end
- if (reset) begin
- dirty_184 = 1'h0;
- end
- if (reset) begin
- dirty_185 = 1'h0;
- end
- if (reset) begin
- dirty_186 = 1'h0;
- end
- if (reset) begin
- dirty_187 = 1'h0;
- end
- if (reset) begin
- dirty_188 = 1'h0;
- end
- if (reset) begin
- dirty_189 = 1'h0;
- end
- if (reset) begin
- dirty_190 = 1'h0;
- end
- if (reset) begin
- dirty_191 = 1'h0;
- end
- if (reset) begin
- dirty_192 = 1'h0;
- end
- if (reset) begin
- dirty_193 = 1'h0;
- end
- if (reset) begin
- dirty_194 = 1'h0;
- end
- if (reset) begin
- dirty_195 = 1'h0;
- end
- if (reset) begin
- dirty_196 = 1'h0;
- end
- if (reset) begin
- dirty_197 = 1'h0;
- end
- if (reset) begin
- dirty_198 = 1'h0;
- end
- if (reset) begin
- dirty_199 = 1'h0;
- end
- if (reset) begin
- dirty_200 = 1'h0;
- end
- if (reset) begin
- dirty_201 = 1'h0;
- end
- if (reset) begin
- dirty_202 = 1'h0;
- end
- if (reset) begin
- dirty_203 = 1'h0;
- end
- if (reset) begin
- dirty_204 = 1'h0;
- end
- if (reset) begin
- dirty_205 = 1'h0;
- end
- if (reset) begin
- dirty_206 = 1'h0;
- end
- if (reset) begin
- dirty_207 = 1'h0;
- end
- if (reset) begin
- dirty_208 = 1'h0;
- end
- if (reset) begin
- dirty_209 = 1'h0;
- end
- if (reset) begin
- dirty_210 = 1'h0;
- end
- if (reset) begin
- dirty_211 = 1'h0;
- end
- if (reset) begin
- dirty_212 = 1'h0;
- end
- if (reset) begin
- dirty_213 = 1'h0;
- end
- if (reset) begin
- dirty_214 = 1'h0;
- end
- if (reset) begin
- dirty_215 = 1'h0;
- end
- if (reset) begin
- dirty_216 = 1'h0;
- end
- if (reset) begin
- dirty_217 = 1'h0;
- end
- if (reset) begin
- dirty_218 = 1'h0;
- end
- if (reset) begin
- dirty_219 = 1'h0;
- end
- if (reset) begin
- dirty_220 = 1'h0;
- end
- if (reset) begin
- dirty_221 = 1'h0;
- end
- if (reset) begin
- dirty_222 = 1'h0;
- end
- if (reset) begin
- dirty_223 = 1'h0;
- end
- if (reset) begin
- dirty_224 = 1'h0;
- end
- if (reset) begin
- dirty_225 = 1'h0;
- end
- if (reset) begin
- dirty_226 = 1'h0;
- end
- if (reset) begin
- dirty_227 = 1'h0;
- end
- if (reset) begin
- dirty_228 = 1'h0;
- end
- if (reset) begin
- dirty_229 = 1'h0;
- end
- if (reset) begin
- dirty_230 = 1'h0;
- end
- if (reset) begin
- dirty_231 = 1'h0;
- end
- if (reset) begin
- dirty_232 = 1'h0;
- end
- if (reset) begin
- dirty_233 = 1'h0;
- end
- if (reset) begin
- dirty_234 = 1'h0;
- end
- if (reset) begin
- dirty_235 = 1'h0;
- end
- if (reset) begin
- dirty_236 = 1'h0;
- end
- if (reset) begin
- dirty_237 = 1'h0;
- end
- if (reset) begin
- dirty_238 = 1'h0;
- end
- if (reset) begin
- dirty_239 = 1'h0;
- end
- if (reset) begin
- dirty_240 = 1'h0;
- end
- if (reset) begin
- dirty_241 = 1'h0;
- end
- if (reset) begin
- dirty_242 = 1'h0;
- end
- if (reset) begin
- dirty_243 = 1'h0;
- end
- if (reset) begin
- dirty_244 = 1'h0;
- end
- if (reset) begin
- dirty_245 = 1'h0;
- end
- if (reset) begin
- dirty_246 = 1'h0;
- end
- if (reset) begin
- dirty_247 = 1'h0;
- end
- if (reset) begin
- dirty_248 = 1'h0;
- end
- if (reset) begin
- dirty_249 = 1'h0;
- end
- if (reset) begin
- dirty_250 = 1'h0;
- end
- if (reset) begin
- dirty_251 = 1'h0;
- end
- if (reset) begin
- dirty_252 = 1'h0;
- end
- if (reset) begin
- dirty_253 = 1'h0;
- end
- if (reset) begin
- dirty_254 = 1'h0;
- end
- if (reset) begin
- dirty_255 = 1'h0;
- end
- if (reset) begin
- fstate = 3'h0;
- end
- if (reset) begin
- flush_0 = 1'h0;
- end
- if (reset) begin
- flush_1 = 1'h0;
- end
- if (reset) begin
- flush_2 = 1'h0;
- end
- if (reset) begin
- flush_3 = 1'h0;
- end
- if (reset) begin
- flush_4 = 1'h0;
- end
- if (reset) begin
- flush_5 = 1'h0;
- end
- if (reset) begin
- flush_6 = 1'h0;
- end
- if (reset) begin
- flush_7 = 1'h0;
- end
- if (reset) begin
- flush_8 = 1'h0;
- end
- if (reset) begin
- flush_9 = 1'h0;
- end
- if (reset) begin
- flush_10 = 1'h0;
- end
- if (reset) begin
- flush_11 = 1'h0;
- end
- if (reset) begin
- flush_12 = 1'h0;
- end
- if (reset) begin
- flush_13 = 1'h0;
- end
- if (reset) begin
- flush_14 = 1'h0;
- end
- if (reset) begin
- flush_15 = 1'h0;
- end
- if (reset) begin
- flush_16 = 1'h0;
- end
- if (reset) begin
- flush_17 = 1'h0;
- end
- if (reset) begin
- flush_18 = 1'h0;
- end
- if (reset) begin
- flush_19 = 1'h0;
- end
- if (reset) begin
- flush_20 = 1'h0;
- end
- if (reset) begin
- flush_21 = 1'h0;
- end
- if (reset) begin
- flush_22 = 1'h0;
- end
- if (reset) begin
- flush_23 = 1'h0;
- end
- if (reset) begin
- flush_24 = 1'h0;
- end
- if (reset) begin
- flush_25 = 1'h0;
- end
- if (reset) begin
- flush_26 = 1'h0;
- end
- if (reset) begin
- flush_27 = 1'h0;
- end
- if (reset) begin
- flush_28 = 1'h0;
- end
- if (reset) begin
- flush_29 = 1'h0;
- end
- if (reset) begin
- flush_30 = 1'h0;
- end
- if (reset) begin
- flush_31 = 1'h0;
- end
- if (reset) begin
- flush_32 = 1'h0;
- end
- if (reset) begin
- flush_33 = 1'h0;
- end
- if (reset) begin
- flush_34 = 1'h0;
- end
- if (reset) begin
- flush_35 = 1'h0;
- end
- if (reset) begin
- flush_36 = 1'h0;
- end
- if (reset) begin
- flush_37 = 1'h0;
- end
- if (reset) begin
- flush_38 = 1'h0;
- end
- if (reset) begin
- flush_39 = 1'h0;
- end
- if (reset) begin
- flush_40 = 1'h0;
- end
- if (reset) begin
- flush_41 = 1'h0;
- end
- if (reset) begin
- flush_42 = 1'h0;
- end
- if (reset) begin
- flush_43 = 1'h0;
- end
- if (reset) begin
- flush_44 = 1'h0;
- end
- if (reset) begin
- flush_45 = 1'h0;
- end
- if (reset) begin
- flush_46 = 1'h0;
- end
- if (reset) begin
- flush_47 = 1'h0;
- end
- if (reset) begin
- flush_48 = 1'h0;
- end
- if (reset) begin
- flush_49 = 1'h0;
- end
- if (reset) begin
- flush_50 = 1'h0;
- end
- if (reset) begin
- flush_51 = 1'h0;
- end
- if (reset) begin
- flush_52 = 1'h0;
- end
- if (reset) begin
- flush_53 = 1'h0;
- end
- if (reset) begin
- flush_54 = 1'h0;
- end
- if (reset) begin
- flush_55 = 1'h0;
- end
- if (reset) begin
- flush_56 = 1'h0;
- end
- if (reset) begin
- flush_57 = 1'h0;
- end
- if (reset) begin
- flush_58 = 1'h0;
- end
- if (reset) begin
- flush_59 = 1'h0;
- end
- if (reset) begin
- flush_60 = 1'h0;
- end
- if (reset) begin
- flush_61 = 1'h0;
- end
- if (reset) begin
- flush_62 = 1'h0;
- end
- if (reset) begin
- flush_63 = 1'h0;
- end
- if (reset) begin
- flush_64 = 1'h0;
- end
- if (reset) begin
- flush_65 = 1'h0;
- end
- if (reset) begin
- flush_66 = 1'h0;
- end
- if (reset) begin
- flush_67 = 1'h0;
- end
- if (reset) begin
- flush_68 = 1'h0;
- end
- if (reset) begin
- flush_69 = 1'h0;
- end
- if (reset) begin
- flush_70 = 1'h0;
- end
- if (reset) begin
- flush_71 = 1'h0;
- end
- if (reset) begin
- flush_72 = 1'h0;
- end
- if (reset) begin
- flush_73 = 1'h0;
- end
- if (reset) begin
- flush_74 = 1'h0;
- end
- if (reset) begin
- flush_75 = 1'h0;
- end
- if (reset) begin
- flush_76 = 1'h0;
- end
- if (reset) begin
- flush_77 = 1'h0;
- end
- if (reset) begin
- flush_78 = 1'h0;
- end
- if (reset) begin
- flush_79 = 1'h0;
- end
- if (reset) begin
- flush_80 = 1'h0;
- end
- if (reset) begin
- flush_81 = 1'h0;
- end
- if (reset) begin
- flush_82 = 1'h0;
- end
- if (reset) begin
- flush_83 = 1'h0;
- end
- if (reset) begin
- flush_84 = 1'h0;
- end
- if (reset) begin
- flush_85 = 1'h0;
- end
- if (reset) begin
- flush_86 = 1'h0;
- end
- if (reset) begin
- flush_87 = 1'h0;
- end
- if (reset) begin
- flush_88 = 1'h0;
- end
- if (reset) begin
- flush_89 = 1'h0;
- end
- if (reset) begin
- flush_90 = 1'h0;
- end
- if (reset) begin
- flush_91 = 1'h0;
- end
- if (reset) begin
- flush_92 = 1'h0;
- end
- if (reset) begin
- flush_93 = 1'h0;
- end
- if (reset) begin
- flush_94 = 1'h0;
- end
- if (reset) begin
- flush_95 = 1'h0;
- end
- if (reset) begin
- flush_96 = 1'h0;
- end
- if (reset) begin
- flush_97 = 1'h0;
- end
- if (reset) begin
- flush_98 = 1'h0;
- end
- if (reset) begin
- flush_99 = 1'h0;
- end
- if (reset) begin
- flush_100 = 1'h0;
- end
- if (reset) begin
- flush_101 = 1'h0;
- end
- if (reset) begin
- flush_102 = 1'h0;
- end
- if (reset) begin
- flush_103 = 1'h0;
- end
- if (reset) begin
- flush_104 = 1'h0;
- end
- if (reset) begin
- flush_105 = 1'h0;
- end
- if (reset) begin
- flush_106 = 1'h0;
- end
- if (reset) begin
- flush_107 = 1'h0;
- end
- if (reset) begin
- flush_108 = 1'h0;
- end
- if (reset) begin
- flush_109 = 1'h0;
- end
- if (reset) begin
- flush_110 = 1'h0;
- end
- if (reset) begin
- flush_111 = 1'h0;
- end
- if (reset) begin
- flush_112 = 1'h0;
- end
- if (reset) begin
- flush_113 = 1'h0;
- end
- if (reset) begin
- flush_114 = 1'h0;
- end
- if (reset) begin
- flush_115 = 1'h0;
- end
- if (reset) begin
- flush_116 = 1'h0;
- end
- if (reset) begin
- flush_117 = 1'h0;
- end
- if (reset) begin
- flush_118 = 1'h0;
- end
- if (reset) begin
- flush_119 = 1'h0;
- end
- if (reset) begin
- flush_120 = 1'h0;
- end
- if (reset) begin
- flush_121 = 1'h0;
- end
- if (reset) begin
- flush_122 = 1'h0;
- end
- if (reset) begin
- flush_123 = 1'h0;
- end
- if (reset) begin
- flush_124 = 1'h0;
- end
- if (reset) begin
- flush_125 = 1'h0;
- end
- if (reset) begin
- flush_126 = 1'h0;
- end
- if (reset) begin
- flush_127 = 1'h0;
- end
- if (reset) begin
- flush_128 = 1'h0;
- end
- if (reset) begin
- flush_129 = 1'h0;
- end
- if (reset) begin
- flush_130 = 1'h0;
- end
- if (reset) begin
- flush_131 = 1'h0;
- end
- if (reset) begin
- flush_132 = 1'h0;
- end
- if (reset) begin
- flush_133 = 1'h0;
- end
- if (reset) begin
- flush_134 = 1'h0;
- end
- if (reset) begin
- flush_135 = 1'h0;
- end
- if (reset) begin
- flush_136 = 1'h0;
- end
- if (reset) begin
- flush_137 = 1'h0;
- end
- if (reset) begin
- flush_138 = 1'h0;
- end
- if (reset) begin
- flush_139 = 1'h0;
- end
- if (reset) begin
- flush_140 = 1'h0;
- end
- if (reset) begin
- flush_141 = 1'h0;
- end
- if (reset) begin
- flush_142 = 1'h0;
- end
- if (reset) begin
- flush_143 = 1'h0;
- end
- if (reset) begin
- flush_144 = 1'h0;
- end
- if (reset) begin
- flush_145 = 1'h0;
- end
- if (reset) begin
- flush_146 = 1'h0;
- end
- if (reset) begin
- flush_147 = 1'h0;
- end
- if (reset) begin
- flush_148 = 1'h0;
- end
- if (reset) begin
- flush_149 = 1'h0;
- end
- if (reset) begin
- flush_150 = 1'h0;
- end
- if (reset) begin
- flush_151 = 1'h0;
- end
- if (reset) begin
- flush_152 = 1'h0;
- end
- if (reset) begin
- flush_153 = 1'h0;
- end
- if (reset) begin
- flush_154 = 1'h0;
- end
- if (reset) begin
- flush_155 = 1'h0;
- end
- if (reset) begin
- flush_156 = 1'h0;
- end
- if (reset) begin
- flush_157 = 1'h0;
- end
- if (reset) begin
- flush_158 = 1'h0;
- end
- if (reset) begin
- flush_159 = 1'h0;
- end
- if (reset) begin
- flush_160 = 1'h0;
- end
- if (reset) begin
- flush_161 = 1'h0;
- end
- if (reset) begin
- flush_162 = 1'h0;
- end
- if (reset) begin
- flush_163 = 1'h0;
- end
- if (reset) begin
- flush_164 = 1'h0;
- end
- if (reset) begin
- flush_165 = 1'h0;
- end
- if (reset) begin
- flush_166 = 1'h0;
- end
- if (reset) begin
- flush_167 = 1'h0;
- end
- if (reset) begin
- flush_168 = 1'h0;
- end
- if (reset) begin
- flush_169 = 1'h0;
- end
- if (reset) begin
- flush_170 = 1'h0;
- end
- if (reset) begin
- flush_171 = 1'h0;
- end
- if (reset) begin
- flush_172 = 1'h0;
- end
- if (reset) begin
- flush_173 = 1'h0;
- end
- if (reset) begin
- flush_174 = 1'h0;
- end
- if (reset) begin
- flush_175 = 1'h0;
- end
- if (reset) begin
- flush_176 = 1'h0;
- end
- if (reset) begin
- flush_177 = 1'h0;
- end
- if (reset) begin
- flush_178 = 1'h0;
- end
- if (reset) begin
- flush_179 = 1'h0;
- end
- if (reset) begin
- flush_180 = 1'h0;
- end
- if (reset) begin
- flush_181 = 1'h0;
- end
- if (reset) begin
- flush_182 = 1'h0;
- end
- if (reset) begin
- flush_183 = 1'h0;
- end
- if (reset) begin
- flush_184 = 1'h0;
- end
- if (reset) begin
- flush_185 = 1'h0;
- end
- if (reset) begin
- flush_186 = 1'h0;
- end
- if (reset) begin
- flush_187 = 1'h0;
- end
- if (reset) begin
- flush_188 = 1'h0;
- end
- if (reset) begin
- flush_189 = 1'h0;
- end
- if (reset) begin
- flush_190 = 1'h0;
- end
- if (reset) begin
- flush_191 = 1'h0;
- end
- if (reset) begin
- flush_192 = 1'h0;
- end
- if (reset) begin
- flush_193 = 1'h0;
- end
- if (reset) begin
- flush_194 = 1'h0;
- end
- if (reset) begin
- flush_195 = 1'h0;
- end
- if (reset) begin
- flush_196 = 1'h0;
- end
- if (reset) begin
- flush_197 = 1'h0;
- end
- if (reset) begin
- flush_198 = 1'h0;
- end
- if (reset) begin
- flush_199 = 1'h0;
- end
- if (reset) begin
- flush_200 = 1'h0;
- end
- if (reset) begin
- flush_201 = 1'h0;
- end
- if (reset) begin
- flush_202 = 1'h0;
- end
- if (reset) begin
- flush_203 = 1'h0;
- end
- if (reset) begin
- flush_204 = 1'h0;
- end
- if (reset) begin
- flush_205 = 1'h0;
- end
- if (reset) begin
- flush_206 = 1'h0;
- end
- if (reset) begin
- flush_207 = 1'h0;
- end
- if (reset) begin
- flush_208 = 1'h0;
- end
- if (reset) begin
- flush_209 = 1'h0;
- end
- if (reset) begin
- flush_210 = 1'h0;
- end
- if (reset) begin
- flush_211 = 1'h0;
- end
- if (reset) begin
- flush_212 = 1'h0;
- end
- if (reset) begin
- flush_213 = 1'h0;
- end
- if (reset) begin
- flush_214 = 1'h0;
- end
- if (reset) begin
- flush_215 = 1'h0;
- end
- if (reset) begin
- flush_216 = 1'h0;
- end
- if (reset) begin
- flush_217 = 1'h0;
- end
- if (reset) begin
- flush_218 = 1'h0;
- end
- if (reset) begin
- flush_219 = 1'h0;
- end
- if (reset) begin
- flush_220 = 1'h0;
- end
- if (reset) begin
- flush_221 = 1'h0;
- end
- if (reset) begin
- flush_222 = 1'h0;
- end
- if (reset) begin
- flush_223 = 1'h0;
- end
- if (reset) begin
- flush_224 = 1'h0;
- end
- if (reset) begin
- flush_225 = 1'h0;
- end
- if (reset) begin
- flush_226 = 1'h0;
- end
- if (reset) begin
- flush_227 = 1'h0;
- end
- if (reset) begin
- flush_228 = 1'h0;
- end
- if (reset) begin
- flush_229 = 1'h0;
- end
- if (reset) begin
- flush_230 = 1'h0;
- end
- if (reset) begin
- flush_231 = 1'h0;
- end
- if (reset) begin
- flush_232 = 1'h0;
- end
- if (reset) begin
- flush_233 = 1'h0;
- end
- if (reset) begin
- flush_234 = 1'h0;
- end
- if (reset) begin
- flush_235 = 1'h0;
- end
- if (reset) begin
- flush_236 = 1'h0;
- end
- if (reset) begin
- flush_237 = 1'h0;
- end
- if (reset) begin
- flush_238 = 1'h0;
- end
- if (reset) begin
- flush_239 = 1'h0;
- end
- if (reset) begin
- flush_240 = 1'h0;
- end
- if (reset) begin
- flush_241 = 1'h0;
- end
- if (reset) begin
- flush_242 = 1'h0;
- end
- if (reset) begin
- flush_243 = 1'h0;
- end
- if (reset) begin
- flush_244 = 1'h0;
- end
- if (reset) begin
- flush_245 = 1'h0;
- end
- if (reset) begin
- flush_246 = 1'h0;
- end
- if (reset) begin
- flush_247 = 1'h0;
- end
- if (reset) begin
- flush_248 = 1'h0;
- end
- if (reset) begin
- flush_249 = 1'h0;
- end
- if (reset) begin
- flush_250 = 1'h0;
- end
- if (reset) begin
- flush_251 = 1'h0;
- end
- if (reset) begin
- flush_252 = 1'h0;
- end
- if (reset) begin
- flush_253 = 1'h0;
- end
- if (reset) begin
- flush_254 = 1'h0;
- end
- if (reset) begin
- flush_255 = 1'h0;
- end
- if (reset) begin
- ractive = 1'h0;
- end
- if (reset) begin
- wactive = 1'h0;
- end
- if (reset) begin
- axiraddrvalid = 1'h0;
- end
- if (reset) begin
- axirdataready = 1'h0;
- end
- if (reset) begin
- axiwrite = 1'h0;
- end
- if (reset) begin
- memwdataEn = 1'h0;
- end
- if (reset) begin
- axiwaddrvalid = 1'h0;
- end
- if (reset) begin
- axiwdatavalid = 1'h0;
- end
- if (reset) begin
- wrespcnt = 9'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module L1DCache(
- input clock,
- input reset,
- input io_dbus_valid,
- output io_dbus_ready,
- input io_dbus_write,
- input [31:0] io_dbus_addr,
- input [31:0] io_dbus_adrx,
- input [5:0] io_dbus_size,
- input [255:0] io_dbus_wdata,
- input [31:0] io_dbus_wmask,
- output [255:0] io_dbus_rdata,
- input io_axi_write_addr_ready,
- output io_axi_write_addr_valid,
- output [31:0] io_axi_write_addr_bits_addr,
- output [3:0] io_axi_write_addr_bits_id,
- input io_axi_write_data_ready,
- output io_axi_write_data_valid,
- output [255:0] io_axi_write_data_bits_data,
- output [31:0] io_axi_write_data_bits_strb,
- output io_axi_write_resp_ready,
- input io_axi_write_resp_valid,
- input [3:0] io_axi_write_resp_bits_id,
- input io_axi_read_addr_ready,
- output io_axi_read_addr_valid,
- output [31:0] io_axi_read_addr_bits_addr,
- output [3:0] io_axi_read_addr_bits_id,
- output io_axi_read_data_ready,
- input io_axi_read_data_valid,
- input [3:0] io_axi_read_data_bits_id,
- input [255:0] io_axi_read_data_bits_data,
- input io_flush_valid,
- output io_flush_ready,
- input io_flush_all,
- input io_volt_sel
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
-`endif // RANDOMIZE_REG_INIT
- wire bank0_clock; // @[L1DCache.scala 45:21]
- wire bank0_reset; // @[L1DCache.scala 45:21]
- wire bank0_io_dbus_valid; // @[L1DCache.scala 45:21]
- wire bank0_io_dbus_ready; // @[L1DCache.scala 45:21]
- wire bank0_io_dbus_write; // @[L1DCache.scala 45:21]
- wire [30:0] bank0_io_dbus_addr; // @[L1DCache.scala 45:21]
- wire [5:0] bank0_io_dbus_size; // @[L1DCache.scala 45:21]
- wire [255:0] bank0_io_dbus_wdata; // @[L1DCache.scala 45:21]
- wire [31:0] bank0_io_dbus_wmask; // @[L1DCache.scala 45:21]
- wire [255:0] bank0_io_dbus_rdata; // @[L1DCache.scala 45:21]
- wire bank0_io_axi_write_addr_ready; // @[L1DCache.scala 45:21]
- wire bank0_io_axi_write_addr_valid; // @[L1DCache.scala 45:21]
- wire [30:0] bank0_io_axi_write_addr_bits_addr; // @[L1DCache.scala 45:21]
- wire bank0_io_axi_write_data_ready; // @[L1DCache.scala 45:21]
- wire bank0_io_axi_write_data_valid; // @[L1DCache.scala 45:21]
- wire [255:0] bank0_io_axi_write_data_bits_data; // @[L1DCache.scala 45:21]
- wire [31:0] bank0_io_axi_write_data_bits_strb; // @[L1DCache.scala 45:21]
- wire bank0_io_axi_write_resp_ready; // @[L1DCache.scala 45:21]
- wire bank0_io_axi_write_resp_valid; // @[L1DCache.scala 45:21]
- wire bank0_io_axi_read_addr_ready; // @[L1DCache.scala 45:21]
- wire bank0_io_axi_read_addr_valid; // @[L1DCache.scala 45:21]
- wire [30:0] bank0_io_axi_read_addr_bits_addr; // @[L1DCache.scala 45:21]
- wire bank0_io_axi_read_data_ready; // @[L1DCache.scala 45:21]
- wire bank0_io_axi_read_data_valid; // @[L1DCache.scala 45:21]
- wire [255:0] bank0_io_axi_read_data_bits_data; // @[L1DCache.scala 45:21]
- wire bank0_io_flush_valid; // @[L1DCache.scala 45:21]
- wire bank0_io_flush_ready; // @[L1DCache.scala 45:21]
- wire bank0_io_flush_all; // @[L1DCache.scala 45:21]
- wire bank0_io_volt_sel; // @[L1DCache.scala 45:21]
- wire bank1_clock; // @[L1DCache.scala 46:21]
- wire bank1_reset; // @[L1DCache.scala 46:21]
- wire bank1_io_dbus_valid; // @[L1DCache.scala 46:21]
- wire bank1_io_dbus_ready; // @[L1DCache.scala 46:21]
- wire bank1_io_dbus_write; // @[L1DCache.scala 46:21]
- wire [30:0] bank1_io_dbus_addr; // @[L1DCache.scala 46:21]
- wire [5:0] bank1_io_dbus_size; // @[L1DCache.scala 46:21]
- wire [255:0] bank1_io_dbus_wdata; // @[L1DCache.scala 46:21]
- wire [31:0] bank1_io_dbus_wmask; // @[L1DCache.scala 46:21]
- wire [255:0] bank1_io_dbus_rdata; // @[L1DCache.scala 46:21]
- wire bank1_io_axi_write_addr_ready; // @[L1DCache.scala 46:21]
- wire bank1_io_axi_write_addr_valid; // @[L1DCache.scala 46:21]
- wire [30:0] bank1_io_axi_write_addr_bits_addr; // @[L1DCache.scala 46:21]
- wire bank1_io_axi_write_data_ready; // @[L1DCache.scala 46:21]
- wire bank1_io_axi_write_data_valid; // @[L1DCache.scala 46:21]
- wire [255:0] bank1_io_axi_write_data_bits_data; // @[L1DCache.scala 46:21]
- wire [31:0] bank1_io_axi_write_data_bits_strb; // @[L1DCache.scala 46:21]
- wire bank1_io_axi_write_resp_ready; // @[L1DCache.scala 46:21]
- wire bank1_io_axi_write_resp_valid; // @[L1DCache.scala 46:21]
- wire bank1_io_axi_read_addr_ready; // @[L1DCache.scala 46:21]
- wire bank1_io_axi_read_addr_valid; // @[L1DCache.scala 46:21]
- wire [30:0] bank1_io_axi_read_addr_bits_addr; // @[L1DCache.scala 46:21]
- wire bank1_io_axi_read_data_ready; // @[L1DCache.scala 46:21]
- wire bank1_io_axi_read_data_valid; // @[L1DCache.scala 46:21]
- wire [255:0] bank1_io_axi_read_data_bits_data; // @[L1DCache.scala 46:21]
- wire bank1_io_flush_valid; // @[L1DCache.scala 46:21]
- wire bank1_io_flush_ready; // @[L1DCache.scala 46:21]
- wire bank1_io_flush_all; // @[L1DCache.scala 46:21]
- wire bank1_io_volt_sel; // @[L1DCache.scala 46:21]
- wire _T_2 = ~reset; // @[L1DCache.scala 67:9]
- wire [5:0] _GEN_35 = {{1'd0}, io_dbus_addr[4:0]}; // @[L1DCache.scala 71:47]
- wire [5:0] _lineend_T_2 = _GEN_35 + io_dbus_size; // @[L1DCache.scala 71:47]
- wire lineend = _lineend_T_2 > 6'h20; // @[L1DCache.scala 71:63]
- wire dempty = io_dbus_size == 6'h0; // @[L1DCache.scala 72:29]
- wire _dsel0_T_2 = ~dempty; // @[L1DCache.scala 73:48]
- wire dsel0 = ~io_dbus_addr[5] & ~dempty | lineend; // @[L1DCache.scala 73:56]
- wire dsel1 = io_dbus_addr[5] & _dsel0_T_2 | lineend; // @[L1DCache.scala 74:56]
- wire [6:0] _preread_T_1 = ~io_dbus_addr[11:5]; // @[L1DCache.scala 75:17]
- wire _preread_T_3 = ~io_dbus_write; // @[L1DCache.scala 75:55]
- wire preread = _preread_T_1 != 7'h0 & ~io_dbus_write & _dsel0_T_2; // @[L1DCache.scala 75:70]
- wire [30:0] addrA_output = {io_dbus_adrx[31:6],io_dbus_adrx[4:0]}; // @[Cat.scala 31:58]
- wire [30:0] addrA_output_1 = {io_dbus_addr[31:6],io_dbus_addr[4:0]}; // @[Cat.scala 31:58]
- reg rsel_0; // @[L1DCache.scala 78:17]
- reg rsel_1; // @[L1DCache.scala 78:17]
- reg rsel_2; // @[L1DCache.scala 78:17]
- reg rsel_3; // @[L1DCache.scala 78:17]
- reg rsel_4; // @[L1DCache.scala 78:17]
- reg rsel_5; // @[L1DCache.scala 78:17]
- reg rsel_6; // @[L1DCache.scala 78:17]
- reg rsel_7; // @[L1DCache.scala 78:17]
- reg rsel_8; // @[L1DCache.scala 78:17]
- reg rsel_9; // @[L1DCache.scala 78:17]
- reg rsel_10; // @[L1DCache.scala 78:17]
- reg rsel_11; // @[L1DCache.scala 78:17]
- reg rsel_12; // @[L1DCache.scala 78:17]
- reg rsel_13; // @[L1DCache.scala 78:17]
- reg rsel_14; // @[L1DCache.scala 78:17]
- reg rsel_15; // @[L1DCache.scala 78:17]
- reg rsel_16; // @[L1DCache.scala 78:17]
- reg rsel_17; // @[L1DCache.scala 78:17]
- reg rsel_18; // @[L1DCache.scala 78:17]
- reg rsel_19; // @[L1DCache.scala 78:17]
- reg rsel_20; // @[L1DCache.scala 78:17]
- reg rsel_21; // @[L1DCache.scala 78:17]
- reg rsel_22; // @[L1DCache.scala 78:17]
- reg rsel_23; // @[L1DCache.scala 78:17]
- reg rsel_24; // @[L1DCache.scala 78:17]
- reg rsel_25; // @[L1DCache.scala 78:17]
- reg rsel_26; // @[L1DCache.scala 78:17]
- reg rsel_27; // @[L1DCache.scala 78:17]
- reg rsel_28; // @[L1DCache.scala 78:17]
- reg rsel_29; // @[L1DCache.scala 78:17]
- reg rsel_30; // @[L1DCache.scala 78:17]
- reg rsel_31; // @[L1DCache.scala 78:17]
- wire [31:0] _T_5 = io_dbus_addr + 32'h20; // @[L1DCache.scala 80:60]
- wire [62:0] _wmaskSA_T_2 = 63'hffffffff << io_dbus_addr[4:0]; // @[L1DCache.scala 83:38]
- wire [31:0] wmaskSA = _wmaskSA_T_2[31:0]; // @[L1DCache.scala 83:70]
- wire [5:0] _wmaskSB_T_3 = 6'h20 - _GEN_35; // @[L1DCache.scala 84:54]
- wire [31:0] wmaskSB = 32'hffffffff >> _wmaskSB_T_3; // @[L1DCache.scala 84:38]
- wire [31:0] wmaskA = io_dbus_wmask & wmaskSA; // @[L1DCache.scala 85:30]
- wire [31:0] wmaskB = io_dbus_wmask & wmaskSB; // @[L1DCache.scala 86:30]
- wire [31:0] _T_12 = wmaskSA | wmaskSB; // @[L1DCache.scala 91:19]
- wire [31:0] _T_18 = wmaskSA & wmaskSB; // @[L1DCache.scala 92:19]
- wire _dbusready_T_3 = bank1_io_dbus_ready | ~dsel1; // @[L1DCache.scala 111:40]
- wire dbusready = (bank0_io_dbus_ready | ~dsel0) & _dbusready_T_3; // @[L1DCache.scala 110:51]
- wire [5:0] addr = io_dbus_addr[5:0]; // @[L1DCache.scala 115:28]
- wire [6:0] _rsel_31_T = {{1'd0}, addr}; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_30_T_1 = addr + 6'h1; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_29_T_1 = addr + 6'h2; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_28_T_1 = addr + 6'h3; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_27_T_1 = addr + 6'h4; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_26_T_1 = addr + 6'h5; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_25_T_1 = addr + 6'h6; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_24_T_1 = addr + 6'h7; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_23_T_1 = addr + 6'h8; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_22_T_1 = addr + 6'h9; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_21_T_1 = addr + 6'ha; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_20_T_1 = addr + 6'hb; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_19_T_1 = addr + 6'hc; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_18_T_1 = addr + 6'hd; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_17_T_1 = addr + 6'he; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_16_T_1 = addr + 6'hf; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_15_T_1 = addr + 6'h10; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_14_T_1 = addr + 6'h11; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_13_T_1 = addr + 6'h12; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_12_T_1 = addr + 6'h13; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_11_T_1 = addr + 6'h14; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_10_T_1 = addr + 6'h15; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_9_T_1 = addr + 6'h16; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_8_T_1 = addr + 6'h17; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_7_T_1 = addr + 6'h18; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_6_T_1 = addr + 6'h19; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_5_T_1 = addr + 6'h1a; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_4_T_1 = addr + 6'h1b; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_3_T_1 = addr + 6'h1c; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_2_T_1 = addr + 6'h1d; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_1_T_1 = addr + 6'h1e; // @[L1DCache.scala 118:40]
- wire [5:0] _rsel_0_T_1 = addr + 6'h1f; // @[L1DCache.scala 118:40]
- wire [7:0] io_dbus_rdata_d0 = bank0_io_dbus_rdata[7:0]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1 = bank1_io_dbus_rdata[7:0]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d = rsel_0 ? io_dbus_rdata_d1 : io_dbus_rdata_d0; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_1 = bank0_io_dbus_rdata[15:8]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_1 = bank1_io_dbus_rdata[15:8]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_1 = rsel_1 ? io_dbus_rdata_d1_1 : io_dbus_rdata_d0_1; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_2 = bank0_io_dbus_rdata[23:16]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_2 = bank1_io_dbus_rdata[23:16]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_2 = rsel_2 ? io_dbus_rdata_d1_2 : io_dbus_rdata_d0_2; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_3 = bank0_io_dbus_rdata[31:24]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_3 = bank1_io_dbus_rdata[31:24]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_3 = rsel_3 ? io_dbus_rdata_d1_3 : io_dbus_rdata_d0_3; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_4 = bank0_io_dbus_rdata[39:32]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_4 = bank1_io_dbus_rdata[39:32]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_4 = rsel_4 ? io_dbus_rdata_d1_4 : io_dbus_rdata_d0_4; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_5 = bank0_io_dbus_rdata[47:40]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_5 = bank1_io_dbus_rdata[47:40]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_5 = rsel_5 ? io_dbus_rdata_d1_5 : io_dbus_rdata_d0_5; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_6 = bank0_io_dbus_rdata[55:48]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_6 = bank1_io_dbus_rdata[55:48]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_6 = rsel_6 ? io_dbus_rdata_d1_6 : io_dbus_rdata_d0_6; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_7 = bank0_io_dbus_rdata[63:56]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_7 = bank1_io_dbus_rdata[63:56]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_7 = rsel_7 ? io_dbus_rdata_d1_7 : io_dbus_rdata_d0_7; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_8 = bank0_io_dbus_rdata[71:64]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_8 = bank1_io_dbus_rdata[71:64]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_8 = rsel_8 ? io_dbus_rdata_d1_8 : io_dbus_rdata_d0_8; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_9 = bank0_io_dbus_rdata[79:72]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_9 = bank1_io_dbus_rdata[79:72]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_9 = rsel_9 ? io_dbus_rdata_d1_9 : io_dbus_rdata_d0_9; // @[L1DCache.scala 126:18]
- wire [79:0] io_dbus_rdata_r_8 = {io_dbus_rdata_d_9,io_dbus_rdata_d_8,io_dbus_rdata_d_7,io_dbus_rdata_d_6,
- io_dbus_rdata_d_5,io_dbus_rdata_d_4,io_dbus_rdata_d_3,io_dbus_rdata_d_2,io_dbus_rdata_d_1,io_dbus_rdata_d}; // @[Cat.scala 31:58]
- wire [7:0] io_dbus_rdata_d0_10 = bank0_io_dbus_rdata[87:80]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_10 = bank1_io_dbus_rdata[87:80]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_10 = rsel_10 ? io_dbus_rdata_d1_10 : io_dbus_rdata_d0_10; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_11 = bank0_io_dbus_rdata[95:88]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_11 = bank1_io_dbus_rdata[95:88]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_11 = rsel_11 ? io_dbus_rdata_d1_11 : io_dbus_rdata_d0_11; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_12 = bank0_io_dbus_rdata[103:96]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_12 = bank1_io_dbus_rdata[103:96]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_12 = rsel_12 ? io_dbus_rdata_d1_12 : io_dbus_rdata_d0_12; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_13 = bank0_io_dbus_rdata[111:104]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_13 = bank1_io_dbus_rdata[111:104]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_13 = rsel_13 ? io_dbus_rdata_d1_13 : io_dbus_rdata_d0_13; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_14 = bank0_io_dbus_rdata[119:112]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_14 = bank1_io_dbus_rdata[119:112]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_14 = rsel_14 ? io_dbus_rdata_d1_14 : io_dbus_rdata_d0_14; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_15 = bank0_io_dbus_rdata[127:120]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_15 = bank1_io_dbus_rdata[127:120]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_15 = rsel_15 ? io_dbus_rdata_d1_15 : io_dbus_rdata_d0_15; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_16 = bank0_io_dbus_rdata[135:128]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_16 = bank1_io_dbus_rdata[135:128]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_16 = rsel_16 ? io_dbus_rdata_d1_16 : io_dbus_rdata_d0_16; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_17 = bank0_io_dbus_rdata[143:136]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_17 = bank1_io_dbus_rdata[143:136]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_17 = rsel_17 ? io_dbus_rdata_d1_17 : io_dbus_rdata_d0_17; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_18 = bank0_io_dbus_rdata[151:144]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_18 = bank1_io_dbus_rdata[151:144]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_18 = rsel_18 ? io_dbus_rdata_d1_18 : io_dbus_rdata_d0_18; // @[L1DCache.scala 126:18]
- wire [151:0] io_dbus_rdata_r_17 = {io_dbus_rdata_d_18,io_dbus_rdata_d_17,io_dbus_rdata_d_16,io_dbus_rdata_d_15,
- io_dbus_rdata_d_14,io_dbus_rdata_d_13,io_dbus_rdata_d_12,io_dbus_rdata_d_11,io_dbus_rdata_d_10,io_dbus_rdata_r_8}; // @[Cat.scala 31:58]
- wire [7:0] io_dbus_rdata_d0_19 = bank0_io_dbus_rdata[159:152]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_19 = bank1_io_dbus_rdata[159:152]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_19 = rsel_19 ? io_dbus_rdata_d1_19 : io_dbus_rdata_d0_19; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_20 = bank0_io_dbus_rdata[167:160]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_20 = bank1_io_dbus_rdata[167:160]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_20 = rsel_20 ? io_dbus_rdata_d1_20 : io_dbus_rdata_d0_20; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_21 = bank0_io_dbus_rdata[175:168]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_21 = bank1_io_dbus_rdata[175:168]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_21 = rsel_21 ? io_dbus_rdata_d1_21 : io_dbus_rdata_d0_21; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_22 = bank0_io_dbus_rdata[183:176]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_22 = bank1_io_dbus_rdata[183:176]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_22 = rsel_22 ? io_dbus_rdata_d1_22 : io_dbus_rdata_d0_22; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_23 = bank0_io_dbus_rdata[191:184]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_23 = bank1_io_dbus_rdata[191:184]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_23 = rsel_23 ? io_dbus_rdata_d1_23 : io_dbus_rdata_d0_23; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_24 = bank0_io_dbus_rdata[199:192]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_24 = bank1_io_dbus_rdata[199:192]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_24 = rsel_24 ? io_dbus_rdata_d1_24 : io_dbus_rdata_d0_24; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_25 = bank0_io_dbus_rdata[207:200]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_25 = bank1_io_dbus_rdata[207:200]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_25 = rsel_25 ? io_dbus_rdata_d1_25 : io_dbus_rdata_d0_25; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_26 = bank0_io_dbus_rdata[215:208]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_26 = bank1_io_dbus_rdata[215:208]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_26 = rsel_26 ? io_dbus_rdata_d1_26 : io_dbus_rdata_d0_26; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_27 = bank0_io_dbus_rdata[223:216]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_27 = bank1_io_dbus_rdata[223:216]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_27 = rsel_27 ? io_dbus_rdata_d1_27 : io_dbus_rdata_d0_27; // @[L1DCache.scala 126:18]
- wire [223:0] io_dbus_rdata_r_26 = {io_dbus_rdata_d_27,io_dbus_rdata_d_26,io_dbus_rdata_d_25,io_dbus_rdata_d_24,
- io_dbus_rdata_d_23,io_dbus_rdata_d_22,io_dbus_rdata_d_21,io_dbus_rdata_d_20,io_dbus_rdata_d_19,io_dbus_rdata_r_17}; // @[Cat.scala 31:58]
- wire [7:0] io_dbus_rdata_d0_28 = bank0_io_dbus_rdata[231:224]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_28 = bank1_io_dbus_rdata[231:224]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_28 = rsel_28 ? io_dbus_rdata_d1_28 : io_dbus_rdata_d0_28; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_29 = bank0_io_dbus_rdata[239:232]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_29 = bank1_io_dbus_rdata[239:232]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_29 = rsel_29 ? io_dbus_rdata_d1_29 : io_dbus_rdata_d0_29; // @[L1DCache.scala 126:18]
- wire [7:0] io_dbus_rdata_d0_30 = bank0_io_dbus_rdata[247:240]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_30 = bank1_io_dbus_rdata[247:240]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_30 = rsel_30 ? io_dbus_rdata_d1_30 : io_dbus_rdata_d0_30; // @[L1DCache.scala 126:18]
- wire [247:0] io_dbus_rdata_r_29 = {io_dbus_rdata_d_30,io_dbus_rdata_d_29,io_dbus_rdata_d_28,io_dbus_rdata_r_26}; // @[Cat.scala 31:58]
- wire [7:0] io_dbus_rdata_d0_31 = bank0_io_dbus_rdata[255:248]; // @[L1DCache.scala 124:35]
- wire [7:0] io_dbus_rdata_d1_31 = bank1_io_dbus_rdata[255:248]; // @[L1DCache.scala 125:35]
- wire [7:0] io_dbus_rdata_d_31 = rsel_31 ? io_dbus_rdata_d1_31 : io_dbus_rdata_d0_31; // @[L1DCache.scala 126:18]
- reg addrLatchActive; // @[L1DCache.scala 141:32]
- reg [31:0] addrLatchData; // @[L1DCache.scala 142:26]
- wire _GEN_32 = addrLatchActive & io_dbus_ready ? 1'h0 : addrLatchActive; // @[L1DCache.scala 147:50 148:21 141:32]
- wire rresp0 = ~io_axi_read_data_bits_id[3]; // @[L1DCache.scala 156:59]
- wire raxi1 = ~bank0_io_axi_read_addr_valid; // @[L1DCache.scala 160:15]
- wire [31:0] io_axi_read_addr_bits_addr_output = {bank0_io_axi_read_addr_bits_addr[30:5],1'h0,
- bank0_io_axi_read_addr_bits_addr[4:0]}; // @[Cat.scala 31:58]
- wire [31:0] io_axi_read_addr_bits_addr_output_1 = {bank1_io_axi_read_addr_bits_addr[30:5],1'h1,
- bank1_io_axi_read_addr_bits_addr[4:0]}; // @[Cat.scala 31:58]
- wire _io_axi_read_data_ready_T_1 = bank1_io_axi_read_data_ready & io_axi_read_data_bits_id[3]; // @[L1DCache.scala 177:58]
- wire wresp0 = ~io_axi_write_resp_bits_id[3]; // @[L1DCache.scala 183:60]
- wire waxi0 = bank0_io_axi_write_addr_valid; // @[L1DCache.scala 181:19 187:11]
- wire waxi1 = ~waxi0; // @[L1DCache.scala 188:14]
- wire _io_axi_write_addr_valid_T_1 = bank1_io_axi_write_addr_valid & waxi1; // @[L1DCache.scala 214:60]
- wire [31:0] io_axi_write_addr_bits_addr_output = {bank0_io_axi_write_addr_bits_addr[30:5],1'h0,
- bank0_io_axi_write_addr_bits_addr[4:0]}; // @[Cat.scala 31:58]
- wire [31:0] io_axi_write_addr_bits_addr_output_1 = {bank1_io_axi_write_addr_bits_addr[30:5],1'h1,
- bank1_io_axi_write_addr_bits_addr[4:0]}; // @[Cat.scala 31:58]
- wire _io_axi_write_data_valid_T_1 = bank1_io_axi_write_data_valid & waxi1; // @[L1DCache.scala 221:60]
- L1DCacheBank bank0 ( // @[L1DCache.scala 45:21]
- .clock(bank0_clock),
- .reset(bank0_reset),
- .io_dbus_valid(bank0_io_dbus_valid),
- .io_dbus_ready(bank0_io_dbus_ready),
- .io_dbus_write(bank0_io_dbus_write),
- .io_dbus_addr(bank0_io_dbus_addr),
- .io_dbus_size(bank0_io_dbus_size),
- .io_dbus_wdata(bank0_io_dbus_wdata),
- .io_dbus_wmask(bank0_io_dbus_wmask),
- .io_dbus_rdata(bank0_io_dbus_rdata),
- .io_axi_write_addr_ready(bank0_io_axi_write_addr_ready),
- .io_axi_write_addr_valid(bank0_io_axi_write_addr_valid),
- .io_axi_write_addr_bits_addr(bank0_io_axi_write_addr_bits_addr),
- .io_axi_write_data_ready(bank0_io_axi_write_data_ready),
- .io_axi_write_data_valid(bank0_io_axi_write_data_valid),
- .io_axi_write_data_bits_data(bank0_io_axi_write_data_bits_data),
- .io_axi_write_data_bits_strb(bank0_io_axi_write_data_bits_strb),
- .io_axi_write_resp_ready(bank0_io_axi_write_resp_ready),
- .io_axi_write_resp_valid(bank0_io_axi_write_resp_valid),
- .io_axi_read_addr_ready(bank0_io_axi_read_addr_ready),
- .io_axi_read_addr_valid(bank0_io_axi_read_addr_valid),
- .io_axi_read_addr_bits_addr(bank0_io_axi_read_addr_bits_addr),
- .io_axi_read_data_ready(bank0_io_axi_read_data_ready),
- .io_axi_read_data_valid(bank0_io_axi_read_data_valid),
- .io_axi_read_data_bits_data(bank0_io_axi_read_data_bits_data),
- .io_flush_valid(bank0_io_flush_valid),
- .io_flush_ready(bank0_io_flush_ready),
- .io_flush_all(bank0_io_flush_all),
- .io_volt_sel(bank0_io_volt_sel)
- );
- L1DCacheBank bank1 ( // @[L1DCache.scala 46:21]
- .clock(bank1_clock),
- .reset(bank1_reset),
- .io_dbus_valid(bank1_io_dbus_valid),
- .io_dbus_ready(bank1_io_dbus_ready),
- .io_dbus_write(bank1_io_dbus_write),
- .io_dbus_addr(bank1_io_dbus_addr),
- .io_dbus_size(bank1_io_dbus_size),
- .io_dbus_wdata(bank1_io_dbus_wdata),
- .io_dbus_wmask(bank1_io_dbus_wmask),
- .io_dbus_rdata(bank1_io_dbus_rdata),
- .io_axi_write_addr_ready(bank1_io_axi_write_addr_ready),
- .io_axi_write_addr_valid(bank1_io_axi_write_addr_valid),
- .io_axi_write_addr_bits_addr(bank1_io_axi_write_addr_bits_addr),
- .io_axi_write_data_ready(bank1_io_axi_write_data_ready),
- .io_axi_write_data_valid(bank1_io_axi_write_data_valid),
- .io_axi_write_data_bits_data(bank1_io_axi_write_data_bits_data),
- .io_axi_write_data_bits_strb(bank1_io_axi_write_data_bits_strb),
- .io_axi_write_resp_ready(bank1_io_axi_write_resp_ready),
- .io_axi_write_resp_valid(bank1_io_axi_write_resp_valid),
- .io_axi_read_addr_ready(bank1_io_axi_read_addr_ready),
- .io_axi_read_addr_valid(bank1_io_axi_read_addr_valid),
- .io_axi_read_addr_bits_addr(bank1_io_axi_read_addr_bits_addr),
- .io_axi_read_data_ready(bank1_io_axi_read_data_ready),
- .io_axi_read_data_valid(bank1_io_axi_read_data_valid),
- .io_axi_read_data_bits_data(bank1_io_axi_read_data_bits_data),
- .io_flush_valid(bank1_io_flush_valid),
- .io_flush_ready(bank1_io_flush_ready),
- .io_flush_all(bank1_io_flush_all),
- .io_volt_sel(bank1_io_volt_sel)
- );
- assign io_dbus_ready = (bank0_io_dbus_ready | ~dsel0) & _dbusready_T_3; // @[L1DCache.scala 110:51]
- assign io_dbus_rdata = {io_dbus_rdata_d_31,io_dbus_rdata_r_29}; // @[Cat.scala 31:58]
- assign io_axi_write_addr_valid = bank0_io_axi_write_addr_valid & waxi0 | _io_axi_write_addr_valid_T_1; // @[L1DCache.scala 213:69]
- assign io_axi_write_addr_bits_addr = waxi0 ? io_axi_write_addr_bits_addr_output : io_axi_write_addr_bits_addr_output_1
- ; // @[L1DCache.scala 215:37]
- assign io_axi_write_addr_bits_id = waxi0 ? 4'h0 : 4'h8; // @[L1DCache.scala 217:35]
- assign io_axi_write_data_valid = bank0_io_axi_write_data_valid & waxi0 | _io_axi_write_data_valid_T_1; // @[L1DCache.scala 220:69]
- assign io_axi_write_data_bits_data = waxi0 ? bank0_io_axi_write_data_bits_data : bank1_io_axi_write_data_bits_data; // @[L1DCache.scala 222:32]
- assign io_axi_write_data_bits_strb = waxi0 ? bank0_io_axi_write_data_bits_strb : bank1_io_axi_write_data_bits_strb; // @[L1DCache.scala 222:32]
- assign io_axi_write_resp_ready = wresp0 | io_axi_write_resp_bits_id[3]; // @[L1DCache.scala 235:70]
- assign io_axi_read_addr_valid = bank0_io_axi_read_addr_valid | bank1_io_axi_read_addr_valid; // @[L1DCache.scala 162:62]
- assign io_axi_read_addr_bits_addr = bank0_io_axi_read_addr_valid ? io_axi_read_addr_bits_addr_output :
- io_axi_read_addr_bits_addr_output_1; // @[L1DCache.scala 163:36]
- assign io_axi_read_addr_bits_id = bank0_io_axi_read_addr_valid ? 4'h0 : 4'h8; // @[L1DCache.scala 165:36]
- assign io_axi_read_data_ready = bank0_io_axi_read_data_ready & rresp0 | _io_axi_read_data_ready_T_1; // @[L1DCache.scala 176:68]
- assign io_flush_ready = bank0_io_flush_ready & bank1_io_flush_ready; // @[L1DCache.scala 253:42]
- assign bank0_clock = clock;
- assign bank0_reset = reset;
- assign bank0_io_dbus_valid = io_dbus_valid & (dsel0 | preread); // @[L1DCache.scala 94:40]
- assign bank0_io_dbus_write = io_dbus_write; // @[L1DCache.scala 95:23]
- assign bank0_io_dbus_addr = io_dbus_addr[5] ? addrA_output : addrA_output_1; // @[L1DCache.scala 76:18]
- assign bank0_io_dbus_size = io_dbus_size; // @[L1DCache.scala 97:23]
- assign bank0_io_dbus_wdata = io_dbus_wdata; // @[L1DCache.scala 100:23]
- assign bank0_io_dbus_wmask = io_dbus_addr[5] ? wmaskB : wmaskA; // @[L1DCache.scala 96:29]
- assign bank0_io_axi_write_addr_ready = io_axi_write_addr_ready & waxi0; // @[L1DCache.scala 224:60]
- assign bank0_io_axi_write_data_ready = io_axi_write_data_ready & waxi0; // @[L1DCache.scala 226:60]
- assign bank0_io_axi_write_resp_valid = io_axi_write_resp_valid & wresp0; // @[L1DCache.scala 229:60]
- assign bank0_io_axi_read_addr_ready = io_axi_read_addr_ready & bank0_io_axi_read_addr_valid; // @[L1DCache.scala 167:58]
- assign bank0_io_axi_read_data_valid = io_axi_read_data_valid & rresp0; // @[L1DCache.scala 170:58]
- assign bank0_io_axi_read_data_bits_data = io_axi_read_data_bits_data; // @[L1DCache.scala 171:31]
- assign bank0_io_flush_valid = io_flush_valid; // @[L1DCache.scala 245:24]
- assign bank0_io_flush_all = io_flush_all; // @[L1DCache.scala 246:24]
- assign bank0_io_volt_sel = io_volt_sel; // @[L1DCache.scala 256:24]
- assign bank1_clock = clock;
- assign bank1_reset = reset;
- assign bank1_io_dbus_valid = io_dbus_valid & (dsel1 | preread); // @[L1DCache.scala 102:40]
- assign bank1_io_dbus_write = io_dbus_write; // @[L1DCache.scala 103:23]
- assign bank1_io_dbus_addr = io_dbus_addr[5] ? addrA_output_1 : addrA_output; // @[L1DCache.scala 77:18]
- assign bank1_io_dbus_size = io_dbus_size; // @[L1DCache.scala 105:23]
- assign bank1_io_dbus_wdata = io_dbus_wdata; // @[L1DCache.scala 108:23]
- assign bank1_io_dbus_wmask = io_dbus_addr[5] ? wmaskA : wmaskB; // @[L1DCache.scala 104:29]
- assign bank1_io_axi_write_addr_ready = io_axi_write_addr_ready & waxi1; // @[L1DCache.scala 225:60]
- assign bank1_io_axi_write_data_ready = io_axi_write_data_ready & waxi1; // @[L1DCache.scala 227:60]
- assign bank1_io_axi_write_resp_valid = io_axi_write_resp_valid & io_axi_write_resp_bits_id[3]; // @[L1DCache.scala 232:60]
- assign bank1_io_axi_read_addr_ready = io_axi_read_addr_ready & raxi1; // @[L1DCache.scala 168:58]
- assign bank1_io_axi_read_data_valid = io_axi_read_data_valid & io_axi_read_data_bits_id[3]; // @[L1DCache.scala 173:58]
- assign bank1_io_axi_read_data_bits_data = io_axi_read_data_bits_data; // @[L1DCache.scala 174:31]
- assign bank1_io_flush_valid = io_flush_valid; // @[L1DCache.scala 249:24]
- assign bank1_io_flush_all = io_flush_all; // @[L1DCache.scala 250:24]
- assign bank1_io_volt_sel = io_volt_sel; // @[L1DCache.scala 257:24]
- always @(posedge clock) begin
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_0 <= _rsel_0_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_1 <= _rsel_1_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_2 <= _rsel_2_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_3 <= _rsel_3_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_4 <= _rsel_4_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_5 <= _rsel_5_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_6 <= _rsel_6_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_7 <= _rsel_7_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_8 <= _rsel_8_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_9 <= _rsel_9_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_10 <= _rsel_10_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_11 <= _rsel_11_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_12 <= _rsel_12_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_13 <= _rsel_13_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_14 <= _rsel_14_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_15 <= _rsel_15_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_16 <= _rsel_16_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_17 <= _rsel_17_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_18 <= _rsel_18_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_19 <= _rsel_19_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_20 <= _rsel_20_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_21 <= _rsel_21_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_22 <= _rsel_22_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_23 <= _rsel_23_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_24 <= _rsel_24_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_25 <= _rsel_25_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_26 <= _rsel_26_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_27 <= _rsel_27_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_28 <= _rsel_28_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_29 <= _rsel_29_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_30 <= _rsel_30_T_1[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & dbusready & _preread_T_3) begin // @[L1DCache.scala 114:55]
- rsel_31 <= _rsel_31_T[5]; // @[L1DCache.scala 118:31]
- end
- if (io_dbus_valid & ~io_dbus_ready & ~addrLatchActive) begin // @[L1DCache.scala 144:62]
- addrLatchData <= io_dbus_addr; // @[L1DCache.scala 146:19]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(io_dbus_size <= 6'h20)) begin
- $fatal; // @[L1DCache.scala 67:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(io_dbus_size <= 6'h20)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:67 assert(io.dbus.size <= linebytes.U)\n"); // @[L1DCache.scala 67:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_dbus_valid & io_dbus_adrx != _T_5))) begin
- $fatal; // @[L1DCache.scala 80:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_dbus_valid & io_dbus_adrx != _T_5))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:80 assert(!(io.dbus.valid && io.dbus.adrx =/= (io.dbus.addr + linebytes.U)))\n"
- ); // @[L1DCache.scala 80:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_T_12 == 32'hffffffff)) begin
- $fatal; // @[L1DCache.scala 91:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_T_12 == 32'hffffffff)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:91 assert((wmaskSA | wmaskSB) === ~0.U(linebytes.W))\n"); // @[L1DCache.scala 91:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(_T_18 == 32'h0)) begin
- $fatal; // @[L1DCache.scala 92:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(_T_18 == 32'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1DCache.scala:92 assert((wmaskSA & wmaskSB) === 0.U)\n"); // @[L1DCache.scala 92:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(addrLatchActive & addrLatchData != io_dbus_addr))) begin
- $fatal; // @[L1DCache.scala 152:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(addrLatchActive & addrLatchData != io_dbus_addr))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:152 assert(!(addrLatchActive && addrLatchData =/= io.dbus.addr))\n"
- ); // @[L1DCache.scala 152:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_axi_write_addr_valid & ~io_axi_write_data_valid))) begin
- $fatal; // @[L1DCache.scala 238:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_axi_write_addr_valid & ~io_axi_write_data_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:238 assert(!(io.axi.write.addr.valid && !io.axi.write.data.valid))\n"
- ); // @[L1DCache.scala 238:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2 & ~(~(io_axi_write_addr_valid & io_axi_write_addr_ready != io_axi_write_data_ready))) begin
- $fatal; // @[L1DCache.scala 239:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2 & ~(~(io_axi_write_addr_valid & io_axi_write_addr_ready != io_axi_write_data_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1DCache.scala:239 assert(!(io.axi.write.addr.valid && (io.axi.write.addr.ready =/= io.axi.write.data.ready)))\n"
- ); // @[L1DCache.scala 239:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1DCache.scala 144:62]
- addrLatchActive <= 1'h0; // @[L1DCache.scala 145:21]
- end else begin
- addrLatchActive <= io_dbus_valid & ~io_dbus_ready & ~addrLatchActive | _GEN_32;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- rsel_0 = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- rsel_1 = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- rsel_2 = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- rsel_3 = _RAND_3[0:0];
- _RAND_4 = {1{`RANDOM}};
- rsel_4 = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- rsel_5 = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- rsel_6 = _RAND_6[0:0];
- _RAND_7 = {1{`RANDOM}};
- rsel_7 = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- rsel_8 = _RAND_8[0:0];
- _RAND_9 = {1{`RANDOM}};
- rsel_9 = _RAND_9[0:0];
- _RAND_10 = {1{`RANDOM}};
- rsel_10 = _RAND_10[0:0];
- _RAND_11 = {1{`RANDOM}};
- rsel_11 = _RAND_11[0:0];
- _RAND_12 = {1{`RANDOM}};
- rsel_12 = _RAND_12[0:0];
- _RAND_13 = {1{`RANDOM}};
- rsel_13 = _RAND_13[0:0];
- _RAND_14 = {1{`RANDOM}};
- rsel_14 = _RAND_14[0:0];
- _RAND_15 = {1{`RANDOM}};
- rsel_15 = _RAND_15[0:0];
- _RAND_16 = {1{`RANDOM}};
- rsel_16 = _RAND_16[0:0];
- _RAND_17 = {1{`RANDOM}};
- rsel_17 = _RAND_17[0:0];
- _RAND_18 = {1{`RANDOM}};
- rsel_18 = _RAND_18[0:0];
- _RAND_19 = {1{`RANDOM}};
- rsel_19 = _RAND_19[0:0];
- _RAND_20 = {1{`RANDOM}};
- rsel_20 = _RAND_20[0:0];
- _RAND_21 = {1{`RANDOM}};
- rsel_21 = _RAND_21[0:0];
- _RAND_22 = {1{`RANDOM}};
- rsel_22 = _RAND_22[0:0];
- _RAND_23 = {1{`RANDOM}};
- rsel_23 = _RAND_23[0:0];
- _RAND_24 = {1{`RANDOM}};
- rsel_24 = _RAND_24[0:0];
- _RAND_25 = {1{`RANDOM}};
- rsel_25 = _RAND_25[0:0];
- _RAND_26 = {1{`RANDOM}};
- rsel_26 = _RAND_26[0:0];
- _RAND_27 = {1{`RANDOM}};
- rsel_27 = _RAND_27[0:0];
- _RAND_28 = {1{`RANDOM}};
- rsel_28 = _RAND_28[0:0];
- _RAND_29 = {1{`RANDOM}};
- rsel_29 = _RAND_29[0:0];
- _RAND_30 = {1{`RANDOM}};
- rsel_30 = _RAND_30[0:0];
- _RAND_31 = {1{`RANDOM}};
- rsel_31 = _RAND_31[0:0];
- _RAND_32 = {1{`RANDOM}};
- addrLatchActive = _RAND_32[0:0];
- _RAND_33 = {1{`RANDOM}};
- addrLatchData = _RAND_33[31:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- addrLatchActive = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module L1ICache(
- input clock,
- input reset,
- input io_ibus_valid,
- output io_ibus_ready,
- input [31:0] io_ibus_addr,
- output [255:0] io_ibus_rdata,
- input io_flush_valid,
- input io_axi_read_addr_ready,
- output io_axi_read_addr_valid,
- output [31:0] io_axi_read_addr_bits_addr,
- output io_axi_read_data_ready,
- input io_axi_read_data_valid,
- input [255:0] io_axi_read_data_bits_data,
- input io_volt_sel
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [31:0] _RAND_14;
- reg [31:0] _RAND_15;
- reg [31:0] _RAND_16;
- reg [31:0] _RAND_17;
- reg [31:0] _RAND_18;
- reg [31:0] _RAND_19;
- reg [31:0] _RAND_20;
- reg [31:0] _RAND_21;
- reg [31:0] _RAND_22;
- reg [31:0] _RAND_23;
- reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
- reg [31:0] _RAND_26;
- reg [31:0] _RAND_27;
- reg [31:0] _RAND_28;
- reg [31:0] _RAND_29;
- reg [31:0] _RAND_30;
- reg [31:0] _RAND_31;
- reg [31:0] _RAND_32;
- reg [31:0] _RAND_33;
- reg [31:0] _RAND_34;
- reg [31:0] _RAND_35;
- reg [31:0] _RAND_36;
- reg [31:0] _RAND_37;
- reg [31:0] _RAND_38;
- reg [31:0] _RAND_39;
- reg [31:0] _RAND_40;
- reg [31:0] _RAND_41;
- reg [31:0] _RAND_42;
- reg [31:0] _RAND_43;
- reg [31:0] _RAND_44;
- reg [31:0] _RAND_45;
- reg [31:0] _RAND_46;
- reg [31:0] _RAND_47;
- reg [31:0] _RAND_48;
- reg [31:0] _RAND_49;
- reg [31:0] _RAND_50;
- reg [31:0] _RAND_51;
- reg [31:0] _RAND_52;
- reg [31:0] _RAND_53;
- reg [31:0] _RAND_54;
- reg [31:0] _RAND_55;
- reg [31:0] _RAND_56;
- reg [31:0] _RAND_57;
- reg [31:0] _RAND_58;
- reg [31:0] _RAND_59;
- reg [31:0] _RAND_60;
- reg [31:0] _RAND_61;
- reg [31:0] _RAND_62;
- reg [31:0] _RAND_63;
- reg [31:0] _RAND_64;
- reg [31:0] _RAND_65;
- reg [31:0] _RAND_66;
- reg [31:0] _RAND_67;
- reg [31:0] _RAND_68;
- reg [31:0] _RAND_69;
- reg [31:0] _RAND_70;
- reg [31:0] _RAND_71;
- reg [31:0] _RAND_72;
- reg [31:0] _RAND_73;
- reg [31:0] _RAND_74;
- reg [31:0] _RAND_75;
- reg [31:0] _RAND_76;
- reg [31:0] _RAND_77;
- reg [31:0] _RAND_78;
- reg [31:0] _RAND_79;
- reg [31:0] _RAND_80;
- reg [31:0] _RAND_81;
- reg [31:0] _RAND_82;
- reg [31:0] _RAND_83;
- reg [31:0] _RAND_84;
- reg [31:0] _RAND_85;
- reg [31:0] _RAND_86;
- reg [31:0] _RAND_87;
- reg [31:0] _RAND_88;
- reg [31:0] _RAND_89;
- reg [31:0] _RAND_90;
- reg [31:0] _RAND_91;
- reg [31:0] _RAND_92;
- reg [31:0] _RAND_93;
- reg [31:0] _RAND_94;
- reg [31:0] _RAND_95;
- reg [31:0] _RAND_96;
- reg [31:0] _RAND_97;
- reg [31:0] _RAND_98;
- reg [31:0] _RAND_99;
- reg [31:0] _RAND_100;
- reg [31:0] _RAND_101;
- reg [31:0] _RAND_102;
- reg [31:0] _RAND_103;
- reg [31:0] _RAND_104;
- reg [31:0] _RAND_105;
- reg [31:0] _RAND_106;
- reg [31:0] _RAND_107;
- reg [31:0] _RAND_108;
- reg [31:0] _RAND_109;
- reg [31:0] _RAND_110;
- reg [31:0] _RAND_111;
- reg [31:0] _RAND_112;
- reg [31:0] _RAND_113;
- reg [31:0] _RAND_114;
- reg [31:0] _RAND_115;
- reg [31:0] _RAND_116;
- reg [31:0] _RAND_117;
- reg [31:0] _RAND_118;
- reg [31:0] _RAND_119;
- reg [31:0] _RAND_120;
- reg [31:0] _RAND_121;
- reg [31:0] _RAND_122;
- reg [31:0] _RAND_123;
- reg [31:0] _RAND_124;
- reg [31:0] _RAND_125;
- reg [31:0] _RAND_126;
- reg [31:0] _RAND_127;
- reg [31:0] _RAND_128;
- reg [31:0] _RAND_129;
- reg [31:0] _RAND_130;
- reg [31:0] _RAND_131;
- reg [31:0] _RAND_132;
- reg [31:0] _RAND_133;
- reg [31:0] _RAND_134;
- reg [31:0] _RAND_135;
- reg [31:0] _RAND_136;
- reg [31:0] _RAND_137;
- reg [31:0] _RAND_138;
- reg [31:0] _RAND_139;
- reg [31:0] _RAND_140;
- reg [31:0] _RAND_141;
- reg [31:0] _RAND_142;
- reg [31:0] _RAND_143;
- reg [31:0] _RAND_144;
- reg [31:0] _RAND_145;
- reg [31:0] _RAND_146;
- reg [31:0] _RAND_147;
- reg [31:0] _RAND_148;
- reg [31:0] _RAND_149;
- reg [31:0] _RAND_150;
- reg [31:0] _RAND_151;
- reg [31:0] _RAND_152;
- reg [31:0] _RAND_153;
- reg [31:0] _RAND_154;
- reg [31:0] _RAND_155;
- reg [31:0] _RAND_156;
- reg [31:0] _RAND_157;
- reg [31:0] _RAND_158;
- reg [31:0] _RAND_159;
- reg [31:0] _RAND_160;
- reg [31:0] _RAND_161;
- reg [31:0] _RAND_162;
- reg [31:0] _RAND_163;
- reg [31:0] _RAND_164;
- reg [31:0] _RAND_165;
- reg [31:0] _RAND_166;
- reg [31:0] _RAND_167;
- reg [31:0] _RAND_168;
- reg [31:0] _RAND_169;
- reg [31:0] _RAND_170;
- reg [31:0] _RAND_171;
- reg [31:0] _RAND_172;
- reg [31:0] _RAND_173;
- reg [31:0] _RAND_174;
- reg [31:0] _RAND_175;
- reg [31:0] _RAND_176;
- reg [31:0] _RAND_177;
- reg [31:0] _RAND_178;
- reg [31:0] _RAND_179;
- reg [31:0] _RAND_180;
- reg [31:0] _RAND_181;
- reg [31:0] _RAND_182;
- reg [31:0] _RAND_183;
- reg [31:0] _RAND_184;
- reg [31:0] _RAND_185;
- reg [31:0] _RAND_186;
- reg [31:0] _RAND_187;
- reg [31:0] _RAND_188;
- reg [31:0] _RAND_189;
- reg [31:0] _RAND_190;
- reg [31:0] _RAND_191;
- reg [31:0] _RAND_192;
- reg [31:0] _RAND_193;
- reg [31:0] _RAND_194;
- reg [31:0] _RAND_195;
- reg [31:0] _RAND_196;
- reg [31:0] _RAND_197;
- reg [31:0] _RAND_198;
- reg [31:0] _RAND_199;
- reg [31:0] _RAND_200;
- reg [31:0] _RAND_201;
- reg [31:0] _RAND_202;
- reg [31:0] _RAND_203;
- reg [31:0] _RAND_204;
- reg [31:0] _RAND_205;
- reg [31:0] _RAND_206;
- reg [31:0] _RAND_207;
- reg [31:0] _RAND_208;
- reg [31:0] _RAND_209;
- reg [31:0] _RAND_210;
- reg [31:0] _RAND_211;
- reg [31:0] _RAND_212;
- reg [31:0] _RAND_213;
- reg [31:0] _RAND_214;
- reg [31:0] _RAND_215;
- reg [31:0] _RAND_216;
- reg [31:0] _RAND_217;
- reg [31:0] _RAND_218;
- reg [31:0] _RAND_219;
- reg [31:0] _RAND_220;
- reg [31:0] _RAND_221;
- reg [31:0] _RAND_222;
- reg [31:0] _RAND_223;
- reg [31:0] _RAND_224;
- reg [31:0] _RAND_225;
- reg [31:0] _RAND_226;
- reg [31:0] _RAND_227;
- reg [31:0] _RAND_228;
- reg [31:0] _RAND_229;
- reg [31:0] _RAND_230;
- reg [31:0] _RAND_231;
- reg [31:0] _RAND_232;
- reg [31:0] _RAND_233;
- reg [31:0] _RAND_234;
- reg [31:0] _RAND_235;
- reg [31:0] _RAND_236;
- reg [31:0] _RAND_237;
- reg [31:0] _RAND_238;
- reg [31:0] _RAND_239;
- reg [31:0] _RAND_240;
- reg [31:0] _RAND_241;
- reg [31:0] _RAND_242;
- reg [31:0] _RAND_243;
- reg [31:0] _RAND_244;
- reg [31:0] _RAND_245;
- reg [31:0] _RAND_246;
- reg [31:0] _RAND_247;
- reg [31:0] _RAND_248;
- reg [31:0] _RAND_249;
- reg [31:0] _RAND_250;
- reg [31:0] _RAND_251;
- reg [31:0] _RAND_252;
- reg [31:0] _RAND_253;
- reg [31:0] _RAND_254;
- reg [31:0] _RAND_255;
- reg [31:0] _RAND_256;
- reg [31:0] _RAND_257;
- reg [31:0] _RAND_258;
- reg [31:0] _RAND_259;
- reg [31:0] _RAND_260;
- reg [31:0] _RAND_261;
- reg [31:0] _RAND_262;
- reg [31:0] _RAND_263;
- reg [31:0] _RAND_264;
- reg [31:0] _RAND_265;
- reg [31:0] _RAND_266;
- reg [31:0] _RAND_267;
- reg [31:0] _RAND_268;
- reg [31:0] _RAND_269;
- reg [31:0] _RAND_270;
- reg [31:0] _RAND_271;
- reg [31:0] _RAND_272;
- reg [31:0] _RAND_273;
- reg [31:0] _RAND_274;
- reg [31:0] _RAND_275;
- reg [31:0] _RAND_276;
- reg [31:0] _RAND_277;
- reg [31:0] _RAND_278;
- reg [31:0] _RAND_279;
- reg [31:0] _RAND_280;
- reg [31:0] _RAND_281;
- reg [31:0] _RAND_282;
- reg [31:0] _RAND_283;
- reg [31:0] _RAND_284;
- reg [31:0] _RAND_285;
- reg [31:0] _RAND_286;
- reg [31:0] _RAND_287;
- reg [31:0] _RAND_288;
- reg [31:0] _RAND_289;
- reg [31:0] _RAND_290;
- reg [31:0] _RAND_291;
- reg [31:0] _RAND_292;
- reg [31:0] _RAND_293;
- reg [31:0] _RAND_294;
- reg [31:0] _RAND_295;
- reg [31:0] _RAND_296;
- reg [31:0] _RAND_297;
- reg [31:0] _RAND_298;
- reg [31:0] _RAND_299;
- reg [31:0] _RAND_300;
- reg [31:0] _RAND_301;
- reg [31:0] _RAND_302;
- reg [31:0] _RAND_303;
- reg [31:0] _RAND_304;
- reg [31:0] _RAND_305;
- reg [31:0] _RAND_306;
- reg [31:0] _RAND_307;
- reg [31:0] _RAND_308;
- reg [31:0] _RAND_309;
- reg [31:0] _RAND_310;
- reg [31:0] _RAND_311;
- reg [31:0] _RAND_312;
- reg [31:0] _RAND_313;
- reg [31:0] _RAND_314;
- reg [31:0] _RAND_315;
- reg [31:0] _RAND_316;
- reg [31:0] _RAND_317;
- reg [31:0] _RAND_318;
- reg [31:0] _RAND_319;
- reg [31:0] _RAND_320;
- reg [31:0] _RAND_321;
- reg [31:0] _RAND_322;
- reg [31:0] _RAND_323;
- reg [31:0] _RAND_324;
- reg [31:0] _RAND_325;
- reg [31:0] _RAND_326;
- reg [31:0] _RAND_327;
- reg [31:0] _RAND_328;
- reg [31:0] _RAND_329;
- reg [31:0] _RAND_330;
- reg [31:0] _RAND_331;
- reg [31:0] _RAND_332;
- reg [31:0] _RAND_333;
- reg [31:0] _RAND_334;
- reg [31:0] _RAND_335;
- reg [31:0] _RAND_336;
- reg [31:0] _RAND_337;
- reg [31:0] _RAND_338;
- reg [31:0] _RAND_339;
- reg [31:0] _RAND_340;
- reg [31:0] _RAND_341;
- reg [31:0] _RAND_342;
- reg [31:0] _RAND_343;
- reg [31:0] _RAND_344;
- reg [31:0] _RAND_345;
- reg [31:0] _RAND_346;
- reg [31:0] _RAND_347;
- reg [31:0] _RAND_348;
- reg [31:0] _RAND_349;
- reg [31:0] _RAND_350;
- reg [31:0] _RAND_351;
- reg [31:0] _RAND_352;
- reg [31:0] _RAND_353;
- reg [31:0] _RAND_354;
- reg [31:0] _RAND_355;
- reg [31:0] _RAND_356;
- reg [31:0] _RAND_357;
- reg [31:0] _RAND_358;
- reg [31:0] _RAND_359;
- reg [31:0] _RAND_360;
- reg [31:0] _RAND_361;
- reg [31:0] _RAND_362;
- reg [31:0] _RAND_363;
- reg [31:0] _RAND_364;
- reg [31:0] _RAND_365;
- reg [31:0] _RAND_366;
- reg [31:0] _RAND_367;
- reg [31:0] _RAND_368;
- reg [31:0] _RAND_369;
- reg [31:0] _RAND_370;
- reg [31:0] _RAND_371;
- reg [31:0] _RAND_372;
- reg [31:0] _RAND_373;
- reg [31:0] _RAND_374;
- reg [31:0] _RAND_375;
- reg [31:0] _RAND_376;
- reg [31:0] _RAND_377;
- reg [31:0] _RAND_378;
- reg [31:0] _RAND_379;
- reg [31:0] _RAND_380;
- reg [31:0] _RAND_381;
- reg [31:0] _RAND_382;
- reg [31:0] _RAND_383;
- reg [31:0] _RAND_384;
- reg [31:0] _RAND_385;
- reg [31:0] _RAND_386;
- reg [31:0] _RAND_387;
- reg [31:0] _RAND_388;
- reg [31:0] _RAND_389;
- reg [31:0] _RAND_390;
- reg [31:0] _RAND_391;
- reg [31:0] _RAND_392;
- reg [31:0] _RAND_393;
- reg [31:0] _RAND_394;
- reg [31:0] _RAND_395;
- reg [31:0] _RAND_396;
- reg [31:0] _RAND_397;
- reg [31:0] _RAND_398;
- reg [31:0] _RAND_399;
- reg [31:0] _RAND_400;
- reg [31:0] _RAND_401;
- reg [31:0] _RAND_402;
- reg [31:0] _RAND_403;
- reg [31:0] _RAND_404;
- reg [31:0] _RAND_405;
- reg [31:0] _RAND_406;
- reg [31:0] _RAND_407;
- reg [31:0] _RAND_408;
- reg [31:0] _RAND_409;
- reg [31:0] _RAND_410;
- reg [31:0] _RAND_411;
- reg [31:0] _RAND_412;
- reg [31:0] _RAND_413;
- reg [31:0] _RAND_414;
- reg [31:0] _RAND_415;
- reg [31:0] _RAND_416;
- reg [31:0] _RAND_417;
- reg [31:0] _RAND_418;
- reg [31:0] _RAND_419;
- reg [31:0] _RAND_420;
- reg [31:0] _RAND_421;
- reg [31:0] _RAND_422;
- reg [31:0] _RAND_423;
- reg [31:0] _RAND_424;
- reg [31:0] _RAND_425;
- reg [31:0] _RAND_426;
- reg [31:0] _RAND_427;
- reg [31:0] _RAND_428;
- reg [31:0] _RAND_429;
- reg [31:0] _RAND_430;
- reg [31:0] _RAND_431;
- reg [31:0] _RAND_432;
- reg [31:0] _RAND_433;
- reg [31:0] _RAND_434;
- reg [31:0] _RAND_435;
- reg [31:0] _RAND_436;
- reg [31:0] _RAND_437;
- reg [31:0] _RAND_438;
- reg [31:0] _RAND_439;
- reg [31:0] _RAND_440;
- reg [31:0] _RAND_441;
- reg [31:0] _RAND_442;
- reg [31:0] _RAND_443;
- reg [31:0] _RAND_444;
- reg [31:0] _RAND_445;
- reg [31:0] _RAND_446;
- reg [31:0] _RAND_447;
- reg [31:0] _RAND_448;
- reg [31:0] _RAND_449;
- reg [31:0] _RAND_450;
- reg [31:0] _RAND_451;
- reg [31:0] _RAND_452;
- reg [31:0] _RAND_453;
- reg [31:0] _RAND_454;
- reg [31:0] _RAND_455;
- reg [31:0] _RAND_456;
- reg [31:0] _RAND_457;
- reg [31:0] _RAND_458;
- reg [31:0] _RAND_459;
- reg [31:0] _RAND_460;
- reg [31:0] _RAND_461;
- reg [31:0] _RAND_462;
- reg [31:0] _RAND_463;
- reg [31:0] _RAND_464;
- reg [31:0] _RAND_465;
- reg [31:0] _RAND_466;
- reg [31:0] _RAND_467;
- reg [31:0] _RAND_468;
- reg [31:0] _RAND_469;
- reg [31:0] _RAND_470;
- reg [31:0] _RAND_471;
- reg [31:0] _RAND_472;
- reg [31:0] _RAND_473;
- reg [31:0] _RAND_474;
- reg [31:0] _RAND_475;
- reg [31:0] _RAND_476;
- reg [31:0] _RAND_477;
- reg [31:0] _RAND_478;
- reg [31:0] _RAND_479;
- reg [31:0] _RAND_480;
- reg [31:0] _RAND_481;
- reg [31:0] _RAND_482;
- reg [31:0] _RAND_483;
- reg [31:0] _RAND_484;
- reg [31:0] _RAND_485;
- reg [31:0] _RAND_486;
- reg [31:0] _RAND_487;
- reg [31:0] _RAND_488;
- reg [31:0] _RAND_489;
- reg [31:0] _RAND_490;
- reg [31:0] _RAND_491;
- reg [31:0] _RAND_492;
- reg [31:0] _RAND_493;
- reg [31:0] _RAND_494;
- reg [31:0] _RAND_495;
- reg [31:0] _RAND_496;
- reg [31:0] _RAND_497;
- reg [31:0] _RAND_498;
- reg [31:0] _RAND_499;
- reg [31:0] _RAND_500;
- reg [31:0] _RAND_501;
- reg [31:0] _RAND_502;
- reg [31:0] _RAND_503;
- reg [31:0] _RAND_504;
- reg [31:0] _RAND_505;
- reg [31:0] _RAND_506;
- reg [31:0] _RAND_507;
- reg [31:0] _RAND_508;
- reg [31:0] _RAND_509;
- reg [31:0] _RAND_510;
- reg [31:0] _RAND_511;
- reg [31:0] _RAND_512;
- reg [31:0] _RAND_513;
- reg [31:0] _RAND_514;
- reg [31:0] _RAND_515;
- reg [31:0] _RAND_516;
- reg [31:0] _RAND_517;
- reg [31:0] _RAND_518;
- reg [31:0] _RAND_519;
- reg [31:0] _RAND_520;
- reg [31:0] _RAND_521;
- reg [31:0] _RAND_522;
- reg [31:0] _RAND_523;
- reg [31:0] _RAND_524;
- reg [31:0] _RAND_525;
- reg [31:0] _RAND_526;
- reg [31:0] _RAND_527;
- reg [31:0] _RAND_528;
- reg [31:0] _RAND_529;
- reg [31:0] _RAND_530;
- reg [31:0] _RAND_531;
- reg [31:0] _RAND_532;
- reg [31:0] _RAND_533;
- reg [31:0] _RAND_534;
- reg [31:0] _RAND_535;
- reg [31:0] _RAND_536;
- reg [31:0] _RAND_537;
- reg [31:0] _RAND_538;
- reg [31:0] _RAND_539;
- reg [31:0] _RAND_540;
- reg [31:0] _RAND_541;
- reg [31:0] _RAND_542;
- reg [31:0] _RAND_543;
- reg [31:0] _RAND_544;
- reg [31:0] _RAND_545;
- reg [31:0] _RAND_546;
- reg [31:0] _RAND_547;
- reg [31:0] _RAND_548;
- reg [31:0] _RAND_549;
- reg [31:0] _RAND_550;
- reg [31:0] _RAND_551;
- reg [31:0] _RAND_552;
- reg [31:0] _RAND_553;
- reg [31:0] _RAND_554;
- reg [31:0] _RAND_555;
- reg [31:0] _RAND_556;
- reg [31:0] _RAND_557;
- reg [31:0] _RAND_558;
- reg [31:0] _RAND_559;
- reg [31:0] _RAND_560;
- reg [31:0] _RAND_561;
- reg [31:0] _RAND_562;
- reg [31:0] _RAND_563;
- reg [31:0] _RAND_564;
- reg [31:0] _RAND_565;
- reg [31:0] _RAND_566;
- reg [31:0] _RAND_567;
- reg [31:0] _RAND_568;
- reg [31:0] _RAND_569;
- reg [31:0] _RAND_570;
- reg [31:0] _RAND_571;
- reg [31:0] _RAND_572;
- reg [31:0] _RAND_573;
- reg [31:0] _RAND_574;
- reg [31:0] _RAND_575;
- reg [31:0] _RAND_576;
- reg [31:0] _RAND_577;
- reg [31:0] _RAND_578;
- reg [31:0] _RAND_579;
- reg [31:0] _RAND_580;
- reg [31:0] _RAND_581;
- reg [31:0] _RAND_582;
- reg [31:0] _RAND_583;
- reg [31:0] _RAND_584;
- reg [31:0] _RAND_585;
- reg [31:0] _RAND_586;
- reg [31:0] _RAND_587;
- reg [31:0] _RAND_588;
- reg [31:0] _RAND_589;
- reg [31:0] _RAND_590;
- reg [31:0] _RAND_591;
- reg [31:0] _RAND_592;
- reg [31:0] _RAND_593;
- reg [31:0] _RAND_594;
- reg [31:0] _RAND_595;
- reg [31:0] _RAND_596;
- reg [31:0] _RAND_597;
- reg [31:0] _RAND_598;
- reg [31:0] _RAND_599;
- reg [31:0] _RAND_600;
- reg [31:0] _RAND_601;
- reg [31:0] _RAND_602;
- reg [31:0] _RAND_603;
- reg [31:0] _RAND_604;
- reg [31:0] _RAND_605;
- reg [31:0] _RAND_606;
- reg [31:0] _RAND_607;
- reg [31:0] _RAND_608;
- reg [31:0] _RAND_609;
- reg [31:0] _RAND_610;
- reg [31:0] _RAND_611;
- reg [31:0] _RAND_612;
- reg [31:0] _RAND_613;
- reg [31:0] _RAND_614;
- reg [31:0] _RAND_615;
- reg [31:0] _RAND_616;
- reg [31:0] _RAND_617;
- reg [31:0] _RAND_618;
- reg [31:0] _RAND_619;
- reg [31:0] _RAND_620;
- reg [31:0] _RAND_621;
- reg [31:0] _RAND_622;
- reg [31:0] _RAND_623;
- reg [31:0] _RAND_624;
- reg [31:0] _RAND_625;
- reg [31:0] _RAND_626;
- reg [31:0] _RAND_627;
- reg [31:0] _RAND_628;
- reg [31:0] _RAND_629;
- reg [31:0] _RAND_630;
- reg [31:0] _RAND_631;
- reg [31:0] _RAND_632;
- reg [31:0] _RAND_633;
- reg [31:0] _RAND_634;
- reg [31:0] _RAND_635;
- reg [31:0] _RAND_636;
- reg [31:0] _RAND_637;
- reg [31:0] _RAND_638;
- reg [31:0] _RAND_639;
- reg [31:0] _RAND_640;
- reg [31:0] _RAND_641;
- reg [31:0] _RAND_642;
- reg [31:0] _RAND_643;
- reg [31:0] _RAND_644;
- reg [31:0] _RAND_645;
- reg [31:0] _RAND_646;
- reg [31:0] _RAND_647;
- reg [31:0] _RAND_648;
- reg [31:0] _RAND_649;
- reg [31:0] _RAND_650;
- reg [31:0] _RAND_651;
- reg [31:0] _RAND_652;
- reg [31:0] _RAND_653;
- reg [31:0] _RAND_654;
- reg [31:0] _RAND_655;
- reg [31:0] _RAND_656;
- reg [31:0] _RAND_657;
- reg [31:0] _RAND_658;
- reg [31:0] _RAND_659;
- reg [31:0] _RAND_660;
- reg [31:0] _RAND_661;
- reg [31:0] _RAND_662;
- reg [31:0] _RAND_663;
- reg [31:0] _RAND_664;
- reg [31:0] _RAND_665;
- reg [31:0] _RAND_666;
- reg [31:0] _RAND_667;
- reg [31:0] _RAND_668;
- reg [31:0] _RAND_669;
- reg [31:0] _RAND_670;
- reg [31:0] _RAND_671;
- reg [31:0] _RAND_672;
- reg [31:0] _RAND_673;
- reg [31:0] _RAND_674;
- reg [31:0] _RAND_675;
- reg [31:0] _RAND_676;
- reg [31:0] _RAND_677;
- reg [31:0] _RAND_678;
- reg [31:0] _RAND_679;
- reg [31:0] _RAND_680;
- reg [31:0] _RAND_681;
- reg [31:0] _RAND_682;
- reg [31:0] _RAND_683;
- reg [31:0] _RAND_684;
- reg [31:0] _RAND_685;
- reg [31:0] _RAND_686;
- reg [31:0] _RAND_687;
- reg [31:0] _RAND_688;
- reg [31:0] _RAND_689;
- reg [31:0] _RAND_690;
- reg [31:0] _RAND_691;
- reg [31:0] _RAND_692;
- reg [31:0] _RAND_693;
- reg [31:0] _RAND_694;
- reg [31:0] _RAND_695;
- reg [31:0] _RAND_696;
- reg [31:0] _RAND_697;
- reg [31:0] _RAND_698;
- reg [31:0] _RAND_699;
- reg [31:0] _RAND_700;
- reg [31:0] _RAND_701;
- reg [31:0] _RAND_702;
- reg [31:0] _RAND_703;
- reg [31:0] _RAND_704;
- reg [31:0] _RAND_705;
- reg [31:0] _RAND_706;
- reg [31:0] _RAND_707;
- reg [31:0] _RAND_708;
- reg [31:0] _RAND_709;
- reg [31:0] _RAND_710;
- reg [31:0] _RAND_711;
- reg [31:0] _RAND_712;
- reg [31:0] _RAND_713;
- reg [31:0] _RAND_714;
- reg [31:0] _RAND_715;
- reg [31:0] _RAND_716;
- reg [31:0] _RAND_717;
- reg [31:0] _RAND_718;
- reg [31:0] _RAND_719;
- reg [31:0] _RAND_720;
- reg [31:0] _RAND_721;
- reg [31:0] _RAND_722;
- reg [31:0] _RAND_723;
- reg [31:0] _RAND_724;
- reg [31:0] _RAND_725;
- reg [31:0] _RAND_726;
- reg [31:0] _RAND_727;
- reg [31:0] _RAND_728;
- reg [31:0] _RAND_729;
- reg [31:0] _RAND_730;
- reg [31:0] _RAND_731;
- reg [31:0] _RAND_732;
- reg [31:0] _RAND_733;
- reg [31:0] _RAND_734;
- reg [31:0] _RAND_735;
- reg [31:0] _RAND_736;
- reg [31:0] _RAND_737;
- reg [31:0] _RAND_738;
- reg [31:0] _RAND_739;
- reg [31:0] _RAND_740;
- reg [31:0] _RAND_741;
- reg [31:0] _RAND_742;
- reg [31:0] _RAND_743;
- reg [31:0] _RAND_744;
- reg [31:0] _RAND_745;
- reg [31:0] _RAND_746;
- reg [31:0] _RAND_747;
- reg [31:0] _RAND_748;
- reg [31:0] _RAND_749;
- reg [31:0] _RAND_750;
- reg [31:0] _RAND_751;
- reg [31:0] _RAND_752;
- reg [31:0] _RAND_753;
- reg [31:0] _RAND_754;
- reg [31:0] _RAND_755;
- reg [31:0] _RAND_756;
- reg [31:0] _RAND_757;
- reg [31:0] _RAND_758;
- reg [31:0] _RAND_759;
- reg [31:0] _RAND_760;
- reg [31:0] _RAND_761;
- reg [31:0] _RAND_762;
- reg [31:0] _RAND_763;
- reg [31:0] _RAND_764;
- reg [31:0] _RAND_765;
- reg [31:0] _RAND_766;
- reg [31:0] _RAND_767;
- reg [31:0] _RAND_768;
- reg [31:0] _RAND_769;
- reg [31:0] _RAND_770;
- reg [31:0] _RAND_771;
- reg [31:0] _RAND_772;
- reg [31:0] _RAND_773;
-`endif // RANDOMIZE_REG_INIT
- wire mem_clock; // @[L1ICache.scala 74:19]
- wire mem_valid; // @[L1ICache.scala 74:19]
- wire mem_write; // @[L1ICache.scala 74:19]
- wire [7:0] mem_addr; // @[L1ICache.scala 74:19]
- wire [255:0] mem_wdata; // @[L1ICache.scala 74:19]
- wire [255:0] mem_rdata; // @[L1ICache.scala 74:19]
- wire mem_volt_sel; // @[L1ICache.scala 74:19]
- reg valid_0; // @[L1ICache.scala 72:22]
- reg valid_1; // @[L1ICache.scala 72:22]
- reg valid_2; // @[L1ICache.scala 72:22]
- reg valid_3; // @[L1ICache.scala 72:22]
- reg valid_4; // @[L1ICache.scala 72:22]
- reg valid_5; // @[L1ICache.scala 72:22]
- reg valid_6; // @[L1ICache.scala 72:22]
- reg valid_7; // @[L1ICache.scala 72:22]
- reg valid_8; // @[L1ICache.scala 72:22]
- reg valid_9; // @[L1ICache.scala 72:22]
- reg valid_10; // @[L1ICache.scala 72:22]
- reg valid_11; // @[L1ICache.scala 72:22]
- reg valid_12; // @[L1ICache.scala 72:22]
- reg valid_13; // @[L1ICache.scala 72:22]
- reg valid_14; // @[L1ICache.scala 72:22]
- reg valid_15; // @[L1ICache.scala 72:22]
- reg valid_16; // @[L1ICache.scala 72:22]
- reg valid_17; // @[L1ICache.scala 72:22]
- reg valid_18; // @[L1ICache.scala 72:22]
- reg valid_19; // @[L1ICache.scala 72:22]
- reg valid_20; // @[L1ICache.scala 72:22]
- reg valid_21; // @[L1ICache.scala 72:22]
- reg valid_22; // @[L1ICache.scala 72:22]
- reg valid_23; // @[L1ICache.scala 72:22]
- reg valid_24; // @[L1ICache.scala 72:22]
- reg valid_25; // @[L1ICache.scala 72:22]
- reg valid_26; // @[L1ICache.scala 72:22]
- reg valid_27; // @[L1ICache.scala 72:22]
- reg valid_28; // @[L1ICache.scala 72:22]
- reg valid_29; // @[L1ICache.scala 72:22]
- reg valid_30; // @[L1ICache.scala 72:22]
- reg valid_31; // @[L1ICache.scala 72:22]
- reg valid_32; // @[L1ICache.scala 72:22]
- reg valid_33; // @[L1ICache.scala 72:22]
- reg valid_34; // @[L1ICache.scala 72:22]
- reg valid_35; // @[L1ICache.scala 72:22]
- reg valid_36; // @[L1ICache.scala 72:22]
- reg valid_37; // @[L1ICache.scala 72:22]
- reg valid_38; // @[L1ICache.scala 72:22]
- reg valid_39; // @[L1ICache.scala 72:22]
- reg valid_40; // @[L1ICache.scala 72:22]
- reg valid_41; // @[L1ICache.scala 72:22]
- reg valid_42; // @[L1ICache.scala 72:22]
- reg valid_43; // @[L1ICache.scala 72:22]
- reg valid_44; // @[L1ICache.scala 72:22]
- reg valid_45; // @[L1ICache.scala 72:22]
- reg valid_46; // @[L1ICache.scala 72:22]
- reg valid_47; // @[L1ICache.scala 72:22]
- reg valid_48; // @[L1ICache.scala 72:22]
- reg valid_49; // @[L1ICache.scala 72:22]
- reg valid_50; // @[L1ICache.scala 72:22]
- reg valid_51; // @[L1ICache.scala 72:22]
- reg valid_52; // @[L1ICache.scala 72:22]
- reg valid_53; // @[L1ICache.scala 72:22]
- reg valid_54; // @[L1ICache.scala 72:22]
- reg valid_55; // @[L1ICache.scala 72:22]
- reg valid_56; // @[L1ICache.scala 72:22]
- reg valid_57; // @[L1ICache.scala 72:22]
- reg valid_58; // @[L1ICache.scala 72:22]
- reg valid_59; // @[L1ICache.scala 72:22]
- reg valid_60; // @[L1ICache.scala 72:22]
- reg valid_61; // @[L1ICache.scala 72:22]
- reg valid_62; // @[L1ICache.scala 72:22]
- reg valid_63; // @[L1ICache.scala 72:22]
- reg valid_64; // @[L1ICache.scala 72:22]
- reg valid_65; // @[L1ICache.scala 72:22]
- reg valid_66; // @[L1ICache.scala 72:22]
- reg valid_67; // @[L1ICache.scala 72:22]
- reg valid_68; // @[L1ICache.scala 72:22]
- reg valid_69; // @[L1ICache.scala 72:22]
- reg valid_70; // @[L1ICache.scala 72:22]
- reg valid_71; // @[L1ICache.scala 72:22]
- reg valid_72; // @[L1ICache.scala 72:22]
- reg valid_73; // @[L1ICache.scala 72:22]
- reg valid_74; // @[L1ICache.scala 72:22]
- reg valid_75; // @[L1ICache.scala 72:22]
- reg valid_76; // @[L1ICache.scala 72:22]
- reg valid_77; // @[L1ICache.scala 72:22]
- reg valid_78; // @[L1ICache.scala 72:22]
- reg valid_79; // @[L1ICache.scala 72:22]
- reg valid_80; // @[L1ICache.scala 72:22]
- reg valid_81; // @[L1ICache.scala 72:22]
- reg valid_82; // @[L1ICache.scala 72:22]
- reg valid_83; // @[L1ICache.scala 72:22]
- reg valid_84; // @[L1ICache.scala 72:22]
- reg valid_85; // @[L1ICache.scala 72:22]
- reg valid_86; // @[L1ICache.scala 72:22]
- reg valid_87; // @[L1ICache.scala 72:22]
- reg valid_88; // @[L1ICache.scala 72:22]
- reg valid_89; // @[L1ICache.scala 72:22]
- reg valid_90; // @[L1ICache.scala 72:22]
- reg valid_91; // @[L1ICache.scala 72:22]
- reg valid_92; // @[L1ICache.scala 72:22]
- reg valid_93; // @[L1ICache.scala 72:22]
- reg valid_94; // @[L1ICache.scala 72:22]
- reg valid_95; // @[L1ICache.scala 72:22]
- reg valid_96; // @[L1ICache.scala 72:22]
- reg valid_97; // @[L1ICache.scala 72:22]
- reg valid_98; // @[L1ICache.scala 72:22]
- reg valid_99; // @[L1ICache.scala 72:22]
- reg valid_100; // @[L1ICache.scala 72:22]
- reg valid_101; // @[L1ICache.scala 72:22]
- reg valid_102; // @[L1ICache.scala 72:22]
- reg valid_103; // @[L1ICache.scala 72:22]
- reg valid_104; // @[L1ICache.scala 72:22]
- reg valid_105; // @[L1ICache.scala 72:22]
- reg valid_106; // @[L1ICache.scala 72:22]
- reg valid_107; // @[L1ICache.scala 72:22]
- reg valid_108; // @[L1ICache.scala 72:22]
- reg valid_109; // @[L1ICache.scala 72:22]
- reg valid_110; // @[L1ICache.scala 72:22]
- reg valid_111; // @[L1ICache.scala 72:22]
- reg valid_112; // @[L1ICache.scala 72:22]
- reg valid_113; // @[L1ICache.scala 72:22]
- reg valid_114; // @[L1ICache.scala 72:22]
- reg valid_115; // @[L1ICache.scala 72:22]
- reg valid_116; // @[L1ICache.scala 72:22]
- reg valid_117; // @[L1ICache.scala 72:22]
- reg valid_118; // @[L1ICache.scala 72:22]
- reg valid_119; // @[L1ICache.scala 72:22]
- reg valid_120; // @[L1ICache.scala 72:22]
- reg valid_121; // @[L1ICache.scala 72:22]
- reg valid_122; // @[L1ICache.scala 72:22]
- reg valid_123; // @[L1ICache.scala 72:22]
- reg valid_124; // @[L1ICache.scala 72:22]
- reg valid_125; // @[L1ICache.scala 72:22]
- reg valid_126; // @[L1ICache.scala 72:22]
- reg valid_127; // @[L1ICache.scala 72:22]
- reg valid_128; // @[L1ICache.scala 72:22]
- reg valid_129; // @[L1ICache.scala 72:22]
- reg valid_130; // @[L1ICache.scala 72:22]
- reg valid_131; // @[L1ICache.scala 72:22]
- reg valid_132; // @[L1ICache.scala 72:22]
- reg valid_133; // @[L1ICache.scala 72:22]
- reg valid_134; // @[L1ICache.scala 72:22]
- reg valid_135; // @[L1ICache.scala 72:22]
- reg valid_136; // @[L1ICache.scala 72:22]
- reg valid_137; // @[L1ICache.scala 72:22]
- reg valid_138; // @[L1ICache.scala 72:22]
- reg valid_139; // @[L1ICache.scala 72:22]
- reg valid_140; // @[L1ICache.scala 72:22]
- reg valid_141; // @[L1ICache.scala 72:22]
- reg valid_142; // @[L1ICache.scala 72:22]
- reg valid_143; // @[L1ICache.scala 72:22]
- reg valid_144; // @[L1ICache.scala 72:22]
- reg valid_145; // @[L1ICache.scala 72:22]
- reg valid_146; // @[L1ICache.scala 72:22]
- reg valid_147; // @[L1ICache.scala 72:22]
- reg valid_148; // @[L1ICache.scala 72:22]
- reg valid_149; // @[L1ICache.scala 72:22]
- reg valid_150; // @[L1ICache.scala 72:22]
- reg valid_151; // @[L1ICache.scala 72:22]
- reg valid_152; // @[L1ICache.scala 72:22]
- reg valid_153; // @[L1ICache.scala 72:22]
- reg valid_154; // @[L1ICache.scala 72:22]
- reg valid_155; // @[L1ICache.scala 72:22]
- reg valid_156; // @[L1ICache.scala 72:22]
- reg valid_157; // @[L1ICache.scala 72:22]
- reg valid_158; // @[L1ICache.scala 72:22]
- reg valid_159; // @[L1ICache.scala 72:22]
- reg valid_160; // @[L1ICache.scala 72:22]
- reg valid_161; // @[L1ICache.scala 72:22]
- reg valid_162; // @[L1ICache.scala 72:22]
- reg valid_163; // @[L1ICache.scala 72:22]
- reg valid_164; // @[L1ICache.scala 72:22]
- reg valid_165; // @[L1ICache.scala 72:22]
- reg valid_166; // @[L1ICache.scala 72:22]
- reg valid_167; // @[L1ICache.scala 72:22]
- reg valid_168; // @[L1ICache.scala 72:22]
- reg valid_169; // @[L1ICache.scala 72:22]
- reg valid_170; // @[L1ICache.scala 72:22]
- reg valid_171; // @[L1ICache.scala 72:22]
- reg valid_172; // @[L1ICache.scala 72:22]
- reg valid_173; // @[L1ICache.scala 72:22]
- reg valid_174; // @[L1ICache.scala 72:22]
- reg valid_175; // @[L1ICache.scala 72:22]
- reg valid_176; // @[L1ICache.scala 72:22]
- reg valid_177; // @[L1ICache.scala 72:22]
- reg valid_178; // @[L1ICache.scala 72:22]
- reg valid_179; // @[L1ICache.scala 72:22]
- reg valid_180; // @[L1ICache.scala 72:22]
- reg valid_181; // @[L1ICache.scala 72:22]
- reg valid_182; // @[L1ICache.scala 72:22]
- reg valid_183; // @[L1ICache.scala 72:22]
- reg valid_184; // @[L1ICache.scala 72:22]
- reg valid_185; // @[L1ICache.scala 72:22]
- reg valid_186; // @[L1ICache.scala 72:22]
- reg valid_187; // @[L1ICache.scala 72:22]
- reg valid_188; // @[L1ICache.scala 72:22]
- reg valid_189; // @[L1ICache.scala 72:22]
- reg valid_190; // @[L1ICache.scala 72:22]
- reg valid_191; // @[L1ICache.scala 72:22]
- reg valid_192; // @[L1ICache.scala 72:22]
- reg valid_193; // @[L1ICache.scala 72:22]
- reg valid_194; // @[L1ICache.scala 72:22]
- reg valid_195; // @[L1ICache.scala 72:22]
- reg valid_196; // @[L1ICache.scala 72:22]
- reg valid_197; // @[L1ICache.scala 72:22]
- reg valid_198; // @[L1ICache.scala 72:22]
- reg valid_199; // @[L1ICache.scala 72:22]
- reg valid_200; // @[L1ICache.scala 72:22]
- reg valid_201; // @[L1ICache.scala 72:22]
- reg valid_202; // @[L1ICache.scala 72:22]
- reg valid_203; // @[L1ICache.scala 72:22]
- reg valid_204; // @[L1ICache.scala 72:22]
- reg valid_205; // @[L1ICache.scala 72:22]
- reg valid_206; // @[L1ICache.scala 72:22]
- reg valid_207; // @[L1ICache.scala 72:22]
- reg valid_208; // @[L1ICache.scala 72:22]
- reg valid_209; // @[L1ICache.scala 72:22]
- reg valid_210; // @[L1ICache.scala 72:22]
- reg valid_211; // @[L1ICache.scala 72:22]
- reg valid_212; // @[L1ICache.scala 72:22]
- reg valid_213; // @[L1ICache.scala 72:22]
- reg valid_214; // @[L1ICache.scala 72:22]
- reg valid_215; // @[L1ICache.scala 72:22]
- reg valid_216; // @[L1ICache.scala 72:22]
- reg valid_217; // @[L1ICache.scala 72:22]
- reg valid_218; // @[L1ICache.scala 72:22]
- reg valid_219; // @[L1ICache.scala 72:22]
- reg valid_220; // @[L1ICache.scala 72:22]
- reg valid_221; // @[L1ICache.scala 72:22]
- reg valid_222; // @[L1ICache.scala 72:22]
- reg valid_223; // @[L1ICache.scala 72:22]
- reg valid_224; // @[L1ICache.scala 72:22]
- reg valid_225; // @[L1ICache.scala 72:22]
- reg valid_226; // @[L1ICache.scala 72:22]
- reg valid_227; // @[L1ICache.scala 72:22]
- reg valid_228; // @[L1ICache.scala 72:22]
- reg valid_229; // @[L1ICache.scala 72:22]
- reg valid_230; // @[L1ICache.scala 72:22]
- reg valid_231; // @[L1ICache.scala 72:22]
- reg valid_232; // @[L1ICache.scala 72:22]
- reg valid_233; // @[L1ICache.scala 72:22]
- reg valid_234; // @[L1ICache.scala 72:22]
- reg valid_235; // @[L1ICache.scala 72:22]
- reg valid_236; // @[L1ICache.scala 72:22]
- reg valid_237; // @[L1ICache.scala 72:22]
- reg valid_238; // @[L1ICache.scala 72:22]
- reg valid_239; // @[L1ICache.scala 72:22]
- reg valid_240; // @[L1ICache.scala 72:22]
- reg valid_241; // @[L1ICache.scala 72:22]
- reg valid_242; // @[L1ICache.scala 72:22]
- reg valid_243; // @[L1ICache.scala 72:22]
- reg valid_244; // @[L1ICache.scala 72:22]
- reg valid_245; // @[L1ICache.scala 72:22]
- reg valid_246; // @[L1ICache.scala 72:22]
- reg valid_247; // @[L1ICache.scala 72:22]
- reg valid_248; // @[L1ICache.scala 72:22]
- reg valid_249; // @[L1ICache.scala 72:22]
- reg valid_250; // @[L1ICache.scala 72:22]
- reg valid_251; // @[L1ICache.scala 72:22]
- reg valid_252; // @[L1ICache.scala 72:22]
- reg valid_253; // @[L1ICache.scala 72:22]
- reg valid_254; // @[L1ICache.scala 72:22]
- reg valid_255; // @[L1ICache.scala 72:22]
- reg [31:0] camaddr_0; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_1; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_2; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_3; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_4; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_5; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_6; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_7; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_8; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_9; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_10; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_11; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_12; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_13; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_14; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_15; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_16; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_17; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_18; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_19; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_20; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_21; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_22; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_23; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_24; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_25; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_26; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_27; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_28; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_29; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_30; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_31; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_32; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_33; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_34; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_35; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_36; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_37; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_38; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_39; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_40; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_41; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_42; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_43; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_44; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_45; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_46; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_47; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_48; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_49; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_50; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_51; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_52; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_53; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_54; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_55; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_56; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_57; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_58; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_59; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_60; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_61; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_62; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_63; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_64; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_65; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_66; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_67; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_68; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_69; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_70; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_71; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_72; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_73; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_74; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_75; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_76; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_77; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_78; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_79; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_80; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_81; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_82; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_83; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_84; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_85; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_86; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_87; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_88; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_89; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_90; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_91; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_92; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_93; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_94; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_95; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_96; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_97; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_98; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_99; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_100; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_101; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_102; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_103; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_104; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_105; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_106; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_107; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_108; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_109; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_110; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_111; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_112; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_113; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_114; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_115; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_116; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_117; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_118; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_119; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_120; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_121; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_122; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_123; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_124; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_125; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_126; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_127; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_128; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_129; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_130; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_131; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_132; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_133; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_134; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_135; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_136; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_137; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_138; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_139; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_140; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_141; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_142; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_143; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_144; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_145; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_146; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_147; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_148; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_149; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_150; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_151; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_152; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_153; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_154; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_155; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_156; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_157; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_158; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_159; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_160; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_161; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_162; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_163; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_164; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_165; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_166; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_167; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_168; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_169; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_170; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_171; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_172; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_173; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_174; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_175; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_176; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_177; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_178; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_179; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_180; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_181; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_182; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_183; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_184; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_185; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_186; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_187; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_188; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_189; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_190; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_191; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_192; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_193; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_194; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_195; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_196; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_197; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_198; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_199; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_200; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_201; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_202; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_203; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_204; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_205; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_206; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_207; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_208; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_209; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_210; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_211; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_212; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_213; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_214; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_215; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_216; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_217; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_218; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_219; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_220; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_221; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_222; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_223; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_224; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_225; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_226; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_227; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_228; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_229; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_230; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_231; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_232; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_233; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_234; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_235; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_236; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_237; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_238; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_239; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_240; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_241; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_242; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_243; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_244; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_245; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_246; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_247; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_248; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_249; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_250; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_251; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_252; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_253; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_254; // @[L1ICache.scala 73:20]
- reg [31:0] camaddr_255; // @[L1ICache.scala 73:20]
- reg [1:0] history_0_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_0_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_0_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_0_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_1_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_1_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_1_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_1_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_2_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_2_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_2_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_2_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_3_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_3_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_3_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_3_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_4_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_4_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_4_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_4_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_5_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_5_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_5_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_5_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_6_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_6_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_6_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_6_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_7_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_7_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_7_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_7_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_8_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_8_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_8_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_8_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_9_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_9_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_9_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_9_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_10_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_10_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_10_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_10_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_11_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_11_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_11_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_11_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_12_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_12_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_12_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_12_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_13_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_13_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_13_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_13_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_14_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_14_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_14_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_14_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_15_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_15_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_15_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_15_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_16_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_16_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_16_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_16_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_17_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_17_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_17_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_17_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_18_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_18_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_18_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_18_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_19_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_19_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_19_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_19_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_20_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_20_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_20_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_20_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_21_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_21_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_21_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_21_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_22_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_22_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_22_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_22_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_23_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_23_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_23_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_23_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_24_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_24_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_24_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_24_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_25_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_25_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_25_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_25_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_26_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_26_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_26_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_26_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_27_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_27_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_27_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_27_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_28_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_28_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_28_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_28_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_29_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_29_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_29_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_29_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_30_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_30_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_30_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_30_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_31_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_31_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_31_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_31_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_32_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_32_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_32_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_32_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_33_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_33_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_33_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_33_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_34_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_34_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_34_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_34_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_35_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_35_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_35_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_35_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_36_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_36_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_36_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_36_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_37_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_37_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_37_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_37_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_38_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_38_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_38_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_38_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_39_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_39_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_39_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_39_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_40_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_40_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_40_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_40_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_41_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_41_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_41_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_41_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_42_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_42_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_42_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_42_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_43_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_43_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_43_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_43_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_44_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_44_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_44_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_44_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_45_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_45_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_45_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_45_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_46_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_46_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_46_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_46_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_47_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_47_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_47_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_47_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_48_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_48_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_48_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_48_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_49_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_49_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_49_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_49_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_50_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_50_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_50_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_50_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_51_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_51_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_51_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_51_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_52_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_52_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_52_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_52_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_53_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_53_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_53_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_53_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_54_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_54_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_54_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_54_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_55_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_55_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_55_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_55_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_56_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_56_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_56_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_56_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_57_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_57_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_57_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_57_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_58_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_58_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_58_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_58_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_59_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_59_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_59_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_59_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_60_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_60_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_60_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_60_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_61_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_61_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_61_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_61_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_62_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_62_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_62_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_62_3; // @[L1ICache.scala 76:20]
- reg [1:0] history_63_0; // @[L1ICache.scala 76:20]
- reg [1:0] history_63_1; // @[L1ICache.scala 76:20]
- reg [1:0] history_63_2; // @[L1ICache.scala 76:20]
- reg [1:0] history_63_3; // @[L1ICache.scala 76:20]
- wire setMatch_1 = io_ibus_addr[10:5] == 6'h0; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_127 = setMatch_1 ? camaddr_1 : 32'h0; // @[Library.scala 22:8]
- wire setMatch_5 = io_ibus_addr[10:5] == 6'h1; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_129 = setMatch_5 ? camaddr_5 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_130 = _ca_T_127 | _ca_T_129; // @[L1ICache.scala 89:36]
- wire setMatch_9 = io_ibus_addr[10:5] == 6'h2; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_131 = setMatch_9 ? camaddr_9 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_132 = _ca_T_130 | _ca_T_131; // @[L1ICache.scala 89:36]
- wire setMatch_13 = io_ibus_addr[10:5] == 6'h3; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_133 = setMatch_13 ? camaddr_13 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_134 = _ca_T_132 | _ca_T_133; // @[L1ICache.scala 89:36]
- wire setMatch_17 = io_ibus_addr[10:5] == 6'h4; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_135 = setMatch_17 ? camaddr_17 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_136 = _ca_T_134 | _ca_T_135; // @[L1ICache.scala 89:36]
- wire setMatch_21 = io_ibus_addr[10:5] == 6'h5; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_137 = setMatch_21 ? camaddr_21 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_138 = _ca_T_136 | _ca_T_137; // @[L1ICache.scala 89:36]
- wire setMatch_25 = io_ibus_addr[10:5] == 6'h6; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_139 = setMatch_25 ? camaddr_25 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_140 = _ca_T_138 | _ca_T_139; // @[L1ICache.scala 89:36]
- wire setMatch_29 = io_ibus_addr[10:5] == 6'h7; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_141 = setMatch_29 ? camaddr_29 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_142 = _ca_T_140 | _ca_T_141; // @[L1ICache.scala 89:36]
- wire setMatch_33 = io_ibus_addr[10:5] == 6'h8; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_143 = setMatch_33 ? camaddr_33 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_144 = _ca_T_142 | _ca_T_143; // @[L1ICache.scala 89:36]
- wire setMatch_37 = io_ibus_addr[10:5] == 6'h9; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_145 = setMatch_37 ? camaddr_37 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_146 = _ca_T_144 | _ca_T_145; // @[L1ICache.scala 89:36]
- wire setMatch_41 = io_ibus_addr[10:5] == 6'ha; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_147 = setMatch_41 ? camaddr_41 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_148 = _ca_T_146 | _ca_T_147; // @[L1ICache.scala 89:36]
- wire setMatch_45 = io_ibus_addr[10:5] == 6'hb; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_149 = setMatch_45 ? camaddr_45 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_150 = _ca_T_148 | _ca_T_149; // @[L1ICache.scala 89:36]
- wire setMatch_49 = io_ibus_addr[10:5] == 6'hc; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_151 = setMatch_49 ? camaddr_49 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_152 = _ca_T_150 | _ca_T_151; // @[L1ICache.scala 89:36]
- wire setMatch_53 = io_ibus_addr[10:5] == 6'hd; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_153 = setMatch_53 ? camaddr_53 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_154 = _ca_T_152 | _ca_T_153; // @[L1ICache.scala 89:36]
- wire setMatch_57 = io_ibus_addr[10:5] == 6'he; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_155 = setMatch_57 ? camaddr_57 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_156 = _ca_T_154 | _ca_T_155; // @[L1ICache.scala 89:36]
- wire setMatch_61 = io_ibus_addr[10:5] == 6'hf; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_157 = setMatch_61 ? camaddr_61 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_158 = _ca_T_156 | _ca_T_157; // @[L1ICache.scala 89:36]
- wire setMatch_65 = io_ibus_addr[10:5] == 6'h10; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_159 = setMatch_65 ? camaddr_65 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_160 = _ca_T_158 | _ca_T_159; // @[L1ICache.scala 89:36]
- wire setMatch_69 = io_ibus_addr[10:5] == 6'h11; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_161 = setMatch_69 ? camaddr_69 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_162 = _ca_T_160 | _ca_T_161; // @[L1ICache.scala 89:36]
- wire setMatch_73 = io_ibus_addr[10:5] == 6'h12; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_163 = setMatch_73 ? camaddr_73 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_164 = _ca_T_162 | _ca_T_163; // @[L1ICache.scala 89:36]
- wire setMatch_77 = io_ibus_addr[10:5] == 6'h13; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_165 = setMatch_77 ? camaddr_77 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_166 = _ca_T_164 | _ca_T_165; // @[L1ICache.scala 89:36]
- wire setMatch_81 = io_ibus_addr[10:5] == 6'h14; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_167 = setMatch_81 ? camaddr_81 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_168 = _ca_T_166 | _ca_T_167; // @[L1ICache.scala 89:36]
- wire setMatch_85 = io_ibus_addr[10:5] == 6'h15; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_169 = setMatch_85 ? camaddr_85 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_170 = _ca_T_168 | _ca_T_169; // @[L1ICache.scala 89:36]
- wire setMatch_89 = io_ibus_addr[10:5] == 6'h16; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_171 = setMatch_89 ? camaddr_89 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_172 = _ca_T_170 | _ca_T_171; // @[L1ICache.scala 89:36]
- wire setMatch_93 = io_ibus_addr[10:5] == 6'h17; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_173 = setMatch_93 ? camaddr_93 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_174 = _ca_T_172 | _ca_T_173; // @[L1ICache.scala 89:36]
- wire setMatch_97 = io_ibus_addr[10:5] == 6'h18; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_175 = setMatch_97 ? camaddr_97 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_176 = _ca_T_174 | _ca_T_175; // @[L1ICache.scala 89:36]
- wire setMatch_101 = io_ibus_addr[10:5] == 6'h19; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_177 = setMatch_101 ? camaddr_101 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_178 = _ca_T_176 | _ca_T_177; // @[L1ICache.scala 89:36]
- wire setMatch_105 = io_ibus_addr[10:5] == 6'h1a; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_179 = setMatch_105 ? camaddr_105 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_180 = _ca_T_178 | _ca_T_179; // @[L1ICache.scala 89:36]
- wire setMatch_109 = io_ibus_addr[10:5] == 6'h1b; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_181 = setMatch_109 ? camaddr_109 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_182 = _ca_T_180 | _ca_T_181; // @[L1ICache.scala 89:36]
- wire setMatch_113 = io_ibus_addr[10:5] == 6'h1c; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_183 = setMatch_113 ? camaddr_113 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_184 = _ca_T_182 | _ca_T_183; // @[L1ICache.scala 89:36]
- wire setMatch_117 = io_ibus_addr[10:5] == 6'h1d; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_185 = setMatch_117 ? camaddr_117 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_186 = _ca_T_184 | _ca_T_185; // @[L1ICache.scala 89:36]
- wire setMatch_121 = io_ibus_addr[10:5] == 6'h1e; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_187 = setMatch_121 ? camaddr_121 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_188 = _ca_T_186 | _ca_T_187; // @[L1ICache.scala 89:36]
- wire setMatch_125 = io_ibus_addr[10:5] == 6'h1f; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_189 = setMatch_125 ? camaddr_125 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_190 = _ca_T_188 | _ca_T_189; // @[L1ICache.scala 89:36]
- wire setMatch_129 = io_ibus_addr[10:5] == 6'h20; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_191 = setMatch_129 ? camaddr_129 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_192 = _ca_T_190 | _ca_T_191; // @[L1ICache.scala 89:36]
- wire setMatch_133 = io_ibus_addr[10:5] == 6'h21; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_193 = setMatch_133 ? camaddr_133 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_194 = _ca_T_192 | _ca_T_193; // @[L1ICache.scala 89:36]
- wire setMatch_137 = io_ibus_addr[10:5] == 6'h22; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_195 = setMatch_137 ? camaddr_137 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_196 = _ca_T_194 | _ca_T_195; // @[L1ICache.scala 89:36]
- wire setMatch_141 = io_ibus_addr[10:5] == 6'h23; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_197 = setMatch_141 ? camaddr_141 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_198 = _ca_T_196 | _ca_T_197; // @[L1ICache.scala 89:36]
- wire setMatch_145 = io_ibus_addr[10:5] == 6'h24; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_199 = setMatch_145 ? camaddr_145 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_200 = _ca_T_198 | _ca_T_199; // @[L1ICache.scala 89:36]
- wire setMatch_149 = io_ibus_addr[10:5] == 6'h25; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_201 = setMatch_149 ? camaddr_149 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_202 = _ca_T_200 | _ca_T_201; // @[L1ICache.scala 89:36]
- wire setMatch_153 = io_ibus_addr[10:5] == 6'h26; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_203 = setMatch_153 ? camaddr_153 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_204 = _ca_T_202 | _ca_T_203; // @[L1ICache.scala 89:36]
- wire setMatch_157 = io_ibus_addr[10:5] == 6'h27; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_205 = setMatch_157 ? camaddr_157 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_206 = _ca_T_204 | _ca_T_205; // @[L1ICache.scala 89:36]
- wire setMatch_161 = io_ibus_addr[10:5] == 6'h28; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_207 = setMatch_161 ? camaddr_161 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_208 = _ca_T_206 | _ca_T_207; // @[L1ICache.scala 89:36]
- wire setMatch_165 = io_ibus_addr[10:5] == 6'h29; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_209 = setMatch_165 ? camaddr_165 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_210 = _ca_T_208 | _ca_T_209; // @[L1ICache.scala 89:36]
- wire setMatch_169 = io_ibus_addr[10:5] == 6'h2a; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_211 = setMatch_169 ? camaddr_169 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_212 = _ca_T_210 | _ca_T_211; // @[L1ICache.scala 89:36]
- wire setMatch_173 = io_ibus_addr[10:5] == 6'h2b; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_213 = setMatch_173 ? camaddr_173 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_214 = _ca_T_212 | _ca_T_213; // @[L1ICache.scala 89:36]
- wire setMatch_177 = io_ibus_addr[10:5] == 6'h2c; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_215 = setMatch_177 ? camaddr_177 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_216 = _ca_T_214 | _ca_T_215; // @[L1ICache.scala 89:36]
- wire setMatch_181 = io_ibus_addr[10:5] == 6'h2d; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_217 = setMatch_181 ? camaddr_181 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_218 = _ca_T_216 | _ca_T_217; // @[L1ICache.scala 89:36]
- wire setMatch_185 = io_ibus_addr[10:5] == 6'h2e; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_219 = setMatch_185 ? camaddr_185 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_220 = _ca_T_218 | _ca_T_219; // @[L1ICache.scala 89:36]
- wire setMatch_189 = io_ibus_addr[10:5] == 6'h2f; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_221 = setMatch_189 ? camaddr_189 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_222 = _ca_T_220 | _ca_T_221; // @[L1ICache.scala 89:36]
- wire setMatch_193 = io_ibus_addr[10:5] == 6'h30; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_223 = setMatch_193 ? camaddr_193 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_224 = _ca_T_222 | _ca_T_223; // @[L1ICache.scala 89:36]
- wire setMatch_197 = io_ibus_addr[10:5] == 6'h31; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_225 = setMatch_197 ? camaddr_197 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_226 = _ca_T_224 | _ca_T_225; // @[L1ICache.scala 89:36]
- wire setMatch_201 = io_ibus_addr[10:5] == 6'h32; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_227 = setMatch_201 ? camaddr_201 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_228 = _ca_T_226 | _ca_T_227; // @[L1ICache.scala 89:36]
- wire setMatch_205 = io_ibus_addr[10:5] == 6'h33; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_229 = setMatch_205 ? camaddr_205 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_230 = _ca_T_228 | _ca_T_229; // @[L1ICache.scala 89:36]
- wire setMatch_209 = io_ibus_addr[10:5] == 6'h34; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_231 = setMatch_209 ? camaddr_209 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_232 = _ca_T_230 | _ca_T_231; // @[L1ICache.scala 89:36]
- wire setMatch_213 = io_ibus_addr[10:5] == 6'h35; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_233 = setMatch_213 ? camaddr_213 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_234 = _ca_T_232 | _ca_T_233; // @[L1ICache.scala 89:36]
- wire setMatch_217 = io_ibus_addr[10:5] == 6'h36; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_235 = setMatch_217 ? camaddr_217 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_236 = _ca_T_234 | _ca_T_235; // @[L1ICache.scala 89:36]
- wire setMatch_221 = io_ibus_addr[10:5] == 6'h37; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_237 = setMatch_221 ? camaddr_221 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_238 = _ca_T_236 | _ca_T_237; // @[L1ICache.scala 89:36]
- wire setMatch_225 = io_ibus_addr[10:5] == 6'h38; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_239 = setMatch_225 ? camaddr_225 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_240 = _ca_T_238 | _ca_T_239; // @[L1ICache.scala 89:36]
- wire setMatch_229 = io_ibus_addr[10:5] == 6'h39; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_241 = setMatch_229 ? camaddr_229 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_242 = _ca_T_240 | _ca_T_241; // @[L1ICache.scala 89:36]
- wire setMatch_233 = io_ibus_addr[10:5] == 6'h3a; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_243 = setMatch_233 ? camaddr_233 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_244 = _ca_T_242 | _ca_T_243; // @[L1ICache.scala 89:36]
- wire setMatch_237 = io_ibus_addr[10:5] == 6'h3b; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_245 = setMatch_237 ? camaddr_237 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_246 = _ca_T_244 | _ca_T_245; // @[L1ICache.scala 89:36]
- wire setMatch_241 = io_ibus_addr[10:5] == 6'h3c; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_247 = setMatch_241 ? camaddr_241 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_248 = _ca_T_246 | _ca_T_247; // @[L1ICache.scala 89:36]
- wire setMatch_245 = io_ibus_addr[10:5] == 6'h3d; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_249 = setMatch_245 ? camaddr_245 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_250 = _ca_T_248 | _ca_T_249; // @[L1ICache.scala 89:36]
- wire setMatch_249 = io_ibus_addr[10:5] == 6'h3e; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_251 = setMatch_249 ? camaddr_249 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_252 = _ca_T_250 | _ca_T_251; // @[L1ICache.scala 89:36]
- wire setMatch_253 = io_ibus_addr[10:5] == 6'h3f; // @[L1ICache.scala 102:81]
- wire [31:0] _ca_T_253 = setMatch_253 ? camaddr_253 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] ca_1 = _ca_T_252 | _ca_T_253; // @[L1ICache.scala 89:36]
- wire matchAddr_1 = io_ibus_addr[31:11] == ca_1[31:11]; // @[L1ICache.scala 97:50]
- wire matchSlotB_1 = valid_1 & setMatch_1 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire [31:0] _ca_T = setMatch_1 ? camaddr_0 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_2 = setMatch_5 ? camaddr_4 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_3 = _ca_T | _ca_T_2; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_4 = setMatch_9 ? camaddr_8 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_5 = _ca_T_3 | _ca_T_4; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_6 = setMatch_13 ? camaddr_12 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_7 = _ca_T_5 | _ca_T_6; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_8 = setMatch_17 ? camaddr_16 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_9 = _ca_T_7 | _ca_T_8; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_10 = setMatch_21 ? camaddr_20 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_11 = _ca_T_9 | _ca_T_10; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_12 = setMatch_25 ? camaddr_24 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_13 = _ca_T_11 | _ca_T_12; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_14 = setMatch_29 ? camaddr_28 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_15 = _ca_T_13 | _ca_T_14; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_16 = setMatch_33 ? camaddr_32 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_17 = _ca_T_15 | _ca_T_16; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_18 = setMatch_37 ? camaddr_36 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_19 = _ca_T_17 | _ca_T_18; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_20 = setMatch_41 ? camaddr_40 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_21 = _ca_T_19 | _ca_T_20; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_22 = setMatch_45 ? camaddr_44 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_23 = _ca_T_21 | _ca_T_22; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_24 = setMatch_49 ? camaddr_48 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_25 = _ca_T_23 | _ca_T_24; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_26 = setMatch_53 ? camaddr_52 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_27 = _ca_T_25 | _ca_T_26; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_28 = setMatch_57 ? camaddr_56 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_29 = _ca_T_27 | _ca_T_28; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_30 = setMatch_61 ? camaddr_60 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_31 = _ca_T_29 | _ca_T_30; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_32 = setMatch_65 ? camaddr_64 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_33 = _ca_T_31 | _ca_T_32; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_34 = setMatch_69 ? camaddr_68 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_35 = _ca_T_33 | _ca_T_34; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_36 = setMatch_73 ? camaddr_72 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_37 = _ca_T_35 | _ca_T_36; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_38 = setMatch_77 ? camaddr_76 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_39 = _ca_T_37 | _ca_T_38; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_40 = setMatch_81 ? camaddr_80 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_41 = _ca_T_39 | _ca_T_40; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_42 = setMatch_85 ? camaddr_84 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_43 = _ca_T_41 | _ca_T_42; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_44 = setMatch_89 ? camaddr_88 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_45 = _ca_T_43 | _ca_T_44; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_46 = setMatch_93 ? camaddr_92 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_47 = _ca_T_45 | _ca_T_46; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_48 = setMatch_97 ? camaddr_96 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_49 = _ca_T_47 | _ca_T_48; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_50 = setMatch_101 ? camaddr_100 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_51 = _ca_T_49 | _ca_T_50; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_52 = setMatch_105 ? camaddr_104 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_53 = _ca_T_51 | _ca_T_52; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_54 = setMatch_109 ? camaddr_108 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_55 = _ca_T_53 | _ca_T_54; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_56 = setMatch_113 ? camaddr_112 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_57 = _ca_T_55 | _ca_T_56; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_58 = setMatch_117 ? camaddr_116 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_59 = _ca_T_57 | _ca_T_58; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_60 = setMatch_121 ? camaddr_120 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_61 = _ca_T_59 | _ca_T_60; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_62 = setMatch_125 ? camaddr_124 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_63 = _ca_T_61 | _ca_T_62; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_64 = setMatch_129 ? camaddr_128 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_65 = _ca_T_63 | _ca_T_64; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_66 = setMatch_133 ? camaddr_132 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_67 = _ca_T_65 | _ca_T_66; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_68 = setMatch_137 ? camaddr_136 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_69 = _ca_T_67 | _ca_T_68; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_70 = setMatch_141 ? camaddr_140 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_71 = _ca_T_69 | _ca_T_70; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_72 = setMatch_145 ? camaddr_144 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_73 = _ca_T_71 | _ca_T_72; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_74 = setMatch_149 ? camaddr_148 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_75 = _ca_T_73 | _ca_T_74; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_76 = setMatch_153 ? camaddr_152 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_77 = _ca_T_75 | _ca_T_76; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_78 = setMatch_157 ? camaddr_156 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_79 = _ca_T_77 | _ca_T_78; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_80 = setMatch_161 ? camaddr_160 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_81 = _ca_T_79 | _ca_T_80; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_82 = setMatch_165 ? camaddr_164 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_83 = _ca_T_81 | _ca_T_82; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_84 = setMatch_169 ? camaddr_168 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_85 = _ca_T_83 | _ca_T_84; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_86 = setMatch_173 ? camaddr_172 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_87 = _ca_T_85 | _ca_T_86; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_88 = setMatch_177 ? camaddr_176 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_89 = _ca_T_87 | _ca_T_88; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_90 = setMatch_181 ? camaddr_180 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_91 = _ca_T_89 | _ca_T_90; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_92 = setMatch_185 ? camaddr_184 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_93 = _ca_T_91 | _ca_T_92; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_94 = setMatch_189 ? camaddr_188 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_95 = _ca_T_93 | _ca_T_94; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_96 = setMatch_193 ? camaddr_192 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_97 = _ca_T_95 | _ca_T_96; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_98 = setMatch_197 ? camaddr_196 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_99 = _ca_T_97 | _ca_T_98; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_100 = setMatch_201 ? camaddr_200 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_101 = _ca_T_99 | _ca_T_100; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_102 = setMatch_205 ? camaddr_204 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_103 = _ca_T_101 | _ca_T_102; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_104 = setMatch_209 ? camaddr_208 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_105 = _ca_T_103 | _ca_T_104; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_106 = setMatch_213 ? camaddr_212 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_107 = _ca_T_105 | _ca_T_106; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_108 = setMatch_217 ? camaddr_216 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_109 = _ca_T_107 | _ca_T_108; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_110 = setMatch_221 ? camaddr_220 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_111 = _ca_T_109 | _ca_T_110; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_112 = setMatch_225 ? camaddr_224 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_113 = _ca_T_111 | _ca_T_112; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_114 = setMatch_229 ? camaddr_228 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_115 = _ca_T_113 | _ca_T_114; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_116 = setMatch_233 ? camaddr_232 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_117 = _ca_T_115 | _ca_T_116; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_118 = setMatch_237 ? camaddr_236 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_119 = _ca_T_117 | _ca_T_118; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_120 = setMatch_241 ? camaddr_240 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_121 = _ca_T_119 | _ca_T_120; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_122 = setMatch_245 ? camaddr_244 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_123 = _ca_T_121 | _ca_T_122; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_124 = setMatch_249 ? camaddr_248 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_125 = _ca_T_123 | _ca_T_124; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_126 = setMatch_253 ? camaddr_252 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] ca = _ca_T_125 | _ca_T_126; // @[L1ICache.scala 89:36]
- wire matchAddr_0 = io_ibus_addr[31:11] == ca[31:11]; // @[L1ICache.scala 97:50]
- wire matchSlotB_0 = valid_0 & setMatch_1 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire [31:0] _ca_T_381 = setMatch_1 ? camaddr_3 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_383 = setMatch_5 ? camaddr_7 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_384 = _ca_T_381 | _ca_T_383; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_385 = setMatch_9 ? camaddr_11 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_386 = _ca_T_384 | _ca_T_385; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_387 = setMatch_13 ? camaddr_15 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_388 = _ca_T_386 | _ca_T_387; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_389 = setMatch_17 ? camaddr_19 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_390 = _ca_T_388 | _ca_T_389; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_391 = setMatch_21 ? camaddr_23 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_392 = _ca_T_390 | _ca_T_391; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_393 = setMatch_25 ? camaddr_27 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_394 = _ca_T_392 | _ca_T_393; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_395 = setMatch_29 ? camaddr_31 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_396 = _ca_T_394 | _ca_T_395; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_397 = setMatch_33 ? camaddr_35 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_398 = _ca_T_396 | _ca_T_397; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_399 = setMatch_37 ? camaddr_39 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_400 = _ca_T_398 | _ca_T_399; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_401 = setMatch_41 ? camaddr_43 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_402 = _ca_T_400 | _ca_T_401; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_403 = setMatch_45 ? camaddr_47 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_404 = _ca_T_402 | _ca_T_403; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_405 = setMatch_49 ? camaddr_51 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_406 = _ca_T_404 | _ca_T_405; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_407 = setMatch_53 ? camaddr_55 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_408 = _ca_T_406 | _ca_T_407; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_409 = setMatch_57 ? camaddr_59 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_410 = _ca_T_408 | _ca_T_409; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_411 = setMatch_61 ? camaddr_63 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_412 = _ca_T_410 | _ca_T_411; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_413 = setMatch_65 ? camaddr_67 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_414 = _ca_T_412 | _ca_T_413; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_415 = setMatch_69 ? camaddr_71 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_416 = _ca_T_414 | _ca_T_415; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_417 = setMatch_73 ? camaddr_75 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_418 = _ca_T_416 | _ca_T_417; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_419 = setMatch_77 ? camaddr_79 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_420 = _ca_T_418 | _ca_T_419; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_421 = setMatch_81 ? camaddr_83 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_422 = _ca_T_420 | _ca_T_421; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_423 = setMatch_85 ? camaddr_87 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_424 = _ca_T_422 | _ca_T_423; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_425 = setMatch_89 ? camaddr_91 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_426 = _ca_T_424 | _ca_T_425; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_427 = setMatch_93 ? camaddr_95 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_428 = _ca_T_426 | _ca_T_427; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_429 = setMatch_97 ? camaddr_99 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_430 = _ca_T_428 | _ca_T_429; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_431 = setMatch_101 ? camaddr_103 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_432 = _ca_T_430 | _ca_T_431; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_433 = setMatch_105 ? camaddr_107 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_434 = _ca_T_432 | _ca_T_433; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_435 = setMatch_109 ? camaddr_111 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_436 = _ca_T_434 | _ca_T_435; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_437 = setMatch_113 ? camaddr_115 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_438 = _ca_T_436 | _ca_T_437; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_439 = setMatch_117 ? camaddr_119 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_440 = _ca_T_438 | _ca_T_439; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_441 = setMatch_121 ? camaddr_123 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_442 = _ca_T_440 | _ca_T_441; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_443 = setMatch_125 ? camaddr_127 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_444 = _ca_T_442 | _ca_T_443; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_445 = setMatch_129 ? camaddr_131 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_446 = _ca_T_444 | _ca_T_445; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_447 = setMatch_133 ? camaddr_135 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_448 = _ca_T_446 | _ca_T_447; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_449 = setMatch_137 ? camaddr_139 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_450 = _ca_T_448 | _ca_T_449; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_451 = setMatch_141 ? camaddr_143 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_452 = _ca_T_450 | _ca_T_451; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_453 = setMatch_145 ? camaddr_147 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_454 = _ca_T_452 | _ca_T_453; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_455 = setMatch_149 ? camaddr_151 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_456 = _ca_T_454 | _ca_T_455; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_457 = setMatch_153 ? camaddr_155 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_458 = _ca_T_456 | _ca_T_457; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_459 = setMatch_157 ? camaddr_159 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_460 = _ca_T_458 | _ca_T_459; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_461 = setMatch_161 ? camaddr_163 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_462 = _ca_T_460 | _ca_T_461; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_463 = setMatch_165 ? camaddr_167 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_464 = _ca_T_462 | _ca_T_463; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_465 = setMatch_169 ? camaddr_171 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_466 = _ca_T_464 | _ca_T_465; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_467 = setMatch_173 ? camaddr_175 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_468 = _ca_T_466 | _ca_T_467; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_469 = setMatch_177 ? camaddr_179 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_470 = _ca_T_468 | _ca_T_469; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_471 = setMatch_181 ? camaddr_183 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_472 = _ca_T_470 | _ca_T_471; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_473 = setMatch_185 ? camaddr_187 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_474 = _ca_T_472 | _ca_T_473; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_475 = setMatch_189 ? camaddr_191 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_476 = _ca_T_474 | _ca_T_475; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_477 = setMatch_193 ? camaddr_195 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_478 = _ca_T_476 | _ca_T_477; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_479 = setMatch_197 ? camaddr_199 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_480 = _ca_T_478 | _ca_T_479; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_481 = setMatch_201 ? camaddr_203 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_482 = _ca_T_480 | _ca_T_481; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_483 = setMatch_205 ? camaddr_207 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_484 = _ca_T_482 | _ca_T_483; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_485 = setMatch_209 ? camaddr_211 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_486 = _ca_T_484 | _ca_T_485; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_487 = setMatch_213 ? camaddr_215 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_488 = _ca_T_486 | _ca_T_487; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_489 = setMatch_217 ? camaddr_219 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_490 = _ca_T_488 | _ca_T_489; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_491 = setMatch_221 ? camaddr_223 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_492 = _ca_T_490 | _ca_T_491; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_493 = setMatch_225 ? camaddr_227 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_494 = _ca_T_492 | _ca_T_493; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_495 = setMatch_229 ? camaddr_231 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_496 = _ca_T_494 | _ca_T_495; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_497 = setMatch_233 ? camaddr_235 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_498 = _ca_T_496 | _ca_T_497; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_499 = setMatch_237 ? camaddr_239 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_500 = _ca_T_498 | _ca_T_499; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_501 = setMatch_241 ? camaddr_243 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_502 = _ca_T_500 | _ca_T_501; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_503 = setMatch_245 ? camaddr_247 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_504 = _ca_T_502 | _ca_T_503; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_505 = setMatch_249 ? camaddr_251 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_506 = _ca_T_504 | _ca_T_505; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_507 = setMatch_253 ? camaddr_255 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] ca_3 = _ca_T_506 | _ca_T_507; // @[L1ICache.scala 89:36]
- wire matchAddr_3 = io_ibus_addr[31:11] == ca_3[31:11]; // @[L1ICache.scala 97:50]
- wire matchSlotB_3 = valid_3 & setMatch_1 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire [31:0] _ca_T_254 = setMatch_1 ? camaddr_2 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_256 = setMatch_5 ? camaddr_6 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_257 = _ca_T_254 | _ca_T_256; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_258 = setMatch_9 ? camaddr_10 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_259 = _ca_T_257 | _ca_T_258; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_260 = setMatch_13 ? camaddr_14 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_261 = _ca_T_259 | _ca_T_260; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_262 = setMatch_17 ? camaddr_18 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_263 = _ca_T_261 | _ca_T_262; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_264 = setMatch_21 ? camaddr_22 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_265 = _ca_T_263 | _ca_T_264; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_266 = setMatch_25 ? camaddr_26 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_267 = _ca_T_265 | _ca_T_266; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_268 = setMatch_29 ? camaddr_30 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_269 = _ca_T_267 | _ca_T_268; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_270 = setMatch_33 ? camaddr_34 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_271 = _ca_T_269 | _ca_T_270; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_272 = setMatch_37 ? camaddr_38 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_273 = _ca_T_271 | _ca_T_272; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_274 = setMatch_41 ? camaddr_42 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_275 = _ca_T_273 | _ca_T_274; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_276 = setMatch_45 ? camaddr_46 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_277 = _ca_T_275 | _ca_T_276; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_278 = setMatch_49 ? camaddr_50 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_279 = _ca_T_277 | _ca_T_278; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_280 = setMatch_53 ? camaddr_54 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_281 = _ca_T_279 | _ca_T_280; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_282 = setMatch_57 ? camaddr_58 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_283 = _ca_T_281 | _ca_T_282; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_284 = setMatch_61 ? camaddr_62 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_285 = _ca_T_283 | _ca_T_284; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_286 = setMatch_65 ? camaddr_66 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_287 = _ca_T_285 | _ca_T_286; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_288 = setMatch_69 ? camaddr_70 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_289 = _ca_T_287 | _ca_T_288; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_290 = setMatch_73 ? camaddr_74 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_291 = _ca_T_289 | _ca_T_290; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_292 = setMatch_77 ? camaddr_78 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_293 = _ca_T_291 | _ca_T_292; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_294 = setMatch_81 ? camaddr_82 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_295 = _ca_T_293 | _ca_T_294; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_296 = setMatch_85 ? camaddr_86 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_297 = _ca_T_295 | _ca_T_296; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_298 = setMatch_89 ? camaddr_90 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_299 = _ca_T_297 | _ca_T_298; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_300 = setMatch_93 ? camaddr_94 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_301 = _ca_T_299 | _ca_T_300; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_302 = setMatch_97 ? camaddr_98 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_303 = _ca_T_301 | _ca_T_302; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_304 = setMatch_101 ? camaddr_102 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_305 = _ca_T_303 | _ca_T_304; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_306 = setMatch_105 ? camaddr_106 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_307 = _ca_T_305 | _ca_T_306; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_308 = setMatch_109 ? camaddr_110 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_309 = _ca_T_307 | _ca_T_308; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_310 = setMatch_113 ? camaddr_114 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_311 = _ca_T_309 | _ca_T_310; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_312 = setMatch_117 ? camaddr_118 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_313 = _ca_T_311 | _ca_T_312; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_314 = setMatch_121 ? camaddr_122 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_315 = _ca_T_313 | _ca_T_314; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_316 = setMatch_125 ? camaddr_126 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_317 = _ca_T_315 | _ca_T_316; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_318 = setMatch_129 ? camaddr_130 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_319 = _ca_T_317 | _ca_T_318; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_320 = setMatch_133 ? camaddr_134 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_321 = _ca_T_319 | _ca_T_320; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_322 = setMatch_137 ? camaddr_138 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_323 = _ca_T_321 | _ca_T_322; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_324 = setMatch_141 ? camaddr_142 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_325 = _ca_T_323 | _ca_T_324; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_326 = setMatch_145 ? camaddr_146 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_327 = _ca_T_325 | _ca_T_326; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_328 = setMatch_149 ? camaddr_150 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_329 = _ca_T_327 | _ca_T_328; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_330 = setMatch_153 ? camaddr_154 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_331 = _ca_T_329 | _ca_T_330; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_332 = setMatch_157 ? camaddr_158 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_333 = _ca_T_331 | _ca_T_332; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_334 = setMatch_161 ? camaddr_162 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_335 = _ca_T_333 | _ca_T_334; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_336 = setMatch_165 ? camaddr_166 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_337 = _ca_T_335 | _ca_T_336; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_338 = setMatch_169 ? camaddr_170 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_339 = _ca_T_337 | _ca_T_338; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_340 = setMatch_173 ? camaddr_174 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_341 = _ca_T_339 | _ca_T_340; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_342 = setMatch_177 ? camaddr_178 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_343 = _ca_T_341 | _ca_T_342; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_344 = setMatch_181 ? camaddr_182 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_345 = _ca_T_343 | _ca_T_344; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_346 = setMatch_185 ? camaddr_186 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_347 = _ca_T_345 | _ca_T_346; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_348 = setMatch_189 ? camaddr_190 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_349 = _ca_T_347 | _ca_T_348; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_350 = setMatch_193 ? camaddr_194 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_351 = _ca_T_349 | _ca_T_350; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_352 = setMatch_197 ? camaddr_198 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_353 = _ca_T_351 | _ca_T_352; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_354 = setMatch_201 ? camaddr_202 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_355 = _ca_T_353 | _ca_T_354; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_356 = setMatch_205 ? camaddr_206 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_357 = _ca_T_355 | _ca_T_356; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_358 = setMatch_209 ? camaddr_210 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_359 = _ca_T_357 | _ca_T_358; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_360 = setMatch_213 ? camaddr_214 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_361 = _ca_T_359 | _ca_T_360; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_362 = setMatch_217 ? camaddr_218 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_363 = _ca_T_361 | _ca_T_362; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_364 = setMatch_221 ? camaddr_222 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_365 = _ca_T_363 | _ca_T_364; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_366 = setMatch_225 ? camaddr_226 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_367 = _ca_T_365 | _ca_T_366; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_368 = setMatch_229 ? camaddr_230 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_369 = _ca_T_367 | _ca_T_368; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_370 = setMatch_233 ? camaddr_234 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_371 = _ca_T_369 | _ca_T_370; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_372 = setMatch_237 ? camaddr_238 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_373 = _ca_T_371 | _ca_T_372; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_374 = setMatch_241 ? camaddr_242 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_375 = _ca_T_373 | _ca_T_374; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_376 = setMatch_245 ? camaddr_246 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_377 = _ca_T_375 | _ca_T_376; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_378 = setMatch_249 ? camaddr_250 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] _ca_T_379 = _ca_T_377 | _ca_T_378; // @[L1ICache.scala 89:36]
- wire [31:0] _ca_T_380 = setMatch_253 ? camaddr_254 : 32'h0; // @[Library.scala 22:8]
- wire [31:0] ca_2 = _ca_T_379 | _ca_T_380; // @[L1ICache.scala 89:36]
- wire matchAddr_2 = io_ibus_addr[31:11] == ca_2[31:11]; // @[L1ICache.scala 97:50]
- wire matchSlotB_2 = valid_2 & setMatch_1 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_5 = valid_5 & setMatch_5 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_4 = valid_4 & setMatch_5 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_7 = valid_7 & setMatch_5 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_6 = valid_6 & setMatch_5 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_lo_lo_lo_lo_lo = {matchSlotB_7,matchSlotB_6,matchSlotB_5,matchSlotB_4,matchSlotB_3,matchSlotB_2,
- matchSlotB_1,matchSlotB_0}; // @[L1ICache.scala 82:30]
- wire matchSlotB_9 = valid_9 & setMatch_9 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_8 = valid_8 & setMatch_9 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_11 = valid_11 & setMatch_9 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_10 = valid_10 & setMatch_9 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_13 = valid_13 & setMatch_13 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_12 = valid_12 & setMatch_13 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_15 = valid_15 & setMatch_13 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_14 = valid_14 & setMatch_13 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [15:0] matchSlot_lo_lo_lo_lo = {matchSlotB_15,matchSlotB_14,matchSlotB_13,matchSlotB_12,matchSlotB_11,
- matchSlotB_10,matchSlotB_9,matchSlotB_8,matchSlot_lo_lo_lo_lo_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_17 = valid_17 & setMatch_17 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_16 = valid_16 & setMatch_17 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_19 = valid_19 & setMatch_17 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_18 = valid_18 & setMatch_17 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_21 = valid_21 & setMatch_21 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_20 = valid_20 & setMatch_21 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_23 = valid_23 & setMatch_21 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_22 = valid_22 & setMatch_21 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_lo_lo_lo_hi_lo = {matchSlotB_23,matchSlotB_22,matchSlotB_21,matchSlotB_20,matchSlotB_19,
- matchSlotB_18,matchSlotB_17,matchSlotB_16}; // @[L1ICache.scala 82:30]
- wire matchSlotB_25 = valid_25 & setMatch_25 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_24 = valid_24 & setMatch_25 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_27 = valid_27 & setMatch_25 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_26 = valid_26 & setMatch_25 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_29 = valid_29 & setMatch_29 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_28 = valid_28 & setMatch_29 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_31 = valid_31 & setMatch_29 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_30 = valid_30 & setMatch_29 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [31:0] matchSlot_lo_lo_lo = {matchSlotB_31,matchSlotB_30,matchSlotB_29,matchSlotB_28,matchSlotB_27,matchSlotB_26,
- matchSlotB_25,matchSlotB_24,matchSlot_lo_lo_lo_hi_lo,matchSlot_lo_lo_lo_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_33 = valid_33 & setMatch_33 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_32 = valid_32 & setMatch_33 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_35 = valid_35 & setMatch_33 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_34 = valid_34 & setMatch_33 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_37 = valid_37 & setMatch_37 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_36 = valid_36 & setMatch_37 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_39 = valid_39 & setMatch_37 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_38 = valid_38 & setMatch_37 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_lo_lo_hi_lo_lo = {matchSlotB_39,matchSlotB_38,matchSlotB_37,matchSlotB_36,matchSlotB_35,
- matchSlotB_34,matchSlotB_33,matchSlotB_32}; // @[L1ICache.scala 82:30]
- wire matchSlotB_41 = valid_41 & setMatch_41 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_40 = valid_40 & setMatch_41 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_43 = valid_43 & setMatch_41 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_42 = valid_42 & setMatch_41 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_45 = valid_45 & setMatch_45 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_44 = valid_44 & setMatch_45 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_47 = valid_47 & setMatch_45 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_46 = valid_46 & setMatch_45 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [15:0] matchSlot_lo_lo_hi_lo = {matchSlotB_47,matchSlotB_46,matchSlotB_45,matchSlotB_44,matchSlotB_43,
- matchSlotB_42,matchSlotB_41,matchSlotB_40,matchSlot_lo_lo_hi_lo_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_49 = valid_49 & setMatch_49 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_48 = valid_48 & setMatch_49 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_51 = valid_51 & setMatch_49 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_50 = valid_50 & setMatch_49 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_53 = valid_53 & setMatch_53 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_52 = valid_52 & setMatch_53 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_55 = valid_55 & setMatch_53 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_54 = valid_54 & setMatch_53 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_lo_lo_hi_hi_lo = {matchSlotB_55,matchSlotB_54,matchSlotB_53,matchSlotB_52,matchSlotB_51,
- matchSlotB_50,matchSlotB_49,matchSlotB_48}; // @[L1ICache.scala 82:30]
- wire matchSlotB_57 = valid_57 & setMatch_57 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_56 = valid_56 & setMatch_57 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_59 = valid_59 & setMatch_57 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_58 = valid_58 & setMatch_57 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_61 = valid_61 & setMatch_61 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_60 = valid_60 & setMatch_61 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_63 = valid_63 & setMatch_61 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_62 = valid_62 & setMatch_61 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [31:0] matchSlot_lo_lo_hi = {matchSlotB_63,matchSlotB_62,matchSlotB_61,matchSlotB_60,matchSlotB_59,matchSlotB_58,
- matchSlotB_57,matchSlotB_56,matchSlot_lo_lo_hi_hi_lo,matchSlot_lo_lo_hi_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_65 = valid_65 & setMatch_65 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_64 = valid_64 & setMatch_65 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_67 = valid_67 & setMatch_65 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_66 = valid_66 & setMatch_65 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_69 = valid_69 & setMatch_69 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_68 = valid_68 & setMatch_69 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_71 = valid_71 & setMatch_69 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_70 = valid_70 & setMatch_69 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_lo_hi_lo_lo_lo = {matchSlotB_71,matchSlotB_70,matchSlotB_69,matchSlotB_68,matchSlotB_67,
- matchSlotB_66,matchSlotB_65,matchSlotB_64}; // @[L1ICache.scala 82:30]
- wire matchSlotB_73 = valid_73 & setMatch_73 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_72 = valid_72 & setMatch_73 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_75 = valid_75 & setMatch_73 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_74 = valid_74 & setMatch_73 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_77 = valid_77 & setMatch_77 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_76 = valid_76 & setMatch_77 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_79 = valid_79 & setMatch_77 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_78 = valid_78 & setMatch_77 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [15:0] matchSlot_lo_hi_lo_lo = {matchSlotB_79,matchSlotB_78,matchSlotB_77,matchSlotB_76,matchSlotB_75,
- matchSlotB_74,matchSlotB_73,matchSlotB_72,matchSlot_lo_hi_lo_lo_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_81 = valid_81 & setMatch_81 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_80 = valid_80 & setMatch_81 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_83 = valid_83 & setMatch_81 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_82 = valid_82 & setMatch_81 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_85 = valid_85 & setMatch_85 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_84 = valid_84 & setMatch_85 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_87 = valid_87 & setMatch_85 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_86 = valid_86 & setMatch_85 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_lo_hi_lo_hi_lo = {matchSlotB_87,matchSlotB_86,matchSlotB_85,matchSlotB_84,matchSlotB_83,
- matchSlotB_82,matchSlotB_81,matchSlotB_80}; // @[L1ICache.scala 82:30]
- wire matchSlotB_89 = valid_89 & setMatch_89 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_88 = valid_88 & setMatch_89 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_91 = valid_91 & setMatch_89 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_90 = valid_90 & setMatch_89 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_93 = valid_93 & setMatch_93 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_92 = valid_92 & setMatch_93 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_95 = valid_95 & setMatch_93 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_94 = valid_94 & setMatch_93 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [31:0] matchSlot_lo_hi_lo = {matchSlotB_95,matchSlotB_94,matchSlotB_93,matchSlotB_92,matchSlotB_91,matchSlotB_90,
- matchSlotB_89,matchSlotB_88,matchSlot_lo_hi_lo_hi_lo,matchSlot_lo_hi_lo_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_97 = valid_97 & setMatch_97 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_96 = valid_96 & setMatch_97 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_99 = valid_99 & setMatch_97 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_98 = valid_98 & setMatch_97 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_101 = valid_101 & setMatch_101 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_100 = valid_100 & setMatch_101 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_103 = valid_103 & setMatch_101 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_102 = valid_102 & setMatch_101 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_lo_hi_hi_lo_lo = {matchSlotB_103,matchSlotB_102,matchSlotB_101,matchSlotB_100,matchSlotB_99,
- matchSlotB_98,matchSlotB_97,matchSlotB_96}; // @[L1ICache.scala 82:30]
- wire matchSlotB_105 = valid_105 & setMatch_105 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_104 = valid_104 & setMatch_105 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_107 = valid_107 & setMatch_105 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_106 = valid_106 & setMatch_105 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_109 = valid_109 & setMatch_109 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_108 = valid_108 & setMatch_109 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_111 = valid_111 & setMatch_109 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_110 = valid_110 & setMatch_109 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [15:0] matchSlot_lo_hi_hi_lo = {matchSlotB_111,matchSlotB_110,matchSlotB_109,matchSlotB_108,matchSlotB_107,
- matchSlotB_106,matchSlotB_105,matchSlotB_104,matchSlot_lo_hi_hi_lo_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_113 = valid_113 & setMatch_113 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_112 = valid_112 & setMatch_113 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_115 = valid_115 & setMatch_113 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_114 = valid_114 & setMatch_113 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_117 = valid_117 & setMatch_117 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_116 = valid_116 & setMatch_117 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_119 = valid_119 & setMatch_117 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_118 = valid_118 & setMatch_117 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_lo_hi_hi_hi_lo = {matchSlotB_119,matchSlotB_118,matchSlotB_117,matchSlotB_116,matchSlotB_115,
- matchSlotB_114,matchSlotB_113,matchSlotB_112}; // @[L1ICache.scala 82:30]
- wire matchSlotB_121 = valid_121 & setMatch_121 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_120 = valid_120 & setMatch_121 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_123 = valid_123 & setMatch_121 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_122 = valid_122 & setMatch_121 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_125 = valid_125 & setMatch_125 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_124 = valid_124 & setMatch_125 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_127 = valid_127 & setMatch_125 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_126 = valid_126 & setMatch_125 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [31:0] matchSlot_lo_hi_hi = {matchSlotB_127,matchSlotB_126,matchSlotB_125,matchSlotB_124,matchSlotB_123,
- matchSlotB_122,matchSlotB_121,matchSlotB_120,matchSlot_lo_hi_hi_hi_lo,matchSlot_lo_hi_hi_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_129 = valid_129 & setMatch_129 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_128 = valid_128 & setMatch_129 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_131 = valid_131 & setMatch_129 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_130 = valid_130 & setMatch_129 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_133 = valid_133 & setMatch_133 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_132 = valid_132 & setMatch_133 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_135 = valid_135 & setMatch_133 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_134 = valid_134 & setMatch_133 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_hi_lo_lo_lo_lo = {matchSlotB_135,matchSlotB_134,matchSlotB_133,matchSlotB_132,matchSlotB_131,
- matchSlotB_130,matchSlotB_129,matchSlotB_128}; // @[L1ICache.scala 82:30]
- wire matchSlotB_137 = valid_137 & setMatch_137 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_136 = valid_136 & setMatch_137 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_139 = valid_139 & setMatch_137 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_138 = valid_138 & setMatch_137 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_141 = valid_141 & setMatch_141 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_140 = valid_140 & setMatch_141 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_143 = valid_143 & setMatch_141 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_142 = valid_142 & setMatch_141 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [15:0] matchSlot_hi_lo_lo_lo = {matchSlotB_143,matchSlotB_142,matchSlotB_141,matchSlotB_140,matchSlotB_139,
- matchSlotB_138,matchSlotB_137,matchSlotB_136,matchSlot_hi_lo_lo_lo_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_145 = valid_145 & setMatch_145 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_144 = valid_144 & setMatch_145 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_147 = valid_147 & setMatch_145 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_146 = valid_146 & setMatch_145 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_149 = valid_149 & setMatch_149 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_148 = valid_148 & setMatch_149 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_151 = valid_151 & setMatch_149 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_150 = valid_150 & setMatch_149 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_hi_lo_lo_hi_lo = {matchSlotB_151,matchSlotB_150,matchSlotB_149,matchSlotB_148,matchSlotB_147,
- matchSlotB_146,matchSlotB_145,matchSlotB_144}; // @[L1ICache.scala 82:30]
- wire matchSlotB_153 = valid_153 & setMatch_153 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_152 = valid_152 & setMatch_153 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_155 = valid_155 & setMatch_153 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_154 = valid_154 & setMatch_153 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_157 = valid_157 & setMatch_157 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_156 = valid_156 & setMatch_157 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_159 = valid_159 & setMatch_157 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_158 = valid_158 & setMatch_157 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [31:0] matchSlot_hi_lo_lo = {matchSlotB_159,matchSlotB_158,matchSlotB_157,matchSlotB_156,matchSlotB_155,
- matchSlotB_154,matchSlotB_153,matchSlotB_152,matchSlot_hi_lo_lo_hi_lo,matchSlot_hi_lo_lo_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_161 = valid_161 & setMatch_161 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_160 = valid_160 & setMatch_161 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_163 = valid_163 & setMatch_161 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_162 = valid_162 & setMatch_161 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_165 = valid_165 & setMatch_165 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_164 = valid_164 & setMatch_165 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_167 = valid_167 & setMatch_165 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_166 = valid_166 & setMatch_165 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_hi_lo_hi_lo_lo = {matchSlotB_167,matchSlotB_166,matchSlotB_165,matchSlotB_164,matchSlotB_163,
- matchSlotB_162,matchSlotB_161,matchSlotB_160}; // @[L1ICache.scala 82:30]
- wire matchSlotB_169 = valid_169 & setMatch_169 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_168 = valid_168 & setMatch_169 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_171 = valid_171 & setMatch_169 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_170 = valid_170 & setMatch_169 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_173 = valid_173 & setMatch_173 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_172 = valid_172 & setMatch_173 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_175 = valid_175 & setMatch_173 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_174 = valid_174 & setMatch_173 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [15:0] matchSlot_hi_lo_hi_lo = {matchSlotB_175,matchSlotB_174,matchSlotB_173,matchSlotB_172,matchSlotB_171,
- matchSlotB_170,matchSlotB_169,matchSlotB_168,matchSlot_hi_lo_hi_lo_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_177 = valid_177 & setMatch_177 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_176 = valid_176 & setMatch_177 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_179 = valid_179 & setMatch_177 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_178 = valid_178 & setMatch_177 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_181 = valid_181 & setMatch_181 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_180 = valid_180 & setMatch_181 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_183 = valid_183 & setMatch_181 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_182 = valid_182 & setMatch_181 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_hi_lo_hi_hi_lo = {matchSlotB_183,matchSlotB_182,matchSlotB_181,matchSlotB_180,matchSlotB_179,
- matchSlotB_178,matchSlotB_177,matchSlotB_176}; // @[L1ICache.scala 82:30]
- wire matchSlotB_185 = valid_185 & setMatch_185 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_184 = valid_184 & setMatch_185 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_187 = valid_187 & setMatch_185 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_186 = valid_186 & setMatch_185 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_189 = valid_189 & setMatch_189 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_188 = valid_188 & setMatch_189 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_191 = valid_191 & setMatch_189 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_190 = valid_190 & setMatch_189 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [31:0] matchSlot_hi_lo_hi = {matchSlotB_191,matchSlotB_190,matchSlotB_189,matchSlotB_188,matchSlotB_187,
- matchSlotB_186,matchSlotB_185,matchSlotB_184,matchSlot_hi_lo_hi_hi_lo,matchSlot_hi_lo_hi_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_193 = valid_193 & setMatch_193 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_192 = valid_192 & setMatch_193 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_195 = valid_195 & setMatch_193 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_194 = valid_194 & setMatch_193 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_197 = valid_197 & setMatch_197 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_196 = valid_196 & setMatch_197 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_199 = valid_199 & setMatch_197 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_198 = valid_198 & setMatch_197 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_hi_hi_lo_lo_lo = {matchSlotB_199,matchSlotB_198,matchSlotB_197,matchSlotB_196,matchSlotB_195,
- matchSlotB_194,matchSlotB_193,matchSlotB_192}; // @[L1ICache.scala 82:30]
- wire matchSlotB_201 = valid_201 & setMatch_201 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_200 = valid_200 & setMatch_201 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_203 = valid_203 & setMatch_201 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_202 = valid_202 & setMatch_201 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_205 = valid_205 & setMatch_205 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_204 = valid_204 & setMatch_205 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_207 = valid_207 & setMatch_205 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_206 = valid_206 & setMatch_205 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [15:0] matchSlot_hi_hi_lo_lo = {matchSlotB_207,matchSlotB_206,matchSlotB_205,matchSlotB_204,matchSlotB_203,
- matchSlotB_202,matchSlotB_201,matchSlotB_200,matchSlot_hi_hi_lo_lo_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_209 = valid_209 & setMatch_209 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_208 = valid_208 & setMatch_209 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_211 = valid_211 & setMatch_209 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_210 = valid_210 & setMatch_209 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_213 = valid_213 & setMatch_213 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_212 = valid_212 & setMatch_213 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_215 = valid_215 & setMatch_213 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_214 = valid_214 & setMatch_213 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_hi_hi_lo_hi_lo = {matchSlotB_215,matchSlotB_214,matchSlotB_213,matchSlotB_212,matchSlotB_211,
- matchSlotB_210,matchSlotB_209,matchSlotB_208}; // @[L1ICache.scala 82:30]
- wire matchSlotB_217 = valid_217 & setMatch_217 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_216 = valid_216 & setMatch_217 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_219 = valid_219 & setMatch_217 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_218 = valid_218 & setMatch_217 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_221 = valid_221 & setMatch_221 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_220 = valid_220 & setMatch_221 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_223 = valid_223 & setMatch_221 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_222 = valid_222 & setMatch_221 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [31:0] matchSlot_hi_hi_lo = {matchSlotB_223,matchSlotB_222,matchSlotB_221,matchSlotB_220,matchSlotB_219,
- matchSlotB_218,matchSlotB_217,matchSlotB_216,matchSlot_hi_hi_lo_hi_lo,matchSlot_hi_hi_lo_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_225 = valid_225 & setMatch_225 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_224 = valid_224 & setMatch_225 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_227 = valid_227 & setMatch_225 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_226 = valid_226 & setMatch_225 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_229 = valid_229 & setMatch_229 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_228 = valid_228 & setMatch_229 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_231 = valid_231 & setMatch_229 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_230 = valid_230 & setMatch_229 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_hi_hi_hi_lo_lo = {matchSlotB_231,matchSlotB_230,matchSlotB_229,matchSlotB_228,matchSlotB_227,
- matchSlotB_226,matchSlotB_225,matchSlotB_224}; // @[L1ICache.scala 82:30]
- wire matchSlotB_233 = valid_233 & setMatch_233 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_232 = valid_232 & setMatch_233 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_235 = valid_235 & setMatch_233 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_234 = valid_234 & setMatch_233 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_237 = valid_237 & setMatch_237 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_236 = valid_236 & setMatch_237 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_239 = valid_239 & setMatch_237 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_238 = valid_238 & setMatch_237 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [15:0] matchSlot_hi_hi_hi_lo = {matchSlotB_239,matchSlotB_238,matchSlotB_237,matchSlotB_236,matchSlotB_235,
- matchSlotB_234,matchSlotB_233,matchSlotB_232,matchSlot_hi_hi_hi_lo_lo}; // @[L1ICache.scala 82:30]
- wire matchSlotB_241 = valid_241 & setMatch_241 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_240 = valid_240 & setMatch_241 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_243 = valid_243 & setMatch_241 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_242 = valid_242 & setMatch_241 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_245 = valid_245 & setMatch_245 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_244 = valid_244 & setMatch_245 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_247 = valid_247 & setMatch_245 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_246 = valid_246 & setMatch_245 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [7:0] matchSlot_hi_hi_hi_hi_lo = {matchSlotB_247,matchSlotB_246,matchSlotB_245,matchSlotB_244,matchSlotB_243,
- matchSlotB_242,matchSlotB_241,matchSlotB_240}; // @[L1ICache.scala 82:30]
- wire matchSlotB_249 = valid_249 & setMatch_249 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_248 = valid_248 & setMatch_249 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_251 = valid_251 & setMatch_249 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_250 = valid_250 & setMatch_249 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire matchSlotB_253 = valid_253 & setMatch_253 & matchAddr_1; // @[L1ICache.scala 110:46]
- wire matchSlotB_252 = valid_252 & setMatch_253 & matchAddr_0; // @[L1ICache.scala 110:46]
- wire matchSlotB_255 = valid_255 & setMatch_253 & matchAddr_3; // @[L1ICache.scala 110:46]
- wire matchSlotB_254 = valid_254 & setMatch_253 & matchAddr_2; // @[L1ICache.scala 110:46]
- wire [31:0] matchSlot_hi_hi_hi = {matchSlotB_255,matchSlotB_254,matchSlotB_253,matchSlotB_252,matchSlotB_251,
- matchSlotB_250,matchSlotB_249,matchSlotB_248,matchSlot_hi_hi_hi_hi_lo,matchSlot_hi_hi_hi_lo}; // @[L1ICache.scala 82:30]
- wire [255:0] matchSlot = {matchSlot_hi_hi_hi,matchSlot_hi_hi_lo,matchSlot_hi_lo_hi,matchSlot_hi_lo_lo,
- matchSlot_lo_hi_hi,matchSlot_lo_hi_lo,matchSlot_lo_lo_hi,matchSlot_lo_lo_lo}; // @[L1ICache.scala 82:30]
- wire historyMatch_1 = history_0_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_1 = setMatch_1 & historyMatch_1; // @[L1ICache.scala 113:36]
- wire historyMatch = history_0_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_0 = setMatch_1 & historyMatch; // @[L1ICache.scala 113:36]
- wire historyMatch_3 = history_0_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_3 = setMatch_1 & historyMatch_3; // @[L1ICache.scala 113:36]
- wire historyMatch_2 = history_0_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_2 = setMatch_1 & historyMatch_2; // @[L1ICache.scala 113:36]
- wire historyMatch_5 = history_1_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_5 = setMatch_5 & historyMatch_5; // @[L1ICache.scala 113:36]
- wire historyMatch_4 = history_1_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_4 = setMatch_5 & historyMatch_4; // @[L1ICache.scala 113:36]
- wire historyMatch_7 = history_1_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_7 = setMatch_5 & historyMatch_7; // @[L1ICache.scala 113:36]
- wire historyMatch_6 = history_1_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_6 = setMatch_5 & historyMatch_6; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_lo_lo_lo_lo_lo = {replaceSlotB_7,replaceSlotB_6,replaceSlotB_5,replaceSlotB_4,replaceSlotB_3,
- replaceSlotB_2,replaceSlotB_1,replaceSlotB_0}; // @[L1ICache.scala 84:34]
- wire historyMatch_9 = history_2_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_9 = setMatch_9 & historyMatch_9; // @[L1ICache.scala 113:36]
- wire historyMatch_8 = history_2_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_8 = setMatch_9 & historyMatch_8; // @[L1ICache.scala 113:36]
- wire historyMatch_11 = history_2_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_11 = setMatch_9 & historyMatch_11; // @[L1ICache.scala 113:36]
- wire historyMatch_10 = history_2_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_10 = setMatch_9 & historyMatch_10; // @[L1ICache.scala 113:36]
- wire historyMatch_13 = history_3_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_13 = setMatch_13 & historyMatch_13; // @[L1ICache.scala 113:36]
- wire historyMatch_12 = history_3_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_12 = setMatch_13 & historyMatch_12; // @[L1ICache.scala 113:36]
- wire historyMatch_15 = history_3_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_15 = setMatch_13 & historyMatch_15; // @[L1ICache.scala 113:36]
- wire historyMatch_14 = history_3_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_14 = setMatch_13 & historyMatch_14; // @[L1ICache.scala 113:36]
- wire [15:0] replaceSlot_lo_lo_lo_lo = {replaceSlotB_15,replaceSlotB_14,replaceSlotB_13,replaceSlotB_12,replaceSlotB_11
- ,replaceSlotB_10,replaceSlotB_9,replaceSlotB_8,replaceSlot_lo_lo_lo_lo_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_17 = history_4_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_17 = setMatch_17 & historyMatch_17; // @[L1ICache.scala 113:36]
- wire historyMatch_16 = history_4_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_16 = setMatch_17 & historyMatch_16; // @[L1ICache.scala 113:36]
- wire historyMatch_19 = history_4_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_19 = setMatch_17 & historyMatch_19; // @[L1ICache.scala 113:36]
- wire historyMatch_18 = history_4_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_18 = setMatch_17 & historyMatch_18; // @[L1ICache.scala 113:36]
- wire historyMatch_21 = history_5_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_21 = setMatch_21 & historyMatch_21; // @[L1ICache.scala 113:36]
- wire historyMatch_20 = history_5_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_20 = setMatch_21 & historyMatch_20; // @[L1ICache.scala 113:36]
- wire historyMatch_23 = history_5_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_23 = setMatch_21 & historyMatch_23; // @[L1ICache.scala 113:36]
- wire historyMatch_22 = history_5_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_22 = setMatch_21 & historyMatch_22; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_lo_lo_lo_hi_lo = {replaceSlotB_23,replaceSlotB_22,replaceSlotB_21,replaceSlotB_20,
- replaceSlotB_19,replaceSlotB_18,replaceSlotB_17,replaceSlotB_16}; // @[L1ICache.scala 84:34]
- wire historyMatch_25 = history_6_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_25 = setMatch_25 & historyMatch_25; // @[L1ICache.scala 113:36]
- wire historyMatch_24 = history_6_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_24 = setMatch_25 & historyMatch_24; // @[L1ICache.scala 113:36]
- wire historyMatch_27 = history_6_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_27 = setMatch_25 & historyMatch_27; // @[L1ICache.scala 113:36]
- wire historyMatch_26 = history_6_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_26 = setMatch_25 & historyMatch_26; // @[L1ICache.scala 113:36]
- wire historyMatch_29 = history_7_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_29 = setMatch_29 & historyMatch_29; // @[L1ICache.scala 113:36]
- wire historyMatch_28 = history_7_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_28 = setMatch_29 & historyMatch_28; // @[L1ICache.scala 113:36]
- wire historyMatch_31 = history_7_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_31 = setMatch_29 & historyMatch_31; // @[L1ICache.scala 113:36]
- wire historyMatch_30 = history_7_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_30 = setMatch_29 & historyMatch_30; // @[L1ICache.scala 113:36]
- wire [31:0] replaceSlot_lo_lo_lo = {replaceSlotB_31,replaceSlotB_30,replaceSlotB_29,replaceSlotB_28,replaceSlotB_27,
- replaceSlotB_26,replaceSlotB_25,replaceSlotB_24,replaceSlot_lo_lo_lo_hi_lo,replaceSlot_lo_lo_lo_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_33 = history_8_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_33 = setMatch_33 & historyMatch_33; // @[L1ICache.scala 113:36]
- wire historyMatch_32 = history_8_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_32 = setMatch_33 & historyMatch_32; // @[L1ICache.scala 113:36]
- wire historyMatch_35 = history_8_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_35 = setMatch_33 & historyMatch_35; // @[L1ICache.scala 113:36]
- wire historyMatch_34 = history_8_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_34 = setMatch_33 & historyMatch_34; // @[L1ICache.scala 113:36]
- wire historyMatch_37 = history_9_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_37 = setMatch_37 & historyMatch_37; // @[L1ICache.scala 113:36]
- wire historyMatch_36 = history_9_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_36 = setMatch_37 & historyMatch_36; // @[L1ICache.scala 113:36]
- wire historyMatch_39 = history_9_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_39 = setMatch_37 & historyMatch_39; // @[L1ICache.scala 113:36]
- wire historyMatch_38 = history_9_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_38 = setMatch_37 & historyMatch_38; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_lo_lo_hi_lo_lo = {replaceSlotB_39,replaceSlotB_38,replaceSlotB_37,replaceSlotB_36,
- replaceSlotB_35,replaceSlotB_34,replaceSlotB_33,replaceSlotB_32}; // @[L1ICache.scala 84:34]
- wire historyMatch_41 = history_10_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_41 = setMatch_41 & historyMatch_41; // @[L1ICache.scala 113:36]
- wire historyMatch_40 = history_10_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_40 = setMatch_41 & historyMatch_40; // @[L1ICache.scala 113:36]
- wire historyMatch_43 = history_10_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_43 = setMatch_41 & historyMatch_43; // @[L1ICache.scala 113:36]
- wire historyMatch_42 = history_10_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_42 = setMatch_41 & historyMatch_42; // @[L1ICache.scala 113:36]
- wire historyMatch_45 = history_11_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_45 = setMatch_45 & historyMatch_45; // @[L1ICache.scala 113:36]
- wire historyMatch_44 = history_11_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_44 = setMatch_45 & historyMatch_44; // @[L1ICache.scala 113:36]
- wire historyMatch_47 = history_11_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_47 = setMatch_45 & historyMatch_47; // @[L1ICache.scala 113:36]
- wire historyMatch_46 = history_11_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_46 = setMatch_45 & historyMatch_46; // @[L1ICache.scala 113:36]
- wire [15:0] replaceSlot_lo_lo_hi_lo = {replaceSlotB_47,replaceSlotB_46,replaceSlotB_45,replaceSlotB_44,replaceSlotB_43
- ,replaceSlotB_42,replaceSlotB_41,replaceSlotB_40,replaceSlot_lo_lo_hi_lo_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_49 = history_12_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_49 = setMatch_49 & historyMatch_49; // @[L1ICache.scala 113:36]
- wire historyMatch_48 = history_12_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_48 = setMatch_49 & historyMatch_48; // @[L1ICache.scala 113:36]
- wire historyMatch_51 = history_12_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_51 = setMatch_49 & historyMatch_51; // @[L1ICache.scala 113:36]
- wire historyMatch_50 = history_12_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_50 = setMatch_49 & historyMatch_50; // @[L1ICache.scala 113:36]
- wire historyMatch_53 = history_13_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_53 = setMatch_53 & historyMatch_53; // @[L1ICache.scala 113:36]
- wire historyMatch_52 = history_13_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_52 = setMatch_53 & historyMatch_52; // @[L1ICache.scala 113:36]
- wire historyMatch_55 = history_13_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_55 = setMatch_53 & historyMatch_55; // @[L1ICache.scala 113:36]
- wire historyMatch_54 = history_13_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_54 = setMatch_53 & historyMatch_54; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_lo_lo_hi_hi_lo = {replaceSlotB_55,replaceSlotB_54,replaceSlotB_53,replaceSlotB_52,
- replaceSlotB_51,replaceSlotB_50,replaceSlotB_49,replaceSlotB_48}; // @[L1ICache.scala 84:34]
- wire historyMatch_57 = history_14_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_57 = setMatch_57 & historyMatch_57; // @[L1ICache.scala 113:36]
- wire historyMatch_56 = history_14_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_56 = setMatch_57 & historyMatch_56; // @[L1ICache.scala 113:36]
- wire historyMatch_59 = history_14_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_59 = setMatch_57 & historyMatch_59; // @[L1ICache.scala 113:36]
- wire historyMatch_58 = history_14_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_58 = setMatch_57 & historyMatch_58; // @[L1ICache.scala 113:36]
- wire historyMatch_61 = history_15_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_61 = setMatch_61 & historyMatch_61; // @[L1ICache.scala 113:36]
- wire historyMatch_60 = history_15_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_60 = setMatch_61 & historyMatch_60; // @[L1ICache.scala 113:36]
- wire historyMatch_63 = history_15_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_63 = setMatch_61 & historyMatch_63; // @[L1ICache.scala 113:36]
- wire historyMatch_62 = history_15_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_62 = setMatch_61 & historyMatch_62; // @[L1ICache.scala 113:36]
- wire [31:0] replaceSlot_lo_lo_hi = {replaceSlotB_63,replaceSlotB_62,replaceSlotB_61,replaceSlotB_60,replaceSlotB_59,
- replaceSlotB_58,replaceSlotB_57,replaceSlotB_56,replaceSlot_lo_lo_hi_hi_lo,replaceSlot_lo_lo_hi_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_65 = history_16_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_65 = setMatch_65 & historyMatch_65; // @[L1ICache.scala 113:36]
- wire historyMatch_64 = history_16_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_64 = setMatch_65 & historyMatch_64; // @[L1ICache.scala 113:36]
- wire historyMatch_67 = history_16_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_67 = setMatch_65 & historyMatch_67; // @[L1ICache.scala 113:36]
- wire historyMatch_66 = history_16_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_66 = setMatch_65 & historyMatch_66; // @[L1ICache.scala 113:36]
- wire historyMatch_69 = history_17_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_69 = setMatch_69 & historyMatch_69; // @[L1ICache.scala 113:36]
- wire historyMatch_68 = history_17_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_68 = setMatch_69 & historyMatch_68; // @[L1ICache.scala 113:36]
- wire historyMatch_71 = history_17_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_71 = setMatch_69 & historyMatch_71; // @[L1ICache.scala 113:36]
- wire historyMatch_70 = history_17_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_70 = setMatch_69 & historyMatch_70; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_lo_hi_lo_lo_lo = {replaceSlotB_71,replaceSlotB_70,replaceSlotB_69,replaceSlotB_68,
- replaceSlotB_67,replaceSlotB_66,replaceSlotB_65,replaceSlotB_64}; // @[L1ICache.scala 84:34]
- wire historyMatch_73 = history_18_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_73 = setMatch_73 & historyMatch_73; // @[L1ICache.scala 113:36]
- wire historyMatch_72 = history_18_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_72 = setMatch_73 & historyMatch_72; // @[L1ICache.scala 113:36]
- wire historyMatch_75 = history_18_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_75 = setMatch_73 & historyMatch_75; // @[L1ICache.scala 113:36]
- wire historyMatch_74 = history_18_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_74 = setMatch_73 & historyMatch_74; // @[L1ICache.scala 113:36]
- wire historyMatch_77 = history_19_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_77 = setMatch_77 & historyMatch_77; // @[L1ICache.scala 113:36]
- wire historyMatch_76 = history_19_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_76 = setMatch_77 & historyMatch_76; // @[L1ICache.scala 113:36]
- wire historyMatch_79 = history_19_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_79 = setMatch_77 & historyMatch_79; // @[L1ICache.scala 113:36]
- wire historyMatch_78 = history_19_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_78 = setMatch_77 & historyMatch_78; // @[L1ICache.scala 113:36]
- wire [15:0] replaceSlot_lo_hi_lo_lo = {replaceSlotB_79,replaceSlotB_78,replaceSlotB_77,replaceSlotB_76,replaceSlotB_75
- ,replaceSlotB_74,replaceSlotB_73,replaceSlotB_72,replaceSlot_lo_hi_lo_lo_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_81 = history_20_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_81 = setMatch_81 & historyMatch_81; // @[L1ICache.scala 113:36]
- wire historyMatch_80 = history_20_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_80 = setMatch_81 & historyMatch_80; // @[L1ICache.scala 113:36]
- wire historyMatch_83 = history_20_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_83 = setMatch_81 & historyMatch_83; // @[L1ICache.scala 113:36]
- wire historyMatch_82 = history_20_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_82 = setMatch_81 & historyMatch_82; // @[L1ICache.scala 113:36]
- wire historyMatch_85 = history_21_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_85 = setMatch_85 & historyMatch_85; // @[L1ICache.scala 113:36]
- wire historyMatch_84 = history_21_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_84 = setMatch_85 & historyMatch_84; // @[L1ICache.scala 113:36]
- wire historyMatch_87 = history_21_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_87 = setMatch_85 & historyMatch_87; // @[L1ICache.scala 113:36]
- wire historyMatch_86 = history_21_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_86 = setMatch_85 & historyMatch_86; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_lo_hi_lo_hi_lo = {replaceSlotB_87,replaceSlotB_86,replaceSlotB_85,replaceSlotB_84,
- replaceSlotB_83,replaceSlotB_82,replaceSlotB_81,replaceSlotB_80}; // @[L1ICache.scala 84:34]
- wire historyMatch_89 = history_22_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_89 = setMatch_89 & historyMatch_89; // @[L1ICache.scala 113:36]
- wire historyMatch_88 = history_22_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_88 = setMatch_89 & historyMatch_88; // @[L1ICache.scala 113:36]
- wire historyMatch_91 = history_22_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_91 = setMatch_89 & historyMatch_91; // @[L1ICache.scala 113:36]
- wire historyMatch_90 = history_22_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_90 = setMatch_89 & historyMatch_90; // @[L1ICache.scala 113:36]
- wire historyMatch_93 = history_23_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_93 = setMatch_93 & historyMatch_93; // @[L1ICache.scala 113:36]
- wire historyMatch_92 = history_23_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_92 = setMatch_93 & historyMatch_92; // @[L1ICache.scala 113:36]
- wire historyMatch_95 = history_23_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_95 = setMatch_93 & historyMatch_95; // @[L1ICache.scala 113:36]
- wire historyMatch_94 = history_23_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_94 = setMatch_93 & historyMatch_94; // @[L1ICache.scala 113:36]
- wire [31:0] replaceSlot_lo_hi_lo = {replaceSlotB_95,replaceSlotB_94,replaceSlotB_93,replaceSlotB_92,replaceSlotB_91,
- replaceSlotB_90,replaceSlotB_89,replaceSlotB_88,replaceSlot_lo_hi_lo_hi_lo,replaceSlot_lo_hi_lo_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_97 = history_24_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_97 = setMatch_97 & historyMatch_97; // @[L1ICache.scala 113:36]
- wire historyMatch_96 = history_24_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_96 = setMatch_97 & historyMatch_96; // @[L1ICache.scala 113:36]
- wire historyMatch_99 = history_24_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_99 = setMatch_97 & historyMatch_99; // @[L1ICache.scala 113:36]
- wire historyMatch_98 = history_24_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_98 = setMatch_97 & historyMatch_98; // @[L1ICache.scala 113:36]
- wire historyMatch_101 = history_25_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_101 = setMatch_101 & historyMatch_101; // @[L1ICache.scala 113:36]
- wire historyMatch_100 = history_25_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_100 = setMatch_101 & historyMatch_100; // @[L1ICache.scala 113:36]
- wire historyMatch_103 = history_25_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_103 = setMatch_101 & historyMatch_103; // @[L1ICache.scala 113:36]
- wire historyMatch_102 = history_25_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_102 = setMatch_101 & historyMatch_102; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_lo_hi_hi_lo_lo = {replaceSlotB_103,replaceSlotB_102,replaceSlotB_101,replaceSlotB_100,
- replaceSlotB_99,replaceSlotB_98,replaceSlotB_97,replaceSlotB_96}; // @[L1ICache.scala 84:34]
- wire historyMatch_105 = history_26_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_105 = setMatch_105 & historyMatch_105; // @[L1ICache.scala 113:36]
- wire historyMatch_104 = history_26_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_104 = setMatch_105 & historyMatch_104; // @[L1ICache.scala 113:36]
- wire historyMatch_107 = history_26_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_107 = setMatch_105 & historyMatch_107; // @[L1ICache.scala 113:36]
- wire historyMatch_106 = history_26_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_106 = setMatch_105 & historyMatch_106; // @[L1ICache.scala 113:36]
- wire historyMatch_109 = history_27_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_109 = setMatch_109 & historyMatch_109; // @[L1ICache.scala 113:36]
- wire historyMatch_108 = history_27_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_108 = setMatch_109 & historyMatch_108; // @[L1ICache.scala 113:36]
- wire historyMatch_111 = history_27_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_111 = setMatch_109 & historyMatch_111; // @[L1ICache.scala 113:36]
- wire historyMatch_110 = history_27_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_110 = setMatch_109 & historyMatch_110; // @[L1ICache.scala 113:36]
- wire [15:0] replaceSlot_lo_hi_hi_lo = {replaceSlotB_111,replaceSlotB_110,replaceSlotB_109,replaceSlotB_108,
- replaceSlotB_107,replaceSlotB_106,replaceSlotB_105,replaceSlotB_104,replaceSlot_lo_hi_hi_lo_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_113 = history_28_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_113 = setMatch_113 & historyMatch_113; // @[L1ICache.scala 113:36]
- wire historyMatch_112 = history_28_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_112 = setMatch_113 & historyMatch_112; // @[L1ICache.scala 113:36]
- wire historyMatch_115 = history_28_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_115 = setMatch_113 & historyMatch_115; // @[L1ICache.scala 113:36]
- wire historyMatch_114 = history_28_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_114 = setMatch_113 & historyMatch_114; // @[L1ICache.scala 113:36]
- wire historyMatch_117 = history_29_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_117 = setMatch_117 & historyMatch_117; // @[L1ICache.scala 113:36]
- wire historyMatch_116 = history_29_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_116 = setMatch_117 & historyMatch_116; // @[L1ICache.scala 113:36]
- wire historyMatch_119 = history_29_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_119 = setMatch_117 & historyMatch_119; // @[L1ICache.scala 113:36]
- wire historyMatch_118 = history_29_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_118 = setMatch_117 & historyMatch_118; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_lo_hi_hi_hi_lo = {replaceSlotB_119,replaceSlotB_118,replaceSlotB_117,replaceSlotB_116,
- replaceSlotB_115,replaceSlotB_114,replaceSlotB_113,replaceSlotB_112}; // @[L1ICache.scala 84:34]
- wire historyMatch_121 = history_30_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_121 = setMatch_121 & historyMatch_121; // @[L1ICache.scala 113:36]
- wire historyMatch_120 = history_30_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_120 = setMatch_121 & historyMatch_120; // @[L1ICache.scala 113:36]
- wire historyMatch_123 = history_30_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_123 = setMatch_121 & historyMatch_123; // @[L1ICache.scala 113:36]
- wire historyMatch_122 = history_30_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_122 = setMatch_121 & historyMatch_122; // @[L1ICache.scala 113:36]
- wire historyMatch_125 = history_31_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_125 = setMatch_125 & historyMatch_125; // @[L1ICache.scala 113:36]
- wire historyMatch_124 = history_31_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_124 = setMatch_125 & historyMatch_124; // @[L1ICache.scala 113:36]
- wire historyMatch_127 = history_31_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_127 = setMatch_125 & historyMatch_127; // @[L1ICache.scala 113:36]
- wire historyMatch_126 = history_31_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_126 = setMatch_125 & historyMatch_126; // @[L1ICache.scala 113:36]
- wire [31:0] replaceSlot_lo_hi_hi = {replaceSlotB_127,replaceSlotB_126,replaceSlotB_125,replaceSlotB_124,
- replaceSlotB_123,replaceSlotB_122,replaceSlotB_121,replaceSlotB_120,replaceSlot_lo_hi_hi_hi_lo,
- replaceSlot_lo_hi_hi_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_129 = history_32_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_129 = setMatch_129 & historyMatch_129; // @[L1ICache.scala 113:36]
- wire historyMatch_128 = history_32_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_128 = setMatch_129 & historyMatch_128; // @[L1ICache.scala 113:36]
- wire historyMatch_131 = history_32_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_131 = setMatch_129 & historyMatch_131; // @[L1ICache.scala 113:36]
- wire historyMatch_130 = history_32_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_130 = setMatch_129 & historyMatch_130; // @[L1ICache.scala 113:36]
- wire historyMatch_133 = history_33_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_133 = setMatch_133 & historyMatch_133; // @[L1ICache.scala 113:36]
- wire historyMatch_132 = history_33_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_132 = setMatch_133 & historyMatch_132; // @[L1ICache.scala 113:36]
- wire historyMatch_135 = history_33_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_135 = setMatch_133 & historyMatch_135; // @[L1ICache.scala 113:36]
- wire historyMatch_134 = history_33_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_134 = setMatch_133 & historyMatch_134; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_hi_lo_lo_lo_lo = {replaceSlotB_135,replaceSlotB_134,replaceSlotB_133,replaceSlotB_132,
- replaceSlotB_131,replaceSlotB_130,replaceSlotB_129,replaceSlotB_128}; // @[L1ICache.scala 84:34]
- wire historyMatch_137 = history_34_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_137 = setMatch_137 & historyMatch_137; // @[L1ICache.scala 113:36]
- wire historyMatch_136 = history_34_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_136 = setMatch_137 & historyMatch_136; // @[L1ICache.scala 113:36]
- wire historyMatch_139 = history_34_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_139 = setMatch_137 & historyMatch_139; // @[L1ICache.scala 113:36]
- wire historyMatch_138 = history_34_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_138 = setMatch_137 & historyMatch_138; // @[L1ICache.scala 113:36]
- wire historyMatch_141 = history_35_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_141 = setMatch_141 & historyMatch_141; // @[L1ICache.scala 113:36]
- wire historyMatch_140 = history_35_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_140 = setMatch_141 & historyMatch_140; // @[L1ICache.scala 113:36]
- wire historyMatch_143 = history_35_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_143 = setMatch_141 & historyMatch_143; // @[L1ICache.scala 113:36]
- wire historyMatch_142 = history_35_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_142 = setMatch_141 & historyMatch_142; // @[L1ICache.scala 113:36]
- wire [15:0] replaceSlot_hi_lo_lo_lo = {replaceSlotB_143,replaceSlotB_142,replaceSlotB_141,replaceSlotB_140,
- replaceSlotB_139,replaceSlotB_138,replaceSlotB_137,replaceSlotB_136,replaceSlot_hi_lo_lo_lo_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_145 = history_36_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_145 = setMatch_145 & historyMatch_145; // @[L1ICache.scala 113:36]
- wire historyMatch_144 = history_36_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_144 = setMatch_145 & historyMatch_144; // @[L1ICache.scala 113:36]
- wire historyMatch_147 = history_36_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_147 = setMatch_145 & historyMatch_147; // @[L1ICache.scala 113:36]
- wire historyMatch_146 = history_36_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_146 = setMatch_145 & historyMatch_146; // @[L1ICache.scala 113:36]
- wire historyMatch_149 = history_37_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_149 = setMatch_149 & historyMatch_149; // @[L1ICache.scala 113:36]
- wire historyMatch_148 = history_37_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_148 = setMatch_149 & historyMatch_148; // @[L1ICache.scala 113:36]
- wire historyMatch_151 = history_37_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_151 = setMatch_149 & historyMatch_151; // @[L1ICache.scala 113:36]
- wire historyMatch_150 = history_37_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_150 = setMatch_149 & historyMatch_150; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_hi_lo_lo_hi_lo = {replaceSlotB_151,replaceSlotB_150,replaceSlotB_149,replaceSlotB_148,
- replaceSlotB_147,replaceSlotB_146,replaceSlotB_145,replaceSlotB_144}; // @[L1ICache.scala 84:34]
- wire historyMatch_153 = history_38_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_153 = setMatch_153 & historyMatch_153; // @[L1ICache.scala 113:36]
- wire historyMatch_152 = history_38_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_152 = setMatch_153 & historyMatch_152; // @[L1ICache.scala 113:36]
- wire historyMatch_155 = history_38_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_155 = setMatch_153 & historyMatch_155; // @[L1ICache.scala 113:36]
- wire historyMatch_154 = history_38_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_154 = setMatch_153 & historyMatch_154; // @[L1ICache.scala 113:36]
- wire historyMatch_157 = history_39_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_157 = setMatch_157 & historyMatch_157; // @[L1ICache.scala 113:36]
- wire historyMatch_156 = history_39_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_156 = setMatch_157 & historyMatch_156; // @[L1ICache.scala 113:36]
- wire historyMatch_159 = history_39_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_159 = setMatch_157 & historyMatch_159; // @[L1ICache.scala 113:36]
- wire historyMatch_158 = history_39_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_158 = setMatch_157 & historyMatch_158; // @[L1ICache.scala 113:36]
- wire [31:0] replaceSlot_hi_lo_lo = {replaceSlotB_159,replaceSlotB_158,replaceSlotB_157,replaceSlotB_156,
- replaceSlotB_155,replaceSlotB_154,replaceSlotB_153,replaceSlotB_152,replaceSlot_hi_lo_lo_hi_lo,
- replaceSlot_hi_lo_lo_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_161 = history_40_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_161 = setMatch_161 & historyMatch_161; // @[L1ICache.scala 113:36]
- wire historyMatch_160 = history_40_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_160 = setMatch_161 & historyMatch_160; // @[L1ICache.scala 113:36]
- wire historyMatch_163 = history_40_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_163 = setMatch_161 & historyMatch_163; // @[L1ICache.scala 113:36]
- wire historyMatch_162 = history_40_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_162 = setMatch_161 & historyMatch_162; // @[L1ICache.scala 113:36]
- wire historyMatch_165 = history_41_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_165 = setMatch_165 & historyMatch_165; // @[L1ICache.scala 113:36]
- wire historyMatch_164 = history_41_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_164 = setMatch_165 & historyMatch_164; // @[L1ICache.scala 113:36]
- wire historyMatch_167 = history_41_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_167 = setMatch_165 & historyMatch_167; // @[L1ICache.scala 113:36]
- wire historyMatch_166 = history_41_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_166 = setMatch_165 & historyMatch_166; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_hi_lo_hi_lo_lo = {replaceSlotB_167,replaceSlotB_166,replaceSlotB_165,replaceSlotB_164,
- replaceSlotB_163,replaceSlotB_162,replaceSlotB_161,replaceSlotB_160}; // @[L1ICache.scala 84:34]
- wire historyMatch_169 = history_42_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_169 = setMatch_169 & historyMatch_169; // @[L1ICache.scala 113:36]
- wire historyMatch_168 = history_42_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_168 = setMatch_169 & historyMatch_168; // @[L1ICache.scala 113:36]
- wire historyMatch_171 = history_42_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_171 = setMatch_169 & historyMatch_171; // @[L1ICache.scala 113:36]
- wire historyMatch_170 = history_42_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_170 = setMatch_169 & historyMatch_170; // @[L1ICache.scala 113:36]
- wire historyMatch_173 = history_43_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_173 = setMatch_173 & historyMatch_173; // @[L1ICache.scala 113:36]
- wire historyMatch_172 = history_43_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_172 = setMatch_173 & historyMatch_172; // @[L1ICache.scala 113:36]
- wire historyMatch_175 = history_43_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_175 = setMatch_173 & historyMatch_175; // @[L1ICache.scala 113:36]
- wire historyMatch_174 = history_43_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_174 = setMatch_173 & historyMatch_174; // @[L1ICache.scala 113:36]
- wire [15:0] replaceSlot_hi_lo_hi_lo = {replaceSlotB_175,replaceSlotB_174,replaceSlotB_173,replaceSlotB_172,
- replaceSlotB_171,replaceSlotB_170,replaceSlotB_169,replaceSlotB_168,replaceSlot_hi_lo_hi_lo_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_177 = history_44_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_177 = setMatch_177 & historyMatch_177; // @[L1ICache.scala 113:36]
- wire historyMatch_176 = history_44_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_176 = setMatch_177 & historyMatch_176; // @[L1ICache.scala 113:36]
- wire historyMatch_179 = history_44_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_179 = setMatch_177 & historyMatch_179; // @[L1ICache.scala 113:36]
- wire historyMatch_178 = history_44_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_178 = setMatch_177 & historyMatch_178; // @[L1ICache.scala 113:36]
- wire historyMatch_181 = history_45_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_181 = setMatch_181 & historyMatch_181; // @[L1ICache.scala 113:36]
- wire historyMatch_180 = history_45_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_180 = setMatch_181 & historyMatch_180; // @[L1ICache.scala 113:36]
- wire historyMatch_183 = history_45_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_183 = setMatch_181 & historyMatch_183; // @[L1ICache.scala 113:36]
- wire historyMatch_182 = history_45_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_182 = setMatch_181 & historyMatch_182; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_hi_lo_hi_hi_lo = {replaceSlotB_183,replaceSlotB_182,replaceSlotB_181,replaceSlotB_180,
- replaceSlotB_179,replaceSlotB_178,replaceSlotB_177,replaceSlotB_176}; // @[L1ICache.scala 84:34]
- wire historyMatch_185 = history_46_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_185 = setMatch_185 & historyMatch_185; // @[L1ICache.scala 113:36]
- wire historyMatch_184 = history_46_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_184 = setMatch_185 & historyMatch_184; // @[L1ICache.scala 113:36]
- wire historyMatch_187 = history_46_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_187 = setMatch_185 & historyMatch_187; // @[L1ICache.scala 113:36]
- wire historyMatch_186 = history_46_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_186 = setMatch_185 & historyMatch_186; // @[L1ICache.scala 113:36]
- wire historyMatch_189 = history_47_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_189 = setMatch_189 & historyMatch_189; // @[L1ICache.scala 113:36]
- wire historyMatch_188 = history_47_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_188 = setMatch_189 & historyMatch_188; // @[L1ICache.scala 113:36]
- wire historyMatch_191 = history_47_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_191 = setMatch_189 & historyMatch_191; // @[L1ICache.scala 113:36]
- wire historyMatch_190 = history_47_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_190 = setMatch_189 & historyMatch_190; // @[L1ICache.scala 113:36]
- wire [31:0] replaceSlot_hi_lo_hi = {replaceSlotB_191,replaceSlotB_190,replaceSlotB_189,replaceSlotB_188,
- replaceSlotB_187,replaceSlotB_186,replaceSlotB_185,replaceSlotB_184,replaceSlot_hi_lo_hi_hi_lo,
- replaceSlot_hi_lo_hi_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_193 = history_48_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_193 = setMatch_193 & historyMatch_193; // @[L1ICache.scala 113:36]
- wire historyMatch_192 = history_48_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_192 = setMatch_193 & historyMatch_192; // @[L1ICache.scala 113:36]
- wire historyMatch_195 = history_48_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_195 = setMatch_193 & historyMatch_195; // @[L1ICache.scala 113:36]
- wire historyMatch_194 = history_48_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_194 = setMatch_193 & historyMatch_194; // @[L1ICache.scala 113:36]
- wire historyMatch_197 = history_49_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_197 = setMatch_197 & historyMatch_197; // @[L1ICache.scala 113:36]
- wire historyMatch_196 = history_49_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_196 = setMatch_197 & historyMatch_196; // @[L1ICache.scala 113:36]
- wire historyMatch_199 = history_49_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_199 = setMatch_197 & historyMatch_199; // @[L1ICache.scala 113:36]
- wire historyMatch_198 = history_49_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_198 = setMatch_197 & historyMatch_198; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_hi_hi_lo_lo_lo = {replaceSlotB_199,replaceSlotB_198,replaceSlotB_197,replaceSlotB_196,
- replaceSlotB_195,replaceSlotB_194,replaceSlotB_193,replaceSlotB_192}; // @[L1ICache.scala 84:34]
- wire historyMatch_201 = history_50_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_201 = setMatch_201 & historyMatch_201; // @[L1ICache.scala 113:36]
- wire historyMatch_200 = history_50_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_200 = setMatch_201 & historyMatch_200; // @[L1ICache.scala 113:36]
- wire historyMatch_203 = history_50_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_203 = setMatch_201 & historyMatch_203; // @[L1ICache.scala 113:36]
- wire historyMatch_202 = history_50_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_202 = setMatch_201 & historyMatch_202; // @[L1ICache.scala 113:36]
- wire historyMatch_205 = history_51_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_205 = setMatch_205 & historyMatch_205; // @[L1ICache.scala 113:36]
- wire historyMatch_204 = history_51_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_204 = setMatch_205 & historyMatch_204; // @[L1ICache.scala 113:36]
- wire historyMatch_207 = history_51_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_207 = setMatch_205 & historyMatch_207; // @[L1ICache.scala 113:36]
- wire historyMatch_206 = history_51_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_206 = setMatch_205 & historyMatch_206; // @[L1ICache.scala 113:36]
- wire [15:0] replaceSlot_hi_hi_lo_lo = {replaceSlotB_207,replaceSlotB_206,replaceSlotB_205,replaceSlotB_204,
- replaceSlotB_203,replaceSlotB_202,replaceSlotB_201,replaceSlotB_200,replaceSlot_hi_hi_lo_lo_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_209 = history_52_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_209 = setMatch_209 & historyMatch_209; // @[L1ICache.scala 113:36]
- wire historyMatch_208 = history_52_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_208 = setMatch_209 & historyMatch_208; // @[L1ICache.scala 113:36]
- wire historyMatch_211 = history_52_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_211 = setMatch_209 & historyMatch_211; // @[L1ICache.scala 113:36]
- wire historyMatch_210 = history_52_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_210 = setMatch_209 & historyMatch_210; // @[L1ICache.scala 113:36]
- wire historyMatch_213 = history_53_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_213 = setMatch_213 & historyMatch_213; // @[L1ICache.scala 113:36]
- wire historyMatch_212 = history_53_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_212 = setMatch_213 & historyMatch_212; // @[L1ICache.scala 113:36]
- wire historyMatch_215 = history_53_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_215 = setMatch_213 & historyMatch_215; // @[L1ICache.scala 113:36]
- wire historyMatch_214 = history_53_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_214 = setMatch_213 & historyMatch_214; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_hi_hi_lo_hi_lo = {replaceSlotB_215,replaceSlotB_214,replaceSlotB_213,replaceSlotB_212,
- replaceSlotB_211,replaceSlotB_210,replaceSlotB_209,replaceSlotB_208}; // @[L1ICache.scala 84:34]
- wire historyMatch_217 = history_54_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_217 = setMatch_217 & historyMatch_217; // @[L1ICache.scala 113:36]
- wire historyMatch_216 = history_54_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_216 = setMatch_217 & historyMatch_216; // @[L1ICache.scala 113:36]
- wire historyMatch_219 = history_54_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_219 = setMatch_217 & historyMatch_219; // @[L1ICache.scala 113:36]
- wire historyMatch_218 = history_54_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_218 = setMatch_217 & historyMatch_218; // @[L1ICache.scala 113:36]
- wire historyMatch_221 = history_55_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_221 = setMatch_221 & historyMatch_221; // @[L1ICache.scala 113:36]
- wire historyMatch_220 = history_55_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_220 = setMatch_221 & historyMatch_220; // @[L1ICache.scala 113:36]
- wire historyMatch_223 = history_55_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_223 = setMatch_221 & historyMatch_223; // @[L1ICache.scala 113:36]
- wire historyMatch_222 = history_55_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_222 = setMatch_221 & historyMatch_222; // @[L1ICache.scala 113:36]
- wire [31:0] replaceSlot_hi_hi_lo = {replaceSlotB_223,replaceSlotB_222,replaceSlotB_221,replaceSlotB_220,
- replaceSlotB_219,replaceSlotB_218,replaceSlotB_217,replaceSlotB_216,replaceSlot_hi_hi_lo_hi_lo,
- replaceSlot_hi_hi_lo_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_225 = history_56_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_225 = setMatch_225 & historyMatch_225; // @[L1ICache.scala 113:36]
- wire historyMatch_224 = history_56_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_224 = setMatch_225 & historyMatch_224; // @[L1ICache.scala 113:36]
- wire historyMatch_227 = history_56_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_227 = setMatch_225 & historyMatch_227; // @[L1ICache.scala 113:36]
- wire historyMatch_226 = history_56_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_226 = setMatch_225 & historyMatch_226; // @[L1ICache.scala 113:36]
- wire historyMatch_229 = history_57_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_229 = setMatch_229 & historyMatch_229; // @[L1ICache.scala 113:36]
- wire historyMatch_228 = history_57_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_228 = setMatch_229 & historyMatch_228; // @[L1ICache.scala 113:36]
- wire historyMatch_231 = history_57_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_231 = setMatch_229 & historyMatch_231; // @[L1ICache.scala 113:36]
- wire historyMatch_230 = history_57_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_230 = setMatch_229 & historyMatch_230; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_hi_hi_hi_lo_lo = {replaceSlotB_231,replaceSlotB_230,replaceSlotB_229,replaceSlotB_228,
- replaceSlotB_227,replaceSlotB_226,replaceSlotB_225,replaceSlotB_224}; // @[L1ICache.scala 84:34]
- wire historyMatch_233 = history_58_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_233 = setMatch_233 & historyMatch_233; // @[L1ICache.scala 113:36]
- wire historyMatch_232 = history_58_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_232 = setMatch_233 & historyMatch_232; // @[L1ICache.scala 113:36]
- wire historyMatch_235 = history_58_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_235 = setMatch_233 & historyMatch_235; // @[L1ICache.scala 113:36]
- wire historyMatch_234 = history_58_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_234 = setMatch_233 & historyMatch_234; // @[L1ICache.scala 113:36]
- wire historyMatch_237 = history_59_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_237 = setMatch_237 & historyMatch_237; // @[L1ICache.scala 113:36]
- wire historyMatch_236 = history_59_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_236 = setMatch_237 & historyMatch_236; // @[L1ICache.scala 113:36]
- wire historyMatch_239 = history_59_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_239 = setMatch_237 & historyMatch_239; // @[L1ICache.scala 113:36]
- wire historyMatch_238 = history_59_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_238 = setMatch_237 & historyMatch_238; // @[L1ICache.scala 113:36]
- wire [15:0] replaceSlot_hi_hi_hi_lo = {replaceSlotB_239,replaceSlotB_238,replaceSlotB_237,replaceSlotB_236,
- replaceSlotB_235,replaceSlotB_234,replaceSlotB_233,replaceSlotB_232,replaceSlot_hi_hi_hi_lo_lo}; // @[L1ICache.scala 84:34]
- wire historyMatch_241 = history_60_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_241 = setMatch_241 & historyMatch_241; // @[L1ICache.scala 113:36]
- wire historyMatch_240 = history_60_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_240 = setMatch_241 & historyMatch_240; // @[L1ICache.scala 113:36]
- wire historyMatch_243 = history_60_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_243 = setMatch_241 & historyMatch_243; // @[L1ICache.scala 113:36]
- wire historyMatch_242 = history_60_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_242 = setMatch_241 & historyMatch_242; // @[L1ICache.scala 113:36]
- wire historyMatch_245 = history_61_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_245 = setMatch_245 & historyMatch_245; // @[L1ICache.scala 113:36]
- wire historyMatch_244 = history_61_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_244 = setMatch_245 & historyMatch_244; // @[L1ICache.scala 113:36]
- wire historyMatch_247 = history_61_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_247 = setMatch_245 & historyMatch_247; // @[L1ICache.scala 113:36]
- wire historyMatch_246 = history_61_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_246 = setMatch_245 & historyMatch_246; // @[L1ICache.scala 113:36]
- wire [7:0] replaceSlot_hi_hi_hi_hi_lo = {replaceSlotB_247,replaceSlotB_246,replaceSlotB_245,replaceSlotB_244,
- replaceSlotB_243,replaceSlotB_242,replaceSlotB_241,replaceSlotB_240}; // @[L1ICache.scala 84:34]
- wire historyMatch_249 = history_62_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_249 = setMatch_249 & historyMatch_249; // @[L1ICache.scala 113:36]
- wire historyMatch_248 = history_62_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_248 = setMatch_249 & historyMatch_248; // @[L1ICache.scala 113:36]
- wire historyMatch_251 = history_62_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_251 = setMatch_249 & historyMatch_251; // @[L1ICache.scala 113:36]
- wire historyMatch_250 = history_62_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_250 = setMatch_249 & historyMatch_250; // @[L1ICache.scala 113:36]
- wire historyMatch_253 = history_63_1 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_253 = setMatch_253 & historyMatch_253; // @[L1ICache.scala 113:36]
- wire historyMatch_252 = history_63_0 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_252 = setMatch_253 & historyMatch_252; // @[L1ICache.scala 113:36]
- wire historyMatch_255 = history_63_3 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_255 = setMatch_253 & historyMatch_255; // @[L1ICache.scala 113:36]
- wire historyMatch_254 = history_63_2 == 2'h0; // @[L1ICache.scala 112:44]
- wire replaceSlotB_254 = setMatch_253 & historyMatch_254; // @[L1ICache.scala 113:36]
- wire [31:0] replaceSlot_hi_hi_hi = {replaceSlotB_255,replaceSlotB_254,replaceSlotB_253,replaceSlotB_252,
- replaceSlotB_251,replaceSlotB_250,replaceSlotB_249,replaceSlotB_248,replaceSlot_hi_hi_hi_hi_lo,
- replaceSlot_hi_hi_hi_lo}; // @[L1ICache.scala 84:34]
- wire [255:0] replaceSlot = {replaceSlot_hi_hi_hi,replaceSlot_hi_hi_lo,replaceSlot_hi_lo_hi,replaceSlot_hi_lo_lo,
- replaceSlot_lo_hi_hi,replaceSlot_lo_hi_lo,replaceSlot_lo_lo_hi,replaceSlot_lo_lo_lo}; // @[L1ICache.scala 84:34]
- wire [1:0] _T_256 = matchSlot[0] + matchSlot[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_258 = matchSlot[2] + matchSlot[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_260 = _T_256 + _T_258; // @[Bitwise.scala 48:55]
- wire [1:0] _T_262 = matchSlot[4] + matchSlot[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_264 = matchSlot[6] + matchSlot[7]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_266 = _T_262 + _T_264; // @[Bitwise.scala 48:55]
- wire [3:0] _T_268 = _T_260 + _T_266; // @[Bitwise.scala 48:55]
- wire [1:0] _T_270 = matchSlot[8] + matchSlot[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_272 = matchSlot[10] + matchSlot[11]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_274 = _T_270 + _T_272; // @[Bitwise.scala 48:55]
- wire [1:0] _T_276 = matchSlot[12] + matchSlot[13]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_278 = matchSlot[14] + matchSlot[15]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_280 = _T_276 + _T_278; // @[Bitwise.scala 48:55]
- wire [3:0] _T_282 = _T_274 + _T_280; // @[Bitwise.scala 48:55]
- wire [4:0] _T_284 = _T_268 + _T_282; // @[Bitwise.scala 48:55]
- wire [1:0] _T_286 = matchSlot[16] + matchSlot[17]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_288 = matchSlot[18] + matchSlot[19]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_290 = _T_286 + _T_288; // @[Bitwise.scala 48:55]
- wire [1:0] _T_292 = matchSlot[20] + matchSlot[21]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_294 = matchSlot[22] + matchSlot[23]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_296 = _T_292 + _T_294; // @[Bitwise.scala 48:55]
- wire [3:0] _T_298 = _T_290 + _T_296; // @[Bitwise.scala 48:55]
- wire [1:0] _T_300 = matchSlot[24] + matchSlot[25]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_302 = matchSlot[26] + matchSlot[27]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_304 = _T_300 + _T_302; // @[Bitwise.scala 48:55]
- wire [1:0] _T_306 = matchSlot[28] + matchSlot[29]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_308 = matchSlot[30] + matchSlot[31]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_310 = _T_306 + _T_308; // @[Bitwise.scala 48:55]
- wire [3:0] _T_312 = _T_304 + _T_310; // @[Bitwise.scala 48:55]
- wire [4:0] _T_314 = _T_298 + _T_312; // @[Bitwise.scala 48:55]
- wire [5:0] _T_316 = _T_284 + _T_314; // @[Bitwise.scala 48:55]
- wire [1:0] _T_318 = matchSlot[32] + matchSlot[33]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_320 = matchSlot[34] + matchSlot[35]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_322 = _T_318 + _T_320; // @[Bitwise.scala 48:55]
- wire [1:0] _T_324 = matchSlot[36] + matchSlot[37]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_326 = matchSlot[38] + matchSlot[39]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_328 = _T_324 + _T_326; // @[Bitwise.scala 48:55]
- wire [3:0] _T_330 = _T_322 + _T_328; // @[Bitwise.scala 48:55]
- wire [1:0] _T_332 = matchSlot[40] + matchSlot[41]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_334 = matchSlot[42] + matchSlot[43]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_336 = _T_332 + _T_334; // @[Bitwise.scala 48:55]
- wire [1:0] _T_338 = matchSlot[44] + matchSlot[45]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_340 = matchSlot[46] + matchSlot[47]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_342 = _T_338 + _T_340; // @[Bitwise.scala 48:55]
- wire [3:0] _T_344 = _T_336 + _T_342; // @[Bitwise.scala 48:55]
- wire [4:0] _T_346 = _T_330 + _T_344; // @[Bitwise.scala 48:55]
- wire [1:0] _T_348 = matchSlot[48] + matchSlot[49]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_350 = matchSlot[50] + matchSlot[51]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_352 = _T_348 + _T_350; // @[Bitwise.scala 48:55]
- wire [1:0] _T_354 = matchSlot[52] + matchSlot[53]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_356 = matchSlot[54] + matchSlot[55]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_358 = _T_354 + _T_356; // @[Bitwise.scala 48:55]
- wire [3:0] _T_360 = _T_352 + _T_358; // @[Bitwise.scala 48:55]
- wire [1:0] _T_362 = matchSlot[56] + matchSlot[57]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_364 = matchSlot[58] + matchSlot[59]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_366 = _T_362 + _T_364; // @[Bitwise.scala 48:55]
- wire [1:0] _T_368 = matchSlot[60] + matchSlot[61]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_370 = matchSlot[62] + matchSlot[63]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_372 = _T_368 + _T_370; // @[Bitwise.scala 48:55]
- wire [3:0] _T_374 = _T_366 + _T_372; // @[Bitwise.scala 48:55]
- wire [4:0] _T_376 = _T_360 + _T_374; // @[Bitwise.scala 48:55]
- wire [5:0] _T_378 = _T_346 + _T_376; // @[Bitwise.scala 48:55]
- wire [6:0] _T_380 = _T_316 + _T_378; // @[Bitwise.scala 48:55]
- wire [1:0] _T_382 = matchSlot[64] + matchSlot[65]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_384 = matchSlot[66] + matchSlot[67]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_386 = _T_382 + _T_384; // @[Bitwise.scala 48:55]
- wire [1:0] _T_388 = matchSlot[68] + matchSlot[69]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_390 = matchSlot[70] + matchSlot[71]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_392 = _T_388 + _T_390; // @[Bitwise.scala 48:55]
- wire [3:0] _T_394 = _T_386 + _T_392; // @[Bitwise.scala 48:55]
- wire [1:0] _T_396 = matchSlot[72] + matchSlot[73]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_398 = matchSlot[74] + matchSlot[75]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_400 = _T_396 + _T_398; // @[Bitwise.scala 48:55]
- wire [1:0] _T_402 = matchSlot[76] + matchSlot[77]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_404 = matchSlot[78] + matchSlot[79]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_406 = _T_402 + _T_404; // @[Bitwise.scala 48:55]
- wire [3:0] _T_408 = _T_400 + _T_406; // @[Bitwise.scala 48:55]
- wire [4:0] _T_410 = _T_394 + _T_408; // @[Bitwise.scala 48:55]
- wire [1:0] _T_412 = matchSlot[80] + matchSlot[81]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_414 = matchSlot[82] + matchSlot[83]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_416 = _T_412 + _T_414; // @[Bitwise.scala 48:55]
- wire [1:0] _T_418 = matchSlot[84] + matchSlot[85]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_420 = matchSlot[86] + matchSlot[87]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_422 = _T_418 + _T_420; // @[Bitwise.scala 48:55]
- wire [3:0] _T_424 = _T_416 + _T_422; // @[Bitwise.scala 48:55]
- wire [1:0] _T_426 = matchSlot[88] + matchSlot[89]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_428 = matchSlot[90] + matchSlot[91]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_430 = _T_426 + _T_428; // @[Bitwise.scala 48:55]
- wire [1:0] _T_432 = matchSlot[92] + matchSlot[93]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_434 = matchSlot[94] + matchSlot[95]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_436 = _T_432 + _T_434; // @[Bitwise.scala 48:55]
- wire [3:0] _T_438 = _T_430 + _T_436; // @[Bitwise.scala 48:55]
- wire [4:0] _T_440 = _T_424 + _T_438; // @[Bitwise.scala 48:55]
- wire [5:0] _T_442 = _T_410 + _T_440; // @[Bitwise.scala 48:55]
- wire [1:0] _T_444 = matchSlot[96] + matchSlot[97]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_446 = matchSlot[98] + matchSlot[99]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_448 = _T_444 + _T_446; // @[Bitwise.scala 48:55]
- wire [1:0] _T_450 = matchSlot[100] + matchSlot[101]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_452 = matchSlot[102] + matchSlot[103]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_454 = _T_450 + _T_452; // @[Bitwise.scala 48:55]
- wire [3:0] _T_456 = _T_448 + _T_454; // @[Bitwise.scala 48:55]
- wire [1:0] _T_458 = matchSlot[104] + matchSlot[105]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_460 = matchSlot[106] + matchSlot[107]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_462 = _T_458 + _T_460; // @[Bitwise.scala 48:55]
- wire [1:0] _T_464 = matchSlot[108] + matchSlot[109]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_466 = matchSlot[110] + matchSlot[111]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_468 = _T_464 + _T_466; // @[Bitwise.scala 48:55]
- wire [3:0] _T_470 = _T_462 + _T_468; // @[Bitwise.scala 48:55]
- wire [4:0] _T_472 = _T_456 + _T_470; // @[Bitwise.scala 48:55]
- wire [1:0] _T_474 = matchSlot[112] + matchSlot[113]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_476 = matchSlot[114] + matchSlot[115]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_478 = _T_474 + _T_476; // @[Bitwise.scala 48:55]
- wire [1:0] _T_480 = matchSlot[116] + matchSlot[117]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_482 = matchSlot[118] + matchSlot[119]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_484 = _T_480 + _T_482; // @[Bitwise.scala 48:55]
- wire [3:0] _T_486 = _T_478 + _T_484; // @[Bitwise.scala 48:55]
- wire [1:0] _T_488 = matchSlot[120] + matchSlot[121]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_490 = matchSlot[122] + matchSlot[123]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_492 = _T_488 + _T_490; // @[Bitwise.scala 48:55]
- wire [1:0] _T_494 = matchSlot[124] + matchSlot[125]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_496 = matchSlot[126] + matchSlot[127]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_498 = _T_494 + _T_496; // @[Bitwise.scala 48:55]
- wire [3:0] _T_500 = _T_492 + _T_498; // @[Bitwise.scala 48:55]
- wire [4:0] _T_502 = _T_486 + _T_500; // @[Bitwise.scala 48:55]
- wire [5:0] _T_504 = _T_472 + _T_502; // @[Bitwise.scala 48:55]
- wire [6:0] _T_506 = _T_442 + _T_504; // @[Bitwise.scala 48:55]
- wire [7:0] _T_508 = _T_380 + _T_506; // @[Bitwise.scala 48:55]
- wire [1:0] _T_510 = matchSlot[128] + matchSlot[129]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_512 = matchSlot[130] + matchSlot[131]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_514 = _T_510 + _T_512; // @[Bitwise.scala 48:55]
- wire [1:0] _T_516 = matchSlot[132] + matchSlot[133]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_518 = matchSlot[134] + matchSlot[135]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_520 = _T_516 + _T_518; // @[Bitwise.scala 48:55]
- wire [3:0] _T_522 = _T_514 + _T_520; // @[Bitwise.scala 48:55]
- wire [1:0] _T_524 = matchSlot[136] + matchSlot[137]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_526 = matchSlot[138] + matchSlot[139]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_528 = _T_524 + _T_526; // @[Bitwise.scala 48:55]
- wire [1:0] _T_530 = matchSlot[140] + matchSlot[141]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_532 = matchSlot[142] + matchSlot[143]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_534 = _T_530 + _T_532; // @[Bitwise.scala 48:55]
- wire [3:0] _T_536 = _T_528 + _T_534; // @[Bitwise.scala 48:55]
- wire [4:0] _T_538 = _T_522 + _T_536; // @[Bitwise.scala 48:55]
- wire [1:0] _T_540 = matchSlot[144] + matchSlot[145]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_542 = matchSlot[146] + matchSlot[147]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_544 = _T_540 + _T_542; // @[Bitwise.scala 48:55]
- wire [1:0] _T_546 = matchSlot[148] + matchSlot[149]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_548 = matchSlot[150] + matchSlot[151]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_550 = _T_546 + _T_548; // @[Bitwise.scala 48:55]
- wire [3:0] _T_552 = _T_544 + _T_550; // @[Bitwise.scala 48:55]
- wire [1:0] _T_554 = matchSlot[152] + matchSlot[153]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_556 = matchSlot[154] + matchSlot[155]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_558 = _T_554 + _T_556; // @[Bitwise.scala 48:55]
- wire [1:0] _T_560 = matchSlot[156] + matchSlot[157]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_562 = matchSlot[158] + matchSlot[159]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_564 = _T_560 + _T_562; // @[Bitwise.scala 48:55]
- wire [3:0] _T_566 = _T_558 + _T_564; // @[Bitwise.scala 48:55]
- wire [4:0] _T_568 = _T_552 + _T_566; // @[Bitwise.scala 48:55]
- wire [5:0] _T_570 = _T_538 + _T_568; // @[Bitwise.scala 48:55]
- wire [1:0] _T_572 = matchSlot[160] + matchSlot[161]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_574 = matchSlot[162] + matchSlot[163]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_576 = _T_572 + _T_574; // @[Bitwise.scala 48:55]
- wire [1:0] _T_578 = matchSlot[164] + matchSlot[165]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_580 = matchSlot[166] + matchSlot[167]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_582 = _T_578 + _T_580; // @[Bitwise.scala 48:55]
- wire [3:0] _T_584 = _T_576 + _T_582; // @[Bitwise.scala 48:55]
- wire [1:0] _T_586 = matchSlot[168] + matchSlot[169]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_588 = matchSlot[170] + matchSlot[171]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_590 = _T_586 + _T_588; // @[Bitwise.scala 48:55]
- wire [1:0] _T_592 = matchSlot[172] + matchSlot[173]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_594 = matchSlot[174] + matchSlot[175]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_596 = _T_592 + _T_594; // @[Bitwise.scala 48:55]
- wire [3:0] _T_598 = _T_590 + _T_596; // @[Bitwise.scala 48:55]
- wire [4:0] _T_600 = _T_584 + _T_598; // @[Bitwise.scala 48:55]
- wire [1:0] _T_602 = matchSlot[176] + matchSlot[177]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_604 = matchSlot[178] + matchSlot[179]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_606 = _T_602 + _T_604; // @[Bitwise.scala 48:55]
- wire [1:0] _T_608 = matchSlot[180] + matchSlot[181]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_610 = matchSlot[182] + matchSlot[183]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_612 = _T_608 + _T_610; // @[Bitwise.scala 48:55]
- wire [3:0] _T_614 = _T_606 + _T_612; // @[Bitwise.scala 48:55]
- wire [1:0] _T_616 = matchSlot[184] + matchSlot[185]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_618 = matchSlot[186] + matchSlot[187]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_620 = _T_616 + _T_618; // @[Bitwise.scala 48:55]
- wire [1:0] _T_622 = matchSlot[188] + matchSlot[189]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_624 = matchSlot[190] + matchSlot[191]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_626 = _T_622 + _T_624; // @[Bitwise.scala 48:55]
- wire [3:0] _T_628 = _T_620 + _T_626; // @[Bitwise.scala 48:55]
- wire [4:0] _T_630 = _T_614 + _T_628; // @[Bitwise.scala 48:55]
- wire [5:0] _T_632 = _T_600 + _T_630; // @[Bitwise.scala 48:55]
- wire [6:0] _T_634 = _T_570 + _T_632; // @[Bitwise.scala 48:55]
- wire [1:0] _T_636 = matchSlot[192] + matchSlot[193]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_638 = matchSlot[194] + matchSlot[195]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_640 = _T_636 + _T_638; // @[Bitwise.scala 48:55]
- wire [1:0] _T_642 = matchSlot[196] + matchSlot[197]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_644 = matchSlot[198] + matchSlot[199]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_646 = _T_642 + _T_644; // @[Bitwise.scala 48:55]
- wire [3:0] _T_648 = _T_640 + _T_646; // @[Bitwise.scala 48:55]
- wire [1:0] _T_650 = matchSlot[200] + matchSlot[201]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_652 = matchSlot[202] + matchSlot[203]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_654 = _T_650 + _T_652; // @[Bitwise.scala 48:55]
- wire [1:0] _T_656 = matchSlot[204] + matchSlot[205]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_658 = matchSlot[206] + matchSlot[207]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_660 = _T_656 + _T_658; // @[Bitwise.scala 48:55]
- wire [3:0] _T_662 = _T_654 + _T_660; // @[Bitwise.scala 48:55]
- wire [4:0] _T_664 = _T_648 + _T_662; // @[Bitwise.scala 48:55]
- wire [1:0] _T_666 = matchSlot[208] + matchSlot[209]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_668 = matchSlot[210] + matchSlot[211]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_670 = _T_666 + _T_668; // @[Bitwise.scala 48:55]
- wire [1:0] _T_672 = matchSlot[212] + matchSlot[213]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_674 = matchSlot[214] + matchSlot[215]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_676 = _T_672 + _T_674; // @[Bitwise.scala 48:55]
- wire [3:0] _T_678 = _T_670 + _T_676; // @[Bitwise.scala 48:55]
- wire [1:0] _T_680 = matchSlot[216] + matchSlot[217]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_682 = matchSlot[218] + matchSlot[219]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_684 = _T_680 + _T_682; // @[Bitwise.scala 48:55]
- wire [1:0] _T_686 = matchSlot[220] + matchSlot[221]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_688 = matchSlot[222] + matchSlot[223]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_690 = _T_686 + _T_688; // @[Bitwise.scala 48:55]
- wire [3:0] _T_692 = _T_684 + _T_690; // @[Bitwise.scala 48:55]
- wire [4:0] _T_694 = _T_678 + _T_692; // @[Bitwise.scala 48:55]
- wire [5:0] _T_696 = _T_664 + _T_694; // @[Bitwise.scala 48:55]
- wire [1:0] _T_698 = matchSlot[224] + matchSlot[225]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_700 = matchSlot[226] + matchSlot[227]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_702 = _T_698 + _T_700; // @[Bitwise.scala 48:55]
- wire [1:0] _T_704 = matchSlot[228] + matchSlot[229]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_706 = matchSlot[230] + matchSlot[231]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_708 = _T_704 + _T_706; // @[Bitwise.scala 48:55]
- wire [3:0] _T_710 = _T_702 + _T_708; // @[Bitwise.scala 48:55]
- wire [1:0] _T_712 = matchSlot[232] + matchSlot[233]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_714 = matchSlot[234] + matchSlot[235]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_716 = _T_712 + _T_714; // @[Bitwise.scala 48:55]
- wire [1:0] _T_718 = matchSlot[236] + matchSlot[237]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_720 = matchSlot[238] + matchSlot[239]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_722 = _T_718 + _T_720; // @[Bitwise.scala 48:55]
- wire [3:0] _T_724 = _T_716 + _T_722; // @[Bitwise.scala 48:55]
- wire [4:0] _T_726 = _T_710 + _T_724; // @[Bitwise.scala 48:55]
- wire [1:0] _T_728 = matchSlot[240] + matchSlot[241]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_730 = matchSlot[242] + matchSlot[243]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_732 = _T_728 + _T_730; // @[Bitwise.scala 48:55]
- wire [1:0] _T_734 = matchSlot[244] + matchSlot[245]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_736 = matchSlot[246] + matchSlot[247]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_738 = _T_734 + _T_736; // @[Bitwise.scala 48:55]
- wire [3:0] _T_740 = _T_732 + _T_738; // @[Bitwise.scala 48:55]
- wire [1:0] _T_742 = matchSlot[248] + matchSlot[249]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_744 = matchSlot[250] + matchSlot[251]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_746 = _T_742 + _T_744; // @[Bitwise.scala 48:55]
- wire [1:0] _T_748 = matchSlot[252] + matchSlot[253]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_750 = matchSlot[254] + matchSlot[255]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_752 = _T_748 + _T_750; // @[Bitwise.scala 48:55]
- wire [3:0] _T_754 = _T_746 + _T_752; // @[Bitwise.scala 48:55]
- wire [4:0] _T_756 = _T_740 + _T_754; // @[Bitwise.scala 48:55]
- wire [5:0] _T_758 = _T_726 + _T_756; // @[Bitwise.scala 48:55]
- wire [6:0] _T_760 = _T_696 + _T_758; // @[Bitwise.scala 48:55]
- wire [7:0] _T_762 = _T_634 + _T_760; // @[Bitwise.scala 48:55]
- wire [8:0] _T_764 = _T_508 + _T_762; // @[Bitwise.scala 48:55]
- wire _T_768 = ~reset; // @[L1ICache.scala 117:9]
- wire [1:0] _T_1026 = replaceSlot[0] + replaceSlot[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1028 = replaceSlot[2] + replaceSlot[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1030 = _T_1026 + _T_1028; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1032 = replaceSlot[4] + replaceSlot[5]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1034 = replaceSlot[6] + replaceSlot[7]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1036 = _T_1032 + _T_1034; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1038 = _T_1030 + _T_1036; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1040 = replaceSlot[8] + replaceSlot[9]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1042 = replaceSlot[10] + replaceSlot[11]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1044 = _T_1040 + _T_1042; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1046 = replaceSlot[12] + replaceSlot[13]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1048 = replaceSlot[14] + replaceSlot[15]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1050 = _T_1046 + _T_1048; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1052 = _T_1044 + _T_1050; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1054 = _T_1038 + _T_1052; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1056 = replaceSlot[16] + replaceSlot[17]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1058 = replaceSlot[18] + replaceSlot[19]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1060 = _T_1056 + _T_1058; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1062 = replaceSlot[20] + replaceSlot[21]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1064 = replaceSlot[22] + replaceSlot[23]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1066 = _T_1062 + _T_1064; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1068 = _T_1060 + _T_1066; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1070 = replaceSlot[24] + replaceSlot[25]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1072 = replaceSlot[26] + replaceSlot[27]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1074 = _T_1070 + _T_1072; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1076 = replaceSlot[28] + replaceSlot[29]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1078 = replaceSlot[30] + replaceSlot[31]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1080 = _T_1076 + _T_1078; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1082 = _T_1074 + _T_1080; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1084 = _T_1068 + _T_1082; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1086 = _T_1054 + _T_1084; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1088 = replaceSlot[32] + replaceSlot[33]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1090 = replaceSlot[34] + replaceSlot[35]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1092 = _T_1088 + _T_1090; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1094 = replaceSlot[36] + replaceSlot[37]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1096 = replaceSlot[38] + replaceSlot[39]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1098 = _T_1094 + _T_1096; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1100 = _T_1092 + _T_1098; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1102 = replaceSlot[40] + replaceSlot[41]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1104 = replaceSlot[42] + replaceSlot[43]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1106 = _T_1102 + _T_1104; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1108 = replaceSlot[44] + replaceSlot[45]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1110 = replaceSlot[46] + replaceSlot[47]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1112 = _T_1108 + _T_1110; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1114 = _T_1106 + _T_1112; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1116 = _T_1100 + _T_1114; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1118 = replaceSlot[48] + replaceSlot[49]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1120 = replaceSlot[50] + replaceSlot[51]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1122 = _T_1118 + _T_1120; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1124 = replaceSlot[52] + replaceSlot[53]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1126 = replaceSlot[54] + replaceSlot[55]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1128 = _T_1124 + _T_1126; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1130 = _T_1122 + _T_1128; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1132 = replaceSlot[56] + replaceSlot[57]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1134 = replaceSlot[58] + replaceSlot[59]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1136 = _T_1132 + _T_1134; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1138 = replaceSlot[60] + replaceSlot[61]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1140 = replaceSlot[62] + replaceSlot[63]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1142 = _T_1138 + _T_1140; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1144 = _T_1136 + _T_1142; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1146 = _T_1130 + _T_1144; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1148 = _T_1116 + _T_1146; // @[Bitwise.scala 48:55]
- wire [6:0] _T_1150 = _T_1086 + _T_1148; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1152 = replaceSlot[64] + replaceSlot[65]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1154 = replaceSlot[66] + replaceSlot[67]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1156 = _T_1152 + _T_1154; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1158 = replaceSlot[68] + replaceSlot[69]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1160 = replaceSlot[70] + replaceSlot[71]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1162 = _T_1158 + _T_1160; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1164 = _T_1156 + _T_1162; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1166 = replaceSlot[72] + replaceSlot[73]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1168 = replaceSlot[74] + replaceSlot[75]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1170 = _T_1166 + _T_1168; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1172 = replaceSlot[76] + replaceSlot[77]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1174 = replaceSlot[78] + replaceSlot[79]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1176 = _T_1172 + _T_1174; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1178 = _T_1170 + _T_1176; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1180 = _T_1164 + _T_1178; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1182 = replaceSlot[80] + replaceSlot[81]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1184 = replaceSlot[82] + replaceSlot[83]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1186 = _T_1182 + _T_1184; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1188 = replaceSlot[84] + replaceSlot[85]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1190 = replaceSlot[86] + replaceSlot[87]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1192 = _T_1188 + _T_1190; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1194 = _T_1186 + _T_1192; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1196 = replaceSlot[88] + replaceSlot[89]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1198 = replaceSlot[90] + replaceSlot[91]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1200 = _T_1196 + _T_1198; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1202 = replaceSlot[92] + replaceSlot[93]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1204 = replaceSlot[94] + replaceSlot[95]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1206 = _T_1202 + _T_1204; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1208 = _T_1200 + _T_1206; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1210 = _T_1194 + _T_1208; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1212 = _T_1180 + _T_1210; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1214 = replaceSlot[96] + replaceSlot[97]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1216 = replaceSlot[98] + replaceSlot[99]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1218 = _T_1214 + _T_1216; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1220 = replaceSlot[100] + replaceSlot[101]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1222 = replaceSlot[102] + replaceSlot[103]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1224 = _T_1220 + _T_1222; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1226 = _T_1218 + _T_1224; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1228 = replaceSlot[104] + replaceSlot[105]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1230 = replaceSlot[106] + replaceSlot[107]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1232 = _T_1228 + _T_1230; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1234 = replaceSlot[108] + replaceSlot[109]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1236 = replaceSlot[110] + replaceSlot[111]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1238 = _T_1234 + _T_1236; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1240 = _T_1232 + _T_1238; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1242 = _T_1226 + _T_1240; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1244 = replaceSlot[112] + replaceSlot[113]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1246 = replaceSlot[114] + replaceSlot[115]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1248 = _T_1244 + _T_1246; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1250 = replaceSlot[116] + replaceSlot[117]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1252 = replaceSlot[118] + replaceSlot[119]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1254 = _T_1250 + _T_1252; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1256 = _T_1248 + _T_1254; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1258 = replaceSlot[120] + replaceSlot[121]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1260 = replaceSlot[122] + replaceSlot[123]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1262 = _T_1258 + _T_1260; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1264 = replaceSlot[124] + replaceSlot[125]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1266 = replaceSlot[126] + replaceSlot[127]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1268 = _T_1264 + _T_1266; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1270 = _T_1262 + _T_1268; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1272 = _T_1256 + _T_1270; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1274 = _T_1242 + _T_1272; // @[Bitwise.scala 48:55]
- wire [6:0] _T_1276 = _T_1212 + _T_1274; // @[Bitwise.scala 48:55]
- wire [7:0] _T_1278 = _T_1150 + _T_1276; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1280 = replaceSlot[128] + replaceSlot[129]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1282 = replaceSlot[130] + replaceSlot[131]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1284 = _T_1280 + _T_1282; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1286 = replaceSlot[132] + replaceSlot[133]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1288 = replaceSlot[134] + replaceSlot[135]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1290 = _T_1286 + _T_1288; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1292 = _T_1284 + _T_1290; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1294 = replaceSlot[136] + replaceSlot[137]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1296 = replaceSlot[138] + replaceSlot[139]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1298 = _T_1294 + _T_1296; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1300 = replaceSlot[140] + replaceSlot[141]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1302 = replaceSlot[142] + replaceSlot[143]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1304 = _T_1300 + _T_1302; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1306 = _T_1298 + _T_1304; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1308 = _T_1292 + _T_1306; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1310 = replaceSlot[144] + replaceSlot[145]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1312 = replaceSlot[146] + replaceSlot[147]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1314 = _T_1310 + _T_1312; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1316 = replaceSlot[148] + replaceSlot[149]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1318 = replaceSlot[150] + replaceSlot[151]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1320 = _T_1316 + _T_1318; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1322 = _T_1314 + _T_1320; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1324 = replaceSlot[152] + replaceSlot[153]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1326 = replaceSlot[154] + replaceSlot[155]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1328 = _T_1324 + _T_1326; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1330 = replaceSlot[156] + replaceSlot[157]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1332 = replaceSlot[158] + replaceSlot[159]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1334 = _T_1330 + _T_1332; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1336 = _T_1328 + _T_1334; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1338 = _T_1322 + _T_1336; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1340 = _T_1308 + _T_1338; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1342 = replaceSlot[160] + replaceSlot[161]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1344 = replaceSlot[162] + replaceSlot[163]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1346 = _T_1342 + _T_1344; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1348 = replaceSlot[164] + replaceSlot[165]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1350 = replaceSlot[166] + replaceSlot[167]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1352 = _T_1348 + _T_1350; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1354 = _T_1346 + _T_1352; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1356 = replaceSlot[168] + replaceSlot[169]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1358 = replaceSlot[170] + replaceSlot[171]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1360 = _T_1356 + _T_1358; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1362 = replaceSlot[172] + replaceSlot[173]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1364 = replaceSlot[174] + replaceSlot[175]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1366 = _T_1362 + _T_1364; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1368 = _T_1360 + _T_1366; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1370 = _T_1354 + _T_1368; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1372 = replaceSlot[176] + replaceSlot[177]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1374 = replaceSlot[178] + replaceSlot[179]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1376 = _T_1372 + _T_1374; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1378 = replaceSlot[180] + replaceSlot[181]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1380 = replaceSlot[182] + replaceSlot[183]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1382 = _T_1378 + _T_1380; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1384 = _T_1376 + _T_1382; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1386 = replaceSlot[184] + replaceSlot[185]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1388 = replaceSlot[186] + replaceSlot[187]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1390 = _T_1386 + _T_1388; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1392 = replaceSlot[188] + replaceSlot[189]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1394 = replaceSlot[190] + replaceSlot[191]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1396 = _T_1392 + _T_1394; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1398 = _T_1390 + _T_1396; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1400 = _T_1384 + _T_1398; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1402 = _T_1370 + _T_1400; // @[Bitwise.scala 48:55]
- wire [6:0] _T_1404 = _T_1340 + _T_1402; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1406 = replaceSlot[192] + replaceSlot[193]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1408 = replaceSlot[194] + replaceSlot[195]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1410 = _T_1406 + _T_1408; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1412 = replaceSlot[196] + replaceSlot[197]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1414 = replaceSlot[198] + replaceSlot[199]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1416 = _T_1412 + _T_1414; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1418 = _T_1410 + _T_1416; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1420 = replaceSlot[200] + replaceSlot[201]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1422 = replaceSlot[202] + replaceSlot[203]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1424 = _T_1420 + _T_1422; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1426 = replaceSlot[204] + replaceSlot[205]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1428 = replaceSlot[206] + replaceSlot[207]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1430 = _T_1426 + _T_1428; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1432 = _T_1424 + _T_1430; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1434 = _T_1418 + _T_1432; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1436 = replaceSlot[208] + replaceSlot[209]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1438 = replaceSlot[210] + replaceSlot[211]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1440 = _T_1436 + _T_1438; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1442 = replaceSlot[212] + replaceSlot[213]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1444 = replaceSlot[214] + replaceSlot[215]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1446 = _T_1442 + _T_1444; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1448 = _T_1440 + _T_1446; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1450 = replaceSlot[216] + replaceSlot[217]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1452 = replaceSlot[218] + replaceSlot[219]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1454 = _T_1450 + _T_1452; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1456 = replaceSlot[220] + replaceSlot[221]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1458 = replaceSlot[222] + replaceSlot[223]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1460 = _T_1456 + _T_1458; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1462 = _T_1454 + _T_1460; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1464 = _T_1448 + _T_1462; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1466 = _T_1434 + _T_1464; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1468 = replaceSlot[224] + replaceSlot[225]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1470 = replaceSlot[226] + replaceSlot[227]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1472 = _T_1468 + _T_1470; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1474 = replaceSlot[228] + replaceSlot[229]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1476 = replaceSlot[230] + replaceSlot[231]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1478 = _T_1474 + _T_1476; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1480 = _T_1472 + _T_1478; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1482 = replaceSlot[232] + replaceSlot[233]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1484 = replaceSlot[234] + replaceSlot[235]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1486 = _T_1482 + _T_1484; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1488 = replaceSlot[236] + replaceSlot[237]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1490 = replaceSlot[238] + replaceSlot[239]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1492 = _T_1488 + _T_1490; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1494 = _T_1486 + _T_1492; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1496 = _T_1480 + _T_1494; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1498 = replaceSlot[240] + replaceSlot[241]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1500 = replaceSlot[242] + replaceSlot[243]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1502 = _T_1498 + _T_1500; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1504 = replaceSlot[244] + replaceSlot[245]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1506 = replaceSlot[246] + replaceSlot[247]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1508 = _T_1504 + _T_1506; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1510 = _T_1502 + _T_1508; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1512 = replaceSlot[248] + replaceSlot[249]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1514 = replaceSlot[250] + replaceSlot[251]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1516 = _T_1512 + _T_1514; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1518 = replaceSlot[252] + replaceSlot[253]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1520 = replaceSlot[254] + replaceSlot[255]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1522 = _T_1518 + _T_1520; // @[Bitwise.scala 48:55]
- wire [3:0] _T_1524 = _T_1516 + _T_1522; // @[Bitwise.scala 48:55]
- wire [4:0] _T_1526 = _T_1510 + _T_1524; // @[Bitwise.scala 48:55]
- wire [5:0] _T_1528 = _T_1496 + _T_1526; // @[Bitwise.scala 48:55]
- wire [6:0] _T_1530 = _T_1466 + _T_1528; // @[Bitwise.scala 48:55]
- wire [7:0] _T_1532 = _T_1404 + _T_1530; // @[Bitwise.scala 48:55]
- wire [8:0] _T_1534 = _T_1278 + _T_1532; // @[Bitwise.scala 48:55]
- wire [1:0] _replaceNum_2_T_1 = replaceSlot[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] _replaceNum_3_T_1 = replaceSlot[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [2:0] _replaceNum_4_T_1 = replaceSlot[4] ? 3'h4 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _replaceNum_5_T_1 = replaceSlot[5] ? 3'h5 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _replaceNum_6_T_1 = replaceSlot[6] ? 3'h6 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _replaceNum_7_T_1 = replaceSlot[7] ? 3'h7 : 3'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_8_T_1 = replaceSlot[8] ? 4'h8 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_9_T_1 = replaceSlot[9] ? 4'h9 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_10_T_1 = replaceSlot[10] ? 4'ha : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_11_T_1 = replaceSlot[11] ? 4'hb : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_12_T_1 = replaceSlot[12] ? 4'hc : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_13_T_1 = replaceSlot[13] ? 4'hd : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_14_T_1 = replaceSlot[14] ? 4'he : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _replaceNum_15_T_1 = replaceSlot[15] ? 4'hf : 4'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_16_T_1 = replaceSlot[16] ? 5'h10 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_17_T_1 = replaceSlot[17] ? 5'h11 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_18_T_1 = replaceSlot[18] ? 5'h12 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_19_T_1 = replaceSlot[19] ? 5'h13 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_20_T_1 = replaceSlot[20] ? 5'h14 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_21_T_1 = replaceSlot[21] ? 5'h15 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_22_T_1 = replaceSlot[22] ? 5'h16 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_23_T_1 = replaceSlot[23] ? 5'h17 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_24_T_1 = replaceSlot[24] ? 5'h18 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_25_T_1 = replaceSlot[25] ? 5'h19 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_26_T_1 = replaceSlot[26] ? 5'h1a : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_27_T_1 = replaceSlot[27] ? 5'h1b : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_28_T_1 = replaceSlot[28] ? 5'h1c : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_29_T_1 = replaceSlot[29] ? 5'h1d : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_30_T_1 = replaceSlot[30] ? 5'h1e : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _replaceNum_31_T_1 = replaceSlot[31] ? 5'h1f : 5'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_32_T_1 = replaceSlot[32] ? 6'h20 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_33_T_1 = replaceSlot[33] ? 6'h21 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_34_T_1 = replaceSlot[34] ? 6'h22 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_35_T_1 = replaceSlot[35] ? 6'h23 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_36_T_1 = replaceSlot[36] ? 6'h24 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_37_T_1 = replaceSlot[37] ? 6'h25 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_38_T_1 = replaceSlot[38] ? 6'h26 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_39_T_1 = replaceSlot[39] ? 6'h27 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_40_T_1 = replaceSlot[40] ? 6'h28 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_41_T_1 = replaceSlot[41] ? 6'h29 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_42_T_1 = replaceSlot[42] ? 6'h2a : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_43_T_1 = replaceSlot[43] ? 6'h2b : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_44_T_1 = replaceSlot[44] ? 6'h2c : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_45_T_1 = replaceSlot[45] ? 6'h2d : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_46_T_1 = replaceSlot[46] ? 6'h2e : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_47_T_1 = replaceSlot[47] ? 6'h2f : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_48_T_1 = replaceSlot[48] ? 6'h30 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_49_T_1 = replaceSlot[49] ? 6'h31 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_50_T_1 = replaceSlot[50] ? 6'h32 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_51_T_1 = replaceSlot[51] ? 6'h33 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_52_T_1 = replaceSlot[52] ? 6'h34 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_53_T_1 = replaceSlot[53] ? 6'h35 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_54_T_1 = replaceSlot[54] ? 6'h36 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_55_T_1 = replaceSlot[55] ? 6'h37 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_56_T_1 = replaceSlot[56] ? 6'h38 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_57_T_1 = replaceSlot[57] ? 6'h39 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_58_T_1 = replaceSlot[58] ? 6'h3a : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_59_T_1 = replaceSlot[59] ? 6'h3b : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_60_T_1 = replaceSlot[60] ? 6'h3c : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_61_T_1 = replaceSlot[61] ? 6'h3d : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_62_T_1 = replaceSlot[62] ? 6'h3e : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _replaceNum_63_T_1 = replaceSlot[63] ? 6'h3f : 6'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_64_T_1 = replaceSlot[64] ? 7'h40 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_65_T_1 = replaceSlot[65] ? 7'h41 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_66_T_1 = replaceSlot[66] ? 7'h42 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_67_T_1 = replaceSlot[67] ? 7'h43 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_68_T_1 = replaceSlot[68] ? 7'h44 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_69_T_1 = replaceSlot[69] ? 7'h45 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_70_T_1 = replaceSlot[70] ? 7'h46 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_71_T_1 = replaceSlot[71] ? 7'h47 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_72_T_1 = replaceSlot[72] ? 7'h48 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_73_T_1 = replaceSlot[73] ? 7'h49 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_74_T_1 = replaceSlot[74] ? 7'h4a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_75_T_1 = replaceSlot[75] ? 7'h4b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_76_T_1 = replaceSlot[76] ? 7'h4c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_77_T_1 = replaceSlot[77] ? 7'h4d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_78_T_1 = replaceSlot[78] ? 7'h4e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_79_T_1 = replaceSlot[79] ? 7'h4f : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_80_T_1 = replaceSlot[80] ? 7'h50 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_81_T_1 = replaceSlot[81] ? 7'h51 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_82_T_1 = replaceSlot[82] ? 7'h52 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_83_T_1 = replaceSlot[83] ? 7'h53 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_84_T_1 = replaceSlot[84] ? 7'h54 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_85_T_1 = replaceSlot[85] ? 7'h55 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_86_T_1 = replaceSlot[86] ? 7'h56 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_87_T_1 = replaceSlot[87] ? 7'h57 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_88_T_1 = replaceSlot[88] ? 7'h58 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_89_T_1 = replaceSlot[89] ? 7'h59 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_90_T_1 = replaceSlot[90] ? 7'h5a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_91_T_1 = replaceSlot[91] ? 7'h5b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_92_T_1 = replaceSlot[92] ? 7'h5c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_93_T_1 = replaceSlot[93] ? 7'h5d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_94_T_1 = replaceSlot[94] ? 7'h5e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_95_T_1 = replaceSlot[95] ? 7'h5f : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_96_T_1 = replaceSlot[96] ? 7'h60 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_97_T_1 = replaceSlot[97] ? 7'h61 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_98_T_1 = replaceSlot[98] ? 7'h62 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_99_T_1 = replaceSlot[99] ? 7'h63 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_100_T_1 = replaceSlot[100] ? 7'h64 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_101_T_1 = replaceSlot[101] ? 7'h65 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_102_T_1 = replaceSlot[102] ? 7'h66 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_103_T_1 = replaceSlot[103] ? 7'h67 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_104_T_1 = replaceSlot[104] ? 7'h68 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_105_T_1 = replaceSlot[105] ? 7'h69 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_106_T_1 = replaceSlot[106] ? 7'h6a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_107_T_1 = replaceSlot[107] ? 7'h6b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_108_T_1 = replaceSlot[108] ? 7'h6c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_109_T_1 = replaceSlot[109] ? 7'h6d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_110_T_1 = replaceSlot[110] ? 7'h6e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_111_T_1 = replaceSlot[111] ? 7'h6f : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_112_T_1 = replaceSlot[112] ? 7'h70 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_113_T_1 = replaceSlot[113] ? 7'h71 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_114_T_1 = replaceSlot[114] ? 7'h72 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_115_T_1 = replaceSlot[115] ? 7'h73 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_116_T_1 = replaceSlot[116] ? 7'h74 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_117_T_1 = replaceSlot[117] ? 7'h75 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_118_T_1 = replaceSlot[118] ? 7'h76 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_119_T_1 = replaceSlot[119] ? 7'h77 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_120_T_1 = replaceSlot[120] ? 7'h78 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_121_T_1 = replaceSlot[121] ? 7'h79 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_122_T_1 = replaceSlot[122] ? 7'h7a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_123_T_1 = replaceSlot[123] ? 7'h7b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_124_T_1 = replaceSlot[124] ? 7'h7c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_125_T_1 = replaceSlot[125] ? 7'h7d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_126_T_1 = replaceSlot[126] ? 7'h7e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _replaceNum_127_T_1 = replaceSlot[127] ? 7'h7f : 7'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_128 = replaceSlot[128] ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_129 = replaceSlot[129] ? 8'h81 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_130 = replaceSlot[130] ? 8'h82 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_131 = replaceSlot[131] ? 8'h83 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_132 = replaceSlot[132] ? 8'h84 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_133 = replaceSlot[133] ? 8'h85 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_134 = replaceSlot[134] ? 8'h86 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_135 = replaceSlot[135] ? 8'h87 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_136 = replaceSlot[136] ? 8'h88 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_137 = replaceSlot[137] ? 8'h89 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_138 = replaceSlot[138] ? 8'h8a : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_139 = replaceSlot[139] ? 8'h8b : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_140 = replaceSlot[140] ? 8'h8c : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_141 = replaceSlot[141] ? 8'h8d : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_142 = replaceSlot[142] ? 8'h8e : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_143 = replaceSlot[143] ? 8'h8f : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_144 = replaceSlot[144] ? 8'h90 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_145 = replaceSlot[145] ? 8'h91 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_146 = replaceSlot[146] ? 8'h92 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_147 = replaceSlot[147] ? 8'h93 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_148 = replaceSlot[148] ? 8'h94 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_149 = replaceSlot[149] ? 8'h95 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_150 = replaceSlot[150] ? 8'h96 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_151 = replaceSlot[151] ? 8'h97 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_152 = replaceSlot[152] ? 8'h98 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_153 = replaceSlot[153] ? 8'h99 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_154 = replaceSlot[154] ? 8'h9a : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_155 = replaceSlot[155] ? 8'h9b : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_156 = replaceSlot[156] ? 8'h9c : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_157 = replaceSlot[157] ? 8'h9d : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_158 = replaceSlot[158] ? 8'h9e : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_159 = replaceSlot[159] ? 8'h9f : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_160 = replaceSlot[160] ? 8'ha0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_161 = replaceSlot[161] ? 8'ha1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_162 = replaceSlot[162] ? 8'ha2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_163 = replaceSlot[163] ? 8'ha3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_164 = replaceSlot[164] ? 8'ha4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_165 = replaceSlot[165] ? 8'ha5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_166 = replaceSlot[166] ? 8'ha6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_167 = replaceSlot[167] ? 8'ha7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_168 = replaceSlot[168] ? 8'ha8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_169 = replaceSlot[169] ? 8'ha9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_170 = replaceSlot[170] ? 8'haa : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_171 = replaceSlot[171] ? 8'hab : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_172 = replaceSlot[172] ? 8'hac : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_173 = replaceSlot[173] ? 8'had : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_174 = replaceSlot[174] ? 8'hae : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_175 = replaceSlot[175] ? 8'haf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_176 = replaceSlot[176] ? 8'hb0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_177 = replaceSlot[177] ? 8'hb1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_178 = replaceSlot[178] ? 8'hb2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_179 = replaceSlot[179] ? 8'hb3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_180 = replaceSlot[180] ? 8'hb4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_181 = replaceSlot[181] ? 8'hb5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_182 = replaceSlot[182] ? 8'hb6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_183 = replaceSlot[183] ? 8'hb7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_184 = replaceSlot[184] ? 8'hb8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_185 = replaceSlot[185] ? 8'hb9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_186 = replaceSlot[186] ? 8'hba : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_187 = replaceSlot[187] ? 8'hbb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_188 = replaceSlot[188] ? 8'hbc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_189 = replaceSlot[189] ? 8'hbd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_190 = replaceSlot[190] ? 8'hbe : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_191 = replaceSlot[191] ? 8'hbf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_192 = replaceSlot[192] ? 8'hc0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_193 = replaceSlot[193] ? 8'hc1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_194 = replaceSlot[194] ? 8'hc2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_195 = replaceSlot[195] ? 8'hc3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_196 = replaceSlot[196] ? 8'hc4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_197 = replaceSlot[197] ? 8'hc5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_198 = replaceSlot[198] ? 8'hc6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_199 = replaceSlot[199] ? 8'hc7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_200 = replaceSlot[200] ? 8'hc8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_201 = replaceSlot[201] ? 8'hc9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_202 = replaceSlot[202] ? 8'hca : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_203 = replaceSlot[203] ? 8'hcb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_204 = replaceSlot[204] ? 8'hcc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_205 = replaceSlot[205] ? 8'hcd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_206 = replaceSlot[206] ? 8'hce : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_207 = replaceSlot[207] ? 8'hcf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_208 = replaceSlot[208] ? 8'hd0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_209 = replaceSlot[209] ? 8'hd1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_210 = replaceSlot[210] ? 8'hd2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_211 = replaceSlot[211] ? 8'hd3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_212 = replaceSlot[212] ? 8'hd4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_213 = replaceSlot[213] ? 8'hd5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_214 = replaceSlot[214] ? 8'hd6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_215 = replaceSlot[215] ? 8'hd7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_216 = replaceSlot[216] ? 8'hd8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_217 = replaceSlot[217] ? 8'hd9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_218 = replaceSlot[218] ? 8'hda : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_219 = replaceSlot[219] ? 8'hdb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_220 = replaceSlot[220] ? 8'hdc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_221 = replaceSlot[221] ? 8'hdd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_222 = replaceSlot[222] ? 8'hde : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_223 = replaceSlot[223] ? 8'hdf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_224 = replaceSlot[224] ? 8'he0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_225 = replaceSlot[225] ? 8'he1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_226 = replaceSlot[226] ? 8'he2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_227 = replaceSlot[227] ? 8'he3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_228 = replaceSlot[228] ? 8'he4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_229 = replaceSlot[229] ? 8'he5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_230 = replaceSlot[230] ? 8'he6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_231 = replaceSlot[231] ? 8'he7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_232 = replaceSlot[232] ? 8'he8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_233 = replaceSlot[233] ? 8'he9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_234 = replaceSlot[234] ? 8'hea : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_235 = replaceSlot[235] ? 8'heb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_236 = replaceSlot[236] ? 8'hec : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_237 = replaceSlot[237] ? 8'hed : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_238 = replaceSlot[238] ? 8'hee : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_239 = replaceSlot[239] ? 8'hef : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_240 = replaceSlot[240] ? 8'hf0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_241 = replaceSlot[241] ? 8'hf1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_242 = replaceSlot[242] ? 8'hf2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_243 = replaceSlot[243] ? 8'hf3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_244 = replaceSlot[244] ? 8'hf4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_245 = replaceSlot[245] ? 8'hf5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_246 = replaceSlot[246] ? 8'hf6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_247 = replaceSlot[247] ? 8'hf7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_248 = replaceSlot[248] ? 8'hf8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_249 = replaceSlot[249] ? 8'hf9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_250 = replaceSlot[250] ? 8'hfa : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_251 = replaceSlot[251] ? 8'hfb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_252 = replaceSlot[252] ? 8'hfc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_253 = replaceSlot[253] ? 8'hfd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_254 = replaceSlot[254] ? 8'hfe : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_255 = replaceSlot[255] ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire [7:0] replaceNum_1 = {{7'd0}, replaceSlot[1]}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] replaceNum_2 = {{6'd0}, _replaceNum_2_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_2 = replaceNum_1 | replaceNum_2; // @[Library.scala 76:39]
- wire [7:0] replaceNum_3 = {{6'd0}, _replaceNum_3_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_3 = _replaceId_T_2 | replaceNum_3; // @[Library.scala 76:39]
- wire [7:0] replaceNum_4 = {{5'd0}, _replaceNum_4_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_4 = _replaceId_T_3 | replaceNum_4; // @[Library.scala 76:39]
- wire [7:0] replaceNum_5 = {{5'd0}, _replaceNum_5_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_5 = _replaceId_T_4 | replaceNum_5; // @[Library.scala 76:39]
- wire [7:0] replaceNum_6 = {{5'd0}, _replaceNum_6_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_6 = _replaceId_T_5 | replaceNum_6; // @[Library.scala 76:39]
- wire [7:0] replaceNum_7 = {{5'd0}, _replaceNum_7_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_7 = _replaceId_T_6 | replaceNum_7; // @[Library.scala 76:39]
- wire [7:0] replaceNum_8 = {{4'd0}, _replaceNum_8_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_8 = _replaceId_T_7 | replaceNum_8; // @[Library.scala 76:39]
- wire [7:0] replaceNum_9 = {{4'd0}, _replaceNum_9_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_9 = _replaceId_T_8 | replaceNum_9; // @[Library.scala 76:39]
- wire [7:0] replaceNum_10 = {{4'd0}, _replaceNum_10_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_10 = _replaceId_T_9 | replaceNum_10; // @[Library.scala 76:39]
- wire [7:0] replaceNum_11 = {{4'd0}, _replaceNum_11_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_11 = _replaceId_T_10 | replaceNum_11; // @[Library.scala 76:39]
- wire [7:0] replaceNum_12 = {{4'd0}, _replaceNum_12_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_12 = _replaceId_T_11 | replaceNum_12; // @[Library.scala 76:39]
- wire [7:0] replaceNum_13 = {{4'd0}, _replaceNum_13_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_13 = _replaceId_T_12 | replaceNum_13; // @[Library.scala 76:39]
- wire [7:0] replaceNum_14 = {{4'd0}, _replaceNum_14_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_14 = _replaceId_T_13 | replaceNum_14; // @[Library.scala 76:39]
- wire [7:0] replaceNum_15 = {{4'd0}, _replaceNum_15_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_15 = _replaceId_T_14 | replaceNum_15; // @[Library.scala 76:39]
- wire [7:0] replaceNum_16 = {{3'd0}, _replaceNum_16_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_16 = _replaceId_T_15 | replaceNum_16; // @[Library.scala 76:39]
- wire [7:0] replaceNum_17 = {{3'd0}, _replaceNum_17_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_17 = _replaceId_T_16 | replaceNum_17; // @[Library.scala 76:39]
- wire [7:0] replaceNum_18 = {{3'd0}, _replaceNum_18_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_18 = _replaceId_T_17 | replaceNum_18; // @[Library.scala 76:39]
- wire [7:0] replaceNum_19 = {{3'd0}, _replaceNum_19_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_19 = _replaceId_T_18 | replaceNum_19; // @[Library.scala 76:39]
- wire [7:0] replaceNum_20 = {{3'd0}, _replaceNum_20_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_20 = _replaceId_T_19 | replaceNum_20; // @[Library.scala 76:39]
- wire [7:0] replaceNum_21 = {{3'd0}, _replaceNum_21_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_21 = _replaceId_T_20 | replaceNum_21; // @[Library.scala 76:39]
- wire [7:0] replaceNum_22 = {{3'd0}, _replaceNum_22_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_22 = _replaceId_T_21 | replaceNum_22; // @[Library.scala 76:39]
- wire [7:0] replaceNum_23 = {{3'd0}, _replaceNum_23_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_23 = _replaceId_T_22 | replaceNum_23; // @[Library.scala 76:39]
- wire [7:0] replaceNum_24 = {{3'd0}, _replaceNum_24_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_24 = _replaceId_T_23 | replaceNum_24; // @[Library.scala 76:39]
- wire [7:0] replaceNum_25 = {{3'd0}, _replaceNum_25_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_25 = _replaceId_T_24 | replaceNum_25; // @[Library.scala 76:39]
- wire [7:0] replaceNum_26 = {{3'd0}, _replaceNum_26_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_26 = _replaceId_T_25 | replaceNum_26; // @[Library.scala 76:39]
- wire [7:0] replaceNum_27 = {{3'd0}, _replaceNum_27_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_27 = _replaceId_T_26 | replaceNum_27; // @[Library.scala 76:39]
- wire [7:0] replaceNum_28 = {{3'd0}, _replaceNum_28_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_28 = _replaceId_T_27 | replaceNum_28; // @[Library.scala 76:39]
- wire [7:0] replaceNum_29 = {{3'd0}, _replaceNum_29_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_29 = _replaceId_T_28 | replaceNum_29; // @[Library.scala 76:39]
- wire [7:0] replaceNum_30 = {{3'd0}, _replaceNum_30_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_30 = _replaceId_T_29 | replaceNum_30; // @[Library.scala 76:39]
- wire [7:0] replaceNum_31 = {{3'd0}, _replaceNum_31_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_31 = _replaceId_T_30 | replaceNum_31; // @[Library.scala 76:39]
- wire [7:0] replaceNum_32 = {{2'd0}, _replaceNum_32_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_32 = _replaceId_T_31 | replaceNum_32; // @[Library.scala 76:39]
- wire [7:0] replaceNum_33 = {{2'd0}, _replaceNum_33_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_33 = _replaceId_T_32 | replaceNum_33; // @[Library.scala 76:39]
- wire [7:0] replaceNum_34 = {{2'd0}, _replaceNum_34_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_34 = _replaceId_T_33 | replaceNum_34; // @[Library.scala 76:39]
- wire [7:0] replaceNum_35 = {{2'd0}, _replaceNum_35_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_35 = _replaceId_T_34 | replaceNum_35; // @[Library.scala 76:39]
- wire [7:0] replaceNum_36 = {{2'd0}, _replaceNum_36_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_36 = _replaceId_T_35 | replaceNum_36; // @[Library.scala 76:39]
- wire [7:0] replaceNum_37 = {{2'd0}, _replaceNum_37_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_37 = _replaceId_T_36 | replaceNum_37; // @[Library.scala 76:39]
- wire [7:0] replaceNum_38 = {{2'd0}, _replaceNum_38_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_38 = _replaceId_T_37 | replaceNum_38; // @[Library.scala 76:39]
- wire [7:0] replaceNum_39 = {{2'd0}, _replaceNum_39_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_39 = _replaceId_T_38 | replaceNum_39; // @[Library.scala 76:39]
- wire [7:0] replaceNum_40 = {{2'd0}, _replaceNum_40_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_40 = _replaceId_T_39 | replaceNum_40; // @[Library.scala 76:39]
- wire [7:0] replaceNum_41 = {{2'd0}, _replaceNum_41_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_41 = _replaceId_T_40 | replaceNum_41; // @[Library.scala 76:39]
- wire [7:0] replaceNum_42 = {{2'd0}, _replaceNum_42_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_42 = _replaceId_T_41 | replaceNum_42; // @[Library.scala 76:39]
- wire [7:0] replaceNum_43 = {{2'd0}, _replaceNum_43_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_43 = _replaceId_T_42 | replaceNum_43; // @[Library.scala 76:39]
- wire [7:0] replaceNum_44 = {{2'd0}, _replaceNum_44_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_44 = _replaceId_T_43 | replaceNum_44; // @[Library.scala 76:39]
- wire [7:0] replaceNum_45 = {{2'd0}, _replaceNum_45_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_45 = _replaceId_T_44 | replaceNum_45; // @[Library.scala 76:39]
- wire [7:0] replaceNum_46 = {{2'd0}, _replaceNum_46_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_46 = _replaceId_T_45 | replaceNum_46; // @[Library.scala 76:39]
- wire [7:0] replaceNum_47 = {{2'd0}, _replaceNum_47_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_47 = _replaceId_T_46 | replaceNum_47; // @[Library.scala 76:39]
- wire [7:0] replaceNum_48 = {{2'd0}, _replaceNum_48_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_48 = _replaceId_T_47 | replaceNum_48; // @[Library.scala 76:39]
- wire [7:0] replaceNum_49 = {{2'd0}, _replaceNum_49_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_49 = _replaceId_T_48 | replaceNum_49; // @[Library.scala 76:39]
- wire [7:0] replaceNum_50 = {{2'd0}, _replaceNum_50_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_50 = _replaceId_T_49 | replaceNum_50; // @[Library.scala 76:39]
- wire [7:0] replaceNum_51 = {{2'd0}, _replaceNum_51_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_51 = _replaceId_T_50 | replaceNum_51; // @[Library.scala 76:39]
- wire [7:0] replaceNum_52 = {{2'd0}, _replaceNum_52_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_52 = _replaceId_T_51 | replaceNum_52; // @[Library.scala 76:39]
- wire [7:0] replaceNum_53 = {{2'd0}, _replaceNum_53_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_53 = _replaceId_T_52 | replaceNum_53; // @[Library.scala 76:39]
- wire [7:0] replaceNum_54 = {{2'd0}, _replaceNum_54_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_54 = _replaceId_T_53 | replaceNum_54; // @[Library.scala 76:39]
- wire [7:0] replaceNum_55 = {{2'd0}, _replaceNum_55_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_55 = _replaceId_T_54 | replaceNum_55; // @[Library.scala 76:39]
- wire [7:0] replaceNum_56 = {{2'd0}, _replaceNum_56_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_56 = _replaceId_T_55 | replaceNum_56; // @[Library.scala 76:39]
- wire [7:0] replaceNum_57 = {{2'd0}, _replaceNum_57_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_57 = _replaceId_T_56 | replaceNum_57; // @[Library.scala 76:39]
- wire [7:0] replaceNum_58 = {{2'd0}, _replaceNum_58_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_58 = _replaceId_T_57 | replaceNum_58; // @[Library.scala 76:39]
- wire [7:0] replaceNum_59 = {{2'd0}, _replaceNum_59_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_59 = _replaceId_T_58 | replaceNum_59; // @[Library.scala 76:39]
- wire [7:0] replaceNum_60 = {{2'd0}, _replaceNum_60_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_60 = _replaceId_T_59 | replaceNum_60; // @[Library.scala 76:39]
- wire [7:0] replaceNum_61 = {{2'd0}, _replaceNum_61_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_61 = _replaceId_T_60 | replaceNum_61; // @[Library.scala 76:39]
- wire [7:0] replaceNum_62 = {{2'd0}, _replaceNum_62_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_62 = _replaceId_T_61 | replaceNum_62; // @[Library.scala 76:39]
- wire [7:0] replaceNum_63 = {{2'd0}, _replaceNum_63_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_63 = _replaceId_T_62 | replaceNum_63; // @[Library.scala 76:39]
- wire [7:0] replaceNum_64 = {{1'd0}, _replaceNum_64_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_64 = _replaceId_T_63 | replaceNum_64; // @[Library.scala 76:39]
- wire [7:0] replaceNum_65 = {{1'd0}, _replaceNum_65_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_65 = _replaceId_T_64 | replaceNum_65; // @[Library.scala 76:39]
- wire [7:0] replaceNum_66 = {{1'd0}, _replaceNum_66_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_66 = _replaceId_T_65 | replaceNum_66; // @[Library.scala 76:39]
- wire [7:0] replaceNum_67 = {{1'd0}, _replaceNum_67_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_67 = _replaceId_T_66 | replaceNum_67; // @[Library.scala 76:39]
- wire [7:0] replaceNum_68 = {{1'd0}, _replaceNum_68_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_68 = _replaceId_T_67 | replaceNum_68; // @[Library.scala 76:39]
- wire [7:0] replaceNum_69 = {{1'd0}, _replaceNum_69_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_69 = _replaceId_T_68 | replaceNum_69; // @[Library.scala 76:39]
- wire [7:0] replaceNum_70 = {{1'd0}, _replaceNum_70_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_70 = _replaceId_T_69 | replaceNum_70; // @[Library.scala 76:39]
- wire [7:0] replaceNum_71 = {{1'd0}, _replaceNum_71_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_71 = _replaceId_T_70 | replaceNum_71; // @[Library.scala 76:39]
- wire [7:0] replaceNum_72 = {{1'd0}, _replaceNum_72_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_72 = _replaceId_T_71 | replaceNum_72; // @[Library.scala 76:39]
- wire [7:0] replaceNum_73 = {{1'd0}, _replaceNum_73_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_73 = _replaceId_T_72 | replaceNum_73; // @[Library.scala 76:39]
- wire [7:0] replaceNum_74 = {{1'd0}, _replaceNum_74_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_74 = _replaceId_T_73 | replaceNum_74; // @[Library.scala 76:39]
- wire [7:0] replaceNum_75 = {{1'd0}, _replaceNum_75_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_75 = _replaceId_T_74 | replaceNum_75; // @[Library.scala 76:39]
- wire [7:0] replaceNum_76 = {{1'd0}, _replaceNum_76_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_76 = _replaceId_T_75 | replaceNum_76; // @[Library.scala 76:39]
- wire [7:0] replaceNum_77 = {{1'd0}, _replaceNum_77_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_77 = _replaceId_T_76 | replaceNum_77; // @[Library.scala 76:39]
- wire [7:0] replaceNum_78 = {{1'd0}, _replaceNum_78_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_78 = _replaceId_T_77 | replaceNum_78; // @[Library.scala 76:39]
- wire [7:0] replaceNum_79 = {{1'd0}, _replaceNum_79_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_79 = _replaceId_T_78 | replaceNum_79; // @[Library.scala 76:39]
- wire [7:0] replaceNum_80 = {{1'd0}, _replaceNum_80_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_80 = _replaceId_T_79 | replaceNum_80; // @[Library.scala 76:39]
- wire [7:0] replaceNum_81 = {{1'd0}, _replaceNum_81_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_81 = _replaceId_T_80 | replaceNum_81; // @[Library.scala 76:39]
- wire [7:0] replaceNum_82 = {{1'd0}, _replaceNum_82_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_82 = _replaceId_T_81 | replaceNum_82; // @[Library.scala 76:39]
- wire [7:0] replaceNum_83 = {{1'd0}, _replaceNum_83_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_83 = _replaceId_T_82 | replaceNum_83; // @[Library.scala 76:39]
- wire [7:0] replaceNum_84 = {{1'd0}, _replaceNum_84_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_84 = _replaceId_T_83 | replaceNum_84; // @[Library.scala 76:39]
- wire [7:0] replaceNum_85 = {{1'd0}, _replaceNum_85_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_85 = _replaceId_T_84 | replaceNum_85; // @[Library.scala 76:39]
- wire [7:0] replaceNum_86 = {{1'd0}, _replaceNum_86_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_86 = _replaceId_T_85 | replaceNum_86; // @[Library.scala 76:39]
- wire [7:0] replaceNum_87 = {{1'd0}, _replaceNum_87_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_87 = _replaceId_T_86 | replaceNum_87; // @[Library.scala 76:39]
- wire [7:0] replaceNum_88 = {{1'd0}, _replaceNum_88_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_88 = _replaceId_T_87 | replaceNum_88; // @[Library.scala 76:39]
- wire [7:0] replaceNum_89 = {{1'd0}, _replaceNum_89_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_89 = _replaceId_T_88 | replaceNum_89; // @[Library.scala 76:39]
- wire [7:0] replaceNum_90 = {{1'd0}, _replaceNum_90_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_90 = _replaceId_T_89 | replaceNum_90; // @[Library.scala 76:39]
- wire [7:0] replaceNum_91 = {{1'd0}, _replaceNum_91_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_91 = _replaceId_T_90 | replaceNum_91; // @[Library.scala 76:39]
- wire [7:0] replaceNum_92 = {{1'd0}, _replaceNum_92_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_92 = _replaceId_T_91 | replaceNum_92; // @[Library.scala 76:39]
- wire [7:0] replaceNum_93 = {{1'd0}, _replaceNum_93_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_93 = _replaceId_T_92 | replaceNum_93; // @[Library.scala 76:39]
- wire [7:0] replaceNum_94 = {{1'd0}, _replaceNum_94_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_94 = _replaceId_T_93 | replaceNum_94; // @[Library.scala 76:39]
- wire [7:0] replaceNum_95 = {{1'd0}, _replaceNum_95_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_95 = _replaceId_T_94 | replaceNum_95; // @[Library.scala 76:39]
- wire [7:0] replaceNum_96 = {{1'd0}, _replaceNum_96_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_96 = _replaceId_T_95 | replaceNum_96; // @[Library.scala 76:39]
- wire [7:0] replaceNum_97 = {{1'd0}, _replaceNum_97_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_97 = _replaceId_T_96 | replaceNum_97; // @[Library.scala 76:39]
- wire [7:0] replaceNum_98 = {{1'd0}, _replaceNum_98_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_98 = _replaceId_T_97 | replaceNum_98; // @[Library.scala 76:39]
- wire [7:0] replaceNum_99 = {{1'd0}, _replaceNum_99_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_99 = _replaceId_T_98 | replaceNum_99; // @[Library.scala 76:39]
- wire [7:0] replaceNum_100 = {{1'd0}, _replaceNum_100_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_100 = _replaceId_T_99 | replaceNum_100; // @[Library.scala 76:39]
- wire [7:0] replaceNum_101 = {{1'd0}, _replaceNum_101_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_101 = _replaceId_T_100 | replaceNum_101; // @[Library.scala 76:39]
- wire [7:0] replaceNum_102 = {{1'd0}, _replaceNum_102_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_102 = _replaceId_T_101 | replaceNum_102; // @[Library.scala 76:39]
- wire [7:0] replaceNum_103 = {{1'd0}, _replaceNum_103_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_103 = _replaceId_T_102 | replaceNum_103; // @[Library.scala 76:39]
- wire [7:0] replaceNum_104 = {{1'd0}, _replaceNum_104_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_104 = _replaceId_T_103 | replaceNum_104; // @[Library.scala 76:39]
- wire [7:0] replaceNum_105 = {{1'd0}, _replaceNum_105_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_105 = _replaceId_T_104 | replaceNum_105; // @[Library.scala 76:39]
- wire [7:0] replaceNum_106 = {{1'd0}, _replaceNum_106_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_106 = _replaceId_T_105 | replaceNum_106; // @[Library.scala 76:39]
- wire [7:0] replaceNum_107 = {{1'd0}, _replaceNum_107_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_107 = _replaceId_T_106 | replaceNum_107; // @[Library.scala 76:39]
- wire [7:0] replaceNum_108 = {{1'd0}, _replaceNum_108_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_108 = _replaceId_T_107 | replaceNum_108; // @[Library.scala 76:39]
- wire [7:0] replaceNum_109 = {{1'd0}, _replaceNum_109_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_109 = _replaceId_T_108 | replaceNum_109; // @[Library.scala 76:39]
- wire [7:0] replaceNum_110 = {{1'd0}, _replaceNum_110_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_110 = _replaceId_T_109 | replaceNum_110; // @[Library.scala 76:39]
- wire [7:0] replaceNum_111 = {{1'd0}, _replaceNum_111_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_111 = _replaceId_T_110 | replaceNum_111; // @[Library.scala 76:39]
- wire [7:0] replaceNum_112 = {{1'd0}, _replaceNum_112_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_112 = _replaceId_T_111 | replaceNum_112; // @[Library.scala 76:39]
- wire [7:0] replaceNum_113 = {{1'd0}, _replaceNum_113_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_113 = _replaceId_T_112 | replaceNum_113; // @[Library.scala 76:39]
- wire [7:0] replaceNum_114 = {{1'd0}, _replaceNum_114_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_114 = _replaceId_T_113 | replaceNum_114; // @[Library.scala 76:39]
- wire [7:0] replaceNum_115 = {{1'd0}, _replaceNum_115_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_115 = _replaceId_T_114 | replaceNum_115; // @[Library.scala 76:39]
- wire [7:0] replaceNum_116 = {{1'd0}, _replaceNum_116_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_116 = _replaceId_T_115 | replaceNum_116; // @[Library.scala 76:39]
- wire [7:0] replaceNum_117 = {{1'd0}, _replaceNum_117_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_117 = _replaceId_T_116 | replaceNum_117; // @[Library.scala 76:39]
- wire [7:0] replaceNum_118 = {{1'd0}, _replaceNum_118_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_118 = _replaceId_T_117 | replaceNum_118; // @[Library.scala 76:39]
- wire [7:0] replaceNum_119 = {{1'd0}, _replaceNum_119_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_119 = _replaceId_T_118 | replaceNum_119; // @[Library.scala 76:39]
- wire [7:0] replaceNum_120 = {{1'd0}, _replaceNum_120_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_120 = _replaceId_T_119 | replaceNum_120; // @[Library.scala 76:39]
- wire [7:0] replaceNum_121 = {{1'd0}, _replaceNum_121_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_121 = _replaceId_T_120 | replaceNum_121; // @[Library.scala 76:39]
- wire [7:0] replaceNum_122 = {{1'd0}, _replaceNum_122_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_122 = _replaceId_T_121 | replaceNum_122; // @[Library.scala 76:39]
- wire [7:0] replaceNum_123 = {{1'd0}, _replaceNum_123_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_123 = _replaceId_T_122 | replaceNum_123; // @[Library.scala 76:39]
- wire [7:0] replaceNum_124 = {{1'd0}, _replaceNum_124_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_124 = _replaceId_T_123 | replaceNum_124; // @[Library.scala 76:39]
- wire [7:0] replaceNum_125 = {{1'd0}, _replaceNum_125_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_125 = _replaceId_T_124 | replaceNum_125; // @[Library.scala 76:39]
- wire [7:0] replaceNum_126 = {{1'd0}, _replaceNum_126_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_126 = _replaceId_T_125 | replaceNum_126; // @[Library.scala 76:39]
- wire [7:0] replaceNum_127 = {{1'd0}, _replaceNum_127_T_1}; // @[L1ICache.scala 122:24 124:19]
- wire [7:0] _replaceId_T_127 = _replaceId_T_126 | replaceNum_127; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_128 = _replaceId_T_127 | replaceNum_128; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_129 = _replaceId_T_128 | replaceNum_129; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_130 = _replaceId_T_129 | replaceNum_130; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_131 = _replaceId_T_130 | replaceNum_131; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_132 = _replaceId_T_131 | replaceNum_132; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_133 = _replaceId_T_132 | replaceNum_133; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_134 = _replaceId_T_133 | replaceNum_134; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_135 = _replaceId_T_134 | replaceNum_135; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_136 = _replaceId_T_135 | replaceNum_136; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_137 = _replaceId_T_136 | replaceNum_137; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_138 = _replaceId_T_137 | replaceNum_138; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_139 = _replaceId_T_138 | replaceNum_139; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_140 = _replaceId_T_139 | replaceNum_140; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_141 = _replaceId_T_140 | replaceNum_141; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_142 = _replaceId_T_141 | replaceNum_142; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_143 = _replaceId_T_142 | replaceNum_143; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_144 = _replaceId_T_143 | replaceNum_144; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_145 = _replaceId_T_144 | replaceNum_145; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_146 = _replaceId_T_145 | replaceNum_146; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_147 = _replaceId_T_146 | replaceNum_147; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_148 = _replaceId_T_147 | replaceNum_148; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_149 = _replaceId_T_148 | replaceNum_149; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_150 = _replaceId_T_149 | replaceNum_150; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_151 = _replaceId_T_150 | replaceNum_151; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_152 = _replaceId_T_151 | replaceNum_152; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_153 = _replaceId_T_152 | replaceNum_153; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_154 = _replaceId_T_153 | replaceNum_154; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_155 = _replaceId_T_154 | replaceNum_155; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_156 = _replaceId_T_155 | replaceNum_156; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_157 = _replaceId_T_156 | replaceNum_157; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_158 = _replaceId_T_157 | replaceNum_158; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_159 = _replaceId_T_158 | replaceNum_159; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_160 = _replaceId_T_159 | replaceNum_160; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_161 = _replaceId_T_160 | replaceNum_161; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_162 = _replaceId_T_161 | replaceNum_162; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_163 = _replaceId_T_162 | replaceNum_163; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_164 = _replaceId_T_163 | replaceNum_164; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_165 = _replaceId_T_164 | replaceNum_165; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_166 = _replaceId_T_165 | replaceNum_166; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_167 = _replaceId_T_166 | replaceNum_167; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_168 = _replaceId_T_167 | replaceNum_168; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_169 = _replaceId_T_168 | replaceNum_169; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_170 = _replaceId_T_169 | replaceNum_170; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_171 = _replaceId_T_170 | replaceNum_171; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_172 = _replaceId_T_171 | replaceNum_172; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_173 = _replaceId_T_172 | replaceNum_173; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_174 = _replaceId_T_173 | replaceNum_174; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_175 = _replaceId_T_174 | replaceNum_175; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_176 = _replaceId_T_175 | replaceNum_176; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_177 = _replaceId_T_176 | replaceNum_177; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_178 = _replaceId_T_177 | replaceNum_178; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_179 = _replaceId_T_178 | replaceNum_179; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_180 = _replaceId_T_179 | replaceNum_180; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_181 = _replaceId_T_180 | replaceNum_181; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_182 = _replaceId_T_181 | replaceNum_182; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_183 = _replaceId_T_182 | replaceNum_183; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_184 = _replaceId_T_183 | replaceNum_184; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_185 = _replaceId_T_184 | replaceNum_185; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_186 = _replaceId_T_185 | replaceNum_186; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_187 = _replaceId_T_186 | replaceNum_187; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_188 = _replaceId_T_187 | replaceNum_188; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_189 = _replaceId_T_188 | replaceNum_189; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_190 = _replaceId_T_189 | replaceNum_190; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_191 = _replaceId_T_190 | replaceNum_191; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_192 = _replaceId_T_191 | replaceNum_192; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_193 = _replaceId_T_192 | replaceNum_193; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_194 = _replaceId_T_193 | replaceNum_194; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_195 = _replaceId_T_194 | replaceNum_195; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_196 = _replaceId_T_195 | replaceNum_196; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_197 = _replaceId_T_196 | replaceNum_197; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_198 = _replaceId_T_197 | replaceNum_198; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_199 = _replaceId_T_198 | replaceNum_199; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_200 = _replaceId_T_199 | replaceNum_200; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_201 = _replaceId_T_200 | replaceNum_201; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_202 = _replaceId_T_201 | replaceNum_202; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_203 = _replaceId_T_202 | replaceNum_203; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_204 = _replaceId_T_203 | replaceNum_204; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_205 = _replaceId_T_204 | replaceNum_205; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_206 = _replaceId_T_205 | replaceNum_206; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_207 = _replaceId_T_206 | replaceNum_207; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_208 = _replaceId_T_207 | replaceNum_208; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_209 = _replaceId_T_208 | replaceNum_209; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_210 = _replaceId_T_209 | replaceNum_210; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_211 = _replaceId_T_210 | replaceNum_211; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_212 = _replaceId_T_211 | replaceNum_212; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_213 = _replaceId_T_212 | replaceNum_213; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_214 = _replaceId_T_213 | replaceNum_214; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_215 = _replaceId_T_214 | replaceNum_215; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_216 = _replaceId_T_215 | replaceNum_216; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_217 = _replaceId_T_216 | replaceNum_217; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_218 = _replaceId_T_217 | replaceNum_218; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_219 = _replaceId_T_218 | replaceNum_219; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_220 = _replaceId_T_219 | replaceNum_220; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_221 = _replaceId_T_220 | replaceNum_221; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_222 = _replaceId_T_221 | replaceNum_222; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_223 = _replaceId_T_222 | replaceNum_223; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_224 = _replaceId_T_223 | replaceNum_224; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_225 = _replaceId_T_224 | replaceNum_225; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_226 = _replaceId_T_225 | replaceNum_226; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_227 = _replaceId_T_226 | replaceNum_227; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_228 = _replaceId_T_227 | replaceNum_228; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_229 = _replaceId_T_228 | replaceNum_229; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_230 = _replaceId_T_229 | replaceNum_230; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_231 = _replaceId_T_230 | replaceNum_231; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_232 = _replaceId_T_231 | replaceNum_232; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_233 = _replaceId_T_232 | replaceNum_233; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_234 = _replaceId_T_233 | replaceNum_234; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_235 = _replaceId_T_234 | replaceNum_235; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_236 = _replaceId_T_235 | replaceNum_236; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_237 = _replaceId_T_236 | replaceNum_237; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_238 = _replaceId_T_237 | replaceNum_238; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_239 = _replaceId_T_238 | replaceNum_239; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_240 = _replaceId_T_239 | replaceNum_240; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_241 = _replaceId_T_240 | replaceNum_241; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_242 = _replaceId_T_241 | replaceNum_242; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_243 = _replaceId_T_242 | replaceNum_243; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_244 = _replaceId_T_243 | replaceNum_244; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_245 = _replaceId_T_244 | replaceNum_245; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_246 = _replaceId_T_245 | replaceNum_246; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_247 = _replaceId_T_246 | replaceNum_247; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_248 = _replaceId_T_247 | replaceNum_248; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_249 = _replaceId_T_248 | replaceNum_249; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_250 = _replaceId_T_249 | replaceNum_250; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_251 = _replaceId_T_250 | replaceNum_251; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_252 = _replaceId_T_251 | replaceNum_252; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_253 = _replaceId_T_252 | replaceNum_253; // @[Library.scala 76:39]
- wire [7:0] _replaceId_T_254 = _replaceId_T_253 | replaceNum_254; // @[Library.scala 76:39]
- wire [7:0] replaceId = _replaceId_T_254 | replaceNum_255; // @[Library.scala 76:39]
- wire [1:0] _readNum_2_T = matchSlotB_2 ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] _readNum_3_T = matchSlotB_3 ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [2:0] _readNum_4_T = matchSlotB_4 ? 3'h4 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _readNum_5_T = matchSlotB_5 ? 3'h5 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _readNum_6_T = matchSlotB_6 ? 3'h6 : 3'h0; // @[Library.scala 22:8]
- wire [2:0] _readNum_7_T = matchSlotB_7 ? 3'h7 : 3'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_8_T = matchSlotB_8 ? 4'h8 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_9_T = matchSlotB_9 ? 4'h9 : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_10_T = matchSlotB_10 ? 4'ha : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_11_T = matchSlotB_11 ? 4'hb : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_12_T = matchSlotB_12 ? 4'hc : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_13_T = matchSlotB_13 ? 4'hd : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_14_T = matchSlotB_14 ? 4'he : 4'h0; // @[Library.scala 22:8]
- wire [3:0] _readNum_15_T = matchSlotB_15 ? 4'hf : 4'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_16_T = matchSlotB_16 ? 5'h10 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_17_T = matchSlotB_17 ? 5'h11 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_18_T = matchSlotB_18 ? 5'h12 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_19_T = matchSlotB_19 ? 5'h13 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_20_T = matchSlotB_20 ? 5'h14 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_21_T = matchSlotB_21 ? 5'h15 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_22_T = matchSlotB_22 ? 5'h16 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_23_T = matchSlotB_23 ? 5'h17 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_24_T = matchSlotB_24 ? 5'h18 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_25_T = matchSlotB_25 ? 5'h19 : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_26_T = matchSlotB_26 ? 5'h1a : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_27_T = matchSlotB_27 ? 5'h1b : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_28_T = matchSlotB_28 ? 5'h1c : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_29_T = matchSlotB_29 ? 5'h1d : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_30_T = matchSlotB_30 ? 5'h1e : 5'h0; // @[Library.scala 22:8]
- wire [4:0] _readNum_31_T = matchSlotB_31 ? 5'h1f : 5'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_32_T = matchSlotB_32 ? 6'h20 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_33_T = matchSlotB_33 ? 6'h21 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_34_T = matchSlotB_34 ? 6'h22 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_35_T = matchSlotB_35 ? 6'h23 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_36_T = matchSlotB_36 ? 6'h24 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_37_T = matchSlotB_37 ? 6'h25 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_38_T = matchSlotB_38 ? 6'h26 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_39_T = matchSlotB_39 ? 6'h27 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_40_T = matchSlotB_40 ? 6'h28 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_41_T = matchSlotB_41 ? 6'h29 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_42_T = matchSlotB_42 ? 6'h2a : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_43_T = matchSlotB_43 ? 6'h2b : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_44_T = matchSlotB_44 ? 6'h2c : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_45_T = matchSlotB_45 ? 6'h2d : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_46_T = matchSlotB_46 ? 6'h2e : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_47_T = matchSlotB_47 ? 6'h2f : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_48_T = matchSlotB_48 ? 6'h30 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_49_T = matchSlotB_49 ? 6'h31 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_50_T = matchSlotB_50 ? 6'h32 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_51_T = matchSlotB_51 ? 6'h33 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_52_T = matchSlotB_52 ? 6'h34 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_53_T = matchSlotB_53 ? 6'h35 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_54_T = matchSlotB_54 ? 6'h36 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_55_T = matchSlotB_55 ? 6'h37 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_56_T = matchSlotB_56 ? 6'h38 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_57_T = matchSlotB_57 ? 6'h39 : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_58_T = matchSlotB_58 ? 6'h3a : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_59_T = matchSlotB_59 ? 6'h3b : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_60_T = matchSlotB_60 ? 6'h3c : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_61_T = matchSlotB_61 ? 6'h3d : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_62_T = matchSlotB_62 ? 6'h3e : 6'h0; // @[Library.scala 22:8]
- wire [5:0] _readNum_63_T = matchSlotB_63 ? 6'h3f : 6'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_64_T = matchSlotB_64 ? 7'h40 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_65_T = matchSlotB_65 ? 7'h41 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_66_T = matchSlotB_66 ? 7'h42 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_67_T = matchSlotB_67 ? 7'h43 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_68_T = matchSlotB_68 ? 7'h44 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_69_T = matchSlotB_69 ? 7'h45 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_70_T = matchSlotB_70 ? 7'h46 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_71_T = matchSlotB_71 ? 7'h47 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_72_T = matchSlotB_72 ? 7'h48 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_73_T = matchSlotB_73 ? 7'h49 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_74_T = matchSlotB_74 ? 7'h4a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_75_T = matchSlotB_75 ? 7'h4b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_76_T = matchSlotB_76 ? 7'h4c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_77_T = matchSlotB_77 ? 7'h4d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_78_T = matchSlotB_78 ? 7'h4e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_79_T = matchSlotB_79 ? 7'h4f : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_80_T = matchSlotB_80 ? 7'h50 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_81_T = matchSlotB_81 ? 7'h51 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_82_T = matchSlotB_82 ? 7'h52 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_83_T = matchSlotB_83 ? 7'h53 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_84_T = matchSlotB_84 ? 7'h54 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_85_T = matchSlotB_85 ? 7'h55 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_86_T = matchSlotB_86 ? 7'h56 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_87_T = matchSlotB_87 ? 7'h57 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_88_T = matchSlotB_88 ? 7'h58 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_89_T = matchSlotB_89 ? 7'h59 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_90_T = matchSlotB_90 ? 7'h5a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_91_T = matchSlotB_91 ? 7'h5b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_92_T = matchSlotB_92 ? 7'h5c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_93_T = matchSlotB_93 ? 7'h5d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_94_T = matchSlotB_94 ? 7'h5e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_95_T = matchSlotB_95 ? 7'h5f : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_96_T = matchSlotB_96 ? 7'h60 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_97_T = matchSlotB_97 ? 7'h61 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_98_T = matchSlotB_98 ? 7'h62 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_99_T = matchSlotB_99 ? 7'h63 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_100_T = matchSlotB_100 ? 7'h64 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_101_T = matchSlotB_101 ? 7'h65 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_102_T = matchSlotB_102 ? 7'h66 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_103_T = matchSlotB_103 ? 7'h67 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_104_T = matchSlotB_104 ? 7'h68 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_105_T = matchSlotB_105 ? 7'h69 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_106_T = matchSlotB_106 ? 7'h6a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_107_T = matchSlotB_107 ? 7'h6b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_108_T = matchSlotB_108 ? 7'h6c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_109_T = matchSlotB_109 ? 7'h6d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_110_T = matchSlotB_110 ? 7'h6e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_111_T = matchSlotB_111 ? 7'h6f : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_112_T = matchSlotB_112 ? 7'h70 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_113_T = matchSlotB_113 ? 7'h71 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_114_T = matchSlotB_114 ? 7'h72 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_115_T = matchSlotB_115 ? 7'h73 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_116_T = matchSlotB_116 ? 7'h74 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_117_T = matchSlotB_117 ? 7'h75 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_118_T = matchSlotB_118 ? 7'h76 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_119_T = matchSlotB_119 ? 7'h77 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_120_T = matchSlotB_120 ? 7'h78 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_121_T = matchSlotB_121 ? 7'h79 : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_122_T = matchSlotB_122 ? 7'h7a : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_123_T = matchSlotB_123 ? 7'h7b : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_124_T = matchSlotB_124 ? 7'h7c : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_125_T = matchSlotB_125 ? 7'h7d : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_126_T = matchSlotB_126 ? 7'h7e : 7'h0; // @[Library.scala 22:8]
- wire [6:0] _readNum_127_T = matchSlotB_127 ? 7'h7f : 7'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_128 = matchSlotB_128 ? 8'h80 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_129 = matchSlotB_129 ? 8'h81 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_130 = matchSlotB_130 ? 8'h82 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_131 = matchSlotB_131 ? 8'h83 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_132 = matchSlotB_132 ? 8'h84 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_133 = matchSlotB_133 ? 8'h85 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_134 = matchSlotB_134 ? 8'h86 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_135 = matchSlotB_135 ? 8'h87 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_136 = matchSlotB_136 ? 8'h88 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_137 = matchSlotB_137 ? 8'h89 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_138 = matchSlotB_138 ? 8'h8a : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_139 = matchSlotB_139 ? 8'h8b : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_140 = matchSlotB_140 ? 8'h8c : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_141 = matchSlotB_141 ? 8'h8d : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_142 = matchSlotB_142 ? 8'h8e : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_143 = matchSlotB_143 ? 8'h8f : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_144 = matchSlotB_144 ? 8'h90 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_145 = matchSlotB_145 ? 8'h91 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_146 = matchSlotB_146 ? 8'h92 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_147 = matchSlotB_147 ? 8'h93 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_148 = matchSlotB_148 ? 8'h94 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_149 = matchSlotB_149 ? 8'h95 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_150 = matchSlotB_150 ? 8'h96 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_151 = matchSlotB_151 ? 8'h97 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_152 = matchSlotB_152 ? 8'h98 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_153 = matchSlotB_153 ? 8'h99 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_154 = matchSlotB_154 ? 8'h9a : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_155 = matchSlotB_155 ? 8'h9b : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_156 = matchSlotB_156 ? 8'h9c : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_157 = matchSlotB_157 ? 8'h9d : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_158 = matchSlotB_158 ? 8'h9e : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_159 = matchSlotB_159 ? 8'h9f : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_160 = matchSlotB_160 ? 8'ha0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_161 = matchSlotB_161 ? 8'ha1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_162 = matchSlotB_162 ? 8'ha2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_163 = matchSlotB_163 ? 8'ha3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_164 = matchSlotB_164 ? 8'ha4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_165 = matchSlotB_165 ? 8'ha5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_166 = matchSlotB_166 ? 8'ha6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_167 = matchSlotB_167 ? 8'ha7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_168 = matchSlotB_168 ? 8'ha8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_169 = matchSlotB_169 ? 8'ha9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_170 = matchSlotB_170 ? 8'haa : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_171 = matchSlotB_171 ? 8'hab : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_172 = matchSlotB_172 ? 8'hac : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_173 = matchSlotB_173 ? 8'had : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_174 = matchSlotB_174 ? 8'hae : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_175 = matchSlotB_175 ? 8'haf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_176 = matchSlotB_176 ? 8'hb0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_177 = matchSlotB_177 ? 8'hb1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_178 = matchSlotB_178 ? 8'hb2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_179 = matchSlotB_179 ? 8'hb3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_180 = matchSlotB_180 ? 8'hb4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_181 = matchSlotB_181 ? 8'hb5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_182 = matchSlotB_182 ? 8'hb6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_183 = matchSlotB_183 ? 8'hb7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_184 = matchSlotB_184 ? 8'hb8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_185 = matchSlotB_185 ? 8'hb9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_186 = matchSlotB_186 ? 8'hba : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_187 = matchSlotB_187 ? 8'hbb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_188 = matchSlotB_188 ? 8'hbc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_189 = matchSlotB_189 ? 8'hbd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_190 = matchSlotB_190 ? 8'hbe : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_191 = matchSlotB_191 ? 8'hbf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_192 = matchSlotB_192 ? 8'hc0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_193 = matchSlotB_193 ? 8'hc1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_194 = matchSlotB_194 ? 8'hc2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_195 = matchSlotB_195 ? 8'hc3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_196 = matchSlotB_196 ? 8'hc4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_197 = matchSlotB_197 ? 8'hc5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_198 = matchSlotB_198 ? 8'hc6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_199 = matchSlotB_199 ? 8'hc7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_200 = matchSlotB_200 ? 8'hc8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_201 = matchSlotB_201 ? 8'hc9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_202 = matchSlotB_202 ? 8'hca : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_203 = matchSlotB_203 ? 8'hcb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_204 = matchSlotB_204 ? 8'hcc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_205 = matchSlotB_205 ? 8'hcd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_206 = matchSlotB_206 ? 8'hce : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_207 = matchSlotB_207 ? 8'hcf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_208 = matchSlotB_208 ? 8'hd0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_209 = matchSlotB_209 ? 8'hd1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_210 = matchSlotB_210 ? 8'hd2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_211 = matchSlotB_211 ? 8'hd3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_212 = matchSlotB_212 ? 8'hd4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_213 = matchSlotB_213 ? 8'hd5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_214 = matchSlotB_214 ? 8'hd6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_215 = matchSlotB_215 ? 8'hd7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_216 = matchSlotB_216 ? 8'hd8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_217 = matchSlotB_217 ? 8'hd9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_218 = matchSlotB_218 ? 8'hda : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_219 = matchSlotB_219 ? 8'hdb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_220 = matchSlotB_220 ? 8'hdc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_221 = matchSlotB_221 ? 8'hdd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_222 = matchSlotB_222 ? 8'hde : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_223 = matchSlotB_223 ? 8'hdf : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_224 = matchSlotB_224 ? 8'he0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_225 = matchSlotB_225 ? 8'he1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_226 = matchSlotB_226 ? 8'he2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_227 = matchSlotB_227 ? 8'he3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_228 = matchSlotB_228 ? 8'he4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_229 = matchSlotB_229 ? 8'he5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_230 = matchSlotB_230 ? 8'he6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_231 = matchSlotB_231 ? 8'he7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_232 = matchSlotB_232 ? 8'he8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_233 = matchSlotB_233 ? 8'he9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_234 = matchSlotB_234 ? 8'hea : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_235 = matchSlotB_235 ? 8'heb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_236 = matchSlotB_236 ? 8'hec : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_237 = matchSlotB_237 ? 8'hed : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_238 = matchSlotB_238 ? 8'hee : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_239 = matchSlotB_239 ? 8'hef : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_240 = matchSlotB_240 ? 8'hf0 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_241 = matchSlotB_241 ? 8'hf1 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_242 = matchSlotB_242 ? 8'hf2 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_243 = matchSlotB_243 ? 8'hf3 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_244 = matchSlotB_244 ? 8'hf4 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_245 = matchSlotB_245 ? 8'hf5 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_246 = matchSlotB_246 ? 8'hf6 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_247 = matchSlotB_247 ? 8'hf7 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_248 = matchSlotB_248 ? 8'hf8 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_249 = matchSlotB_249 ? 8'hf9 : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_250 = matchSlotB_250 ? 8'hfa : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_251 = matchSlotB_251 ? 8'hfb : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_252 = matchSlotB_252 ? 8'hfc : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_253 = matchSlotB_253 ? 8'hfd : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_254 = matchSlotB_254 ? 8'hfe : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_255 = matchSlotB_255 ? 8'hff : 8'h0; // @[Library.scala 22:8]
- wire [7:0] readNum_1 = {{7'd0}, matchSlotB_1}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] readNum_2 = {{6'd0}, _readNum_2_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_2 = readNum_1 | readNum_2; // @[Library.scala 76:39]
- wire [7:0] readNum_3 = {{6'd0}, _readNum_3_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_3 = _readId_T_2 | readNum_3; // @[Library.scala 76:39]
- wire [7:0] readNum_4 = {{5'd0}, _readNum_4_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_4 = _readId_T_3 | readNum_4; // @[Library.scala 76:39]
- wire [7:0] readNum_5 = {{5'd0}, _readNum_5_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_5 = _readId_T_4 | readNum_5; // @[Library.scala 76:39]
- wire [7:0] readNum_6 = {{5'd0}, _readNum_6_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_6 = _readId_T_5 | readNum_6; // @[Library.scala 76:39]
- wire [7:0] readNum_7 = {{5'd0}, _readNum_7_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_7 = _readId_T_6 | readNum_7; // @[Library.scala 76:39]
- wire [7:0] readNum_8 = {{4'd0}, _readNum_8_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_8 = _readId_T_7 | readNum_8; // @[Library.scala 76:39]
- wire [7:0] readNum_9 = {{4'd0}, _readNum_9_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_9 = _readId_T_8 | readNum_9; // @[Library.scala 76:39]
- wire [7:0] readNum_10 = {{4'd0}, _readNum_10_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_10 = _readId_T_9 | readNum_10; // @[Library.scala 76:39]
- wire [7:0] readNum_11 = {{4'd0}, _readNum_11_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_11 = _readId_T_10 | readNum_11; // @[Library.scala 76:39]
- wire [7:0] readNum_12 = {{4'd0}, _readNum_12_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_12 = _readId_T_11 | readNum_12; // @[Library.scala 76:39]
- wire [7:0] readNum_13 = {{4'd0}, _readNum_13_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_13 = _readId_T_12 | readNum_13; // @[Library.scala 76:39]
- wire [7:0] readNum_14 = {{4'd0}, _readNum_14_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_14 = _readId_T_13 | readNum_14; // @[Library.scala 76:39]
- wire [7:0] readNum_15 = {{4'd0}, _readNum_15_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_15 = _readId_T_14 | readNum_15; // @[Library.scala 76:39]
- wire [7:0] readNum_16 = {{3'd0}, _readNum_16_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_16 = _readId_T_15 | readNum_16; // @[Library.scala 76:39]
- wire [7:0] readNum_17 = {{3'd0}, _readNum_17_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_17 = _readId_T_16 | readNum_17; // @[Library.scala 76:39]
- wire [7:0] readNum_18 = {{3'd0}, _readNum_18_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_18 = _readId_T_17 | readNum_18; // @[Library.scala 76:39]
- wire [7:0] readNum_19 = {{3'd0}, _readNum_19_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_19 = _readId_T_18 | readNum_19; // @[Library.scala 76:39]
- wire [7:0] readNum_20 = {{3'd0}, _readNum_20_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_20 = _readId_T_19 | readNum_20; // @[Library.scala 76:39]
- wire [7:0] readNum_21 = {{3'd0}, _readNum_21_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_21 = _readId_T_20 | readNum_21; // @[Library.scala 76:39]
- wire [7:0] readNum_22 = {{3'd0}, _readNum_22_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_22 = _readId_T_21 | readNum_22; // @[Library.scala 76:39]
- wire [7:0] readNum_23 = {{3'd0}, _readNum_23_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_23 = _readId_T_22 | readNum_23; // @[Library.scala 76:39]
- wire [7:0] readNum_24 = {{3'd0}, _readNum_24_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_24 = _readId_T_23 | readNum_24; // @[Library.scala 76:39]
- wire [7:0] readNum_25 = {{3'd0}, _readNum_25_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_25 = _readId_T_24 | readNum_25; // @[Library.scala 76:39]
- wire [7:0] readNum_26 = {{3'd0}, _readNum_26_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_26 = _readId_T_25 | readNum_26; // @[Library.scala 76:39]
- wire [7:0] readNum_27 = {{3'd0}, _readNum_27_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_27 = _readId_T_26 | readNum_27; // @[Library.scala 76:39]
- wire [7:0] readNum_28 = {{3'd0}, _readNum_28_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_28 = _readId_T_27 | readNum_28; // @[Library.scala 76:39]
- wire [7:0] readNum_29 = {{3'd0}, _readNum_29_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_29 = _readId_T_28 | readNum_29; // @[Library.scala 76:39]
- wire [7:0] readNum_30 = {{3'd0}, _readNum_30_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_30 = _readId_T_29 | readNum_30; // @[Library.scala 76:39]
- wire [7:0] readNum_31 = {{3'd0}, _readNum_31_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_31 = _readId_T_30 | readNum_31; // @[Library.scala 76:39]
- wire [7:0] readNum_32 = {{2'd0}, _readNum_32_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_32 = _readId_T_31 | readNum_32; // @[Library.scala 76:39]
- wire [7:0] readNum_33 = {{2'd0}, _readNum_33_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_33 = _readId_T_32 | readNum_33; // @[Library.scala 76:39]
- wire [7:0] readNum_34 = {{2'd0}, _readNum_34_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_34 = _readId_T_33 | readNum_34; // @[Library.scala 76:39]
- wire [7:0] readNum_35 = {{2'd0}, _readNum_35_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_35 = _readId_T_34 | readNum_35; // @[Library.scala 76:39]
- wire [7:0] readNum_36 = {{2'd0}, _readNum_36_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_36 = _readId_T_35 | readNum_36; // @[Library.scala 76:39]
- wire [7:0] readNum_37 = {{2'd0}, _readNum_37_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_37 = _readId_T_36 | readNum_37; // @[Library.scala 76:39]
- wire [7:0] readNum_38 = {{2'd0}, _readNum_38_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_38 = _readId_T_37 | readNum_38; // @[Library.scala 76:39]
- wire [7:0] readNum_39 = {{2'd0}, _readNum_39_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_39 = _readId_T_38 | readNum_39; // @[Library.scala 76:39]
- wire [7:0] readNum_40 = {{2'd0}, _readNum_40_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_40 = _readId_T_39 | readNum_40; // @[Library.scala 76:39]
- wire [7:0] readNum_41 = {{2'd0}, _readNum_41_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_41 = _readId_T_40 | readNum_41; // @[Library.scala 76:39]
- wire [7:0] readNum_42 = {{2'd0}, _readNum_42_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_42 = _readId_T_41 | readNum_42; // @[Library.scala 76:39]
- wire [7:0] readNum_43 = {{2'd0}, _readNum_43_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_43 = _readId_T_42 | readNum_43; // @[Library.scala 76:39]
- wire [7:0] readNum_44 = {{2'd0}, _readNum_44_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_44 = _readId_T_43 | readNum_44; // @[Library.scala 76:39]
- wire [7:0] readNum_45 = {{2'd0}, _readNum_45_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_45 = _readId_T_44 | readNum_45; // @[Library.scala 76:39]
- wire [7:0] readNum_46 = {{2'd0}, _readNum_46_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_46 = _readId_T_45 | readNum_46; // @[Library.scala 76:39]
- wire [7:0] readNum_47 = {{2'd0}, _readNum_47_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_47 = _readId_T_46 | readNum_47; // @[Library.scala 76:39]
- wire [7:0] readNum_48 = {{2'd0}, _readNum_48_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_48 = _readId_T_47 | readNum_48; // @[Library.scala 76:39]
- wire [7:0] readNum_49 = {{2'd0}, _readNum_49_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_49 = _readId_T_48 | readNum_49; // @[Library.scala 76:39]
- wire [7:0] readNum_50 = {{2'd0}, _readNum_50_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_50 = _readId_T_49 | readNum_50; // @[Library.scala 76:39]
- wire [7:0] readNum_51 = {{2'd0}, _readNum_51_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_51 = _readId_T_50 | readNum_51; // @[Library.scala 76:39]
- wire [7:0] readNum_52 = {{2'd0}, _readNum_52_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_52 = _readId_T_51 | readNum_52; // @[Library.scala 76:39]
- wire [7:0] readNum_53 = {{2'd0}, _readNum_53_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_53 = _readId_T_52 | readNum_53; // @[Library.scala 76:39]
- wire [7:0] readNum_54 = {{2'd0}, _readNum_54_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_54 = _readId_T_53 | readNum_54; // @[Library.scala 76:39]
- wire [7:0] readNum_55 = {{2'd0}, _readNum_55_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_55 = _readId_T_54 | readNum_55; // @[Library.scala 76:39]
- wire [7:0] readNum_56 = {{2'd0}, _readNum_56_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_56 = _readId_T_55 | readNum_56; // @[Library.scala 76:39]
- wire [7:0] readNum_57 = {{2'd0}, _readNum_57_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_57 = _readId_T_56 | readNum_57; // @[Library.scala 76:39]
- wire [7:0] readNum_58 = {{2'd0}, _readNum_58_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_58 = _readId_T_57 | readNum_58; // @[Library.scala 76:39]
- wire [7:0] readNum_59 = {{2'd0}, _readNum_59_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_59 = _readId_T_58 | readNum_59; // @[Library.scala 76:39]
- wire [7:0] readNum_60 = {{2'd0}, _readNum_60_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_60 = _readId_T_59 | readNum_60; // @[Library.scala 76:39]
- wire [7:0] readNum_61 = {{2'd0}, _readNum_61_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_61 = _readId_T_60 | readNum_61; // @[Library.scala 76:39]
- wire [7:0] readNum_62 = {{2'd0}, _readNum_62_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_62 = _readId_T_61 | readNum_62; // @[Library.scala 76:39]
- wire [7:0] readNum_63 = {{2'd0}, _readNum_63_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_63 = _readId_T_62 | readNum_63; // @[Library.scala 76:39]
- wire [7:0] readNum_64 = {{1'd0}, _readNum_64_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_64 = _readId_T_63 | readNum_64; // @[Library.scala 76:39]
- wire [7:0] readNum_65 = {{1'd0}, _readNum_65_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_65 = _readId_T_64 | readNum_65; // @[Library.scala 76:39]
- wire [7:0] readNum_66 = {{1'd0}, _readNum_66_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_66 = _readId_T_65 | readNum_66; // @[Library.scala 76:39]
- wire [7:0] readNum_67 = {{1'd0}, _readNum_67_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_67 = _readId_T_66 | readNum_67; // @[Library.scala 76:39]
- wire [7:0] readNum_68 = {{1'd0}, _readNum_68_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_68 = _readId_T_67 | readNum_68; // @[Library.scala 76:39]
- wire [7:0] readNum_69 = {{1'd0}, _readNum_69_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_69 = _readId_T_68 | readNum_69; // @[Library.scala 76:39]
- wire [7:0] readNum_70 = {{1'd0}, _readNum_70_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_70 = _readId_T_69 | readNum_70; // @[Library.scala 76:39]
- wire [7:0] readNum_71 = {{1'd0}, _readNum_71_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_71 = _readId_T_70 | readNum_71; // @[Library.scala 76:39]
- wire [7:0] readNum_72 = {{1'd0}, _readNum_72_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_72 = _readId_T_71 | readNum_72; // @[Library.scala 76:39]
- wire [7:0] readNum_73 = {{1'd0}, _readNum_73_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_73 = _readId_T_72 | readNum_73; // @[Library.scala 76:39]
- wire [7:0] readNum_74 = {{1'd0}, _readNum_74_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_74 = _readId_T_73 | readNum_74; // @[Library.scala 76:39]
- wire [7:0] readNum_75 = {{1'd0}, _readNum_75_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_75 = _readId_T_74 | readNum_75; // @[Library.scala 76:39]
- wire [7:0] readNum_76 = {{1'd0}, _readNum_76_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_76 = _readId_T_75 | readNum_76; // @[Library.scala 76:39]
- wire [7:0] readNum_77 = {{1'd0}, _readNum_77_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_77 = _readId_T_76 | readNum_77; // @[Library.scala 76:39]
- wire [7:0] readNum_78 = {{1'd0}, _readNum_78_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_78 = _readId_T_77 | readNum_78; // @[Library.scala 76:39]
- wire [7:0] readNum_79 = {{1'd0}, _readNum_79_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_79 = _readId_T_78 | readNum_79; // @[Library.scala 76:39]
- wire [7:0] readNum_80 = {{1'd0}, _readNum_80_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_80 = _readId_T_79 | readNum_80; // @[Library.scala 76:39]
- wire [7:0] readNum_81 = {{1'd0}, _readNum_81_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_81 = _readId_T_80 | readNum_81; // @[Library.scala 76:39]
- wire [7:0] readNum_82 = {{1'd0}, _readNum_82_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_82 = _readId_T_81 | readNum_82; // @[Library.scala 76:39]
- wire [7:0] readNum_83 = {{1'd0}, _readNum_83_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_83 = _readId_T_82 | readNum_83; // @[Library.scala 76:39]
- wire [7:0] readNum_84 = {{1'd0}, _readNum_84_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_84 = _readId_T_83 | readNum_84; // @[Library.scala 76:39]
- wire [7:0] readNum_85 = {{1'd0}, _readNum_85_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_85 = _readId_T_84 | readNum_85; // @[Library.scala 76:39]
- wire [7:0] readNum_86 = {{1'd0}, _readNum_86_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_86 = _readId_T_85 | readNum_86; // @[Library.scala 76:39]
- wire [7:0] readNum_87 = {{1'd0}, _readNum_87_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_87 = _readId_T_86 | readNum_87; // @[Library.scala 76:39]
- wire [7:0] readNum_88 = {{1'd0}, _readNum_88_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_88 = _readId_T_87 | readNum_88; // @[Library.scala 76:39]
- wire [7:0] readNum_89 = {{1'd0}, _readNum_89_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_89 = _readId_T_88 | readNum_89; // @[Library.scala 76:39]
- wire [7:0] readNum_90 = {{1'd0}, _readNum_90_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_90 = _readId_T_89 | readNum_90; // @[Library.scala 76:39]
- wire [7:0] readNum_91 = {{1'd0}, _readNum_91_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_91 = _readId_T_90 | readNum_91; // @[Library.scala 76:39]
- wire [7:0] readNum_92 = {{1'd0}, _readNum_92_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_92 = _readId_T_91 | readNum_92; // @[Library.scala 76:39]
- wire [7:0] readNum_93 = {{1'd0}, _readNum_93_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_93 = _readId_T_92 | readNum_93; // @[Library.scala 76:39]
- wire [7:0] readNum_94 = {{1'd0}, _readNum_94_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_94 = _readId_T_93 | readNum_94; // @[Library.scala 76:39]
- wire [7:0] readNum_95 = {{1'd0}, _readNum_95_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_95 = _readId_T_94 | readNum_95; // @[Library.scala 76:39]
- wire [7:0] readNum_96 = {{1'd0}, _readNum_96_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_96 = _readId_T_95 | readNum_96; // @[Library.scala 76:39]
- wire [7:0] readNum_97 = {{1'd0}, _readNum_97_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_97 = _readId_T_96 | readNum_97; // @[Library.scala 76:39]
- wire [7:0] readNum_98 = {{1'd0}, _readNum_98_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_98 = _readId_T_97 | readNum_98; // @[Library.scala 76:39]
- wire [7:0] readNum_99 = {{1'd0}, _readNum_99_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_99 = _readId_T_98 | readNum_99; // @[Library.scala 76:39]
- wire [7:0] readNum_100 = {{1'd0}, _readNum_100_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_100 = _readId_T_99 | readNum_100; // @[Library.scala 76:39]
- wire [7:0] readNum_101 = {{1'd0}, _readNum_101_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_101 = _readId_T_100 | readNum_101; // @[Library.scala 76:39]
- wire [7:0] readNum_102 = {{1'd0}, _readNum_102_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_102 = _readId_T_101 | readNum_102; // @[Library.scala 76:39]
- wire [7:0] readNum_103 = {{1'd0}, _readNum_103_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_103 = _readId_T_102 | readNum_103; // @[Library.scala 76:39]
- wire [7:0] readNum_104 = {{1'd0}, _readNum_104_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_104 = _readId_T_103 | readNum_104; // @[Library.scala 76:39]
- wire [7:0] readNum_105 = {{1'd0}, _readNum_105_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_105 = _readId_T_104 | readNum_105; // @[Library.scala 76:39]
- wire [7:0] readNum_106 = {{1'd0}, _readNum_106_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_106 = _readId_T_105 | readNum_106; // @[Library.scala 76:39]
- wire [7:0] readNum_107 = {{1'd0}, _readNum_107_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_107 = _readId_T_106 | readNum_107; // @[Library.scala 76:39]
- wire [7:0] readNum_108 = {{1'd0}, _readNum_108_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_108 = _readId_T_107 | readNum_108; // @[Library.scala 76:39]
- wire [7:0] readNum_109 = {{1'd0}, _readNum_109_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_109 = _readId_T_108 | readNum_109; // @[Library.scala 76:39]
- wire [7:0] readNum_110 = {{1'd0}, _readNum_110_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_110 = _readId_T_109 | readNum_110; // @[Library.scala 76:39]
- wire [7:0] readNum_111 = {{1'd0}, _readNum_111_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_111 = _readId_T_110 | readNum_111; // @[Library.scala 76:39]
- wire [7:0] readNum_112 = {{1'd0}, _readNum_112_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_112 = _readId_T_111 | readNum_112; // @[Library.scala 76:39]
- wire [7:0] readNum_113 = {{1'd0}, _readNum_113_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_113 = _readId_T_112 | readNum_113; // @[Library.scala 76:39]
- wire [7:0] readNum_114 = {{1'd0}, _readNum_114_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_114 = _readId_T_113 | readNum_114; // @[Library.scala 76:39]
- wire [7:0] readNum_115 = {{1'd0}, _readNum_115_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_115 = _readId_T_114 | readNum_115; // @[Library.scala 76:39]
- wire [7:0] readNum_116 = {{1'd0}, _readNum_116_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_116 = _readId_T_115 | readNum_116; // @[Library.scala 76:39]
- wire [7:0] readNum_117 = {{1'd0}, _readNum_117_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_117 = _readId_T_116 | readNum_117; // @[Library.scala 76:39]
- wire [7:0] readNum_118 = {{1'd0}, _readNum_118_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_118 = _readId_T_117 | readNum_118; // @[Library.scala 76:39]
- wire [7:0] readNum_119 = {{1'd0}, _readNum_119_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_119 = _readId_T_118 | readNum_119; // @[Library.scala 76:39]
- wire [7:0] readNum_120 = {{1'd0}, _readNum_120_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_120 = _readId_T_119 | readNum_120; // @[Library.scala 76:39]
- wire [7:0] readNum_121 = {{1'd0}, _readNum_121_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_121 = _readId_T_120 | readNum_121; // @[Library.scala 76:39]
- wire [7:0] readNum_122 = {{1'd0}, _readNum_122_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_122 = _readId_T_121 | readNum_122; // @[Library.scala 76:39]
- wire [7:0] readNum_123 = {{1'd0}, _readNum_123_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_123 = _readId_T_122 | readNum_123; // @[Library.scala 76:39]
- wire [7:0] readNum_124 = {{1'd0}, _readNum_124_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_124 = _readId_T_123 | readNum_124; // @[Library.scala 76:39]
- wire [7:0] readNum_125 = {{1'd0}, _readNum_125_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_125 = _readId_T_124 | readNum_125; // @[Library.scala 76:39]
- wire [7:0] readNum_126 = {{1'd0}, _readNum_126_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_126 = _readId_T_125 | readNum_126; // @[Library.scala 76:39]
- wire [7:0] readNum_127 = {{1'd0}, _readNum_127_T}; // @[L1ICache.scala 130:21 132:16]
- wire [7:0] _readId_T_127 = _readId_T_126 | readNum_127; // @[Library.scala 76:39]
- wire [7:0] _readId_T_128 = _readId_T_127 | readNum_128; // @[Library.scala 76:39]
- wire [7:0] _readId_T_129 = _readId_T_128 | readNum_129; // @[Library.scala 76:39]
- wire [7:0] _readId_T_130 = _readId_T_129 | readNum_130; // @[Library.scala 76:39]
- wire [7:0] _readId_T_131 = _readId_T_130 | readNum_131; // @[Library.scala 76:39]
- wire [7:0] _readId_T_132 = _readId_T_131 | readNum_132; // @[Library.scala 76:39]
- wire [7:0] _readId_T_133 = _readId_T_132 | readNum_133; // @[Library.scala 76:39]
- wire [7:0] _readId_T_134 = _readId_T_133 | readNum_134; // @[Library.scala 76:39]
- wire [7:0] _readId_T_135 = _readId_T_134 | readNum_135; // @[Library.scala 76:39]
- wire [7:0] _readId_T_136 = _readId_T_135 | readNum_136; // @[Library.scala 76:39]
- wire [7:0] _readId_T_137 = _readId_T_136 | readNum_137; // @[Library.scala 76:39]
- wire [7:0] _readId_T_138 = _readId_T_137 | readNum_138; // @[Library.scala 76:39]
- wire [7:0] _readId_T_139 = _readId_T_138 | readNum_139; // @[Library.scala 76:39]
- wire [7:0] _readId_T_140 = _readId_T_139 | readNum_140; // @[Library.scala 76:39]
- wire [7:0] _readId_T_141 = _readId_T_140 | readNum_141; // @[Library.scala 76:39]
- wire [7:0] _readId_T_142 = _readId_T_141 | readNum_142; // @[Library.scala 76:39]
- wire [7:0] _readId_T_143 = _readId_T_142 | readNum_143; // @[Library.scala 76:39]
- wire [7:0] _readId_T_144 = _readId_T_143 | readNum_144; // @[Library.scala 76:39]
- wire [7:0] _readId_T_145 = _readId_T_144 | readNum_145; // @[Library.scala 76:39]
- wire [7:0] _readId_T_146 = _readId_T_145 | readNum_146; // @[Library.scala 76:39]
- wire [7:0] _readId_T_147 = _readId_T_146 | readNum_147; // @[Library.scala 76:39]
- wire [7:0] _readId_T_148 = _readId_T_147 | readNum_148; // @[Library.scala 76:39]
- wire [7:0] _readId_T_149 = _readId_T_148 | readNum_149; // @[Library.scala 76:39]
- wire [7:0] _readId_T_150 = _readId_T_149 | readNum_150; // @[Library.scala 76:39]
- wire [7:0] _readId_T_151 = _readId_T_150 | readNum_151; // @[Library.scala 76:39]
- wire [7:0] _readId_T_152 = _readId_T_151 | readNum_152; // @[Library.scala 76:39]
- wire [7:0] _readId_T_153 = _readId_T_152 | readNum_153; // @[Library.scala 76:39]
- wire [7:0] _readId_T_154 = _readId_T_153 | readNum_154; // @[Library.scala 76:39]
- wire [7:0] _readId_T_155 = _readId_T_154 | readNum_155; // @[Library.scala 76:39]
- wire [7:0] _readId_T_156 = _readId_T_155 | readNum_156; // @[Library.scala 76:39]
- wire [7:0] _readId_T_157 = _readId_T_156 | readNum_157; // @[Library.scala 76:39]
- wire [7:0] _readId_T_158 = _readId_T_157 | readNum_158; // @[Library.scala 76:39]
- wire [7:0] _readId_T_159 = _readId_T_158 | readNum_159; // @[Library.scala 76:39]
- wire [7:0] _readId_T_160 = _readId_T_159 | readNum_160; // @[Library.scala 76:39]
- wire [7:0] _readId_T_161 = _readId_T_160 | readNum_161; // @[Library.scala 76:39]
- wire [7:0] _readId_T_162 = _readId_T_161 | readNum_162; // @[Library.scala 76:39]
- wire [7:0] _readId_T_163 = _readId_T_162 | readNum_163; // @[Library.scala 76:39]
- wire [7:0] _readId_T_164 = _readId_T_163 | readNum_164; // @[Library.scala 76:39]
- wire [7:0] _readId_T_165 = _readId_T_164 | readNum_165; // @[Library.scala 76:39]
- wire [7:0] _readId_T_166 = _readId_T_165 | readNum_166; // @[Library.scala 76:39]
- wire [7:0] _readId_T_167 = _readId_T_166 | readNum_167; // @[Library.scala 76:39]
- wire [7:0] _readId_T_168 = _readId_T_167 | readNum_168; // @[Library.scala 76:39]
- wire [7:0] _readId_T_169 = _readId_T_168 | readNum_169; // @[Library.scala 76:39]
- wire [7:0] _readId_T_170 = _readId_T_169 | readNum_170; // @[Library.scala 76:39]
- wire [7:0] _readId_T_171 = _readId_T_170 | readNum_171; // @[Library.scala 76:39]
- wire [7:0] _readId_T_172 = _readId_T_171 | readNum_172; // @[Library.scala 76:39]
- wire [7:0] _readId_T_173 = _readId_T_172 | readNum_173; // @[Library.scala 76:39]
- wire [7:0] _readId_T_174 = _readId_T_173 | readNum_174; // @[Library.scala 76:39]
- wire [7:0] _readId_T_175 = _readId_T_174 | readNum_175; // @[Library.scala 76:39]
- wire [7:0] _readId_T_176 = _readId_T_175 | readNum_176; // @[Library.scala 76:39]
- wire [7:0] _readId_T_177 = _readId_T_176 | readNum_177; // @[Library.scala 76:39]
- wire [7:0] _readId_T_178 = _readId_T_177 | readNum_178; // @[Library.scala 76:39]
- wire [7:0] _readId_T_179 = _readId_T_178 | readNum_179; // @[Library.scala 76:39]
- wire [7:0] _readId_T_180 = _readId_T_179 | readNum_180; // @[Library.scala 76:39]
- wire [7:0] _readId_T_181 = _readId_T_180 | readNum_181; // @[Library.scala 76:39]
- wire [7:0] _readId_T_182 = _readId_T_181 | readNum_182; // @[Library.scala 76:39]
- wire [7:0] _readId_T_183 = _readId_T_182 | readNum_183; // @[Library.scala 76:39]
- wire [7:0] _readId_T_184 = _readId_T_183 | readNum_184; // @[Library.scala 76:39]
- wire [7:0] _readId_T_185 = _readId_T_184 | readNum_185; // @[Library.scala 76:39]
- wire [7:0] _readId_T_186 = _readId_T_185 | readNum_186; // @[Library.scala 76:39]
- wire [7:0] _readId_T_187 = _readId_T_186 | readNum_187; // @[Library.scala 76:39]
- wire [7:0] _readId_T_188 = _readId_T_187 | readNum_188; // @[Library.scala 76:39]
- wire [7:0] _readId_T_189 = _readId_T_188 | readNum_189; // @[Library.scala 76:39]
- wire [7:0] _readId_T_190 = _readId_T_189 | readNum_190; // @[Library.scala 76:39]
- wire [7:0] _readId_T_191 = _readId_T_190 | readNum_191; // @[Library.scala 76:39]
- wire [7:0] _readId_T_192 = _readId_T_191 | readNum_192; // @[Library.scala 76:39]
- wire [7:0] _readId_T_193 = _readId_T_192 | readNum_193; // @[Library.scala 76:39]
- wire [7:0] _readId_T_194 = _readId_T_193 | readNum_194; // @[Library.scala 76:39]
- wire [7:0] _readId_T_195 = _readId_T_194 | readNum_195; // @[Library.scala 76:39]
- wire [7:0] _readId_T_196 = _readId_T_195 | readNum_196; // @[Library.scala 76:39]
- wire [7:0] _readId_T_197 = _readId_T_196 | readNum_197; // @[Library.scala 76:39]
- wire [7:0] _readId_T_198 = _readId_T_197 | readNum_198; // @[Library.scala 76:39]
- wire [7:0] _readId_T_199 = _readId_T_198 | readNum_199; // @[Library.scala 76:39]
- wire [7:0] _readId_T_200 = _readId_T_199 | readNum_200; // @[Library.scala 76:39]
- wire [7:0] _readId_T_201 = _readId_T_200 | readNum_201; // @[Library.scala 76:39]
- wire [7:0] _readId_T_202 = _readId_T_201 | readNum_202; // @[Library.scala 76:39]
- wire [7:0] _readId_T_203 = _readId_T_202 | readNum_203; // @[Library.scala 76:39]
- wire [7:0] _readId_T_204 = _readId_T_203 | readNum_204; // @[Library.scala 76:39]
- wire [7:0] _readId_T_205 = _readId_T_204 | readNum_205; // @[Library.scala 76:39]
- wire [7:0] _readId_T_206 = _readId_T_205 | readNum_206; // @[Library.scala 76:39]
- wire [7:0] _readId_T_207 = _readId_T_206 | readNum_207; // @[Library.scala 76:39]
- wire [7:0] _readId_T_208 = _readId_T_207 | readNum_208; // @[Library.scala 76:39]
- wire [7:0] _readId_T_209 = _readId_T_208 | readNum_209; // @[Library.scala 76:39]
- wire [7:0] _readId_T_210 = _readId_T_209 | readNum_210; // @[Library.scala 76:39]
- wire [7:0] _readId_T_211 = _readId_T_210 | readNum_211; // @[Library.scala 76:39]
- wire [7:0] _readId_T_212 = _readId_T_211 | readNum_212; // @[Library.scala 76:39]
- wire [7:0] _readId_T_213 = _readId_T_212 | readNum_213; // @[Library.scala 76:39]
- wire [7:0] _readId_T_214 = _readId_T_213 | readNum_214; // @[Library.scala 76:39]
- wire [7:0] _readId_T_215 = _readId_T_214 | readNum_215; // @[Library.scala 76:39]
- wire [7:0] _readId_T_216 = _readId_T_215 | readNum_216; // @[Library.scala 76:39]
- wire [7:0] _readId_T_217 = _readId_T_216 | readNum_217; // @[Library.scala 76:39]
- wire [7:0] _readId_T_218 = _readId_T_217 | readNum_218; // @[Library.scala 76:39]
- wire [7:0] _readId_T_219 = _readId_T_218 | readNum_219; // @[Library.scala 76:39]
- wire [7:0] _readId_T_220 = _readId_T_219 | readNum_220; // @[Library.scala 76:39]
- wire [7:0] _readId_T_221 = _readId_T_220 | readNum_221; // @[Library.scala 76:39]
- wire [7:0] _readId_T_222 = _readId_T_221 | readNum_222; // @[Library.scala 76:39]
- wire [7:0] _readId_T_223 = _readId_T_222 | readNum_223; // @[Library.scala 76:39]
- wire [7:0] _readId_T_224 = _readId_T_223 | readNum_224; // @[Library.scala 76:39]
- wire [7:0] _readId_T_225 = _readId_T_224 | readNum_225; // @[Library.scala 76:39]
- wire [7:0] _readId_T_226 = _readId_T_225 | readNum_226; // @[Library.scala 76:39]
- wire [7:0] _readId_T_227 = _readId_T_226 | readNum_227; // @[Library.scala 76:39]
- wire [7:0] _readId_T_228 = _readId_T_227 | readNum_228; // @[Library.scala 76:39]
- wire [7:0] _readId_T_229 = _readId_T_228 | readNum_229; // @[Library.scala 76:39]
- wire [7:0] _readId_T_230 = _readId_T_229 | readNum_230; // @[Library.scala 76:39]
- wire [7:0] _readId_T_231 = _readId_T_230 | readNum_231; // @[Library.scala 76:39]
- wire [7:0] _readId_T_232 = _readId_T_231 | readNum_232; // @[Library.scala 76:39]
- wire [7:0] _readId_T_233 = _readId_T_232 | readNum_233; // @[Library.scala 76:39]
- wire [7:0] _readId_T_234 = _readId_T_233 | readNum_234; // @[Library.scala 76:39]
- wire [7:0] _readId_T_235 = _readId_T_234 | readNum_235; // @[Library.scala 76:39]
- wire [7:0] _readId_T_236 = _readId_T_235 | readNum_236; // @[Library.scala 76:39]
- wire [7:0] _readId_T_237 = _readId_T_236 | readNum_237; // @[Library.scala 76:39]
- wire [7:0] _readId_T_238 = _readId_T_237 | readNum_238; // @[Library.scala 76:39]
- wire [7:0] _readId_T_239 = _readId_T_238 | readNum_239; // @[Library.scala 76:39]
- wire [7:0] _readId_T_240 = _readId_T_239 | readNum_240; // @[Library.scala 76:39]
- wire [7:0] _readId_T_241 = _readId_T_240 | readNum_241; // @[Library.scala 76:39]
- wire [7:0] _readId_T_242 = _readId_T_241 | readNum_242; // @[Library.scala 76:39]
- wire [7:0] _readId_T_243 = _readId_T_242 | readNum_243; // @[Library.scala 76:39]
- wire [7:0] _readId_T_244 = _readId_T_243 | readNum_244; // @[Library.scala 76:39]
- wire [7:0] _readId_T_245 = _readId_T_244 | readNum_245; // @[Library.scala 76:39]
- wire [7:0] _readId_T_246 = _readId_T_245 | readNum_246; // @[Library.scala 76:39]
- wire [7:0] _readId_T_247 = _readId_T_246 | readNum_247; // @[Library.scala 76:39]
- wire [7:0] _readId_T_248 = _readId_T_247 | readNum_248; // @[Library.scala 76:39]
- wire [7:0] _readId_T_249 = _readId_T_248 | readNum_249; // @[Library.scala 76:39]
- wire [7:0] _readId_T_250 = _readId_T_249 | readNum_250; // @[Library.scala 76:39]
- wire [7:0] _readId_T_251 = _readId_T_250 | readNum_251; // @[Library.scala 76:39]
- wire [7:0] _readId_T_252 = _readId_T_251 | readNum_252; // @[Library.scala 76:39]
- wire [7:0] _readId_T_253 = _readId_T_252 | readNum_253; // @[Library.scala 76:39]
- wire [7:0] _readId_T_254 = _readId_T_253 | readNum_254; // @[Library.scala 76:39]
- wire [7:0] readId = _readId_T_254 | readNum_255; // @[Library.scala 76:39]
- wire [3:0] matchSet_1 = matchSlot[3:0]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_1544 = matchSet_1[0] + matchSet_1[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1546 = matchSet_1[2] + matchSet_1[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1548 = _T_1544 + _T_1546; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices__2 = matchSet_1[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices__3 = matchSet_1[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices__1 = {{1'd0}, matchSet_1[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_2 = matchIndices__1 | matchIndices__2; // @[Library.scala 76:39]
- wire [1:0] matchIndex = _matchIndex_T_2 | matchIndices__3; // @[Library.scala 76:39]
- wire _T_1557 = io_ibus_valid & io_ibus_ready & setMatch_1; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_1 = 2'h1 == matchIndex ? history_0_1 : history_0_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_2 = 2'h2 == matchIndex ? history_0_2 : _GEN_1; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_3 = 2'h3 == matchIndex ? history_0_3 : _GEN_2; // @[L1ICache.scala 153:{36,36}]
- wire _T_1559 = history_0_0 > _GEN_3; // @[L1ICache.scala 153:36]
- wire [1:0] _history_0_0_T_1 = history_0_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1565 = history_0_1 > _GEN_3; // @[L1ICache.scala 153:36]
- wire [1:0] _history_0_1_T_1 = history_0_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1571 = history_0_2 > _GEN_3; // @[L1ICache.scala 153:36]
- wire [1:0] _history_0_2_T_1 = history_0_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1577 = history_0_3 > _GEN_3; // @[L1ICache.scala 153:36]
- wire [1:0] _history_0_3_T_1 = history_0_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_2 = matchSlot[7:4]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_1586 = matchSet_2[0] + matchSet_2[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1588 = matchSet_2[2] + matchSet_2[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1590 = _T_1586 + _T_1588; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_1_2 = matchSet_2[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_1_3 = matchSet_2[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_1_1 = {{1'd0}, matchSet_2[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_5 = matchIndices_1_1 | matchIndices_1_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_1 = _matchIndex_T_5 | matchIndices_1_3; // @[Library.scala 76:39]
- wire _T_1599 = io_ibus_valid & io_ibus_ready & setMatch_5; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_17 = 2'h1 == matchIndex_1 ? history_1_1 : history_1_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_18 = 2'h2 == matchIndex_1 ? history_1_2 : _GEN_17; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_19 = 2'h3 == matchIndex_1 ? history_1_3 : _GEN_18; // @[L1ICache.scala 153:{36,36}]
- wire _T_1601 = history_1_0 > _GEN_19; // @[L1ICache.scala 153:36]
- wire [1:0] _history_1_0_T_1 = history_1_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1607 = history_1_1 > _GEN_19; // @[L1ICache.scala 153:36]
- wire [1:0] _history_1_1_T_1 = history_1_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1613 = history_1_2 > _GEN_19; // @[L1ICache.scala 153:36]
- wire [1:0] _history_1_2_T_1 = history_1_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1619 = history_1_3 > _GEN_19; // @[L1ICache.scala 153:36]
- wire [1:0] _history_1_3_T_1 = history_1_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_3 = matchSlot[11:8]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_1628 = matchSet_3[0] + matchSet_3[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1630 = matchSet_3[2] + matchSet_3[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1632 = _T_1628 + _T_1630; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_2_2 = matchSet_3[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_2_3 = matchSet_3[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_2_1 = {{1'd0}, matchSet_3[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_8 = matchIndices_2_1 | matchIndices_2_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_2 = _matchIndex_T_8 | matchIndices_2_3; // @[Library.scala 76:39]
- wire _T_1641 = io_ibus_valid & io_ibus_ready & setMatch_9; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_33 = 2'h1 == matchIndex_2 ? history_2_1 : history_2_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_34 = 2'h2 == matchIndex_2 ? history_2_2 : _GEN_33; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_35 = 2'h3 == matchIndex_2 ? history_2_3 : _GEN_34; // @[L1ICache.scala 153:{36,36}]
- wire _T_1643 = history_2_0 > _GEN_35; // @[L1ICache.scala 153:36]
- wire [1:0] _history_2_0_T_1 = history_2_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1649 = history_2_1 > _GEN_35; // @[L1ICache.scala 153:36]
- wire [1:0] _history_2_1_T_1 = history_2_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1655 = history_2_2 > _GEN_35; // @[L1ICache.scala 153:36]
- wire [1:0] _history_2_2_T_1 = history_2_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1661 = history_2_3 > _GEN_35; // @[L1ICache.scala 153:36]
- wire [1:0] _history_2_3_T_1 = history_2_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_4 = matchSlot[15:12]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_1670 = matchSet_4[0] + matchSet_4[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1672 = matchSet_4[2] + matchSet_4[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1674 = _T_1670 + _T_1672; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_3_2 = matchSet_4[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_3_3 = matchSet_4[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_3_1 = {{1'd0}, matchSet_4[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_11 = matchIndices_3_1 | matchIndices_3_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_3 = _matchIndex_T_11 | matchIndices_3_3; // @[Library.scala 76:39]
- wire _T_1683 = io_ibus_valid & io_ibus_ready & setMatch_13; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_49 = 2'h1 == matchIndex_3 ? history_3_1 : history_3_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_50 = 2'h2 == matchIndex_3 ? history_3_2 : _GEN_49; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_51 = 2'h3 == matchIndex_3 ? history_3_3 : _GEN_50; // @[L1ICache.scala 153:{36,36}]
- wire _T_1685 = history_3_0 > _GEN_51; // @[L1ICache.scala 153:36]
- wire [1:0] _history_3_0_T_1 = history_3_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1691 = history_3_1 > _GEN_51; // @[L1ICache.scala 153:36]
- wire [1:0] _history_3_1_T_1 = history_3_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1697 = history_3_2 > _GEN_51; // @[L1ICache.scala 153:36]
- wire [1:0] _history_3_2_T_1 = history_3_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1703 = history_3_3 > _GEN_51; // @[L1ICache.scala 153:36]
- wire [1:0] _history_3_3_T_1 = history_3_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_5 = matchSlot[19:16]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_1712 = matchSet_5[0] + matchSet_5[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1714 = matchSet_5[2] + matchSet_5[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1716 = _T_1712 + _T_1714; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_4_2 = matchSet_5[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_4_3 = matchSet_5[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_4_1 = {{1'd0}, matchSet_5[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_14 = matchIndices_4_1 | matchIndices_4_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_4 = _matchIndex_T_14 | matchIndices_4_3; // @[Library.scala 76:39]
- wire _T_1725 = io_ibus_valid & io_ibus_ready & setMatch_17; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_65 = 2'h1 == matchIndex_4 ? history_4_1 : history_4_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_66 = 2'h2 == matchIndex_4 ? history_4_2 : _GEN_65; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_67 = 2'h3 == matchIndex_4 ? history_4_3 : _GEN_66; // @[L1ICache.scala 153:{36,36}]
- wire _T_1727 = history_4_0 > _GEN_67; // @[L1ICache.scala 153:36]
- wire [1:0] _history_4_0_T_1 = history_4_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1733 = history_4_1 > _GEN_67; // @[L1ICache.scala 153:36]
- wire [1:0] _history_4_1_T_1 = history_4_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1739 = history_4_2 > _GEN_67; // @[L1ICache.scala 153:36]
- wire [1:0] _history_4_2_T_1 = history_4_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1745 = history_4_3 > _GEN_67; // @[L1ICache.scala 153:36]
- wire [1:0] _history_4_3_T_1 = history_4_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_6 = matchSlot[23:20]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_1754 = matchSet_6[0] + matchSet_6[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1756 = matchSet_6[2] + matchSet_6[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1758 = _T_1754 + _T_1756; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_5_2 = matchSet_6[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_5_3 = matchSet_6[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_5_1 = {{1'd0}, matchSet_6[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_17 = matchIndices_5_1 | matchIndices_5_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_5 = _matchIndex_T_17 | matchIndices_5_3; // @[Library.scala 76:39]
- wire _T_1767 = io_ibus_valid & io_ibus_ready & setMatch_21; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_81 = 2'h1 == matchIndex_5 ? history_5_1 : history_5_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_82 = 2'h2 == matchIndex_5 ? history_5_2 : _GEN_81; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_83 = 2'h3 == matchIndex_5 ? history_5_3 : _GEN_82; // @[L1ICache.scala 153:{36,36}]
- wire _T_1769 = history_5_0 > _GEN_83; // @[L1ICache.scala 153:36]
- wire [1:0] _history_5_0_T_1 = history_5_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1775 = history_5_1 > _GEN_83; // @[L1ICache.scala 153:36]
- wire [1:0] _history_5_1_T_1 = history_5_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1781 = history_5_2 > _GEN_83; // @[L1ICache.scala 153:36]
- wire [1:0] _history_5_2_T_1 = history_5_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1787 = history_5_3 > _GEN_83; // @[L1ICache.scala 153:36]
- wire [1:0] _history_5_3_T_1 = history_5_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_7 = matchSlot[27:24]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_1796 = matchSet_7[0] + matchSet_7[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1798 = matchSet_7[2] + matchSet_7[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1800 = _T_1796 + _T_1798; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_6_2 = matchSet_7[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_6_3 = matchSet_7[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_6_1 = {{1'd0}, matchSet_7[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_20 = matchIndices_6_1 | matchIndices_6_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_6 = _matchIndex_T_20 | matchIndices_6_3; // @[Library.scala 76:39]
- wire _T_1809 = io_ibus_valid & io_ibus_ready & setMatch_25; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_97 = 2'h1 == matchIndex_6 ? history_6_1 : history_6_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_98 = 2'h2 == matchIndex_6 ? history_6_2 : _GEN_97; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_99 = 2'h3 == matchIndex_6 ? history_6_3 : _GEN_98; // @[L1ICache.scala 153:{36,36}]
- wire _T_1811 = history_6_0 > _GEN_99; // @[L1ICache.scala 153:36]
- wire [1:0] _history_6_0_T_1 = history_6_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1817 = history_6_1 > _GEN_99; // @[L1ICache.scala 153:36]
- wire [1:0] _history_6_1_T_1 = history_6_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1823 = history_6_2 > _GEN_99; // @[L1ICache.scala 153:36]
- wire [1:0] _history_6_2_T_1 = history_6_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1829 = history_6_3 > _GEN_99; // @[L1ICache.scala 153:36]
- wire [1:0] _history_6_3_T_1 = history_6_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_8 = matchSlot[31:28]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_1838 = matchSet_8[0] + matchSet_8[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1840 = matchSet_8[2] + matchSet_8[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1842 = _T_1838 + _T_1840; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_7_2 = matchSet_8[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_7_3 = matchSet_8[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_7_1 = {{1'd0}, matchSet_8[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_23 = matchIndices_7_1 | matchIndices_7_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_7 = _matchIndex_T_23 | matchIndices_7_3; // @[Library.scala 76:39]
- wire _T_1851 = io_ibus_valid & io_ibus_ready & setMatch_29; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_113 = 2'h1 == matchIndex_7 ? history_7_1 : history_7_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_114 = 2'h2 == matchIndex_7 ? history_7_2 : _GEN_113; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_115 = 2'h3 == matchIndex_7 ? history_7_3 : _GEN_114; // @[L1ICache.scala 153:{36,36}]
- wire _T_1853 = history_7_0 > _GEN_115; // @[L1ICache.scala 153:36]
- wire [1:0] _history_7_0_T_1 = history_7_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1859 = history_7_1 > _GEN_115; // @[L1ICache.scala 153:36]
- wire [1:0] _history_7_1_T_1 = history_7_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1865 = history_7_2 > _GEN_115; // @[L1ICache.scala 153:36]
- wire [1:0] _history_7_2_T_1 = history_7_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1871 = history_7_3 > _GEN_115; // @[L1ICache.scala 153:36]
- wire [1:0] _history_7_3_T_1 = history_7_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_9 = matchSlot[35:32]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_1880 = matchSet_9[0] + matchSet_9[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1882 = matchSet_9[2] + matchSet_9[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1884 = _T_1880 + _T_1882; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_8_2 = matchSet_9[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_8_3 = matchSet_9[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_8_1 = {{1'd0}, matchSet_9[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_26 = matchIndices_8_1 | matchIndices_8_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_8 = _matchIndex_T_26 | matchIndices_8_3; // @[Library.scala 76:39]
- wire _T_1893 = io_ibus_valid & io_ibus_ready & setMatch_33; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_129 = 2'h1 == matchIndex_8 ? history_8_1 : history_8_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_130 = 2'h2 == matchIndex_8 ? history_8_2 : _GEN_129; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_131 = 2'h3 == matchIndex_8 ? history_8_3 : _GEN_130; // @[L1ICache.scala 153:{36,36}]
- wire _T_1895 = history_8_0 > _GEN_131; // @[L1ICache.scala 153:36]
- wire [1:0] _history_8_0_T_1 = history_8_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1901 = history_8_1 > _GEN_131; // @[L1ICache.scala 153:36]
- wire [1:0] _history_8_1_T_1 = history_8_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1907 = history_8_2 > _GEN_131; // @[L1ICache.scala 153:36]
- wire [1:0] _history_8_2_T_1 = history_8_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1913 = history_8_3 > _GEN_131; // @[L1ICache.scala 153:36]
- wire [1:0] _history_8_3_T_1 = history_8_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_10 = matchSlot[39:36]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_1922 = matchSet_10[0] + matchSet_10[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1924 = matchSet_10[2] + matchSet_10[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1926 = _T_1922 + _T_1924; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_9_2 = matchSet_10[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_9_3 = matchSet_10[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_9_1 = {{1'd0}, matchSet_10[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_29 = matchIndices_9_1 | matchIndices_9_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_9 = _matchIndex_T_29 | matchIndices_9_3; // @[Library.scala 76:39]
- wire _T_1935 = io_ibus_valid & io_ibus_ready & setMatch_37; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_145 = 2'h1 == matchIndex_9 ? history_9_1 : history_9_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_146 = 2'h2 == matchIndex_9 ? history_9_2 : _GEN_145; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_147 = 2'h3 == matchIndex_9 ? history_9_3 : _GEN_146; // @[L1ICache.scala 153:{36,36}]
- wire _T_1937 = history_9_0 > _GEN_147; // @[L1ICache.scala 153:36]
- wire [1:0] _history_9_0_T_1 = history_9_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1943 = history_9_1 > _GEN_147; // @[L1ICache.scala 153:36]
- wire [1:0] _history_9_1_T_1 = history_9_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1949 = history_9_2 > _GEN_147; // @[L1ICache.scala 153:36]
- wire [1:0] _history_9_2_T_1 = history_9_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1955 = history_9_3 > _GEN_147; // @[L1ICache.scala 153:36]
- wire [1:0] _history_9_3_T_1 = history_9_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_11 = matchSlot[43:40]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_1964 = matchSet_11[0] + matchSet_11[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_1966 = matchSet_11[2] + matchSet_11[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_1968 = _T_1964 + _T_1966; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_10_2 = matchSet_11[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_10_3 = matchSet_11[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_10_1 = {{1'd0}, matchSet_11[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_32 = matchIndices_10_1 | matchIndices_10_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_10 = _matchIndex_T_32 | matchIndices_10_3; // @[Library.scala 76:39]
- wire _T_1977 = io_ibus_valid & io_ibus_ready & setMatch_41; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_161 = 2'h1 == matchIndex_10 ? history_10_1 : history_10_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_162 = 2'h2 == matchIndex_10 ? history_10_2 : _GEN_161; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_163 = 2'h3 == matchIndex_10 ? history_10_3 : _GEN_162; // @[L1ICache.scala 153:{36,36}]
- wire _T_1979 = history_10_0 > _GEN_163; // @[L1ICache.scala 153:36]
- wire [1:0] _history_10_0_T_1 = history_10_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1985 = history_10_1 > _GEN_163; // @[L1ICache.scala 153:36]
- wire [1:0] _history_10_1_T_1 = history_10_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1991 = history_10_2 > _GEN_163; // @[L1ICache.scala 153:36]
- wire [1:0] _history_10_2_T_1 = history_10_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_1997 = history_10_3 > _GEN_163; // @[L1ICache.scala 153:36]
- wire [1:0] _history_10_3_T_1 = history_10_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_12 = matchSlot[47:44]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2006 = matchSet_12[0] + matchSet_12[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2008 = matchSet_12[2] + matchSet_12[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2010 = _T_2006 + _T_2008; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_11_2 = matchSet_12[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_11_3 = matchSet_12[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_11_1 = {{1'd0}, matchSet_12[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_35 = matchIndices_11_1 | matchIndices_11_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_11 = _matchIndex_T_35 | matchIndices_11_3; // @[Library.scala 76:39]
- wire _T_2019 = io_ibus_valid & io_ibus_ready & setMatch_45; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_177 = 2'h1 == matchIndex_11 ? history_11_1 : history_11_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_178 = 2'h2 == matchIndex_11 ? history_11_2 : _GEN_177; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_179 = 2'h3 == matchIndex_11 ? history_11_3 : _GEN_178; // @[L1ICache.scala 153:{36,36}]
- wire _T_2021 = history_11_0 > _GEN_179; // @[L1ICache.scala 153:36]
- wire [1:0] _history_11_0_T_1 = history_11_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2027 = history_11_1 > _GEN_179; // @[L1ICache.scala 153:36]
- wire [1:0] _history_11_1_T_1 = history_11_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2033 = history_11_2 > _GEN_179; // @[L1ICache.scala 153:36]
- wire [1:0] _history_11_2_T_1 = history_11_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2039 = history_11_3 > _GEN_179; // @[L1ICache.scala 153:36]
- wire [1:0] _history_11_3_T_1 = history_11_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_13 = matchSlot[51:48]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2048 = matchSet_13[0] + matchSet_13[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2050 = matchSet_13[2] + matchSet_13[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2052 = _T_2048 + _T_2050; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_12_2 = matchSet_13[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_12_3 = matchSet_13[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_12_1 = {{1'd0}, matchSet_13[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_38 = matchIndices_12_1 | matchIndices_12_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_12 = _matchIndex_T_38 | matchIndices_12_3; // @[Library.scala 76:39]
- wire _T_2061 = io_ibus_valid & io_ibus_ready & setMatch_49; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_193 = 2'h1 == matchIndex_12 ? history_12_1 : history_12_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_194 = 2'h2 == matchIndex_12 ? history_12_2 : _GEN_193; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_195 = 2'h3 == matchIndex_12 ? history_12_3 : _GEN_194; // @[L1ICache.scala 153:{36,36}]
- wire _T_2063 = history_12_0 > _GEN_195; // @[L1ICache.scala 153:36]
- wire [1:0] _history_12_0_T_1 = history_12_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2069 = history_12_1 > _GEN_195; // @[L1ICache.scala 153:36]
- wire [1:0] _history_12_1_T_1 = history_12_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2075 = history_12_2 > _GEN_195; // @[L1ICache.scala 153:36]
- wire [1:0] _history_12_2_T_1 = history_12_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2081 = history_12_3 > _GEN_195; // @[L1ICache.scala 153:36]
- wire [1:0] _history_12_3_T_1 = history_12_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_14 = matchSlot[55:52]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2090 = matchSet_14[0] + matchSet_14[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2092 = matchSet_14[2] + matchSet_14[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2094 = _T_2090 + _T_2092; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_13_2 = matchSet_14[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_13_3 = matchSet_14[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_13_1 = {{1'd0}, matchSet_14[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_41 = matchIndices_13_1 | matchIndices_13_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_13 = _matchIndex_T_41 | matchIndices_13_3; // @[Library.scala 76:39]
- wire _T_2103 = io_ibus_valid & io_ibus_ready & setMatch_53; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_209 = 2'h1 == matchIndex_13 ? history_13_1 : history_13_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_210 = 2'h2 == matchIndex_13 ? history_13_2 : _GEN_209; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_211 = 2'h3 == matchIndex_13 ? history_13_3 : _GEN_210; // @[L1ICache.scala 153:{36,36}]
- wire _T_2105 = history_13_0 > _GEN_211; // @[L1ICache.scala 153:36]
- wire [1:0] _history_13_0_T_1 = history_13_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2111 = history_13_1 > _GEN_211; // @[L1ICache.scala 153:36]
- wire [1:0] _history_13_1_T_1 = history_13_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2117 = history_13_2 > _GEN_211; // @[L1ICache.scala 153:36]
- wire [1:0] _history_13_2_T_1 = history_13_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2123 = history_13_3 > _GEN_211; // @[L1ICache.scala 153:36]
- wire [1:0] _history_13_3_T_1 = history_13_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_15 = matchSlot[59:56]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2132 = matchSet_15[0] + matchSet_15[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2134 = matchSet_15[2] + matchSet_15[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2136 = _T_2132 + _T_2134; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_14_2 = matchSet_15[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_14_3 = matchSet_15[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_14_1 = {{1'd0}, matchSet_15[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_44 = matchIndices_14_1 | matchIndices_14_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_14 = _matchIndex_T_44 | matchIndices_14_3; // @[Library.scala 76:39]
- wire _T_2145 = io_ibus_valid & io_ibus_ready & setMatch_57; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_225 = 2'h1 == matchIndex_14 ? history_14_1 : history_14_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_226 = 2'h2 == matchIndex_14 ? history_14_2 : _GEN_225; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_227 = 2'h3 == matchIndex_14 ? history_14_3 : _GEN_226; // @[L1ICache.scala 153:{36,36}]
- wire _T_2147 = history_14_0 > _GEN_227; // @[L1ICache.scala 153:36]
- wire [1:0] _history_14_0_T_1 = history_14_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2153 = history_14_1 > _GEN_227; // @[L1ICache.scala 153:36]
- wire [1:0] _history_14_1_T_1 = history_14_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2159 = history_14_2 > _GEN_227; // @[L1ICache.scala 153:36]
- wire [1:0] _history_14_2_T_1 = history_14_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2165 = history_14_3 > _GEN_227; // @[L1ICache.scala 153:36]
- wire [1:0] _history_14_3_T_1 = history_14_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_16 = matchSlot[63:60]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2174 = matchSet_16[0] + matchSet_16[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2176 = matchSet_16[2] + matchSet_16[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2178 = _T_2174 + _T_2176; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_15_2 = matchSet_16[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_15_3 = matchSet_16[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_15_1 = {{1'd0}, matchSet_16[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_47 = matchIndices_15_1 | matchIndices_15_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_15 = _matchIndex_T_47 | matchIndices_15_3; // @[Library.scala 76:39]
- wire _T_2187 = io_ibus_valid & io_ibus_ready & setMatch_61; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_241 = 2'h1 == matchIndex_15 ? history_15_1 : history_15_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_242 = 2'h2 == matchIndex_15 ? history_15_2 : _GEN_241; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_243 = 2'h3 == matchIndex_15 ? history_15_3 : _GEN_242; // @[L1ICache.scala 153:{36,36}]
- wire _T_2189 = history_15_0 > _GEN_243; // @[L1ICache.scala 153:36]
- wire [1:0] _history_15_0_T_1 = history_15_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2195 = history_15_1 > _GEN_243; // @[L1ICache.scala 153:36]
- wire [1:0] _history_15_1_T_1 = history_15_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2201 = history_15_2 > _GEN_243; // @[L1ICache.scala 153:36]
- wire [1:0] _history_15_2_T_1 = history_15_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2207 = history_15_3 > _GEN_243; // @[L1ICache.scala 153:36]
- wire [1:0] _history_15_3_T_1 = history_15_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_17 = matchSlot[67:64]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2216 = matchSet_17[0] + matchSet_17[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2218 = matchSet_17[2] + matchSet_17[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2220 = _T_2216 + _T_2218; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_16_2 = matchSet_17[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_16_3 = matchSet_17[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_16_1 = {{1'd0}, matchSet_17[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_50 = matchIndices_16_1 | matchIndices_16_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_16 = _matchIndex_T_50 | matchIndices_16_3; // @[Library.scala 76:39]
- wire _T_2229 = io_ibus_valid & io_ibus_ready & setMatch_65; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_257 = 2'h1 == matchIndex_16 ? history_16_1 : history_16_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_258 = 2'h2 == matchIndex_16 ? history_16_2 : _GEN_257; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_259 = 2'h3 == matchIndex_16 ? history_16_3 : _GEN_258; // @[L1ICache.scala 153:{36,36}]
- wire _T_2231 = history_16_0 > _GEN_259; // @[L1ICache.scala 153:36]
- wire [1:0] _history_16_0_T_1 = history_16_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2237 = history_16_1 > _GEN_259; // @[L1ICache.scala 153:36]
- wire [1:0] _history_16_1_T_1 = history_16_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2243 = history_16_2 > _GEN_259; // @[L1ICache.scala 153:36]
- wire [1:0] _history_16_2_T_1 = history_16_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2249 = history_16_3 > _GEN_259; // @[L1ICache.scala 153:36]
- wire [1:0] _history_16_3_T_1 = history_16_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_18 = matchSlot[71:68]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2258 = matchSet_18[0] + matchSet_18[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2260 = matchSet_18[2] + matchSet_18[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2262 = _T_2258 + _T_2260; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_17_2 = matchSet_18[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_17_3 = matchSet_18[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_17_1 = {{1'd0}, matchSet_18[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_53 = matchIndices_17_1 | matchIndices_17_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_17 = _matchIndex_T_53 | matchIndices_17_3; // @[Library.scala 76:39]
- wire _T_2271 = io_ibus_valid & io_ibus_ready & setMatch_69; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_273 = 2'h1 == matchIndex_17 ? history_17_1 : history_17_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_274 = 2'h2 == matchIndex_17 ? history_17_2 : _GEN_273; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_275 = 2'h3 == matchIndex_17 ? history_17_3 : _GEN_274; // @[L1ICache.scala 153:{36,36}]
- wire _T_2273 = history_17_0 > _GEN_275; // @[L1ICache.scala 153:36]
- wire [1:0] _history_17_0_T_1 = history_17_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2279 = history_17_1 > _GEN_275; // @[L1ICache.scala 153:36]
- wire [1:0] _history_17_1_T_1 = history_17_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2285 = history_17_2 > _GEN_275; // @[L1ICache.scala 153:36]
- wire [1:0] _history_17_2_T_1 = history_17_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2291 = history_17_3 > _GEN_275; // @[L1ICache.scala 153:36]
- wire [1:0] _history_17_3_T_1 = history_17_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_19 = matchSlot[75:72]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2300 = matchSet_19[0] + matchSet_19[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2302 = matchSet_19[2] + matchSet_19[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2304 = _T_2300 + _T_2302; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_18_2 = matchSet_19[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_18_3 = matchSet_19[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_18_1 = {{1'd0}, matchSet_19[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_56 = matchIndices_18_1 | matchIndices_18_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_18 = _matchIndex_T_56 | matchIndices_18_3; // @[Library.scala 76:39]
- wire _T_2313 = io_ibus_valid & io_ibus_ready & setMatch_73; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_289 = 2'h1 == matchIndex_18 ? history_18_1 : history_18_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_290 = 2'h2 == matchIndex_18 ? history_18_2 : _GEN_289; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_291 = 2'h3 == matchIndex_18 ? history_18_3 : _GEN_290; // @[L1ICache.scala 153:{36,36}]
- wire _T_2315 = history_18_0 > _GEN_291; // @[L1ICache.scala 153:36]
- wire [1:0] _history_18_0_T_1 = history_18_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2321 = history_18_1 > _GEN_291; // @[L1ICache.scala 153:36]
- wire [1:0] _history_18_1_T_1 = history_18_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2327 = history_18_2 > _GEN_291; // @[L1ICache.scala 153:36]
- wire [1:0] _history_18_2_T_1 = history_18_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2333 = history_18_3 > _GEN_291; // @[L1ICache.scala 153:36]
- wire [1:0] _history_18_3_T_1 = history_18_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_20 = matchSlot[79:76]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2342 = matchSet_20[0] + matchSet_20[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2344 = matchSet_20[2] + matchSet_20[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2346 = _T_2342 + _T_2344; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_19_2 = matchSet_20[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_19_3 = matchSet_20[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_19_1 = {{1'd0}, matchSet_20[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_59 = matchIndices_19_1 | matchIndices_19_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_19 = _matchIndex_T_59 | matchIndices_19_3; // @[Library.scala 76:39]
- wire _T_2355 = io_ibus_valid & io_ibus_ready & setMatch_77; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_305 = 2'h1 == matchIndex_19 ? history_19_1 : history_19_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_306 = 2'h2 == matchIndex_19 ? history_19_2 : _GEN_305; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_307 = 2'h3 == matchIndex_19 ? history_19_3 : _GEN_306; // @[L1ICache.scala 153:{36,36}]
- wire _T_2357 = history_19_0 > _GEN_307; // @[L1ICache.scala 153:36]
- wire [1:0] _history_19_0_T_1 = history_19_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2363 = history_19_1 > _GEN_307; // @[L1ICache.scala 153:36]
- wire [1:0] _history_19_1_T_1 = history_19_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2369 = history_19_2 > _GEN_307; // @[L1ICache.scala 153:36]
- wire [1:0] _history_19_2_T_1 = history_19_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2375 = history_19_3 > _GEN_307; // @[L1ICache.scala 153:36]
- wire [1:0] _history_19_3_T_1 = history_19_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_21 = matchSlot[83:80]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2384 = matchSet_21[0] + matchSet_21[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2386 = matchSet_21[2] + matchSet_21[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2388 = _T_2384 + _T_2386; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_20_2 = matchSet_21[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_20_3 = matchSet_21[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_20_1 = {{1'd0}, matchSet_21[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_62 = matchIndices_20_1 | matchIndices_20_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_20 = _matchIndex_T_62 | matchIndices_20_3; // @[Library.scala 76:39]
- wire _T_2397 = io_ibus_valid & io_ibus_ready & setMatch_81; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_321 = 2'h1 == matchIndex_20 ? history_20_1 : history_20_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_322 = 2'h2 == matchIndex_20 ? history_20_2 : _GEN_321; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_323 = 2'h3 == matchIndex_20 ? history_20_3 : _GEN_322; // @[L1ICache.scala 153:{36,36}]
- wire _T_2399 = history_20_0 > _GEN_323; // @[L1ICache.scala 153:36]
- wire [1:0] _history_20_0_T_1 = history_20_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2405 = history_20_1 > _GEN_323; // @[L1ICache.scala 153:36]
- wire [1:0] _history_20_1_T_1 = history_20_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2411 = history_20_2 > _GEN_323; // @[L1ICache.scala 153:36]
- wire [1:0] _history_20_2_T_1 = history_20_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2417 = history_20_3 > _GEN_323; // @[L1ICache.scala 153:36]
- wire [1:0] _history_20_3_T_1 = history_20_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_22 = matchSlot[87:84]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2426 = matchSet_22[0] + matchSet_22[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2428 = matchSet_22[2] + matchSet_22[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2430 = _T_2426 + _T_2428; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_21_2 = matchSet_22[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_21_3 = matchSet_22[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_21_1 = {{1'd0}, matchSet_22[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_65 = matchIndices_21_1 | matchIndices_21_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_21 = _matchIndex_T_65 | matchIndices_21_3; // @[Library.scala 76:39]
- wire _T_2439 = io_ibus_valid & io_ibus_ready & setMatch_85; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_337 = 2'h1 == matchIndex_21 ? history_21_1 : history_21_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_338 = 2'h2 == matchIndex_21 ? history_21_2 : _GEN_337; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_339 = 2'h3 == matchIndex_21 ? history_21_3 : _GEN_338; // @[L1ICache.scala 153:{36,36}]
- wire _T_2441 = history_21_0 > _GEN_339; // @[L1ICache.scala 153:36]
- wire [1:0] _history_21_0_T_1 = history_21_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2447 = history_21_1 > _GEN_339; // @[L1ICache.scala 153:36]
- wire [1:0] _history_21_1_T_1 = history_21_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2453 = history_21_2 > _GEN_339; // @[L1ICache.scala 153:36]
- wire [1:0] _history_21_2_T_1 = history_21_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2459 = history_21_3 > _GEN_339; // @[L1ICache.scala 153:36]
- wire [1:0] _history_21_3_T_1 = history_21_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_23 = matchSlot[91:88]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2468 = matchSet_23[0] + matchSet_23[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2470 = matchSet_23[2] + matchSet_23[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2472 = _T_2468 + _T_2470; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_22_2 = matchSet_23[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_22_3 = matchSet_23[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_22_1 = {{1'd0}, matchSet_23[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_68 = matchIndices_22_1 | matchIndices_22_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_22 = _matchIndex_T_68 | matchIndices_22_3; // @[Library.scala 76:39]
- wire _T_2481 = io_ibus_valid & io_ibus_ready & setMatch_89; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_353 = 2'h1 == matchIndex_22 ? history_22_1 : history_22_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_354 = 2'h2 == matchIndex_22 ? history_22_2 : _GEN_353; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_355 = 2'h3 == matchIndex_22 ? history_22_3 : _GEN_354; // @[L1ICache.scala 153:{36,36}]
- wire _T_2483 = history_22_0 > _GEN_355; // @[L1ICache.scala 153:36]
- wire [1:0] _history_22_0_T_1 = history_22_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2489 = history_22_1 > _GEN_355; // @[L1ICache.scala 153:36]
- wire [1:0] _history_22_1_T_1 = history_22_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2495 = history_22_2 > _GEN_355; // @[L1ICache.scala 153:36]
- wire [1:0] _history_22_2_T_1 = history_22_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2501 = history_22_3 > _GEN_355; // @[L1ICache.scala 153:36]
- wire [1:0] _history_22_3_T_1 = history_22_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_24 = matchSlot[95:92]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2510 = matchSet_24[0] + matchSet_24[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2512 = matchSet_24[2] + matchSet_24[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2514 = _T_2510 + _T_2512; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_23_2 = matchSet_24[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_23_3 = matchSet_24[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_23_1 = {{1'd0}, matchSet_24[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_71 = matchIndices_23_1 | matchIndices_23_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_23 = _matchIndex_T_71 | matchIndices_23_3; // @[Library.scala 76:39]
- wire _T_2523 = io_ibus_valid & io_ibus_ready & setMatch_93; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_369 = 2'h1 == matchIndex_23 ? history_23_1 : history_23_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_370 = 2'h2 == matchIndex_23 ? history_23_2 : _GEN_369; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_371 = 2'h3 == matchIndex_23 ? history_23_3 : _GEN_370; // @[L1ICache.scala 153:{36,36}]
- wire _T_2525 = history_23_0 > _GEN_371; // @[L1ICache.scala 153:36]
- wire [1:0] _history_23_0_T_1 = history_23_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2531 = history_23_1 > _GEN_371; // @[L1ICache.scala 153:36]
- wire [1:0] _history_23_1_T_1 = history_23_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2537 = history_23_2 > _GEN_371; // @[L1ICache.scala 153:36]
- wire [1:0] _history_23_2_T_1 = history_23_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2543 = history_23_3 > _GEN_371; // @[L1ICache.scala 153:36]
- wire [1:0] _history_23_3_T_1 = history_23_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_25 = matchSlot[99:96]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2552 = matchSet_25[0] + matchSet_25[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2554 = matchSet_25[2] + matchSet_25[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2556 = _T_2552 + _T_2554; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_24_2 = matchSet_25[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_24_3 = matchSet_25[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_24_1 = {{1'd0}, matchSet_25[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_74 = matchIndices_24_1 | matchIndices_24_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_24 = _matchIndex_T_74 | matchIndices_24_3; // @[Library.scala 76:39]
- wire _T_2565 = io_ibus_valid & io_ibus_ready & setMatch_97; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_385 = 2'h1 == matchIndex_24 ? history_24_1 : history_24_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_386 = 2'h2 == matchIndex_24 ? history_24_2 : _GEN_385; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_387 = 2'h3 == matchIndex_24 ? history_24_3 : _GEN_386; // @[L1ICache.scala 153:{36,36}]
- wire _T_2567 = history_24_0 > _GEN_387; // @[L1ICache.scala 153:36]
- wire [1:0] _history_24_0_T_1 = history_24_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2573 = history_24_1 > _GEN_387; // @[L1ICache.scala 153:36]
- wire [1:0] _history_24_1_T_1 = history_24_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2579 = history_24_2 > _GEN_387; // @[L1ICache.scala 153:36]
- wire [1:0] _history_24_2_T_1 = history_24_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2585 = history_24_3 > _GEN_387; // @[L1ICache.scala 153:36]
- wire [1:0] _history_24_3_T_1 = history_24_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_26 = matchSlot[103:100]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2594 = matchSet_26[0] + matchSet_26[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2596 = matchSet_26[2] + matchSet_26[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2598 = _T_2594 + _T_2596; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_25_2 = matchSet_26[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_25_3 = matchSet_26[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_25_1 = {{1'd0}, matchSet_26[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_77 = matchIndices_25_1 | matchIndices_25_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_25 = _matchIndex_T_77 | matchIndices_25_3; // @[Library.scala 76:39]
- wire _T_2607 = io_ibus_valid & io_ibus_ready & setMatch_101; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_401 = 2'h1 == matchIndex_25 ? history_25_1 : history_25_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_402 = 2'h2 == matchIndex_25 ? history_25_2 : _GEN_401; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_403 = 2'h3 == matchIndex_25 ? history_25_3 : _GEN_402; // @[L1ICache.scala 153:{36,36}]
- wire _T_2609 = history_25_0 > _GEN_403; // @[L1ICache.scala 153:36]
- wire [1:0] _history_25_0_T_1 = history_25_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2615 = history_25_1 > _GEN_403; // @[L1ICache.scala 153:36]
- wire [1:0] _history_25_1_T_1 = history_25_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2621 = history_25_2 > _GEN_403; // @[L1ICache.scala 153:36]
- wire [1:0] _history_25_2_T_1 = history_25_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2627 = history_25_3 > _GEN_403; // @[L1ICache.scala 153:36]
- wire [1:0] _history_25_3_T_1 = history_25_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_27 = matchSlot[107:104]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2636 = matchSet_27[0] + matchSet_27[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2638 = matchSet_27[2] + matchSet_27[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2640 = _T_2636 + _T_2638; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_26_2 = matchSet_27[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_26_3 = matchSet_27[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_26_1 = {{1'd0}, matchSet_27[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_80 = matchIndices_26_1 | matchIndices_26_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_26 = _matchIndex_T_80 | matchIndices_26_3; // @[Library.scala 76:39]
- wire _T_2649 = io_ibus_valid & io_ibus_ready & setMatch_105; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_417 = 2'h1 == matchIndex_26 ? history_26_1 : history_26_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_418 = 2'h2 == matchIndex_26 ? history_26_2 : _GEN_417; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_419 = 2'h3 == matchIndex_26 ? history_26_3 : _GEN_418; // @[L1ICache.scala 153:{36,36}]
- wire _T_2651 = history_26_0 > _GEN_419; // @[L1ICache.scala 153:36]
- wire [1:0] _history_26_0_T_1 = history_26_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2657 = history_26_1 > _GEN_419; // @[L1ICache.scala 153:36]
- wire [1:0] _history_26_1_T_1 = history_26_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2663 = history_26_2 > _GEN_419; // @[L1ICache.scala 153:36]
- wire [1:0] _history_26_2_T_1 = history_26_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2669 = history_26_3 > _GEN_419; // @[L1ICache.scala 153:36]
- wire [1:0] _history_26_3_T_1 = history_26_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_28 = matchSlot[111:108]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2678 = matchSet_28[0] + matchSet_28[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2680 = matchSet_28[2] + matchSet_28[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2682 = _T_2678 + _T_2680; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_27_2 = matchSet_28[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_27_3 = matchSet_28[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_27_1 = {{1'd0}, matchSet_28[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_83 = matchIndices_27_1 | matchIndices_27_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_27 = _matchIndex_T_83 | matchIndices_27_3; // @[Library.scala 76:39]
- wire _T_2691 = io_ibus_valid & io_ibus_ready & setMatch_109; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_433 = 2'h1 == matchIndex_27 ? history_27_1 : history_27_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_434 = 2'h2 == matchIndex_27 ? history_27_2 : _GEN_433; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_435 = 2'h3 == matchIndex_27 ? history_27_3 : _GEN_434; // @[L1ICache.scala 153:{36,36}]
- wire _T_2693 = history_27_0 > _GEN_435; // @[L1ICache.scala 153:36]
- wire [1:0] _history_27_0_T_1 = history_27_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2699 = history_27_1 > _GEN_435; // @[L1ICache.scala 153:36]
- wire [1:0] _history_27_1_T_1 = history_27_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2705 = history_27_2 > _GEN_435; // @[L1ICache.scala 153:36]
- wire [1:0] _history_27_2_T_1 = history_27_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2711 = history_27_3 > _GEN_435; // @[L1ICache.scala 153:36]
- wire [1:0] _history_27_3_T_1 = history_27_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_29 = matchSlot[115:112]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2720 = matchSet_29[0] + matchSet_29[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2722 = matchSet_29[2] + matchSet_29[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2724 = _T_2720 + _T_2722; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_28_2 = matchSet_29[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_28_3 = matchSet_29[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_28_1 = {{1'd0}, matchSet_29[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_86 = matchIndices_28_1 | matchIndices_28_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_28 = _matchIndex_T_86 | matchIndices_28_3; // @[Library.scala 76:39]
- wire _T_2733 = io_ibus_valid & io_ibus_ready & setMatch_113; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_449 = 2'h1 == matchIndex_28 ? history_28_1 : history_28_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_450 = 2'h2 == matchIndex_28 ? history_28_2 : _GEN_449; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_451 = 2'h3 == matchIndex_28 ? history_28_3 : _GEN_450; // @[L1ICache.scala 153:{36,36}]
- wire _T_2735 = history_28_0 > _GEN_451; // @[L1ICache.scala 153:36]
- wire [1:0] _history_28_0_T_1 = history_28_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2741 = history_28_1 > _GEN_451; // @[L1ICache.scala 153:36]
- wire [1:0] _history_28_1_T_1 = history_28_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2747 = history_28_2 > _GEN_451; // @[L1ICache.scala 153:36]
- wire [1:0] _history_28_2_T_1 = history_28_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2753 = history_28_3 > _GEN_451; // @[L1ICache.scala 153:36]
- wire [1:0] _history_28_3_T_1 = history_28_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_30 = matchSlot[119:116]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2762 = matchSet_30[0] + matchSet_30[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2764 = matchSet_30[2] + matchSet_30[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2766 = _T_2762 + _T_2764; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_29_2 = matchSet_30[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_29_3 = matchSet_30[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_29_1 = {{1'd0}, matchSet_30[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_89 = matchIndices_29_1 | matchIndices_29_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_29 = _matchIndex_T_89 | matchIndices_29_3; // @[Library.scala 76:39]
- wire _T_2775 = io_ibus_valid & io_ibus_ready & setMatch_117; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_465 = 2'h1 == matchIndex_29 ? history_29_1 : history_29_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_466 = 2'h2 == matchIndex_29 ? history_29_2 : _GEN_465; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_467 = 2'h3 == matchIndex_29 ? history_29_3 : _GEN_466; // @[L1ICache.scala 153:{36,36}]
- wire _T_2777 = history_29_0 > _GEN_467; // @[L1ICache.scala 153:36]
- wire [1:0] _history_29_0_T_1 = history_29_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2783 = history_29_1 > _GEN_467; // @[L1ICache.scala 153:36]
- wire [1:0] _history_29_1_T_1 = history_29_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2789 = history_29_2 > _GEN_467; // @[L1ICache.scala 153:36]
- wire [1:0] _history_29_2_T_1 = history_29_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2795 = history_29_3 > _GEN_467; // @[L1ICache.scala 153:36]
- wire [1:0] _history_29_3_T_1 = history_29_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_31 = matchSlot[123:120]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2804 = matchSet_31[0] + matchSet_31[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2806 = matchSet_31[2] + matchSet_31[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2808 = _T_2804 + _T_2806; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_30_2 = matchSet_31[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_30_3 = matchSet_31[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_30_1 = {{1'd0}, matchSet_31[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_92 = matchIndices_30_1 | matchIndices_30_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_30 = _matchIndex_T_92 | matchIndices_30_3; // @[Library.scala 76:39]
- wire _T_2817 = io_ibus_valid & io_ibus_ready & setMatch_121; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_481 = 2'h1 == matchIndex_30 ? history_30_1 : history_30_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_482 = 2'h2 == matchIndex_30 ? history_30_2 : _GEN_481; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_483 = 2'h3 == matchIndex_30 ? history_30_3 : _GEN_482; // @[L1ICache.scala 153:{36,36}]
- wire _T_2819 = history_30_0 > _GEN_483; // @[L1ICache.scala 153:36]
- wire [1:0] _history_30_0_T_1 = history_30_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2825 = history_30_1 > _GEN_483; // @[L1ICache.scala 153:36]
- wire [1:0] _history_30_1_T_1 = history_30_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2831 = history_30_2 > _GEN_483; // @[L1ICache.scala 153:36]
- wire [1:0] _history_30_2_T_1 = history_30_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2837 = history_30_3 > _GEN_483; // @[L1ICache.scala 153:36]
- wire [1:0] _history_30_3_T_1 = history_30_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_32 = matchSlot[127:124]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2846 = matchSet_32[0] + matchSet_32[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2848 = matchSet_32[2] + matchSet_32[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2850 = _T_2846 + _T_2848; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_31_2 = matchSet_32[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_31_3 = matchSet_32[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_31_1 = {{1'd0}, matchSet_32[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_95 = matchIndices_31_1 | matchIndices_31_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_31 = _matchIndex_T_95 | matchIndices_31_3; // @[Library.scala 76:39]
- wire _T_2859 = io_ibus_valid & io_ibus_ready & setMatch_125; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_497 = 2'h1 == matchIndex_31 ? history_31_1 : history_31_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_498 = 2'h2 == matchIndex_31 ? history_31_2 : _GEN_497; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_499 = 2'h3 == matchIndex_31 ? history_31_3 : _GEN_498; // @[L1ICache.scala 153:{36,36}]
- wire _T_2861 = history_31_0 > _GEN_499; // @[L1ICache.scala 153:36]
- wire [1:0] _history_31_0_T_1 = history_31_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2867 = history_31_1 > _GEN_499; // @[L1ICache.scala 153:36]
- wire [1:0] _history_31_1_T_1 = history_31_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2873 = history_31_2 > _GEN_499; // @[L1ICache.scala 153:36]
- wire [1:0] _history_31_2_T_1 = history_31_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2879 = history_31_3 > _GEN_499; // @[L1ICache.scala 153:36]
- wire [1:0] _history_31_3_T_1 = history_31_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_33 = matchSlot[131:128]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2888 = matchSet_33[0] + matchSet_33[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2890 = matchSet_33[2] + matchSet_33[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2892 = _T_2888 + _T_2890; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_32_2 = matchSet_33[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_32_3 = matchSet_33[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_32_1 = {{1'd0}, matchSet_33[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_98 = matchIndices_32_1 | matchIndices_32_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_32 = _matchIndex_T_98 | matchIndices_32_3; // @[Library.scala 76:39]
- wire _T_2901 = io_ibus_valid & io_ibus_ready & setMatch_129; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_513 = 2'h1 == matchIndex_32 ? history_32_1 : history_32_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_514 = 2'h2 == matchIndex_32 ? history_32_2 : _GEN_513; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_515 = 2'h3 == matchIndex_32 ? history_32_3 : _GEN_514; // @[L1ICache.scala 153:{36,36}]
- wire _T_2903 = history_32_0 > _GEN_515; // @[L1ICache.scala 153:36]
- wire [1:0] _history_32_0_T_1 = history_32_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2909 = history_32_1 > _GEN_515; // @[L1ICache.scala 153:36]
- wire [1:0] _history_32_1_T_1 = history_32_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2915 = history_32_2 > _GEN_515; // @[L1ICache.scala 153:36]
- wire [1:0] _history_32_2_T_1 = history_32_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2921 = history_32_3 > _GEN_515; // @[L1ICache.scala 153:36]
- wire [1:0] _history_32_3_T_1 = history_32_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_34 = matchSlot[135:132]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2930 = matchSet_34[0] + matchSet_34[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2932 = matchSet_34[2] + matchSet_34[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2934 = _T_2930 + _T_2932; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_33_2 = matchSet_34[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_33_3 = matchSet_34[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_33_1 = {{1'd0}, matchSet_34[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_101 = matchIndices_33_1 | matchIndices_33_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_33 = _matchIndex_T_101 | matchIndices_33_3; // @[Library.scala 76:39]
- wire _T_2943 = io_ibus_valid & io_ibus_ready & setMatch_133; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_529 = 2'h1 == matchIndex_33 ? history_33_1 : history_33_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_530 = 2'h2 == matchIndex_33 ? history_33_2 : _GEN_529; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_531 = 2'h3 == matchIndex_33 ? history_33_3 : _GEN_530; // @[L1ICache.scala 153:{36,36}]
- wire _T_2945 = history_33_0 > _GEN_531; // @[L1ICache.scala 153:36]
- wire [1:0] _history_33_0_T_1 = history_33_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2951 = history_33_1 > _GEN_531; // @[L1ICache.scala 153:36]
- wire [1:0] _history_33_1_T_1 = history_33_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2957 = history_33_2 > _GEN_531; // @[L1ICache.scala 153:36]
- wire [1:0] _history_33_2_T_1 = history_33_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2963 = history_33_3 > _GEN_531; // @[L1ICache.scala 153:36]
- wire [1:0] _history_33_3_T_1 = history_33_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_35 = matchSlot[139:136]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_2972 = matchSet_35[0] + matchSet_35[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_2974 = matchSet_35[2] + matchSet_35[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_2976 = _T_2972 + _T_2974; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_34_2 = matchSet_35[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_34_3 = matchSet_35[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_34_1 = {{1'd0}, matchSet_35[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_104 = matchIndices_34_1 | matchIndices_34_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_34 = _matchIndex_T_104 | matchIndices_34_3; // @[Library.scala 76:39]
- wire _T_2985 = io_ibus_valid & io_ibus_ready & setMatch_137; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_545 = 2'h1 == matchIndex_34 ? history_34_1 : history_34_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_546 = 2'h2 == matchIndex_34 ? history_34_2 : _GEN_545; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_547 = 2'h3 == matchIndex_34 ? history_34_3 : _GEN_546; // @[L1ICache.scala 153:{36,36}]
- wire _T_2987 = history_34_0 > _GEN_547; // @[L1ICache.scala 153:36]
- wire [1:0] _history_34_0_T_1 = history_34_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2993 = history_34_1 > _GEN_547; // @[L1ICache.scala 153:36]
- wire [1:0] _history_34_1_T_1 = history_34_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_2999 = history_34_2 > _GEN_547; // @[L1ICache.scala 153:36]
- wire [1:0] _history_34_2_T_1 = history_34_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3005 = history_34_3 > _GEN_547; // @[L1ICache.scala 153:36]
- wire [1:0] _history_34_3_T_1 = history_34_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_36 = matchSlot[143:140]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3014 = matchSet_36[0] + matchSet_36[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3016 = matchSet_36[2] + matchSet_36[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3018 = _T_3014 + _T_3016; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_35_2 = matchSet_36[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_35_3 = matchSet_36[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_35_1 = {{1'd0}, matchSet_36[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_107 = matchIndices_35_1 | matchIndices_35_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_35 = _matchIndex_T_107 | matchIndices_35_3; // @[Library.scala 76:39]
- wire _T_3027 = io_ibus_valid & io_ibus_ready & setMatch_141; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_561 = 2'h1 == matchIndex_35 ? history_35_1 : history_35_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_562 = 2'h2 == matchIndex_35 ? history_35_2 : _GEN_561; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_563 = 2'h3 == matchIndex_35 ? history_35_3 : _GEN_562; // @[L1ICache.scala 153:{36,36}]
- wire _T_3029 = history_35_0 > _GEN_563; // @[L1ICache.scala 153:36]
- wire [1:0] _history_35_0_T_1 = history_35_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3035 = history_35_1 > _GEN_563; // @[L1ICache.scala 153:36]
- wire [1:0] _history_35_1_T_1 = history_35_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3041 = history_35_2 > _GEN_563; // @[L1ICache.scala 153:36]
- wire [1:0] _history_35_2_T_1 = history_35_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3047 = history_35_3 > _GEN_563; // @[L1ICache.scala 153:36]
- wire [1:0] _history_35_3_T_1 = history_35_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_37 = matchSlot[147:144]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3056 = matchSet_37[0] + matchSet_37[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3058 = matchSet_37[2] + matchSet_37[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3060 = _T_3056 + _T_3058; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_36_2 = matchSet_37[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_36_3 = matchSet_37[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_36_1 = {{1'd0}, matchSet_37[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_110 = matchIndices_36_1 | matchIndices_36_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_36 = _matchIndex_T_110 | matchIndices_36_3; // @[Library.scala 76:39]
- wire _T_3069 = io_ibus_valid & io_ibus_ready & setMatch_145; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_577 = 2'h1 == matchIndex_36 ? history_36_1 : history_36_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_578 = 2'h2 == matchIndex_36 ? history_36_2 : _GEN_577; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_579 = 2'h3 == matchIndex_36 ? history_36_3 : _GEN_578; // @[L1ICache.scala 153:{36,36}]
- wire _T_3071 = history_36_0 > _GEN_579; // @[L1ICache.scala 153:36]
- wire [1:0] _history_36_0_T_1 = history_36_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3077 = history_36_1 > _GEN_579; // @[L1ICache.scala 153:36]
- wire [1:0] _history_36_1_T_1 = history_36_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3083 = history_36_2 > _GEN_579; // @[L1ICache.scala 153:36]
- wire [1:0] _history_36_2_T_1 = history_36_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3089 = history_36_3 > _GEN_579; // @[L1ICache.scala 153:36]
- wire [1:0] _history_36_3_T_1 = history_36_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_38 = matchSlot[151:148]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3098 = matchSet_38[0] + matchSet_38[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3100 = matchSet_38[2] + matchSet_38[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3102 = _T_3098 + _T_3100; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_37_2 = matchSet_38[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_37_3 = matchSet_38[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_37_1 = {{1'd0}, matchSet_38[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_113 = matchIndices_37_1 | matchIndices_37_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_37 = _matchIndex_T_113 | matchIndices_37_3; // @[Library.scala 76:39]
- wire _T_3111 = io_ibus_valid & io_ibus_ready & setMatch_149; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_593 = 2'h1 == matchIndex_37 ? history_37_1 : history_37_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_594 = 2'h2 == matchIndex_37 ? history_37_2 : _GEN_593; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_595 = 2'h3 == matchIndex_37 ? history_37_3 : _GEN_594; // @[L1ICache.scala 153:{36,36}]
- wire _T_3113 = history_37_0 > _GEN_595; // @[L1ICache.scala 153:36]
- wire [1:0] _history_37_0_T_1 = history_37_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3119 = history_37_1 > _GEN_595; // @[L1ICache.scala 153:36]
- wire [1:0] _history_37_1_T_1 = history_37_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3125 = history_37_2 > _GEN_595; // @[L1ICache.scala 153:36]
- wire [1:0] _history_37_2_T_1 = history_37_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3131 = history_37_3 > _GEN_595; // @[L1ICache.scala 153:36]
- wire [1:0] _history_37_3_T_1 = history_37_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_39 = matchSlot[155:152]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3140 = matchSet_39[0] + matchSet_39[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3142 = matchSet_39[2] + matchSet_39[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3144 = _T_3140 + _T_3142; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_38_2 = matchSet_39[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_38_3 = matchSet_39[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_38_1 = {{1'd0}, matchSet_39[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_116 = matchIndices_38_1 | matchIndices_38_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_38 = _matchIndex_T_116 | matchIndices_38_3; // @[Library.scala 76:39]
- wire _T_3153 = io_ibus_valid & io_ibus_ready & setMatch_153; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_609 = 2'h1 == matchIndex_38 ? history_38_1 : history_38_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_610 = 2'h2 == matchIndex_38 ? history_38_2 : _GEN_609; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_611 = 2'h3 == matchIndex_38 ? history_38_3 : _GEN_610; // @[L1ICache.scala 153:{36,36}]
- wire _T_3155 = history_38_0 > _GEN_611; // @[L1ICache.scala 153:36]
- wire [1:0] _history_38_0_T_1 = history_38_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3161 = history_38_1 > _GEN_611; // @[L1ICache.scala 153:36]
- wire [1:0] _history_38_1_T_1 = history_38_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3167 = history_38_2 > _GEN_611; // @[L1ICache.scala 153:36]
- wire [1:0] _history_38_2_T_1 = history_38_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3173 = history_38_3 > _GEN_611; // @[L1ICache.scala 153:36]
- wire [1:0] _history_38_3_T_1 = history_38_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_40 = matchSlot[159:156]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3182 = matchSet_40[0] + matchSet_40[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3184 = matchSet_40[2] + matchSet_40[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3186 = _T_3182 + _T_3184; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_39_2 = matchSet_40[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_39_3 = matchSet_40[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_39_1 = {{1'd0}, matchSet_40[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_119 = matchIndices_39_1 | matchIndices_39_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_39 = _matchIndex_T_119 | matchIndices_39_3; // @[Library.scala 76:39]
- wire _T_3195 = io_ibus_valid & io_ibus_ready & setMatch_157; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_625 = 2'h1 == matchIndex_39 ? history_39_1 : history_39_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_626 = 2'h2 == matchIndex_39 ? history_39_2 : _GEN_625; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_627 = 2'h3 == matchIndex_39 ? history_39_3 : _GEN_626; // @[L1ICache.scala 153:{36,36}]
- wire _T_3197 = history_39_0 > _GEN_627; // @[L1ICache.scala 153:36]
- wire [1:0] _history_39_0_T_1 = history_39_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3203 = history_39_1 > _GEN_627; // @[L1ICache.scala 153:36]
- wire [1:0] _history_39_1_T_1 = history_39_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3209 = history_39_2 > _GEN_627; // @[L1ICache.scala 153:36]
- wire [1:0] _history_39_2_T_1 = history_39_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3215 = history_39_3 > _GEN_627; // @[L1ICache.scala 153:36]
- wire [1:0] _history_39_3_T_1 = history_39_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_41 = matchSlot[163:160]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3224 = matchSet_41[0] + matchSet_41[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3226 = matchSet_41[2] + matchSet_41[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3228 = _T_3224 + _T_3226; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_40_2 = matchSet_41[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_40_3 = matchSet_41[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_40_1 = {{1'd0}, matchSet_41[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_122 = matchIndices_40_1 | matchIndices_40_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_40 = _matchIndex_T_122 | matchIndices_40_3; // @[Library.scala 76:39]
- wire _T_3237 = io_ibus_valid & io_ibus_ready & setMatch_161; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_641 = 2'h1 == matchIndex_40 ? history_40_1 : history_40_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_642 = 2'h2 == matchIndex_40 ? history_40_2 : _GEN_641; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_643 = 2'h3 == matchIndex_40 ? history_40_3 : _GEN_642; // @[L1ICache.scala 153:{36,36}]
- wire _T_3239 = history_40_0 > _GEN_643; // @[L1ICache.scala 153:36]
- wire [1:0] _history_40_0_T_1 = history_40_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3245 = history_40_1 > _GEN_643; // @[L1ICache.scala 153:36]
- wire [1:0] _history_40_1_T_1 = history_40_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3251 = history_40_2 > _GEN_643; // @[L1ICache.scala 153:36]
- wire [1:0] _history_40_2_T_1 = history_40_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3257 = history_40_3 > _GEN_643; // @[L1ICache.scala 153:36]
- wire [1:0] _history_40_3_T_1 = history_40_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_42 = matchSlot[167:164]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3266 = matchSet_42[0] + matchSet_42[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3268 = matchSet_42[2] + matchSet_42[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3270 = _T_3266 + _T_3268; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_41_2 = matchSet_42[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_41_3 = matchSet_42[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_41_1 = {{1'd0}, matchSet_42[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_125 = matchIndices_41_1 | matchIndices_41_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_41 = _matchIndex_T_125 | matchIndices_41_3; // @[Library.scala 76:39]
- wire _T_3279 = io_ibus_valid & io_ibus_ready & setMatch_165; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_657 = 2'h1 == matchIndex_41 ? history_41_1 : history_41_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_658 = 2'h2 == matchIndex_41 ? history_41_2 : _GEN_657; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_659 = 2'h3 == matchIndex_41 ? history_41_3 : _GEN_658; // @[L1ICache.scala 153:{36,36}]
- wire _T_3281 = history_41_0 > _GEN_659; // @[L1ICache.scala 153:36]
- wire [1:0] _history_41_0_T_1 = history_41_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3287 = history_41_1 > _GEN_659; // @[L1ICache.scala 153:36]
- wire [1:0] _history_41_1_T_1 = history_41_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3293 = history_41_2 > _GEN_659; // @[L1ICache.scala 153:36]
- wire [1:0] _history_41_2_T_1 = history_41_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3299 = history_41_3 > _GEN_659; // @[L1ICache.scala 153:36]
- wire [1:0] _history_41_3_T_1 = history_41_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_43 = matchSlot[171:168]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3308 = matchSet_43[0] + matchSet_43[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3310 = matchSet_43[2] + matchSet_43[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3312 = _T_3308 + _T_3310; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_42_2 = matchSet_43[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_42_3 = matchSet_43[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_42_1 = {{1'd0}, matchSet_43[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_128 = matchIndices_42_1 | matchIndices_42_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_42 = _matchIndex_T_128 | matchIndices_42_3; // @[Library.scala 76:39]
- wire _T_3321 = io_ibus_valid & io_ibus_ready & setMatch_169; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_673 = 2'h1 == matchIndex_42 ? history_42_1 : history_42_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_674 = 2'h2 == matchIndex_42 ? history_42_2 : _GEN_673; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_675 = 2'h3 == matchIndex_42 ? history_42_3 : _GEN_674; // @[L1ICache.scala 153:{36,36}]
- wire _T_3323 = history_42_0 > _GEN_675; // @[L1ICache.scala 153:36]
- wire [1:0] _history_42_0_T_1 = history_42_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3329 = history_42_1 > _GEN_675; // @[L1ICache.scala 153:36]
- wire [1:0] _history_42_1_T_1 = history_42_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3335 = history_42_2 > _GEN_675; // @[L1ICache.scala 153:36]
- wire [1:0] _history_42_2_T_1 = history_42_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3341 = history_42_3 > _GEN_675; // @[L1ICache.scala 153:36]
- wire [1:0] _history_42_3_T_1 = history_42_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_44 = matchSlot[175:172]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3350 = matchSet_44[0] + matchSet_44[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3352 = matchSet_44[2] + matchSet_44[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3354 = _T_3350 + _T_3352; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_43_2 = matchSet_44[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_43_3 = matchSet_44[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_43_1 = {{1'd0}, matchSet_44[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_131 = matchIndices_43_1 | matchIndices_43_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_43 = _matchIndex_T_131 | matchIndices_43_3; // @[Library.scala 76:39]
- wire _T_3363 = io_ibus_valid & io_ibus_ready & setMatch_173; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_689 = 2'h1 == matchIndex_43 ? history_43_1 : history_43_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_690 = 2'h2 == matchIndex_43 ? history_43_2 : _GEN_689; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_691 = 2'h3 == matchIndex_43 ? history_43_3 : _GEN_690; // @[L1ICache.scala 153:{36,36}]
- wire _T_3365 = history_43_0 > _GEN_691; // @[L1ICache.scala 153:36]
- wire [1:0] _history_43_0_T_1 = history_43_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3371 = history_43_1 > _GEN_691; // @[L1ICache.scala 153:36]
- wire [1:0] _history_43_1_T_1 = history_43_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3377 = history_43_2 > _GEN_691; // @[L1ICache.scala 153:36]
- wire [1:0] _history_43_2_T_1 = history_43_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3383 = history_43_3 > _GEN_691; // @[L1ICache.scala 153:36]
- wire [1:0] _history_43_3_T_1 = history_43_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_45 = matchSlot[179:176]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3392 = matchSet_45[0] + matchSet_45[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3394 = matchSet_45[2] + matchSet_45[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3396 = _T_3392 + _T_3394; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_44_2 = matchSet_45[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_44_3 = matchSet_45[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_44_1 = {{1'd0}, matchSet_45[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_134 = matchIndices_44_1 | matchIndices_44_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_44 = _matchIndex_T_134 | matchIndices_44_3; // @[Library.scala 76:39]
- wire _T_3405 = io_ibus_valid & io_ibus_ready & setMatch_177; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_705 = 2'h1 == matchIndex_44 ? history_44_1 : history_44_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_706 = 2'h2 == matchIndex_44 ? history_44_2 : _GEN_705; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_707 = 2'h3 == matchIndex_44 ? history_44_3 : _GEN_706; // @[L1ICache.scala 153:{36,36}]
- wire _T_3407 = history_44_0 > _GEN_707; // @[L1ICache.scala 153:36]
- wire [1:0] _history_44_0_T_1 = history_44_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3413 = history_44_1 > _GEN_707; // @[L1ICache.scala 153:36]
- wire [1:0] _history_44_1_T_1 = history_44_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3419 = history_44_2 > _GEN_707; // @[L1ICache.scala 153:36]
- wire [1:0] _history_44_2_T_1 = history_44_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3425 = history_44_3 > _GEN_707; // @[L1ICache.scala 153:36]
- wire [1:0] _history_44_3_T_1 = history_44_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_46 = matchSlot[183:180]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3434 = matchSet_46[0] + matchSet_46[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3436 = matchSet_46[2] + matchSet_46[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3438 = _T_3434 + _T_3436; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_45_2 = matchSet_46[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_45_3 = matchSet_46[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_45_1 = {{1'd0}, matchSet_46[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_137 = matchIndices_45_1 | matchIndices_45_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_45 = _matchIndex_T_137 | matchIndices_45_3; // @[Library.scala 76:39]
- wire _T_3447 = io_ibus_valid & io_ibus_ready & setMatch_181; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_721 = 2'h1 == matchIndex_45 ? history_45_1 : history_45_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_722 = 2'h2 == matchIndex_45 ? history_45_2 : _GEN_721; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_723 = 2'h3 == matchIndex_45 ? history_45_3 : _GEN_722; // @[L1ICache.scala 153:{36,36}]
- wire _T_3449 = history_45_0 > _GEN_723; // @[L1ICache.scala 153:36]
- wire [1:0] _history_45_0_T_1 = history_45_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3455 = history_45_1 > _GEN_723; // @[L1ICache.scala 153:36]
- wire [1:0] _history_45_1_T_1 = history_45_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3461 = history_45_2 > _GEN_723; // @[L1ICache.scala 153:36]
- wire [1:0] _history_45_2_T_1 = history_45_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3467 = history_45_3 > _GEN_723; // @[L1ICache.scala 153:36]
- wire [1:0] _history_45_3_T_1 = history_45_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_47 = matchSlot[187:184]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3476 = matchSet_47[0] + matchSet_47[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3478 = matchSet_47[2] + matchSet_47[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3480 = _T_3476 + _T_3478; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_46_2 = matchSet_47[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_46_3 = matchSet_47[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_46_1 = {{1'd0}, matchSet_47[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_140 = matchIndices_46_1 | matchIndices_46_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_46 = _matchIndex_T_140 | matchIndices_46_3; // @[Library.scala 76:39]
- wire _T_3489 = io_ibus_valid & io_ibus_ready & setMatch_185; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_737 = 2'h1 == matchIndex_46 ? history_46_1 : history_46_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_738 = 2'h2 == matchIndex_46 ? history_46_2 : _GEN_737; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_739 = 2'h3 == matchIndex_46 ? history_46_3 : _GEN_738; // @[L1ICache.scala 153:{36,36}]
- wire _T_3491 = history_46_0 > _GEN_739; // @[L1ICache.scala 153:36]
- wire [1:0] _history_46_0_T_1 = history_46_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3497 = history_46_1 > _GEN_739; // @[L1ICache.scala 153:36]
- wire [1:0] _history_46_1_T_1 = history_46_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3503 = history_46_2 > _GEN_739; // @[L1ICache.scala 153:36]
- wire [1:0] _history_46_2_T_1 = history_46_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3509 = history_46_3 > _GEN_739; // @[L1ICache.scala 153:36]
- wire [1:0] _history_46_3_T_1 = history_46_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_48 = matchSlot[191:188]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3518 = matchSet_48[0] + matchSet_48[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3520 = matchSet_48[2] + matchSet_48[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3522 = _T_3518 + _T_3520; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_47_2 = matchSet_48[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_47_3 = matchSet_48[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_47_1 = {{1'd0}, matchSet_48[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_143 = matchIndices_47_1 | matchIndices_47_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_47 = _matchIndex_T_143 | matchIndices_47_3; // @[Library.scala 76:39]
- wire _T_3531 = io_ibus_valid & io_ibus_ready & setMatch_189; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_753 = 2'h1 == matchIndex_47 ? history_47_1 : history_47_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_754 = 2'h2 == matchIndex_47 ? history_47_2 : _GEN_753; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_755 = 2'h3 == matchIndex_47 ? history_47_3 : _GEN_754; // @[L1ICache.scala 153:{36,36}]
- wire _T_3533 = history_47_0 > _GEN_755; // @[L1ICache.scala 153:36]
- wire [1:0] _history_47_0_T_1 = history_47_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3539 = history_47_1 > _GEN_755; // @[L1ICache.scala 153:36]
- wire [1:0] _history_47_1_T_1 = history_47_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3545 = history_47_2 > _GEN_755; // @[L1ICache.scala 153:36]
- wire [1:0] _history_47_2_T_1 = history_47_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3551 = history_47_3 > _GEN_755; // @[L1ICache.scala 153:36]
- wire [1:0] _history_47_3_T_1 = history_47_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_49 = matchSlot[195:192]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3560 = matchSet_49[0] + matchSet_49[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3562 = matchSet_49[2] + matchSet_49[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3564 = _T_3560 + _T_3562; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_48_2 = matchSet_49[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_48_3 = matchSet_49[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_48_1 = {{1'd0}, matchSet_49[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_146 = matchIndices_48_1 | matchIndices_48_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_48 = _matchIndex_T_146 | matchIndices_48_3; // @[Library.scala 76:39]
- wire _T_3573 = io_ibus_valid & io_ibus_ready & setMatch_193; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_769 = 2'h1 == matchIndex_48 ? history_48_1 : history_48_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_770 = 2'h2 == matchIndex_48 ? history_48_2 : _GEN_769; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_771 = 2'h3 == matchIndex_48 ? history_48_3 : _GEN_770; // @[L1ICache.scala 153:{36,36}]
- wire _T_3575 = history_48_0 > _GEN_771; // @[L1ICache.scala 153:36]
- wire [1:0] _history_48_0_T_1 = history_48_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3581 = history_48_1 > _GEN_771; // @[L1ICache.scala 153:36]
- wire [1:0] _history_48_1_T_1 = history_48_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3587 = history_48_2 > _GEN_771; // @[L1ICache.scala 153:36]
- wire [1:0] _history_48_2_T_1 = history_48_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3593 = history_48_3 > _GEN_771; // @[L1ICache.scala 153:36]
- wire [1:0] _history_48_3_T_1 = history_48_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_50 = matchSlot[199:196]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3602 = matchSet_50[0] + matchSet_50[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3604 = matchSet_50[2] + matchSet_50[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3606 = _T_3602 + _T_3604; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_49_2 = matchSet_50[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_49_3 = matchSet_50[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_49_1 = {{1'd0}, matchSet_50[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_149 = matchIndices_49_1 | matchIndices_49_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_49 = _matchIndex_T_149 | matchIndices_49_3; // @[Library.scala 76:39]
- wire _T_3615 = io_ibus_valid & io_ibus_ready & setMatch_197; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_785 = 2'h1 == matchIndex_49 ? history_49_1 : history_49_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_786 = 2'h2 == matchIndex_49 ? history_49_2 : _GEN_785; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_787 = 2'h3 == matchIndex_49 ? history_49_3 : _GEN_786; // @[L1ICache.scala 153:{36,36}]
- wire _T_3617 = history_49_0 > _GEN_787; // @[L1ICache.scala 153:36]
- wire [1:0] _history_49_0_T_1 = history_49_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3623 = history_49_1 > _GEN_787; // @[L1ICache.scala 153:36]
- wire [1:0] _history_49_1_T_1 = history_49_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3629 = history_49_2 > _GEN_787; // @[L1ICache.scala 153:36]
- wire [1:0] _history_49_2_T_1 = history_49_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3635 = history_49_3 > _GEN_787; // @[L1ICache.scala 153:36]
- wire [1:0] _history_49_3_T_1 = history_49_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_51 = matchSlot[203:200]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3644 = matchSet_51[0] + matchSet_51[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3646 = matchSet_51[2] + matchSet_51[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3648 = _T_3644 + _T_3646; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_50_2 = matchSet_51[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_50_3 = matchSet_51[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_50_1 = {{1'd0}, matchSet_51[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_152 = matchIndices_50_1 | matchIndices_50_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_50 = _matchIndex_T_152 | matchIndices_50_3; // @[Library.scala 76:39]
- wire _T_3657 = io_ibus_valid & io_ibus_ready & setMatch_201; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_801 = 2'h1 == matchIndex_50 ? history_50_1 : history_50_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_802 = 2'h2 == matchIndex_50 ? history_50_2 : _GEN_801; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_803 = 2'h3 == matchIndex_50 ? history_50_3 : _GEN_802; // @[L1ICache.scala 153:{36,36}]
- wire _T_3659 = history_50_0 > _GEN_803; // @[L1ICache.scala 153:36]
- wire [1:0] _history_50_0_T_1 = history_50_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3665 = history_50_1 > _GEN_803; // @[L1ICache.scala 153:36]
- wire [1:0] _history_50_1_T_1 = history_50_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3671 = history_50_2 > _GEN_803; // @[L1ICache.scala 153:36]
- wire [1:0] _history_50_2_T_1 = history_50_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3677 = history_50_3 > _GEN_803; // @[L1ICache.scala 153:36]
- wire [1:0] _history_50_3_T_1 = history_50_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_52 = matchSlot[207:204]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3686 = matchSet_52[0] + matchSet_52[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3688 = matchSet_52[2] + matchSet_52[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3690 = _T_3686 + _T_3688; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_51_2 = matchSet_52[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_51_3 = matchSet_52[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_51_1 = {{1'd0}, matchSet_52[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_155 = matchIndices_51_1 | matchIndices_51_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_51 = _matchIndex_T_155 | matchIndices_51_3; // @[Library.scala 76:39]
- wire _T_3699 = io_ibus_valid & io_ibus_ready & setMatch_205; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_817 = 2'h1 == matchIndex_51 ? history_51_1 : history_51_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_818 = 2'h2 == matchIndex_51 ? history_51_2 : _GEN_817; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_819 = 2'h3 == matchIndex_51 ? history_51_3 : _GEN_818; // @[L1ICache.scala 153:{36,36}]
- wire _T_3701 = history_51_0 > _GEN_819; // @[L1ICache.scala 153:36]
- wire [1:0] _history_51_0_T_1 = history_51_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3707 = history_51_1 > _GEN_819; // @[L1ICache.scala 153:36]
- wire [1:0] _history_51_1_T_1 = history_51_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3713 = history_51_2 > _GEN_819; // @[L1ICache.scala 153:36]
- wire [1:0] _history_51_2_T_1 = history_51_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3719 = history_51_3 > _GEN_819; // @[L1ICache.scala 153:36]
- wire [1:0] _history_51_3_T_1 = history_51_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_53 = matchSlot[211:208]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3728 = matchSet_53[0] + matchSet_53[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3730 = matchSet_53[2] + matchSet_53[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3732 = _T_3728 + _T_3730; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_52_2 = matchSet_53[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_52_3 = matchSet_53[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_52_1 = {{1'd0}, matchSet_53[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_158 = matchIndices_52_1 | matchIndices_52_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_52 = _matchIndex_T_158 | matchIndices_52_3; // @[Library.scala 76:39]
- wire _T_3741 = io_ibus_valid & io_ibus_ready & setMatch_209; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_833 = 2'h1 == matchIndex_52 ? history_52_1 : history_52_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_834 = 2'h2 == matchIndex_52 ? history_52_2 : _GEN_833; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_835 = 2'h3 == matchIndex_52 ? history_52_3 : _GEN_834; // @[L1ICache.scala 153:{36,36}]
- wire _T_3743 = history_52_0 > _GEN_835; // @[L1ICache.scala 153:36]
- wire [1:0] _history_52_0_T_1 = history_52_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3749 = history_52_1 > _GEN_835; // @[L1ICache.scala 153:36]
- wire [1:0] _history_52_1_T_1 = history_52_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3755 = history_52_2 > _GEN_835; // @[L1ICache.scala 153:36]
- wire [1:0] _history_52_2_T_1 = history_52_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3761 = history_52_3 > _GEN_835; // @[L1ICache.scala 153:36]
- wire [1:0] _history_52_3_T_1 = history_52_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_54 = matchSlot[215:212]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3770 = matchSet_54[0] + matchSet_54[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3772 = matchSet_54[2] + matchSet_54[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3774 = _T_3770 + _T_3772; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_53_2 = matchSet_54[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_53_3 = matchSet_54[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_53_1 = {{1'd0}, matchSet_54[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_161 = matchIndices_53_1 | matchIndices_53_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_53 = _matchIndex_T_161 | matchIndices_53_3; // @[Library.scala 76:39]
- wire _T_3783 = io_ibus_valid & io_ibus_ready & setMatch_213; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_849 = 2'h1 == matchIndex_53 ? history_53_1 : history_53_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_850 = 2'h2 == matchIndex_53 ? history_53_2 : _GEN_849; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_851 = 2'h3 == matchIndex_53 ? history_53_3 : _GEN_850; // @[L1ICache.scala 153:{36,36}]
- wire _T_3785 = history_53_0 > _GEN_851; // @[L1ICache.scala 153:36]
- wire [1:0] _history_53_0_T_1 = history_53_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3791 = history_53_1 > _GEN_851; // @[L1ICache.scala 153:36]
- wire [1:0] _history_53_1_T_1 = history_53_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3797 = history_53_2 > _GEN_851; // @[L1ICache.scala 153:36]
- wire [1:0] _history_53_2_T_1 = history_53_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3803 = history_53_3 > _GEN_851; // @[L1ICache.scala 153:36]
- wire [1:0] _history_53_3_T_1 = history_53_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_55 = matchSlot[219:216]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3812 = matchSet_55[0] + matchSet_55[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3814 = matchSet_55[2] + matchSet_55[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3816 = _T_3812 + _T_3814; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_54_2 = matchSet_55[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_54_3 = matchSet_55[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_54_1 = {{1'd0}, matchSet_55[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_164 = matchIndices_54_1 | matchIndices_54_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_54 = _matchIndex_T_164 | matchIndices_54_3; // @[Library.scala 76:39]
- wire _T_3825 = io_ibus_valid & io_ibus_ready & setMatch_217; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_865 = 2'h1 == matchIndex_54 ? history_54_1 : history_54_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_866 = 2'h2 == matchIndex_54 ? history_54_2 : _GEN_865; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_867 = 2'h3 == matchIndex_54 ? history_54_3 : _GEN_866; // @[L1ICache.scala 153:{36,36}]
- wire _T_3827 = history_54_0 > _GEN_867; // @[L1ICache.scala 153:36]
- wire [1:0] _history_54_0_T_1 = history_54_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3833 = history_54_1 > _GEN_867; // @[L1ICache.scala 153:36]
- wire [1:0] _history_54_1_T_1 = history_54_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3839 = history_54_2 > _GEN_867; // @[L1ICache.scala 153:36]
- wire [1:0] _history_54_2_T_1 = history_54_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3845 = history_54_3 > _GEN_867; // @[L1ICache.scala 153:36]
- wire [1:0] _history_54_3_T_1 = history_54_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_56 = matchSlot[223:220]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3854 = matchSet_56[0] + matchSet_56[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3856 = matchSet_56[2] + matchSet_56[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3858 = _T_3854 + _T_3856; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_55_2 = matchSet_56[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_55_3 = matchSet_56[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_55_1 = {{1'd0}, matchSet_56[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_167 = matchIndices_55_1 | matchIndices_55_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_55 = _matchIndex_T_167 | matchIndices_55_3; // @[Library.scala 76:39]
- wire _T_3867 = io_ibus_valid & io_ibus_ready & setMatch_221; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_881 = 2'h1 == matchIndex_55 ? history_55_1 : history_55_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_882 = 2'h2 == matchIndex_55 ? history_55_2 : _GEN_881; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_883 = 2'h3 == matchIndex_55 ? history_55_3 : _GEN_882; // @[L1ICache.scala 153:{36,36}]
- wire _T_3869 = history_55_0 > _GEN_883; // @[L1ICache.scala 153:36]
- wire [1:0] _history_55_0_T_1 = history_55_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3875 = history_55_1 > _GEN_883; // @[L1ICache.scala 153:36]
- wire [1:0] _history_55_1_T_1 = history_55_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3881 = history_55_2 > _GEN_883; // @[L1ICache.scala 153:36]
- wire [1:0] _history_55_2_T_1 = history_55_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3887 = history_55_3 > _GEN_883; // @[L1ICache.scala 153:36]
- wire [1:0] _history_55_3_T_1 = history_55_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_57 = matchSlot[227:224]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3896 = matchSet_57[0] + matchSet_57[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3898 = matchSet_57[2] + matchSet_57[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3900 = _T_3896 + _T_3898; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_56_2 = matchSet_57[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_56_3 = matchSet_57[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_56_1 = {{1'd0}, matchSet_57[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_170 = matchIndices_56_1 | matchIndices_56_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_56 = _matchIndex_T_170 | matchIndices_56_3; // @[Library.scala 76:39]
- wire _T_3909 = io_ibus_valid & io_ibus_ready & setMatch_225; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_897 = 2'h1 == matchIndex_56 ? history_56_1 : history_56_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_898 = 2'h2 == matchIndex_56 ? history_56_2 : _GEN_897; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_899 = 2'h3 == matchIndex_56 ? history_56_3 : _GEN_898; // @[L1ICache.scala 153:{36,36}]
- wire _T_3911 = history_56_0 > _GEN_899; // @[L1ICache.scala 153:36]
- wire [1:0] _history_56_0_T_1 = history_56_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3917 = history_56_1 > _GEN_899; // @[L1ICache.scala 153:36]
- wire [1:0] _history_56_1_T_1 = history_56_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3923 = history_56_2 > _GEN_899; // @[L1ICache.scala 153:36]
- wire [1:0] _history_56_2_T_1 = history_56_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3929 = history_56_3 > _GEN_899; // @[L1ICache.scala 153:36]
- wire [1:0] _history_56_3_T_1 = history_56_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_58 = matchSlot[231:228]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3938 = matchSet_58[0] + matchSet_58[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3940 = matchSet_58[2] + matchSet_58[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3942 = _T_3938 + _T_3940; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_57_2 = matchSet_58[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_57_3 = matchSet_58[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_57_1 = {{1'd0}, matchSet_58[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_173 = matchIndices_57_1 | matchIndices_57_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_57 = _matchIndex_T_173 | matchIndices_57_3; // @[Library.scala 76:39]
- wire _T_3951 = io_ibus_valid & io_ibus_ready & setMatch_229; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_913 = 2'h1 == matchIndex_57 ? history_57_1 : history_57_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_914 = 2'h2 == matchIndex_57 ? history_57_2 : _GEN_913; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_915 = 2'h3 == matchIndex_57 ? history_57_3 : _GEN_914; // @[L1ICache.scala 153:{36,36}]
- wire _T_3953 = history_57_0 > _GEN_915; // @[L1ICache.scala 153:36]
- wire [1:0] _history_57_0_T_1 = history_57_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3959 = history_57_1 > _GEN_915; // @[L1ICache.scala 153:36]
- wire [1:0] _history_57_1_T_1 = history_57_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3965 = history_57_2 > _GEN_915; // @[L1ICache.scala 153:36]
- wire [1:0] _history_57_2_T_1 = history_57_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_3971 = history_57_3 > _GEN_915; // @[L1ICache.scala 153:36]
- wire [1:0] _history_57_3_T_1 = history_57_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_59 = matchSlot[235:232]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_3980 = matchSet_59[0] + matchSet_59[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_3982 = matchSet_59[2] + matchSet_59[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_3984 = _T_3980 + _T_3982; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_58_2 = matchSet_59[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_58_3 = matchSet_59[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_58_1 = {{1'd0}, matchSet_59[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_176 = matchIndices_58_1 | matchIndices_58_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_58 = _matchIndex_T_176 | matchIndices_58_3; // @[Library.scala 76:39]
- wire _T_3993 = io_ibus_valid & io_ibus_ready & setMatch_233; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_929 = 2'h1 == matchIndex_58 ? history_58_1 : history_58_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_930 = 2'h2 == matchIndex_58 ? history_58_2 : _GEN_929; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_931 = 2'h3 == matchIndex_58 ? history_58_3 : _GEN_930; // @[L1ICache.scala 153:{36,36}]
- wire _T_3995 = history_58_0 > _GEN_931; // @[L1ICache.scala 153:36]
- wire [1:0] _history_58_0_T_1 = history_58_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4001 = history_58_1 > _GEN_931; // @[L1ICache.scala 153:36]
- wire [1:0] _history_58_1_T_1 = history_58_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4007 = history_58_2 > _GEN_931; // @[L1ICache.scala 153:36]
- wire [1:0] _history_58_2_T_1 = history_58_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4013 = history_58_3 > _GEN_931; // @[L1ICache.scala 153:36]
- wire [1:0] _history_58_3_T_1 = history_58_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_60 = matchSlot[239:236]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_4022 = matchSet_60[0] + matchSet_60[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_4024 = matchSet_60[2] + matchSet_60[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_4026 = _T_4022 + _T_4024; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_59_2 = matchSet_60[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_59_3 = matchSet_60[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_59_1 = {{1'd0}, matchSet_60[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_179 = matchIndices_59_1 | matchIndices_59_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_59 = _matchIndex_T_179 | matchIndices_59_3; // @[Library.scala 76:39]
- wire _T_4035 = io_ibus_valid & io_ibus_ready & setMatch_237; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_945 = 2'h1 == matchIndex_59 ? history_59_1 : history_59_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_946 = 2'h2 == matchIndex_59 ? history_59_2 : _GEN_945; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_947 = 2'h3 == matchIndex_59 ? history_59_3 : _GEN_946; // @[L1ICache.scala 153:{36,36}]
- wire _T_4037 = history_59_0 > _GEN_947; // @[L1ICache.scala 153:36]
- wire [1:0] _history_59_0_T_1 = history_59_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4043 = history_59_1 > _GEN_947; // @[L1ICache.scala 153:36]
- wire [1:0] _history_59_1_T_1 = history_59_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4049 = history_59_2 > _GEN_947; // @[L1ICache.scala 153:36]
- wire [1:0] _history_59_2_T_1 = history_59_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4055 = history_59_3 > _GEN_947; // @[L1ICache.scala 153:36]
- wire [1:0] _history_59_3_T_1 = history_59_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_61 = matchSlot[243:240]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_4064 = matchSet_61[0] + matchSet_61[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_4066 = matchSet_61[2] + matchSet_61[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_4068 = _T_4064 + _T_4066; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_60_2 = matchSet_61[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_60_3 = matchSet_61[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_60_1 = {{1'd0}, matchSet_61[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_182 = matchIndices_60_1 | matchIndices_60_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_60 = _matchIndex_T_182 | matchIndices_60_3; // @[Library.scala 76:39]
- wire _T_4077 = io_ibus_valid & io_ibus_ready & setMatch_241; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_961 = 2'h1 == matchIndex_60 ? history_60_1 : history_60_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_962 = 2'h2 == matchIndex_60 ? history_60_2 : _GEN_961; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_963 = 2'h3 == matchIndex_60 ? history_60_3 : _GEN_962; // @[L1ICache.scala 153:{36,36}]
- wire _T_4079 = history_60_0 > _GEN_963; // @[L1ICache.scala 153:36]
- wire [1:0] _history_60_0_T_1 = history_60_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4085 = history_60_1 > _GEN_963; // @[L1ICache.scala 153:36]
- wire [1:0] _history_60_1_T_1 = history_60_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4091 = history_60_2 > _GEN_963; // @[L1ICache.scala 153:36]
- wire [1:0] _history_60_2_T_1 = history_60_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4097 = history_60_3 > _GEN_963; // @[L1ICache.scala 153:36]
- wire [1:0] _history_60_3_T_1 = history_60_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_62 = matchSlot[247:244]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_4106 = matchSet_62[0] + matchSet_62[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_4108 = matchSet_62[2] + matchSet_62[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_4110 = _T_4106 + _T_4108; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_61_2 = matchSet_62[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_61_3 = matchSet_62[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_61_1 = {{1'd0}, matchSet_62[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_185 = matchIndices_61_1 | matchIndices_61_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_61 = _matchIndex_T_185 | matchIndices_61_3; // @[Library.scala 76:39]
- wire _T_4119 = io_ibus_valid & io_ibus_ready & setMatch_245; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_977 = 2'h1 == matchIndex_61 ? history_61_1 : history_61_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_978 = 2'h2 == matchIndex_61 ? history_61_2 : _GEN_977; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_979 = 2'h3 == matchIndex_61 ? history_61_3 : _GEN_978; // @[L1ICache.scala 153:{36,36}]
- wire _T_4121 = history_61_0 > _GEN_979; // @[L1ICache.scala 153:36]
- wire [1:0] _history_61_0_T_1 = history_61_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4127 = history_61_1 > _GEN_979; // @[L1ICache.scala 153:36]
- wire [1:0] _history_61_1_T_1 = history_61_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4133 = history_61_2 > _GEN_979; // @[L1ICache.scala 153:36]
- wire [1:0] _history_61_2_T_1 = history_61_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4139 = history_61_3 > _GEN_979; // @[L1ICache.scala 153:36]
- wire [1:0] _history_61_3_T_1 = history_61_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_63 = matchSlot[251:248]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_4148 = matchSet_63[0] + matchSet_63[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_4150 = matchSet_63[2] + matchSet_63[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_4152 = _T_4148 + _T_4150; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_62_2 = matchSet_63[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_62_3 = matchSet_63[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_62_1 = {{1'd0}, matchSet_63[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_188 = matchIndices_62_1 | matchIndices_62_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_62 = _matchIndex_T_188 | matchIndices_62_3; // @[Library.scala 76:39]
- wire _T_4161 = io_ibus_valid & io_ibus_ready & setMatch_249; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_993 = 2'h1 == matchIndex_62 ? history_62_1 : history_62_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_994 = 2'h2 == matchIndex_62 ? history_62_2 : _GEN_993; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_995 = 2'h3 == matchIndex_62 ? history_62_3 : _GEN_994; // @[L1ICache.scala 153:{36,36}]
- wire _T_4163 = history_62_0 > _GEN_995; // @[L1ICache.scala 153:36]
- wire [1:0] _history_62_0_T_1 = history_62_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4169 = history_62_1 > _GEN_995; // @[L1ICache.scala 153:36]
- wire [1:0] _history_62_1_T_1 = history_62_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4175 = history_62_2 > _GEN_995; // @[L1ICache.scala 153:36]
- wire [1:0] _history_62_2_T_1 = history_62_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4181 = history_62_3 > _GEN_995; // @[L1ICache.scala 153:36]
- wire [1:0] _history_62_3_T_1 = history_62_3 - 2'h1; // @[L1ICache.scala 154:42]
- wire [3:0] matchSet_64 = matchSlot[255:252]; // @[L1ICache.scala 138:29]
- wire [1:0] _T_4190 = matchSet_64[0] + matchSet_64[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_4192 = matchSet_64[2] + matchSet_64[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_4194 = _T_4190 + _T_4192; // @[Bitwise.scala 48:55]
- wire [1:0] matchIndices_63_2 = matchSet_64[2] ? 2'h2 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_63_3 = matchSet_64[3] ? 2'h3 : 2'h0; // @[Library.scala 22:8]
- wire [1:0] matchIndices_63_1 = {{1'd0}, matchSet_64[1]}; // @[L1ICache.scala 140:28 142:23]
- wire [1:0] _matchIndex_T_191 = matchIndices_63_1 | matchIndices_63_2; // @[Library.scala 76:39]
- wire [1:0] matchIndex_63 = _matchIndex_T_191 | matchIndices_63_3; // @[Library.scala 76:39]
- wire _T_4203 = io_ibus_valid & io_ibus_ready & setMatch_253; // @[L1ICache.scala 149:42]
- wire [1:0] _GEN_1009 = 2'h1 == matchIndex_63 ? history_63_1 : history_63_0; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_1010 = 2'h2 == matchIndex_63 ? history_63_2 : _GEN_1009; // @[L1ICache.scala 153:{36,36}]
- wire [1:0] _GEN_1011 = 2'h3 == matchIndex_63 ? history_63_3 : _GEN_1010; // @[L1ICache.scala 153:{36,36}]
- wire _T_4205 = history_63_0 > _GEN_1011; // @[L1ICache.scala 153:36]
- wire [1:0] _history_63_0_T_1 = history_63_0 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4211 = history_63_1 > _GEN_1011; // @[L1ICache.scala 153:36]
- wire [1:0] _history_63_1_T_1 = history_63_1 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4217 = history_63_2 > _GEN_1011; // @[L1ICache.scala 153:36]
- wire [1:0] _history_63_2_T_1 = history_63_2 - 2'h1; // @[L1ICache.scala 154:42]
- wire _T_4223 = history_63_3 > _GEN_1011; // @[L1ICache.scala 153:36]
- wire [1:0] _history_63_3_T_1 = history_63_3 - 2'h1; // @[L1ICache.scala 154:42]
- reg axivalid; // @[L1ICache.scala 193:25]
- reg axiready; // @[L1ICache.scala 194:25]
- reg [31:0] axiaddr; // @[L1ICache.scala 195:20]
- reg [7:0] replaceIdReg; // @[L1ICache.scala 197:25]
- wire _T_4230 = io_ibus_valid & ~io_ibus_ready; // @[L1ICache.scala 199:23]
- wire _T_4231 = ~axivalid; // @[L1ICache.scala 199:44]
- wire _T_4233 = ~axiready; // @[L1ICache.scala 199:57]
- wire _T_4234 = io_ibus_valid & ~io_ibus_ready & ~axivalid & ~axiready; // @[L1ICache.scala 199:54]
- wire _T_4235 = io_axi_read_addr_valid & io_axi_read_addr_ready; // @[L1ICache.scala 203:32]
- wire _GEN_1281 = _T_4234 | axivalid; // @[L1ICache.scala 205:75 206:14 193:25]
- wire _T_4242 = io_axi_read_data_valid & io_axi_read_data_ready; // @[L1ICache.scala 209:32]
- wire _GEN_1283 = _T_4235 & _T_4233 | axiready; // @[L1ICache.scala 211:79 212:14 194:25]
- wire _GEN_1541 = 8'h0 == replaceIdReg | valid_0; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1542 = 8'h1 == replaceIdReg | valid_1; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1543 = 8'h2 == replaceIdReg | valid_2; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1544 = 8'h3 == replaceIdReg | valid_3; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1545 = 8'h4 == replaceIdReg | valid_4; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1546 = 8'h5 == replaceIdReg | valid_5; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1547 = 8'h6 == replaceIdReg | valid_6; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1548 = 8'h7 == replaceIdReg | valid_7; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1549 = 8'h8 == replaceIdReg | valid_8; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1550 = 8'h9 == replaceIdReg | valid_9; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1551 = 8'ha == replaceIdReg | valid_10; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1552 = 8'hb == replaceIdReg | valid_11; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1553 = 8'hc == replaceIdReg | valid_12; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1554 = 8'hd == replaceIdReg | valid_13; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1555 = 8'he == replaceIdReg | valid_14; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1556 = 8'hf == replaceIdReg | valid_15; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1557 = 8'h10 == replaceIdReg | valid_16; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1558 = 8'h11 == replaceIdReg | valid_17; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1559 = 8'h12 == replaceIdReg | valid_18; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1560 = 8'h13 == replaceIdReg | valid_19; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1561 = 8'h14 == replaceIdReg | valid_20; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1562 = 8'h15 == replaceIdReg | valid_21; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1563 = 8'h16 == replaceIdReg | valid_22; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1564 = 8'h17 == replaceIdReg | valid_23; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1565 = 8'h18 == replaceIdReg | valid_24; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1566 = 8'h19 == replaceIdReg | valid_25; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1567 = 8'h1a == replaceIdReg | valid_26; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1568 = 8'h1b == replaceIdReg | valid_27; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1569 = 8'h1c == replaceIdReg | valid_28; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1570 = 8'h1d == replaceIdReg | valid_29; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1571 = 8'h1e == replaceIdReg | valid_30; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1572 = 8'h1f == replaceIdReg | valid_31; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1573 = 8'h20 == replaceIdReg | valid_32; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1574 = 8'h21 == replaceIdReg | valid_33; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1575 = 8'h22 == replaceIdReg | valid_34; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1576 = 8'h23 == replaceIdReg | valid_35; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1577 = 8'h24 == replaceIdReg | valid_36; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1578 = 8'h25 == replaceIdReg | valid_37; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1579 = 8'h26 == replaceIdReg | valid_38; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1580 = 8'h27 == replaceIdReg | valid_39; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1581 = 8'h28 == replaceIdReg | valid_40; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1582 = 8'h29 == replaceIdReg | valid_41; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1583 = 8'h2a == replaceIdReg | valid_42; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1584 = 8'h2b == replaceIdReg | valid_43; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1585 = 8'h2c == replaceIdReg | valid_44; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1586 = 8'h2d == replaceIdReg | valid_45; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1587 = 8'h2e == replaceIdReg | valid_46; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1588 = 8'h2f == replaceIdReg | valid_47; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1589 = 8'h30 == replaceIdReg | valid_48; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1590 = 8'h31 == replaceIdReg | valid_49; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1591 = 8'h32 == replaceIdReg | valid_50; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1592 = 8'h33 == replaceIdReg | valid_51; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1593 = 8'h34 == replaceIdReg | valid_52; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1594 = 8'h35 == replaceIdReg | valid_53; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1595 = 8'h36 == replaceIdReg | valid_54; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1596 = 8'h37 == replaceIdReg | valid_55; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1597 = 8'h38 == replaceIdReg | valid_56; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1598 = 8'h39 == replaceIdReg | valid_57; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1599 = 8'h3a == replaceIdReg | valid_58; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1600 = 8'h3b == replaceIdReg | valid_59; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1601 = 8'h3c == replaceIdReg | valid_60; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1602 = 8'h3d == replaceIdReg | valid_61; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1603 = 8'h3e == replaceIdReg | valid_62; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1604 = 8'h3f == replaceIdReg | valid_63; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1605 = 8'h40 == replaceIdReg | valid_64; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1606 = 8'h41 == replaceIdReg | valid_65; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1607 = 8'h42 == replaceIdReg | valid_66; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1608 = 8'h43 == replaceIdReg | valid_67; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1609 = 8'h44 == replaceIdReg | valid_68; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1610 = 8'h45 == replaceIdReg | valid_69; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1611 = 8'h46 == replaceIdReg | valid_70; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1612 = 8'h47 == replaceIdReg | valid_71; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1613 = 8'h48 == replaceIdReg | valid_72; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1614 = 8'h49 == replaceIdReg | valid_73; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1615 = 8'h4a == replaceIdReg | valid_74; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1616 = 8'h4b == replaceIdReg | valid_75; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1617 = 8'h4c == replaceIdReg | valid_76; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1618 = 8'h4d == replaceIdReg | valid_77; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1619 = 8'h4e == replaceIdReg | valid_78; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1620 = 8'h4f == replaceIdReg | valid_79; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1621 = 8'h50 == replaceIdReg | valid_80; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1622 = 8'h51 == replaceIdReg | valid_81; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1623 = 8'h52 == replaceIdReg | valid_82; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1624 = 8'h53 == replaceIdReg | valid_83; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1625 = 8'h54 == replaceIdReg | valid_84; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1626 = 8'h55 == replaceIdReg | valid_85; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1627 = 8'h56 == replaceIdReg | valid_86; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1628 = 8'h57 == replaceIdReg | valid_87; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1629 = 8'h58 == replaceIdReg | valid_88; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1630 = 8'h59 == replaceIdReg | valid_89; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1631 = 8'h5a == replaceIdReg | valid_90; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1632 = 8'h5b == replaceIdReg | valid_91; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1633 = 8'h5c == replaceIdReg | valid_92; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1634 = 8'h5d == replaceIdReg | valid_93; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1635 = 8'h5e == replaceIdReg | valid_94; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1636 = 8'h5f == replaceIdReg | valid_95; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1637 = 8'h60 == replaceIdReg | valid_96; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1638 = 8'h61 == replaceIdReg | valid_97; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1639 = 8'h62 == replaceIdReg | valid_98; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1640 = 8'h63 == replaceIdReg | valid_99; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1641 = 8'h64 == replaceIdReg | valid_100; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1642 = 8'h65 == replaceIdReg | valid_101; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1643 = 8'h66 == replaceIdReg | valid_102; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1644 = 8'h67 == replaceIdReg | valid_103; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1645 = 8'h68 == replaceIdReg | valid_104; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1646 = 8'h69 == replaceIdReg | valid_105; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1647 = 8'h6a == replaceIdReg | valid_106; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1648 = 8'h6b == replaceIdReg | valid_107; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1649 = 8'h6c == replaceIdReg | valid_108; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1650 = 8'h6d == replaceIdReg | valid_109; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1651 = 8'h6e == replaceIdReg | valid_110; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1652 = 8'h6f == replaceIdReg | valid_111; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1653 = 8'h70 == replaceIdReg | valid_112; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1654 = 8'h71 == replaceIdReg | valid_113; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1655 = 8'h72 == replaceIdReg | valid_114; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1656 = 8'h73 == replaceIdReg | valid_115; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1657 = 8'h74 == replaceIdReg | valid_116; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1658 = 8'h75 == replaceIdReg | valid_117; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1659 = 8'h76 == replaceIdReg | valid_118; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1660 = 8'h77 == replaceIdReg | valid_119; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1661 = 8'h78 == replaceIdReg | valid_120; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1662 = 8'h79 == replaceIdReg | valid_121; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1663 = 8'h7a == replaceIdReg | valid_122; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1664 = 8'h7b == replaceIdReg | valid_123; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1665 = 8'h7c == replaceIdReg | valid_124; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1666 = 8'h7d == replaceIdReg | valid_125; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1667 = 8'h7e == replaceIdReg | valid_126; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1668 = 8'h7f == replaceIdReg | valid_127; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1669 = 8'h80 == replaceIdReg | valid_128; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1670 = 8'h81 == replaceIdReg | valid_129; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1671 = 8'h82 == replaceIdReg | valid_130; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1672 = 8'h83 == replaceIdReg | valid_131; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1673 = 8'h84 == replaceIdReg | valid_132; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1674 = 8'h85 == replaceIdReg | valid_133; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1675 = 8'h86 == replaceIdReg | valid_134; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1676 = 8'h87 == replaceIdReg | valid_135; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1677 = 8'h88 == replaceIdReg | valid_136; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1678 = 8'h89 == replaceIdReg | valid_137; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1679 = 8'h8a == replaceIdReg | valid_138; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1680 = 8'h8b == replaceIdReg | valid_139; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1681 = 8'h8c == replaceIdReg | valid_140; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1682 = 8'h8d == replaceIdReg | valid_141; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1683 = 8'h8e == replaceIdReg | valid_142; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1684 = 8'h8f == replaceIdReg | valid_143; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1685 = 8'h90 == replaceIdReg | valid_144; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1686 = 8'h91 == replaceIdReg | valid_145; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1687 = 8'h92 == replaceIdReg | valid_146; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1688 = 8'h93 == replaceIdReg | valid_147; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1689 = 8'h94 == replaceIdReg | valid_148; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1690 = 8'h95 == replaceIdReg | valid_149; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1691 = 8'h96 == replaceIdReg | valid_150; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1692 = 8'h97 == replaceIdReg | valid_151; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1693 = 8'h98 == replaceIdReg | valid_152; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1694 = 8'h99 == replaceIdReg | valid_153; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1695 = 8'h9a == replaceIdReg | valid_154; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1696 = 8'h9b == replaceIdReg | valid_155; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1697 = 8'h9c == replaceIdReg | valid_156; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1698 = 8'h9d == replaceIdReg | valid_157; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1699 = 8'h9e == replaceIdReg | valid_158; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1700 = 8'h9f == replaceIdReg | valid_159; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1701 = 8'ha0 == replaceIdReg | valid_160; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1702 = 8'ha1 == replaceIdReg | valid_161; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1703 = 8'ha2 == replaceIdReg | valid_162; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1704 = 8'ha3 == replaceIdReg | valid_163; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1705 = 8'ha4 == replaceIdReg | valid_164; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1706 = 8'ha5 == replaceIdReg | valid_165; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1707 = 8'ha6 == replaceIdReg | valid_166; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1708 = 8'ha7 == replaceIdReg | valid_167; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1709 = 8'ha8 == replaceIdReg | valid_168; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1710 = 8'ha9 == replaceIdReg | valid_169; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1711 = 8'haa == replaceIdReg | valid_170; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1712 = 8'hab == replaceIdReg | valid_171; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1713 = 8'hac == replaceIdReg | valid_172; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1714 = 8'had == replaceIdReg | valid_173; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1715 = 8'hae == replaceIdReg | valid_174; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1716 = 8'haf == replaceIdReg | valid_175; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1717 = 8'hb0 == replaceIdReg | valid_176; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1718 = 8'hb1 == replaceIdReg | valid_177; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1719 = 8'hb2 == replaceIdReg | valid_178; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1720 = 8'hb3 == replaceIdReg | valid_179; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1721 = 8'hb4 == replaceIdReg | valid_180; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1722 = 8'hb5 == replaceIdReg | valid_181; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1723 = 8'hb6 == replaceIdReg | valid_182; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1724 = 8'hb7 == replaceIdReg | valid_183; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1725 = 8'hb8 == replaceIdReg | valid_184; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1726 = 8'hb9 == replaceIdReg | valid_185; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1727 = 8'hba == replaceIdReg | valid_186; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1728 = 8'hbb == replaceIdReg | valid_187; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1729 = 8'hbc == replaceIdReg | valid_188; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1730 = 8'hbd == replaceIdReg | valid_189; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1731 = 8'hbe == replaceIdReg | valid_190; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1732 = 8'hbf == replaceIdReg | valid_191; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1733 = 8'hc0 == replaceIdReg | valid_192; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1734 = 8'hc1 == replaceIdReg | valid_193; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1735 = 8'hc2 == replaceIdReg | valid_194; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1736 = 8'hc3 == replaceIdReg | valid_195; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1737 = 8'hc4 == replaceIdReg | valid_196; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1738 = 8'hc5 == replaceIdReg | valid_197; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1739 = 8'hc6 == replaceIdReg | valid_198; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1740 = 8'hc7 == replaceIdReg | valid_199; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1741 = 8'hc8 == replaceIdReg | valid_200; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1742 = 8'hc9 == replaceIdReg | valid_201; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1743 = 8'hca == replaceIdReg | valid_202; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1744 = 8'hcb == replaceIdReg | valid_203; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1745 = 8'hcc == replaceIdReg | valid_204; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1746 = 8'hcd == replaceIdReg | valid_205; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1747 = 8'hce == replaceIdReg | valid_206; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1748 = 8'hcf == replaceIdReg | valid_207; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1749 = 8'hd0 == replaceIdReg | valid_208; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1750 = 8'hd1 == replaceIdReg | valid_209; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1751 = 8'hd2 == replaceIdReg | valid_210; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1752 = 8'hd3 == replaceIdReg | valid_211; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1753 = 8'hd4 == replaceIdReg | valid_212; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1754 = 8'hd5 == replaceIdReg | valid_213; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1755 = 8'hd6 == replaceIdReg | valid_214; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1756 = 8'hd7 == replaceIdReg | valid_215; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1757 = 8'hd8 == replaceIdReg | valid_216; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1758 = 8'hd9 == replaceIdReg | valid_217; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1759 = 8'hda == replaceIdReg | valid_218; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1760 = 8'hdb == replaceIdReg | valid_219; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1761 = 8'hdc == replaceIdReg | valid_220; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1762 = 8'hdd == replaceIdReg | valid_221; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1763 = 8'hde == replaceIdReg | valid_222; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1764 = 8'hdf == replaceIdReg | valid_223; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1765 = 8'he0 == replaceIdReg | valid_224; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1766 = 8'he1 == replaceIdReg | valid_225; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1767 = 8'he2 == replaceIdReg | valid_226; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1768 = 8'he3 == replaceIdReg | valid_227; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1769 = 8'he4 == replaceIdReg | valid_228; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1770 = 8'he5 == replaceIdReg | valid_229; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1771 = 8'he6 == replaceIdReg | valid_230; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1772 = 8'he7 == replaceIdReg | valid_231; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1773 = 8'he8 == replaceIdReg | valid_232; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1774 = 8'he9 == replaceIdReg | valid_233; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1775 = 8'hea == replaceIdReg | valid_234; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1776 = 8'heb == replaceIdReg | valid_235; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1777 = 8'hec == replaceIdReg | valid_236; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1778 = 8'hed == replaceIdReg | valid_237; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1779 = 8'hee == replaceIdReg | valid_238; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1780 = 8'hef == replaceIdReg | valid_239; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1781 = 8'hf0 == replaceIdReg | valid_240; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1782 = 8'hf1 == replaceIdReg | valid_241; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1783 = 8'hf2 == replaceIdReg | valid_242; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1784 = 8'hf3 == replaceIdReg | valid_243; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1785 = 8'hf4 == replaceIdReg | valid_244; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1786 = 8'hf5 == replaceIdReg | valid_245; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1787 = 8'hf6 == replaceIdReg | valid_246; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1788 = 8'hf7 == replaceIdReg | valid_247; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1789 = 8'hf8 == replaceIdReg | valid_248; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1790 = 8'hf9 == replaceIdReg | valid_249; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1791 = 8'hfa == replaceIdReg | valid_250; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1792 = 8'hfb == replaceIdReg | valid_251; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1793 = 8'hfc == replaceIdReg | valid_252; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1794 = 8'hfd == replaceIdReg | valid_253; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1795 = 8'hfe == replaceIdReg | valid_254; // @[L1ICache.scala 222:{25,25} 72:22]
- wire _GEN_1796 = 8'hff == replaceIdReg | valid_255; // @[L1ICache.scala 222:{25,25} 72:22]
- wire [31:0] alignedAddr = {io_ibus_addr[31:5],5'h0}; // @[Cat.scala 31:58]
- wire [31:0] _axiaddr_T_1 = axiaddr + 32'h20; // @[L1ICache.scala 230:24]
- reg addrLatchActive; // @[L1ICache.scala 242:32]
- reg [31:0] addrLatchData; // @[L1ICache.scala 243:26]
- wire _GEN_3079 = addrLatchActive & io_ibus_ready ? 1'h0 : addrLatchActive; // @[L1ICache.scala 250:50 251:21 242:32]
- wire _GEN_3080 = _T_4230 & ~addrLatchActive | _GEN_3079; // @[L1ICache.scala 247:69 248:21]
- wire memread = io_ibus_valid & _T_4231 & _T_4233; // @[L1ICache.scala 260:45]
- Sram_1rw_256x256 mem ( // @[L1ICache.scala 74:19]
- .clock(mem_clock),
- .valid(mem_valid),
- .write(mem_write),
- .addr(mem_addr),
- .wdata(mem_wdata),
- .rdata(mem_rdata),
- .volt_sel(mem_volt_sel)
- );
- assign io_ibus_ready = io_ibus_valid & matchSlot != 256'h0; // @[L1ICache.scala 120:29]
- assign io_ibus_rdata = mem_rdata; // @[L1ICache.scala 189:17]
- assign io_axi_read_addr_valid = axivalid; // @[L1ICache.scala 234:26]
- assign io_axi_read_addr_bits_addr = axiaddr; // @[L1ICache.scala 235:30]
- assign io_axi_read_data_ready = axiready; // @[L1ICache.scala 237:26]
- assign mem_clock = clock; // @[L1ICache.scala 261:19]
- assign mem_valid = memread | _T_4242; // @[L1ICache.scala 262:30]
- assign mem_write = axiready; // @[L1ICache.scala 263:19]
- assign mem_addr = axiready ? replaceIdReg : readId; // @[L1ICache.scala 264:25]
- assign mem_wdata = io_axi_read_data_bits_data; // @[L1ICache.scala 265:19]
- assign mem_volt_sel = io_volt_sel; // @[L1ICache.scala 266:19]
- always @(posedge clock) begin
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h0 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_0 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h1 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_1 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h2 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_2 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h3 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_3 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h4 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_4 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h5 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_5 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h6 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_6 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h7 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_7 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h8 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_8 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h9 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_9 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'ha == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_10 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hb == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_11 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hc == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_12 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hd == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_13 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'he == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_14 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hf == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_15 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h10 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_16 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h11 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_17 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h12 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_18 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h13 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_19 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h14 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_20 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h15 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_21 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h16 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_22 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h17 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_23 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h18 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_24 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h19 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_25 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h1a == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_26 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h1b == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_27 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h1c == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_28 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h1d == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_29 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h1e == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_30 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h1f == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_31 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h20 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_32 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h21 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_33 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h22 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_34 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h23 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_35 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h24 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_36 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h25 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_37 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h26 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_38 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h27 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_39 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h28 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_40 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h29 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_41 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h2a == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_42 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h2b == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_43 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h2c == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_44 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h2d == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_45 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h2e == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_46 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h2f == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_47 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h30 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_48 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h31 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_49 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h32 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_50 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h33 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_51 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h34 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_52 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h35 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_53 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h36 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_54 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h37 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_55 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h38 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_56 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h39 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_57 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h3a == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_58 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h3b == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_59 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h3c == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_60 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h3d == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_61 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h3e == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_62 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h3f == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_63 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h40 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_64 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h41 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_65 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h42 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_66 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h43 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_67 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h44 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_68 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h45 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_69 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h46 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_70 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h47 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_71 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h48 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_72 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h49 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_73 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h4a == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_74 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h4b == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_75 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h4c == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_76 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h4d == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_77 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h4e == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_78 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h4f == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_79 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h50 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_80 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h51 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_81 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h52 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_82 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h53 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_83 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h54 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_84 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h55 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_85 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h56 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_86 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h57 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_87 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h58 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_88 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h59 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_89 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h5a == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_90 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h5b == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_91 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h5c == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_92 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h5d == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_93 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h5e == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_94 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h5f == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_95 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h60 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_96 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h61 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_97 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h62 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_98 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h63 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_99 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h64 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_100 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h65 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_101 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h66 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_102 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h67 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_103 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h68 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_104 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h69 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_105 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h6a == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_106 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h6b == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_107 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h6c == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_108 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h6d == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_109 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h6e == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_110 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h6f == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_111 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h70 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_112 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h71 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_113 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h72 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_114 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h73 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_115 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h74 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_116 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h75 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_117 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h76 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_118 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h77 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_119 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h78 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_120 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h79 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_121 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h7a == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_122 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h7b == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_123 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h7c == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_124 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h7d == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_125 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h7e == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_126 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h7f == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_127 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h80 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_128 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h81 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_129 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h82 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_130 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h83 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_131 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h84 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_132 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h85 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_133 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h86 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_134 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h87 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_135 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h88 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_136 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h89 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_137 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h8a == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_138 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h8b == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_139 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h8c == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_140 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h8d == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_141 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h8e == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_142 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h8f == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_143 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h90 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_144 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h91 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_145 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h92 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_146 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h93 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_147 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h94 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_148 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h95 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_149 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h96 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_150 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h97 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_151 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h98 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_152 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h99 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_153 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h9a == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_154 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h9b == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_155 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h9c == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_156 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h9d == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_157 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h9e == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_158 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'h9f == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_159 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'ha0 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_160 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'ha1 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_161 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'ha2 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_162 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'ha3 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_163 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'ha4 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_164 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'ha5 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_165 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'ha6 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_166 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'ha7 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_167 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'ha8 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_168 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'ha9 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_169 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'haa == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_170 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hab == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_171 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hac == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_172 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'had == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_173 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hae == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_174 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'haf == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_175 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hb0 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_176 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hb1 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_177 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hb2 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_178 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hb3 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_179 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hb4 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_180 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hb5 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_181 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hb6 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_182 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hb7 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_183 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hb8 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_184 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hb9 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_185 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hba == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_186 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hbb == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_187 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hbc == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_188 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hbd == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_189 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hbe == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_190 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hbf == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_191 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hc0 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_192 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hc1 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_193 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hc2 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_194 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hc3 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_195 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hc4 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_196 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hc5 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_197 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hc6 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_198 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hc7 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_199 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hc8 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_200 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hc9 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_201 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hca == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_202 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hcb == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_203 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hcc == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_204 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hcd == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_205 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hce == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_206 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hcf == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_207 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hd0 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_208 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hd1 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_209 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hd2 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_210 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hd3 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_211 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hd4 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_212 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hd5 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_213 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hd6 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_214 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hd7 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_215 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hd8 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_216 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hd9 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_217 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hda == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_218 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hdb == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_219 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hdc == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_220 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hdd == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_221 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hde == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_222 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hdf == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_223 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'he0 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_224 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'he1 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_225 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'he2 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_226 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'he3 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_227 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'he4 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_228 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'he5 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_229 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'he6 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_230 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'he7 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_231 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'he8 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_232 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'he9 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_233 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hea == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_234 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'heb == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_235 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hec == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_236 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hed == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_237 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hee == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_238 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hef == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_239 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hf0 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_240 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hf1 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_241 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hf2 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_242 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hf3 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_243 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hf4 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_244 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hf5 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_245 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hf6 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_246 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hf7 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_247 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hf8 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_248 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hf9 == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_249 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hfa == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_250 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hfb == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_251 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hfc == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_252 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hfd == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_253 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hfe == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_254 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- if (8'hff == replaceId) begin // @[L1ICache.scala 228:24]
- camaddr_255 <= alignedAddr; // @[L1ICache.scala 228:24]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_0_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_1) begin // @[L1ICache.scala 149:117]
- if (matchSet_1[0]) begin // @[L1ICache.scala 151:28]
- history_0_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_0_0 > _GEN_3) begin // @[L1ICache.scala 153:50]
- history_0_0 <= _history_0_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_0_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_1) begin // @[L1ICache.scala 149:117]
- if (matchSet_1[1]) begin // @[L1ICache.scala 151:28]
- history_0_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_0_1 > _GEN_3) begin // @[L1ICache.scala 153:50]
- history_0_1 <= _history_0_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_0_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_1) begin // @[L1ICache.scala 149:117]
- if (matchSet_1[2]) begin // @[L1ICache.scala 151:28]
- history_0_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_0_2 > _GEN_3) begin // @[L1ICache.scala 153:50]
- history_0_2 <= _history_0_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_0_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_1) begin // @[L1ICache.scala 149:117]
- if (matchSet_1[3]) begin // @[L1ICache.scala 151:28]
- history_0_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_0_3 > _GEN_3) begin // @[L1ICache.scala 153:50]
- history_0_3 <= _history_0_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_1_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_5) begin // @[L1ICache.scala 149:117]
- if (matchSet_2[0]) begin // @[L1ICache.scala 151:28]
- history_1_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_1_0 > _GEN_19) begin // @[L1ICache.scala 153:50]
- history_1_0 <= _history_1_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_1_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_5) begin // @[L1ICache.scala 149:117]
- if (matchSet_2[1]) begin // @[L1ICache.scala 151:28]
- history_1_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_1_1 > _GEN_19) begin // @[L1ICache.scala 153:50]
- history_1_1 <= _history_1_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_1_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_5) begin // @[L1ICache.scala 149:117]
- if (matchSet_2[2]) begin // @[L1ICache.scala 151:28]
- history_1_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_1_2 > _GEN_19) begin // @[L1ICache.scala 153:50]
- history_1_2 <= _history_1_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_1_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_5) begin // @[L1ICache.scala 149:117]
- if (matchSet_2[3]) begin // @[L1ICache.scala 151:28]
- history_1_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_1_3 > _GEN_19) begin // @[L1ICache.scala 153:50]
- history_1_3 <= _history_1_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_2_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_9) begin // @[L1ICache.scala 149:117]
- if (matchSet_3[0]) begin // @[L1ICache.scala 151:28]
- history_2_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_2_0 > _GEN_35) begin // @[L1ICache.scala 153:50]
- history_2_0 <= _history_2_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_2_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_9) begin // @[L1ICache.scala 149:117]
- if (matchSet_3[1]) begin // @[L1ICache.scala 151:28]
- history_2_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_2_1 > _GEN_35) begin // @[L1ICache.scala 153:50]
- history_2_1 <= _history_2_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_2_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_9) begin // @[L1ICache.scala 149:117]
- if (matchSet_3[2]) begin // @[L1ICache.scala 151:28]
- history_2_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_2_2 > _GEN_35) begin // @[L1ICache.scala 153:50]
- history_2_2 <= _history_2_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_2_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_9) begin // @[L1ICache.scala 149:117]
- if (matchSet_3[3]) begin // @[L1ICache.scala 151:28]
- history_2_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_2_3 > _GEN_35) begin // @[L1ICache.scala 153:50]
- history_2_3 <= _history_2_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_3_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_13) begin // @[L1ICache.scala 149:117]
- if (matchSet_4[0]) begin // @[L1ICache.scala 151:28]
- history_3_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_3_0 > _GEN_51) begin // @[L1ICache.scala 153:50]
- history_3_0 <= _history_3_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_3_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_13) begin // @[L1ICache.scala 149:117]
- if (matchSet_4[1]) begin // @[L1ICache.scala 151:28]
- history_3_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_3_1 > _GEN_51) begin // @[L1ICache.scala 153:50]
- history_3_1 <= _history_3_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_3_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_13) begin // @[L1ICache.scala 149:117]
- if (matchSet_4[2]) begin // @[L1ICache.scala 151:28]
- history_3_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_3_2 > _GEN_51) begin // @[L1ICache.scala 153:50]
- history_3_2 <= _history_3_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_3_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_13) begin // @[L1ICache.scala 149:117]
- if (matchSet_4[3]) begin // @[L1ICache.scala 151:28]
- history_3_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_3_3 > _GEN_51) begin // @[L1ICache.scala 153:50]
- history_3_3 <= _history_3_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_4_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_17) begin // @[L1ICache.scala 149:117]
- if (matchSet_5[0]) begin // @[L1ICache.scala 151:28]
- history_4_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_4_0 > _GEN_67) begin // @[L1ICache.scala 153:50]
- history_4_0 <= _history_4_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_4_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_17) begin // @[L1ICache.scala 149:117]
- if (matchSet_5[1]) begin // @[L1ICache.scala 151:28]
- history_4_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_4_1 > _GEN_67) begin // @[L1ICache.scala 153:50]
- history_4_1 <= _history_4_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_4_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_17) begin // @[L1ICache.scala 149:117]
- if (matchSet_5[2]) begin // @[L1ICache.scala 151:28]
- history_4_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_4_2 > _GEN_67) begin // @[L1ICache.scala 153:50]
- history_4_2 <= _history_4_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_4_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_17) begin // @[L1ICache.scala 149:117]
- if (matchSet_5[3]) begin // @[L1ICache.scala 151:28]
- history_4_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_4_3 > _GEN_67) begin // @[L1ICache.scala 153:50]
- history_4_3 <= _history_4_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_5_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_21) begin // @[L1ICache.scala 149:117]
- if (matchSet_6[0]) begin // @[L1ICache.scala 151:28]
- history_5_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_5_0 > _GEN_83) begin // @[L1ICache.scala 153:50]
- history_5_0 <= _history_5_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_5_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_21) begin // @[L1ICache.scala 149:117]
- if (matchSet_6[1]) begin // @[L1ICache.scala 151:28]
- history_5_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_5_1 > _GEN_83) begin // @[L1ICache.scala 153:50]
- history_5_1 <= _history_5_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_5_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_21) begin // @[L1ICache.scala 149:117]
- if (matchSet_6[2]) begin // @[L1ICache.scala 151:28]
- history_5_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_5_2 > _GEN_83) begin // @[L1ICache.scala 153:50]
- history_5_2 <= _history_5_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_5_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_21) begin // @[L1ICache.scala 149:117]
- if (matchSet_6[3]) begin // @[L1ICache.scala 151:28]
- history_5_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_5_3 > _GEN_83) begin // @[L1ICache.scala 153:50]
- history_5_3 <= _history_5_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_6_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_25) begin // @[L1ICache.scala 149:117]
- if (matchSet_7[0]) begin // @[L1ICache.scala 151:28]
- history_6_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_6_0 > _GEN_99) begin // @[L1ICache.scala 153:50]
- history_6_0 <= _history_6_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_6_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_25) begin // @[L1ICache.scala 149:117]
- if (matchSet_7[1]) begin // @[L1ICache.scala 151:28]
- history_6_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_6_1 > _GEN_99) begin // @[L1ICache.scala 153:50]
- history_6_1 <= _history_6_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_6_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_25) begin // @[L1ICache.scala 149:117]
- if (matchSet_7[2]) begin // @[L1ICache.scala 151:28]
- history_6_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_6_2 > _GEN_99) begin // @[L1ICache.scala 153:50]
- history_6_2 <= _history_6_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_6_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_25) begin // @[L1ICache.scala 149:117]
- if (matchSet_7[3]) begin // @[L1ICache.scala 151:28]
- history_6_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_6_3 > _GEN_99) begin // @[L1ICache.scala 153:50]
- history_6_3 <= _history_6_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_7_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_29) begin // @[L1ICache.scala 149:117]
- if (matchSet_8[0]) begin // @[L1ICache.scala 151:28]
- history_7_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_7_0 > _GEN_115) begin // @[L1ICache.scala 153:50]
- history_7_0 <= _history_7_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_7_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_29) begin // @[L1ICache.scala 149:117]
- if (matchSet_8[1]) begin // @[L1ICache.scala 151:28]
- history_7_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_7_1 > _GEN_115) begin // @[L1ICache.scala 153:50]
- history_7_1 <= _history_7_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_7_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_29) begin // @[L1ICache.scala 149:117]
- if (matchSet_8[2]) begin // @[L1ICache.scala 151:28]
- history_7_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_7_2 > _GEN_115) begin // @[L1ICache.scala 153:50]
- history_7_2 <= _history_7_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_7_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_29) begin // @[L1ICache.scala 149:117]
- if (matchSet_8[3]) begin // @[L1ICache.scala 151:28]
- history_7_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_7_3 > _GEN_115) begin // @[L1ICache.scala 153:50]
- history_7_3 <= _history_7_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_8_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_33) begin // @[L1ICache.scala 149:117]
- if (matchSet_9[0]) begin // @[L1ICache.scala 151:28]
- history_8_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_8_0 > _GEN_131) begin // @[L1ICache.scala 153:50]
- history_8_0 <= _history_8_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_8_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_33) begin // @[L1ICache.scala 149:117]
- if (matchSet_9[1]) begin // @[L1ICache.scala 151:28]
- history_8_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_8_1 > _GEN_131) begin // @[L1ICache.scala 153:50]
- history_8_1 <= _history_8_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_8_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_33) begin // @[L1ICache.scala 149:117]
- if (matchSet_9[2]) begin // @[L1ICache.scala 151:28]
- history_8_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_8_2 > _GEN_131) begin // @[L1ICache.scala 153:50]
- history_8_2 <= _history_8_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_8_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_33) begin // @[L1ICache.scala 149:117]
- if (matchSet_9[3]) begin // @[L1ICache.scala 151:28]
- history_8_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_8_3 > _GEN_131) begin // @[L1ICache.scala 153:50]
- history_8_3 <= _history_8_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_9_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_37) begin // @[L1ICache.scala 149:117]
- if (matchSet_10[0]) begin // @[L1ICache.scala 151:28]
- history_9_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_9_0 > _GEN_147) begin // @[L1ICache.scala 153:50]
- history_9_0 <= _history_9_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_9_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_37) begin // @[L1ICache.scala 149:117]
- if (matchSet_10[1]) begin // @[L1ICache.scala 151:28]
- history_9_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_9_1 > _GEN_147) begin // @[L1ICache.scala 153:50]
- history_9_1 <= _history_9_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_9_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_37) begin // @[L1ICache.scala 149:117]
- if (matchSet_10[2]) begin // @[L1ICache.scala 151:28]
- history_9_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_9_2 > _GEN_147) begin // @[L1ICache.scala 153:50]
- history_9_2 <= _history_9_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_9_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_37) begin // @[L1ICache.scala 149:117]
- if (matchSet_10[3]) begin // @[L1ICache.scala 151:28]
- history_9_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_9_3 > _GEN_147) begin // @[L1ICache.scala 153:50]
- history_9_3 <= _history_9_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_10_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_41) begin // @[L1ICache.scala 149:117]
- if (matchSet_11[0]) begin // @[L1ICache.scala 151:28]
- history_10_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_10_0 > _GEN_163) begin // @[L1ICache.scala 153:50]
- history_10_0 <= _history_10_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_10_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_41) begin // @[L1ICache.scala 149:117]
- if (matchSet_11[1]) begin // @[L1ICache.scala 151:28]
- history_10_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_10_1 > _GEN_163) begin // @[L1ICache.scala 153:50]
- history_10_1 <= _history_10_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_10_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_41) begin // @[L1ICache.scala 149:117]
- if (matchSet_11[2]) begin // @[L1ICache.scala 151:28]
- history_10_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_10_2 > _GEN_163) begin // @[L1ICache.scala 153:50]
- history_10_2 <= _history_10_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_10_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_41) begin // @[L1ICache.scala 149:117]
- if (matchSet_11[3]) begin // @[L1ICache.scala 151:28]
- history_10_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_10_3 > _GEN_163) begin // @[L1ICache.scala 153:50]
- history_10_3 <= _history_10_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_11_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_45) begin // @[L1ICache.scala 149:117]
- if (matchSet_12[0]) begin // @[L1ICache.scala 151:28]
- history_11_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_11_0 > _GEN_179) begin // @[L1ICache.scala 153:50]
- history_11_0 <= _history_11_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_11_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_45) begin // @[L1ICache.scala 149:117]
- if (matchSet_12[1]) begin // @[L1ICache.scala 151:28]
- history_11_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_11_1 > _GEN_179) begin // @[L1ICache.scala 153:50]
- history_11_1 <= _history_11_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_11_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_45) begin // @[L1ICache.scala 149:117]
- if (matchSet_12[2]) begin // @[L1ICache.scala 151:28]
- history_11_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_11_2 > _GEN_179) begin // @[L1ICache.scala 153:50]
- history_11_2 <= _history_11_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_11_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_45) begin // @[L1ICache.scala 149:117]
- if (matchSet_12[3]) begin // @[L1ICache.scala 151:28]
- history_11_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_11_3 > _GEN_179) begin // @[L1ICache.scala 153:50]
- history_11_3 <= _history_11_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_12_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_49) begin // @[L1ICache.scala 149:117]
- if (matchSet_13[0]) begin // @[L1ICache.scala 151:28]
- history_12_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_12_0 > _GEN_195) begin // @[L1ICache.scala 153:50]
- history_12_0 <= _history_12_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_12_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_49) begin // @[L1ICache.scala 149:117]
- if (matchSet_13[1]) begin // @[L1ICache.scala 151:28]
- history_12_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_12_1 > _GEN_195) begin // @[L1ICache.scala 153:50]
- history_12_1 <= _history_12_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_12_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_49) begin // @[L1ICache.scala 149:117]
- if (matchSet_13[2]) begin // @[L1ICache.scala 151:28]
- history_12_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_12_2 > _GEN_195) begin // @[L1ICache.scala 153:50]
- history_12_2 <= _history_12_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_12_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_49) begin // @[L1ICache.scala 149:117]
- if (matchSet_13[3]) begin // @[L1ICache.scala 151:28]
- history_12_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_12_3 > _GEN_195) begin // @[L1ICache.scala 153:50]
- history_12_3 <= _history_12_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_13_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_53) begin // @[L1ICache.scala 149:117]
- if (matchSet_14[0]) begin // @[L1ICache.scala 151:28]
- history_13_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_13_0 > _GEN_211) begin // @[L1ICache.scala 153:50]
- history_13_0 <= _history_13_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_13_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_53) begin // @[L1ICache.scala 149:117]
- if (matchSet_14[1]) begin // @[L1ICache.scala 151:28]
- history_13_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_13_1 > _GEN_211) begin // @[L1ICache.scala 153:50]
- history_13_1 <= _history_13_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_13_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_53) begin // @[L1ICache.scala 149:117]
- if (matchSet_14[2]) begin // @[L1ICache.scala 151:28]
- history_13_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_13_2 > _GEN_211) begin // @[L1ICache.scala 153:50]
- history_13_2 <= _history_13_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_13_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_53) begin // @[L1ICache.scala 149:117]
- if (matchSet_14[3]) begin // @[L1ICache.scala 151:28]
- history_13_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_13_3 > _GEN_211) begin // @[L1ICache.scala 153:50]
- history_13_3 <= _history_13_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_14_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_57) begin // @[L1ICache.scala 149:117]
- if (matchSet_15[0]) begin // @[L1ICache.scala 151:28]
- history_14_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_14_0 > _GEN_227) begin // @[L1ICache.scala 153:50]
- history_14_0 <= _history_14_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_14_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_57) begin // @[L1ICache.scala 149:117]
- if (matchSet_15[1]) begin // @[L1ICache.scala 151:28]
- history_14_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_14_1 > _GEN_227) begin // @[L1ICache.scala 153:50]
- history_14_1 <= _history_14_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_14_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_57) begin // @[L1ICache.scala 149:117]
- if (matchSet_15[2]) begin // @[L1ICache.scala 151:28]
- history_14_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_14_2 > _GEN_227) begin // @[L1ICache.scala 153:50]
- history_14_2 <= _history_14_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_14_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_57) begin // @[L1ICache.scala 149:117]
- if (matchSet_15[3]) begin // @[L1ICache.scala 151:28]
- history_14_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_14_3 > _GEN_227) begin // @[L1ICache.scala 153:50]
- history_14_3 <= _history_14_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_15_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_61) begin // @[L1ICache.scala 149:117]
- if (matchSet_16[0]) begin // @[L1ICache.scala 151:28]
- history_15_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_15_0 > _GEN_243) begin // @[L1ICache.scala 153:50]
- history_15_0 <= _history_15_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_15_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_61) begin // @[L1ICache.scala 149:117]
- if (matchSet_16[1]) begin // @[L1ICache.scala 151:28]
- history_15_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_15_1 > _GEN_243) begin // @[L1ICache.scala 153:50]
- history_15_1 <= _history_15_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_15_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_61) begin // @[L1ICache.scala 149:117]
- if (matchSet_16[2]) begin // @[L1ICache.scala 151:28]
- history_15_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_15_2 > _GEN_243) begin // @[L1ICache.scala 153:50]
- history_15_2 <= _history_15_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_15_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_61) begin // @[L1ICache.scala 149:117]
- if (matchSet_16[3]) begin // @[L1ICache.scala 151:28]
- history_15_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_15_3 > _GEN_243) begin // @[L1ICache.scala 153:50]
- history_15_3 <= _history_15_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_16_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_65) begin // @[L1ICache.scala 149:117]
- if (matchSet_17[0]) begin // @[L1ICache.scala 151:28]
- history_16_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_16_0 > _GEN_259) begin // @[L1ICache.scala 153:50]
- history_16_0 <= _history_16_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_16_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_65) begin // @[L1ICache.scala 149:117]
- if (matchSet_17[1]) begin // @[L1ICache.scala 151:28]
- history_16_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_16_1 > _GEN_259) begin // @[L1ICache.scala 153:50]
- history_16_1 <= _history_16_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_16_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_65) begin // @[L1ICache.scala 149:117]
- if (matchSet_17[2]) begin // @[L1ICache.scala 151:28]
- history_16_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_16_2 > _GEN_259) begin // @[L1ICache.scala 153:50]
- history_16_2 <= _history_16_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_16_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_65) begin // @[L1ICache.scala 149:117]
- if (matchSet_17[3]) begin // @[L1ICache.scala 151:28]
- history_16_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_16_3 > _GEN_259) begin // @[L1ICache.scala 153:50]
- history_16_3 <= _history_16_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_17_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_69) begin // @[L1ICache.scala 149:117]
- if (matchSet_18[0]) begin // @[L1ICache.scala 151:28]
- history_17_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_17_0 > _GEN_275) begin // @[L1ICache.scala 153:50]
- history_17_0 <= _history_17_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_17_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_69) begin // @[L1ICache.scala 149:117]
- if (matchSet_18[1]) begin // @[L1ICache.scala 151:28]
- history_17_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_17_1 > _GEN_275) begin // @[L1ICache.scala 153:50]
- history_17_1 <= _history_17_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_17_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_69) begin // @[L1ICache.scala 149:117]
- if (matchSet_18[2]) begin // @[L1ICache.scala 151:28]
- history_17_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_17_2 > _GEN_275) begin // @[L1ICache.scala 153:50]
- history_17_2 <= _history_17_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_17_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_69) begin // @[L1ICache.scala 149:117]
- if (matchSet_18[3]) begin // @[L1ICache.scala 151:28]
- history_17_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_17_3 > _GEN_275) begin // @[L1ICache.scala 153:50]
- history_17_3 <= _history_17_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_18_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_73) begin // @[L1ICache.scala 149:117]
- if (matchSet_19[0]) begin // @[L1ICache.scala 151:28]
- history_18_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_18_0 > _GEN_291) begin // @[L1ICache.scala 153:50]
- history_18_0 <= _history_18_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_18_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_73) begin // @[L1ICache.scala 149:117]
- if (matchSet_19[1]) begin // @[L1ICache.scala 151:28]
- history_18_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_18_1 > _GEN_291) begin // @[L1ICache.scala 153:50]
- history_18_1 <= _history_18_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_18_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_73) begin // @[L1ICache.scala 149:117]
- if (matchSet_19[2]) begin // @[L1ICache.scala 151:28]
- history_18_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_18_2 > _GEN_291) begin // @[L1ICache.scala 153:50]
- history_18_2 <= _history_18_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_18_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_73) begin // @[L1ICache.scala 149:117]
- if (matchSet_19[3]) begin // @[L1ICache.scala 151:28]
- history_18_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_18_3 > _GEN_291) begin // @[L1ICache.scala 153:50]
- history_18_3 <= _history_18_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_19_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_77) begin // @[L1ICache.scala 149:117]
- if (matchSet_20[0]) begin // @[L1ICache.scala 151:28]
- history_19_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_19_0 > _GEN_307) begin // @[L1ICache.scala 153:50]
- history_19_0 <= _history_19_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_19_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_77) begin // @[L1ICache.scala 149:117]
- if (matchSet_20[1]) begin // @[L1ICache.scala 151:28]
- history_19_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_19_1 > _GEN_307) begin // @[L1ICache.scala 153:50]
- history_19_1 <= _history_19_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_19_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_77) begin // @[L1ICache.scala 149:117]
- if (matchSet_20[2]) begin // @[L1ICache.scala 151:28]
- history_19_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_19_2 > _GEN_307) begin // @[L1ICache.scala 153:50]
- history_19_2 <= _history_19_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_19_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_77) begin // @[L1ICache.scala 149:117]
- if (matchSet_20[3]) begin // @[L1ICache.scala 151:28]
- history_19_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_19_3 > _GEN_307) begin // @[L1ICache.scala 153:50]
- history_19_3 <= _history_19_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_20_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_81) begin // @[L1ICache.scala 149:117]
- if (matchSet_21[0]) begin // @[L1ICache.scala 151:28]
- history_20_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_20_0 > _GEN_323) begin // @[L1ICache.scala 153:50]
- history_20_0 <= _history_20_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_20_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_81) begin // @[L1ICache.scala 149:117]
- if (matchSet_21[1]) begin // @[L1ICache.scala 151:28]
- history_20_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_20_1 > _GEN_323) begin // @[L1ICache.scala 153:50]
- history_20_1 <= _history_20_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_20_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_81) begin // @[L1ICache.scala 149:117]
- if (matchSet_21[2]) begin // @[L1ICache.scala 151:28]
- history_20_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_20_2 > _GEN_323) begin // @[L1ICache.scala 153:50]
- history_20_2 <= _history_20_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_20_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_81) begin // @[L1ICache.scala 149:117]
- if (matchSet_21[3]) begin // @[L1ICache.scala 151:28]
- history_20_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_20_3 > _GEN_323) begin // @[L1ICache.scala 153:50]
- history_20_3 <= _history_20_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_21_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_85) begin // @[L1ICache.scala 149:117]
- if (matchSet_22[0]) begin // @[L1ICache.scala 151:28]
- history_21_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_21_0 > _GEN_339) begin // @[L1ICache.scala 153:50]
- history_21_0 <= _history_21_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_21_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_85) begin // @[L1ICache.scala 149:117]
- if (matchSet_22[1]) begin // @[L1ICache.scala 151:28]
- history_21_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_21_1 > _GEN_339) begin // @[L1ICache.scala 153:50]
- history_21_1 <= _history_21_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_21_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_85) begin // @[L1ICache.scala 149:117]
- if (matchSet_22[2]) begin // @[L1ICache.scala 151:28]
- history_21_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_21_2 > _GEN_339) begin // @[L1ICache.scala 153:50]
- history_21_2 <= _history_21_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_21_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_85) begin // @[L1ICache.scala 149:117]
- if (matchSet_22[3]) begin // @[L1ICache.scala 151:28]
- history_21_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_21_3 > _GEN_339) begin // @[L1ICache.scala 153:50]
- history_21_3 <= _history_21_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_22_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_89) begin // @[L1ICache.scala 149:117]
- if (matchSet_23[0]) begin // @[L1ICache.scala 151:28]
- history_22_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_22_0 > _GEN_355) begin // @[L1ICache.scala 153:50]
- history_22_0 <= _history_22_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_22_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_89) begin // @[L1ICache.scala 149:117]
- if (matchSet_23[1]) begin // @[L1ICache.scala 151:28]
- history_22_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_22_1 > _GEN_355) begin // @[L1ICache.scala 153:50]
- history_22_1 <= _history_22_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_22_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_89) begin // @[L1ICache.scala 149:117]
- if (matchSet_23[2]) begin // @[L1ICache.scala 151:28]
- history_22_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_22_2 > _GEN_355) begin // @[L1ICache.scala 153:50]
- history_22_2 <= _history_22_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_22_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_89) begin // @[L1ICache.scala 149:117]
- if (matchSet_23[3]) begin // @[L1ICache.scala 151:28]
- history_22_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_22_3 > _GEN_355) begin // @[L1ICache.scala 153:50]
- history_22_3 <= _history_22_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_23_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_93) begin // @[L1ICache.scala 149:117]
- if (matchSet_24[0]) begin // @[L1ICache.scala 151:28]
- history_23_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_23_0 > _GEN_371) begin // @[L1ICache.scala 153:50]
- history_23_0 <= _history_23_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_23_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_93) begin // @[L1ICache.scala 149:117]
- if (matchSet_24[1]) begin // @[L1ICache.scala 151:28]
- history_23_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_23_1 > _GEN_371) begin // @[L1ICache.scala 153:50]
- history_23_1 <= _history_23_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_23_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_93) begin // @[L1ICache.scala 149:117]
- if (matchSet_24[2]) begin // @[L1ICache.scala 151:28]
- history_23_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_23_2 > _GEN_371) begin // @[L1ICache.scala 153:50]
- history_23_2 <= _history_23_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_23_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_93) begin // @[L1ICache.scala 149:117]
- if (matchSet_24[3]) begin // @[L1ICache.scala 151:28]
- history_23_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_23_3 > _GEN_371) begin // @[L1ICache.scala 153:50]
- history_23_3 <= _history_23_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_24_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_97) begin // @[L1ICache.scala 149:117]
- if (matchSet_25[0]) begin // @[L1ICache.scala 151:28]
- history_24_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_24_0 > _GEN_387) begin // @[L1ICache.scala 153:50]
- history_24_0 <= _history_24_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_24_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_97) begin // @[L1ICache.scala 149:117]
- if (matchSet_25[1]) begin // @[L1ICache.scala 151:28]
- history_24_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_24_1 > _GEN_387) begin // @[L1ICache.scala 153:50]
- history_24_1 <= _history_24_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_24_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_97) begin // @[L1ICache.scala 149:117]
- if (matchSet_25[2]) begin // @[L1ICache.scala 151:28]
- history_24_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_24_2 > _GEN_387) begin // @[L1ICache.scala 153:50]
- history_24_2 <= _history_24_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_24_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_97) begin // @[L1ICache.scala 149:117]
- if (matchSet_25[3]) begin // @[L1ICache.scala 151:28]
- history_24_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_24_3 > _GEN_387) begin // @[L1ICache.scala 153:50]
- history_24_3 <= _history_24_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_25_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_101) begin // @[L1ICache.scala 149:117]
- if (matchSet_26[0]) begin // @[L1ICache.scala 151:28]
- history_25_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_25_0 > _GEN_403) begin // @[L1ICache.scala 153:50]
- history_25_0 <= _history_25_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_25_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_101) begin // @[L1ICache.scala 149:117]
- if (matchSet_26[1]) begin // @[L1ICache.scala 151:28]
- history_25_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_25_1 > _GEN_403) begin // @[L1ICache.scala 153:50]
- history_25_1 <= _history_25_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_25_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_101) begin // @[L1ICache.scala 149:117]
- if (matchSet_26[2]) begin // @[L1ICache.scala 151:28]
- history_25_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_25_2 > _GEN_403) begin // @[L1ICache.scala 153:50]
- history_25_2 <= _history_25_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_25_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_101) begin // @[L1ICache.scala 149:117]
- if (matchSet_26[3]) begin // @[L1ICache.scala 151:28]
- history_25_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_25_3 > _GEN_403) begin // @[L1ICache.scala 153:50]
- history_25_3 <= _history_25_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_26_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_105) begin // @[L1ICache.scala 149:117]
- if (matchSet_27[0]) begin // @[L1ICache.scala 151:28]
- history_26_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_26_0 > _GEN_419) begin // @[L1ICache.scala 153:50]
- history_26_0 <= _history_26_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_26_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_105) begin // @[L1ICache.scala 149:117]
- if (matchSet_27[1]) begin // @[L1ICache.scala 151:28]
- history_26_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_26_1 > _GEN_419) begin // @[L1ICache.scala 153:50]
- history_26_1 <= _history_26_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_26_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_105) begin // @[L1ICache.scala 149:117]
- if (matchSet_27[2]) begin // @[L1ICache.scala 151:28]
- history_26_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_26_2 > _GEN_419) begin // @[L1ICache.scala 153:50]
- history_26_2 <= _history_26_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_26_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_105) begin // @[L1ICache.scala 149:117]
- if (matchSet_27[3]) begin // @[L1ICache.scala 151:28]
- history_26_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_26_3 > _GEN_419) begin // @[L1ICache.scala 153:50]
- history_26_3 <= _history_26_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_27_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_109) begin // @[L1ICache.scala 149:117]
- if (matchSet_28[0]) begin // @[L1ICache.scala 151:28]
- history_27_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_27_0 > _GEN_435) begin // @[L1ICache.scala 153:50]
- history_27_0 <= _history_27_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_27_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_109) begin // @[L1ICache.scala 149:117]
- if (matchSet_28[1]) begin // @[L1ICache.scala 151:28]
- history_27_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_27_1 > _GEN_435) begin // @[L1ICache.scala 153:50]
- history_27_1 <= _history_27_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_27_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_109) begin // @[L1ICache.scala 149:117]
- if (matchSet_28[2]) begin // @[L1ICache.scala 151:28]
- history_27_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_27_2 > _GEN_435) begin // @[L1ICache.scala 153:50]
- history_27_2 <= _history_27_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_27_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_109) begin // @[L1ICache.scala 149:117]
- if (matchSet_28[3]) begin // @[L1ICache.scala 151:28]
- history_27_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_27_3 > _GEN_435) begin // @[L1ICache.scala 153:50]
- history_27_3 <= _history_27_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_28_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_113) begin // @[L1ICache.scala 149:117]
- if (matchSet_29[0]) begin // @[L1ICache.scala 151:28]
- history_28_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_28_0 > _GEN_451) begin // @[L1ICache.scala 153:50]
- history_28_0 <= _history_28_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_28_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_113) begin // @[L1ICache.scala 149:117]
- if (matchSet_29[1]) begin // @[L1ICache.scala 151:28]
- history_28_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_28_1 > _GEN_451) begin // @[L1ICache.scala 153:50]
- history_28_1 <= _history_28_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_28_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_113) begin // @[L1ICache.scala 149:117]
- if (matchSet_29[2]) begin // @[L1ICache.scala 151:28]
- history_28_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_28_2 > _GEN_451) begin // @[L1ICache.scala 153:50]
- history_28_2 <= _history_28_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_28_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_113) begin // @[L1ICache.scala 149:117]
- if (matchSet_29[3]) begin // @[L1ICache.scala 151:28]
- history_28_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_28_3 > _GEN_451) begin // @[L1ICache.scala 153:50]
- history_28_3 <= _history_28_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_29_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_117) begin // @[L1ICache.scala 149:117]
- if (matchSet_30[0]) begin // @[L1ICache.scala 151:28]
- history_29_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_29_0 > _GEN_467) begin // @[L1ICache.scala 153:50]
- history_29_0 <= _history_29_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_29_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_117) begin // @[L1ICache.scala 149:117]
- if (matchSet_30[1]) begin // @[L1ICache.scala 151:28]
- history_29_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_29_1 > _GEN_467) begin // @[L1ICache.scala 153:50]
- history_29_1 <= _history_29_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_29_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_117) begin // @[L1ICache.scala 149:117]
- if (matchSet_30[2]) begin // @[L1ICache.scala 151:28]
- history_29_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_29_2 > _GEN_467) begin // @[L1ICache.scala 153:50]
- history_29_2 <= _history_29_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_29_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_117) begin // @[L1ICache.scala 149:117]
- if (matchSet_30[3]) begin // @[L1ICache.scala 151:28]
- history_29_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_29_3 > _GEN_467) begin // @[L1ICache.scala 153:50]
- history_29_3 <= _history_29_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_30_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_121) begin // @[L1ICache.scala 149:117]
- if (matchSet_31[0]) begin // @[L1ICache.scala 151:28]
- history_30_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_30_0 > _GEN_483) begin // @[L1ICache.scala 153:50]
- history_30_0 <= _history_30_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_30_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_121) begin // @[L1ICache.scala 149:117]
- if (matchSet_31[1]) begin // @[L1ICache.scala 151:28]
- history_30_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_30_1 > _GEN_483) begin // @[L1ICache.scala 153:50]
- history_30_1 <= _history_30_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_30_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_121) begin // @[L1ICache.scala 149:117]
- if (matchSet_31[2]) begin // @[L1ICache.scala 151:28]
- history_30_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_30_2 > _GEN_483) begin // @[L1ICache.scala 153:50]
- history_30_2 <= _history_30_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_30_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_121) begin // @[L1ICache.scala 149:117]
- if (matchSet_31[3]) begin // @[L1ICache.scala 151:28]
- history_30_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_30_3 > _GEN_483) begin // @[L1ICache.scala 153:50]
- history_30_3 <= _history_30_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_31_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_125) begin // @[L1ICache.scala 149:117]
- if (matchSet_32[0]) begin // @[L1ICache.scala 151:28]
- history_31_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_31_0 > _GEN_499) begin // @[L1ICache.scala 153:50]
- history_31_0 <= _history_31_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_31_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_125) begin // @[L1ICache.scala 149:117]
- if (matchSet_32[1]) begin // @[L1ICache.scala 151:28]
- history_31_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_31_1 > _GEN_499) begin // @[L1ICache.scala 153:50]
- history_31_1 <= _history_31_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_31_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_125) begin // @[L1ICache.scala 149:117]
- if (matchSet_32[2]) begin // @[L1ICache.scala 151:28]
- history_31_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_31_2 > _GEN_499) begin // @[L1ICache.scala 153:50]
- history_31_2 <= _history_31_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_31_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_125) begin // @[L1ICache.scala 149:117]
- if (matchSet_32[3]) begin // @[L1ICache.scala 151:28]
- history_31_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_31_3 > _GEN_499) begin // @[L1ICache.scala 153:50]
- history_31_3 <= _history_31_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_32_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_129) begin // @[L1ICache.scala 149:117]
- if (matchSet_33[0]) begin // @[L1ICache.scala 151:28]
- history_32_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_32_0 > _GEN_515) begin // @[L1ICache.scala 153:50]
- history_32_0 <= _history_32_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_32_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_129) begin // @[L1ICache.scala 149:117]
- if (matchSet_33[1]) begin // @[L1ICache.scala 151:28]
- history_32_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_32_1 > _GEN_515) begin // @[L1ICache.scala 153:50]
- history_32_1 <= _history_32_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_32_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_129) begin // @[L1ICache.scala 149:117]
- if (matchSet_33[2]) begin // @[L1ICache.scala 151:28]
- history_32_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_32_2 > _GEN_515) begin // @[L1ICache.scala 153:50]
- history_32_2 <= _history_32_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_32_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_129) begin // @[L1ICache.scala 149:117]
- if (matchSet_33[3]) begin // @[L1ICache.scala 151:28]
- history_32_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_32_3 > _GEN_515) begin // @[L1ICache.scala 153:50]
- history_32_3 <= _history_32_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_33_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_133) begin // @[L1ICache.scala 149:117]
- if (matchSet_34[0]) begin // @[L1ICache.scala 151:28]
- history_33_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_33_0 > _GEN_531) begin // @[L1ICache.scala 153:50]
- history_33_0 <= _history_33_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_33_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_133) begin // @[L1ICache.scala 149:117]
- if (matchSet_34[1]) begin // @[L1ICache.scala 151:28]
- history_33_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_33_1 > _GEN_531) begin // @[L1ICache.scala 153:50]
- history_33_1 <= _history_33_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_33_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_133) begin // @[L1ICache.scala 149:117]
- if (matchSet_34[2]) begin // @[L1ICache.scala 151:28]
- history_33_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_33_2 > _GEN_531) begin // @[L1ICache.scala 153:50]
- history_33_2 <= _history_33_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_33_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_133) begin // @[L1ICache.scala 149:117]
- if (matchSet_34[3]) begin // @[L1ICache.scala 151:28]
- history_33_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_33_3 > _GEN_531) begin // @[L1ICache.scala 153:50]
- history_33_3 <= _history_33_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_34_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_137) begin // @[L1ICache.scala 149:117]
- if (matchSet_35[0]) begin // @[L1ICache.scala 151:28]
- history_34_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_34_0 > _GEN_547) begin // @[L1ICache.scala 153:50]
- history_34_0 <= _history_34_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_34_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_137) begin // @[L1ICache.scala 149:117]
- if (matchSet_35[1]) begin // @[L1ICache.scala 151:28]
- history_34_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_34_1 > _GEN_547) begin // @[L1ICache.scala 153:50]
- history_34_1 <= _history_34_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_34_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_137) begin // @[L1ICache.scala 149:117]
- if (matchSet_35[2]) begin // @[L1ICache.scala 151:28]
- history_34_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_34_2 > _GEN_547) begin // @[L1ICache.scala 153:50]
- history_34_2 <= _history_34_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_34_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_137) begin // @[L1ICache.scala 149:117]
- if (matchSet_35[3]) begin // @[L1ICache.scala 151:28]
- history_34_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_34_3 > _GEN_547) begin // @[L1ICache.scala 153:50]
- history_34_3 <= _history_34_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_35_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_141) begin // @[L1ICache.scala 149:117]
- if (matchSet_36[0]) begin // @[L1ICache.scala 151:28]
- history_35_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_35_0 > _GEN_563) begin // @[L1ICache.scala 153:50]
- history_35_0 <= _history_35_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_35_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_141) begin // @[L1ICache.scala 149:117]
- if (matchSet_36[1]) begin // @[L1ICache.scala 151:28]
- history_35_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_35_1 > _GEN_563) begin // @[L1ICache.scala 153:50]
- history_35_1 <= _history_35_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_35_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_141) begin // @[L1ICache.scala 149:117]
- if (matchSet_36[2]) begin // @[L1ICache.scala 151:28]
- history_35_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_35_2 > _GEN_563) begin // @[L1ICache.scala 153:50]
- history_35_2 <= _history_35_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_35_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_141) begin // @[L1ICache.scala 149:117]
- if (matchSet_36[3]) begin // @[L1ICache.scala 151:28]
- history_35_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_35_3 > _GEN_563) begin // @[L1ICache.scala 153:50]
- history_35_3 <= _history_35_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_36_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_145) begin // @[L1ICache.scala 149:117]
- if (matchSet_37[0]) begin // @[L1ICache.scala 151:28]
- history_36_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_36_0 > _GEN_579) begin // @[L1ICache.scala 153:50]
- history_36_0 <= _history_36_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_36_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_145) begin // @[L1ICache.scala 149:117]
- if (matchSet_37[1]) begin // @[L1ICache.scala 151:28]
- history_36_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_36_1 > _GEN_579) begin // @[L1ICache.scala 153:50]
- history_36_1 <= _history_36_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_36_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_145) begin // @[L1ICache.scala 149:117]
- if (matchSet_37[2]) begin // @[L1ICache.scala 151:28]
- history_36_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_36_2 > _GEN_579) begin // @[L1ICache.scala 153:50]
- history_36_2 <= _history_36_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_36_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_145) begin // @[L1ICache.scala 149:117]
- if (matchSet_37[3]) begin // @[L1ICache.scala 151:28]
- history_36_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_36_3 > _GEN_579) begin // @[L1ICache.scala 153:50]
- history_36_3 <= _history_36_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_37_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_149) begin // @[L1ICache.scala 149:117]
- if (matchSet_38[0]) begin // @[L1ICache.scala 151:28]
- history_37_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_37_0 > _GEN_595) begin // @[L1ICache.scala 153:50]
- history_37_0 <= _history_37_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_37_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_149) begin // @[L1ICache.scala 149:117]
- if (matchSet_38[1]) begin // @[L1ICache.scala 151:28]
- history_37_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_37_1 > _GEN_595) begin // @[L1ICache.scala 153:50]
- history_37_1 <= _history_37_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_37_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_149) begin // @[L1ICache.scala 149:117]
- if (matchSet_38[2]) begin // @[L1ICache.scala 151:28]
- history_37_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_37_2 > _GEN_595) begin // @[L1ICache.scala 153:50]
- history_37_2 <= _history_37_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_37_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_149) begin // @[L1ICache.scala 149:117]
- if (matchSet_38[3]) begin // @[L1ICache.scala 151:28]
- history_37_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_37_3 > _GEN_595) begin // @[L1ICache.scala 153:50]
- history_37_3 <= _history_37_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_38_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_153) begin // @[L1ICache.scala 149:117]
- if (matchSet_39[0]) begin // @[L1ICache.scala 151:28]
- history_38_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_38_0 > _GEN_611) begin // @[L1ICache.scala 153:50]
- history_38_0 <= _history_38_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_38_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_153) begin // @[L1ICache.scala 149:117]
- if (matchSet_39[1]) begin // @[L1ICache.scala 151:28]
- history_38_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_38_1 > _GEN_611) begin // @[L1ICache.scala 153:50]
- history_38_1 <= _history_38_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_38_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_153) begin // @[L1ICache.scala 149:117]
- if (matchSet_39[2]) begin // @[L1ICache.scala 151:28]
- history_38_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_38_2 > _GEN_611) begin // @[L1ICache.scala 153:50]
- history_38_2 <= _history_38_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_38_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_153) begin // @[L1ICache.scala 149:117]
- if (matchSet_39[3]) begin // @[L1ICache.scala 151:28]
- history_38_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_38_3 > _GEN_611) begin // @[L1ICache.scala 153:50]
- history_38_3 <= _history_38_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_39_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_157) begin // @[L1ICache.scala 149:117]
- if (matchSet_40[0]) begin // @[L1ICache.scala 151:28]
- history_39_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_39_0 > _GEN_627) begin // @[L1ICache.scala 153:50]
- history_39_0 <= _history_39_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_39_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_157) begin // @[L1ICache.scala 149:117]
- if (matchSet_40[1]) begin // @[L1ICache.scala 151:28]
- history_39_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_39_1 > _GEN_627) begin // @[L1ICache.scala 153:50]
- history_39_1 <= _history_39_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_39_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_157) begin // @[L1ICache.scala 149:117]
- if (matchSet_40[2]) begin // @[L1ICache.scala 151:28]
- history_39_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_39_2 > _GEN_627) begin // @[L1ICache.scala 153:50]
- history_39_2 <= _history_39_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_39_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_157) begin // @[L1ICache.scala 149:117]
- if (matchSet_40[3]) begin // @[L1ICache.scala 151:28]
- history_39_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_39_3 > _GEN_627) begin // @[L1ICache.scala 153:50]
- history_39_3 <= _history_39_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_40_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_161) begin // @[L1ICache.scala 149:117]
- if (matchSet_41[0]) begin // @[L1ICache.scala 151:28]
- history_40_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_40_0 > _GEN_643) begin // @[L1ICache.scala 153:50]
- history_40_0 <= _history_40_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_40_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_161) begin // @[L1ICache.scala 149:117]
- if (matchSet_41[1]) begin // @[L1ICache.scala 151:28]
- history_40_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_40_1 > _GEN_643) begin // @[L1ICache.scala 153:50]
- history_40_1 <= _history_40_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_40_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_161) begin // @[L1ICache.scala 149:117]
- if (matchSet_41[2]) begin // @[L1ICache.scala 151:28]
- history_40_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_40_2 > _GEN_643) begin // @[L1ICache.scala 153:50]
- history_40_2 <= _history_40_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_40_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_161) begin // @[L1ICache.scala 149:117]
- if (matchSet_41[3]) begin // @[L1ICache.scala 151:28]
- history_40_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_40_3 > _GEN_643) begin // @[L1ICache.scala 153:50]
- history_40_3 <= _history_40_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_41_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_165) begin // @[L1ICache.scala 149:117]
- if (matchSet_42[0]) begin // @[L1ICache.scala 151:28]
- history_41_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_41_0 > _GEN_659) begin // @[L1ICache.scala 153:50]
- history_41_0 <= _history_41_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_41_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_165) begin // @[L1ICache.scala 149:117]
- if (matchSet_42[1]) begin // @[L1ICache.scala 151:28]
- history_41_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_41_1 > _GEN_659) begin // @[L1ICache.scala 153:50]
- history_41_1 <= _history_41_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_41_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_165) begin // @[L1ICache.scala 149:117]
- if (matchSet_42[2]) begin // @[L1ICache.scala 151:28]
- history_41_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_41_2 > _GEN_659) begin // @[L1ICache.scala 153:50]
- history_41_2 <= _history_41_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_41_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_165) begin // @[L1ICache.scala 149:117]
- if (matchSet_42[3]) begin // @[L1ICache.scala 151:28]
- history_41_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_41_3 > _GEN_659) begin // @[L1ICache.scala 153:50]
- history_41_3 <= _history_41_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_42_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_169) begin // @[L1ICache.scala 149:117]
- if (matchSet_43[0]) begin // @[L1ICache.scala 151:28]
- history_42_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_42_0 > _GEN_675) begin // @[L1ICache.scala 153:50]
- history_42_0 <= _history_42_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_42_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_169) begin // @[L1ICache.scala 149:117]
- if (matchSet_43[1]) begin // @[L1ICache.scala 151:28]
- history_42_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_42_1 > _GEN_675) begin // @[L1ICache.scala 153:50]
- history_42_1 <= _history_42_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_42_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_169) begin // @[L1ICache.scala 149:117]
- if (matchSet_43[2]) begin // @[L1ICache.scala 151:28]
- history_42_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_42_2 > _GEN_675) begin // @[L1ICache.scala 153:50]
- history_42_2 <= _history_42_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_42_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_169) begin // @[L1ICache.scala 149:117]
- if (matchSet_43[3]) begin // @[L1ICache.scala 151:28]
- history_42_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_42_3 > _GEN_675) begin // @[L1ICache.scala 153:50]
- history_42_3 <= _history_42_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_43_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_173) begin // @[L1ICache.scala 149:117]
- if (matchSet_44[0]) begin // @[L1ICache.scala 151:28]
- history_43_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_43_0 > _GEN_691) begin // @[L1ICache.scala 153:50]
- history_43_0 <= _history_43_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_43_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_173) begin // @[L1ICache.scala 149:117]
- if (matchSet_44[1]) begin // @[L1ICache.scala 151:28]
- history_43_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_43_1 > _GEN_691) begin // @[L1ICache.scala 153:50]
- history_43_1 <= _history_43_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_43_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_173) begin // @[L1ICache.scala 149:117]
- if (matchSet_44[2]) begin // @[L1ICache.scala 151:28]
- history_43_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_43_2 > _GEN_691) begin // @[L1ICache.scala 153:50]
- history_43_2 <= _history_43_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_43_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_173) begin // @[L1ICache.scala 149:117]
- if (matchSet_44[3]) begin // @[L1ICache.scala 151:28]
- history_43_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_43_3 > _GEN_691) begin // @[L1ICache.scala 153:50]
- history_43_3 <= _history_43_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_44_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_177) begin // @[L1ICache.scala 149:117]
- if (matchSet_45[0]) begin // @[L1ICache.scala 151:28]
- history_44_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_44_0 > _GEN_707) begin // @[L1ICache.scala 153:50]
- history_44_0 <= _history_44_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_44_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_177) begin // @[L1ICache.scala 149:117]
- if (matchSet_45[1]) begin // @[L1ICache.scala 151:28]
- history_44_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_44_1 > _GEN_707) begin // @[L1ICache.scala 153:50]
- history_44_1 <= _history_44_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_44_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_177) begin // @[L1ICache.scala 149:117]
- if (matchSet_45[2]) begin // @[L1ICache.scala 151:28]
- history_44_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_44_2 > _GEN_707) begin // @[L1ICache.scala 153:50]
- history_44_2 <= _history_44_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_44_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_177) begin // @[L1ICache.scala 149:117]
- if (matchSet_45[3]) begin // @[L1ICache.scala 151:28]
- history_44_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_44_3 > _GEN_707) begin // @[L1ICache.scala 153:50]
- history_44_3 <= _history_44_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_45_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_181) begin // @[L1ICache.scala 149:117]
- if (matchSet_46[0]) begin // @[L1ICache.scala 151:28]
- history_45_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_45_0 > _GEN_723) begin // @[L1ICache.scala 153:50]
- history_45_0 <= _history_45_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_45_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_181) begin // @[L1ICache.scala 149:117]
- if (matchSet_46[1]) begin // @[L1ICache.scala 151:28]
- history_45_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_45_1 > _GEN_723) begin // @[L1ICache.scala 153:50]
- history_45_1 <= _history_45_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_45_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_181) begin // @[L1ICache.scala 149:117]
- if (matchSet_46[2]) begin // @[L1ICache.scala 151:28]
- history_45_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_45_2 > _GEN_723) begin // @[L1ICache.scala 153:50]
- history_45_2 <= _history_45_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_45_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_181) begin // @[L1ICache.scala 149:117]
- if (matchSet_46[3]) begin // @[L1ICache.scala 151:28]
- history_45_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_45_3 > _GEN_723) begin // @[L1ICache.scala 153:50]
- history_45_3 <= _history_45_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_46_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_185) begin // @[L1ICache.scala 149:117]
- if (matchSet_47[0]) begin // @[L1ICache.scala 151:28]
- history_46_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_46_0 > _GEN_739) begin // @[L1ICache.scala 153:50]
- history_46_0 <= _history_46_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_46_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_185) begin // @[L1ICache.scala 149:117]
- if (matchSet_47[1]) begin // @[L1ICache.scala 151:28]
- history_46_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_46_1 > _GEN_739) begin // @[L1ICache.scala 153:50]
- history_46_1 <= _history_46_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_46_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_185) begin // @[L1ICache.scala 149:117]
- if (matchSet_47[2]) begin // @[L1ICache.scala 151:28]
- history_46_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_46_2 > _GEN_739) begin // @[L1ICache.scala 153:50]
- history_46_2 <= _history_46_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_46_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_185) begin // @[L1ICache.scala 149:117]
- if (matchSet_47[3]) begin // @[L1ICache.scala 151:28]
- history_46_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_46_3 > _GEN_739) begin // @[L1ICache.scala 153:50]
- history_46_3 <= _history_46_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_47_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_189) begin // @[L1ICache.scala 149:117]
- if (matchSet_48[0]) begin // @[L1ICache.scala 151:28]
- history_47_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_47_0 > _GEN_755) begin // @[L1ICache.scala 153:50]
- history_47_0 <= _history_47_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_47_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_189) begin // @[L1ICache.scala 149:117]
- if (matchSet_48[1]) begin // @[L1ICache.scala 151:28]
- history_47_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_47_1 > _GEN_755) begin // @[L1ICache.scala 153:50]
- history_47_1 <= _history_47_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_47_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_189) begin // @[L1ICache.scala 149:117]
- if (matchSet_48[2]) begin // @[L1ICache.scala 151:28]
- history_47_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_47_2 > _GEN_755) begin // @[L1ICache.scala 153:50]
- history_47_2 <= _history_47_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_47_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_189) begin // @[L1ICache.scala 149:117]
- if (matchSet_48[3]) begin // @[L1ICache.scala 151:28]
- history_47_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_47_3 > _GEN_755) begin // @[L1ICache.scala 153:50]
- history_47_3 <= _history_47_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_48_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_193) begin // @[L1ICache.scala 149:117]
- if (matchSet_49[0]) begin // @[L1ICache.scala 151:28]
- history_48_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_48_0 > _GEN_771) begin // @[L1ICache.scala 153:50]
- history_48_0 <= _history_48_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_48_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_193) begin // @[L1ICache.scala 149:117]
- if (matchSet_49[1]) begin // @[L1ICache.scala 151:28]
- history_48_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_48_1 > _GEN_771) begin // @[L1ICache.scala 153:50]
- history_48_1 <= _history_48_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_48_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_193) begin // @[L1ICache.scala 149:117]
- if (matchSet_49[2]) begin // @[L1ICache.scala 151:28]
- history_48_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_48_2 > _GEN_771) begin // @[L1ICache.scala 153:50]
- history_48_2 <= _history_48_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_48_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_193) begin // @[L1ICache.scala 149:117]
- if (matchSet_49[3]) begin // @[L1ICache.scala 151:28]
- history_48_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_48_3 > _GEN_771) begin // @[L1ICache.scala 153:50]
- history_48_3 <= _history_48_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_49_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_197) begin // @[L1ICache.scala 149:117]
- if (matchSet_50[0]) begin // @[L1ICache.scala 151:28]
- history_49_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_49_0 > _GEN_787) begin // @[L1ICache.scala 153:50]
- history_49_0 <= _history_49_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_49_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_197) begin // @[L1ICache.scala 149:117]
- if (matchSet_50[1]) begin // @[L1ICache.scala 151:28]
- history_49_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_49_1 > _GEN_787) begin // @[L1ICache.scala 153:50]
- history_49_1 <= _history_49_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_49_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_197) begin // @[L1ICache.scala 149:117]
- if (matchSet_50[2]) begin // @[L1ICache.scala 151:28]
- history_49_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_49_2 > _GEN_787) begin // @[L1ICache.scala 153:50]
- history_49_2 <= _history_49_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_49_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_197) begin // @[L1ICache.scala 149:117]
- if (matchSet_50[3]) begin // @[L1ICache.scala 151:28]
- history_49_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_49_3 > _GEN_787) begin // @[L1ICache.scala 153:50]
- history_49_3 <= _history_49_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_50_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_201) begin // @[L1ICache.scala 149:117]
- if (matchSet_51[0]) begin // @[L1ICache.scala 151:28]
- history_50_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_50_0 > _GEN_803) begin // @[L1ICache.scala 153:50]
- history_50_0 <= _history_50_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_50_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_201) begin // @[L1ICache.scala 149:117]
- if (matchSet_51[1]) begin // @[L1ICache.scala 151:28]
- history_50_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_50_1 > _GEN_803) begin // @[L1ICache.scala 153:50]
- history_50_1 <= _history_50_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_50_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_201) begin // @[L1ICache.scala 149:117]
- if (matchSet_51[2]) begin // @[L1ICache.scala 151:28]
- history_50_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_50_2 > _GEN_803) begin // @[L1ICache.scala 153:50]
- history_50_2 <= _history_50_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_50_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_201) begin // @[L1ICache.scala 149:117]
- if (matchSet_51[3]) begin // @[L1ICache.scala 151:28]
- history_50_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_50_3 > _GEN_803) begin // @[L1ICache.scala 153:50]
- history_50_3 <= _history_50_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_51_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_205) begin // @[L1ICache.scala 149:117]
- if (matchSet_52[0]) begin // @[L1ICache.scala 151:28]
- history_51_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_51_0 > _GEN_819) begin // @[L1ICache.scala 153:50]
- history_51_0 <= _history_51_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_51_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_205) begin // @[L1ICache.scala 149:117]
- if (matchSet_52[1]) begin // @[L1ICache.scala 151:28]
- history_51_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_51_1 > _GEN_819) begin // @[L1ICache.scala 153:50]
- history_51_1 <= _history_51_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_51_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_205) begin // @[L1ICache.scala 149:117]
- if (matchSet_52[2]) begin // @[L1ICache.scala 151:28]
- history_51_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_51_2 > _GEN_819) begin // @[L1ICache.scala 153:50]
- history_51_2 <= _history_51_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_51_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_205) begin // @[L1ICache.scala 149:117]
- if (matchSet_52[3]) begin // @[L1ICache.scala 151:28]
- history_51_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_51_3 > _GEN_819) begin // @[L1ICache.scala 153:50]
- history_51_3 <= _history_51_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_52_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_209) begin // @[L1ICache.scala 149:117]
- if (matchSet_53[0]) begin // @[L1ICache.scala 151:28]
- history_52_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_52_0 > _GEN_835) begin // @[L1ICache.scala 153:50]
- history_52_0 <= _history_52_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_52_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_209) begin // @[L1ICache.scala 149:117]
- if (matchSet_53[1]) begin // @[L1ICache.scala 151:28]
- history_52_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_52_1 > _GEN_835) begin // @[L1ICache.scala 153:50]
- history_52_1 <= _history_52_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_52_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_209) begin // @[L1ICache.scala 149:117]
- if (matchSet_53[2]) begin // @[L1ICache.scala 151:28]
- history_52_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_52_2 > _GEN_835) begin // @[L1ICache.scala 153:50]
- history_52_2 <= _history_52_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_52_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_209) begin // @[L1ICache.scala 149:117]
- if (matchSet_53[3]) begin // @[L1ICache.scala 151:28]
- history_52_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_52_3 > _GEN_835) begin // @[L1ICache.scala 153:50]
- history_52_3 <= _history_52_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_53_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_213) begin // @[L1ICache.scala 149:117]
- if (matchSet_54[0]) begin // @[L1ICache.scala 151:28]
- history_53_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_53_0 > _GEN_851) begin // @[L1ICache.scala 153:50]
- history_53_0 <= _history_53_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_53_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_213) begin // @[L1ICache.scala 149:117]
- if (matchSet_54[1]) begin // @[L1ICache.scala 151:28]
- history_53_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_53_1 > _GEN_851) begin // @[L1ICache.scala 153:50]
- history_53_1 <= _history_53_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_53_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_213) begin // @[L1ICache.scala 149:117]
- if (matchSet_54[2]) begin // @[L1ICache.scala 151:28]
- history_53_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_53_2 > _GEN_851) begin // @[L1ICache.scala 153:50]
- history_53_2 <= _history_53_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_53_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_213) begin // @[L1ICache.scala 149:117]
- if (matchSet_54[3]) begin // @[L1ICache.scala 151:28]
- history_53_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_53_3 > _GEN_851) begin // @[L1ICache.scala 153:50]
- history_53_3 <= _history_53_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_54_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_217) begin // @[L1ICache.scala 149:117]
- if (matchSet_55[0]) begin // @[L1ICache.scala 151:28]
- history_54_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_54_0 > _GEN_867) begin // @[L1ICache.scala 153:50]
- history_54_0 <= _history_54_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_54_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_217) begin // @[L1ICache.scala 149:117]
- if (matchSet_55[1]) begin // @[L1ICache.scala 151:28]
- history_54_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_54_1 > _GEN_867) begin // @[L1ICache.scala 153:50]
- history_54_1 <= _history_54_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_54_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_217) begin // @[L1ICache.scala 149:117]
- if (matchSet_55[2]) begin // @[L1ICache.scala 151:28]
- history_54_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_54_2 > _GEN_867) begin // @[L1ICache.scala 153:50]
- history_54_2 <= _history_54_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_54_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_217) begin // @[L1ICache.scala 149:117]
- if (matchSet_55[3]) begin // @[L1ICache.scala 151:28]
- history_54_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_54_3 > _GEN_867) begin // @[L1ICache.scala 153:50]
- history_54_3 <= _history_54_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_55_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_221) begin // @[L1ICache.scala 149:117]
- if (matchSet_56[0]) begin // @[L1ICache.scala 151:28]
- history_55_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_55_0 > _GEN_883) begin // @[L1ICache.scala 153:50]
- history_55_0 <= _history_55_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_55_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_221) begin // @[L1ICache.scala 149:117]
- if (matchSet_56[1]) begin // @[L1ICache.scala 151:28]
- history_55_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_55_1 > _GEN_883) begin // @[L1ICache.scala 153:50]
- history_55_1 <= _history_55_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_55_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_221) begin // @[L1ICache.scala 149:117]
- if (matchSet_56[2]) begin // @[L1ICache.scala 151:28]
- history_55_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_55_2 > _GEN_883) begin // @[L1ICache.scala 153:50]
- history_55_2 <= _history_55_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_55_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_221) begin // @[L1ICache.scala 149:117]
- if (matchSet_56[3]) begin // @[L1ICache.scala 151:28]
- history_55_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_55_3 > _GEN_883) begin // @[L1ICache.scala 153:50]
- history_55_3 <= _history_55_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_56_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_225) begin // @[L1ICache.scala 149:117]
- if (matchSet_57[0]) begin // @[L1ICache.scala 151:28]
- history_56_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_56_0 > _GEN_899) begin // @[L1ICache.scala 153:50]
- history_56_0 <= _history_56_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_56_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_225) begin // @[L1ICache.scala 149:117]
- if (matchSet_57[1]) begin // @[L1ICache.scala 151:28]
- history_56_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_56_1 > _GEN_899) begin // @[L1ICache.scala 153:50]
- history_56_1 <= _history_56_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_56_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_225) begin // @[L1ICache.scala 149:117]
- if (matchSet_57[2]) begin // @[L1ICache.scala 151:28]
- history_56_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_56_2 > _GEN_899) begin // @[L1ICache.scala 153:50]
- history_56_2 <= _history_56_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_56_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_225) begin // @[L1ICache.scala 149:117]
- if (matchSet_57[3]) begin // @[L1ICache.scala 151:28]
- history_56_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_56_3 > _GEN_899) begin // @[L1ICache.scala 153:50]
- history_56_3 <= _history_56_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_57_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_229) begin // @[L1ICache.scala 149:117]
- if (matchSet_58[0]) begin // @[L1ICache.scala 151:28]
- history_57_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_57_0 > _GEN_915) begin // @[L1ICache.scala 153:50]
- history_57_0 <= _history_57_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_57_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_229) begin // @[L1ICache.scala 149:117]
- if (matchSet_58[1]) begin // @[L1ICache.scala 151:28]
- history_57_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_57_1 > _GEN_915) begin // @[L1ICache.scala 153:50]
- history_57_1 <= _history_57_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_57_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_229) begin // @[L1ICache.scala 149:117]
- if (matchSet_58[2]) begin // @[L1ICache.scala 151:28]
- history_57_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_57_2 > _GEN_915) begin // @[L1ICache.scala 153:50]
- history_57_2 <= _history_57_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_57_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_229) begin // @[L1ICache.scala 149:117]
- if (matchSet_58[3]) begin // @[L1ICache.scala 151:28]
- history_57_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_57_3 > _GEN_915) begin // @[L1ICache.scala 153:50]
- history_57_3 <= _history_57_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_58_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_233) begin // @[L1ICache.scala 149:117]
- if (matchSet_59[0]) begin // @[L1ICache.scala 151:28]
- history_58_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_58_0 > _GEN_931) begin // @[L1ICache.scala 153:50]
- history_58_0 <= _history_58_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_58_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_233) begin // @[L1ICache.scala 149:117]
- if (matchSet_59[1]) begin // @[L1ICache.scala 151:28]
- history_58_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_58_1 > _GEN_931) begin // @[L1ICache.scala 153:50]
- history_58_1 <= _history_58_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_58_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_233) begin // @[L1ICache.scala 149:117]
- if (matchSet_59[2]) begin // @[L1ICache.scala 151:28]
- history_58_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_58_2 > _GEN_931) begin // @[L1ICache.scala 153:50]
- history_58_2 <= _history_58_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_58_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_233) begin // @[L1ICache.scala 149:117]
- if (matchSet_59[3]) begin // @[L1ICache.scala 151:28]
- history_58_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_58_3 > _GEN_931) begin // @[L1ICache.scala 153:50]
- history_58_3 <= _history_58_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_59_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_237) begin // @[L1ICache.scala 149:117]
- if (matchSet_60[0]) begin // @[L1ICache.scala 151:28]
- history_59_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_59_0 > _GEN_947) begin // @[L1ICache.scala 153:50]
- history_59_0 <= _history_59_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_59_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_237) begin // @[L1ICache.scala 149:117]
- if (matchSet_60[1]) begin // @[L1ICache.scala 151:28]
- history_59_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_59_1 > _GEN_947) begin // @[L1ICache.scala 153:50]
- history_59_1 <= _history_59_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_59_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_237) begin // @[L1ICache.scala 149:117]
- if (matchSet_60[2]) begin // @[L1ICache.scala 151:28]
- history_59_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_59_2 > _GEN_947) begin // @[L1ICache.scala 153:50]
- history_59_2 <= _history_59_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_59_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_237) begin // @[L1ICache.scala 149:117]
- if (matchSet_60[3]) begin // @[L1ICache.scala 151:28]
- history_59_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_59_3 > _GEN_947) begin // @[L1ICache.scala 153:50]
- history_59_3 <= _history_59_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_60_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_241) begin // @[L1ICache.scala 149:117]
- if (matchSet_61[0]) begin // @[L1ICache.scala 151:28]
- history_60_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_60_0 > _GEN_963) begin // @[L1ICache.scala 153:50]
- history_60_0 <= _history_60_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_60_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_241) begin // @[L1ICache.scala 149:117]
- if (matchSet_61[1]) begin // @[L1ICache.scala 151:28]
- history_60_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_60_1 > _GEN_963) begin // @[L1ICache.scala 153:50]
- history_60_1 <= _history_60_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_60_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_241) begin // @[L1ICache.scala 149:117]
- if (matchSet_61[2]) begin // @[L1ICache.scala 151:28]
- history_60_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_60_2 > _GEN_963) begin // @[L1ICache.scala 153:50]
- history_60_2 <= _history_60_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_60_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_241) begin // @[L1ICache.scala 149:117]
- if (matchSet_61[3]) begin // @[L1ICache.scala 151:28]
- history_60_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_60_3 > _GEN_963) begin // @[L1ICache.scala 153:50]
- history_60_3 <= _history_60_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_61_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_245) begin // @[L1ICache.scala 149:117]
- if (matchSet_62[0]) begin // @[L1ICache.scala 151:28]
- history_61_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_61_0 > _GEN_979) begin // @[L1ICache.scala 153:50]
- history_61_0 <= _history_61_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_61_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_245) begin // @[L1ICache.scala 149:117]
- if (matchSet_62[1]) begin // @[L1ICache.scala 151:28]
- history_61_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_61_1 > _GEN_979) begin // @[L1ICache.scala 153:50]
- history_61_1 <= _history_61_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_61_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_245) begin // @[L1ICache.scala 149:117]
- if (matchSet_62[2]) begin // @[L1ICache.scala 151:28]
- history_61_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_61_2 > _GEN_979) begin // @[L1ICache.scala 153:50]
- history_61_2 <= _history_61_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_61_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_245) begin // @[L1ICache.scala 149:117]
- if (matchSet_62[3]) begin // @[L1ICache.scala 151:28]
- history_61_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_61_3 > _GEN_979) begin // @[L1ICache.scala 153:50]
- history_61_3 <= _history_61_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_62_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_249) begin // @[L1ICache.scala 149:117]
- if (matchSet_63[0]) begin // @[L1ICache.scala 151:28]
- history_62_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_62_0 > _GEN_995) begin // @[L1ICache.scala 153:50]
- history_62_0 <= _history_62_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_62_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_249) begin // @[L1ICache.scala 149:117]
- if (matchSet_63[1]) begin // @[L1ICache.scala 151:28]
- history_62_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_62_1 > _GEN_995) begin // @[L1ICache.scala 153:50]
- history_62_1 <= _history_62_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_62_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_249) begin // @[L1ICache.scala 149:117]
- if (matchSet_63[2]) begin // @[L1ICache.scala 151:28]
- history_62_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_62_2 > _GEN_995) begin // @[L1ICache.scala 153:50]
- history_62_2 <= _history_62_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_62_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_249) begin // @[L1ICache.scala 149:117]
- if (matchSet_63[3]) begin // @[L1ICache.scala 151:28]
- history_62_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_62_3 > _GEN_995) begin // @[L1ICache.scala 153:50]
- history_62_3 <= _history_62_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_63_0 <= 2'h0; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_253) begin // @[L1ICache.scala 149:117]
- if (matchSet_64[0]) begin // @[L1ICache.scala 151:28]
- history_63_0 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_63_0 > _GEN_1011) begin // @[L1ICache.scala 153:50]
- history_63_0 <= _history_63_0_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_63_1 <= 2'h1; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_253) begin // @[L1ICache.scala 149:117]
- if (matchSet_64[1]) begin // @[L1ICache.scala 151:28]
- history_63_1 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_63_1 > _GEN_1011) begin // @[L1ICache.scala 153:50]
- history_63_1 <= _history_63_1_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_63_2 <= 2'h2; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_253) begin // @[L1ICache.scala 149:117]
- if (matchSet_64[2]) begin // @[L1ICache.scala 151:28]
- history_63_2 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_63_2 > _GEN_1011) begin // @[L1ICache.scala 153:50]
- history_63_2 <= _history_63_2_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (reset) begin // @[L1ICache.scala 164:23]
- history_63_3 <= 2'h3; // @[L1ICache.scala 167:23]
- end else if (io_ibus_valid & io_ibus_ready & setMatch_253) begin // @[L1ICache.scala 149:117]
- if (matchSet_64[3]) begin // @[L1ICache.scala 151:28]
- history_63_3 <= 2'h3; // @[L1ICache.scala 152:25]
- end else if (history_63_3 > _GEN_1011) begin // @[L1ICache.scala 153:50]
- history_63_3 <= _history_63_3_T_1; // @[L1ICache.scala 154:25]
- end
- end
- if (_T_4234) begin // @[L1ICache.scala 225:68]
- axiaddr <= alignedAddr; // @[L1ICache.scala 227:13]
- end else if (_T_4235) begin // @[L1ICache.scala 229:66]
- axiaddr <= _axiaddr_T_1; // @[L1ICache.scala 230:13]
- end
- if (io_ibus_valid & ~io_ibus_ready & ~axivalid & ~axiready) begin // @[L1ICache.scala 199:68]
- replaceIdReg <= replaceId; // @[L1ICache.scala 200:18]
- end
- if (!(io_flush_valid)) begin // @[L1ICache.scala 245:25]
- if (_T_4230 & ~addrLatchActive) begin // @[L1ICache.scala 247:69]
- addrLatchData <= io_ibus_addr; // @[L1ICache.scala 249:19]
- end
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_764 <= 9'h1)) begin
- $fatal; // @[L1ICache.scala 117:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_764 <= 9'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:117 assert(PopCount(matchSlot) <= 1.U)\n"); // @[L1ICache.scala 117:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_1534 <= 9'h1)) begin
- $fatal; // @[L1ICache.scala 118:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_1534 <= 9'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:118 assert(PopCount(replaceSlot) <= 1.U)\n"); // @[L1ICache.scala 118:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_1548 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_1548 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1557 & ~matchSet_1[0] & _T_1559 & _T_768 & ~(history_0_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1557 & ~matchSet_1[0] & _T_1559 & _T_768 & ~(history_0_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1557 & ~matchSet_1[1] & _T_1565 & _T_768 & ~(history_0_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1557 & ~matchSet_1[1] & _T_1565 & _T_768 & ~(history_0_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1557 & ~matchSet_1[2] & _T_1571 & _T_768 & ~(history_0_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1557 & ~matchSet_1[2] & _T_1571 & _T_768 & ~(history_0_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1557 & ~matchSet_1[3] & _T_1577 & _T_768 & ~(history_0_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1557 & ~matchSet_1[3] & _T_1577 & _T_768 & ~(history_0_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_1590 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_1590 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1599 & ~matchSet_2[0] & _T_1601 & _T_768 & ~(history_1_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1599 & ~matchSet_2[0] & _T_1601 & _T_768 & ~(history_1_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1599 & ~matchSet_2[1] & _T_1607 & _T_768 & ~(history_1_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1599 & ~matchSet_2[1] & _T_1607 & _T_768 & ~(history_1_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1599 & ~matchSet_2[2] & _T_1613 & _T_768 & ~(history_1_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1599 & ~matchSet_2[2] & _T_1613 & _T_768 & ~(history_1_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1599 & ~matchSet_2[3] & _T_1619 & _T_768 & ~(history_1_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1599 & ~matchSet_2[3] & _T_1619 & _T_768 & ~(history_1_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_1632 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_1632 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1641 & ~matchSet_3[0] & _T_1643 & _T_768 & ~(history_2_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1641 & ~matchSet_3[0] & _T_1643 & _T_768 & ~(history_2_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1641 & ~matchSet_3[1] & _T_1649 & _T_768 & ~(history_2_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1641 & ~matchSet_3[1] & _T_1649 & _T_768 & ~(history_2_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1641 & ~matchSet_3[2] & _T_1655 & _T_768 & ~(history_2_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1641 & ~matchSet_3[2] & _T_1655 & _T_768 & ~(history_2_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1641 & ~matchSet_3[3] & _T_1661 & _T_768 & ~(history_2_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1641 & ~matchSet_3[3] & _T_1661 & _T_768 & ~(history_2_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_1674 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_1674 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1683 & ~matchSet_4[0] & _T_1685 & _T_768 & ~(history_3_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1683 & ~matchSet_4[0] & _T_1685 & _T_768 & ~(history_3_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1683 & ~matchSet_4[1] & _T_1691 & _T_768 & ~(history_3_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1683 & ~matchSet_4[1] & _T_1691 & _T_768 & ~(history_3_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1683 & ~matchSet_4[2] & _T_1697 & _T_768 & ~(history_3_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1683 & ~matchSet_4[2] & _T_1697 & _T_768 & ~(history_3_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1683 & ~matchSet_4[3] & _T_1703 & _T_768 & ~(history_3_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1683 & ~matchSet_4[3] & _T_1703 & _T_768 & ~(history_3_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_1716 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_1716 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1725 & ~matchSet_5[0] & _T_1727 & _T_768 & ~(history_4_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1725 & ~matchSet_5[0] & _T_1727 & _T_768 & ~(history_4_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1725 & ~matchSet_5[1] & _T_1733 & _T_768 & ~(history_4_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1725 & ~matchSet_5[1] & _T_1733 & _T_768 & ~(history_4_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1725 & ~matchSet_5[2] & _T_1739 & _T_768 & ~(history_4_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1725 & ~matchSet_5[2] & _T_1739 & _T_768 & ~(history_4_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1725 & ~matchSet_5[3] & _T_1745 & _T_768 & ~(history_4_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1725 & ~matchSet_5[3] & _T_1745 & _T_768 & ~(history_4_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_1758 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_1758 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1767 & ~matchSet_6[0] & _T_1769 & _T_768 & ~(history_5_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1767 & ~matchSet_6[0] & _T_1769 & _T_768 & ~(history_5_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1767 & ~matchSet_6[1] & _T_1775 & _T_768 & ~(history_5_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1767 & ~matchSet_6[1] & _T_1775 & _T_768 & ~(history_5_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1767 & ~matchSet_6[2] & _T_1781 & _T_768 & ~(history_5_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1767 & ~matchSet_6[2] & _T_1781 & _T_768 & ~(history_5_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1767 & ~matchSet_6[3] & _T_1787 & _T_768 & ~(history_5_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1767 & ~matchSet_6[3] & _T_1787 & _T_768 & ~(history_5_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_1800 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_1800 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1809 & ~matchSet_7[0] & _T_1811 & _T_768 & ~(history_6_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1809 & ~matchSet_7[0] & _T_1811 & _T_768 & ~(history_6_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1809 & ~matchSet_7[1] & _T_1817 & _T_768 & ~(history_6_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1809 & ~matchSet_7[1] & _T_1817 & _T_768 & ~(history_6_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1809 & ~matchSet_7[2] & _T_1823 & _T_768 & ~(history_6_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1809 & ~matchSet_7[2] & _T_1823 & _T_768 & ~(history_6_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1809 & ~matchSet_7[3] & _T_1829 & _T_768 & ~(history_6_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1809 & ~matchSet_7[3] & _T_1829 & _T_768 & ~(history_6_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_1842 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_1842 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1851 & ~matchSet_8[0] & _T_1853 & _T_768 & ~(history_7_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1851 & ~matchSet_8[0] & _T_1853 & _T_768 & ~(history_7_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1851 & ~matchSet_8[1] & _T_1859 & _T_768 & ~(history_7_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1851 & ~matchSet_8[1] & _T_1859 & _T_768 & ~(history_7_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1851 & ~matchSet_8[2] & _T_1865 & _T_768 & ~(history_7_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1851 & ~matchSet_8[2] & _T_1865 & _T_768 & ~(history_7_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1851 & ~matchSet_8[3] & _T_1871 & _T_768 & ~(history_7_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1851 & ~matchSet_8[3] & _T_1871 & _T_768 & ~(history_7_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_1884 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_1884 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1893 & ~matchSet_9[0] & _T_1895 & _T_768 & ~(history_8_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1893 & ~matchSet_9[0] & _T_1895 & _T_768 & ~(history_8_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1893 & ~matchSet_9[1] & _T_1901 & _T_768 & ~(history_8_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1893 & ~matchSet_9[1] & _T_1901 & _T_768 & ~(history_8_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1893 & ~matchSet_9[2] & _T_1907 & _T_768 & ~(history_8_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1893 & ~matchSet_9[2] & _T_1907 & _T_768 & ~(history_8_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1893 & ~matchSet_9[3] & _T_1913 & _T_768 & ~(history_8_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1893 & ~matchSet_9[3] & _T_1913 & _T_768 & ~(history_8_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_1926 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_1926 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1935 & ~matchSet_10[0] & _T_1937 & _T_768 & ~(history_9_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1935 & ~matchSet_10[0] & _T_1937 & _T_768 & ~(history_9_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1935 & ~matchSet_10[1] & _T_1943 & _T_768 & ~(history_9_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1935 & ~matchSet_10[1] & _T_1943 & _T_768 & ~(history_9_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1935 & ~matchSet_10[2] & _T_1949 & _T_768 & ~(history_9_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1935 & ~matchSet_10[2] & _T_1949 & _T_768 & ~(history_9_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1935 & ~matchSet_10[3] & _T_1955 & _T_768 & ~(history_9_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1935 & ~matchSet_10[3] & _T_1955 & _T_768 & ~(history_9_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_1968 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_1968 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1977 & ~matchSet_11[0] & _T_1979 & _T_768 & ~(history_10_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1977 & ~matchSet_11[0] & _T_1979 & _T_768 & ~(history_10_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1977 & ~matchSet_11[1] & _T_1985 & _T_768 & ~(history_10_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1977 & ~matchSet_11[1] & _T_1985 & _T_768 & ~(history_10_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1977 & ~matchSet_11[2] & _T_1991 & _T_768 & ~(history_10_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1977 & ~matchSet_11[2] & _T_1991 & _T_768 & ~(history_10_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_1977 & ~matchSet_11[3] & _T_1997 & _T_768 & ~(history_10_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_1977 & ~matchSet_11[3] & _T_1997 & _T_768 & ~(history_10_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2010 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2010 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2019 & ~matchSet_12[0] & _T_2021 & _T_768 & ~(history_11_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2019 & ~matchSet_12[0] & _T_2021 & _T_768 & ~(history_11_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2019 & ~matchSet_12[1] & _T_2027 & _T_768 & ~(history_11_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2019 & ~matchSet_12[1] & _T_2027 & _T_768 & ~(history_11_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2019 & ~matchSet_12[2] & _T_2033 & _T_768 & ~(history_11_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2019 & ~matchSet_12[2] & _T_2033 & _T_768 & ~(history_11_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2019 & ~matchSet_12[3] & _T_2039 & _T_768 & ~(history_11_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2019 & ~matchSet_12[3] & _T_2039 & _T_768 & ~(history_11_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2052 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2052 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2061 & ~matchSet_13[0] & _T_2063 & _T_768 & ~(history_12_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2061 & ~matchSet_13[0] & _T_2063 & _T_768 & ~(history_12_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2061 & ~matchSet_13[1] & _T_2069 & _T_768 & ~(history_12_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2061 & ~matchSet_13[1] & _T_2069 & _T_768 & ~(history_12_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2061 & ~matchSet_13[2] & _T_2075 & _T_768 & ~(history_12_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2061 & ~matchSet_13[2] & _T_2075 & _T_768 & ~(history_12_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2061 & ~matchSet_13[3] & _T_2081 & _T_768 & ~(history_12_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2061 & ~matchSet_13[3] & _T_2081 & _T_768 & ~(history_12_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2094 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2094 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2103 & ~matchSet_14[0] & _T_2105 & _T_768 & ~(history_13_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2103 & ~matchSet_14[0] & _T_2105 & _T_768 & ~(history_13_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2103 & ~matchSet_14[1] & _T_2111 & _T_768 & ~(history_13_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2103 & ~matchSet_14[1] & _T_2111 & _T_768 & ~(history_13_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2103 & ~matchSet_14[2] & _T_2117 & _T_768 & ~(history_13_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2103 & ~matchSet_14[2] & _T_2117 & _T_768 & ~(history_13_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2103 & ~matchSet_14[3] & _T_2123 & _T_768 & ~(history_13_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2103 & ~matchSet_14[3] & _T_2123 & _T_768 & ~(history_13_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2136 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2136 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2145 & ~matchSet_15[0] & _T_2147 & _T_768 & ~(history_14_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2145 & ~matchSet_15[0] & _T_2147 & _T_768 & ~(history_14_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2145 & ~matchSet_15[1] & _T_2153 & _T_768 & ~(history_14_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2145 & ~matchSet_15[1] & _T_2153 & _T_768 & ~(history_14_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2145 & ~matchSet_15[2] & _T_2159 & _T_768 & ~(history_14_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2145 & ~matchSet_15[2] & _T_2159 & _T_768 & ~(history_14_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2145 & ~matchSet_15[3] & _T_2165 & _T_768 & ~(history_14_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2145 & ~matchSet_15[3] & _T_2165 & _T_768 & ~(history_14_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2178 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2178 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2187 & ~matchSet_16[0] & _T_2189 & _T_768 & ~(history_15_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2187 & ~matchSet_16[0] & _T_2189 & _T_768 & ~(history_15_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2187 & ~matchSet_16[1] & _T_2195 & _T_768 & ~(history_15_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2187 & ~matchSet_16[1] & _T_2195 & _T_768 & ~(history_15_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2187 & ~matchSet_16[2] & _T_2201 & _T_768 & ~(history_15_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2187 & ~matchSet_16[2] & _T_2201 & _T_768 & ~(history_15_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2187 & ~matchSet_16[3] & _T_2207 & _T_768 & ~(history_15_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2187 & ~matchSet_16[3] & _T_2207 & _T_768 & ~(history_15_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2220 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2220 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2229 & ~matchSet_17[0] & _T_2231 & _T_768 & ~(history_16_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2229 & ~matchSet_17[0] & _T_2231 & _T_768 & ~(history_16_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2229 & ~matchSet_17[1] & _T_2237 & _T_768 & ~(history_16_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2229 & ~matchSet_17[1] & _T_2237 & _T_768 & ~(history_16_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2229 & ~matchSet_17[2] & _T_2243 & _T_768 & ~(history_16_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2229 & ~matchSet_17[2] & _T_2243 & _T_768 & ~(history_16_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2229 & ~matchSet_17[3] & _T_2249 & _T_768 & ~(history_16_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2229 & ~matchSet_17[3] & _T_2249 & _T_768 & ~(history_16_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2262 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2262 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2271 & ~matchSet_18[0] & _T_2273 & _T_768 & ~(history_17_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2271 & ~matchSet_18[0] & _T_2273 & _T_768 & ~(history_17_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2271 & ~matchSet_18[1] & _T_2279 & _T_768 & ~(history_17_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2271 & ~matchSet_18[1] & _T_2279 & _T_768 & ~(history_17_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2271 & ~matchSet_18[2] & _T_2285 & _T_768 & ~(history_17_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2271 & ~matchSet_18[2] & _T_2285 & _T_768 & ~(history_17_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2271 & ~matchSet_18[3] & _T_2291 & _T_768 & ~(history_17_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2271 & ~matchSet_18[3] & _T_2291 & _T_768 & ~(history_17_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2304 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2304 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2313 & ~matchSet_19[0] & _T_2315 & _T_768 & ~(history_18_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2313 & ~matchSet_19[0] & _T_2315 & _T_768 & ~(history_18_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2313 & ~matchSet_19[1] & _T_2321 & _T_768 & ~(history_18_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2313 & ~matchSet_19[1] & _T_2321 & _T_768 & ~(history_18_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2313 & ~matchSet_19[2] & _T_2327 & _T_768 & ~(history_18_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2313 & ~matchSet_19[2] & _T_2327 & _T_768 & ~(history_18_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2313 & ~matchSet_19[3] & _T_2333 & _T_768 & ~(history_18_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2313 & ~matchSet_19[3] & _T_2333 & _T_768 & ~(history_18_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2346 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2346 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2355 & ~matchSet_20[0] & _T_2357 & _T_768 & ~(history_19_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2355 & ~matchSet_20[0] & _T_2357 & _T_768 & ~(history_19_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2355 & ~matchSet_20[1] & _T_2363 & _T_768 & ~(history_19_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2355 & ~matchSet_20[1] & _T_2363 & _T_768 & ~(history_19_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2355 & ~matchSet_20[2] & _T_2369 & _T_768 & ~(history_19_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2355 & ~matchSet_20[2] & _T_2369 & _T_768 & ~(history_19_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2355 & ~matchSet_20[3] & _T_2375 & _T_768 & ~(history_19_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2355 & ~matchSet_20[3] & _T_2375 & _T_768 & ~(history_19_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2388 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2388 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2397 & ~matchSet_21[0] & _T_2399 & _T_768 & ~(history_20_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2397 & ~matchSet_21[0] & _T_2399 & _T_768 & ~(history_20_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2397 & ~matchSet_21[1] & _T_2405 & _T_768 & ~(history_20_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2397 & ~matchSet_21[1] & _T_2405 & _T_768 & ~(history_20_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2397 & ~matchSet_21[2] & _T_2411 & _T_768 & ~(history_20_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2397 & ~matchSet_21[2] & _T_2411 & _T_768 & ~(history_20_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2397 & ~matchSet_21[3] & _T_2417 & _T_768 & ~(history_20_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2397 & ~matchSet_21[3] & _T_2417 & _T_768 & ~(history_20_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2430 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2430 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2439 & ~matchSet_22[0] & _T_2441 & _T_768 & ~(history_21_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2439 & ~matchSet_22[0] & _T_2441 & _T_768 & ~(history_21_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2439 & ~matchSet_22[1] & _T_2447 & _T_768 & ~(history_21_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2439 & ~matchSet_22[1] & _T_2447 & _T_768 & ~(history_21_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2439 & ~matchSet_22[2] & _T_2453 & _T_768 & ~(history_21_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2439 & ~matchSet_22[2] & _T_2453 & _T_768 & ~(history_21_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2439 & ~matchSet_22[3] & _T_2459 & _T_768 & ~(history_21_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2439 & ~matchSet_22[3] & _T_2459 & _T_768 & ~(history_21_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2472 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2472 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2481 & ~matchSet_23[0] & _T_2483 & _T_768 & ~(history_22_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2481 & ~matchSet_23[0] & _T_2483 & _T_768 & ~(history_22_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2481 & ~matchSet_23[1] & _T_2489 & _T_768 & ~(history_22_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2481 & ~matchSet_23[1] & _T_2489 & _T_768 & ~(history_22_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2481 & ~matchSet_23[2] & _T_2495 & _T_768 & ~(history_22_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2481 & ~matchSet_23[2] & _T_2495 & _T_768 & ~(history_22_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2481 & ~matchSet_23[3] & _T_2501 & _T_768 & ~(history_22_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2481 & ~matchSet_23[3] & _T_2501 & _T_768 & ~(history_22_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2514 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2514 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2523 & ~matchSet_24[0] & _T_2525 & _T_768 & ~(history_23_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2523 & ~matchSet_24[0] & _T_2525 & _T_768 & ~(history_23_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2523 & ~matchSet_24[1] & _T_2531 & _T_768 & ~(history_23_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2523 & ~matchSet_24[1] & _T_2531 & _T_768 & ~(history_23_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2523 & ~matchSet_24[2] & _T_2537 & _T_768 & ~(history_23_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2523 & ~matchSet_24[2] & _T_2537 & _T_768 & ~(history_23_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2523 & ~matchSet_24[3] & _T_2543 & _T_768 & ~(history_23_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2523 & ~matchSet_24[3] & _T_2543 & _T_768 & ~(history_23_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2556 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2556 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2565 & ~matchSet_25[0] & _T_2567 & _T_768 & ~(history_24_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2565 & ~matchSet_25[0] & _T_2567 & _T_768 & ~(history_24_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2565 & ~matchSet_25[1] & _T_2573 & _T_768 & ~(history_24_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2565 & ~matchSet_25[1] & _T_2573 & _T_768 & ~(history_24_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2565 & ~matchSet_25[2] & _T_2579 & _T_768 & ~(history_24_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2565 & ~matchSet_25[2] & _T_2579 & _T_768 & ~(history_24_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2565 & ~matchSet_25[3] & _T_2585 & _T_768 & ~(history_24_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2565 & ~matchSet_25[3] & _T_2585 & _T_768 & ~(history_24_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2598 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2598 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2607 & ~matchSet_26[0] & _T_2609 & _T_768 & ~(history_25_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2607 & ~matchSet_26[0] & _T_2609 & _T_768 & ~(history_25_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2607 & ~matchSet_26[1] & _T_2615 & _T_768 & ~(history_25_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2607 & ~matchSet_26[1] & _T_2615 & _T_768 & ~(history_25_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2607 & ~matchSet_26[2] & _T_2621 & _T_768 & ~(history_25_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2607 & ~matchSet_26[2] & _T_2621 & _T_768 & ~(history_25_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2607 & ~matchSet_26[3] & _T_2627 & _T_768 & ~(history_25_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2607 & ~matchSet_26[3] & _T_2627 & _T_768 & ~(history_25_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2640 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2640 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2649 & ~matchSet_27[0] & _T_2651 & _T_768 & ~(history_26_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2649 & ~matchSet_27[0] & _T_2651 & _T_768 & ~(history_26_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2649 & ~matchSet_27[1] & _T_2657 & _T_768 & ~(history_26_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2649 & ~matchSet_27[1] & _T_2657 & _T_768 & ~(history_26_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2649 & ~matchSet_27[2] & _T_2663 & _T_768 & ~(history_26_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2649 & ~matchSet_27[2] & _T_2663 & _T_768 & ~(history_26_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2649 & ~matchSet_27[3] & _T_2669 & _T_768 & ~(history_26_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2649 & ~matchSet_27[3] & _T_2669 & _T_768 & ~(history_26_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2682 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2682 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2691 & ~matchSet_28[0] & _T_2693 & _T_768 & ~(history_27_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2691 & ~matchSet_28[0] & _T_2693 & _T_768 & ~(history_27_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2691 & ~matchSet_28[1] & _T_2699 & _T_768 & ~(history_27_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2691 & ~matchSet_28[1] & _T_2699 & _T_768 & ~(history_27_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2691 & ~matchSet_28[2] & _T_2705 & _T_768 & ~(history_27_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2691 & ~matchSet_28[2] & _T_2705 & _T_768 & ~(history_27_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2691 & ~matchSet_28[3] & _T_2711 & _T_768 & ~(history_27_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2691 & ~matchSet_28[3] & _T_2711 & _T_768 & ~(history_27_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2724 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2724 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2733 & ~matchSet_29[0] & _T_2735 & _T_768 & ~(history_28_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2733 & ~matchSet_29[0] & _T_2735 & _T_768 & ~(history_28_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2733 & ~matchSet_29[1] & _T_2741 & _T_768 & ~(history_28_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2733 & ~matchSet_29[1] & _T_2741 & _T_768 & ~(history_28_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2733 & ~matchSet_29[2] & _T_2747 & _T_768 & ~(history_28_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2733 & ~matchSet_29[2] & _T_2747 & _T_768 & ~(history_28_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2733 & ~matchSet_29[3] & _T_2753 & _T_768 & ~(history_28_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2733 & ~matchSet_29[3] & _T_2753 & _T_768 & ~(history_28_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2766 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2766 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2775 & ~matchSet_30[0] & _T_2777 & _T_768 & ~(history_29_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2775 & ~matchSet_30[0] & _T_2777 & _T_768 & ~(history_29_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2775 & ~matchSet_30[1] & _T_2783 & _T_768 & ~(history_29_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2775 & ~matchSet_30[1] & _T_2783 & _T_768 & ~(history_29_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2775 & ~matchSet_30[2] & _T_2789 & _T_768 & ~(history_29_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2775 & ~matchSet_30[2] & _T_2789 & _T_768 & ~(history_29_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2775 & ~matchSet_30[3] & _T_2795 & _T_768 & ~(history_29_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2775 & ~matchSet_30[3] & _T_2795 & _T_768 & ~(history_29_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2808 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2808 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2817 & ~matchSet_31[0] & _T_2819 & _T_768 & ~(history_30_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2817 & ~matchSet_31[0] & _T_2819 & _T_768 & ~(history_30_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2817 & ~matchSet_31[1] & _T_2825 & _T_768 & ~(history_30_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2817 & ~matchSet_31[1] & _T_2825 & _T_768 & ~(history_30_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2817 & ~matchSet_31[2] & _T_2831 & _T_768 & ~(history_30_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2817 & ~matchSet_31[2] & _T_2831 & _T_768 & ~(history_30_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2817 & ~matchSet_31[3] & _T_2837 & _T_768 & ~(history_30_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2817 & ~matchSet_31[3] & _T_2837 & _T_768 & ~(history_30_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2850 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2850 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2859 & ~matchSet_32[0] & _T_2861 & _T_768 & ~(history_31_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2859 & ~matchSet_32[0] & _T_2861 & _T_768 & ~(history_31_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2859 & ~matchSet_32[1] & _T_2867 & _T_768 & ~(history_31_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2859 & ~matchSet_32[1] & _T_2867 & _T_768 & ~(history_31_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2859 & ~matchSet_32[2] & _T_2873 & _T_768 & ~(history_31_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2859 & ~matchSet_32[2] & _T_2873 & _T_768 & ~(history_31_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2859 & ~matchSet_32[3] & _T_2879 & _T_768 & ~(history_31_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2859 & ~matchSet_32[3] & _T_2879 & _T_768 & ~(history_31_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2892 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2892 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2901 & ~matchSet_33[0] & _T_2903 & _T_768 & ~(history_32_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2901 & ~matchSet_33[0] & _T_2903 & _T_768 & ~(history_32_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2901 & ~matchSet_33[1] & _T_2909 & _T_768 & ~(history_32_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2901 & ~matchSet_33[1] & _T_2909 & _T_768 & ~(history_32_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2901 & ~matchSet_33[2] & _T_2915 & _T_768 & ~(history_32_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2901 & ~matchSet_33[2] & _T_2915 & _T_768 & ~(history_32_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2901 & ~matchSet_33[3] & _T_2921 & _T_768 & ~(history_32_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2901 & ~matchSet_33[3] & _T_2921 & _T_768 & ~(history_32_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2934 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2934 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2943 & ~matchSet_34[0] & _T_2945 & _T_768 & ~(history_33_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2943 & ~matchSet_34[0] & _T_2945 & _T_768 & ~(history_33_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2943 & ~matchSet_34[1] & _T_2951 & _T_768 & ~(history_33_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2943 & ~matchSet_34[1] & _T_2951 & _T_768 & ~(history_33_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2943 & ~matchSet_34[2] & _T_2957 & _T_768 & ~(history_33_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2943 & ~matchSet_34[2] & _T_2957 & _T_768 & ~(history_33_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2943 & ~matchSet_34[3] & _T_2963 & _T_768 & ~(history_33_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2943 & ~matchSet_34[3] & _T_2963 & _T_768 & ~(history_33_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_2976 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_2976 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2985 & ~matchSet_35[0] & _T_2987 & _T_768 & ~(history_34_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2985 & ~matchSet_35[0] & _T_2987 & _T_768 & ~(history_34_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2985 & ~matchSet_35[1] & _T_2993 & _T_768 & ~(history_34_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2985 & ~matchSet_35[1] & _T_2993 & _T_768 & ~(history_34_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2985 & ~matchSet_35[2] & _T_2999 & _T_768 & ~(history_34_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2985 & ~matchSet_35[2] & _T_2999 & _T_768 & ~(history_34_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_2985 & ~matchSet_35[3] & _T_3005 & _T_768 & ~(history_34_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_2985 & ~matchSet_35[3] & _T_3005 & _T_768 & ~(history_34_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3018 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3018 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3027 & ~matchSet_36[0] & _T_3029 & _T_768 & ~(history_35_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3027 & ~matchSet_36[0] & _T_3029 & _T_768 & ~(history_35_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3027 & ~matchSet_36[1] & _T_3035 & _T_768 & ~(history_35_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3027 & ~matchSet_36[1] & _T_3035 & _T_768 & ~(history_35_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3027 & ~matchSet_36[2] & _T_3041 & _T_768 & ~(history_35_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3027 & ~matchSet_36[2] & _T_3041 & _T_768 & ~(history_35_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3027 & ~matchSet_36[3] & _T_3047 & _T_768 & ~(history_35_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3027 & ~matchSet_36[3] & _T_3047 & _T_768 & ~(history_35_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3060 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3060 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3069 & ~matchSet_37[0] & _T_3071 & _T_768 & ~(history_36_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3069 & ~matchSet_37[0] & _T_3071 & _T_768 & ~(history_36_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3069 & ~matchSet_37[1] & _T_3077 & _T_768 & ~(history_36_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3069 & ~matchSet_37[1] & _T_3077 & _T_768 & ~(history_36_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3069 & ~matchSet_37[2] & _T_3083 & _T_768 & ~(history_36_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3069 & ~matchSet_37[2] & _T_3083 & _T_768 & ~(history_36_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3069 & ~matchSet_37[3] & _T_3089 & _T_768 & ~(history_36_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3069 & ~matchSet_37[3] & _T_3089 & _T_768 & ~(history_36_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3102 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3102 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3111 & ~matchSet_38[0] & _T_3113 & _T_768 & ~(history_37_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3111 & ~matchSet_38[0] & _T_3113 & _T_768 & ~(history_37_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3111 & ~matchSet_38[1] & _T_3119 & _T_768 & ~(history_37_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3111 & ~matchSet_38[1] & _T_3119 & _T_768 & ~(history_37_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3111 & ~matchSet_38[2] & _T_3125 & _T_768 & ~(history_37_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3111 & ~matchSet_38[2] & _T_3125 & _T_768 & ~(history_37_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3111 & ~matchSet_38[3] & _T_3131 & _T_768 & ~(history_37_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3111 & ~matchSet_38[3] & _T_3131 & _T_768 & ~(history_37_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3144 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3144 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3153 & ~matchSet_39[0] & _T_3155 & _T_768 & ~(history_38_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3153 & ~matchSet_39[0] & _T_3155 & _T_768 & ~(history_38_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3153 & ~matchSet_39[1] & _T_3161 & _T_768 & ~(history_38_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3153 & ~matchSet_39[1] & _T_3161 & _T_768 & ~(history_38_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3153 & ~matchSet_39[2] & _T_3167 & _T_768 & ~(history_38_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3153 & ~matchSet_39[2] & _T_3167 & _T_768 & ~(history_38_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3153 & ~matchSet_39[3] & _T_3173 & _T_768 & ~(history_38_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3153 & ~matchSet_39[3] & _T_3173 & _T_768 & ~(history_38_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3186 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3186 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3195 & ~matchSet_40[0] & _T_3197 & _T_768 & ~(history_39_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3195 & ~matchSet_40[0] & _T_3197 & _T_768 & ~(history_39_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3195 & ~matchSet_40[1] & _T_3203 & _T_768 & ~(history_39_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3195 & ~matchSet_40[1] & _T_3203 & _T_768 & ~(history_39_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3195 & ~matchSet_40[2] & _T_3209 & _T_768 & ~(history_39_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3195 & ~matchSet_40[2] & _T_3209 & _T_768 & ~(history_39_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3195 & ~matchSet_40[3] & _T_3215 & _T_768 & ~(history_39_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3195 & ~matchSet_40[3] & _T_3215 & _T_768 & ~(history_39_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3228 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3228 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3237 & ~matchSet_41[0] & _T_3239 & _T_768 & ~(history_40_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3237 & ~matchSet_41[0] & _T_3239 & _T_768 & ~(history_40_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3237 & ~matchSet_41[1] & _T_3245 & _T_768 & ~(history_40_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3237 & ~matchSet_41[1] & _T_3245 & _T_768 & ~(history_40_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3237 & ~matchSet_41[2] & _T_3251 & _T_768 & ~(history_40_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3237 & ~matchSet_41[2] & _T_3251 & _T_768 & ~(history_40_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3237 & ~matchSet_41[3] & _T_3257 & _T_768 & ~(history_40_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3237 & ~matchSet_41[3] & _T_3257 & _T_768 & ~(history_40_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3270 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3270 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3279 & ~matchSet_42[0] & _T_3281 & _T_768 & ~(history_41_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3279 & ~matchSet_42[0] & _T_3281 & _T_768 & ~(history_41_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3279 & ~matchSet_42[1] & _T_3287 & _T_768 & ~(history_41_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3279 & ~matchSet_42[1] & _T_3287 & _T_768 & ~(history_41_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3279 & ~matchSet_42[2] & _T_3293 & _T_768 & ~(history_41_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3279 & ~matchSet_42[2] & _T_3293 & _T_768 & ~(history_41_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3279 & ~matchSet_42[3] & _T_3299 & _T_768 & ~(history_41_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3279 & ~matchSet_42[3] & _T_3299 & _T_768 & ~(history_41_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3312 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3312 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3321 & ~matchSet_43[0] & _T_3323 & _T_768 & ~(history_42_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3321 & ~matchSet_43[0] & _T_3323 & _T_768 & ~(history_42_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3321 & ~matchSet_43[1] & _T_3329 & _T_768 & ~(history_42_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3321 & ~matchSet_43[1] & _T_3329 & _T_768 & ~(history_42_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3321 & ~matchSet_43[2] & _T_3335 & _T_768 & ~(history_42_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3321 & ~matchSet_43[2] & _T_3335 & _T_768 & ~(history_42_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3321 & ~matchSet_43[3] & _T_3341 & _T_768 & ~(history_42_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3321 & ~matchSet_43[3] & _T_3341 & _T_768 & ~(history_42_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3354 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3354 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3363 & ~matchSet_44[0] & _T_3365 & _T_768 & ~(history_43_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3363 & ~matchSet_44[0] & _T_3365 & _T_768 & ~(history_43_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3363 & ~matchSet_44[1] & _T_3371 & _T_768 & ~(history_43_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3363 & ~matchSet_44[1] & _T_3371 & _T_768 & ~(history_43_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3363 & ~matchSet_44[2] & _T_3377 & _T_768 & ~(history_43_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3363 & ~matchSet_44[2] & _T_3377 & _T_768 & ~(history_43_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3363 & ~matchSet_44[3] & _T_3383 & _T_768 & ~(history_43_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3363 & ~matchSet_44[3] & _T_3383 & _T_768 & ~(history_43_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3396 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3396 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3405 & ~matchSet_45[0] & _T_3407 & _T_768 & ~(history_44_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3405 & ~matchSet_45[0] & _T_3407 & _T_768 & ~(history_44_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3405 & ~matchSet_45[1] & _T_3413 & _T_768 & ~(history_44_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3405 & ~matchSet_45[1] & _T_3413 & _T_768 & ~(history_44_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3405 & ~matchSet_45[2] & _T_3419 & _T_768 & ~(history_44_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3405 & ~matchSet_45[2] & _T_3419 & _T_768 & ~(history_44_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3405 & ~matchSet_45[3] & _T_3425 & _T_768 & ~(history_44_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3405 & ~matchSet_45[3] & _T_3425 & _T_768 & ~(history_44_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3438 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3438 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3447 & ~matchSet_46[0] & _T_3449 & _T_768 & ~(history_45_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3447 & ~matchSet_46[0] & _T_3449 & _T_768 & ~(history_45_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3447 & ~matchSet_46[1] & _T_3455 & _T_768 & ~(history_45_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3447 & ~matchSet_46[1] & _T_3455 & _T_768 & ~(history_45_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3447 & ~matchSet_46[2] & _T_3461 & _T_768 & ~(history_45_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3447 & ~matchSet_46[2] & _T_3461 & _T_768 & ~(history_45_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3447 & ~matchSet_46[3] & _T_3467 & _T_768 & ~(history_45_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3447 & ~matchSet_46[3] & _T_3467 & _T_768 & ~(history_45_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3480 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3480 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3489 & ~matchSet_47[0] & _T_3491 & _T_768 & ~(history_46_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3489 & ~matchSet_47[0] & _T_3491 & _T_768 & ~(history_46_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3489 & ~matchSet_47[1] & _T_3497 & _T_768 & ~(history_46_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3489 & ~matchSet_47[1] & _T_3497 & _T_768 & ~(history_46_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3489 & ~matchSet_47[2] & _T_3503 & _T_768 & ~(history_46_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3489 & ~matchSet_47[2] & _T_3503 & _T_768 & ~(history_46_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3489 & ~matchSet_47[3] & _T_3509 & _T_768 & ~(history_46_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3489 & ~matchSet_47[3] & _T_3509 & _T_768 & ~(history_46_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3522 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3522 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3531 & ~matchSet_48[0] & _T_3533 & _T_768 & ~(history_47_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3531 & ~matchSet_48[0] & _T_3533 & _T_768 & ~(history_47_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3531 & ~matchSet_48[1] & _T_3539 & _T_768 & ~(history_47_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3531 & ~matchSet_48[1] & _T_3539 & _T_768 & ~(history_47_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3531 & ~matchSet_48[2] & _T_3545 & _T_768 & ~(history_47_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3531 & ~matchSet_48[2] & _T_3545 & _T_768 & ~(history_47_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3531 & ~matchSet_48[3] & _T_3551 & _T_768 & ~(history_47_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3531 & ~matchSet_48[3] & _T_3551 & _T_768 & ~(history_47_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3564 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3564 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3573 & ~matchSet_49[0] & _T_3575 & _T_768 & ~(history_48_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3573 & ~matchSet_49[0] & _T_3575 & _T_768 & ~(history_48_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3573 & ~matchSet_49[1] & _T_3581 & _T_768 & ~(history_48_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3573 & ~matchSet_49[1] & _T_3581 & _T_768 & ~(history_48_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3573 & ~matchSet_49[2] & _T_3587 & _T_768 & ~(history_48_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3573 & ~matchSet_49[2] & _T_3587 & _T_768 & ~(history_48_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3573 & ~matchSet_49[3] & _T_3593 & _T_768 & ~(history_48_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3573 & ~matchSet_49[3] & _T_3593 & _T_768 & ~(history_48_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3606 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3606 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3615 & ~matchSet_50[0] & _T_3617 & _T_768 & ~(history_49_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3615 & ~matchSet_50[0] & _T_3617 & _T_768 & ~(history_49_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3615 & ~matchSet_50[1] & _T_3623 & _T_768 & ~(history_49_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3615 & ~matchSet_50[1] & _T_3623 & _T_768 & ~(history_49_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3615 & ~matchSet_50[2] & _T_3629 & _T_768 & ~(history_49_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3615 & ~matchSet_50[2] & _T_3629 & _T_768 & ~(history_49_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3615 & ~matchSet_50[3] & _T_3635 & _T_768 & ~(history_49_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3615 & ~matchSet_50[3] & _T_3635 & _T_768 & ~(history_49_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3648 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3648 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3657 & ~matchSet_51[0] & _T_3659 & _T_768 & ~(history_50_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3657 & ~matchSet_51[0] & _T_3659 & _T_768 & ~(history_50_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3657 & ~matchSet_51[1] & _T_3665 & _T_768 & ~(history_50_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3657 & ~matchSet_51[1] & _T_3665 & _T_768 & ~(history_50_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3657 & ~matchSet_51[2] & _T_3671 & _T_768 & ~(history_50_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3657 & ~matchSet_51[2] & _T_3671 & _T_768 & ~(history_50_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3657 & ~matchSet_51[3] & _T_3677 & _T_768 & ~(history_50_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3657 & ~matchSet_51[3] & _T_3677 & _T_768 & ~(history_50_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3690 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3690 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3699 & ~matchSet_52[0] & _T_3701 & _T_768 & ~(history_51_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3699 & ~matchSet_52[0] & _T_3701 & _T_768 & ~(history_51_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3699 & ~matchSet_52[1] & _T_3707 & _T_768 & ~(history_51_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3699 & ~matchSet_52[1] & _T_3707 & _T_768 & ~(history_51_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3699 & ~matchSet_52[2] & _T_3713 & _T_768 & ~(history_51_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3699 & ~matchSet_52[2] & _T_3713 & _T_768 & ~(history_51_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3699 & ~matchSet_52[3] & _T_3719 & _T_768 & ~(history_51_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3699 & ~matchSet_52[3] & _T_3719 & _T_768 & ~(history_51_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3732 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3732 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3741 & ~matchSet_53[0] & _T_3743 & _T_768 & ~(history_52_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3741 & ~matchSet_53[0] & _T_3743 & _T_768 & ~(history_52_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3741 & ~matchSet_53[1] & _T_3749 & _T_768 & ~(history_52_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3741 & ~matchSet_53[1] & _T_3749 & _T_768 & ~(history_52_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3741 & ~matchSet_53[2] & _T_3755 & _T_768 & ~(history_52_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3741 & ~matchSet_53[2] & _T_3755 & _T_768 & ~(history_52_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3741 & ~matchSet_53[3] & _T_3761 & _T_768 & ~(history_52_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3741 & ~matchSet_53[3] & _T_3761 & _T_768 & ~(history_52_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3774 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3774 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3783 & ~matchSet_54[0] & _T_3785 & _T_768 & ~(history_53_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3783 & ~matchSet_54[0] & _T_3785 & _T_768 & ~(history_53_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3783 & ~matchSet_54[1] & _T_3791 & _T_768 & ~(history_53_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3783 & ~matchSet_54[1] & _T_3791 & _T_768 & ~(history_53_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3783 & ~matchSet_54[2] & _T_3797 & _T_768 & ~(history_53_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3783 & ~matchSet_54[2] & _T_3797 & _T_768 & ~(history_53_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3783 & ~matchSet_54[3] & _T_3803 & _T_768 & ~(history_53_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3783 & ~matchSet_54[3] & _T_3803 & _T_768 & ~(history_53_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3816 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3816 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3825 & ~matchSet_55[0] & _T_3827 & _T_768 & ~(history_54_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3825 & ~matchSet_55[0] & _T_3827 & _T_768 & ~(history_54_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3825 & ~matchSet_55[1] & _T_3833 & _T_768 & ~(history_54_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3825 & ~matchSet_55[1] & _T_3833 & _T_768 & ~(history_54_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3825 & ~matchSet_55[2] & _T_3839 & _T_768 & ~(history_54_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3825 & ~matchSet_55[2] & _T_3839 & _T_768 & ~(history_54_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3825 & ~matchSet_55[3] & _T_3845 & _T_768 & ~(history_54_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3825 & ~matchSet_55[3] & _T_3845 & _T_768 & ~(history_54_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3858 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3858 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3867 & ~matchSet_56[0] & _T_3869 & _T_768 & ~(history_55_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3867 & ~matchSet_56[0] & _T_3869 & _T_768 & ~(history_55_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3867 & ~matchSet_56[1] & _T_3875 & _T_768 & ~(history_55_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3867 & ~matchSet_56[1] & _T_3875 & _T_768 & ~(history_55_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3867 & ~matchSet_56[2] & _T_3881 & _T_768 & ~(history_55_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3867 & ~matchSet_56[2] & _T_3881 & _T_768 & ~(history_55_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3867 & ~matchSet_56[3] & _T_3887 & _T_768 & ~(history_55_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3867 & ~matchSet_56[3] & _T_3887 & _T_768 & ~(history_55_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3900 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3900 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3909 & ~matchSet_57[0] & _T_3911 & _T_768 & ~(history_56_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3909 & ~matchSet_57[0] & _T_3911 & _T_768 & ~(history_56_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3909 & ~matchSet_57[1] & _T_3917 & _T_768 & ~(history_56_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3909 & ~matchSet_57[1] & _T_3917 & _T_768 & ~(history_56_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3909 & ~matchSet_57[2] & _T_3923 & _T_768 & ~(history_56_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3909 & ~matchSet_57[2] & _T_3923 & _T_768 & ~(history_56_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3909 & ~matchSet_57[3] & _T_3929 & _T_768 & ~(history_56_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3909 & ~matchSet_57[3] & _T_3929 & _T_768 & ~(history_56_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3942 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3942 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3951 & ~matchSet_58[0] & _T_3953 & _T_768 & ~(history_57_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3951 & ~matchSet_58[0] & _T_3953 & _T_768 & ~(history_57_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3951 & ~matchSet_58[1] & _T_3959 & _T_768 & ~(history_57_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3951 & ~matchSet_58[1] & _T_3959 & _T_768 & ~(history_57_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3951 & ~matchSet_58[2] & _T_3965 & _T_768 & ~(history_57_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3951 & ~matchSet_58[2] & _T_3965 & _T_768 & ~(history_57_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3951 & ~matchSet_58[3] & _T_3971 & _T_768 & ~(history_57_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3951 & ~matchSet_58[3] & _T_3971 & _T_768 & ~(history_57_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_3984 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_3984 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3993 & ~matchSet_59[0] & _T_3995 & _T_768 & ~(history_58_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3993 & ~matchSet_59[0] & _T_3995 & _T_768 & ~(history_58_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3993 & ~matchSet_59[1] & _T_4001 & _T_768 & ~(history_58_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3993 & ~matchSet_59[1] & _T_4001 & _T_768 & ~(history_58_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3993 & ~matchSet_59[2] & _T_4007 & _T_768 & ~(history_58_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3993 & ~matchSet_59[2] & _T_4007 & _T_768 & ~(history_58_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_3993 & ~matchSet_59[3] & _T_4013 & _T_768 & ~(history_58_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_3993 & ~matchSet_59[3] & _T_4013 & _T_768 & ~(history_58_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_4026 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_4026 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4035 & ~matchSet_60[0] & _T_4037 & _T_768 & ~(history_59_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4035 & ~matchSet_60[0] & _T_4037 & _T_768 & ~(history_59_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4035 & ~matchSet_60[1] & _T_4043 & _T_768 & ~(history_59_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4035 & ~matchSet_60[1] & _T_4043 & _T_768 & ~(history_59_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4035 & ~matchSet_60[2] & _T_4049 & _T_768 & ~(history_59_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4035 & ~matchSet_60[2] & _T_4049 & _T_768 & ~(history_59_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4035 & ~matchSet_60[3] & _T_4055 & _T_768 & ~(history_59_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4035 & ~matchSet_60[3] & _T_4055 & _T_768 & ~(history_59_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_4068 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_4068 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4077 & ~matchSet_61[0] & _T_4079 & _T_768 & ~(history_60_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4077 & ~matchSet_61[0] & _T_4079 & _T_768 & ~(history_60_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4077 & ~matchSet_61[1] & _T_4085 & _T_768 & ~(history_60_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4077 & ~matchSet_61[1] & _T_4085 & _T_768 & ~(history_60_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4077 & ~matchSet_61[2] & _T_4091 & _T_768 & ~(history_60_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4077 & ~matchSet_61[2] & _T_4091 & _T_768 & ~(history_60_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4077 & ~matchSet_61[3] & _T_4097 & _T_768 & ~(history_60_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4077 & ~matchSet_61[3] & _T_4097 & _T_768 & ~(history_60_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_4110 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_4110 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4119 & ~matchSet_62[0] & _T_4121 & _T_768 & ~(history_61_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4119 & ~matchSet_62[0] & _T_4121 & _T_768 & ~(history_61_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4119 & ~matchSet_62[1] & _T_4127 & _T_768 & ~(history_61_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4119 & ~matchSet_62[1] & _T_4127 & _T_768 & ~(history_61_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4119 & ~matchSet_62[2] & _T_4133 & _T_768 & ~(history_61_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4119 & ~matchSet_62[2] & _T_4133 & _T_768 & ~(history_61_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4119 & ~matchSet_62[3] & _T_4139 & _T_768 & ~(history_61_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4119 & ~matchSet_62[3] & _T_4139 & _T_768 & ~(history_61_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_4152 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_4152 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4161 & ~matchSet_63[0] & _T_4163 & _T_768 & ~(history_62_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4161 & ~matchSet_63[0] & _T_4163 & _T_768 & ~(history_62_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4161 & ~matchSet_63[1] & _T_4169 & _T_768 & ~(history_62_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4161 & ~matchSet_63[1] & _T_4169 & _T_768 & ~(history_62_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4161 & ~matchSet_63[2] & _T_4175 & _T_768 & ~(history_62_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4161 & ~matchSet_63[2] & _T_4175 & _T_768 & ~(history_62_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4161 & ~matchSet_63[3] & _T_4181 & _T_768 & ~(history_62_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4161 & ~matchSet_63[3] & _T_4181 & _T_768 & ~(history_62_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(_T_4194 <= 3'h1)) begin
- $fatal; // @[L1ICache.scala 139:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(_T_4194 <= 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:139 assert(PopCount(matchSet) <= 1.U)\n"); // @[L1ICache.scala 139:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4203 & ~matchSet_64[0] & _T_4205 & _T_768 & ~(history_63_0 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4203 & ~matchSet_64[0] & _T_4205 & _T_768 & ~(history_63_0 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4203 & ~matchSet_64[1] & _T_4211 & _T_768 & ~(history_63_1 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4203 & ~matchSet_64[1] & _T_4211 & _T_768 & ~(history_63_1 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4203 & ~matchSet_64[2] & _T_4217 & _T_768 & ~(history_63_2 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4203 & ~matchSet_64[2] & _T_4217 & _T_768 & ~(history_63_2 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_4203 & ~matchSet_64[3] & _T_4223 & _T_768 & ~(history_63_3 > 2'h0)) begin
- $fatal; // @[L1ICache.scala 155:17]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_4203 & ~matchSet_64[3] & _T_4223 & _T_768 & ~(history_63_3 > 2'h0)) begin
- $fwrite(32'h80000002,"Assertion failed\n at L1ICache.scala:155 assert(history(i)(j) > 0.U)\n"); // @[L1ICache.scala 155:17]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(~(addrLatchActive & ~io_ibus_valid))) begin
- $fatal; // @[L1ICache.scala 254:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(~(addrLatchActive & ~io_ibus_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1ICache.scala:254 assert(!(addrLatchActive && !io.ibus.valid))\n"); // @[L1ICache.scala 254:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_768 & ~(~(addrLatchActive & addrLatchData != io_ibus_addr))) begin
- $fatal; // @[L1ICache.scala 255:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_768 & ~(~(addrLatchActive & addrLatchData != io_ibus_addr))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at L1ICache.scala:255 assert(!(addrLatchActive && addrLatchData =/= io.ibus.addr))\n"
- ); // @[L1ICache.scala 255:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_0 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_0 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h0 == replaceId) begin
- valid_0 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_0 <= _GEN_1541;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_1 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_1 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h1 == replaceId) begin
- valid_1 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_1 <= _GEN_1542;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_2 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_2 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h2 == replaceId) begin
- valid_2 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_2 <= _GEN_1543;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_3 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_3 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h3 == replaceId) begin
- valid_3 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_3 <= _GEN_1544;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_4 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_4 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h4 == replaceId) begin
- valid_4 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_4 <= _GEN_1545;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_5 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_5 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h5 == replaceId) begin
- valid_5 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_5 <= _GEN_1546;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_6 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_6 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h6 == replaceId) begin
- valid_6 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_6 <= _GEN_1547;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_7 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_7 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h7 == replaceId) begin
- valid_7 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_7 <= _GEN_1548;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_8 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_8 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h8 == replaceId) begin
- valid_8 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_8 <= _GEN_1549;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_9 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_9 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h9 == replaceId) begin
- valid_9 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_9 <= _GEN_1550;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_10 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_10 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'ha == replaceId) begin
- valid_10 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_10 <= _GEN_1551;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_11 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_11 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hb == replaceId) begin
- valid_11 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_11 <= _GEN_1552;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_12 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_12 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hc == replaceId) begin
- valid_12 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_12 <= _GEN_1553;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_13 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_13 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hd == replaceId) begin
- valid_13 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_13 <= _GEN_1554;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_14 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_14 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'he == replaceId) begin
- valid_14 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_14 <= _GEN_1555;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_15 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_15 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hf == replaceId) begin
- valid_15 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_15 <= _GEN_1556;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_16 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_16 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h10 == replaceId) begin
- valid_16 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_16 <= _GEN_1557;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_17 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_17 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h11 == replaceId) begin
- valid_17 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_17 <= _GEN_1558;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_18 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_18 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h12 == replaceId) begin
- valid_18 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_18 <= _GEN_1559;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_19 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_19 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h13 == replaceId) begin
- valid_19 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_19 <= _GEN_1560;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_20 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_20 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h14 == replaceId) begin
- valid_20 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_20 <= _GEN_1561;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_21 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_21 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h15 == replaceId) begin
- valid_21 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_21 <= _GEN_1562;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_22 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_22 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h16 == replaceId) begin
- valid_22 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_22 <= _GEN_1563;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_23 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_23 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h17 == replaceId) begin
- valid_23 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_23 <= _GEN_1564;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_24 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_24 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h18 == replaceId) begin
- valid_24 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_24 <= _GEN_1565;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_25 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_25 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h19 == replaceId) begin
- valid_25 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_25 <= _GEN_1566;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_26 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_26 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h1a == replaceId) begin
- valid_26 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_26 <= _GEN_1567;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_27 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_27 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h1b == replaceId) begin
- valid_27 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_27 <= _GEN_1568;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_28 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_28 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h1c == replaceId) begin
- valid_28 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_28 <= _GEN_1569;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_29 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_29 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h1d == replaceId) begin
- valid_29 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_29 <= _GEN_1570;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_30 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_30 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h1e == replaceId) begin
- valid_30 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_30 <= _GEN_1571;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_31 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_31 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h1f == replaceId) begin
- valid_31 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_31 <= _GEN_1572;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_32 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_32 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h20 == replaceId) begin
- valid_32 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_32 <= _GEN_1573;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_33 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_33 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h21 == replaceId) begin
- valid_33 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_33 <= _GEN_1574;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_34 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_34 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h22 == replaceId) begin
- valid_34 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_34 <= _GEN_1575;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_35 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_35 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h23 == replaceId) begin
- valid_35 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_35 <= _GEN_1576;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_36 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_36 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h24 == replaceId) begin
- valid_36 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_36 <= _GEN_1577;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_37 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_37 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h25 == replaceId) begin
- valid_37 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_37 <= _GEN_1578;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_38 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_38 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h26 == replaceId) begin
- valid_38 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_38 <= _GEN_1579;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_39 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_39 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h27 == replaceId) begin
- valid_39 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_39 <= _GEN_1580;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_40 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_40 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h28 == replaceId) begin
- valid_40 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_40 <= _GEN_1581;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_41 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_41 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h29 == replaceId) begin
- valid_41 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_41 <= _GEN_1582;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_42 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_42 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h2a == replaceId) begin
- valid_42 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_42 <= _GEN_1583;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_43 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_43 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h2b == replaceId) begin
- valid_43 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_43 <= _GEN_1584;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_44 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_44 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h2c == replaceId) begin
- valid_44 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_44 <= _GEN_1585;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_45 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_45 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h2d == replaceId) begin
- valid_45 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_45 <= _GEN_1586;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_46 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_46 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h2e == replaceId) begin
- valid_46 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_46 <= _GEN_1587;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_47 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_47 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h2f == replaceId) begin
- valid_47 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_47 <= _GEN_1588;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_48 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_48 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h30 == replaceId) begin
- valid_48 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_48 <= _GEN_1589;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_49 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_49 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h31 == replaceId) begin
- valid_49 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_49 <= _GEN_1590;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_50 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_50 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h32 == replaceId) begin
- valid_50 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_50 <= _GEN_1591;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_51 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_51 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h33 == replaceId) begin
- valid_51 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_51 <= _GEN_1592;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_52 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_52 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h34 == replaceId) begin
- valid_52 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_52 <= _GEN_1593;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_53 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_53 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h35 == replaceId) begin
- valid_53 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_53 <= _GEN_1594;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_54 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_54 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h36 == replaceId) begin
- valid_54 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_54 <= _GEN_1595;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_55 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_55 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h37 == replaceId) begin
- valid_55 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_55 <= _GEN_1596;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_56 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_56 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h38 == replaceId) begin
- valid_56 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_56 <= _GEN_1597;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_57 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_57 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h39 == replaceId) begin
- valid_57 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_57 <= _GEN_1598;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_58 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_58 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h3a == replaceId) begin
- valid_58 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_58 <= _GEN_1599;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_59 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_59 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h3b == replaceId) begin
- valid_59 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_59 <= _GEN_1600;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_60 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_60 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h3c == replaceId) begin
- valid_60 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_60 <= _GEN_1601;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_61 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_61 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h3d == replaceId) begin
- valid_61 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_61 <= _GEN_1602;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_62 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_62 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h3e == replaceId) begin
- valid_62 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_62 <= _GEN_1603;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_63 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_63 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h3f == replaceId) begin
- valid_63 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_63 <= _GEN_1604;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_64 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_64 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h40 == replaceId) begin
- valid_64 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_64 <= _GEN_1605;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_65 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_65 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h41 == replaceId) begin
- valid_65 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_65 <= _GEN_1606;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_66 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_66 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h42 == replaceId) begin
- valid_66 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_66 <= _GEN_1607;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_67 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_67 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h43 == replaceId) begin
- valid_67 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_67 <= _GEN_1608;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_68 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_68 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h44 == replaceId) begin
- valid_68 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_68 <= _GEN_1609;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_69 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_69 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h45 == replaceId) begin
- valid_69 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_69 <= _GEN_1610;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_70 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_70 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h46 == replaceId) begin
- valid_70 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_70 <= _GEN_1611;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_71 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_71 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h47 == replaceId) begin
- valid_71 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_71 <= _GEN_1612;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_72 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_72 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h48 == replaceId) begin
- valid_72 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_72 <= _GEN_1613;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_73 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_73 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h49 == replaceId) begin
- valid_73 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_73 <= _GEN_1614;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_74 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_74 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h4a == replaceId) begin
- valid_74 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_74 <= _GEN_1615;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_75 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_75 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h4b == replaceId) begin
- valid_75 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_75 <= _GEN_1616;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_76 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_76 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h4c == replaceId) begin
- valid_76 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_76 <= _GEN_1617;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_77 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_77 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h4d == replaceId) begin
- valid_77 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_77 <= _GEN_1618;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_78 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_78 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h4e == replaceId) begin
- valid_78 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_78 <= _GEN_1619;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_79 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_79 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h4f == replaceId) begin
- valid_79 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_79 <= _GEN_1620;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_80 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_80 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h50 == replaceId) begin
- valid_80 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_80 <= _GEN_1621;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_81 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_81 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h51 == replaceId) begin
- valid_81 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_81 <= _GEN_1622;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_82 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_82 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h52 == replaceId) begin
- valid_82 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_82 <= _GEN_1623;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_83 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_83 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h53 == replaceId) begin
- valid_83 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_83 <= _GEN_1624;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_84 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_84 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h54 == replaceId) begin
- valid_84 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_84 <= _GEN_1625;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_85 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_85 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h55 == replaceId) begin
- valid_85 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_85 <= _GEN_1626;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_86 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_86 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h56 == replaceId) begin
- valid_86 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_86 <= _GEN_1627;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_87 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_87 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h57 == replaceId) begin
- valid_87 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_87 <= _GEN_1628;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_88 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_88 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h58 == replaceId) begin
- valid_88 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_88 <= _GEN_1629;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_89 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_89 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h59 == replaceId) begin
- valid_89 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_89 <= _GEN_1630;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_90 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_90 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h5a == replaceId) begin
- valid_90 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_90 <= _GEN_1631;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_91 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_91 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h5b == replaceId) begin
- valid_91 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_91 <= _GEN_1632;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_92 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_92 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h5c == replaceId) begin
- valid_92 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_92 <= _GEN_1633;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_93 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_93 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h5d == replaceId) begin
- valid_93 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_93 <= _GEN_1634;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_94 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_94 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h5e == replaceId) begin
- valid_94 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_94 <= _GEN_1635;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_95 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_95 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h5f == replaceId) begin
- valid_95 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_95 <= _GEN_1636;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_96 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_96 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h60 == replaceId) begin
- valid_96 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_96 <= _GEN_1637;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_97 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_97 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h61 == replaceId) begin
- valid_97 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_97 <= _GEN_1638;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_98 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_98 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h62 == replaceId) begin
- valid_98 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_98 <= _GEN_1639;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_99 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_99 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h63 == replaceId) begin
- valid_99 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_99 <= _GEN_1640;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_100 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_100 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h64 == replaceId) begin
- valid_100 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_100 <= _GEN_1641;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_101 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_101 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h65 == replaceId) begin
- valid_101 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_101 <= _GEN_1642;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_102 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_102 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h66 == replaceId) begin
- valid_102 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_102 <= _GEN_1643;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_103 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_103 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h67 == replaceId) begin
- valid_103 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_103 <= _GEN_1644;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_104 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_104 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h68 == replaceId) begin
- valid_104 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_104 <= _GEN_1645;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_105 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_105 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h69 == replaceId) begin
- valid_105 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_105 <= _GEN_1646;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_106 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_106 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h6a == replaceId) begin
- valid_106 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_106 <= _GEN_1647;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_107 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_107 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h6b == replaceId) begin
- valid_107 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_107 <= _GEN_1648;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_108 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_108 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h6c == replaceId) begin
- valid_108 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_108 <= _GEN_1649;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_109 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_109 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h6d == replaceId) begin
- valid_109 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_109 <= _GEN_1650;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_110 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_110 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h6e == replaceId) begin
- valid_110 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_110 <= _GEN_1651;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_111 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_111 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h6f == replaceId) begin
- valid_111 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_111 <= _GEN_1652;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_112 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_112 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h70 == replaceId) begin
- valid_112 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_112 <= _GEN_1653;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_113 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_113 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h71 == replaceId) begin
- valid_113 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_113 <= _GEN_1654;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_114 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_114 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h72 == replaceId) begin
- valid_114 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_114 <= _GEN_1655;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_115 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_115 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h73 == replaceId) begin
- valid_115 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_115 <= _GEN_1656;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_116 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_116 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h74 == replaceId) begin
- valid_116 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_116 <= _GEN_1657;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_117 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_117 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h75 == replaceId) begin
- valid_117 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_117 <= _GEN_1658;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_118 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_118 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h76 == replaceId) begin
- valid_118 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_118 <= _GEN_1659;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_119 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_119 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h77 == replaceId) begin
- valid_119 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_119 <= _GEN_1660;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_120 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_120 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h78 == replaceId) begin
- valid_120 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_120 <= _GEN_1661;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_121 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_121 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h79 == replaceId) begin
- valid_121 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_121 <= _GEN_1662;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_122 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_122 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h7a == replaceId) begin
- valid_122 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_122 <= _GEN_1663;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_123 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_123 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h7b == replaceId) begin
- valid_123 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_123 <= _GEN_1664;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_124 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_124 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h7c == replaceId) begin
- valid_124 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_124 <= _GEN_1665;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_125 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_125 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h7d == replaceId) begin
- valid_125 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_125 <= _GEN_1666;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_126 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_126 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h7e == replaceId) begin
- valid_126 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_126 <= _GEN_1667;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_127 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_127 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h7f == replaceId) begin
- valid_127 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_127 <= _GEN_1668;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_128 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_128 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h80 == replaceId) begin
- valid_128 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_128 <= _GEN_1669;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_129 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_129 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h81 == replaceId) begin
- valid_129 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_129 <= _GEN_1670;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_130 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_130 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h82 == replaceId) begin
- valid_130 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_130 <= _GEN_1671;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_131 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_131 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h83 == replaceId) begin
- valid_131 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_131 <= _GEN_1672;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_132 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_132 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h84 == replaceId) begin
- valid_132 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_132 <= _GEN_1673;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_133 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_133 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h85 == replaceId) begin
- valid_133 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_133 <= _GEN_1674;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_134 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_134 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h86 == replaceId) begin
- valid_134 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_134 <= _GEN_1675;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_135 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_135 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h87 == replaceId) begin
- valid_135 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_135 <= _GEN_1676;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_136 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_136 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h88 == replaceId) begin
- valid_136 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_136 <= _GEN_1677;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_137 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_137 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h89 == replaceId) begin
- valid_137 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_137 <= _GEN_1678;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_138 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_138 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h8a == replaceId) begin
- valid_138 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_138 <= _GEN_1679;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_139 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_139 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h8b == replaceId) begin
- valid_139 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_139 <= _GEN_1680;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_140 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_140 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h8c == replaceId) begin
- valid_140 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_140 <= _GEN_1681;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_141 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_141 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h8d == replaceId) begin
- valid_141 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_141 <= _GEN_1682;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_142 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_142 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h8e == replaceId) begin
- valid_142 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_142 <= _GEN_1683;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_143 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_143 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h8f == replaceId) begin
- valid_143 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_143 <= _GEN_1684;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_144 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_144 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h90 == replaceId) begin
- valid_144 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_144 <= _GEN_1685;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_145 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_145 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h91 == replaceId) begin
- valid_145 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_145 <= _GEN_1686;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_146 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_146 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h92 == replaceId) begin
- valid_146 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_146 <= _GEN_1687;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_147 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_147 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h93 == replaceId) begin
- valid_147 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_147 <= _GEN_1688;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_148 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_148 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h94 == replaceId) begin
- valid_148 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_148 <= _GEN_1689;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_149 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_149 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h95 == replaceId) begin
- valid_149 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_149 <= _GEN_1690;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_150 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_150 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h96 == replaceId) begin
- valid_150 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_150 <= _GEN_1691;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_151 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_151 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h97 == replaceId) begin
- valid_151 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_151 <= _GEN_1692;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_152 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_152 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h98 == replaceId) begin
- valid_152 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_152 <= _GEN_1693;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_153 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_153 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h99 == replaceId) begin
- valid_153 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_153 <= _GEN_1694;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_154 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_154 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h9a == replaceId) begin
- valid_154 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_154 <= _GEN_1695;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_155 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_155 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h9b == replaceId) begin
- valid_155 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_155 <= _GEN_1696;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_156 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_156 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h9c == replaceId) begin
- valid_156 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_156 <= _GEN_1697;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_157 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_157 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h9d == replaceId) begin
- valid_157 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_157 <= _GEN_1698;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_158 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_158 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h9e == replaceId) begin
- valid_158 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_158 <= _GEN_1699;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_159 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_159 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'h9f == replaceId) begin
- valid_159 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_159 <= _GEN_1700;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_160 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_160 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'ha0 == replaceId) begin
- valid_160 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_160 <= _GEN_1701;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_161 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_161 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'ha1 == replaceId) begin
- valid_161 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_161 <= _GEN_1702;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_162 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_162 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'ha2 == replaceId) begin
- valid_162 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_162 <= _GEN_1703;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_163 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_163 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'ha3 == replaceId) begin
- valid_163 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_163 <= _GEN_1704;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_164 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_164 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'ha4 == replaceId) begin
- valid_164 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_164 <= _GEN_1705;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_165 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_165 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'ha5 == replaceId) begin
- valid_165 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_165 <= _GEN_1706;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_166 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_166 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'ha6 == replaceId) begin
- valid_166 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_166 <= _GEN_1707;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_167 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_167 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'ha7 == replaceId) begin
- valid_167 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_167 <= _GEN_1708;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_168 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_168 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'ha8 == replaceId) begin
- valid_168 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_168 <= _GEN_1709;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_169 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_169 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'ha9 == replaceId) begin
- valid_169 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_169 <= _GEN_1710;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_170 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_170 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'haa == replaceId) begin
- valid_170 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_170 <= _GEN_1711;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_171 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_171 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hab == replaceId) begin
- valid_171 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_171 <= _GEN_1712;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_172 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_172 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hac == replaceId) begin
- valid_172 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_172 <= _GEN_1713;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_173 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_173 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'had == replaceId) begin
- valid_173 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_173 <= _GEN_1714;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_174 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_174 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hae == replaceId) begin
- valid_174 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_174 <= _GEN_1715;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_175 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_175 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'haf == replaceId) begin
- valid_175 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_175 <= _GEN_1716;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_176 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_176 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hb0 == replaceId) begin
- valid_176 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_176 <= _GEN_1717;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_177 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_177 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hb1 == replaceId) begin
- valid_177 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_177 <= _GEN_1718;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_178 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_178 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hb2 == replaceId) begin
- valid_178 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_178 <= _GEN_1719;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_179 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_179 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hb3 == replaceId) begin
- valid_179 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_179 <= _GEN_1720;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_180 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_180 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hb4 == replaceId) begin
- valid_180 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_180 <= _GEN_1721;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_181 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_181 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hb5 == replaceId) begin
- valid_181 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_181 <= _GEN_1722;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_182 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_182 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hb6 == replaceId) begin
- valid_182 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_182 <= _GEN_1723;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_183 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_183 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hb7 == replaceId) begin
- valid_183 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_183 <= _GEN_1724;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_184 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_184 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hb8 == replaceId) begin
- valid_184 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_184 <= _GEN_1725;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_185 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_185 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hb9 == replaceId) begin
- valid_185 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_185 <= _GEN_1726;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_186 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_186 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hba == replaceId) begin
- valid_186 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_186 <= _GEN_1727;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_187 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_187 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hbb == replaceId) begin
- valid_187 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_187 <= _GEN_1728;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_188 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_188 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hbc == replaceId) begin
- valid_188 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_188 <= _GEN_1729;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_189 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_189 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hbd == replaceId) begin
- valid_189 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_189 <= _GEN_1730;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_190 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_190 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hbe == replaceId) begin
- valid_190 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_190 <= _GEN_1731;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_191 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_191 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hbf == replaceId) begin
- valid_191 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_191 <= _GEN_1732;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_192 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_192 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hc0 == replaceId) begin
- valid_192 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_192 <= _GEN_1733;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_193 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_193 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hc1 == replaceId) begin
- valid_193 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_193 <= _GEN_1734;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_194 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_194 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hc2 == replaceId) begin
- valid_194 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_194 <= _GEN_1735;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_195 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_195 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hc3 == replaceId) begin
- valid_195 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_195 <= _GEN_1736;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_196 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_196 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hc4 == replaceId) begin
- valid_196 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_196 <= _GEN_1737;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_197 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_197 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hc5 == replaceId) begin
- valid_197 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_197 <= _GEN_1738;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_198 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_198 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hc6 == replaceId) begin
- valid_198 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_198 <= _GEN_1739;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_199 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_199 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hc7 == replaceId) begin
- valid_199 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_199 <= _GEN_1740;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_200 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_200 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hc8 == replaceId) begin
- valid_200 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_200 <= _GEN_1741;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_201 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_201 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hc9 == replaceId) begin
- valid_201 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_201 <= _GEN_1742;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_202 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_202 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hca == replaceId) begin
- valid_202 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_202 <= _GEN_1743;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_203 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_203 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hcb == replaceId) begin
- valid_203 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_203 <= _GEN_1744;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_204 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_204 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hcc == replaceId) begin
- valid_204 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_204 <= _GEN_1745;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_205 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_205 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hcd == replaceId) begin
- valid_205 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_205 <= _GEN_1746;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_206 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_206 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hce == replaceId) begin
- valid_206 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_206 <= _GEN_1747;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_207 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_207 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hcf == replaceId) begin
- valid_207 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_207 <= _GEN_1748;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_208 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_208 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hd0 == replaceId) begin
- valid_208 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_208 <= _GEN_1749;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_209 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_209 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hd1 == replaceId) begin
- valid_209 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_209 <= _GEN_1750;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_210 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_210 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hd2 == replaceId) begin
- valid_210 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_210 <= _GEN_1751;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_211 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_211 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hd3 == replaceId) begin
- valid_211 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_211 <= _GEN_1752;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_212 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_212 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hd4 == replaceId) begin
- valid_212 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_212 <= _GEN_1753;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_213 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_213 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hd5 == replaceId) begin
- valid_213 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_213 <= _GEN_1754;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_214 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_214 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hd6 == replaceId) begin
- valid_214 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_214 <= _GEN_1755;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_215 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_215 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hd7 == replaceId) begin
- valid_215 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_215 <= _GEN_1756;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_216 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_216 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hd8 == replaceId) begin
- valid_216 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_216 <= _GEN_1757;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_217 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_217 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hd9 == replaceId) begin
- valid_217 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_217 <= _GEN_1758;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_218 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_218 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hda == replaceId) begin
- valid_218 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_218 <= _GEN_1759;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_219 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_219 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hdb == replaceId) begin
- valid_219 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_219 <= _GEN_1760;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_220 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_220 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hdc == replaceId) begin
- valid_220 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_220 <= _GEN_1761;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_221 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_221 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hdd == replaceId) begin
- valid_221 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_221 <= _GEN_1762;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_222 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_222 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hde == replaceId) begin
- valid_222 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_222 <= _GEN_1763;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_223 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_223 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hdf == replaceId) begin
- valid_223 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_223 <= _GEN_1764;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_224 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_224 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'he0 == replaceId) begin
- valid_224 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_224 <= _GEN_1765;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_225 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_225 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'he1 == replaceId) begin
- valid_225 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_225 <= _GEN_1766;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_226 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_226 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'he2 == replaceId) begin
- valid_226 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_226 <= _GEN_1767;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_227 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_227 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'he3 == replaceId) begin
- valid_227 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_227 <= _GEN_1768;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_228 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_228 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'he4 == replaceId) begin
- valid_228 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_228 <= _GEN_1769;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_229 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_229 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'he5 == replaceId) begin
- valid_229 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_229 <= _GEN_1770;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_230 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_230 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'he6 == replaceId) begin
- valid_230 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_230 <= _GEN_1771;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_231 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_231 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'he7 == replaceId) begin
- valid_231 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_231 <= _GEN_1772;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_232 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_232 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'he8 == replaceId) begin
- valid_232 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_232 <= _GEN_1773;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_233 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_233 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'he9 == replaceId) begin
- valid_233 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_233 <= _GEN_1774;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_234 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_234 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hea == replaceId) begin
- valid_234 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_234 <= _GEN_1775;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_235 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_235 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'heb == replaceId) begin
- valid_235 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_235 <= _GEN_1776;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_236 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_236 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hec == replaceId) begin
- valid_236 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_236 <= _GEN_1777;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_237 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_237 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hed == replaceId) begin
- valid_237 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_237 <= _GEN_1778;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_238 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_238 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hee == replaceId) begin
- valid_238 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_238 <= _GEN_1779;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_239 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_239 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hef == replaceId) begin
- valid_239 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_239 <= _GEN_1780;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_240 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_240 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hf0 == replaceId) begin
- valid_240 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_240 <= _GEN_1781;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_241 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_241 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hf1 == replaceId) begin
- valid_241 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_241 <= _GEN_1782;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_242 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_242 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hf2 == replaceId) begin
- valid_242 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_242 <= _GEN_1783;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_243 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_243 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hf3 == replaceId) begin
- valid_243 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_243 <= _GEN_1784;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_244 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_244 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hf4 == replaceId) begin
- valid_244 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_244 <= _GEN_1785;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_245 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_245 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hf5 == replaceId) begin
- valid_245 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_245 <= _GEN_1786;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_246 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_246 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hf6 == replaceId) begin
- valid_246 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_246 <= _GEN_1787;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_247 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_247 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hf7 == replaceId) begin
- valid_247 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_247 <= _GEN_1788;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_248 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_248 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hf8 == replaceId) begin
- valid_248 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_248 <= _GEN_1789;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_249 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_249 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hf9 == replaceId) begin
- valid_249 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_249 <= _GEN_1790;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_250 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_250 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hfa == replaceId) begin
- valid_250 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_250 <= _GEN_1791;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_251 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_251 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hfb == replaceId) begin
- valid_251 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_251 <= _GEN_1792;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_252 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_252 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hfc == replaceId) begin
- valid_252 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_252 <= _GEN_1793;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_253 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_253 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hfd == replaceId) begin
- valid_253 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_253 <= _GEN_1794;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_254 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_254 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hfe == replaceId) begin
- valid_254 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_254 <= _GEN_1795;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 215:25]
- valid_255 <= 1'h0; // @[L1ICache.scala 217:16]
- end else if (io_flush_valid) begin // @[L1ICache.scala 219:75]
- valid_255 <= 1'h0; // @[L1ICache.scala 220:{22,22} 72:22]
- end else if (_T_4234) begin // @[L1ICache.scala 221:66]
- if (8'hff == replaceId) begin
- valid_255 <= 1'h0;
- end
- end else if (_T_4242) begin // @[L1ICache.scala 72:22]
- valid_255 <= _GEN_1796;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 203:59]
- axivalid <= 1'h0; // @[L1ICache.scala 204:14]
- end else if (io_axi_read_addr_valid & io_axi_read_addr_ready) begin
- axivalid <= 1'h0;
- end else begin
- axivalid <= _GEN_1281;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 209:59]
- axiready <= 1'h0; // @[L1ICache.scala 210:14]
- end else if (io_axi_read_data_valid & io_axi_read_data_ready) begin
- axiready <= 1'h0;
- end else begin
- axiready <= _GEN_1283;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[L1ICache.scala 245:25]
- addrLatchActive <= 1'h0; // @[L1ICache.scala 246:21]
- end else if (io_flush_valid) begin
- addrLatchActive <= 1'h0;
- end else begin
- addrLatchActive <= _GEN_3080;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- valid_0 = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- valid_1 = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- valid_2 = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- valid_3 = _RAND_3[0:0];
- _RAND_4 = {1{`RANDOM}};
- valid_4 = _RAND_4[0:0];
- _RAND_5 = {1{`RANDOM}};
- valid_5 = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- valid_6 = _RAND_6[0:0];
- _RAND_7 = {1{`RANDOM}};
- valid_7 = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- valid_8 = _RAND_8[0:0];
- _RAND_9 = {1{`RANDOM}};
- valid_9 = _RAND_9[0:0];
- _RAND_10 = {1{`RANDOM}};
- valid_10 = _RAND_10[0:0];
- _RAND_11 = {1{`RANDOM}};
- valid_11 = _RAND_11[0:0];
- _RAND_12 = {1{`RANDOM}};
- valid_12 = _RAND_12[0:0];
- _RAND_13 = {1{`RANDOM}};
- valid_13 = _RAND_13[0:0];
- _RAND_14 = {1{`RANDOM}};
- valid_14 = _RAND_14[0:0];
- _RAND_15 = {1{`RANDOM}};
- valid_15 = _RAND_15[0:0];
- _RAND_16 = {1{`RANDOM}};
- valid_16 = _RAND_16[0:0];
- _RAND_17 = {1{`RANDOM}};
- valid_17 = _RAND_17[0:0];
- _RAND_18 = {1{`RANDOM}};
- valid_18 = _RAND_18[0:0];
- _RAND_19 = {1{`RANDOM}};
- valid_19 = _RAND_19[0:0];
- _RAND_20 = {1{`RANDOM}};
- valid_20 = _RAND_20[0:0];
- _RAND_21 = {1{`RANDOM}};
- valid_21 = _RAND_21[0:0];
- _RAND_22 = {1{`RANDOM}};
- valid_22 = _RAND_22[0:0];
- _RAND_23 = {1{`RANDOM}};
- valid_23 = _RAND_23[0:0];
- _RAND_24 = {1{`RANDOM}};
- valid_24 = _RAND_24[0:0];
- _RAND_25 = {1{`RANDOM}};
- valid_25 = _RAND_25[0:0];
- _RAND_26 = {1{`RANDOM}};
- valid_26 = _RAND_26[0:0];
- _RAND_27 = {1{`RANDOM}};
- valid_27 = _RAND_27[0:0];
- _RAND_28 = {1{`RANDOM}};
- valid_28 = _RAND_28[0:0];
- _RAND_29 = {1{`RANDOM}};
- valid_29 = _RAND_29[0:0];
- _RAND_30 = {1{`RANDOM}};
- valid_30 = _RAND_30[0:0];
- _RAND_31 = {1{`RANDOM}};
- valid_31 = _RAND_31[0:0];
- _RAND_32 = {1{`RANDOM}};
- valid_32 = _RAND_32[0:0];
- _RAND_33 = {1{`RANDOM}};
- valid_33 = _RAND_33[0:0];
- _RAND_34 = {1{`RANDOM}};
- valid_34 = _RAND_34[0:0];
- _RAND_35 = {1{`RANDOM}};
- valid_35 = _RAND_35[0:0];
- _RAND_36 = {1{`RANDOM}};
- valid_36 = _RAND_36[0:0];
- _RAND_37 = {1{`RANDOM}};
- valid_37 = _RAND_37[0:0];
- _RAND_38 = {1{`RANDOM}};
- valid_38 = _RAND_38[0:0];
- _RAND_39 = {1{`RANDOM}};
- valid_39 = _RAND_39[0:0];
- _RAND_40 = {1{`RANDOM}};
- valid_40 = _RAND_40[0:0];
- _RAND_41 = {1{`RANDOM}};
- valid_41 = _RAND_41[0:0];
- _RAND_42 = {1{`RANDOM}};
- valid_42 = _RAND_42[0:0];
- _RAND_43 = {1{`RANDOM}};
- valid_43 = _RAND_43[0:0];
- _RAND_44 = {1{`RANDOM}};
- valid_44 = _RAND_44[0:0];
- _RAND_45 = {1{`RANDOM}};
- valid_45 = _RAND_45[0:0];
- _RAND_46 = {1{`RANDOM}};
- valid_46 = _RAND_46[0:0];
- _RAND_47 = {1{`RANDOM}};
- valid_47 = _RAND_47[0:0];
- _RAND_48 = {1{`RANDOM}};
- valid_48 = _RAND_48[0:0];
- _RAND_49 = {1{`RANDOM}};
- valid_49 = _RAND_49[0:0];
- _RAND_50 = {1{`RANDOM}};
- valid_50 = _RAND_50[0:0];
- _RAND_51 = {1{`RANDOM}};
- valid_51 = _RAND_51[0:0];
- _RAND_52 = {1{`RANDOM}};
- valid_52 = _RAND_52[0:0];
- _RAND_53 = {1{`RANDOM}};
- valid_53 = _RAND_53[0:0];
- _RAND_54 = {1{`RANDOM}};
- valid_54 = _RAND_54[0:0];
- _RAND_55 = {1{`RANDOM}};
- valid_55 = _RAND_55[0:0];
- _RAND_56 = {1{`RANDOM}};
- valid_56 = _RAND_56[0:0];
- _RAND_57 = {1{`RANDOM}};
- valid_57 = _RAND_57[0:0];
- _RAND_58 = {1{`RANDOM}};
- valid_58 = _RAND_58[0:0];
- _RAND_59 = {1{`RANDOM}};
- valid_59 = _RAND_59[0:0];
- _RAND_60 = {1{`RANDOM}};
- valid_60 = _RAND_60[0:0];
- _RAND_61 = {1{`RANDOM}};
- valid_61 = _RAND_61[0:0];
- _RAND_62 = {1{`RANDOM}};
- valid_62 = _RAND_62[0:0];
- _RAND_63 = {1{`RANDOM}};
- valid_63 = _RAND_63[0:0];
- _RAND_64 = {1{`RANDOM}};
- valid_64 = _RAND_64[0:0];
- _RAND_65 = {1{`RANDOM}};
- valid_65 = _RAND_65[0:0];
- _RAND_66 = {1{`RANDOM}};
- valid_66 = _RAND_66[0:0];
- _RAND_67 = {1{`RANDOM}};
- valid_67 = _RAND_67[0:0];
- _RAND_68 = {1{`RANDOM}};
- valid_68 = _RAND_68[0:0];
- _RAND_69 = {1{`RANDOM}};
- valid_69 = _RAND_69[0:0];
- _RAND_70 = {1{`RANDOM}};
- valid_70 = _RAND_70[0:0];
- _RAND_71 = {1{`RANDOM}};
- valid_71 = _RAND_71[0:0];
- _RAND_72 = {1{`RANDOM}};
- valid_72 = _RAND_72[0:0];
- _RAND_73 = {1{`RANDOM}};
- valid_73 = _RAND_73[0:0];
- _RAND_74 = {1{`RANDOM}};
- valid_74 = _RAND_74[0:0];
- _RAND_75 = {1{`RANDOM}};
- valid_75 = _RAND_75[0:0];
- _RAND_76 = {1{`RANDOM}};
- valid_76 = _RAND_76[0:0];
- _RAND_77 = {1{`RANDOM}};
- valid_77 = _RAND_77[0:0];
- _RAND_78 = {1{`RANDOM}};
- valid_78 = _RAND_78[0:0];
- _RAND_79 = {1{`RANDOM}};
- valid_79 = _RAND_79[0:0];
- _RAND_80 = {1{`RANDOM}};
- valid_80 = _RAND_80[0:0];
- _RAND_81 = {1{`RANDOM}};
- valid_81 = _RAND_81[0:0];
- _RAND_82 = {1{`RANDOM}};
- valid_82 = _RAND_82[0:0];
- _RAND_83 = {1{`RANDOM}};
- valid_83 = _RAND_83[0:0];
- _RAND_84 = {1{`RANDOM}};
- valid_84 = _RAND_84[0:0];
- _RAND_85 = {1{`RANDOM}};
- valid_85 = _RAND_85[0:0];
- _RAND_86 = {1{`RANDOM}};
- valid_86 = _RAND_86[0:0];
- _RAND_87 = {1{`RANDOM}};
- valid_87 = _RAND_87[0:0];
- _RAND_88 = {1{`RANDOM}};
- valid_88 = _RAND_88[0:0];
- _RAND_89 = {1{`RANDOM}};
- valid_89 = _RAND_89[0:0];
- _RAND_90 = {1{`RANDOM}};
- valid_90 = _RAND_90[0:0];
- _RAND_91 = {1{`RANDOM}};
- valid_91 = _RAND_91[0:0];
- _RAND_92 = {1{`RANDOM}};
- valid_92 = _RAND_92[0:0];
- _RAND_93 = {1{`RANDOM}};
- valid_93 = _RAND_93[0:0];
- _RAND_94 = {1{`RANDOM}};
- valid_94 = _RAND_94[0:0];
- _RAND_95 = {1{`RANDOM}};
- valid_95 = _RAND_95[0:0];
- _RAND_96 = {1{`RANDOM}};
- valid_96 = _RAND_96[0:0];
- _RAND_97 = {1{`RANDOM}};
- valid_97 = _RAND_97[0:0];
- _RAND_98 = {1{`RANDOM}};
- valid_98 = _RAND_98[0:0];
- _RAND_99 = {1{`RANDOM}};
- valid_99 = _RAND_99[0:0];
- _RAND_100 = {1{`RANDOM}};
- valid_100 = _RAND_100[0:0];
- _RAND_101 = {1{`RANDOM}};
- valid_101 = _RAND_101[0:0];
- _RAND_102 = {1{`RANDOM}};
- valid_102 = _RAND_102[0:0];
- _RAND_103 = {1{`RANDOM}};
- valid_103 = _RAND_103[0:0];
- _RAND_104 = {1{`RANDOM}};
- valid_104 = _RAND_104[0:0];
- _RAND_105 = {1{`RANDOM}};
- valid_105 = _RAND_105[0:0];
- _RAND_106 = {1{`RANDOM}};
- valid_106 = _RAND_106[0:0];
- _RAND_107 = {1{`RANDOM}};
- valid_107 = _RAND_107[0:0];
- _RAND_108 = {1{`RANDOM}};
- valid_108 = _RAND_108[0:0];
- _RAND_109 = {1{`RANDOM}};
- valid_109 = _RAND_109[0:0];
- _RAND_110 = {1{`RANDOM}};
- valid_110 = _RAND_110[0:0];
- _RAND_111 = {1{`RANDOM}};
- valid_111 = _RAND_111[0:0];
- _RAND_112 = {1{`RANDOM}};
- valid_112 = _RAND_112[0:0];
- _RAND_113 = {1{`RANDOM}};
- valid_113 = _RAND_113[0:0];
- _RAND_114 = {1{`RANDOM}};
- valid_114 = _RAND_114[0:0];
- _RAND_115 = {1{`RANDOM}};
- valid_115 = _RAND_115[0:0];
- _RAND_116 = {1{`RANDOM}};
- valid_116 = _RAND_116[0:0];
- _RAND_117 = {1{`RANDOM}};
- valid_117 = _RAND_117[0:0];
- _RAND_118 = {1{`RANDOM}};
- valid_118 = _RAND_118[0:0];
- _RAND_119 = {1{`RANDOM}};
- valid_119 = _RAND_119[0:0];
- _RAND_120 = {1{`RANDOM}};
- valid_120 = _RAND_120[0:0];
- _RAND_121 = {1{`RANDOM}};
- valid_121 = _RAND_121[0:0];
- _RAND_122 = {1{`RANDOM}};
- valid_122 = _RAND_122[0:0];
- _RAND_123 = {1{`RANDOM}};
- valid_123 = _RAND_123[0:0];
- _RAND_124 = {1{`RANDOM}};
- valid_124 = _RAND_124[0:0];
- _RAND_125 = {1{`RANDOM}};
- valid_125 = _RAND_125[0:0];
- _RAND_126 = {1{`RANDOM}};
- valid_126 = _RAND_126[0:0];
- _RAND_127 = {1{`RANDOM}};
- valid_127 = _RAND_127[0:0];
- _RAND_128 = {1{`RANDOM}};
- valid_128 = _RAND_128[0:0];
- _RAND_129 = {1{`RANDOM}};
- valid_129 = _RAND_129[0:0];
- _RAND_130 = {1{`RANDOM}};
- valid_130 = _RAND_130[0:0];
- _RAND_131 = {1{`RANDOM}};
- valid_131 = _RAND_131[0:0];
- _RAND_132 = {1{`RANDOM}};
- valid_132 = _RAND_132[0:0];
- _RAND_133 = {1{`RANDOM}};
- valid_133 = _RAND_133[0:0];
- _RAND_134 = {1{`RANDOM}};
- valid_134 = _RAND_134[0:0];
- _RAND_135 = {1{`RANDOM}};
- valid_135 = _RAND_135[0:0];
- _RAND_136 = {1{`RANDOM}};
- valid_136 = _RAND_136[0:0];
- _RAND_137 = {1{`RANDOM}};
- valid_137 = _RAND_137[0:0];
- _RAND_138 = {1{`RANDOM}};
- valid_138 = _RAND_138[0:0];
- _RAND_139 = {1{`RANDOM}};
- valid_139 = _RAND_139[0:0];
- _RAND_140 = {1{`RANDOM}};
- valid_140 = _RAND_140[0:0];
- _RAND_141 = {1{`RANDOM}};
- valid_141 = _RAND_141[0:0];
- _RAND_142 = {1{`RANDOM}};
- valid_142 = _RAND_142[0:0];
- _RAND_143 = {1{`RANDOM}};
- valid_143 = _RAND_143[0:0];
- _RAND_144 = {1{`RANDOM}};
- valid_144 = _RAND_144[0:0];
- _RAND_145 = {1{`RANDOM}};
- valid_145 = _RAND_145[0:0];
- _RAND_146 = {1{`RANDOM}};
- valid_146 = _RAND_146[0:0];
- _RAND_147 = {1{`RANDOM}};
- valid_147 = _RAND_147[0:0];
- _RAND_148 = {1{`RANDOM}};
- valid_148 = _RAND_148[0:0];
- _RAND_149 = {1{`RANDOM}};
- valid_149 = _RAND_149[0:0];
- _RAND_150 = {1{`RANDOM}};
- valid_150 = _RAND_150[0:0];
- _RAND_151 = {1{`RANDOM}};
- valid_151 = _RAND_151[0:0];
- _RAND_152 = {1{`RANDOM}};
- valid_152 = _RAND_152[0:0];
- _RAND_153 = {1{`RANDOM}};
- valid_153 = _RAND_153[0:0];
- _RAND_154 = {1{`RANDOM}};
- valid_154 = _RAND_154[0:0];
- _RAND_155 = {1{`RANDOM}};
- valid_155 = _RAND_155[0:0];
- _RAND_156 = {1{`RANDOM}};
- valid_156 = _RAND_156[0:0];
- _RAND_157 = {1{`RANDOM}};
- valid_157 = _RAND_157[0:0];
- _RAND_158 = {1{`RANDOM}};
- valid_158 = _RAND_158[0:0];
- _RAND_159 = {1{`RANDOM}};
- valid_159 = _RAND_159[0:0];
- _RAND_160 = {1{`RANDOM}};
- valid_160 = _RAND_160[0:0];
- _RAND_161 = {1{`RANDOM}};
- valid_161 = _RAND_161[0:0];
- _RAND_162 = {1{`RANDOM}};
- valid_162 = _RAND_162[0:0];
- _RAND_163 = {1{`RANDOM}};
- valid_163 = _RAND_163[0:0];
- _RAND_164 = {1{`RANDOM}};
- valid_164 = _RAND_164[0:0];
- _RAND_165 = {1{`RANDOM}};
- valid_165 = _RAND_165[0:0];
- _RAND_166 = {1{`RANDOM}};
- valid_166 = _RAND_166[0:0];
- _RAND_167 = {1{`RANDOM}};
- valid_167 = _RAND_167[0:0];
- _RAND_168 = {1{`RANDOM}};
- valid_168 = _RAND_168[0:0];
- _RAND_169 = {1{`RANDOM}};
- valid_169 = _RAND_169[0:0];
- _RAND_170 = {1{`RANDOM}};
- valid_170 = _RAND_170[0:0];
- _RAND_171 = {1{`RANDOM}};
- valid_171 = _RAND_171[0:0];
- _RAND_172 = {1{`RANDOM}};
- valid_172 = _RAND_172[0:0];
- _RAND_173 = {1{`RANDOM}};
- valid_173 = _RAND_173[0:0];
- _RAND_174 = {1{`RANDOM}};
- valid_174 = _RAND_174[0:0];
- _RAND_175 = {1{`RANDOM}};
- valid_175 = _RAND_175[0:0];
- _RAND_176 = {1{`RANDOM}};
- valid_176 = _RAND_176[0:0];
- _RAND_177 = {1{`RANDOM}};
- valid_177 = _RAND_177[0:0];
- _RAND_178 = {1{`RANDOM}};
- valid_178 = _RAND_178[0:0];
- _RAND_179 = {1{`RANDOM}};
- valid_179 = _RAND_179[0:0];
- _RAND_180 = {1{`RANDOM}};
- valid_180 = _RAND_180[0:0];
- _RAND_181 = {1{`RANDOM}};
- valid_181 = _RAND_181[0:0];
- _RAND_182 = {1{`RANDOM}};
- valid_182 = _RAND_182[0:0];
- _RAND_183 = {1{`RANDOM}};
- valid_183 = _RAND_183[0:0];
- _RAND_184 = {1{`RANDOM}};
- valid_184 = _RAND_184[0:0];
- _RAND_185 = {1{`RANDOM}};
- valid_185 = _RAND_185[0:0];
- _RAND_186 = {1{`RANDOM}};
- valid_186 = _RAND_186[0:0];
- _RAND_187 = {1{`RANDOM}};
- valid_187 = _RAND_187[0:0];
- _RAND_188 = {1{`RANDOM}};
- valid_188 = _RAND_188[0:0];
- _RAND_189 = {1{`RANDOM}};
- valid_189 = _RAND_189[0:0];
- _RAND_190 = {1{`RANDOM}};
- valid_190 = _RAND_190[0:0];
- _RAND_191 = {1{`RANDOM}};
- valid_191 = _RAND_191[0:0];
- _RAND_192 = {1{`RANDOM}};
- valid_192 = _RAND_192[0:0];
- _RAND_193 = {1{`RANDOM}};
- valid_193 = _RAND_193[0:0];
- _RAND_194 = {1{`RANDOM}};
- valid_194 = _RAND_194[0:0];
- _RAND_195 = {1{`RANDOM}};
- valid_195 = _RAND_195[0:0];
- _RAND_196 = {1{`RANDOM}};
- valid_196 = _RAND_196[0:0];
- _RAND_197 = {1{`RANDOM}};
- valid_197 = _RAND_197[0:0];
- _RAND_198 = {1{`RANDOM}};
- valid_198 = _RAND_198[0:0];
- _RAND_199 = {1{`RANDOM}};
- valid_199 = _RAND_199[0:0];
- _RAND_200 = {1{`RANDOM}};
- valid_200 = _RAND_200[0:0];
- _RAND_201 = {1{`RANDOM}};
- valid_201 = _RAND_201[0:0];
- _RAND_202 = {1{`RANDOM}};
- valid_202 = _RAND_202[0:0];
- _RAND_203 = {1{`RANDOM}};
- valid_203 = _RAND_203[0:0];
- _RAND_204 = {1{`RANDOM}};
- valid_204 = _RAND_204[0:0];
- _RAND_205 = {1{`RANDOM}};
- valid_205 = _RAND_205[0:0];
- _RAND_206 = {1{`RANDOM}};
- valid_206 = _RAND_206[0:0];
- _RAND_207 = {1{`RANDOM}};
- valid_207 = _RAND_207[0:0];
- _RAND_208 = {1{`RANDOM}};
- valid_208 = _RAND_208[0:0];
- _RAND_209 = {1{`RANDOM}};
- valid_209 = _RAND_209[0:0];
- _RAND_210 = {1{`RANDOM}};
- valid_210 = _RAND_210[0:0];
- _RAND_211 = {1{`RANDOM}};
- valid_211 = _RAND_211[0:0];
- _RAND_212 = {1{`RANDOM}};
- valid_212 = _RAND_212[0:0];
- _RAND_213 = {1{`RANDOM}};
- valid_213 = _RAND_213[0:0];
- _RAND_214 = {1{`RANDOM}};
- valid_214 = _RAND_214[0:0];
- _RAND_215 = {1{`RANDOM}};
- valid_215 = _RAND_215[0:0];
- _RAND_216 = {1{`RANDOM}};
- valid_216 = _RAND_216[0:0];
- _RAND_217 = {1{`RANDOM}};
- valid_217 = _RAND_217[0:0];
- _RAND_218 = {1{`RANDOM}};
- valid_218 = _RAND_218[0:0];
- _RAND_219 = {1{`RANDOM}};
- valid_219 = _RAND_219[0:0];
- _RAND_220 = {1{`RANDOM}};
- valid_220 = _RAND_220[0:0];
- _RAND_221 = {1{`RANDOM}};
- valid_221 = _RAND_221[0:0];
- _RAND_222 = {1{`RANDOM}};
- valid_222 = _RAND_222[0:0];
- _RAND_223 = {1{`RANDOM}};
- valid_223 = _RAND_223[0:0];
- _RAND_224 = {1{`RANDOM}};
- valid_224 = _RAND_224[0:0];
- _RAND_225 = {1{`RANDOM}};
- valid_225 = _RAND_225[0:0];
- _RAND_226 = {1{`RANDOM}};
- valid_226 = _RAND_226[0:0];
- _RAND_227 = {1{`RANDOM}};
- valid_227 = _RAND_227[0:0];
- _RAND_228 = {1{`RANDOM}};
- valid_228 = _RAND_228[0:0];
- _RAND_229 = {1{`RANDOM}};
- valid_229 = _RAND_229[0:0];
- _RAND_230 = {1{`RANDOM}};
- valid_230 = _RAND_230[0:0];
- _RAND_231 = {1{`RANDOM}};
- valid_231 = _RAND_231[0:0];
- _RAND_232 = {1{`RANDOM}};
- valid_232 = _RAND_232[0:0];
- _RAND_233 = {1{`RANDOM}};
- valid_233 = _RAND_233[0:0];
- _RAND_234 = {1{`RANDOM}};
- valid_234 = _RAND_234[0:0];
- _RAND_235 = {1{`RANDOM}};
- valid_235 = _RAND_235[0:0];
- _RAND_236 = {1{`RANDOM}};
- valid_236 = _RAND_236[0:0];
- _RAND_237 = {1{`RANDOM}};
- valid_237 = _RAND_237[0:0];
- _RAND_238 = {1{`RANDOM}};
- valid_238 = _RAND_238[0:0];
- _RAND_239 = {1{`RANDOM}};
- valid_239 = _RAND_239[0:0];
- _RAND_240 = {1{`RANDOM}};
- valid_240 = _RAND_240[0:0];
- _RAND_241 = {1{`RANDOM}};
- valid_241 = _RAND_241[0:0];
- _RAND_242 = {1{`RANDOM}};
- valid_242 = _RAND_242[0:0];
- _RAND_243 = {1{`RANDOM}};
- valid_243 = _RAND_243[0:0];
- _RAND_244 = {1{`RANDOM}};
- valid_244 = _RAND_244[0:0];
- _RAND_245 = {1{`RANDOM}};
- valid_245 = _RAND_245[0:0];
- _RAND_246 = {1{`RANDOM}};
- valid_246 = _RAND_246[0:0];
- _RAND_247 = {1{`RANDOM}};
- valid_247 = _RAND_247[0:0];
- _RAND_248 = {1{`RANDOM}};
- valid_248 = _RAND_248[0:0];
- _RAND_249 = {1{`RANDOM}};
- valid_249 = _RAND_249[0:0];
- _RAND_250 = {1{`RANDOM}};
- valid_250 = _RAND_250[0:0];
- _RAND_251 = {1{`RANDOM}};
- valid_251 = _RAND_251[0:0];
- _RAND_252 = {1{`RANDOM}};
- valid_252 = _RAND_252[0:0];
- _RAND_253 = {1{`RANDOM}};
- valid_253 = _RAND_253[0:0];
- _RAND_254 = {1{`RANDOM}};
- valid_254 = _RAND_254[0:0];
- _RAND_255 = {1{`RANDOM}};
- valid_255 = _RAND_255[0:0];
- _RAND_256 = {1{`RANDOM}};
- camaddr_0 = _RAND_256[31:0];
- _RAND_257 = {1{`RANDOM}};
- camaddr_1 = _RAND_257[31:0];
- _RAND_258 = {1{`RANDOM}};
- camaddr_2 = _RAND_258[31:0];
- _RAND_259 = {1{`RANDOM}};
- camaddr_3 = _RAND_259[31:0];
- _RAND_260 = {1{`RANDOM}};
- camaddr_4 = _RAND_260[31:0];
- _RAND_261 = {1{`RANDOM}};
- camaddr_5 = _RAND_261[31:0];
- _RAND_262 = {1{`RANDOM}};
- camaddr_6 = _RAND_262[31:0];
- _RAND_263 = {1{`RANDOM}};
- camaddr_7 = _RAND_263[31:0];
- _RAND_264 = {1{`RANDOM}};
- camaddr_8 = _RAND_264[31:0];
- _RAND_265 = {1{`RANDOM}};
- camaddr_9 = _RAND_265[31:0];
- _RAND_266 = {1{`RANDOM}};
- camaddr_10 = _RAND_266[31:0];
- _RAND_267 = {1{`RANDOM}};
- camaddr_11 = _RAND_267[31:0];
- _RAND_268 = {1{`RANDOM}};
- camaddr_12 = _RAND_268[31:0];
- _RAND_269 = {1{`RANDOM}};
- camaddr_13 = _RAND_269[31:0];
- _RAND_270 = {1{`RANDOM}};
- camaddr_14 = _RAND_270[31:0];
- _RAND_271 = {1{`RANDOM}};
- camaddr_15 = _RAND_271[31:0];
- _RAND_272 = {1{`RANDOM}};
- camaddr_16 = _RAND_272[31:0];
- _RAND_273 = {1{`RANDOM}};
- camaddr_17 = _RAND_273[31:0];
- _RAND_274 = {1{`RANDOM}};
- camaddr_18 = _RAND_274[31:0];
- _RAND_275 = {1{`RANDOM}};
- camaddr_19 = _RAND_275[31:0];
- _RAND_276 = {1{`RANDOM}};
- camaddr_20 = _RAND_276[31:0];
- _RAND_277 = {1{`RANDOM}};
- camaddr_21 = _RAND_277[31:0];
- _RAND_278 = {1{`RANDOM}};
- camaddr_22 = _RAND_278[31:0];
- _RAND_279 = {1{`RANDOM}};
- camaddr_23 = _RAND_279[31:0];
- _RAND_280 = {1{`RANDOM}};
- camaddr_24 = _RAND_280[31:0];
- _RAND_281 = {1{`RANDOM}};
- camaddr_25 = _RAND_281[31:0];
- _RAND_282 = {1{`RANDOM}};
- camaddr_26 = _RAND_282[31:0];
- _RAND_283 = {1{`RANDOM}};
- camaddr_27 = _RAND_283[31:0];
- _RAND_284 = {1{`RANDOM}};
- camaddr_28 = _RAND_284[31:0];
- _RAND_285 = {1{`RANDOM}};
- camaddr_29 = _RAND_285[31:0];
- _RAND_286 = {1{`RANDOM}};
- camaddr_30 = _RAND_286[31:0];
- _RAND_287 = {1{`RANDOM}};
- camaddr_31 = _RAND_287[31:0];
- _RAND_288 = {1{`RANDOM}};
- camaddr_32 = _RAND_288[31:0];
- _RAND_289 = {1{`RANDOM}};
- camaddr_33 = _RAND_289[31:0];
- _RAND_290 = {1{`RANDOM}};
- camaddr_34 = _RAND_290[31:0];
- _RAND_291 = {1{`RANDOM}};
- camaddr_35 = _RAND_291[31:0];
- _RAND_292 = {1{`RANDOM}};
- camaddr_36 = _RAND_292[31:0];
- _RAND_293 = {1{`RANDOM}};
- camaddr_37 = _RAND_293[31:0];
- _RAND_294 = {1{`RANDOM}};
- camaddr_38 = _RAND_294[31:0];
- _RAND_295 = {1{`RANDOM}};
- camaddr_39 = _RAND_295[31:0];
- _RAND_296 = {1{`RANDOM}};
- camaddr_40 = _RAND_296[31:0];
- _RAND_297 = {1{`RANDOM}};
- camaddr_41 = _RAND_297[31:0];
- _RAND_298 = {1{`RANDOM}};
- camaddr_42 = _RAND_298[31:0];
- _RAND_299 = {1{`RANDOM}};
- camaddr_43 = _RAND_299[31:0];
- _RAND_300 = {1{`RANDOM}};
- camaddr_44 = _RAND_300[31:0];
- _RAND_301 = {1{`RANDOM}};
- camaddr_45 = _RAND_301[31:0];
- _RAND_302 = {1{`RANDOM}};
- camaddr_46 = _RAND_302[31:0];
- _RAND_303 = {1{`RANDOM}};
- camaddr_47 = _RAND_303[31:0];
- _RAND_304 = {1{`RANDOM}};
- camaddr_48 = _RAND_304[31:0];
- _RAND_305 = {1{`RANDOM}};
- camaddr_49 = _RAND_305[31:0];
- _RAND_306 = {1{`RANDOM}};
- camaddr_50 = _RAND_306[31:0];
- _RAND_307 = {1{`RANDOM}};
- camaddr_51 = _RAND_307[31:0];
- _RAND_308 = {1{`RANDOM}};
- camaddr_52 = _RAND_308[31:0];
- _RAND_309 = {1{`RANDOM}};
- camaddr_53 = _RAND_309[31:0];
- _RAND_310 = {1{`RANDOM}};
- camaddr_54 = _RAND_310[31:0];
- _RAND_311 = {1{`RANDOM}};
- camaddr_55 = _RAND_311[31:0];
- _RAND_312 = {1{`RANDOM}};
- camaddr_56 = _RAND_312[31:0];
- _RAND_313 = {1{`RANDOM}};
- camaddr_57 = _RAND_313[31:0];
- _RAND_314 = {1{`RANDOM}};
- camaddr_58 = _RAND_314[31:0];
- _RAND_315 = {1{`RANDOM}};
- camaddr_59 = _RAND_315[31:0];
- _RAND_316 = {1{`RANDOM}};
- camaddr_60 = _RAND_316[31:0];
- _RAND_317 = {1{`RANDOM}};
- camaddr_61 = _RAND_317[31:0];
- _RAND_318 = {1{`RANDOM}};
- camaddr_62 = _RAND_318[31:0];
- _RAND_319 = {1{`RANDOM}};
- camaddr_63 = _RAND_319[31:0];
- _RAND_320 = {1{`RANDOM}};
- camaddr_64 = _RAND_320[31:0];
- _RAND_321 = {1{`RANDOM}};
- camaddr_65 = _RAND_321[31:0];
- _RAND_322 = {1{`RANDOM}};
- camaddr_66 = _RAND_322[31:0];
- _RAND_323 = {1{`RANDOM}};
- camaddr_67 = _RAND_323[31:0];
- _RAND_324 = {1{`RANDOM}};
- camaddr_68 = _RAND_324[31:0];
- _RAND_325 = {1{`RANDOM}};
- camaddr_69 = _RAND_325[31:0];
- _RAND_326 = {1{`RANDOM}};
- camaddr_70 = _RAND_326[31:0];
- _RAND_327 = {1{`RANDOM}};
- camaddr_71 = _RAND_327[31:0];
- _RAND_328 = {1{`RANDOM}};
- camaddr_72 = _RAND_328[31:0];
- _RAND_329 = {1{`RANDOM}};
- camaddr_73 = _RAND_329[31:0];
- _RAND_330 = {1{`RANDOM}};
- camaddr_74 = _RAND_330[31:0];
- _RAND_331 = {1{`RANDOM}};
- camaddr_75 = _RAND_331[31:0];
- _RAND_332 = {1{`RANDOM}};
- camaddr_76 = _RAND_332[31:0];
- _RAND_333 = {1{`RANDOM}};
- camaddr_77 = _RAND_333[31:0];
- _RAND_334 = {1{`RANDOM}};
- camaddr_78 = _RAND_334[31:0];
- _RAND_335 = {1{`RANDOM}};
- camaddr_79 = _RAND_335[31:0];
- _RAND_336 = {1{`RANDOM}};
- camaddr_80 = _RAND_336[31:0];
- _RAND_337 = {1{`RANDOM}};
- camaddr_81 = _RAND_337[31:0];
- _RAND_338 = {1{`RANDOM}};
- camaddr_82 = _RAND_338[31:0];
- _RAND_339 = {1{`RANDOM}};
- camaddr_83 = _RAND_339[31:0];
- _RAND_340 = {1{`RANDOM}};
- camaddr_84 = _RAND_340[31:0];
- _RAND_341 = {1{`RANDOM}};
- camaddr_85 = _RAND_341[31:0];
- _RAND_342 = {1{`RANDOM}};
- camaddr_86 = _RAND_342[31:0];
- _RAND_343 = {1{`RANDOM}};
- camaddr_87 = _RAND_343[31:0];
- _RAND_344 = {1{`RANDOM}};
- camaddr_88 = _RAND_344[31:0];
- _RAND_345 = {1{`RANDOM}};
- camaddr_89 = _RAND_345[31:0];
- _RAND_346 = {1{`RANDOM}};
- camaddr_90 = _RAND_346[31:0];
- _RAND_347 = {1{`RANDOM}};
- camaddr_91 = _RAND_347[31:0];
- _RAND_348 = {1{`RANDOM}};
- camaddr_92 = _RAND_348[31:0];
- _RAND_349 = {1{`RANDOM}};
- camaddr_93 = _RAND_349[31:0];
- _RAND_350 = {1{`RANDOM}};
- camaddr_94 = _RAND_350[31:0];
- _RAND_351 = {1{`RANDOM}};
- camaddr_95 = _RAND_351[31:0];
- _RAND_352 = {1{`RANDOM}};
- camaddr_96 = _RAND_352[31:0];
- _RAND_353 = {1{`RANDOM}};
- camaddr_97 = _RAND_353[31:0];
- _RAND_354 = {1{`RANDOM}};
- camaddr_98 = _RAND_354[31:0];
- _RAND_355 = {1{`RANDOM}};
- camaddr_99 = _RAND_355[31:0];
- _RAND_356 = {1{`RANDOM}};
- camaddr_100 = _RAND_356[31:0];
- _RAND_357 = {1{`RANDOM}};
- camaddr_101 = _RAND_357[31:0];
- _RAND_358 = {1{`RANDOM}};
- camaddr_102 = _RAND_358[31:0];
- _RAND_359 = {1{`RANDOM}};
- camaddr_103 = _RAND_359[31:0];
- _RAND_360 = {1{`RANDOM}};
- camaddr_104 = _RAND_360[31:0];
- _RAND_361 = {1{`RANDOM}};
- camaddr_105 = _RAND_361[31:0];
- _RAND_362 = {1{`RANDOM}};
- camaddr_106 = _RAND_362[31:0];
- _RAND_363 = {1{`RANDOM}};
- camaddr_107 = _RAND_363[31:0];
- _RAND_364 = {1{`RANDOM}};
- camaddr_108 = _RAND_364[31:0];
- _RAND_365 = {1{`RANDOM}};
- camaddr_109 = _RAND_365[31:0];
- _RAND_366 = {1{`RANDOM}};
- camaddr_110 = _RAND_366[31:0];
- _RAND_367 = {1{`RANDOM}};
- camaddr_111 = _RAND_367[31:0];
- _RAND_368 = {1{`RANDOM}};
- camaddr_112 = _RAND_368[31:0];
- _RAND_369 = {1{`RANDOM}};
- camaddr_113 = _RAND_369[31:0];
- _RAND_370 = {1{`RANDOM}};
- camaddr_114 = _RAND_370[31:0];
- _RAND_371 = {1{`RANDOM}};
- camaddr_115 = _RAND_371[31:0];
- _RAND_372 = {1{`RANDOM}};
- camaddr_116 = _RAND_372[31:0];
- _RAND_373 = {1{`RANDOM}};
- camaddr_117 = _RAND_373[31:0];
- _RAND_374 = {1{`RANDOM}};
- camaddr_118 = _RAND_374[31:0];
- _RAND_375 = {1{`RANDOM}};
- camaddr_119 = _RAND_375[31:0];
- _RAND_376 = {1{`RANDOM}};
- camaddr_120 = _RAND_376[31:0];
- _RAND_377 = {1{`RANDOM}};
- camaddr_121 = _RAND_377[31:0];
- _RAND_378 = {1{`RANDOM}};
- camaddr_122 = _RAND_378[31:0];
- _RAND_379 = {1{`RANDOM}};
- camaddr_123 = _RAND_379[31:0];
- _RAND_380 = {1{`RANDOM}};
- camaddr_124 = _RAND_380[31:0];
- _RAND_381 = {1{`RANDOM}};
- camaddr_125 = _RAND_381[31:0];
- _RAND_382 = {1{`RANDOM}};
- camaddr_126 = _RAND_382[31:0];
- _RAND_383 = {1{`RANDOM}};
- camaddr_127 = _RAND_383[31:0];
- _RAND_384 = {1{`RANDOM}};
- camaddr_128 = _RAND_384[31:0];
- _RAND_385 = {1{`RANDOM}};
- camaddr_129 = _RAND_385[31:0];
- _RAND_386 = {1{`RANDOM}};
- camaddr_130 = _RAND_386[31:0];
- _RAND_387 = {1{`RANDOM}};
- camaddr_131 = _RAND_387[31:0];
- _RAND_388 = {1{`RANDOM}};
- camaddr_132 = _RAND_388[31:0];
- _RAND_389 = {1{`RANDOM}};
- camaddr_133 = _RAND_389[31:0];
- _RAND_390 = {1{`RANDOM}};
- camaddr_134 = _RAND_390[31:0];
- _RAND_391 = {1{`RANDOM}};
- camaddr_135 = _RAND_391[31:0];
- _RAND_392 = {1{`RANDOM}};
- camaddr_136 = _RAND_392[31:0];
- _RAND_393 = {1{`RANDOM}};
- camaddr_137 = _RAND_393[31:0];
- _RAND_394 = {1{`RANDOM}};
- camaddr_138 = _RAND_394[31:0];
- _RAND_395 = {1{`RANDOM}};
- camaddr_139 = _RAND_395[31:0];
- _RAND_396 = {1{`RANDOM}};
- camaddr_140 = _RAND_396[31:0];
- _RAND_397 = {1{`RANDOM}};
- camaddr_141 = _RAND_397[31:0];
- _RAND_398 = {1{`RANDOM}};
- camaddr_142 = _RAND_398[31:0];
- _RAND_399 = {1{`RANDOM}};
- camaddr_143 = _RAND_399[31:0];
- _RAND_400 = {1{`RANDOM}};
- camaddr_144 = _RAND_400[31:0];
- _RAND_401 = {1{`RANDOM}};
- camaddr_145 = _RAND_401[31:0];
- _RAND_402 = {1{`RANDOM}};
- camaddr_146 = _RAND_402[31:0];
- _RAND_403 = {1{`RANDOM}};
- camaddr_147 = _RAND_403[31:0];
- _RAND_404 = {1{`RANDOM}};
- camaddr_148 = _RAND_404[31:0];
- _RAND_405 = {1{`RANDOM}};
- camaddr_149 = _RAND_405[31:0];
- _RAND_406 = {1{`RANDOM}};
- camaddr_150 = _RAND_406[31:0];
- _RAND_407 = {1{`RANDOM}};
- camaddr_151 = _RAND_407[31:0];
- _RAND_408 = {1{`RANDOM}};
- camaddr_152 = _RAND_408[31:0];
- _RAND_409 = {1{`RANDOM}};
- camaddr_153 = _RAND_409[31:0];
- _RAND_410 = {1{`RANDOM}};
- camaddr_154 = _RAND_410[31:0];
- _RAND_411 = {1{`RANDOM}};
- camaddr_155 = _RAND_411[31:0];
- _RAND_412 = {1{`RANDOM}};
- camaddr_156 = _RAND_412[31:0];
- _RAND_413 = {1{`RANDOM}};
- camaddr_157 = _RAND_413[31:0];
- _RAND_414 = {1{`RANDOM}};
- camaddr_158 = _RAND_414[31:0];
- _RAND_415 = {1{`RANDOM}};
- camaddr_159 = _RAND_415[31:0];
- _RAND_416 = {1{`RANDOM}};
- camaddr_160 = _RAND_416[31:0];
- _RAND_417 = {1{`RANDOM}};
- camaddr_161 = _RAND_417[31:0];
- _RAND_418 = {1{`RANDOM}};
- camaddr_162 = _RAND_418[31:0];
- _RAND_419 = {1{`RANDOM}};
- camaddr_163 = _RAND_419[31:0];
- _RAND_420 = {1{`RANDOM}};
- camaddr_164 = _RAND_420[31:0];
- _RAND_421 = {1{`RANDOM}};
- camaddr_165 = _RAND_421[31:0];
- _RAND_422 = {1{`RANDOM}};
- camaddr_166 = _RAND_422[31:0];
- _RAND_423 = {1{`RANDOM}};
- camaddr_167 = _RAND_423[31:0];
- _RAND_424 = {1{`RANDOM}};
- camaddr_168 = _RAND_424[31:0];
- _RAND_425 = {1{`RANDOM}};
- camaddr_169 = _RAND_425[31:0];
- _RAND_426 = {1{`RANDOM}};
- camaddr_170 = _RAND_426[31:0];
- _RAND_427 = {1{`RANDOM}};
- camaddr_171 = _RAND_427[31:0];
- _RAND_428 = {1{`RANDOM}};
- camaddr_172 = _RAND_428[31:0];
- _RAND_429 = {1{`RANDOM}};
- camaddr_173 = _RAND_429[31:0];
- _RAND_430 = {1{`RANDOM}};
- camaddr_174 = _RAND_430[31:0];
- _RAND_431 = {1{`RANDOM}};
- camaddr_175 = _RAND_431[31:0];
- _RAND_432 = {1{`RANDOM}};
- camaddr_176 = _RAND_432[31:0];
- _RAND_433 = {1{`RANDOM}};
- camaddr_177 = _RAND_433[31:0];
- _RAND_434 = {1{`RANDOM}};
- camaddr_178 = _RAND_434[31:0];
- _RAND_435 = {1{`RANDOM}};
- camaddr_179 = _RAND_435[31:0];
- _RAND_436 = {1{`RANDOM}};
- camaddr_180 = _RAND_436[31:0];
- _RAND_437 = {1{`RANDOM}};
- camaddr_181 = _RAND_437[31:0];
- _RAND_438 = {1{`RANDOM}};
- camaddr_182 = _RAND_438[31:0];
- _RAND_439 = {1{`RANDOM}};
- camaddr_183 = _RAND_439[31:0];
- _RAND_440 = {1{`RANDOM}};
- camaddr_184 = _RAND_440[31:0];
- _RAND_441 = {1{`RANDOM}};
- camaddr_185 = _RAND_441[31:0];
- _RAND_442 = {1{`RANDOM}};
- camaddr_186 = _RAND_442[31:0];
- _RAND_443 = {1{`RANDOM}};
- camaddr_187 = _RAND_443[31:0];
- _RAND_444 = {1{`RANDOM}};
- camaddr_188 = _RAND_444[31:0];
- _RAND_445 = {1{`RANDOM}};
- camaddr_189 = _RAND_445[31:0];
- _RAND_446 = {1{`RANDOM}};
- camaddr_190 = _RAND_446[31:0];
- _RAND_447 = {1{`RANDOM}};
- camaddr_191 = _RAND_447[31:0];
- _RAND_448 = {1{`RANDOM}};
- camaddr_192 = _RAND_448[31:0];
- _RAND_449 = {1{`RANDOM}};
- camaddr_193 = _RAND_449[31:0];
- _RAND_450 = {1{`RANDOM}};
- camaddr_194 = _RAND_450[31:0];
- _RAND_451 = {1{`RANDOM}};
- camaddr_195 = _RAND_451[31:0];
- _RAND_452 = {1{`RANDOM}};
- camaddr_196 = _RAND_452[31:0];
- _RAND_453 = {1{`RANDOM}};
- camaddr_197 = _RAND_453[31:0];
- _RAND_454 = {1{`RANDOM}};
- camaddr_198 = _RAND_454[31:0];
- _RAND_455 = {1{`RANDOM}};
- camaddr_199 = _RAND_455[31:0];
- _RAND_456 = {1{`RANDOM}};
- camaddr_200 = _RAND_456[31:0];
- _RAND_457 = {1{`RANDOM}};
- camaddr_201 = _RAND_457[31:0];
- _RAND_458 = {1{`RANDOM}};
- camaddr_202 = _RAND_458[31:0];
- _RAND_459 = {1{`RANDOM}};
- camaddr_203 = _RAND_459[31:0];
- _RAND_460 = {1{`RANDOM}};
- camaddr_204 = _RAND_460[31:0];
- _RAND_461 = {1{`RANDOM}};
- camaddr_205 = _RAND_461[31:0];
- _RAND_462 = {1{`RANDOM}};
- camaddr_206 = _RAND_462[31:0];
- _RAND_463 = {1{`RANDOM}};
- camaddr_207 = _RAND_463[31:0];
- _RAND_464 = {1{`RANDOM}};
- camaddr_208 = _RAND_464[31:0];
- _RAND_465 = {1{`RANDOM}};
- camaddr_209 = _RAND_465[31:0];
- _RAND_466 = {1{`RANDOM}};
- camaddr_210 = _RAND_466[31:0];
- _RAND_467 = {1{`RANDOM}};
- camaddr_211 = _RAND_467[31:0];
- _RAND_468 = {1{`RANDOM}};
- camaddr_212 = _RAND_468[31:0];
- _RAND_469 = {1{`RANDOM}};
- camaddr_213 = _RAND_469[31:0];
- _RAND_470 = {1{`RANDOM}};
- camaddr_214 = _RAND_470[31:0];
- _RAND_471 = {1{`RANDOM}};
- camaddr_215 = _RAND_471[31:0];
- _RAND_472 = {1{`RANDOM}};
- camaddr_216 = _RAND_472[31:0];
- _RAND_473 = {1{`RANDOM}};
- camaddr_217 = _RAND_473[31:0];
- _RAND_474 = {1{`RANDOM}};
- camaddr_218 = _RAND_474[31:0];
- _RAND_475 = {1{`RANDOM}};
- camaddr_219 = _RAND_475[31:0];
- _RAND_476 = {1{`RANDOM}};
- camaddr_220 = _RAND_476[31:0];
- _RAND_477 = {1{`RANDOM}};
- camaddr_221 = _RAND_477[31:0];
- _RAND_478 = {1{`RANDOM}};
- camaddr_222 = _RAND_478[31:0];
- _RAND_479 = {1{`RANDOM}};
- camaddr_223 = _RAND_479[31:0];
- _RAND_480 = {1{`RANDOM}};
- camaddr_224 = _RAND_480[31:0];
- _RAND_481 = {1{`RANDOM}};
- camaddr_225 = _RAND_481[31:0];
- _RAND_482 = {1{`RANDOM}};
- camaddr_226 = _RAND_482[31:0];
- _RAND_483 = {1{`RANDOM}};
- camaddr_227 = _RAND_483[31:0];
- _RAND_484 = {1{`RANDOM}};
- camaddr_228 = _RAND_484[31:0];
- _RAND_485 = {1{`RANDOM}};
- camaddr_229 = _RAND_485[31:0];
- _RAND_486 = {1{`RANDOM}};
- camaddr_230 = _RAND_486[31:0];
- _RAND_487 = {1{`RANDOM}};
- camaddr_231 = _RAND_487[31:0];
- _RAND_488 = {1{`RANDOM}};
- camaddr_232 = _RAND_488[31:0];
- _RAND_489 = {1{`RANDOM}};
- camaddr_233 = _RAND_489[31:0];
- _RAND_490 = {1{`RANDOM}};
- camaddr_234 = _RAND_490[31:0];
- _RAND_491 = {1{`RANDOM}};
- camaddr_235 = _RAND_491[31:0];
- _RAND_492 = {1{`RANDOM}};
- camaddr_236 = _RAND_492[31:0];
- _RAND_493 = {1{`RANDOM}};
- camaddr_237 = _RAND_493[31:0];
- _RAND_494 = {1{`RANDOM}};
- camaddr_238 = _RAND_494[31:0];
- _RAND_495 = {1{`RANDOM}};
- camaddr_239 = _RAND_495[31:0];
- _RAND_496 = {1{`RANDOM}};
- camaddr_240 = _RAND_496[31:0];
- _RAND_497 = {1{`RANDOM}};
- camaddr_241 = _RAND_497[31:0];
- _RAND_498 = {1{`RANDOM}};
- camaddr_242 = _RAND_498[31:0];
- _RAND_499 = {1{`RANDOM}};
- camaddr_243 = _RAND_499[31:0];
- _RAND_500 = {1{`RANDOM}};
- camaddr_244 = _RAND_500[31:0];
- _RAND_501 = {1{`RANDOM}};
- camaddr_245 = _RAND_501[31:0];
- _RAND_502 = {1{`RANDOM}};
- camaddr_246 = _RAND_502[31:0];
- _RAND_503 = {1{`RANDOM}};
- camaddr_247 = _RAND_503[31:0];
- _RAND_504 = {1{`RANDOM}};
- camaddr_248 = _RAND_504[31:0];
- _RAND_505 = {1{`RANDOM}};
- camaddr_249 = _RAND_505[31:0];
- _RAND_506 = {1{`RANDOM}};
- camaddr_250 = _RAND_506[31:0];
- _RAND_507 = {1{`RANDOM}};
- camaddr_251 = _RAND_507[31:0];
- _RAND_508 = {1{`RANDOM}};
- camaddr_252 = _RAND_508[31:0];
- _RAND_509 = {1{`RANDOM}};
- camaddr_253 = _RAND_509[31:0];
- _RAND_510 = {1{`RANDOM}};
- camaddr_254 = _RAND_510[31:0];
- _RAND_511 = {1{`RANDOM}};
- camaddr_255 = _RAND_511[31:0];
- _RAND_512 = {1{`RANDOM}};
- history_0_0 = _RAND_512[1:0];
- _RAND_513 = {1{`RANDOM}};
- history_0_1 = _RAND_513[1:0];
- _RAND_514 = {1{`RANDOM}};
- history_0_2 = _RAND_514[1:0];
- _RAND_515 = {1{`RANDOM}};
- history_0_3 = _RAND_515[1:0];
- _RAND_516 = {1{`RANDOM}};
- history_1_0 = _RAND_516[1:0];
- _RAND_517 = {1{`RANDOM}};
- history_1_1 = _RAND_517[1:0];
- _RAND_518 = {1{`RANDOM}};
- history_1_2 = _RAND_518[1:0];
- _RAND_519 = {1{`RANDOM}};
- history_1_3 = _RAND_519[1:0];
- _RAND_520 = {1{`RANDOM}};
- history_2_0 = _RAND_520[1:0];
- _RAND_521 = {1{`RANDOM}};
- history_2_1 = _RAND_521[1:0];
- _RAND_522 = {1{`RANDOM}};
- history_2_2 = _RAND_522[1:0];
- _RAND_523 = {1{`RANDOM}};
- history_2_3 = _RAND_523[1:0];
- _RAND_524 = {1{`RANDOM}};
- history_3_0 = _RAND_524[1:0];
- _RAND_525 = {1{`RANDOM}};
- history_3_1 = _RAND_525[1:0];
- _RAND_526 = {1{`RANDOM}};
- history_3_2 = _RAND_526[1:0];
- _RAND_527 = {1{`RANDOM}};
- history_3_3 = _RAND_527[1:0];
- _RAND_528 = {1{`RANDOM}};
- history_4_0 = _RAND_528[1:0];
- _RAND_529 = {1{`RANDOM}};
- history_4_1 = _RAND_529[1:0];
- _RAND_530 = {1{`RANDOM}};
- history_4_2 = _RAND_530[1:0];
- _RAND_531 = {1{`RANDOM}};
- history_4_3 = _RAND_531[1:0];
- _RAND_532 = {1{`RANDOM}};
- history_5_0 = _RAND_532[1:0];
- _RAND_533 = {1{`RANDOM}};
- history_5_1 = _RAND_533[1:0];
- _RAND_534 = {1{`RANDOM}};
- history_5_2 = _RAND_534[1:0];
- _RAND_535 = {1{`RANDOM}};
- history_5_3 = _RAND_535[1:0];
- _RAND_536 = {1{`RANDOM}};
- history_6_0 = _RAND_536[1:0];
- _RAND_537 = {1{`RANDOM}};
- history_6_1 = _RAND_537[1:0];
- _RAND_538 = {1{`RANDOM}};
- history_6_2 = _RAND_538[1:0];
- _RAND_539 = {1{`RANDOM}};
- history_6_3 = _RAND_539[1:0];
- _RAND_540 = {1{`RANDOM}};
- history_7_0 = _RAND_540[1:0];
- _RAND_541 = {1{`RANDOM}};
- history_7_1 = _RAND_541[1:0];
- _RAND_542 = {1{`RANDOM}};
- history_7_2 = _RAND_542[1:0];
- _RAND_543 = {1{`RANDOM}};
- history_7_3 = _RAND_543[1:0];
- _RAND_544 = {1{`RANDOM}};
- history_8_0 = _RAND_544[1:0];
- _RAND_545 = {1{`RANDOM}};
- history_8_1 = _RAND_545[1:0];
- _RAND_546 = {1{`RANDOM}};
- history_8_2 = _RAND_546[1:0];
- _RAND_547 = {1{`RANDOM}};
- history_8_3 = _RAND_547[1:0];
- _RAND_548 = {1{`RANDOM}};
- history_9_0 = _RAND_548[1:0];
- _RAND_549 = {1{`RANDOM}};
- history_9_1 = _RAND_549[1:0];
- _RAND_550 = {1{`RANDOM}};
- history_9_2 = _RAND_550[1:0];
- _RAND_551 = {1{`RANDOM}};
- history_9_3 = _RAND_551[1:0];
- _RAND_552 = {1{`RANDOM}};
- history_10_0 = _RAND_552[1:0];
- _RAND_553 = {1{`RANDOM}};
- history_10_1 = _RAND_553[1:0];
- _RAND_554 = {1{`RANDOM}};
- history_10_2 = _RAND_554[1:0];
- _RAND_555 = {1{`RANDOM}};
- history_10_3 = _RAND_555[1:0];
- _RAND_556 = {1{`RANDOM}};
- history_11_0 = _RAND_556[1:0];
- _RAND_557 = {1{`RANDOM}};
- history_11_1 = _RAND_557[1:0];
- _RAND_558 = {1{`RANDOM}};
- history_11_2 = _RAND_558[1:0];
- _RAND_559 = {1{`RANDOM}};
- history_11_3 = _RAND_559[1:0];
- _RAND_560 = {1{`RANDOM}};
- history_12_0 = _RAND_560[1:0];
- _RAND_561 = {1{`RANDOM}};
- history_12_1 = _RAND_561[1:0];
- _RAND_562 = {1{`RANDOM}};
- history_12_2 = _RAND_562[1:0];
- _RAND_563 = {1{`RANDOM}};
- history_12_3 = _RAND_563[1:0];
- _RAND_564 = {1{`RANDOM}};
- history_13_0 = _RAND_564[1:0];
- _RAND_565 = {1{`RANDOM}};
- history_13_1 = _RAND_565[1:0];
- _RAND_566 = {1{`RANDOM}};
- history_13_2 = _RAND_566[1:0];
- _RAND_567 = {1{`RANDOM}};
- history_13_3 = _RAND_567[1:0];
- _RAND_568 = {1{`RANDOM}};
- history_14_0 = _RAND_568[1:0];
- _RAND_569 = {1{`RANDOM}};
- history_14_1 = _RAND_569[1:0];
- _RAND_570 = {1{`RANDOM}};
- history_14_2 = _RAND_570[1:0];
- _RAND_571 = {1{`RANDOM}};
- history_14_3 = _RAND_571[1:0];
- _RAND_572 = {1{`RANDOM}};
- history_15_0 = _RAND_572[1:0];
- _RAND_573 = {1{`RANDOM}};
- history_15_1 = _RAND_573[1:0];
- _RAND_574 = {1{`RANDOM}};
- history_15_2 = _RAND_574[1:0];
- _RAND_575 = {1{`RANDOM}};
- history_15_3 = _RAND_575[1:0];
- _RAND_576 = {1{`RANDOM}};
- history_16_0 = _RAND_576[1:0];
- _RAND_577 = {1{`RANDOM}};
- history_16_1 = _RAND_577[1:0];
- _RAND_578 = {1{`RANDOM}};
- history_16_2 = _RAND_578[1:0];
- _RAND_579 = {1{`RANDOM}};
- history_16_3 = _RAND_579[1:0];
- _RAND_580 = {1{`RANDOM}};
- history_17_0 = _RAND_580[1:0];
- _RAND_581 = {1{`RANDOM}};
- history_17_1 = _RAND_581[1:0];
- _RAND_582 = {1{`RANDOM}};
- history_17_2 = _RAND_582[1:0];
- _RAND_583 = {1{`RANDOM}};
- history_17_3 = _RAND_583[1:0];
- _RAND_584 = {1{`RANDOM}};
- history_18_0 = _RAND_584[1:0];
- _RAND_585 = {1{`RANDOM}};
- history_18_1 = _RAND_585[1:0];
- _RAND_586 = {1{`RANDOM}};
- history_18_2 = _RAND_586[1:0];
- _RAND_587 = {1{`RANDOM}};
- history_18_3 = _RAND_587[1:0];
- _RAND_588 = {1{`RANDOM}};
- history_19_0 = _RAND_588[1:0];
- _RAND_589 = {1{`RANDOM}};
- history_19_1 = _RAND_589[1:0];
- _RAND_590 = {1{`RANDOM}};
- history_19_2 = _RAND_590[1:0];
- _RAND_591 = {1{`RANDOM}};
- history_19_3 = _RAND_591[1:0];
- _RAND_592 = {1{`RANDOM}};
- history_20_0 = _RAND_592[1:0];
- _RAND_593 = {1{`RANDOM}};
- history_20_1 = _RAND_593[1:0];
- _RAND_594 = {1{`RANDOM}};
- history_20_2 = _RAND_594[1:0];
- _RAND_595 = {1{`RANDOM}};
- history_20_3 = _RAND_595[1:0];
- _RAND_596 = {1{`RANDOM}};
- history_21_0 = _RAND_596[1:0];
- _RAND_597 = {1{`RANDOM}};
- history_21_1 = _RAND_597[1:0];
- _RAND_598 = {1{`RANDOM}};
- history_21_2 = _RAND_598[1:0];
- _RAND_599 = {1{`RANDOM}};
- history_21_3 = _RAND_599[1:0];
- _RAND_600 = {1{`RANDOM}};
- history_22_0 = _RAND_600[1:0];
- _RAND_601 = {1{`RANDOM}};
- history_22_1 = _RAND_601[1:0];
- _RAND_602 = {1{`RANDOM}};
- history_22_2 = _RAND_602[1:0];
- _RAND_603 = {1{`RANDOM}};
- history_22_3 = _RAND_603[1:0];
- _RAND_604 = {1{`RANDOM}};
- history_23_0 = _RAND_604[1:0];
- _RAND_605 = {1{`RANDOM}};
- history_23_1 = _RAND_605[1:0];
- _RAND_606 = {1{`RANDOM}};
- history_23_2 = _RAND_606[1:0];
- _RAND_607 = {1{`RANDOM}};
- history_23_3 = _RAND_607[1:0];
- _RAND_608 = {1{`RANDOM}};
- history_24_0 = _RAND_608[1:0];
- _RAND_609 = {1{`RANDOM}};
- history_24_1 = _RAND_609[1:0];
- _RAND_610 = {1{`RANDOM}};
- history_24_2 = _RAND_610[1:0];
- _RAND_611 = {1{`RANDOM}};
- history_24_3 = _RAND_611[1:0];
- _RAND_612 = {1{`RANDOM}};
- history_25_0 = _RAND_612[1:0];
- _RAND_613 = {1{`RANDOM}};
- history_25_1 = _RAND_613[1:0];
- _RAND_614 = {1{`RANDOM}};
- history_25_2 = _RAND_614[1:0];
- _RAND_615 = {1{`RANDOM}};
- history_25_3 = _RAND_615[1:0];
- _RAND_616 = {1{`RANDOM}};
- history_26_0 = _RAND_616[1:0];
- _RAND_617 = {1{`RANDOM}};
- history_26_1 = _RAND_617[1:0];
- _RAND_618 = {1{`RANDOM}};
- history_26_2 = _RAND_618[1:0];
- _RAND_619 = {1{`RANDOM}};
- history_26_3 = _RAND_619[1:0];
- _RAND_620 = {1{`RANDOM}};
- history_27_0 = _RAND_620[1:0];
- _RAND_621 = {1{`RANDOM}};
- history_27_1 = _RAND_621[1:0];
- _RAND_622 = {1{`RANDOM}};
- history_27_2 = _RAND_622[1:0];
- _RAND_623 = {1{`RANDOM}};
- history_27_3 = _RAND_623[1:0];
- _RAND_624 = {1{`RANDOM}};
- history_28_0 = _RAND_624[1:0];
- _RAND_625 = {1{`RANDOM}};
- history_28_1 = _RAND_625[1:0];
- _RAND_626 = {1{`RANDOM}};
- history_28_2 = _RAND_626[1:0];
- _RAND_627 = {1{`RANDOM}};
- history_28_3 = _RAND_627[1:0];
- _RAND_628 = {1{`RANDOM}};
- history_29_0 = _RAND_628[1:0];
- _RAND_629 = {1{`RANDOM}};
- history_29_1 = _RAND_629[1:0];
- _RAND_630 = {1{`RANDOM}};
- history_29_2 = _RAND_630[1:0];
- _RAND_631 = {1{`RANDOM}};
- history_29_3 = _RAND_631[1:0];
- _RAND_632 = {1{`RANDOM}};
- history_30_0 = _RAND_632[1:0];
- _RAND_633 = {1{`RANDOM}};
- history_30_1 = _RAND_633[1:0];
- _RAND_634 = {1{`RANDOM}};
- history_30_2 = _RAND_634[1:0];
- _RAND_635 = {1{`RANDOM}};
- history_30_3 = _RAND_635[1:0];
- _RAND_636 = {1{`RANDOM}};
- history_31_0 = _RAND_636[1:0];
- _RAND_637 = {1{`RANDOM}};
- history_31_1 = _RAND_637[1:0];
- _RAND_638 = {1{`RANDOM}};
- history_31_2 = _RAND_638[1:0];
- _RAND_639 = {1{`RANDOM}};
- history_31_3 = _RAND_639[1:0];
- _RAND_640 = {1{`RANDOM}};
- history_32_0 = _RAND_640[1:0];
- _RAND_641 = {1{`RANDOM}};
- history_32_1 = _RAND_641[1:0];
- _RAND_642 = {1{`RANDOM}};
- history_32_2 = _RAND_642[1:0];
- _RAND_643 = {1{`RANDOM}};
- history_32_3 = _RAND_643[1:0];
- _RAND_644 = {1{`RANDOM}};
- history_33_0 = _RAND_644[1:0];
- _RAND_645 = {1{`RANDOM}};
- history_33_1 = _RAND_645[1:0];
- _RAND_646 = {1{`RANDOM}};
- history_33_2 = _RAND_646[1:0];
- _RAND_647 = {1{`RANDOM}};
- history_33_3 = _RAND_647[1:0];
- _RAND_648 = {1{`RANDOM}};
- history_34_0 = _RAND_648[1:0];
- _RAND_649 = {1{`RANDOM}};
- history_34_1 = _RAND_649[1:0];
- _RAND_650 = {1{`RANDOM}};
- history_34_2 = _RAND_650[1:0];
- _RAND_651 = {1{`RANDOM}};
- history_34_3 = _RAND_651[1:0];
- _RAND_652 = {1{`RANDOM}};
- history_35_0 = _RAND_652[1:0];
- _RAND_653 = {1{`RANDOM}};
- history_35_1 = _RAND_653[1:0];
- _RAND_654 = {1{`RANDOM}};
- history_35_2 = _RAND_654[1:0];
- _RAND_655 = {1{`RANDOM}};
- history_35_3 = _RAND_655[1:0];
- _RAND_656 = {1{`RANDOM}};
- history_36_0 = _RAND_656[1:0];
- _RAND_657 = {1{`RANDOM}};
- history_36_1 = _RAND_657[1:0];
- _RAND_658 = {1{`RANDOM}};
- history_36_2 = _RAND_658[1:0];
- _RAND_659 = {1{`RANDOM}};
- history_36_3 = _RAND_659[1:0];
- _RAND_660 = {1{`RANDOM}};
- history_37_0 = _RAND_660[1:0];
- _RAND_661 = {1{`RANDOM}};
- history_37_1 = _RAND_661[1:0];
- _RAND_662 = {1{`RANDOM}};
- history_37_2 = _RAND_662[1:0];
- _RAND_663 = {1{`RANDOM}};
- history_37_3 = _RAND_663[1:0];
- _RAND_664 = {1{`RANDOM}};
- history_38_0 = _RAND_664[1:0];
- _RAND_665 = {1{`RANDOM}};
- history_38_1 = _RAND_665[1:0];
- _RAND_666 = {1{`RANDOM}};
- history_38_2 = _RAND_666[1:0];
- _RAND_667 = {1{`RANDOM}};
- history_38_3 = _RAND_667[1:0];
- _RAND_668 = {1{`RANDOM}};
- history_39_0 = _RAND_668[1:0];
- _RAND_669 = {1{`RANDOM}};
- history_39_1 = _RAND_669[1:0];
- _RAND_670 = {1{`RANDOM}};
- history_39_2 = _RAND_670[1:0];
- _RAND_671 = {1{`RANDOM}};
- history_39_3 = _RAND_671[1:0];
- _RAND_672 = {1{`RANDOM}};
- history_40_0 = _RAND_672[1:0];
- _RAND_673 = {1{`RANDOM}};
- history_40_1 = _RAND_673[1:0];
- _RAND_674 = {1{`RANDOM}};
- history_40_2 = _RAND_674[1:0];
- _RAND_675 = {1{`RANDOM}};
- history_40_3 = _RAND_675[1:0];
- _RAND_676 = {1{`RANDOM}};
- history_41_0 = _RAND_676[1:0];
- _RAND_677 = {1{`RANDOM}};
- history_41_1 = _RAND_677[1:0];
- _RAND_678 = {1{`RANDOM}};
- history_41_2 = _RAND_678[1:0];
- _RAND_679 = {1{`RANDOM}};
- history_41_3 = _RAND_679[1:0];
- _RAND_680 = {1{`RANDOM}};
- history_42_0 = _RAND_680[1:0];
- _RAND_681 = {1{`RANDOM}};
- history_42_1 = _RAND_681[1:0];
- _RAND_682 = {1{`RANDOM}};
- history_42_2 = _RAND_682[1:0];
- _RAND_683 = {1{`RANDOM}};
- history_42_3 = _RAND_683[1:0];
- _RAND_684 = {1{`RANDOM}};
- history_43_0 = _RAND_684[1:0];
- _RAND_685 = {1{`RANDOM}};
- history_43_1 = _RAND_685[1:0];
- _RAND_686 = {1{`RANDOM}};
- history_43_2 = _RAND_686[1:0];
- _RAND_687 = {1{`RANDOM}};
- history_43_3 = _RAND_687[1:0];
- _RAND_688 = {1{`RANDOM}};
- history_44_0 = _RAND_688[1:0];
- _RAND_689 = {1{`RANDOM}};
- history_44_1 = _RAND_689[1:0];
- _RAND_690 = {1{`RANDOM}};
- history_44_2 = _RAND_690[1:0];
- _RAND_691 = {1{`RANDOM}};
- history_44_3 = _RAND_691[1:0];
- _RAND_692 = {1{`RANDOM}};
- history_45_0 = _RAND_692[1:0];
- _RAND_693 = {1{`RANDOM}};
- history_45_1 = _RAND_693[1:0];
- _RAND_694 = {1{`RANDOM}};
- history_45_2 = _RAND_694[1:0];
- _RAND_695 = {1{`RANDOM}};
- history_45_3 = _RAND_695[1:0];
- _RAND_696 = {1{`RANDOM}};
- history_46_0 = _RAND_696[1:0];
- _RAND_697 = {1{`RANDOM}};
- history_46_1 = _RAND_697[1:0];
- _RAND_698 = {1{`RANDOM}};
- history_46_2 = _RAND_698[1:0];
- _RAND_699 = {1{`RANDOM}};
- history_46_3 = _RAND_699[1:0];
- _RAND_700 = {1{`RANDOM}};
- history_47_0 = _RAND_700[1:0];
- _RAND_701 = {1{`RANDOM}};
- history_47_1 = _RAND_701[1:0];
- _RAND_702 = {1{`RANDOM}};
- history_47_2 = _RAND_702[1:0];
- _RAND_703 = {1{`RANDOM}};
- history_47_3 = _RAND_703[1:0];
- _RAND_704 = {1{`RANDOM}};
- history_48_0 = _RAND_704[1:0];
- _RAND_705 = {1{`RANDOM}};
- history_48_1 = _RAND_705[1:0];
- _RAND_706 = {1{`RANDOM}};
- history_48_2 = _RAND_706[1:0];
- _RAND_707 = {1{`RANDOM}};
- history_48_3 = _RAND_707[1:0];
- _RAND_708 = {1{`RANDOM}};
- history_49_0 = _RAND_708[1:0];
- _RAND_709 = {1{`RANDOM}};
- history_49_1 = _RAND_709[1:0];
- _RAND_710 = {1{`RANDOM}};
- history_49_2 = _RAND_710[1:0];
- _RAND_711 = {1{`RANDOM}};
- history_49_3 = _RAND_711[1:0];
- _RAND_712 = {1{`RANDOM}};
- history_50_0 = _RAND_712[1:0];
- _RAND_713 = {1{`RANDOM}};
- history_50_1 = _RAND_713[1:0];
- _RAND_714 = {1{`RANDOM}};
- history_50_2 = _RAND_714[1:0];
- _RAND_715 = {1{`RANDOM}};
- history_50_3 = _RAND_715[1:0];
- _RAND_716 = {1{`RANDOM}};
- history_51_0 = _RAND_716[1:0];
- _RAND_717 = {1{`RANDOM}};
- history_51_1 = _RAND_717[1:0];
- _RAND_718 = {1{`RANDOM}};
- history_51_2 = _RAND_718[1:0];
- _RAND_719 = {1{`RANDOM}};
- history_51_3 = _RAND_719[1:0];
- _RAND_720 = {1{`RANDOM}};
- history_52_0 = _RAND_720[1:0];
- _RAND_721 = {1{`RANDOM}};
- history_52_1 = _RAND_721[1:0];
- _RAND_722 = {1{`RANDOM}};
- history_52_2 = _RAND_722[1:0];
- _RAND_723 = {1{`RANDOM}};
- history_52_3 = _RAND_723[1:0];
- _RAND_724 = {1{`RANDOM}};
- history_53_0 = _RAND_724[1:0];
- _RAND_725 = {1{`RANDOM}};
- history_53_1 = _RAND_725[1:0];
- _RAND_726 = {1{`RANDOM}};
- history_53_2 = _RAND_726[1:0];
- _RAND_727 = {1{`RANDOM}};
- history_53_3 = _RAND_727[1:0];
- _RAND_728 = {1{`RANDOM}};
- history_54_0 = _RAND_728[1:0];
- _RAND_729 = {1{`RANDOM}};
- history_54_1 = _RAND_729[1:0];
- _RAND_730 = {1{`RANDOM}};
- history_54_2 = _RAND_730[1:0];
- _RAND_731 = {1{`RANDOM}};
- history_54_3 = _RAND_731[1:0];
- _RAND_732 = {1{`RANDOM}};
- history_55_0 = _RAND_732[1:0];
- _RAND_733 = {1{`RANDOM}};
- history_55_1 = _RAND_733[1:0];
- _RAND_734 = {1{`RANDOM}};
- history_55_2 = _RAND_734[1:0];
- _RAND_735 = {1{`RANDOM}};
- history_55_3 = _RAND_735[1:0];
- _RAND_736 = {1{`RANDOM}};
- history_56_0 = _RAND_736[1:0];
- _RAND_737 = {1{`RANDOM}};
- history_56_1 = _RAND_737[1:0];
- _RAND_738 = {1{`RANDOM}};
- history_56_2 = _RAND_738[1:0];
- _RAND_739 = {1{`RANDOM}};
- history_56_3 = _RAND_739[1:0];
- _RAND_740 = {1{`RANDOM}};
- history_57_0 = _RAND_740[1:0];
- _RAND_741 = {1{`RANDOM}};
- history_57_1 = _RAND_741[1:0];
- _RAND_742 = {1{`RANDOM}};
- history_57_2 = _RAND_742[1:0];
- _RAND_743 = {1{`RANDOM}};
- history_57_3 = _RAND_743[1:0];
- _RAND_744 = {1{`RANDOM}};
- history_58_0 = _RAND_744[1:0];
- _RAND_745 = {1{`RANDOM}};
- history_58_1 = _RAND_745[1:0];
- _RAND_746 = {1{`RANDOM}};
- history_58_2 = _RAND_746[1:0];
- _RAND_747 = {1{`RANDOM}};
- history_58_3 = _RAND_747[1:0];
- _RAND_748 = {1{`RANDOM}};
- history_59_0 = _RAND_748[1:0];
- _RAND_749 = {1{`RANDOM}};
- history_59_1 = _RAND_749[1:0];
- _RAND_750 = {1{`RANDOM}};
- history_59_2 = _RAND_750[1:0];
- _RAND_751 = {1{`RANDOM}};
- history_59_3 = _RAND_751[1:0];
- _RAND_752 = {1{`RANDOM}};
- history_60_0 = _RAND_752[1:0];
- _RAND_753 = {1{`RANDOM}};
- history_60_1 = _RAND_753[1:0];
- _RAND_754 = {1{`RANDOM}};
- history_60_2 = _RAND_754[1:0];
- _RAND_755 = {1{`RANDOM}};
- history_60_3 = _RAND_755[1:0];
- _RAND_756 = {1{`RANDOM}};
- history_61_0 = _RAND_756[1:0];
- _RAND_757 = {1{`RANDOM}};
- history_61_1 = _RAND_757[1:0];
- _RAND_758 = {1{`RANDOM}};
- history_61_2 = _RAND_758[1:0];
- _RAND_759 = {1{`RANDOM}};
- history_61_3 = _RAND_759[1:0];
- _RAND_760 = {1{`RANDOM}};
- history_62_0 = _RAND_760[1:0];
- _RAND_761 = {1{`RANDOM}};
- history_62_1 = _RAND_761[1:0];
- _RAND_762 = {1{`RANDOM}};
- history_62_2 = _RAND_762[1:0];
- _RAND_763 = {1{`RANDOM}};
- history_62_3 = _RAND_763[1:0];
- _RAND_764 = {1{`RANDOM}};
- history_63_0 = _RAND_764[1:0];
- _RAND_765 = {1{`RANDOM}};
- history_63_1 = _RAND_765[1:0];
- _RAND_766 = {1{`RANDOM}};
- history_63_2 = _RAND_766[1:0];
- _RAND_767 = {1{`RANDOM}};
- history_63_3 = _RAND_767[1:0];
- _RAND_768 = {1{`RANDOM}};
- axivalid = _RAND_768[0:0];
- _RAND_769 = {1{`RANDOM}};
- axiready = _RAND_769[0:0];
- _RAND_770 = {1{`RANDOM}};
- axiaddr = _RAND_770[31:0];
- _RAND_771 = {1{`RANDOM}};
- replaceIdReg = _RAND_771[7:0];
- _RAND_772 = {1{`RANDOM}};
- addrLatchActive = _RAND_772[0:0];
- _RAND_773 = {1{`RANDOM}};
- addrLatchData = _RAND_773[31:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- valid_0 = 1'h0;
- end
- if (reset) begin
- valid_1 = 1'h0;
- end
- if (reset) begin
- valid_2 = 1'h0;
- end
- if (reset) begin
- valid_3 = 1'h0;
- end
- if (reset) begin
- valid_4 = 1'h0;
- end
- if (reset) begin
- valid_5 = 1'h0;
- end
- if (reset) begin
- valid_6 = 1'h0;
- end
- if (reset) begin
- valid_7 = 1'h0;
- end
- if (reset) begin
- valid_8 = 1'h0;
- end
- if (reset) begin
- valid_9 = 1'h0;
- end
- if (reset) begin
- valid_10 = 1'h0;
- end
- if (reset) begin
- valid_11 = 1'h0;
- end
- if (reset) begin
- valid_12 = 1'h0;
- end
- if (reset) begin
- valid_13 = 1'h0;
- end
- if (reset) begin
- valid_14 = 1'h0;
- end
- if (reset) begin
- valid_15 = 1'h0;
- end
- if (reset) begin
- valid_16 = 1'h0;
- end
- if (reset) begin
- valid_17 = 1'h0;
- end
- if (reset) begin
- valid_18 = 1'h0;
- end
- if (reset) begin
- valid_19 = 1'h0;
- end
- if (reset) begin
- valid_20 = 1'h0;
- end
- if (reset) begin
- valid_21 = 1'h0;
- end
- if (reset) begin
- valid_22 = 1'h0;
- end
- if (reset) begin
- valid_23 = 1'h0;
- end
- if (reset) begin
- valid_24 = 1'h0;
- end
- if (reset) begin
- valid_25 = 1'h0;
- end
- if (reset) begin
- valid_26 = 1'h0;
- end
- if (reset) begin
- valid_27 = 1'h0;
- end
- if (reset) begin
- valid_28 = 1'h0;
- end
- if (reset) begin
- valid_29 = 1'h0;
- end
- if (reset) begin
- valid_30 = 1'h0;
- end
- if (reset) begin
- valid_31 = 1'h0;
- end
- if (reset) begin
- valid_32 = 1'h0;
- end
- if (reset) begin
- valid_33 = 1'h0;
- end
- if (reset) begin
- valid_34 = 1'h0;
- end
- if (reset) begin
- valid_35 = 1'h0;
- end
- if (reset) begin
- valid_36 = 1'h0;
- end
- if (reset) begin
- valid_37 = 1'h0;
- end
- if (reset) begin
- valid_38 = 1'h0;
- end
- if (reset) begin
- valid_39 = 1'h0;
- end
- if (reset) begin
- valid_40 = 1'h0;
- end
- if (reset) begin
- valid_41 = 1'h0;
- end
- if (reset) begin
- valid_42 = 1'h0;
- end
- if (reset) begin
- valid_43 = 1'h0;
- end
- if (reset) begin
- valid_44 = 1'h0;
- end
- if (reset) begin
- valid_45 = 1'h0;
- end
- if (reset) begin
- valid_46 = 1'h0;
- end
- if (reset) begin
- valid_47 = 1'h0;
- end
- if (reset) begin
- valid_48 = 1'h0;
- end
- if (reset) begin
- valid_49 = 1'h0;
- end
- if (reset) begin
- valid_50 = 1'h0;
- end
- if (reset) begin
- valid_51 = 1'h0;
- end
- if (reset) begin
- valid_52 = 1'h0;
- end
- if (reset) begin
- valid_53 = 1'h0;
- end
- if (reset) begin
- valid_54 = 1'h0;
- end
- if (reset) begin
- valid_55 = 1'h0;
- end
- if (reset) begin
- valid_56 = 1'h0;
- end
- if (reset) begin
- valid_57 = 1'h0;
- end
- if (reset) begin
- valid_58 = 1'h0;
- end
- if (reset) begin
- valid_59 = 1'h0;
- end
- if (reset) begin
- valid_60 = 1'h0;
- end
- if (reset) begin
- valid_61 = 1'h0;
- end
- if (reset) begin
- valid_62 = 1'h0;
- end
- if (reset) begin
- valid_63 = 1'h0;
- end
- if (reset) begin
- valid_64 = 1'h0;
- end
- if (reset) begin
- valid_65 = 1'h0;
- end
- if (reset) begin
- valid_66 = 1'h0;
- end
- if (reset) begin
- valid_67 = 1'h0;
- end
- if (reset) begin
- valid_68 = 1'h0;
- end
- if (reset) begin
- valid_69 = 1'h0;
- end
- if (reset) begin
- valid_70 = 1'h0;
- end
- if (reset) begin
- valid_71 = 1'h0;
- end
- if (reset) begin
- valid_72 = 1'h0;
- end
- if (reset) begin
- valid_73 = 1'h0;
- end
- if (reset) begin
- valid_74 = 1'h0;
- end
- if (reset) begin
- valid_75 = 1'h0;
- end
- if (reset) begin
- valid_76 = 1'h0;
- end
- if (reset) begin
- valid_77 = 1'h0;
- end
- if (reset) begin
- valid_78 = 1'h0;
- end
- if (reset) begin
- valid_79 = 1'h0;
- end
- if (reset) begin
- valid_80 = 1'h0;
- end
- if (reset) begin
- valid_81 = 1'h0;
- end
- if (reset) begin
- valid_82 = 1'h0;
- end
- if (reset) begin
- valid_83 = 1'h0;
- end
- if (reset) begin
- valid_84 = 1'h0;
- end
- if (reset) begin
- valid_85 = 1'h0;
- end
- if (reset) begin
- valid_86 = 1'h0;
- end
- if (reset) begin
- valid_87 = 1'h0;
- end
- if (reset) begin
- valid_88 = 1'h0;
- end
- if (reset) begin
- valid_89 = 1'h0;
- end
- if (reset) begin
- valid_90 = 1'h0;
- end
- if (reset) begin
- valid_91 = 1'h0;
- end
- if (reset) begin
- valid_92 = 1'h0;
- end
- if (reset) begin
- valid_93 = 1'h0;
- end
- if (reset) begin
- valid_94 = 1'h0;
- end
- if (reset) begin
- valid_95 = 1'h0;
- end
- if (reset) begin
- valid_96 = 1'h0;
- end
- if (reset) begin
- valid_97 = 1'h0;
- end
- if (reset) begin
- valid_98 = 1'h0;
- end
- if (reset) begin
- valid_99 = 1'h0;
- end
- if (reset) begin
- valid_100 = 1'h0;
- end
- if (reset) begin
- valid_101 = 1'h0;
- end
- if (reset) begin
- valid_102 = 1'h0;
- end
- if (reset) begin
- valid_103 = 1'h0;
- end
- if (reset) begin
- valid_104 = 1'h0;
- end
- if (reset) begin
- valid_105 = 1'h0;
- end
- if (reset) begin
- valid_106 = 1'h0;
- end
- if (reset) begin
- valid_107 = 1'h0;
- end
- if (reset) begin
- valid_108 = 1'h0;
- end
- if (reset) begin
- valid_109 = 1'h0;
- end
- if (reset) begin
- valid_110 = 1'h0;
- end
- if (reset) begin
- valid_111 = 1'h0;
- end
- if (reset) begin
- valid_112 = 1'h0;
- end
- if (reset) begin
- valid_113 = 1'h0;
- end
- if (reset) begin
- valid_114 = 1'h0;
- end
- if (reset) begin
- valid_115 = 1'h0;
- end
- if (reset) begin
- valid_116 = 1'h0;
- end
- if (reset) begin
- valid_117 = 1'h0;
- end
- if (reset) begin
- valid_118 = 1'h0;
- end
- if (reset) begin
- valid_119 = 1'h0;
- end
- if (reset) begin
- valid_120 = 1'h0;
- end
- if (reset) begin
- valid_121 = 1'h0;
- end
- if (reset) begin
- valid_122 = 1'h0;
- end
- if (reset) begin
- valid_123 = 1'h0;
- end
- if (reset) begin
- valid_124 = 1'h0;
- end
- if (reset) begin
- valid_125 = 1'h0;
- end
- if (reset) begin
- valid_126 = 1'h0;
- end
- if (reset) begin
- valid_127 = 1'h0;
- end
- if (reset) begin
- valid_128 = 1'h0;
- end
- if (reset) begin
- valid_129 = 1'h0;
- end
- if (reset) begin
- valid_130 = 1'h0;
- end
- if (reset) begin
- valid_131 = 1'h0;
- end
- if (reset) begin
- valid_132 = 1'h0;
- end
- if (reset) begin
- valid_133 = 1'h0;
- end
- if (reset) begin
- valid_134 = 1'h0;
- end
- if (reset) begin
- valid_135 = 1'h0;
- end
- if (reset) begin
- valid_136 = 1'h0;
- end
- if (reset) begin
- valid_137 = 1'h0;
- end
- if (reset) begin
- valid_138 = 1'h0;
- end
- if (reset) begin
- valid_139 = 1'h0;
- end
- if (reset) begin
- valid_140 = 1'h0;
- end
- if (reset) begin
- valid_141 = 1'h0;
- end
- if (reset) begin
- valid_142 = 1'h0;
- end
- if (reset) begin
- valid_143 = 1'h0;
- end
- if (reset) begin
- valid_144 = 1'h0;
- end
- if (reset) begin
- valid_145 = 1'h0;
- end
- if (reset) begin
- valid_146 = 1'h0;
- end
- if (reset) begin
- valid_147 = 1'h0;
- end
- if (reset) begin
- valid_148 = 1'h0;
- end
- if (reset) begin
- valid_149 = 1'h0;
- end
- if (reset) begin
- valid_150 = 1'h0;
- end
- if (reset) begin
- valid_151 = 1'h0;
- end
- if (reset) begin
- valid_152 = 1'h0;
- end
- if (reset) begin
- valid_153 = 1'h0;
- end
- if (reset) begin
- valid_154 = 1'h0;
- end
- if (reset) begin
- valid_155 = 1'h0;
- end
- if (reset) begin
- valid_156 = 1'h0;
- end
- if (reset) begin
- valid_157 = 1'h0;
- end
- if (reset) begin
- valid_158 = 1'h0;
- end
- if (reset) begin
- valid_159 = 1'h0;
- end
- if (reset) begin
- valid_160 = 1'h0;
- end
- if (reset) begin
- valid_161 = 1'h0;
- end
- if (reset) begin
- valid_162 = 1'h0;
- end
- if (reset) begin
- valid_163 = 1'h0;
- end
- if (reset) begin
- valid_164 = 1'h0;
- end
- if (reset) begin
- valid_165 = 1'h0;
- end
- if (reset) begin
- valid_166 = 1'h0;
- end
- if (reset) begin
- valid_167 = 1'h0;
- end
- if (reset) begin
- valid_168 = 1'h0;
- end
- if (reset) begin
- valid_169 = 1'h0;
- end
- if (reset) begin
- valid_170 = 1'h0;
- end
- if (reset) begin
- valid_171 = 1'h0;
- end
- if (reset) begin
- valid_172 = 1'h0;
- end
- if (reset) begin
- valid_173 = 1'h0;
- end
- if (reset) begin
- valid_174 = 1'h0;
- end
- if (reset) begin
- valid_175 = 1'h0;
- end
- if (reset) begin
- valid_176 = 1'h0;
- end
- if (reset) begin
- valid_177 = 1'h0;
- end
- if (reset) begin
- valid_178 = 1'h0;
- end
- if (reset) begin
- valid_179 = 1'h0;
- end
- if (reset) begin
- valid_180 = 1'h0;
- end
- if (reset) begin
- valid_181 = 1'h0;
- end
- if (reset) begin
- valid_182 = 1'h0;
- end
- if (reset) begin
- valid_183 = 1'h0;
- end
- if (reset) begin
- valid_184 = 1'h0;
- end
- if (reset) begin
- valid_185 = 1'h0;
- end
- if (reset) begin
- valid_186 = 1'h0;
- end
- if (reset) begin
- valid_187 = 1'h0;
- end
- if (reset) begin
- valid_188 = 1'h0;
- end
- if (reset) begin
- valid_189 = 1'h0;
- end
- if (reset) begin
- valid_190 = 1'h0;
- end
- if (reset) begin
- valid_191 = 1'h0;
- end
- if (reset) begin
- valid_192 = 1'h0;
- end
- if (reset) begin
- valid_193 = 1'h0;
- end
- if (reset) begin
- valid_194 = 1'h0;
- end
- if (reset) begin
- valid_195 = 1'h0;
- end
- if (reset) begin
- valid_196 = 1'h0;
- end
- if (reset) begin
- valid_197 = 1'h0;
- end
- if (reset) begin
- valid_198 = 1'h0;
- end
- if (reset) begin
- valid_199 = 1'h0;
- end
- if (reset) begin
- valid_200 = 1'h0;
- end
- if (reset) begin
- valid_201 = 1'h0;
- end
- if (reset) begin
- valid_202 = 1'h0;
- end
- if (reset) begin
- valid_203 = 1'h0;
- end
- if (reset) begin
- valid_204 = 1'h0;
- end
- if (reset) begin
- valid_205 = 1'h0;
- end
- if (reset) begin
- valid_206 = 1'h0;
- end
- if (reset) begin
- valid_207 = 1'h0;
- end
- if (reset) begin
- valid_208 = 1'h0;
- end
- if (reset) begin
- valid_209 = 1'h0;
- end
- if (reset) begin
- valid_210 = 1'h0;
- end
- if (reset) begin
- valid_211 = 1'h0;
- end
- if (reset) begin
- valid_212 = 1'h0;
- end
- if (reset) begin
- valid_213 = 1'h0;
- end
- if (reset) begin
- valid_214 = 1'h0;
- end
- if (reset) begin
- valid_215 = 1'h0;
- end
- if (reset) begin
- valid_216 = 1'h0;
- end
- if (reset) begin
- valid_217 = 1'h0;
- end
- if (reset) begin
- valid_218 = 1'h0;
- end
- if (reset) begin
- valid_219 = 1'h0;
- end
- if (reset) begin
- valid_220 = 1'h0;
- end
- if (reset) begin
- valid_221 = 1'h0;
- end
- if (reset) begin
- valid_222 = 1'h0;
- end
- if (reset) begin
- valid_223 = 1'h0;
- end
- if (reset) begin
- valid_224 = 1'h0;
- end
- if (reset) begin
- valid_225 = 1'h0;
- end
- if (reset) begin
- valid_226 = 1'h0;
- end
- if (reset) begin
- valid_227 = 1'h0;
- end
- if (reset) begin
- valid_228 = 1'h0;
- end
- if (reset) begin
- valid_229 = 1'h0;
- end
- if (reset) begin
- valid_230 = 1'h0;
- end
- if (reset) begin
- valid_231 = 1'h0;
- end
- if (reset) begin
- valid_232 = 1'h0;
- end
- if (reset) begin
- valid_233 = 1'h0;
- end
- if (reset) begin
- valid_234 = 1'h0;
- end
- if (reset) begin
- valid_235 = 1'h0;
- end
- if (reset) begin
- valid_236 = 1'h0;
- end
- if (reset) begin
- valid_237 = 1'h0;
- end
- if (reset) begin
- valid_238 = 1'h0;
- end
- if (reset) begin
- valid_239 = 1'h0;
- end
- if (reset) begin
- valid_240 = 1'h0;
- end
- if (reset) begin
- valid_241 = 1'h0;
- end
- if (reset) begin
- valid_242 = 1'h0;
- end
- if (reset) begin
- valid_243 = 1'h0;
- end
- if (reset) begin
- valid_244 = 1'h0;
- end
- if (reset) begin
- valid_245 = 1'h0;
- end
- if (reset) begin
- valid_246 = 1'h0;
- end
- if (reset) begin
- valid_247 = 1'h0;
- end
- if (reset) begin
- valid_248 = 1'h0;
- end
- if (reset) begin
- valid_249 = 1'h0;
- end
- if (reset) begin
- valid_250 = 1'h0;
- end
- if (reset) begin
- valid_251 = 1'h0;
- end
- if (reset) begin
- valid_252 = 1'h0;
- end
- if (reset) begin
- valid_253 = 1'h0;
- end
- if (reset) begin
- valid_254 = 1'h0;
- end
- if (reset) begin
- valid_255 = 1'h0;
- end
- if (reset) begin
- axivalid = 1'h0;
- end
- if (reset) begin
- axiready = 1'h0;
- end
- if (reset) begin
- addrLatchActive = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Slice_8(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input io_in_bits_cwrite,
- input [31:0] io_in_bits_caddr,
- input [6:0] io_in_bits_cid,
- input io_out_ready,
- output io_out_valid,
- output io_out_bits_cwrite,
- output [31:0] io_out_bits_caddr,
- output [6:0] io_out_bits_cid
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [31:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
-`endif // RANDOMIZE_REG_INIT
- reg [1:0] ipos; // @[Slice.scala 38:21]
- reg [1:0] opos; // @[Slice.scala 39:21]
- reg mem_0_cwrite; // @[Slice.scala 41:16]
- reg [31:0] mem_0_caddr; // @[Slice.scala 41:16]
- reg [6:0] mem_0_cid; // @[Slice.scala 41:16]
- reg mem_1_cwrite; // @[Slice.scala 41:16]
- reg [31:0] mem_1_caddr; // @[Slice.scala 41:16]
- reg [6:0] mem_1_cid; // @[Slice.scala 41:16]
- wire empty = ipos == opos; // @[Slice.scala 43:20]
- wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 45:28]
- wire ovalid = io_out_valid & io_out_ready; // @[Slice.scala 46:29]
- wire [1:0] _ipos_T_1 = ipos + 2'h1; // @[Slice.scala 49:18]
- wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 53:18]
- wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 61:36]
- wire _io_in_ready_T = ~full; // @[Slice.scala 65:22]
- wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 72:18]
- wire _T_5 = ivalid & ovalid; // @[Slice.scala 73:18]
- wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 73:28]
- wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 72:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 78:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 77:39]
- assign io_in_ready = ~full; // @[Slice.scala 65:22]
- assign io_out_valid = ~empty; // @[Slice.scala 102:21]
- assign io_out_bits_cwrite = mem_0_cwrite; // @[Slice.scala 103:18]
- assign io_out_bits_caddr = mem_0_caddr; // @[Slice.scala 103:18]
- assign io_out_bits_cid = mem_0_cid; // @[Slice.scala 103:18]
- always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_cwrite <= io_in_bits_cwrite; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_cwrite <= mem_1_cwrite; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_caddr <= io_in_bits_caddr; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_caddr <= mem_1_caddr; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_cid <= io_in_bits_cid; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_cid <= mem_1_cid; // @[Slice.scala 69:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_cwrite <= io_in_bits_cwrite; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_caddr <= io_in_bits_caddr; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_cid <= io_in_bits_cid; // @[Slice.scala 79:14]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 48:17]
- ipos <= 2'h0; // @[Slice.scala 49:10]
- end else if (ivalid) begin // @[Slice.scala 38:21]
- ipos <= _ipos_T_1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 52:17]
- opos <= 2'h0; // @[Slice.scala 53:10]
- end else if (ovalid) begin // @[Slice.scala 39:21]
- opos <= _opos_T_1;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- ipos = _RAND_0[1:0];
- _RAND_1 = {1{`RANDOM}};
- opos = _RAND_1[1:0];
- _RAND_2 = {1{`RANDOM}};
- mem_0_cwrite = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- mem_0_caddr = _RAND_3[31:0];
- _RAND_4 = {1{`RANDOM}};
- mem_0_cid = _RAND_4[6:0];
- _RAND_5 = {1{`RANDOM}};
- mem_1_cwrite = _RAND_5[0:0];
- _RAND_6 = {1{`RANDOM}};
- mem_1_caddr = _RAND_6[31:0];
- _RAND_7 = {1{`RANDOM}};
- mem_1_cid = _RAND_7[6:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- ipos = 2'h0;
- end
- if (reset) begin
- opos = 2'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Slice_9(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input [255:0] io_in_bits_wdata,
- input [31:0] io_in_bits_wmask,
- input io_out_ready,
- output io_out_valid,
- output [255:0] io_out_bits_wdata,
- output [31:0] io_out_bits_wmask
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [255:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [255:0] _RAND_4;
- reg [31:0] _RAND_5;
-`endif // RANDOMIZE_REG_INIT
- reg [1:0] ipos; // @[Slice.scala 38:21]
- reg [1:0] opos; // @[Slice.scala 39:21]
- reg [255:0] mem_0_wdata; // @[Slice.scala 41:16]
- reg [31:0] mem_0_wmask; // @[Slice.scala 41:16]
- reg [255:0] mem_1_wdata; // @[Slice.scala 41:16]
- reg [31:0] mem_1_wmask; // @[Slice.scala 41:16]
- wire empty = ipos == opos; // @[Slice.scala 43:20]
- wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 45:28]
- wire ovalid = io_out_valid & io_out_ready; // @[Slice.scala 46:29]
- wire [1:0] _ipos_T_1 = ipos + 2'h1; // @[Slice.scala 49:18]
- wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 53:18]
- wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 61:36]
- wire _io_in_ready_T = ~full; // @[Slice.scala 65:22]
- wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 72:18]
- wire _T_5 = ivalid & ovalid; // @[Slice.scala 73:18]
- wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 73:28]
- wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 72:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 78:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 77:39]
- assign io_in_ready = ~full; // @[Slice.scala 65:22]
- assign io_out_valid = ~empty; // @[Slice.scala 102:21]
- assign io_out_bits_wdata = mem_0_wdata; // @[Slice.scala 103:18]
- assign io_out_bits_wmask = mem_0_wmask; // @[Slice.scala 103:18]
- always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_wdata <= io_in_bits_wdata; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_wdata <= mem_1_wdata; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_wmask <= io_in_bits_wmask; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_wmask <= mem_1_wmask; // @[Slice.scala 69:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_wdata <= io_in_bits_wdata; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_wmask <= io_in_bits_wmask; // @[Slice.scala 79:14]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 48:17]
- ipos <= 2'h0; // @[Slice.scala 49:10]
- end else if (ivalid) begin // @[Slice.scala 38:21]
- ipos <= _ipos_T_1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 52:17]
- opos <= 2'h0; // @[Slice.scala 53:10]
- end else if (ovalid) begin // @[Slice.scala 39:21]
- opos <= _opos_T_1;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- ipos = _RAND_0[1:0];
- _RAND_1 = {1{`RANDOM}};
- opos = _RAND_1[1:0];
- _RAND_2 = {8{`RANDOM}};
- mem_0_wdata = _RAND_2[255:0];
- _RAND_3 = {1{`RANDOM}};
- mem_0_wmask = _RAND_3[31:0];
- _RAND_4 = {8{`RANDOM}};
- mem_1_wdata = _RAND_4[255:0];
- _RAND_5 = {1{`RANDOM}};
- mem_1_wmask = _RAND_5[31:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- ipos = 2'h0;
- end
- if (reset) begin
- opos = 2'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Slice_10(
- input clock,
- input reset,
- output io_in_ready,
- input io_in_valid,
- input [6:0] io_in_bits_rid,
- input [255:0] io_in_bits_rdata,
- input io_out_ready,
- output io_out_valid,
- output [6:0] io_out_bits_rid,
- output [255:0] io_out_bits_rdata
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [255:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [255:0] _RAND_5;
-`endif // RANDOMIZE_REG_INIT
- reg [1:0] ipos; // @[Slice.scala 38:21]
- reg [1:0] opos; // @[Slice.scala 39:21]
- reg [6:0] mem_0_rid; // @[Slice.scala 41:16]
- reg [255:0] mem_0_rdata; // @[Slice.scala 41:16]
- reg [6:0] mem_1_rid; // @[Slice.scala 41:16]
- reg [255:0] mem_1_rdata; // @[Slice.scala 41:16]
- wire empty = ipos == opos; // @[Slice.scala 43:20]
- wire ivalid = io_in_valid & io_in_ready; // @[Slice.scala 45:28]
- wire ovalid = io_out_valid & io_out_ready; // @[Slice.scala 46:29]
- wire [1:0] _ipos_T_1 = ipos + 2'h1; // @[Slice.scala 49:18]
- wire [1:0] _opos_T_1 = opos + 2'h1; // @[Slice.scala 53:18]
- wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; // @[Slice.scala 61:36]
- wire _io_in_ready_T = ~full; // @[Slice.scala 65:22]
- wire _T_3 = ivalid & ~ovalid; // @[Slice.scala 72:18]
- wire _T_5 = ivalid & ovalid; // @[Slice.scala 73:18]
- wire _T_7 = ivalid & ovalid & _io_in_ready_T; // @[Slice.scala 73:28]
- wire _T_8 = ivalid & ~ovalid & empty | _T_7; // @[Slice.scala 72:38]
- wire _T_14 = _T_5 & full; // @[Slice.scala 78:28]
- wire _T_15 = _T_3 & ~empty | _T_14; // @[Slice.scala 77:39]
- assign io_in_ready = ~full; // @[Slice.scala 65:22]
- assign io_out_valid = ~empty; // @[Slice.scala 102:21]
- assign io_out_bits_rid = mem_0_rid; // @[Slice.scala 103:18]
- assign io_out_bits_rdata = mem_0_rdata; // @[Slice.scala 103:18]
- always @(posedge clock) begin
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_rid <= io_in_bits_rid; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_rid <= mem_1_rid; // @[Slice.scala 69:14]
- end
- if (_T_8) begin // @[Slice.scala 73:38]
- mem_0_rdata <= io_in_bits_rdata; // @[Slice.scala 74:14]
- end else if (ovalid & full) begin // @[Slice.scala 68:27]
- mem_0_rdata <= mem_1_rdata; // @[Slice.scala 69:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_rid <= io_in_bits_rid; // @[Slice.scala 79:14]
- end
- if (_T_15) begin // @[Slice.scala 78:37]
- mem_1_rdata <= io_in_bits_rdata; // @[Slice.scala 79:14]
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 48:17]
- ipos <= 2'h0; // @[Slice.scala 49:10]
- end else if (ivalid) begin // @[Slice.scala 38:21]
- ipos <= _ipos_T_1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Slice.scala 52:17]
- opos <= 2'h0; // @[Slice.scala 53:10]
- end else if (ovalid) begin // @[Slice.scala 39:21]
- opos <= _opos_T_1;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- ipos = _RAND_0[1:0];
- _RAND_1 = {1{`RANDOM}};
- opos = _RAND_1[1:0];
- _RAND_2 = {1{`RANDOM}};
- mem_0_rid = _RAND_2[6:0];
- _RAND_3 = {8{`RANDOM}};
- mem_0_rdata = _RAND_3[255:0];
- _RAND_4 = {1{`RANDOM}};
- mem_1_rid = _RAND_4[6:0];
- _RAND_5 = {8{`RANDOM}};
- mem_1_rdata = _RAND_5[255:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- ipos = 2'h0;
- end
- if (reset) begin
- opos = 2'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Axi2Sram(
- input clock,
- input reset,
- output io_in0_write_addr_ready,
- input io_in0_write_addr_valid,
- input [31:0] io_in0_write_addr_bits_addr,
- input [6:0] io_in0_write_addr_bits_id,
- output io_in0_write_data_ready,
- input io_in0_write_data_valid,
- input [255:0] io_in0_write_data_bits_data,
- input [31:0] io_in0_write_data_bits_strb,
- output io_in0_write_resp_valid,
- output io_in0_read_addr_ready,
- input io_in0_read_addr_valid,
- input [31:0] io_in0_read_addr_bits_addr,
- input [6:0] io_in0_read_addr_bits_id,
- output io_in0_read_data_valid,
- output [6:0] io_in0_read_data_bits_id,
- output [255:0] io_in0_read_data_bits_data,
- output io_in1_write_addr_ready,
- input io_in1_write_addr_valid,
- input [31:0] io_in1_write_addr_bits_addr,
- output io_in1_write_data_ready,
- input io_in1_write_data_valid,
- input [255:0] io_in1_write_data_bits_data,
- input [31:0] io_in1_write_data_bits_strb,
- output io_in1_read_addr_ready,
- input io_in1_read_addr_valid,
- input [31:0] io_in1_read_addr_bits_addr,
- output io_in1_read_data_valid,
- output [255:0] io_in1_read_data_bits_data,
- output io_in2_write_addr_ready,
- input io_in2_write_addr_valid,
- input [31:0] io_in2_write_addr_bits_addr,
- input [6:0] io_in2_write_addr_bits_id,
- output io_in2_write_data_ready,
- input io_in2_write_data_valid,
- input [255:0] io_in2_write_data_bits_data,
- input [31:0] io_in2_write_data_bits_strb,
- input io_in2_write_resp_ready,
- output io_in2_write_resp_valid,
- output [6:0] io_in2_write_resp_bits_id,
- output io_in2_read_addr_ready,
- input io_in2_read_addr_valid,
- input [31:0] io_in2_read_addr_bits_addr,
- input [6:0] io_in2_read_addr_bits_id,
- input io_in2_read_data_ready,
- output io_in2_read_data_valid,
- output [6:0] io_in2_read_data_bits_id,
- output [255:0] io_in2_read_data_bits_data,
- output io_in3_read_addr_ready,
- input io_in3_read_addr_valid,
- input [31:0] io_in3_read_addr_bits_addr,
- input io_in3_read_data_ready,
- output io_in3_read_data_valid,
- output [255:0] io_in3_read_data_bits_data,
- output io_out_cvalid,
- input io_out_cready,
- output io_out_cwrite,
- output [31:0] io_out_caddr,
- output [6:0] io_out_cid,
- output [255:0] io_out_wdata,
- output [31:0] io_out_wmask,
- input io_out_rvalid,
- input [6:0] io_out_rid,
- input [255:0] io_out_rdata
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
-`endif // RANDOMIZE_REG_INIT
- wire cctrl_clock; // @[Slice.scala 23:11]
- wire cctrl_reset; // @[Slice.scala 23:11]
- wire cctrl_io_in_ready; // @[Slice.scala 23:11]
- wire cctrl_io_in_valid; // @[Slice.scala 23:11]
- wire cctrl_io_in_bits_cwrite; // @[Slice.scala 23:11]
- wire [31:0] cctrl_io_in_bits_caddr; // @[Slice.scala 23:11]
- wire [6:0] cctrl_io_in_bits_cid; // @[Slice.scala 23:11]
- wire cctrl_io_out_ready; // @[Slice.scala 23:11]
- wire cctrl_io_out_valid; // @[Slice.scala 23:11]
- wire cctrl_io_out_bits_cwrite; // @[Slice.scala 23:11]
- wire [31:0] cctrl_io_out_bits_caddr; // @[Slice.scala 23:11]
- wire [6:0] cctrl_io_out_bits_cid; // @[Slice.scala 23:11]
- wire wdata_clock; // @[Slice.scala 23:11]
- wire wdata_reset; // @[Slice.scala 23:11]
- wire wdata_io_in_ready; // @[Slice.scala 23:11]
- wire wdata_io_in_valid; // @[Slice.scala 23:11]
- wire [255:0] wdata_io_in_bits_wdata; // @[Slice.scala 23:11]
- wire [31:0] wdata_io_in_bits_wmask; // @[Slice.scala 23:11]
- wire wdata_io_out_ready; // @[Slice.scala 23:11]
- wire wdata_io_out_valid; // @[Slice.scala 23:11]
- wire [255:0] wdata_io_out_bits_wdata; // @[Slice.scala 23:11]
- wire [31:0] wdata_io_out_bits_wmask; // @[Slice.scala 23:11]
- wire rdata_clock; // @[Slice.scala 23:11]
- wire rdata_reset; // @[Slice.scala 23:11]
- wire rdata_io_in_ready; // @[Slice.scala 23:11]
- wire rdata_io_in_valid; // @[Slice.scala 23:11]
- wire [6:0] rdata_io_in_bits_rid; // @[Slice.scala 23:11]
- wire [255:0] rdata_io_in_bits_rdata; // @[Slice.scala 23:11]
- wire rdata_io_out_ready; // @[Slice.scala 23:11]
- wire rdata_io_out_valid; // @[Slice.scala 23:11]
- wire [6:0] rdata_io_out_bits_rid; // @[Slice.scala 23:11]
- wire [255:0] rdata_io_out_bits_rdata; // @[Slice.scala 23:11]
- wire _cctrl_io_in_valid_T = io_in0_read_addr_valid | io_in1_read_addr_valid; // @[Axi2Sram.scala 115:28]
- wire _cctrl_io_in_valid_T_1 = io_in0_read_addr_valid | io_in1_read_addr_valid | io_in2_read_addr_valid; // @[Axi2Sram.scala 115:35]
- wire _cctrl_io_in_valid_T_2 = io_in0_read_addr_valid | io_in1_read_addr_valid | io_in2_read_addr_valid |
- io_in3_read_addr_valid; // @[Axi2Sram.scala 115:42]
- wire _cctrl_io_in_valid_T_3 = io_in0_read_addr_valid | io_in1_read_addr_valid | io_in2_read_addr_valid |
- io_in3_read_addr_valid | io_in0_write_addr_valid; // @[Axi2Sram.scala 115:49]
- wire _cctrl_io_in_valid_T_4 = io_in0_read_addr_valid | io_in1_read_addr_valid | io_in2_read_addr_valid |
- io_in3_read_addr_valid | io_in0_write_addr_valid | io_in1_write_addr_valid; // @[Axi2Sram.scala 115:56]
- wire _cctrl_io_in_bits_cwrite_T_5 = ~_cctrl_io_in_valid_T_2; // @[Axi2Sram.scala 117:53]
- wire [31:0] _cctrl_io_in_bits_caddr_T = io_in1_write_addr_valid ? io_in1_write_addr_bits_addr :
- io_in2_write_addr_bits_addr; // @[Axi2Sram.scala 126:32]
- wire [31:0] _cctrl_io_in_bits_caddr_T_1 = io_in0_write_addr_valid ? io_in0_write_addr_bits_addr :
- _cctrl_io_in_bits_caddr_T; // @[Axi2Sram.scala 125:32]
- wire [31:0] _cctrl_io_in_bits_caddr_T_2 = io_in3_read_addr_valid ? io_in3_read_addr_bits_addr :
- _cctrl_io_in_bits_caddr_T_1; // @[Axi2Sram.scala 124:32]
- wire [31:0] _cctrl_io_in_bits_caddr_T_3 = io_in2_read_addr_valid ? io_in2_read_addr_bits_addr :
- _cctrl_io_in_bits_caddr_T_2; // @[Axi2Sram.scala 123:32]
- wire [31:0] _cctrl_io_in_bits_caddr_T_4 = io_in1_read_addr_valid ? io_in1_read_addr_bits_addr :
- _cctrl_io_in_bits_caddr_T_3; // @[Axi2Sram.scala 122:32]
- wire [6:0] cctrl_io_in_bits_cid_e = {{1'd0}, io_in0_read_addr_bits_id[5:0]}; // @[Axi2Sram.scala 72:30]
- wire [6:0] _GEN_3 = {{3'd0}, io_in2_read_addr_bits_id[3:0]}; // @[Axi2Sram.scala 78:30]
- wire [6:0] cctrl_io_in_bits_cid_e_2 = 7'h60 | _GEN_3; // @[Axi2Sram.scala 78:30]
- wire [6:0] _cctrl_io_in_bits_cid_T = io_in3_read_addr_valid ? 7'h70 : 7'h0; // @[Axi2Sram.scala 132:30]
- wire [6:0] _cctrl_io_in_bits_cid_T_1 = io_in2_read_addr_valid ? cctrl_io_in_bits_cid_e_2 : _cctrl_io_in_bits_cid_T; // @[Axi2Sram.scala 131:30]
- wire [6:0] _cctrl_io_in_bits_cid_T_2 = io_in1_read_addr_valid ? 7'h40 : _cctrl_io_in_bits_cid_T_1; // @[Axi2Sram.scala 130:30]
- wire [255:0] _wdata_io_in_bits_wdata_T = io_in1_write_addr_valid ? io_in1_write_data_bits_data :
- io_in2_write_data_bits_data; // @[Axi2Sram.scala 136:32]
- wire [31:0] _wdata_io_in_bits_wmask_T = io_in1_write_addr_valid ? io_in1_write_data_bits_strb :
- io_in2_write_data_bits_strb; // @[Axi2Sram.scala 140:32]
- wire rs0 = ~rdata_io_out_bits_rid[6]; // @[Axi2Sram.scala 55:15]
- wire rs1 = rdata_io_out_bits_rid[6:5] == 2'h2; // @[Axi2Sram.scala 57:15]
- wire rs2 = rdata_io_out_bits_rid[6:4] == 3'h6; // @[Axi2Sram.scala 59:15]
- wire rs3 = rdata_io_out_bits_rid[6:4] == 3'h7; // @[Axi2Sram.scala 61:15]
- wire _rdata_io_out_ready_T_2 = rs0 | rs1; // @[Axi2Sram.scala 161:55]
- wire _rdata_io_out_ready_T_3 = rs2 & io_in2_read_data_ready; // @[Axi2Sram.scala 163:29]
- wire _rdata_io_out_ready_T_4 = _rdata_io_out_ready_T_2 | _rdata_io_out_ready_T_3; // @[Axi2Sram.scala 162:55]
- wire _rdata_io_out_ready_T_5 = rs3 & io_in3_read_data_ready; // @[Axi2Sram.scala 164:29]
- reg wrespvalid0; // @[Axi2Sram.scala 188:28]
- reg wrespvalid2; // @[Axi2Sram.scala 190:28]
- reg [6:0] wrespid; // @[Axi2Sram.scala 191:20]
- wire _wrespvalid0_T = io_in0_write_addr_valid & io_in0_write_addr_ready; // @[Axi2Sram.scala 193:42]
- wire _wrespvalid1_T = io_in1_write_addr_valid & io_in1_write_addr_ready; // @[Axi2Sram.scala 194:42]
- wire _wrespvalid2_T = io_in2_write_addr_valid & io_in2_write_addr_ready; // @[Axi2Sram.scala 195:42]
- wire _T_3 = io_in0_read_addr_valid & io_in0_read_addr_ready; // @[Axi2Sram.scala 235:46]
- wire _T_4 = io_in1_read_addr_valid & io_in1_read_addr_ready; // @[Axi2Sram.scala 236:46]
- wire _T_5 = io_in2_read_addr_valid & io_in2_read_addr_ready; // @[Axi2Sram.scala 237:46]
- wire _T_6 = io_in3_read_addr_valid & io_in3_read_addr_ready; // @[Axi2Sram.scala 238:46]
- wire [6:0] _T_10 = {_T_3,_T_4,_T_5,_T_6,_wrespvalid0_T,_wrespvalid1_T,_wrespvalid2_T}; // @[Cat.scala 31:58]
- wire [1:0] _T_18 = _T_10[1] + _T_10[2]; // @[Bitwise.scala 48:55]
- wire [1:0] _GEN_4 = {{1'd0}, _T_10[0]}; // @[Bitwise.scala 48:55]
- wire [2:0] _T_20 = _GEN_4 + _T_18; // @[Bitwise.scala 48:55]
- wire [1:0] _T_22 = _T_10[3] + _T_10[4]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_24 = _T_10[5] + _T_10[6]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_26 = _T_22 + _T_24; // @[Bitwise.scala 48:55]
- wire [2:0] _GEN_5 = {{1'd0}, _T_20[1:0]}; // @[Bitwise.scala 48:55]
- wire [3:0] _T_28 = _GEN_5 + _T_26; // @[Bitwise.scala 48:55]
- wire _T_30 = _T_28[2:0] <= 3'h1; // @[Axi2Sram.scala 241:76]
- wire _T_32 = ~reset; // @[Axi2Sram.scala 235:9]
- wire _T_101 = cctrl_io_in_valid & cctrl_io_in_ready & cctrl_io_in_bits_cwrite; // @[Axi2Sram.scala 260:51]
- wire [3:0] _T_122 = {rs0,rs1,rs2,rs3}; // @[Cat.scala 31:58]
- wire [1:0] _T_127 = _T_122[0] + _T_122[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_129 = _T_122[2] + _T_122[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_131 = _T_127 + _T_129; // @[Bitwise.scala 48:55]
- Slice_8 cctrl ( // @[Slice.scala 23:11]
- .clock(cctrl_clock),
- .reset(cctrl_reset),
- .io_in_ready(cctrl_io_in_ready),
- .io_in_valid(cctrl_io_in_valid),
- .io_in_bits_cwrite(cctrl_io_in_bits_cwrite),
- .io_in_bits_caddr(cctrl_io_in_bits_caddr),
- .io_in_bits_cid(cctrl_io_in_bits_cid),
- .io_out_ready(cctrl_io_out_ready),
- .io_out_valid(cctrl_io_out_valid),
- .io_out_bits_cwrite(cctrl_io_out_bits_cwrite),
- .io_out_bits_caddr(cctrl_io_out_bits_caddr),
- .io_out_bits_cid(cctrl_io_out_bits_cid)
- );
- Slice_9 wdata ( // @[Slice.scala 23:11]
- .clock(wdata_clock),
- .reset(wdata_reset),
- .io_in_ready(wdata_io_in_ready),
- .io_in_valid(wdata_io_in_valid),
- .io_in_bits_wdata(wdata_io_in_bits_wdata),
- .io_in_bits_wmask(wdata_io_in_bits_wmask),
- .io_out_ready(wdata_io_out_ready),
- .io_out_valid(wdata_io_out_valid),
- .io_out_bits_wdata(wdata_io_out_bits_wdata),
- .io_out_bits_wmask(wdata_io_out_bits_wmask)
- );
- Slice_10 rdata ( // @[Slice.scala 23:11]
- .clock(rdata_clock),
- .reset(rdata_reset),
- .io_in_ready(rdata_io_in_ready),
- .io_in_valid(rdata_io_in_valid),
- .io_in_bits_rid(rdata_io_in_bits_rid),
- .io_in_bits_rdata(rdata_io_in_bits_rdata),
- .io_out_ready(rdata_io_out_ready),
- .io_out_valid(rdata_io_out_valid),
- .io_out_bits_rid(rdata_io_out_bits_rid),
- .io_out_bits_rdata(rdata_io_out_bits_rdata)
- );
- assign io_in0_write_addr_ready = cctrl_io_in_ready & _cctrl_io_in_bits_cwrite_T_5; // @[Axi2Sram.scala 147:48]
- assign io_in0_write_data_ready = io_in0_write_addr_ready; // @[Axi2Sram.scala 150:27]
- assign io_in0_write_resp_valid = wrespvalid0; // @[Axi2Sram.scala 205:27]
- assign io_in0_read_addr_ready = cctrl_io_in_ready; // @[Axi2Sram.scala 143:27]
- assign io_in0_read_data_valid = rs0 & rdata_io_out_valid; // @[Axi2Sram.scala 166:33]
- assign io_in0_read_data_bits_id = rdata_io_out_bits_rid; // @[Axi2Sram.scala 176:28]
- assign io_in0_read_data_bits_data = rdata_io_out_bits_rdata; // @[Axi2Sram.scala 171:30]
- assign io_in1_write_addr_ready = cctrl_io_in_ready & ~_cctrl_io_in_valid_T_3; // @[Axi2Sram.scala 148:48]
- assign io_in1_write_data_ready = io_in1_write_addr_ready; // @[Axi2Sram.scala 151:27]
- assign io_in1_read_addr_ready = cctrl_io_in_ready & ~io_in0_read_addr_valid; // @[Axi2Sram.scala 144:48]
- assign io_in1_read_data_valid = rs1 & rdata_io_out_valid; // @[Axi2Sram.scala 167:33]
- assign io_in1_read_data_bits_data = rdata_io_out_bits_rdata; // @[Axi2Sram.scala 172:30]
- assign io_in2_write_addr_ready = cctrl_io_in_ready & ~_cctrl_io_in_valid_T_4; // @[Axi2Sram.scala 149:48]
- assign io_in2_write_data_ready = io_in2_write_addr_ready; // @[Axi2Sram.scala 152:27]
- assign io_in2_write_resp_valid = wrespvalid2; // @[Axi2Sram.scala 207:27]
- assign io_in2_write_resp_bits_id = wrespid; // @[Axi2Sram.scala 211:29]
- assign io_in2_read_addr_ready = cctrl_io_in_ready & ~_cctrl_io_in_valid_T; // @[Axi2Sram.scala 145:48]
- assign io_in2_read_data_valid = rs2 & rdata_io_out_valid; // @[Axi2Sram.scala 168:33]
- assign io_in2_read_data_bits_id = rdata_io_out_bits_rid; // @[Axi2Sram.scala 178:28]
- assign io_in2_read_data_bits_data = rdata_io_out_bits_rdata; // @[Axi2Sram.scala 173:30]
- assign io_in3_read_addr_ready = cctrl_io_in_ready & ~_cctrl_io_in_valid_T_1; // @[Axi2Sram.scala 146:48]
- assign io_in3_read_data_valid = rs3 & rdata_io_out_valid; // @[Axi2Sram.scala 169:33]
- assign io_in3_read_data_bits_data = rdata_io_out_bits_rdata; // @[Axi2Sram.scala 174:30]
- assign io_out_cvalid = cctrl_io_out_valid; // @[Axi2Sram.scala 219:17]
- assign io_out_cwrite = cctrl_io_out_bits_cwrite; // @[Axi2Sram.scala 220:17]
- assign io_out_caddr = cctrl_io_out_bits_caddr; // @[Axi2Sram.scala 221:17]
- assign io_out_cid = cctrl_io_out_bits_cid; // @[Axi2Sram.scala 222:17]
- assign io_out_wdata = wdata_io_out_bits_wdata; // @[Axi2Sram.scala 226:16]
- assign io_out_wmask = wdata_io_out_bits_wmask; // @[Axi2Sram.scala 227:16]
- assign cctrl_clock = clock;
- assign cctrl_reset = reset;
- assign cctrl_io_in_valid = io_in0_read_addr_valid | io_in1_read_addr_valid | io_in2_read_addr_valid |
- io_in3_read_addr_valid | io_in0_write_addr_valid | io_in1_write_addr_valid | io_in2_write_addr_valid; // @[Axi2Sram.scala 115:63]
- assign cctrl_io_in_bits_cwrite = (io_in0_write_addr_valid | io_in1_write_addr_valid | io_in2_write_addr_valid) & ~
- _cctrl_io_in_valid_T_2; // @[Axi2Sram.scala 117:50]
- assign cctrl_io_in_bits_caddr = io_in0_read_addr_valid ? io_in0_read_addr_bits_addr : _cctrl_io_in_bits_caddr_T_4; // @[Axi2Sram.scala 121:32]
- assign cctrl_io_in_bits_cid = io_in0_read_addr_valid ? cctrl_io_in_bits_cid_e : _cctrl_io_in_bits_cid_T_2; // @[Axi2Sram.scala 129:30]
- assign cctrl_io_out_ready = io_out_cready; // @[Axi2Sram.scala 223:22]
- assign wdata_clock = clock;
- assign wdata_reset = reset;
- assign wdata_io_in_valid = cctrl_io_in_bits_cwrite & cctrl_io_in_ready; // @[Axi2Sram.scala 119:48]
- assign wdata_io_in_bits_wdata = io_in0_write_addr_valid ? io_in0_write_data_bits_data : _wdata_io_in_bits_wdata_T; // @[Axi2Sram.scala 135:32]
- assign wdata_io_in_bits_wmask = io_in0_write_addr_valid ? io_in0_write_data_bits_strb : _wdata_io_in_bits_wmask_T; // @[Axi2Sram.scala 139:32]
- assign wdata_io_out_ready = io_out_cready & cctrl_io_out_valid & cctrl_io_out_bits_cwrite; // @[Axi2Sram.scala 224:61]
- assign rdata_clock = clock;
- assign rdata_reset = reset;
- assign rdata_io_in_valid = io_out_rvalid; // @[Axi2Sram.scala 229:21]
- assign rdata_io_in_bits_rid = io_out_rid; // @[Axi2Sram.scala 230:26]
- assign rdata_io_in_bits_rdata = io_out_rdata; // @[Axi2Sram.scala 231:26]
- assign rdata_io_out_ready = _rdata_io_out_ready_T_4 | _rdata_io_out_ready_T_5; // @[Axi2Sram.scala 163:55]
- always @(posedge clock) begin
- if (_wrespvalid0_T) begin // @[Axi2Sram.scala 197:61]
- wrespid <= io_in0_write_addr_bits_id; // @[Axi2Sram.scala 198:13]
- end else if (_wrespvalid1_T) begin // @[Axi2Sram.scala 199:68]
- wrespid <= 7'h0; // @[Axi2Sram.scala 200:13]
- end else if (_wrespvalid2_T) begin // @[Axi2Sram.scala 201:68]
- wrespid <= io_in2_write_addr_bits_id; // @[Axi2Sram.scala 202:13]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~_T_30) begin
- $fatal; // @[Axi2Sram.scala 235:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~_T_30) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:235 assert(PopCount(Cat(io.in0.read.addr.valid && io.in0.read.addr.ready,\n"
- ); // @[Axi2Sram.scala 235:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_32 & ~(io_in0_write_addr_valid == io_in0_write_data_valid)) begin
- $fatal; // @[Axi2Sram.scala 243:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_32 & ~(io_in0_write_addr_valid == io_in0_write_data_valid)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:243 assert(io.in0.write.addr.valid === io.in0.write.data.valid)\n"
- ); // @[Axi2Sram.scala 243:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_32 & ~(io_in1_write_addr_valid == io_in1_write_data_valid)) begin
- $fatal; // @[Axi2Sram.scala 244:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_32 & ~(io_in1_write_addr_valid == io_in1_write_data_valid)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:244 assert(io.in1.write.addr.valid === io.in1.write.data.valid)\n"
- ); // @[Axi2Sram.scala 244:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_32 & ~(io_in2_write_addr_valid == io_in2_write_data_valid)) begin
- $fatal; // @[Axi2Sram.scala 245:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_32 & ~(io_in2_write_addr_valid == io_in2_write_data_valid)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:245 assert(io.in2.write.addr.valid === io.in2.write.data.valid)\n"
- ); // @[Axi2Sram.scala 245:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_32 & ~(io_in0_write_addr_ready == io_in0_write_data_ready)) begin
- $fatal; // @[Axi2Sram.scala 247:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_32 & ~(io_in0_write_addr_ready == io_in0_write_data_ready)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:247 assert(io.in0.write.addr.ready === io.in0.write.data.ready)\n"
- ); // @[Axi2Sram.scala 247:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_32 & ~(io_in1_write_addr_ready == io_in1_write_data_ready)) begin
- $fatal; // @[Axi2Sram.scala 248:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_32 & ~(io_in1_write_addr_ready == io_in1_write_data_ready)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:248 assert(io.in1.write.addr.ready === io.in1.write.data.ready)\n"
- ); // @[Axi2Sram.scala 248:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_32 & ~(io_in2_write_addr_ready == io_in2_write_data_ready)) begin
- $fatal; // @[Axi2Sram.scala 249:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_32 & ~(io_in2_write_addr_ready == io_in2_write_data_ready)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:249 assert(io.in2.write.addr.ready === io.in2.write.data.ready)\n"
- ); // @[Axi2Sram.scala 249:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_32 & ~(~(io_in2_read_data_valid & ~io_in2_read_data_ready))) begin
- $fatal; // @[Axi2Sram.scala 253:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_32 & ~(~(io_in2_read_data_valid & ~io_in2_read_data_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:253 assert(!(io.in2.read.data.valid && !io.in2.read.data.ready))\n"
- ); // @[Axi2Sram.scala 253:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_32 & ~(~(io_in3_read_data_valid & ~io_in3_read_data_ready))) begin
- $fatal; // @[Axi2Sram.scala 254:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_32 & ~(~(io_in3_read_data_valid & ~io_in3_read_data_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:254 assert(!(io.in3.read.data.valid && !io.in3.read.data.ready))\n"
- ); // @[Axi2Sram.scala 254:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_32 & ~(~(io_in2_write_resp_valid & ~io_in2_write_resp_ready))) begin
- $fatal; // @[Axi2Sram.scala 258:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_32 & ~(~(io_in2_write_resp_valid & ~io_in2_write_resp_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:258 assert(!(io.in2.write.resp.valid && !io.in2.write.resp.ready))\n"
- ); // @[Axi2Sram.scala 258:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_32 & ~(~(cctrl_io_in_valid & cctrl_io_in_ready & cctrl_io_in_bits_cwrite & ~wdata_io_in_valid))) begin
- $fatal; // @[Axi2Sram.scala 260:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_32 & ~(~(cctrl_io_in_valid & cctrl_io_in_ready & cctrl_io_in_bits_cwrite & ~wdata_io_in_valid))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:260 assert(!(cctrl.io.in.valid && cctrl.io.in.ready && cctrl.io.in.bits.cwrite && !wdata.io.in.valid))\n"
- ); // @[Axi2Sram.scala 260:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_32 & ~(~(_T_101 & ~wdata_io_in_ready))) begin
- $fatal; // @[Axi2Sram.scala 261:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_32 & ~(~(_T_101 & ~wdata_io_in_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:261 assert(!(cctrl.io.in.valid && cctrl.io.in.ready && cctrl.io.in.bits.cwrite && !wdata.io.in.ready))\n"
- ); // @[Axi2Sram.scala 261:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_32 & ~(~(rdata_io_in_valid & ~rdata_io_in_ready))) begin
- $fatal; // @[Axi2Sram.scala 263:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_32 & ~(~(rdata_io_in_valid & ~rdata_io_in_ready))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:263 assert(!(rdata.io.in.valid && !rdata.io.in.ready))\n"); // @[Axi2Sram.scala 263:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_32 & ~(_T_131 <= 3'h1)) begin
- $fatal; // @[Axi2Sram.scala 265:9]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_32 & ~(_T_131 <= 3'h1)) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Axi2Sram.scala:265 assert(PopCount(Cat(rs0, rs1, rs2, rs3)) <= 1.U)\n"); // @[Axi2Sram.scala 265:9]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Axi2Sram.scala 193:42]
- wrespvalid0 <= 1'h0;
- end else begin
- wrespvalid0 <= io_in0_write_addr_valid & io_in0_write_addr_ready;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Axi2Sram.scala 195:42]
- wrespvalid2 <= 1'h0;
- end else begin
- wrespvalid2 <= io_in2_write_addr_valid & io_in2_write_addr_ready;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- wrespvalid0 = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- wrespvalid2 = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- wrespid = _RAND_2[6:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- wrespvalid0 = 1'h0;
- end
- if (reset) begin
- wrespvalid2 = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
-module Kelvin(
- input clk_i,
- input rst_ni,
- output cvalid,
- input cready,
- output cwrite,
- output [31:0] caddr,
- output [6:0] cid,
- output [255:0] wdata,
- output [31:0] wmask,
- input rvalid,
- input [6:0] rid,
- input [255:0] rdata,
- input clk_freeze,
- input ml_reset,
- input [31:0] pc_start,
- input volt_sel,
- output finish,
- output host_req,
- output fault,
- output slog_valid,
- output [4:0] slog_addr,
- output [31:0] slog_data
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
-`endif // RANDOMIZE_REG_INIT
- wire cg_clk_i; // @[Kelvin.scala 56:18]
- wire cg_enable; // @[Kelvin.scala 56:18]
- wire cg_clk_o; // @[Kelvin.scala 56:18]
- wire core_clock; // @[Core.scala 23:18]
- wire core_reset; // @[Core.scala 23:18]
- wire [31:0] core_io_csr_in_value_0; // @[Core.scala 23:18]
- wire core_io_halted; // @[Core.scala 23:18]
- wire core_io_fault; // @[Core.scala 23:18]
- wire core_io_ibus_valid; // @[Core.scala 23:18]
- wire core_io_ibus_ready; // @[Core.scala 23:18]
- wire [31:0] core_io_ibus_addr; // @[Core.scala 23:18]
- wire [255:0] core_io_ibus_rdata; // @[Core.scala 23:18]
- wire core_io_dbus_valid; // @[Core.scala 23:18]
- wire core_io_dbus_ready; // @[Core.scala 23:18]
- wire core_io_dbus_write; // @[Core.scala 23:18]
- wire [31:0] core_io_dbus_addr; // @[Core.scala 23:18]
- wire [31:0] core_io_dbus_adrx; // @[Core.scala 23:18]
- wire [5:0] core_io_dbus_size; // @[Core.scala 23:18]
- wire [255:0] core_io_dbus_wdata; // @[Core.scala 23:18]
- wire [31:0] core_io_dbus_wmask; // @[Core.scala 23:18]
- wire [255:0] core_io_dbus_rdata; // @[Core.scala 23:18]
- wire core_io_axi0_write_addr_ready; // @[Core.scala 23:18]
- wire core_io_axi0_write_addr_valid; // @[Core.scala 23:18]
- wire [31:0] core_io_axi0_write_addr_bits_addr; // @[Core.scala 23:18]
- wire [5:0] core_io_axi0_write_addr_bits_id; // @[Core.scala 23:18]
- wire core_io_axi0_write_data_ready; // @[Core.scala 23:18]
- wire core_io_axi0_write_data_valid; // @[Core.scala 23:18]
- wire [255:0] core_io_axi0_write_data_bits_data; // @[Core.scala 23:18]
- wire [31:0] core_io_axi0_write_data_bits_strb; // @[Core.scala 23:18]
- wire core_io_axi0_write_resp_valid; // @[Core.scala 23:18]
- wire core_io_axi0_read_addr_ready; // @[Core.scala 23:18]
- wire core_io_axi0_read_addr_valid; // @[Core.scala 23:18]
- wire [31:0] core_io_axi0_read_addr_bits_addr; // @[Core.scala 23:18]
- wire [5:0] core_io_axi0_read_addr_bits_id; // @[Core.scala 23:18]
- wire core_io_axi0_read_data_valid; // @[Core.scala 23:18]
- wire [5:0] core_io_axi0_read_data_bits_id; // @[Core.scala 23:18]
- wire [255:0] core_io_axi0_read_data_bits_data; // @[Core.scala 23:18]
- wire core_io_axi1_write_addr_ready; // @[Core.scala 23:18]
- wire core_io_axi1_write_addr_valid; // @[Core.scala 23:18]
- wire [31:0] core_io_axi1_write_addr_bits_addr; // @[Core.scala 23:18]
- wire core_io_axi1_write_data_valid; // @[Core.scala 23:18]
- wire [255:0] core_io_axi1_write_data_bits_data; // @[Core.scala 23:18]
- wire [31:0] core_io_axi1_write_data_bits_strb; // @[Core.scala 23:18]
- wire core_io_axi1_read_addr_ready; // @[Core.scala 23:18]
- wire core_io_axi1_read_addr_valid; // @[Core.scala 23:18]
- wire [31:0] core_io_axi1_read_addr_bits_addr; // @[Core.scala 23:18]
- wire core_io_axi1_read_data_valid; // @[Core.scala 23:18]
- wire [255:0] core_io_axi1_read_data_bits_data; // @[Core.scala 23:18]
- wire core_io_iflush_valid; // @[Core.scala 23:18]
- wire core_io_dflush_valid; // @[Core.scala 23:18]
- wire core_io_dflush_ready; // @[Core.scala 23:18]
- wire core_io_dflush_all; // @[Core.scala 23:18]
- wire core_io_slog_valid; // @[Core.scala 23:18]
- wire [4:0] core_io_slog_addr; // @[Core.scala 23:18]
- wire [31:0] core_io_slog_data; // @[Core.scala 23:18]
- wire l1d_clock; // @[L1DCache.scala 24:18]
- wire l1d_reset; // @[L1DCache.scala 24:18]
- wire l1d_io_dbus_valid; // @[L1DCache.scala 24:18]
- wire l1d_io_dbus_ready; // @[L1DCache.scala 24:18]
- wire l1d_io_dbus_write; // @[L1DCache.scala 24:18]
- wire [31:0] l1d_io_dbus_addr; // @[L1DCache.scala 24:18]
- wire [31:0] l1d_io_dbus_adrx; // @[L1DCache.scala 24:18]
- wire [5:0] l1d_io_dbus_size; // @[L1DCache.scala 24:18]
- wire [255:0] l1d_io_dbus_wdata; // @[L1DCache.scala 24:18]
- wire [31:0] l1d_io_dbus_wmask; // @[L1DCache.scala 24:18]
- wire [255:0] l1d_io_dbus_rdata; // @[L1DCache.scala 24:18]
- wire l1d_io_axi_write_addr_ready; // @[L1DCache.scala 24:18]
- wire l1d_io_axi_write_addr_valid; // @[L1DCache.scala 24:18]
- wire [31:0] l1d_io_axi_write_addr_bits_addr; // @[L1DCache.scala 24:18]
- wire [3:0] l1d_io_axi_write_addr_bits_id; // @[L1DCache.scala 24:18]
- wire l1d_io_axi_write_data_ready; // @[L1DCache.scala 24:18]
- wire l1d_io_axi_write_data_valid; // @[L1DCache.scala 24:18]
- wire [255:0] l1d_io_axi_write_data_bits_data; // @[L1DCache.scala 24:18]
- wire [31:0] l1d_io_axi_write_data_bits_strb; // @[L1DCache.scala 24:18]
- wire l1d_io_axi_write_resp_ready; // @[L1DCache.scala 24:18]
- wire l1d_io_axi_write_resp_valid; // @[L1DCache.scala 24:18]
- wire [3:0] l1d_io_axi_write_resp_bits_id; // @[L1DCache.scala 24:18]
- wire l1d_io_axi_read_addr_ready; // @[L1DCache.scala 24:18]
- wire l1d_io_axi_read_addr_valid; // @[L1DCache.scala 24:18]
- wire [31:0] l1d_io_axi_read_addr_bits_addr; // @[L1DCache.scala 24:18]
- wire [3:0] l1d_io_axi_read_addr_bits_id; // @[L1DCache.scala 24:18]
- wire l1d_io_axi_read_data_ready; // @[L1DCache.scala 24:18]
- wire l1d_io_axi_read_data_valid; // @[L1DCache.scala 24:18]
- wire [3:0] l1d_io_axi_read_data_bits_id; // @[L1DCache.scala 24:18]
- wire [255:0] l1d_io_axi_read_data_bits_data; // @[L1DCache.scala 24:18]
- wire l1d_io_flush_valid; // @[L1DCache.scala 24:18]
- wire l1d_io_flush_ready; // @[L1DCache.scala 24:18]
- wire l1d_io_flush_all; // @[L1DCache.scala 24:18]
- wire l1d_io_volt_sel; // @[L1DCache.scala 24:18]
- wire l1i_clock; // @[L1ICache.scala 23:18]
- wire l1i_reset; // @[L1ICache.scala 23:18]
- wire l1i_io_ibus_valid; // @[L1ICache.scala 23:18]
- wire l1i_io_ibus_ready; // @[L1ICache.scala 23:18]
- wire [31:0] l1i_io_ibus_addr; // @[L1ICache.scala 23:18]
- wire [255:0] l1i_io_ibus_rdata; // @[L1ICache.scala 23:18]
- wire l1i_io_flush_valid; // @[L1ICache.scala 23:18]
- wire l1i_io_axi_read_addr_ready; // @[L1ICache.scala 23:18]
- wire l1i_io_axi_read_addr_valid; // @[L1ICache.scala 23:18]
- wire [31:0] l1i_io_axi_read_addr_bits_addr; // @[L1ICache.scala 23:18]
- wire l1i_io_axi_read_data_ready; // @[L1ICache.scala 23:18]
- wire l1i_io_axi_read_data_valid; // @[L1ICache.scala 23:18]
- wire [255:0] l1i_io_axi_read_data_bits_data; // @[L1ICache.scala 23:18]
- wire l1i_io_volt_sel; // @[L1ICache.scala 23:18]
- wire bus_clock; // @[Axi2Sram.scala 23:18]
- wire bus_reset; // @[Axi2Sram.scala 23:18]
- wire bus_io_in0_write_addr_ready; // @[Axi2Sram.scala 23:18]
- wire bus_io_in0_write_addr_valid; // @[Axi2Sram.scala 23:18]
- wire [31:0] bus_io_in0_write_addr_bits_addr; // @[Axi2Sram.scala 23:18]
- wire [6:0] bus_io_in0_write_addr_bits_id; // @[Axi2Sram.scala 23:18]
- wire bus_io_in0_write_data_ready; // @[Axi2Sram.scala 23:18]
- wire bus_io_in0_write_data_valid; // @[Axi2Sram.scala 23:18]
- wire [255:0] bus_io_in0_write_data_bits_data; // @[Axi2Sram.scala 23:18]
- wire [31:0] bus_io_in0_write_data_bits_strb; // @[Axi2Sram.scala 23:18]
- wire bus_io_in0_write_resp_valid; // @[Axi2Sram.scala 23:18]
- wire bus_io_in0_read_addr_ready; // @[Axi2Sram.scala 23:18]
- wire bus_io_in0_read_addr_valid; // @[Axi2Sram.scala 23:18]
- wire [31:0] bus_io_in0_read_addr_bits_addr; // @[Axi2Sram.scala 23:18]
- wire [6:0] bus_io_in0_read_addr_bits_id; // @[Axi2Sram.scala 23:18]
- wire bus_io_in0_read_data_valid; // @[Axi2Sram.scala 23:18]
- wire [6:0] bus_io_in0_read_data_bits_id; // @[Axi2Sram.scala 23:18]
- wire [255:0] bus_io_in0_read_data_bits_data; // @[Axi2Sram.scala 23:18]
- wire bus_io_in1_write_addr_ready; // @[Axi2Sram.scala 23:18]
- wire bus_io_in1_write_addr_valid; // @[Axi2Sram.scala 23:18]
- wire [31:0] bus_io_in1_write_addr_bits_addr; // @[Axi2Sram.scala 23:18]
- wire bus_io_in1_write_data_ready; // @[Axi2Sram.scala 23:18]
- wire bus_io_in1_write_data_valid; // @[Axi2Sram.scala 23:18]
- wire [255:0] bus_io_in1_write_data_bits_data; // @[Axi2Sram.scala 23:18]
- wire [31:0] bus_io_in1_write_data_bits_strb; // @[Axi2Sram.scala 23:18]
- wire bus_io_in1_read_addr_ready; // @[Axi2Sram.scala 23:18]
- wire bus_io_in1_read_addr_valid; // @[Axi2Sram.scala 23:18]
- wire [31:0] bus_io_in1_read_addr_bits_addr; // @[Axi2Sram.scala 23:18]
- wire bus_io_in1_read_data_valid; // @[Axi2Sram.scala 23:18]
- wire [255:0] bus_io_in1_read_data_bits_data; // @[Axi2Sram.scala 23:18]
- wire bus_io_in2_write_addr_ready; // @[Axi2Sram.scala 23:18]
- wire bus_io_in2_write_addr_valid; // @[Axi2Sram.scala 23:18]
- wire [31:0] bus_io_in2_write_addr_bits_addr; // @[Axi2Sram.scala 23:18]
- wire [6:0] bus_io_in2_write_addr_bits_id; // @[Axi2Sram.scala 23:18]
- wire bus_io_in2_write_data_ready; // @[Axi2Sram.scala 23:18]
- wire bus_io_in2_write_data_valid; // @[Axi2Sram.scala 23:18]
- wire [255:0] bus_io_in2_write_data_bits_data; // @[Axi2Sram.scala 23:18]
- wire [31:0] bus_io_in2_write_data_bits_strb; // @[Axi2Sram.scala 23:18]
- wire bus_io_in2_write_resp_ready; // @[Axi2Sram.scala 23:18]
- wire bus_io_in2_write_resp_valid; // @[Axi2Sram.scala 23:18]
- wire [6:0] bus_io_in2_write_resp_bits_id; // @[Axi2Sram.scala 23:18]
- wire bus_io_in2_read_addr_ready; // @[Axi2Sram.scala 23:18]
- wire bus_io_in2_read_addr_valid; // @[Axi2Sram.scala 23:18]
- wire [31:0] bus_io_in2_read_addr_bits_addr; // @[Axi2Sram.scala 23:18]
- wire [6:0] bus_io_in2_read_addr_bits_id; // @[Axi2Sram.scala 23:18]
- wire bus_io_in2_read_data_ready; // @[Axi2Sram.scala 23:18]
- wire bus_io_in2_read_data_valid; // @[Axi2Sram.scala 23:18]
- wire [6:0] bus_io_in2_read_data_bits_id; // @[Axi2Sram.scala 23:18]
- wire [255:0] bus_io_in2_read_data_bits_data; // @[Axi2Sram.scala 23:18]
- wire bus_io_in3_read_addr_ready; // @[Axi2Sram.scala 23:18]
- wire bus_io_in3_read_addr_valid; // @[Axi2Sram.scala 23:18]
- wire [31:0] bus_io_in3_read_addr_bits_addr; // @[Axi2Sram.scala 23:18]
- wire bus_io_in3_read_data_ready; // @[Axi2Sram.scala 23:18]
- wire bus_io_in3_read_data_valid; // @[Axi2Sram.scala 23:18]
- wire [255:0] bus_io_in3_read_data_bits_data; // @[Axi2Sram.scala 23:18]
- wire bus_io_out_cvalid; // @[Axi2Sram.scala 23:18]
- wire bus_io_out_cready; // @[Axi2Sram.scala 23:18]
- wire bus_io_out_cwrite; // @[Axi2Sram.scala 23:18]
- wire [31:0] bus_io_out_caddr; // @[Axi2Sram.scala 23:18]
- wire [6:0] bus_io_out_cid; // @[Axi2Sram.scala 23:18]
- wire [255:0] bus_io_out_wdata; // @[Axi2Sram.scala 23:18]
- wire [31:0] bus_io_out_wmask; // @[Axi2Sram.scala 23:18]
- wire bus_io_out_rvalid; // @[Axi2Sram.scala 23:18]
- wire [6:0] bus_io_out_rid; // @[Axi2Sram.scala 23:18]
- wire [255:0] bus_io_out_rdata; // @[Axi2Sram.scala 23:18]
- wire rst_i = ~rst_ni | ml_reset; // @[Kelvin.scala 70:58]
- reg rst_q1; // @[Kelvin.scala 74:25]
- reg rst_q2; // @[Kelvin.scala 75:25]
- ClockGate cg ( // @[Kelvin.scala 56:18]
- .clk_i(cg_clk_i),
- .enable(cg_enable),
- .clk_o(cg_clk_o)
- );
- Core core ( // @[Core.scala 23:18]
- .clock(core_clock),
- .reset(core_reset),
- .io_csr_in_value_0(core_io_csr_in_value_0),
- .io_halted(core_io_halted),
- .io_fault(core_io_fault),
- .io_ibus_valid(core_io_ibus_valid),
- .io_ibus_ready(core_io_ibus_ready),
- .io_ibus_addr(core_io_ibus_addr),
- .io_ibus_rdata(core_io_ibus_rdata),
- .io_dbus_valid(core_io_dbus_valid),
- .io_dbus_ready(core_io_dbus_ready),
- .io_dbus_write(core_io_dbus_write),
- .io_dbus_addr(core_io_dbus_addr),
- .io_dbus_adrx(core_io_dbus_adrx),
- .io_dbus_size(core_io_dbus_size),
- .io_dbus_wdata(core_io_dbus_wdata),
- .io_dbus_wmask(core_io_dbus_wmask),
- .io_dbus_rdata(core_io_dbus_rdata),
- .io_axi0_write_addr_ready(core_io_axi0_write_addr_ready),
- .io_axi0_write_addr_valid(core_io_axi0_write_addr_valid),
- .io_axi0_write_addr_bits_addr(core_io_axi0_write_addr_bits_addr),
- .io_axi0_write_addr_bits_id(core_io_axi0_write_addr_bits_id),
- .io_axi0_write_data_ready(core_io_axi0_write_data_ready),
- .io_axi0_write_data_valid(core_io_axi0_write_data_valid),
- .io_axi0_write_data_bits_data(core_io_axi0_write_data_bits_data),
- .io_axi0_write_data_bits_strb(core_io_axi0_write_data_bits_strb),
- .io_axi0_write_resp_valid(core_io_axi0_write_resp_valid),
- .io_axi0_read_addr_ready(core_io_axi0_read_addr_ready),
- .io_axi0_read_addr_valid(core_io_axi0_read_addr_valid),
- .io_axi0_read_addr_bits_addr(core_io_axi0_read_addr_bits_addr),
- .io_axi0_read_addr_bits_id(core_io_axi0_read_addr_bits_id),
- .io_axi0_read_data_valid(core_io_axi0_read_data_valid),
- .io_axi0_read_data_bits_id(core_io_axi0_read_data_bits_id),
- .io_axi0_read_data_bits_data(core_io_axi0_read_data_bits_data),
- .io_axi1_write_addr_ready(core_io_axi1_write_addr_ready),
- .io_axi1_write_addr_valid(core_io_axi1_write_addr_valid),
- .io_axi1_write_addr_bits_addr(core_io_axi1_write_addr_bits_addr),
- .io_axi1_write_data_valid(core_io_axi1_write_data_valid),
- .io_axi1_write_data_bits_data(core_io_axi1_write_data_bits_data),
- .io_axi1_write_data_bits_strb(core_io_axi1_write_data_bits_strb),
- .io_axi1_read_addr_ready(core_io_axi1_read_addr_ready),
- .io_axi1_read_addr_valid(core_io_axi1_read_addr_valid),
- .io_axi1_read_addr_bits_addr(core_io_axi1_read_addr_bits_addr),
- .io_axi1_read_data_valid(core_io_axi1_read_data_valid),
- .io_axi1_read_data_bits_data(core_io_axi1_read_data_bits_data),
- .io_iflush_valid(core_io_iflush_valid),
- .io_dflush_valid(core_io_dflush_valid),
- .io_dflush_ready(core_io_dflush_ready),
- .io_dflush_all(core_io_dflush_all),
- .io_slog_valid(core_io_slog_valid),
- .io_slog_addr(core_io_slog_addr),
- .io_slog_data(core_io_slog_data)
- );
- L1DCache l1d ( // @[L1DCache.scala 24:18]
- .clock(l1d_clock),
- .reset(l1d_reset),
- .io_dbus_valid(l1d_io_dbus_valid),
- .io_dbus_ready(l1d_io_dbus_ready),
- .io_dbus_write(l1d_io_dbus_write),
- .io_dbus_addr(l1d_io_dbus_addr),
- .io_dbus_adrx(l1d_io_dbus_adrx),
- .io_dbus_size(l1d_io_dbus_size),
- .io_dbus_wdata(l1d_io_dbus_wdata),
- .io_dbus_wmask(l1d_io_dbus_wmask),
- .io_dbus_rdata(l1d_io_dbus_rdata),
- .io_axi_write_addr_ready(l1d_io_axi_write_addr_ready),
- .io_axi_write_addr_valid(l1d_io_axi_write_addr_valid),
- .io_axi_write_addr_bits_addr(l1d_io_axi_write_addr_bits_addr),
- .io_axi_write_addr_bits_id(l1d_io_axi_write_addr_bits_id),
- .io_axi_write_data_ready(l1d_io_axi_write_data_ready),
- .io_axi_write_data_valid(l1d_io_axi_write_data_valid),
- .io_axi_write_data_bits_data(l1d_io_axi_write_data_bits_data),
- .io_axi_write_data_bits_strb(l1d_io_axi_write_data_bits_strb),
- .io_axi_write_resp_ready(l1d_io_axi_write_resp_ready),
- .io_axi_write_resp_valid(l1d_io_axi_write_resp_valid),
- .io_axi_write_resp_bits_id(l1d_io_axi_write_resp_bits_id),
- .io_axi_read_addr_ready(l1d_io_axi_read_addr_ready),
- .io_axi_read_addr_valid(l1d_io_axi_read_addr_valid),
- .io_axi_read_addr_bits_addr(l1d_io_axi_read_addr_bits_addr),
- .io_axi_read_addr_bits_id(l1d_io_axi_read_addr_bits_id),
- .io_axi_read_data_ready(l1d_io_axi_read_data_ready),
- .io_axi_read_data_valid(l1d_io_axi_read_data_valid),
- .io_axi_read_data_bits_id(l1d_io_axi_read_data_bits_id),
- .io_axi_read_data_bits_data(l1d_io_axi_read_data_bits_data),
- .io_flush_valid(l1d_io_flush_valid),
- .io_flush_ready(l1d_io_flush_ready),
- .io_flush_all(l1d_io_flush_all),
- .io_volt_sel(l1d_io_volt_sel)
- );
- L1ICache l1i ( // @[L1ICache.scala 23:18]
- .clock(l1i_clock),
- .reset(l1i_reset),
- .io_ibus_valid(l1i_io_ibus_valid),
- .io_ibus_ready(l1i_io_ibus_ready),
- .io_ibus_addr(l1i_io_ibus_addr),
- .io_ibus_rdata(l1i_io_ibus_rdata),
- .io_flush_valid(l1i_io_flush_valid),
- .io_axi_read_addr_ready(l1i_io_axi_read_addr_ready),
- .io_axi_read_addr_valid(l1i_io_axi_read_addr_valid),
- .io_axi_read_addr_bits_addr(l1i_io_axi_read_addr_bits_addr),
- .io_axi_read_data_ready(l1i_io_axi_read_data_ready),
- .io_axi_read_data_valid(l1i_io_axi_read_data_valid),
- .io_axi_read_data_bits_data(l1i_io_axi_read_data_bits_data),
- .io_volt_sel(l1i_io_volt_sel)
- );
- Axi2Sram bus ( // @[Axi2Sram.scala 23:18]
- .clock(bus_clock),
- .reset(bus_reset),
- .io_in0_write_addr_ready(bus_io_in0_write_addr_ready),
- .io_in0_write_addr_valid(bus_io_in0_write_addr_valid),
- .io_in0_write_addr_bits_addr(bus_io_in0_write_addr_bits_addr),
- .io_in0_write_addr_bits_id(bus_io_in0_write_addr_bits_id),
- .io_in0_write_data_ready(bus_io_in0_write_data_ready),
- .io_in0_write_data_valid(bus_io_in0_write_data_valid),
- .io_in0_write_data_bits_data(bus_io_in0_write_data_bits_data),
- .io_in0_write_data_bits_strb(bus_io_in0_write_data_bits_strb),
- .io_in0_write_resp_valid(bus_io_in0_write_resp_valid),
- .io_in0_read_addr_ready(bus_io_in0_read_addr_ready),
- .io_in0_read_addr_valid(bus_io_in0_read_addr_valid),
- .io_in0_read_addr_bits_addr(bus_io_in0_read_addr_bits_addr),
- .io_in0_read_addr_bits_id(bus_io_in0_read_addr_bits_id),
- .io_in0_read_data_valid(bus_io_in0_read_data_valid),
- .io_in0_read_data_bits_id(bus_io_in0_read_data_bits_id),
- .io_in0_read_data_bits_data(bus_io_in0_read_data_bits_data),
- .io_in1_write_addr_ready(bus_io_in1_write_addr_ready),
- .io_in1_write_addr_valid(bus_io_in1_write_addr_valid),
- .io_in1_write_addr_bits_addr(bus_io_in1_write_addr_bits_addr),
- .io_in1_write_data_ready(bus_io_in1_write_data_ready),
- .io_in1_write_data_valid(bus_io_in1_write_data_valid),
- .io_in1_write_data_bits_data(bus_io_in1_write_data_bits_data),
- .io_in1_write_data_bits_strb(bus_io_in1_write_data_bits_strb),
- .io_in1_read_addr_ready(bus_io_in1_read_addr_ready),
- .io_in1_read_addr_valid(bus_io_in1_read_addr_valid),
- .io_in1_read_addr_bits_addr(bus_io_in1_read_addr_bits_addr),
- .io_in1_read_data_valid(bus_io_in1_read_data_valid),
- .io_in1_read_data_bits_data(bus_io_in1_read_data_bits_data),
- .io_in2_write_addr_ready(bus_io_in2_write_addr_ready),
- .io_in2_write_addr_valid(bus_io_in2_write_addr_valid),
- .io_in2_write_addr_bits_addr(bus_io_in2_write_addr_bits_addr),
- .io_in2_write_addr_bits_id(bus_io_in2_write_addr_bits_id),
- .io_in2_write_data_ready(bus_io_in2_write_data_ready),
- .io_in2_write_data_valid(bus_io_in2_write_data_valid),
- .io_in2_write_data_bits_data(bus_io_in2_write_data_bits_data),
- .io_in2_write_data_bits_strb(bus_io_in2_write_data_bits_strb),
- .io_in2_write_resp_ready(bus_io_in2_write_resp_ready),
- .io_in2_write_resp_valid(bus_io_in2_write_resp_valid),
- .io_in2_write_resp_bits_id(bus_io_in2_write_resp_bits_id),
- .io_in2_read_addr_ready(bus_io_in2_read_addr_ready),
- .io_in2_read_addr_valid(bus_io_in2_read_addr_valid),
- .io_in2_read_addr_bits_addr(bus_io_in2_read_addr_bits_addr),
- .io_in2_read_addr_bits_id(bus_io_in2_read_addr_bits_id),
- .io_in2_read_data_ready(bus_io_in2_read_data_ready),
- .io_in2_read_data_valid(bus_io_in2_read_data_valid),
- .io_in2_read_data_bits_id(bus_io_in2_read_data_bits_id),
- .io_in2_read_data_bits_data(bus_io_in2_read_data_bits_data),
- .io_in3_read_addr_ready(bus_io_in3_read_addr_ready),
- .io_in3_read_addr_valid(bus_io_in3_read_addr_valid),
- .io_in3_read_addr_bits_addr(bus_io_in3_read_addr_bits_addr),
- .io_in3_read_data_ready(bus_io_in3_read_data_ready),
- .io_in3_read_data_valid(bus_io_in3_read_data_valid),
- .io_in3_read_data_bits_data(bus_io_in3_read_data_bits_data),
- .io_out_cvalid(bus_io_out_cvalid),
- .io_out_cready(bus_io_out_cready),
- .io_out_cwrite(bus_io_out_cwrite),
- .io_out_caddr(bus_io_out_caddr),
- .io_out_cid(bus_io_out_cid),
- .io_out_wdata(bus_io_out_wdata),
- .io_out_wmask(bus_io_out_wmask),
- .io_out_rvalid(bus_io_out_rvalid),
- .io_out_rid(bus_io_out_rid),
- .io_out_rdata(bus_io_out_rdata)
- );
- assign cvalid = bus_io_out_cvalid; // @[Kelvin.scala 120:12]
- assign cwrite = bus_io_out_cwrite; // @[Kelvin.scala 122:12]
- assign caddr = bus_io_out_caddr; // @[Kelvin.scala 123:12]
- assign cid = bus_io_out_cid; // @[Kelvin.scala 124:12]
- assign wdata = bus_io_out_wdata; // @[Kelvin.scala 125:12]
- assign wmask = bus_io_out_wmask; // @[Kelvin.scala 126:12]
- assign finish = core_io_halted; // @[Kelvin.scala 93:14]
- assign host_req = 1'h0; // @[Kelvin.scala 94:14]
- assign fault = core_io_fault; // @[Kelvin.scala 95:14]
- assign slog_valid = core_io_slog_valid; // @[Kelvin.scala 99:12]
- assign slog_addr = core_io_slog_addr; // @[Kelvin.scala 99:12]
- assign slog_data = core_io_slog_data; // @[Kelvin.scala 99:12]
- assign cg_clk_i = clk_i; // @[Kelvin.scala 57:16]
- assign cg_enable = ~clk_freeze; // @[Kelvin.scala 58:19]
- assign core_clock = cg_clk_o;
- assign core_reset = rst_q2; // @[Kelvin.scala 83:49]
- assign core_io_csr_in_value_0 = pc_start; // @[Kelvin.scala 137:29]
- assign core_io_ibus_ready = l1i_io_ibus_ready; // @[Kelvin.scala 107:21]
- assign core_io_ibus_rdata = l1i_io_ibus_rdata; // @[Kelvin.scala 107:21]
- assign core_io_dbus_ready = l1d_io_dbus_ready; // @[Kelvin.scala 103:21]
- assign core_io_dbus_rdata = l1d_io_dbus_rdata; // @[Kelvin.scala 103:21]
- assign core_io_axi0_write_addr_ready = bus_io_in0_write_addr_ready; // @[Kelvin.scala 113:16]
- assign core_io_axi0_write_data_ready = bus_io_in0_write_data_ready; // @[Kelvin.scala 113:16]
- assign core_io_axi0_write_resp_valid = bus_io_in0_write_resp_valid; // @[Kelvin.scala 113:16]
- assign core_io_axi0_read_addr_ready = bus_io_in0_read_addr_ready; // @[Kelvin.scala 113:16]
- assign core_io_axi0_read_data_valid = bus_io_in0_read_data_valid; // @[Kelvin.scala 113:16]
- assign core_io_axi0_read_data_bits_id = bus_io_in0_read_data_bits_id[5:0]; // @[Kelvin.scala 113:16]
- assign core_io_axi0_read_data_bits_data = bus_io_in0_read_data_bits_data; // @[Kelvin.scala 113:16]
- assign core_io_axi1_write_addr_ready = bus_io_in1_write_addr_ready; // @[Kelvin.scala 114:16]
- assign core_io_axi1_read_addr_ready = bus_io_in1_read_addr_ready; // @[Kelvin.scala 114:16]
- assign core_io_axi1_read_data_valid = bus_io_in1_read_data_valid; // @[Kelvin.scala 114:16]
- assign core_io_axi1_read_data_bits_data = bus_io_in1_read_data_bits_data; // @[Kelvin.scala 114:16]
- assign core_io_dflush_ready = l1d_io_flush_ready; // @[Kelvin.scala 104:21]
- assign l1d_clock = cg_clk_o;
- assign l1d_reset = rst_q2; // @[Kelvin.scala 83:49]
- assign l1d_io_dbus_valid = core_io_dbus_valid; // @[Kelvin.scala 103:21]
- assign l1d_io_dbus_write = core_io_dbus_write; // @[Kelvin.scala 103:21]
- assign l1d_io_dbus_addr = core_io_dbus_addr; // @[Kelvin.scala 103:21]
- assign l1d_io_dbus_adrx = core_io_dbus_adrx; // @[Kelvin.scala 103:21]
- assign l1d_io_dbus_size = core_io_dbus_size; // @[Kelvin.scala 103:21]
- assign l1d_io_dbus_wdata = core_io_dbus_wdata; // @[Kelvin.scala 103:21]
- assign l1d_io_dbus_wmask = core_io_dbus_wmask; // @[Kelvin.scala 103:21]
- assign l1d_io_axi_write_addr_ready = bus_io_in2_write_addr_ready; // @[Kelvin.scala 115:16]
- assign l1d_io_axi_write_data_ready = bus_io_in2_write_data_ready; // @[Kelvin.scala 115:16]
- assign l1d_io_axi_write_resp_valid = bus_io_in2_write_resp_valid; // @[Kelvin.scala 115:16]
- assign l1d_io_axi_write_resp_bits_id = bus_io_in2_write_resp_bits_id[3:0]; // @[Kelvin.scala 115:16]
- assign l1d_io_axi_read_addr_ready = bus_io_in2_read_addr_ready; // @[Kelvin.scala 115:16]
- assign l1d_io_axi_read_data_valid = bus_io_in2_read_data_valid; // @[Kelvin.scala 115:16]
- assign l1d_io_axi_read_data_bits_id = bus_io_in2_read_data_bits_id[3:0]; // @[Kelvin.scala 115:16]
- assign l1d_io_axi_read_data_bits_data = bus_io_in2_read_data_bits_data; // @[Kelvin.scala 115:16]
- assign l1d_io_flush_valid = core_io_dflush_valid; // @[Kelvin.scala 104:21]
- assign l1d_io_flush_all = core_io_dflush_all; // @[Kelvin.scala 104:21]
- assign l1d_io_volt_sel = volt_sel; // @[Kelvin.scala 105:21]
- assign l1i_clock = cg_clk_o;
- assign l1i_reset = rst_q2; // @[Kelvin.scala 83:49]
- assign l1i_io_ibus_valid = core_io_ibus_valid; // @[Kelvin.scala 107:21]
- assign l1i_io_ibus_addr = core_io_ibus_addr; // @[Kelvin.scala 107:21]
- assign l1i_io_flush_valid = core_io_iflush_valid; // @[Kelvin.scala 108:21]
- assign l1i_io_axi_read_addr_ready = bus_io_in3_read_addr_ready; // @[Kelvin.scala 116:21]
- assign l1i_io_axi_read_data_valid = bus_io_in3_read_data_valid; // @[Kelvin.scala 116:21]
- assign l1i_io_axi_read_data_bits_data = bus_io_in3_read_data_bits_data; // @[Kelvin.scala 116:21]
- assign l1i_io_volt_sel = volt_sel; // @[Kelvin.scala 109:21]
- assign bus_clock = cg_clk_o;
- assign bus_reset = rst_q2; // @[Kelvin.scala 83:49]
- assign bus_io_in0_write_addr_valid = core_io_axi0_write_addr_valid; // @[Kelvin.scala 113:16]
- assign bus_io_in0_write_addr_bits_addr = core_io_axi0_write_addr_bits_addr; // @[Kelvin.scala 113:16]
- assign bus_io_in0_write_addr_bits_id = {{1'd0}, core_io_axi0_write_addr_bits_id}; // @[Kelvin.scala 113:16]
- assign bus_io_in0_write_data_valid = core_io_axi0_write_data_valid; // @[Kelvin.scala 113:16]
- assign bus_io_in0_write_data_bits_data = core_io_axi0_write_data_bits_data; // @[Kelvin.scala 113:16]
- assign bus_io_in0_write_data_bits_strb = core_io_axi0_write_data_bits_strb; // @[Kelvin.scala 113:16]
- assign bus_io_in0_read_addr_valid = core_io_axi0_read_addr_valid; // @[Kelvin.scala 113:16]
- assign bus_io_in0_read_addr_bits_addr = core_io_axi0_read_addr_bits_addr; // @[Kelvin.scala 113:16]
- assign bus_io_in0_read_addr_bits_id = {{1'd0}, core_io_axi0_read_addr_bits_id}; // @[Kelvin.scala 113:16]
- assign bus_io_in1_write_addr_valid = core_io_axi1_write_addr_valid; // @[Kelvin.scala 114:16]
- assign bus_io_in1_write_addr_bits_addr = core_io_axi1_write_addr_bits_addr; // @[Kelvin.scala 114:16]
- assign bus_io_in1_write_data_valid = core_io_axi1_write_data_valid; // @[Kelvin.scala 114:16]
- assign bus_io_in1_write_data_bits_data = core_io_axi1_write_data_bits_data; // @[Kelvin.scala 114:16]
- assign bus_io_in1_write_data_bits_strb = core_io_axi1_write_data_bits_strb; // @[Kelvin.scala 114:16]
- assign bus_io_in1_read_addr_valid = core_io_axi1_read_addr_valid; // @[Kelvin.scala 114:16]
- assign bus_io_in1_read_addr_bits_addr = core_io_axi1_read_addr_bits_addr; // @[Kelvin.scala 114:16]
- assign bus_io_in2_write_addr_valid = l1d_io_axi_write_addr_valid; // @[Kelvin.scala 115:16]
- assign bus_io_in2_write_addr_bits_addr = l1d_io_axi_write_addr_bits_addr; // @[Kelvin.scala 115:16]
- assign bus_io_in2_write_addr_bits_id = {{3'd0}, l1d_io_axi_write_addr_bits_id}; // @[Kelvin.scala 115:16]
- assign bus_io_in2_write_data_valid = l1d_io_axi_write_data_valid; // @[Kelvin.scala 115:16]
- assign bus_io_in2_write_data_bits_data = l1d_io_axi_write_data_bits_data; // @[Kelvin.scala 115:16]
- assign bus_io_in2_write_data_bits_strb = l1d_io_axi_write_data_bits_strb; // @[Kelvin.scala 115:16]
- assign bus_io_in2_write_resp_ready = l1d_io_axi_write_resp_ready; // @[Kelvin.scala 115:16]
- assign bus_io_in2_read_addr_valid = l1d_io_axi_read_addr_valid; // @[Kelvin.scala 115:16]
- assign bus_io_in2_read_addr_bits_addr = l1d_io_axi_read_addr_bits_addr; // @[Kelvin.scala 115:16]
- assign bus_io_in2_read_addr_bits_id = {{3'd0}, l1d_io_axi_read_addr_bits_id}; // @[Kelvin.scala 115:16]
- assign bus_io_in2_read_data_ready = l1d_io_axi_read_data_ready; // @[Kelvin.scala 115:16]
- assign bus_io_in3_read_addr_valid = l1i_io_axi_read_addr_valid; // @[Kelvin.scala 116:21]
- assign bus_io_in3_read_addr_bits_addr = l1i_io_axi_read_addr_bits_addr; // @[Kelvin.scala 116:21]
- assign bus_io_in3_read_data_ready = l1i_io_axi_read_data_ready; // @[Kelvin.scala 116:21]
- assign bus_io_out_cready = cready; // @[Kelvin.scala 121:23]
- assign bus_io_out_rvalid = rvalid; // @[Kelvin.scala 127:23]
- assign bus_io_out_rid = rid; // @[Kelvin.scala 128:20]
- assign bus_io_out_rdata = rdata; // @[Kelvin.scala 129:22]
- always @(posedge clk_i or posedge rst_i) begin
- if (rst_i) begin // @[Kelvin.scala 74:25]
- rst_q1 <= 1'h1; // @[Kelvin.scala 74:25]
- end else begin
- rst_q1 <= 1'h0; // @[Kelvin.scala 76:12]
- end
- end
- always @(posedge clk_i or posedge rst_i) begin
- if (rst_i) begin // @[Kelvin.scala 75:25]
- rst_q2 <= 1'h1; // @[Kelvin.scala 75:25]
- end else begin
- rst_q2 <= rst_q1; // @[Kelvin.scala 77:12]
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- rst_q1 = _RAND_0[0:0];
- _RAND_1 = {1{`RANDOM}};
- rst_q2 = _RAND_1[0:0];
-`endif // RANDOMIZE_REG_INIT
- if (rst_i) begin
- rst_q1 = 1'h1;
- end
- if (rst_i) begin
- rst_q2 = 1'h1;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
diff --git a/sw/device/examples/hello_world/run_verilator_hello_world.sh b/sw/device/examples/hello_world/run_verilator_hello_world.sh
index e220a8a..f5ba0f1 100755
--- a/sw/device/examples/hello_world/run_verilator_hello_world.sh
+++ b/sw/device/examples/hello_world/run_verilator_hello_world.sh
@@ -37,7 +37,7 @@
# This cycle count is tuned so we don't need to wait too long for the test to
# finish.
-TEST_CYCLES=700000
+TEST_CYCLES=730000
GPIO_TEST=0
